Project import generated by Copybara. GitOrigin-RevId: f62630018ec2379f747f3b0c6fe513f44d9a6317
diff --git a/Makefile b/Makefile index 6ab2a8e..0b1531d 100644 --- a/Makefile +++ b/Makefile
@@ -404,7 +404,9 @@ UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null) UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION) -export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION +ACSRELEASE = $(shell cat include/config/acs.release 2> /dev/null) + +export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION ACSRELEASE export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC export CPP AR NM LDR STRIP OBJCOPY OBJDUMP @@ -494,6 +496,10 @@ KBUILD_CFLAGS += -DAML_ENABLE_PRODUCTION_MODE endif +ifeq ($(ENABLE_UBOOT_CLI),1) + KBUILD_CFLAGS += -DCONFIG_ENABLE_UBOOT_CLI +endif + ifeq ($(mixed-targets),1) # =========================================================================== # We're called with mixed targets (*config and build targets). @@ -638,7 +644,8 @@ KBUILD_CFLAGS += -O2 endif -KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector) +STACK_CFLAGS := $(call cc-option,-fstack-protector-strong) +KBUILD_CFLAGS += $(STACK_CFLAGS) KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks) # change __FILE__ to the relative path from the srctree @@ -775,7 +782,6 @@ u-boot-init := $(head-y) u-boot-main := $(libs-y) - # Add GCC lib ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a @@ -1574,10 +1580,17 @@ echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" endef +define filechk_acs.release + echo "$(BOARD)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" +endef + # Store (new) UBOOTRELEASE string in include/config/uboot.release include/config/uboot.release: include/config/auto.conf FORCE $(call filechk,uboot.release) +include/config/acs.release: include/config/auto.conf FORCE + $(call filechk,acs.release) + # Things we need to do before we recursively start building the kernel # or the modules are listed in "prepare". @@ -1591,7 +1604,7 @@ # prepare3 is used to check if we are building in a separate output directory, # and if so do: # 1) Check that make has not been executed in the kernel src $(srctree) -prepare3: include/config/uboot.release +prepare3: include/config/uboot.release include/config/acs.release ifneq ($(KBUILD_SRC),) @$(kecho) ' Using $(srctree) as source for U-Boot' $(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \ @@ -1628,9 +1641,11 @@ define filechk_version.h (echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \ + echo \#define ACS_VERSION \"$(ACSRELEASE)\"; \ echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \ echo \#define CONFIG_SYSTEM_AS_ROOT \"${SYSTEMMODE}\"; \ echo \#define CONFIG_AVB2 \"${AVBMODE}\"; \ + echo \#define CONFIG_CMD_BOOTCTOL_VAB \"${BOOTCTRLMODE}\"; \ echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \ echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; ) endef @@ -1652,6 +1667,7 @@ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ + LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"'; \ else \ return 42; \ fi; \ @@ -1661,6 +1677,7 @@ LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \ LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \ LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \ + LC_ALL=C date +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"'; \ fi) endef @@ -1683,7 +1700,7 @@ export U_BOOT_TIME_GIT=$(shell git log -1 --format=%cd --date=format:"%T") export U_BOOT_DATE_GIT=$(shell git log -1 --format=%cd --date=format:"%b %d %C%y") -$(version_h): include/config/uboot.release FORCE +$(version_h): include/config/uboot.release include/config/acs.release FORCE $(call filechk,version.h) ifeq ($(KBUILD_TIME_STAMP),0)
diff --git a/arch/arm/dts/meson-a-series.dtsi b/arch/arm/dts/meson-a-series.dtsi index 12c923b..ccdac71 100644 --- a/arch/arm/dts/meson-a-series.dtsi +++ b/arch/arm/dts/meson-a-series.dtsi
@@ -268,7 +268,7 @@ }; pwm_ab: pwm@2400 { - compatible = "amlogic,a1-pwm"; + compatible = "amlogic,meson-v2-pwm"; reg = <0x0 0x2400 0x0 0x20>, <0x0 0x08c4 0x0 0x04>; #pwm-cells = <3>; @@ -276,7 +276,7 @@ }; pwm_cd: pwm@2800 { - compatible = "amlogic,a1-pwm"; + compatible = "amlogic,meson-v2-pwm"; reg = <0x0 0x2800 0x0 0x20>, <0x0 0x08c8 0x0 0x04>; #pwm-cells = <3>; @@ -284,7 +284,7 @@ }; pwm_ef: pwm@5400 { - compatible = "amlogic,a1-pwm-ef"; + compatible = "amlogic,meson-v2-pwm"; reg = <0x0 0x5400 0x0 0x20>, <0x0 0x08cc 0x0 0x04>; #pwm-cells = <3>; @@ -312,9 +312,9 @@ status = "disabled"; }; - spicc0: spi@13000 { + spicc0: spi@3800 { compatible = "amlogic,meson-g12a-spicc"; - reg = <0x0 0x13000 0x0 0x44>; + reg = <0x0 0x3800 0x0 0x44>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -332,28 +332,17 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; compatible = "spi-flash"; - #address-cells = <1>; - #size-cells = <0>; status = "okay"; }; spi-nand@1 { reg = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <0>; status = "okay"; }; }; - spicc1: spi@15000 { - compatible = "amlogic,meson-g12a-spicc"; - reg = <0x0 0x15000 0x0 0x44>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - watchdog@0f0d0 { compatible = "amlogic,meson-a1-wdt"; reg = <0x0 0x0f0d0 0x0 0x10>; @@ -514,10 +503,11 @@ #address-cells = <2>; #size-cells = <2>; phy-version = <2>; - reg = <0x0 0xfe004420 0x0 0x80 + reg = <0x0 0xfe004420 0x0 0x60 0x0 0xfe000004 0x0 0x100 0x0 0xfe004000 0x0 0x2000 0x0 0xfe0008dc 0x0 0x4>; + dwc2_a_reg = <0xff500000>; #phy-cells = <0>; };
diff --git a/arch/arm/dts/meson-a1-a113l-ad401.dtsi b/arch/arm/dts/meson-a1-a113l-ad401.dtsi index 62c0309..bb9ff07 100644 --- a/arch/arm/dts/meson-a1-a113l-ad401.dtsi +++ b/arch/arm/dts/meson-a1-a113l-ad401.dtsi
@@ -18,7 +18,6 @@ serial1 = &uart_a; spi0 = &spifc; spi1 = &spicc0; - spi2 = &spicc1; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -252,20 +251,6 @@ &usb2_phy_v2 { status = "okay"; portnum = <1>; - phy20-reset-level-bit = <6>; - usb-reset-bit = <4>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; }; &usb3_phy_v2 { @@ -294,7 +279,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spifc_pins>; max-frequency = <24000000>; - max-io = <4>; max-cs = <2>; /* 512M */ clocks = <&clkc CLKID_FCLK_DIV3>, @@ -305,11 +289,11 @@ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; }; -&spicc1 { - status = "okay"; - /* pinctrl-names = "default"; */ - /* pinctrl-0 = <&spicc1_pins>; */ - /*cs-gpios = <&gpio GPIOH_6 0>;*/ +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_a>; + cs-gpios = <&gpio GPIOA_8 0>; }; &pwm_ab {
diff --git a/arch/arm/dts/meson-a1-a113l-ad402.dtsi b/arch/arm/dts/meson-a1-a113l-ad402.dtsi index 62c0309..bb9ff07 100644 --- a/arch/arm/dts/meson-a1-a113l-ad402.dtsi +++ b/arch/arm/dts/meson-a1-a113l-ad402.dtsi
@@ -18,7 +18,6 @@ serial1 = &uart_a; spi0 = &spifc; spi1 = &spicc0; - spi2 = &spicc1; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -252,20 +251,6 @@ &usb2_phy_v2 { status = "okay"; portnum = <1>; - phy20-reset-level-bit = <6>; - usb-reset-bit = <4>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; }; &usb3_phy_v2 { @@ -294,7 +279,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spifc_pins>; max-frequency = <24000000>; - max-io = <4>; max-cs = <2>; /* 512M */ clocks = <&clkc CLKID_FCLK_DIV3>, @@ -305,11 +289,11 @@ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; }; -&spicc1 { - status = "okay"; - /* pinctrl-names = "default"; */ - /* pinctrl-0 = <&spicc1_pins>; */ - /*cs-gpios = <&gpio GPIOH_6 0>;*/ +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_a>; + cs-gpios = <&gpio GPIOA_8 0>; }; &pwm_ab {
diff --git a/arch/arm/dts/meson-a1-a113l-ad409.dtsi b/arch/arm/dts/meson-a1-a113l-ad409.dtsi index 27807f7..338a247 100644 --- a/arch/arm/dts/meson-a1-a113l-ad409.dtsi +++ b/arch/arm/dts/meson-a1-a113l-ad409.dtsi
@@ -18,7 +18,6 @@ serial1 = &uart_a; spi0 = &spifc; spi1 = &spicc0; - spi2 = &spicc1; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -226,20 +225,6 @@ &usb2_phy_v2 { status = "okay"; portnum = <1>; - phy20-reset-level-bit = <6>; - usb-reset-bit = <4>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; }; &usb3_phy_v2 { @@ -268,7 +253,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spifc_pins>; max-frequency = <24000000>; - max-io = <4>; max-cs = <2>; /* 512M */ clocks = <&clkc CLKID_FCLK_DIV3>, @@ -279,9 +263,9 @@ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; }; -&spicc1 { - status = "okay"; - /* pinctrl-names = "default"; */ - /* pinctrl-0 = <&spicc1_pins>; */ - /*cs-gpios = <&gpio GPIOH_6 0>;*/ +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_a>; + cs-gpios = <&gpio GPIOA_8 0>; };
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi index 9ac54a2..36d58cd 100644 --- a/arch/arm/dts/meson-a1.dtsi +++ b/arch/arm/dts/meson-a1.dtsi
@@ -190,20 +190,16 @@ /*amlogic,mmc-syscon = <&sd_emmc_c>;*/ }; -/* &spicc0 { - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_COMP>; - clock-names = "core", "comp"; + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC, no set for power on already */ + /* pm-id = <22>; */ }; -&spicc1 { - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_COMP>; - clock-names = "core", "comp"; - }; -*/ - &pinctrl_periphs { jtag_a_pins:jtag_a_pin { mux { @@ -336,6 +332,16 @@ }; }; + spicc0_pins_a: spicc0_pins_a { + mux { + groups = "spi_a_mosi_a", + "spi_a_miso_a", + "spi_a_sclk_a"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + pwm_a_pins1: pwm_a_pins1 { mux { groups = "pwm_a_x6";
diff --git a/arch/arm/dts/meson-c-series.dtsi b/arch/arm/dts/meson-c-series.dtsi index 5a7fff5..89b755d 100644 --- a/arch/arm/dts/meson-c-series.dtsi +++ b/arch/arm/dts/meson-c-series.dtsi
@@ -268,22 +268,41 @@ }; pwm_ab: pwm@2400 { - compatible = "amlogic,a1-pwm-ab"; - reg = <0x0 0x2400 0x0 0x20>; + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x2400 0x0 0x20>, + <0x0 0x08c4 0x0 0x04>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@2800 { - compatible = "amlogic,a1-pwm-cd"; - reg = <0x0 0x2800 0x0 0x20>; + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x2800 0x0 0x20>, + <0x0 0x08c8 0x0 0x04>; #pwm-cells = <3>; status = "disabled"; }; pwm_ef: pwm@5400 { - compatible = "amlogic,a1-pwm-ef"; - reg = <0x0 0x5400 0x0 0x20>; + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0x5400 0x0 0x20>, + <0x0 0x08cc 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_gh: pwm@a400 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xa400 0x0 0x20>, + <0x0 0x0928 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ij: pwm@a800 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xa800 0x0 0x20>, + <0x0 0x092c 0x0 0x04>; #pwm-cells = <3>; status = "disabled"; }; @@ -321,22 +340,23 @@ spifc: spi@14000 { compatible = "amlogic,spifc"; reg = <0x0 0x14000 0x0 0x80>; - #ahb = <0x0 0xf6000000 0x0 0x4000000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; - spi-flash@0 { - compatible = "spi-flash"; - #address-cells = <1>; - #size-cells = <0>; - status = "disable"; - }; - spi-nand@1 { - compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - }; + spi-flash@0 { + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + compatible = "spi-flash"; + status = "okay"; + }; + spi-nand@1 { + reg = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + compatible = "spi-nand"; + status = "okay"; + }; }; spicc1: spi@3c00 { @@ -512,10 +532,11 @@ #address-cells = <2>; #size-cells = <2>; phy-version = <2>; - reg = <0x0 0xfe004420 0x0 0x80 + reg = <0x0 0xfe004420 0x0 0x60 0x0 0xfe000004 0x0 0x100 0x0 0xfe004000 0x0 0x2000 0x0 0xfe0008dc 0x0 0x4>; + dwc2_a_reg = <0xff500000>; #phy-cells = <0>; };
diff --git a/arch/arm/dts/meson-c1-c308x-ae400.dtsi b/arch/arm/dts/meson-c1-c308x-ae400.dtsi index 6f332c3..a88346f 100644 --- a/arch/arm/dts/meson-c1-c308x-ae400.dtsi +++ b/arch/arm/dts/meson-c1-c308x-ae400.dtsi
@@ -198,20 +198,6 @@ &usb2_phy_v2 { status = "okay"; portnum = <1>; - phy20-reset-level-bit = <4>; - usb-reset-bit = <3>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; }; &usb3_phy_v2 { @@ -237,21 +223,24 @@ &spifc { status = "okay"; - /* pinctrl-names = "default"; */ - /* pinctrl-0 = <&spifc_all_pins>; */ + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; max-frequency = <24000000>; - max-io = <1>; max-cs = <2>; - //clocks = <&clkc CLKID_CLK81>; - //clock-names = "core"; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; }; &spicc0 { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&spicc0_pins1>; - cs-gpios = <&gpio GPIOA_8 0>, - <&gpio GPIOA_9 0>; + cs-gpios = <&gpio GPIOA_8 0>; }; &spicc1 {
diff --git a/arch/arm/dts/meson-c1-c308x-ae401.dtsi b/arch/arm/dts/meson-c1-c308x-ae401.dtsi index 45713bb..d742529 100644 --- a/arch/arm/dts/meson-c1-c308x-ae401.dtsi +++ b/arch/arm/dts/meson-c1-c308x-ae401.dtsi
@@ -159,8 +159,8 @@ bus-width = <8>; cap-sd-highspeed; cap-mmc-highspeed; -// mmc-hs200-1_8v; - max-frequency = <40000000>; + //mmc-hs200-1_8v; + max-frequency = <50000000>; non-removable; disable-wp; /* mmc-ddr-1_8v; */ @@ -239,20 +239,6 @@ &usb2_phy_v2 { status = "okay"; portnum = <1>; - phy20-reset-level-bit = <4>; - usb-reset-bit = <3>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; }; &usb3_phy_v2 { @@ -278,21 +264,24 @@ &spifc { status = "okay"; - /* pinctrl-names = "default"; */ - /* pinctrl-0 = <&spifc_all_pins>; */ + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; max-frequency = <24000000>; - max-io = <1>; max-cs = <2>; - //clocks = <&clkc CLKID_CLK81>; - //clock-names = "core"; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; }; &spicc0 { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&spicc0_pins1>; - cs-gpios = <&gpio GPIOA_8 0>, - <&gpio GPIOA_9 0>; + cs-gpios = <&gpio GPIOA_8 0>; }; &spicc1 {
diff --git a/arch/arm/dts/meson-c1-c308x-ae402.dts b/arch/arm/dts/meson-c1-c308x-ae402.dts new file mode 100644 index 0000000..2fb0f98 --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae402.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c1-c308x-ae402.dtsi" +#include "meson-c1_skt-panel.dtsi" + +/ { + compatible = "amlogic,ae402", "amlogic,c308x", "amlogic,meson-c1"; + model = "Amlogic Meson C1 AE402 Reference Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae402.dtsi b/arch/arm/dts/meson-c1-c308x-ae402.dtsi new file mode 100644 index 0000000..43c7b60 --- /dev/null +++ b/arch/arm/dts/meson-c1-c308x-ae402.dtsi
@@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c1-c308x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_tx_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + //mmc-hs200-1_8v; + max-frequency = <50000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_tx_phase = <0>; + + hs2_co_phase = <2>; + hs2_tx_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; + + /* + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <1024>; + + meson-nand-user-mode = <2>; + meson-nand-ran-mode = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "env"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "system"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "rootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "media"; + reg = <0x04000000 0x8000000>; + }; + };*/ + +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c1-c308x-ae409.dtsi b/arch/arm/dts/meson-c1-c308x-ae409.dtsi index 9ae6700..18554d9 100644 --- a/arch/arm/dts/meson-c1-c308x-ae409.dtsi +++ b/arch/arm/dts/meson-c1-c308x-ae409.dtsi
@@ -198,20 +198,6 @@ &usb2_phy_v2 { status = "okay"; portnum = <1>; - phy20-reset-level-bit = <4>; - usb-reset-bit = <3>; - u2-ctrl-sleep-shift = <24>; - u2-hhi-mem-pd-shift = <0x0>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <24>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; }; &usb3_phy_v2 { @@ -237,21 +223,24 @@ &spifc { status = "okay"; - /* pinctrl-names = "default"; */ - /* pinctrl-0 = <&spifc_all_pins>; */ + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; max-frequency = <24000000>; - max-io = <1>; max-cs = <2>; - //clocks = <&clkc CLKID_CLK81>; - //clock-names = "core"; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; }; &spicc0 { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&spicc0_pins1>; - cs-gpios = <&gpio GPIOA_8 0>, - <&gpio GPIOA_9 0>; + cs-gpios = <&gpio GPIOA_8 0>; }; &spicc1 {
diff --git a/arch/arm/dts/meson-c1.dtsi b/arch/arm/dts/meson-c1.dtsi index 7d90066..cc3138c 100644 --- a/arch/arm/dts/meson-c1.dtsi +++ b/arch/arm/dts/meson-c1.dtsi
@@ -156,59 +156,61 @@ }; &sd_emmc_a { - /* - clocks = <&clkc CLKID_SD_EMMC_A>, - <&xtal>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "core", "clkin0", "clkin1"; - */ + clocks = <&clkc CLKID_SD_EMMC_A_MUX>, + <&clkc CLKID_SD_EMMC_A_DIV>, + <&clkc CLKID_SD_EMMC_A_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_A_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; }; &sd_emmc_b { - /* - clocks = <&clkc CLKID_SD_EMMC_B_P0_MUX>, - <&clkc CLKID_SD_EMMC_B_P0_DIV>, - <&clkc CLKID_SD_EMMC_B_P0_GATE>, - <&clkc CLKID_SD_EMMC_B>, - <&xtal>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "mux", "div", "gate", "core", "clkin0", "clkin1"; - */ + clocks = <&clkc CLKID_SD_EMMC_B_MUX>, + <&clkc CLKID_SD_EMMC_B_DIV>, + <&clkc CLKID_SD_EMMC_B_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_B_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; }; &sd_emmc_c { - /* - clocks = <&clkc CLKID_SD_EMMC_C_P0_MUX>, - <&clkc CLKID_SD_EMMC_C_P0_DIV>, - <&clkc CLKID_SD_EMMC_C_P0_GATE>, - <&clkc CLKID_SD_EMMC_C>, - <&xtal>, - <&clkc CLKID_FCLK_DIV2>; - clock-names = "mux", "div", "gate", "core", "clkin0", "clkin1"; - */ + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; }; &nand { - clocks = <&clkc CLKID_FCLK_DIV2>, - <&clkc CLKID_SD_EMMC_C_MUX>, + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, <&clkc CLKID_SD_EMMC_C_DIV>, - <&clkc CLKID_SD_EMMC_C_GATE>; - clock-names = "clkin", "clkin1", "clkin2", "clkin3"; + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_XTAL_GATE>; + clock-names = "mux", "div", "gate", "fdiv2", "xtal"; }; -/* &spicc0 { - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_COMP>; - clock-names = "core", "comp"; + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC, no set for power on already */ + /* pm-id = <22>; */ }; &spicc1 { - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_COMP>; - clock-names = "core", "comp"; - }; -*/ + clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC_B, must set to power on */ + pm-id = <39>; +}; + &pinctrl_periphs { jtag_a_pins:jtag_a_pin { mux { @@ -382,6 +384,182 @@ drive-strength = <3>; }; }; + + pwm_a_pins1: pwm_a_pins1 { + mux { + groups = "pwm_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins1: pwm_e_pins1 { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_d"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_m"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm_f_pins3 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_g_pins1: pwm_g_pins1 { + mux { + groups = "pwm_g_d"; + function = "pwm_g"; + }; + }; + + pwm_g_pins2: pwm_g_pins2 { + mux { + groups = "pwm_g_x"; + function = "pwm_g"; + }; + }; + + pwm_g_pins3: pwm_g_pins3 { + mux { + groups = "pwm_g_m"; + function = "pwm_g"; + }; + }; + + pwm_g_pins4: pwm_g_pins4 { + mux { + groups = "pwm_g_a7"; + function = "pwm_g"; + }; + }; + + pwm_g_pins5: pwm_g_pins5 { + mux { + groups = "pwm_g_a1"; + function = "pwm_g"; + }; + }; + + pwm_h_pins1: pwm_h_pins1 { + mux { + groups = "pwm_h_x"; + function = "pwm_h"; + }; + }; + + pwm_h_pins2: pwm_h_pins2 { + mux { + groups = "pwm_h_m"; + function = "pwm_h"; + }; + }; + + pwm_h_pins3: pwm_h_pins3 { + mux { + groups = "pwm_h_a8"; + function = "pwm_h"; + }; + }; + + pwm_h_pins4: pwm_h_pins4 { + mux { + groups = "pwm_h_a2"; + function = "pwm_h"; + }; + }; + + pwm_i_pins1: pwm_i_pins1 { + mux { + groups = "pwm_i_x"; + function = "pwm_i"; + }; + }; + + pwm_i_pins2: pwm_i_pins2 { + mux { + groups = "pwm_i_m"; + function = "pwm_i"; + }; + }; + + pwm_i_pins3: pwm_i_pins3 { + mux { + groups = "pwm_i_a9"; + function = "pwm_i"; + }; + }; + + pwm_i_pins4: pwm_i_pins4 { + mux { + groups = "pwm_i_a3"; + function = "pwm_i"; + }; + }; + + pwm_j_pins1: pwm_j_pins1 { + mux { + groups = "pwm_j_x"; + function = "pwm_j"; + }; + }; + + pwm_j_pins2: pwm_j_pins2 { + mux { + groups = "pwm_j_m"; + function = "pwm_j"; + }; + }; + + pwm_j_pins3: pwm_j_pins3 { + mux { + groups = "pwm_j_a10"; + function = "pwm_j"; + }; + }; + + pwm_j_pins4: pwm_j_pins4 { + mux { + groups = "pwm_j_a4"; + function = "pwm_j"; + }; + }; + emmc_pins: emmc { mux { groups = "emmc_nand_d0", @@ -517,4 +695,17 @@ drive-strength = <2>; }; }; + + spifc_pins: spifc_pins { + mux { + groups = "spif_mo", + "spif_mi", + "spif_clk", + "spif_cs", + "spif_hold", + "spif_wp_n"; + function = "spif"; + drive-strength = <3>; + }; + }; };
diff --git a/arch/arm/dts/meson-c2-c305x-af400.dts b/arch/arm/dts/meson-c2-c305x-af400.dts new file mode 100644 index 0000000..69dcdd9 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af400.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af400.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF400 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af400.dtsi b/arch/arm/dts/meson-c2-c305x-af400.dtsi new file mode 100644 index 0000000..f313da1 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af400.dtsi
@@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x-af401.dts b/arch/arm/dts/meson-c2-c305x-af401.dts new file mode 100644 index 0000000..707f9c2 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af401.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af401.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af401", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF401 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af401.dtsi b/arch/arm/dts/meson-c2-c305x-af401.dtsi new file mode 100644 index 0000000..2857303 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af401.dtsi
@@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x-af409.dts b/arch/arm/dts/meson-c2-c305x-af409.dts new file mode 100644 index 0000000..b0d4fdc --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af409.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af409.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af409", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF409 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af409.dtsi b/arch/arm/dts/meson-c2-c305x-af409.dtsi new file mode 100644 index 0000000..f313da1 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af409.dtsi
@@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x-af419.dts b/arch/arm/dts/meson-c2-c305x-af419.dts new file mode 100644 index 0000000..3799307 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af419.dts
@@ -0,0 +1,90 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af419.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af419", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF419 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af419.dtsi b/arch/arm/dts/meson-c2-c305x-af419.dtsi new file mode 100644 index 0000000..f313da1 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x-af419.dtsi
@@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c305x.dtsi b/arch/arm/dts/meson-c2-c305x.dtsi new file mode 100644 index 0000000..9668492 --- /dev/null +++ b/arch/arm/dts/meson-c2-c305x.dtsi
@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-c2.dtsi" +#include "meson-c2-mali.dtsi" + +/ { + compatible = "amlogic,c305x", "amlogic,meson-c2"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +};
diff --git a/arch/arm/dts/meson-c2-c325x-2rs4.dts b/arch/arm/dts/meson-c2-c325x-2rs4.dts new file mode 100644 index 0000000..d96b261 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-2rs4.dts
@@ -0,0 +1,95 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c325x-2rs4.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Google 2RS4 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_master_pins1>; + clock-frequency = <400000>; /* max supported freq */ +}; + +&i2c4 { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_master_pins1>; + clock-frequency = <400000>; /* 400K, b/159627458 */ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-2rs4.dtsi b/arch/arm/dts/meson-c2-c325x-2rs4.dtsi new file mode 100644 index 0000000..2442995 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-2rs4.dtsi
@@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <167000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; + phy20-reset-level-bit = <4>; + usb-reset-bit = <3>; + u2-ctrl-sleep-shift = <24>; + u2-hhi-mem-pd-shift = <0x0>; + u2-hhi-mem-pd-mask = <0x3>; + u2-ctrl-iso-shift = <24>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xfe18>; + pll-setting-5 = <0x8000fff>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>, + <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c325x-a049.dts b/arch/arm/dts/meson-c2-c325x-a049.dts new file mode 100644 index 0000000..ce36a5e --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-a049.dts
@@ -0,0 +1,96 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c325x-a049.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Google A049 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&i2c4 { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_master_pins1>; + clock-frequency = <400000>; /* 400K, b/159627458 */ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-a049.dtsi b/arch/arm/dts/meson-c2-c325x-a049.dtsi new file mode 100644 index 0000000..2442995 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-a049.dtsi
@@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <167000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; + phy20-reset-level-bit = <4>; + usb-reset-bit = <3>; + u2-ctrl-sleep-shift = <24>; + u2-hhi-mem-pd-shift = <0x0>; + u2-hhi-mem-pd-mask = <0x3>; + u2-ctrl-iso-shift = <24>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xfe18>; + pll-setting-5 = <0x8000fff>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>, + <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c325x-bla4.dts b/arch/arm/dts/meson-c2-c325x-bla4.dts new file mode 100644 index 0000000..7ab3160 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-bla4.dts
@@ -0,0 +1,95 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c325x-bla4.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Google BLA4 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_master_pins2>; + clock-frequency = <400000>; /* max supported freq */ +}; + +&i2c4 { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_master_pins1>; + clock-frequency = <400000>; /* 400K, b/159627458 */ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-bla4.dtsi b/arch/arm/dts/meson-c2-c325x-bla4.dtsi new file mode 100644 index 0000000..2442995 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-bla4.dtsi
@@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <167000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; + phy20-reset-level-bit = <4>; + usb-reset-bit = <3>; + u2-ctrl-sleep-shift = <24>; + u2-hhi-mem-pd-shift = <0x0>; + u2-hhi-mem-pd-mask = <0x3>; + u2-ctrl-iso-shift = <24>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xfe18>; + pll-setting-5 = <0x8000fff>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>, + <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c325x-bsv3.dts b/arch/arm/dts/meson-c2-c325x-bsv3.dts new file mode 100644 index 0000000..b405642 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-bsv3.dts
@@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c325x-bsv3.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Google BSV3 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_master_pins1>; + clock-frequency = <400000>; /* max supported freq */ + + ps13216: ps13216@10 { + compatible = "photeon,ps13216"; + reg = <0x10>; + enable-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c4 { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_master_pins1>; + clock-frequency = <400000>; /* 400K, b/159627458 */ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-bsv3.dtsi b/arch/arm/dts/meson-c2-c325x-bsv3.dtsi new file mode 100644 index 0000000..2442995 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-bsv3.dtsi
@@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <167000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; + phy20-reset-level-bit = <4>; + usb-reset-bit = <3>; + u2-ctrl-sleep-shift = <24>; + u2-hhi-mem-pd-shift = <0x0>; + u2-hhi-mem-pd-mask = <0x3>; + u2-ctrl-iso-shift = <24>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xfe18>; + pll-setting-5 = <0x8000fff>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>, + <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c325x-spencer.dts b/arch/arm/dts/meson-c2-c325x-spencer.dts new file mode 100644 index 0000000..bc291c7 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-spencer.dts
@@ -0,0 +1,96 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c325x-spencer.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Google Spencer Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&i2c4 { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_master_pins1>; + clock-frequency = <400000>; /* 400K, b/159627458 */ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-spencer.dtsi b/arch/arm/dts/meson-c2-c325x-spencer.dtsi new file mode 100644 index 0000000..2442995 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-spencer.dtsi
@@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <167000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; + phy20-reset-level-bit = <4>; + usb-reset-bit = <3>; + u2-ctrl-sleep-shift = <24>; + u2-hhi-mem-pd-shift = <0x0>; + u2-hhi-mem-pd-mask = <0x3>; + u2-ctrl-iso-shift = <24>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xfe18>; + pll-setting-5 = <0x8000fff>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>, + <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c325x-venus.dts b/arch/arm/dts/meson-c2-c325x-venus.dts new file mode 100644 index 0000000..888cc30 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-venus.dts
@@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c325x-venus.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Google Venus Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_master_pins1>; + clock-frequency = <400000>; /* max supported freq */ + + ps13216: ps13216@10 { + compatible = "photeon,ps13216"; + reg = <0x10>; + enable-gpios = <&gpio GPIOC_1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c4 { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_master_pins1>; + clock-frequency = <400000>; /* 400K, b/159627458 */ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-venus.dtsi b/arch/arm/dts/meson-c2-c325x-venus.dtsi new file mode 100644 index 0000000..2442995 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-venus.dtsi
@@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <167000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; + phy20-reset-level-bit = <4>; + usb-reset-bit = <3>; + u2-ctrl-sleep-shift = <24>; + u2-hhi-mem-pd-shift = <0x0>; + u2-hhi-mem-pd-mask = <0x3>; + u2-ctrl-iso-shift = <24>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xfe18>; + pll-setting-5 = <0x8000fff>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>, + <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-c325x-xua4.dts b/arch/arm/dts/meson-c2-c325x-xua4.dts new file mode 100644 index 0000000..5f0c2bd --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-xua4.dts
@@ -0,0 +1,95 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c325x-xua4.dtsi" + +/ { + compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2"; + model = "Google XUA4 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_master_pins2>; + clock-frequency = <400000>; /* max supported freq */ +}; + +&i2c4 { + status= "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_master_pins1>; + clock-frequency = <400000>; /* 400K, b/159627458 */ +}; + +ðmac { + status = "okay"; + internal_phy = <0>; + pinctrl-0 = <&external_eth_rmii_pins>; + pinctrl-names = "external_eth_rmii_pins"; + mc_val = <0x1624>; +}; +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c325x-xua4.dtsi b/arch/arm/dts/meson-c2-c325x-xua4.dtsi new file mode 100644 index 0000000..2442995 --- /dev/null +++ b/arch/arm/dts/meson-c2-c325x-xua4.dtsi
@@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-c2-c305x.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <167000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <1>; + phy20-reset-level-bit = <4>; + usb-reset-bit = <3>; + u2-ctrl-sleep-shift = <24>; + u2-hhi-mem-pd-shift = <0x0>; + u2-hhi-mem-pd-mask = <0x3>; + u2-ctrl-iso-shift = <24>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xfe18>; + pll-setting-5 = <0x8000fff>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOD_9"; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + max-frequency = <24000000>; + max-cs = <2>; + /* 512M */ + clocks = <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SPIFC_MUX>, + <&clkc CLKID_SPIFC_DIV>, + <&clkc CLKID_SPIFC_GATE>, + <&clkc CLKID_SPIFC_XTAL_GATE>; + clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins1>; + cs-gpios = <&gpio GPIOA_8 0>, + <&gpio GPIOA_9 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins1>; + cs-gpios = <&gpio GPIOA_14 0>; +};
diff --git a/arch/arm/dts/meson-c2-mali.dtsi b/arch/arm/dts/meson-c2-mali.dtsi new file mode 100644 index 0000000..2655b42 --- /dev/null +++ b/arch/arm/dts/meson-c2-mali.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +&apb { + mali: gpu@40000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0x40000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/ + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + /* + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; *//* Glitch free mux */ + /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, *//* Do Nothing */ + //<&clkc CLKID_MALI_0>; + /*assigned-clock-rates = <0>,*/ /* Do Nothing */ + /* <666666666>, + <0>;*/ /* Do Nothing */ + }; +};
diff --git a/arch/arm/dts/meson-c2-pxp.dts b/arch/arm/dts/meson-c2-pxp.dts new file mode 100644 index 0000000..02c94a0 --- /dev/null +++ b/arch/arm/dts/meson-c2-pxp.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-c2-c305x-af409.dtsi" +#include "meson-c2_skt-panel.dtsi" + +/ { + compatible = "amlogic,af409", "amlogic,c305x", "amlogic,meson-c2"; + model = "Amlogic Meson C2 AF409 Socket Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2.dtsi b/arch/arm/dts/meson-c2.dtsi new file mode 100644 index 0000000..ea5b4bb --- /dev/null +++ b/arch/arm/dts/meson-c2.dtsi
@@ -0,0 +1,776 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-c-series.dtsi" +#include <dt-bindings/gpio/meson-c2-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> + +/ { + compatible = "amlogic,meson-c2"; + + vpu { + compatible = "amlogic, vpu-g12a"; + status = "okay"; + /*clocks = <&clkc CLKID_VAPB_MUX>, + * <&clkc CLKID_VPU_INTR>, + * <&clkc CLKID_VPU_P0_COMP>, + * <&clkc CLKID_VPU_P1_COMP>, + * <&clkc CLKID_VPU_MUX>; + *clock-names = "vapb_clk", + * "vpu_intr_gate", + * "vpu_clk0", + * "vpu_clk1", + * "vpu_clk"; + */ + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + meson-fb { + status = "okay"; + logo_addr = "0x7f800000"; + }; +}; + +ðmac { + compatible = "amlogic,g12a-eth-dwmac"; + reg = <0x0 0xff080000 0x0 0x10000 + 0x0 0xFE009000 0x0 0x8 + 0x0 0xFE009400 0x0 0xa0>; + reg-names = "eth_base", "eth_top", "eth_cfg"; + phy_cntl1 = <0x41054147>; + internal_phy = <1>; + mc_val = <0x4be04>; + reset-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + analog_ver = <2>; /*1:c1; 2:c2*/ + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + tx_amp_src = <0xfe005b30>; +// clocks = <&clkc CLKID_ETH_CORE>, +// <&clkc CLKID_FCLK_DIV2>, +// <&clkc CLKID_MPLL2>; +// clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&cbus { + pinctrl_periphs: pinctrl@0400 { + compatible = "amlogic,meson-c2-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@0400 { + reg = <0x0 0x0400 0x0 0x0040>, + <0x0 0x0480 0x0 0x01d8>; + reg-names = "mux", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 90>; + }; + }; + + i2c_gpio_0: i2c-gpio-0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + status = "okay"; + gpios = <&gpio GPIOM_12 GPIO_ACTIVE_HIGH>, /* SDA */ + <&gpio GPIOM_13 GPIO_ACTIVE_HIGH>; /* CLK */ + + i2c-gpio,delay-us = <5>; + }; +}; + +&periphs { + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x15c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-c2-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SARADC_MUX>, + <&clkc CLKID_SARADC_DIV>, + <&clkc CLKID_SAR_ADC_GATE>; + clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; +}; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A_MUX>, + <&clkc CLKID_SD_EMMC_A_DIV>, + <&clkc CLKID_SD_EMMC_A_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_A_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B_MUX>, + <&clkc CLKID_SD_EMMC_B_DIV>, + <&clkc CLKID_SD_EMMC_B_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_B_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_XTAL_GATE>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&nand { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_SD_EMMC_C_XTAL_GATE>; + clock-names = "mux", "div", "gate", "fdiv2", "xtal"; +}; + +&spicc0 { + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC, no set for power on already */ + /* pm-id = <22>; */ +}; + +&spicc1 { + clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC_B, must set to power on */ + pm-id = <39>; +}; + +&pinctrl_periphs { + jtag_a_pins:jtag_a_pin { + mux { + groups = "jtag_a_clk", + "jtag_a_tms", + "jtag_a_tdi", + "jtag_a_tdo"; + function = "jtag_a"; + }; + }; + + jtag_b_pins:jtag_b_pin { + mux { + groups = "jtag_b_clk", + "jtag_b_tms", + "jtag_b_tdi", + "jtag_b_tdo"; + function = "jtag_b"; + }; + }; + + swd_a_pins:swd_a_pin { + mux { + groups = "swclk", + "swdio"; + function = "sw"; + }; + }; + + /*i2c0 pinmux*/ + i2c0_master_pins1:i2c0_pins1 { + mux { + groups = "i2c_a_scl_d", + "i2c_a_sda_d"; + function = "i2c_a"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c0_master_pins2:i2c0_pins2 { + mux { + groups = "i2c_a_scl_e", + "i2c_a_sda_e"; + function = "i2c_a"; + bias-disable; + drive-strength = <3>; + }; + }; + + /* i2c1 pinmux */ + i2c1_master_pins2:i2c1_pins2 { + mux { + groups = "i2c_b_scl_a", + "i2c_b_sda_a"; + function = "i2c_b"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c1_master_pins3:i2c1_pins3 { + mux { + groups = "i2c_b_scl_m", + "i2c_b_sda_m"; + function = "i2c_b"; + bias-disable; + drive-strength = <3>; + }; + }; + + /* i2c2 pinmux */ + i2c2_master_pins1:i2c2_pins1 { + mux { + groups = "i2c_c_scl_x", + "i2c_c_sda_x"; + function = "i2c_c"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c2_master_pins2:i2c2_pins2 { + mux { + groups = "i2c_c_scl_m", + "i2c_c_sda_m"; + function = "i2c_c"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c2_master_pins3:i2c2_pins3 { + mux { + groups = "i2c_c_scl_a", + "i2c_c_sda_a"; + function = "i2c_c"; + bias-disable; + drive-strength = <3>; + }; + }; + + /* i2c3 pinmux */ + i2c3_master_pins1:i2c3_pins1 { + mux { + groups = "i2c_d_scl_x", + "i2c_d_sda_x"; + function = "i2c_d"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c3_master_pins2:i2c3_pins2 { + mux { + groups = "i2c_d_scl_a", + "i2c_d_sda_a"; + function = "i2c_d"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c3_master_pins3:i2c3_pins3 { + mux { + groups = "i2c_d_scl_m", + "i2c_d_sda_m"; + function = "i2c_d"; + bias-disable; + drive-strength = <3>; + }; + }; + + /* i2c4 pinmux */ + i2c4_master_pins1:i2c4_pins1 { + mux { + groups = "i2c_e_scl_c", + "i2c_e_sda_c"; + function = "i2c_e"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c4_master_pins2:i2c4_pins2 { + mux { + groups = "i2c_e_scl_m", + "i2c_e_sda_m"; + function = "i2c_e"; + bias-disable; + drive-strength = <3>; + }; + }; + + i2c4_master_pins3:i2c4_pins3 { + mux { + groups = "i2c_e_scl_a", + "i2c_e_sda_a"; + function = "i2c_e"; + bias-disable; + drive-strength = <3>; + }; + }; + + pwm_a_pins1: pwm_a_pins1 { + mux { + groups = "pwm_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d"; + function = "pwm_d"; + }; + }; + + pwm_e_pins1: pwm_e_pins1 { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_d"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_m"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm_f_pins3 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_g_pins1: pwm_g_pins1 { + mux { + groups = "pwm_g_d10"; + function = "pwm_g"; + }; + }; + + pwm_g_pins2: pwm_g_pins2 { + mux { + groups = "pwm_g_x"; + function = "pwm_g"; + }; + }; + + pwm_g_pins3: pwm_g_pins3 { + mux { + groups = "pwm_g_m"; + function = "pwm_g"; + }; + }; + + pwm_g_pins4: pwm_g_pins4 { + mux { + groups = "pwm_g_a7"; + function = "pwm_g"; + }; + }; + + pwm_g_pins5: pwm_g_pins5 { + mux { + groups = "pwm_g_a1"; + function = "pwm_g"; + }; + }; + + pwm_g_pins6: pwm_g_pins6 { + mux { + groups = "pwm_g_d12"; + function = "pwm_g"; + }; + }; + + pwm_g_pins7: pwm_g_pins7 { + mux { + groups = "pwm_g_d13"; + function = "pwm_g"; + }; + }; + + pwm_h_pins1: pwm_h_pins1 { + mux { + groups = "pwm_h_x"; + function = "pwm_h"; + }; + }; + + pwm_h_pins2: pwm_h_pins2 { + mux { + groups = "pwm_h_m"; + function = "pwm_h"; + }; + }; + + pwm_h_pins3: pwm_h_pins3 { + mux { + groups = "pwm_h_a8"; + function = "pwm_h"; + }; + }; + + pwm_h_pins4: pwm_h_pins4 { + mux { + groups = "pwm_h_a2"; + function = "pwm_h"; + }; + }; + + pwm_h_pins5: pwm_h_pins5 { + mux { + groups = "pwm_h_d"; + function = "pwm_h"; + }; + }; + + pwm_i_pins1: pwm_i_pins1 { + mux { + groups = "pwm_i_m"; + function = "pwm_i"; + }; + }; + + pwm_i_pins2: pwm_i_pins2 { + mux { + groups = "pwm_i_a9"; + function = "pwm_i"; + }; + }; + + pwm_i_pins3: pwm_i_pins3 { + mux { + groups = "pwm_i_a3"; + function = "pwm_i"; + }; + }; + + pwm_i_pins4: pwm_i_pins4 { + mux { + groups = "pwm_i_d"; + function = "pwm_i"; + }; + }; + + pwm_j_pins1: pwm_j_pins1 { + mux { + groups = "pwm_j_x"; + function = "pwm_j"; + }; + }; + + pwm_j_pins2: pwm_j_pins2 { + mux { + groups = "pwm_j_m"; + function = "pwm_j"; + }; + }; + + pwm_j_pins3: pwm_j_pins3 { + mux { + groups = "pwm_j_a10"; + function = "pwm_j"; + }; + }; + + pwm_j_pins4: pwm_j_pins4 { + mux { + groups = "pwm_j_a4"; + function = "pwm_j"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + input-enable; + drive-strength = <3>; + }; + mux1 { + groups = "emmc_nand_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + drive-strength = <3>; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "emmc_clk"; + function = "emmc"; + bias-pull-down; + drive-strength = <3>; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + input-enable; + drive-strength = <4>; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd"; + function = "sdcard"; + bias-pull-up; + input-enable; + drive-strength = <4>; + }; + mux1 { + groups ="sdcard_clk"; + function = "sdcard"; + bias-pull-up; + output-high; + drive-strength = <4>; + }; + }; + + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "sdcard_clk"; + function = "sdcard"; + bias-pull-down; + drive-strength = <4>; + }; + }; + + to_sduart_pins: to_sduart_pins{ + mux { + groups = "uart_b_rx_c", "uart_b_tx_c"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + sd_to_uart_pins: sd_to_uart_pins{ + mux { + groups = "uart_b_rx_d", "uart_b_tx_d"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + spicc0_pins1: spicc0_pins1 { + mux { + groups = "spi_a_mosi_a", + "spi_a_miso_a", + "spi_a_sclk_a"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + spicc0_pins2: spicc0_pins2 { + mux { + groups = "spi_a_mosi_c", + "spi_a_miso_c", + "spi_a_sclk_c"; + function = "spi_a"; + drive-strength = <2>; + }; + }; + + spicc1_pins1: spicc1_pins1 { + mux { + groups = "spi_b_mosi_a", + "spi_b_miso_a", + "spi_b_sclk_a"; + function = "spi_b"; + drive-strength = <2>; + }; + }; + + spifc_pins: spifc_pins { + mux { + groups = "spif_mo", + "spif_mi", + "spif_clk", + "spif_cs", + "spif_hold", + "spif_wp_n"; + function = "spif"; + drive-strength = <4>; + }; + }; + external_eth_rmii_pins: external_eth_rmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength = <3>; + }; + }; + external_eth_rgmii_pins: external_eth_rgmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_tx_clk", + "eth_txen", + "eth_txd0", + "eth_txd1", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength = <3>; + }; + }; +};
diff --git a/arch/arm/dts/meson-c2_skt-panel.dtsi b/arch/arm/dts/meson-c2_skt-panel.dtsi new file mode 100644 index 0000000..c3ac22e --- /dev/null +++ b/arch/arm/dts/meson-c2_skt-panel.dtsi
@@ -0,0 +1,742 @@ +/* + * arch/arm64/boot/dts/amlogic/meson-c2__skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12a"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + */ + reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ + 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + */ + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_3{ + model_name = "TL050FHV02CT"; + interface = "mipi"; + basic_setting = <1080 1920 /*h_active, v_active*/ + 1125 2100 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 65 119>; /*screen_widht, screen_height*/ + lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/ + 44 108 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 118125000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 960 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <3>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 + 0 0 1 20 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 + 0 1 1 100 + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_4{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_3{ + index = <3>; + extern_name = "mipi_default";/*TL050FHV02CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 + 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00 + 0x00 0x38 0x00 0x00 + 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E + 0x00 0x38 0x00 0x10 0x03 0x04 + 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2 + 0x03 0xD3 0x0C + 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 3 0x99 0x00 0x00 + 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 + 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00 + 0x29 3 0x9C 0x00 0x00 + 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10 + 0x10 0x00 0x00 + 0x29 3 0x9E 0x00 0x00 + 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A + 0x1F 0x00 0x1F 0x14 0x1F + 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x15 + 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F + 0x0B 0x1F 0x09 0x1F 0x1F + 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09 + 0x1F 0x01 0x1F 0x15 0x1F + 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x14 + 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F + 0x08 0x1F 0x0A 0x1F 0x1F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 + 0x29 4 0xBC 0x00 0x00 0x00 + 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 + 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD4 0x03 0xC5 0x03 0xFF + 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD8 0x03 0xC5 0x03 0xFF + 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xDF 0x03 0xC5 0x03 0xFF + 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE3 0x03 0xC5 0x03 0xFF + 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE7 0x03 0xC5 0x03 0xFF + 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xEB 0x03 0xC5 0x03 0xFF + 0x29 4 0xB0 0x05 0x05 0x05 + 0x29 4 0xB1 0x05 0x05 0x05 + 0x29 4 0xB3 0x10 0x10 0x10 + 0x29 4 0xB4 0x06 0x06 0x06 + 0x29 4 0xB6 0x44 0x44 0x44 + 0x29 4 0xB7 0x34 0x34 0x34 + 0x29 4 0xB8 0x34 0x34 0x34 + 0x29 4 0xB9 0x24 0x24 0x24 + 0x29 4 0xBA 0x24 0x24 0x24 + 0x29 4 0xBC 0x00 0x70 0x00 + 0x29 4 0xBD 0x00 0x70 0x00 + 0x23 2 0xBE 0x50 + 0x23 2 0x35 0x00 + 0x13 1 0x11 + 0xfd 1 200 + 0x13 1 0x29 + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12a"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + /* pinctrl-0 = <&pwm_f_pins2>; */ + /* pinctrl-1 = <&bl_pwm_off_pins>; */ + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/ + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ +
diff --git a/arch/arm/dts/meson-g12.dtsi b/arch/arm/dts/meson-g12.dtsi index 4b74845..45bb2e9 100644 --- a/arch/arm/dts/meson-g12.dtsi +++ b/arch/arm/dts/meson-g12.dtsi
@@ -330,14 +330,10 @@ status = "disabled"; spi-flash@0 { compatible = "spi-flash"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; spi-nand@1 { compatible = "spi-nand"; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; };
diff --git a/arch/arm/dts/meson-g12a-s905d2-u200.dtsi b/arch/arm/dts/meson-g12a-s905d2-u200.dtsi old mode 100644 new mode 100755 index 800c4ac..839642b --- a/arch/arm/dts/meson-g12a-s905d2-u200.dtsi +++ b/arch/arm/dts/meson-g12a-s905d2-u200.dtsi
@@ -241,17 +241,7 @@ &usb2_phy_v2 { status = "okay"; portnum = <2>; - phy20-reset-level-bit = <16>; - phy21-reset-level-bit = <17>; - usb-reset-bit = <2>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f49e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; + dwc2_a_reg = <0xff400000>; }; &usb3_phy_v2 {
diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi index 509d7f7..5f1902b 100644 --- a/arch/arm/dts/meson-g12a.dtsi +++ b/arch/arm/dts/meson-g12a.dtsi
@@ -918,16 +918,20 @@ clock-names = "clkin", "clkin1", "clkin2", "clkin3"; }; -/* &spicc0 { - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_COMP>; - clock-names = "core", "comp"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC0>, + <&clkc CLKID_SPICC0_DIV>, <&clkc CLKID_SPICC0_GATE>; + clock-names = "core", "core-gate", "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC0_MUX>, <&clkc CLKID_SPICC0_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; }; &spicc1 { - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_COMP>; - clock-names = "core", "comp"; - }; -*/ + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC1>, + <&clkc CLKID_SPICC1_DIV>, <&clkc CLKID_SPICC1_GATE>; + clock-names = "core", "core-gate", "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC1_MUX>, <&clkc CLKID_SPICC1_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; +};
diff --git a/arch/arm/dts/meson-g12b-a311d-w400.dtsi b/arch/arm/dts/meson-g12b-a311d-w400.dtsi old mode 100644 new mode 100755 index 2c1f0ab..a19771a --- a/arch/arm/dts/meson-g12b-a311d-w400.dtsi +++ b/arch/arm/dts/meson-g12b-a311d-w400.dtsi
@@ -191,18 +191,7 @@ &usb2_phy_v2 { status = "okay"; portnum = <2>; - phy20-reset-level-bit = <16>; - phy21-reset-level-bit = <17>; - usb-reset-bit = <2>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0xfff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; - disconnect-threshold = <0x3c>; + dwc2_a_reg = <0xff400000>; }; &usb3_phy_v2 {
diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi index 20967cb..f3131ce 100644 --- a/arch/arm/dts/meson-g12b.dtsi +++ b/arch/arm/dts/meson-g12b.dtsi
@@ -910,19 +910,24 @@ }; -/* &spicc0 { - clocks = <&clkc CLKID_SPICC0>, - <&clkc CLKID_SPICC0_COMP>; - clock-names = "core", "comp"; + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC0>, + <&clkc CLKID_SPICC0_DIV>, <&clkc CLKID_SPICC0_GATE>; + clock-names = "core", "core-gate", "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC0_MUX>, <&clkc CLKID_SPICC0_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; }; &spicc1 { - clocks = <&clkc CLKID_SPICC1>, - <&clkc CLKID_SPICC1_COMP>; - clock-names = "core", "comp"; - }; -*/ + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC1>, + <&clkc CLKID_SPICC1_DIV>, <&clkc CLKID_SPICC1_GATE>; + clock-names = "core", "core-gate", "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC1_MUX>, <&clkc CLKID_SPICC1_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; +}; + /* &spifc { clocks = <&clkc CLKID_CLK81>;
diff --git a/arch/arm/dts/meson-sc2-mali.dtsi b/arch/arm/dts/meson-sc2-mali.dtsi new file mode 100644 index 0000000..2655b42 --- /dev/null +++ b/arch/arm/dts/meson-sc2-mali.dtsi
@@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +&apb { + mali: gpu@40000 { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + reg = <0x0 0x40000 0x0 0x40000>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/ + clock-names = "bus", "core"; + + /* + * Mali clocking is provided by two identical clock paths + * MALI_0 and MALI_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + */ + /* + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; *//* Glitch free mux */ + /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, *//* Do Nothing */ + //<&clkc CLKID_MALI_0>; + /*assigned-clock-rates = <0>,*/ /* Do Nothing */ + /* <666666666>, + <0>;*/ /* Do Nothing */ + }; +};
diff --git a/arch/arm/dts/meson-sc2-pxp.dts b/arch/arm/dts/meson-sc2-pxp.dts new file mode 100644 index 0000000..657a17e --- /dev/null +++ b/arch/arm/dts/meson-sc2-pxp.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-pxp.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-pxp", "amlogic,s905c2", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 PXP Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-pxp.dtsi b/arch/arm/dts/meson-sc2-pxp.dtsi new file mode 100644 index 0000000..adcb3ae --- /dev/null +++ b/arch/arm/dts/meson-sc2-pxp.dtsi
@@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905x4.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; +// mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + hs_co_phase = <2>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "disabled"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "disabled"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts new file mode 100644 index 0000000..f3dae71 --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-s905x4-ah212-ddr3.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-s905x4-ah212-dd3", "amlogic,s905x4", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 S905X4 AH212 DDR3 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi new file mode 100644 index 0000000..46c0c6d --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi
@@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905x4.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <3>; + init_tx_phase = <0>; + + hs_co_phase = <3>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; + spi-nand@1 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212.dts b/arch/arm/dts/meson-sc2-s905x4-ah212.dts new file mode 100644 index 0000000..d0237ae --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah212.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-s905x4-ah212.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-s905x4-ah212", "amlogic,s905x4", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 S905X4 AH212 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi new file mode 100644 index 0000000..2d1cba0 --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi
@@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905x4.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; + /*mc_val = <0x1621>;*/ +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <3>; + init_tx_phase = <0>; + + hs_co_phase = <3>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; + spi-nand@1 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah219.dts b/arch/arm/dts/meson-sc2-s905x4-ah219.dts new file mode 100644 index 0000000..87f3efd --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah219.dts
@@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "meson-sc2-s905x4-ah219.dtsi" +#include "meson-sc2_skt-panel.dtsi" + +/ { + compatible = "amlogic,sc2-s905x4-ah219", "amlogic,s905x4", "amlogic,meson-sc2"; + model = "Amlogic Meson SC2 S905X4 AH219 Board"; +}; + +/* This UART is brought out to the DB9 connector */ +&uart_a { + status = "okay"; +}; + +&uart_b { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* demo for i2c user */ +&i2c3 { + status= "disabled"; + clock-frequency = <100000>; + /* pinctrl-names = "default";*/ + /* pinctrl-0 = <&i2c3_master_pins2>;*/ +}; + +&pinctrl_periphs { + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + groups = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi new file mode 100644 index 0000000..3c5f16b --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi
@@ -0,0 +1,256 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. + * Based on meson-gx-p23x-q20x.dtsi: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * - Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +/* Common DTSI for devices which are based on the P212 reference board. */ + +#include "meson-sc2-s905x4.dtsi" + +/ { + aliases { + serial0 = &uart_b; + serial1 = &uart_a; + spi0 = &spifc; + spi1 = &spicc0; + spi2 = &spicc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c_gpio_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + vddio_boot: regulator-vddio_boot { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/ + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + tee: tee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; +}; + +ðmac { + status = "okay"; + internal_phy = <1>; + mc_val = <0x4be04>; +/*exphy setting*/ +// pinctrl-names = "external_eth_rgmii_pins"; +// pinctrl-0 = <&external_eth_rgmii_pins>; +// internal_phy = <0>; +// mc_val = <0x1621>; +}; + +&ir { + status = "disabled"; + /* pinctrl-0 = <&remote_input_ao_pins>; */ + /* pinctrl-names = "default"; */ +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao18>; +}; + +/* Wireless SDIO Module */ +&sd_emmc_a { + status = "disabled"; + /*pinctrl-0 = <&sdio_pins>;*/ + /*pinctrl-names = "default";*/ + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + non-removable; + disable-wp; + card_type = <3>; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_pins &to_sduart_pins>; + pinctrl-names = "sd_all_pins", "sd_uart"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + card_type = <5>; + + init_co_phase = <2>; + init_tx_phase = <0>; + + sd_hs_co_phase = <2>; + sd_hs_to_phase = <0>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + /* mmc-ddr-1_8v; */ + card_type = <1>; + + init_co_phase = <3>; + init_tx_phase = <0>; + + hs_co_phase = <3>; + hs_to_phase = <0>; + + hs2_co_phase = <2>; + hs2_to_phase = <0>; + + hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vddio_boot>; +}; + +/* nand */ +&nand { + status = "okay"; + pinctrl-names = "default", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&nand_cs_pins>; +}; + +&dwc3 { + status = "okay"; + dr_mode = "host"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + /* pinctrl-0 = <&pwm_e_pins>; */ + /* pinctrl-names = "default"; */ +}; + +/* This is connected to the Bluetooth module: */ +&uart_a { + status = "okay"; + /* pinctrl-0 = <&a_uart_pins>; */ + /* pinctrl-names = "default"; */ + uart-has-rtscts; +}; + +&spifc { + status = "okay"; + cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>; + spi-flash@0 { + status = "okay"; + }; + spi-nand@1 { + status = "okay"; + }; +}; + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins_h>; + cs-gpios = <&gpio GPIOH_6 0>; +};
diff --git a/arch/arm/dts/meson-sc2-s905x4.dtsi b/arch/arm/dts/meson-sc2-s905x4.dtsi new file mode 100644 index 0000000..fb227cf --- /dev/null +++ b/arch/arm/dts/meson-sc2-s905x4.dtsi
@@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-sc2.dtsi" +#include "meson-sc2-mali.dtsi" + +/ { + compatible = "amlogic,s905x4", "amlogic,meson-sc2"; +}; + +ðmac { + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +};
diff --git a/arch/arm/dts/meson-sc2-series.dtsi b/arch/arm/dts/meson-sc2-series.dtsi new file mode 100644 index 0000000..7c1b712 --- /dev/null +++ b/arch/arm/dts/meson-sc2-series.dtsi
@@ -0,0 +1,511 @@ +/* + * Copyright (c) 2016 Andreas Färber + * + * Copyright (c) 2016 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> +#include <dt-bindings/clock/sc2-clkc.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 16 MiB reserved for Hardware ROM Firmware */ + hwrom_reserved: hwrom@0 { + reg = <0x0 0x0 0x0 0x1000000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@10000000 { + reg = <0x0 0x10000000 0x0 0x200000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0xbc00000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + firmware { + sm: secure-monitor { + compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; + }; + }; + + efuse: efuse { + compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse"; + #address-cells = <1>; + #size-cells = <1>; + + }; + + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@2c001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xffc01000 0 0x1000>, + <0x0 0xffc02000 0 0x2000>, + <0x0 0xffc04000 0 0x2000>, + <0x0 0xffc06000 0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + sram: sram@f7000000 { + compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram"; + reg = <0x0 0xf7000000 0x0 0x48000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xf7000000 0x48000>; + + cpu_scp_lpri: scp-shmem@0 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47000 0x400>; + }; + + cpu_scp_hpri: scp-shmem@200 { + compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + reg = <0x47400 0x400>; + }; + }; + + cbus: cbus@fe070000 { + compatible = "simple-bus"; + reg = <0x0 0xfe070000 0x0 0xF000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>; + + uart_a: serial@8000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x8000 0x0 0x18>; + clocks = <&xtal>; + status = "disabled"; + }; + + uart_b: serial@a000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0xa000 0x0 0x18>; + clocks = <&xtal>; + status = "disabled"; + }; + + ir: ir@8040 { + compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; + reg = <0x0 0x8040 0x0 0x40>; + interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + reset: reset-controller@1000 { + compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; + reg = <0x0 0x01000 0x0 0x1000>; + #reset-cells = <1>; + }; + + uart_c: serial@22000 { + compatible = "amlogic,meson-uart"; + reg = <0x0 0x22000 0x0 0x18>; + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>; + status = "disabled"; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "okay"; + select = "disable"; /* disable/jtag-a/jtag-b */ + pinctrl-names="jtag_a_pins", "jtag_b_pins"; + pinctrl-0=<&jtag_a_pins>; + pinctrl-1=<&jtag_b_pins>; + }; + }; + + periphs: periphs@ff634000 { + compatible = "simple-bus"; + reg = <0x0 0xff634000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + + hwrng: rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x0 0x0 0x4>; + }; + }; + + hiubus: hiubus@ff63c000 { + compatible = "simple-bus"; + reg = <0x0 0xff63c000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>; + + mailbox: mailbox@404 { + compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; + reg = <0 0x404 0 0x4c>; + interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, + <0 209 IRQ_TYPE_EDGE_RISING>, + <0 210 IRQ_TYPE_EDGE_RISING>; + #mbox-cells = <1>; + }; + }; + + clkc: clock-controller@0 { + compatible = "amlogic,sc2-clkc"; + #clock-cells = <1>; + reg = <0x0 0xfe000000 0x0 0x82e8>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + i2c0: i2c@fe001400 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe066000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@fe005c00 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe068000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe006800 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06a000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe006c00 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06c000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe00b000 { + compatible = "amlogic,meson-i2c"; + reg = <0x0 0xfe06e000 0x0 0x24>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc0: spi@fe050000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0xfe050000 0x0 0x44>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc1: spi@fe052000 { + compatible = "amlogic,meson-g12a-spicc"; + reg = <0x0 0xfe052000 0x0 0x44>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@fe056000 { + compatible = "amlogic,spifc"; + status = "disabled"; + reg = <0x0 0xfe056000 0x0 0x80>; + /* clocks = <&clkc CLKID_CLK81>; */ + /* clock-names = "core"; */ + pinctrl-names = "default"; + pinctrl-0 = <&spifc_pins>; + #address-cells = <1>; + #size-cells = <0>; + spi-flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; + spi-nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <20000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "disabled"; + }; + }; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic,g12a-eth-dwmac"; + phy_cntl1 = <0x41054147>; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + status = "disabled"; + }; + + saradc: adc@fe026000 { + compatible = "amlogic,meson-saradc"; + reg = <0x0 0xfe026000 0x0 0x48>; + status = "disabled"; + }; + + nand: nfc@fe08c800 { + compatible = "amlogic,meson-nfc"; + reg = <0x0 0xfe08c800 0x0 0x200>; + interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clk_reg = <0 0xfe08c000>; + }; + + apb: apb@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x1000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + + watchdog@2100 { + compatible = "amlogic,meson-sc2-wdt"; + reg = <0x0 0x2100 0x0 0x10>; + clocks = <&xtal>; + clock-names = "wdt-clk"; + }; + + sd_emmc_a: sdio { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x88000 0x0 0x800>; + interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sdio"; + }; + + sd_emmc_b: sd { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x8a000 0x0 0x800>; + interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "sd"; + }; + + sd_emmc_c: emmc { + compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x8c000 0x0 0x800>; + interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + pinname = "emmc"; + }; + }; + + dwc3: dwc3@fde00000 { + compatible = "snps,dwc3","synopsys,xhci-dwc3"; + status = "disable"; + reg = <0x0 0xfde00000 0x0 0x100000>; + phys = <&usb2_phy_v2>, <&usb3_phy_v2>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + usb2_phy_v2: usb2phy@fe03a000 { + compatible = "amlogic, amlogic-new-usb2-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <2>; + reg = <0x0 0xfe03a000 0x0 0x80 + 0x0 0xFE002000 0x0 0x100 + 0x0 0xfe03c000 0x0 0x2000 + 0x0 0xfe03e000 0x0 0x2000>; + dwc2_a_reg = <0xfdd00000>; + #phy-cells = <0>; + }; + + usb3_phy_v2: usb3phy@fe03a080 { + compatible = "amlogic, amlogic-new-usb3-v2"; + status = "disable"; + #address-cells = <2>; + #size-cells = <2>; + phy-version = <3>; + reg = <0x0 0xfe03a080 0x0 0x20>; + phy-reg = <0xfe03c000>; + phy-reg-size = <0x2000>; + usb2-phy-reg = <0xfe03a000>; + usb2-phy-reg-size = <0x80>; + #phy-cells = <0>; + }; + }; +};
diff --git a/arch/arm/dts/meson-sc2.dtsi b/arch/arm/dts/meson-sc2.dtsi new file mode 100644 index 0000000..6cad1e6 --- /dev/null +++ b/arch/arm/dts/meson-sc2.dtsi
@@ -0,0 +1,819 @@ +/* + * Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione <carlo@endlessm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "meson-sc2-series.dtsi" +#include <dt-bindings/gpio/meson-sc2-gpio.h> +#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/pwm/meson.h> + +/ { + compatible = "amlogic,meson-sc2"; + + vpu { + compatible = "amlogic, vpu-g12a"; + status = "okay"; + /*clocks = <&clkc CLKID_VAPB_MUX>, + * <&clkc CLKID_VPU_INTR>, + * <&clkc CLKID_VPU_P0_COMP>, + * <&clkc CLKID_VPU_P1_COMP>, + * <&clkc CLKID_VPU_MUX>; + *clock-names = "vapb_clk", + * "vpu_intr_gate", + * "vpu_clk0", + * "vpu_clk1", + * "vpu_clk"; + */ + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + fb { + status = "okay"; + logo_addr = "0x7f800000"; + }; + + pinctrl_periphs: pinctrl@fe004000 { + compatible = "amlogic,meson-sc2-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@fe004000 { + reg = <0x0 0xfe004000 0x0 0x004c>, + <0x0 0xfe0040c0 0x0 0x0220>; + reg-names = "mux", + "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_periphs 0 0 87>; + }; + }; + + i2c_gpio_0: i2c-gpio-0 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + status = "okay"; + gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */ + <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */ + + i2c-gpio,delay-us = <5>; + is_odpin = <1>; + }; + + pwm_ab: pwm@fe058000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe058000 0x0 0x20>, + <0x0 0xfe000180 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@fe05a000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05a000 0x0 0x20>, + <0x0 0xfe000184 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@fe05c000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05c000 0x0 0x20>, + <0x0 0xfe000188 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_gh: pwm@fe05e000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe05e000 0x0 0x20>, + <0x0 0xfe00018c 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ij: pwm@fe060000 { + compatible = "amlogic,meson-v2-pwm"; + reg = <0x0 0xfe060000 0x0 0x20>, + <0x0 0xfe000190 0x0 0x04>; + #pwm-cells = <3>; + status = "disabled"; + }; +}; + +ðmac { + compatible = "amlogic,g12a-eth-dwmac"; + reg = <0x0 0xfdc00000 0x0 0x10000 + 0x0 0xFE024000 0x0 0x8 + 0x0 0xFE028000 0x0 0xa0>; + reg-names = "eth_base", "eth_top", "eth_cfg"; + phy_cntl1 = <0x41054147>; + internal_phy = <1>; + mc_val = <0x4be04>; + cali_val = <0x80000>; + reset-gpios = <&gpio GPIOZ_15 GPIO_ACTIVE_HIGH>; + analog_ver = <1>; /*1:c1; 2:c2*/ + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + chip_num = <3>; + //tx_amp_src = <0xfe005b30>; +// clocks = <&clkc CLKID_ETH_CORE>, +// <&clkc CLKID_FCLK_DIV2>, +// <&clkc CLKID_MPLL2>; +// clock-names = "stmmaceth", "clkin0", "clkin1"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&periphs { + + eth-phy-mux { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x15c 0x0 0x4>; + mux-mask = <0xffffffff>; + mdio-parent-bus = <&mdio0>; + + internal_mdio: mdio@e40908ff { + reg = <0xe40908ff>; + #address-cells = <1>; + #size-cells = <0>; + + internal_phy: ethernet-phy@8 { + compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; + reg = <8>; + max-speed = <100>; + }; + }; + + external_mdio: mdio@2009087f { + reg = <0x2009087f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&saradc { + compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc"; + clocks = <&xtal>, + <&clkc CLKID_SARADC_MUX>, + <&clkc CLKID_SARADC_DIV>, + <&clkc CLKID_SAR_ADC_GATE>; + clock-names = "xtal", "adc_mux", "adc_div", "adc_gate"; +}; + +&sd_emmc_a { + clocks = <&clkc CLKID_SD_EMMC_A_MUX>, + <&clkc CLKID_SD_EMMC_A_DIV>, + <&clkc CLKID_SD_EMMC_A_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_b { + clocks = <&clkc CLKID_SD_EMMC_B_MUX>, + <&clkc CLKID_SD_EMMC_B_DIV>, + <&clkc CLKID_SD_EMMC_B_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&sd_emmc_c { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "clkin", "xtal"; +}; + +&nand { + clocks = <&clkc CLKID_SD_EMMC_C_MUX>, + <&clkc CLKID_SD_EMMC_C_DIV>, + <&clkc CLKID_SD_EMMC_C_GATE>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_XTAL>; + clock-names = "mux", "div", "gate", "fdiv2", "xtal"; +}; + +&spicc0 { + clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC, no set for power on already */ + /* pm-id = <22>; */ +}; + +&spicc1 { + clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>; + clock-names = "async", "async-gate"; + assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>; + assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>; + assigned-clock-rates = <0>, <200000000>; + /* =PM_SPICC_B, no set for power on already */ + /* pm-id = <39>; */ +}; + +&pinctrl_periphs { + i2c0_master_pins1:i2c0_pins1 { + mux { + groups = "i2c_a_sda_c", + "i2c_a_scl_c"; + function = "i2c_a"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_master_pins2:i2c0_pins2 { + mux { + groups = "i2c_a_sda_h", + "i2c_a_scl_h"; + function = "i2c_a"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_master_pins3:i2c0_pins3 { + mux { + groups = "i2c_a_sda_z0", + "i2c_a_scl_z1"; + function = "i2c_a"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c0_master_pins4:i2c0_pins4 { + mux { + groups = "i2c_a_sda_z7", + "i2c_a_scl_z8"; + function = "i2c_a"; + drive-strength = <3>; + bias-disable; + + }; + }; + + i2c1_master_pins1:i2c1_pins1 { + mux { + groups = "i2c_b_sda_z", + "i2c_b_scl_z"; + function = "i2c_b"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_master_pins2:i2c1_pins2 { + mux { + groups = "i2c_b_sda_x", + "i2c_b_scl_x"; + function = "i2c_b"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_master_pins3:i2c1_pins3 { + mux { + groups = "i2c_b_sda_h2", + "i2c_b_scl_h3"; + function = "i2c_b"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c1_master_pins4:i2c1_pins4 { + mux { + groups = "i2c_b_sda_h6", + "i2c_b_scl_h7"; + function = "i2c_b"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_master_pins1:i2c2_pins1 { + mux { + groups = "i2c_c_sda_x", + "i2c_c_scl_x"; + function = "i2c_c"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_master_pins2:i2c2_pins2 { + mux { + groups = "i2c_c_sda_z10", + "i2c_c_scl_z11"; + function = "i2c_c"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c2_master_pins3:i2c2_pins3 { + mux { + groups = "i2c_c_sda_z14", + "i2c_c_scl_z15"; + function = "i2c_c"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c3_master_pins1:i2c3_pins1 { + mux { + groups = "i2c_d_sda_h", + "i2c_d_scl_h"; + function = "i2c_d"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c3_master_pins2:i2c3_pins2 { + mux { + groups = "i2c_d_sda_a", + "i2c_d_scl_a"; + function = "i2c_d"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_master_pin1:i2c4_pins1 { + mux { + groups = "i2c_e_sda_d", + "i2c_e_scl_d"; + function = "i2c_e"; + drive-strength = <3>; + bias-disable; + }; + }; + + i2c4_master_pin2:i2c4_pins2 { + mux { + groups = "i2c_e_sda_e", + "i2c_e_scl_e"; + function = "i2c_e"; + drive-strength = <3>; + bias-disable; + }; + }; + + jtag_a_pins:jtag_a_pin { + mux { + groups = "jtag_1_clk", + "jtag_1_tms", + "jtag_1_tdi", + "jtag_1_tdo"; + function = "jtag_1"; + }; + }; + + jtag_b_pins:jtag_b_pin { + mux { + groups = "jtag_2_clk", + "jtag_2_tms", + "jtag_2_tdi", + "jtag_2_tdo"; + function = "jtag_2"; + }; + }; + + swd_a_pins:swd_a_pin { + mux { + groups = "swclk", + "swdio"; + function = "sw"; + }; + }; + + emmc_pins: emmc { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + input-enable; + }; + mux1 { + groups = "emmc_nand_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "emmc_clk"; + function = "emmc"; + bias-pull-down; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + }; + }; + + sdcard_pins: sdcard { + mux { + groups = "sdcard_d0_c", + "sdcard_d1_c", + "sdcard_d2_c", + "sdcard_d3_c", + "sdcard_cmd_c"; + function = "sdcard"; + bias-pull-up; + input-enable; + drive-strength = <4>; + }; + mux1 { + groups ="sdcard_clk_c"; + function = "sdcard"; + bias-pull-up; + output-high; + drive-strength = <4>; + }; + }; + + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "sdcard_clk_c"; + function = "sdcard"; + bias-pull-down; + }; + }; + + to_sduart_pins: to_sduart_pins{ + mux { + groups = "uart_b_rx_c", "uart_b_tx_c"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + sd_to_uart_pins: sd_to_uart_pins{ + mux { + groups = "uart_b_rx_d", "uart_b_tx_d"; + function = "uart_b"; + bias-pull-up; + input-enable; + }; + }; + + spicc0_pins_x: spicc0_pins_x { + mux { + groups = "spi_a_mosi_x", + "spi_a_miso_x", + //"spi_a_ss0_x", + "spi_a_sclk_x"; + function = "spi_a"; + drive-strength = <1>; + }; + }; + + spicc0_pins_c: spicc0_pins_c { + mux { + groups = "spi_a_mosi_c", + "spi_a_miso_c", + //"spi_a_ss0_c", + "spi_a_sclk_c"; + function = "spi_a"; + drive-strength = <1>; + }; + }; + + spicc1_pins_h: spicc1_pins_h { + mux { + groups = "spi_b_mosi_h", + "spi_b_miso_h", + //"spi_b_ss0_h", + "spi_b_sclk_h"; + function = "spi_b"; + drive-strength = <1>; + }; + }; + + spifc_pins: spifc_pins { + mux { + groups = "nor_d", + "nor_q", + "nor_c", + //"nor_cs", + "nor_hold", + "nor_wp"; + function = "nor"; + drive-strength = <3>; + }; + }; + + pwm_a_pins1: pwm_a_pins1 { + mux { + groups = "pwm_a_e"; + function = "pwm_a"; + }; + }; + + pwm_a_pins2: pwm_a_pins2 { + mux { + groups = "pwm_a_x"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b_h"; + function = "pwm_b"; + }; + }; + + pwm_b_pins2: pwm_b_pins2 { + mux { + groups = "pwm_b_z0"; + function = "pwm_b"; + }; + }; + + pwm_b_pins3: pwm_b_pins3 { + mux { + groups = "pwm_b_z13"; + function = "pwm_b"; + }; + }; + + pwm_b_pins4: pwm_b_pins4 { + mux { + groups = "pwm_b_x7"; + function = "pwm_b"; + }; + }; + + pwm_b_pins5: pwm_b_pins5 { + mux { + groups = "pwm_b_x19"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c_c"; + function = "pwm_c"; + }; + }; + + pwm_c_pins2: pwm_c_pins2 { + mux { + groups = "pwm_c_x"; + function = "pwm_c"; + }; + }; + + pwm_c_pins3: pwm_c_pins3 { + mux { + groups = "pwm_c_z"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d_z"; + function = "pwm_d"; + }; + }; + + pwm_d_pins2: pwm_d_pins2 { + mux { + groups = "pwm_d_x3"; + function = "pwm_d"; + }; + }; + + pwm_d_pins3: pwm_d_pins3 { + mux { + groups = "pwm_d_x6"; + function = "pwm_d"; + }; + }; + + pwm_e_pins: pwm_e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_h"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm_f_pins3 { + mux { + groups = "pwm_f_z"; + function = "pwm_f"; + }; + }; + + pwm_g_pins1: pwm_g_pins1 { + mux { + groups = "pwm_g"; + function = "pwm_g"; + }; + }; + + pwm_h_pins1: pwm_h_pins1 { + mux { + groups = "pwm_h"; + function = "pwm_h"; + }; + }; + + pwm_i_pins1: pwm_i_pins1 { + mux { + groups = "pwm_i_d4"; + function = "pwm_i"; + }; + }; + + pwm_i_pins2: pwm_i_pins2 { + mux { + groups = "pwm_i_d6"; + function = "pwm_i"; + }; + }; + + pwm_j_pins1: pwm_j_pins1 { + mux { + groups = "pwm_j_e"; + function = "pwm_j"; + }; + }; + + pwm_j_pins2: pwm_j_pins2 { + mux { + groups = "pwm_j_d5"; + function = "pwm_j"; + }; + }; + + pwm_j_pins3: pwm_j_pins3 { + mux { + groups = "pwm_j_d10"; + function = "pwm_j"; + }; + }; + + pwm_i_hiz_pins1: pwm_i_hiz_pins1 { + mux { + groups = "pwm_i_hiz"; + function = "pwm_i_hiz"; + }; + }; + + pwm_g_hiz_pins1: pwm_g_hiz_pins1 { + mux { + groups = "pwm_g_hiz"; + function = "pwm_g_hiz"; + }; + }; + external_eth_rmii_pins: external_eth_rmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_txen", + "eth_txd0", + "eth_txd1"; + function = "eth"; + drive-strength = <3>; + }; + }; + external_eth_rgmii_pins: external_eth_rgmii_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen", + "eth_txd0", + "eth_txd1", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength = <3>; + }; + }; +};
diff --git a/arch/arm/dts/meson-sc2_skt-panel.dtsi b/arch/arm/dts/meson-sc2_skt-panel.dtsi new file mode 100644 index 0000000..fbb676c --- /dev/null +++ b/arch/arm/dts/meson-sc2_skt-panel.dtsi
@@ -0,0 +1,742 @@ +/* + * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12a"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + */ + reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */ + 0x0 0xff644000 0x0 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + */ + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_3{ + model_name = "TL050FHV02CT"; + interface = "mipi"; + basic_setting = <1080 1920 /*h_active, v_active*/ + 1125 2100 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 65 119>; /*screen_widht, screen_height*/ + lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/ + 44 108 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 118125000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 960 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <3>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 + 0 0 1 20 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 + 0 1 1 100 + 0xff 0 0 0>; + backlight_index = <0>; + }; + + lcd_4{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_3{ + index = <3>; + extern_name = "mipi_default";/*TL050FHV02CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03 + 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00 + 0x00 0x38 0x00 0x00 + 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E + 0x00 0x38 0x00 0x10 0x03 0x04 + 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2 + 0x03 0xD3 0x0C + 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 + 0x29 3 0x99 0x00 0x00 + 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00 + 0x00 0x00 0x00 0x00 0x00 0x00 + 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00 + 0x29 3 0x9C 0x00 0x00 + 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10 + 0x10 0x00 0x00 + 0x29 3 0x9E 0x00 0x00 + 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A + 0x1F 0x00 0x1F 0x14 0x1F + 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x15 + 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F + 0x0B 0x1F 0x09 0x1F 0x1F + 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09 + 0x1F 0x01 0x1F 0x15 0x1F + 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x1F + 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F + 0x1F 0x1F 0x1F 0x1F 0x14 + 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F + 0x08 0x1F 0x0A 0x1F 0x1F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00 + 0x29 4 0xBC 0x00 0x00 0x00 + 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F + 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01 + 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD4 0x03 0xC5 0x03 0xFF + 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xD8 0x03 0xC5 0x03 0xFF + 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xDF 0x03 0xC5 0x03 0xFF + 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE3 0x03 0xC5 0x03 0xFF + 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xE7 0x03 0xC5 0x03 0xFF + 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00 + 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D + 0x00 0x79 0x00 0xA7 + 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01 + 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED + 0x02 0x2F 0x02 0x74 + 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02 + 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73 + 0x03 0x8C 0x03 0xA5 + 0x29 5 0xEB 0x03 0xC5 0x03 0xFF + 0x29 4 0xB0 0x05 0x05 0x05 + 0x29 4 0xB1 0x05 0x05 0x05 + 0x29 4 0xB3 0x10 0x10 0x10 + 0x29 4 0xB4 0x06 0x06 0x06 + 0x29 4 0xB6 0x44 0x44 0x44 + 0x29 4 0xB7 0x34 0x34 0x34 + 0x29 4 0xB8 0x34 0x34 0x34 + 0x29 4 0xB9 0x24 0x24 0x24 + 0x29 4 0xBA 0x24 0x24 0x24 + 0x29 4 0xBC 0x00 0x70 0x00 + 0x29 4 0xBD 0x00 0x70 0x00 + 0x23 2 0xBE 0x50 + 0x23 2 0x35 0x00 + 0x13 1 0x11 + 0xfd 1 200 + 0x13 1 0x29 + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12a"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + /* pinctrl-0 = <&pwm_f_pins2>; */ + /* pinctrl-1 = <&bl_pwm_off_pins>; */ + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/ + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ +
diff --git a/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi b/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi old mode 100644 new mode 100755 index 1d5d97d..839642b --- a/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi +++ b/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi
@@ -241,21 +241,7 @@ &usb2_phy_v2 { status = "okay"; portnum = <2>; - phy20-reset-level-bit = <16>; - phy21-reset-level-bit = <17>; - usb-reset-bit = <2>; - u2-ctrl-sleep-shift = <17>; - u2-hhi-mem-pd-shift = <30>; - u2-hhi-mem-pd-mask = <0x3>; - u2-ctrl-iso-shift = <17>; - pll-setting-1 = <0x09400414>; - pll-setting-2 = <0x927E0000>; - pll-setting-3 = <0xac5f69e5>; - pll-setting-4 = <0xfe18>; - pll-setting-5 = <0x8000fff>; - pll-setting-6 = <0x78000>; - pll-setting-7 = <0xe0004>; - pll-setting-8 = <0xe000c>; + dwc2_a_reg = <0xff400000>; }; &usb3_phy_v2 {
diff --git a/arch/arm/include/asm/arch-a1/bl31_apis.h b/arch/arm/include/asm/arch-a1/bl31_apis.h index 6982ca5..e6faefa 100644 --- a/arch/arm/include/asm/arch-a1/bl31_apis.h +++ b/arch/arm/include/asm/arch-a1/bl31_apis.h
@@ -87,6 +87,16 @@ /*set boot first timeout*/ #define SET_BOOT_FIRST 0x82000087 +/* KEYMASTER */ +#define SET_BOOT_PARAMS 0x82000072 +#define SHA256_DIGEST_SIZE 32 +typedef struct { + uint32_t device_locked; + uint32_t verified_boot_state; + uint8_t verified_boot_key[SHA256_DIGEST_SIZE]; + uint8_t verified_boot_hash[SHA256_DIGEST_SIZE]; +} keymaster_boot_params; + /* Secure HAL APIs */ #define TRUSTZONE_HAL_API_SRAM 0x400 @@ -152,4 +162,5 @@ void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0); void set_boot_first_timeout(uint64_t arg0); int bl31_get_cornerinfo(uint8_t *outbuf, int size); +int32_t set_boot_params(const keymaster_boot_params*); #endif
diff --git a/arch/arm/include/asm/arch-a1/cpu.h b/arch/arm/include/asm/arch-a1/cpu.h index d41497e..676a912 100644 --- a/arch/arm/include/asm/arch-a1/cpu.h +++ b/arch/arm/include/asm/arch-a1/cpu.h
@@ -24,8 +24,13 @@ /* #define CONFIG_DDR_SIZE 256 */ /* dram */ +#ifdef CONFIG_UBOOT_RUN_IN_SRAM #define PHYS_SDRAM_1_BASE 0xFFE00000UL #define PHYS_SDRAM_1_SIZE 0x00180000UL +#else +#define PHYS_SDRAM_1_BASE 0x00000000UL +#define PHYS_SDRAM_1_SIZE 0x10000000UL +#endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE)
diff --git a/arch/arm/include/asm/arch-a1/register.h b/arch/arm/include/asm/arch-a1/register.h index f81cd35..d800df7 100644 --- a/arch/arm/include/asm/arch-a1/register.h +++ b/arch/arm/include/asm/arch-a1/register.h
@@ -4078,6 +4078,6 @@ // // Closing file: ./REG_LIST_RTL.h // - +#include "soc_def.h" #endif // REGISTER_H
diff --git a/arch/arm/include/asm/arch-a1/soc_def.h b/arch/arm/include/asm/arch-a1/soc_def.h new file mode 100644 index 0000000..f0a0b1a --- /dev/null +++ b/arch/arm/include/asm/arch-a1/soc_def.h
@@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __A1_DEF_H__ +#define __A1_DEF_H__ + +#define SEC_AO_SEC_GP_CFG2 (SYSCTRL_SEC_STATUS_REG6) + +#endif /* __A1_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-a1/timing.h b/arch/arm/include/asm/arch-a1/timing.h index 9c8284a..a431d1b 100644 --- a/arch/arm/include/asm/arch-a1/timing.h +++ b/arch/arm/include/asm/arch-a1/timing.h
@@ -36,6 +36,11 @@ #define POWERKEY_CFG2 2 #define POWERKEY_CFG3 3 +/* Share vddcore parameters with bl2 */ +#define BL2_INIT_STAGE_VDDCORE_TABLE 0x84 +#define BL2_INIT_STAGE_VDDCORE_CONFIG 0x85 +#define BL2_INIT_STAGE_VDDCORE_CONFIG_1 0x86 + typedef struct bl2_reg { unsigned int reg; unsigned int value; @@ -370,7 +375,7 @@ //system reserve,do not modify /* align8 */ unsigned char char_rev1; - unsigned char char_rev2; + unsigned char training_offset;//char_rev2; unsigned int ddr_dmc_remap[5]; unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify @@ -520,4 +525,4 @@ PMU_SMB_LPDDR4_2D_t lpddr4u_2d; } dmem_cfg_t; -#endif //__AML_TIMING_H_ \ No newline at end of file +#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-a1/usb.h b/arch/arm/include/asm/arch-a1/usb.h index c01594a..0efea92 100644 --- a/arch/arm/include/asm/arch-a1/usb.h +++ b/arch/arm/include/asm/arch-a1/usb.h
@@ -10,6 +10,8 @@ #include <asm/types.h> #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> +#include <generic-phy.h> +#include <asm-generic/gpio.h> #define USB_PHY_PORT_MAX 1 /* Phy register MACRO definitions */ @@ -74,6 +76,23 @@ /* XHCI PHY register structure */ #define PHY_REGISTER_SIZE 0x20 + +struct phy_aml_usb2_priv { + unsigned int base_addr; + unsigned int reset_addr; + unsigned int dwc2_a_addr; + unsigned int u2_port_num; + unsigned int usbphy_reset_bit[8]; + unsigned int clktree_usb_bus_ctrl_addr; + unsigned int usb_phy2_pll_base_addr[4]; +}; + +struct phy_aml_usb3_priv { + unsigned int base_addr; + unsigned int usb3_port_num; + struct gpio_desc desc; +}; + /* Register definitions */ typedef struct u2p_aml_regs { volatile uint32_t u2p_r0; @@ -216,5 +235,13 @@ #define USB_ID_MODE_HARDWARE (1) #define USB_ID_MODE_SW_HOST (2) #define USB_ID_MODE_SW_DEVICE (3) +int usb2_phy_tuning(uint32_t phy2_pll_base, int port); +void set_usb_pll(uint32_t phy2_pll_base); +int usb_save_phy_dev (unsigned int number, struct phy *phy); +int usb2_phy_init (struct phy *phy); +unsigned int usb_get_dwc_a_base_addr(void); +unsigned int usb_get_device_mode_phy_base(void); +void usb_phy_tuning_reset(void); +void usb_device_mode_init(void); #endif
diff --git a/arch/arm/include/asm/arch-c1/acs.h b/arch/arm/include/asm/arch-c1/acs.h index c98cbee..65de6df 100644 --- a/arch/arm/include/asm/arch-c1/acs.h +++ b/arch/arm/include/asm/arch-c1/acs.h
@@ -46,6 +46,7 @@ char board_id[12]; unsigned short ddr_struct_size[12]; unsigned long ddr_struct_org_size; + char revision[40]; }__attribute__ ((packed)) acs_set_t; #endif
diff --git a/arch/arm/include/asm/arch-c1/bl31_apis.h b/arch/arm/include/asm/arch-c1/bl31_apis.h index fc573cc..df5b0ba 100644 --- a/arch/arm/include/asm/arch-c1/bl31_apis.h +++ b/arch/arm/include/asm/arch-c1/bl31_apis.h
@@ -88,6 +88,16 @@ /*set boot first timeout*/ #define SET_BOOT_FIRST 0x82000087 +/* KEYMASTER */ +#define SET_BOOT_PARAMS 0x82000072 +#define SHA256_DIGEST_SIZE 32 +typedef struct { + uint32_t device_locked; + uint32_t verified_boot_state; + uint8_t verified_boot_key[SHA256_DIGEST_SIZE]; + uint8_t verified_boot_hash[SHA256_DIGEST_SIZE]; +} keymaster_boot_params; + /* Secure HAL APIs */ #define TRUSTZONE_HAL_API_SRAM 0x400 @@ -156,4 +166,5 @@ void set_boot_first_timeout(uint64_t arg0); int bl31_get_cornerinfo(uint8_t *outbuf, int size); unsigned aml_get_dvfs_id(void); +int32_t set_boot_params(const keymaster_boot_params*); #endif
diff --git a/arch/arm/include/asm/arch-c1/cpu.h b/arch/arm/include/asm/arch-c1/cpu.h index 9105538..84de9fa 100644 --- a/arch/arm/include/asm/arch-c1/cpu.h +++ b/arch/arm/include/asm/arch-c1/cpu.h
@@ -21,7 +21,7 @@ #endif /* for uboot envrionment use */ -/* #define CONFIG_DDR_SIZE 256 */ +#define CONFIG_DDR_SIZE 256 /* dram */ #define PHYS_SDRAM_1_BASE 0x00000000UL
diff --git a/arch/arm/include/asm/arch-c1/register.h b/arch/arm/include/asm/arch-c1/register.h index c5b36d0..34a8114 100644 --- a/arch/arm/include/asm/arch-c1/register.h +++ b/arch/arm/include/asm/arch-c1/register.h
@@ -7220,6 +7220,6 @@ // // Closing file: ./REG_LIST_RTL.h // - +#include "soc_def.h" #endif // REGISTER_H
diff --git a/arch/arm/include/asm/arch-c1/regs.h b/arch/arm/include/asm/arch-c1/regs.h index 8b13789..7b2bcac 100644 --- a/arch/arm/include/asm/arch-c1/regs.h +++ b/arch/arm/include/asm/arch-c1/regs.h
@@ -1 +1,58 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ +#ifndef __AML_REG_H__ +#define __AML_REG_H__ +/* + * all used regs + */ +/* + * ISA_TIMERE use SYSCTRL_TIMERE + * WATCHDOG_CNTL use RESETCTRL_WATCHDOG_CTRL0 + * WATCHDOG_TCNT use RESETCTRL_WATCHDOG_CNT + * WATCHDOG_RST use RESETCTRL_WATCHDOG_CLR + */ +#define ISA_TIMERE ((0x0041 << 2) + 0xfe005800) +#define WATCHDOG_CNTL ((0x0040 << 2) + 0xfe000000) +#define WATCHDOG_TCNT ((0x0042 << 2) + 0xfe000000) +#define WATCHDOG_RST ((0x0043 << 2) + 0xfe000000) + +/* + * SEC_AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4 + * AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4 + * AO_RTI_STATUS_REG3 use SYSCTRL_SEC_STICKY_REG1 + * AO_SEC_SD_CFG15 use SYSCTRL_SEC_STATUS_REG2 + */ +#define SEC_AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800) +#define AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800) +#define AO_RTI_STATUS_REG3 ((0x00e1 << 2) + 0xfe005800) +#define AO_SEC_SD_CFG15 ((0x00c2 << 2) + 0xfe005800) + +/* PREG_STICKY_REG8 use SYSCTRL_STICKY_REG7 + * P_AO_SEC_GP_CFG12 use SYSCTRL_DEBUG_REG6 + * P_AO_SEC_GP_CFG13 use SYSCTRL_DEBUG_REG7 + */ +#define PREG_STICKY_REG8 ((0x00b7 << 2) + 0xfe005800) +#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)((0x0096 << 2) + 0xfe005800) +#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)((0x0097 << 2) + 0xfe005800) + +/* + * P_AO_RTI_PINMUX_REG0 use PADCTRL_PIN_MUX_REG0 + * P_AO_TIMEBASE_CNTL1 use CLKTREE_TIMEBASE_CTRL1 + * AO_UART_WFIFO use UART_B_WFIFO + */ +#define P_AO_RTI_PINMUX_REG0 ((0x0000 << 2) + 0xfe000400) +#define P_AO_TIMEBASE_CNTL1 ((0x0016 << 2) + 0xfe000800) +#define AO_UART_WFIFO ((0x0000 << 2) + 0xfe002000) + +/* + * Not AO watch dog + */ +#define P_WATCHDOG_CNTL (volatile uint32_t *)(WATCHDOG_CNTL) +#define P_WATCHDOG_TCNT (volatile uint32_t *)(WATCHDOG_TCNT) +#define P_WATCHDOG_RST (volatile uint32_t *)(WATCHDOG_RST) +#define P_ISA_TIMERE (volatile uint32_t *)(ISA_TIMERE) + +#endif /* __AML_REG_H__ */
diff --git a/arch/arm/include/asm/arch-c1/soc_def.h b/arch/arm/include/asm/arch-c1/soc_def.h new file mode 100644 index 0000000..e927661 --- /dev/null +++ b/arch/arm/include/asm/arch-c1/soc_def.h
@@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __C1_DEF_H__ +#define __C1_DEF_H__ + +#define SEC_AO_SEC_GP_CFG2 (SYSCTRL_SEC_STATUS_REG6) + +#endif /* __C1_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-c1/timing.h b/arch/arm/include/asm/arch-c1/timing.h index 6d184f5..b335335 100644 --- a/arch/arm/include/asm/arch-c1/timing.h +++ b/arch/arm/include/asm/arch-c1/timing.h
@@ -360,7 +360,7 @@ //system reserve,do not modify /* align8 */ unsigned char char_rev1; - unsigned char char_rev2; + unsigned char training_offset;//char_rev2; unsigned int ddr_dmc_remap[5]; unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify
diff --git a/arch/arm/include/asm/arch-c1/usb.h b/arch/arm/include/asm/arch-c1/usb.h index c01594a..0efea92 100644 --- a/arch/arm/include/asm/arch-c1/usb.h +++ b/arch/arm/include/asm/arch-c1/usb.h
@@ -10,6 +10,8 @@ #include <asm/types.h> #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> +#include <generic-phy.h> +#include <asm-generic/gpio.h> #define USB_PHY_PORT_MAX 1 /* Phy register MACRO definitions */ @@ -74,6 +76,23 @@ /* XHCI PHY register structure */ #define PHY_REGISTER_SIZE 0x20 + +struct phy_aml_usb2_priv { + unsigned int base_addr; + unsigned int reset_addr; + unsigned int dwc2_a_addr; + unsigned int u2_port_num; + unsigned int usbphy_reset_bit[8]; + unsigned int clktree_usb_bus_ctrl_addr; + unsigned int usb_phy2_pll_base_addr[4]; +}; + +struct phy_aml_usb3_priv { + unsigned int base_addr; + unsigned int usb3_port_num; + struct gpio_desc desc; +}; + /* Register definitions */ typedef struct u2p_aml_regs { volatile uint32_t u2p_r0; @@ -216,5 +235,13 @@ #define USB_ID_MODE_HARDWARE (1) #define USB_ID_MODE_SW_HOST (2) #define USB_ID_MODE_SW_DEVICE (3) +int usb2_phy_tuning(uint32_t phy2_pll_base, int port); +void set_usb_pll(uint32_t phy2_pll_base); +int usb_save_phy_dev (unsigned int number, struct phy *phy); +int usb2_phy_init (struct phy *phy); +unsigned int usb_get_dwc_a_base_addr(void); +unsigned int usb_get_device_mode_phy_base(void); +void usb_phy_tuning_reset(void); +void usb_device_mode_init(void); #endif
diff --git a/arch/arm/include/asm/arch-c2/acs.h b/arch/arm/include/asm/arch-c2/acs.h new file mode 100644 index 0000000..65de6df --- /dev/null +++ b/arch/arm/include/asm/arch-c2/acs.h
@@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ACS_H +#define __ACS_H + +#ifndef __ASSEMBLY__ +typedef struct acs_setting{ + char acs_magic[5]; //acs setting magic word, make sure this piece of data was right. + unsigned char chip_type; //chip type + unsigned short version; //version of acs_setting struct, for PC tool use. + unsigned long acs_set_length; //length of current struct. + + //ddr setting part, 16 bytes + char ddr_magic[5]; //magic word to indicate that following 12 bytes was ddr setting. + unsigned char ddr_set_version; //struct version, for PC tool use. + unsigned short ddr_set_length; //length of ddr struct. + unsigned long ddr_set_addr; //address of ddr setting. + + char ddr_reg_magic[5]; + unsigned char ddr_reg_version; + unsigned short ddr_reg_length; + unsigned long ddr_reg_addr; + + char pll_magic[5]; + unsigned char pll_set_version; + unsigned short pll_set_length; + unsigned long pll_set_addr; + + char sto_magic[5]; + unsigned char sto_set_version; + unsigned short sto_set_length; + unsigned long sto_set_addr; + + char bl2_regs_magic[5]; + unsigned char bl2_regs_version; + unsigned short bl2_regs_length; + unsigned long bl2_regs_addr; + + char rsv_magic[5]; + unsigned char rsv_set_version; + unsigned short rsv_set_length; + unsigned long rsv_set_addr; + char board_id[12]; + unsigned short ddr_struct_size[12]; + unsigned long ddr_struct_org_size; + char revision[40]; +}__attribute__ ((packed)) acs_set_t; + +#endif +#endif
diff --git a/arch/arm/include/asm/arch-c2/bl31_apis.h b/arch/arm/include/asm/arch-c2/bl31_apis.h new file mode 100644 index 0000000..4fe2eec --- /dev/null +++ b/arch/arm/include/asm/arch-c2/bl31_apis.h
@@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* + * Trustzone API + * + * Copyright (C) 2012 Amlogic, Inc. + * + * Author: Platform-SH@amlogic.com + * + */ + +#ifndef __GXBB_BL31_APIS_H +#define __GXBB_BL31_APIS_H + +#include <asm/arch/io.h> + +/*#define SRAM_READ 0x82000010 +#define CORE_RD_REV1 0x82000011 +#define SRAM_ACS_READ 0x82000012 +#define SRAM_ACS_INDIRECT_READ 0x82000013*/ + +#define GET_SHARE_MEM_INPUT_BASE 0x82000020 +#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021 +#define GET_REBOOT_REASON 0x82000022 +#define GET_SHARE_STORAGE_IN_BASE 0x82000023 +#define GET_SHARE_STORAGE_OUT_BASE 0x82000024 +#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025 +#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026 +#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027 +#define SET_STORAGE_INFO 0x82000028 +#define SET_REBOOT_REASON 0x82000049 +#define GET_DVFS_TABLE_INDEX 0x82000088 + +/* Set Reboot Reason then Reboot*/ +#define PSCI_SYS_REBOOT 0x84000009 + +/* SECUREOS DEFINITION*/ +/* SMC Identifiers for non-secure world functions */ +#define CALL_TRUSTZONE_HAL_API 0x5 + +/* EFUSE */ +#define EFUSE_READ 0x82000030 +#define EFUSE_WRITE 0x82000031 +#define EFUSE_WRITE_PATTERN 0x82000032 +#define EFUSE_USER_MAX 0x82000033 + +#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0 +#define DEBUG_EFUSE_READ_PATTERN 0x820000F1 + +/* JTAG*/ +#define JTAG_ON 0x82000040 +#define JTAG_OFF 0x82000041 + +#define SET_USB_BOOT_FUNC 0x82000043 + /* USB BOOT FUNC sub command list*/ + #define CLEAR_USB_BOOT 1 + #define FORCE_USB_BOOT 2 + #define RUN_COMD_USB_BOOT 3 + #define PANIC_DUMP_USB_BOOT 4 + +#define GET_CHIP_ID 0x82000044 + +/* tsensor calibration data */ +#define TSENSOR_CALI_SET 0x8200004C + +/*oscring efuse value get */ +#define OSCRING_EFUSE_GET 0x8200004D +/* Security Key*/ +#define SECURITY_KEY_QUERY 0x82000060 +#define SECURITY_KEY_READ 0x82000061 +#define SECURITY_KEY_WRITE 0x82000062 +#define SECURITY_KEY_TELL 0x82000063 +#define SECURITY_KEY_VERIFY 0x82000064 +#define SECURITY_KEY_STATUS 0x82000065 +#define SECURITY_KEY_NOTIFY 0x82000066 +#define SECURITY_KEY_LIST 0x82000067 +#define SECURITY_KEY_REMOVE 0x82000068 +#define SECURITY_KEY_NOTIFY_EX 0x82000069 +#define SECURITY_KEY_SET_ENCTYPE 0x8200006A +#define SECURITY_KEY_GET_ENCTYPE 0x8200006B +#define SECURITY_KEY_VERSION 0x8200006C + +/*viu probe en*/ +#define VIU_PREOBE_EN 0x82000080 +/*set boot first timeout*/ +#define SET_BOOT_FIRST 0x82000087 + +/* Secure HAL APIs */ +#define TRUSTZONE_HAL_API_SRAM 0x400 + +/*start hifi4 */ +#define START_HIFI4 0x82000090 +#define DSP_SEC_POWERSET 0x82000092 +#define POWER_CTRL 0x82000093 +#define POWER_CTRL_IRQ_SET 0x82000094 +#define POWER_STATUS 0x82000095 + +#define SRAM_HAL_API_CHECK_EFUSE 0x403 +struct sram_hal_api_arg { + unsigned int cmd; + unsigned int req_len; + unsigned int res_len; + unsigned long req_phy_addr; + unsigned long res_phy_addr; + unsigned long ret_phy_addr; +}; + +#define JTAG_STATE_ON 0 +#define JTAG_STATE_OFF 1 +#define JTAG_M3_AO 0 +#define JTAG_M3_EE 1 +#define JTAG_A53_AO 2 +#define JTAG_A53_EE 3 +#define CLUSTER_BIT 2 + + +///////////////////////////////////////////////////////////////////////////////// +#define AML_DATA_PROCESS (0x820000FF) + #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10) + #define AML_D_P_W_EFUSE_PASSWORD (0x11) + #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12) + #define AML_D_P_W_EFUSE_AMLOGIC (0x20) + #define AML_D_P_IMG_DECRYPT (0x40) + #define AML_D_P_IMG_DECRYPT_V3 (0x41) + #define AML_D_P_EXT_IMG_DECRYPT_V3 (0x51) + #define AML_D_P_UPGRADE_CHECK (0x80) + #define AML_D_Q_IMG_SIG_HDR_SIZE (0x100) + #define AML_D_P_MRK_CHECK (0x200) + +#define GXB_EFUSE_PATTERN_SIZE (0x500) +#define GXB_IMG_SIZE (24<<20) +#define GXB_IMG_LOAD_ADDR (0x1080000) + #define GXB_IMG_DEC_KNL (1<<0) + #define GXB_IMG_DEC_RMD (1<<1) + #define GXB_IMG_DEC_DTB (1<<2) + #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB) + +#define PDID_ACODEC 14 +#define PDID_AUDIO 15 +#define PDID_PDM 26 + +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +void aml_set_jtag_state(unsigned state, unsigned select); +unsigned aml_get_reboot_reason(void); +unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); +void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); +unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long ); +long get_sharemem_info(unsigned long); +void set_usb_boot_function(unsigned long command); +void aml_system_off(void); + +void bl31_get_chipid(unsigned int *, unsigned int *, + unsigned int *, unsigned int *); +void set_viu_probe_enable(void); +void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value); +void power_set_dsp(unsigned int id, unsigned int powerflag); +void power_set_ctl(unsigned int id, unsigned int powerflag); +void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0); +void set_boot_first_timeout(uint64_t arg0); +int bl31_get_cornerinfo(uint8_t *outbuf, int size); +unsigned aml_get_dvfs_id(void); +void __attribute__((weak))aml_set_bootsequence(uint32_t val) +{ + return 0; +} +#endif
diff --git a/arch/arm/include/asm/arch-c2/board_id.h b/arch/arm/include/asm/arch-c2/board_id.h new file mode 100644 index 0000000..6488771 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/board_id.h
@@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +unsigned int get_board_id(void); \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c2/clk_measure.h b/arch/arm/include/asm/arch-c2/clk_measure.h new file mode 100644 index 0000000..46edac4 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/clk_measure.h
@@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _ARCH_MESON_C2_MEASURE_H_ +#define _ARCH_MESON_A1_MEASURE_H_ + +static const char* clk_msr_table[] = { + [0] = "tdmout_b_sclk", + [1] = "tdmout_a_sclk", + [2] = "tdmin_lb_sclk", + [3] = "tdmin_b_sclk", + [4] = "tdmin_a_sclk", + [5] = "vad_clk", + [6] = "resampleA_clk", + [7] = "pdm_sysclk", + [8] = "pdm_dclk", + [9] = "locker_out_clk", + [10] = "locker_in_clk", + [12] = "tdmin_vad_clk", + [13] = "au_adc_clk", + [14] = "au_dac_clk", + [15] = "resampleb_clk", + [16] = "spicc_a_clk", + [17] = "spifc_clk", + [18] = "sd_emmc_a_clk", + [19] = "spicc_b_clk", + [20] = "axi_clk_frcpu", + [21] = "deskew_pll_clk", + [24] = "ts_clk", + [25] = "pwm_f_clk", + [26] = "pwm_e_clk", + [27] = "pwm_d_clk", + [28] = "pwm_c_clk", + [29] = "pwm_b_clk", + [30] = "pwm_a_clk", + [31] = "saradc_clk", + [32] = "usb_bus", + [34] = "dsp_a_clk", + [35] = "axi_clk_nic", + [36] = "sys_clk_nic", + [37] = "gp_pll_ckout2", + [38] = "gp_pll_ckout1", + [39] = "gpio_msr", + [40] = "rng_ring_osc0", + [41] = "rng_ring_osc1", + [42] = "rng_ring_osc2", + [43] = "rng_ring_osc3", + [45] = "sys_cpu_clk_div16", + + [64] = "usb_pll_out", + [65] = "sar_adc_clk", + [66] = "mod_crt_clk25", + [67] = "mod_crt_clk12_24", + [68] = "cts_mipi_isp_clk", + [69] = "cts_mipi_csi_phy_clk", + [70] = "cts_nna_axi_clk", + [71] = "cts_nna_core_clk", + [73] = "cts_secpu_clk", + [74] = "cts_jpeg_enc_clk ", + [75] = "cts_rtc_clk", + [76] = "cts_ge2d_clk", + [77] = "cts_gdc_axi_clk", + [78] = "cts_gdc_core_clk", + [79] = "cts_pwm_j_clk", + [80] = "cts_pwm_i_clk", + [81] = "cts_pwm_h_clk", + [82] = "cts_pwm_g_clk", + [83] = "cts_wave_cclk", + [84] = "cts_wave_bclk", + [85] = "cts_wave_aclk", + [86] = "cts_sd_emmc_C_clk", + [87] = "cts_sd_emmc_B_clk", + [89] = "mipi_csi_phy0_clk", + [90] = "mipi_csi_phy1_clk", + [91] = "mod_eth_phy_ref_clk", + [92] = "ddr_dpll_pt_clk", + [93] = "osc_ring_cpu0", + [94] = "osc_ring_cpu0", + [95] = "osc_ring_cpu0", +}; + +int clk_msr(int index); + +#endif
diff --git a/arch/arm/include/asm/arch-c2/clock.h b/arch/arm/include/asm/arch-c2/clock.h new file mode 100644 index 0000000..e361e1f --- /dev/null +++ b/arch/arm/include/asm/arch-c2/clock.h
@@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __C2_H +#define __C2_H + +/* + * Clock controller register address + * APB_BASE: APB0_BASE_ADDR = 0xfe000800 + */ +#define C2_SYS_OSCIN_CTRL 0x0 +#define C2_RTC_BY_OSCIN_CTRL0 0x4 +#define C2_RTC_BY_OSCIN_CTRL1 0x8 +#define C2_RTC_CTRL 0xc +#define C2_SYS_CLK_CTRL0 0x10 +#define C2_AXI_CLK_CTRL0 0x14 +#define C2_SYS_CLK_EN0 0x18 +#define C2_SYS_CLK_EN1 0x1c +#define C2_SYS_CLK_EN2 0x20 +#define C2_AXI_CLK_EN 0x24 +#define C2_DSPA_CLK_EN 0x28 +#define C2_DSPB_CLK_EN 0x2c +#define C2_DSPA_CLK_CTRL0 0x30 +#define C2_DSPB_CLK_CTRL0 0x34 +#define C2_CLK12_24_CTRL 0x38 +#define C2_GEN_CLK_CTRL 0x3c +#define C2_TIMESTAMP_CTRL0 0x40 +#define C2_TIMESTAMP_CTRL1 0x44 +#define C2_TIMESTAMP_CTRL2 0x48 +#define C2_TIMESTAMP_VAL0 0x4c +#define C2_TIMESTAMP_VAL1 0x50 +#define C2_TIMEBASE_CTRL0 0x54 +#define C2_TIMEBASE_CTRL1 0x58 +#define C2_SAR_ADC_CLK_CTRL 0xc0 +#define C2_PWM_CLK_AB_CTRL 0xc4 +#define C2_PWM_CLK_CD_CTRL 0xc8 +#define C2_PWM_CLK_EF_CTRL 0xcc +#define C2_SPICC_CLK_CTRL 0xd0 +#define C2_TS_CLK_CTRL 0xd4 +#define C2_SPIFC_CLK_CTRL 0xd8 +#define C2_USB_BUSCLK_CTRL 0xdc +#define C2_SD_EMMC_CLK_CTRL 0xe0 +#define C2_CECA_CLK_CTRL0 0xe4 +#define C2_CECA_CLK_CTRL1 0xe8 +#define C2_CECB_CLK_CTRL0 0xec +#define C2_CECB_CLK_CTRL1 0xf0 +#define C2_PSRAM_CLK_CTRL 0xf4 +#define C2_DMC_CLK_CTRL 0xf8 +#define C2_FCLK_DIV1_SEL 0xfc +#define C2_TST_CTRL 0x100 +#define C2_WAVE_CLK_CTRL0 0x104 +#define C2_WAVE_CLK_CTRL1 0x108 +#define C2_JPEG_CLK_CTRL 0x10C +#define C2_MIPI_ISP_CLK_CTRL 0x110 +#define C2_NNA_CLK_CTRL 0x114 +#define C2_GDC_CLK_CTRL 0x118 +#define C2_GE2D_CLK_CTRL 0x11C +#define C2_SD_EMMC_CLK_CTRL1 0x120 +#define C2_ETH_CLK_CTRL 0x124 +#define C2_PWM_CLK_GH_CTRL 0x128 +#define C2_PWM_CLK_IJ_CTRL 0x12C +#define C2_MBIST_ATSPEED_CTRL 0x130 + +/* + * For PLl register offset + * APB_BASE: APB0_BASE_ADDR = 0xfe007c00 + */ +#define C2_ANACTRL_FIXPLL_GATE_DIS 0x40 + 0x7400 +#define C2_ANACTRL_FIXPLL_CTRL0 0x80 + 0x7400 +#define C2_ANACTRL_FIXPLL_CTRL1 0x84 + 0x7400 +#define C2_ANACTRL_FIXPLL_CTRL2 0x88 + 0x7400 +#define C2_ANACTRL_FIXPLL_CTRL3 0x8c + 0x7400 +#define C2_ANACTRL_FIXPLL_CTRL4 0x90 + 0x7400 +#define C2_ANACTRL_FIXPLL_CTRL5 0x94 + 0x7400 +#define C2_ANACTRL_FIXPLL_CTRL6 0x98 + 0x7400 +#define C2_ANACTRL_FIXPLL_STS 0x9c + 0x7400 +#define C2_ANACTRL_GPPLL_CTRL0 0xc0 + 0x7400 +#define C2_ANACTRL_GPPLL_CTRL1 0xc4 + 0x7400 +#define C2_ANACTRL_GPPLL_CTRL2 0xc8 + 0x7400 +#define C2_ANACTRL_GPPLL_CTRL3 0xcc + 0x7400 +#define C2_ANACTRL_GPPLL_CTRL4 0xd0 + 0x7400 +#define C2_ANACTRL_GPPLL_CTRL5 0xd4 + 0x7400 +#define C2_ANACTRL_GPPLL_STS 0xd8 + 0x7400 +#define C2_ANACTRL_GPPLL_CTRL6 0xdc + 0x7400 +#define C2_ANACTRL_SYSPLL_CTRL0 0x100 + 0x7400 +#define C2_ANACTRL_SYSPLL_CTRL1 0x104 + 0x7400 +#define C2_ANACTRL_SYSPLL_CTRL2 0x108 + 0x7400 +#define C2_ANACTRL_SYSPLL_CTRL3 0x10c + 0x7400 +#define C2_ANACTRL_SYSPLL_CTRL4 0x110 + 0x7400 +#define C2_ANACTRL_SYSPLL_STS 0x114 + 0x7400 +#define C2_ANACTRL_HIFIPLL_CTRL0 0x140 + 0x7400 +#define C2_ANACTRL_HIFIPLL_CTRL1 0x144 + 0x7400 +#define C2_ANACTRL_HIFIPLL_CTRL2 0x148 + 0x7400 +#define C2_ANACTRL_HIFIPLL_CTRL3 0x14c + 0x7400 +#define C2_ANACTRL_HIFIPLL_CTRL4 0x150 + 0x7400 +#define C2_ANACTRL_HIFIPLL_STS 0x154 + 0x7400 +//#define C1_ANACTRL_AUDDDS_CTRL0 0x180 + 0x7400 +//#define C1_ANACTRL_AUDDDS_CTRL1 0x184 + 0x7400 +//#define C1_ANACTRL_AUDDDS_CTRL2 0x188 + 0x7400 +//#define C1_ANACTRL_AUDDDS_CTRL3 0x18c + 0x7400 +//#define C1_ANACTRL_AUDDDS_CTRL4 0x190 + 0x7400 +//#define C1_ANACTRL_AUDDDS_STS 0x194 + 0x7400 +#define C2_ANACTRL_MISCTOP_CTRL0 0x1c0 + 0x7400 +#define C2_ANACTRL_POR_CNTL 0x208 + 0x7400 + +/* + * CPU clok register offset + * APB_BASE: APB1_BASE_ADDR = 0xfe007400 + */ +/* + *#define C1_CPUCTRL_CLK_CTRL0 0x0 + 0x7400 + *#define C1_CPUCTRL_CLK_CTRL1 0x4 + 0x7400 + *#define C1_CPUCTRL_CLK_CTRL5 0x14 + 0x7400 + *#define C1_CPUCTRL_CLK_CTRL6 0x18 + 0x7400 + */ + +#include <dt-bindings/clock/c2-clkc.h> +#define NR_CLKS (CLKID_END_BASE) + +#endif /* __C1_H */
diff --git a/arch/arm/include/asm/arch-c2/core.h b/arch/arm/include/asm/arch-c2/core.h new file mode 100644 index 0000000..97fd220 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/core.h
@@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CORE_H__ +#define __CORE_H__ + +int get_core_mpidr(unsigned int cpuid); +int get_core_idx(unsigned int mpidr); +int get_core_max(void); + +#endif
diff --git a/arch/arm/include/asm/arch-c2/cpu.h b/arch/arm/include/asm/arch-c2/cpu.h new file mode 100644 index 0000000..be63bd3 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/cpu.h
@@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _CPU_H +#define _CPU_H +/* #include <config.h> */ +/* #include <asm/plat-cpu.h> */ +/* #include <asm/arch/ddr.h> */ + +#if 0 +#define CONFIG_AML_MESON 1 +#define CONFIG_AML_MESON_GX 1 +#define CONFIG_AML_MESON_G12A 1 +#endif + +/*enable viu probe*/ +#if 0 +#define CONFIG_CMD_VIU_PROBE 1 +#endif + +/* for uboot envrionment use */ +#define CONFIG_DDR_SIZE 256 + +/* dram */ +#define PHYS_SDRAM_1_BASE 0x00000000UL +#define PHYS_SDRAM_1_SIZE 0x10000000UL +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE + +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE) + +/* console/print buffer */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +/* use "hush" command parser */ +#if 0 +#define CONFIG_SYS_HUSH_PARSER +#endif + +#if 0 +#define CONFIG_DTB_MEM_ADDR 0x1000000 +#endif + +#if 0 +#define CONFIG_AML_CUSTOMER_ID (0) +#endif + +#define AML_CUSTOMER_ID (0) + +//#define CONFIG_SILENT_CONSOLE +//#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC +//#define CONFIG_SILENT_U_BOOT_ONLY + +/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */ +#define CONFIG_AML_BL33_COMPRESS_ENABLE 1 + +/* 2018.03.19 G12A only support v3 format for normal & secure boot */ +#define CONFIG_AML_SECURE_BOOT_V3 1 + +#define NR_CPUS 4 + +#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0 +#define PACKAGE_ID_MASK 0xFF + +/*C2 SoC secure boot solution default not support AES algorithm*/ +#define CONFIG_AML_CRYPTO_AES 1 + + +/*Flag for enable AES key generate to EFUSE pattern, with this flag only +AES key will be generated to EFUSE pattern, it can be used for use case +like the AES key not ready when secure boot enabled for the first time. +*/ +//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1 + +#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-c2/cpu_config.h b/arch/arm/include/asm/arch-c2/cpu_config.h new file mode 100644 index 0000000..45e7e80 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/cpu_config.h
@@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _BOOT_ROM_CONFIG_H_ +#define _BOOT_ROM_CONFIG_H_ + +/*********************************************************** + * The following constants are GXBB definition + **********************************************************/ +#define ROMBOOT_START 0xD9040000 +#define ROM_SIZE (64*1024) +#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE) + +/*********************************************************** + * AHB-SRAM Total Size 80KB, layout shown as below + * + * ROMCODE use the top 32KB + * + * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved + * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry + * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info + * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror + * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) + * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * + * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * + * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS + * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer + * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved + * + **********************************************************/ +#define RAM_START 0xD9000000 +#define RAM_SIZE (80 * 1024) +#define BL1_RAM_START (RAM_START + 0xC000) +#define BL1_RAM_SIZE (32 * 1024) +#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE) +#define BSS_START (BL1_RAM_START + (2 * 1024)) +#define BSS_SIZE (18 * 1024) +#define _STACK_END (BSS_START + BSS_SIZE + 8*1024) +#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024) +#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR) +#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512) +#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256) +#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER) +#define BL1_SEC_MBX (BL1_RAM_END - 2*1024) +#define BL1_NAND_BUFF (BL1_RAM_START + 1024) +#define BL1_USB_BUFF (BL1_NAND_BUFF) + +#define MEMORY_LOC RAM_START + +#define SRAM_DEBUG_BUFF_SIZE 256 + +/* BL2 SPL size */ +#define BL2_SIZE (64 * 1024) + +//for signature test +//#define CONFIG_AML_SIG_TEST_BUILD + +/* Software SHA2 */ +#define CONFIG_SHA2_SW + +/* Hardware SHA2 */ +#define CONFIG_SHA2_HW +#define SHA2_HW_UPDATE_API + +/* Keep timer config in conf.h */ +#define CONFIG_TIMER + +/* Bootrom debug info */ +#define CONFIG_DEBUG_INFO + +/* Mincrypt RSA library */ +//#define CONFIG_MINCRYPT + +/* PolarSSL RSA library */ +#define CONFIG_POLARSSL_RSA + +#ifdef CONFIG_POLARSSL_RSA +#ifndef CONFIG_MALLOC +#define CONFIG_MALLOC +#endif /* ! CONFIG_MALLOC */ +#endif /* CONFIG_POLARSSL_RSA */ + +#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-c2/cpu_reset.h b/arch/arm/include/asm/arch-c2/cpu_reset.h new file mode 100644 index 0000000..46f9abf --- /dev/null +++ b/arch/arm/include/asm/arch-c2/cpu_reset.h
@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _BOOT_ROM_WATCHDOG_H +#define _BOOT_ROM_WATCHDOG_H +#include <asm/arch/secure_apb.h> + +void reset_system(void); + +/* uboot reset interface */ +void reset_cpu(unsigned long flag); + +#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-c2/cpu_sdio.h b/arch/arm/include/asm/arch-c2/cpu_sdio.h new file mode 100644 index 0000000..46f366a --- /dev/null +++ b/arch/arm/include/asm/arch-c2/cpu_sdio.h
@@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CPU_SDIO_H__ +#define __CPU_SDIO_H__ + +#define SD_EMMC_BASE_A 0xFFE03000 +#define SD_EMMC_BASE_B 0xFFE05000 +#define SD_EMMC_BASE_C 0xFFE07000 + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +struct sd_emmc_global_regs { + volatile uint32_t gclock; // 0x00 + volatile uint32_t gdelay; // 0x04 + volatile uint32_t gdelay1; //0x08 + volatile uint32_t gadjust; // 0x0c + volatile uint32_t gcalout; // 0x10 + volatile uint32_t reserved_14[11]; // 0x14~0x3c + volatile uint32_t gstart; // 0x40 + volatile uint32_t gcfg; // 0x44 + volatile uint32_t gstatus; // 0x48 + volatile uint32_t girq_en; // 0x4c + volatile uint32_t gcmd_cfg; // 0x50 + volatile uint32_t gcmd_arg; // 0x54 + volatile uint32_t gcmd_dat; // 0x58 + volatile uint32_t gcmd_rsp0; // 0x5c + volatile uint32_t gcmd_rsp1; // 0x60 + volatile uint32_t gcmd_rsp2; // 0x64 + volatile uint32_t gcmd_rsp3; // 0x68 + volatile uint32_t reserved_6c; // 0x6c + volatile uint32_t gcurr_cfg; // 0x70 + volatile uint32_t gcurr_arg; // 0x74 + volatile uint32_t gcurr_dat; // 0x78 + volatile uint32_t gcurr_rsp; // 0x7c + volatile uint32_t gnext_cfg; // 0x80 + volatile uint32_t gnext_arg; // 0x84 + volatile uint32_t gnext_dat; // 0x88 + volatile uint32_t gnext_rsp; // 0x8c + volatile uint32_t grxd; // 0x90 + volatile uint32_t gtxd; // 0x94 + volatile uint32_t reserved_98[90]; // 0x98~0x1fc + volatile uint32_t gdesc[128]; // 0x200 + volatile uint32_t gping[128]; // 0x400 + volatile uint32_t gpong[128]; // 0x800 +}; + +union sd_emmc_setup { + uint32_t d32; + struct { + unsigned bw:3; + unsigned fast:1; + unsigned par:3; + unsigned hcs:1; + unsigned sd:1; + unsigned sdhc:1; + unsigned type:6; + unsigned rca:16; + } b; +}; + +struct sd_emmc_desc_info{ + uint32_t cmd_info; + uint32_t cmd_arg; + uint32_t data_addr; + uint32_t resp_addr; +}; + +struct cmd_cfg{ + uint32_t length:9; + uint32_t block_mode:1; + uint32_t r1b:1; + uint32_t end_of_chain:1; + uint32_t timeout:4; + uint32_t no_resp:1; + uint32_t no_cmd:1; + uint32_t data_io:1; + uint32_t data_wr:1; + uint32_t resp_nocrc:1; + uint32_t resp_128:1; + uint32_t resp_num:1; + uint32_t data_num:1; + uint32_t cmd_index:6; + uint32_t error:1; + uint32_t owner:1; +}; + +struct sd_emmc_status{ + uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/ + uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */ + uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/ + uint32_t resp_err:1; /*[10] Response CRC error.*/ + uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/ + uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/ + /* Consider the multiple block read/write, set the proper timeout limits.*/ + uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */ + uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/ + uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */ + uint32_t dat_i:8; /*[23:16] Input data signals. */ + uint32_t cmd_i:1; /*[24] nput response signal. */ + uint32_t ds:1; /*[25] Input data strobe. */ + uint32_t bus_fsm:4; /*[29:26] BUS fsm */ + uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/ + uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_clock{ + uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */ + /*Clock off: cfg_div==0, the clock is disabled */ + /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */ + uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/ + /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */ + uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t reserved14:2; + uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ + uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ + uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */ + /*Any APB3 access or descriptor execution will keep clock on.*/ + uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */ + uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/ + uint32_t reserved26:1; +}; + +struct sd_emmc_delay{ + uint32_t dat0:6; /*[3:0] Data 0 delay line. */ + uint32_t dat1:6; /*[7:4] Data 1 delay line. */ + uint32_t dat2:6; /*[11:8] Data 2 delay line. */ + uint32_t dat3:6; /*[15:12] Data 3 delay line. */ + uint32_t dat4:6; /*[19:16] Data 4 delay line. */ + uint32_t spare:2; +}; + +struct sd_emmc_delay1{ + uint32_t dat5:6; /*[23:20] Data 5 delay line. */ + uint32_t dat6:6; /*[27:24] Data 6 delay line. */ + uint32_t dat7:6; /*[31:28] Data 7 delay line. */ + uint32_t dat8:6; /*[31:28] Data 7 delay line. */ + uint32_t dat9:6; /*[31:28] Data 7 delay line. */ + uint32_t spare:2; +}; + +struct sd_emmc_adjust{ + uint32_t cmd_delay:4; /*[3:0] Command delay line. */ + uint32_t ds_delay:4; /*[7:4] DS delay line. */ + uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/ + /*Signals are labeled from 0 to 9 the same as delay lines. */ + uint32_t cali_enable:1; /*[12] Enable calibration. */ + uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */ + uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */ + uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/ + uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */ + uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */ + /*set cali_enable to 1 to use this function*/ + uint32_t reserved23:9; +}; + + +struct sd_emmc_calout{ + uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */ + uint32_t reserved6:1; + uint32_t cali_vld:1; /*[7] The reading is valid. */ + uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */ + uint32_t reserved16:16; +}; + + +struct sd_emmc_start{ + uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */ + /* 0: Read descriptor from external DDR */ + uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */ + uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */ + /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */ + /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_config{ + uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/ + uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */ + uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */ + uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */ + uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */ + uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */ + uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */ + uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/ + uint32_t spare:1; /*[18] Spare, ??? need check*/ + uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/ + uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/ + uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/ + uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/ + /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/ + /*DDR slow response, stop clock is used in voltage switch.*/ + uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/ + /* 0: core clock is always on.*/ + uint32_t txd_add_err:1; /*[24] TXD add error test*/ + /*Test feature, should not be used in normal condition.*/ + /*It will inverted the first CRC bits of the 3rd block.*/ + /*Block index starts from 0, 1, 2, ¡*/ + uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/ + /*The total number of retries of one descriptor is limited to 15, */ + /*after 15 retries, the TXD_err is set to high.*/ + uint32_t revd:8; /*[31:26] reved*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_irq_en{ + uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/ + uint32_t txd_err:1; /*[8] TX data CRC error. */ + uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */ + uint32_t resp_err:1; /*[10] Response CRC error.*/ + uint32_t resp_timeout:1; /*[11] No response received before time limit. */ + uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */ + uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */ + uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */ + uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */ + uint32_t revd:16; /*[31:16] reved*/ +}; + +struct sd_emmc_data_info{ + uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/ + uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/ + uint32_t revd:30; /*[31:17] Reved. */ +}; + + +struct sd_emmc_card_info{ + uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */ + uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/ + uint32_t revd:30; /*[31:17] Reved. */ +}; + +#endif
diff --git a/arch/arm/include/asm/arch-c2/ddr.h b/arch/arm/include/asm/arch-c2/ddr.h new file mode 100644 index 0000000..ad27855 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/ddr.h
@@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <io.h> +#include <stdint.h> +#include <asm/arch/ddr_define.h> + +/* io defines */ +//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data) +//#define rd_reg(addr) (*((volatile uint32_t *)(addr))) +#define wr_reg(addr, data) writel(data, addr) +#define rd_reg(addr) readl(addr) +/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/ +#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value))) +#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc))); +#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc))); +#define wait_equal(addr, data) do{}while(data != (rd_reg(addr))); + +/* function defines */ +unsigned int ddr_init(void); +unsigned int ddr_init_pll(void); +unsigned int ddr_init_dmc(void); +unsigned int ddr_init_pctl(void); +unsigned int hot_boot(void); +void ddr_print_info(void); +void ddr_test(void); +void ddr_pre_init(void); +void ddr_debug(void); + +/* pctl status */ +#define UPCTL_STAT_MASK (7) +#define UPCTL_STAT_INIT (0) +#define UPCTL_STAT_CONFIG (1) +#define UPCTL_STAT_ACCESS (3) +#define UPCTL_STAT_LOW_POWER (5) + +/* pctl cmds */ +#define UPCTL_CMD_INIT (0) +#define UPCTL_CMD_CONFIG (1) +#define UPCTL_CMD_GO (2) +#define UPCTL_CMD_SLEEP (3) +#define UPCTL_CMD_WAKEUP (4) + +/* PUB PIR setting */ +#define PUB_PIR_INIT (1<<0) +#define PUB_PIR_ZCAL (1<<1) +#define PUB_PIR_CA (1<<2) +#define PUB_PIR_PLLINIT (1<<4) +#define PUB_PIR_DCAL (1<<5) +#define PUB_PIR_PHYRST (1<<6) +#define PUB_PIR_DRAMRST (1<<7) +#define PUB_PIR_DRAMINIT (1<<8) +#define PUB_PIR_WL (1<<9) +#define PUB_PIR_QSGATE (1<<10) +#define PUB_PIR_WLADJ (1<<11) +#define PUB_PIR_RDDSKW (1<<12) +#define PUB_PIR_WRDSKW (1<<13) +#define PUB_PIR_RDEYE (1<<14) +#define PUB_PIR_WREYE (1<<15) +#define PUB_PIR_ICPC (1<<16) +#define PUB_PIR_PLLBYP (1<<17) +#define PUB_PIR_CTLDINIT (1<<18) +#define PUB_PIR_RDIMMINIT (1<<19) +#define PUB_PIR_CLRSR (1<<27) +#define PUB_PIR_LOCKBYP (1<<28) +#define PUB_PIR_DCALBYP (1<<29) +#define PUB_PIR_ZCALBYP (1<<30) +#define PUB_PIR_INITBYP (1<<31) + +/* PHY initialize register (PIR) */ +#define DDR_PIR ((PUB_PIR_ZCAL) |\ + (PUB_PIR_PLLINIT) |\ + (PUB_PIR_DCAL) |\ + (PUB_PIR_PHYRST) |\ + (PUB_PIR_DRAMRST) |\ + (PUB_PIR_DRAMINIT) |\ + (PUB_PIR_WL) |\ + (PUB_PIR_QSGATE) |\ + (PUB_PIR_WLADJ) |\ + (PUB_PIR_RDDSKW) |\ + (PUB_PIR_WRDSKW) |\ + (PUB_PIR_RDEYE) |\ + (PUB_PIR_WREYE) \ + ) + +/* PHY general status register (PGSR0) */ +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) +#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \ + (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff)) +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2) +#define DDR_PGSR0_CHECK() +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +#define DDR_PGSR0_CHECK() +#endif + +/* other regs */ +#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-c2/ddr_define.h b/arch/arm/include/asm/arch-c2/ddr_define.h new file mode 100644 index 0000000..ce4a51d --- /dev/null +++ b/arch/arm/include/asm/arch-c2/ddr_define.h
@@ -0,0 +1,577 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* board id */ +#define CONFIG_BOARD_ID_MASK 0xFF +#define CONFIG_FW_INFO_MASK 0xFFFFFFFF + +#define RESULT_OK 0x0 +#define RESULT_FAIL 0xFF +#define RESULT_PLL_LOCK_FAIL 0x0F +#define RESULT_USB_BOOT_NEVER 0xF0 + +#define DDR_HDTCTRL_ENABLE_AMLOGIC_DDR4_PHY_VREF_CORRECTION 0x7 +#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN 0x9 +#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_WRITE_DQ 0x00210005 +#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_WRITE_DQM 0x00290005 +#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_READ_DQ 0x003a0005 + +#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_START_1 0x00200004 +#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_START_2 0x001e0004 +#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_VREF 0x0014001f +#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_VREF_END 0x00610000 + +#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_START_1 0x001c0004 +#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_START_2 0x00230004 +#define DDR_HDTCTRL_SHOW_LPDDR4_TRAINING_TDQS2DQ 0x00dd0002 +//#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_VREF 0x0014001f +//#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_VREF_END 0x00610000 +#define DMC_PSTATE_MAX 4 + +#define CONFIG_CHIP_TYPE_DRAM 0x1F +#define CONFIG_CHIP_TYPE_PSRAM 0x2F +#define CONFIG_DDR_TYPE_DDR3 0 +#define CONFIG_DDR_TYPE_DDR4 1 +#define CONFIG_DDR_TYPE_LPDDR4 2 +#define CONFIG_DDR_TYPE_LPDDR3 3 +#define CONFIG_DDR_TYPE_LPDDR2 4 +//#define CONFIG_DDR_TYPE_LPDDR4X 5 +#define CONFIG_DDR_TYPE_AUTO 0xf +#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4 + +/* lpddr3 related define */ +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3 + +#define LPDDR_DIE_ROW_COL_R13_C9 0 +#define LPDDR_DIE_ROW_COL_R14_C9 1 +#define LPDDR_DIE_ROW_COL_R14_C10 2 +#define LPDDR_DIE_ROW_COL_R13_C10 3 +#define LPDDR_DIE_ROW_COL_R14_C11 4 + +#if 0 +/* ddr channel defines */ +#define CONFIG_DDR0_16BIT 1 +#define CONFIG_DDR0_RANK0 2 +#define CONFIG_DDR0_RANK01 3 +#define CONFIG_DDR0_16BIT_2 4 +#define CONFIG_DDR_CHL_AUTO 0xF +#define CONFIG_DDR0_16BIT_CH0 0x1 +#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 +#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 +#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 +#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 +#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 +#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 +#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 +#define ENABLE_SKIP_1D_MEM_LOAD 0x0 +#define ENABLE_SKIP_1D_MEM_TRAINING 0x1 +#define ENABLE_SKIP_2D_MEM_LOAD 0x2 +#define ENABLE_SKIP_2D_MEM_TRAINING 0x3 + +#define PHY_IMEM_STEP_1D 0x1 +#define PHY_IMEM_STEP_2D 0x2 + +#endif +#define VREF_SOC 0x1 +#define VREF_DRAM 0x2 + + +#define CFG_DDR_BASE_ADDR 0X0 +#define CFG_DDR_START_OFFSET 0X01000000 //SKIP 16MB + +/* ddr type identifier */ +#define CONFIG_DDR_TIMMING_LPDDR2 0x02 +#define CONFIG_DDR_TIMMING_LPDDR3 0x03 +#define CONFIG_DDR_TIMMING_DDR3_7 0x07 +#define CONFIG_DDR_TIMMING_DDR3_9 0x09 +#define CONFIG_DDR_TIMMING_DDR3_11 0x0B +#define CONFIG_DDR_TIMMING_DDR3_12 0x0C +#define CONFIG_DDR_TIMMING_DDR3_13 0x0D +#define CONFIG_DDR_TIMMING_DDR3_14 0x0E + +#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F +#define CONFIG_DDR_TIMMING_DDR4_1866 0x10 +#define CONFIG_DDR_TIMMING_DDR4_2133 0x11 +#define CONFIG_DDR_TIMMING_DDR4_2400 0x12 +#define CONFIG_DDR_TIMMING_DDR4_2666 0x13 +#define CONFIG_DDR_TIMMING_DDR4_3200 0x14 + +#define CONFIG_DDR_FUNC_TEST (1<<0) + +#define CONFIG_DDR_INIT_RETRY_TOTAL (10) +#define CONFIG_DDR_PCTL_RETRY_TOTAL (100) + +#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \ + (chl_set == CONFIG_DDR0_16BIT)) +#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01) || \ + (chl_set == CONFIG_DDR0_16BIT_2)) + +#ifndef CONFIG_LPDDR3_CA_TRAINING_CA0 +#define CONFIG_LPDDR3_CA_TRAINING_CA0 CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 +#endif +#ifndef CONFIG_LPDDR3_CA_TRAINING_CA1 +#define CONFIG_LPDDR3_CA_TRAINING_CA1 CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 +#endif + +/* DMC_DDR_CTRL defines */ +#define DDR_DDR4_ENABLE (1<<22) +#define DDR_RANK1_ENABLE (1<<21) +#define DDR_DDR4_BG_ENABLE (1<<20) +#define DDR_16BIT_ENABLE (1<<16) + +#define DDR_RANK1_SIZE_CTRL (3) +#define DDR_RANK0_SIZE_CTRL (0) + +/* ddr functions */ +#define DDR_FUNC_D2PLL (1<<0) +#define DDR_FUNC_LP (1<<1) +#define DDR_FUNC_ZQ_PD (1<<2) +#define DDR_FUNC_EXT_VREF (1<<3) +#define DDR_FUNC_DDR4_TIMING_TEST (1<<4) +#define DDR_FUNC_DDR_PLL_BYPASS (1<<5) +#define DDR_FUNC_RDBI (1<<6) +#define DDR_FUNC_LPDDR3_CA (1<<7) +#define DDR_FUNC_PRINT_WINDOW (1<<8) +#define DDR_FUNC_FULL_TEST (1<<10) +#define DDR_FUNC_NONSEC_SCRAMBLE (1<<11) +#define DDR_FUNC_LPDDR3_CA_CA0_BIT0 (1<<20) +#define DDR_FUNC_LPDDR3_CA_CA0_BIT1 (1<<21) +#define DDR_FUNC_LPDDR3_CA_CA1_BIT0 (1<<22) +#define DDR_FUNC_LPDDR3_CA_CA1_BIT1 (1<<23) +#define DDR_FUNC_LPDDR3_CA_CA0_OFFSET (20) +#define DDR_FUNC_LPDDR3_CA_CA1_OFFSET (22) +#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25) +#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28) +#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29) +#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) +#define DDR_FUNC_SCRAMBLE (1<<31) + + +/* dwc imem/dmem */ +#define DWC_MEM_LOAD_ADDR 0xFFFE0000 +#define DWC_IRAM_ADDR (0x50000) +#define DWC_IRAM_SIZE (0x8000) /* 32K */ +#define DWC_DRAM_ADDR (0x54000) +#define DWC_DRAM_SIZE (0x4000) /* 16K */ + +/* dwc apb regs */ +#define UctWriteProtShadow 0xd0004 +#define UctWriteOnlyShadow 0xd0032 +#define UctWriteProt 0xd0031 +#define UctDatWriteOnlyShadow 0xd0034 + +/* pctl status */ +#define UPCTL_STAT_MASK (7) +#define UPCTL_STAT_INIT (0) +#define UPCTL_STAT_CONFIG (1) +#define UPCTL_STAT_ACCESS (3) +#define UPCTL_STAT_LOW_POWER (5) + +/* pctl cmds */ +#define UPCTL_CMD_INIT (0) +#define UPCTL_CMD_CONFIG (1) +#define UPCTL_CMD_GO (2) +#define UPCTL_CMD_SLEEP (3) +#define UPCTL_CMD_WAKEUP (4) + + +/* name id defined in firmware header */ +#define DDR_NAME_ID_AML_FW 0x304c4d41 //AML0 +#define DDR_NAME_ID_PIEI 0x61656165 //eaea +#define DDR_NAME_ID_DDR3 0x33333364 //d333 +#define DDR_NAME_ID_DDR4 0x34343464 //d444 +#define DDR_NAME_ID_DDR4_2D 0x32323464 //d422 +#define DDR_NAME_ID_LPDDR3 0x33336C64 //dl33 +#define DDR_NAME_ID_LPDDR4 0x34346C64 //dl44 +#define DDR_NAME_ID_LPDDR4_2D 0x30346C64 //dl42 +#define DDR_NAME_ID_DIAGNOSE1 0x31676464 //ddg1 +#define DDR_NAME_ID_DIAGNOSE2 0x32676464 //ddg2 +/* PIEI */ +#define DDR_PIEI_START_FLAG 0xfeed //eaea + +/* dram cfg magic */ +#define DRAM_CFG_MAGIC 0x2e676663 + +/* flow control */ +#define DDR_FIRMWARE_VERSION_1 0x00201709 +#define FW_LOAD_STEP_AML_FW 0xF +#define FW_LOAD_STEP_PIEI 0 +#define FW_LOAD_STEP_1D 1 +#define FW_LOAD_STEP_2D 2 +#define FW_LOAD_STEP_DIAG1 3 +#define FW_LOAD_STEP_DIAG2 4 + +/* basic defines */ +#define AML_AC_PINMUX_G0_TOTAL 6 +#define AML_AC_PINMUX_G1_TOTAL 29 +#define AML_DFI_PINMUX_TOTAL 26 +#define AML_DQ_PINMUX_TOTAL 36 +#define AML_DQ_BYTES_TOTAL 4 + + +/* d2pll defines */ +#define D2PLL_ENABLE 1 +#define DDR_STICKY_MAGIC_NUMBER 0x20180000 +#define DDR_CHIP_ID 0x30 +#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config +#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test +#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000 +#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000 + + +/* debug function*/ + +/* ddr configs */ +#define DDR_RFC_TYPE_DDR3_512Mbx1 0 +#define DDR_RFC_TYPE_DDR3_512Mbx2 1 +#define DDR_RFC_TYPE_DDR3_512Mbx4 2 +#define DDR_RFC_TYPE_DDR3_512Mbx8 3 +#define DDR_RFC_TYPE_DDR3_512Mbx16 4 +#define DDR_RFC_TYPE_DDR4_2Gbx1 5 +#define DDR_RFC_TYPE_DDR4_2Gbx2 6 +#define DDR_RFC_TYPE_DDR4_2Gbx4 7 +#define DDR_RFC_TYPE_DDR4_2Gbx8 8 + +#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 +#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 +#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 +#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12 +#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13 + +#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0) +#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1) +#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2) +#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3) +#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4) + +#define IMPEDENCE_120P3_240P2_480P1 1 +#define IMPEDENCE_120P6_1 2 +#define IMPEDENCE_120P3_240P2_480P1_ODT 3 + +#define IMPEDENCE_AML_SOC_DATA 1 +#define IMPEDENCE_AML_SOC_AC 2 + + +#define VREF_DDR4_SDRAM_DAC 1 +#define VREF_LPDDR4_SDRAM_DAC 2 +#define VREF_LPDDR4X_SDRAM_DAC 3 +#define VREF_SOC_AML_DAC_LPDDR4 4 +#define VREF_SOC_AML_DAC_LPDDR4X 5 +#define VREF_SOC_AML_DAC_DDR3 6 +#define VREF_SOC_AML_DAC_DDR4 7 + +#define DDR_PHY_BLOCK_ANIB 0x0 +#define DDR_PHY_BLOCK_DBYTE 0x1 +#define DDR_PHY_BLOCK_MASTER 0x2 +#define DDR_PHY_BLOCK_ACSM 0x4 +#define DDR_PHY_BLOCK_UPTCL_MEMORY 0x5 +#define DDR_PHY_BLOCK_PPGC 0x7 +#define DDR_PHY_BLOCK_INITENG 0x9 +#define DDR_PHY_BLOCK_PUB 0xC +#define DDR_PHY_BLOCK_APBONLY 0xD + +/* others */ /* useless? */ + +/* bist */ +#define CONFIG_DDR_CODE_INCLUDE_LPDDR3 0 +#define CONFIG_DDR_CODE_INCLUDE_DDR4 1 +#define CONFIG_DEBUG_INCLUDE_D2PLL 1 +#define CONFIG_DEBUG_DDR_BIST_TEST_WINDOWS 1 +#define CONFIG_DEBUG_DDR_BIST_ONLY_COMPARE_ONE_LANE 1 +#define CONFIG_DEBUG_DDR_BIST_BYTE_EXTRA_PATTERN 1 +#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE 1 +#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE_USE_LINEAR 0 +#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE_USE_FAST_LINEAR 1 +#define CONFIG_DEBUG_DDR_BIST_USE_OLD_METHOD_AGAIN 0 +#define CONFIG_DDR_DMC_DDR_TEST 0 +#define CONFIG_DDR_CPU_DDR_TEST 0 +#define CONFIG_BIST_USE_THRESHOLD 0 +#define CONFIG_DEBUG_DDR_BIST_TEST_2D_EYE 0 + +#define CONFIG_DEBUG_DDR_BIST_TEST_DATA +//#define CONFIG_DEBUG_DDR_BIST_TEST_ADD + +#define DDR_BIST_LANE_DATA0 0 +#define DDR_BIST_LANE_DATA1 1 +#define DDR_BIST_LANE_DATA2 2 +#define DDR_BIST_LANE_DATA3 3 +#define DDR_BIST_LANE_AC 4 + +#define DDR_BIST_PATTERN_WALK_0 0 +#define DDR_BIST_PATTERN_WALK_1 1 +#define DDR_BIST_PATTERN_WALK_RANDOM 2 +#define DDR_BIST_PATTERN_WALK_PRE 3 + +/* diagnose function defines */ +#define CONFIG_DIAGNOSE_DISABLE 0x0 +#define CONFIG_DIAGNOSE_1D 0x1 +#define CONFIG_DIAGNOSE_2D 0x2 +#define CONFIG_DIAGNOSE_1D_2D 0x3 + +#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12 +#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13 + + +#define CONFIG_BOARD_ID_DISABLE 0 +#define CONFIG_BOARD_ID_MASK 0xFF + +#define CONFIG_DDR_TYPE_DDR3 0 +#define CONFIG_DDR_TYPE_DDR4 1 +#define CONFIG_DDR_TYPE_LPDDR4 2 +#define CONFIG_DDR_TYPE_LPDDR3 3 +#define CONFIG_DDR_TYPE_LPDDR2 4 +#define CONFIG_DDR_TYPE_LPDDR4X 5 + +#define CONFIG_DDR0_16BIT_CH0 1 +#define CONFIG_DDR0_16BIT_RANK01_CH0 4 +#define CONFIG_DDR0_32BIT_RANK0_CH0 2 +#define CONFIG_DDR0_32BIT_RANK01_CH01 3 +#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 5 +#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 6 +#define CONFIG_DDR0_32BIT_RANK01_CH0 7 +#define CONFIG_DDR0_32BIT_RANK0_CH01 8 +#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_LOW_CH0 0x9 +#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_HIGH_CH0 0xa +#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0_MODE2 0xB +#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_LOW_CH0_MODE2 0xC + +#define CONFIG_DISABLE_D32_D63 0xf0 +#define CONFIG_DISABLE_D16_D31 0xfc + +#define CONFIG_DDR0_SIZE_0MB 0 +#define CONFIG_DDR0_SIZE_128MB 128 +#define CONFIG_DDR0_SIZE_256MB 256 +#define CONFIG_DDR0_SIZE_512MB 512 +#define CONFIG_DDR0_SIZE_768MB 768 +#define CONFIG_DDR0_SIZE_1024MB 1024 +#define CONFIG_DDR0_SIZE_1536MB 1536 +#define CONFIG_DDR0_SIZE_2048MB 2048 +#define CONFIG_DDR0_SIZE_3072MB 3072 +#define CONFIG_DDR0_SIZE_4096MB 4096 +#define CONFIG_DDR0_SIZE_AUTO_SIZE 0xffff +#define CONFIG_DDR1_SIZE_0MB 0 +#define CONFIG_DDR1_SIZE_128MB 128 +#define CONFIG_DDR1_SIZE_256MB 256 +#define CONFIG_DDR1_SIZE_512MB 512 +#define CONFIG_DDR1_SIZE_768MB 768 +#define CONFIG_DDR1_SIZE_1024MB 1024 +#define CONFIG_DDR1_SIZE_1536MB 1536 +#define CONFIG_DDR1_SIZE_2048MB 2048 +#define CONFIG_DDR1_SIZE_3072MB 3072 +#define CONFIG_DDR1_SIZE_4096MB 4096 +#define CONFIG_DDR1_SIZE_AUTO_SIZE 0xffff + +#define CONFIG_DRAM_MODE_X4 1 +#define CONFIG_DRAM_MODE_X8 1 +#define CONFIG_DRAM_MODE_X16 0 + +#define CONFIG_USE_DDR_1T_MODE 0 +#define CONFIG_USE_DDR_2T_MODE 1 + +#define eLOG_CHL_0 0 +#define eLOG_CHL_1 1 +#define eLOG_CHL_2 2 +#define eLOG_CHL_3 3 +#define eLOG_CHL_4 4 +#define eLOG_CHL_5 5 +#define eLOG_CHL_6 6 +#define eLOG_CHL_7 7 + +#define LOG_LEVEL_BASIC (1<<eLOG_CHL_0) +#define LOG_LEVEL_FULL (1<<eLOG_CHL_0)|(1<<eLOG_CHL_1)|(1<<eLOG_CHL_2)|(1<<eLOG_CHL_3)|(1<<eLOG_CHL_4)|(1<<eLOG_CHL_5)|(1<<eLOG_CHL_6) +#define LOG_LEVEL_DEBUG (1<<eLOG_CHL_0)|(1<<eLOG_CHL_1)|(1<<eLOG_CHL_2)|(1<<eLOG_CHL_3)|(1<<eLOG_CHL_4)|(1<<eLOG_CHL_5)|(1<<eLOG_CHL_6)|(1<<eLOG_CHL_7) + +#define DDR_WRITE_READ_DBI_DISABLE 0 +#define DDR_READ_DBI_ENABLE 1 +#define DDR_WRITE_DBI_ENABLE 2 +#define DDR_WRITE_READ_DBI_ENABLE 3 + +#define DDR_PLL_SSC_DISABLE 0 +#define DDR_PLL_SSC_3000PPM 0x3000 +#define DDR_PLL_SSC_5000PPM 0x3001 +#define DDR_PLL_SSC_6000PPM 0x3002 +#define DDR_PLL_SSC_8000PPM 0x3003 +#define DDR_PLL_SSC_9000PPM 0x3004 + +#define DDR_DMC_REMAP_DDR3_32BIT {\ + [0] = ( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25 ),\ + [1] = ( 11| 0 << 5 | 0 << 10 | 12 << 15 | 16 << 20 | 17 << 25 ),\ + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\ + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\ + [4] = ( 30| 13 << 5 | 14 << 10 | 15 << 15 | 0 << 20 | 0 << 25 ),\ + } + +#define DDR_DMC_REMAP_DDR4_32BIT {\ + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),\ + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\ + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\ + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\ + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 31 << 25 ),\ + } + + +#define DDR_DMC_REMAP_DDR3_16BIT {\ + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\ + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\ + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\ + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\ + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),\ + } + +#define DDR_DMC_REMAP_DDR4_16BIT {\ + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\ + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\ + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\ + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\ + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 30 << 25 ),\ + } +#define DDR_DMC_REMAP_LPDDR4_16BIT {\ + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\ + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\ + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\ + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\ + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),\ + } + +#define DDR_DMC_REMAP_LPDDR4_32BIT {\ + [0] = ( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25 ),\ + [1] = ( 11| 0 << 5 | 0 << 10 | 12 << 15 | 14 << 20 | 15 << 25 ),\ + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\ + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\ + [4] = ( 30| 13 << 5 | 16 << 10 | 20 << 15 | 0 << 20 | 0 << 25 ),\ + } + //cs0 write bit0-1,cs0 read bit4-5,cs1 write bit 8-9,cs1 read bit 12-13 +#define DDR_DRAM_ODT_DISABLE 0 +#define DDR_DRAM_ODT_W_CS0_ODT0 0x1 +#define DDR_DRAM_ODT_W_CS0_ODT0_CS1_ODT1 0x201 +#define DDR_DRAM_ODT_W_CS0_ODT1_CS1_ODT0 0x102 +#define DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01 0x303 +#define DDR_DRAM_ODT_W_CS0_ODT0_CS1_ODT1__R_CS0_ODT1_CS1_ODT0 0x1221 +#define DDR_DRAM_ODT_W_CS0_ODT1_CS1_ODT0__R_CS0_ODT1_CS1_ODT0 0x1122 +#define DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01__R_CS0_ODT1_CS1_ODT0 0x1323 +#define DDR_DRAM_ODT_R_CS0_ODT1_CS1_ODT0 0x1020 + +#define DDR_SOC_AC_DRV_0_OHM 0 +#define DDR_SOC_AC_DRV_120_OHM 120 +#define DDR_SOC_AC_DRV_60_OHM 60 +#define DDR_SOC_AC_DRV_40_OHM 40 +#define DDR_SOC_AC_DRV_30_OHM 30 +#define DDR_SOC_AC_DRV_24_OHM 24 +#define DDR_SOC_AC_DRV_20_OHM 20 + +#define DDR_SOC_DATA_DRV_ODT_0_OHM 0 +#define DDR_SOC_DATA_DRV_ODT_240_OHM 240 +#define DDR_SOC_DATA_DRV_ODT_120_OHM 120 +#define DDR_SOC_DATA_DRV_ODT_80_OHM 80 +#define DDR_SOC_DATA_DRV_ODT_60_OHM 60 +#define DDR_SOC_DATA_DRV_ODT_48_OHM 48 +#define DDR_SOC_DATA_DRV_ODT_40_OHM 40 +#define DDR_SOC_DATA_DRV_ODT_34_OHM 34 + +#define DDR_DRAM_DDR3_DRV_34_OHM 34 +#define DDR_DRAM_DDR3_DRV_40_OHM 40 +#define DDR_DRAM_DDR4_DRV_34_OHM 34 +#define DDR_DRAM_DDR4_DRV_48_OHM 48 +#define DDR_DRAM_LPDDR3_DRV_34_OHM 34 +#define DDR_DRAM_LPDDR3_DRV_40_OHM 40 +#define DDR_DRAM_LPDDR3_DRV_48_OHM 48 +#define DDR_DRAM_LPDDR4_DRV_40_OHM 40 +#define DDR_DRAM_LPDDR4_DRV_48_OHM 48 +#define DDR_DRAM_LPDDR4_DRV_60_OHM 60 +#define DDR_DRAM_LPDDR4_DRV_80_OHM 80 +#define DDR_DRAM_LPDDR4_DRV_120_OHM 120 +#define DDR_DRAM_LPDDR4_DRV_240_OHM 240 + +#define DDR_DRAM_DDR3_ODT_0_OHM 0 +#define DDR_DRAM_DDR3_ODT_120_OHM 120 +#define DDR_DRAM_DDR3_ODT_60_OHM 60 +#define DDR_DRAM_DDR3_ODT_40_OHM 40 +#define DDR_DRAM_LPDDR3_ODT_0_OHM 0 +#define DDR_DRAM_LPDDR3_ODT_240_OHM 240 +#define DDR_DRAM_LPDDR3_ODT_120_OHM 120 +#define DDR_DRAM_LPDDR3_ODT_60_OHM 60 +#define DDR_DRAM_LPDDR4_ODT_0_OHM 0 +#define DDR_DRAM_LPDDR4_ODT_240_OHM 240 +#define DDR_DRAM_LPDDR4_ODT_120_OHM 120 +#define DDR_DRAM_LPDDR4_ODT_80_OHM 80 +#define DDR_DRAM_LPDDR4_ODT_60_OHM 60 +#define DDR_DRAM_LPDDR4_ODT_48_OHM 48 +#define DDR_DRAM_LPDDR4_ODT_40_OHM 40 +#define DDR_DRAM_DDR4_ODT_0_OHM 0 +#define DDR_DRAM_DDR4_ODT_34_OHM 34 +#define DDR_DRAM_DDR4_ODT_40_OHM 40 +#define DDR_DRAM_DDR4_ODT_48_OHM 48 +#define DDR_DRAM_DDR4_ODT_60_OHM 60 +#define DDR_DRAM_DDR4_ODT_80_OHM 80 +#define DDR_DRAM_DDR4_ODT_120_OHM 120 +#define DDR_DRAM_DDR4_ODT_240_OHM 240 + +#define DDR_DRAM_DDR_WR_ODT_0_OHM 0 +#define DDR_DRAM_DDR3_WR_ODT_0_OHM 0 +#define DDR_DRAM_DDR3_WR_ODT_120_OHM 120 +#define DDR_DRAM_DDR3_WR_ODT_60_OHM 60 +#define DDR_DRAM_DDR4_WR_ODT_0_OHM 0 +#define DDR_DRAM_DDR4_WR_ODT_240_OHM 240 +#define DDR_DRAM_DDR4_WR_ODT_120_OHM 120 +#define DDR_DRAM_DDR4_WR_ODT_80_OHM 80 + +#define DDR_DRAM_DDR_AC_ODT_0_OHM 0 +#define DDR_DRAM_LPDDR4_AC_ODT_0_OHM 0 +#define DDR_DRAM_LPDDR4_AC_ODT_240_OHM 240 +#define DDR_DRAM_LPDDR4_AC_ODT_120_OHM 120 +#define DDR_DRAM_LPDDR4_AC_ODT_80_OHM 80 +#define DDR_DRAM_LPDDR4_AC_ODT_60_OHM 60 +#define DDR_DRAM_LPDDR4_AC_ODT_48_OHM 48 +#define DDR_DRAM_LPDDR4_AC_ODT_40_OHM 40 + +#define DDR_DRAM_LPDDR4_OUTPUT_2_5_VDDQ 0 +#define DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ 1 + +#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_0_DDR3 1 +#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_1_DDR4 2 +#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_2_DDR4 3 +#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_3_LPDDR4 4 + +#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3 5 +#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR4 6 +#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_LPDDR4 7 +#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_3_LPDDR4 8 + +#define DDR_SOC_READ_DQS_GATE_MODE_WIDE_MODE_RPULL_0_DDR3 9 +#define DDR_SOC_READ_DQS_GATE_MODE_WIDE_MODE_RPULL_1_LPDDR4 10 + +#if 0 +#define DDR_SOC_READ_DQS_GATE_MODE_RPULL_WIDE_WINDOW 1 + +#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_0 2 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_1 3 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_2 4 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_3 5 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_0 6 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_1 7 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_2 8 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_3 9 + +#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_0 10 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_1 11 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_2 12 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_3 13 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_0 14 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_1 15 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_2 16 +#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_3 17 + +#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_0 18 +#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_1 19 +#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_2 20 +#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_3 21 +#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_0 22 +#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_1 23 +#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_2 24 +#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_3 25 +#endif
diff --git a/arch/arm/include/asm/arch-c2/efuse.h b/arch/arm/include/asm/arch-c2/efuse.h new file mode 100644 index 0000000..4a68e88 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/efuse.h
@@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __EFUSE_H +#define __EFUSE_H + +#include <config.h> +#include <common.h> + +/* efuse HAL_API arg */ +struct efuse_hal_api_arg { + unsigned int cmd; /* R/W */ + unsigned int offset; + unsigned int size; + unsigned long buffer_phy; + unsigned long retcnt_phy; +}; + + +#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */ + +#define EFUSE_HAL_API_READ 0 +#define EFUSE_HAL_API_WRITE 1 +#define EFUSE_HAL_API_WRITE_PATTERN 2 +#define EFUSE_HAL_API_USER_MAX 3 + +#define EFUSE_USER_MASK (0x1 << 16) +#define EFUSE_THERMAL_MASK (0x1 << 17) +#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18) +#define EFUSE_ENCRYPT_MASK (0x1 << 19) + +//#define ASSIST_HW_REV 0x1f53 + +int efuse_read_usr(char *buf, size_t count, loff_t *ppos); +int efuse_write_usr(char *buf, size_t count, loff_t *ppos); +uint32_t efuse_get_max(void); +ssize_t efuse_read(char *buf, size_t count, loff_t *ppos); +ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos); + +int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg); +int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg); + +#endif +
diff --git a/arch/arm/include/asm/arch-c2/eth_setup.h b/arch/arm/include/asm/arch-c2/eth_setup.h new file mode 100644 index 0000000..6e643f6 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/eth_setup.h
@@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/io.h> + +/* + *board configuration interface. + * */ +struct eth_clock_conf{ + int enable; + int clock_50MHZ_phase; + //add ... as you need. +}; + +struct eth_board_socket{ +char *name ; +int (*eth_clock_configure)(struct eth_clock_conf); +int (*eth_pinmux_setup)(void); +int (*eth_hw_reset)(void); + +}; + + + +/* + *clock define part + */ + +#define ETH_BASE (0xff3f0000) +#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050) + /* Ethernet ctrl */ +#define ETH_PLL_CNTL_DIVEN (1<<0) +#define ETH_PLL_CNTL_MACSPD (1<<1) +#define ETH_PLL_CNTL_DATEND (1<<2) +#define ETH_PLL_CNTL_DESEND (1<<3) + + +/* + please refer following doc for detail + @AppNote-M3-ClockTrees.docx + + select clk: -> CBUS_REG(0x1076) + + 7-sys_pll_div2 + 6-vid2_pll_clk + 5-vid_pll_clk + 4-aud_pll_clk + 3-ddr_pll_clk + 2-misc_pll_clk + 1-sys_pll_clk + 0-XTAL + + clk_freq:800MHz + output_clk:50MHz + aways,maybe changed for others? +*/ + +#define ETH_CLKSRC_XTAL (0) +#define ETH_CLKSRC_SYS_PLL_CLK (1) +#define ETH_CLKSRC_MISC_PLL_CLK (2) +#define ETH_CLKSRC_DDR_PLL_CLK (3) +#define ETH_CLKSRC_AUD_PLL_CLK ( +#define ETH_CLKSRC_VID_PLL_CLK (5) +#define ETH_CLKSRC_VID2_PLL_CLK (6) +#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7) +#define CLK_1M (1000000) + +typedef union eth_aml_reg0 { + /** raw register data */ + unsigned int d32; + /** register bits */ + struct { + unsigned phy_intf_sel:3; + unsigned rx_clk_rmii_invert:1; + unsigned rgmii_tx_clk_src:1; + unsigned rgmii_tx_clk_phase:2; + unsigned rgmii_tx_clk_ratio:3; + unsigned phy_ref_clk_enable:1; + unsigned clk_rmii_i_invert:1; + unsigned clk_en:1; + unsigned adj_enable:1; + unsigned adj_setup:1; + unsigned adj_delay:5; + unsigned adj_skew:5; + unsigned cali_start:1; + unsigned cali_rise:1; + unsigned cali_sel:3; + unsigned rgmii_rx_reuse:1; + unsigned eth_urgent:1; + } b; +} eth_aml_reg0_t; + +#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0) + +int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk); +
diff --git a/arch/arm/include/asm/arch-c2/gpio.h b/arch/arm/include/asm/arch-c2/gpio.h new file mode 100644 index 0000000..2467368 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/gpio.h
@@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ASM_ARCH_MESON_GPIO_H +#define __ASM_ARCH_MESON_GPIO_H + + +#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-c2/i2c.h b/arch/arm/include/asm/arch-c2/i2c.h new file mode 100644 index 0000000..a93a09d --- /dev/null +++ b/arch/arm/include/asm/arch-c2/i2c.h
@@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_MACH_I2C__ +#define __AML_MACH_I2C__ + +#include <asm/io.h> +#include <asm/arch/secure_apb.h> + +/** + * struct i2c_msg - an I2C transaction segment beginning with START + * @addr: Slave address, either seven or ten bits. When this is a ten + * bit address, I2C_M_TEN must be set in @flags and the adapter + * must support I2C_FUNC_10BIT_ADDR. + * @flags: I2C_M_RD is handled by all adapters. No other flags may be + * provided unless the adapter exported the relevant I2C_FUNC_* + * flags through i2c_check_functionality(). + * @len: Number of data bytes in @buf being read from or written to the + * I2C slave address. For read transactions where I2C_M_RECV_LEN + * is set, the caller guarantees that this buffer can hold up to + * 32 bytes in addition to the initial length byte sent by the + * slave (plus, if used, the SMBus PEC); and this value will be + * incremented by the number of block data bytes received. + * @buf: The buffer into which data is read, or from which it's written. + * + * An i2c_msg is the low level representation of one segment of an I2C + * transaction. It is visible to drivers in the @i2c_transfer() procedure, + * to userspace from i2c-dev, and to I2C adapter drivers through the + * @i2c_adapter.@master_xfer() method. + * + * Except when I2C "protocol mangling" is used, all I2C adapters implement + * the standard rules for I2C transactions. Each transaction begins with a + * START. That is followed by the slave address, and a bit encoding read + * versus write. Then follow all the data bytes, possibly including a byte + * with SMBus PEC. The transfer terminates with a NAK, or when all those + * bytes have been transferred and ACKed. If this is the last message in a + * group, it is followed by a STOP. Otherwise it is followed by the next + * @i2c_msg transaction segment, beginning with a (repeated) START. + * + * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then + * passing certain @flags may have changed those standard protocol behaviors. + * Those flags are only for use with broken/nonconforming slaves, and with + * adapters which are known to support the specific mangling options they + * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR). + */ +struct i2c_msg { + __u16 addr; /* slave address */ + __u16 flags; +#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */ + __u16 len; /* msg length */ + __u8 *buf; /* pointer to msg data */ +}; + +#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG) +//#define MESON_I2C_MASTER_AO_END (0xc810051c+5) + +#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG) +#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG) +#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG) +#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG) +#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1) + +#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG) +#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1) + + +#define AML_I2C_MASTER_AO 0 +#define AML_I2C_MASTER_A 1 +#define AML_I2C_MASTER_B 2 +#define AML_I2C_MASTER_C 3 +#define AML_I2C_MASTER_D 4 + + +#define AML_I2C_SLAVE_ADDR 0x6c + +/*M1 i2c pinmux + * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE + * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13] + * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13] + * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17] + * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21] + * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6] + * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3] + * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14] + * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10] + * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29] + * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26] + * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10] + * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7] + * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28] + * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26] +*/ + +/*i2c master a*/ + + +#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9) +#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7) +#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9) +#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8) + +#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5) +#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22) +#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5) +#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23) + +/*i2c master b*/ + + +#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6) +#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7) + +#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14) +#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15) + +/*i2c master c*/ +#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4) +#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28) +#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4) +#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29) + +#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1) +#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22) +#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1) +#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23) + +/*i2c master d*/ + + +#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10) +#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11) + +#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23) +#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24) + +/*i2c master AO*/ + + +#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */ +#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8) +#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */ +#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9) + +/*i2c slave*/ +#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13) +#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13) + +#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14) +#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10) + +#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) +#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10) +#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) +#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7) + +#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17) +#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21) + +#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6) +#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3) + +#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) +#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29) +#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) +#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26) + +#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) +#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28) +#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) +#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26) + + +#define AML_I2C_SPPED_50K 50000 +#define AML_I2C_SPPED_100K 100000 +#define AML_I2C_SPPED_200K 200000 +#define AML_I2C_SPPED_300K 300000 +#define AML_I2C_SPPED_400K 400000 + +struct aml_pinmux_reg_bit { + unsigned long scl_reg; + unsigned long sda_reg; + unsigned int scl_bit; + unsigned int sda_bit; +}; + +struct aml_i2c_platform{ + unsigned int slave_addr;/*7bit addr*/ + unsigned int wait_count;/*i2c wait ack timeout = + wait_count * wait_ack_interval */ + unsigned int wait_ack_interval; + unsigned int wait_read_interval; + unsigned int wait_xfer_interval; + unsigned int master_no; + unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/ + unsigned int master_i2c_speed; + + /* only need 1 i2c master to comunicate with several devices, + * should I prepare 2 master interface to use simultaneously?*/ + struct resource * resource; + struct aml_pinmux_reg_bit master_ao_pinmux; + struct aml_pinmux_reg_bit master_a_pinmux; + struct aml_pinmux_reg_bit master_b_pinmux; + struct aml_pinmux_reg_bit master_c_pinmux; + struct aml_pinmux_reg_bit master_d_pinmux; + + struct aml_pinmux_reg_bit slave_reg_bit; +}; + +/**************i2c software gpio***************/ + +#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N) +#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O) +#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I) + +#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N) +#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O) +#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I) + +#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N) +#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O) +#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I) + +struct aml_sw_i2c_pins +{ + unsigned int scl_reg_out; + unsigned int scl_reg_in; + unsigned int scl_bit; + unsigned int scl_oe; + unsigned int sda_reg_out; + unsigned int sda_reg_in; + unsigned int sda_bit; + unsigned int sda_oe; +}; + + +struct aml_sw_i2c_platform { + struct aml_sw_i2c_pins sw_pins; + + /* local settings */ + int udelay; /* half clock cycle time in us, + minimum 2 us for fast-mode I2C, + minimum 5 us for standard-mode I2C and SMBus, + maximum 50 us for SMBus */ + int timeout; /* in jiffies */ +}; + + +#endif //__AML_MACH_I2C__ + +
diff --git a/arch/arm/include/asm/arch-c2/io.h b/arch/arm/include/asm/arch-c2/io.h new file mode 100644 index 0000000..fd3981a --- /dev/null +++ b/arch/arm/include/asm/arch-c2/io.h
@@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MACH_MESSON_REGS_IO_H +#define __MACH_MESSON_REGS_IO_H + +#ifndef __ASSEMBLY__ + +#include <asm/io.h> +#define IO_CBUS_BASE (0xFFD00000L) +#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */ +#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */ +#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */ +#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */ +#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */ + +#define CBUS_REG_OFFSET(reg) ((reg) << 2) +#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg)) + +#define AXI_REG_OFFSET(reg) ((reg) << 2) +#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg)) + +#define AHB_REG_OFFSET(reg) ((reg) << 2) +#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg)) + +#define VPU_REG_OFFSET(reg) ((reg) << 2) +#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg)) + + +#define APB_REG_OFFSET(reg) (reg) +#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg)) +#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) + +#define APB_HDMI_REG_OFFSET(reg) (reg) +#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg)) +#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) + + +#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg)) +#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg))) +#define WRITE_CBUS_REG_BITS(reg, val, start, len) \ + WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_CBUS_REG_BITS(reg, start, len) \ + ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask)))) +#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask))) + +#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg)) +#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg))) +#define WRITE_AXI_REG_BITS(reg, val, start, len) \ + WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_AXI_REG_BITS(reg, start, len) \ + ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask)))) +#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask))) + +#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg)) +#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg))) +#define WRITE_AHB_REG_BITS(reg, val, start, len) \ + WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_AHB_REG_BITS(reg, start, len) \ + ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask)))) +#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask))) + +#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg)) +#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg))) +#define WRITE_APB_REG_BITS(reg, val, start, len) \ + WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_APB_REG_BITS(reg, start, len) \ + ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask)))) +#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask))) + +#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg)) +#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg))) +#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \ + WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_APB_HDMI_REG_BITS(reg, start, len) \ + ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask)))) +#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask))) + +/* for back compatible alias */ +#define WRITE_MPEG_REG(reg, val) \ + WRITE_CBUS_REG(reg, val) +#define READ_MPEG_REG(reg) \ + READ_CBUS_REG(reg) +#define WRITE_MPEG_REG_BITS(reg, val, start, len) \ + WRITE_CBUS_REG_BITS(reg, val, start, len) +#define READ_MPEG_REG_BITS(reg, start, len) \ + READ_CBUS_REG_BITS(reg, start, len) +#define CLEAR_MPEG_REG_MASK(reg, mask) \ + CLEAR_CBUS_REG_MASK(reg, mask) +#define SET_MPEG_REG_MASK(reg, mask) \ + SET_CBUS_REG_MASK(reg, mask) +#endif + + +#endif
diff --git a/arch/arm/include/asm/arch-c2/mailbox.h b/arch/arm/include/asm/arch-c2/mailbox.h new file mode 100644 index 0000000..04ae20f --- /dev/null +++ b/arch/arm/include/asm/arch-c2/mailbox.h
@@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + + /* + * + * Copyright (C) 2012 Amlogic, Inc. + * + * Author: Platform-SH@amlogic.com + * + */ + +#ifndef __GXBB_MAILBOX_H_ +#define __GXBB_MAILBOX_H_ + +#define SCPI_CMD_SENSOR_VALUE 0x1C +#define SCPI_CMD_SET_USR_DATA 0x20 +#define SCPI_CMD_OPEN_SCP_LOG 0xC4 +#define SCPI_CMD_THERMAL_CALIB 0xC5 + +#define SCPI_CMD_USB_BOOT 0xB0 +#define SCPI_CMD_USB_UNBOOT 0xB1 +#define SCPI_CMD_SDCARD_BOOT 0xB2 +#define SCPI_CMD_CLEAR_BOOT 0xB3 + +#define SCPI_CMD_REV_PWM_DELT 0x42 + +#define LOW_PRIORITY 0 +#define HIGH_PRIORITY 1 + +#define P_SHARE_SRAM_BASE 0xfffa0000 +#define SRAM_SIZE 0x48000 +#define MHU_HIGH_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0xc00) +#define MHU_HIGH_AP_TO_SCP_PAYLOAD (MHU_HIGH_SCP_TO_AP_PAYLOAD + 0x200) +#define MHU_LOW_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0x1000) +#define MHU_LOW_AP_TO_SCP_PAYLOAD (MHU_LOW_SCP_TO_AP_PAYLOAD + 0x200) + +enum scpi_client_id { + SCPI_CL_NONE, + SCPI_CL_CLOCKS, + SCPI_CL_DVFS, + SCPI_CL_POWER, + SCPI_CL_THERMAL, + SCPI_CL_REMOTE, + SCPI_CL_LED_TIMER, + SCPI_MAX = 0xff, +}; + +enum scpi_error_codes { + SCPI_SUCCESS = 0, /* Success */ + SCPI_ERR_PARAM = 1, /* Invalid parameter(s) */ + SCPI_ERR_ALIGN = 2, /* Invalid alignment */ + SCPI_ERR_SIZE = 3, /* Invalid size */ + SCPI_ERR_HANDLER = 4, /* Invalid handler/callback */ + SCPI_ERR_ACCESS = 5, /* Invalid access/permission denied */ + SCPI_ERR_RANGE = 6, /* Value out of range */ + SCPI_ERR_TIMEOUT = 7, /* Timeout has occurred */ + SCPI_ERR_NOMEM = 8, /* Invalid memory area or pointer */ + SCPI_ERR_PWRSTATE = 9, /* Invalid power state */ + SCPI_ERR_SUPPORT = 10, /* Not supported or disabled */ + SCPI_ERR_DEVICE = 11, /* Device error */ + SCPI_ERR_MAX +}; + +void open_scp_log(unsigned int channel); +int thermal_calibration(unsigned int type, unsigned int data); +int thermal_get_value(unsigned int sensor_id, unsigned int *value); +int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size); +void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt); + #endif
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr3.h new file mode 100644 index 0000000..c067367 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR3U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR3U_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // + // + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = DDR3 unbuffered + // 0x02 = Reserved + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A + + + + + + + + + + + + + + + + + + + + uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A + + + + uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A + // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset. + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A + + uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A + + uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A + + uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A + + uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A + + uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A + + uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A + + uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A + + uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A + + uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A + + uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A + + uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A + + uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A + + uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A + + uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A + + uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A + + uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A + + uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A + + uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A + + uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A + + uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A + + uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A + + uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A + + uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A + + uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A + + uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A + +} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4.h new file mode 100644 index 0000000..6dfd4d0 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR4U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR4U_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D. + // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = Reserved + // 0x02 = DDR4 unbuffered + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = Run Reserved + // SequenceCtrl[11] = Run Reserved + // SequenceCtrl[12] = Run Reserved + // SequenceCtrl[13] = Run Reserved + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A + + + + + + + + + + + + + + + + + + + + uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A + + + + uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A + // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset. + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value of DDR mode register MR3 for all ranks for current pstate + uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value of DDR mode register MR4 for all ranks for current pstate + uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value of DDR mode register MR5 for all ranks for current pstate + uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0. + uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // X16 device map. Corresponds to CS[3:0]. + // X16Present[0] = CS0 is populated with X16 devices + // X16Present[1] = CS1 is populated with X16 devices + // X16Present[2] = CS2 is populated with X16 devices + // X16Present[3] = CS3 is populated with X16 devices + // X16Present[7:4] = Reserved (must be programmed to 0) + // + // Ranks may not contain mixed device types. + uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // controls timing of chip select signals when DDR4 gear-down mode is active + // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs + // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode + uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM: + // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0 + // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0 + // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0 + uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM: + // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1 + // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1 + // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1 + uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM: + // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2 + // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2 + // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2 + uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM: + // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3 + // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3 + // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3 + uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM: + // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4 + // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4 + // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4 + uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM: + // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5 + // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5 + // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5 + uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM: + // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6 + // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6 + // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6 + uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM: + // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7 + // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7 + // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7 + uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices. + uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices. + uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices. + uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices. + uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices. + uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices. + uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices. + uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices. + uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices. + uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices. + uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices. + uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices. + uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices. + uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices. + uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices. + uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices. + uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices. + uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices. + uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices. + uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices. + uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices. + uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices. + uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices. + uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices. + uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices. + uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices. + uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices. + uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices. + uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices. + uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices. + uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices. + uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices. + uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices. + uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices. + uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices. + uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices. + uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices. + uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices. + uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices. + uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices. + uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices. + uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices. + uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices. + uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices. + uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices. + uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices. + uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices. + uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices. + uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices. + uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices. + uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices. + uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices. + uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices. + uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices. + uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices. + uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices. + uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices. + uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices. + uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices. + uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices. + uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A + + uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A + + uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A + + uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A + + uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1). + // RdDBI is dynamically disabled in certain training steps, + // and so the [RdDBI disabled] CAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_CAS_L[0] == 0: use value in MR0 + // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2] + // Other bits are ignored + uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1). + // 2tCK write prambles are dynamically disabled in certain training steps, + // and so the [1tCK write preamble] WCAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_WCAS_L[0] == 0: use value in MR2 + // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3] + // Other bits are ignored + uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + // Contains various options for training DDR4 Devices. + // + // Bit fields: + // + // D4Misc[7:1] RFU, must be zero + // + // D4Misc[0] = protect memory reset + // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training. + // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training +} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4_2d.h new file mode 100644 index 0000000..35b1e23 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR4U_2D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR4U_2D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D. + // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = Reserved + // 0x02 = DDR4 unbuffered + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = RFU, must be zero + // SequenceCtrl[2] = RFU, must be zero + // SequenceCtrl[3] = RFU, must be zero + // SequenceCtrl[4] = RFU, must be zero + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = RFU, must be zero + // SequenceCtrl[9] = RFU, must be zero + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Bit fields, if 2D read training enabled, then use these additional options: + // [0] DFE + // 1 = Run rx2D with DFE + // 0 = Run rx2D with DFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Bit fields, if 2D write training is enabled, then use these additional options: + // [0] FFE + // 1 = Train tx2D with FFE + // 0 = Train tx2D with FFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5] FFE Decision Algorithm Control + // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy. + // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy. + // [6-7] RFU, must be zero + // + uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // Bitmap that designates the phy's vref source for every pstate + // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock. + // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training. + uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye. + uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye. + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved5D[0-3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 1 kilobit per point (legacy behavior) + // 1 = 2 kilobits per point + // 2 = 4 kilobits per point + // … + // 15 = 32 megabits per point + // + // Reserved5D[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved5D[5:7]: RFU, must be 0 + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value of DDR mode register MR3 for all ranks for current pstate + uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value of DDR mode register MR4 for all ranks for current pstate + uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value of DDR mode register MR5 for all ranks for current pstate + uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0. + uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // X16 device map. Corresponds to CS[3:0]. + // X16Present[0] = CS0 is populated with X16 devices + // X16Present[1] = CS1 is populated with X16 devices + // X16Present[2] = CS2 is populated with X16 devices + // X16Present[3] = CS3 is populated with X16 devices + // X16Present[7:4] = Reserved (must be programmed to 0) + // + // Ranks may not contain mixed device types. + uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // controls timing of chip select signals when DDR4 gear-down mode is active + // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs + // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode + uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM: + // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0 + // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0 + // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0 + uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM: + // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1 + // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1 + // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1 + uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM: + // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2 + // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2 + // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2 + uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM: + // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3 + // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3 + // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3 + uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM: + // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4 + // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4 + // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4 + uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM: + // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5 + // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5 + // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5 + uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM: + // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6 + // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6 + // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6 + uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM: + // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7 + // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7 + // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7 + uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices. + uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices. + uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices. + uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices. + uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices. + uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices. + uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices. + uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices. + uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices. + uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices. + uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices. + uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices. + uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices. + uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices. + uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices. + uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices. + uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices. + uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices. + uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices. + uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices. + uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices. + uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices. + uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices. + uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices. + uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices. + uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices. + uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices. + uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices. + uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices. + uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices. + uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices. + uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices. + uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices. + uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices. + uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices. + uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices. + uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices. + uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices. + uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices. + uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices. + uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices. + uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices. + uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices. + uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices. + uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices. + uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices. + uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices. + uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices. + uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices. + uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices. + uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices. + uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices. + uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices. + uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices. + uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices. + uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices. + uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices. + uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices. + uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices. + uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices. + uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A + + uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A + + uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A + + uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A + + uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1). + // RdDBI is dynamically disabled in certain training steps, + // and so the [RdDBI disabled] CAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_CAS_L[0] == 0: use value in MR0 + // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2] + // Other bits are ignored + uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1). + // 2tCK write prambles are dynamically disabled in certain training steps, + // and so the [1tCK write preamble] WCAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_WCAS_L[0] == 0: use value in MR2 + // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3] + // Other bits are ignored + uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + // Contains various options for training DDR4 Devices. + // + // Bit fields: + // + // D4Misc[7:1] RFU, must be zero + // + // D4Misc[0] = protect memory reset + // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training. + // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training +} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr3.h new file mode 100644 index 0000000..6850d06 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR3_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR3_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:5] RFU, must be zero + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] RFU, must be zero + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = Run LPCA - CA Training + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[14] = RFU, must be zero + // SequenceCtrl[15] = RFU, must be zero + // + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // This should be set to 1 for all systems. + // + // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value: + // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0 + // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0] + uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value: + // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1 + // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0] + uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value: + // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2 + // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0] + uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value: + // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3 + // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0] + uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value: + // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4 + // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0] + uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value: + // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5 + // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0] + uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value: + // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6 + // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0] + uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value: + // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7 + // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0] + uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. +} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4.h new file mode 100644 index 0000000..d194621 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR4_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR4_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Quick Rd2D during 1D Training + // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] Disable Boot Clock + // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended) + // 0x0 = Use Boot Frequency Clock + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.25*VDDQ, set this field to 0x20. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Lp4 specific options for training. + // + // Bit fields: + // + // Lp4Misc[0] Enable dfi_reset_n + // + // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training. + // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + // + // 0x1 = Enables dfi_reset_n to control memreset after training. + // PHY Internal registers control memreset during training only. + // To ensure that no glitches occur on BP_MEMRESET at the end of training, + // The MC must drive dfi_reset_n=1'b1 _prior to starting training_ + // + // Lp4Misc[7-1] RFU, must be zero + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved0E[0:3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 288 bits per point (legacy behavior) + // 1 = 576 bits per point + // 2 = 1.125 kilobits per point + // … + // 15 = 9 megabits per point + // + // Reserved0E[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved0E[5:7]: RFU, must be 0 + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[11-10] = RFU, must be zero + // SequenceCtrl[12] = Run LPCA - CA Training + // SequenceCtrl[15-13] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // It is recommended in most LPDDR4 system configurations to set this to 1. + // + // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels. + // + uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Enable Quickboot. + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D stages: Rd2D, Wr2D + // + // Reserved1A[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1A[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR14 + // 2 = limit to +/-4 %VDDQ from MR14 + // … + // 15 = limit to +/-30% VDDQ from MR14 + uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // CA training option bit field + // [0] CA VREF Training + // 1 = Enable CA VREF Training + // 0 = Disable CA VREF Training + // [1-7] RFU must be zero + uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // X8 mode configuration: + // 0x0 = x16 configuration for all devices + // 0xF = x8 configuration for all devices + // All other values are RFU + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + + + + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0} + uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0} + uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0} + uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0} + uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0} + uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1} + uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1} + uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1} + uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1} + uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1} + uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1} + uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1} + uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1} + uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1} + uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1} + uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In + // Terminating Rank for CA bus on Channel A + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + + uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A + + uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A + + uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A + + uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A + + uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A + + uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A + + uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A + + uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A + + uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A + + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + + uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0} + uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0} + uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0} + uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0} + uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0} + uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0} + uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0} + uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0} + uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0} + uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0} + uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1} + uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1} + uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1} + uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1} + uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1} + uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1} + uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1} + uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1} + uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1} + uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1} + uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + // Terminating Rank for CA bus on Channel B + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + + uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + + uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + + uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + + uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A + +} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4_2d.h new file mode 100644 index 0000000..c6ab3d3 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR4_2D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR4_2D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Quick Rd2D during 1D Training + // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] Disable Boot Clock + // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended) + // 0x0 = Use Boot Frequency Clock + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.25*VDDQ, set this field to 0x20. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Lp4 specific options for training. + // + // Bit fields: + // + // Lp4Misc[0] Enable dfi_reset_n + // + // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training. + // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + // + // 0x1 = Enables dfi_reset_n to control memreset after training. + // PHY Internal registers control memreset during training only. + // To ensure that no glitches occur on BP_MEMRESET at the end of training, + // The MC must drive dfi_reset_n=1'b1 _prior to starting training_ + // + // Lp4Misc[7-1] RFU, must be zero + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved0E[0:3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 288 bits per point (legacy behavior) + // 1 = 576 bits per point + // 2 = 1.125 kilobits per point + // … + // 15 = 9 megabits per point + // + // Reserved0E[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved0E[5:7]: RFU, must be 0 + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = RFU, must be zero + // SequenceCtrl[2] = RFU, must be zero + // SequenceCtrl[3] = RFU, must be zero + // SequenceCtrl[4] = RFU, must be zero + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = RFU, must be zero + // SequenceCtrl[9] = RFU, must be zero + // SequenceCtrl[11-10] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[15-13] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // It is recommended in most LPDDR4 system configurations to set this to 1. + // + // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D stages: Rd2D, Wr2D + // + // Reserved1A[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1A[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR14 + // 2 = limit to +/-4 %VDDQ from MR14 + // … + // 15 = limit to +/-30% VDDQ from MR14 + uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // CA training option bit field + // [0] CA VREF Setting + // 1 = Set MR12 from internal register + // 0 = Set MR12 from message block + // [1-7] RFU must be zero + uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // X8 mode configuration: + // 0x0 = x16 configuration for all devices + // 0xF = x8 configuration for all devices + // All other values are RFU + uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // Bit fields, if 2D read training enabled, then use these additional options: + // [0] DFE + // 1 = Run rx2D with DFE + // 0 = Run rx2D with DFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Bit fields, if 2D write training is enabled, then use these additional options: + // [0] FFE + // 1 = Train tx2D with FFE + // 0 = Train tx2D with FFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + // Bitmap that designates the phy's vref source for every pstate + // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock. + // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training. + uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye. + uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0} + uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0} + uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0} + uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0} + uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0} + uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1} + uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1} + uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1} + uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1} + uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1} + uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1} + uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1} + uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1} + uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1} + uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1} + uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In + // Terminating Rank for CA bus on Channel A + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + + uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // Trained DQ Vref setting for Ch A Rank 0 + uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // Trained DQ Vref setting for Ch A Rank 1 + uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0} + uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0} + uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0} + uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0} + uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0} + uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0} + uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0} + uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0} + uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0} + uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0} + uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1} + uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1} + uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1} + uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1} + uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1} + uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1} + uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1} + uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1} + uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1} + uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1} + uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + // Terminating Rank for CA bus on Channel B + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + + uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out + // Trained DQ Vref setting for Ch B Rank 0 + uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out + // Trained DQ Vref setting for Ch B Rank 1 + uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. +} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-c2/nand.h b/arch/arm/include/asm/arch-c2/nand.h new file mode 100644 index 0000000..91484ac --- /dev/null +++ b/arch/arm/include/asm/arch-c2/nand.h
@@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __NAND_H__ +#define __NAND_H__ +#include <asm/arch/cpu_config.h> + +#ifndef SD_EMMC_BASE_C +#define SD_EMMC_BASE_C 0xd0074000 +#endif + +#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11)) +#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C) +#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00) +#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04) +#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08) +#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c) +#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10) +#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14) +#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18) +#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c) +#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20) +#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24) +#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28) +#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c) + +#define CEF (0xf<<10) +#define CE0 (0xe<<10) +#define CE1 (0xd<<10) +#define CE2 (0xb<<10) +#define CE3 (0x7<<10) + +#define IO4 ((0xe<<10)|(1<<18)) +#define IO5 ((0xd<<10)|(1<<18)) +#define IO6 ((0xb<<10)|(1<<18)) + +#define CLE (0x5<<14) +#define ALE (0x6<<14) +#define DWR (0x4<<14) +#define DRD (0x8<<14) +#define IDLE (0xc<<14) +#define RB (1<<20) + +#define M2N ((0<<17) | (2<<20) | (1<<19)) +#define N2M ((1<<17) | (2<<20) | (1<<19)) +#define STS ((3<<17) | (2<<20)) +#define ADL ((0<<16) | (3<<20)) +#define ADH ((1<<16) | (3<<20)) +#define AIL ((2<<16) | (3<<20)) +#define AIH ((3<<16) | (3<<20)) +#define ASL ((4<<16) | (3<<20)) +#define ASH ((5<<16) | (3<<20)) +#define SEED ((8<<16) | (3<<20)) + +// NAND Flash Manufacturer ID Codes +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec +#define NAND_MFR_FUJITSU 0x04 +#define NAND_MFR_NATIONAL 0x8f +#define NAND_MFR_RENESAS 0x07 +#define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_HYNIX 0xad +#define NAND_MFR_MICRON 0x2c +#define NAND_MFR_AMD 0x01 +#define NAND_MFR_INTEL 0x89 +#define NAND_MFR_SANDISK 0x45 +#define NAND_MFR_USER 0x100 +#define NAND_MFR_EFUSE 0x101 + +typedef struct nand_setup { + union { + uint32_t d32; + struct { + unsigned cmd:22; + unsigned large_page:1; // 22 + unsigned no_rb:1; // 23 from efuse + unsigned a2:1; // 24 + unsigned reserved25:1; // 25 + unsigned page_list:1; // 26 + unsigned sync_mode:2; // 27 from efuse + unsigned size:2; // 29 from efuse + unsigned active:1; // 31 + } b; + } cfg; + uint16_t id; + uint16_t max; // id:0x100 user, max:0 disable. +} nand_setup_t; + +typedef struct _nand_cmd{ + unsigned char type; + unsigned char val; +} nand_cmd_t; + +typedef struct _ext_info{ + uint32_t read_info; //nand_read_info; + uint32_t new_type; //new_nand_type; + uint32_t page_per_blk; //pages_in_block; + uint32_t xlc; //slc=1, mlc=2, tlc=3. + uint32_t rsv1[5]; +} ext_info_t; + +typedef struct _nand_page0 { + nand_setup_t nand_setup; //8 + unsigned char page_list[16]; //16 + nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F) + ext_info_t ext_info; //64 +} nand_page0_t; //384 bytes max. + +//#define NAND_PAGE0_BUF BL1_NAND_BUFF +#define NAND_PAGE0_BUF (0x1800000) +#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t)) +#define NAND_RETRY_USER (NAND_PAGE_LIST + 16) +#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512) +#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1) +//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1) + +#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num))) +#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) // +#define ERROR_NAND_ECC ERROR_MOD(2,2) // +#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) // +#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) // +#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) // +#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) // + +#define NAND_SECTOR_SIZE (512) +#define NAND_MAX_PAGESIZE (0x4000) //16K +#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE) + +#define INFO_BYTE_PER_ECCPAGE (8) +uint32_t nfio_init(void); +uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size); +#endif /* __NAND_H__ */ +
diff --git a/arch/arm/include/asm/arch-c2/oscring.h b/arch/arm/include/asm/arch-c2/oscring.h new file mode 100644 index 0000000..ce7d7eb --- /dev/null +++ b/arch/arm/include/asm/arch-c2/oscring.h
@@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __OSCRING_H__ +#define __OSCRING_H__ + +#define OSCRING_CTL_REG0 SYSCTRL_OSC_RING_CTRL0 +#define OSCRING_CTL_DATA0 0x00000555 /*0:25*/ +#define OSCRING_CTL_REG1 SYSCTRL_OSC_RING_CTRL1 +#define OSCRING_CTL_DATA1 0x15555555 /*0:7*/ +#define OSCRING_CTL_REG2 SYSCTRL_OSC_RING_CTRL2 +#define OSCRING_CTL_DATA2 0x00000555 + +#define RING_PWM_VCCK PWMAB_PWM_B +#define RING_PWM_EE PWMAB_PWM_A + +int ring_msr(int index); +#endif
diff --git a/arch/arm/include/asm/arch-c2/p_register.h b/arch/arm/include/asm/arch-c2/p_register.h new file mode 100644 index 0000000..24b136d --- /dev/null +++ b/arch/arm/include/asm/arch-c2/p_register.h
@@ -0,0 +1,4083 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifdef P_REGISTER_H +#else +#define P_REGISTER_H + +// +// Reading file: ./REG_LIST_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Reading file: REG_LIST_AUDIO_RTL.h +// +//======================================================================== +// AUDIO - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe050000 +// ----------------------------------------------- +#define P_EE_AUDIO_CLK_GATE_EN0 ((volatile uint32_t *)0xfe050000) +#define P_EE_AUDIO_CLK_GATE_EN1 ((volatile uint32_t *)0xfe050004) +#define P_EE_AUDIO_MCLK_A_CTRL ((volatile uint32_t *)0xfe050008) +#define P_EE_AUDIO_MCLK_B_CTRL ((volatile uint32_t *)0xfe05000c) +#define P_EE_AUDIO_MCLK_C_CTRL ((volatile uint32_t *)0xfe050010) +#define P_EE_AUDIO_MCLK_D_CTRL ((volatile uint32_t *)0xfe050014) +#define P_EE_AUDIO_MCLK_E_CTRL ((volatile uint32_t *)0xfe050018) +#define P_EE_AUDIO_MCLK_F_CTRL ((volatile uint32_t *)0xfe05001c) +#define P_EE_AUDIO_PAD_CTRL0 ((volatile uint32_t *)0xfe050020) +#define P_EE_AUDIO_PAD_CTRL1 ((volatile uint32_t *)0xfe050024) +#define P_EE_AUDIO_SW_RESET0 ((volatile uint32_t *)0xfe050028) +#define P_EE_AUDIO_SW_RESET1 ((volatile uint32_t *)0xfe05002c) +#define P_EE_AUDIO_CLK81_CTRL ((volatile uint32_t *)0xfe050030) +#define P_EE_AUDIO_CLK81_EN ((volatile uint32_t *)0xfe050034) +#define P_EE_AUDIO_MST_A_SCLK_CTRL0 ((volatile uint32_t *)0xfe050040) +#define P_EE_AUDIO_MST_A_SCLK_CTRL1 ((volatile uint32_t *)0xfe050044) +#define P_EE_AUDIO_MST_B_SCLK_CTRL0 ((volatile uint32_t *)0xfe050048) +#define P_EE_AUDIO_MST_B_SCLK_CTRL1 ((volatile uint32_t *)0xfe05004c) +#define P_EE_AUDIO_MST_C_SCLK_CTRL0 ((volatile uint32_t *)0xfe050050) +#define P_EE_AUDIO_MST_C_SCLK_CTRL1 ((volatile uint32_t *)0xfe050054) +#define P_EE_AUDIO_MST_D_SCLK_CTRL0 ((volatile uint32_t *)0xfe050058) +#define P_EE_AUDIO_MST_D_SCLK_CTRL1 ((volatile uint32_t *)0xfe05005c) +#define P_EE_AUDIO_MST_E_SCLK_CTRL0 ((volatile uint32_t *)0xfe050060) +#define P_EE_AUDIO_MST_E_SCLK_CTRL1 ((volatile uint32_t *)0xfe050064) +#define P_EE_AUDIO_MST_F_SCLK_CTRL0 ((volatile uint32_t *)0xfe050068) +#define P_EE_AUDIO_MST_F_SCLK_CTRL1 ((volatile uint32_t *)0xfe05006c) +#define P_EE_AUDIO_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe050070) +#define P_EE_AUDIO_MST_DLY_CTRL1 ((volatile uint32_t *)0xfe050074) +#define P_EE_AUDIO_CLK_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050080) +#define P_EE_AUDIO_CLK_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050084) +#define P_EE_AUDIO_CLK_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050088) +#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe05008c) +#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL ((volatile uint32_t *)0xfe050090) +#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL ((volatile uint32_t *)0xfe050094) +#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL ((volatile uint32_t *)0xfe050098) +#define P_EE_AUDIO_CLK_SPDIFIN_CTRL ((volatile uint32_t *)0xfe05009c) +#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL ((volatile uint32_t *)0xfe0500a0) +#define P_EE_AUDIO_CLK_RESAMPLEA_CTRL ((volatile uint32_t *)0xfe0500a4) +#define P_EE_AUDIO_CLK_LOCKER_CTRL ((volatile uint32_t *)0xfe0500a8) +#define P_EE_AUDIO_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe0500ac) +#define P_EE_AUDIO_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe0500b0) +#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((volatile uint32_t *)0xfe0500b4) +#define P_EE_AUDIO_CLK_RESAMPLEB_CTRL ((volatile uint32_t *)0xfe0500b8) +#define P_EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((volatile uint32_t *)0xfe0500bc) +#define P_EE_AUDIO_CLK_EQDRC_CTRL0 ((volatile uint32_t *)0xfe0500c0) +#define P_EE_AUDIO_VAD_CLK_CTRL ((volatile uint32_t *)0xfe0500c4) +#define P_EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500c8) +#define P_EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500cc) +#define P_EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500d0) +#define P_EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500d4) +#define P_EE_AUDIO_CLK_LOCKERB_CTRL ((volatile uint32_t *)0xfe0500d8) +#define P_EE_AUDIO_TODDR_A_CTRL0 ((volatile uint32_t *)0xfe050100) +#define P_EE_AUDIO_TODDR_A_CTRL1 ((volatile uint32_t *)0xfe050104) +#define P_EE_AUDIO_TODDR_A_START_ADDR ((volatile uint32_t *)0xfe050108) +#define P_EE_AUDIO_TODDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe05010c) +#define P_EE_AUDIO_TODDR_A_INT_ADDR ((volatile uint32_t *)0xfe050110) +#define P_EE_AUDIO_TODDR_A_STATUS1 ((volatile uint32_t *)0xfe050114) +#define P_EE_AUDIO_TODDR_A_STATUS2 ((volatile uint32_t *)0xfe050118) +#define P_EE_AUDIO_TODDR_A_START_ADDRB ((volatile uint32_t *)0xfe05011c) +#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe050120) +#define P_EE_AUDIO_TODDR_A_INIT_ADDR ((volatile uint32_t *)0xfe050124) +#define P_EE_AUDIO_TODDR_A_CTRL2 ((volatile uint32_t *)0xfe050128) +#define P_EE_AUDIO_TODDR_B_CTRL0 ((volatile uint32_t *)0xfe050140) +#define P_EE_AUDIO_TODDR_B_CTRL1 ((volatile uint32_t *)0xfe050144) +#define P_EE_AUDIO_TODDR_B_START_ADDR ((volatile uint32_t *)0xfe050148) +#define P_EE_AUDIO_TODDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05014c) +#define P_EE_AUDIO_TODDR_B_INT_ADDR ((volatile uint32_t *)0xfe050150) +#define P_EE_AUDIO_TODDR_B_STATUS1 ((volatile uint32_t *)0xfe050154) +#define P_EE_AUDIO_TODDR_B_STATUS2 ((volatile uint32_t *)0xfe050158) +#define P_EE_AUDIO_TODDR_B_START_ADDRB ((volatile uint32_t *)0xfe05015c) +#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050160) +#define P_EE_AUDIO_TODDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050164) +#define P_EE_AUDIO_TODDR_B_CTRL2 ((volatile uint32_t *)0xfe050168) +#define P_EE_AUDIO_TODDR_C_CTRL0 ((volatile uint32_t *)0xfe050180) +#define P_EE_AUDIO_TODDR_C_CTRL1 ((volatile uint32_t *)0xfe050184) +#define P_EE_AUDIO_TODDR_C_START_ADDR ((volatile uint32_t *)0xfe050188) +#define P_EE_AUDIO_TODDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05018c) +#define P_EE_AUDIO_TODDR_C_INT_ADDR ((volatile uint32_t *)0xfe050190) +#define P_EE_AUDIO_TODDR_C_STATUS1 ((volatile uint32_t *)0xfe050194) +#define P_EE_AUDIO_TODDR_C_STATUS2 ((volatile uint32_t *)0xfe050198) +#define P_EE_AUDIO_TODDR_C_START_ADDRB ((volatile uint32_t *)0xfe05019c) +#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe0501a0) +#define P_EE_AUDIO_TODDR_C_INIT_ADDR ((volatile uint32_t *)0xfe0501a4) +#define P_EE_AUDIO_TODDR_C_CTRL2 ((volatile uint32_t *)0xfe0501a8) +#define P_EE_AUDIO_FRDDR_A_CTRL0 ((volatile uint32_t *)0xfe0501c0) +#define P_EE_AUDIO_FRDDR_A_CTRL1 ((volatile uint32_t *)0xfe0501c4) +#define P_EE_AUDIO_FRDDR_A_START_ADDR ((volatile uint32_t *)0xfe0501c8) +#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe0501cc) +#define P_EE_AUDIO_FRDDR_A_INT_ADDR ((volatile uint32_t *)0xfe0501d0) +#define P_EE_AUDIO_FRDDR_A_STATUS1 ((volatile uint32_t *)0xfe0501d4) +#define P_EE_AUDIO_FRDDR_A_STATUS2 ((volatile uint32_t *)0xfe0501d8) +#define P_EE_AUDIO_FRDDR_A_START_ADDRB ((volatile uint32_t *)0xfe0501dc) +#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe0501e0) +#define P_EE_AUDIO_FRDDR_A_INIT_ADDR ((volatile uint32_t *)0xfe0501e4) +#define P_EE_AUDIO_FRDDR_A_CTRL2 ((volatile uint32_t *)0xfe0501e8) +#define P_EE_AUDIO_FRDDR_B_CTRL0 ((volatile uint32_t *)0xfe050200) +#define P_EE_AUDIO_FRDDR_B_CTRL1 ((volatile uint32_t *)0xfe050204) +#define P_EE_AUDIO_FRDDR_B_START_ADDR ((volatile uint32_t *)0xfe050208) +#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05020c) +#define P_EE_AUDIO_FRDDR_B_INT_ADDR ((volatile uint32_t *)0xfe050210) +#define P_EE_AUDIO_FRDDR_B_STATUS1 ((volatile uint32_t *)0xfe050214) +#define P_EE_AUDIO_FRDDR_B_STATUS2 ((volatile uint32_t *)0xfe050218) +#define P_EE_AUDIO_FRDDR_B_START_ADDRB ((volatile uint32_t *)0xfe05021c) +#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050220) +#define P_EE_AUDIO_FRDDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050224) +#define P_EE_AUDIO_FRDDR_B_CTRL2 ((volatile uint32_t *)0xfe050228) +#define P_EE_AUDIO_FRDDR_C_CTRL0 ((volatile uint32_t *)0xfe050240) +#define P_EE_AUDIO_FRDDR_C_CTRL1 ((volatile uint32_t *)0xfe050244) +#define P_EE_AUDIO_FRDDR_C_START_ADDR ((volatile uint32_t *)0xfe050248) +#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05024c) +#define P_EE_AUDIO_FRDDR_C_INT_ADDR ((volatile uint32_t *)0xfe050250) +#define P_EE_AUDIO_FRDDR_C_STATUS1 ((volatile uint32_t *)0xfe050254) +#define P_EE_AUDIO_FRDDR_C_STATUS2 ((volatile uint32_t *)0xfe050258) +#define P_EE_AUDIO_FRDDR_C_START_ADDRB ((volatile uint32_t *)0xfe05025c) +#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe050260) +#define P_EE_AUDIO_FRDDR_C_INIT_ADDR ((volatile uint32_t *)0xfe050264) +#define P_EE_AUDIO_FRDDR_C_CTRL2 ((volatile uint32_t *)0xfe050268) +#define P_EE_AUDIO_ARB_CTRL ((volatile uint32_t *)0xfe050280) +#define P_EE_AUDIO_LB_A_CTRL0 ((volatile uint32_t *)0xfe0502c0) +#define P_EE_AUDIO_LB_A_CTRL1 ((volatile uint32_t *)0xfe0502c4) +#define P_EE_AUDIO_LB_A_CTRL2 ((volatile uint32_t *)0xfe0502c8) +#define P_EE_AUDIO_LB_A_CTRL3 ((volatile uint32_t *)0xfe0502cc) +#define P_EE_AUDIO_LB_A_DAT_CH_ID0 ((volatile uint32_t *)0xfe0502d0) +#define P_EE_AUDIO_LB_A_DAT_CH_ID1 ((volatile uint32_t *)0xfe0502d4) +#define P_EE_AUDIO_LB_A_DAT_CH_ID2 ((volatile uint32_t *)0xfe0502d8) +#define P_EE_AUDIO_LB_A_DAT_CH_ID3 ((volatile uint32_t *)0xfe0502dc) +#define P_EE_AUDIO_LB_A_LB_CH_ID0 ((volatile uint32_t *)0xfe0502e0) +#define P_EE_AUDIO_LB_A_LB_CH_ID1 ((volatile uint32_t *)0xfe0502e4) +#define P_EE_AUDIO_LB_A_LB_CH_ID2 ((volatile uint32_t *)0xfe0502e8) +#define P_EE_AUDIO_LB_A_LB_CH_ID3 ((volatile uint32_t *)0xfe0502ec) +#define P_EE_AUDIO_LB_A_STS ((volatile uint32_t *)0xfe0502f0) +#define P_EE_AUDIO_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050300) +#define P_EE_AUDIO_TDMIN_A_SWAP0 ((volatile uint32_t *)0xfe050304) +#define P_EE_AUDIO_TDMIN_A_MASK0 ((volatile uint32_t *)0xfe050308) +#define P_EE_AUDIO_TDMIN_A_MASK1 ((volatile uint32_t *)0xfe05030c) +#define P_EE_AUDIO_TDMIN_A_MASK2 ((volatile uint32_t *)0xfe050310) +#define P_EE_AUDIO_TDMIN_A_MASK3 ((volatile uint32_t *)0xfe050314) +#define P_EE_AUDIO_TDMIN_A_STAT ((volatile uint32_t *)0xfe050318) +#define P_EE_AUDIO_TDMIN_A_MUTE_VAL ((volatile uint32_t *)0xfe05031c) +#define P_EE_AUDIO_TDMIN_A_MUTE0 ((volatile uint32_t *)0xfe050320) +#define P_EE_AUDIO_TDMIN_A_MUTE1 ((volatile uint32_t *)0xfe050324) +#define P_EE_AUDIO_TDMIN_A_MUTE2 ((volatile uint32_t *)0xfe050328) +#define P_EE_AUDIO_TDMIN_A_MUTE3 ((volatile uint32_t *)0xfe05032c) +#define P_EE_AUDIO_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050340) +#define P_EE_AUDIO_TDMIN_B_SWAP0 ((volatile uint32_t *)0xfe050344) +#define P_EE_AUDIO_TDMIN_B_MASK0 ((volatile uint32_t *)0xfe050348) +#define P_EE_AUDIO_TDMIN_B_MASK1 ((volatile uint32_t *)0xfe05034c) +#define P_EE_AUDIO_TDMIN_B_MASK2 ((volatile uint32_t *)0xfe050350) +#define P_EE_AUDIO_TDMIN_B_MASK3 ((volatile uint32_t *)0xfe050354) +#define P_EE_AUDIO_TDMIN_B_STAT ((volatile uint32_t *)0xfe050358) +#define P_EE_AUDIO_TDMIN_B_MUTE_VAL ((volatile uint32_t *)0xfe05035c) +#define P_EE_AUDIO_TDMIN_B_MUTE0 ((volatile uint32_t *)0xfe050360) +#define P_EE_AUDIO_TDMIN_B_MUTE1 ((volatile uint32_t *)0xfe050364) +#define P_EE_AUDIO_TDMIN_B_MUTE2 ((volatile uint32_t *)0xfe050368) +#define P_EE_AUDIO_TDMIN_B_MUTE3 ((volatile uint32_t *)0xfe05036c) +#define P_EE_AUDIO_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050380) +#define P_EE_AUDIO_TDMIN_C_SWAP0 ((volatile uint32_t *)0xfe050384) +#define P_EE_AUDIO_TDMIN_C_MASK0 ((volatile uint32_t *)0xfe050388) +#define P_EE_AUDIO_TDMIN_C_MASK1 ((volatile uint32_t *)0xfe05038c) +#define P_EE_AUDIO_TDMIN_C_MASK2 ((volatile uint32_t *)0xfe050390) +#define P_EE_AUDIO_TDMIN_C_MASK3 ((volatile uint32_t *)0xfe050394) +#define P_EE_AUDIO_TDMIN_C_STAT ((volatile uint32_t *)0xfe050398) +#define P_EE_AUDIO_TDMIN_C_MUTE_VAL ((volatile uint32_t *)0xfe05039c) +#define P_EE_AUDIO_TDMIN_C_MUTE0 ((volatile uint32_t *)0xfe0503a0) +#define P_EE_AUDIO_TDMIN_C_MUTE1 ((volatile uint32_t *)0xfe0503a4) +#define P_EE_AUDIO_TDMIN_C_MUTE2 ((volatile uint32_t *)0xfe0503a8) +#define P_EE_AUDIO_TDMIN_C_MUTE3 ((volatile uint32_t *)0xfe0503ac) +#define P_EE_AUDIO_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe0503c0) +#define P_EE_AUDIO_TDMIN_LB_SWAP0 ((volatile uint32_t *)0xfe0503c4) +#define P_EE_AUDIO_TDMIN_LB_MASK0 ((volatile uint32_t *)0xfe0503c8) +#define P_EE_AUDIO_TDMIN_LB_MASK1 ((volatile uint32_t *)0xfe0503cc) +#define P_EE_AUDIO_TDMIN_LB_MASK2 ((volatile uint32_t *)0xfe0503d0) +#define P_EE_AUDIO_TDMIN_LB_MASK3 ((volatile uint32_t *)0xfe0503d4) +#define P_EE_AUDIO_TDMIN_LB_STAT ((volatile uint32_t *)0xfe0503d8) +#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0503dc) +#define P_EE_AUDIO_TDMIN_LB_MUTE0 ((volatile uint32_t *)0xfe0503e0) +#define P_EE_AUDIO_TDMIN_LB_MUTE1 ((volatile uint32_t *)0xfe0503e4) +#define P_EE_AUDIO_TDMIN_LB_MUTE2 ((volatile uint32_t *)0xfe0503e8) +#define P_EE_AUDIO_TDMIN_LB_MUTE3 ((volatile uint32_t *)0xfe0503ec) +#define P_EE_AUDIO_SPDIFIN_CTRL0 ((volatile uint32_t *)0xfe050400) +#define P_EE_AUDIO_SPDIFIN_CTRL1 ((volatile uint32_t *)0xfe050404) +#define P_EE_AUDIO_SPDIFIN_CTRL2 ((volatile uint32_t *)0xfe050408) +#define P_EE_AUDIO_SPDIFIN_CTRL3 ((volatile uint32_t *)0xfe05040c) +#define P_EE_AUDIO_SPDIFIN_CTRL4 ((volatile uint32_t *)0xfe050410) +#define P_EE_AUDIO_SPDIFIN_CTRL5 ((volatile uint32_t *)0xfe050414) +#define P_EE_AUDIO_SPDIFIN_CTRL6 ((volatile uint32_t *)0xfe050418) +#define P_EE_AUDIO_SPDIFIN_STAT0 ((volatile uint32_t *)0xfe05041c) +#define P_EE_AUDIO_SPDIFIN_STAT1 ((volatile uint32_t *)0xfe050420) +#define P_EE_AUDIO_SPDIFIN_STAT2 ((volatile uint32_t *)0xfe050424) +#define P_EE_AUDIO_SPDIFIN_MUTE_VAL ((volatile uint32_t *)0xfe050428) +#define P_EE_AUDIO_RESAMPLEA_CTRL0 ((volatile uint32_t *)0xfe050440) +#define P_EE_AUDIO_RESAMPLEA_CTRL1 ((volatile uint32_t *)0xfe050444) +#define P_EE_AUDIO_RESAMPLEA_CTRL2 ((volatile uint32_t *)0xfe050448) +#define P_EE_AUDIO_RESAMPLEA_CTRL3 ((volatile uint32_t *)0xfe05044c) +#define P_EE_AUDIO_RESAMPLEA_COEF0 ((volatile uint32_t *)0xfe050450) +#define P_EE_AUDIO_RESAMPLEA_COEF1 ((volatile uint32_t *)0xfe050454) +#define P_EE_AUDIO_RESAMPLEA_COEF2 ((volatile uint32_t *)0xfe050458) +#define P_EE_AUDIO_RESAMPLEA_COEF3 ((volatile uint32_t *)0xfe05045c) +#define P_EE_AUDIO_RESAMPLEA_COEF4 ((volatile uint32_t *)0xfe050460) +#define P_EE_AUDIO_RESAMPLEA_STATUS1 ((volatile uint32_t *)0xfe050464) +#define P_EE_AUDIO_SPDIFOUT_STAT ((volatile uint32_t *)0xfe050480) +#define P_EE_AUDIO_SPDIFOUT_GAIN0 ((volatile uint32_t *)0xfe050484) +#define P_EE_AUDIO_SPDIFOUT_GAIN1 ((volatile uint32_t *)0xfe050488) +#define P_EE_AUDIO_SPDIFOUT_CTRL0 ((volatile uint32_t *)0xfe05048c) +#define P_EE_AUDIO_SPDIFOUT_CTRL1 ((volatile uint32_t *)0xfe050490) +#define P_EE_AUDIO_SPDIFOUT_PREAMB ((volatile uint32_t *)0xfe050494) +#define P_EE_AUDIO_SPDIFOUT_SWAP ((volatile uint32_t *)0xfe050498) +#define P_EE_AUDIO_SPDIFOUT_CHSTS0 ((volatile uint32_t *)0xfe05049c) +#define P_EE_AUDIO_SPDIFOUT_CHSTS1 ((volatile uint32_t *)0xfe0504a0) +#define P_EE_AUDIO_SPDIFOUT_CHSTS2 ((volatile uint32_t *)0xfe0504a4) +#define P_EE_AUDIO_SPDIFOUT_CHSTS3 ((volatile uint32_t *)0xfe0504a8) +#define P_EE_AUDIO_SPDIFOUT_CHSTS4 ((volatile uint32_t *)0xfe0504ac) +#define P_EE_AUDIO_SPDIFOUT_CHSTS5 ((volatile uint32_t *)0xfe0504b0) +#define P_EE_AUDIO_SPDIFOUT_CHSTS6 ((volatile uint32_t *)0xfe0504b4) +#define P_EE_AUDIO_SPDIFOUT_CHSTS7 ((volatile uint32_t *)0xfe0504b8) +#define P_EE_AUDIO_SPDIFOUT_CHSTS8 ((volatile uint32_t *)0xfe0504bc) +#define P_EE_AUDIO_SPDIFOUT_CHSTS9 ((volatile uint32_t *)0xfe0504c0) +#define P_EE_AUDIO_SPDIFOUT_CHSTSA ((volatile uint32_t *)0xfe0504c4) +#define P_EE_AUDIO_SPDIFOUT_CHSTSB ((volatile uint32_t *)0xfe0504c8) +#define P_EE_AUDIO_SPDIFOUT_MUTE_VAL ((volatile uint32_t *)0xfe0504cc) +#define P_EE_AUDIO_TDMOUT_A_CTRL0 ((volatile uint32_t *)0xfe050500) +#define P_EE_AUDIO_TDMOUT_A_CTRL1 ((volatile uint32_t *)0xfe050504) +#define P_EE_AUDIO_TDMOUT_A_SWAP0 ((volatile uint32_t *)0xfe050508) +#define P_EE_AUDIO_TDMOUT_A_MASK0 ((volatile uint32_t *)0xfe05050c) +#define P_EE_AUDIO_TDMOUT_A_MASK1 ((volatile uint32_t *)0xfe050510) +#define P_EE_AUDIO_TDMOUT_A_MASK2 ((volatile uint32_t *)0xfe050514) +#define P_EE_AUDIO_TDMOUT_A_MASK3 ((volatile uint32_t *)0xfe050518) +#define P_EE_AUDIO_TDMOUT_A_STAT ((volatile uint32_t *)0xfe05051c) +#define P_EE_AUDIO_TDMOUT_A_GAIN0 ((volatile uint32_t *)0xfe050520) +#define P_EE_AUDIO_TDMOUT_A_GAIN1 ((volatile uint32_t *)0xfe050524) +#define P_EE_AUDIO_TDMOUT_A_MUTE_VAL ((volatile uint32_t *)0xfe050528) +#define P_EE_AUDIO_TDMOUT_A_MUTE0 ((volatile uint32_t *)0xfe05052c) +#define P_EE_AUDIO_TDMOUT_A_MUTE1 ((volatile uint32_t *)0xfe050530) +#define P_EE_AUDIO_TDMOUT_A_MUTE2 ((volatile uint32_t *)0xfe050534) +#define P_EE_AUDIO_TDMOUT_A_MUTE3 ((volatile uint32_t *)0xfe050538) +#define P_EE_AUDIO_TDMOUT_A_MASK_VAL ((volatile uint32_t *)0xfe05053c) +#define P_EE_AUDIO_TDMOUT_B_CTRL0 ((volatile uint32_t *)0xfe050540) +#define P_EE_AUDIO_TDMOUT_B_CTRL1 ((volatile uint32_t *)0xfe050544) +#define P_EE_AUDIO_TDMOUT_B_SWAP0 ((volatile uint32_t *)0xfe050548) +#define P_EE_AUDIO_TDMOUT_B_MASK0 ((volatile uint32_t *)0xfe05054c) +#define P_EE_AUDIO_TDMOUT_B_MASK1 ((volatile uint32_t *)0xfe050550) +#define P_EE_AUDIO_TDMOUT_B_MASK2 ((volatile uint32_t *)0xfe050554) +#define P_EE_AUDIO_TDMOUT_B_MASK3 ((volatile uint32_t *)0xfe050558) +#define P_EE_AUDIO_TDMOUT_B_STAT ((volatile uint32_t *)0xfe05055c) +#define P_EE_AUDIO_TDMOUT_B_GAIN0 ((volatile uint32_t *)0xfe050560) +#define P_EE_AUDIO_TDMOUT_B_GAIN1 ((volatile uint32_t *)0xfe050564) +#define P_EE_AUDIO_TDMOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe050568) +#define P_EE_AUDIO_TDMOUT_B_MUTE0 ((volatile uint32_t *)0xfe05056c) +#define P_EE_AUDIO_TDMOUT_B_MUTE1 ((volatile uint32_t *)0xfe050570) +#define P_EE_AUDIO_TDMOUT_B_MUTE2 ((volatile uint32_t *)0xfe050574) +#define P_EE_AUDIO_TDMOUT_B_MUTE3 ((volatile uint32_t *)0xfe050578) +#define P_EE_AUDIO_TDMOUT_B_MASK_VAL ((volatile uint32_t *)0xfe05057c) +#define P_EE_AUDIO_TDMOUT_C_CTRL0 ((volatile uint32_t *)0xfe050580) +#define P_EE_AUDIO_TDMOUT_C_CTRL1 ((volatile uint32_t *)0xfe050584) +#define P_EE_AUDIO_TDMOUT_C_SWAP0 ((volatile uint32_t *)0xfe050588) +#define P_EE_AUDIO_TDMOUT_C_MASK0 ((volatile uint32_t *)0xfe05058c) +#define P_EE_AUDIO_TDMOUT_C_MASK1 ((volatile uint32_t *)0xfe050590) +#define P_EE_AUDIO_TDMOUT_C_MASK2 ((volatile uint32_t *)0xfe050594) +#define P_EE_AUDIO_TDMOUT_C_MASK3 ((volatile uint32_t *)0xfe050598) +#define P_EE_AUDIO_TDMOUT_C_STAT ((volatile uint32_t *)0xfe05059c) +#define P_EE_AUDIO_TDMOUT_C_GAIN0 ((volatile uint32_t *)0xfe0505a0) +#define P_EE_AUDIO_TDMOUT_C_GAIN1 ((volatile uint32_t *)0xfe0505a4) +#define P_EE_AUDIO_TDMOUT_C_MUTE_VAL ((volatile uint32_t *)0xfe0505a8) +#define P_EE_AUDIO_TDMOUT_C_MUTE0 ((volatile uint32_t *)0xfe0505ac) +#define P_EE_AUDIO_TDMOUT_C_MUTE1 ((volatile uint32_t *)0xfe0505b0) +#define P_EE_AUDIO_TDMOUT_C_MUTE2 ((volatile uint32_t *)0xfe0505b4) +#define P_EE_AUDIO_TDMOUT_C_MUTE3 ((volatile uint32_t *)0xfe0505b8) +#define P_EE_AUDIO_TDMOUT_C_MASK_VAL ((volatile uint32_t *)0xfe0505bc) +//`define EE_AUDIO_POW_DET_CTRL0 10'h180 +//`define EE_AUDIO_POW_DET_CTRL1 10'h181 +//`define EE_AUDIO_POW_DET_TH_HI 10'h182 +//`define EE_AUDIO_POW_DET_TH_LO 10'h183 +//`define EE_AUDIO_POW_DET_VALUE 10'h184 +#define P_EE_AUDIO_SECURITY_CTRL0 ((volatile uint32_t *)0xfe050640) +#define P_EE_AUDIO_SECURITY_CTRL1 ((volatile uint32_t *)0xfe050644) +#define P_EE_AUDIO_SPDIFOUT_B_STAT ((volatile uint32_t *)0xfe050680) +#define P_EE_AUDIO_SPDIFOUT_B_GAIN0 ((volatile uint32_t *)0xfe050684) +#define P_EE_AUDIO_SPDIFOUT_B_GAIN1 ((volatile uint32_t *)0xfe050688) +#define P_EE_AUDIO_SPDIFOUT_B_CTRL0 ((volatile uint32_t *)0xfe05068c) +#define P_EE_AUDIO_SPDIFOUT_B_CTRL1 ((volatile uint32_t *)0xfe050690) +#define P_EE_AUDIO_SPDIFOUT_B_PREAMB ((volatile uint32_t *)0xfe050694) +#define P_EE_AUDIO_SPDIFOUT_B_SWAP ((volatile uint32_t *)0xfe050698) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 ((volatile uint32_t *)0xfe05069c) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 ((volatile uint32_t *)0xfe0506a0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 ((volatile uint32_t *)0xfe0506a4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 ((volatile uint32_t *)0xfe0506a8) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 ((volatile uint32_t *)0xfe0506ac) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 ((volatile uint32_t *)0xfe0506b0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 ((volatile uint32_t *)0xfe0506b4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 ((volatile uint32_t *)0xfe0506b8) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 ((volatile uint32_t *)0xfe0506bc) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 ((volatile uint32_t *)0xfe0506c0) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTSA ((volatile uint32_t *)0xfe0506c4) +#define P_EE_AUDIO_SPDIFOUT_B_CHSTSB ((volatile uint32_t *)0xfe0506c8) +#define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe0506cc) +#define P_EE_AUDIO_TORAM_CTRL0 ((volatile uint32_t *)0xfe050700) +#define P_EE_AUDIO_TORAM_CTRL1 ((volatile uint32_t *)0xfe050704) +#define P_EE_AUDIO_TORAM_START_ADDR ((volatile uint32_t *)0xfe050708) +#define P_EE_AUDIO_TORAM_FINISH_ADDR ((volatile uint32_t *)0xfe05070c) +#define P_EE_AUDIO_TORAM_INT_ADDR ((volatile uint32_t *)0xfe050710) +#define P_EE_AUDIO_TORAM_STATUS1 ((volatile uint32_t *)0xfe050714) +#define P_EE_AUDIO_TORAM_STATUS2 ((volatile uint32_t *)0xfe050718) +#define P_EE_AUDIO_TORAM_INIT_ADDR ((volatile uint32_t *)0xfe05071c) +#define P_EE_AUDIO_TOACODEC_CTRL0 ((volatile uint32_t *)0xfe050740) +#define P_EE_AUDIO_TOHDMITX_CTRL0 ((volatile uint32_t *)0xfe050744) +#define P_EE_AUDIO_TOVAD_CTRL0 ((volatile uint32_t *)0xfe050748) +#define P_EE_AUDIO_FRATV_CTRL0 ((volatile uint32_t *)0xfe05074c) +#define P_EE_AUDIO_RESAMPLEB_CTRL0 ((volatile uint32_t *)0xfe050780) +#define P_EE_AUDIO_RESAMPLEB_CTRL1 ((volatile uint32_t *)0xfe050784) +#define P_EE_AUDIO_RESAMPLEB_CTRL2 ((volatile uint32_t *)0xfe050788) +#define P_EE_AUDIO_RESAMPLEB_CTRL3 ((volatile uint32_t *)0xfe05078c) +#define P_EE_AUDIO_RESAMPLEB_COEF0 ((volatile uint32_t *)0xfe050790) +#define P_EE_AUDIO_RESAMPLEB_COEF1 ((volatile uint32_t *)0xfe050794) +#define P_EE_AUDIO_RESAMPLEB_COEF2 ((volatile uint32_t *)0xfe050798) +#define P_EE_AUDIO_RESAMPLEB_COEF3 ((volatile uint32_t *)0xfe05079c) +#define P_EE_AUDIO_RESAMPLEB_COEF4 ((volatile uint32_t *)0xfe0507a0) +#define P_EE_AUDIO_RESAMPLEB_STATUS1 ((volatile uint32_t *)0xfe0507a4) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL0 ((volatile uint32_t *)0xfe0507c0) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL1 ((volatile uint32_t *)0xfe0507c4) +#define P_EE_AUDIO_SPDIFIN_LB_CTRL6 ((volatile uint32_t *)0xfe0507d8) +#define P_EE_AUDIO_SPDIFIN_LB_STAT0 ((volatile uint32_t *)0xfe0507dc) +#define P_EE_AUDIO_SPDIFIN_LB_STAT1 ((volatile uint32_t *)0xfe0507e0) +#define P_EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0507e8) +#define P_EE_AUDIO_FRHDMIRX_CTRL0 ((volatile uint32_t *)0xfe050800) +#define P_EE_AUDIO_FRHDMIRX_CTRL1 ((volatile uint32_t *)0xfe050804) +#define P_EE_AUDIO_FRHDMIRX_CTRL2 ((volatile uint32_t *)0xfe050808) +#define P_EE_AUDIO_FRHDMIRX_CTRL3 ((volatile uint32_t *)0xfe05080c) +#define P_EE_AUDIO_FRHDMIRX_CTRL4 ((volatile uint32_t *)0xfe050810) +#define P_EE_AUDIO_FRHDMIRX_CTRL5 ((volatile uint32_t *)0xfe050814) +#define P_EE_AUDIO_FRHDMIRX_STAT0 ((volatile uint32_t *)0xfe050828) +#define P_EE_AUDIO_FRHDMIRX_STAT1 ((volatile uint32_t *)0xfe05082c) +#define P_EE_AUDIO_TODDR_D_CTRL0 ((volatile uint32_t *)0xfe050840) +#define P_EE_AUDIO_TODDR_D_CTRL1 ((volatile uint32_t *)0xfe050844) +#define P_EE_AUDIO_TODDR_D_START_ADDR ((volatile uint32_t *)0xfe050848) +#define P_EE_AUDIO_TODDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05084c) +#define P_EE_AUDIO_TODDR_D_INT_ADDR ((volatile uint32_t *)0xfe050850) +#define P_EE_AUDIO_TODDR_D_STATUS1 ((volatile uint32_t *)0xfe050854) +#define P_EE_AUDIO_TODDR_D_STATUS2 ((volatile uint32_t *)0xfe050858) +#define P_EE_AUDIO_TODDR_D_START_ADDRB ((volatile uint32_t *)0xfe05085c) +#define P_EE_AUDIO_TODDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe050860) +#define P_EE_AUDIO_TODDR_D_INIT_ADDR ((volatile uint32_t *)0xfe050864) +#define P_EE_AUDIO_TODDR_D_CTRL2 ((volatile uint32_t *)0xfe050868) +#define P_EE_AUDIO_FRDDR_D_CTRL0 ((volatile uint32_t *)0xfe050880) +#define P_EE_AUDIO_FRDDR_D_CTRL1 ((volatile uint32_t *)0xfe050884) +#define P_EE_AUDIO_FRDDR_D_START_ADDR ((volatile uint32_t *)0xfe050888) +#define P_EE_AUDIO_FRDDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05088c) +#define P_EE_AUDIO_FRDDR_D_INT_ADDR ((volatile uint32_t *)0xfe050890) +#define P_EE_AUDIO_FRDDR_D_STATUS1 ((volatile uint32_t *)0xfe050894) +#define P_EE_AUDIO_FRDDR_D_STATUS2 ((volatile uint32_t *)0xfe050898) +#define P_EE_AUDIO_FRDDR_D_START_ADDRB ((volatile uint32_t *)0xfe05089c) +#define P_EE_AUDIO_FRDDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe0508a0) +#define P_EE_AUDIO_FRDDR_D_INIT_ADDR ((volatile uint32_t *)0xfe0508a4) +#define P_EE_AUDIO_FRDDR_D_CTRL2 ((volatile uint32_t *)0xfe0508a8) +#define P_EE_AUDIO_LB_B_CTRL0 ((volatile uint32_t *)0xfe0508c0) +#define P_EE_AUDIO_LB_B_CTRL1 ((volatile uint32_t *)0xfe0508c4) +#define P_EE_AUDIO_LB_B_CTRL2 ((volatile uint32_t *)0xfe0508c8) +#define P_EE_AUDIO_LB_B_CTRL3 ((volatile uint32_t *)0xfe0508cc) +#define P_EE_AUDIO_LB_B_DAT_CH_ID0 ((volatile uint32_t *)0xfe0508d0) +#define P_EE_AUDIO_LB_B_DAT_CH_ID1 ((volatile uint32_t *)0xfe0508d4) +#define P_EE_AUDIO_LB_B_DAT_CH_ID2 ((volatile uint32_t *)0xfe0508d8) +#define P_EE_AUDIO_LB_B_DAT_CH_ID3 ((volatile uint32_t *)0xfe0508dc) +#define P_EE_AUDIO_LB_B_LB_CH_ID0 ((volatile uint32_t *)0xfe0508e0) +#define P_EE_AUDIO_LB_B_LB_CH_ID1 ((volatile uint32_t *)0xfe0508e4) +#define P_EE_AUDIO_LB_B_LB_CH_ID2 ((volatile uint32_t *)0xfe0508e8) +#define P_EE_AUDIO_LB_B_LB_CH_ID3 ((volatile uint32_t *)0xfe0508ec) +#define P_EE_AUDIO_LB_B_STS ((volatile uint32_t *)0xfe0508f0) +#define P_EE_AUDIO_TODDR_E_CTRL0 ((volatile uint32_t *)0xfe050900) +#define P_EE_AUDIO_TODDR_E_CTRL1 ((volatile uint32_t *)0xfe050904) +#define P_EE_AUDIO_TODDR_E_START_ADDR ((volatile uint32_t *)0xfe050908) +#define P_EE_AUDIO_TODDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05090c) +#define P_EE_AUDIO_TODDR_E_INT_ADDR ((volatile uint32_t *)0xfe050910) +#define P_EE_AUDIO_TODDR_E_STATUS1 ((volatile uint32_t *)0xfe050914) +#define P_EE_AUDIO_TODDR_E_STATUS2 ((volatile uint32_t *)0xfe050918) +#define P_EE_AUDIO_TODDR_E_START_ADDRB ((volatile uint32_t *)0xfe05091c) +#define P_EE_AUDIO_TODDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050920) +#define P_EE_AUDIO_TODDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050924) +#define P_EE_AUDIO_TODDR_E_CTRL2 ((volatile uint32_t *)0xfe050928) +#define P_EE_AUDIO_FRDDR_E_CTRL0 ((volatile uint32_t *)0xfe050940) +#define P_EE_AUDIO_FRDDR_E_CTRL1 ((volatile uint32_t *)0xfe050944) +#define P_EE_AUDIO_FRDDR_E_START_ADDR ((volatile uint32_t *)0xfe050948) +#define P_EE_AUDIO_FRDDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05094c) +#define P_EE_AUDIO_FRDDR_E_INT_ADDR ((volatile uint32_t *)0xfe050950) +#define P_EE_AUDIO_FRDDR_E_STATUS1 ((volatile uint32_t *)0xfe050954) +#define P_EE_AUDIO_FRDDR_E_STATUS2 ((volatile uint32_t *)0xfe050958) +#define P_EE_AUDIO_FRDDR_E_START_ADDRB ((volatile uint32_t *)0xfe05095c) +#define P_EE_AUDIO_FRDDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050960) +#define P_EE_AUDIO_FRDDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050964) +#define P_EE_AUDIO_FRDDR_E_CTRL2 ((volatile uint32_t *)0xfe050968) +#define P_EE_AUDIO_TDMIN_A_SWAP1 ((volatile uint32_t *)0xfe050980) +#define P_EE_AUDIO_TDMIN_A_MASK4 ((volatile uint32_t *)0xfe050984) +#define P_EE_AUDIO_TDMIN_A_MASK5 ((volatile uint32_t *)0xfe050988) +#define P_EE_AUDIO_TDMIN_A_MASK6 ((volatile uint32_t *)0xfe05098c) +#define P_EE_AUDIO_TDMIN_A_MASK7 ((volatile uint32_t *)0xfe050990) +#define P_EE_AUDIO_TDMIN_A_MUTE4 ((volatile uint32_t *)0xfe050994) +#define P_EE_AUDIO_TDMIN_A_MUTE5 ((volatile uint32_t *)0xfe050998) +#define P_EE_AUDIO_TDMIN_A_MUTE6 ((volatile uint32_t *)0xfe05099c) +#define P_EE_AUDIO_TDMIN_A_MUTE7 ((volatile uint32_t *)0xfe0509a0) +#define P_EE_AUDIO_TDMIN_B_SWAP1 ((volatile uint32_t *)0xfe0509c0) +#define P_EE_AUDIO_TDMIN_B_MASK4 ((volatile uint32_t *)0xfe0509c4) +#define P_EE_AUDIO_TDMIN_B_MASK5 ((volatile uint32_t *)0xfe0509c8) +#define P_EE_AUDIO_TDMIN_B_MASK6 ((volatile uint32_t *)0xfe0509cc) +#define P_EE_AUDIO_TDMIN_B_MASK7 ((volatile uint32_t *)0xfe0509d0) +#define P_EE_AUDIO_TDMIN_B_MUTE4 ((volatile uint32_t *)0xfe0509d4) +#define P_EE_AUDIO_TDMIN_B_MUTE5 ((volatile uint32_t *)0xfe0509d8) +#define P_EE_AUDIO_TDMIN_B_MUTE6 ((volatile uint32_t *)0xfe0509dc) +#define P_EE_AUDIO_TDMIN_B_MUTE7 ((volatile uint32_t *)0xfe0509e0) +#define P_EE_AUDIO_TDMIN_C_SWAP1 ((volatile uint32_t *)0xfe050a00) +#define P_EE_AUDIO_TDMIN_C_MASK4 ((volatile uint32_t *)0xfe050a04) +#define P_EE_AUDIO_TDMIN_C_MASK5 ((volatile uint32_t *)0xfe050a08) +#define P_EE_AUDIO_TDMIN_C_MASK6 ((volatile uint32_t *)0xfe050a0c) +#define P_EE_AUDIO_TDMIN_C_MASK7 ((volatile uint32_t *)0xfe050a10) +#define P_EE_AUDIO_TDMIN_C_MUTE4 ((volatile uint32_t *)0xfe050a14) +#define P_EE_AUDIO_TDMIN_C_MUTE5 ((volatile uint32_t *)0xfe050a18) +#define P_EE_AUDIO_TDMIN_C_MUTE6 ((volatile uint32_t *)0xfe050a1c) +#define P_EE_AUDIO_TDMIN_C_MUTE7 ((volatile uint32_t *)0xfe050a20) +#define P_EE_AUDIO_TDMIN_LB_SWAP1 ((volatile uint32_t *)0xfe050a40) +#define P_EE_AUDIO_TDMIN_LB_MASK4 ((volatile uint32_t *)0xfe050a44) +#define P_EE_AUDIO_TDMIN_LB_MASK5 ((volatile uint32_t *)0xfe050a48) +#define P_EE_AUDIO_TDMIN_LB_MASK6 ((volatile uint32_t *)0xfe050a4c) +#define P_EE_AUDIO_TDMIN_LB_MASK7 ((volatile uint32_t *)0xfe050a50) +#define P_EE_AUDIO_TDMIN_LB_MUTE4 ((volatile uint32_t *)0xfe050a54) +#define P_EE_AUDIO_TDMIN_LB_MUTE5 ((volatile uint32_t *)0xfe050a58) +#define P_EE_AUDIO_TDMIN_LB_MUTE6 ((volatile uint32_t *)0xfe050a5c) +#define P_EE_AUDIO_TDMIN_LB_MUTE7 ((volatile uint32_t *)0xfe050a60) +#define P_EE_AUDIO_TDMOUT_A_CTRL2 ((volatile uint32_t *)0xfe050a80) +#define P_EE_AUDIO_TDMOUT_A_SWAP1 ((volatile uint32_t *)0xfe050a84) +#define P_EE_AUDIO_TDMOUT_A_GAIN2 ((volatile uint32_t *)0xfe050a88) +#define P_EE_AUDIO_TDMOUT_A_GAIN3 ((volatile uint32_t *)0xfe050a8c) +#define P_EE_AUDIO_TDMOUT_A_MASK4 ((volatile uint32_t *)0xfe050a90) +#define P_EE_AUDIO_TDMOUT_A_MASK5 ((volatile uint32_t *)0xfe050a94) +#define P_EE_AUDIO_TDMOUT_A_MASK6 ((volatile uint32_t *)0xfe050a98) +#define P_EE_AUDIO_TDMOUT_A_MASK7 ((volatile uint32_t *)0xfe050a9c) +#define P_EE_AUDIO_TDMOUT_A_MUTE4 ((volatile uint32_t *)0xfe050aa0) +#define P_EE_AUDIO_TDMOUT_A_MUTE5 ((volatile uint32_t *)0xfe050aa4) +#define P_EE_AUDIO_TDMOUT_A_MUTE6 ((volatile uint32_t *)0xfe050aa8) +#define P_EE_AUDIO_TDMOUT_A_MUTE7 ((volatile uint32_t *)0xfe050aac) +#define P_EE_AUDIO_TDMOUT_B_CTRL2 ((volatile uint32_t *)0xfe050ac0) +#define P_EE_AUDIO_TDMOUT_B_SWAP1 ((volatile uint32_t *)0xfe050ac4) +#define P_EE_AUDIO_TDMOUT_B_GAIN2 ((volatile uint32_t *)0xfe050ac8) +#define P_EE_AUDIO_TDMOUT_B_GAIN3 ((volatile uint32_t *)0xfe050acc) +#define P_EE_AUDIO_TDMOUT_B_MASK4 ((volatile uint32_t *)0xfe050ad0) +#define P_EE_AUDIO_TDMOUT_B_MASK5 ((volatile uint32_t *)0xfe050ad4) +#define P_EE_AUDIO_TDMOUT_B_MASK6 ((volatile uint32_t *)0xfe050ad8) +#define P_EE_AUDIO_TDMOUT_B_MASK7 ((volatile uint32_t *)0xfe050adc) +#define P_EE_AUDIO_TDMOUT_B_MUTE4 ((volatile uint32_t *)0xfe050ae0) +#define P_EE_AUDIO_TDMOUT_B_MUTE5 ((volatile uint32_t *)0xfe050ae4) +#define P_EE_AUDIO_TDMOUT_B_MUTE6 ((volatile uint32_t *)0xfe050ae8) +#define P_EE_AUDIO_TDMOUT_B_MUTE7 ((volatile uint32_t *)0xfe050aec) +#define P_EE_AUDIO_TDMOUT_C_CTRL2 ((volatile uint32_t *)0xfe050b00) +#define P_EE_AUDIO_TDMOUT_C_SWAP1 ((volatile uint32_t *)0xfe050b04) +#define P_EE_AUDIO_TDMOUT_C_GAIN2 ((volatile uint32_t *)0xfe050b08) +#define P_EE_AUDIO_TDMOUT_C_GAIN3 ((volatile uint32_t *)0xfe050b0c) +#define P_EE_AUDIO_TDMOUT_C_MASK4 ((volatile uint32_t *)0xfe050b10) +#define P_EE_AUDIO_TDMOUT_C_MASK5 ((volatile uint32_t *)0xfe050b14) +#define P_EE_AUDIO_TDMOUT_C_MASK6 ((volatile uint32_t *)0xfe050b18) +#define P_EE_AUDIO_TDMOUT_C_MASK7 ((volatile uint32_t *)0xfe050b1c) +#define P_EE_AUDIO_TDMOUT_C_MUTE4 ((volatile uint32_t *)0xfe050b20) +#define P_EE_AUDIO_TDMOUT_C_MUTE5 ((volatile uint32_t *)0xfe050b24) +#define P_EE_AUDIO_TDMOUT_C_MUTE6 ((volatile uint32_t *)0xfe050b28) +#define P_EE_AUDIO_TDMOUT_C_MUTE7 ((volatile uint32_t *)0xfe050b2c) +//======================================================================== +// PDM - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051000 +// ----------------------------------------------- +#define P_PDM_CTRL ((volatile uint32_t *)0xfe051000) +//bit 31: PDM enable. +//bit 30: invert the PDM_DCLK. +//bit 29: output mode: 1: 24bits. 0: 32 bits. +//bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode. +//bit 27~9: not used. +//bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO. +//bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode. +//bit 7:0. PDM channel enable. each bit for one channel. +#define P_PDM_HCIC_CTRL1 ((volatile uint32_t *)0xfe051004) +//bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output. +//bit 29:24. hcic final gain shift parameter. +//bit 23:16 hcic final gain multiplier. +//bit 8:4 hcic down sample rate. +//bit 3:0 hcic stage number. must be between 3 to 9. +#define P_PDM_HCIC_CTRL2 ((volatile uint32_t *)0xfe051008) +//Not used. +#define P_PDM_F1_CTRL ((volatile uint32_t *)0xfe05100c) +//bit 31 . filter 1 enable. +//bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26] +// 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26] +// 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26]. +//bit 15:12. filter 1 down sample rate. +//bit 8:0. filter 1 stage number. +#define P_PDM_F2_CTRL ((volatile uint32_t *)0xfe051010) +//bit 31 . filter 2 enable. +//bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. +//bit 15:12. filter 2 down sample rate. +//bit 8:0. filter 2 stage number. +#define P_PDM_F3_CTRL ((volatile uint32_t *)0xfe051014) +//bit 31 . filter 3 enable. +//bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. +//bit 15:12. filter 3 down sample rate. +//bit 8:0. filter 3 stage number. +#define P_PDM_HPF_CTRL ((volatile uint32_t *)0xfe051018) +//bit 31 High pass filter enable. +//bit 20:16 high pass filter shift steps. 6~19 steps. +//bit 15:0 high pass filter output factor. +#define P_PDM_CHAN_CTRL ((volatile uint32_t *)0xfe05101c) +//bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK. +//bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK. +//bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK. +//bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK. +#define P_PDM_CHAN_CTRL1 ((volatile uint32_t *)0xfe051020) +//bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK. +//bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK. +//bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK. +//bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK. +#define P_PDM_COEFF_ADDR ((volatile uint32_t *)0xfe051024) +// address of the write/read of coeff data. +#define P_PDM_COEFF_DATA ((volatile uint32_t *)0xfe051028) +//write/read data to coeff memory. +#define P_PDM_CLKG_CTRL ((volatile uint32_t *)0xfe05102c) +// auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating. +//31:7 not used. +//bit 6 filt_ctrl module auto clock gating control. +//bit 5 sinc fifo module auto clock gating control. +//bit 4 filter module auto clock gating control. +//bit 3 apb module auto clock gating control. +//bit 2 coeff memory module auto clock gating control. +//bit 1 each channel module auto clock gating control. +//bit 0 cts_pdm_clk auto clock gating control. +#define P_PDM_STS ((volatile uint32_t *)0xfe051030) +//bit 1 HPF filter output overflow. means the PCLK is too slow. +//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function. +#define P_PDM_MUTE_VALUE ((volatile uint32_t *)0xfe051034) +#define P_PDM_MASK_NUM ((volatile uint32_t *)0xfe051038) +//======================================================================== +// EQ DRC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe052000 +// ----------------------------------------------- +#define P_AED_COEF_RAM_CNTL ((volatile uint32_t *)0xfe052000) +#define P_AED_COEF_RAM_DATA ((volatile uint32_t *)0xfe052004) +#define P_AED_EQ_EN ((volatile uint32_t *)0xfe052008) +#define P_AED_EQ_TAP_CNTL ((volatile uint32_t *)0xfe05200c) +#define P_AED_EQ_VOLUME ((volatile uint32_t *)0xfe052010) +#define P_AED_EQ_VOLUME_SLEW_CNT ((volatile uint32_t *)0xfe052014) +#define P_AED_MUTE ((volatile uint32_t *)0xfe052018) +#define P_AED_DRC_CNTL ((volatile uint32_t *)0xfe05201c) +#define P_AED_DRC_RMS_COEF0 ((volatile uint32_t *)0xfe052020) +#define P_AED_DRC_RMS_COEF1 ((volatile uint32_t *)0xfe052024) +#define P_AED_DRC_THD0 ((volatile uint32_t *)0xfe052028) +#define P_AED_DRC_THD1 ((volatile uint32_t *)0xfe05202c) +#define P_AED_DRC_THD2 ((volatile uint32_t *)0xfe052030) +#define P_AED_DRC_THD3 ((volatile uint32_t *)0xfe052034) +#define P_AED_DRC_THD4 ((volatile uint32_t *)0xfe052038) +#define P_AED_DRC_K0 ((volatile uint32_t *)0xfe05203c) +#define P_AED_DRC_K1 ((volatile uint32_t *)0xfe052040) +#define P_AED_DRC_K2 ((volatile uint32_t *)0xfe052044) +#define P_AED_DRC_K3 ((volatile uint32_t *)0xfe052048) +#define P_AED_DRC_K4 ((volatile uint32_t *)0xfe05204c) +#define P_AED_DRC_K5 ((volatile uint32_t *)0xfe052050) +#define P_AED_DRC_THD_OUT0 ((volatile uint32_t *)0xfe052054) +#define P_AED_DRC_THD_OUT1 ((volatile uint32_t *)0xfe052058) +#define P_AED_DRC_THD_OUT2 ((volatile uint32_t *)0xfe05205c) +#define P_AED_DRC_THD_OUT3 ((volatile uint32_t *)0xfe052060) +#define P_AED_DRC_OFFSET ((volatile uint32_t *)0xfe052064) +#define P_AED_DRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe052068) +#define P_AED_DRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe05206c) +#define P_AED_DRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052070) +#define P_AED_DRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052074) +#define P_AED_DRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052078) +#define P_AED_DRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05207c) +#define P_AED_DRC_RELEASE_COEF30 ((volatile uint32_t *)0xfe052080) +#define P_AED_DRC_RELEASE_COEF31 ((volatile uint32_t *)0xfe052084) +#define P_AED_DRC_RELEASE_COEF40 ((volatile uint32_t *)0xfe052088) +#define P_AED_DRC_RELEASE_COEF41 ((volatile uint32_t *)0xfe05208c) +#define P_AED_DRC_RELEASE_COEF50 ((volatile uint32_t *)0xfe052090) +#define P_AED_DRC_RELEASE_COEF51 ((volatile uint32_t *)0xfe052094) +#define P_AED_DRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe052098) +#define P_AED_DRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe05209c) +#define P_AED_DRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe0520a0) +#define P_AED_DRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe0520a4) +#define P_AED_DRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe0520a8) +#define P_AED_DRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe0520ac) +#define P_AED_DRC_ATTACK_COEF30 ((volatile uint32_t *)0xfe0520b0) +#define P_AED_DRC_ATTACK_COEF31 ((volatile uint32_t *)0xfe0520b4) +#define P_AED_DRC_ATTACK_COEF40 ((volatile uint32_t *)0xfe0520b8) +#define P_AED_DRC_ATTACK_COEF41 ((volatile uint32_t *)0xfe0520bc) +#define P_AED_DRC_ATTACK_COEF50 ((volatile uint32_t *)0xfe0520c0) +#define P_AED_DRC_ATTACK_COEF51 ((volatile uint32_t *)0xfe0520c4) +#define P_AED_DRC_LOOPBACK_CNTL ((volatile uint32_t *)0xfe0520c8) +#define P_AED_MDRC_CNTL ((volatile uint32_t *)0xfe0520cc) +#define P_AED_MDRC_RMS_COEF00 ((volatile uint32_t *)0xfe0520d0) +#define P_AED_MDRC_RMS_COEF01 ((volatile uint32_t *)0xfe0520d4) +#define P_AED_MDRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe0520d8) +#define P_AED_MDRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe0520dc) +#define P_AED_MDRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe0520e0) +#define P_AED_MDRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe0520e4) +#define P_AED_MDRC_THD0 ((volatile uint32_t *)0xfe0520e8) +#define P_AED_MDRC_K0 ((volatile uint32_t *)0xfe0520ec) +#define P_AED_MDRC_LOW_GAIN ((volatile uint32_t *)0xfe0520f0) +#define P_AED_MDRC_OFFSET0 ((volatile uint32_t *)0xfe0520f4) +#define P_AED_MDRC_RMS_COEF10 ((volatile uint32_t *)0xfe0520f8) +#define P_AED_MDRC_RMS_COEF11 ((volatile uint32_t *)0xfe0520fc) +#define P_AED_MDRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052100) +#define P_AED_MDRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052104) +#define P_AED_MDRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe052108) +#define P_AED_MDRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe05210c) +#define P_AED_MDRC_THD1 ((volatile uint32_t *)0xfe052110) +#define P_AED_MDRC_K1 ((volatile uint32_t *)0xfe052114) +#define P_AED_MDRC_OFFSET1 ((volatile uint32_t *)0xfe052118) +#define P_AED_MDRC_MID_GAIN ((volatile uint32_t *)0xfe05211c) +#define P_AED_MDRC_RMS_COEF20 ((volatile uint32_t *)0xfe052120) +#define P_AED_MDRC_RMS_COEF21 ((volatile uint32_t *)0xfe052124) +#define P_AED_MDRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052128) +#define P_AED_MDRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05212c) +#define P_AED_MDRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe052130) +#define P_AED_MDRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe052134) +#define P_AED_MDRC_THD2 ((volatile uint32_t *)0xfe052138) +#define P_AED_MDRC_K2 ((volatile uint32_t *)0xfe05213c) +#define P_AED_MDRC_OFFSET2 ((volatile uint32_t *)0xfe052140) +#define P_AED_MDRC_HIGH_GAIN ((volatile uint32_t *)0xfe052144) +#define P_AED_ED_CNTL ((volatile uint32_t *)0xfe052148) +#define P_AED_DC_EN ((volatile uint32_t *)0xfe05214c) +#define P_AED_ND_LOW_THD ((volatile uint32_t *)0xfe052150) +#define P_AED_ND_HIGH_THD ((volatile uint32_t *)0xfe052154) +#define P_AED_ND_CNT_THD ((volatile uint32_t *)0xfe052158) +#define P_AED_ND_SUM_NUM ((volatile uint32_t *)0xfe05215c) +#define P_AED_ND_CZ_NUM ((volatile uint32_t *)0xfe052160) +#define P_AED_ND_SUM_THD0 ((volatile uint32_t *)0xfe052164) +#define P_AED_ND_SUM_THD1 ((volatile uint32_t *)0xfe052168) +#define P_AED_ND_CZ_THD0 ((volatile uint32_t *)0xfe05216c) +#define P_AED_ND_CZ_THD1 ((volatile uint32_t *)0xfe052170) +#define P_AED_ND_COND_CNTL ((volatile uint32_t *)0xfe052174) +#define P_AED_ND_RELEASE_COEF0 ((volatile uint32_t *)0xfe052178) +#define P_AED_ND_RELEASE_COEF1 ((volatile uint32_t *)0xfe05217c) +#define P_AED_ND_ATTACK_COEF0 ((volatile uint32_t *)0xfe052180) +#define P_AED_ND_ATTACK_COEF1 ((volatile uint32_t *)0xfe052184) +#define P_AED_ND_CNTL ((volatile uint32_t *)0xfe052188) +#define P_AED_MIX0_LL ((volatile uint32_t *)0xfe05218c) +#define P_AED_MIX0_RL ((volatile uint32_t *)0xfe052190) +#define P_AED_MIX0_LR ((volatile uint32_t *)0xfe052194) +#define P_AED_MIX0_RR ((volatile uint32_t *)0xfe052198) +#define P_AED_CLIP_THD ((volatile uint32_t *)0xfe05219c) +#define P_AED_CH1_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a0) +#define P_AED_CH2_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a4) +#define P_AED_CH1_ND_CZ_OUT ((volatile uint32_t *)0xfe0521a8) +#define P_AED_CH2_ND_CZ_OUT ((volatile uint32_t *)0xfe0521ac) +#define P_AED_NOISE_STATUS ((volatile uint32_t *)0xfe0521b0) +#define P_AED_POW_CURRENT_S0 ((volatile uint32_t *)0xfe0521b4) +#define P_AED_POW_CURRENT_S1 ((volatile uint32_t *)0xfe0521b8) +#define P_AED_POW_CURRENT_S2 ((volatile uint32_t *)0xfe0521bc) +#define P_AED_POW_OUT0 ((volatile uint32_t *)0xfe0521c0) +#define P_AED_POW_OUT1 ((volatile uint32_t *)0xfe0521c4) +#define P_AED_POW_OUT2 ((volatile uint32_t *)0xfe0521c8) +#define P_AED_POW_ADJ_INDEX0 ((volatile uint32_t *)0xfe0521cc) +#define P_AED_POW_ADJ_INDEX1 ((volatile uint32_t *)0xfe0521d0) +#define P_AED_POW_ADJ_INDEX2 ((volatile uint32_t *)0xfe0521d4) +#define P_AED_DRC_GAIN_INDEX0 ((volatile uint32_t *)0xfe0521d8) +#define P_AED_DRC_GAIN_INDEX1 ((volatile uint32_t *)0xfe0521dc) +#define P_AED_DRC_GAIN_INDEX2 ((volatile uint32_t *)0xfe0521e0) +#define P_AED_CH1_VOLUME_STATE ((volatile uint32_t *)0xfe0521e4) +#define P_AED_CH2_VOLUME_STATE ((volatile uint32_t *)0xfe0521e8) +#define P_AED_CH1_VOLUME_GAIN ((volatile uint32_t *)0xfe0521ec) +#define P_AED_CH2_VOLUME_GAIN ((volatile uint32_t *)0xfe0521f0) +#define P_AED_FULL_POW_CURRENT ((volatile uint32_t *)0xfe0521f4) +#define P_AED_FULL_POW_OUT ((volatile uint32_t *)0xfe0521f8) +#define P_AED_FULL_POW_ADJ ((volatile uint32_t *)0xfe0521fc) +#define P_AED_FULL_DRC_GAIN ((volatile uint32_t *)0xfe052200) +#define P_AED_MASTER_VOLUME_STATE ((volatile uint32_t *)0xfe052204) +#define P_AED_MASTER_VOLUME_GAIN ((volatile uint32_t *)0xfe052208) +#define P_AED_TOP_CTL0 ((volatile uint32_t *)0xfe05220c) +#define P_AED_TOP_CTL1 ((volatile uint32_t *)0xfe052210) +#define P_AED_TOP_CTL2 ((volatile uint32_t *)0xfe052214) +//======================================================================== +// AUDIO locker - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051400 +// ----------------------------------------------- +#define P_AUD_LOCK_EN ((volatile uint32_t *)0xfe051400) +#define P_AUD_LOCK_SW_RESET ((volatile uint32_t *)0xfe051404) +#define P_AUD_LOCK_SW_LATCH ((volatile uint32_t *)0xfe051408) +#define P_AUD_LOCK_HW_LATCH ((volatile uint32_t *)0xfe05140c) +#define P_AUD_LOCK_REFCLK_SRC ((volatile uint32_t *)0xfe051410) +#define P_AUD_LOCK_REFCLK_LAT_INT ((volatile uint32_t *)0xfe051414) +#define P_AUD_LOCK_IMCLK_LAT_INT ((volatile uint32_t *)0xfe051418) +#define P_AUD_LOCK_OMCLK_LAT_INT ((volatile uint32_t *)0xfe05141c) +#define P_AUD_LOCK_REFCLK_DS_INT ((volatile uint32_t *)0xfe051420) +#define P_AUD_LOCK_IMCLK_DS_INT ((volatile uint32_t *)0xfe051424) +#define P_AUD_LOCK_OMCLK_DS_INT ((volatile uint32_t *)0xfe051428) +#define P_AUD_LOCK_INT_CLR ((volatile uint32_t *)0xfe05142c) +#define P_AUD_LOCK_GCLK_CTRL ((volatile uint32_t *)0xfe051430) +#define P_AUD_LOCK_INT_CTRL ((volatile uint32_t *)0xfe051434) +#define P_RO_REF2IMCLK_CNT_L ((volatile uint32_t *)0xfe051440) +#define P_RO_REF2IMCLK_CNT_H ((volatile uint32_t *)0xfe051444) +#define P_RO_REF2OMCLK_CNT_L ((volatile uint32_t *)0xfe051448) +#define P_RO_REF2OMCLK_CNT_H ((volatile uint32_t *)0xfe05144c) +#define P_RO_IMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051450) +#define P_RO_IMCLK2REF_CNT_H ((volatile uint32_t *)0xfe051454) +#define P_RO_OMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051458) +#define P_RO_OMCLK2REF_CNT_H ((volatile uint32_t *)0xfe05145c) +#define P_RO_REFCLK_PKG_CNT ((volatile uint32_t *)0xfe051460) +#define P_RO_IMCLK_PKG_CNT ((volatile uint32_t *)0xfe051464) +#define P_RO_OMCLK_PKG_CNT ((volatile uint32_t *)0xfe051468) +#define P_RO_AUD_LOCK_INT_STATUS ((volatile uint32_t *)0xfe05146c) +//======================================================================== +// AUDIO VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051800 +// ----------------------------------------------- +// +// Reading file: VAD_REG.h +// +#define P_VAD_TOP_CTRL0 ((volatile uint32_t *)0xfe051800) +#define P_VAD_TOP_CTRL1 ((volatile uint32_t *)0xfe051804) +#define P_VAD_TOP_CTRL2 ((volatile uint32_t *)0xfe051808) +#define P_VAD_FIR_CTRL ((volatile uint32_t *)0xfe05180c) +#define P_VAD_FIR_EMP ((volatile uint32_t *)0xfe051810) +#define P_VAD_FIR_COEF0 ((volatile uint32_t *)0xfe051814) +#define P_VAD_FIR_COEF1 ((volatile uint32_t *)0xfe051818) +#define P_VAD_FIR_COEF2 ((volatile uint32_t *)0xfe05181c) +#define P_VAD_FIR_COEF3 ((volatile uint32_t *)0xfe051820) +#define P_VAD_FIR_COEF4 ((volatile uint32_t *)0xfe051824) +#define P_VAD_FIR_COEF5 ((volatile uint32_t *)0xfe051828) +#define P_VAD_FIR_COEF6 ((volatile uint32_t *)0xfe05182c) +#define P_VAD_FIR_COEF7 ((volatile uint32_t *)0xfe051830) +#define P_VAD_FIR_COEF8 ((volatile uint32_t *)0xfe051834) +#define P_VAD_FIR_COEF9 ((volatile uint32_t *)0xfe051838) +#define P_VAD_FIR_COEF10 ((volatile uint32_t *)0xfe05183c) +#define P_VAD_FIR_COEF11 ((volatile uint32_t *)0xfe051840) +#define P_VAD_FIR_COEF12 ((volatile uint32_t *)0xfe051844) +#define P_VAD_FRAME_CTRL0 ((volatile uint32_t *)0xfe051848) +#define P_VAD_FRAME_CTRL1 ((volatile uint32_t *)0xfe05184c) +#define P_VAD_FRAME_CTRL2 ((volatile uint32_t *)0xfe051850) +#define P_VAD_CEP_CTRL0 ((volatile uint32_t *)0xfe051854) +#define P_VAD_CEP_CTRL1 ((volatile uint32_t *)0xfe051858) +#define P_VAD_CEP_CTRL2 ((volatile uint32_t *)0xfe05185c) +#define P_VAD_CEP_CTRL3 ((volatile uint32_t *)0xfe051860) +#define P_VAD_CEP_CTRL4 ((volatile uint32_t *)0xfe051864) +#define P_VAD_CEP_CTRL5 ((volatile uint32_t *)0xfe051868) +#define P_VAD_DEC_CTRL ((volatile uint32_t *)0xfe05186c) +#define P_VAD_TOP_STS0 ((volatile uint32_t *)0xfe051870) +#define P_VAD_TOP_STS1 ((volatile uint32_t *)0xfe051874) +#define P_VAD_TOP_STS2 ((volatile uint32_t *)0xfe051878) +#define P_VAD_FIR_STS0 ((volatile uint32_t *)0xfe05187c) +#define P_VAD_FIR_STS1 ((volatile uint32_t *)0xfe051880) +#define P_VAD_POW_STS0 ((volatile uint32_t *)0xfe051884) +#define P_VAD_POW_STS1 ((volatile uint32_t *)0xfe051888) +#define P_VAD_POW_STS2 ((volatile uint32_t *)0xfe05188c) +#define P_VAD_FFT_STS0 ((volatile uint32_t *)0xfe051890) +#define P_VAD_FFT_STS1 ((volatile uint32_t *)0xfe051894) +#define P_VAD_SPE_STS0 ((volatile uint32_t *)0xfe051898) +#define P_VAD_SPE_STS1 ((volatile uint32_t *)0xfe05189c) +#define P_VAD_SPE_STS2 ((volatile uint32_t *)0xfe0518a0) +#define P_VAD_SPE_STS3 ((volatile uint32_t *)0xfe0518a4) +#define P_VAD_DEC_STS0 ((volatile uint32_t *)0xfe0518a8) +#define P_VAD_DEC_STS1 ((volatile uint32_t *)0xfe0518ac) +#define P_VAD_LUT_CTRL ((volatile uint32_t *)0xfe0518b0) +#define P_VAD_LUT_WR ((volatile uint32_t *)0xfe0518b4) +#define P_VAD_LUT_RD ((volatile uint32_t *)0xfe0518b8) +#define P_VAD_IN_SEL0 ((volatile uint32_t *)0xfe0518bc) +#define P_VAD_IN_SEL1 ((volatile uint32_t *)0xfe0518c0) +#define P_VAD_TO_DDR ((volatile uint32_t *)0xfe0518c4) +// +// Closing file: VAD_REG.h +// +//======================================================================== +// AUDIO RESAMPLEA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051c00 +// ----------------------------------------------- +// +// Reading file: RESAMPLE.h +// +#define P_AUDIO_RSAMP_CTRL0 ((volatile uint32_t *)0xfe051c00) +//Bit 31:3 reserved +//Bit 2 reg_lock_rst //unsigned , default =0; +//Bit 1 reg_rsamp_rst //unsigned , default =0; +//Bit 0 reg_sw_rst //unsigned , default =0; +#define P_AUDIO_RSAMP_CTRL1 ((volatile uint32_t *)0xfe051c04) +//Bit 31:26 reserved //unsigned , default =0; +//Bit 25 reg_rsamp_rst_sel //unsigned , default =0; +//Bit 24 reg_module_bypas //unsigned , default =0; +//Bit 23:18 reg_gclk_ctrl //unsigned , default =0; +//Bit 17:13 reg_in_msb //unsigned , default =23; +//Bit 12 reg_output_en //unsigned , default =0; +//Bit 11 reg_rsamp_en //unsigned , default =0; +//Bit 10 reg_filt_en //unsigned , default =0; +//Bit 9 reg_post_en //unsigned , default =0; +//Bit 8 reg_inp_mux_mode //unsigned , default =0; +//Bit 7:4 reserved //unsigned , default =2; +//Bit 3:0 reg_inp_mux //unsigned , default =0; +#define P_AUDIO_RSAMP_CTRL2 ((volatile uint32_t *)0xfe051c08) +//Bit 31:30 reserved //unsigned , default =0; +//Bit 29:24 reg_chx_size //unsigned , default =2; +//Bit 23:18 reserved //unsigned , default =0; +//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4 +//Bit 15:8 reg_filt_tap //unsigned , default =63; +//Bit 7:0 reg_intp_tap //unsigned , default =63; +#define P_AUDIO_RSAMP_PHSINIT ((volatile uint32_t *)0xfe051c0c) +//Bit 31:28 reserved //unsigned , default = 0; +//Bit 27:0 reg_init_phs //unsigned , default = 0; +#define P_AUDIO_RSAMP_PHSSTEP ((volatile uint32_t *)0xfe051c10) +//Bit 31 reserved //unsigned , default = 0; +//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000 +#define P_AUDIO_RSAMP_SHIFT ((volatile uint32_t *)0xfe051c14) +//Bit 31:24 reg_rsft_iir //unsigned , default = 23; +//Bit 23:16 reg_rsft_blnd //unsigned , default = 21; +//Bit 15:8 reg_rsft_sinc //unsigned , default = 31; +//Bit 7:0 reg_rsft_aa //unsigned , default = 31; +#define P_AUDIO_RSAMP_ADJ_CTRL0 ((volatile uint32_t *)0xfe051c18) +//Bit 31:3 reserved //unsigned +//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0; +//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0; +//Bit 0 reg_rsamp_adj_en //unsigned , default = 0; +#define P_AUDIO_RSAMP_ADJ_CTRL1 ((volatile uint32_t *)0xfe051c1c) +//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8; +//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768; +#define P_AUDIO_RSAMP_ADJ_SFT ((volatile uint32_t *)0xfe051c20) +//Bit 31:30 reserved //unsigned , default = 0; +//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0; +//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9; +//Bit 23:21 reserved //unsigned , default = 0; +//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1; +//Bit 15:13 reserved //unsigned , default = 0; +//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6; +//Bit 7:6 reserved //unsigned , default = 0; +//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12; +#define P_AUDIO_RSAMP_ADJ_IDET_LEN ((volatile uint32_t *)0xfe051c24) +//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000; +#define P_AUDIO_RSAMP_ADJ_FORCE ((volatile uint32_t *)0xfe051c28) +//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8; +#define P_AUDIO_RSAMP_ADJ_KI_FORCE ((volatile uint32_t *)0xfe051c2c) +//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0; +#define P_AUDIO_RSAMP_RO_STATUS ((volatile uint32_t *)0xfe051c40) +//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]} +#define P_AUDIO_RSAMP_RO_ADJ_FREQ ((volatile uint32_t *)0xfe051c44) +//Bit 31:0 ro_rsamp_adj_freq +#define P_AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((volatile uint32_t *)0xfe051c48) +//Bit 31:0 ro_det_diff_bak +#define P_AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((volatile uint32_t *)0xfe051c4c) +//Bit 31:0 ro_det_diff_dlt +#define P_AUDIO_RSAMP_RO_ADJ_PHS_ERR ((volatile uint32_t *)0xfe051c50) +//Bit 31:0 ro_det_phase_err +#define P_AUDIO_RSAMP_RO_ADJ_KI_OUT ((volatile uint32_t *)0xfe051c54) +//Bit 31:0 ro_rsamp_ki_out +#define P_AUDIO_RSAMP_RO_IN_CNT ((volatile uint32_t *)0xfe051c58) +//Bit 31:0 ro_rsamp_in_cnt +#define P_AUDIO_RSAMP_RO_OUT_CNT ((volatile uint32_t *)0xfe051c5c) +//Bit 31:0 ro_rsamp_out_cnt +#define P_AUDIO_RSAMP_POST_COEF0 ((volatile uint32_t *)0xfe051c80) +//Bit 31:0 reg_post_coef0 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF1 ((volatile uint32_t *)0xfe051c84) +//Bit 31:0 reg_post_coef1 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF2 ((volatile uint32_t *)0xfe051c88) +//Bit 31:0 reg_post_coef2 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF3 ((volatile uint32_t *)0xfe051c8c) +//Bit 31:0 reg_post_coef3 //signed , default = 0; +#define P_AUDIO_RSAMP_POST_COEF4 ((volatile uint32_t *)0xfe051c90) +//Bit 31:0 reg_post_coef4 //signed , default = 0; +#define P_AUDIO_RSAMP_AA_COEF_ADDR ((volatile uint32_t *)0xfe051cc0) +//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0; +#define P_AUDIO_RSAMP_AA_COEF_DATA ((volatile uint32_t *)0xfe051cc4) +//Bit 31:0 reg_aa_coef_data //signed , default = 0; +#define P_AUDIO_RSAMP_SINC_COEF_ADDR ((volatile uint32_t *)0xfe051d00) +//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0; +#define P_AUDIO_RSAMP_SINC_COEF_DATA ((volatile uint32_t *)0xfe051d04) +//Bit 31:0 reg_sinc_coef_data //signed , default = 0; +// +// Closing file: RESAMPLE.h +// +//======================================================================== +// AUDIO TOP_VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe054800 +// ----------------------------------------------- +#define P_EE_AUDIO2_CLK81_CTRL ((volatile uint32_t *)0xfe054800) +#define P_EE_AUDIO2_CLK81_EN ((volatile uint32_t *)0xfe054804) +#define P_EE_AUDIO2_SW_RESET0 ((volatile uint32_t *)0xfe054808) +#define P_EE_AUDIO2_CLK_GATE_EN0 ((volatile uint32_t *)0xfe05480c) +#define P_EE_AUDIO2_SECURITY_CTRL0 ((volatile uint32_t *)0xfe054810) +#define P_EE_AUDIO2_MCLK_VAD_CTRL ((volatile uint32_t *)0xfe054840) +#define P_EE_AUDIO2_VAD_CLK_CTRL ((volatile uint32_t *)0xfe054844) +#define P_EE_AUDIO2_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe054848) +#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((volatile uint32_t *)0xfe05484c) +#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((volatile uint32_t *)0xfe054850) +#define P_EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054854) +#define P_EE_AUDIO2_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe054858) +#define P_EE_AUDIO2_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe05485c) +#define P_EE_AUDIO2_TOVAD_CTRL0 ((volatile uint32_t *)0xfe054880) +#define P_EE_AUDIO2_TODDR_VAD_CTRL0 ((volatile uint32_t *)0xfe0548c0) +#define P_EE_AUDIO2_TODDR_VAD_CTRL1 ((volatile uint32_t *)0xfe0548c4) +#define P_EE_AUDIO2_TODDR_VAD_CTRL2 ((volatile uint32_t *)0xfe0548c8) +#define P_EE_AUDIO2_TODDR_VAD_START_ADDR ((volatile uint32_t *)0xfe0548cc) +#define P_EE_AUDIO2_TODDR_VAD_INIT_ADDR ((volatile uint32_t *)0xfe0548d0) +#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((volatile uint32_t *)0xfe0548d4) +#define P_EE_AUDIO2_TODDR_VAD_START_ADDRB ((volatile uint32_t *)0xfe0548d8) +#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((volatile uint32_t *)0xfe0548dc) +#define P_EE_AUDIO2_TODDR_VAD_INT_ADDR ((volatile uint32_t *)0xfe0548e0) +#define P_EE_AUDIO2_TODDR_VAD_STATUS1 ((volatile uint32_t *)0xfe0548e4) +#define P_EE_AUDIO2_TODDR_VAD_STATUS2 ((volatile uint32_t *)0xfe0548e8) +#define P_EE_AUDIO2_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054900) +#define P_EE_AUDIO2_TDMIN_VAD_SWAP0 ((volatile uint32_t *)0xfe054904) +#define P_EE_AUDIO2_TDMIN_VAD_SWAP1 ((volatile uint32_t *)0xfe054908) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((volatile uint32_t *)0xfe05490c) +#define P_EE_AUDIO2_TDMIN_VAD_STAT ((volatile uint32_t *)0xfe054910) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE0 ((volatile uint32_t *)0xfe054940) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE1 ((volatile uint32_t *)0xfe054944) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE2 ((volatile uint32_t *)0xfe054948) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE3 ((volatile uint32_t *)0xfe05494c) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE4 ((volatile uint32_t *)0xfe054950) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE5 ((volatile uint32_t *)0xfe054954) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE6 ((volatile uint32_t *)0xfe054958) +#define P_EE_AUDIO2_TDMIN_VAD_MUTE7 ((volatile uint32_t *)0xfe05495c) +#define P_EE_AUDIO2_TDMIN_VAD_MASK0 ((volatile uint32_t *)0xfe054960) +#define P_EE_AUDIO2_TDMIN_VAD_MASK1 ((volatile uint32_t *)0xfe054964) +#define P_EE_AUDIO2_TDMIN_VAD_MASK2 ((volatile uint32_t *)0xfe054968) +#define P_EE_AUDIO2_TDMIN_VAD_MASK3 ((volatile uint32_t *)0xfe05496c) +#define P_EE_AUDIO2_TDMIN_VAD_MASK4 ((volatile uint32_t *)0xfe054970) +#define P_EE_AUDIO2_TDMIN_VAD_MASK5 ((volatile uint32_t *)0xfe054974) +#define P_EE_AUDIO2_TDMIN_VAD_MASK6 ((volatile uint32_t *)0xfe054978) +#define P_EE_AUDIO2_TDMIN_VAD_MASK7 ((volatile uint32_t *)0xfe05497c) +// +// Closing file: REG_LIST_AUDIO_RTL.h +// +// +// Reading file: ../spifc/rtl/spifc_reg.vh +// +//`ifdef SPIFC_REG_DEFINE +//`else +//`define SPIFC_REG_DEFINE +//`define SPIFC BASE ADDR 32'hfd000400 +// ----------------------------------------------- +// APB_BASE: APB2_BASE_ADDR = 0xfd000400 +// ----------------------------------------------- +//AHB domain regsiter. +#define P_SPIFC_AHB_CTRL ((volatile uint32_t *)0xfd000400) +//bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request. +//bit 30. decerr_en for (AXI->AHB bridge). +//bit 29. force_incr. for ( AXI->AHB bridge). +//bit 19. critical word first. CWF_EN. 1: enable. 0 : disable. +//bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved. +//bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi. +//if disabled the 3 HRDATA buffer will random be used for all masters. +//bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation. +//bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation. +//bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation. +//bit 11:0. not used. +#define P_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfd000404) +//bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable. +//bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable. +//bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable. +//bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable. +//bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode. +//bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode. +//bit 0. not used. +#define P_SPIFC_SEC_CTRL ((volatile uint32_t *)0xfd000408) +//bit 31. ADDRESS security range enable. 1 = enable; 0: disable. +//bit 14. range6 enable: 1: enable; 0 : disable. +//bit 13. range5 enable: 1: enable; 0 : disable. +//bit 12. range4 enable: 1: enable; 0 : disable. +//bit 11. range3 enable: 1: enable; 0 : disable. +//bit 10. range2 enable: 1: enable; 0 : disable. +//bit 9. range1 enable: 1: enable; 0 : disable. +//bit 8. range0 enable: 1: enable; 0 : disable. +//bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register. +//bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register. +#define P_SPIFC_RANGE0_STA ((volatile uint32_t *)0xfd000440) +//bit 28 :6. +//AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE0_EDA ((volatile uint32_t *)0xfd000444) +//bit 28 :6. +//AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE0_CTRL ((volatile uint32_t *)0xfd000448) +// AHB secruity range 0 control. +//bit 15:8 range 0 access control for DMA access. +//bit 15 range 0 access control for DMA thread 7 +//bit 14 range 0 access control for DMA Thread 6 +//bit 13 range 0 access control for DMA Thread 5. +//bit 12 range 0 access control for DMA Thread 4. +// bit 11. range 0 access control for DMA thread 3 +// bit 10. range 0 access control for DMA Thread 2 +// bit 9. range 0 access control for DMA Thread 1. +// bit 8. range 0 access control for DMA Thread 0. +// bit 7. range 0 access control for HMASTER == 7 Not used. +// bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 0 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 0 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 0 access control for HMASTER == 3 //DSPA secure +// bit 2. range 0 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 0 access control for HMASTER == 1 //CPU secure access +// bit 0. range 0 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE1_STA ((volatile uint32_t *)0xfd00044c) +//bit 28 :6. +//AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE1_EDA ((volatile uint32_t *)0xfd000450) +//bit 28 :6. +//AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE1_CTRL ((volatile uint32_t *)0xfd000454) +// AHB secruity range 1 control. +//bit 15:8 range 1 access control for DMA access. +//bit 15 range 1 access control for DMA thread 7 +//bit 14 range 1 access control for DMA Thread 6 +//bit 13 range 1 access control for DMA Thread 5. +//bit 12 range 1 access control for DMA Thread 4. +// bit 11. range 1 access control for DMA thread 3 +// bit 10. range 1 access control for DMA Thread 2 +// bit 9. range 1 access control for DMA Thread 1. +// bit 8. range 1 access control for DMA Thread 0. +// bit 7. range 1 access control for HMASTER == 7 Not used. +// bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 1 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 1 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 1 access control for HMASTER == 3 //DSPA secure +// bit 2. range 1 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 1 access control for HMASTER == 1 //CPU secure access +// bit 0. range 1 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE2_STA ((volatile uint32_t *)0xfd000458) +//bit 28 :6. +//AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE2_EDA ((volatile uint32_t *)0xfd00045c) +//bit 28 :6. +//AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE2_CTRL ((volatile uint32_t *)0xfd000460) +// AHB secruity range 2 control. +//bit 15:8 range 2 access control for DMA access. +//bit 15 range 2 access control for DMA thread 7 +//bit 14 range 2 access control for DMA Thread 6 +//bit 13 range 2 access control for DMA Thread 5. +//bit 12 range 2 access control for DMA Thread 4. +// bit 11. range 2 access control for DMA thread 3 +// bit 10. range 2 access control for DMA Thread 2 +// bit 9. range 2 access control for DMA Thread 1. +// bit 8. range 2 access control for DMA Thread 0. +// bit 7. range 2 access control for HMASTER == 7 Not used. +// bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 2 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 2 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 2 access control for HMASTER == 3 //DSPA secure +// bit 2. range 2 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 2 access control for HMASTER == 1 //CPU secure access +// bit 0. range 2 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE3_STA ((volatile uint32_t *)0xfd000464) +//bit 28 :6. +//AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE3_EDA ((volatile uint32_t *)0xfd000468) +//bit 28 :6. +//AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE3_CTRL ((volatile uint32_t *)0xfd00046c) +// AHB secruity range 3 control. +//bit 15:8 range 3 access control for DMA access. +//bit 15 range 3 access control for DMA thread 7 +//bit 14 range 3 access control for DMA Thread 6 +//bit 13 range 3 access control for DMA Thread 5. +//bit 12 range 3 access control for DMA Thread 4. +// bit 11. range 3 access control for DMA thread 3 +// bit 10. range 3 access control for DMA Thread 2 +// bit 9. range 3 access control for DMA Thread 1. +// bit 8. range 3 access control for DMA Thread 0. +// bit 7. range 3 access control for HMASTER == 7 Not used. +// bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 3 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 3 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 3 access control for HMASTER == 3 //DSPA secure +// bit 2. range 3 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 3 access control for HMASTER == 1 //CPU secure access +// bit 0. range 3 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE4_STA ((volatile uint32_t *)0xfd000470) +//bit 28 :6. +//AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE4_EDA ((volatile uint32_t *)0xfd000474) +//bit 28 :6. +//AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE4_CTRL ((volatile uint32_t *)0xfd000478) +// AHB secruity range 4 control. +//bit 15:8 range 4 access control for DMA access. +//bit 15 range 4 access control for DMA thread 7 +//bit 14 range 4 access control for DMA Thread 6 +//bit 13 range 4 access control for DMA Thread 5. +//bit 12 range 4 access control for DMA Thread 4. +// bit 11. range 4 access control for DMA thread 3 +// bit 10. range 4 access control for DMA Thread 2 +// bit 9. range 4 access control for DMA Thread 1. +// bit 8. range 4 access control for DMA Thread 0. +// bit 7. range 4 access control for HMASTER == 7 Not used. +// bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 4 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 4 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 4 access control for HMASTER == 3 //DSPA secure +// bit 2. range 4 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 4 access control for HMASTER == 1 //CPU secure access +// bit 0. range 4 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE5_STA ((volatile uint32_t *)0xfd00047c) +//bit 28 :6. +//AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE5_EDA ((volatile uint32_t *)0xfd000484) +//bit 28 :6. +//AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE5_CTRL ((volatile uint32_t *)0xfd000480) +// AHB secruity range 5 control. +//bit 15:8 range 5 access control for DMA access. +//bit 15 range 5 access control for DMA thread 7 +//bit 14 range 5 access control for DMA Thread 6 +//bit 13 range 5 access control for DMA Thread 5. +//bit 12 range 5 access control for DMA Thread 4. +// bit 11. range 5 access control for DMA thread 3 +// bit 10. range 5 access control for DMA Thread 2 +// bit 9. range 5 access control for DMA Thread 1. +// bit 8. range 5 access control for DMA Thread 0. +// bit 7. range 5 access control for HMASTER == 7 Not used. +// bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 5 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 5 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 5 access control for HMASTER == 3 //DSPA secure +// bit 2. range 5 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 5 access control for HMASTER == 1 //CPU secure access +// bit 0. range 5 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE6_STA ((volatile uint32_t *)0xfd000488) +//bit 28 :6. +//AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE6_EDA ((volatile uint32_t *)0xfd00048c) +//bit 28 :6. +//AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. +//bit 5:0. always 0. +#define P_SPIFC_RANGE6_CTRL ((volatile uint32_t *)0xfd000490) +// AHB secruity range 6 control. +//bit 15:8 range 6 access control for DMA access. +//bit 15 range 6 access control for DMA thread 7 +//bit 14 range 6 access control for DMA Thread 6 +//bit 13 range 6 access control for DMA Thread 5. +//bit 12 range 6 access control for DMA Thread 4. +// bit 11. range 6 access control for DMA thread 3 +// bit 10. range 6 access control for DMA Thread 2 +// bit 9. range 6 access control for DMA Thread 1. +// bit 8. range 6 access control for DMA Thread 0. +// bit 7. range 6 access control for HMASTER == 7 Not used. +// bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 6 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 6 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 6 access control for HMASTER == 3 //DSPA secure +// bit 2. range 6 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 6 access control for HMASTER == 1 //CPU secure access +// bit 0. range 6 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_RANGE7_CTRL ((volatile uint32_t *)0xfd000494) +// AHB secruity range 7( default range) control. +//bit 15:8 range 7 access control for DMA access. +//bit 15 range 7 access control for DMA thread 7 +//bit 14 range 7 access control for DMA Thread 6 +//bit 13 range 7 access control for DMA Thread 5. +//bit 12 range 7 access control for DMA Thread 4. +// bit 11. range 7 access control for DMA thread 3 +// bit 10. range 7 access control for DMA Thread 2 +// bit 9. range 7 access control for DMA Thread 1. +// bit 8. range 7 access control for DMA Thread 0. +// bit 7. range 7 access control for HMASTER == 7 Not used. +// bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. +// bit 5. range 7 access control for HMASTER == 5 //DSPB non secure +// bit 4. range 7 access control for HMASTER == 4 //DSPB non secure +// bit 3. range 7 access control for HMASTER == 3 //DSPA secure +// bit 2. range 7 access control for HMASTER == 2 //DSPA non secure +// bit 1. range 7 access control for HMASTER == 1 //CPU secure access +// bit 0. range 7 access control for HMASTER == 0 //CPU non secure. +#define P_SPIFC_AHB_WTCH_CTRL ((volatile uint32_t *)0xfd000498) +//bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response. +#define P_SPIFC_SEC_VIO0 ((volatile uint32_t *)0xfd00049c) +//bit 31:0 VIO ADDR +#define P_SPIFC_SEC_VIO1 ((volatile uint32_t *)0xfd0004a0) +//bit 31. AHB VIO status. write 1 to clear the error info. +//bit 6:5 HMASTER. +//bit 4:2 HPROT. +//bit 1 HNONSEC. +//bit 0 HWRITE. +#define P_SPIFC_AHB_STS ((volatile uint32_t *)0xfd0004a4) +//bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy. +//bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing. +//bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle. +//bit 28:0. not used. +//SPI cts_spi_clk domain regsiter. +#define P_SPIFC_USER_CTRL0 ((volatile uint32_t *)0xfd000600) +//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. +//bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command. +//bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash. +#define P_SPIFC_USER_CTRL1 ((volatile uint32_t *)0xfd000604) +//bit 31. not used. +//bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period. +//bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode. +//bit 27:20. user command code. the code need to send in command period. +//bit 19. user address cycle enable. +//bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode. +//bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes. +//bit 14 user datout enable. +//bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data. +//bit 12 user data output source. 0: from data buffer. 1: from status register. +//bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode. +//bit 9:0 User data out bytes num. +#define P_SPIFC_USER_CTRL2 ((volatile uint32_t *)0xfd000608) +//bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles. +//bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode. +//bit 28:23 user dummy clock cycle number. +//bit 19:16. user command input/output direction control. 000000: right after the last output. +// 1: after the first cycle of dummy cycle. +// ..... +// 4'hf: right before the datin cycle. +//bit 15:8. data on the dummy cycle after the first byte. +//bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode. +#define P_SPIFC_USER_CTRL3 ((volatile uint32_t *)0xfd00060c) +//bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle. +//bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer. +//bit 29: 1: enable datain data AES describle. 0: not use AES. +//bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode. +//bit 25:16. user data in data bytes. how many bytes of user datain expected. +#define P_SPIFC_USER_ADDR ((volatile uint32_t *)0xfd000610) +//bit 31:0. 32bits user address. +#define P_SPIFC_AHB_REQ_CTRL ((volatile uint32_t *)0xfd000614) +//bit 31. AHB request enable. +//bit 30 AHB cmd_en. command cycle enable. +//bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 27:20:.AHB command code. +//bit 19. ahb request address cycle enable. +//bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes. +//bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle. +//bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. +//bit 7 DATA IN AES enable. 1: enable 0: disable. +//bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting. +#define P_SPIFC_AHB_REQ_CTRL1 ((volatile uint32_t *)0xfd000618) +//bit 31. ahb Dummy enable. +//bit 30:29. ahb dummy mode. +//bit 28:23. ahb request dummy clock cycles. +//bit 15:0. ahb dummy period output data. +#define P_SPIFC_AHB_REQ_CTRL2 ((volatile uint32_t *)0xfd00061c) +//bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE. +// if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary). +// if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE. +//00 : 64byte boundary. +//01 : 32byte boundary. +//10 : 16byte boundary. +//11 : reserved. +#define P_SPIFC_ACTIMING0 ((volatile uint32_t *)0xfd000620) +//bit 31:30. tSLCH +//bit 29:28 tCLSH +//bit 20:16 tSHWL +//bit 15:12 tSHSL2 +//bit 11:8 tSHSL1 +//bit 7:0 tWHSL +#define P_SPIFC_ACTIMING1 ((volatile uint32_t *)0xfd000624) +//bit 31. D2 pin WP_n function enable. +//bit 30. D2 Pin value in WP_n fucntion. +//bit 29. D3 Pin HOLD_n function enable. +//bit 8. DTR mode. not support. +//bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay. +//bit 3:0. not used. +#define P_SPIFC_ACTIMING2 ((volatile uint32_t *)0xfd000628) +//bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data. +//bit [3:0] spi clock input pin delay adjustment. +//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0. +#define P_SPIFC_DBUF_CTRL ((volatile uint32_t *)0xfd000640) +//bit 31. 1 = write DBUF. 0 : read DBUF. +//bit 30. 1. = auto update address. 0 don't change address. +//bit 7:0 DBUF address unit 32bits. +#define P_SPIFC_DBUF_DATA ((volatile uint32_t *)0xfd000644) +//bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF. +#define P_SPIFC_USER_DBUF_ADDR ((volatile uint32_t *)0xfd000648) +//bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0. +#define P_SPIFC_FLASH_STATUS ((volatile uint32_t *)0xfd000680) +#define P_SPIFC_STATUS ((volatile uint32_t *)0xfd000684) +//bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready. +//bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy. +#define P_SPIFC_CTRL ((volatile uint32_t *)0xfd000688) +//bit 15:14. mempd for DBUF MEMORY. +//bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable. +//bit 12. spifc controller clock disable. 1 = disable. 0 = enable. +//bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable. +//bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable. +//bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode. +//bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode. +//bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode. +//`endif +// +// Closing file: ../spifc/rtl/spifc_reg.vh +// +// +// Reading file: ../psram/rtl/psram_reg.vh +// +//`ifdef PSRAM_REG_DEFINE +//`else +//`define PSRAM_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007400 +// ----------------------------------------------- +#define P_PSRAM_AXI_INTF_CTRL ((volatile uint32_t *)0xfe007400) +//bit 3 axi interface soft reset. 1 = reset AXI interface. 0 = normal. +//bit 2 disable axi interface clock. 1 = disable; 0 = enable. +//bit 1 axi interface auto clock gating enable. 1 = enable; 0 = disable. +//bit 0 axi interface AXI request enable. 1 = enable. 0 = disable. +#define P_PSRAM_DBUF_CTRL ((volatile uint32_t *)0xfe007404) +//bit 16. MWRITE_EN. 1 : enabel mask write(with DM pin). 0 not enable. +//bit 15:0 DBUF AGE to write back to PSRAM if DBUF is dirty. but whole DBUF data is not READ to write.(with MWRITE enabled). +#define P_PSRAM_DBUF_CTRL1 ((volatile uint32_t *)0xfe007408) +//bit 15:0 DBUF AGE to write back to psram if DBUF is dirty and whole DBUF data is ready to write. +#define P_PSRAM_APB_CTRL ((volatile uint32_t *)0xfe00740c) +//7:4 PSRAM PHY register APB secure contrl. +//bit 7, 1: no secure control. 0 : use bit 4 to match PPROT[0] bit. +//bit 4. when bit 7 == 0, bit 4 must match PPROT[0] to access. +//3:0 PCTL_CTRL APB bus control regsiters secure control. +//bit 3, 1: no secure control. 0 : use bit 0 to match PPROT[0] bit. +//bit 0. when bit 3 == 0, bit 0 must match PPROT[0] to access. +#define P_PSRAM_SEC_CTRL ((volatile uint32_t *)0xfe007410) +//bit 31. ADDRESS security range enable. 1 = enable; 0: disable. +//if scruity range disabled, but AXI data describle enabled key0 is selected. +//bit 23 range 7 des key selection 0 : key0; 1: key1; +//bit 22 range 6 des key selection 0 : key0; 1: key1; +//bit 21 range 5 des key selection 0 : key0; 1: key1; +//bit 20 range 4 des key selection 0 : key0; 1: key1; +//bit 19 range 3 des key selection 0 : key0; 1: key1; +//bit 18 range 2 des key selection 0 : key0; 1: key1; +//bit 17 range 1 des key selection 0 : key0; 1: key1; +//bit 16 range0 des key selection 0 : key0; 1: key1; +//bit 6. range6 enable: 1: enable; 0 : disable. +//bit 5. range5 enable: 1: enable; 0 : disable. +//bit 4. range4 enable: 1: enable; 0 : disable. +//bit 3. range3 enable: 1: enable; 0 : disable. +//bit 2. range2 enable: 1: enable; 0 : disable. +//bit 1. range1 enable: 1: enable; 0 : disable. +//bit 0. range0 enable: 1: enable; 0 : disable. +#define P_PSRAM_DES_PADDING ((volatile uint32_t *)0xfe007414) +//bit 31 :0 Padding, with address together to generate describle 64 bits input. +#define P_PSRAM_RANGE0_STA ((volatile uint32_t *)0xfe007440) +//bit 22 :0. +//AXI security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE0_EDA ((volatile uint32_t *)0xfe007444) +//bit 22 :0. +//AXI security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfe007448) +// AXI secruity range 0 control. +#define P_PSRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfe00744c) +// AXI secruity range 0 control. +#define P_PSRAM_RANGE1_STA ((volatile uint32_t *)0xfe007450) +//bit 22 :0. +//AXI security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE1_EDA ((volatile uint32_t *)0xfe007454) +//bit 22 :0. +//AXI security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfe007458) +// AXI secruity range 1 control. +#define P_PSRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfe00745c) +// AXI secruity range 1 control. +#define P_PSRAM_RANGE2_STA ((volatile uint32_t *)0xfe007460) +//bit 31 : 6. +//AXI security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE2_EDA ((volatile uint32_t *)0xfe007464) +//bit 31 :6. +//AXI security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfe007468) +#define P_PSRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfe00746c) +#define P_PSRAM_RANGE3_STA ((volatile uint32_t *)0xfe007470) +//bit 31 : 6. +//AXI security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE3_EDA ((volatile uint32_t *)0xfe007474) +//bit 31 :6. +//AXI security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfe007478) +// AXI secruity range 3 control. +#define P_PSRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfe00747c) +// AXI secruity range 3 control. +#define P_PSRAM_RANGE4_STA ((volatile uint32_t *)0xfe007480) +//bit 31 :6. +//AXI security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE4_EDA ((volatile uint32_t *)0xfe007484) +//bit 31 :6. +//AXI security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfe007488) +// AXI secruity range 4 control. +#define P_PSRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfe00748c) +#define P_PSRAM_RANGE5_STA ((volatile uint32_t *)0xfe007490) +//bit 22 :0. +//AXI security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE5_EDA ((volatile uint32_t *)0xfe007494) +//bit 22 :0. +//AXI security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfe007498) +// AXI secruity range 5 control. +#define P_PSRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfe00749c) +// AXI secruity range 5 control. +#define P_PSRAM_RANGE6_STA ((volatile uint32_t *)0xfe0074a0) +//bit 22 :0. +//AXI security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE6_EDA ((volatile uint32_t *)0xfe0074a4) +//bit 22 :0. +//AXI security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. +#define P_PSRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfe0074a8) +// AXI secruity range 6 control. +#define P_PSRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfe0074ac) +// AXI secruity range 6 control. +#define P_PSRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfe0074b0) +#define P_PSRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfe0074b4) +#define P_PSRAM_VIO_STATUS ((volatile uint32_t *)0xfe0074b8) +//bit 31: security violation. write 1 to clean security violation status. +//bit 30. 1 : AXI write violation. 0 : axi read violation. +//bit 18:16. AXI ARPROT/AWPROT> +//bit 11:0. AXI violation ID. +#define P_PSRAM_VIO_ADDR ((volatile uint32_t *)0xfe0074bc) +//read only +//31:0 AXI violation address. +#define P_PSRAM_USER_CTRL0 ((volatile uint32_t *)0xfe007600) +//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. +//bit 30. usr request done. after user command done. this bit set to 1. +//bit 29. USR COMMAND enable. +//bit 28. command type0. 1 READ command. 0 write command. +//bit 27. command type1. 1 for register. 0 : for memory. +//bit 21~16. USR command clock cycles +//bit 15~0. USR COMMAND CODE. +#define P_PSRAM_USER_CTRL1 ((volatile uint32_t *)0xfe007604) +//bit 31. USR_ADDR_EN +//bit 30:29. USR_ADDR_DW +//bit 28~20. USR address clock cycle number. +//bit 19:16 USR data output/input switch postion +//bit 15. USR DUMMY ENABLE +//bit 13~8. USR DUMMY clock cycles. +//bit 5:0 USR data DQS read enable postion. +#define P_PSRAM_USER_CTRL2 ((volatile uint32_t *)0xfe007608) +//bit 31 usr des key selection. 1 : key 1; 0 : key 0. +//bit 30. usr check latency. for Winbond PSRAM data read/write, DQS input indentify the latency is doubled or not. +//bit 29. usr data des enable. +//bit 28 usr datain enable. +//bit 27. usr datain destination. 1 : write to CFG_STS register. 0 : write to DATA REGISTERs. +//bit 26~16 usr data in clock cycle number. +//bit 15. usr datout enable. +//bit 14. usr data out source 1 : from CFG_STS register. 0 from DATA register. +//bit 13~11. not used. +//bit 10~0. usr dataout clock cycles. +#define P_PSRAM_USER_CTRL3 ((volatile uint32_t *)0xfe00760c) +//bit 17:16. which cycle to ask phy to check read/write latency at PSRAM SEND COMMOND stage. +//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2. +//bit 15:0. user dummy data when output in dummy cycle. +#define P_PSRAM_USER_ADDR ((volatile uint32_t *)0xfe007610) +//bit 31:0. 32bits user address. +#define P_PSRAM_AXI_REQ_CTRL0 ((volatile uint32_t *)0xfe007614) +//bit 31. AXI request enable. +//bit 30 AXI cmd_en. command cycle enable. +//bit 29:24. AXI request command cycle clock numbers. +//bit 22. AXI request address cycle enable. +//bit 21:16. AXI request address cycle clock number. +//bit 15:14. AXI address cycle data width. +//bit 13:12. at which clock cycle to send signal to phy to check latency flag for WINBOND PSRAM flexible latency. +//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2. +//bit 6 // AXI Write dummy enable. +//bit 5:0 // axi write dummy clock cycle number. +#define P_PSRAM_AXI_REQ_CTRL1 ((volatile uint32_t *)0xfe007618) +//bit 31:16. AXI request psram READ command code. +//bit 15:0. AXI request psram write command code. +#define P_PSRAM_AXI_REQ_CTRL2 ((volatile uint32_t *)0xfe00761c) +//bit 31. AXI read request Dummy enable. +//bit 30. Check latency enable for WINBOND PSRAM flexible latency. +//bit 27:22. clock cycles in dummy stage to eanble PSRAM PHY reading logic. +//bit 21:16. axi_read dummy clock cycles number. +//bit 15:0. dummy data if output in dummy cycles. +#define P_PSRAM_AXI_REQ_CTRL3 ((volatile uint32_t *)0xfe007620) +//bit 31 des enable. +//bit 26:16. DATA input clock cycles. +//bit 10:0. DATA output clock cycles. +#define P_PSRAM_ACTIMING0 ((volatile uint32_t *)0xfe007624) +//bit 31:30. tSLCH +//bit 29:28 tCLSH +//bit 20:16 tSHWL +//bit 15:12 tSHSL2 +//bit 11:8 tSHSL1 +//bit 7:0 tWHSL +#define P_PSRAM_ACTIMING1 ((volatile uint32_t *)0xfe007628) +//bit 7:0 tRWR for winbond PSRAM, = tRWR -3. Winbond PSRAM include one CS cycle and 2 command cycle. +//for APMEMORY should be same value of tCPH +#define P_PSRAM_ACTIMING2 ((volatile uint32_t *)0xfe00762c) +#define P_PSRAM_WDG_CTRL ((volatile uint32_t *)0xfe007630) +//bit [31] 1: force to reset PSRAM PCTL and PHY logic. 0: normal. +//bit [30] 1: automatic reset PSRAM PCTL and PHY logic if watch dog triggered. +//bit 12:0. watch dog timer. for Winbond PSRAM should be 1us for tRC. for APMEMORY should be 1us for tCEM. +//SPI DATA BUFFER. There's a total 512KByte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the PSRAM_USE_DBUF_ADDR last 2 bits must be 0. +#define P_PSRAM_DBUF_0 ((volatile uint32_t *)0xfe007640) +#define P_PSRAM_DBUF_1 ((volatile uint32_t *)0xfe007644) +#define P_PSRAM_DBUF_2 ((volatile uint32_t *)0xfe007648) +#define P_PSRAM_DBUF_3 ((volatile uint32_t *)0xfe00764c) +#define P_PSRAM_DBUF_4 ((volatile uint32_t *)0xfe007650) +#define P_PSRAM_DBUF_5 ((volatile uint32_t *)0xfe007654) +#define P_PSRAM_DBUF_6 ((volatile uint32_t *)0xfe007658) +#define P_PSRAM_DBUF_7 ((volatile uint32_t *)0xfe00765c) +#define P_PSRAM_DBUF_8 ((volatile uint32_t *)0xfe007660) +#define P_PSRAM_DBUF_9 ((volatile uint32_t *)0xfe007664) +#define P_PSRAM_DBUF_A ((volatile uint32_t *)0xfe007668) +#define P_PSRAM_DBUF_B ((volatile uint32_t *)0xfe00766c) +#define P_PSRAM_DBUF_C ((volatile uint32_t *)0xfe007670) +#define P_PSRAM_DBUF_D ((volatile uint32_t *)0xfe007674) +#define P_PSRAM_DBUF_E ((volatile uint32_t *)0xfe007678) +#define P_PSRAM_DBUF_F ((volatile uint32_t *)0xfe00767c) +#define P_PSRAM_CFG_STS ((volatile uint32_t *)0xfe007680) +//32bits register to save the USR read command read back values. +#define P_PSRAM_STATUS ((volatile uint32_t *)0xfe007684) +//bit 31. usr_req_done flag. 1 : user request done . write 1 to clean. +//bit 30~11. +//bit 10:8 +//bit 7:3. +//bit 2. axi_data buffer idle bit. 1 : idle. 0 : working. +//bit 1. axi interface idle bit. 1 : idle. 0 : working. +//bit 0. psram ctrl idle bit. 1 : idle. 0 : working. +#define P_PSRAM_CTRL ((volatile uint32_t *)0xfe007688) +//bit 31. PSRAM in DTR mode. +//bit 30. psram input data latch clock select. 1: from clock input pin. 0: from DQS +//if use clock input pin as data input latch clock, bit 13:12 should select 01. +//bit 29:27. PSRAM mode. +//'b000 : STR SPI mode. +//'b001 : STR QPI mode. +//'b010 : DTR QPI mode. +//'b011 : DTR OPI FLASH. +//'b100 : APmemory PSRAM mode. +//'b101 : Winbond PSRAM mode. +//bit 26. enable to generation interruption after usr request done. 1: enable. 0: disable. +//bit 25. to enable APMEMORY 2 command cycle mode. 1 : enable : 0: 3 command cycles. +//bit 24. to enable the psram clock output always enable. 1 : enable. 0: disable. +//bit 23. to enable the psram clock output extend mode to cover APMEMORY tCPI. +//bit 22. to disable the CKN output. 1: disable PSRAM CK_N pin output. 0: CK_N working normal. +//bit 21. PSRAM DATA IN/OUT high 8bit and low 8 bit endian. 1 : rising edge is low byte. falling edge data is high byte. 0 : rising edge is high byte. falling edge data is low byte. +//bit 20. PSRAM ADDRESS unit. 1: Byte. 0 : word. +// APMEMORY used byte address. Winbond use word address. +//bit 19. DQSEN generation. if use dqs to latch input data, this bit should be set to 1 to ask DMC generate ENABLE singal in dummy stage. 0: not generate DQS_EN. +//bit 18. PSRAM RESET I/O oe_n value. if need RESET pin. +//bit 17. PSRAM RESET I/O output vale. if need reset pin. +//bit 16. force CS output low. for APMEMORY exit DPPD mode. 1: to force cs output low : 0 output normal working mode. +//bit 13:12. psram data in clock enable selection. 00: use DQSEN. 01: use clkin cnt. +//bit 11. DM Disable. 1: disable DM output. 0: with dmoutput. +//bit 9. psram pctl auto clock gating enable. 1: enable. 0 : disable. +//bit 8. psram pctl clock disable. 1: disable. 0 : enable. +//bit 2 PSRAM SPI mode, DQ2 works as WP(write protection mode). +//bit 1. DQ2 WP mode value. +//bit 0. PSRAM SPI mode, DQ3 works as HOLD function. +#define P_PSRAM_PIN_CTRL ((volatile uint32_t *)0xfe00768c) +//bit 30:28 DATA 6 DQ pin selection. +//bit 27:24 DATA 6 DQ pin selection. +//bit 22:20 DATA 5 DQ pin selection. +//bit 18:16 DATA 4 DQ pin selection. +//bit 14:12 DATA 3 DQ pin selection. +//bit 10:8 DATA 2 DQ pin selection. +//bit 6:4 DATA 1 DQ pin selection. +//bit 2:0 DATA 0 DQ pin selection. +//0 : from DQ[0] +//1 : from DQ[1] +//2 : from DQ[2] +//3 : from DQ[3] +//4 : from DQ[4] +//5 : from DQ[5] +//6 : from DQ[6] +//7 : from DQ[7] +//psram_dly_16 is used for all DQ[0~] in/out/oen delay adjustment. +//psram_dly_16 consists of 15 delay cells, one delay cell is 50ps delay( typical corner). +//psram_dly_16 is control by delay_sel[3:0]. 0 = no delay. 1~15 controls how many delay cells used. +//psram_dly_16 can be controlled by each control register either with real delay mode or VT updated with 4xclock period. +//psram_lcdl is used for DQS/DQSN input and CK/CKN output delay 90degree delay generation and/or delay fine tune. +//psram_lcdl consits of 96 delay cells, same delay cell used in psram_dly_16. +//psram_lcdl should be calibrated with the psram_4xclock. and tracked with psram_4xclock with VT updated. +#define P_PSRAM_DQ0_DIN_DLY ((volatile uint32_t *)0xfe007700) +//bit 6:0. DQ0 DIN delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_DIN_DLY ((volatile uint32_t *)0xfe007704) +//bit 6:0. DQ1 input delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_DIN_DLY ((volatile uint32_t *)0xfe007708) +//bit 6:0. DQ2 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_DIN_DLY ((volatile uint32_t *)0xfe00770c) +//bit 6:0. DQ3 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_DIN_DLY ((volatile uint32_t *)0xfe007710) +//bit 6:0. DQ4 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_DIN_DLY ((volatile uint32_t *)0xfe007714) +//bit 6:0. DQ5 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_DIN_DLY ((volatile uint32_t *)0xfe007718) +//bit 6:0. DQ6 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_DIN_DLY ((volatile uint32_t *)0xfe00771c) +//bit 6:0. DQ7 input delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ0_DOUT_DLY ((volatile uint32_t *)0xfe007720) +//bit 6:0. DQ0 DOUT delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_DOUT_DLY ((volatile uint32_t *)0xfe007724) +//bit 6:0. DQ1 output delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_DOUT_DLY ((volatile uint32_t *)0xfe007728) +//bit 6:0. DQ2 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_DOUT_DLY ((volatile uint32_t *)0xfe00772c) +//bit 6:0. DQ3 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_DOUT_DLY ((volatile uint32_t *)0xfe007730) +//bit 6:0. DQ4 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_DOUT_DLY ((volatile uint32_t *)0xfe007734) +//bit 6:0. DQ5 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_DOUT_DLY ((volatile uint32_t *)0xfe007738) +//bit 6:0. DQ6 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_DOUT_DLY ((volatile uint32_t *)0xfe00773c) +//bit 6:0. DQ7 output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ0_OEN_DLY ((volatile uint32_t *)0xfe007740) +//bit 6:0. DQ0 OEN delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ1_OEN_DLY ((volatile uint32_t *)0xfe007744) +//bit 6:0. DQ1 output enable delay control. in DLY16 read mode, only [3:0] is valid. +#define P_PSRAM_DQ2_OEN_DLY ((volatile uint32_t *)0xfe007748) +//bit 6:0. DQ2 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ3_OEN_DLY ((volatile uint32_t *)0xfe00774c) +//bit 6:0. DQ3 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ4_OEN_DLY ((volatile uint32_t *)0xfe007750) +//bit 6:0. DQ4 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ5_OEN_DLY ((volatile uint32_t *)0xfe007754) +//bit 6:0. DQ5 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ6_OEN_DLY ((volatile uint32_t *)0xfe007758) +//bit 6:0. DQ6 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQ7_OEN_DLY ((volatile uint32_t *)0xfe00775c) +//bit 6:0. DQ7 output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DM_DOUT_DLY ((volatile uint32_t *)0xfe007760) +//bit 6:0. DM output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DM_OEN_DLY ((volatile uint32_t *)0xfe007764) +//bit 6:0. DM output enable delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_CS_DOUT_DLY ((volatile uint32_t *)0xfe007768) +//bit 6:0. CS output delay control. in DLY16 real mode, only [3:0] is valid. +#define P_PSRAM_DQS_DIN_DLY ((volatile uint32_t *)0xfe00776c) +//bit 6:0. DQS input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_DQSN_DIN_DLY ((volatile uint32_t *)0xfe007770) +//bit 6:0. DQSN input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_CKN_DOUT_DLY ((volatile uint32_t *)0xfe007774) +//bit 6:0. CKN output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_CK_DOUT_DLY ((volatile uint32_t *)0xfe007778) +//bit 6:0. CK output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_RDEN_DLY ((volatile uint32_t *)0xfe00777c) +//bit 10:7. READ enable phase delay. unit = 1UI. for AP QPI PSRAM. PSRAM only send one cycle DQS preamble. +// We have to used this UI delay to compensate the whole clock output delay and the DQS input delay. +// if run high frequency, this delay need to be trained. the valid value from 0 ~ 12. Since one UI is 1/4 of PSRAM clock, +// the total delay of the clock output delay + input delay should be less than 3 PSRAM clock. +//bit 6:0. READ enable fine tune delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0; +// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1; +#define P_PSRAM_LCDL_CTRL ((volatile uint32_t *)0xfe0077c0) +//bit 31. write 1 to update all delay cell delays control. +//bit 30. write 1 to calibration LCDL. +//bit 29. LCDL track enable. 1: enable LCDL auto track VT changes. +//bit 28. LCDL delay control mode. +//1 : real delay mode. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means one delay cells. +//0 : UI MODE. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means 1/64 psram_4xclk period. +//bit 27. DLY16 ( psram_dly_16 cell) delay control mode. +//1 : real delay mode. For all data delay control register, one number means one delay cells. +//0 : UI MODE. For all data delay control register, one number means 1/64 psram_4xclk period. +//bit 27:24. not used. +//bit 23:0. timer do trigger LCDL track the VT once. each track will compensate the UI with 1/16 delay cell delay. +//LCDL calibration ctroller. +#define P_PSRAM_LCDL_CAL_CTRL1 ((volatile uint32_t *)0xfe0077c4) +//27:24. which LCDL delay line used to run calibration. +//19:16. LCDL calibration loop end position. +//15:12. LCDL calibration loop initial position. +//10:0. LCDL calibration initial phase counter. +#define P_PSRAM_LCDL_CAL_CTRL2 ((volatile uint32_t *)0xfe0077c8) +//26:16 LCDL phase lock limit. if the lcdl phase counter difference between 2 calibration loops is less than this number, The LCDL would be locked and stop the calibration. +//10:0. deta_init. the first loop phase changing number. +#define P_PSRAM_LCDL_CAL_CTRL3 ((volatile uint32_t *)0xfe0077cc) +//29:25 to configure LCDL calibration step 5 position. +//24:20 to configure LCDL calibration step 4 position. +//19:15 to configure LCDL calibration step 3 position. +//14:10 to configure LCDL calibration step 2 position. +//9:5 to configure LCDL calibration step 1 position. +//4:0 to configure LCDL calibration step 0 position. +#define P_PSRAM_LCDL_CAL_CTRL4 ((volatile uint32_t *)0xfe0077d0) +//19:15 to configure LCDL calibration step 9 position. +//14:10 to configure LCDL calibration step 8 position. +//9:5 to configure LCDL calibration step 7 position. +//4:0 to configure LCDL calibration step 6 position. +#define P_PSRAM_CLK_UI ((volatile uint32_t *)0xfe0077d4) +//bit 6:0. 4xCLOCK period delay measured from LCDL calibration. +#define P_PSRAM_LCDL_PH ((volatile uint32_t *)0xfe0077d8) +//10:0 LCDL phase counter after calibration. +#define P_PSRAM_LCDL_STATUS ((volatile uint32_t *)0xfe0077dc) +//bit 31. LCDL lock status. 1: LCDL locked to 4x clock. +//`endif +// +// Closing file: ../psram/rtl/psram_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +//`ifdef DMC_SEC_REG_DEFINE +//`else +//`define DMC_SEC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd021000 +// ----------------------------------------------- +//`define DMC_SEC_REG_BASE 32'hfd021000 +// ID assignment inside DMC.. +// id[12 :0] total 13 bit ID. +// id[12] == 1: for DMC internal TEST module. +// id[12] == 0: for AXI port input. +// id[11:0] == AXI port ID. +// id[2:0] == 0 : A55 CPU. +// id[2:0] == 1 : DSPA +// id[2:0] == 2 : DSPB +// id[2:0] == 3 : Not used. +// id[2:0] == 4 : for Device. +//Device sublevel ID. +//id[9:7] == 5 : for audio. id[3] == 0: audio +//id[9:7] == 6 : for DMA. id[6:4] for DMA thread id. id[3] for DMC security level. +//id[9:7] == others: for device other masters. +// id[2:0] == 5 : for USB device. +// id[2:0] == 6 : for I2C debug input. +// id[2:0] == 7 : for USB host. +#define P_DMC_SEC_RANGE0_STA ((volatile uint32_t *)0xfd021000) +//bit 31:12. range0 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE0_EDA ((volatile uint32_t *)0xfd021004) +//bit 31:12. range0 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE0_RID_CTRL ((volatile uint32_t *)0xfd021008) +//range 0 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE0_WID_CTRL ((volatile uint32_t *)0xfd02100c) +//range 0 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE1_STA ((volatile uint32_t *)0xfd021010) +//bit 31:12. range1 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE1_EDA ((volatile uint32_t *)0xfd021014) +//bit 31:12. range0 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE1_RID_CTRL ((volatile uint32_t *)0xfd021018) +//range 1 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE1_WID_CTRL ((volatile uint32_t *)0xfd02101c) +//range 1 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE2_STA ((volatile uint32_t *)0xfd021020) +//bit 31:12. range2 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE2_EDA ((volatile uint32_t *)0xfd021024) +//bit 31:12. range2 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE2_RID_CTRL ((volatile uint32_t *)0xfd021028) +//range 2 read access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0). +//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE2_WID_CTRL ((volatile uint32_t *)0xfd02102c) +//range 2 write access enable based on DMC ID assignments. +//bit 28. for AXI port 3. Not used in A1. should be 0. +//bit 27. for dmc_test. 1 = enable. 0 = disable. +//bit 26. for usbhost. 1 = enable. 0 = disable. +//bit 25. for i2c. 1 = enable. 0 = disable. +//bit 24. for usbdevide. 1 = enable. 0 = disable. +//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable. +//bit 22:18.for AXI device sub level id 5 ~ 0. +//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0). +//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5). +//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access. +//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access. +//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access. +#define P_DMC_SEC_RANGE3_STA ((volatile uint32_t *)0xfd021030) +//bit 31:12. range3 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE3_EDA ((volatile uint32_t *)0xfd021034) +//bit 31:12. range3 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE3_RID_CTRL ((volatile uint32_t *)0xfd021038) +//range 3 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE3_WID_CTRL ((volatile uint32_t *)0xfd02103c) +//range 3 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE4_STA ((volatile uint32_t *)0xfd021040) +//bit 31:12. range4 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE4_EDA ((volatile uint32_t *)0xfd021044) +//bit 31:12. range4 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE4_RID_CTRL ((volatile uint32_t *)0xfd021048) +//range 4 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE4_WID_CTRL ((volatile uint32_t *)0xfd02104c) +//range 4 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE5_STA ((volatile uint32_t *)0xfd021050) +//bit 31:12. range5 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE5_EDA ((volatile uint32_t *)0xfd021054) +//bit 31:12. range5 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE5_RID_CTRL ((volatile uint32_t *)0xfd021058) +//range 5 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE5_WID_CTRL ((volatile uint32_t *)0xfd02105c) +//range 5 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE6_STA ((volatile uint32_t *)0xfd021060) +//bit 31:12. range5 start address. in 4KB boundary. +#define P_DMC_SEC_RANGE6_EDA ((volatile uint32_t *)0xfd021064) +//bit 31:12. range6 end address. in 4KB boundary. +#define P_DMC_SEC_RANGE6_RID_CTRL ((volatile uint32_t *)0xfd021068) +//range 6 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE6_WID_CTRL ((volatile uint32_t *)0xfd02106c) +//range 6 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +//range 7 is default range if the access not hit any of the previous 7 range, if would hit range 7. +#define P_DMC_SEC_RANGE7_RID_CTRL ((volatile uint32_t *)0xfd021070) +//range 7 read access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_RID_CTRL for each bit define. +#define P_DMC_SEC_RANGE7_WID_CTRL ((volatile uint32_t *)0xfd021074) +//range 7 write access enable based on DMC ID assignments. +//check DMC_SEC_RANGE0_WID_CTRL for each bit define. +#define P_DMC_SEC_RANGE_CTRL ((volatile uint32_t *)0xfd021078) +//bit 23:16 8 range security level. to chosse with DES KEY to use data describle. +//bit 7:0 8 range enable. each bit for one range to indentify the range is enabled or not. +//registers to check the security protection and watch point error information. +#define P_DMC_DES_CTRL ((volatile uint32_t *)0xfd021080) +//bit 1 data describle enable. +//bit 0 wirte 1 to block DES CTRL and DES PADDING read/write. +#define P_DMC_DES_PADDING ((volatile uint32_t *)0xfd021084) +#define P_DMC_SEC_STATUS ((volatile uint32_t *)0xfd0212e0) +//bit 31~2. not used. +//bit 1 write security violation. +//bit 0. read security violation. +#define P_DMC_VIO_ADDR0 ((volatile uint32_t *)0xfd0212e4) +//ddr0 write secure violation address. +#define P_DMC_VIO_ADDR1 ((volatile uint32_t *)0xfd0212e8) +//bit 31:18 . not used. always 0. +//17 ddr0 secure check violation. +//16 ddr0 write address overflow. write out of DDR size. +//15:13. ddr0 write violation AWPROT bits. +//12:0 ddr0_write violation ID. Please check ID assignment for ID bit defines. +#define P_DMC_VIO_ADDR2 ((volatile uint32_t *)0xfd0212ec) +//ddr0 write secure violation address. +#define P_DMC_VIO_ADDR3 ((volatile uint32_t *)0xfd0212f0) +//bit 31:18 . not used. always 0. +//17 ddr0 secure check violation. +//16 ddr0 read address overflow. write out of DDR size. +//15:13. ddr0 read violation AWPROT bits. +//12:0 ddr0_read violation ID. please ID assignment for ID bit defines. +//DDR0_ADDRMAP is used for RANK0 bank, row, col address mapping from AXI 32bits linear address. +#define P_DDR0_ADDRMAP_0 ((volatile uint32_t *)0xfd021340) +//29:25 ca8. +//24:20 ca7. +//19:15 ca6. +//14:10 ca5. +//9:5 ca4. +//4:0 ca3. +#define P_DDR0_ADDRMAP_1 ((volatile uint32_t *)0xfd021344) +//29:25 ra2. +//24:20 ra1. +//19:15 ra0. +//14:10 ca11. +//9:5 ca10. +//4:0 ca9. +#define P_DDR0_ADDRMAP_2 ((volatile uint32_t *)0xfd021348) +//29:25 ra8. +//24:20 ra7. +//19:15 ra6. +//14:10 ra5. +//9:5 ra4. +//4:0 ra3. +#define P_DDR0_ADDRMAP_3 ((volatile uint32_t *)0xfd02134c) +//29:25 ra14. +//24:20 ra13. +//19:15 ra12. +//14:10 ra11. +//9:5 ra10. +//4:0 ra9. +#define P_DDR0_ADDRMAP_4 ((volatile uint32_t *)0xfd021350) +//29:25 ra16 for DDR4 SDRAM +//24:20 bg1 for DDR4 SDRAM. +//19:15 ba2. or bg0 for DDR4. +//14:10 ba1. +//9:5 ba0. +//4:0 ra15. +#define P_DMC_DDR_CTRL ((volatile uint32_t *)0xfd021368) +// DDR PHY and DMC only supports 16bits and rank0 only. +//bit 24:22 3'b000 : ddr3 mode. +//3'b001 : ddr4 mode. +//3'b010 : lpddr3 mode. +//3'b011 : lpddr4 mode. +//bit 20 DDR4 BG1 enable bit. +//bit 3:0 : DDR rank 0 size bit [2:0]. +//4'b0000 : DDR rank 0 is 128Mbyte. +//4'b0001 : DDR rank 0 is 256Mbyte. +//4'b0010 : DDR rank 0 is 512Mbyte. +//4'b0011 : DDR rank 0 is 1Gbyte. +//4'b0100 : DDR rank 0 is 2Gbyte. +//4'b0101 : DDR rank 0 is 4Gbyte. +//4'b1000 : DDR rank 0 is 4Gbyte. +//4'b1001 : DDR rank 0 is 4Gbyte. +//others : reserved. +#define P_DMC_APB_SEC_CTRL ((volatile uint32_t *)0xfd02136c) +//bit 19:16. DMC normal APB register secure control. +//bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 16 to access those regsiter. +//Bit15:12. DMC sticky APB regsiter secure control. +//bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to access those register. +//bit 11:8. not used. +//Bit 7:4. DMC DDR SDRAM protocal contorl register contorl +//bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to access those register. +//bit 3:0. PHY APB regsiter secure control. +//bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to access those register. +#define P_DMC_DDR_PHY_CTRL ((volatile uint32_t *)0xfd0212fc) +//bit 4 PwrOkIn +//bit 3. PHY APB soft reset_n +//bit 2. PHY soft reset_n +//bit 1. PHY DfiClk enable. +//bit 0. PHY DfiCtlClk enable. +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd021400 +// ----------------------------------------------- +//`define DMC_TEST_REG_BASE 32'hfd021400 +#define P_DMC_TEST_WRCMD_ADDR ((volatile uint32_t *)0xfd021770) +// the current write cmd address. +#define P_DMC_TEST_RDRSP_ADDR ((volatile uint32_t *)0xfd021774) +// the failed read response address(for error data ) +#define P_DMC_TEST_RDCMD_ADDR ((volatile uint32_t *)0xfd021778) +// the current read command address. +#define P_DMC_TEST_WDG ((volatile uint32_t *)0xfd02177c) +//31:16. write response watch dog. +//15:0. read response watch dog. +#define P_DMC_TEST_STA ((volatile uint32_t *)0xfd021780) +//test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. +// for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0. +#define P_DMC_TEST_EDA ((volatile uint32_t *)0xfd021784) +//test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. +// for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1. +#define P_DMC_TEST_CTRL ((volatile uint32_t *)0xfd021788) +//bit 31. enable test. +//bit 30. when enable test, enable the write to DDR function. +//bit 29. when enable test, enable the read from DDR function. +//bit 28. Not used. +//bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer. +//bit 26. Not used. +//bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address. +// 1: test module would pick the random address from test start address and test end address. +//bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers. +// for write if the write command number == the DMC_TEST_NUM, the write is done. +// for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times. +// 1 : finshed at end address. +//bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}). +// 0 : the WDATA is the data in write register. +//bit 23. Not used. +//bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times. +//bit 19. limit write. 0: no outstanding write request limitation. +// 1: limit the outstanding write commands to the number of bits [15:8] +//bit 18. limit read. 0. no outstanding read request limitation. +// 1. limit the read outstanding request to the number of bits[7:0]. +//bit 17:16. Not used. +//bit 15:8. write outstanding commands limit. +//bit 7:0. read outstanding commands limit. +#define P_DMC_TEST_NUM ((volatile uint32_t *)0xfd02178c) +// how many test command for the test if the DMC_TEST_CTRL bit 24 is 0. +#define P_DMC_TEST_WD0 ((volatile uint32_t *)0xfd021790) +// write data 0 for write command. also for read back data comparision. +#define P_DMC_TEST_WD1 ((volatile uint32_t *)0xfd021794) +// write data 1 for write command. also for read back data comparision. +#define P_DMC_TEST_WD2 ((volatile uint32_t *)0xfd021798) +// write data 2 for write command. also for read back data comparision. +#define P_DMC_TEST_WD3 ((volatile uint32_t *)0xfd02179c) +// write data 3 for write command. also for read back data comparision. +#define P_DMC_TEST_WD4 ((volatile uint32_t *)0xfd0217a0) +// write data 4 for write command. also for read back data comparision. +#define P_DMC_TEST_WD5 ((volatile uint32_t *)0xfd0217a4) +// write data 5 for write command. also for read back data comparision. +#define P_DMC_TEST_WD6 ((volatile uint32_t *)0xfd0217a8) +// write data 6 for write command. also for read back data comparision. +#define P_DMC_TEST_WD7 ((volatile uint32_t *)0xfd0217ac) +// write data 7 for write command. also for read back data comparision. +#define P_DMC_TEST_RD0 ((volatile uint32_t *)0xfd0217b0) +// the read back data 0. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD1 ((volatile uint32_t *)0xfd0217b4) +// the read back data 1. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD2 ((volatile uint32_t *)0xfd0217b8) +// the read back data 2. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD3 ((volatile uint32_t *)0xfd0217bc) +// the read back data 3. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD4 ((volatile uint32_t *)0xfd0217c0) +// the read back data 4. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD5 ((volatile uint32_t *)0xfd0217c4) +// the read back data 5. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD6 ((volatile uint32_t *)0xfd0217c8) +// the read back data 6. if error happens, it would capture the first error data. +#define P_DMC_TEST_RD7 ((volatile uint32_t *)0xfd0217cc) +// the read back data 7. if error happens, it would capture the first error data. +#define P_DMC_TEST_ERR_ADDR ((volatile uint32_t *)0xfd0217d0) +// it capature the first error address. +#define P_DMC_TEST_ERR_CNT ((volatile uint32_t *)0xfd0217d4) +// how many data error happens in the whole test period. +#define P_DMC_TEST_STS ((volatile uint32_t *)0xfd0217d8) +//bit 31, test done bit. write 1 to clean. +//bit 30, indicate address err +//bit 29~7. not used. +//bit 6. read data resp error(caused by security or rd latency). +//bit 5. test MRR/MPR rd latency error. write 1 clear +//bit 4, sha done. write 1 to clean. +//bit 3, write done. write 1 to clean. +//bit 2, read done. write 1 to clean +//bit 1, write watchdog triggered. write 1 to clean +//bit 0, read watchdog triggered. write 1 to clean. +#define P_DMC_TEST_COMP_MASK ((volatile uint32_t *)0xfd0214cc) +//32bits for DMC TEST COMPARE bit enable. +//1 : to MASK this bit. 0: compare this bit. +#define P_DMC_TEST_RDBI0 ((volatile uint32_t *)0xfd0214d0) +//MPC RD FIFO command DBI read back data +//bit 31:16 the second cycle. +//bit 15:0 the first cycle. +#define P_DMC_TEST_RDBI1 ((volatile uint32_t *)0xfd0214d4) +//MPC RD FIFO command DBI read back data +//bit 31:16. the Forth cycle. +//bit 15:0. the third cycle. +#define P_DMC_TEST_WSTRB0 ((volatile uint32_t *)0xfd0214d8) +//MPC WR FIFO command DM bit write data +//bit 31:16 the second cycle. +//bit 15:0 the first cycle. +#define P_DMC_TEST_DRAM_CMD ((volatile uint32_t *)0xfd0214e0) +//bit 31. cmd done. write 0 to clean. +//bit 30. data done. write 0 to clean. +//bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W +//bit 4. LPDDR4 MPC write data command( MPC WR FIFO). Not support LPDDR4 in A1. +//bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).Not support LPDDR4 in A1. +//bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)Not support LPDDR4 in A1. +//bit 1. mrr comand. +//bit 0. mrw command. +#define P_DMC_TEST_DRAM_CMD_CODE ((volatile uint32_t *)0xfd0214e4) +//bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles. +// LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles; +// DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles. +//bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. In A1, only rank0 supported. +//bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.In A1, only rank0 supported. +//bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0]. +//bit 15:0 opcode. +#define P_DMC_TEST_DRAM_CMD_TIME ((volatile uint32_t *)0xfd0214e8) +//bit 31:16 PRE CMD timer. //delay how many cycle to start the command. +//bit 15:0 POST CMD timer //delay how many cycle after the command execute. +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +//`ifdef DMC_REG_DEFINE +//`else +//`define DMC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020000 +// ----------------------------------------------- +//`define DMC_REG_BASE 32'hfd020000 +#define P_DMC_SOFT_RST2 ((volatile uint32_t *)0xfd02000c) +//bit 31~11. reserved for future. +//bit 10 DMC DFI cmd soft reset_n +//bit 9 DMC DFI MISC soft reset_n +//bit 8 DMC DFI data soft reset_n +//bit 7 DMC DFI dcu soft reset_n +//bit 6 DMC siu soft reset_n +//bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode. +//bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode. +//bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode. +//bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode. +//bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode. +//bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1: +#define P_DMC_VERSION ((volatile uint32_t *)0xfd020014) +//read only 32'h000b0000. for A1 +#define P_DMC_MON_CTRL0 ((volatile uint32_t *)0xfd020080) +//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. +//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. +//bit 1. qos monitor 1 enable. +//bit 0. qos monitor 0 enable. +#define P_DMC_MON_CTRL1 ((volatile uint32_t *)0xfd020084) +//bit 8:0. qos monitor 0 channel select. +//bit 8 to select DMC TEST +//bit 7:0 each bit enable one AXI subID. +#define P_DMC_MON_CTRL2 ((volatile uint32_t *)0xfd020088) +//bit 8. to enabe monitor 0 second level subID selection for example device. +//bit 7:0 each bit to enable one second level subID inside device. +#define P_DMC_MON_CTRL3 ((volatile uint32_t *)0xfd02008c) +//bit 8:0. qos monitor 1 channel select. +//bit 8 to select DMC TEST +//bit 7:0 each bit enable one AXI subID. +#define P_DMC_MON_CTRL4 ((volatile uint32_t *)0xfd020090) +//bit 8. to enabe monitor 1 second level subID selection for example device. +//bit 7:0 each bit to enable one second level subID inside device. +#define P_DMC_MON_ALL_REQ_CNT ((volatile uint32_t *)0xfd0200a4) +// at the test period, the whole MMC request time. +#define P_DMC_MON_ALL_GRANT_CNT ((volatile uint32_t *)0xfd0200a8) +// at the test period, the whole MMC granted data cycles. 64bits unit. +#define P_DMC_MON_ONE_GRANT_CNT ((volatile uint32_t *)0xfd0200ac) +// at the test period, the granted data cycles for the selected channel and ports. +#define P_DMC_MON_SEC_GRANT_CNT ((volatile uint32_t *)0xfd0200b0) +// at the test period, the granted data cycles for the selected channel and ports. +#define P_DMC_MON_TIMER ((volatile uint32_t *)0xfd0200bc) +// timer for the monitor period. +#define P_DMC_CLKG_CTRL2 ((volatile uint32_t *)0xfd0200c8) +//bit 10 enable auto clock gating for dfi command generation +//bit 9 enable auto clock gating for dram cntroller +//bit 8 enable auto clock gating for dfi data path. +//bit 7. enalbe auto clock gating for write rsp generation. +//bit 6. enalbe auto clock gating for read rsp generation. +//bit 5. enalbe auto clock gating for ddr0 command filter. +//bit 4. enalbe auto clock gating for ddr0 write reorder buffer. +//bit 3. enalbe auto clock gating for ddr0 write data buffer. +//bit 2. enalbe auto clock gating for ddr0 read reorder buffer. +//bit 1. reserved +//bit 0. reserved +#define P_DMC_CLKG_CTRL3 ((volatile uint32_t *)0xfd0200cc) +//bit 10 force to disable the clock of dfi command generation +//bit 9 force to disable the clock of dram cntroller +//bit 8 force to disable the clock of dfi data path. +//bit 7. force to disalbe the clock of write rsp generation. +//bit 6. force to disalbe the clock of read rsp generation. +//bit 5. force to disalbe the clock of command filter. +//bit 4. force to disalbe the clock of write reorder buffer. +//bit 3. force to disalbe the clock of write data buffer. +//bit 2. force to disalbe the clock of read reorder buffer. +//bit 1. reserved. +//bit 0. reserved. +#define P_DMC_CHAN_STS ((volatile uint32_t *)0xfd0200d8) +//bit 4 always 1 +//bit 3 ddr0 write data buffer idle. 1 : idle 0: busy. +//bit 2 always 1. +//bit 1 ddr0 wbuf idle. 1 : idle 0: busy. +//bit 0. axi0 channel idle. 1 : idle 0: busy. +#define P_DMC_CMD_FILTER_CTRL3 ((volatile uint32_t *)0xfd020108) +//bit 31. force wbuf empty. +//bit 30:26 wbuf high level number +//bit 25:21 wbuf mid level number +//bit 20:16 wbuf low level number +//bit 14:10 rbuf high level number +//bit 9:5 rbuf middle level number +//bit 4:0 rbuf low level number +#define P_DMC_CMD_FILTER_CTRL4 ((volatile uint32_t *)0xfd02010c) +//bit 29:25. tITW.long +//bit 24:20. tITW. short +//bit 19:12 tAP auto precharge the bank not used if idle that long time. +//bit 11:6 write to read accesses if there write hit request. +//bit 5:0 read to write accesses if there write hit request. +#define P_DMC_CMD_FILTER_CTRL5 ((volatile uint32_t *)0xfd020110) +//bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer. +//bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long. +//bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request. +//bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request. +#define P_DMC_CMD_FILTER_CTRL6 ((volatile uint32_t *)0xfd020114) +//bit 31:24 write urgent 3 request pending hold num. +//bit 23:16 write urgent 2 request pending hold num. +//bit 15:8. write urgent 1 request pending hold num. +//bit 7:0. write urgent 0 request pending hold num. +#define P_DMC_CMD_FILTER_CTRL7 ((volatile uint32_t *)0xfd020118) +//bit 15:8 write to read waiting cycles if there write hit request. +//bit 7:0 read to write waiting cycles if there write hit request. +#define P_DMC_CMD_BUFFER_CTRL ((volatile uint32_t *)0xfd02011c) +//bit 31:26 total write buffer number. default 32. +//bit 25:20 total read buffer number. default 32. +//bit 19:8 reserved. +//bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long. +#define P_DMC_CMD_BUFFER_CTRL1 ((volatile uint32_t *)0xfd020120) +//bit 29:24 read buffer number in non-urgent request. +//bit 23:16 read buffer bank miss watch dog threshold. +//bit 15:12 read buffer urgent level 3 counter inc weight. +//bit 11:8 read buffer urgent level 2 counter inc weight. +//bit 7:4 read buffer urgent level 1 counter inc weight. +//bit 3:0 read buffer urgent level 0 counter inc weight. +#define P_DMC_AXI0_CHAN_CTRL ((volatile uint32_t *)0xfd020200) +//bit 31 AXI interface request enable. +//bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable. +//bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock. +//bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode. +//bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode. +//bit 15:12 ugt3 QOS level. +//bit 11:8 ugt2 QOS level. +//bit 7:4 ugt1 QOS level. +//bit 3:0 not used. +#define P_DMC_AXI0_HOLD_CTRL ((volatile uint32_t *)0xfd020204) +//31:24 write hold num. max outstanding request number. +//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//15:8 read hold num. max outstanding request number. +//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define P_DMC_AXI5_HOLD_CTRL ((volatile uint32_t *)0xfd020254) +//31:24 write hold num. max outstanding request number. +//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//15:8 read hold num. max outstanding request number. +//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +//`ifdef DMC_SIU_REG_DEFINE +//`else +//`define DMC_SIU_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020400 +// ----------------------------------------------- +//`define DMC_DRAM_REG_BASE 32'hfd020400 +//in A1 project, don't support hardware controlled frequency change. +#define P_DMC_DRAM_TMRD ((volatile uint32_t *)0xfd020400) +//bit 3:0. tMRD. +#define P_DMC_DRAM_TRFC ((volatile uint32_t *)0xfd020404) +//bit 9:0 tRFC +#define P_DMC_DRAM_TRP ((volatile uint32_t *)0xfd020408) +//bit 21:16. tRP for precharge all banks. +//bit 5:0. tRP for precharge one bank. +#define P_DMC_DRAM_TRTW ((volatile uint32_t *)0xfd02040c) +//bit 5:0 tRTW +#define P_DMC_DRAM_TCL ((volatile uint32_t *)0xfd020410) +//bit 5:0 tCL/tRL. read latency. +#define P_DMC_DRAM_TCWL ((volatile uint32_t *)0xfd020414) +//bit 5:0. CWL: write latency. +#define P_DMC_DRAM_TRAS ((volatile uint32_t *)0xfd020418) +//bit 7:0. tRAS. minimum active to precharge time for same bank. +#define P_DMC_DRAM_TRC ((volatile uint32_t *)0xfd02041c) +//bit 7:0. tRC. minimum active to active time for same bank. +#define P_DMC_DRAM_TRCD ((volatile uint32_t *)0xfd020420) +//bit 7:0 tRCD active to read/write timing for same bank. +#define P_DMC_DRAM_TRRD ((volatile uint32_t *)0xfd020424) +//bit 21:16. tRRD_l active bank A to active B in same band group for DDR4. +//bit 5:0. tRRD/tRRD_s active bank A to active bank b time. +//tRRD_s: active bank A to active bank b in different bank grousp for DDR4. +#define P_DMC_DRAM_TFAW ((volatile uint32_t *)0xfd020428) +//bit 8:0 tFAW. four active command windows +#define P_DMC_DRAM_TRTP ((volatile uint32_t *)0xfd02042c) +//bit 5:0 tRTP. +#define P_DMC_DRAM_TWR ((volatile uint32_t *)0xfd020430) +//bit 5:0 tWR. +#define P_DMC_DRAM_TWTR ((volatile uint32_t *)0xfd020434) +//bit 5:0 tWTR. +#define P_DMC_DRAM_TCCD ((volatile uint32_t *)0xfd020438) +//bit 19:16. tCCD/tCCD_l. +//bit 3:0 tCCD/tCCD_s read to read command time or write to write command time. +#define P_DMC_DRAM_TEXSR ((volatile uint32_t *)0xfd02043c) +//bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command. +#define P_DMC_DRAM_TXS ((volatile uint32_t *)0xfd020440) +//bit 9:0 tXS. EXIT SELF_REFRESH to other command time +#define P_DMC_DRAM_TXP ((volatile uint32_t *)0xfd020444) +//bit 3:0. tXP. EXIT power down to other command time +#define P_DMC_DRAM_TXPDLL ((volatile uint32_t *)0xfd020448) +//bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL). +#define P_DMC_DRAM_TZQCS ((volatile uint32_t *)0xfd02044c) +//bit 11:0. ZQCS command to other command time. +#define P_DMC_DRAM_TCKSRE ((volatile uint32_t *)0xfd020450) +//bit 4:0. enter self refresh to disable clock time. +#define P_DMC_DRAM_TCKSRX ((volatile uint32_t *)0xfd020454) +//bit 4:0. enable clock to exit self refresh time. +#define P_DMC_DRAM_TCKE ((volatile uint32_t *)0xfd020458) +//bit 4:0. CKE high or low minimum time. +#define P_DMC_DRAM_TMOD ((volatile uint32_t *)0xfd02045c) +//bit 4:0 tMOD. MRR/MRW to other command time. +#define P_DMC_DRAM_TDQS ((volatile uint32_t *)0xfd020460) +//bit 3:0 tDQS. the delay to access different rank. +#define P_DMC_DRAM_TRSTL ((volatile uint32_t *)0xfd020464) +//not used. +#define P_DMC_DRAM_TZQLAT ((volatile uint32_t *)0xfd020468) +//bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode. +#define P_DMC_DRAM_TMRR ((volatile uint32_t *)0xfd02046c) +//bit 7:0 tMRR not used in DMC. not support MR READ. +#define P_DMC_DRAM_TCKESR ((volatile uint32_t *)0xfd020470) +//bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode. +#define P_DMC_DRAM_TDPD ((volatile uint32_t *)0xfd020474) +//not support. +#define P_DMC_DRAM_DFITCTRLDELAY ((volatile uint32_t *)0xfd020478) +//bit 3:0. DFI_t_ctrldealy +#define P_DMC_DRAM_DFITPHYWRDATA ((volatile uint32_t *)0xfd02047c) +//bit 5:0. dfi_t_phy_wrdata. +#define P_DMC_DRAM_DFITPHYWRLAT ((volatile uint32_t *)0xfd020480) +//bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2. +#define P_DMC_DRAM_DFITRDDATAEN ((volatile uint32_t *)0xfd020484) +//bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1. +#define P_DMC_DRAM_DFITPHYRDLAT ((volatile uint32_t *)0xfd020488) +//bit 5:0. dfi_t_rdlat. +#define P_DMC_DRAM_DFITCTRLUPDMIN ((volatile uint32_t *)0xfd02048c) +//bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ. +#define P_DMC_DRAM_DFITCTRLUPDMAX ((volatile uint32_t *)0xfd020490) +//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response. +#define P_DMC_DRAM_DFITMSTRRESP ((volatile uint32_t *)0xfd020494) +//not used. +#define P_DMC_DRAM_DFITREFMSKI ((volatile uint32_t *)0xfd020498) +//not used. +#define P_DMC_DRAM_DFITCTRLUPDI ((volatile uint32_t *)0xfd02049c) +//not used. +#define P_DMC_DRAM_DFITDRAMCLK ((volatile uint32_t *)0xfd0204a0) +//bit 17 dram clk1 enable. +//bit 16 dram clk0 enable. +//bit 15:8 DRAM CLK disable waiting time +//bit 7:0 DRAM CLK enable enable timer +#define P_DMC_DRAM_DFITLPRESP ((volatile uint32_t *)0xfd0204a8) +//bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req. +#define P_DMC_DRAM_DFITPHYMSTR ((volatile uint32_t *)0xfd0204ac) +//bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response. +// always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4. +#define P_DMC_DRAM_TCKECK ((volatile uint32_t *)0xfd0204b0) +//bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay +#define P_DMC_DRAM_TREFI ((volatile uint32_t *)0xfd0204b4) +//write this register will update the auto refresh related register to the auto refresh control logic. +//bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period. +//bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period. +//bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns. +//bit 7:0. t100ns period. unit is dmc clock cycles +#define P_DMC_DRAM_TSR ((volatile uint32_t *)0xfd0204b8) +//bit 5:0 tSR. self resfresh enter to exit time. +#define P_DMC_DRAM_TCCDMW ((volatile uint32_t *)0xfd0204bc) +//bit 5:0. 4*tCCD in LPDDR4 mask write. +#define P_DMC_DRAM_TESCKE ((volatile uint32_t *)0xfd0204c0) +//bit 5:0 tESCKE. enter self refresh to power time for LPDDR4. +#define P_DMC_DRAM_TREFI_DDR3 ((volatile uint32_t *)0xfd0204c4) +//7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command. +#define P_DMC_DRAM_TZQCAL ((volatile uint32_t *)0xfd0204c8) +//7:0. ZQCAL for LPDDR4. +#define P_DMC_DRAM_T10US ((volatile uint32_t *)0xfd0204cc) +//10us clock cycle number used for LP2 mode. +#define P_DMC_DRAM_TMRRI ((volatile uint32_t *)0xfd0204d0) +//bit 7:0 tMRRI for MRR +#define P_DMC_DRAM_DFITPHYUPDTYPE0 ((volatile uint32_t *)0xfd020600) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 0. +#define P_DMC_DRAM_DFITPHYUPDTYPE1 ((volatile uint32_t *)0xfd020604) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 1. +#define P_DMC_DRAM_DFITPHYUPDTYPE2 ((volatile uint32_t *)0xfd020608) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 2. +#define P_DMC_DRAM_DFITPHYUPDTYPE3 ((volatile uint32_t *)0xfd02060c) +//dfi_phyupd_ack hold time for dfi_phyupd_req type = 3. +#define P_DMC_DRAM_DFIODTCFG ((volatile uint32_t *)0xfd020610) +//bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. +//bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. +//bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0. +//bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1. +//bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0. +//bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity. +//bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0. +//bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. +//bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. +//bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. +#define P_DMC_DRAM_DFIODTCFG1 ((volatile uint32_t *)0xfd020614) +//bit 27:24 ODT length for BL8 read transfer. +//bit 19:16. ODT length for BL8 write transfer. +//bit 12:8. ODT latency for reads. suppose to be 0. +//bit 4:0. ODT latency for writes. suppose to be 0. +#define P_DMC_DRAM_MCFG ((volatile uint32_t *)0xfd020618) +//bit 14. 1: cke init low. 0 : cke init high. +//bit 13 1: dbi write enable only for LPDDR4. +//bit 12. 1: dbi read inversion. 0: dbi read high inversion. +//bit 11. 1: dbi read enable. 0: dbi not enabled. +//bit 10 1: enable staggered chip select for 2 ranks DRAM. +//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state. +//bit 8 send auto refr cmd before enter register triggered self refresh +//bit 7 send auto refr cmd after exit regsiter triggered self refresh mode. +//bit 6 disable dram clock after enter register triggered self refresh. +//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode. +//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4. +//bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh. +//bit 2 send ZQCS command after exit register triggered self refresh. +//bit 1 enable PHY triggered DFI_PHYUPD_REQ. +//bit 0 2T mode. always 1 in DDR3/4 mode. +#define P_DMC_DRAM_DFI_CTRL ((volatile uint32_t *)0xfd020624) +//bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable. +//bit 30:0. not used. +#define P_DMC_DRAM_DFIINITCFG ((volatile uint32_t *)0xfd020628) +//bit 31. dfi_init_complete status. read only. +//bit 15:14. Frequency set 1 dfi_freq_ratio value. Not used in A1 +//bit 12:8 Frequency set 1 dfi_freq value. Not used in A1 +//bit 7:6 Frequency set 0 dfi_freq_ratio value. +//bit 5:1 Frequency set 0 dfi_freq value. +//bit 0. dfi_init_start value can be use manually config dfi_init_start signal. +#define P_DMC_DRAM_ZQ_CTRL ((volatile uint32_t *)0xfd02062c) +// only bit 0 can be enable in A1. +//bit 2 send ZQCS command to RANK0 then send comand to RANK1. +//bit 1. send ZQCS command to both RANK0 and RANK1 together. +//bit 0. send ZQCS command to only rank0. +#define P_DMC_DRAM_APD_CTRL ((volatile uint32_t *)0xfd020630) +//bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode +//bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode. +//bit 11 enable DFI_LP_REQ when enter Auto power down mode. +//bit 10 disable DFI_clk_disable when enter auto power down mode. +//bit 9:0 0 disable auto power down mode. +//non zero value to enable auto power down when DMC is in idle state for this number of clock cycles. +#define P_DMC_DRAM_ASR_CTRL ((volatile uint32_t *)0xfd020634) +//bit [25] LP2 mode PHYCLK enable. 1 : keep PHY clock enable after enter LP2 mode. 0 : shutdown PHY clock after enter LP2 mode. +//bit [24] LP2 mode SRX waiting enable. if Self refresh too long, waiting 10us for the PHY stable before DDR SDRAM exit from self refresh state. +//bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode. +//bit 17 : send REFRESH command after exit from auto self refersh mode(ASR). +//bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR). +//bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR). +//bit 14 : send dfi_ctrl_upd after exit from ASR mode +//bit 13 : send power down command when enter ASR mode. //for LPDDR4 only. +//bit 12 : set the PHY enter LP2 mode after enter ASR mode. +//bit 11 : send DFI_LP_REQ after enter ASR mode. +//bit 10 : set DFI_CLK_DISABLE after enter ASR mode. +//bit 9:0. 0 disable auto ASR mode. +// Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode. +#define P_DMC_DRAM_PHYMSTR_CTRL ((volatile uint32_t *)0xfd020640) +//not used in A1. should be all 0. +#define P_DMC_DRAM_DFIODTRANKMAP ((volatile uint32_t *)0xfd020644) +//not used in A1. +#define P_DMC_DRAM_REFR_CTRL ((volatile uint32_t *)0xfd020648) +//bit 17:8 auto refresh request pending cnt if there's page hit request. +//bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period +//bit 5 enable dmc send ZQCS command . +//bit 4. enable dmc send DFI_CTRUPD_REQ. +//bit 3:1. how many refresh command send for one period. = this number + 1 +//bit 0. enable dmc send auto refresh command. +#define P_DMC_DRAM_FREQ_CTRL ((volatile uint32_t *)0xfd02064c) +//bit 31 . wiret 1 to change freqency read 0: finished. +//bit 30:9. not used. +//bit 9. 1 : FREQ MRW done. let FREQ change machine continue. +//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle. +// 0 after freq change finishes the state machine go back to access state. +//bit 7 when change PLL setting, disable dmc clock +//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk. +//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait. +//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0. +//bit 3:1. not used. +//bit 0. current frequency selection. +#define P_DMC_DRAM_SCFG ((volatile uint32_t *)0xfd020650) +// bit 2:0 only one bit can be high at same time. +// bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request. +// bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request. +// bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request. +#define P_DMC_DRAM_STAT ((volatile uint32_t *)0xfd020654) +//bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back. +//bit 28:24 dram_sr_state +//bit 23:20 stop_st +//bit 19:15 sleep_st +//bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode. +//1 : ACCESS sending precharege command. +//2 : ACCESS sending AUTO REFESH command. +//3 : ACCESS sending DIF_CTRLUPD_REQ command. +//4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4). +//5 : ACCESS sending ZQLATCH command to LPDDR4 only. +//bit 11:8 APD STATUS: 0 : APD_IDLE +//1 : APD sending PRECHARGE command +//2 : APD sending CKE low command +//3 : APD sending DISABLE DRAM CLOCK command +//4 : APD sending DFI_LP_CTRL_REQ +//5 : APD in Auto Power down mode. +//6 : APD deassert DFI_LP_CTRL_REQ +//7 : APD sending enable DRAM CLOCK command +//8 : APD sending out CKE high command. +//bit 7:4: DRAM_STATUS: 0 : DRAM IDLE +//1 : DRAM_STOP/DRAM_CFG +//2 : DRAM_ACCESS +//3 : DRAM_SLEEP +//4 : DRAM APD(AUTO POWER DOWN). +//5 : IDLE -> STOP/CONFIG +//6 : STOP -> SLEEP +//7 : STOP -> ACCESS +//8 : ACCESS -> SLEEP. +//9 : ACCESS -> STOP +//A : ACCESS -> APD +//B : SLEEP -> STOP +//C : SLEEP -> ACCESS +//D : APD -> ACCESS +//bit 3 reserved. +//bit 2 1 : DRAM enter normal working state. +//bit 1 1 : DRAM enter sleep state. self refresh state. +//bit 0 1 : dram enter cfg state. +#define P_DMC_DRAM_STAT1 ((volatile uint32_t *)0xfd020658) +//bit 11:8 freq_st. +//bit 7:5 train_st +//bit 4:0 dram_phy_st +#define P_DMC_PHY_RETRAINING_CTRL ((volatile uint32_t *)0xfd02065c) +// A1 not support LPDDR4 so this register is not used in A1. +//bit 31 : phy_retraining enable. +//bit 30 : check vpu sleep_en. +//bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency. +//bit 23:0: retraining period unit : 100ns. +#define P_DMC_DFI_ERR_STAT ((volatile uint32_t *)0xfd020660) +//LPDDR4 PHY DFI error infomation. +//bit 31:20. not used. +//bit 9. ddr0_dfi_error +//bit 8:5 ddr0_dfi_error_info. +//bit 4. ddr1_dfi_error. +//bit 3:0. ddr1_dfi_error_info. +#define P_DMC_LP2_TIMER ((volatile uint32_t *)0xfd020668) +//bit 15:0. timer setting to measure how long the chip is entered LP2 mode. +//this timer is 40bits counter with DMC PCLK. +//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode. +#define P_DMC_DRAM_DFI_SWAP_0 ((volatile uint32_t *)0xfd020680) +//bit 5:0. dfi_act_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_1 ((volatile uint32_t *)0xfd020684) +//bit 5:0. dfi_ras_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_2 ((volatile uint32_t *)0xfd020688) +//bit 5:0. dfi_cas_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_3 ((volatile uint32_t *)0xfd02068c) +//bit 5:0. dfi_we_n function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_4 ((volatile uint32_t *)0xfd020690) +//bit 5:0. dfi_bg0 function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_5 ((volatile uint32_t *)0xfd020694) +//bit 5:0. dfi_bg[1] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_6 ((volatile uint32_t *)0xfd020698) +//bit 5:0. dfi_ba[0] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_7 ((volatile uint32_t *)0xfd02069c) +//bit 5:0. dfi_ba[1] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_8 ((volatile uint32_t *)0xfd0206a0) +//bit 5:0. dfi_ba[2] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_9 ((volatile uint32_t *)0xfd0206a4) +//bit 5:0. dfi_a[0] function select +// 6'h00 : the function itself. +// 6'h01 : act_n. +// 6'h02 : ras_n. +// 6'h03 : cas_n. +// 6'h04 : we_n. +// 6'h05 : bg[0]. +// 6'h06 : bg[1]. +// 6'h07 : ba[0]. +// 6'h08 : ba[1]. +// 6'h09 : ba[2]. +// 6'h0a : a[0]. +// 6'h0b : a[1]. +// 6'h0c : a[2]. +// 6'h0d : a[3]. +// 6'h0e : a[4]. +// 6'h0f : a[5]. +// 6'h10 : a[6]. +// 6'h11 : a[7]. +// 6'h12 : a[8]. +// 6'h13 : a[9]. +// 6'h14 : a[10]. +// 6'h15 : a[11]. +// 6'h16 : a[12]. +// 6'h17 : a[13]. +// 6'h18 : a[14]. +// 6'h19 : a[15]. +// 6'h1a : a[16]. +// 6'h1b : a[17]. +#define P_DMC_DRAM_DFI_SWAP_10 ((volatile uint32_t *)0xfd0206a8) +//bit 5:0. dfi_a[1] function select +#define P_DMC_DRAM_DFI_SWAP_11 ((volatile uint32_t *)0xfd0206ac) +//bit 5:0. dfi_a[2] function select +#define P_DMC_DRAM_DFI_SWAP_12 ((volatile uint32_t *)0xfd0206b0) +//bit 5:0. dfi_a[3] function select +#define P_DMC_DRAM_DFI_SWAP_13 ((volatile uint32_t *)0xfd0206b4) +//bit 5:0. dfi_a[4] function select +#define P_DMC_DRAM_DFI_SWAP_14 ((volatile uint32_t *)0xfd0206b8) +//bit 5:0. dfi_a[5] function select +#define P_DMC_DRAM_DFI_SWAP_15 ((volatile uint32_t *)0xfd0206bc) +//bit 5:0. dfi_a[6] function select +#define P_DMC_DRAM_DFI_SWAP_16 ((volatile uint32_t *)0xfd0206c0) +//bit 5:0. dfi_a[7] function select +#define P_DMC_DRAM_DFI_SWAP_17 ((volatile uint32_t *)0xfd0206c4) +//bit 5:0. dfi_a[8] function select +#define P_DMC_DRAM_DFI_SWAP_18 ((volatile uint32_t *)0xfd0206c8) +//bit 5:0. dfi_a[9] function select +#define P_DMC_DRAM_DFI_SWAP_19 ((volatile uint32_t *)0xfd0206cc) +//bit 5:0. dfi_a[10] function select +#define P_DMC_DRAM_DFI_SWAP_20 ((volatile uint32_t *)0xfd0206d0) +//bit 5:0. dfi_a[11] function select +#define P_DMC_DRAM_DFI_SWAP_21 ((volatile uint32_t *)0xfd0206d4) +//bit 5:0. dfi_a[12] function select +#define P_DMC_DRAM_DFI_SWAP_22 ((volatile uint32_t *)0xfd0206d8) +//bit 5:0. dfi_a[13] function select +#define P_DMC_DRAM_DFI_SWAP_23 ((volatile uint32_t *)0xfd0206dc) +//bit 5:0. dfi_a[14] function select +#define P_DMC_DRAM_DFI_SWAP_24 ((volatile uint32_t *)0xfd0206e0) +//bit 5:0. dfi_a[15] function select +#define P_DMC_DRAM_DFI_SWAP_25 ((volatile uint32_t *)0xfd0206e4) +//bit 5:0. dfi_a[16] function select +#define P_DMC_DRAM_DFI_SWAP_26 ((volatile uint32_t *)0xfd0206ec) +//bit 5:0. dfi_a[17] function select +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//`ifdef DMC_STICKY_REG_DEFINE +//`else +//`define DMC_STICKY_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd020800 +// ----------------------------------------------- +//`define DMC_STICKY_REG_BASE 32'hfd020800 +//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted. +#define P_DMC_STICKY_0 ((volatile uint32_t *)0xfd020800) +#define P_DMC_STICKY_1 ((volatile uint32_t *)0xfd020804) +#define P_DMC_STICKY_2 ((volatile uint32_t *)0xfd020808) +#define P_DMC_STICKY_3 ((volatile uint32_t *)0xfd02080c) +#define P_DMC_STICKY_4 ((volatile uint32_t *)0xfd020810) +#define P_DMC_STICKY_5 ((volatile uint32_t *)0xfd020814) +#define P_DMC_STICKY_6 ((volatile uint32_t *)0xfd020818) +#define P_DMC_STICKY_7 ((volatile uint32_t *)0xfd02081c) +#define P_DMC_STICKY_8 ((volatile uint32_t *)0xfd020820) +#define P_DMC_STICKY_9 ((volatile uint32_t *)0xfd020824) +#define P_DMC_STICKY_10 ((volatile uint32_t *)0xfd020828) +#define P_DMC_STICKY_11 ((volatile uint32_t *)0xfd02082c) +#define P_DMC_STICKY_12 ((volatile uint32_t *)0xfd020830) +#define P_DMC_STICKY_13 ((volatile uint32_t *)0xfd020834) +#define P_DMC_STICKY_14 ((volatile uint32_t *)0xfd020838) +#define P_DMC_STICKY_15 ((volatile uint32_t *)0xfd02083c) +#define P_DMC_STICKY_16 ((volatile uint32_t *)0xfd020840) +#define P_DMC_STICKY_17 ((volatile uint32_t *)0xfd020844) +#define P_DMC_STICKY_18 ((volatile uint32_t *)0xfd020848) +#define P_DMC_STICKY_19 ((volatile uint32_t *)0xfd02084c) +#define P_DMC_STICKY_20 ((volatile uint32_t *)0xfd020850) +#define P_DMC_STICKY_21 ((volatile uint32_t *)0xfd020854) +#define P_DMC_STICKY_22 ((volatile uint32_t *)0xfd020858) +#define P_DMC_STICKY_23 ((volatile uint32_t *)0xfd02085c) +#define P_DMC_STICKY_24 ((volatile uint32_t *)0xfd020860) +#define P_DMC_STICKY_25 ((volatile uint32_t *)0xfd020864) +#define P_DMC_STICKY_26 ((volatile uint32_t *)0xfd020868) +#define P_DMC_STICKY_27 ((volatile uint32_t *)0xfd02086c) +#define P_DMC_STICKY_28 ((volatile uint32_t *)0xfd020870) +#define P_DMC_STICKY_29 ((volatile uint32_t *)0xfd020874) +#define P_DMC_STICKY_30 ((volatile uint32_t *)0xfd020878) +#define P_DMC_STICKY_31 ((volatile uint32_t *)0xfd02087c) +#define P_DMC_STICKY_32 ((volatile uint32_t *)0xfd020880) +#define P_DMC_STICKY_33 ((volatile uint32_t *)0xfd020884) +#define P_DMC_STICKY_34 ((volatile uint32_t *)0xfd020888) +#define P_DMC_STICKY_35 ((volatile uint32_t *)0xfd02088c) +#define P_DMC_STICKY_36 ((volatile uint32_t *)0xfd020890) +#define P_DMC_STICKY_37 ((volatile uint32_t *)0xfd020894) +#define P_DMC_STICKY_38 ((volatile uint32_t *)0xfd020898) +#define P_DMC_STICKY_39 ((volatile uint32_t *)0xfd02089c) +#define P_DMC_STICKY_40 ((volatile uint32_t *)0xfd0208a0) +#define P_DMC_STICKY_41 ((volatile uint32_t *)0xfd0208a4) +#define P_DMC_STICKY_42 ((volatile uint32_t *)0xfd0208a8) +#define P_DMC_STICKY_43 ((volatile uint32_t *)0xfd0208ac) +#define P_DMC_STICKY_44 ((volatile uint32_t *)0xfd0208b0) +#define P_DMC_STICKY_45 ((volatile uint32_t *)0xfd0208b4) +#define P_DMC_STICKY_46 ((volatile uint32_t *)0xfd0208b8) +#define P_DMC_STICKY_47 ((volatile uint32_t *)0xfd0208bc) +#define P_DMC_STICKY_48 ((volatile uint32_t *)0xfd0208c0) +#define P_DMC_STICKY_49 ((volatile uint32_t *)0xfd0208c4) +#define P_DMC_STICKY_50 ((volatile uint32_t *)0xfd0208c8) +#define P_DMC_STICKY_51 ((volatile uint32_t *)0xfd0208cc) +#define P_DMC_STICKY_52 ((volatile uint32_t *)0xfd0208d0) +#define P_DMC_STICKY_53 ((volatile uint32_t *)0xfd0208d4) +#define P_DMC_STICKY_54 ((volatile uint32_t *)0xfd0208d8) +#define P_DMC_STICKY_55 ((volatile uint32_t *)0xfd0208dc) +#define P_DMC_STICKY_56 ((volatile uint32_t *)0xfd0208e0) +#define P_DMC_STICKY_57 ((volatile uint32_t *)0xfd0208e4) +#define P_DMC_STICKY_58 ((volatile uint32_t *)0xfd0208e8) +#define P_DMC_STICKY_59 ((volatile uint32_t *)0xfd0208ec) +#define P_DMC_STICKY_60 ((volatile uint32_t *)0xfd0208f0) +#define P_DMC_STICKY_61 ((volatile uint32_t *)0xfd0208f4) +#define P_DMC_STICKY_62 ((volatile uint32_t *)0xfd0208f8) +#define P_DMC_STICKY_63 ((volatile uint32_t *)0xfd0208fc) +//`endif +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//======================================================================== +// APB0_RESET_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000000 +// ----------------------------------------------- +#define P_RESETCTRL_RESET0 ((volatile uint32_t *)0xfe000000) +#define P_RESETCTRL_RESET1 ((volatile uint32_t *)0xfe000004) +#define P_RESETCTRL_RESET2 ((volatile uint32_t *)0xfe000008) +#define P_RESETCTRL_RESET0_LEVEL ((volatile uint32_t *)0xfe000040) +#define P_RESETCTRL_RESET1_LEVEL ((volatile uint32_t *)0xfe000044) +#define P_RESETCTRL_RESET2_LEVEL ((volatile uint32_t *)0xfe000048) +#define P_RESETCTRL_RESET0_MASK ((volatile uint32_t *)0xfe000080) +#define P_RESETCTRL_RESET1_MASK ((volatile uint32_t *)0xfe000084) +#define P_RESETCTRL_RESET2_MASK ((volatile uint32_t *)0xfe000088) +#define P_RESETCTRL_RESET_HOLD_CYC ((volatile uint32_t *)0xfe0000c0) +#define P_RESETCTRL_WATCHDOG_CTRL0 ((volatile uint32_t *)0xfe000100) +#define P_RESETCTRL_WATCHDOG_CTRL1 ((volatile uint32_t *)0xfe000104) +#define P_RESETCTRL_WATCHDOG_CNT ((volatile uint32_t *)0xfe000108) +#define P_RESETCTRL_WATCHDOG_CLR ((volatile uint32_t *)0xfe00010c) +#define P_RESETCTRL_SEC_RESET0 ((volatile uint32_t *)0xfe000140) +#define P_RESETCTRL_SEC_RESET0_LEVEL ((volatile uint32_t *)0xfe000144) +#define P_RESETCTRL_SEC_RESET0_MASK ((volatile uint32_t *)0xfe000148) +//======================================================================== +// APB0_PAD_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000400 +// ----------------------------------------------- +#define P_PADCTRL_PIN_MUX_REG0 ((volatile uint32_t *)0xfe000400) +#define P_PADCTRL_PIN_MUX_REG1 ((volatile uint32_t *)0xfe000404) +#define P_PADCTRL_PIN_MUX_REG2 ((volatile uint32_t *)0xfe000408) +#define P_PADCTRL_PIN_MUX_REG3 ((volatile uint32_t *)0xfe00040c) +#define P_PADCTRL_PIN_MUX_REG4 ((volatile uint32_t *)0xfe000410) +#define P_PADCTRL_PIN_MUX_REG5 ((volatile uint32_t *)0xfe000414) +#define P_PADCTRL_PIN_MUX_REG6 ((volatile uint32_t *)0xfe000418) +#define P_PADCTRL_PIN_MUX_REG7 ((volatile uint32_t *)0xfe00041c) +#define P_PADCTRL_PIN_MUX_REG8 ((volatile uint32_t *)0xfe000420) +#define P_PADCTRL_PIN_MUX_REG9 ((volatile uint32_t *)0xfe000424) +#define P_PADCTRL_PIN_MUX_REGA ((volatile uint32_t *)0xfe000428) +#define P_PADCTRL_PIN_MUX_REGB ((volatile uint32_t *)0xfe00042c) +#define P_PADCTRL_PIN_MUX_REGC ((volatile uint32_t *)0xfe000430) +#define P_PADCTRL_PIN_MUX_REGD ((volatile uint32_t *)0xfe000434) +#define P_PADCTRL_PIN_MUX_REGE ((volatile uint32_t *)0xfe000438) +#define P_PADCTRL_PIN_MUX_REGF ((volatile uint32_t *)0xfe00043c) +#define P_PADCTRL_GPIO_IRQ_CTRL0 ((volatile uint32_t *)0xfe000440) +#define P_PADCTRL_GPIO_IRQ_CTRL1 ((volatile uint32_t *)0xfe000444) +#define P_PADCTRL_GPIO_IRQ_CTRL2 ((volatile uint32_t *)0xfe000448) +#define P_PADCTRL_GPIO_IRQ_CTRL3 ((volatile uint32_t *)0xfe00044c) +#define P_PADCTRL_GPIO_IRQ_CTRL4 ((volatile uint32_t *)0xfe000450) +#define P_PADCTRL_WORLDSYNC_CTRL0 ((volatile uint32_t *)0xfe000460) +#define P_PADCTRL_GPIO_MSR_CTRL0 ((volatile uint32_t *)0xfe000464) +#define P_PADCTRL_GPIOP_I ((volatile uint32_t *)0xfe000480) +#define P_PADCTRL_GPIOP_O ((volatile uint32_t *)0xfe000484) +#define P_PADCTRL_GPIOP_OEN ((volatile uint32_t *)0xfe000488) +#define P_PADCTRL_GPIOP_PULL_EN ((volatile uint32_t *)0xfe00048c) +#define P_PADCTRL_GPIOP_PULL_UP ((volatile uint32_t *)0xfe000490) +#define P_PADCTRL_GPIOP_DS ((volatile uint32_t *)0xfe000494) +#define P_PADCTRL_GPIOB_I ((volatile uint32_t *)0xfe0004c0) +#define P_PADCTRL_GPIOB_O ((volatile uint32_t *)0xfe0004c4) +#define P_PADCTRL_GPIOB_OEN ((volatile uint32_t *)0xfe0004c8) +#define P_PADCTRL_GPIOB_PULL_EN ((volatile uint32_t *)0xfe0004cc) +#define P_PADCTRL_GPIOB_PULL_UP ((volatile uint32_t *)0xfe0004d0) +#define P_PADCTRL_GPIOB_DS ((volatile uint32_t *)0xfe0004d4) +#define P_PADCTRL_GPIOX_I ((volatile uint32_t *)0xfe000500) +#define P_PADCTRL_GPIOX_O ((volatile uint32_t *)0xfe000504) +#define P_PADCTRL_GPIOX_OEN ((volatile uint32_t *)0xfe000508) +#define P_PADCTRL_GPIOX_PULL_EN ((volatile uint32_t *)0xfe00050c) +#define P_PADCTRL_GPIOX_PULL_UP ((volatile uint32_t *)0xfe000510) +#define P_PADCTRL_GPIOX_DS ((volatile uint32_t *)0xfe000514) +#define P_PADCTRL_GPIOX_DS_EXT ((volatile uint32_t *)0xfe000518) +#define P_PADCTRL_GPIOF_I ((volatile uint32_t *)0xfe000540) +#define P_PADCTRL_GPIOF_O ((volatile uint32_t *)0xfe000544) +#define P_PADCTRL_GPIOF_OEN ((volatile uint32_t *)0xfe000548) +#define P_PADCTRL_GPIOF_PULL_EN ((volatile uint32_t *)0xfe00054c) +#define P_PADCTRL_GPIOF_PULL_UP ((volatile uint32_t *)0xfe000550) +#define P_PADCTRL_GPIOF_DS ((volatile uint32_t *)0xfe000554) +#define P_PADCTRL_GPIOA_I ((volatile uint32_t *)0xfe000580) +#define P_PADCTRL_GPIOA_O ((volatile uint32_t *)0xfe000584) +#define P_PADCTRL_GPIOA_OEN ((volatile uint32_t *)0xfe000588) +#define P_PADCTRL_GPIOA_PULL_EN ((volatile uint32_t *)0xfe00058c) +#define P_PADCTRL_GPIOA_PULL_UP ((volatile uint32_t *)0xfe000590) +#define P_PADCTRL_GPIOA_DS ((volatile uint32_t *)0xfe000594) +#define P_PADCTRL_TESTN_I ((volatile uint32_t *)0xfe0005c0) +#define P_PADCTRL_TESTN_O ((volatile uint32_t *)0xfe0005c4) +#define P_PADCTRL_TESTN_OEN ((volatile uint32_t *)0xfe0005c8) +#define P_PADCTRL_TESTN_PULL_EN ((volatile uint32_t *)0xfe0005cc) +#define P_PADCTRL_TESTN_PULL_UP ((volatile uint32_t *)0xfe0005d0) +#define P_PADCTRL_TESTN_DS ((volatile uint32_t *)0xfe0005d4) +#define P_PADCTRL_MUTE_CTRL ((volatile uint32_t *)0xfe000600) +//======================================================================== +// APB0_CLK_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000800 +// ----------------------------------------------- +#define P_CLKTREE_SYS_OSCIN_CTRL ((volatile uint32_t *)0xfe000800) +#define P_CLKTREE_RTC_BY_OSCIN_CTRL0 ((volatile uint32_t *)0xfe000804) +#define P_CLKTREE_RTC_BY_OSCIN_CTRL1 ((volatile uint32_t *)0xfe000808) +#define P_CLKTREE_RTC_CTRL ((volatile uint32_t *)0xfe00080c) +#define P_CLKTREE_SYS_CLK_CTRL0 ((volatile uint32_t *)0xfe000810) +#define P_CLKTREE_AXI_CLK_CTRL0 ((volatile uint32_t *)0xfe000814) +#define P_CLKTREE_SYS_CLK_EN0 ((volatile uint32_t *)0xfe00081c) +#define P_CLKTREE_SYS_CLK_EN1 ((volatile uint32_t *)0xfe000820) +#define P_CLKTREE_AXI_CLK_EN ((volatile uint32_t *)0xfe000824) +#define P_CLKTREE_DSPA_CLK_EN ((volatile uint32_t *)0xfe000828) +#define P_CLKTREE_DSPB_CLK_EN ((volatile uint32_t *)0xfe00082c) +#define P_CLKTREE_DSPA_CLK_CTRL0 ((volatile uint32_t *)0xfe000830) +#define P_CLKTREE_DSPB_CLK_CTRL0 ((volatile uint32_t *)0xfe000834) +#define P_CLKTREE_CLK12_24_CTRL ((volatile uint32_t *)0xfe000838) +#define P_CLKTREE_GEN_CLK_CTRL ((volatile uint32_t *)0xfe00083c) +#define P_CLKTREE_TIMESTAMP_CTRL0 ((volatile uint32_t *)0xfe000840) +#define P_CLKTREE_TIMESTAMP_CTRL1 ((volatile uint32_t *)0xfe000844) +#define P_CLKTREE_TIMESTAMP_CTRL2 ((volatile uint32_t *)0xfe000848) +#define P_CLKTREE_TIMESTAMP_VAL0 ((volatile uint32_t *)0xfe00084c) +#define P_CLKTREE_TIMESTAMP_VAL1 ((volatile uint32_t *)0xfe000850) +#define P_CLKTREE_TIMEBASE_CTRL0 ((volatile uint32_t *)0xfe000854) +#define P_CLKTREE_TIMEBASE_CTRL1 ((volatile uint32_t *)0xfe000858) +#define P_CLKTREE_SAR_ADC_CLK_CTRL ((volatile uint32_t *)0xfe0008c0) +#define P_CLKTREE_PWM_CLK_AB_CTRL ((volatile uint32_t *)0xfe0008c4) +#define P_CLKTREE_PWM_CLK_CD_CTRL ((volatile uint32_t *)0xfe0008c8) +#define P_CLKTREE_PWM_CLK_EF_CTRL ((volatile uint32_t *)0xfe0008cc) +#define P_CLKTREE_SPICC_CLK_CTRL ((volatile uint32_t *)0xfe0008d0) +#define P_CLKTREE_TS_CLK_CTRL ((volatile uint32_t *)0xfe0008d4) +#define P_CLKTREE_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfe0008d8) +#define P_CLKTREE_USB_BUSCLK_CTRL ((volatile uint32_t *)0xfe0008dc) +#define P_CLKTREE_SD_EMMC_CLK_CTRL ((volatile uint32_t *)0xfe0008e0) +#define P_CLKTREE_CECA_CLK_CTRL0 ((volatile uint32_t *)0xfe0008e4) +#define P_CLKTREE_CECA_CLK_CTRL1 ((volatile uint32_t *)0xfe0008e8) +#define P_CLKTREE_CECB_CLK_CTRL0 ((volatile uint32_t *)0xfe0008ec) +#define P_CLKTREE_CECB_CLK_CTRL1 ((volatile uint32_t *)0xfe0008f0) +#define P_CLKTREE_PSRAM_CLK_CTRL ((volatile uint32_t *)0xfe0008f4) +#define P_CLKTREE_DMC_CLK_CTRL ((volatile uint32_t *)0xfe0008f8) +#define P_CLKTREE_FCLK_DIV1_SEL ((volatile uint32_t *)0xfe0008fc) +#define P_CLKTREE_TST_CTRL0 ((volatile uint32_t *)0xfe000900) +//======================================================================== +// APB0_CEC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000c00 +// ----------------------------------------------- +#define P_CECA_GEN_CNTL ((volatile uint32_t *)0xfe000c00) +#define P_CECA_RW_REG ((volatile uint32_t *)0xfe000c04) +#define P_CECA_INTR_MASKN ((volatile uint32_t *)0xfe000c08) +#define P_CECA_INTR_CLR ((volatile uint32_t *)0xfe000c0c) +#define P_CECA_INTR_STAT ((volatile uint32_t *)0xfe000c10) +#define P_CECB_GEN_CNTL ((volatile uint32_t *)0xfe000c40) +#define P_CECB_RW_REG ((volatile uint32_t *)0xfe000c44) +#define P_CECB_INTR_MASKN ((volatile uint32_t *)0xfe000c48) +#define P_CECB_INTR_CLR ((volatile uint32_t *)0xfe000c4c) +#define P_CECB_INTR_STAT ((volatile uint32_t *)0xfe000c50) +//======================================================================== +// APB0_IR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001000 +// ----------------------------------------------- +#define P_IRCTRL_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001000) +#define P_IRCTRL_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001004) +#define P_IRCTRL_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001008) +#define P_IRCTRL_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00100c) +#define P_IRCTRL_IR_DEC_REG0 ((volatile uint32_t *)0xfe001010) +#define P_IRCTRL_IR_DEC_FRAME ((volatile uint32_t *)0xfe001014) +#define P_IRCTRL_IR_DEC_STATUS ((volatile uint32_t *)0xfe001018) +#define P_IRCTRL_IR_DEC_REG1 ((volatile uint32_t *)0xfe00101c) +#define P_IRCTRL_MF_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001040) +#define P_IRCTRL_MF_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001044) +#define P_IRCTRL_MF_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001048) +#define P_IRCTRL_MF_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00104c) +#define P_IRCTRL_MF_IR_DEC_REG0 ((volatile uint32_t *)0xfe001050) +#define P_IRCTRL_MF_IR_DEC_FRAME ((volatile uint32_t *)0xfe001054) +#define P_IRCTRL_MF_IR_DEC_STATUS ((volatile uint32_t *)0xfe001058) +#define P_IRCTRL_MF_IR_DEC_REG1 ((volatile uint32_t *)0xfe00105c) +#define P_IRCTRL_MF_IR_DEC_REG2 ((volatile uint32_t *)0xfe001060) +#define P_IRCTRL_MF_IR_DEC_DURATN2 ((volatile uint32_t *)0xfe001064) +#define P_IRCTRL_MF_IR_DEC_DURATN3 ((volatile uint32_t *)0xfe001068) +#define P_IRCTRL_MF_IR_DEC_FRAME1 ((volatile uint32_t *)0xfe00106c) +#define P_IRCTRL_MF_IR_DEC_STATUS1 ((volatile uint32_t *)0xfe001070) +#define P_IRCTRL_MF_IR_DEC_STATUS2 ((volatile uint32_t *)0xfe001074) +#define P_IRCTRL_MF_IR_DEC_REG3 ((volatile uint32_t *)0xfe001078) +#define P_IRCTRL_MF_IR_DEC_FRAME_RSV0 ((volatile uint32_t *)0xfe00107c) +#define P_IRCTRL_MF_IR_DEC_FRAME_RSV1 ((volatile uint32_t *)0xfe001080) +#define P_IRCTRL_MF_IR_DEC_FILTE ((volatile uint32_t *)0xfe001084) +#define P_IRCTRL_MF_IR_DEC_IRQ_CTL ((volatile uint32_t *)0xfe001088) +#define P_IRCTRL_MF_IR_DEC_FIFO_CTL ((volatile uint32_t *)0xfe00108c) +#define P_IRCTRL_MF_IR_DEC_WIDTH_NEW ((volatile uint32_t *)0xfe001090) +#define P_IRCTRL_MF_IR_DEC_REPEAT_DET ((volatile uint32_t *)0xfe001094) +#define P_IRCTRL_IR_DEC_DEMOD_CNTL0 ((volatile uint32_t *)0xfe0010c0) +#define P_IRCTRL_IR_DEC_DEMOD_CNTL1 ((volatile uint32_t *)0xfe0010c4) +#define P_IRCTRL_IR_DEC_DEMOD_IIR_THD ((volatile uint32_t *)0xfe0010c8) +#define P_IRCTRL_IR_DEC_DEMOD_THD0 ((volatile uint32_t *)0xfe0010cc) +#define P_IRCTRL_IR_DEC_DEMOD_THD1 ((volatile uint32_t *)0xfe0010d0) +#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((volatile uint32_t *)0xfe0010d4) +#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((volatile uint32_t *)0xfe0010d8) +#define P_IRCTRL_IR_DEC_DEMOD_CNT0 ((volatile uint32_t *)0xfe0010dc) +#define P_IRCTRL_IR_DEC_DEMOD_CNT1 ((volatile uint32_t *)0xfe0010e0) +#define P_IRCTRL_IR_BLASTER_ADDR0 ((volatile uint32_t *)0xfe00110c) +#define P_IRCTRL_IR_BLASTER_ADDR1 ((volatile uint32_t *)0xfe001110) +#define P_IRCTRL_IR_BLASTER_ADDR2 ((volatile uint32_t *)0xfe001114) +#define P_IRCTRL_IR_BLASTER_ADDR3 ((volatile uint32_t *)0xfe001118) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001400 +// ----------------------------------------------- +#define P_I2C_M_A_CONTROL_REG ((volatile uint32_t *)0xfe001400) +#define P_I2C_M_A_SLAVE_ADDR ((volatile uint32_t *)0xfe001404) +#define P_I2C_M_A_TOKEN_LIST0 ((volatile uint32_t *)0xfe001408) +#define P_I2C_M_A_TOKEN_LIST1 ((volatile uint32_t *)0xfe00140c) +#define P_I2C_M_A_WDATA_REG0 ((volatile uint32_t *)0xfe001410) +#define P_I2C_M_A_WDATA_REG1 ((volatile uint32_t *)0xfe001414) +#define P_I2C_M_A_RDATA_REG0 ((volatile uint32_t *)0xfe001418) +#define P_I2C_M_A_RDATA_REG1 ((volatile uint32_t *)0xfe00141c) +#define P_I2C_M_A_TIMEOUT_TH ((volatile uint32_t *)0xfe001420) +//======================================================================== +// APB0_I2C_S - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001800 +// ----------------------------------------------- +#define P_I2C_S_A_CONTROL_REG ((volatile uint32_t *)0xfe001800) +#define P_I2C_S_A_SEND_REG ((volatile uint32_t *)0xfe001804) +#define P_I2C_S_A_RECV_REG ((volatile uint32_t *)0xfe001808) +#define P_I2C_S_A_CNTL1_REG ((volatile uint32_t *)0xfe00180c) +//======================================================================== +// APB0_UART_A - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001c00 +// ----------------------------------------------- +#define P_UART_A_WFIFO ((volatile uint32_t *)0xfe001c00) +#define P_UART_A_RFIFO ((volatile uint32_t *)0xfe001c04) +#define P_UART_A_CONTROL ((volatile uint32_t *)0xfe001c08) +#define P_UART_A_STATUS ((volatile uint32_t *)0xfe001c0c) +#define P_UART_A_MISC ((volatile uint32_t *)0xfe001c10) +#define P_UART_A_REG5 ((volatile uint32_t *)0xfe001c14) +//======================================================================== +// APB0_UART_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002000 +// ----------------------------------------------- +#define P_UART_B_WFIFO ((volatile uint32_t *)0xfe002000) +#define P_UART_B_RFIFO ((volatile uint32_t *)0xfe002004) +#define P_UART_B_CONTROL ((volatile uint32_t *)0xfe002008) +#define P_UART_B_STATUS ((volatile uint32_t *)0xfe00200c) +#define P_UART_B_MISC ((volatile uint32_t *)0xfe002010) +#define P_UART_B_REG5 ((volatile uint32_t *)0xfe002014) +//======================================================================== +// APB0_PWM_AB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002400 +// ----------------------------------------------- +#define P_PWMAB_PWM_A ((volatile uint32_t *)0xfe002400) +#define P_PWMAB_PWM_B ((volatile uint32_t *)0xfe002404) +#define P_PWMAB_MISC_REG_AB ((volatile uint32_t *)0xfe002408) +#define P_PWMAB_DELTA_SIGMA_AB ((volatile uint32_t *)0xfe00240c) +#define P_PWMAB_TIME_AB ((volatile uint32_t *)0xfe002410) +#define P_PWMAB_A2 ((volatile uint32_t *)0xfe002414) +#define P_PWMAB_B2 ((volatile uint32_t *)0xfe002418) +#define P_PWMAB_BLINK_AB ((volatile uint32_t *)0xfe00241c) +#define P_PWMAB_LOCK_AB ((volatile uint32_t *)0xfe002420) +//======================================================================== +// APB0_PWM_CD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002800 +// ----------------------------------------------- +#define P_PWMCD_PWM_C ((volatile uint32_t *)0xfe002800) +#define P_PWMCD_PWM_D ((volatile uint32_t *)0xfe002804) +#define P_PWMCD_MISC_REG_CD ((volatile uint32_t *)0xfe002808) +#define P_PWMCD_DELTA_SIGMA_CD ((volatile uint32_t *)0xfe00280c) +#define P_PWMCD_TIME_CD ((volatile uint32_t *)0xfe002810) +#define P_PWMCD_C2 ((volatile uint32_t *)0xfe002814) +#define P_PWMCD_D2 ((volatile uint32_t *)0xfe002818) +#define P_PWMCD_BLINK_CD ((volatile uint32_t *)0xfe00281c) +#define P_PWMCD_LOCK_CD ((volatile uint32_t *)0xfe002820) +//======================================================================== +// APB0_SARADC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002c00 +// ----------------------------------------------- +#define P_SAR_ADC_REG0 ((volatile uint32_t *)0xfe002c00) +#define P_SAR_ADC_CHAN_LIST ((volatile uint32_t *)0xfe002c04) +#define P_SAR_ADC_AVG_CNTL ((volatile uint32_t *)0xfe002c08) +#define P_SAR_ADC_REG3 ((volatile uint32_t *)0xfe002c0c) +#define P_SAR_ADC_DELAY ((volatile uint32_t *)0xfe002c10) +#define P_SAR_ADC_LAST_RD ((volatile uint32_t *)0xfe002c14) +#define P_SAR_ADC_FIFO_RD ((volatile uint32_t *)0xfe002c18) +#define P_SAR_ADC_AUX_SW ((volatile uint32_t *)0xfe002c1c) +#define P_SAR_ADC_CHAN_10_SW ((volatile uint32_t *)0xfe002c20) +#define P_SAR_ADC_DETECT_IDLE_SW ((volatile uint32_t *)0xfe002c24) +#define P_SAR_ADC_DELTA_10 ((volatile uint32_t *)0xfe002c28) +#define P_SAR_ADC_REG11 ((volatile uint32_t *)0xfe002c2c) +#define P_SAR_ADC_REG12 ((volatile uint32_t *)0xfe002c30) +#define P_SAR_ADC_REG13 ((volatile uint32_t *)0xfe002c34) +#define P_SAR_ADC_CHNL01 ((volatile uint32_t *)0xfe002c38) +#define P_SAR_ADC_CHNL23 ((volatile uint32_t *)0xfe002c3c) +#define P_SAR_ADC_CHNL45 ((volatile uint32_t *)0xfe002c40) +#define P_SAR_ADC_CHNL67 ((volatile uint32_t *)0xfe002c44) +//======================================================================== +// JTAGCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003000 +// ----------------------------------------------- +#define P_JTAGCTRL_CTRL0 ((volatile uint32_t *)0xfe003000) +#define P_JTAGCTRL_PWD_CTRL0 ((volatile uint32_t *)0xfe003004) +#define P_JTAGCTRL_PWD_ADDR0 ((volatile uint32_t *)0xfe003008) +#define P_JTAGCTRL_PWD_ADDR1 ((volatile uint32_t *)0xfe00300c) +#define P_JTAGCTRL_PWD_ADDR2 ((volatile uint32_t *)0xfe003010) +#define P_JTAGCTRL_PWD_ADDR3 ((volatile uint32_t *)0xfe003014) +#define P_JTAGCTRL_PWD_VALUE0 ((volatile uint32_t *)0xfe003018) +#define P_JTAGCTRL_PWD_VALUE1 ((volatile uint32_t *)0xfe00301c) +#define P_JTAGCTRL_PWD_VALUE2 ((volatile uint32_t *)0xfe003020) +#define P_JTAGCTRL_PWD_VALUE3 ((volatile uint32_t *)0xfe003024) +#define P_JTAGCTRL_PWD_STS ((volatile uint32_t *)0xfe003028) +//======================================================================== +// APB0_MSR_CLK - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003400 +// ----------------------------------------------- +#define P_MSR_CLK_REG0 ((volatile uint32_t *)0xfe003400) +#define P_MSR_CLK_REG1 ((volatile uint32_t *)0xfe003404) +#define P_MSR_CLK_REG2 ((volatile uint32_t *)0xfe003408) +#define P_MSR_CLK_REG3 ((volatile uint32_t *)0xfe00340c) +#define P_MSR_CLK_REG4 ((volatile uint32_t *)0xfe003410) +#define P_MSR_CLK_REG5 ((volatile uint32_t *)0xfe003414) +#define P_MSR_CLK_DUTY ((volatile uint32_t *)0xfe003418) +//======================================================================== +// APB0_SPICCA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003800 +// ----------------------------------------------- +#define P_SPICC_A_RXDATA ((volatile uint32_t *)0xfe003800) +#define P_SPICC_A_TXDATA ((volatile uint32_t *)0xfe003804) +#define P_SPICC_A_CONREG ((volatile uint32_t *)0xfe003808) +#define P_SPICC_A_INTREG ((volatile uint32_t *)0xfe00380c) +#define P_SPICC_A_DMAREG ((volatile uint32_t *)0xfe003810) +#define P_SPICC_A_STATREG ((volatile uint32_t *)0xfe003814) +#define P_SPICC_A_PERIODREG ((volatile uint32_t *)0xfe003818) +#define P_SPICC_A_TESTREG ((volatile uint32_t *)0xfe00381c) +#define P_SPICC_A_DRADDR ((volatile uint32_t *)0xfe003820) +#define P_SPICC_A_DWADDR ((volatile uint32_t *)0xfe003824) +#define P_SPICC_A_LD_CNTL0 ((volatile uint32_t *)0xfe003828) +#define P_SPICC_A_LD_CNTL1 ((volatile uint32_t *)0xfe00382c) +#define P_SPICC_A_LD_RADDR ((volatile uint32_t *)0xfe003830) +#define P_SPICC_A_LD_WADDR ((volatile uint32_t *)0xfe003834) +#define P_SPICC_A_ENHANCE_CNTL ((volatile uint32_t *)0xfe003838) +#define P_SPICC_A_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe00383c) +#define P_SPICC_A_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003840) +//======================================================================== +// APB0_SPICCB_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003c00 +// ----------------------------------------------- +#define P_SPICC_B_RXDATA ((volatile uint32_t *)0xfe003c00) +#define P_SPICC_B_TXDATA ((volatile uint32_t *)0xfe003c04) +#define P_SPICC_B_CONREG ((volatile uint32_t *)0xfe003c08) +#define P_SPICC_B_INTREG ((volatile uint32_t *)0xfe003c0c) +#define P_SPICC_B_DMAREG ((volatile uint32_t *)0xfe003c10) +#define P_SPICC_B_STATREG ((volatile uint32_t *)0xfe003c14) +#define P_SPICC_B_PERIODREG ((volatile uint32_t *)0xfe003c18) +#define P_SPICC_B_TESTREG ((volatile uint32_t *)0xfe003c1c) +#define P_SPICC_B_DRADDR ((volatile uint32_t *)0xfe003c20) +#define P_SPICC_B_DWADDR ((volatile uint32_t *)0xfe003c24) +#define P_SPICC_B_LD_CNTL0 ((volatile uint32_t *)0xfe003c28) +#define P_SPICC_B_LD_CNTL1 ((volatile uint32_t *)0xfe003c2c) +#define P_SPICC_B_LD_RADDR ((volatile uint32_t *)0xfe003c30) +#define P_SPICC_B_LD_WADDR ((volatile uint32_t *)0xfe003c34) +#define P_SPICC_B_ENHANCE_CNTL ((volatile uint32_t *)0xfe003c38) +#define P_SPICC_B_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe003c3c) +#define P_SPICC_B_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003c40) +//======================================================================== +// USBCTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004000 +// ----------------------------------------------- +#define P_USB_CTRL0 ((volatile uint32_t *)0xfe004000) +#define P_USB_CTRL1 ((volatile uint32_t *)0xfe004004) +#define P_USB_CTRL2 ((volatile uint32_t *)0xfe004008) +#define P_USB_CTRL3 ((volatile uint32_t *)0xfe00400c) +#define P_USB_CTRL4 ((volatile uint32_t *)0xfe004010) +#define P_USB_CTRL5 ((volatile uint32_t *)0xfe004014) +#define P_USB_CTRL6 ((volatile uint32_t *)0xfe004018) +#define P_USB_CTRL7 ((volatile uint32_t *)0xfe00401c) +#define P_USB_CTRL8 ((volatile uint32_t *)0xfe004020) +#define P_USB_CTRL9 ((volatile uint32_t *)0xfe004024) +#define P_USB_CTRL10 ((volatile uint32_t *)0xfe004028) +#define P_USB_CTRL11 ((volatile uint32_t *)0xfe00402c) +#define P_USB_CTRL12 ((volatile uint32_t *)0xfe004030) +#define P_USB_CTRL13 ((volatile uint32_t *)0xfe004034) +#define P_USB_CTRL14 ((volatile uint32_t *)0xfe004038) +#define P_USB_CTRL15 ((volatile uint32_t *)0xfe00403c) +#define P_USB_CTRL16 ((volatile uint32_t *)0xfe004040) +#define P_USB_CTRL17 ((volatile uint32_t *)0xfe004044) +#define P_USB_CTRL18 ((volatile uint32_t *)0xfe004048) +#define P_USB_CTRL19 ((volatile uint32_t *)0xfe00404c) +#define P_USB_CTRL20 ((volatile uint32_t *)0xfe004050) +#define P_USB_CTRL21 ((volatile uint32_t *)0xfe004054) +#define P_USB_CTRL22 ((volatile uint32_t *)0xfe004058) +#define P_USB_CTRL23 ((volatile uint32_t *)0xfe00405c) +#define P_USB_CTRL24 ((volatile uint32_t *)0xfe004060) +#define P_USB_CTRL25 ((volatile uint32_t *)0xfe004064) +#define P_USB_CTRL26 ((volatile uint32_t *)0xfe004068) +#define P_USB_CTRL27 ((volatile uint32_t *)0xfe00406c) +#define P_USB_CTRL28 ((volatile uint32_t *)0xfe004070) +#define P_USB_CTRL29 ((volatile uint32_t *)0xfe004074) +#define P_USB_CTRL30 ((volatile uint32_t *)0xfe004078) +#define P_USB_CTRL31 ((volatile uint32_t *)0xfe00407c) +//======================================================================== +// APB0_ACODEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004800 +// ----------------------------------------------- +#define P_ACODEC_0 ((volatile uint32_t *)0xfe004800) +#define P_ACODEC_1 ((volatile uint32_t *)0xfe004804) +#define P_ACODEC_2 ((volatile uint32_t *)0xfe004808) +#define P_ACODEC_3 ((volatile uint32_t *)0xfe00480c) +#define P_ACODEC_4 ((volatile uint32_t *)0xfe004810) +#define P_ACODEC_5 ((volatile uint32_t *)0xfe004814) +#define P_ACODEC_6 ((volatile uint32_t *)0xfe004818) +#define P_ACODEC_7 ((volatile uint32_t *)0xfe00481c) +#define P_ACODEC_8 ((volatile uint32_t *)0xfe004820) +#define P_ACODEC_9 ((volatile uint32_t *)0xfe004824) +#define P_ACODEC_STS0 ((volatile uint32_t *)0xfe004840) +//======================================================================== +// APB0_TEMP_SENSOR - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004c00 +// ----------------------------------------------- +#define P_TS_CFG_REG1 ((volatile uint32_t *)0xfe004c04) +#define P_TS_CFG_REG2 ((volatile uint32_t *)0xfe004c08) +#define P_TS_CFG_REG3 ((volatile uint32_t *)0xfe004c0c) +#define P_TS_CFG_REG4 ((volatile uint32_t *)0xfe004c10) +#define P_TS_CFG_REG5 ((volatile uint32_t *)0xfe004c14) +#define P_TS_CFG_REG6 ((volatile uint32_t *)0xfe004c18) +#define P_TS_CFG_REG7 ((volatile uint32_t *)0xfe004c1c) +#define P_TS_STAT0 ((volatile uint32_t *)0xfe004c40) +#define P_TS_STAT1 ((volatile uint32_t *)0xfe004c44) +#define P_TS_STAT2 ((volatile uint32_t *)0xfe004c48) +#define P_TS_STAT3 ((volatile uint32_t *)0xfe004c4c) +#define P_TS_STAT4 ((volatile uint32_t *)0xfe004c50) +#define P_TS_STAT5 ((volatile uint32_t *)0xfe004c54) +#define P_TS_STAT6 ((volatile uint32_t *)0xfe004c58) +#define P_TS_STAT7 ((volatile uint32_t *)0xfe004c5c) +#define P_TS_STAT8 ((volatile uint32_t *)0xfe004c60) +#define P_TS_STAT9 ((volatile uint32_t *)0xfe004c64) +//======================================================================== +// APB0_KL_EFUSE_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005000 +// ----------------------------------------------- +// +// Reading file: ../crypto/crypto_reg.h +// +#define P_OTP_TEE_RDY ((volatile uint32_t *)0xfe005000) +#define P_OTP_TEE_CHK ((volatile uint32_t *)0xfe005004) +#define P_OTP_TEE_CFG ((volatile uint32_t *)0xfe005008) +#define P_OTP_TEE_WR_DAT0 ((volatile uint32_t *)0xfe005010) +#define P_OTP_TEE_WR_DAT1 ((volatile uint32_t *)0xfe005014) +#define P_OTP_TEE_WR_DAT2 ((volatile uint32_t *)0xfe005018) +#define P_OTP_TEE_WR_DAT3 ((volatile uint32_t *)0xfe00501c) +#define P_OTP_TEE_RD_DAT0 ((volatile uint32_t *)0xfe005020) +#define P_OTP_TEE_RD_DAT1 ((volatile uint32_t *)0xfe005024) +#define P_OTP_TEE_RD_DAT2 ((volatile uint32_t *)0xfe005028) +#define P_OTP_TEE_RD_DAT3 ((volatile uint32_t *)0xfe00502c) +#define P_OTP_RMA_PW0 ((volatile uint32_t *)0xfe005030) +#define P_OTP_RMA_PW1 ((volatile uint32_t *)0xfe005034) +#define P_OTP_RMA_PW2 ((volatile uint32_t *)0xfe005038) +#define P_OTP_RMA_PW3 ((volatile uint32_t *)0xfe00503c) +#define P_OTP_REE_RDY ((volatile uint32_t *)0xfe005040) +#define P_OTP_REE_CHK ((volatile uint32_t *)0xfe005044) +#define P_OTP_REE_CFG ((volatile uint32_t *)0xfe005048) +#define P_OTP_REE_RD_DAT0 ((volatile uint32_t *)0xfe005050) +#define P_OTP_REE_RD_DAT1 ((volatile uint32_t *)0xfe005054) +#define P_OTP_REE_RD_DAT2 ((volatile uint32_t *)0xfe005058) +#define P_OTP_REE_RD_DAT3 ((volatile uint32_t *)0xfe00505c) +#define P_OTP_LIC0 ((volatile uint32_t *)0xfe005060) +#define P_OTP_LIC1 ((volatile uint32_t *)0xfe005064) +#define P_OTP_LIC2 ((volatile uint32_t *)0xfe005068) +#define P_OTP_LIC3 ((volatile uint32_t *)0xfe00506c) +#define P_RNG_SEC_CONFIG_REG1 ((volatile uint32_t *)0xfe005104) +#define P_RNG_SEC_CONFIG_REG2 ((volatile uint32_t *)0xfe005108) +#define P_RNG_SEC_DATA ((volatile uint32_t *)0xfe005110) +#define P_RNG_SEC_STS ((volatile uint32_t *)0xfe005114) +#define P_RNG_USR_DATA ((volatile uint32_t *)0xfe005118) +#define P_RNG_USR_STS ((volatile uint32_t *)0xfe00511c) +#define P_KTE_SLOT0 ((volatile uint32_t *)0xfe005180) +#define P_KTE_SLOT1 ((volatile uint32_t *)0xfe005184) +#define P_KTE_SLOT2 ((volatile uint32_t *)0xfe005188) +#define P_KTE_SLOT3 ((volatile uint32_t *)0xfe00518c) +#define P_KTE_SLOT4 ((volatile uint32_t *)0xfe005190) +#define P_KTE_SLOT5 ((volatile uint32_t *)0xfe005194) +#define P_KTE_SLOT6 ((volatile uint32_t *)0xfe005198) +#define P_KTE_SLOT7 ((volatile uint32_t *)0xfe00519c) +#define P_MKL_TEE_RDY ((volatile uint32_t *)0xfe005200) +#define P_MKL_TEE_CHK ((volatile uint32_t *)0xfe005204) +#define P_MKL_TEE_CFG ((volatile uint32_t *)0xfe005208) +#define P_MKL_TEE_EK ((volatile uint32_t *)0xfe005210) +#define P_MKL_REE_RDY ((volatile uint32_t *)0xfe005280) +#define P_MKL_REE_CHK ((volatile uint32_t *)0xfe005284) +#define P_MKL_REE_CFG ((volatile uint32_t *)0xfe005288) +#define P_MKL_REE_EK ((volatile uint32_t *)0xfe005290) +// +// Closing file: ../crypto/crypto_reg.h +// +//======================================================================== +// APB0_PWM_EF - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005400 +// ----------------------------------------------- +#define P_PWMEF_PWM_E ((volatile uint32_t *)0xfe005400) +#define P_PWMEF_PWM_F ((volatile uint32_t *)0xfe005404) +#define P_PWMEF_MISC_REG_EF ((volatile uint32_t *)0xfe005408) +#define P_PWMEF_DELTA_SIGMA_EF ((volatile uint32_t *)0xfe00540c) +#define P_PWMEF_TIME_EF ((volatile uint32_t *)0xfe005410) +#define P_PWMEF_E2 ((volatile uint32_t *)0xfe005414) +#define P_PWMEF_F2 ((volatile uint32_t *)0xfe005418) +#define P_PWMEF_BLINK_EF ((volatile uint32_t *)0xfe00541c) +#define P_PWMEF_LOCK_EF ((volatile uint32_t *)0xfe005420) +//======================================================================== +// APB0_SYS_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005800 +// ----------------------------------------------- +#define P_SYSCTRL_METAL_REV0 ((volatile uint32_t *)0xfe005800) +#define P_SYSCTRL_METAL_REV1 ((volatile uint32_t *)0xfe005804) +//`define SYSCTRL_PROD_ENABLE 8'h0a +#define P_SYSCTRL_CHIP_ID ((volatile uint32_t *)0xfe00582c) +#define P_SYSCTRL_WRITEONCE1_REG0 ((volatile uint32_t *)0xfe005840) +#define P_SYSCTRL_WRITEONCE1_STICKY_REG0 ((volatile uint32_t *)0xfe005844) +#define P_SYSCTRL_WRITEONCE1_SEC_REG0 ((volatile uint32_t *)0xfe005848) +#define P_SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe00584c) +#define P_SYSCTRL_WRITEONCE_REG0 ((volatile uint32_t *)0xfe005850) +#define P_SYSCTRL_WRITEONCE_REG1 ((volatile uint32_t *)0xfe005854) +#define P_SYSCTRL_WRITEONCE_SEC_REG0 ((volatile uint32_t *)0xfe005858) +#define P_SYSCTRL_WRITEONCE_STICKY_REG0 ((volatile uint32_t *)0xfe00585c) +#define P_SYSCTRL_WRITEONCE_STICKY_REG1 ((volatile uint32_t *)0xfe005860) +#define P_SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe005864) +#define P_SYSCTRL_TIMERA_CTRL ((volatile uint32_t *)0xfe0058c0) +#define P_SYSCTRL_TIMERA ((volatile uint32_t *)0xfe0058c4) +#define P_SYSCTRL_TIMERB_CTRL ((volatile uint32_t *)0xfe0058c8) +#define P_SYSCTRL_TIMERB ((volatile uint32_t *)0xfe0058cc) +#define P_SYSCTRL_TIMERC_CTRL ((volatile uint32_t *)0xfe0058d0) +#define P_SYSCTRL_TIMERC ((volatile uint32_t *)0xfe0058d4) +#define P_SYSCTRL_TIMERD_CTRL ((volatile uint32_t *)0xfe0058d8) +#define P_SYSCTRL_TIMERD ((volatile uint32_t *)0xfe0058dc) +#define P_SYSCTRL_SEC_TIMERA_CTRL ((volatile uint32_t *)0xfe0058e0) +#define P_SYSCTRL_SEC_TIMERA ((volatile uint32_t *)0xfe0058e4) +#define P_SYSCTRL_TIMERE_CTRL ((volatile uint32_t *)0xfe005900) +#define P_SYSCTRL_TIMERE ((volatile uint32_t *)0xfe005904) +#define P_SYSCTRL_TIMERE_HI ((volatile uint32_t *)0xfe005908) +#define P_SYSCTRL_TIMERF_CTRL ((volatile uint32_t *)0xfe00590c) +#define P_SYSCTRL_TIMERF ((volatile uint32_t *)0xfe005910) +#define P_SYSCTRL_TIMERF_HI ((volatile uint32_t *)0xfe005914) +#define P_SYSCTRL_SEC_TIMERE_CTRL ((volatile uint32_t *)0xfe005918) +#define P_SYSCTRL_SEC_TIMERE ((volatile uint32_t *)0xfe00591c) +#define P_SYSCTRL_SEC_TIMERE_HI ((volatile uint32_t *)0xfe005920) +#define P_SYSCTRL_OSC_RING_CTRL0 ((volatile uint32_t *)0xfe005940) +#define P_SYSCTRL_SEC_DDR_AXI_SEL ((volatile uint32_t *)0xfe005944) +#define P_SYSCTRL_AM2AXI_CTRL0 ((volatile uint32_t *)0xfe005948) +#define P_SYSCTRL_AM2AXI_STS ((volatile uint32_t *)0xfe00594c) +#define P_SYSCTRL_POC ((volatile uint32_t *)0xfe005980) +//`define SYSCTRL_PROD_PWD_VALUE0 8'h80 +//`define SYSCTRL_PROD_PWD_VALUE1 8'h81 +//`define SYSCTRL_PROD_PWD_VALUE2 8'h82 +//`define SYSCTRL_PROD_PWD_VALUE3 8'h83 +//`define SYSCTRL_PROD_STATUS 8'h84 +#define P_SYSCTRL_DEBUG_REG0 ((volatile uint32_t *)0xfe005a40) +#define P_SYSCTRL_DEBUG_REG1 ((volatile uint32_t *)0xfe005a44) +#define P_SYSCTRL_DEBUG_REG2 ((volatile uint32_t *)0xfe005a48) +#define P_SYSCTRL_DEBUG_REG3 ((volatile uint32_t *)0xfe005a4c) +#define P_SYSCTRL_DEBUG_REG4 ((volatile uint32_t *)0xfe005a50) +#define P_SYSCTRL_DEBUG_REG5 ((volatile uint32_t *)0xfe005a54) +#define P_SYSCTRL_DEBUG_REG6 ((volatile uint32_t *)0xfe005a58) +#define P_SYSCTRL_DEBUG_REG7 ((volatile uint32_t *)0xfe005a5c) +#define P_SYSCTRL_STATUS_REG0 ((volatile uint32_t *)0xfe005a80) +#define P_SYSCTRL_STATUS_REG1 ((volatile uint32_t *)0xfe005a84) +#define P_SYSCTRL_STATUS_REG2 ((volatile uint32_t *)0xfe005a88) +#define P_SYSCTRL_STATUS_REG3 ((volatile uint32_t *)0xfe005a8c) +#define P_SYSCTRL_STATUS_REG4 ((volatile uint32_t *)0xfe005a90) +#define P_SYSCTRL_STATUS_REG5 ((volatile uint32_t *)0xfe005a94) +#define P_SYSCTRL_STATUS_REG6 ((volatile uint32_t *)0xfe005a98) +#define P_SYSCTRL_STATUS_REG7 ((volatile uint32_t *)0xfe005a9c) +#define P_SYSCTRL_STICKY_REG0 ((volatile uint32_t *)0xfe005ac0) +#define P_SYSCTRL_STICKY_REG1 ((volatile uint32_t *)0xfe005ac4) +#define P_SYSCTRL_STICKY_REG2 ((volatile uint32_t *)0xfe005ac8) +#define P_SYSCTRL_STICKY_REG3 ((volatile uint32_t *)0xfe005acc) +#define P_SYSCTRL_STICKY_REG4 ((volatile uint32_t *)0xfe005ad0) +#define P_SYSCTRL_STICKY_REG5 ((volatile uint32_t *)0xfe005ad4) +#define P_SYSCTRL_STICKY_REG6 ((volatile uint32_t *)0xfe005ad8) +#define P_SYSCTRL_STICKY_REG7 ((volatile uint32_t *)0xfe005adc) +#define P_SYSCTRL_SEC_STATUS_REG0 ((volatile uint32_t *)0xfe005b00) +#define P_SYSCTRL_SEC_STATUS_REG1 ((volatile uint32_t *)0xfe005b04) +#define P_SYSCTRL_SEC_STATUS_REG2 ((volatile uint32_t *)0xfe005b08) +#define P_SYSCTRL_SEC_STATUS_REG3 ((volatile uint32_t *)0xfe005b0c) +#define P_SYSCTRL_SEC_STATUS_REG4 ((volatile uint32_t *)0xfe005b10) +#define P_SYSCTRL_SEC_STATUS_REG5 ((volatile uint32_t *)0xfe005b14) +#define P_SYSCTRL_SEC_STATUS_REG6 ((volatile uint32_t *)0xfe005b18) +#define P_SYSCTRL_SEC_STATUS_REG7 ((volatile uint32_t *)0xfe005b1c) +#define P_SYSCTRL_SEC_STATUS_REG8 ((volatile uint32_t *)0xfe005b20) +#define P_SYSCTRL_SEC_STATUS_REG9 ((volatile uint32_t *)0xfe005b24) +#define P_SYSCTRL_SEC_STATUS_REG10 ((volatile uint32_t *)0xfe005b28) +#define P_SYSCTRL_SEC_STATUS_REG11 ((volatile uint32_t *)0xfe005b2c) +#define P_SYSCTRL_SEC_STATUS_REG12 ((volatile uint32_t *)0xfe005b30) +#define P_SYSCTRL_SEC_STATUS_REG13 ((volatile uint32_t *)0xfe005b34) +#define P_SYSCTRL_SEC_STATUS_REG14 ((volatile uint32_t *)0xfe005b38) +#define P_SYSCTRL_SEC_STATUS_REG15 ((volatile uint32_t *)0xfe005b3c) +#define P_SYSCTRL_SEC_STATUS_REG16 ((volatile uint32_t *)0xfe005b40) +#define P_SYSCTRL_SEC_STATUS_REG17 ((volatile uint32_t *)0xfe005b44) +#define P_SYSCTRL_SEC_STATUS_REG18 ((volatile uint32_t *)0xfe005b48) +#define P_SYSCTRL_SEC_STATUS_REG19 ((volatile uint32_t *)0xfe005b4c) +#define P_SYSCTRL_SEC_STATUS_REG20 ((volatile uint32_t *)0xfe005b50) +#define P_SYSCTRL_SEC_STATUS_REG21 ((volatile uint32_t *)0xfe005b54) +#define P_SYSCTRL_SEC_STATUS_REG22 ((volatile uint32_t *)0xfe005b58) +#define P_SYSCTRL_SEC_STATUS_REG23 ((volatile uint32_t *)0xfe005b5c) +#define P_SYSCTRL_SEC_STICKY_REG0 ((volatile uint32_t *)0xfe005b80) +#define P_SYSCTRL_SEC_STICKY_REG1 ((volatile uint32_t *)0xfe005b84) +#define P_SYSCTRL_SEC_STICKY_REG2 ((volatile uint32_t *)0xfe005b88) +#define P_SYSCTRL_SEC_STICKY_REG3 ((volatile uint32_t *)0xfe005b8c) +#define P_SYSCTRL_SEC_STICKY_REG4 ((volatile uint32_t *)0xfe005b90) +#define P_SYSCTRL_SEC_STICKY_REG5 ((volatile uint32_t *)0xfe005b94) +#define P_SYSCTRL_SEC_STICKY_REG6 ((volatile uint32_t *)0xfe005b98) +#define P_SYSCTRL_SEC_STICKY_REG7 ((volatile uint32_t *)0xfe005b9c) +#define P_SYSCTRL_MSG_INDEX0_STICKY ((volatile uint32_t *)0xfe005bc0) +#define P_SYSCTRL_MSG_INDEX1_STICKY ((volatile uint32_t *)0xfe005bc4) +#define P_SYSCTRL_MSG_INDEX2_STICKY ((volatile uint32_t *)0xfe005bc8) +#define P_SYSCTRL_MSG_INDEX3_STICKY ((volatile uint32_t *)0xfe005bcc) +//======================================================================== +// APB0_I2C_M_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005c00 +// ----------------------------------------------- +#define P_I2C_M_B_CONTROL_REG ((volatile uint32_t *)0xfe005c00) +#define P_I2C_M_B_SLAVE_ADDR ((volatile uint32_t *)0xfe005c04) +#define P_I2C_M_B_TOKEN_LIST0 ((volatile uint32_t *)0xfe005c08) +#define P_I2C_M_B_TOKEN_LIST1 ((volatile uint32_t *)0xfe005c0c) +#define P_I2C_M_B_WDATA_REG0 ((volatile uint32_t *)0xfe005c10) +#define P_I2C_M_B_WDATA_REG1 ((volatile uint32_t *)0xfe005c14) +#define P_I2C_M_B_RDATA_REG0 ((volatile uint32_t *)0xfe005c18) +#define P_I2C_M_B_RDATA_REG1 ((volatile uint32_t *)0xfe005c1c) +#define P_I2C_M_B_TIMEOUT_TH ((volatile uint32_t *)0xfe005c20) +//======================================================================== +// APB0_DMA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006000 +// ----------------------------------------------- +//TODO +//======================================================================== +// APB0_IRQ_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006400 +// ----------------------------------------------- +#define P_IRQCTRL_IRQOUT_MASK0 ((volatile uint32_t *)0xfe006400) +#define P_IRQCTRL_IRQOUT_MASK1 ((volatile uint32_t *)0xfe006404) +#define P_IRQCTRL_IRQOUT_MASK2 ((volatile uint32_t *)0xfe006408) +#define P_IRQCTRL_IRQOUT_MASK3 ((volatile uint32_t *)0xfe00640c) +#define P_IRQCTRL_IRQOUT_INV0 ((volatile uint32_t *)0xfe006440) +#define P_IRQCTRL_IRQOUT_INV1 ((volatile uint32_t *)0xfe006444) +#define P_IRQCTRL_IRQOUT_INV2 ((volatile uint32_t *)0xfe006448) +#define P_IRQCTRL_IRQOUT_INV3 ((volatile uint32_t *)0xfe00644c) +//`define APB0_IRQIN_MASK0_CLK_USB 8'h00 +//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01 +//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02 +//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03 +//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04 +//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05 +//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10 +//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11 +//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12 +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006800 +// ----------------------------------------------- +#define P_I2C_M_C_CONTROL_REG ((volatile uint32_t *)0xfe006800) +#define P_I2C_M_C_SLAVE_ADDR ((volatile uint32_t *)0xfe006804) +#define P_I2C_M_C_TOKEN_LIST0 ((volatile uint32_t *)0xfe006808) +#define P_I2C_M_C_TOKEN_LIST1 ((volatile uint32_t *)0xfe00680c) +#define P_I2C_M_C_WDATA_REG0 ((volatile uint32_t *)0xfe006810) +#define P_I2C_M_C_WDATA_REG1 ((volatile uint32_t *)0xfe006814) +#define P_I2C_M_C_RDATA_REG0 ((volatile uint32_t *)0xfe006818) +#define P_I2C_M_C_RDATA_REG1 ((volatile uint32_t *)0xfe00681c) +#define P_I2C_M_C_TIMEOUT_TH ((volatile uint32_t *)0xfe006820) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006c00 +// ----------------------------------------------- +#define P_I2C_M_D_CONTROL_REG ((volatile uint32_t *)0xfe006c00) +#define P_I2C_M_D_SLAVE_ADDR ((volatile uint32_t *)0xfe006c04) +#define P_I2C_M_D_TOKEN_LIST0 ((volatile uint32_t *)0xfe006c08) +#define P_I2C_M_D_TOKEN_LIST1 ((volatile uint32_t *)0xfe006c0c) +#define P_I2C_M_D_WDATA_REG0 ((volatile uint32_t *)0xfe006c10) +#define P_I2C_M_D_WDATA_REG1 ((volatile uint32_t *)0xfe006c14) +#define P_I2C_M_D_RDATA_REG0 ((volatile uint32_t *)0xfe006c18) +#define P_I2C_M_D_RDATA_REG1 ((volatile uint32_t *)0xfe006c1c) +#define P_I2C_M_D_TIMEOUT_TH ((volatile uint32_t *)0xfe006c20) +//======================================================================== +// APB0_UART_C - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007000 +// ----------------------------------------------- +#define P_UART_C_WFIFO ((volatile uint32_t *)0xfe007000) +#define P_UART_C_RFIFO ((volatile uint32_t *)0xfe007004) +#define P_UART_C_CONTROL ((volatile uint32_t *)0xfe007008) +#define P_UART_C_STATUS ((volatile uint32_t *)0xfe00700c) +#define P_UART_C_MISC ((volatile uint32_t *)0xfe007010) +#define P_UART_C_REG5 ((volatile uint32_t *)0xfe007014) +//======================================================================== +// APB0_PWR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007800 +// ----------------------------------------------- +#define P_PWRCTRL_PWR_ACK0 ((volatile uint32_t *)0xfe007800) +#define P_PWRCTRL_ISO_EN0 ((volatile uint32_t *)0xfe007804) +#define P_PWRCTRL_PWR_OFF0 ((volatile uint32_t *)0xfe007808) +#define P_PWRCTRL_SAVE_EN0 ((volatile uint32_t *)0xfe00780c) +#define P_PWRCTRL_RESTORE_EN0 ((volatile uint32_t *)0xfe007810) +#define P_PWRCTRL_MEM_PD0 ((volatile uint32_t *)0xfe007840) +#define P_PWRCTRL_MEM_PD1 ((volatile uint32_t *)0xfe007844) +#define P_PWRCTRL_MEM_PD2 ((volatile uint32_t *)0xfe007848) +#define P_PWRCTRL_MEM_PD3 ((volatile uint32_t *)0xfe00784c) +#define P_PWRCTRL_MEM_PD4 ((volatile uint32_t *)0xfe007850) +#define P_PWRCTRL_R_ISO_EN0 ((volatile uint32_t *)0xfe007880) +#define P_PWRCTRL_R_PWR_OFF0 ((volatile uint32_t *)0xfe007884) +#define P_PWRCTRL_R_MEM_PD0 ((volatile uint32_t *)0xfe007888) +#define P_PWRCTRL_R_MEM_PD1 ((volatile uint32_t *)0xfe00788c) +#define P_PWRCTRL_R_MEM_PD2 ((volatile uint32_t *)0xfe007890) +#define P_PWRCTRL_R_MEM_PD3 ((volatile uint32_t *)0xfe007894) +#define P_PWRCTRL_R_MEM_PD4 ((volatile uint32_t *)0xfe007898) +//`define PWRCTRL_MEM_PD_DSPA 8'h10 +//`define PWRCTRL_MEM_PD_DSPB 8'h11 +//`define PWRCTRL_MEM_PD_RAMA 8'h12 +//`define PWRCTRL_MEM_PD_RAMB 8'h13 +//`define PWRCTRL_MEM_PD_CPU 8'h14 +//`define PWRCTRL_MEM_PD_AUDIO 8'h20 +//`define PWRCTRL_MEM_PD_USBCTRL 8'h21 +//`define PWRCTRL_MEM_PD_SPICC 8'h22 +//`define PWRCTRL_MEM_PD_SPIFC 8'h23 +//`define PWRCTRL_MEM_PD_IR 8'h24 +//`define PWRCTRL_MEM_PD_SDIO 8'h25 +//`define PWRCTRL_MEM_PD_KLEFUSE 8'h26 +//`define PWRCTRL_MEM_PD_PSRAM 8'h27 +//`define PWRCTRL_MEM_PD_DDR 8'h28 +//`define PWRCTRL_MEM_PD_DMC 8'h29 +#define P_PWRCTRL_AUTO_OFF_CTRL ((volatile uint32_t *)0xfe0078c0) +#define P_PWRCTRL_AUTO_OFF ((volatile uint32_t *)0xfe0078c4) +#define P_PWRCTRL_AUTO_OFF_STS ((volatile uint32_t *)0xfe0078c8) +#define P_PWRCTRL_TIMER_TH_01 ((volatile uint32_t *)0xfe0078cc) +#define P_PWRCTRL_TIMER_TH_23 ((volatile uint32_t *)0xfe0078d0) +#define P_PWRCTRL_TIMER_TH_45 ((volatile uint32_t *)0xfe0078d4) +#define P_PWRCTRL_TIMER_TH_67 ((volatile uint32_t *)0xfe0078d8) +#define P_PWRCTRL_MASK_PWR_ACK0 ((volatile uint32_t *)0xfe007900) +#define P_PWRCTRL_MASK_RSTN_OFF0 ((volatile uint32_t *)0xfe007904) +#define P_PWRCTRL_MASK_RSTN_ON0 ((volatile uint32_t *)0xfe007908) +#define P_PWRCTRL_MASK_PWR_OFF0 ((volatile uint32_t *)0xfe00790c) +#define P_PWRCTRL_MASK_PWR_ON0 ((volatile uint32_t *)0xfe007910) +#define P_PWRCTRL_MASK_ISO_OFF0 ((volatile uint32_t *)0xfe007914) +#define P_PWRCTRL_MASK_ISO_ON0 ((volatile uint32_t *)0xfe007918) +#define P_PWRCTRL_MASK_MEM_OFF0 ((volatile uint32_t *)0xfe007940) +#define P_PWRCTRL_MASK_MEM_OFF1 ((volatile uint32_t *)0xfe007944) +#define P_PWRCTRL_MASK_MEM_OFF2 ((volatile uint32_t *)0xfe007948) +#define P_PWRCTRL_MASK_MEM_OFF3 ((volatile uint32_t *)0xfe00794c) +#define P_PWRCTRL_MASK_MEM_OFF4 ((volatile uint32_t *)0xfe007950) +#define P_PWRCTRL_MASK_MEM_ON0 ((volatile uint32_t *)0xfe007960) +#define P_PWRCTRL_MASK_MEM_ON1 ((volatile uint32_t *)0xfe007964) +#define P_PWRCTRL_MASK_MEM_ON2 ((volatile uint32_t *)0xfe007968) +#define P_PWRCTRL_MASK_MEM_ON3 ((volatile uint32_t *)0xfe00796c) +#define P_PWRCTRL_MASK_MEM_ON4 ((volatile uint32_t *)0xfe007970) +//======================================================================== +// APB0_ANA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007c00 +// ----------------------------------------------- +#define P_ANACTRL_FIXPLL_CTRL0 ((volatile uint32_t *)0xfe007c80) +#define P_ANACTRL_FIXPLL_CTRL1 ((volatile uint32_t *)0xfe007c84) +#define P_ANACTRL_FIXPLL_CTRL2 ((volatile uint32_t *)0xfe007c88) +#define P_ANACTRL_FIXPLL_CTRL3 ((volatile uint32_t *)0xfe007c8c) +#define P_ANACTRL_FIXPLL_CTRL4 ((volatile uint32_t *)0xfe007c90) +#define P_ANACTRL_FIXPLL_STS ((volatile uint32_t *)0xfe007c94) +#define P_ANACTRL_SYSPLL_CTRL0 ((volatile uint32_t *)0xfe007d00) +#define P_ANACTRL_SYSPLL_CTRL1 ((volatile uint32_t *)0xfe007d04) +#define P_ANACTRL_SYSPLL_CTRL2 ((volatile uint32_t *)0xfe007d08) +#define P_ANACTRL_SYSPLL_CTRL3 ((volatile uint32_t *)0xfe007d0c) +#define P_ANACTRL_SYSPLL_CTRL4 ((volatile uint32_t *)0xfe007d10) +#define P_ANACTRL_SYSPLL_STS ((volatile uint32_t *)0xfe007d14) +#define P_ANACTRL_HIFIPLL_CTRL0 ((volatile uint32_t *)0xfe007d40) +#define P_ANACTRL_HIFIPLL_CTRL1 ((volatile uint32_t *)0xfe007d44) +#define P_ANACTRL_HIFIPLL_CTRL2 ((volatile uint32_t *)0xfe007d48) +#define P_ANACTRL_HIFIPLL_CTRL3 ((volatile uint32_t *)0xfe007d4c) +#define P_ANACTRL_HIFIPLL_CTRL4 ((volatile uint32_t *)0xfe007d50) +#define P_ANACTRL_HIFIPLL_STS ((volatile uint32_t *)0xfe007d54) +#define P_ANACTRL_AUDDDS_CTRL0 ((volatile uint32_t *)0xfe007d80) +#define P_ANACTRL_AUDDDS_CTRL1 ((volatile uint32_t *)0xfe007d84) +#define P_ANACTRL_AUDDDS_CTRL2 ((volatile uint32_t *)0xfe007d88) +#define P_ANACTRL_AUDDDS_CTRL3 ((volatile uint32_t *)0xfe007d8c) +#define P_ANACTRL_AUDDDS_CTRL4 ((volatile uint32_t *)0xfe007d90) +#define P_ANACTRL_AUDDDS_STS ((volatile uint32_t *)0xfe007d94) +#define P_ANACTRL_MISCTOP_CTRL0 ((volatile uint32_t *)0xfe007dc0) +#define P_ANACTRL_POR_CNTL ((volatile uint32_t *)0xfe007e08) +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe020000 +// ----------------------------------------------- +#define P_RSA_BASE ((volatile uint32_t *)0xfe020000) +//======================================================================== +// CPUCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000000 +// ----------------------------------------------- +#define P_CPUCTRL_CTRL0 ((volatile uint32_t *)0xfd000000) +#define P_CPUCTRL_CTRL1 ((volatile uint32_t *)0xfd000004) +#define P_CPUCTRL_CTRL2 ((volatile uint32_t *)0xfd000008) +#define P_CPUCTRL_CTRL3 ((volatile uint32_t *)0xfd00000c) +#define P_CPUCTRL_CTRL4 ((volatile uint32_t *)0xfd000010) +#define P_CPUCTRL_CTRL5 ((volatile uint32_t *)0xfd000014) +#define P_CPUCTRL_CTRL6 ((volatile uint32_t *)0xfd000018) +#define P_CPUCTRL_CTRL7 ((volatile uint32_t *)0xfd00001c) +#define P_CPUCTRL_CTRL8 ((volatile uint32_t *)0xfd000020) +#define P_CPUCTRL_CTRL9 ((volatile uint32_t *)0xfd000024) +#define P_CPUCTRL_CTRL10 ((volatile uint32_t *)0xfd000028) +#define P_CPUCTRL_CTRL11 ((volatile uint32_t *)0xfd00002c) +#define P_CPUCTRL_CTRL12 ((volatile uint32_t *)0xfd000030) +#define P_CPUCTRL_CTRL13 ((volatile uint32_t *)0xfd000034) +#define P_CPUCTRL_CTRL14 ((volatile uint32_t *)0xfd000038) +#define P_CPUCTRL_CTRL15 ((volatile uint32_t *)0xfd00003c) +#define P_CPUCTRL_STS0 ((volatile uint32_t *)0xfd000040) +#define P_CPUCTRL_STS1 ((volatile uint32_t *)0xfd000044) +#define P_CPUCTRL_STS2 ((volatile uint32_t *)0xfd000048) +#define P_CPUCTRL_STS3 ((volatile uint32_t *)0xfd00004c) +#define P_CPUCTRL_STS4 ((volatile uint32_t *)0xfd000050) +#define P_CPUCTRL_STS5 ((volatile uint32_t *)0xfd000054) +#define P_CPUCTRL_STS6 ((volatile uint32_t *)0xfd000058) +#define P_CPUCTRL_STS7 ((volatile uint32_t *)0xfd00005c) +#define P_CPUCTRL_STS8 ((volatile uint32_t *)0xfd000060) +#define P_CPUCTRL_STS9 ((volatile uint32_t *)0xfd000064) +#define P_CPUCTRL_CLK_CTRL0 ((volatile uint32_t *)0xfd000080) +#define P_CPUCTRL_CLK_CTRL1 ((volatile uint32_t *)0xfd000084) +#define P_CPUCTRL_CLK_CTRL2 ((volatile uint32_t *)0xfd000088) +#define P_CPUCTRL_CLK_CTRL3 ((volatile uint32_t *)0xfd00008c) +#define P_CPUCTRL_CLK_CTRL4 ((volatile uint32_t *)0xfd000090) +#define P_CPUCTRL_CLK_CTRL5 ((volatile uint32_t *)0xfd000094) +#define P_CPUCTRL_CLK_CTRL6 ((volatile uint32_t *)0xfd000098) +#define P_CPUCTRL_CLK_CTRL7 ((volatile uint32_t *)0xfd00009c) +#define P_CPUCTRL_RESET_CTRL ((volatile uint32_t *)0xfd0000c0) +#define P_CPUCTRL_ROM_DISABLE ((volatile uint32_t *)0xfd0000c4) +//======================================================================== +// RAMA_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000800 +// ----------------------------------------------- +#define P_SRAM_RANGE0_STA ((volatile uint32_t *)0xfd000800) +#define P_SRAM_RANGE1_STA ((volatile uint32_t *)0xfd000804) +#define P_SRAM_RANGE2_STA ((volatile uint32_t *)0xfd000808) +#define P_SRAM_RANGE3_STA ((volatile uint32_t *)0xfd00080c) +#define P_SRAM_RANGE4_STA ((volatile uint32_t *)0xfd000810) +#define P_SRAM_RANGE5_STA ((volatile uint32_t *)0xfd000814) +#define P_SRAM_RANGE6_STA ((volatile uint32_t *)0xfd000818) +#define P_SRAM_RANGE0_EDA ((volatile uint32_t *)0xfd00081c) +#define P_SRAM_RANGE1_EDA ((volatile uint32_t *)0xfd000820) +#define P_SRAM_RANGE2_EDA ((volatile uint32_t *)0xfd000824) +#define P_SRAM_RANGE3_EDA ((volatile uint32_t *)0xfd000828) +#define P_SRAM_RANGE4_EDA ((volatile uint32_t *)0xfd00082c) +#define P_SRAM_RANGE5_EDA ((volatile uint32_t *)0xfd000830) +#define P_SRAM_RANGE6_EDA ((volatile uint32_t *)0xfd000834) +#define P_SRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfd000838) +#define P_SRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfd00083c) +#define P_SRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfd000840) +#define P_SRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfd000844) +#define P_SRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfd000848) +#define P_SRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfd00084c) +#define P_SRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfd000850) +#define P_SRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfd000854) +#define P_SRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfd000858) +#define P_SRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfd00085c) +#define P_SRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfd000860) +#define P_SRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfd000864) +#define P_SRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfd000868) +#define P_SRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfd00086c) +#define P_SRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfd000870) +#define P_SRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfd000874) +#define P_SRAM_SEC_CTRL0 ((volatile uint32_t *)0xfd000878) +#define P_SRAM_REG_LOCK ((volatile uint32_t *)0xfd00087c) +//======================================================================== +// RAMB_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfd000c00 +// ----------------------------------------------- +#define P_SRAM_RANGE0_STA_B ((volatile uint32_t *)0xfd000c00) +#define P_SRAM_RANGE1_STA_B ((volatile uint32_t *)0xfd000c04) +#define P_SRAM_RANGE2_STA_B ((volatile uint32_t *)0xfd000c08) +#define P_SRAM_RANGE3_STA_B ((volatile uint32_t *)0xfd000c0c) +#define P_SRAM_RANGE4_STA_B ((volatile uint32_t *)0xfd000c10) +#define P_SRAM_RANGE5_STA_B ((volatile uint32_t *)0xfd000c14) +#define P_SRAM_RANGE6_STA_B ((volatile uint32_t *)0xfd000c18) +#define P_SRAM_RANGE0_EDA_B ((volatile uint32_t *)0xfd000c1c) +#define P_SRAM_RANGE1_EDA_B ((volatile uint32_t *)0xfd000c20) +#define P_SRAM_RANGE2_EDA_B ((volatile uint32_t *)0xfd000c24) +#define P_SRAM_RANGE3_EDA_B ((volatile uint32_t *)0xfd000c28) +#define P_SRAM_RANGE4_EDA_B ((volatile uint32_t *)0xfd000c2c) +#define P_SRAM_RANGE5_EDA_B ((volatile uint32_t *)0xfd000c30) +#define P_SRAM_RANGE6_EDA_B ((volatile uint32_t *)0xfd000c34) +#define P_SRAM_RANGE0_CTRL0_B ((volatile uint32_t *)0xfd000c38) +#define P_SRAM_RANGE1_CTRL0_B ((volatile uint32_t *)0xfd000c3c) +#define P_SRAM_RANGE2_CTRL0_B ((volatile uint32_t *)0xfd000c40) +#define P_SRAM_RANGE3_CTRL0_B ((volatile uint32_t *)0xfd000c44) +#define P_SRAM_RANGE4_CTRL0_B ((volatile uint32_t *)0xfd000c48) +#define P_SRAM_RANGE5_CTRL0_B ((volatile uint32_t *)0xfd000c4c) +#define P_SRAM_RANGE6_CTRL0_B ((volatile uint32_t *)0xfd000c50) +#define P_SRAM_RANGE7_CTRL0_B ((volatile uint32_t *)0xfd000c54) +#define P_SRAM_RANGE0_CTRL1_B ((volatile uint32_t *)0xfd000c58) +#define P_SRAM_RANGE1_CTRL1_B ((volatile uint32_t *)0xfd000c5c) +#define P_SRAM_RANGE2_CTRL1_B ((volatile uint32_t *)0xfd000c60) +#define P_SRAM_RANGE3_CTRL1_B ((volatile uint32_t *)0xfd000c64) +#define P_SRAM_RANGE4_CTRL1_B ((volatile uint32_t *)0xfd000c68) +#define P_SRAM_RANGE5_CTRL1_B ((volatile uint32_t *)0xfd000c6c) +#define P_SRAM_RANGE6_CTRL1_B ((volatile uint32_t *)0xfd000c70) +#define P_SRAM_RANGE7_CTRL1_B ((volatile uint32_t *)0xfd000c74) +#define P_SRAM_SEC_CTRL0_B ((volatile uint32_t *)0xfd000c78) +#define P_SRAM_REG_LOCK_B ((volatile uint32_t *)0xfd000c7c) +// +// Reading file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +//======================================================================== +// DSPA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe030000 +// ----------------------------------------------- +#define P_DSP_CFG0 ((volatile uint32_t *)0xfe030000) +#define P_DSP_CFG1 ((volatile uint32_t *)0xfe030004) +#define P_DSP_CFG2 ((volatile uint32_t *)0xfe030008) +#define P_DSP_IMPWIRE ((volatile uint32_t *)0xfe03000c) +#define P_DSP_RESET_VEC ((volatile uint32_t *)0xfe030010) +#define P_DSP_SEC_CFG0 ((volatile uint32_t *)0xfe030018) +#define P_DSP_SEC_CFG1 ((volatile uint32_t *)0xfe03001c) +#define P_DSP_IRQ_CTRL0 ((volatile uint32_t *)0xfe030040) +#define P_DSP_IRQ_CTRL1 ((volatile uint32_t *)0xfe030044) +#define P_DSP_IRQ_CTRL2 ((volatile uint32_t *)0xfe030048) +#define P_DSP_IRQ_CTRL3 ((volatile uint32_t *)0xfe03004c) +#define P_DSP_IRQ_CTRL4 ((volatile uint32_t *)0xfe030050) +#define P_DSP_IRQ_CTRL5 ((volatile uint32_t *)0xfe030054) +#define P_DSP_IRQ_CTRL6 ((volatile uint32_t *)0xfe030058) +#define P_DSP_IRQ_CTRL7 ((volatile uint32_t *)0xfe03005c) +#define P_DSP_IRQ_CTRL8 ((volatile uint32_t *)0xfe030060) +#define P_DSP_IRQ_STS ((volatile uint32_t *)0xfe03007c) +#define P_DSP_REMAP0 ((volatile uint32_t *)0xfe030080) +#define P_DSP_REMAP1 ((volatile uint32_t *)0xfe030084) +#define P_DSP_REMAP2 ((volatile uint32_t *)0xfe030088) +#define P_DSP_STS0 ((volatile uint32_t *)0xfe030100) +#define P_DSP_STS1 ((volatile uint32_t *)0xfe030104) +#define P_DSP_STS2 ((volatile uint32_t *)0xfe030108) +#define P_DSP_STS3 ((volatile uint32_t *)0xfe03010c) +#define P_DSP_STS4 ((volatile uint32_t *)0xfe030110) +#define P_DSP_STS5 ((volatile uint32_t *)0xfe030114) +#define P_DSP_MAILBOX_SET_0 ((volatile uint32_t *)0xfe030140) +#define P_DSP_MAILBOX_SET_1 ((volatile uint32_t *)0xfe030144) +#define P_DSP_MAILBOX_SET_2 ((volatile uint32_t *)0xfe030148) +#define P_DSP_MAILBOX_SET_3 ((volatile uint32_t *)0xfe03014c) +#define P_DSP_MAILBOX_SET_4 ((volatile uint32_t *)0xfe030150) +#define P_DSP_MAILBOX_SET_5 ((volatile uint32_t *)0xfe030154) +#define P_DSP_MAILBOX_SET_6 ((volatile uint32_t *)0xfe030158) +#define P_DSP_MAILBOX_SET_7 ((volatile uint32_t *)0xfe03015c) +#define P_DSP_MAILBOX_SET_8 ((volatile uint32_t *)0xfe030160) +#define P_DSP_MAILBOX_SET_9 ((volatile uint32_t *)0xfe030164) +#define P_DSP_MAILBOX_SET_10 ((volatile uint32_t *)0xfe030168) +#define P_DSP_MAILBOX_SET_11 ((volatile uint32_t *)0xfe03016c) +#define P_DSP_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe030180) +#define P_DSP_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe030184) +#define P_DSP_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe030188) +#define P_DSP_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe03018c) +#define P_DSP_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe030190) +#define P_DSP_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe030194) +#define P_DSP_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe030198) +#define P_DSP_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe03019c) +#define P_DSP_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0301a0) +#define P_DSP_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0301a4) +#define P_DSP_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0301a8) +#define P_DSP_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0301ac) +#define P_DSP_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0301c0) +#define P_DSP_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0301c4) +#define P_DSP_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0301c8) +#define P_DSP_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0301cc) +#define P_DSP_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0301d0) +#define P_DSP_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0301d4) +#define P_DSP_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0301d8) +#define P_DSP_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0301dc) +#define P_DSP_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0301e0) +#define P_DSP_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0301e4) +#define P_DSP_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0301e8) +#define P_DSP_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0301ec) +#define P_DSP_QIF_CTRL ((volatile uint32_t *)0xfe030200) +#define P_DSP_QIF_STS ((volatile uint32_t *)0xfe030204) +#define P_DSP_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe030208) +#define P_DSP_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe03020c) +#define P_DSP_WRFIFO_TODSP ((volatile uint32_t *)0xfe030210) +#define P_DSP_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe030220) +#define P_DSP_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe030224) +#define P_DSP_RDFIFO_FRDSP ((volatile uint32_t *)0xfe030228) +//======================================================================== +// DSPB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe040000 +// ----------------------------------------------- +#define P_DSPB_CFG0 ((volatile uint32_t *)0xfe040000) +#define P_DSPB_CFG1 ((volatile uint32_t *)0xfe040004) +#define P_DSPB_CFG2 ((volatile uint32_t *)0xfe040008) +#define P_DSPB_IMPWIRE ((volatile uint32_t *)0xfe04000c) +#define P_DSPB_RESET_VEC ((volatile uint32_t *)0xfe040010) +#define P_DSPB_SEC_CFG0 ((volatile uint32_t *)0xfe040018) +#define P_DSPB_SEC_CFG1 ((volatile uint32_t *)0xfe04001c) +#define P_DSPB_IRQ_CTRL0 ((volatile uint32_t *)0xfe040040) +#define P_DSPB_IRQ_CTRL1 ((volatile uint32_t *)0xfe040044) +#define P_DSPB_IRQ_CTRL2 ((volatile uint32_t *)0xfe040048) +#define P_DSPB_IRQ_CTRL3 ((volatile uint32_t *)0xfe04004c) +#define P_DSPB_IRQ_CTRL4 ((volatile uint32_t *)0xfe040050) +#define P_DSPB_IRQ_CTRL5 ((volatile uint32_t *)0xfe040054) +#define P_DSPB_IRQ_CTRL6 ((volatile uint32_t *)0xfe040058) +#define P_DSPB_IRQ_CTRL7 ((volatile uint32_t *)0xfe04005c) +#define P_DSPB_IRQ_CTRL8 ((volatile uint32_t *)0xfe040060) +#define P_DSPB_IRQ_STS ((volatile uint32_t *)0xfe04007c) +#define P_DSPB_REMAP0 ((volatile uint32_t *)0xfe040080) +#define P_DSPB_REMAP1 ((volatile uint32_t *)0xfe040084) +#define P_DSPB_REMAP2 ((volatile uint32_t *)0xfe040088) +#define P_DSPB_STS0 ((volatile uint32_t *)0xfe040100) +#define P_DSPB_STS1 ((volatile uint32_t *)0xfe040104) +#define P_DSPB_STS2 ((volatile uint32_t *)0xfe040108) +#define P_DSPB_STS3 ((volatile uint32_t *)0xfe04010c) +#define P_DSPB_STS4 ((volatile uint32_t *)0xfe040110) +#define P_DSPB_STS5 ((volatile uint32_t *)0xfe040114) +#define P_DSPB_MAILBOX_SET_0 ((volatile uint32_t *)0xfe040140) +#define P_DSPB_MAILBOX_SET_1 ((volatile uint32_t *)0xfe040144) +#define P_DSPB_MAILBOX_SET_2 ((volatile uint32_t *)0xfe040148) +#define P_DSPB_MAILBOX_SET_3 ((volatile uint32_t *)0xfe04014c) +#define P_DSPB_MAILBOX_SET_4 ((volatile uint32_t *)0xfe040150) +#define P_DSPB_MAILBOX_SET_5 ((volatile uint32_t *)0xfe040154) +#define P_DSPB_MAILBOX_SET_6 ((volatile uint32_t *)0xfe040158) +#define P_DSPB_MAILBOX_SET_7 ((volatile uint32_t *)0xfe04015c) +#define P_DSPB_MAILBOX_SET_8 ((volatile uint32_t *)0xfe040160) +#define P_DSPB_MAILBOX_SET_9 ((volatile uint32_t *)0xfe040164) +#define P_DSPB_MAILBOX_SET_10 ((volatile uint32_t *)0xfe040168) +#define P_DSPB_MAILBOX_SET_11 ((volatile uint32_t *)0xfe04016c) +#define P_DSPB_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe040180) +#define P_DSPB_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe040184) +#define P_DSPB_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe040188) +#define P_DSPB_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe04018c) +#define P_DSPB_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe040190) +#define P_DSPB_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe040194) +#define P_DSPB_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe040198) +#define P_DSPB_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe04019c) +#define P_DSPB_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0401a0) +#define P_DSPB_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0401a4) +#define P_DSPB_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0401a8) +#define P_DSPB_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0401ac) +#define P_DSPB_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0401c0) +#define P_DSPB_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0401c4) +#define P_DSPB_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0401c8) +#define P_DSPB_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0401cc) +#define P_DSPB_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0401d0) +#define P_DSPB_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0401d4) +#define P_DSPB_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0401d8) +#define P_DSPB_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0401dc) +#define P_DSPB_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0401e0) +#define P_DSPB_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0401e4) +#define P_DSPB_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0401e8) +#define P_DSPB_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0401ec) +#define P_DSPB_QIF_CTRL ((volatile uint32_t *)0xfe040200) +#define P_DSPB_QIF_STS ((volatile uint32_t *)0xfe040204) +#define P_DSPB_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe040208) +#define P_DSPB_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe04020c) +#define P_DSPB_WRFIFO_TODSP ((volatile uint32_t *)0xfe040210) +#define P_DSPB_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe040220) +#define P_DSPB_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe040224) +#define P_DSPB_RDFIFO_FRDSP ((volatile uint32_t *)0xfe040228) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ./REG_LIST_RTL.h +// + +#endif // P_REGISTER_H +
diff --git a/arch/arm/include/asm/arch-c2/pinctrl_init.h b/arch/arm/include/asm/arch-c2/pinctrl_init.h new file mode 100644 index 0000000..cfbc42a --- /dev/null +++ b/arch/arm/include/asm/arch-c2/pinctrl_init.h
@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _MESON_PINCTRL_INIT_H_ +#define _MESON_PINCTRL_INIT_H_ + +#define PIN_CONTROLLER_NUM 2 +extern int pinctrl_devices_active(int pinctrl_num); + +#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-c2/pll.h b/arch/arm/include/asm/arch-c2/pll.h new file mode 100644 index 0000000..f43c364 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/pll.h
@@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __PLL_H +#define __PLL_H + +#define PLL_TEST_SYS_TOTAL 2 +#define PLL_TEST_HDMI_TOTAL 3 +#define PLL_TEST_HIFI_TOTAL 2 +#define PLL_TEST_GP0_TOTAL 2 + +typedef struct sys_pll_set_s { + unsigned int cpu_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; +}sys_pll_set_t; + +typedef struct sys_pll_cfg_s { + sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL]; +}sys_pll_cfg_t; + +typedef struct hifi_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; +}hifi_pll_set_t; + +typedef struct hifi_pll_cfg_s { + hifi_pll_set_t hifi_pll[PLL_TEST_HIFI_TOTAL]; +}hifi_pll_cfg_t; + +typedef struct hifipll_rate_table_s { + unsigned int rate; + unsigned int m; + unsigned int n; + unsigned int od; +}hifipll_rate_table_t; + +typedef struct gpll_rate_table_s { + unsigned int rate; + unsigned int m; + unsigned int n; + unsigned int od; +}gpll_rate_table_t; + +typedef struct ddspll_rate_table_t { + unsigned int RATE; + unsigned int CTS; + unsigned int N; +}ddspll_rate_table_t; + +typedef struct gp_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; +}gp_pll_set_t; + +typedef struct gp0_pll_cfg_s { + gp_pll_set_t gp0_pll[PLL_TEST_GP0_TOTAL]; +}gp0_pll_cfg_t; + +typedef struct dds_pll_set_s { + unsigned int pll_clk; + unsigned int misctop_cntl0; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; +}dds_pll_set_t; + +typedef struct usbphy_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; +}usbphy_pll_set_t; + +typedef struct ethphy_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; +}ethphy_pll_set_t; + +enum pll_enum { + PLL_SYS = 0, + PLL_FIX, + PLL_DDR, + PLL_HIFI, + PLL_GP, + PLL_DDS, + PLL_USBPHY, + PLL_ETHPHY, + PLL_ENUM, +}; +int pll_test(int argc, char * const argv[]); + +#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-c2/pwr_ctrl.h b/arch/arm/include/asm/arch-c2/pwr_ctrl.h new file mode 100644 index 0000000..f80d1e2 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/pwr_ctrl.h
@@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#define PWR_ON 1 +#define PWR_OFF 0 + +enum pm_e { + PM_CPU_PWR0, + PM_CPU_CORE0, + PM_CPU_CORE1, + PM_SPTOP = 5, + PM_DSP_A = 8, + PM_DSP_B, + PM_UART, + PM_DMC, + PM_I2C, + PM_SDEMMC_B, + PM_ACODEC, + PM_AUDIO, + PM_MKL_OTP, + PM_DMA, + PM_SDEMMC_A, + PM_SRAM_A, + PM_SRAM_B, + PM_IR, + PM_SPICC, + PM_SPIFC, + PM_USB, + PM_NIC, + PM_PDM, + PM_RSA, + PM_MIPI_ISP, + PM_HCODEC, + PM_WAVE, + PM_SDEMMC_C, + PM_SRAM_C, + PM_GDC, + PM_GE2D, + PM_NNA, + PM_ETH, + PM_GIC, + PM_DDR, + PM_SPICC_B +}; + +unsigned long pwr_ctrl_psci_smc(enum pm_e power_domain, bool power_control); \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c2/reboot.h b/arch/arm/include/asm/arch-c2/reboot.h new file mode 100644 index 0000000..f6a3230 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/reboot.h
@@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __REBOOT_H +#define __REBOOT_H + +/* +Reboot reason AND corresponding env setting: +0: Cold boot cold_boot +1: Normal boot normal +2: Factory reset factory_reset +3: Upgrade system update +4: Fastboot fastboot +5: Suspend suspend_off +6: Hibernate hibernate +7: Fastboot Bootloader bootloader +8: Shutdown reboot shutdown_reboot +9: RPMBP reboot rpmbp +10: quiescent reboot quiescent reboot +11: Crash dump crash_dump +12: Kernel panic kernel_panic +13: Watchdog reboot watchdog_reboot +14: quiescent recovery reboot quiescent recovery +15: reserved +*/ +#define AMLOGIC_COLD_BOOT 0 +#define AMLOGIC_NORMAL_BOOT 1 +#define AMLOGIC_FACTORY_RESET_REBOOT 2 +#define AMLOGIC_UPDATE_REBOOT 3 +#define AMLOGIC_FASTBOOT_REBOOT 4 +#define AMLOGIC_SUSPEND_REBOOT 5 +#define AMLOGIC_HIBERNATE_REBOOT 6 +#define AMLOGIC_BOOTLOADER_REBOOT 7 /* fastboot bootloader */ +#define AMLOGIC_SHUTDOWN_REBOOT 8 +#define AMLOGIC_RPMBP_REBOOT 9 +#define AMLOGIC_QUIESCENT_REBOOT 10 +#define AMLOGIC_CRASH_REBOOT 11 +#define AMLOGIC_KERNEL_PANIC 12 +#define AMLOGIC_WATCHDOG_REBOOT 13 +#define AMLOGIC_RECOVERY_QUIESCENT_REBOOT 14 +#define AMLOGIC_DELAYED_REBOOT 15 + +/* +old version env +0x01010101, normal +0x02020202, factory_reset +0x03030303, update +0x09090909, usb_burning +0x0b0b0b0b, suspend_off +*/ + +#endif +
diff --git a/arch/arm/include/asm/arch-c2/register.h b/arch/arm/include/asm/arch-c2/register.h new file mode 100644 index 0000000..ec64c8f --- /dev/null +++ b/arch/arm/include/asm/arch-c2/register.h
@@ -0,0 +1,8310 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifdef REGISTER_H +#else +#define REGISTER_H + + +#if 0 +#ifndef VERIFICATION + #define Wr64(addr, data) *(volatile uint64_t *)(addr)=(data) + #define Rd64(addr) *(volatile uint64_t *)(addr) + #define Wr(addr, data) *(volatile uint32_t *)(addr)=(data) + #define Rd(addr) *(volatile uint32_t *)(addr) + #define Wr_reg_bits(reg, val, start, len) \ + Wr(reg, ((Rd(reg) & ~(((1L<<(len))-1)<<(start))) | ((uint32_t)(val) << (start)))) +#else + #include "dpi.h" +#endif +#endif + +// +// Reading file: ./REG_LIST_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Reading file: REG_LIST_AUDIO_RTL.h +// +//======================================================================== +// AUDIO - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe050000 +// ----------------------------------------------- +#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe050000) +#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe050000) +#define EE_AUDIO_PAD_CTRL0 ((0x0008 << 2) + 0xfe050000) +#define EE_AUDIO_PAD_CTRL1 ((0x0009 << 2) + 0xfe050000) +#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe050000) +#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe050000) +#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe050000) +#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe050000) +#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe050000) +#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe050000) +#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe050000) +#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe050000) +#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe050000) +#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe050000) +#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe050000) +#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe050000) +#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe050000) +#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe050000) +#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe050000) +#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe050000) +#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe050000) +#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe050000) +#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe050000) +#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe050000) +#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe050000) +#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe050000) +#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe050000) +#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe050000) +#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe050000) +#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe050000) +#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe050000) +#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe050000) +#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe050000) +#define EE_AUDIO_ARB_CTRL0 ((0x00a0 << 2) + 0xfe050000) +#define EE_AUDIO_ARB_CTRL1 ((0x00a1 << 2) + 0xfe050000) +#define EE_AUDIO_ARB_STS ((0x00a8 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CHSYNC_CTRL_INSERT ((0x00bd << 2) + 0xfe050000) +#define EE_AUDIO_LB_A_CHSYNC_CTRL_ORIG ((0x00be << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe050000) +//`define EE_AUDIO_POW_DET_CTRL0 10'h180 +//`define EE_AUDIO_POW_DET_CTRL1 10'h181 +//`define EE_AUDIO_POW_DET_TH_HI 10'h182 +//`define EE_AUDIO_POW_DET_TH_LO 10'h183 +//`define EE_AUDIO_POW_DET_VALUE 10'h184 +#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe050000) +#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe050000) +#define EE_AUDIO_IRQ_FIFO_CNT ((0x0192 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN2 ((0x01b4 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN3 ((0x01b5 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN_EN ((0x01b6 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFOUT_B_GAIN_CTRL ((0x01b7 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe050000) +#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe050000) +#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe050000) +#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe050000) +#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe050000) +#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe050000) +#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe050000) +#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe050000) +#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CHSYNC_CTRL_INSERT ((0x023d << 2) + 0xfe050000) +#define EE_AUDIO_LB_B_CHSYNC_CTRL_ORIG ((0x023e << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe050000) +#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe050000) +#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN_EN ((0x02ac << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_A_GAIN_CTRL ((0x02ad << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN_EN ((0x02bc << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_B_GAIN_CTRL ((0x02bd << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe050000) +#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHNUM_ID0 ((0x0300 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHNUM_ID1 ((0x0301 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHNUM_ID2 ((0x0302 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHNUM_ID3 ((0x0303 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHNUM_ID4 ((0x0304 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHNUM_ID5 ((0x0305 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHNUM_ID6 ((0x0306 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHNUM_ID7 ((0x0307 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_A_CHSYNC_CTRL ((0x030f << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHNUM_ID0 ((0x0310 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHNUM_ID1 ((0x0311 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHNUM_ID2 ((0x0312 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHNUM_ID3 ((0x0313 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHNUM_ID4 ((0x0314 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHNUM_ID5 ((0x0315 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHNUM_ID6 ((0x0316 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHNUM_ID7 ((0x0317 << 2) + 0xfe050000) +#define EE_AUDIO_TODDR_B_CHSYNC_CTRL ((0x031f << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID0 ((0x0350 << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID1 ((0x0351 << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID2 ((0x0352 << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID3 ((0x0353 << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID4 ((0x0354 << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID5 ((0x0355 << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID6 ((0x0356 << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID7 ((0x0357 << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_CHSYNC_MASK ((0x035e << 2) + 0xfe050000) +#define EE_AUDIO_RSAMP_A_CHSYNC_CTRL ((0x035f << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_STS0 ((0x0380 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_STS1 ((0x0381 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_MASK0 ((0x0382 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_MASK1 ((0x0383 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_MODE0 ((0x0384 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_MODE1 ((0x0385 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_CLR0 ((0x0386 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_CLR1 ((0x0387 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_INV0 ((0x0388 << 2) + 0xfe050000) +#define EE_AUDIO_EXCEPTION_IRQ_INV1 ((0x0389 << 2) + 0xfe050000) +//======================================================================== +// PDM - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051000 +// ----------------------------------------------- +#define PDM_CTRL ((0x0000 << 2) + 0xfe051000) + //bit 31: PDM enable. + //bit 30: invert the PDM_DCLK. + //bit 29: output mode: 1: 24bits. 0: 32 bits. + //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode. + //bit 27~9: not used. + //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO. + //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode. + //bit 7:0. PDM channel enable. each bit for one channel. +#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe051000) + //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output. + //bit 29:24. hcic final gain shift parameter. + //bit 23:16 hcic final gain multiplier. + //bit 8:4 hcic down sample rate. + //bit 3:0 hcic stage number. must be between 3 to 9. +#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe051000) + //Not used. +#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe051000) + //bit 31 . filter 1 enable. + //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26] + // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26] + // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26]. + //bit 15:12. filter 1 down sample rate. + //bit 8:0. filter 1 stage number. +#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe051000) + //bit 31 . filter 2 enable. + //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. + //bit 15:12. filter 2 down sample rate. + //bit 8:0. filter 2 stage number. +#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe051000) + //bit 31 . filter 3 enable. + //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. + //bit 15:12. filter 3 down sample rate. + //bit 8:0. filter 3 stage number. +#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe051000) + //bit 31 High pass filter enable. + //bit 20:16 high pass filter shift steps. 6~19 steps. + //bit 15:0 high pass filter output factor. +#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe051000) + //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK. + //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK. + //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK. + //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK. +#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe051000) + //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK. + //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK. + //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK. + //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK. +#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe051000) + // address of the write/read of coeff data. +#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe051000) + //write/read data to coeff memory. +#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe051000) + // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating. + //31:7 not used. + //bit 6 filt_ctrl module auto clock gating control. + //bit 5 sinc fifo module auto clock gating control. + //bit 4 filter module auto clock gating control. + //bit 3 apb module auto clock gating control. + //bit 2 coeff memory module auto clock gating control. + //bit 1 each channel module auto clock gating control. + //bit 0 cts_pdm_clk auto clock gating control. +#define PDM_STS ((0x000c << 2) + 0xfe051000) +//bit 1 HPF filter output overflow. means the PCLK is too slow. +//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function. +#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe051000) +#define PDM_MASK_NUM ((0x000e << 2) + 0xfe051000) +//======================================================================== +// EQ DRC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe052000 +// ----------------------------------------------- +#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe052000) +#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe052000) +#define AED_EQ_EN ((0x0002 << 2) + 0xfe052000) +#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe052000) +#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe052000) +#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe052000) +#define AED_MUTE ((0x0006 << 2) + 0xfe052000) +#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe052000) +#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe052000) +#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe052000) +#define AED_DRC_THD0 ((0x000a << 2) + 0xfe052000) +#define AED_DRC_THD1 ((0x000b << 2) + 0xfe052000) +#define AED_DRC_THD2 ((0x000c << 2) + 0xfe052000) +#define AED_DRC_THD3 ((0x000d << 2) + 0xfe052000) +#define AED_DRC_THD4 ((0x000e << 2) + 0xfe052000) +#define AED_DRC_K0 ((0x000f << 2) + 0xfe052000) +#define AED_DRC_K1 ((0x0010 << 2) + 0xfe052000) +#define AED_DRC_K2 ((0x0011 << 2) + 0xfe052000) +#define AED_DRC_K3 ((0x0012 << 2) + 0xfe052000) +#define AED_DRC_K4 ((0x0013 << 2) + 0xfe052000) +#define AED_DRC_K5 ((0x0014 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe052000) +#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe052000) +#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe052000) +#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe052000) +#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe052000) +#define AED_MDRC_K0 ((0x003b << 2) + 0xfe052000) +#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe052000) +#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe052000) +#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe052000) +#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe052000) +#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe052000) +#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe052000) +#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe052000) +#define AED_MDRC_K2 ((0x004f << 2) + 0xfe052000) +#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe052000) +#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe052000) +#define AED_ED_CNTL ((0x0052 << 2) + 0xfe052000) +#define AED_DC_EN ((0x0053 << 2) + 0xfe052000) +#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe052000) +#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe052000) +#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe052000) +#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe052000) +#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe052000) +#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe052000) +#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe052000) +#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe052000) +#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe052000) +#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe052000) +#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe052000) +#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe052000) +#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe052000) +#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe052000) +#define AED_ND_CNTL ((0x0062 << 2) + 0xfe052000) +#define AED_MIX0_LL ((0x0063 << 2) + 0xfe052000) +#define AED_MIX0_RL ((0x0064 << 2) + 0xfe052000) +#define AED_MIX0_LR ((0x0065 << 2) + 0xfe052000) +#define AED_MIX0_RR ((0x0066 << 2) + 0xfe052000) +#define AED_CLIP_THD ((0x0067 << 2) + 0xfe052000) +#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe052000) +#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe052000) +#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe052000) +#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe052000) +#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe052000) +#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe052000) +#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe052000) +#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe052000) +#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe052000) +#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe052000) +#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe052000) +#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe052000) +#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe052000) +#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe052000) +#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe052000) +#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe052000) +#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe052000) +#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe052000) +#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe052000) +#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe052000) +#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe052000) +#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe052000) +#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe052000) +#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe052000) +#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe052000) +#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe052000) +#define AED_TOP_ST ((0x0086 << 2) + 0xfe052000) +#define AED_EQDRC_DYNAMIC_CNTL ((0x0090 << 2) + 0xfe052000) +#define AED_COEF_RAM_CNTL_B ((0x0091 << 2) + 0xfe052000) +#define AED_COEF_RAM_DATA_B ((0x0092 << 2) + 0xfe052000) +#define AED_DRC_RMS_COEF0_B ((0x0093 << 2) + 0xfe052000) +#define AED_DRC_RMS_COEF1_B ((0x0094 << 2) + 0xfe052000) +#define AED_DRC_THD0_B ((0x0095 << 2) + 0xfe052000) +#define AED_DRC_THD1_B ((0x0096 << 2) + 0xfe052000) +#define AED_DRC_THD2_B ((0x0097 << 2) + 0xfe052000) +#define AED_DRC_THD3_B ((0x0098 << 2) + 0xfe052000) +#define AED_DRC_THD4_B ((0x0099 << 2) + 0xfe052000) +#define AED_DRC_K0_B ((0x009a << 2) + 0xfe052000) +#define AED_DRC_K1_B ((0x009b << 2) + 0xfe052000) +#define AED_DRC_K2_B ((0x009c << 2) + 0xfe052000) +#define AED_DRC_K3_B ((0x009d << 2) + 0xfe052000) +#define AED_DRC_K4_B ((0x009e << 2) + 0xfe052000) +#define AED_DRC_K5_B ((0x009f << 2) + 0xfe052000) +#define AED_DRC_THD_OUT0_B ((0x00a0 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT1_B ((0x00a1 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT2_B ((0x00a2 << 2) + 0xfe052000) +#define AED_DRC_THD_OUT3_B ((0x00a3 << 2) + 0xfe052000) +#define AED_DRC_OFFSET_B ((0x00a4 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF00_B ((0x00a5 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF01_B ((0x00a6 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF10_B ((0x00a7 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF11_B ((0x00a8 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF20_B ((0x00a9 << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF21_B ((0x00aa << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF30_B ((0x00ab << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF31_B ((0x00ac << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF40_B ((0x00ad << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF41_B ((0x00ae << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF50_B ((0x00af << 2) + 0xfe052000) +#define AED_DRC_RELEASE_COEF51_B ((0x00b0 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF00_B ((0x00b1 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF01_B ((0x00b2 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF10_B ((0x00b3 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF11_B ((0x00b4 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF20_B ((0x00b5 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF21_B ((0x00b6 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF30_B ((0x00b7 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF31_B ((0x00b8 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF40_B ((0x00b9 << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF41_B ((0x00ba << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF50_B ((0x00bb << 2) + 0xfe052000) +#define AED_DRC_ATTACK_COEF51_B ((0x00bc << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF00_B ((0x00bd << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF01_B ((0x00be << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF10_B ((0x00bf << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF11_B ((0x00c0 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF20_B ((0x00c1 << 2) + 0xfe052000) +#define AED_MDRC_RMS_COEF21_B ((0x00c2 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF00_B ((0x00c3 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF01_B ((0x00c4 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF10_B ((0x00c5 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF11_B ((0x00c6 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF20_B ((0x00c7 << 2) + 0xfe052000) +#define AED_MDRC_RELEASE_COEF21_B ((0x00c8 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF00_B ((0x00c9 << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF01_B ((0x00ca << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF10_B ((0x00cb << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF11_B ((0x00cc << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF20_B ((0x00cd << 2) + 0xfe052000) +#define AED_MDRC_ATTACK_COEF21_B ((0x00ce << 2) + 0xfe052000) +#define AED_MDRC_THD0_B ((0x00cf << 2) + 0xfe052000) +#define AED_MDRC_THD1_B ((0x00d0 << 2) + 0xfe052000) +#define AED_MDRC_THD2_B ((0x00d1 << 2) + 0xfe052000) +#define AED_MDRC_K0_B ((0x00d2 << 2) + 0xfe052000) +#define AED_MDRC_K1_B ((0x00d3 << 2) + 0xfe052000) +#define AED_MDRC_K2_B ((0x00d4 << 2) + 0xfe052000) +#define AED_MDRC_OFFSET0_B ((0x00d5 << 2) + 0xfe052000) +#define AED_MDRC_OFFSET1_B ((0x00d6 << 2) + 0xfe052000) +#define AED_MDRC_OFFSET2_B ((0x00d7 << 2) + 0xfe052000) +#define AED_MDRC_LOW_GAIN_B ((0x00d8 << 2) + 0xfe052000) +#define AED_MDRC_MID_GAIN_B ((0x00d9 << 2) + 0xfe052000) +#define AED_MDRC_HIGH_GAIN_B ((0x00da << 2) + 0xfe052000) +#define AED_DRC_CNTL_B ((0x00db << 2) + 0xfe052000) +#define AED_DRC_LOOPBACK_CNTL_B ((0x00dc << 2) + 0xfe052000) +#define AED_MDRC_CNTL_B ((0x00dd << 2) + 0xfe052000) +#define AED_STATUS_REG ((0x00de << 2) + 0xfe052000) +//======================================================================== +// AUDIO locker - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051400 +// ----------------------------------------------- +#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe051400) +#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe051400) +#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe051400) +#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe051400) +#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe051400) +#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe051400) +#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe051400) +#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe051400) +#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe051400) +#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe051400) +#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe051400) +#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe051400) +#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe051400) +#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe051400) +#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe051400) +#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe051400) +#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe051400) +#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe051400) +#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe051400) +#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe051400) +#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe051400) +#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe051400) +#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe051400) +#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe051400) +//======================================================================== +// AUDIO VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051800 +// ----------------------------------------------- +// +// Reading file: VAD_REG.h +// +#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe051800) +#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe051800) +#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe051800) +#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe051800) +#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe051800) +#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe051800) +#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe051800) +#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe051800) +#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe051800) +#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe051800) +#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe051800) +#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe051800) +#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe051800) +#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe051800) +#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe051800) +#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe051800) +#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe051800) +#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe051800) +#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe051800) +#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe051800) +#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe051800) +#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe051800) +#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe051800) +#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe051800) +#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe051800) +#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe051800) +#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe051800) +#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe051800) +#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe051800) +#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe051800) +#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe051800) +#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe051800) +#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe051800) +#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe051800) +#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe051800) +#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe051800) +#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe051800) +#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe051800) +#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe051800) +#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe051800) +#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe051800) +#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe051800) +#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe051800) +#define VAD_LUT_WR ((0x002d << 2) + 0xfe051800) +#define VAD_LUT_RD ((0x002e << 2) + 0xfe051800) +#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe051800) +#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe051800) +#define VAD_TO_DDR ((0x0031 << 2) + 0xfe051800) +#define VAD_SYNC_CTRL0 ((0x0032 << 2) + 0xfe051800) +#define VAD_SYNC_CHNUM_ID0 ((0x0033 << 2) + 0xfe051800) +#define VAD_SYNC_CHNUM_ID1 ((0x0034 << 2) + 0xfe051800) +#define VAD_SYNC_CHNUM_ID2 ((0x0035 << 2) + 0xfe051800) +#define VAD_SYNC_CHNUM_ID3 ((0x0036 << 2) + 0xfe051800) +#define VAD_SYNC_CHNUM_ID4 ((0x0037 << 2) + 0xfe051800) +#define VAD_SYNC_CHNUM_ID5 ((0x0038 << 2) + 0xfe051800) +#define VAD_SYNC_CHNUM_ID6 ((0x0039 << 2) + 0xfe051800) +#define VAD_SYNC_CHNUM_ID7 ((0x003a << 2) + 0xfe051800) +// +// Closing file: VAD_REG.h +// +//======================================================================== +// AUDIO RESAMPLEA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe051c00 +// ----------------------------------------------- +// +// Reading file: RESAMPLE.h +// +#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe051c00) +//Bit 31:3 reserved +//Bit 2 reg_lock_rst //unsigned , default =0; +//Bit 1 reg_rsamp_rst //unsigned , default =0; +//Bit 0 reg_sw_rst //unsigned , default =0; +#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe051c00) +//Bit 31:27 reserved //unsigned , default =0; +//Bit 26 reg_watchdog_en //unsigned , default =0; +//Bit 25 reg_rsamp_rst_sel //unsigned , default =0; +//Bit 24 reg_module_bypas //unsigned , default =0; +//Bit 23:18 reg_gclk_ctrl //unsigned , default =0; +//Bit 17:13 reg_in_msb //unsigned , default =23; +//Bit 12 reg_output_en //unsigned , default =0; +//Bit 11 reg_rsamp_en //unsigned , default =0; +//Bit 10 reg_filt_en //unsigned , default =0; +//Bit 9 reg_post_en //unsigned , default =0; +//Bit 8 reg_inp_mux_mode //unsigned , default =0; +//Bit 7:4 reserved //unsigned , default =2; +//Bit 3:0 reg_inp_mux //unsigned , default =0; +#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe051c00) +//Bit 31:30 reserved //unsigned , default =0; +//Bit 29:24 reg_chx_size //unsigned , default =2; +//Bit 23:18 reserved //unsigned , default =0; +//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4 +//Bit 15:8 reg_filt_tap //unsigned , default =63; +//Bit 7:0 reg_intp_tap //unsigned , default =63; +#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe051c00) +//Bit 31:28 reserved //unsigned , default = 0; +//Bit 27:0 reg_init_phs //unsigned , default = 0; +#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe051c00) +//Bit 31 reserved //unsigned , default = 0; +//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000 +#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe051c00) +//Bit 31:24 reg_rsft_iir //unsigned , default = 23; +//Bit 23:16 reg_rsft_blnd //unsigned , default = 21; +//Bit 15:8 reg_rsft_sinc //unsigned , default = 31; +//Bit 7:0 reg_rsft_aa //unsigned , default = 31; +#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe051c00) +//Bit 31:3 reserved //unsigned +//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0; +//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0; +//Bit 0 reg_rsamp_adj_en //unsigned , default = 0; +#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe051c00) +//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8; +//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768; +#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe051c00) +//Bit 31:30 reserved //unsigned , default = 0; +//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0; +//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9; +//Bit 23:21 reserved //unsigned , default = 0; +//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1; +//Bit 15:13 reserved //unsigned , default = 0; +//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6; +//Bit 7:6 reserved //unsigned , default = 0; +//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12; +#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000; +#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8; +#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe051c00) +//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0; +#define AUDIO_RSAMP_WATCHDOG_THRD ((0x000c << 2) + 0xfe051c00) +//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000; +#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]} +#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_adj_freq +#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_diff_bak +#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_diff_dlt +#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_phase_err +#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_ki_out +#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_in_cnt +#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe051c00) +//Bit 31:0 ro_rsamp_out_cnt +#define AUDIO_RSAMP_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe051c00) +//Bit 31:0 ro_det_phase_err_var +#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef0 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef1 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef2 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef3 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe051c00) +//Bit 31:0 reg_post_coef4 //signed , default = 0; +#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe051c00) +//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe051c00) +//Bit 31:0 reg_aa_coef_data //signed , default = 0; +#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe051c00) +//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe051c00) +//Bit 31:0 reg_sinc_coef_data //signed , default = 0; +// +// Closing file: RESAMPLE.h +// +//======================================================================== +// AUDIO TOP_VAD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe054800 +// ----------------------------------------------- +#define EE_AUDIO2_CLK81_CTRL ((0x0000 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK81_EN ((0x0001 << 2) + 0xfe054800) +#define EE_AUDIO2_SW_RESET0 ((0x0002 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_GATE_EN0 ((0x0003 << 2) + 0xfe054800) +#define EE_AUDIO2_SECURITY_CTRL0 ((0x0004 << 2) + 0xfe054800) +#define EE_AUDIO2_IRQ_FIFO_CNT ((0x0007 << 2) + 0xfe054800) +#define EE_AUDIO2_DDRASYNC_STAT ((0x0008 << 2) + 0xfe054800) +#define EE_AUDIO2_MCLK_VAD_CTRL ((0x0010 << 2) + 0xfe054800) +#define EE_AUDIO2_VAD_CLK_CTRL ((0x0011 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_DLY_CTRL0 ((0x0012 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((0x0013 << 2) + 0xfe054800) +#define EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((0x0014 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((0x0015 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_PDMIN_CTRL0 ((0x0016 << 2) + 0xfe054800) +#define EE_AUDIO2_CLK_PDMIN_CTRL1 ((0x0017 << 2) + 0xfe054800) +#define EE_AUDIO2_TOVAD_CTRL0 ((0x0020 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL0 ((0x0030 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL1 ((0x0031 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CTRL2 ((0x0032 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_START_ADDR ((0x0033 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_INIT_ADDR ((0x0034 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((0x0035 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_START_ADDRB ((0x0036 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((0x0037 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_INT_ADDR ((0x0038 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_STATUS1 ((0x0039 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_STATUS2 ((0x003a << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_CTRL ((0x0040 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_SWAP0 ((0x0041 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_SWAP1 ((0x0042 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((0x0043 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_STAT ((0x0044 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE0 ((0x0050 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE1 ((0x0051 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE2 ((0x0052 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE3 ((0x0053 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE4 ((0x0054 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE5 ((0x0055 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE6 ((0x0056 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MUTE7 ((0x0057 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK0 ((0x0058 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK1 ((0x0059 << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK2 ((0x005a << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK3 ((0x005b << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK4 ((0x005c << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK5 ((0x005d << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK6 ((0x005e << 2) + 0xfe054800) +#define EE_AUDIO2_TDMIN_VAD_MASK7 ((0x005f << 2) + 0xfe054800) +#define EE_AUDIO2_EXCEPTION_IRQ_STS0 ((0x0060 << 2) + 0xfe054800) +#define EE_AUDIO2_EXCEPTION_IRQ_MASK0 ((0x0062 << 2) + 0xfe054800) +#define EE_AUDIO2_EXCEPTION_IRQ_MODE0 ((0x0064 << 2) + 0xfe054800) +#define EE_AUDIO2_EXCEPTION_IRQ_CLR0 ((0x0066 << 2) + 0xfe054800) +#define EE_AUDIO2_EXCEPTION_IRQ_INV0 ((0x0068 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHNUM_ID0 ((0x0070 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHNUM_ID1 ((0x0071 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHNUM_ID2 ((0x0072 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHNUM_ID3 ((0x0073 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHNUM_ID4 ((0x0074 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHNUM_ID5 ((0x0075 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHNUM_ID6 ((0x0076 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHNUM_ID7 ((0x0077 << 2) + 0xfe054800) +#define EE_AUDIO2_TODDR_VAD_CHSYNC_CTRL ((0x007f << 2) + 0xfe054800) +// +// Closing file: REG_LIST_AUDIO_RTL.h +// +// +// Reading file: ../spifc/rtl/spifc_reg.vh +// +//`ifdef SPIFC_REG_DEFINE +//`else +//`define SPIFC_REG_DEFINE +//`define SPIFC BASE ADDR 32'hfe00ac00 +// ----------------------------------------------- +// APB_BASE: APB2_BASE_ADDR = 0xfe00ac00 +// ----------------------------------------------- +//AHB domain regsiter. +#define SPIFC_AHB_CTRL ((0x0000 << 2) + 0xfe00ac00) + //bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request. + //bit 30. decerr_en for (AXI->AHB bridge). + //bit 29. force_incr. for ( AXI->AHB bridge). + //bit 20. ahb_idle_ctrl. 1: show idle status in C1 mode. 0: show Idle always. + //bit 19. critical word first. CWF_EN. 1: enable. 0 : disable. + //bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved. + //bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi. + //if disabled the 3 HRDATA buffer will random be used for all masters. + //bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation. + //bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation. + //bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation. + //bit 11. clr_wtchdg: 1: clear WTCHDG_STS bits in STS registers. 0 : normal. + //bit 10:0. not used. +#define SPIFC_CLK_CTRL ((0x0001 << 2) + 0xfe00ac00) + //bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable. + //bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable. + //bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable. + //bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable. + //bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable. + //bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable. + //bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode. + //bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode. + //bit 0. not used. +#define SPIFC_SEC_CTRL ((0x0002 << 2) + 0xfe00ac00) + //bit 31. ADDRESS security range enable. 1 = enable; 0: disable. + //bit 14. range6 enable: 1: enable; 0 : disable. + //bit 13. range5 enable: 1: enable; 0 : disable. + //bit 12. range4 enable: 1: enable; 0 : disable. + //bit 11. range3 enable: 1: enable; 0 : disable. + //bit 10. range2 enable: 1: enable; 0 : disable. + //bit 9. range1 enable: 1: enable; 0 : disable. + //bit 8. range0 enable: 1: enable; 0 : disable. +#define SPIFC_APB_CTRL ((0x0003 << 2) + 0xfe00ac00) + //bit 31 APB control lock bit. if this bit = 1, this register can't access any more. + //bit 30~16. Not used. + //bit 15:8. SPI clock domain regsiter APB access control. each bit for one APB user ID. + //bit 7:0 AHB clock domain register APB access control. each bit for one APB user ID. +#define SPIFC_RANGE0_STA ((0x0010 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE0_EDA ((0x0011 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +//HMASTER[4:0] defines: +//5'h0: CPU secure data access. +//5'h1: CPU secure instruction access. +//5'h2: CPU non-secure data access. +//5'h3: CPU non-secure instruction access. +//5'h4: DSPA secure data access. +//5'h5: DSPA secure instruction access. +//5'h6: DSPA non-secure data access. +//5'h7: DSPA non-secure instruction access. +//5'h08~5'h0f. for DMA access with HMASTER[2:0] as DMA thread ID. +//5'h10 all other REQUEST not CPU DSP and DMA. +//5'h1x. Not used. +#define SPIFC_RANGE0_CTRL ((0x0012 << 2) + 0xfe00ac00) + // AHB secruity range 0 control. + // bit 16. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + //bit 15:8 range 0 access control for DMA access. + //bit 15 range 0 access control for DMA thread 7 + //bit 14 range 0 access control for DMA Thread 6 + //bit 13 range 0 access control for DMA Thread 5. + //bit 12 range 0 access control for DMA Thread 4. + // bit 11. range 0 access control for DMA thread 3 + // bit 10. range 0 access control for DMA Thread 2 + // bit 9. range 0 access control for DMA Thread 1. + // bit 8. range 0 access control for DMA Thread 0. + // bit 7. range 0 access control for HMASTER == 7 //DSPA secure instruction access. + // bit 6. range 0 access control for HMASTER == 6 //DSPA secure data access. + // bit 5. range 0 access control for HMASTER == 5 //DSPA non secure instruction access + // bit 4. range 0 access control for HMASTER == 4 //DSPA non secure data access. + // bit 3. range 0 access control for HMASTER == 3 //CPU secure instruction access. + // bit 2. range 0 access control for HMASTER == 2 //CPU secure data access. + // bit 1. range 0 access control for HMASTER == 1 //CPU non secure instruction access + // bit 0. range 0 access control for HMASTER == 0 //CPU non secure data access. +#define SPIFC_RANGE1_STA ((0x0013 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE1_EDA ((0x0014 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE1_CTRL ((0x0015 << 2) + 0xfe00ac00) + // AHB secruity range 1 control. + //bit 15:8 range 1 access control for DMA access. + //bit 15 range 1 access control for DMA thread 7 + //bit 14 range 1 access control for DMA Thread 6 + //bit 13 range 1 access control for DMA Thread 5. + //bit 12 range 1 access control for DMA Thread 4. + // bit 11. range 1 access control for DMA thread 3 + // bit 10. range 1 access control for DMA Thread 2 + // bit 9. range 1 access control for DMA Thread 1. + // bit 8. range 1 access control for DMA Thread 0. + // bit 7. range 1 access control for HMASTER == 7 Not used. + // bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 1 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 1 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 1 access control for HMASTER == 3 //DSPA secure + // bit 2. range 1 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 1 access control for HMASTER == 1 //CPU secure access + // bit 0. range 1 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE2_STA ((0x0016 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE2_EDA ((0x0017 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE2_CTRL ((0x0018 << 2) + 0xfe00ac00) + // AHB secruity range 2 control. + //bit 15:8 range 2 access control for DMA access. + //bit 15 range 2 access control for DMA thread 7 + //bit 14 range 2 access control for DMA Thread 6 + //bit 13 range 2 access control for DMA Thread 5. + //bit 12 range 2 access control for DMA Thread 4. + // bit 11. range 2 access control for DMA thread 3 + // bit 10. range 2 access control for DMA Thread 2 + // bit 9. range 2 access control for DMA Thread 1. + // bit 8. range 2 access control for DMA Thread 0. + // bit 7. range 2 access control for HMASTER == 7 Not used. + // bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 2 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 2 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 2 access control for HMASTER == 3 //DSPA secure + // bit 2. range 2 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 2 access control for HMASTER == 1 //CPU secure access + // bit 0. range 2 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE3_STA ((0x0019 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE3_EDA ((0x001a << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE3_CTRL ((0x001b << 2) + 0xfe00ac00) + // AHB secruity range 3 control. + //bit 15:8 range 3 access control for DMA access. + //bit 15 range 3 access control for DMA thread 7 + //bit 14 range 3 access control for DMA Thread 6 + //bit 13 range 3 access control for DMA Thread 5. + //bit 12 range 3 access control for DMA Thread 4. + // bit 11. range 3 access control for DMA thread 3 + // bit 10. range 3 access control for DMA Thread 2 + // bit 9. range 3 access control for DMA Thread 1. + // bit 8. range 3 access control for DMA Thread 0. + // bit 7. range 3 access control for HMASTER == 7 Not used. + // bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 3 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 3 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 3 access control for HMASTER == 3 //DSPA secure + // bit 2. range 3 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 3 access control for HMASTER == 1 //CPU secure access + // bit 0. range 3 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE4_STA ((0x001c << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE4_EDA ((0x001d << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE4_CTRL ((0x001e << 2) + 0xfe00ac00) + // AHB secruity range 4 control. + //bit 15:8 range 4 access control for DMA access. + //bit 15 range 4 access control for DMA thread 7 + //bit 14 range 4 access control for DMA Thread 6 + //bit 13 range 4 access control for DMA Thread 5. + //bit 12 range 4 access control for DMA Thread 4. + // bit 11. range 4 access control for DMA thread 3 + // bit 10. range 4 access control for DMA Thread 2 + // bit 9. range 4 access control for DMA Thread 1. + // bit 8. range 4 access control for DMA Thread 0. + // bit 7. range 4 access control for HMASTER == 7 Not used. + // bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 4 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 4 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 4 access control for HMASTER == 3 //DSPA secure + // bit 2. range 4 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 4 access control for HMASTER == 1 //CPU secure access + // bit 0. range 4 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE5_STA ((0x001f << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE5_EDA ((0x0021 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE5_CTRL ((0x0020 << 2) + 0xfe00ac00) + // AHB secruity range 5 control. + //bit 15:8 range 5 access control for DMA access. + //bit 15 range 5 access control for DMA thread 7 + //bit 14 range 5 access control for DMA Thread 6 + //bit 13 range 5 access control for DMA Thread 5. + //bit 12 range 5 access control for DMA Thread 4. + // bit 11. range 5 access control for DMA thread 3 + // bit 10. range 5 access control for DMA Thread 2 + // bit 9. range 5 access control for DMA Thread 1. + // bit 8. range 5 access control for DMA Thread 0. + // bit 7. range 5 access control for HMASTER == 7 Not used. + // bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 5 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 5 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 5 access control for HMASTER == 3 //DSPA secure + // bit 2. range 5 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 5 access control for HMASTER == 1 //CPU secure access + // bit 0. range 5 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE6_STA ((0x0022 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE6_EDA ((0x0023 << 2) + 0xfe00ac00) + //bit 28 :6. + //AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6. + //bit 5:0. always 0. +#define SPIFC_RANGE6_CTRL ((0x0024 << 2) + 0xfe00ac00) + // AHB secruity range 6 control. + //bit 15:8 range 6 access control for DMA access. + //bit 15 range 6 access control for DMA thread 7 + //bit 14 range 6 access control for DMA Thread 6 + //bit 13 range 6 access control for DMA Thread 5. + //bit 12 range 6 access control for DMA Thread 4. + // bit 11. range 6 access control for DMA thread 3 + // bit 10. range 6 access control for DMA Thread 2 + // bit 9. range 6 access control for DMA Thread 1. + // bit 8. range 6 access control for DMA Thread 0. + // bit 7. range 6 access control for HMASTER == 7 Not used. + // bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 6 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 6 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 6 access control for HMASTER == 3 //DSPA secure + // bit 2. range 6 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 6 access control for HMASTER == 1 //CPU secure access + // bit 0. range 6 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_RANGE7_CTRL ((0x0025 << 2) + 0xfe00ac00) + // AHB secruity range 7( default range) control. + //bit 15:8 range 7 access control for DMA access. + //bit 15 range 7 access control for DMA thread 7 + //bit 14 range 7 access control for DMA Thread 6 + //bit 13 range 7 access control for DMA Thread 5. + //bit 12 range 7 access control for DMA Thread 4. + // bit 11. range 7 access control for DMA thread 3 + // bit 10. range 7 access control for DMA Thread 2 + // bit 9. range 7 access control for DMA Thread 1. + // bit 8. range 7 access control for DMA Thread 0. + // bit 7. range 7 access control for HMASTER == 7 Not used. + // bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA. + // bit 5. range 7 access control for HMASTER == 5 //DSPB non secure + // bit 4. range 7 access control for HMASTER == 4 //DSPB non secure + // bit 3. range 7 access control for HMASTER == 3 //DSPA secure + // bit 2. range 7 access control for HMASTER == 2 //DSPA non secure + // bit 1. range 7 access control for HMASTER == 1 //CPU secure access + // bit 0. range 7 access control for HMASTER == 0 //CPU non secure. +#define SPIFC_AHB_WTCH_CTRL ((0x0026 << 2) + 0xfe00ac00) + //bit 16. Wtch dog enable. + //bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response. +#define SPIFC_SEC_VIO0 ((0x0027 << 2) + 0xfe00ac00) + //bit 31:0 VIO ADDR +#define SPIFC_SEC_VIO1 ((0x0028 << 2) + 0xfe00ac00) + //bit 31. AHB VIO status. write 1 to clear the error info. + //bit 30:6 Not used. + //bit 5:1 HMASTER. + //bit 0 HWRITE. +#define SPIFC_AHB_STS ((0x0029 << 2) + 0xfe00ac00) + //bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy. + //bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing. + //bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle. + //bit 28. WTCHDG_STS. 1: AHB BUS access watchdog triggered. 0: no watchdo triggered. + //bit 27:21. not used. + //bit 20:16. WTCHDOG triggered AHB Master. + //bit 15:0. not used. +#define SPIFC_AHB_WTCH_ADDR ((0x0030 << 2) + 0xfe00ac00) + //bit 27:0 WTCHDG triggered AHB ADDRESS +//SPI cts_spi_clk domain regsiter. +#define SPIFC_USER_CTRL0 ((0x0080 << 2) + 0xfe00ac00) + //bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL. + //bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command. + //bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash. +#define SPIFC_USER_CTRL1 ((0x0081 << 2) + 0xfe00ac00) + //bit 31. not used. + //bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period. + //bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode. + //bit 27:20. user command code. the code need to send in command period. + //bit 19. user address cycle enable. + //bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode. + //bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes. + //bit 14 user datout enable. + //bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data. + //bit 12 user data output source. 0: from data buffer. 1: from status register. + //bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode. + //bit 9:0 User data out bytes num. +#define SPIFC_USER_CTRL2 ((0x0082 << 2) + 0xfe00ac00) + //bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles. + //bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode. + //bit 28:23 user dummy clock cycle number. + //bit 19:16. user command input/output direction control. 000000: right after the last output. + // 1: after the first cycle of dummy cycle. + // ..... + // 4'hf: right before the datin cycle. + //bit 15:8. data on the dummy cycle after the first byte. + //bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode. +#define SPIFC_USER_CTRL3 ((0x0083 << 2) + 0xfe00ac00) + //bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle. + //bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer. + //bit 29: 1: enable datain data AES describle. 0: not use AES. + //bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode. + //bit 25:16. user data in data bytes. how many bytes of user datain expected. +#define SPIFC_USER_ADDR ((0x0084 << 2) + 0xfe00ac00) + //bit 31:0. 32bits user address. +#define SPIFC_AHB_REQ_CTRL ((0x0085 << 2) + 0xfe00ac00) + //bit 31. AHB request enable. + //bit 30 AHB cmd_en. command cycle enable. + //bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. + //bit 27:20:.AHB command code. + //bit 19. ahb request address cycle enable. + //bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. + //bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes. + //bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle. + //bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode. + //bit 7 DATA IN AES enable. 1: enable 0: disable. + //bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting. +#define SPIFC_AHB_REQ_CTRL1 ((0x0086 << 2) + 0xfe00ac00) + //bit 31. ahb Dummy enable. + //bit 30:29. ahb dummy mode. + //bit 28:23. ahb request dummy clock cycles. + //bit 15:0. ahb dummy period output data. +#define SPIFC_AHB_REQ_CTRL2 ((0x0087 << 2) + 0xfe00ac00) + //bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE. + // if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary). + // if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE. + //00 : 64byte boundary. + //01 : 32byte boundary. + //10 : 16byte boundary. + //11 : reserved. +#define SPIFC_ACTIMING0 ((0x0088 << 2) + 0xfe00ac00) + //bit 31:30. tSLCH + //bit 29:28 tCLSH + //bit 20:16 tSHWL + //bit 15:12 tSHSL2 + //bit 11:8 tSHSL1 + //bit 7:0 tWHSL +#define SPIFC_ACTIMING1 ((0x0089 << 2) + 0xfe00ac00) + //bit 31. D2 pin WP_n function enable. + //bit 30. D2 Pin value in WP_n fucntion. + //bit 29. D3 Pin HOLD_n function enable. + //bit 8. DTR mode. not support. + //bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay. + //bit 3:0. not used. +#define SPIFC_ACTIMING2 ((0x008a << 2) + 0xfe00ac00) + //bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data. + //bit [3:0] spi clock input pin delay adjustment. +//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM . +// since each APB access is 32bits. So we use word address as APB read/write address. +// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0. +#define SPIFC_DBUF_CTRL ((0x0090 << 2) + 0xfe00ac00) + //bit 31. 1 = write DBUF. 0 : read DBUF. + //bit 30. 1. = auto update address. 0 don't change address. + //bit 7:0 DBUF address unit 32bits. +#define SPIFC_DBUF_DATA ((0x0091 << 2) + 0xfe00ac00) + //bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF. +#define SPIFC_USER_DBUF_ADDR ((0x0092 << 2) + 0xfe00ac00) + //bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0. +#define SPIFC_FLASH_STATUS ((0x00a0 << 2) + 0xfe00ac00) +#define SPIFC_STATUS ((0x00a1 << 2) + 0xfe00ac00) + //bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready. + //bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy. +#define SPIFC_CTRL ((0x00a2 << 2) + 0xfe00ac00) + //bit 15:14. mempd for DBUF MEMORY. + //bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable. + //bit 12. spifc controller clock disable. 1 = disable. 0 = enable. + //bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable. + //bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable. + //bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode. + //bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode. + //bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode. +//`endif +// +// Closing file: ../spifc/rtl/spifc_reg.vh +// +// +// Reading file: ../mmc_new/dmc_clk_freq/rtl/dmc_clk_freq.vh +// +//`ifdef DMC_FREQ_REG_DEFINE +//`else +//`define DMC_FREQ_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfe024c00 +// ----------------------------------------------- +//`define DMC_FREQ_REG_BASE 32'hfe024c00 +#define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xfe024c00) + //bit 31 : ddr_gp_pll_rst. default 1 + //bit 30 : ddr_gp_pll_rstn. default 0. + //bit 29 : ddr_gp_pll_lk_rstn default 0 + //bit 28 : ddr_gp_pll_en. default 0 + //bit 25:24 : ddr_gp_pll_output_od2 default 0 + //bit 23:20 : ddr_gp_pll_od1 default 0 + //bit 17:16 : ddr_gp_pll_od_s1 default 0 + //bit 15 : ddr_gp_pll_clk1x_inv_sel default 0 + //bit 14 : ddr_gp_pll_clk4x_by_en default 0 + //bit 12:8 : ddr_gp_pll_n default 0 + //bit 7:0 : ddr_gp_pll_pll_div_m default 0 +#define AM_DDR_PLL_CNTL1 ((0x0001 << 2) + 0xfe024c00) + //bit 31 : ddr_sdm_pll_rst default 1 + //bit 30 : ddr_sdm_pll_e default 0. + //bit 29 : ddr_sdm_pll_dvdd_pd default 0 + //bit 28 : ddr_sdm_pll_free_run default 0 + //bit 17:16 : ddr_sdm_pll_output_od default 1 + //bit 12:8 : ddr_sdm_pll_n default 1 + //bit 7:0 : ddr_sdm_pll_div_m +#define AM_DDR_PLL_CNTL2 ((0x0002 << 2) + 0xfe024c00) + //default 0x0 + //bit 31:24 : ddr_sdm_pll_reve + //bit 23:20 : ddr_sdm_pll_cp_adj + //bit 19:16 : ddr_sdm_pll_bias_icp_adj + //bit 15:14 : ddr_sdm_pll_lock_long + //bit 12 : ddr_sdm_pll_dead_time_select + //bit 11 : ddr_sdm_pll_cp_offset_en + //bit 10 : ddr_sdm_pll_ldo0p8_adj + //bit 9 : ddr_sdm_pll_ldo1p5_adj + //bit 8 : ddr_sdm_pll_lock_f + //bit 7:6 : ddr_sdm_pll_r3_cnt + //bit 5:4 : ddr_sdm_pll_r2_cnt + //bit 3:2 : ddr_sdm_pll_c3_cnt + //bit 1:0 : ddr_sdm_pll_c2_cnt. +#define AM_DDR_PLL_CNTL3 ((0x0003 << 2) + 0xfe024c00) + //default 0x0 + //bit 31:4 : not used. + //bit 3:2 : ddr_sdm_pll_ini_vco_adj + //bit 1:0 : ddr_sdm_pll_lkdet_sel +#define AM_DDR_PLL_CNTL4 ((0x0004 << 2) + 0xfe024c00) + //default 0x0 + //bit 31 : ddr_gp_pll_dpll_load + //bit 30 : ddr_gp_pll_free_run + //bit 29:28 : ddr_gp_pll_judge_win + //bit 27 : ddr_gp_pll_ldo0p8_ref_mux + //bit 26 : ddr_gp_pll_ldo1p5_adj + //bit 25 : ddr_gp_pll_ldo0p8_daj + //bit 24:21 : ddr_gp_pll_ssc_str_m + //bit 20:18 : ddr_gp_pll_fref_sel + //bit 17:16 : ddr_gp_pll_lk_vco_div_od + //bit 15:12 : ddr_gp_pll_cp_icp_ctrl + //bit 11:8 : ddr_gp_pll_ssc_dep_sel + //bit 7 : ddr_gp_pll_dead_time_select + //bit 6:0 : ddr_gp_pll_m_s1 +#define AM_DDR_PLL_CNTL5 ((0x0005 << 2) + 0xfe024c00) + //default 0x0 + //bit 31:24 : ddr_gp_pll_reve + //bit 23:22 : ddr_gp_pll_ss_mode + //bit 21:20 : ddr_gp_pll_ini_vco_adj + //bit 19:16 : ddr_gp_pll_bias_icp_ctrl + //bit 15 : ddr_gp_pll_clk_by_sel + //bit 14 : ddr_gp_pll_cp_offset_en + //bit 13 : ddr_gp_pll_lk_width + //bit 12 : ddr_gp_pll_lk_bypass + //bit 11 : ddr_gp_pll_sdm_en + //bit 10 : ddr_gp_pll_shift_en + //bit 9 : ddr_gp_pll_load_en + //bit 8:4 : ddr_gp_pll_vco_limit + //bit 3:2 : ddr_gp_pll_shift_v + //bit 1:0 : ddr_gp_pll_os_ssc +#define AM_DDR_PLL_CNTL6 ((0x0006 << 2) + 0xfe024c00) + //default 0x0 + //bit 31:30 : ddr_gp_pll_c3_cnt + //bit 29:28 : ddr_gp_pll_c2_cnt + //bit 27:26 : ddr_gp_pll_r3_cnt + //bit 25:24 : ddr_gp_pll_r2_cnt + //bit 23:19 : ddr_gp_pll_inte_num + //bit 18:0 : ddr_gp_pll_fracin +#define AM_DDR_PLL_STS ((0x0007 << 2) + 0xfe024c00) + //bit 31 : DDR PLL lock bit. 1 = locked. 0 = not locked. + //bit 30:0 : not used. +#define DDR_CLK_CNTL ((0x0008 << 2) + 0xfe024c00) + //bit 31 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion. + // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again. + //bit 30. ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin. + //bit 29. not used. + //bit 28. clock generation logic soft reset. 0 = reset. + //bit 27. phy_4xclk phase inverter.. + //bit 25. DDRPHY DfiClk/DMC clock selection. 1: AM_PLL clk output /2. 0: directly output from AM_PLL . + //bit 24. enable AM_PLL CLK output /2 function. 1: enable. 0: disable. if try to use this clkoutput/2 function. + //bit 26. pll_freq divide/2. 1: use pll div/2 clock as the n_clk. 0: use pll clock as n_clk. this setting is used for the synopsys DDR PHY PLL fast lock mode. + //bit 2. enable dmc_clk. + //bit 1. not used. + //bit 0. enable LPDDR4-PHY clock +#define DDR_PHY_CTRL ((0x0009 << 2) + 0xfe024c00) + // LPDDR4 power on reset need to special combination of PwrOkIn and phy_reset_n. + //bit 31: DDr PHY power on status. read only. + //bit 4. DDR PHY PwrOkIn pin. + //bit 1. DDR PHY APB soft reset_n. + //bit 0. phy_reset_n. +#define AM_DDR_PLL_FREQ1_OD ((0x000c << 2) + 0xfe024c00) + //freqency set 1 PLL OD and OD1 setting. when change to freqency 1 will use this setting. +//frequency set 0 use original DDR_PLL_CNTL0 setting. + //bit 8 currunt FREQ selection. it can forced to change to select which freqency to select, or it can auto changed by FREQ change hardware. + //bit 7:0 is the FREQ1 GP_PLL output clock setting. + //bit 7 gp_pll_clk1x_inv_sel + //bit 6 gp_pll_clk4x_by_en + //bit 5:4 gp_pll_output_od2. + //bit 3:0. gp_pll_od1. +//`endif +// +// Closing file: ../mmc_new/dmc_clk_freq/rtl/dmc_clk_freq.vh +// +// +// Reading file: ../mmc_new/dmc/rtl/dmc_sec.vh +// +//`ifdef DMC_SEC_REG_DEFINE +//`else +//`define DMC_SEC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfe025000 +// ----------------------------------------------- +//`define DMC_SEC_REG_BASE 32'hfe025000 +// DMC ID assignment. +// ID[13 :0] total 14 bit ID. +// ID[4:0]: for MASTER IDs. +// 0: A55 CPU. +// 1: DSPA +// 2: DSPB +// 3: WAVE +// 4: GDC +// 5: GE2D +// 6: ISP +// 7: NNA +// 8: JPEG +// 9~15: not used in C1. +// 16 : Device. need to look at ID bit [11:9] to see the sub module master. +// 16 : for Device. need to look at ID bit [11:9] to see the sub module master. +// 17 : for USB AHB device. +// 18 : for USB AXI host. +// 19 : for I2C debug input. +// 20~30: Not used in C1 +// 31: DMC internal test channel. +// Device master is for small periphs. it is consists of 8 sub modules and identified with ID bits [11:9] +// bit[11:9] == 0 : ETH +// bit[11:9] == 1 : SPICC_A +// bit[11:9] == 2 : SPICC_B +// bit[11:9] == 3 : SD_EMMCA +// bit[11:9] == 4 : SD_EMMCB +// bit[11:9] == 5 : AUDIO. For AUDIO need to check ID[8:5] for detail. +// ID[8:5] == 0: TO_DDR A +// ID[8:5] == 1: TO_DDR B +// ID[8:5] == 4: FROM_DDR A +// ID[8:5] == 5: FROM_DDR B +// bit[11:9] == 6 : DMA. For DMC need to check ID [8:6] for totoal 8 threads IDs. +// bit[11:9] == 7 : NAND_EMMCC +// Total 16 address regions can be defined in All DDR address space. +// The first 15 region can be defined by start address and end address in 4Kbyte boundary. The 16th range is all other space not defined by the first 15 regions. +// all the 15 regions can be enabled or disabled seperately. Each range use security level bit to select one of the two des key to do data scramble. +// The region can be overlapped or crossover. For one transaction, DMC would check the address from region 0 to 15. +// DMC would use the policy defined in the region that this transaction address hit first. +#define DMC_SEC_RANGE0_CTRL ((0x0000 << 2) + 0xfe025000) + //bit 31:16 | 0 | range0_eda | range 0 end address higher 16bits. + //bit 15:0 | 0 | range0_sta | range 0 start address higher 16bits. +#define DMC_SEC_RANGE0_CTRL1 ((0x0001 << 2) + 0xfe025000) + //bit 7:5 | 0 | range0_secrity_level | range0 secruity level for DMC and DEMUX only. + //bit 4 | 0 | range0_prot_en | range0 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range0_local_des_en | range0 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not. + //bit 2 | 0 | range0_lock | lock range 0 registers. write 1 to lock range 0 register. can't change anymore. + //bit 1 | 0 | range0_key_sel | range 0 data describle key selection. 1 : key1. 0 : key0. + //bit 0 | 0 | range0_en | range 0 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE1_CTRL ((0x0002 << 2) + 0xfe025000) + //bit 31:16 | 0 | range1_eda | range 1 end address higher 16bits. + //bit 15:0 | 0 | range1_sta | range 1 start address higher 16bits. +#define DMC_SEC_RANGE1_CTRL1 ((0x0003 << 2) + 0xfe025000) + //bit 7:5 | 0 | range1_secrity_level | range1 secruity level for DMC and DEMUX only. + //bit 4 | 0 | range1_prot_en | range1 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range1_local_des_en | range1 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not. + //bit 2 | 0 | range1_lock | lock range 1 registers. write 1 to lock range 1 register. can't change anymore. + //bit 1 | 0 | range1_key_sel | range 1 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | range1_en | range 0 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE2_CTRL ((0x0004 << 2) + 0xfe025000) + //bit 31:16 | 0 | range2_eda | range 2 end address higher 16bits. + //bit 15:0 | 0 | range2_sta | range 2 start address higher 16bits. +#define DMC_SEC_RANGE2_CTRL1 ((0x0005 << 2) + 0xfe025000) + //bit 7:5 | 0 | range2_secrity_level | range2 secruity level for DMC and DEMUX only. + //bit 4 | 0 | range2_prot_en | range2 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range2_local_des_en | range2 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not. + //bit 2 | 0 | range2_lock | lock range 2 registers. write 1 to lock range 2 register. can't change anymore. + //bit 1 | 0 | range2_key_sel | range 2 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | range2_en | range 2 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE3_CTRL ((0x0006 << 2) + 0xfe025000) + //bit 31:16 | 0 | range3_eda | range 3 end address higher 16bits. + //bit 15:0 | 0 | range3_sta | range 3 start address higher 16bits. +#define DMC_SEC_RANGE3_CTRL1 ((0x0007 << 2) + 0xfe025000) + //bit 7:5 | 0 | range3_secrity_level | range3 secruity level for DMC and DEMUX only. + //bit 4 | 0 | range3_prot_en | range3 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range3_local_des_en | range3 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not. + //bit 2 | 0 | range3_lock | lock range 3 registers. write 1 to lock range 3 related registers. can't change anymore. + //bit 1 | 0 | range3_key_sel | range 3 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | range3_en | range 3 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE4_CTRL ((0x0008 << 2) + 0xfe025000) + //bit 31:16 | 0 | range4_eda | range 4 end address higher 16bits. + //bit 15:0 | 0 | range4_sta | range 4 start address higher 16bits. +#define DMC_SEC_RANGE4_CTRL1 ((0x0009 << 2) + 0xfe025000) + //bit 7:5 | 0 | range4_secrity_level | range4 secruity level for DMC and DEMUX only. + //bit 4 | 0 | range4_prot_en | range4 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range4_local_des_en | range4 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not. + //bit 2 | 0 | range4_lock | lock range 4 registers. write 1 to lock range 4 related registers. can't change anymore. + //bit 1 | 0 | range4_key_sel | range 4 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | range4_en | range 4 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE5_CTRL ((0x000a << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_CTRL1 ((0x000b << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_CTRL ((0x000c << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_CTRL1 ((0x000d << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_CTRL ((0x000e << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_CTRL1 ((0x000f << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_CTRL ((0x0010 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_CTRL1 ((0x0011 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_CTRL ((0x0012 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_CTRL1 ((0x0013 << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_CTRL ((0x0014 << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_CTRL1 ((0x0015 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_CTRL ((0x0016 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_CTRL1 ((0x0017 << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_CTRL ((0x0018 << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_CTRL1 ((0x0019 << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_CTRL ((0x001a << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_CTRL1 ((0x001b << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_CTRL ((0x001c << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_CTRL1 ((0x001d << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_CTRL1 ((0x001f << 2) + 0xfe025000) +//per range per sub ID access enable. +#define DMC_SEC_RANGE0_RID_CTRL0 ((0x0020 << 2) + 0xfe025000) + //range_rd_sid_en[31:0]; +#define DMC_SEC_RANGE0_RID_CTRL1 ((0x0021 << 2) + 0xfe025000) + //range_rd_sid_en[63:32]; +#define DMC_SEC_RANGE0_RID_CTRL2 ((0x0022 << 2) + 0xfe025000) + //range_rd_sid_en[95:64]; +#define DMC_SEC_RANGE0_RID_CTRL3 ((0x0023 << 2) + 0xfe025000) + //range_rd_sid_en[127:96]; +#define DMC_SEC_RANGE0_RID_CTRL4 ((0x0024 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_RID_CTRL0 ((0x0026 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_RID_CTRL1 ((0x0027 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_RID_CTRL2 ((0x0028 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_RID_CTRL3 ((0x0029 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_RID_CTRL4 ((0x002a << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_RID_CTRL0 ((0x002c << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_RID_CTRL1 ((0x002d << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_RID_CTRL2 ((0x002e << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_RID_CTRL3 ((0x002f << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_RID_CTRL4 ((0x0030 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_RID_CTRL0 ((0x0032 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_RID_CTRL1 ((0x0033 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_RID_CTRL2 ((0x0034 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_RID_CTRL3 ((0x0035 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_RID_CTRL4 ((0x0036 << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_RID_CTRL0 ((0x0038 << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_RID_CTRL1 ((0x0039 << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_RID_CTRL2 ((0x003a << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_RID_CTRL3 ((0x003b << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_RID_CTRL4 ((0x003c << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_RID_CTRL0 ((0x003e << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_RID_CTRL1 ((0x003f << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_RID_CTRL2 ((0x0040 << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_RID_CTRL3 ((0x0041 << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_RID_CTRL4 ((0x0042 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_RID_CTRL0 ((0x0044 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_RID_CTRL1 ((0x0045 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_RID_CTRL2 ((0x0046 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_RID_CTRL3 ((0x0047 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_RID_CTRL4 ((0x0048 << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_RID_CTRL0 ((0x004a << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_RID_CTRL1 ((0x004b << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_RID_CTRL2 ((0x004c << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_RID_CTRL3 ((0x004d << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_RID_CTRL4 ((0x004e << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_RID_CTRL0 ((0x0050 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_RID_CTRL1 ((0x0051 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_RID_CTRL2 ((0x0052 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_RID_CTRL3 ((0x0053 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_RID_CTRL4 ((0x0054 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_RID_CTRL0 ((0x0056 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_RID_CTRL1 ((0x0057 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_RID_CTRL2 ((0x0058 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_RID_CTRL3 ((0x0059 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_RID_CTRL4 ((0x005a << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_RID_CTRL0 ((0x005c << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_RID_CTRL1 ((0x005d << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_RID_CTRL2 ((0x005e << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_RID_CTRL3 ((0x005f << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_RID_CTRL4 ((0x0060 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_RID_CTRL0 ((0x0062 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_RID_CTRL1 ((0x0063 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_RID_CTRL2 ((0x0064 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_RID_CTRL3 ((0x0065 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_RID_CTRL4 ((0x0066 << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_RID_CTRL0 ((0x0068 << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_RID_CTRL1 ((0x0069 << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_RID_CTRL2 ((0x006a << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_RID_CTRL3 ((0x006b << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_RID_CTRL4 ((0x006c << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_RID_CTRL0 ((0x006e << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_RID_CTRL1 ((0x006f << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_RID_CTRL2 ((0x0070 << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_RID_CTRL3 ((0x0071 << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_RID_CTRL4 ((0x0072 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_RID_CTRL0 ((0x0074 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_RID_CTRL1 ((0x0075 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_RID_CTRL2 ((0x0076 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_RID_CTRL3 ((0x0077 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_RID_CTRL4 ((0x0078 << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_RID_CTRL0 ((0x007a << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_RID_CTRL1 ((0x007b << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_RID_CTRL2 ((0x007c << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_RID_CTRL3 ((0x007d << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_RID_CTRL4 ((0x007e << 2) + 0xfe025000) +//per range per sub ID access enable. +#define DMC_SEC_RANGE0_WID_CTRL0 ((0x0080 << 2) + 0xfe025000) +#define DMC_SEC_RANGE0_WID_CTRL1 ((0x0081 << 2) + 0xfe025000) +#define DMC_SEC_RANGE0_WID_CTRL2 ((0x0082 << 2) + 0xfe025000) +#define DMC_SEC_RANGE0_WID_CTRL3 ((0x0083 << 2) + 0xfe025000) +#define DMC_SEC_RANGE0_WID_CTRL4 ((0x0084 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_WID_CTRL0 ((0x0086 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_WID_CTRL1 ((0x0087 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_WID_CTRL2 ((0x0088 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_WID_CTRL3 ((0x0089 << 2) + 0xfe025000) +#define DMC_SEC_RANGE1_WID_CTRL4 ((0x008a << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_WID_CTRL0 ((0x008c << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_WID_CTRL1 ((0x008d << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_WID_CTRL2 ((0x008e << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_WID_CTRL3 ((0x008f << 2) + 0xfe025000) +#define DMC_SEC_RANGE2_WID_CTRL4 ((0x0090 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_WID_CTRL0 ((0x0092 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_WID_CTRL1 ((0x0093 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_WID_CTRL2 ((0x0094 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_WID_CTRL3 ((0x0095 << 2) + 0xfe025000) +#define DMC_SEC_RANGE3_WID_CTRL4 ((0x0096 << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_WID_CTRL0 ((0x0098 << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_WID_CTRL1 ((0x0099 << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_WID_CTRL2 ((0x009a << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_WID_CTRL3 ((0x009b << 2) + 0xfe025000) +#define DMC_SEC_RANGE4_WID_CTRL4 ((0x009c << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_WID_CTRL0 ((0x009e << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_WID_CTRL1 ((0x009f << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_WID_CTRL2 ((0x00a0 << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_WID_CTRL3 ((0x00a1 << 2) + 0xfe025000) +#define DMC_SEC_RANGE5_WID_CTRL4 ((0x00a2 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_WID_CTRL0 ((0x00a4 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_WID_CTRL1 ((0x00a5 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_WID_CTRL2 ((0x00a6 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_WID_CTRL3 ((0x00a7 << 2) + 0xfe025000) +#define DMC_SEC_RANGE6_WID_CTRL4 ((0x00a8 << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_WID_CTRL0 ((0x00aa << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_WID_CTRL1 ((0x00ab << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_WID_CTRL2 ((0x00ac << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_WID_CTRL3 ((0x00ad << 2) + 0xfe025000) +#define DMC_SEC_RANGE7_WID_CTRL4 ((0x00ae << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_WID_CTRL0 ((0x00b0 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_WID_CTRL1 ((0x00b1 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_WID_CTRL2 ((0x00b2 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_WID_CTRL3 ((0x00b3 << 2) + 0xfe025000) +#define DMC_SEC_RANGE8_WID_CTRL4 ((0x00b4 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_WID_CTRL0 ((0x00b6 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_WID_CTRL1 ((0x00b7 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_WID_CTRL2 ((0x00b8 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_WID_CTRL3 ((0x00b9 << 2) + 0xfe025000) +#define DMC_SEC_RANGE9_WID_CTRL4 ((0x00ba << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_WID_CTRL0 ((0x00bc << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_WID_CTRL1 ((0x00bd << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_WID_CTRL2 ((0x00be << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_WID_CTRL3 ((0x00bf << 2) + 0xfe025000) +#define DMC_SEC_RANGE10_WID_CTRL4 ((0x00c0 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_WID_CTRL0 ((0x00c2 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_WID_CTRL1 ((0x00c3 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_WID_CTRL2 ((0x00c4 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_WID_CTRL3 ((0x00c5 << 2) + 0xfe025000) +#define DMC_SEC_RANGE11_WID_CTRL4 ((0x00c6 << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_WID_CTRL0 ((0x00c8 << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_WID_CTRL1 ((0x00c9 << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_WID_CTRL2 ((0x00ca << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_WID_CTRL3 ((0x00cb << 2) + 0xfe025000) +#define DMC_SEC_RANGE12_WID_CTRL4 ((0x00cc << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_WID_CTRL0 ((0x00ce << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_WID_CTRL1 ((0x00cf << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_WID_CTRL2 ((0x00d0 << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_WID_CTRL3 ((0x00d1 << 2) + 0xfe025000) +#define DMC_SEC_RANGE13_WID_CTRL4 ((0x00d2 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_WID_CTRL0 ((0x00d4 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_WID_CTRL1 ((0x00d5 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_WID_CTRL2 ((0x00d6 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_WID_CTRL3 ((0x00d7 << 2) + 0xfe025000) +#define DMC_SEC_RANGE14_WID_CTRL4 ((0x00d8 << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_WID_CTRL0 ((0x00da << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_WID_CTRL1 ((0x00db << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_WID_CTRL2 ((0x00dc << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_WID_CTRL3 ((0x00dd << 2) + 0xfe025000) +#define DMC_SEC_RANGE15_WID_CTRL4 ((0x00de << 2) + 0xfe025000) +#define DMC_DES_PADDING ((0x00e0 << 2) + 0xfe025000) + //bit 31:0 | 0 | des_pading | 32bits address padding used for DES dkey generation. +#define DMC_DES_CTRL ((0x00e1 << 2) + 0xfe025000) + //bit 31 : range15_des_en policy : 1 range15_des_en = range15_local_des_en && GLOBAL_DES_EN. 0 : range15_des_en = range15_local_des_en || GLOBAL_DES_EN. + //bit 30 : range14_des_en policy : 1 range14_des_en = range14_local_des_en && GLOBAL_DES_EN. 0 : range14_des_en = range14_local_des_en || GLOBAL_DES_EN. + //bit 29 : range13_des_en policy : 1 range13_des_en = range13_local_des_en && GLOBAL_DES_EN. 0 : range13_des_en = range13_local_des_en || GLOBAL_DES_EN. + //bit 28 : range12_des_en policy : 1 range12_des_en = range12_local_des_en && GLOBAL_DES_EN. 0 : range12_des_en = range12_local_des_en || GLOBAL_DES_EN. + //bit 27 : range11_des_en policy : 1 range11_des_en = range11_local_des_en && GLOBAL_DES_EN. 0 : range11_des_en = range11_local_des_en || GLOBAL_DES_EN. + //bit 26 : range10_des_en policy : 1 range11_des_en = range10_local_des_en && GLOBAL_DES_EN. 0 : range10_des_en = range10_local_des_en || GLOBAL_DES_EN. + //bit 25 : range9_des_en policy : 1 range9_des_en = range9_local_des_en && GLOBAL_DES_EN. 0 : range9_des_en = range9_local_des_en || GLOBAL_DES_EN. + //bit 24 : range8_des_en policy : 1 range8_des_en = range8_local_des_en && GLOBAL_DES_EN. 0 : range8_des_en = range8_local_des_en || GLOBAL_DES_EN. + //bit 23 : range7_des_en policy : 1 range7_des_en = range7_local_des_en && GLOBAL_DES_EN. 0 : range7_des_en = range7_local_des_en || GLOBAL_DES_EN. + //bit 22 : range6_des_en policy : 1 range6_des_en = range6_local_des_en && GLOBAL_DES_EN. 0 : range6_des_en = range6_local_des_en || GLOBAL_DES_EN. + //bit 21 : range5_des_en policy : 1 range5_des_en = range5_local_des_en && GLOBAL_DES_EN. 0 : range5_des_en = range5_local_des_en || GLOBAL_DES_EN. + //bit 20 : range4_des_en policy : 1 range4_des_en = range4_local_des_en && GLOBAL_DES_EN. 0 : range4_des_en = range4_local_des_en || GLOBAL_DES_EN. + //bit 19 : range3_des_en policy : 1 range3_des_en = range3_local_des_en && GLOBAL_DES_EN. 0 : range3_des_en = range3_local_des_en || GLOBAL_DES_EN. + //bit 18 : range2_des_en policy : 1 range2_des_en = range2_local_des_en && GLOBAL_DES_EN. 0 : range2_des_en = range2_local_des_en || GLOBAL_DES_EN. + //bit 17 : range1_des_en policy : 1 range1_des_en = range1_local_des_en && GLOBAL_DES_EN. 0 : range1_des_en = range1_local_des_en || GLOBAL_DES_EN. + //bit 16 : range0_des_en policy : 1 range0_des_en = range0_local_des_en && GLOBAL_DES_EN. 0 : range0_des_en = range0_local_des_en || GLOBAL_DES_EN. + //bit 1 | 0 | GLOBAL_DES_EN | 1: Global DES enable. 0 : global DES disable. default is 0. + //bit 0 | 0 | DES_lock | one time lock bit. after write 1 to this bit, DMC_DES_CTRL,DMC_DES_PADDING can't be write and read. +//DES KEY register can only be reset by pad reset. But it can be changed by software after watch dog reset. +#define DMC_DES_KEY0_REG0 ((0x00e2 << 2) + 0xfe025000) +#define DMC_DES_KEY0_REG1 ((0x00e3 << 2) + 0xfe025000) +#define DMC_DES_KEY0_REG2 ((0x00e4 << 2) + 0xfe025000) +#define DMC_DES_KEY0_REG3 ((0x00e5 << 2) + 0xfe025000) +#define DMC_DES_KEY1_REG0 ((0x00e6 << 2) + 0xfe025000) +#define DMC_DES_KEY1_REG1 ((0x00e7 << 2) + 0xfe025000) +#define DMC_DES_KEY1_REG2 ((0x00e8 << 2) + 0xfe025000) +#define DMC_DES_KEY1_REG3 ((0x00e9 << 2) + 0xfe025000) +//FROM SC2, the APB bus provided Master ID through PUSER signals. +//there's total 8 master IDs could access DMC non-secure registers. +//we assign 1 control bit for each APB Master and each DMC non-secure register domains +#define DDR_APB_SEC_CTRL0 ((0x00f0 << 2) + 0xfe025000) + // APB access control for dmc REQUEST control register access control register. + // default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL1 ((0x00f1 << 2) + 0xfe025000) + // APB access control for DMC DRAM timing parameter and DFI inteface registers. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL2 ((0x00f2 << 2) + 0xfe025000) + // APB access control for DMC PLL clock frequency control regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL3 ((0x00f3 << 2) + 0xfe025000) + // APB access control for DMC sticky control regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL4 ((0x00f4 << 2) + 0xfe025000) + // APB access control for DMC test control regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL5 ((0x00f5 << 2) + 0xfe025000) + // APB access control for DMC clk reset control regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL6 ((0x00f6 << 2) + 0xfe025000) + // APB access control for DMC protection regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL7 ((0x00f7 << 2) + 0xfe025000) + // APB access control for DMC normal regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL8 ((0x00f8 << 2) + 0xfe025000) + // APB access control for DDR PHY group 0 regsiters. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL9 ((0x00f9 << 2) + 0xfe025000) + // APB access control for DDR PHY group 1 regsiters. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +//registers to check the security protection and watch point error information. +#define DMC_SEC_STATUS ((0x00fa << 2) + 0xfe025000) + //bit 31~2. not used. + //bit 6 + //bit 5 + //bit 4 + //bit 3 1 : normal security register write violation.( APB bus WDATA not equre the register value when APB write). write 1 to clean this bit to 0. + //bit 2 sec_alert. 1 DMC secruity register alert function triggered. can't clean. only reset DMC can clear this bit. + //bit 1 write security violation. + //bit 0. read security violation. +#define DMC_VIO_ADDR0 ((0x00fb << 2) + 0xfe025000) + //ddr0 write secure violation address. +#define DMC_VIO_ADDR1 ((0x00fc << 2) + 0xfe025000) + //bit 31:24 . not used. always 0. + //24 ddr0 secure check violation. + //23 not used. + //22 not used. + //21 not used. + //20. not used. + //19 ddr0 write address overflow. write out of DDR size. + //18:16. ddr0 write violation AWPROT bits. + //15:0 ddr0_write violation ID. +#define DMC_VIO_ADDR2 ((0x00fd << 2) + 0xfe025000) + //ddr0 read seure violation address +#define DMC_VIO_ADDR3 ((0x00fe << 2) + 0xfe025000) + //24 ddr0 read secure check violation. + //23 not used. + //22 not used. + //21 ddr0 read trap1 violation + //20 ddr0 read trap0 violation + //19 ddr 0 read address overflow. write out of DDR size. + //18:16. ddr 0 read violation ARPROT bits. + //15:0 ddr 0 read violation ID. +#define DMC_DDR_CTRL ((0x0100 << 2) + 0xfe025000) + //bit 24:22 3'b000 : ddr3 mode. + //3'b001 : ddr4 mode. + //3'b010 : lpddr3 mode. + //3'b011 : lpddr4 mode. + //bit 21. rank1 enable bit. if 1, rank1 used the address map is as bit 5:3 defined. + //bit 20 DDR4 BG1 enable bit. + //bit 18: ddrphy_16b, DDR PHY DDR SDRAM data bits width. 1: 16bits. 0 : 32 bits. + //bit 16. ddr_16b, 1: only use 16bits data in a 32bits DDR PHY data interface. 0 : normal data interface. + //bit 7:4 : ddr1_size. DDR rank1 size control. + //4'b0000 : DDR rank 1 is 128Mbyte. + //4'b0001 : DDR rank 1 is 256Mbyte. + //4'b0010 : DDR rank 1 is 512Mbyte. + //4'b0011 : DDR rank 1 is 1Gbyte. + //4'b0100 : DDR rank 1 is 2Gbyte. + //4'b0101 : DDR rank 1 is 4Gbyte. + //4'b1000 : DDR rank 1 is 192Mbyte. + //4'b1001 : DDR rank 1 is 374Mbyte. + //4'b1010 : DDR rank 1 is 768Mbyte. + //4'b1011 : DDR rank 1 is 1.5Gbyte. + //4'b1100 : DDR rank 1 is 3Gbyte. + //others : reserved. + //bit 3:0 : ddr0_size. DDR rank0 size control. + //4'b0000 : DDR rank 0 is 128Mbyte. + //4'b0001 : DDR rank 0 is 256Mbyte. + //4'b0010 : DDR rank 0 is 512Mbyte. + //4'b0011 : DDR rank 0 is 1Gbyte. + //4'b0100 : DDR rank 0 is 2Gbyte. + //4'b0101 : DDR rank 0 is 4Gbyte. + //4'b1000 : DDR rank 1 is 192Mbyte. + //4'b1001 : DDR rank 1 is 374Mbyte. + //4'b1010 : DDR rank 1 is 768Mbyte. + //4'b1011 : DDR rank 1 is 1.5Gbyte. + //4'b1100 : DDR rank 1 is 3Gbyte. + //others : reserved. +//DDR3/4 LPDDR3/4 SDRAM address to 32bits linear address address map: +//DDR0_ADDRMAP is used to select RANK0 bank, row, col address selection. +//DDR1_ADDRMAP is used to select RANK1 bank, row, col address selection. +#define DDR0_ADDRMAP_0 ((0x0101 << 2) + 0xfe025000) + //29:25 ca8. + //24:20 ca7. + //19:15 ca6. + //14:10 ca5. + //9:5 ca4. + //4:0 ca3. +#define DDR0_ADDRMAP_1 ((0x0102 << 2) + 0xfe025000) + //29:25 ra2. + //24:20 ra1. + //19:15 ra0. + //14:10 ca11. + //9:5 ca10. + //4:0 ca9. +#define DDR0_ADDRMAP_2 ((0x0103 << 2) + 0xfe025000) + //29:25 ra8. + //24:20 ra7. + //19:15 ra6. + //14:10 ra5. + //9:5 ra4. + //4:0 ra3. +#define DDR0_ADDRMAP_3 ((0x0104 << 2) + 0xfe025000) + //29:25 ra14. + //24:20 ra13. + //19:15 ra12. + //14:10 ra11. + //9:5 ra10. + //4:0 ra9. +#define DDR0_ADDRMAP_4 ((0x0105 << 2) + 0xfe025000) + //29:25 ra16 for DDR4 SDRAM + //24:20 bg1 for DDR4 SDRAM. + //19:15 ba2. or bg0 for DDR4. + //14:10 ba1. + //9:5 ba0. + //4:0 ra15. +#define DDR1_ADDRMAP_0 ((0x0106 << 2) + 0xfe025000) + //29:25 ca8. + //24:20 ca7. + //19:15 ca6. + //14:10 ca5. + //9:5 ca4. + //4:0 ca3. +#define DDR1_ADDRMAP_1 ((0x0107 << 2) + 0xfe025000) + //29:25 ra2. + //24:20 ra1. + //19:15 ra0. + //14:10 ca11. + //9:5 ca10. + //4:0 ca9. +#define DDR1_ADDRMAP_2 ((0x0108 << 2) + 0xfe025000) + //29:25 ra8. + //24:20 ra7. + //19:15 ra6. + //14:10 ra5. + //9:5 ra4. + //4:0 ra3. +#define DDR1_ADDRMAP_3 ((0x0109 << 2) + 0xfe025000) + //29:25 ra14. + //24:20 ra13. + //19:15 ra12. + //14:10 ra11. + //9:5 ra10. + //4:0 ra9. +#define DDR1_ADDRMAP_4 ((0x010a << 2) + 0xfe025000) + //29:25 ra16 for DDR4 SDRAM + //24:20 bg1 for DDR4 SDRAM. + //19:15 ba2 or bg0 for DDR4 SDRAM.. + //14:10 ba1. + //9:5 ba0. + //4:0 ra15. +#define DDR_MEM_PD_CTRL ((0x010b << 2) + 0xfe025000) + //bit 31:14 not used. + //2 bit control for each mem. 00 normal working. 11 power down. + //bit 13:12 wc_fifo + //bit 11:10 wd_mem + //bit 9:8 rd_mem + //bit 7:6 dfifo + //bit 5:4 cfifo + //bit 3:2 cav_ram + //bit 1:0 sticky ram +#define DMC_AXI2DDR0 ((0x0120 << 2) + 0xfe025000) + //for AXI address first 256MB AXI ADDRESS[31:28] == 4'b0000. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR1 ((0x0121 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b0001. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR2 ((0x0122 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b0010. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR3 ((0x0123 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b0011. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR4 ((0x0124 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b0100. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR5 ((0x0125 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b0101. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR6 ((0x0126 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b0110. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR7 ((0x0127 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b0111. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR8 ((0x0128 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b1000. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR9 ((0x0129 << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b1001. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRA ((0x012a << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b1010. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRB ((0x012b << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b1011. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRC ((0x012c << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b1100. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRD ((0x012d << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b1101. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRE ((0x012e << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b1110. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRF ((0x012f << 2) + 0xfe025000) + //for AXI_ADDRESS[31:28] == 4'b1111. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_DDR_CTRL1 ((0x0130 << 2) + 0xfe025000) + //bit 0. DMC_DDR_LOCK. 1: LOCK DMC_DDR_CTRL, DMC_DDR_CTRL1, DMC_AXI2DDRx, DDR0/1_ADDRMAP_x registers. those register can't modified any more. + // 0: all these regsiters can be read/write by secure APB access. +// +// Closing file: ../mmc_new/dmc/rtl/dmc_sec.vh +// +// +// Reading file: ../mmc_new/dmc/rtl/dmc_test.vh +// +// ----------------------------------------------- +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfe037800 +// ----------------------------------------------- +// ----------------------------------------------- +//`define DMC_TEST_REG_BASE 32'hfe025800 +#define DMC_TEST_STA ((0x0000 << 2) + 0xfe037800) + //test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. + // for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0. +#define DMC_TEST_EDA ((0x0001 << 2) + 0xfe037800) + //test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. + // for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1. +#define DMC_TEST_CTRL ((0x0002 << 2) + 0xfe037800) + //bit 31. enable test. + //bit 30. when enable test, enable the write to DDR function. + //bit 29. when enable test, enable the read from DDR function. + //bit 28. when enable test, enable the sha calculation function must be same as read enable but without write function. + //bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer. + //bit 26. 0: save sha result to test_sha_message registers. 1 : don't save. + //bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address. + // 1: test module would pick the random address from test start address and test end address. + //bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers. + // for write if the write command number == the DMC_TEST_NUM, the write is done. + // for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times. + // 1 : finshed at end address. + //bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}). + // 0 : the WDATA is the data in write register. + //bit 23. 1 compare the sha result with the test sha message registers. 0 : dont compare the result. + //bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times. + //bit 19. limit write. 0: no outstanding write request limitation. + // 1: limit the outstanding write commands to the number of bits [15:8] + //bit 18. limit read. 0. no outstanding read request limitation. + // 1. limit the read outstanding request to the number of bits[7:0]. + //bit 17:16. sha mode for sha function enabled. 00 : not used. 01 : sha1. 2: sha2-256. 3: sha2_224. not used in GXL fixed to be Sha 2. + //bit 15:8. write outstanding commands limit. + //bit 7:0. read outstanding commands limit. +#define DMC_TEST_NUM ((0x0003 << 2) + 0xfe037800) + // how many test command for the test if the DMC_TEST_CTRL bit 24 is 0. +#define DMC_TEST_WDG ((0x0004 << 2) + 0xfe037800) + //31:16. write response watch dog. + //15:0. read response watch dog. +#define DMC_TEST_COMP_MASK ((0x0005 << 2) + 0xfe037800) + //32bits for DMC TEST COMPARE bit enable. + //1 : to MASK this bit. 0: compare this bit. +#define DMC_TEST_WSTRB0 ((0x0006 << 2) + 0xfe037800) + //MPC WR FIFO command DM bit write data + //bit 31:16 the second cycle. + //bit 15:0 the first cycle. +#define DMC_TEST_WSTRB1 ((0x0007 << 2) + 0xfe037800) + //MPC WR FIFO command DM bit write data + //bit 31:16. the Forth cycle. + //bit 15:0. the third cycle. +#define DMC_TEST_WD0 ((0x0010 << 2) + 0xfe037800) + // write data 0 for write command. also for read back data comparision. +#define DMC_TEST_WD1 ((0x0011 << 2) + 0xfe037800) + // write data 1 for write command. also for read back data comparision. +#define DMC_TEST_WD2 ((0x0012 << 2) + 0xfe037800) + // write data 2 for write command. also for read back data comparision. +#define DMC_TEST_WD3 ((0x0013 << 2) + 0xfe037800) + // write data 3 for write command. also for read back data comparision. +#define DMC_TEST_WD4 ((0x0014 << 2) + 0xfe037800) + // write data 4 for write command. also for read back data comparision. +#define DMC_TEST_WD5 ((0x0015 << 2) + 0xfe037800) + // write data 5 for write command. also for read back data comparision. +#define DMC_TEST_WD6 ((0x0016 << 2) + 0xfe037800) + // write data 6 for write command. also for read back data comparision. +#define DMC_TEST_WD7 ((0x0017 << 2) + 0xfe037800) + // write data 7 for write command. also for read back data comparision. +#define DMC_TEST_WD8 ((0x0018 << 2) + 0xfe037800) + // write data 8 for write command. also for read back data comparision. +#define DMC_TEST_WD9 ((0x0019 << 2) + 0xfe037800) + // write data 9 for write command. also for read back data comparision. +#define DMC_TEST_WD10 ((0x001a << 2) + 0xfe037800) + // write data 10 for write command. also for read back data comparision. +#define DMC_TEST_WD11 ((0x001b << 2) + 0xfe037800) + // write data 11 for write command. also for read back data comparision. +#define DMC_TEST_WD12 ((0x001c << 2) + 0xfe037800) + // write data 12 for write command. also for read back data comparision. +#define DMC_TEST_WD13 ((0x001d << 2) + 0xfe037800) + // write data 13 for write command. also for read back data comparision. +#define DMC_TEST_WD14 ((0x001e << 2) + 0xfe037800) + // write data 14 for write command. also for read back data comparision. +#define DMC_TEST_WD15 ((0x001f << 2) + 0xfe037800) + // write data 15 for write command. also for read back data comparision. +#define DMC_TEST_RD0 ((0x0020 << 2) + 0xfe037800) + // the read back data 0. if error happens, it would capture the first error data. +#define DMC_TEST_RD1 ((0x0021 << 2) + 0xfe037800) + // the read back data 1. if error happens, it would capture the first error data. +#define DMC_TEST_RD2 ((0x0022 << 2) + 0xfe037800) + // the read back data 2. if error happens, it would capture the first error data. +#define DMC_TEST_RD3 ((0x0023 << 2) + 0xfe037800) + // the read back data 3. if error happens, it would capture the first error data. +#define DMC_TEST_RD4 ((0x0024 << 2) + 0xfe037800) + // the read back data 4. if error happens, it would capture the first error data. +#define DMC_TEST_RD5 ((0x0025 << 2) + 0xfe037800) + // the read back data 5. if error happens, it would capture the first error data. +#define DMC_TEST_RD6 ((0x0026 << 2) + 0xfe037800) + // the read back data 6. if error happens, it would capture the first error data. +#define DMC_TEST_RD7 ((0x0027 << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD8 ((0x0028 << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD9 ((0x0029 << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD10 ((0x002a << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD11 ((0x002b << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD12 ((0x002c << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD13 ((0x002d << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD14 ((0x002e << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD15 ((0x002f << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_ERR_ADDR ((0x0040 << 2) + 0xfe037800) + //read only. it capature the first error address. +#define DMC_TEST_ERR_CNT ((0x0041 << 2) + 0xfe037800) + //read only. how many data error happens in the whole test period. +#define DMC_TEST_STS ((0x0042 << 2) + 0xfe037800) + //read only. + //bit 31, test done bit. write 1 to clean. + //bit 30, indicate address err + //bit 29~7. not used. + //bit 6. read data resp error(caused by security or rd latency). + //bit 5. test MRR/MPR rd latency error. write 1 clear + //bit 4, sha done. write 1 to clean. + //bit 3, write done. write 1 to clean. + //bit 2, read done. write 1 to clean + //bit 1, write watchdog triggered. write 1 to clean + //bit 0, read watchdog triggered. write 1 to clean. +#define DMC_TEST_WRCMD_ADDR ((0x0043 << 2) + 0xfe037800) + //read only. the current write cmd address. +#define DMC_TEST_RDCMD_ADDR ((0x0044 << 2) + 0xfe037800) + //read only. the current read command address. +#define DMC_TEST_RDRSP_ADDR ((0x0045 << 2) + 0xfe037800) + //read only. the failed read response address(for error data ) +//`endif +// +// Closing file: ../mmc_new/dmc/rtl/dmc_test.vh +// +// +// Reading file: ../mmc_new/dmc/rtl/dmc_reg.vh +// +//`ifdef DMC_REG_DEFINE +//`else +//`define DMC_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfe024000 +// ----------------------------------------------- +//`define DMC_REG_BASE 32'hfe024000 +#define DMC_SOFT_RST ((0x0001 << 2) + 0xfe024000) + //bit 31~24. reserved for future. + //bit 23:16 8 AMBUS input interface n_clk domain reset_n signal. 0 : reset. 1: normal working mode. + //bit 15:0. 16 AXI BUS input intefaces n_clk domain reset_n signal. 0: reset. 1: normal working mode. each bit for one interface. +#define DMC_SOFT_RST1 ((0x0002 << 2) + 0xfe024000) + //To reset the Async interface, you need to disable the interface both clock domain, then reset both n_clk and m_clk domain + //bit 31~24 not used. + //bit 23.16 8 am bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode. + //bit 15:0. 16 AXI bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode. +#define DMC_SOFT_RST2 ((0x0003 << 2) + 0xfe024000) + //bit 31~11. reserved for future. + //bit 10 DMC DFI cmd soft reset_n + //bit 9 DMC DFI MISC soft reset_n + //bit 8 DMC DFI data soft reset_n + //bit 7 DMC DFI dcu soft reset_n + //bit 6 DMC siu soft reset_n + //bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode. + //bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode. + //bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode. + //bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode. + //bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode. + //bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1: +#define DMC_RST_STS1 ((0x0004 << 2) + 0xfe024000) + //31~24. not used. + //23~0. Read only. the DMC_SOFT_RST1 signal in n_clk domain. the purpose of this register is when one of the 2 clocks is too slow or too fast, we can read this register to make sure another clock domain reset is done. +#define DMC_CLKG_CTRL0 ((0x0006 << 2) + 0xfe024000) + //bit 23:16. enable the 8 ambus interfaces both main and n_clk auto clock gating function. each 1 bit for one interface. + //bit 15:0. enable the 16 axi interfaces both main and n_clk auto clock gating function. each 1 bit for one interface. +#define DMC_CLKG_CTRL1 ((0x0007 << 2) + 0xfe024000) + //bit 23:16. force to disable the 8 ambus interfaces both main and n_clk. each 1 bit for one interface. + //bit 15:0. force to disable the 16 axi interfaces both main and n_clk. each 1 bit for one interface. +#define DMC_CLKG_CTRL2 ((0x0008 << 2) + 0xfe024000) + //bit 12 enalbe auto clock gating for awcmdfifo. + //bit 11 enalbe auto clock gating for arcmdfifo. + //bit 10 enable auto clock gating for dfi command generation + //bit 9 enable auto clock gating for dram cntroller + //bit 8 enable auto clock gating for dfi data path. + //bit 7. enalbe auto clock gating for write rsp generation. + //bit 6. enalbe auto clock gating for read rsp generation. + //bit 5. enalbe auto clock gating for ddr0 command filter. + //bit 4. enalbe auto clock gating for ddr0 write reorder buffer. + //bit 3. enalbe auto clock gating for ddr0 write data buffer. + //bit 2. enalbe auto clock gating for ddr0 read reorder buffer. + //bit 1. enalbe auto clock gating for read canvas. + //bit 0. enalbe auto clock gating for write canvas. +#define DMC_CLKG_CTRL3 ((0x0009 << 2) + 0xfe024000) + //bit 12 force to disable the clock of awcmdfifo. + //bit 11 force to disable the clock of arcmdfifo. + //bit 10 force to disable the clock of dfi command generation + //bit 9 force to disable the clock of dram cntroller + //bit 8 force to disable the clock of dfi data path. + //bit 7. force to disalbe the clock of write rsp generation. + //bit 6. force to disalbe the clock of read rsp generation. + //bit 5. force to disalbe the clock of command filter. + //bit 4. force to disalbe the clock of write reorder buffer. + //bit 3. force to disalbe the clock of write data buffer. + //bit 2. force to disalbe the clock of read reorder buffer. + //bit 1. force to disalbe the clock of read canvas. + //bit 0. force to disalbe the clock of write canvas. +#define DMC_VERSION ((0x0010 << 2) + 0xfe024000) + //read only 32'h000a0006. for TM2_REVB +#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfe024000) + //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. + //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. + //bit 3. qos monitor 3 enable. + //bit 2. qos monitor 2 enable. + //bit 1. qos monitor 1 enable. + //bit 0. qos monitor 0 enable. +#define DMC_MON_CTRL1 ((0x0021 << 2) + 0xfe024000) + //enable to check which modules bandwidth in QOS monitor 0 + //32bits for 32 different ID protection. + //bit 24. prot_en for all undefined IDs. + //bit 23. prot_en for SDEMMC_C + //bit 22. prot_en for DMA + //bit 21. prot_en for AUDIO + //bit 20. prot_en for SDEMMC_B + //bit 19. prot_en for SDEMMC_A + //bit 18. prot_en for SPICC_B + //bit 17. prot_en for SPICC_A + //bit 16. prot_en for ETH + //bit 15. prot_en for DMC TEST + //bit 14. prot_en for VAD + //bit 13. prot_en for NNA + //bit 12. prot_en for ISP + //bit 11. prot_en for USB Host + //bit 10. prot_en for USB Devi + //bit 9. prot_en for GE2D SRC1 + //bit 8. prot_en for GE2D SRC0/DEST + //bit 7. prot_en for GDC + //bit 6. prot_en for WAVE + //bit 5. prot_en for JPEG + //bit 4. prot_en for DSPA + //bit 3. prot_en for RICV + //bit 2. prot_en for JTAG/PROD + //bit 1. prot_en for REE + //bit 0. prot_en for TEE +#define DMC_MON_CTRL2 ((0x0022 << 2) + 0xfe024000) + //not used in C2 +#define DMC_MON_CTRL3 ((0x0023 << 2) + 0xfe024000) + //enable to check which modules bandwidth in QOS monitor 1 + //32bits for 32 different ID protection. + //bit 24. prot_en for all undefined IDs. + //bit 23. prot_en for SDEMMC_C + //bit 22. prot_en for DMA + //bit 21. prot_en for AUDIO + //bit 20. prot_en for SDEMMC_B + //bit 19. prot_en for SDEMMC_A + //bit 18. prot_en for SPICC_B + //bit 17. prot_en for SPICC_A + //bit 16. prot_en for ETH + //bit 15. prot_en for DMC TEST + //bit 14. prot_en for VAD + //bit 13. prot_en for NNA + //bit 12. prot_en for ISP + //bit 11. prot_en for USB Host + //bit 10. prot_en for USB Devi + //bit 9. prot_en for GE2D SRC1 + //bit 8. prot_en for GE2D SRC0/DEST + //bit 7. prot_en for GDC + //bit 6. prot_en for WAVE + //bit 5. prot_en for JPEG + //bit 4. prot_en for DSPA + //bit 3. prot_en for RICV + //bit 2. prot_en for JTAG/PROD + //bit 1. prot_en for REE + //bit 0. prot_en for TEE +#define DMC_MON_CTRL4 ((0x0024 << 2) + 0xfe024000) + //not used in C2 +#define DMC_MON_CTRL5 ((0x0025 << 2) + 0xfe024000) + //enable to check which modules bandwidth in QOS monitor 2 + //32bits for 32 different ID protection. + //bit 24. prot_en for all undefined IDs. + //bit 23. prot_en for SDEMMC_C + //bit 22. prot_en for DMA + //bit 21. prot_en for AUDIO + //bit 20. prot_en for SDEMMC_B + //bit 19. prot_en for SDEMMC_A + //bit 18. prot_en for SPICC_B + //bit 17. prot_en for SPICC_A + //bit 16. prot_en for ETH + //bit 15. prot_en for DMC TEST + //bit 14. prot_en for VAD + //bit 13. prot_en for NNA + //bit 12. prot_en for ISP + //bit 11. prot_en for USB Host + //bit 10. prot_en for USB Devi + //bit 9. prot_en for GE2D SRC1 + //bit 8. prot_en for GE2D SRC0/DEST + //bit 7. prot_en for GDC + //bit 6. prot_en for WAVE + //bit 5. prot_en for JPEG + //bit 4. prot_en for DSPA + //bit 3. prot_en for RICV + //bit 2. prot_en for JTAG/PROD + //bit 1. prot_en for REE + //bit 0. prot_en for TEE +#define DMC_MON_CTRL6 ((0x0026 << 2) + 0xfe024000) + //not USED in C2 +#define DMC_MON_CTRL7 ((0x0027 << 2) + 0xfe024000) + //enable to check which modules bandwidth in QOS monitor 3 + //32bits for 32 different ID protection. + //bit 24. prot_en for all undefined IDs. + //bit 23. prot_en for SDEMMC_C + //bit 22. prot_en for DMA + //bit 21. prot_en for AUDIO + //bit 20. prot_en for SDEMMC_B + //bit 19. prot_en for SDEMMC_A + //bit 18. prot_en for SPICC_B + //bit 17. prot_en for SPICC_A + //bit 16. prot_en for ETH + //bit 15. prot_en for DMC TEST + //bit 14. prot_en for VAD + //bit 13. prot_en for NNA + //bit 12. prot_en for ISP + //bit 11. prot_en for USB Host + //bit 10. prot_en for USB Devi + //bit 9. prot_en for GE2D SRC1 + //bit 8. prot_en for GE2D SRC0/DEST + //bit 7. prot_en for GDC + //bit 6. prot_en for WAVE + //bit 5. prot_en for JPEG + //bit 4. prot_en for DSPA + //bit 3. prot_en for RICV + //bit 2. prot_en for JTAG/PROD + //bit 1. prot_en for REE + //bit 0. prot_en for TEE +#define DMC_MON_CTRL8 ((0x0028 << 2) + 0xfe024000) + //not used. +#define DMC_MON_ALL_REQ_CNT ((0x0029 << 2) + 0xfe024000) + // at the test period, the whole MMC request time. +#define DMC_MON_ALL_GRANT_CNT ((0x002a << 2) + 0xfe024000) + // at the test period, the whole MMC granted data cycles. 64bits unit. +#define DMC_MON_ONE_GRANT_CNT ((0x002b << 2) + 0xfe024000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_SEC_GRANT_CNT ((0x002c << 2) + 0xfe024000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_THD_GRANT_CNT ((0x002d << 2) + 0xfe024000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_FOR_GRANT_CNT ((0x002e << 2) + 0xfe024000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_TIMER ((0x002f << 2) + 0xfe024000) + // timer for the monitor period. +#define DMC_IRQ_STS ((0x0030 << 2) + 0xfe024000) + //bit 31:3 Not used. + //bit 2 : QOS Monitor interrupt flag. 1: means there's QOS monitor interrup. write 1 to clean this interrupt. + //bit 1 : WRITE protection interrupt. 1: means there's write protection violation. need to write DMC_PROT_IRQ_CTRL bit 1to clean this bit. + //bit 0 : read protection interrupt. 1: means there's read protection violation. need to write DMC_PROT_IRQ_CTRL bit 0 to clean this bit. +#define DMC_AXI0_HOLD_CTRL ((0x0031 << 2) + 0xfe024000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI5_HOLD_CTRL ((0x0035 << 2) + 0xfe024000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_CHAN_STS ((0x003c << 2) + 0xfe024000) + //bit 4 always 1 + //bit 3 ddr0 write data buffer idle. 1 : idle 0: busy. + //bit 2 always 1. + //bit 1 ddr0 wbuf idle. 1 : idle 0: busy. + //bit 0. axi0 channel idle. 1 : idle 0: busy. +#define DMC_CMD_FILTER_CTRL1 ((0x0040 << 2) + 0xfe024000) + //not used. +#define DMC_CMD_FILTER_CTRL2 ((0x0041 << 2) + 0xfe024000) + //31:24. keep the bank active if there's urgent level 3 read bank hit request. + //23:16. keep the bank active if there's urgent level 2 read bank hit request. + //15:8. keep the bank active if there's urgent level 1 read bank hit request. + //7:0. keep the bank active if there's urgent level 0 read bank hit request. +#define DMC_CMD_FILTER_CTRL3 ((0x0042 << 2) + 0xfe024000) + //bit 31. force wbuf empty. + //bit 30:26 wbuf high level number + //bit 25:21 wbuf mid level number + //bit 20:16 wbuf low level number + //bit 14:10 rbuf high level number + //bit 9:5 rbuf middle level number + //bit 4:0 rbuf low level number +#define DMC_CMD_FILTER_CTRL4 ((0x0043 << 2) + 0xfe024000) + //bit 29:25. tITW.long + //bit 24:20. tITW. short + //bit 19:12 tAP auto precharge the bank not used if idle that long time. + //bit 11:6 write to read accesses if there write hit request. + //bit 5:0 read to write accesses if there write hit request. +#define DMC_CMD_FILTER_CTRL5 ((0x0044 << 2) + 0xfe024000) + //bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer. + //bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long. + //bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request. + //bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request. +#define DMC_CMD_FILTER_CTRL6 ((0x0045 << 2) + 0xfe024000) + //bit 31:24 write urgent 3 request pending hold num. + //bit 23:16 write urgent 2 request pending hold num. + //bit 15:8. write urgent 1 request pending hold num. + //bit 7:0. write urgent 0 request pending hold num. +#define DMC_CMD_FILTER_CTRL7 ((0x0046 << 2) + 0xfe024000) + //bit 31:24. aw_req_pedning singal assertion after wbuf full. + //bit 23:16 aw_req_pending singal hold how long if wbuf not full. + //bit 15:8 write to read waiting cycles if there write hit request. + //bit 7:0 read to write waiting cycles if there write hit request. +#define DMC_CMD_FILTER_CTRL8 ((0x0047 << 2) + 0xfe024000) + //bit 31:8 reserved. + //bit 7:0 rank limit to change to another rank. +#define DMC_CMD_BUFFER_CTRL ((0x0048 << 2) + 0xfe024000) + //bit 31:26 total write buffer number. default 32. + //bit 25:20 total read buffer number. default 32. + //bit 19:14 reserved. + //bit 13:8 wr cmd fifo depth + //bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long. +#define DMC_CMD_BUFFER_CTRL1 ((0x0049 << 2) + 0xfe024000) + //bit 29:24 read buffer number in non-urgent request. + //bit 23:16 read buffer bank miss watch dog threshold. + //bit 15:12 read buffer urgent level 3 counter inc weight. + //bit 11:8 read buffer urgent level 2 counter inc weight. + //bit 7:4 read buffer urgent level 1 counter inc weight. + //bit 3:0 read buffer urgent level 0 counter inc weight. +#define DMC_AXI0_CHAN_CTRL ((0x0080 << 2) + 0xfe024000) + //bit 31 AXI interface request enable. + //bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable. + //bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock. + //bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode. + //bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode. + //bit 15:12 ugt3 QOS level. + //bit 11:8 ugt2 QOS level. + //bit 7:4 ugt1 QOS level. + //bit 3:0 not used. +#define DMC_PROT0_RANGE ((0x0090 << 2) + 0xfe024000) + //protection 0 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address. + //bit 31:16 : range end address. + //bit 15:0 : range start address +#define DMC_PROT0_CTRL ((0x0091 << 2) + 0xfe024000) + //32bits for 32 different ID protection. + //bit 24. prot_en for all undefined IDs. + //bit 23. prot_en for SDEMMC_C + //bit 22. prot_en for DMA + //bit 21. prot_en for AUDIO + //bit 20. prot_en for SDEMMC_B + //bit 19. prot_en for SDEMMC_A + //bit 18. prot_en for SPICC_B + //bit 17. prot_en for SPICC_A + //bit 16. prot_en for ETH + //bit 15. prot_en for DMC TEST + //bit 14. prot_en for VAD + //bit 13. prot_en for NNA + //bit 12. prot_en for ISP + //bit 11. prot_en for USB Host + //bit 10. prot_en for USB Devi + //bit 9. prot_en for GE2D SRC1 + //bit 8. prot_en for GE2D SRC0/DEST + //bit 7. prot_en for GDC + //bit 6. prot_en for WAVE + //bit 5. prot_en for JPEG + //bit 4. prot_en for DSPA + //bit 3. prot_en for RICV + //bit 2. prot_en for JTAG/PROD + //bit 1. prot_en for REE + //bit 0. prot_en for TEE +#define DMC_PROT0_CTRL1 ((0x0092 << 2) + 0xfe024000) + //bit 26. protection 0 read access protection enable. + //bit 25. protection 0 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR. + //bit 24. protection range 0 write access protection enable. +#define DMC_PROT1_RANGE ((0x0093 << 2) + 0xfe024000) + //protection 1 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address. + //bit 31:16 : range end address. + //bit 15:0 : range start address +#define DMC_PROT1_CTRL ((0x0094 << 2) + 0xfe024000) + //32bits for 32 different ID protection. + //bit 24. prot_en for all undefined IDs. + //bit 23. prot_en for SDEMMC_C + //bit 22. prot_en for DMA + //bit 21. prot_en for AUDIO + //bit 20. prot_en for SDEMMC_B + //bit 19. prot_en for SDEMMC_A + //bit 18. prot_en for SPICC_B + //bit 17. prot_en for SPICC_A + //bit 16. prot_en for ETH + //bit 15. prot_en for DMC TEST + //bit 14. prot_en for VAD + //bit 13. prot_en for NNA + //bit 12. prot_en for ISP + //bit 11. prot_en for USB Host + //bit 10. prot_en for USB Devi + //bit 9. prot_en for GE2D SRC1 + //bit 8. prot_en for GE2D SRC0/DEST + //bit 7. prot_en for GDC + //bit 6. prot_en for WAVE + //bit 5. prot_en for JPEG + //bit 4. prot_en for DSPA + //bit 3. prot_en for RICV + //bit 2. prot_en for JTAG/PROD + //bit 1. prot_en for REE + //bit 0. prot_en for TEE +#define DMC_PROT1_CTRL1 ((0x0095 << 2) + 0xfe024000) + //bit 26. protection range 1 read access protection enable bit. + //bit 25. protection 1 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR. + //bit 24. protection range 1 write access protection enable bit. +#define DMC_PROT_VIO_0 ((0x0096 << 2) + 0xfe024000) + //ddr0 write proection violation address. +#define DMC_PROT_VIO_1 ((0x0097 << 2) + 0xfe024000) + //31 ddr0 protection 1 vilation. + //30 ddr0 protection 0 vilation. + //29 not used. + //28:26. ddr0 write violation AWPROT bits. + //25:16. ddr0_write AWUSER[9:0]; + //15:0 ddr0_write violation ID. +#define DMC_PROT_VIO_2 ((0x0098 << 2) + 0xfe024000) + //ddr0 read prot violation address +#define DMC_PROT_VIO_3 ((0x0099 << 2) + 0xfe024000) + //bit 31:21 . not used. always 0. + //20 ddr0 read protection 1 violation. + //19 ddr0 read protection 0 violation. + //18:16. ddr0 read violation ARPROT bits. + //15:0 ddr0 read violation ID. +#define DMC_PROT_IRQ_CTRL ((0x009a << 2) + 0xfe024000) + //bit 2 : protect function IRQ enable. + //bit 1 : write protection violation. write 1 to clean write protection vio registers. + //bit 0 : read protection violation. write 1 to clean read protection vio registers. +//`endif +// +// Closing file: ../mmc_new/dmc/rtl/dmc_reg.vh +// +// +// Reading file: ../mmc_new/dmc/rtl/dmc_siu_reg.vh +// +//`ifdef DMC_SIU_REG_DEFINE +//`else +//`define DMC_SIU_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfe024400 +// ----------------------------------------------- +//`define DMC_DRAM_REG_BASE 32'hfe024400 +//there's 2 set of timing DDR timing parameter for 2 set of DDR freqency parameter. +//when change frequency, the hardware would automatically select one of these two set of timing parameter +//DMC_DRAM_* is for Frequency set 0. +//DMC_NFQ_* is for Freqency set 1. +#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xfe024400) + //bit 4:0. tMRD. //MR command cycles, in DDR3/4. in LPDDR4, it should be value of tMRW +#define DMC_DRAM_TRFC ((0x0001 << 2) + 0xfe024400) + //bit 9:0 tRFC +#define DMC_DRAM_TRP ((0x0002 << 2) + 0xfe024400) + //bit 21:16. tRP for precharge all banks. + //bit 5:0. tRP for precharge one bank. +#define DMC_DRAM_TRTW ((0x0003 << 2) + 0xfe024400) + //bit 5:0 tRTW + //In LPDDR4 . the total read command -> write command = RL +DQSCK_MAX + BL/2 - tODT_on + tWPRE +RD(tRPST) + tODT_on. + // tRTW = TDQSCK_MAX + tWPRE + tRD(tRPST) tODT_on + (delay margin) + //In DDR4 mode. +#define DMC_DRAM_TCL ((0x0004 << 2) + 0xfe024400) + //bit 5:0 tCL/tRL. read latency. +#define DMC_DRAM_TCWL ((0x0005 << 2) + 0xfe024400) + //bit 5:0. CWL: write latency. +#define DMC_DRAM_TRAS ((0x0006 << 2) + 0xfe024400) + //bit 7:0. tRAS. minimum active to precharge time for same bank. +#define DMC_DRAM_TRC ((0x0007 << 2) + 0xfe024400) + //bit 7:0. tRC. minimum active to active time for same bank. +#define DMC_DRAM_TRCD ((0x0008 << 2) + 0xfe024400) + //bit 7:0 tRCD active to read/write timing for same bank. +#define DMC_DRAM_TRRD ((0x0009 << 2) + 0xfe024400) + //bit 21:16. tRRD_l active bank A to active B in same band group for DDR4. + //bit 5:0. tRRD/tRRD_s active bank A to active bank b time. + //tRRD_s: active bank A to active bank b in different bank grousp for DDR4. +#define DMC_DRAM_TFAW ((0x000a << 2) + 0xfe024400) + //bit 8:0 tFAW. four active command windows +#define DMC_DRAM_TRTP ((0x000b << 2) + 0xfe024400) + //bit 5:0 tRTP. +#define DMC_DRAM_TWR ((0x000c << 2) + 0xfe024400) + //bit 5:0 tWR. +#define DMC_DRAM_TWTR ((0x000d << 2) + 0xfe024400) + //bit 5:0 tWTR. +#define DMC_DRAM_TCCD ((0x000e << 2) + 0xfe024400) + //bit 19:16. tCCD/tCCD_l. + //bit 3:0 tCCD/tCCD_s read to read command time or write to write command time. +#define DMC_DRAM_TEXSR ((0x000f << 2) + 0xfe024400) + //bit 12:0. tEXSR. EXIT SELF-REFRESH to read/write command. +#define DMC_DRAM_TXS ((0x0010 << 2) + 0xfe024400) + //bit 9:0 tXS. EXIT SELF_REFRESH to other command time +#define DMC_DRAM_TXP ((0x0011 << 2) + 0xfe024400) + //bit 3:0. tXP. EXIT power down to other command time +#define DMC_DRAM_TXPDLL ((0x0012 << 2) + 0xfe024400) + //bit 12:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL). +#define DMC_DRAM_TZQCS ((0x0013 << 2) + 0xfe024400) + //bit 11:0. ZQCS command to other command time. +#define DMC_DRAM_TCKSRE ((0x0014 << 2) + 0xfe024400) + //bit 4:0. enter self refresh to disable clock time. +#define DMC_DRAM_TCKSRX ((0x0015 << 2) + 0xfe024400) + //bit 4:0. enable clock to exit self refresh time. +#define DMC_DRAM_TCKE ((0x0016 << 2) + 0xfe024400) + //bit 4:0. CKE high or low minimum time. +#define DMC_DRAM_TMOD ((0x0017 << 2) + 0xfe024400) + //bit 4:0 tMOD. MRR/MRW to other command time. in LPDDR4, still use this register but it called tMRD. +#define DMC_DRAM_TDQS ((0x0018 << 2) + 0xfe024400) + //bit 31:28 reserved + //bit 27:24 tDQS. the delay for write after read in different rank. + //bit 23:20 reserved + //bit 19:16 tDQS. the delay for read after write in different rank. + //bit 15:12 reserved + //bit 11:8 tDQS. the delay for write after write in different rank. + //bit 7:4 reserved + //bit 3:0 tDQS. the delay for read after read in different rank. +#define DMC_DRAM_TRSTL ((0x0019 << 2) + 0xfe024400) + //not used. +#define DMC_DRAM_TZQLAT ((0x001a << 2) + 0xfe024400) + //bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode. +#define DMC_DRAM_TMRR ((0x001b << 2) + 0xfe024400) + //bit 7:0 tMRR not used in DMC. +#define DMC_DRAM_TCKESR ((0x001c << 2) + 0xfe024400) + //bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode. +#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfe024400) + //not support. +#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfe024400) + //bit 3:0. DFI_t_ctrldealy +#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfe024400) + //bit 5:0. dfi_t_phy_wrdata. +#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfe024400) + //bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2. +#define DMC_DRAM_DFITRDDATAEN ((0x0021 << 2) + 0xfe024400) + //bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1. +#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfe024400) + //bit 5:0. dfi_t_rdlat. +#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfe024400) + //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ. +#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfe024400) + //bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response. +#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfe024400) + //not used. +#define DMC_DRAM_DFITCTRLUPDI ((0x0027 << 2) + 0xfe024400) + //not used. +#define DMC_DRAM_DFITDRAMCLK ((0x0028 << 2) + 0xfe024400) +//bit 17 dram clk1 enable. +//bit 16 dram clk0 enable. +//bit 15:8 DRAM CLK disable waiting time +//bit 7:0 DRAM CLK enable enable timer +#define DMC_DRAM_DFITLPRESP ((0x002a << 2) + 0xfe024400) + //bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req. +#define DMC_DRAM_TCKECK ((0x002c << 2) + 0xfe024400) + //bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay +#define DMC_DRAM_TREFI ((0x002d << 2) + 0xfe024400) + //write this register will update the auto refresh related register to the auto refresh control logic. + //bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period. + //bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period. + //bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns. + //bit 7:0. t100ns period. unit is dmc clock cycles +#define DMC_DRAM_TSR ((0x002e << 2) + 0xfe024400) + //bit 5:0 tSR. self resfresh enter to exit time. +#define DMC_DRAM_TCCDMW ((0x002f << 2) + 0xfe024400) + //bit 5:0. 4*tCCD in LPDDR4 mask write. +#define DMC_DRAM_TESCKE ((0x0030 << 2) + 0xfe024400) + //bit 5:0 tESCKE. enter self refresh to power time for LPDDR4. +#define DMC_DRAM_TREFI_DDR3 ((0x0031 << 2) + 0xfe024400) + //7:0. DDR3 SDRAM tREFI single auto refresh time . the unit is t100ns. + //use this to check in 8*tREFI time, the DMC should not sent more than 16 auto REFRESH command. +#define DMC_DRAM_TZQCAL ((0x0032 << 2) + 0xfe024400) + //11:0. ZQCAL for LPDDR4. ZQINIT/ZQoper for DDR3/4 ZQCL command. +#define DMC_DRAM_T10US ((0x0033 << 2) + 0xfe024400) + //10us clock cycle number used for LP2 mode. +#define DMC_DRAM_TMRRI ((0x0034 << 2) + 0xfe024400) +//bit 7:0 tMRRI for MRR +#define DMC_DRAM_TXS_FAST ((0x0035 << 2) + 0xfe024400) + //bit 9:0 DDR4 mode XS_FAST exit self_refrest to zqcl/zqcs/mrs command. +#define DMC_DRAM_DFIODTCFG ((0x0036 << 2) + 0xfe024400) + //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. + //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. + //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0. + //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1. + //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0. + //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity. + //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0. + //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. + //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. + //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. +#define DMC_DRAM_DFIODTCFG1 ((0x0037 << 2) + 0xfe024400) + //bit 27:24 ODT length for BL8 read transfer. + //bit 19:16. ODT length for BL8 write transfer. + //bit 12:8. ODT latency for reads. suppose to be 0. + //bit 4:0. ODT latency for writes. suppose to be 0. +#define DMC_DRAM_TWODTON ((0x0038 << 2) + 0xfe024400) + //bit 5:0 DRAM write access ODT on time. + // in DDR3/4 should be same as WL. + // in LPDDR4 = tODTLon + tODTon.min +#define DMC_DRAM_TRETRAIN ((0x0039 << 2) + 0xfe024400) + //bit 15:0 LPDDR4 OSCRING retraining timer(units = auto_refresh timer). sync with autorefresh +#define DMC_DRAM_PHYADDRON ((0x003a << 2) + 0xfe024400) + //PHY_CTRL_ADDR_ON for new PHY. default : 12 +#define DMC_DRAM_PHYWRON ((0x003b << 2) + 0xfe024400) + // PHY_CTRL_WR_ON. = 10 + WL/2 + (tDQSS+ tDQS2DQ + tWPST)/dfi_clk + BL/4 +#define DMC_DRAM_PHYRDON ((0x003c << 2) + 0xfe024400) + // PHY_CTRL_RD_ON. = 10 + RL/2 + (tDQSCK+ tRPST + tDQSQ)/dfi_clk + BL/4 +#define DMC_DRAM_DFITRDDATACSEN ((0x003d << 2) + 0xfe024400) +#define DMC_DRAM_DFITPHYWRCSLAT ((0x003e << 2) + 0xfe024400) +//timing paramter for frequency set 1. +#define DMC_NFQ_TMRD ((0x0040 << 2) + 0xfe024400) +#define DMC_NFQ_TRFC ((0x0041 << 2) + 0xfe024400) +#define DMC_NFQ_TRP ((0x0042 << 2) + 0xfe024400) +#define DMC_NFQ_TRTW ((0x0043 << 2) + 0xfe024400) +#define DMC_NFQ_TCL ((0x0044 << 2) + 0xfe024400) +#define DMC_NFQ_TCWL ((0x0045 << 2) + 0xfe024400) +#define DMC_NFQ_TRAS ((0x0046 << 2) + 0xfe024400) +#define DMC_NFQ_TRC ((0x0047 << 2) + 0xfe024400) +#define DMC_NFQ_TRCD ((0x0048 << 2) + 0xfe024400) +#define DMC_NFQ_TRRD ((0x0049 << 2) + 0xfe024400) +#define DMC_NFQ_TFAW ((0x004a << 2) + 0xfe024400) +#define DMC_NFQ_TRTP ((0x004b << 2) + 0xfe024400) +#define DMC_NFQ_TWR ((0x004c << 2) + 0xfe024400) +#define DMC_NFQ_TWTR ((0x004d << 2) + 0xfe024400) +#define DMC_NFQ_TCCD ((0x004e << 2) + 0xfe024400) +#define DMC_NFQ_TEXSR ((0x004f << 2) + 0xfe024400) +#define DMC_NFQ_TXS ((0x0050 << 2) + 0xfe024400) +#define DMC_NFQ_TXP ((0x0051 << 2) + 0xfe024400) +#define DMC_NFQ_TXPDLL ((0x0052 << 2) + 0xfe024400) +#define DMC_NFQ_TZQCS ((0x0053 << 2) + 0xfe024400) +#define DMC_NFQ_TCKSRE ((0x0054 << 2) + 0xfe024400) +#define DMC_NFQ_TCKSRX ((0x0055 << 2) + 0xfe024400) +#define DMC_NFQ_TCKE ((0x0056 << 2) + 0xfe024400) +#define DMC_NFQ_TMOD ((0x0057 << 2) + 0xfe024400) +#define DMC_NFQ_TDQS ((0x0058 << 2) + 0xfe024400) +#define DMC_NFQ_TRSTL ((0x0059 << 2) + 0xfe024400) +#define DMC_NFQ_TZQLAT ((0x005a << 2) + 0xfe024400) +#define DMC_NFQ_TMRR ((0x005b << 2) + 0xfe024400) +#define DMC_NFQ_TCKESR ((0x005c << 2) + 0xfe024400) +#define DMC_NFQ_TDPD ((0x005d << 2) + 0xfe024400) +#define DMC_NFQ_DFITCTRLDELAY ((0x005e << 2) + 0xfe024400) +#define DMC_NFQ_DFITPHYWRDATA ((0x005f << 2) + 0xfe024400) +#define DMC_NFQ_DFITPHYWRLAT ((0x0060 << 2) + 0xfe024400) +#define DMC_NFQ_DFITRDDATAEN ((0x0061 << 2) + 0xfe024400) +#define DMC_NFQ_DFITPHYRDLAT ((0x0062 << 2) + 0xfe024400) +#define DMC_NFQ_DFITCTRLUPDMIN ((0x0063 << 2) + 0xfe024400) +#define DMC_NFQ_DFITCTRLUPDMAX ((0x0064 << 2) + 0xfe024400) +#define DMC_NFQ_DFITREFMSKI ((0x0066 << 2) + 0xfe024400) +#define DMC_NFQ_DFITCTRLUPDI ((0x0067 << 2) + 0xfe024400) +#define DMC_NFQ_DFITDRAMCLK ((0x0068 << 2) + 0xfe024400) +#define DMC_NFQ_DFITLPRESP ((0x006a << 2) + 0xfe024400) +#define DMC_NFQ_TCKECK ((0x006c << 2) + 0xfe024400) +#define DMC_NFQ_TREFI ((0x006d << 2) + 0xfe024400) +#define DMC_NFQ_TSR ((0x006e << 2) + 0xfe024400) +#define DMC_NFQ_TCCDMW ((0x006f << 2) + 0xfe024400) +#define DMC_NFQ_TESCKE ((0x0070 << 2) + 0xfe024400) +#define DMC_NFQ_TREFI_DDR3 ((0x0071 << 2) + 0xfe024400) +#define DMC_NFQ_TZQCAL ((0x0072 << 2) + 0xfe024400) +#define DMC_NFQ_T10US ((0x0073 << 2) + 0xfe024400) +#define DMC_NFQ_TMRRI ((0x0074 << 2) + 0xfe024400) +#define DMC_NFQ_TXS_FAST ((0x0075 << 2) + 0xfe024400) +#define DMC_NFQ_DFIODTCFG ((0x0076 << 2) + 0xfe024400) +#define DMC_NFQ_DFIODTCFG1 ((0x0077 << 2) + 0xfe024400) +#define DMC_NFQ_TWODTON ((0x0078 << 2) + 0xfe024400) +#define DMC_NFQ_TRETRAIN ((0x0079 << 2) + 0xfe024400) +#define DMC_NFQ_PHYADDRON ((0x007a << 2) + 0xfe024400) +#define DMC_NFQ_PHYWRON ((0x007b << 2) + 0xfe024400) +#define DMC_NFQ_PHYRDON ((0x007c << 2) + 0xfe024400) +#define DMC_NFQ_DFITRDDATACSEN ((0x007d << 2) + 0xfe024400) +#define DMC_NFQ_DFITPHYWRCSLAT ((0x007e << 2) + 0xfe024400) +//end of second frequency timing parameter +#define DMC_DRAM_DFITPHYUPDTYPE0 ((0x0080 << 2) + 0xfe024400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 0. +#define DMC_DRAM_DFITPHYUPDTYPE1 ((0x0081 << 2) + 0xfe024400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 1. +#define DMC_DRAM_DFITPHYUPDTYPE2 ((0x0082 << 2) + 0xfe024400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 2. +#define DMC_DRAM_DFITPHYUPDTYPE3 ((0x0083 << 2) + 0xfe024400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 3. +#define DMC_DRAM_MCFG ((0x0086 << 2) + 0xfe024400) + //bit 18. send retrain command after siu self refresh exit. 1 : enable. 0 : disable. + //bit 17. in DDR3/4 mode, send ZQCL command after exit register triggered self refresh. + //bit 16. send refresh command after finish frequency change. 1 : enable. 0 : disable. + //bit 15. send refresh command after finish LPDDR4 retraining. 1 : enable. 0 : disable. + //bit 14. 1: cke init low. 0 : cke init high. + //bit 13 1: dbi write enable only for LPDDR4. + //bit 12. 1: dbi read inversion. 0: dbi read high inversion. + //bit 11. 1: dbi read enable. 0: dbi not enabled. + //bit 10 1: enable staggered chip select for 2 ranks DRAM. + //bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state. + //bit 8 send auto refr cmd before enter register triggered self refresh + //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode. + //bit 6 disable dram clock after enter register triggered self refresh. + //bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode. + //bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4. + //bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh. + //bit 2 send ZQCS command after exit register triggered self refresh. + //bit 1 enable PHY triggered DFI_PHYUPD_REQ. + //bit 0 2T mode. always 1 in DDR3/4 mode. +#define DMC_DRAM_DFI_CTRL ((0x0089 << 2) + 0xfe024400) + //bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable. + //bit 18: dfi_rddata_cs_n polariy. 0: rank0 select = 2'b10. rank1 select = 2'b10. 1: rank0 select = 2'b01, rank1_select = 2'b10. + //bit 17: dfi_wrdata_cs_n polariy. 0: rank0 select = 2'b10. rank1 select = 2'b10. 1: rank0 select = 2'b01, rank1_select = 2'b10. + //bit 16: force PHY ctrl_on if = 1, phy_ctrl_on singal will keep on. + //bit 15 siu_dfi1_lp_en + //bit 14 siu_dfi_lp_ack_and + //bit 13 siu_dfi_lp_ack_or + //bit 12 siu_dfi1_init_start_en + //bit 11 siu_dfi_init_com_and + //bit 10 siu_dfi_init_com_or + //bit 9 siu_dfi1_freq_en + //bit 8 siu_dfi1_dram_clk_dis_en + //bit 7 siu_dfi_phyupd_type_sel + //bit 6 siu_dfi1_phyupd_ack_en + //bit 5 siu_dfi_phyupd_req_and + //bit 4 siu_dfi_phyupd_req_or + //bit 3 siu_dfi_ctrlupd_ack_and + //bit 2 siu_dfi_ctrlupd_ack_or + //bit 1 siu_dfi1_ctrlupd_req_en + //bit 0 siu_dfi1_cmd_en +#define DMC_DRAM_DFIINITCFG ((0x008a << 2) + 0xfe024400) + //bit 31. dfi_init_complete status. read only. + //bit 15:14. Frequency set 1 dfi_freq_ratio value. + //bit 12:8 Frequency set 1 dfi_freq value. + //bit 7:6 Frequency set 0 dfi_freq_ratio value. + //bit 5:1 Frequency set 0 dfi_freq value. + //bit 0. dfi_init_start value can be use manually config dfi_init_start signal. +#define DMC_DRAM_ZQ_CTRL ((0x008b << 2) + 0xfe024400) + // only 1 bit can be enabled at same time. + //bit 2 send ZQCS command to RANK0 then send comand to RANK1. + //bit 1. send ZQCS command to both RANK0 and RANK1 together. + //bit 0. send ZQCS command to only rank0. +#define DMC_DRAM_APD_CTRL ((0x008c << 2) + 0xfe024400) + //bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode + //bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode. + //bit 11 enable DFI_LP_REQ when enter Auto power down mode. + //bit 10 disable DFI_clk_disable when enter auto power down mode. + //bit 9:0 0 disable auto power down mode. + //non zero value to enable auto power down when DMC is in idle state for this number of clock cycles. +#define DMC_DRAM_ASR_CTRL ((0x008d << 2) + 0xfe024400) + //bit 31. enable RETRAIN PHY after auto selfrefresh exit. for AM_PHY only. + //bit 30. in DDR3/4 mode, send ZQCL command after exit from auto self refresh mode. + //bit 29. enable PHY clock in LP2 mode. 1: enable. 0 : disable. + //bit 28. enable dmc wait 10us after LP2 mode exit if it's long time the PHY in LP2 mode.. + //bit [27:24] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode. + //bit 23 : send REFRESH command after exit from auto self refersh mode(ASR). + //bit 22 : send REFERSH command before enter to Auto self refresh mode(ASR). + //bit 21 : send ZQCS command after exit from Auto self refresh mode(ASR). + //bit 20 : send dfi_ctrl_upd after exit from ASR mode + //bit 19 : send power down command when enter ASR mode. //for LPDDR4 only. + //bit 18 : set the PHY enter LP2 mode after enter ASR mode. + //bit 17 : send DFI_LP_REQ after enter ASR mode. + //bit 16 : set DFI_CLK_DISABLE after enter ASR mode. + //bit 15:0. 0 disable auto ASR mode. + // Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode. +#define DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xfe024400) + //bit 17:8 auto refresh request pending cnt if there's page hit request. + //bit 7 retrain enable for auto refresh requent. 1: enable. 0: disable. + //bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period + //bit 5 enable dmc send ZQCS command . + //bit 4. enable dmc send DFI_CTRUPD_REQ. + //bit 3:1. how many refresh command send for one period. = this number + 1 + //bit 0. enable dmc send auto refresh command. +#define DMC_DRAM_FREQ_CTRL ((0x0093 << 2) + 0xfe024400) +//bit 31 . write 1 to change freqency read 0: finished. +//bit 30. waiting for software to send some manual command. 1 : waiting. 0 : not ready yet. +//bit 29:9. not used. +//bit 19:16. how many cycles to send PLL change req after init_complete signal to low. +//bit 15. freq pre config_en. Before freq enter stop state let DMC configure DDR SDRAM. +//bit 13. freq post config_en. After freq enter stop state let DMC configure DDR SDRAM. +//bit 13. send zqcl after freq change in DDR3/4 mode. +//bit 13. send zqcl after freq change in DDR3/4 mode. +//bit 12. send zqcs after freq change. 1: enable. 0 not send. +//bit 11. in AUTO MRW fucntion: the data format. 1: use USR_CMD format. 0: MRW format. +//bit 10. AUTO MRW function: 1 use hardware auto MRW function. 0: don't do auto MRW. +//bit 9. 1 : FREQ MRW done. let FREQ change machine continue. +//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle. + // 0 after freq change finishes the state machine go back to access state. +//bit 7 when change PLL setting, disable dmc clock +//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk. +//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait. +//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0. +//bit 3:1. not used. +//bit 0. current frequency selection. +#define DMC_DRAM_SCFG ((0x0094 << 2) + 0xfe024400) + // bit 2:0 only one bit can be high at same time. + // bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request. + // bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request. + // bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request. +#define DMC_DRAM_STAT ((0x0095 << 2) + 0xfe024400) + //bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back. + //bit 28:24 dram_sr_state + //bit 23:20 stop_st + //bit 19:15 sleep_st + //bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode. + //1 : ACCESS sending precharege command. + //2 : ACCESS sending AUTO REFESH command. + //3 : ACCESS sending DIF_CTRLUPD_REQ command. + //4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4). + //5 : ACCESS sending ZQLATCH command to LPDDR4 only. + //bit 11:8 APD STATUS: 0 : APD_IDLE + //1 : APD sending PRECHARGE command + //2 : APD sending CKE low command + //3 : APD sending DISABLE DRAM CLOCK command + //4 : APD sending DFI_LP_CTRL_REQ + //5 : APD in Auto Power down mode. + //6 : APD deassert DFI_LP_CTRL_REQ + //7 : APD sending enable DRAM CLOCK command + //8 : APD sending out CKE high command. + //bit 7:4: DRAM_STATUS: 0 : DRAM IDLE + //1 : DRAM_STOP/DRAM_CFG + //2 : DRAM_ACCESS + //3 : DRAM_SLEEP + //4 : DRAM APD(AUTO POWER DOWN). + //5 : IDLE -> STOP/CONFIG + //6 : STOP -> SLEEP + //7 : STOP -> ACCESS + //8 : ACCESS -> SLEEP. + //9 : ACCESS -> STOP + //A : ACCESS -> APD + //B : SLEEP -> STOP + //C : SLEEP -> ACCESS + //D : APD -> ACCESS + //bit 3 reserved. + //bit 2 1 : DRAM enter normal working state. + //bit 1 1 : DRAM enter sleep state. self refresh state. + //bit 0 1 : dram enter cfg state. +#define DMC_DRAM_STAT1 ((0x0096 << 2) + 0xfe024400) + //bit 11:8 freq_st. + //bit 7:5 train_st + //bit 4:0 dram_phy_st +#define DMC_PHY_RETRAINING_CTRL ((0x0097 << 2) + 0xfe024400) + //bit 31 : phy_retraining enable. + //bit 30 : check vpu sleep_en. + //bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency. + //bit 23:0: retraining period unit : 100ns. +#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfe024400) + //LPDDR4 PHY DFI error infomation. + //bit 31:20. not used. + //bit 9. ddr0_dfi_error + //bit 8:5 ddr0_dfi_error_info. + //bit 4. ddr1_dfi_error. + //bit 3:0. ddr1_dfi_error_info. +#define DMC_LP2_TIMER ((0x009a << 2) + 0xfe024400) +//bit 15:0. timer setting to measure how long the chip is entered LP2 mode. +//this timer is 40bits counter with DMC PCLK. +//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode. +#define DMC_DRAM_COMPLETE_WAIT ((0x009b << 2) + 0xfe024400) + //read only how long to waiting for DFI_INIT_COMPLETE become high after DFI_INIT_START triggered. +#define DMC_DRAM_DFI_SWAP_0 ((0x00a0 << 2) + 0xfe024400) + //bit 5:0. dfi_act_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_1 ((0x00a1 << 2) + 0xfe024400) + //bit 5:0. dfi_ras_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_2 ((0x00a2 << 2) + 0xfe024400) + //bit 5:0. dfi_cas_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_3 ((0x00a3 << 2) + 0xfe024400) + //bit 5:0. dfi_we_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_4 ((0x00a4 << 2) + 0xfe024400) + //bit 5:0. dfi_bg0 function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_5 ((0x00a5 << 2) + 0xfe024400) + //bit 5:0. dfi_bg[1] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_6 ((0x00a6 << 2) + 0xfe024400) + //bit 5:0. dfi_ba[0] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_7 ((0x00a7 << 2) + 0xfe024400) + //bit 5:0. dfi_ba[1] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_8 ((0x00a8 << 2) + 0xfe024400) + //bit 5:0. dfi_ba[2] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_9 ((0x00a9 << 2) + 0xfe024400) + //bit 5:0. dfi_a[0] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_10 ((0x00aa << 2) + 0xfe024400) + //bit 5:0. dfi_a[1] function select +#define DMC_DRAM_DFI_SWAP_11 ((0x00ab << 2) + 0xfe024400) + //bit 5:0. dfi_a[2] function select +#define DMC_DRAM_DFI_SWAP_12 ((0x00ac << 2) + 0xfe024400) + //bit 5:0. dfi_a[3] function select +#define DMC_DRAM_DFI_SWAP_13 ((0x00ad << 2) + 0xfe024400) + //bit 5:0. dfi_a[4] function select +#define DMC_DRAM_DFI_SWAP_14 ((0x00ae << 2) + 0xfe024400) + //bit 5:0. dfi_a[5] function select +#define DMC_DRAM_DFI_SWAP_15 ((0x00af << 2) + 0xfe024400) + //bit 5:0. dfi_a[6] function select +#define DMC_DRAM_DFI_SWAP_16 ((0x00b0 << 2) + 0xfe024400) + //bit 5:0. dfi_a[7] function select +#define DMC_DRAM_DFI_SWAP_17 ((0x00b1 << 2) + 0xfe024400) + //bit 5:0. dfi_a[8] function select +#define DMC_DRAM_DFI_SWAP_18 ((0x00b2 << 2) + 0xfe024400) + //bit 5:0. dfi_a[9] function select +#define DMC_DRAM_DFI_SWAP_19 ((0x00b3 << 2) + 0xfe024400) + //bit 5:0. dfi_a[10] function select +#define DMC_DRAM_DFI_SWAP_20 ((0x00b4 << 2) + 0xfe024400) + //bit 5:0. dfi_a[11] function select +#define DMC_DRAM_DFI_SWAP_21 ((0x00b5 << 2) + 0xfe024400) + //bit 5:0. dfi_a[12] function select +#define DMC_DRAM_DFI_SWAP_22 ((0x00b6 << 2) + 0xfe024400) + //bit 5:0. dfi_a[13] function select +#define DMC_DRAM_DFI_SWAP_23 ((0x00b7 << 2) + 0xfe024400) + //bit 5:0. dfi_a[14] function select +#define DMC_DRAM_DFI_SWAP_24 ((0x00b8 << 2) + 0xfe024400) + //bit 5:0. dfi_a[15] function select +#define DMC_DRAM_DFI_SWAP_25 ((0x00b9 << 2) + 0xfe024400) + //bit 5:0. dfi_a[16] function select +#define DMC_DRAM_DFI_SWAP_26 ((0x00ba << 2) + 0xfe024400) + //bit 5:0. dfi_a[17] function select +#define DMC_DRAM_CMD ((0x00d0 << 2) + 0xfe024400) + //bit 31. cmd done. write 0 to clean. + //bit 30. data done. write 0 to clean. + //bit 5. user defined command. + //bit 4. LPDDR4 MPC write data command( MPC WR FIFO). + //bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO). + //bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....) + //bit 1. mrr comand. + //bit 0. mrw command. +#define DMC_DRAM_CMD_CODE ((0x00d1 << 2) + 0xfe024400) + //bit 31:28 user command case: = {act_n, ras_n, cas_n, we_n} + //bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles. + // LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles; + // DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles. + //bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. + //bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select. + //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0]. + //bit 15:0 opcode. +#define DMC_DRAM_CMD_TIME ((0x00d2 << 2) + 0xfe024400) +//bit 31:16 PRE CMD timer. //delay how many cycle to start the command. +//bit 15:0 POST CMD timer //delay how many cycle after the command execute. +#define DMC_DRAM_WSTRB0 ((0x00d3 << 2) + 0xfe024400) +#define DMC_DRAM_WSTRB1 ((0x00d4 << 2) + 0xfe024400) +#define DMC_DRAM_RDBI0 ((0x00d5 << 2) + 0xfe024400) + //MPC RD FIFO command DBI read back data + //bit 31:16 the second cycle. + //bit 15:0 the first cycle. +#define DMC_DRAM_RDBI1 ((0x00d6 << 2) + 0xfe024400) + //MPC RD FIFO command DBI read back data + //bit 31:16. the Forth cycle. + //bit 15:0. the third cycle. +//WD0~16 and RD0~16 can be used as MRW command as Frequency change . +//WD0~16 is for Freq1 DRAM MR setting, it would send to DRAM right before FREQ0-> FREQ1 +//RD0_16 is for Freq0 DRAM MR setting. it would send to DRAM right before FREQ1-> FREQ0. +//each register can be one MRW command. So total 16 MRW command can be sent to DRAM. +//The register formats: +//bit 31. MRW/USER comand enable. 1: enabled command. 0 not enabled. +//bit 30. last MRW/USER command. if this bit =1, After send this command, the DRAM controller will contine frequency next stage. +//bit 29:26. USER COMMAND parameter: in DDR3/DDR4. {act_n, ras_n, cas_n, we_n} value for user command + //in LPDDR4. bit 16: 1 4 cycles command. 0 2 cycles command. +//bit 25 MRW/USER command rank 1 select. 1: select. 0: not select. +//bit 24. MRW/USER command rank 0 select. 1: select. 0: not select. +//bit 23:0. USER command. + //DDR3: 18:16 bank address. 15:0: address. + //DDR4: 20:19 bank group address. 18:16: bank address. 15:0 address. + //LPDDR3: 9:0. rising edge address. 19:10. falling edge address. + //LPDDR4. 5:0, first edge address, 11:6 second edge address, 17:12: third edge address. 23:18, forth edge address. + //MRW command format: + //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0]. + //bit 15:0 opcode. +#define DMC_DRAM_WD0 ((0x00e0 << 2) + 0xfe024400) +#define DMC_DRAM_WD1 ((0x00e1 << 2) + 0xfe024400) +#define DMC_DRAM_WD2 ((0x00e2 << 2) + 0xfe024400) +#define DMC_DRAM_WD3 ((0x00e3 << 2) + 0xfe024400) +#define DMC_DRAM_WD4 ((0x00e4 << 2) + 0xfe024400) +#define DMC_DRAM_WD5 ((0x00e5 << 2) + 0xfe024400) +#define DMC_DRAM_WD6 ((0x00e6 << 2) + 0xfe024400) +#define DMC_DRAM_WD7 ((0x00e7 << 2) + 0xfe024400) +#define DMC_DRAM_WD8 ((0x00e8 << 2) + 0xfe024400) +#define DMC_DRAM_WD9 ((0x00e9 << 2) + 0xfe024400) +#define DMC_DRAM_WD10 ((0x00ea << 2) + 0xfe024400) +#define DMC_DRAM_WD11 ((0x00eb << 2) + 0xfe024400) +#define DMC_DRAM_WD12 ((0x00ec << 2) + 0xfe024400) +#define DMC_DRAM_WD13 ((0x00ed << 2) + 0xfe024400) +#define DMC_DRAM_WD14 ((0x00ee << 2) + 0xfe024400) +#define DMC_DRAM_WD15 ((0x00ef << 2) + 0xfe024400) +#define DMC_DRAM_RD0 ((0x00f0 << 2) + 0xfe024400) +#define DMC_DRAM_RD1 ((0x00f1 << 2) + 0xfe024400) +#define DMC_DRAM_RD2 ((0x00f2 << 2) + 0xfe024400) +#define DMC_DRAM_RD3 ((0x00f3 << 2) + 0xfe024400) +#define DMC_DRAM_RD4 ((0x00f4 << 2) + 0xfe024400) +#define DMC_DRAM_RD5 ((0x00f5 << 2) + 0xfe024400) +#define DMC_DRAM_RD6 ((0x00f6 << 2) + 0xfe024400) +#define DMC_DRAM_RD7 ((0x00f7 << 2) + 0xfe024400) +#define DMC_DRAM_RD8 ((0x00f8 << 2) + 0xfe024400) +#define DMC_DRAM_RD9 ((0x00f9 << 2) + 0xfe024400) +#define DMC_DRAM_RD10 ((0x00fa << 2) + 0xfe024400) +#define DMC_DRAM_RD11 ((0x00fb << 2) + 0xfe024400) +#define DMC_DRAM_RD12 ((0x00fc << 2) + 0xfe024400) +#define DMC_DRAM_RD13 ((0x00fd << 2) + 0xfe024400) +#define DMC_DRAM_RD14 ((0x00fe << 2) + 0xfe024400) +#define DMC_DRAM_RD15 ((0x00ff << 2) + 0xfe024400) +// +// Closing file: ../mmc_new/dmc/rtl/dmc_siu_reg.vh +// +// +// Reading file: ../mmc_new/dmc/rtl/dmc_sticky_reg.vh +// +//`ifdef DMC_STICKY_REG_DEFINE +//`else +//`define DMC_STICKY_REG_DEFINE +// ----------------------------------------------- +// APB_BASE: APB1_BASE_ADDR = 0xfe024800 +// ----------------------------------------------- +//`define DMC_STICKY_REG_BASE 32'hfe024800 +//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted. +#define DMC_STICKY_0 ((0x0000 << 2) + 0xfe024800) +#define DMC_STICKY_1 ((0x0001 << 2) + 0xfe024800) +#define DMC_STICKY_2 ((0x0002 << 2) + 0xfe024800) +#define DMC_STICKY_3 ((0x0003 << 2) + 0xfe024800) +#define DMC_STICKY_4 ((0x0004 << 2) + 0xfe024800) +#define DMC_STICKY_5 ((0x0005 << 2) + 0xfe024800) +#define DMC_STICKY_6 ((0x0006 << 2) + 0xfe024800) +#define DMC_STICKY_7 ((0x0007 << 2) + 0xfe024800) +#define DMC_STICKY_8 ((0x0008 << 2) + 0xfe024800) +#define DMC_STICKY_9 ((0x0009 << 2) + 0xfe024800) +#define DMC_STICKY_10 ((0x000a << 2) + 0xfe024800) +#define DMC_STICKY_11 ((0x000b << 2) + 0xfe024800) +#define DMC_STICKY_12 ((0x000c << 2) + 0xfe024800) +#define DMC_STICKY_13 ((0x000d << 2) + 0xfe024800) +#define DMC_STICKY_14 ((0x000e << 2) + 0xfe024800) +#define DMC_STICKY_15 ((0x000f << 2) + 0xfe024800) +#define DMC_STICKY_16 ((0x0010 << 2) + 0xfe024800) +#define DMC_STICKY_17 ((0x0011 << 2) + 0xfe024800) +#define DMC_STICKY_18 ((0x0012 << 2) + 0xfe024800) +#define DMC_STICKY_19 ((0x0013 << 2) + 0xfe024800) +#define DMC_STICKY_20 ((0x0014 << 2) + 0xfe024800) +#define DMC_STICKY_21 ((0x0015 << 2) + 0xfe024800) +#define DMC_STICKY_22 ((0x0016 << 2) + 0xfe024800) +#define DMC_STICKY_23 ((0x0017 << 2) + 0xfe024800) +#define DMC_STICKY_24 ((0x0018 << 2) + 0xfe024800) +#define DMC_STICKY_25 ((0x0019 << 2) + 0xfe024800) +#define DMC_STICKY_26 ((0x001a << 2) + 0xfe024800) +#define DMC_STICKY_27 ((0x001b << 2) + 0xfe024800) +#define DMC_STICKY_28 ((0x001c << 2) + 0xfe024800) +#define DMC_STICKY_29 ((0x001d << 2) + 0xfe024800) +#define DMC_STICKY_30 ((0x001e << 2) + 0xfe024800) +#define DMC_STICKY_31 ((0x001f << 2) + 0xfe024800) +#define DMC_STICKY_32 ((0x0020 << 2) + 0xfe024800) +#define DMC_STICKY_33 ((0x0021 << 2) + 0xfe024800) +#define DMC_STICKY_34 ((0x0022 << 2) + 0xfe024800) +#define DMC_STICKY_35 ((0x0023 << 2) + 0xfe024800) +#define DMC_STICKY_36 ((0x0024 << 2) + 0xfe024800) +#define DMC_STICKY_37 ((0x0025 << 2) + 0xfe024800) +#define DMC_STICKY_38 ((0x0026 << 2) + 0xfe024800) +#define DMC_STICKY_39 ((0x0027 << 2) + 0xfe024800) +#define DMC_STICKY_40 ((0x0028 << 2) + 0xfe024800) +#define DMC_STICKY_41 ((0x0029 << 2) + 0xfe024800) +#define DMC_STICKY_42 ((0x002a << 2) + 0xfe024800) +#define DMC_STICKY_43 ((0x002b << 2) + 0xfe024800) +#define DMC_STICKY_44 ((0x002c << 2) + 0xfe024800) +#define DMC_STICKY_45 ((0x002d << 2) + 0xfe024800) +#define DMC_STICKY_46 ((0x002e << 2) + 0xfe024800) +#define DMC_STICKY_47 ((0x002f << 2) + 0xfe024800) +#define DMC_STICKY_48 ((0x0030 << 2) + 0xfe024800) +#define DMC_STICKY_49 ((0x0031 << 2) + 0xfe024800) +#define DMC_STICKY_50 ((0x0032 << 2) + 0xfe024800) +#define DMC_STICKY_51 ((0x0033 << 2) + 0xfe024800) +#define DMC_STICKY_52 ((0x0034 << 2) + 0xfe024800) +#define DMC_STICKY_53 ((0x0035 << 2) + 0xfe024800) +#define DMC_STICKY_54 ((0x0036 << 2) + 0xfe024800) +#define DMC_STICKY_55 ((0x0037 << 2) + 0xfe024800) +#define DMC_STICKY_56 ((0x0038 << 2) + 0xfe024800) +#define DMC_STICKY_57 ((0x0039 << 2) + 0xfe024800) +#define DMC_STICKY_58 ((0x003a << 2) + 0xfe024800) +#define DMC_STICKY_59 ((0x003b << 2) + 0xfe024800) +#define DMC_STICKY_60 ((0x003c << 2) + 0xfe024800) +#define DMC_STICKY_61 ((0x003d << 2) + 0xfe024800) +#define DMC_STICKY_62 ((0x003e << 2) + 0xfe024800) +#define DMC_STICKY_63 ((0x003f << 2) + 0xfe024800) +//`endif +// +// Closing file: ../mmc_new/dmc/rtl/dmc_sticky_reg.vh +// +// +// Reading file: ../sp/rtl/SP_REG_LIST.h +// +//======================================================================== +// APB_MPU_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB_BASE_ADDR = 0xfe00c000 +// ----------------------------------------------- +#define MPU_REGION0_ST ((0x0000 << 2) + 0xfe00c000) +#define MPU_REGION0_ED ((0x0001 << 2) + 0xfe00c000) +#define MPU_REGION1_ST ((0x0002 << 2) + 0xfe00c000) +#define MPU_REGION1_ED ((0x0003 << 2) + 0xfe00c000) +#define MPU_REGION2_ST ((0x0004 << 2) + 0xfe00c000) +#define MPU_REGION2_ED ((0x0005 << 2) + 0xfe00c000) +#define MPU_REGION3_ST ((0x0006 << 2) + 0xfe00c000) +#define MPU_REGION3_ED ((0x0007 << 2) + 0xfe00c000) +#define MPU_REGION4_ST ((0x0008 << 2) + 0xfe00c000) +#define MPU_REGION4_ED ((0x0009 << 2) + 0xfe00c000) +#define MPU_REGION5_ST ((0x000a << 2) + 0xfe00c000) +#define MPU_REGION5_ED ((0x000b << 2) + 0xfe00c000) +#define MPU_REGION6_ST ((0x000c << 2) + 0xfe00c000) +#define MPU_REGION6_ED ((0x000d << 2) + 0xfe00c000) +#define MPU_REGION7_ST ((0x000e << 2) + 0xfe00c000) +#define MPU_REGION7_ED ((0x000f << 2) + 0xfe00c000) +#define MPU_REGION8_ST ((0x0010 << 2) + 0xfe00c000) +#define MPU_REGION8_ED ((0x0011 << 2) + 0xfe00c000) +#define MPU_REGION9_ST ((0x0012 << 2) + 0xfe00c000) +#define MPU_REGION9_ED ((0x0013 << 2) + 0xfe00c000) +#define MPU_REGION10_ST ((0x0014 << 2) + 0xfe00c000) +#define MPU_REGION10_ED ((0x0015 << 2) + 0xfe00c000) +#define MPU_REGION11_ST ((0x0016 << 2) + 0xfe00c000) +#define MPU_REGION11_ED ((0x0017 << 2) + 0xfe00c000) +#define MPU_REGION12_ST ((0x0018 << 2) + 0xfe00c000) +#define MPU_REGION12_ED ((0x0019 << 2) + 0xfe00c000) +#define MPU_REGION13_ST ((0x001a << 2) + 0xfe00c000) +#define MPU_REGION13_ED ((0x001b << 2) + 0xfe00c000) +#define MPU_REGION14_ST ((0x001c << 2) + 0xfe00c000) +#define MPU_REGION14_ED ((0x001d << 2) + 0xfe00c000) +#define MPU_REGION15_ST ((0x001e << 2) + 0xfe00c000) +#define MPU_REGION15_ED ((0x001f << 2) + 0xfe00c000) +#define MPU_SEC_CTRL0 ((0x0020 << 2) + 0xfe00c000) +#define MPU_ILLEGAL0_INFO0 ((0x0021 << 2) + 0xfe00c000) +#define MPU_ILLEGAL0_INFO1 ((0x0022 << 2) + 0xfe00c000) +#define MPU_ILLEGAL0_COUNT ((0x0023 << 2) + 0xfe00c000) +#define MPU_ILLEGAL1_INFO0 ((0x0024 << 2) + 0xfe00c000) +#define MPU_ILLEGAL1_INFO1 ((0x0025 << 2) + 0xfe00c000) +#define MPU_ILLEGAL1_COUNT ((0x0026 << 2) + 0xfe00c000) +#define MPU_CONFIG_VIO ((0x0027 << 2) + 0xfe00c000) +//======================================================================== +// APB_MAILBOX_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB_BASE_ADDR = 0xff010000 +// ----------------------------------------------- +// `define MB_SCPU2REE_CSR_ADDR 12'h300 +// `define MB_SCPU2REE_DATA_ST_ADDR 12'h380 +// `define MB_SCPU2REE_DATA_ED_ADDR 12'h39f +// `define MB_SCPU2TEE_CSR_ADDR 12'h100 +// `define MB_SCPU2TEE_DATA_ST_ADDR 12'h180 +// `define MB_SCPU2TEE_DATA_ED_ADDR 12'h19f +// `define MB_REE2SCPU_CSR_ADDR 12'h200 +// `define MB_REE2SCPU_DATA_ST_ADDR 12'h280 +// `define MB_REE2SCPU_DATA_ED_ADDR 12'h29f +// `define MB_TEE2SCPU_CSR_ADDR 12'h0 +// `define MB_TEE2SCPU_DATA_ST_ADDR 12'h80 +// `define MB_TEE2SCPU_DATA_ED_ADDR 12'h9f +//======================================================================== +// APB_EDP_KL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB_BASE_ADDR = 0xff020000 +// ----------------------------------------------- +//======================================================================== +// APB_RSA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB_BASE_ADDR = 0xff030000 +// ----------------------------------------------- +//======================================================================== +// APB_DMA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB_BASE_ADDR = 0xff060000 +// ----------------------------------------------- +//======================================================================== +// APB_REG_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB_BASE_ADDR = 0xfe00c200 +// ----------------------------------------------- +#define SP_TOP_CTRL0 ((0x0000 << 2) + 0xfe00c200) +#define SP_TOP_CTRL1 ((0x0001 << 2) + 0xfe00c200) +#define SP_TOP_CTRL2 ((0x0002 << 2) + 0xfe00c200) +#define SP_TOP_CTRL3 ((0x0003 << 2) + 0xfe00c200) +#define SP_TOP_CTRL4 ((0x0004 << 2) + 0xfe00c200) +#define SP_TOP_CTRL5 ((0x0005 << 2) + 0xfe00c200) +#define SP_TOP_CTRL6 ((0x0006 << 2) + 0xfe00c200) +#define SP_TOP_CTRL7 ((0x0007 << 2) + 0xfe00c200) +#define SP_TOP_CTRL8 ((0x0008 << 2) + 0xfe00c200) +#define SP_TOP_CTRL9 ((0x0009 << 2) + 0xfe00c200) +#define SP_TOP_CTRL10_LOCK ((0x000a << 2) + 0xfe00c200) +#define SP_TOP_CTRL11_LOCK ((0x000b << 2) + 0xfe00c200) +#define SP_TOP_CTRL12_LOCK ((0x000c << 2) + 0xfe00c200) +#define SP_TOP_CTRL13_LOCK ((0x000d << 2) + 0xfe00c200) +#define SP_TOP_CTRL14_LOCK ((0x000e << 2) + 0xfe00c200) +#define SP_TOP_LOCK_CTRL ((0x000f << 2) + 0xfe00c200) +#define SP_TOP_STATUS0 ((0x0020 << 2) + 0xfe00c200) +#define SP_TOP_STATUS1 ((0x0021 << 2) + 0xfe00c200) +#define SP_TOP_STATUS2 ((0x0022 << 2) + 0xfe00c200) +#define SP_TOP_STATUS3 ((0x0023 << 2) + 0xfe00c200) +#define SP_TOP_ACPU_CTRL0 ((0x0010 << 2) + 0xfe00c200) +#define SP_TOP_ACPU_CTRL1 ((0x0011 << 2) + 0xfe00c200) +#define SP_TOP_ACPU_CTRL2 ((0x0012 << 2) + 0xfe00c200) +#define SP_TOP_ACPU_CTRL3 ((0x0013 << 2) + 0xfe00c200) +#define SP_TOP_ACPU_LOCK_CTRL ((0x0014 << 2) + 0xfe00c200) +#define SP_TOP_ACPU_STATUS0 ((0x0018 << 2) + 0xfe00c200) +#define SP_TOP_ACPU_STATUS1 ((0x0019 << 2) + 0xfe00c200) +#define SP_TOP_ACPU_STATUS2 ((0x001a << 2) + 0xfe00c200) +#define SP_TOP_ACPU_STATUS3 ((0x001b << 2) + 0xfe00c200) +#define SP_TOP_INFO0 ((0x0030 << 2) + 0xfe00c200) +#define SP_TOP_INFO1 ((0x0031 << 2) + 0xfe00c200) +#define SP_TOP_INFO2 ((0x0032 << 2) + 0xfe00c200) +#define SP_TOP_INFO3 ((0x0033 << 2) + 0xfe00c200) +#define SP_TOP_INFO4 ((0x0034 << 2) + 0xfe00c200) +#define SP_TOP_INFO5 ((0x0035 << 2) + 0xfe00c200) +#define SP_TOP_INFO6 ((0x0036 << 2) + 0xfe00c200) +#define SP_TOP_INFO7 ((0x0037 << 2) + 0xfe00c200) +#define SP_TOP_INFO8 ((0x0038 << 2) + 0xfe00c200) +#define SP_TOP_INFO9 ((0x0039 << 2) + 0xfe00c200) +#define SP_TOP_INFO10 ((0x003a << 2) + 0xfe00c200) +#define SP_TOP_INFO11 ((0x003b << 2) + 0xfe00c200) +#define SP_TOP_INFO12 ((0x003c << 2) + 0xfe00c200) +#define SP_TOP_INFO13 ((0x003d << 2) + 0xfe00c200) +#define SP_TOP_INFO14 ((0x003e << 2) + 0xfe00c200) +#define SP_TOP_INFO15 ((0x003f << 2) + 0xfe00c200) +#define SP_EXCEPTION_HANDLER ((0x0040 << 2) + 0xfe00c200) +#define SP_AOCPU_IRQ_SEL0 ((0x0060 << 2) + 0xfe00c200) +#define SP_AOCPU_IRQ_SEL1 ((0x0061 << 2) + 0xfe00c200) +#define SP_AOCPU_IRQ_SEL2 ((0x0062 << 2) + 0xfe00c200) +#define SP_AOCPU_IRQ_SEL3 ((0x0063 << 2) + 0xfe00c200) +#define SP_AOCPU_IRQ_SEL4 ((0x0064 << 2) + 0xfe00c200) +#define SP_AOCPU_IRQ_SEL5 ((0x0065 << 2) + 0xfe00c200) +#define SP_AOCPU_IRQ_SEL6 ((0x0066 << 2) + 0xfe00c200) +#define SP_AOCPU_IRQ_SEL7 ((0x0067 << 2) + 0xfe00c200) +//======================================================================== +// APB_RNG_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB_BASE_ADDR = 0xff0e0000 +// ----------------------------------------------- +//======================================================================== +// APB_OTP_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB_BASE_ADDR = 0xff0f0000 +// ----------------------------------------------- +// +// Closing file: ../sp/rtl/SP_REG_LIST.h +// +//======================================================================== +// APB0_RESET_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000000 +// ----------------------------------------------- +#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe000000) +#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe000000) +#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe000000) +#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe000000) +#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe000000) +#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe000000) +#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe000000) +#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe000000) +#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe000000) +#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe000000) +#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe000000) +#define RESETCTRL_SEC_RESET0_LEVEL ((0x0051 << 2) + 0xfe000000) +#define RESETCTRL_SEC_RESET0_MASK ((0x0052 << 2) + 0xfe000000) +//======================================================================== +// APB0_PAD_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000400 +// ----------------------------------------------- +#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe000400) +#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0010 << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0011 << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0012 << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0013 << 2) + 0xfe000400) +#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0014 << 2) + 0xfe000400) +#define PADCTRL_WORLDSYNC_CTRL0 ((0x0018 << 2) + 0xfe000400) +#define PADCTRL_GPIO_MSR_CTRL0 ((0x0019 << 2) + 0xfe000400) +#define PADCTRL_MISC_CTRL0 ((0x001a << 2) + 0xfe000400) +#define PADCTRL_GPIOD_I ((0x0020 << 2) + 0xfe000400) +#define PADCTRL_GPIOD_O ((0x0021 << 2) + 0xfe000400) +#define PADCTRL_GPIOD_OEN ((0x0022 << 2) + 0xfe000400) +#define PADCTRL_GPIOD_PULL_EN ((0x0023 << 2) + 0xfe000400) +#define PADCTRL_GPIOD_PULL_UP ((0x0024 << 2) + 0xfe000400) +#define PADCTRL_GPIOD_DS ((0x0025 << 2) + 0xfe000400) +#define PADCTRL_GPIOD_VTHX ((0x0026 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_I ((0x0030 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_O ((0x0031 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_OEN ((0x0032 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_PULL_EN ((0x0033 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_PULL_UP ((0x0034 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_VTHX ((0x0036 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_I ((0x0040 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_O ((0x0041 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_OEN ((0x0042 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_PULL_EN ((0x0043 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_PULL_UP ((0x0044 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_DS ((0x0045 << 2) + 0xfe000400) +#define PADCTRL_GPIOB_VTHX ((0x0046 << 2) + 0xfe000400) +#define PADCTRL_GPIOC_I ((0x0050 << 2) + 0xfe000400) +#define PADCTRL_GPIOC_O ((0x0051 << 2) + 0xfe000400) +#define PADCTRL_GPIOC_OEN ((0x0052 << 2) + 0xfe000400) +#define PADCTRL_GPIOC_PULL_EN ((0x0053 << 2) + 0xfe000400) +#define PADCTRL_GPIOC_PULL_UP ((0x0054 << 2) + 0xfe000400) +#define PADCTRL_GPIOC_DS ((0x0055 << 2) + 0xfe000400) +#define PADCTRL_GPIOC_VTHX ((0x0056 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_I ((0x0060 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_O ((0x0061 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_OEN ((0x0062 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_PULL_EN ((0x0063 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_PULL_UP ((0x0064 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_DS ((0x0065 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_DS_EXT ((0x0066 << 2) + 0xfe000400) +#define PADCTRL_GPIOX_VTHX ((0x0067 << 2) + 0xfe000400) +#define PADCTRL_GPIOM_I ((0x0070 << 2) + 0xfe000400) +#define PADCTRL_GPIOM_O ((0x0071 << 2) + 0xfe000400) +#define PADCTRL_GPIOM_OEN ((0x0072 << 2) + 0xfe000400) +#define PADCTRL_GPIOM_PULL_EN ((0x0073 << 2) + 0xfe000400) +#define PADCTRL_GPIOM_PULL_UP ((0x0074 << 2) + 0xfe000400) +#define PADCTRL_GPIOM_DS ((0x0075 << 2) + 0xfe000400) +#define PADCTRL_GPIOM_VTHX ((0x0076 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_I ((0x0080 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_O ((0x0081 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_OEN ((0x0082 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_PULL_EN ((0x0083 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_PULL_UP ((0x0084 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_DS ((0x0085 << 2) + 0xfe000400) +#define PADCTRL_GPIOA_VTHX ((0x0086 << 2) + 0xfe000400) +#define PADCTRL_TESTN_I ((0x0090 << 2) + 0xfe000400) +#define PADCTRL_TESTN_O ((0x0091 << 2) + 0xfe000400) +#define PADCTRL_TESTN_OEN ((0x0092 << 2) + 0xfe000400) +#define PADCTRL_TESTN_PULL_EN ((0x0093 << 2) + 0xfe000400) +#define PADCTRL_TESTN_PULL_UP ((0x0094 << 2) + 0xfe000400) +#define PADCTRL_TESTN_DS ((0x0095 << 2) + 0xfe000400) +#define PADCTRL_MUTE_CTRL ((0x00a0 << 2) + 0xfe000400) +//======================================================================== +// APB0_CLK_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000800 +// ----------------------------------------------- +#define CLKTREE_SYS_OSCIN_CTRL ((0x0000 << 2) + 0xfe000800) +#define CLKTREE_RTC_BY_OSCIN_CTRL0 ((0x0001 << 2) + 0xfe000800) +#define CLKTREE_RTC_BY_OSCIN_CTRL1 ((0x0002 << 2) + 0xfe000800) +#define CLKTREE_RTC_CTRL ((0x0003 << 2) + 0xfe000800) +#define CLKTREE_SYS_CLK_CTRL0 ((0x0004 << 2) + 0xfe000800) +#define CLKTREE_AXI_CLK_CTRL0 ((0x0005 << 2) + 0xfe000800) +#define CLKTREE_SYS_CLK_EN0 ((0x0006 << 2) + 0xfe000800) +#define CLKTREE_SYS_CLK_EN1 ((0x0007 << 2) + 0xfe000800) +#define CLKTREE_SYS_CLK_EN2 ((0x0008 << 2) + 0xfe000800) +#define CLKTREE_AXI_CLK_EN ((0x0009 << 2) + 0xfe000800) +#define CLKTREE_DSPA_CLK_EN ((0x000a << 2) + 0xfe000800) +#define CLKTREE_DSPB_CLK_EN ((0x000b << 2) + 0xfe000800) +#define CLKTREE_DSPA_CLK_CTRL0 ((0x000c << 2) + 0xfe000800) +#define CLKTREE_DSPB_CLK_CTRL0 ((0x000d << 2) + 0xfe000800) +#define CLKTREE_CLK12_24_CTRL ((0x000e << 2) + 0xfe000800) +#define CLKTREE_GEN_CLK_CTRL ((0x000f << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_CTRL0 ((0x0010 << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_CTRL1 ((0x0011 << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_CTRL2 ((0x0012 << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_VAL0 ((0x0013 << 2) + 0xfe000800) +#define CLKTREE_TIMESTAMP_VAL1 ((0x0014 << 2) + 0xfe000800) +#define CLKTREE_TIMEBASE_CTRL0 ((0x0015 << 2) + 0xfe000800) +#define CLKTREE_TIMEBASE_CTRL1 ((0x0016 << 2) + 0xfe000800) +#define CLKTREE_SAR_ADC_CLK_CTRL ((0x0030 << 2) + 0xfe000800) +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define CLKTREE_PWM_CLK_CD_CTRL ((0x0032 << 2) + 0xfe000800) +#define CLKTREE_PWM_CLK_EF_CTRL ((0x0033 << 2) + 0xfe000800) +#define CLKTREE_SPICC_CLK_CTRL ((0x0034 << 2) + 0xfe000800) +#define CLKTREE_TS_CLK_CTRL ((0x0035 << 2) + 0xfe000800) +#define CLKTREE_SPIFC_CLK_CTRL ((0x0036 << 2) + 0xfe000800) +#define CLKTREE_USB_BUSCLK_CTRL ((0x0037 << 2) + 0xfe000800) +#define CLKTREE_SD_EMMC_CLK_CTRL ((0x0038 << 2) + 0xfe000800) +#define CLKTREE_CECA_CLK_CTRL0 ((0x0039 << 2) + 0xfe000800) +#define CLKTREE_CECA_CLK_CTRL1 ((0x003a << 2) + 0xfe000800) +#define CLKTREE_CECB_CLK_CTRL0 ((0x003b << 2) + 0xfe000800) +#define CLKTREE_CECB_CLK_CTRL1 ((0x003c << 2) + 0xfe000800) +#define CLKTREE_PSRAM_CLK_CTRL ((0x003d << 2) + 0xfe000800) +#define CLKTREE_DMC_CLK_CTRL ((0x003e << 2) + 0xfe000800) +#define CLKTREE_FCLK_DIV1_SEL ((0x003f << 2) + 0xfe000800) +#define CLKTREE_TST_CTRL0 ((0x0040 << 2) + 0xfe000800) +#define CLKTREE_WAVE_CLK_CTRL0 ((0x0041 << 2) + 0xfe000800) +#define CLKTREE_WAVE_CLK_CTRL1 ((0x0042 << 2) + 0xfe000800) +#define CLKTREE_JPEG_CLK_CTRL ((0x0043 << 2) + 0xfe000800) +#define CLKTREE_MIPI_ISP_CLK_CTRL ((0x0044 << 2) + 0xfe000800) +#define CLKTREE_NNA_CLK_CTRL ((0x0045 << 2) + 0xfe000800) +#define CLKTREE_GDC_CLK_CTRL ((0x0046 << 2) + 0xfe000800) +#define CLKTREE_GE2D_CLK_CTRL ((0x0047 << 2) + 0xfe000800) +#define CLKTREE_SD_EMMC_CLK_CTRL1 ((0x0048 << 2) + 0xfe000800) +#define CLKTREE_ETH_CLK_CTRL ((0x0049 << 2) + 0xfe000800) +#define CLKTREE_PWM_CLK_GH_CTRL ((0x004a << 2) + 0xfe000800) +#define CLKTREE_PWM_CLK_IJ_CTRL ((0x004b << 2) + 0xfe000800) +#define CLKTREE_MBIST_ATSPEED_CTRL ((0x004c << 2) + 0xfe000800) +#define CLKTREE_SECPU_CLK_CTRL ((0x004d << 2) + 0xfe000800) +//======================================================================== +// APB0_CEC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe000c00 +// ----------------------------------------------- +#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe000c00) +#define CECA_RW_REG ((0x0001 << 2) + 0xfe000c00) +#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe000c00) +#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe000c00) +#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe000c00) +#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe000c00) +#define CECB_RW_REG ((0x0011 << 2) + 0xfe000c00) +#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe000c00) +#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe000c00) +#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe000c00) +//======================================================================== +// APB0_IR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001000 +// ----------------------------------------------- +#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe001000) +#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe001000) +#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe001000) +#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe001000) +#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe001000) +#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe001000) +#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe001000) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001400 +// ----------------------------------------------- +#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe001400) +#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe001400) +#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe001400) +#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe001400) +#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe001400) +#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe001400) +#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe001400) +#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe001400) +#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe001400) +#define I2C_M_A_CNTL_DELY1 ((0x0009 << 2) + 0xfe001400) +#define I2C_M_A_CNTL_DELY2 ((0x000a << 2) + 0xfe001400) +#define I2C_M_A_LOW_DELY ((0x000b << 2) + 0xfe001400) +#define I2C_M_A_HIGH_DELY ((0x000c << 2) + 0xfe001400) +#define I2C_M_A_FIFO_CTRL0 ((0x000d << 2) + 0xfe001400) +#define I2C_M_A_FIFO_CTRL1 ((0x000e << 2) + 0xfe001400) +#define I2C_M_A_FIFO_PENDING ((0x000f << 2) + 0xfe001400) +#define I2C_M_A_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe001400) +#define I2C_M_A_FIFO_ST0 ((0x0011 << 2) + 0xfe001400) +//======================================================================== +// APB0_I2C_S - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001800 +// ----------------------------------------------- +#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe001800) +#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe001800) +#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe001800) +#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe001800) +//======================================================================== +// APB0_UART_A - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe001c00 +// ----------------------------------------------- +#define UART_A_WFIFO ((0x0000 << 2) + 0xfe001c00) +#define UART_A_RFIFO ((0x0001 << 2) + 0xfe001c00) +#define UART_A_CONTROL ((0x0002 << 2) + 0xfe001c00) +#define UART_A_STATUS ((0x0003 << 2) + 0xfe001c00) +#define UART_A_MISC ((0x0004 << 2) + 0xfe001c00) +#define UART_A_REG5 ((0x0005 << 2) + 0xfe001c00) +//======================================================================== +// APB0_UART_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002000 +// ----------------------------------------------- +#define UART_B_WFIFO ((0x0000 << 2) + 0xfe002000) +#define UART_B_RFIFO ((0x0001 << 2) + 0xfe002000) +#define UART_B_CONTROL ((0x0002 << 2) + 0xfe002000) +#define UART_B_STATUS ((0x0003 << 2) + 0xfe002000) +#define UART_B_MISC ((0x0004 << 2) + 0xfe002000) +#define UART_B_REG5 ((0x0005 << 2) + 0xfe002000) +//======================================================================== +// APB0_PWM_AB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002400 +// ----------------------------------------------- +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) +#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe002400) +#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe002400) +#define PWMAB_A2 ((0x0005 << 2) + 0xfe002400) +#define PWMAB_B2 ((0x0006 << 2) + 0xfe002400) +#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe002400) +#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe002400) +//======================================================================== +// APB0_PWM_CD - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002800 +// ----------------------------------------------- +#define PWMCD_PWM_C ((0x0000 << 2) + 0xfe002800) +#define PWMCD_PWM_D ((0x0001 << 2) + 0xfe002800) +#define PWMCD_MISC_REG_CD ((0x0002 << 2) + 0xfe002800) +#define PWMCD_DELTA_SIGMA_CD ((0x0003 << 2) + 0xfe002800) +#define PWMCD_TIME_CD ((0x0004 << 2) + 0xfe002800) +#define PWMCD_C2 ((0x0005 << 2) + 0xfe002800) +#define PWMCD_D2 ((0x0006 << 2) + 0xfe002800) +#define PWMCD_BLINK_CD ((0x0007 << 2) + 0xfe002800) +#define PWMCD_LOCK_CD ((0x0008 << 2) + 0xfe002800) +//======================================================================== +// APB0_SARADC - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe002c00 +// ----------------------------------------------- +#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe002c00) +#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe002c00) +#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe002c00) +#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe002c00) +#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe002c00) +#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe002c00) +#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe002c00) +#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe002c00) +#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe002c00) +#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe002c00) +#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe002c00) +#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe002c00) +#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe002c00) +#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe002c00) +#define SAR_ADC_REG14 ((0x000e << 2) + 0xfe002c00) +#define SAR_ADC_CH0_CTRL1 ((0x0013 << 2) + 0xfe002c00) +#define SAR_ADC_CH0_CTRL2 ((0x0014 << 2) + 0xfe002c00) +#define SAR_ADC_CH0_CTRL3 ((0x0015 << 2) + 0xfe002c00) +#define SAR_ADC_CH1_CTRL1 ((0x0016 << 2) + 0xfe002c00) +#define SAR_ADC_CH1_CTRL2 ((0x0017 << 2) + 0xfe002c00) +#define SAR_ADC_CH1_CTRL3 ((0x0018 << 2) + 0xfe002c00) +#define SAR_ADC_CH2_CTRL1 ((0x0019 << 2) + 0xfe002c00) +#define SAR_ADC_CH2_CTRL2 ((0x001a << 2) + 0xfe002c00) +#define SAR_ADC_CH2_CTRL3 ((0x001b << 2) + 0xfe002c00) +#define SAR_ADC_CH3_CTRL1 ((0x001c << 2) + 0xfe002c00) +#define SAR_ADC_CH3_CTRL2 ((0x001d << 2) + 0xfe002c00) +#define SAR_ADC_CH3_CTRL3 ((0x001e << 2) + 0xfe002c00) +#define SAR_ADC_CH4_CTRL1 ((0x001f << 2) + 0xfe002c00) +#define SAR_ADC_CH4_CTRL2 ((0x0020 << 2) + 0xfe002c00) +#define SAR_ADC_CH4_CTRL3 ((0x0021 << 2) + 0xfe002c00) +#define SAR_ADC_CH5_CTRL1 ((0x0022 << 2) + 0xfe002c00) +#define SAR_ADC_CH5_CTRL2 ((0x0023 << 2) + 0xfe002c00) +#define SAR_ADC_CH5_CTRL3 ((0x0024 << 2) + 0xfe002c00) +#define SAR_ADC_CH6_CTRL1 ((0x0025 << 2) + 0xfe002c00) +#define SAR_ADC_CH6_CTRL2 ((0x0026 << 2) + 0xfe002c00) +#define SAR_ADC_CH6_CTRL3 ((0x0027 << 2) + 0xfe002c00) +#define SAR_ADC_CH7_CTRL1 ((0x0028 << 2) + 0xfe002c00) +#define SAR_ADC_CH7_CTRL2 ((0x0029 << 2) + 0xfe002c00) +#define SAR_ADC_CH7_CTRL3 ((0x002a << 2) + 0xfe002c00) +#define SAR_ADC_HCIC_CTRL1 ((0x002b << 2) + 0xfe002c00) +#define SAR_ADC_F1_CTRL ((0x002c << 2) + 0xfe002c00) +#define SAR_ADC_F2_CTRL ((0x002d << 2) + 0xfe002c00) +#define SAR_ADC_F3_CTRL ((0x002e << 2) + 0xfe002c00) +#define SAR_ADC_DECI_FILTER_CTRL ((0x002f << 2) + 0xfe002c00) +#define SAR_ADC_COEF_RAM_CNTL ((0x0030 << 2) + 0xfe002c00) +#define SAR_ADC_COEF_RAM_DATA ((0x0031 << 2) + 0xfe002c00) +#define SAR_ADC_FIFO_RD_NEW ((0x0032 << 2) + 0xfe002c00) +#define SAR_ADC_RAW ((0x0033 << 2) + 0xfe002c00) +#define SAR_ADC_CHNL0 ((0x0034 << 2) + 0xfe002c00) +#define SAR_ADC_CHNL1 ((0x0035 << 2) + 0xfe002c00) +#define SAR_ADC_CHNL2 ((0x0036 << 2) + 0xfe002c00) +#define SAR_ADC_CHNL3 ((0x0037 << 2) + 0xfe002c00) +#define SAR_ADC_CHNL4 ((0x0038 << 2) + 0xfe002c00) +#define SAR_ADC_CHNL5 ((0x0039 << 2) + 0xfe002c00) +#define SAR_ADC_CHNL6 ((0x003a << 2) + 0xfe002c00) +#define SAR_ADC_CHNL7 ((0x003b << 2) + 0xfe002c00) +//======================================================================== +// JTAGCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003000 +// ----------------------------------------------- +#define JTAGCTRL_CTRL0 ((0x0000 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_CTRL0 ((0x0001 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_ADDR0 ((0x0002 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_ADDR1 ((0x0003 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_ADDR2 ((0x0004 << 2) + 0xfe003000) +#define JTAGCTRL_PWD_ADDR3 ((0x0005 << 2) + 0xfe003000) +#define JTEECTRL_PWD_ADDR0 ((0x0006 << 2) + 0xfe003000) +#define JTEECTRL_PWD_ADDR1 ((0x0007 << 2) + 0xfe003000) +#define JTEECTRL_PWD_ADDR2 ((0x0008 << 2) + 0xfe003000) +#define JTEECTRL_PWD_ADDR3 ((0x0009 << 2) + 0xfe003000) +#define JSECCTRL_PWD_ADDR0 ((0x000a << 2) + 0xfe003000) +#define JSECCTRL_PWD_ADDR1 ((0x000b << 2) + 0xfe003000) +#define JSECCTRL_PWD_ADDR2 ((0x000c << 2) + 0xfe003000) +#define JSECCTRL_PWD_ADDR3 ((0x000d << 2) + 0xfe003000) +#define JTAGCTRL_PWD_STS ((0x000e << 2) + 0xfe003000) +//======================================================================== +// APB0_MSR_CLK - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003400 +// ----------------------------------------------- +#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe003400) +#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe003400) +#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe003400) +#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe003400) +#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe003400) +#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe003400) +#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe003400) +//======================================================================== +// APB0_SPICCA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003800 +// ----------------------------------------------- +#define SPICC_A_RXDATA ((0x0000 << 2) + 0xfe003800) +#define SPICC_A_TXDATA ((0x0001 << 2) + 0xfe003800) +#define SPICC_A_CONREG ((0x0002 << 2) + 0xfe003800) +#define SPICC_A_INTREG ((0x0003 << 2) + 0xfe003800) +#define SPICC_A_DMAREG ((0x0004 << 2) + 0xfe003800) +#define SPICC_A_STATREG ((0x0005 << 2) + 0xfe003800) +#define SPICC_A_PERIODREG ((0x0006 << 2) + 0xfe003800) +#define SPICC_A_TESTREG ((0x0007 << 2) + 0xfe003800) +#define SPICC_A_DRADDR ((0x0008 << 2) + 0xfe003800) +#define SPICC_A_DWADDR ((0x0009 << 2) + 0xfe003800) +#define SPICC_A_LD_CNTL0 ((0x000a << 2) + 0xfe003800) +#define SPICC_A_LD_CNTL1 ((0x000b << 2) + 0xfe003800) +#define SPICC_A_LD_RADDR ((0x000c << 2) + 0xfe003800) +#define SPICC_A_LD_WADDR ((0x000d << 2) + 0xfe003800) +#define SPICC_A_ENHANCE_CNTL ((0x000e << 2) + 0xfe003800) +#define SPICC_A_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003800) +#define SPICC_A_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003800) +//======================================================================== +// APB0_SPICCB_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe003c00 +// ----------------------------------------------- +#define SPICC_B_RXDATA ((0x0000 << 2) + 0xfe003c00) +#define SPICC_B_TXDATA ((0x0001 << 2) + 0xfe003c00) +#define SPICC_B_CONREG ((0x0002 << 2) + 0xfe003c00) +#define SPICC_B_INTREG ((0x0003 << 2) + 0xfe003c00) +#define SPICC_B_DMAREG ((0x0004 << 2) + 0xfe003c00) +#define SPICC_B_STATREG ((0x0005 << 2) + 0xfe003c00) +#define SPICC_B_PERIODREG ((0x0006 << 2) + 0xfe003c00) +#define SPICC_B_TESTREG ((0x0007 << 2) + 0xfe003c00) +#define SPICC_B_DRADDR ((0x0008 << 2) + 0xfe003c00) +#define SPICC_B_DWADDR ((0x0009 << 2) + 0xfe003c00) +#define SPICC_B_LD_CNTL0 ((0x000a << 2) + 0xfe003c00) +#define SPICC_B_LD_CNTL1 ((0x000b << 2) + 0xfe003c00) +#define SPICC_B_LD_RADDR ((0x000c << 2) + 0xfe003c00) +#define SPICC_B_LD_WADDR ((0x000d << 2) + 0xfe003c00) +#define SPICC_B_ENHANCE_CNTL ((0x000e << 2) + 0xfe003c00) +#define SPICC_B_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003c00) +#define SPICC_B_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003c00) +//======================================================================== +// USBCTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004000 +// ----------------------------------------------- +#define USB_CTRL0 ((0x0000 << 2) + 0xfe004000) +#define USB_CTRL1 ((0x0001 << 2) + 0xfe004000) +#define USB_CTRL2 ((0x0002 << 2) + 0xfe004000) +#define USB_CTRL3 ((0x0003 << 2) + 0xfe004000) +#define USB_CTRL4 ((0x0004 << 2) + 0xfe004000) +#define USB_CTRL5 ((0x0005 << 2) + 0xfe004000) +#define USB_CTRL6 ((0x0006 << 2) + 0xfe004000) +#define USB_CTRL7 ((0x0007 << 2) + 0xfe004000) +#define USB_CTRL8 ((0x0008 << 2) + 0xfe004000) +#define USB_CTRL9 ((0x0009 << 2) + 0xfe004000) +#define USB_CTRL10 ((0x000a << 2) + 0xfe004000) +#define USB_CTRL11 ((0x000b << 2) + 0xfe004000) +#define USB_CTRL12 ((0x000c << 2) + 0xfe004000) +#define USB_CTRL13 ((0x000d << 2) + 0xfe004000) +#define USB_CTRL14 ((0x000e << 2) + 0xfe004000) +#define USB_CTRL15 ((0x000f << 2) + 0xfe004000) +#define USB_CTRL16 ((0x0010 << 2) + 0xfe004000) +#define USB_CTRL17 ((0x0011 << 2) + 0xfe004000) +#define USB_CTRL18 ((0x0012 << 2) + 0xfe004000) +#define USB_CTRL19 ((0x0013 << 2) + 0xfe004000) +#define USB_CTRL20 ((0x0014 << 2) + 0xfe004000) +#define USB_CTRL21 ((0x0015 << 2) + 0xfe004000) +#define USB_CTRL22 ((0x0016 << 2) + 0xfe004000) +#define USB_CTRL23 ((0x0017 << 2) + 0xfe004000) +#define USB_CTRL24 ((0x0018 << 2) + 0xfe004000) +#define USB_CTRL25 ((0x0019 << 2) + 0xfe004000) +#define USB_CTRL26 ((0x001a << 2) + 0xfe004000) +#define USB_CTRL27 ((0x001b << 2) + 0xfe004000) +#define USB_CTRL28 ((0x001c << 2) + 0xfe004000) +#define USB_CTRL29 ((0x001d << 2) + 0xfe004000) +#define USB_CTRL30 ((0x001e << 2) + 0xfe004000) +#define USB_CTRL31 ((0x001f << 2) + 0xfe004000) +//======================================================================== +// APB0_ACODEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004800 +// ----------------------------------------------- +#define ACODEC_0 ((0x0000 << 2) + 0xfe004800) +#define ACODEC_1 ((0x0001 << 2) + 0xfe004800) +#define ACODEC_2 ((0x0002 << 2) + 0xfe004800) +#define ACODEC_3 ((0x0003 << 2) + 0xfe004800) +#define ACODEC_4 ((0x0004 << 2) + 0xfe004800) +#define ACODEC_5 ((0x0005 << 2) + 0xfe004800) +#define ACODEC_6 ((0x0006 << 2) + 0xfe004800) +#define ACODEC_7 ((0x0007 << 2) + 0xfe004800) +#define ACODEC_8 ((0x0008 << 2) + 0xfe004800) +#define ACODEC_9 ((0x0009 << 2) + 0xfe004800) +#define ACODEC_STS0 ((0x0010 << 2) + 0xfe004800) +//======================================================================== +// APB0_TEMP_SENSOR - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe004c00 +// ----------------------------------------------- +#define TS_CFG_REG1 ((0x0001 << 2) + 0xfe004c00) +#define TS_CFG_REG2 ((0x0002 << 2) + 0xfe004c00) +#define TS_CFG_REG3 ((0x0003 << 2) + 0xfe004c00) +#define TS_CFG_REG4 ((0x0004 << 2) + 0xfe004c00) +#define TS_CFG_REG5 ((0x0005 << 2) + 0xfe004c00) +#define TS_CFG_REG6 ((0x0006 << 2) + 0xfe004c00) +#define TS_CFG_REG7 ((0x0007 << 2) + 0xfe004c00) +#define TS_STAT0 ((0x0010 << 2) + 0xfe004c00) +#define TS_STAT1 ((0x0011 << 2) + 0xfe004c00) +#define TS_STAT2 ((0x0012 << 2) + 0xfe004c00) +#define TS_STAT3 ((0x0013 << 2) + 0xfe004c00) +#define TS_STAT4 ((0x0014 << 2) + 0xfe004c00) +#define TS_STAT5 ((0x0015 << 2) + 0xfe004c00) +#define TS_STAT6 ((0x0016 << 2) + 0xfe004c00) +#define TS_STAT7 ((0x0017 << 2) + 0xfe004c00) +#define TS_STAT8 ((0x0018 << 2) + 0xfe004c00) +#define TS_STAT9 ((0x0019 << 2) + 0xfe004c00) +//======================================================================== +// APB0_KL_EFUSE_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005000 +// ----------------------------------------------- +// +// Reading file: ../crypto/crypto_reg.h +// +#define OTP_TEE_RDY ((0x0000 << 2) + 0xfe005000) +#define OTP_TEE_CHK ((0x0001 << 2) + 0xfe005000) +#define OTP_TEE_CFG ((0x0002 << 2) + 0xfe005000) +#define OTP_TEE_WR_DAT0 ((0x0004 << 2) + 0xfe005000) +#define OTP_TEE_WR_DAT1 ((0x0005 << 2) + 0xfe005000) +#define OTP_TEE_WR_DAT2 ((0x0006 << 2) + 0xfe005000) +#define OTP_TEE_WR_DAT3 ((0x0007 << 2) + 0xfe005000) +#define OTP_TEE_RD_DAT0 ((0x0008 << 2) + 0xfe005000) +#define OTP_TEE_RD_DAT1 ((0x0009 << 2) + 0xfe005000) +#define OTP_TEE_RD_DAT2 ((0x000a << 2) + 0xfe005000) +#define OTP_TEE_RD_DAT3 ((0x000b << 2) + 0xfe005000) +#define OTP_RMA_PW0 ((0x000c << 2) + 0xfe005000) +#define OTP_RMA_PW1 ((0x000d << 2) + 0xfe005000) +#define OTP_RMA_PW2 ((0x000e << 2) + 0xfe005000) +#define OTP_RMA_PW3 ((0x000f << 2) + 0xfe005000) +#define OTP_REE_RDY ((0x0010 << 2) + 0xfe005000) +#define OTP_REE_CHK ((0x0011 << 2) + 0xfe005000) +#define OTP_REE_CFG ((0x0012 << 2) + 0xfe005000) +#define OTP_REE_RD_DAT0 ((0x0014 << 2) + 0xfe005000) +#define OTP_REE_RD_DAT1 ((0x0015 << 2) + 0xfe005000) +#define OTP_REE_RD_DAT2 ((0x0016 << 2) + 0xfe005000) +#define OTP_REE_RD_DAT3 ((0x0017 << 2) + 0xfe005000) +#define OTP_SEC_RDY ((0x0020 << 2) + 0xfe005000) +#define OTP_SEC_CHK ((0x0021 << 2) + 0xfe005000) +#define OTP_SEC_CFG ((0x0022 << 2) + 0xfe005000) +#define OTP_SEC_WR_DAT0 ((0x0024 << 2) + 0xfe005000) +#define OTP_SEC_WR_DAT1 ((0x0025 << 2) + 0xfe005000) +#define OTP_SEC_WR_DAT2 ((0x0026 << 2) + 0xfe005000) +#define OTP_SEC_WR_DAT3 ((0x0027 << 2) + 0xfe005000) +#define OTP_SEC_RD_DAT0 ((0x0028 << 2) + 0xfe005000) +#define OTP_SEC_RD_DAT1 ((0x0029 << 2) + 0xfe005000) +#define OTP_SEC_RD_DAT2 ((0x002a << 2) + 0xfe005000) +#define OTP_SEC_RD_DAT3 ((0x002b << 2) + 0xfe005000) +#define OTP_LIC0 ((0x0018 << 2) + 0xfe005000) +#define OTP_LIC1 ((0x0019 << 2) + 0xfe005000) +#define OTP_LIC2 ((0x001a << 2) + 0xfe005000) +#define OTP_LIC3 ((0x001b << 2) + 0xfe005000) +#define RNG_SEC_CONFIG_REG1 ((0x0041 << 2) + 0xfe005000) +#define RNG_SEC_CONFIG_REG2 ((0x0042 << 2) + 0xfe005000) +#define RNG_SEC_DATA ((0x0044 << 2) + 0xfe005000) +#define RNG_SEC_STS ((0x0045 << 2) + 0xfe005000) +#define RNG_USR_DATA ((0x0046 << 2) + 0xfe005000) +#define RNG_USR_STS ((0x0047 << 2) + 0xfe005000) +#define RNG_ENCLAVE_CONFIG_REG1 ((0x0048 << 2) + 0xfe005000) +#define RNG_ENCLAVE_CONFIG_REG2 ((0x0049 << 2) + 0xfe005000) +#define RNG_ENCLAVE_DATA ((0x004a << 2) + 0xfe005000) +#define RNG_ENCLAVE_STS ((0x004b << 2) + 0xfe005000) +#define KTE_SLOT0 ((0x0060 << 2) + 0xfe005000) +#define KTE_SLOT1 ((0x0061 << 2) + 0xfe005000) +#define KTE_SLOT2 ((0x0062 << 2) + 0xfe005000) +#define KTE_SLOT3 ((0x0063 << 2) + 0xfe005000) +#define KTE_SLOT4 ((0x0064 << 2) + 0xfe005000) +#define KTE_SLOT5 ((0x0065 << 2) + 0xfe005000) +#define KTE_SLOT6 ((0x0066 << 2) + 0xfe005000) +#define KTE_SLOT7 ((0x0067 << 2) + 0xfe005000) +#define KTE_SLOT8 ((0x0068 << 2) + 0xfe005000) +#define KTE_SLOT9 ((0x0069 << 2) + 0xfe005000) +#define KTE_SLOT10 ((0x006a << 2) + 0xfe005000) +#define KTE_SLOT11 ((0x006b << 2) + 0xfe005000) +#define MKL_TEE_RDY ((0x0080 << 2) + 0xfe005000) +#define MKL_TEE_CHK ((0x0081 << 2) + 0xfe005000) +#define MKL_TEE_CFG ((0x0082 << 2) + 0xfe005000) +#define MKL_TEE_EK ((0x0084 << 2) + 0xfe005000) +#define MKL_REE_RDY ((0x00a0 << 2) + 0xfe005000) +#define MKL_REE_CHK ((0x00a1 << 2) + 0xfe005000) +#define MKL_REE_CFG ((0x00a2 << 2) + 0xfe005000) +#define MKL_REE_EK ((0x00a4 << 2) + 0xfe005000) +#define MKL_SEC_RDY ((0x00c0 << 2) + 0xfe005000) +#define MKL_SEC_CHK ((0x00c1 << 2) + 0xfe005000) +#define MKL_SEC_CFG ((0x00c2 << 2) + 0xfe005000) +#define MKL_SEC_EK ((0x00c4 << 2) + 0xfe005000) +// +// Closing file: ../crypto/crypto_reg.h +// +//======================================================================== +// APB0_PWM_EF - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005400 +// ----------------------------------------------- +#define PWMEF_PWM_E ((0x0000 << 2) + 0xfe005400) +#define PWMEF_PWM_F ((0x0001 << 2) + 0xfe005400) +#define PWMEF_MISC_REG_EF ((0x0002 << 2) + 0xfe005400) +#define PWMEF_DELTA_SIGMA_EF ((0x0003 << 2) + 0xfe005400) +#define PWMEF_TIME_EF ((0x0004 << 2) + 0xfe005400) +#define PWMEF_E2 ((0x0005 << 2) + 0xfe005400) +#define PWMEF_F2 ((0x0006 << 2) + 0xfe005400) +#define PWMEF_BLINK_EF ((0x0007 << 2) + 0xfe005400) +#define PWMEF_LOCK_EF ((0x0008 << 2) + 0xfe005400) +//======================================================================== +// APB0_SYS_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005800 +// ----------------------------------------------- +#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe005800) +#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe005800) +#define SYSCTRL_METAL_REV2 ((0x0002 << 2) + 0xfe005800) +//`define SYSCTRL_PROD_ENABLE 8'h0a +#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe005800) +#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe005800) +#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe005800) +#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe005800) +#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe005800) +#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe005800) +#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe005800) +#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe005800) +#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe005800) +#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe005800) +#define SYSCTRL_TIMERE_CTRL ((0x0040 << 2) + 0xfe005800) +#define SYSCTRL_TIMERE ((0x0041 << 2) + 0xfe005800) +#define SYSCTRL_TIMERE_HI ((0x0042 << 2) + 0xfe005800) +#define SYSCTRL_TIMERF_CTRL ((0x0043 << 2) + 0xfe005800) +#define SYSCTRL_TIMERF ((0x0044 << 2) + 0xfe005800) +#define SYSCTRL_TIMERF_HI ((0x0045 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERE_CTRL ((0x0046 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERE ((0x0047 << 2) + 0xfe005800) +#define SYSCTRL_SEC_TIMERE_HI ((0x0048 << 2) + 0xfe005800) +#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe005800) +#define SYSCTRL_SEC_DDR_AXI_SEL ((0x0051 << 2) + 0xfe005800) +#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe005800) +#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe005800) +#define SYSCTRL_OSC_RING_CTRL1 ((0x0054 << 2) + 0xfe005800) +#define SYSCTRL_OSC_RING_CTRL2 ((0x0055 << 2) + 0xfe005800) +#define SYSCTRL_POC ((0x0060 << 2) + 0xfe005800) +#define SYSCTRL_TOP_SPSRAM_EMA_CTL ((0x0070 << 2) + 0xfe005800) +#define SYSCTRL_TOP_DP1CLK_EMA_CTL ((0x0071 << 2) + 0xfe005800) +#define SYSCTRL_TOP_DP2CLK_EMA_CTL ((0x0072 << 2) + 0xfe005800) +#define SYSCTRL_TOP_ROM_EMA_CTL ((0x0073 << 2) + 0xfe005800) +#define SYSCTRL_CPU_SPSRAM_EMA_CTL ((0x0074 << 2) + 0xfe005800) +#define SYSCTRL_CPU_DP1CLK_EMA_CTL ((0x0075 << 2) + 0xfe005800) +#define SYSCTRL_CPU_DP2CLK_EMA_CTL ((0x0076 << 2) + 0xfe005800) +#define SYSCTRL_NNA_SPSRAM_EMA_CTL ((0x0078 << 2) + 0xfe005800) +#define SYSCTRL_NNA_DP1CLK_EMA_CTL ((0x0079 << 2) + 0xfe005800) +#define SYSCTRL_NNA_DP2CLK_EMA_CTL ((0x007a << 2) + 0xfe005800) +#define SYSCTRL_DDR_TEST_CTL ((0x007c << 2) + 0xfe005800) +//`define SYSCTRL_PROD_PWD_VALUE0 8'h80 +//`define SYSCTRL_PROD_PWD_VALUE1 8'h81 +//`define SYSCTRL_PROD_PWD_VALUE2 8'h82 +//`define SYSCTRL_PROD_PWD_VALUE3 8'h83 +//`define SYSCTRL_PROD_STATUS 8'h84 +#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe005800) +#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe005800) +#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe005800) +#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe005800) +#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe005800) +#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe005800) +#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe005800) +#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe005800) +#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe005800) +//======================================================================== +// APB0_I2C_M_B - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe005c00 +// ----------------------------------------------- +#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe005c00) +#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe005c00) +#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe005c00) +#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe005c00) +#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe005c00) +#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe005c00) +#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe005c00) +#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe005c00) +#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe005c00) +#define I2C_M_B_CNTL_DELY1 ((0x0009 << 2) + 0xfe005c00) +#define I2C_M_B_CNTL_DELY2 ((0x000a << 2) + 0xfe005c00) +#define I2C_M_B_LOW_DELY ((0x000b << 2) + 0xfe005c00) +#define I2C_M_B_HIGH_DELY ((0x000c << 2) + 0xfe005c00) +#define I2C_M_B_FIFO_CTRL0 ((0x000d << 2) + 0xfe005c00) +#define I2C_M_B_FIFO_CTRL1 ((0x000e << 2) + 0xfe005c00) +#define I2C_M_B_FIFO_PENDING ((0x000f << 2) + 0xfe005c00) +#define I2C_M_B_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe005c00) +#define I2C_M_B_FIFO_ST0 ((0x0011 << 2) + 0xfe005c00) +//======================================================================== +// APB0_DMA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006000 +// ----------------------------------------------- +//TODO +//======================================================================== +// APB0_IRQ_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006400 +// ----------------------------------------------- +#define IRQCTRL_IRQ_INV0 ((0x0000 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_INV1 ((0x0001 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_INV2 ((0x0002 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_INV3 ((0x0003 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_INV4 ((0x0004 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_INV5 ((0x0005 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_INV6 ((0x0006 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_INV7 ((0x0007 << 2) + 0xfe006400) +#define IRQCTRL_MASK0_GIC ((0x0010 << 2) + 0xfe006400) +#define IRQCTRL_MASK1_GIC ((0x0011 << 2) + 0xfe006400) +#define IRQCTRL_MASK2_GIC ((0x0012 << 2) + 0xfe006400) +#define IRQCTRL_MASK3_GIC ((0x0013 << 2) + 0xfe006400) +#define IRQCTRL_MASK4_GIC ((0x0014 << 2) + 0xfe006400) +#define IRQCTRL_MASK5_GIC ((0x0015 << 2) + 0xfe006400) +#define IRQCTRL_MASK6_GIC ((0x0016 << 2) + 0xfe006400) +#define IRQCTRL_MASK7_GIC ((0x0017 << 2) + 0xfe006400) +#define IRQCTRL_MASK0_DSP ((0x0020 << 2) + 0xfe006400) +#define IRQCTRL_MASK1_DSP ((0x0021 << 2) + 0xfe006400) +#define IRQCTRL_MASK2_DSP ((0x0022 << 2) + 0xfe006400) +#define IRQCTRL_MASK3_DSP ((0x0023 << 2) + 0xfe006400) +#define IRQCTRL_MASK4_DSP ((0x0024 << 2) + 0xfe006400) +#define IRQCTRL_MASK5_DSP ((0x0025 << 2) + 0xfe006400) +#define IRQCTRL_MASK6_DSP ((0x0026 << 2) + 0xfe006400) +#define IRQCTRL_MASK7_DSP ((0x0027 << 2) + 0xfe006400) +#define IRQCTRL_MASK0_PWRCTRL ((0x0030 << 2) + 0xfe006400) +#define IRQCTRL_MASK1_PWRCTRL ((0x0031 << 2) + 0xfe006400) +#define IRQCTRL_MASK2_PWRCTRL ((0x0032 << 2) + 0xfe006400) +#define IRQCTRL_MASK3_PWRCTRL ((0x0033 << 2) + 0xfe006400) +#define IRQCTRL_MASK4_PWRCTRL ((0x0034 << 2) + 0xfe006400) +#define IRQCTRL_MASK5_PWRCTRL ((0x0035 << 2) + 0xfe006400) +#define IRQCTRL_MASK6_PWRCTRL ((0x0036 << 2) + 0xfe006400) +#define IRQCTRL_MASK7_PWRCTRL ((0x0037 << 2) + 0xfe006400) +#define IRQCTRL_MASK0_AOCPU ((0x0040 << 2) + 0xfe006400) +#define IRQCTRL_MASK1_AOCPU ((0x0041 << 2) + 0xfe006400) +#define IRQCTRL_MASK2_AOCPU ((0x0042 << 2) + 0xfe006400) +#define IRQCTRL_MASK3_AOCPU ((0x0043 << 2) + 0xfe006400) +#define IRQCTRL_MASK4_AOCPU ((0x0044 << 2) + 0xfe006400) +#define IRQCTRL_MASK5_AOCPU ((0x0045 << 2) + 0xfe006400) +#define IRQCTRL_MASK6_AOCPU ((0x0046 << 2) + 0xfe006400) +#define IRQCTRL_MASK7_AOCPU ((0x0047 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_MODE0 ((0x0050 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_MODE1 ((0x0051 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_MODE2 ((0x0052 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_MODE3 ((0x0053 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_MODE4 ((0x0054 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_MODE5 ((0x0055 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_MODE6 ((0x0056 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_MODE7 ((0x0057 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH0 ((0x0060 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH1 ((0x0061 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH2 ((0x0062 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH3 ((0x0063 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH4 ((0x0064 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH5 ((0x0065 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH6 ((0x0066 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH7 ((0x0067 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH_CLR0 ((0x0070 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH_CLR1 ((0x0071 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH_CLR2 ((0x0072 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH_CLR3 ((0x0073 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH_CLR4 ((0x0074 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH_CLR5 ((0x0075 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH_CLR6 ((0x0076 << 2) + 0xfe006400) +#define IRQCTRL_IRQ_LATCH_CLR7 ((0x0077 << 2) + 0xfe006400) +#define IRQCTRL_LOCK_BIT ((0x0080 << 2) + 0xfe006400) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006800 +// ----------------------------------------------- +#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe006800) +#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe006800) +#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006800) +#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006800) +#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe006800) +#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe006800) +#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe006800) +#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe006800) +#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe006800) +#define I2C_M_C_CNTL_DELY1 ((0x0009 << 2) + 0xfe006800) +#define I2C_M_C_CNTL_DELY2 ((0x000a << 2) + 0xfe006800) +#define I2C_M_C_LOW_DELY ((0x000b << 2) + 0xfe006800) +#define I2C_M_C_HIGH_DELY ((0x000c << 2) + 0xfe006800) +#define I2C_M_C_FIFO_CTRL0 ((0x000d << 2) + 0xfe006800) +#define I2C_M_C_FIFO_CTRL1 ((0x000e << 2) + 0xfe006800) +#define I2C_M_C_FIFO_PENDING ((0x000f << 2) + 0xfe006800) +#define I2C_M_C_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe006800) +#define I2C_M_C_FIFO_ST0 ((0x0011 << 2) + 0xfe006800) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe006c00 +// ----------------------------------------------- +#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe006c00) +#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe006c00) +#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006c00) +#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006c00) +#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe006c00) +#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe006c00) +#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe006c00) +#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe006c00) +#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe006c00) +#define I2C_M_D_CNTL_DELY1 ((0x0009 << 2) + 0xfe006c00) +#define I2C_M_D_CNTL_DELY2 ((0x000a << 2) + 0xfe006c00) +#define I2C_M_D_LOW_DELY ((0x000b << 2) + 0xfe006c00) +#define I2C_M_D_HIGH_DELY ((0x000c << 2) + 0xfe006c00) +#define I2C_M_D_FIFO_CTRL0 ((0x000d << 2) + 0xfe006c00) +#define I2C_M_D_FIFO_CTRL1 ((0x000e << 2) + 0xfe006c00) +#define I2C_M_D_FIFO_PENDING ((0x000f << 2) + 0xfe006c00) +#define I2C_M_D_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe006c00) +#define I2C_M_D_FIFO_ST0 ((0x0011 << 2) + 0xfe006c00) +//======================================================================== +// APB0_UART_C - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007000 +// ----------------------------------------------- +#define UART_C_WFIFO ((0x0000 << 2) + 0xfe007000) +#define UART_C_RFIFO ((0x0001 << 2) + 0xfe007000) +#define UART_C_CONTROL ((0x0002 << 2) + 0xfe007000) +#define UART_C_STATUS ((0x0003 << 2) + 0xfe007000) +#define UART_C_MISC ((0x0004 << 2) + 0xfe007000) +#define UART_C_REG5 ((0x0005 << 2) + 0xfe007000) +//======================================================================== +// CPUCTRL_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007400 +// ----------------------------------------------- +#define CPUCTRL_CTRL0 ((0x0000 << 2) + 0xfe007400) +#define CPUCTRL_CTRL1 ((0x0001 << 2) + 0xfe007400) +#define CPUCTRL_CTRL2 ((0x0002 << 2) + 0xfe007400) +#define CPUCTRL_CTRL3 ((0x0003 << 2) + 0xfe007400) +#define CPUCTRL_CTRL4 ((0x0004 << 2) + 0xfe007400) +#define CPUCTRL_CTRL5 ((0x0005 << 2) + 0xfe007400) +#define CPUCTRL_CTRL6 ((0x0006 << 2) + 0xfe007400) +#define CPUCTRL_CTRL7 ((0x0007 << 2) + 0xfe007400) +#define CPUCTRL_CTRL8 ((0x0008 << 2) + 0xfe007400) +#define CPUCTRL_CTRL9 ((0x0009 << 2) + 0xfe007400) +#define CPUCTRL_CTRL10 ((0x000a << 2) + 0xfe007400) +#define CPUCTRL_CTRL11 ((0x000b << 2) + 0xfe007400) +#define CPUCTRL_CTRL12 ((0x000c << 2) + 0xfe007400) +#define CPUCTRL_CTRL13 ((0x000d << 2) + 0xfe007400) +#define CPUCTRL_CTRL14 ((0x000e << 2) + 0xfe007400) +#define CPUCTRL_CTRL15 ((0x000f << 2) + 0xfe007400) +#define CPUCTRL_STS0 ((0x0010 << 2) + 0xfe007400) +#define CPUCTRL_STS1 ((0x0011 << 2) + 0xfe007400) +#define CPUCTRL_STS2 ((0x0012 << 2) + 0xfe007400) +#define CPUCTRL_STS3 ((0x0013 << 2) + 0xfe007400) +#define CPUCTRL_STS4 ((0x0014 << 2) + 0xfe007400) +#define CPUCTRL_STS5 ((0x0015 << 2) + 0xfe007400) +#define CPUCTRL_STS6 ((0x0016 << 2) + 0xfe007400) +#define CPUCTRL_STS7 ((0x0017 << 2) + 0xfe007400) +#define CPUCTRL_STS8 ((0x0018 << 2) + 0xfe007400) +#define CPUCTRL_STS9 ((0x0019 << 2) + 0xfe007400) +#define CPUCTRL_CLK_CTRL0 ((0x0020 << 2) + 0xfe007400) +#define CPUCTRL_CLK_CTRL1 ((0x0021 << 2) + 0xfe007400) +#define CPUCTRL_CLK_CTRL2 ((0x0022 << 2) + 0xfe007400) +#define CPUCTRL_CLK_CTRL3 ((0x0023 << 2) + 0xfe007400) +#define CPUCTRL_CLK_CTRL4 ((0x0024 << 2) + 0xfe007400) +#define CPUCTRL_CLK_CTRL5 ((0x0025 << 2) + 0xfe007400) +#define CPUCTRL_CLK_CTRL6 ((0x0026 << 2) + 0xfe007400) +#define CPUCTRL_CLK_CTRL7 ((0x0027 << 2) + 0xfe007400) +#define CPUCTRL_RESET_CTRL ((0x0030 << 2) + 0xfe007400) +#define CPUCTRL_ROM_DISABLE ((0x0031 << 2) + 0xfe007400) +//======================================================================== +// APB0_CAPU - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007800 +// ----------------------------------------------- +#define CAPU_ACCESS_EN_SLOT00_16M ((0x0000 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT00_1K ((0x0010 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT01_1K ((0x0011 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT02_1K ((0x0012 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT03_1K ((0x0013 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT04_1K ((0x0014 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT05_1K ((0x0015 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT06_1K ((0x0016 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT07_1K ((0x0017 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT08_1K ((0x0018 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT09_1K ((0x0019 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT10_1K ((0x001a << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT11_1K ((0x001b << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT12_1K ((0x001c << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT13_1K ((0x001d << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT14_1K ((0x001e << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT15_1K ((0x001f << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT16_1K ((0x0020 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT17_1K ((0x0021 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT18_1K ((0x0022 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT19_1K ((0x0023 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT20_1K ((0x0024 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT21_1K ((0x0025 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT22_1K ((0x0026 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT23_1K ((0x0027 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT24_1K ((0x0028 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT25_1K ((0x0029 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT26_1K ((0x002a << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT27_1K ((0x002b << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT28_1K ((0x002c << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT29_1K ((0x002d << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT30_1K ((0x002e << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT31_1K ((0x002f << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT32_1K ((0x0030 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT33_1K ((0x0031 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT34_1K ((0x0032 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT35_1K ((0x0033 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT36_1K ((0x0034 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT37_1K ((0x0035 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT38_1K ((0x0036 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT39_1K ((0x0037 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT40_1K ((0x0038 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT41_1K ((0x0039 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT42_1K ((0x003a << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT43_1K ((0x003b << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT44_1K ((0x003c << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT45_1K ((0x003d << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT46_1K ((0x003e << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT47_1K ((0x003f << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT48_1K ((0x0040 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT49_1K ((0x0041 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT00_4K ((0x0050 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT01_4K ((0x0051 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT02_4K ((0x0052 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT03_4K ((0x0053 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT00_8K ((0x0054 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT01_8K ((0x0055 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT02_8K ((0x0056 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT00_64K ((0x0060 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT01_64K ((0x0061 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT02_64K ((0x0062 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT03_64K ((0x0063 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT04_64K ((0x0064 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_SLOT00_8M ((0x0070 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_AHB_ISP ((0x00a0 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_AHB_ETH ((0x00a1 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_AHB_NNA ((0x00a2 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_AHB_USBDEV ((0x00a3 << 2) + 0xfe007800) +#define CAPU_ACCESS_EN_AHB_USBHOST ((0x00a4 << 2) + 0xfe007800) +//======================================================================== +// APB0_PWR_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe013000 +// ----------------------------------------------- +#define PWRCTRL_PWR_ACK0 ((0x0001 << 2) + 0xfe013000) +#define PWRCTRL_PWR_ACK1 ((0x0002 << 2) + 0xfe013000) +#define PWRCTRL_PWR_OFF0 ((0x0003 << 2) + 0xfe013000) +#define PWRCTRL_PWR_OFF1 ((0x0004 << 2) + 0xfe013000) +#define PWRCTRL_ISO_EN0 ((0x0005 << 2) + 0xfe013000) +#define PWRCTRL_ISO_EN1 ((0x0006 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD0 ((0x0007 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD1 ((0x0008 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD2 ((0x0009 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD3 ((0x000a << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD4 ((0x000b << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD5 ((0x000c << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD6 ((0x000d << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD7 ((0x000e << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD8 ((0x000f << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD9 ((0x0010 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD10 ((0x0011 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD11 ((0x0012 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD12 ((0x0013 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD13 ((0x0014 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD14 ((0x0015 << 2) + 0xfe013000) +#define PWRCTRL_MEM_PD15 ((0x0016 << 2) + 0xfe013000) +#define PWRCTRL_FOCRST0 ((0x0020 << 2) + 0xfe013000) +#define PWRCTRL_FOCRST1 ((0x0021 << 2) + 0xfe013000) +#define PWRCTRL_DDRPHY_PWROFF_CTRL ((0x0030 << 2) + 0xfe013000) +#define PWRCTRL_NNA_AXI_PWR_CNTL ((0x0031 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL0 ((0x0040 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL1 ((0x0041 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL2 ((0x0042 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL3 ((0x0043 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL4 ((0x0044 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_TIMER_TH_01 ((0x0048 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_TIMER_TH_23 ((0x0049 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_TIMER_TH_45 ((0x004a << 2) + 0xfe013000) +#define PWRCTRL_CPU0_TIMER_TH_67 ((0x004b << 2) + 0xfe013000) +#define PWRCTRL_CPU0_TIMER_TH_89 ((0x004c << 2) + 0xfe013000) +#define PWRCTRL_CPU0_IRQ_MASK0 ((0x0050 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_IRQ_MASK1 ((0x0051 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_IRQ_MASK2 ((0x0052 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_IRQ_MASK3 ((0x0053 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_IRQ_MASK4 ((0x0054 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_IRQ_MASK5 ((0x0055 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_IRQ_MASK6 ((0x0056 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_IRQ_MASK7 ((0x0057 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_MEMPD_INIT_SET ((0x0060 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_MEMPD_OFF_SET ((0x0061 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_MEMPD_ON_A_SET ((0x0062 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_MEMPD_ON_B_SET ((0x0063 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_MEMPD_ON_C_SET ((0x0064 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_MEMPD_ON_D_SET ((0x0065 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_MEMPD_STS ((0x0066 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_FSM_STS0 ((0x0067 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_FSM_STS1 ((0x0068 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_FSM_STS2 ((0x0069 << 2) + 0xfe013000) +#define PWRCTRL_CPU0_FSM_START ((0x006e << 2) + 0xfe013000) +#define PWRCTRL_CPU0_FSM_JUMP ((0x006f << 2) + 0xfe013000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL0 ((0x0070 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL1 ((0x0071 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL2 ((0x0072 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL3 ((0x0073 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL4 ((0x0074 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_TIMER_TH_01 ((0x0078 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_TIMER_TH_23 ((0x0079 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_TIMER_TH_45 ((0x007a << 2) + 0xfe013000) +#define PWRCTRL_CPU1_TIMER_TH_67 ((0x007b << 2) + 0xfe013000) +#define PWRCTRL_CPU1_TIMER_TH_89 ((0x007c << 2) + 0xfe013000) +#define PWRCTRL_CPU1_IRQ_MASK0 ((0x0080 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_IRQ_MASK1 ((0x0081 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_IRQ_MASK2 ((0x0082 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_IRQ_MASK3 ((0x0083 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_IRQ_MASK4 ((0x0084 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_IRQ_MASK5 ((0x0085 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_IRQ_MASK6 ((0x0086 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_IRQ_MASK7 ((0x0087 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_MEMPD_INIT_SET ((0x0090 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_MEMPD_OFF_SET ((0x0091 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_MEMPD_ON_A_SET ((0x0092 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_MEMPD_ON_B_SET ((0x0093 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_MEMPD_ON_C_SET ((0x0094 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_MEMPD_ON_D_SET ((0x0095 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_MEMPD_STS ((0x0096 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_FSM_STS0 ((0x0097 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_FSM_STS1 ((0x0098 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_FSM_STS2 ((0x0099 << 2) + 0xfe013000) +#define PWRCTRL_CPU1_FSM_START ((0x009e << 2) + 0xfe013000) +#define PWRCTRL_CPU1_FSM_JUMP ((0x009f << 2) + 0xfe013000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL0 ((0x00a0 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL1 ((0x00a1 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL2 ((0x00a2 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL3 ((0x00a3 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL4 ((0x00a4 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_TIMER_TH_01 ((0x00a8 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_TIMER_TH_23 ((0x00a9 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_TIMER_TH_45 ((0x00aa << 2) + 0xfe013000) +#define PWRCTRL_CPU2_TIMER_TH_67 ((0x00ab << 2) + 0xfe013000) +#define PWRCTRL_CPU2_TIMER_TH_89 ((0x00ac << 2) + 0xfe013000) +#define PWRCTRL_CPU2_IRQ_MASK0 ((0x00b0 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_IRQ_MASK1 ((0x00b1 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_IRQ_MASK2 ((0x00b2 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_IRQ_MASK3 ((0x00b3 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_IRQ_MASK4 ((0x00b4 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_IRQ_MASK5 ((0x00b5 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_IRQ_MASK6 ((0x00b6 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_IRQ_MASK7 ((0x00b7 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_MEMPD_INIT_SET ((0x00c0 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_MEMPD_OFF_SET ((0x00c1 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_MEMPD_ON_A_SET ((0x00c2 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_MEMPD_ON_B_SET ((0x00c3 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_MEMPD_ON_C_SET ((0x00c4 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_MEMPD_ON_D_SET ((0x00c5 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_MEMPD_STS ((0x00c6 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_FSM_STS0 ((0x00c7 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_FSM_STS1 ((0x00c8 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_FSM_STS2 ((0x00c9 << 2) + 0xfe013000) +#define PWRCTRL_CPU2_FSM_START ((0x00ce << 2) + 0xfe013000) +#define PWRCTRL_CPU2_FSM_JUMP ((0x00cf << 2) + 0xfe013000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL0 ((0x00d0 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL1 ((0x00d1 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL2 ((0x00d2 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL3 ((0x00d3 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL4 ((0x00d4 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_TIMER_TH_01 ((0x00d8 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_TIMER_TH_23 ((0x00d9 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_TIMER_TH_45 ((0x00da << 2) + 0xfe013000) +#define PWRCTRL_CPU3_TIMER_TH_67 ((0x00db << 2) + 0xfe013000) +#define PWRCTRL_CPU3_TIMER_TH_89 ((0x00dc << 2) + 0xfe013000) +#define PWRCTRL_CPU3_IRQ_MASK0 ((0x00e0 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_IRQ_MASK1 ((0x00e1 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_IRQ_MASK2 ((0x00e2 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_IRQ_MASK3 ((0x00e3 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_IRQ_MASK4 ((0x00e4 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_IRQ_MASK5 ((0x00e5 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_IRQ_MASK6 ((0x00e6 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_IRQ_MASK7 ((0x00e7 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_MEMPD_INIT_SET ((0x00f0 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_MEMPD_OFF_SET ((0x00f1 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_MEMPD_ON_A_SET ((0x00f2 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_MEMPD_ON_B_SET ((0x00f3 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_MEMPD_ON_C_SET ((0x00f4 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_MEMPD_ON_D_SET ((0x00f5 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_MEMPD_STS ((0x00f6 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_FSM_STS0 ((0x00f7 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_FSM_STS1 ((0x00f8 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_FSM_STS2 ((0x00f9 << 2) + 0xfe013000) +#define PWRCTRL_CPU3_FSM_START ((0x00fe << 2) + 0xfe013000) +#define PWRCTRL_CPU3_FSM_JUMP ((0x00ff << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL0 ((0x0100 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL1 ((0x0101 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL2 ((0x0102 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL3 ((0x0103 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL4 ((0x0104 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_TIMER_TH_01 ((0x0108 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_TIMER_TH_23 ((0x0109 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_TIMER_TH_45 ((0x010a << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_TIMER_TH_67 ((0x010b << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_TIMER_TH_89 ((0x010c << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_IRQ_MASK0 ((0x0110 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_IRQ_MASK1 ((0x0111 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_IRQ_MASK2 ((0x0112 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_IRQ_MASK3 ((0x0113 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_IRQ_MASK4 ((0x0114 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_IRQ_MASK5 ((0x0115 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_IRQ_MASK6 ((0x0116 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_IRQ_MASK7 ((0x0117 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_MEMPD_INIT_SET ((0x0120 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_MEMPD_OFF_SET ((0x0121 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_MEMPD_ON_A_SET ((0x0122 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_MEMPD_ON_B_SET ((0x0123 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_MEMPD_ON_C_SET ((0x0124 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_MEMPD_ON_D_SET ((0x0125 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_MEMPD_STS ((0x0126 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_FSM_STS0 ((0x0127 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_FSM_STS1 ((0x0128 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_FSM_STS2 ((0x0129 << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_FSM_START ((0x012e << 2) + 0xfe013000) +#define PWRCTRL_CPUTOP_FSM_JUMP ((0x012f << 2) + 0xfe013000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL0 ((0x0130 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL1 ((0x0131 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL2 ((0x0132 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL3 ((0x0133 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL4 ((0x0134 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_TIMER_TH_01 ((0x0138 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_TIMER_TH_23 ((0x0139 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_TIMER_TH_45 ((0x013a << 2) + 0xfe013000) +#define PWRCTRL_DSPA_TIMER_TH_67 ((0x013b << 2) + 0xfe013000) +#define PWRCTRL_DSPA_TIMER_TH_89 ((0x013c << 2) + 0xfe013000) +#define PWRCTRL_DSPA_IRQ_MASK0 ((0x0140 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_IRQ_MASK1 ((0x0141 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_IRQ_MASK2 ((0x0142 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_IRQ_MASK3 ((0x0143 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_IRQ_MASK4 ((0x0144 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_IRQ_MASK5 ((0x0145 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_IRQ_MASK6 ((0x0146 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_IRQ_MASK7 ((0x0147 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_MEMPD_INIT_SET ((0x0150 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_MEMPD_OFF_SET ((0x0151 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_MEMPD_ON_A_SET ((0x0152 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_MEMPD_ON_B_SET ((0x0153 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_MEMPD_ON_C_SET ((0x0154 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_MEMPD_ON_D_SET ((0x0155 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_MEMPD_STS ((0x0156 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_FSM_STS0 ((0x0157 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_FSM_STS1 ((0x0158 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_FSM_STS2 ((0x0159 << 2) + 0xfe013000) +#define PWRCTRL_DSPA_FSM_START ((0x015e << 2) + 0xfe013000) +#define PWRCTRL_DSPA_FSM_JUMP ((0x015f << 2) + 0xfe013000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL0 ((0x0160 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL1 ((0x0161 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL2 ((0x0162 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL3 ((0x0163 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL4 ((0x0164 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_TIMER_TH_01 ((0x0168 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_TIMER_TH_23 ((0x0169 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_TIMER_TH_45 ((0x016a << 2) + 0xfe013000) +#define PWRCTRL_DSPB_TIMER_TH_67 ((0x016b << 2) + 0xfe013000) +#define PWRCTRL_DSPB_TIMER_TH_89 ((0x016c << 2) + 0xfe013000) +#define PWRCTRL_DSPB_IRQ_MASK0 ((0x0170 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_IRQ_MASK1 ((0x0171 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_IRQ_MASK2 ((0x0172 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_IRQ_MASK3 ((0x0173 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_IRQ_MASK4 ((0x0174 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_IRQ_MASK5 ((0x0175 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_IRQ_MASK6 ((0x0176 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_IRQ_MASK7 ((0x0177 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_MEMPD_INIT_SET ((0x0180 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_MEMPD_OFF_SET ((0x0181 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_MEMPD_ON_A_SET ((0x0182 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_MEMPD_ON_B_SET ((0x0183 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_MEMPD_ON_C_SET ((0x0184 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_MEMPD_ON_D_SET ((0x0185 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_MEMPD_STS ((0x0186 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_FSM_STS0 ((0x0187 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_FSM_STS1 ((0x0188 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_FSM_STS2 ((0x0189 << 2) + 0xfe013000) +#define PWRCTRL_DSPB_FSM_START ((0x018e << 2) + 0xfe013000) +#define PWRCTRL_DSPB_FSM_JUMP ((0x018f << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_AUTO_OFF_CTRL0 ((0x0190 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_AUTO_OFF_CTRL1 ((0x0191 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_AUTO_OFF_CTRL2 ((0x0192 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_AUTO_OFF_CTRL3 ((0x0193 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_AUTO_OFF_CTRL4 ((0x0194 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_TIMER_TH_01 ((0x0198 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_TIMER_TH_23 ((0x0199 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_TIMER_TH_45 ((0x019a << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_TIMER_TH_67 ((0x019b << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_TIMER_TH_89 ((0x019c << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_IRQ_MASK0 ((0x01a0 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_IRQ_MASK1 ((0x01a1 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_IRQ_MASK2 ((0x01a2 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_IRQ_MASK3 ((0x01a3 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_IRQ_MASK4 ((0x01a4 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_IRQ_MASK5 ((0x01a5 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_IRQ_MASK6 ((0x01a6 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_IRQ_MASK7 ((0x01a7 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_MEMPD_INIT_SET ((0x01b0 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_MEMPD_OFF_SET ((0x01b1 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_MEMPD_ON_A_SET ((0x01b2 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_MEMPD_ON_B_SET ((0x01b3 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_MEMPD_ON_C_SET ((0x01b4 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_MEMPD_ON_D_SET ((0x01b5 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_MEMPD_STS ((0x01b6 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_FSM_STS0 ((0x01b7 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_FSM_STS1 ((0x01b8 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_FSM_STS2 ((0x01b9 << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_FSM_START ((0x01be << 2) + 0xfe013000) +#define PWRCTRL_SPTOP_FSM_JUMP ((0x01bf << 2) + 0xfe013000) +//======================================================================== +// APB0_ANA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe007c00 +// ----------------------------------------------- +#define ANACTRL_PLL_GATE_DIS ((0x0010 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL0 ((0x0020 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL1 ((0x0021 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL2 ((0x0022 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL3 ((0x0023 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL4 ((0x0024 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL5 ((0x0025 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_CTRL6 ((0x0026 << 2) + 0xfe007c00) +#define ANACTRL_FIXPLL_STS ((0x0027 << 2) + 0xfe007c00) +#define ANACTRL_GPPLL_CTRL0 ((0x0030 << 2) + 0xfe007c00) +#define ANACTRL_GPPLL_CTRL1 ((0x0031 << 2) + 0xfe007c00) +#define ANACTRL_GPPLL_CTRL2 ((0x0032 << 2) + 0xfe007c00) +#define ANACTRL_GPPLL_CTRL3 ((0x0033 << 2) + 0xfe007c00) +#define ANACTRL_GPPLL_CTRL4 ((0x0034 << 2) + 0xfe007c00) +#define ANACTRL_GPPLL_CTRL5 ((0x0035 << 2) + 0xfe007c00) +#define ANACTRL_GPPLL_STS ((0x0036 << 2) + 0xfe007c00) +#define ANACTRL_GPPLL_CTRL6 ((0x0037 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL0 ((0x0040 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL1 ((0x0041 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL2 ((0x0042 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL3 ((0x0043 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_CTRL4 ((0x0044 << 2) + 0xfe007c00) +#define ANACTRL_SYSPLL_STS ((0x0045 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL0 ((0x0050 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL1 ((0x0051 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL2 ((0x0052 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL3 ((0x0053 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_CTRL4 ((0x0054 << 2) + 0xfe007c00) +#define ANACTRL_HIFIPLL_STS ((0x0055 << 2) + 0xfe007c00) +//`define ANACTRL_AUDDDS_CTRL0 8'h60 +//`define ANACTRL_AUDDDS_CTRL1 8'h61 +//`define ANACTRL_AUDDDS_CTRL2 8'h62 +//`define ANACTRL_AUDDDS_CTRL3 8'h63 +//`define ANACTRL_AUDDDS_CTRL4 8'h64 +//`define ANACTRL_AUDDDS_STS 8'h65 +#define ANACTRL_MISCTOP_CTRL0 ((0x0070 << 2) + 0xfe007c00) +#define ANACTRL_POR_CNTL ((0x0082 << 2) + 0xfe007c00) +#define ANACTRL_CSI_PHY_CNTL0 ((0x0090 << 2) + 0xfe007c00) +#define ANACTRL_CSI_PHY_CNTL1 ((0x0091 << 2) + 0xfe007c00) +#define ANACTRL_CSI_PHY_CNTL2 ((0x0092 << 2) + 0xfe007c00) +#define ANACTRL_CSI_PHY_CNTL3 ((0x0093 << 2) + 0xfe007c00) +#define ANACTRL_CSI_PHY_STS ((0x0094 << 2) + 0xfe007c00) +#define ANACTRL_ISP_MAX_ADDR_CNTL ((0x0095 << 2) + 0xfe007c00) +//======================================================================== +// APB0_ETHTOP - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe009000 +// ----------------------------------------------- +#define ETHTOP_CNTL0 ((0x0000 << 2) + 0xfe009000) +#define ETHTOP_CNTL1 ((0x0001 << 2) + 0xfe009000) +//======================================================================== +// APB0_ETHPHY - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe009400 +// ----------------------------------------------- +#define ETH_PHY_DBG_CTL0 ((0x0000 << 2) + 0xfe009400) +#define ETH_PHY_DBG_CTL1 ((0x0001 << 2) + 0xfe009400) +#define ETH_PHY_DBG_CFG0 ((0x0002 << 2) + 0xfe009400) +#define ETH_PHY_DBG_CFG1 ((0x0003 << 2) + 0xfe009400) +#define ETH_PHY_DBG_CFG2 ((0x0004 << 2) + 0xfe009400) +#define ETH_PHY_DBG_CFG3 ((0x0005 << 2) + 0xfe009400) +#define ETH_PHY_DBG_CFG4 ((0x0006 << 2) + 0xfe009400) +#define ETH_PLL_STS ((0x0010 << 2) + 0xfe009400) +#define ETH_PLL_CTL0 ((0x0011 << 2) + 0xfe009400) +#define ETH_PLL_CTL1 ((0x0012 << 2) + 0xfe009400) +#define ETH_PLL_CTL2 ((0x0013 << 2) + 0xfe009400) +#define ETH_PLL_CTL3 ((0x0014 << 2) + 0xfe009400) +#define ETH_PLL_CTL4 ((0x0015 << 2) + 0xfe009400) +#define ETH_PLL_CTL5 ((0x0016 << 2) + 0xfe009400) +#define ETH_PLL_CTL6 ((0x0017 << 2) + 0xfe009400) +#define ETH_PLL_CTL7 ((0x0018 << 2) + 0xfe009400) +#define ETH_PHY_CNTL0 ((0x0020 << 2) + 0xfe009400) +#define ETH_PHY_CNTL1 ((0x0021 << 2) + 0xfe009400) +#define ETH_PHY_CNTL2 ((0x0022 << 2) + 0xfe009400) +#define ETH_PHY_CNTL3 ((0x0023 << 2) + 0xfe009400) +#define ETH_PHY_STS0 ((0x0025 << 2) + 0xfe009400) +#define ETH_PHY_STS1 ((0x0026 << 2) + 0xfe009400) +#define ETH_PHY_STS2 ((0x0027 << 2) + 0xfe009400) +#define ETH_PHY_DBG_REG ((0x0028 << 2) + 0xfe009400) +//======================================================================== +// APB0_UART_D - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe009c00 +// ----------------------------------------------- +#define UART_D_WFIFO ((0x0000 << 2) + 0xfe009c00) +#define UART_D_RFIFO ((0x0001 << 2) + 0xfe009c00) +#define UART_D_CONTROL ((0x0002 << 2) + 0xfe009c00) +#define UART_D_STATUS ((0x0003 << 2) + 0xfe009c00) +#define UART_D_MISC ((0x0004 << 2) + 0xfe009c00) +#define UART_D_REG5 ((0x0005 << 2) + 0xfe009c00) +//======================================================================== +// APB0_UART_E - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe00a000 +// ----------------------------------------------- +#define UART_E_WFIFO ((0x0000 << 2) + 0xfe00a000) +#define UART_E_RFIFO ((0x0001 << 2) + 0xfe00a000) +#define UART_E_CONTROL ((0x0002 << 2) + 0xfe00a000) +#define UART_E_STATUS ((0x0003 << 2) + 0xfe00a000) +#define UART_E_MISC ((0x0004 << 2) + 0xfe00a000) +#define UART_E_REG5 ((0x0005 << 2) + 0xfe00a000) +//======================================================================== +// APB0_PWM_GH - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe00a400 +// ----------------------------------------------- +#define PWMGH_PWM_G ((0x0000 << 2) + 0xfe00a400) +#define PWMGH_PWM_H ((0x0001 << 2) + 0xfe00a400) +#define PWMGH_MISC_REG_GH ((0x0002 << 2) + 0xfe00a400) +#define PWMGH_DELTA_SIGMA_GH ((0x0003 << 2) + 0xfe00a400) +#define PWMGH_TIME_GH ((0x0004 << 2) + 0xfe00a400) +#define PWMGH_G2 ((0x0005 << 2) + 0xfe00a400) +#define PWMGH_H2 ((0x0006 << 2) + 0xfe00a400) +#define PWMGH_BLINK_GH ((0x0007 << 2) + 0xfe00a400) +#define PWMGH_LOCK_GH ((0x0008 << 2) + 0xfe00a400) +//======================================================================== +// APB0_PWM_IJ - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe00a800 +// ----------------------------------------------- +#define PWMIJ_PWM_I ((0x0000 << 2) + 0xfe00a800) +#define PWMIJ_PWM_J ((0x0001 << 2) + 0xfe00a800) +#define PWMIJ_MISC_REG_IJ ((0x0002 << 2) + 0xfe00a800) +#define PWMIJ_DELTA_SIGMA_IJ ((0x0003 << 2) + 0xfe00a800) +#define PWMIJ_TIME_IJ ((0x0004 << 2) + 0xfe00a800) +#define PWMIJ_I2 ((0x0005 << 2) + 0xfe00a800) +#define PWMIJ_J2 ((0x0006 << 2) + 0xfe00a800) +#define PWMIJ_BLINK_IJ ((0x0007 << 2) + 0xfe00a800) +#define PWMIJ_LOCK_IJ ((0x0008 << 2) + 0xfe00a800) +//======================================================================== +// APB0_I2C_M - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe00b000 +// ----------------------------------------------- +#define I2C_M_E_CONTROL_REG ((0x0000 << 2) + 0xfe00b000) +#define I2C_M_E_SLAVE_ADDR ((0x0001 << 2) + 0xfe00b000) +#define I2C_M_E_TOKEN_LIST0 ((0x0002 << 2) + 0xfe00b000) +#define I2C_M_E_TOKEN_LIST1 ((0x0003 << 2) + 0xfe00b000) +#define I2C_M_E_WDATA_REG0 ((0x0004 << 2) + 0xfe00b000) +#define I2C_M_E_WDATA_REG1 ((0x0005 << 2) + 0xfe00b000) +#define I2C_M_E_RDATA_REG0 ((0x0006 << 2) + 0xfe00b000) +#define I2C_M_E_RDATA_REG1 ((0x0007 << 2) + 0xfe00b000) +#define I2C_M_E_TIMEOUT_TH ((0x0008 << 2) + 0xfe00b000) +#define I2C_M_E_CNTL_DELY1 ((0x0009 << 2) + 0xfe00b000) +#define I2C_M_E_CNTL_DELY2 ((0x000a << 2) + 0xfe00b000) +#define I2C_M_E_LOW_DELY ((0x000b << 2) + 0xfe00b000) +#define I2C_M_E_HIGH_DELY ((0x000c << 2) + 0xfe00b000) +#define I2C_M_E_FIFO_CTRL0 ((0x000d << 2) + 0xfe00b000) +#define I2C_M_E_FIFO_CTRL1 ((0x000e << 2) + 0xfe00b000) +#define I2C_M_E_FIFO_PENDING ((0x000f << 2) + 0xfe00b000) +#define I2C_M_E_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe00b000) +#define I2C_M_E_FIFO_ST0 ((0x0011 << 2) + 0xfe00b000) +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe020000 +// ----------------------------------------------- +#define RSA_BASE ((0x0000 << 2) + 0xfe020000) +//======================================================================== +// MAILBOX_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe00c400 +// ----------------------------------------------- +#define MAILBOX_SET_0 ((0x0000 << 2) + 0xfe00c400) +#define MAILBOX_CLR_0 ((0x0001 << 2) + 0xfe00c400) +#define MAILBOX_STAT_0 ((0x0002 << 2) + 0xfe00c400) +#define MAILBOX_SET_1 ((0x0004 << 2) + 0xfe00c400) +#define MAILBOX_CLR_1 ((0x0005 << 2) + 0xfe00c400) +#define MAILBOX_STAT_1 ((0x0006 << 2) + 0xfe00c400) +#define MAILBOX_SET_2 ((0x0008 << 2) + 0xfe00c400) +#define MAILBOX_CLR_2 ((0x0009 << 2) + 0xfe00c400) +#define MAILBOX_STAT_2 ((0x000a << 2) + 0xfe00c400) +#define MAILBOX_SET_3 ((0x000c << 2) + 0xfe00c400) +#define MAILBOX_CLR_3 ((0x000d << 2) + 0xfe00c400) +#define MAILBOX_STAT_3 ((0x000e << 2) + 0xfe00c400) +//======================================================================== +// RAMA_SEC_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe00b400 +// ----------------------------------------------- +#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfe00b400) +#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfe00b400) +#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfe00b400) +#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfe00b400) +#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfe00b400) +#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfe00b400) +#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfe00b400) +#define SRAM_RANGE7_STA ((0x0007 << 2) + 0xfe00b400) +#define SRAM_RANGE8_STA ((0x0008 << 2) + 0xfe00b400) +#define SRAM_RANGE9_STA ((0x0009 << 2) + 0xfe00b400) +#define SRAM_RANGE10_STA ((0x000a << 2) + 0xfe00b400) +#define SRAM_RANGE11_STA ((0x000b << 2) + 0xfe00b400) +#define SRAM_RANGE12_STA ((0x000c << 2) + 0xfe00b400) +#define SRAM_RANGE13_STA ((0x000d << 2) + 0xfe00b400) +#define SRAM_RANGE14_STA ((0x000e << 2) + 0xfe00b400) +#define SRAM_RANGE0_EDA ((0x000f << 2) + 0xfe00b400) +#define SRAM_RANGE1_EDA ((0x0010 << 2) + 0xfe00b400) +#define SRAM_RANGE2_EDA ((0x0011 << 2) + 0xfe00b400) +#define SRAM_RANGE3_EDA ((0x0012 << 2) + 0xfe00b400) +#define SRAM_RANGE4_EDA ((0x0013 << 2) + 0xfe00b400) +#define SRAM_RANGE5_EDA ((0x0014 << 2) + 0xfe00b400) +#define SRAM_RANGE6_EDA ((0x0015 << 2) + 0xfe00b400) +#define SRAM_RANGE7_EDA ((0x0016 << 2) + 0xfe00b400) +#define SRAM_RANGE8_EDA ((0x0017 << 2) + 0xfe00b400) +#define SRAM_RANGE9_EDA ((0x0018 << 2) + 0xfe00b400) +#define SRAM_RANGE10_EDA ((0x0019 << 2) + 0xfe00b400) +#define SRAM_RANGE11_EDA ((0x001a << 2) + 0xfe00b400) +#define SRAM_RANGE12_EDA ((0x001b << 2) + 0xfe00b400) +#define SRAM_RANGE13_EDA ((0x001c << 2) + 0xfe00b400) +#define SRAM_RANGE14_EDA ((0x001d << 2) + 0xfe00b400) +#define SRAM_RANGE0_READ_CTRL0 ((0x001e << 2) + 0xfe00b400) +#define SRAM_RANGE1_READ_CTRL0 ((0x001f << 2) + 0xfe00b400) +#define SRAM_RANGE2_READ_CTRL0 ((0x0020 << 2) + 0xfe00b400) +#define SRAM_RANGE3_READ_CTRL0 ((0x0021 << 2) + 0xfe00b400) +#define SRAM_RANGE4_READ_CTRL0 ((0x0022 << 2) + 0xfe00b400) +#define SRAM_RANGE5_READ_CTRL0 ((0x0023 << 2) + 0xfe00b400) +#define SRAM_RANGE6_READ_CTRL0 ((0x0024 << 2) + 0xfe00b400) +#define SRAM_RANGE7_READ_CTRL0 ((0x0025 << 2) + 0xfe00b400) +#define SRAM_RANGE8_READ_CTRL0 ((0x0026 << 2) + 0xfe00b400) +#define SRAM_RANGE9_READ_CTRL0 ((0x0027 << 2) + 0xfe00b400) +#define SRAM_RANGE10_READ_CTRL0 ((0x0028 << 2) + 0xfe00b400) +#define SRAM_RANGE11_READ_CTRL0 ((0x0029 << 2) + 0xfe00b400) +#define SRAM_RANGE12_READ_CTRL0 ((0x002a << 2) + 0xfe00b400) +#define SRAM_RANGE13_READ_CTRL0 ((0x002b << 2) + 0xfe00b400) +#define SRAM_RANGE14_READ_CTRL0 ((0x002c << 2) + 0xfe00b400) +#define SRAM_RANGE15_READ_CTRL0 ((0x002d << 2) + 0xfe00b400) +#define SRAM_RANGE0_WRITE_CTRL0 ((0x002e << 2) + 0xfe00b400) +#define SRAM_RANGE1_WRITE_CTRL0 ((0x002f << 2) + 0xfe00b400) +#define SRAM_RANGE2_WRITE_CTRL0 ((0x0030 << 2) + 0xfe00b400) +#define SRAM_RANGE3_WRITE_CTRL0 ((0x0031 << 2) + 0xfe00b400) +#define SRAM_RANGE4_WRITE_CTRL0 ((0x0032 << 2) + 0xfe00b400) +#define SRAM_RANGE5_WRITE_CTRL0 ((0x0033 << 2) + 0xfe00b400) +#define SRAM_RANGE6_WRITE_CTRL0 ((0x0034 << 2) + 0xfe00b400) +#define SRAM_RANGE7_WRITE_CTRL0 ((0x0035 << 2) + 0xfe00b400) +#define SRAM_RANGE8_WRITE_CTRL0 ((0x0036 << 2) + 0xfe00b400) +#define SRAM_RANGE9_WRITE_CTRL0 ((0x0037 << 2) + 0xfe00b400) +#define SRAM_RANGE10_WRITE_CTRL0 ((0x0038 << 2) + 0xfe00b400) +#define SRAM_RANGE11_WRITE_CTRL0 ((0x0039 << 2) + 0xfe00b400) +#define SRAM_RANGE12_WRITE_CTRL0 ((0x003a << 2) + 0xfe00b400) +#define SRAM_RANGE13_WRITE_CTRL0 ((0x003b << 2) + 0xfe00b400) +#define SRAM_RANGE14_WRITE_CTRL0 ((0x003c << 2) + 0xfe00b400) +#define SRAM_RANGE15_WRITE_CTRL0 ((0x003d << 2) + 0xfe00b400) +#define SRAM_RANGE0_READ_CTRL1 ((0x003e << 2) + 0xfe00b400) +#define SRAM_RANGE1_READ_CTRL1 ((0x003f << 2) + 0xfe00b400) +#define SRAM_RANGE2_READ_CTRL1 ((0x0040 << 2) + 0xfe00b400) +#define SRAM_RANGE3_READ_CTRL1 ((0x0041 << 2) + 0xfe00b400) +#define SRAM_RANGE4_READ_CTRL1 ((0x0042 << 2) + 0xfe00b400) +#define SRAM_RANGE5_READ_CTRL1 ((0x0043 << 2) + 0xfe00b400) +#define SRAM_RANGE6_READ_CTRL1 ((0x0044 << 2) + 0xfe00b400) +#define SRAM_RANGE7_READ_CTRL1 ((0x0045 << 2) + 0xfe00b400) +#define SRAM_RANGE8_READ_CTRL1 ((0x0046 << 2) + 0xfe00b400) +#define SRAM_RANGE9_READ_CTRL1 ((0x0047 << 2) + 0xfe00b400) +#define SRAM_RANGE10_READ_CTRL1 ((0x0048 << 2) + 0xfe00b400) +#define SRAM_RANGE11_READ_CTRL1 ((0x0049 << 2) + 0xfe00b400) +#define SRAM_RANGE12_READ_CTRL1 ((0x004a << 2) + 0xfe00b400) +#define SRAM_RANGE13_READ_CTRL1 ((0x004b << 2) + 0xfe00b400) +#define SRAM_RANGE14_READ_CTRL1 ((0x004c << 2) + 0xfe00b400) +#define SRAM_RANGE15_READ_CTRL1 ((0x004d << 2) + 0xfe00b400) +#define SRAM_RANGE0_WRITE_CTRL1 ((0x004e << 2) + 0xfe00b400) +#define SRAM_RANGE1_WRITE_CTRL1 ((0x004f << 2) + 0xfe00b400) +#define SRAM_RANGE2_WRITE_CTRL1 ((0x0050 << 2) + 0xfe00b400) +#define SRAM_RANGE3_WRITE_CTRL1 ((0x0051 << 2) + 0xfe00b400) +#define SRAM_RANGE4_WRITE_CTRL1 ((0x0052 << 2) + 0xfe00b400) +#define SRAM_RANGE5_WRITE_CTRL1 ((0x0053 << 2) + 0xfe00b400) +#define SRAM_RANGE6_WRITE_CTRL1 ((0x0054 << 2) + 0xfe00b400) +#define SRAM_RANGE7_WRITE_CTRL1 ((0x0055 << 2) + 0xfe00b400) +#define SRAM_RANGE8_WRITE_CTRL1 ((0x0056 << 2) + 0xfe00b400) +#define SRAM_RANGE9_WRITE_CTRL1 ((0x0057 << 2) + 0xfe00b400) +#define SRAM_RANGE10_WRITE_CTRL1 ((0x0058 << 2) + 0xfe00b400) +#define SRAM_RANGE11_WRITE_CTRL1 ((0x0059 << 2) + 0xfe00b400) +#define SRAM_RANGE12_WRITE_CTRL1 ((0x005a << 2) + 0xfe00b400) +#define SRAM_RANGE13_WRITE_CTRL1 ((0x005b << 2) + 0xfe00b400) +#define SRAM_RANGE14_WRITE_CTRL1 ((0x005c << 2) + 0xfe00b400) +#define SRAM_RANGE15_WRITE_CTRL1 ((0x005d << 2) + 0xfe00b400) +#define SRAM_SEC_CTRL0 ((0x005e << 2) + 0xfe00b400) +#define SRAM_REG_LOCK0 ((0x005f << 2) + 0xfe00b400) +#define SRAM_REG_LOCK1 ((0x0060 << 2) + 0xfe00b400) +#define SRAM_REG_LOCK2 ((0x0061 << 2) + 0xfe00b400) +// +// Reading file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +//======================================================================== +// DSPA - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe030000 +// ----------------------------------------------- +#define DSP_CFG0 ((0x0000 << 2) + 0xfe030000) +#define DSP_CFG1 ((0x0001 << 2) + 0xfe030000) +#define DSP_CFG2 ((0x0002 << 2) + 0xfe030000) +#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe030000) +#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe030000) +#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe030000) +#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe030000) +#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe030000) +#define DSP_IRQ_STS ((0x001f << 2) + 0xfe030000) +#define DSP_REMAP0 ((0x0020 << 2) + 0xfe030000) +#define DSP_REMAP1 ((0x0021 << 2) + 0xfe030000) +#define DSP_REMAP2 ((0x0022 << 2) + 0xfe030000) +#define DSP_STS0 ((0x0040 << 2) + 0xfe030000) +#define DSP_STS1 ((0x0041 << 2) + 0xfe030000) +#define DSP_STS2 ((0x0042 << 2) + 0xfe030000) +#define DSP_STS3 ((0x0043 << 2) + 0xfe030000) +#define DSP_STS4 ((0x0044 << 2) + 0xfe030000) +#define DSP_STS5 ((0x0045 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_10 ((0x005a << 2) + 0xfe030000) +#define DSP_MAILBOX_SET_11 ((0x005b << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe030000) +#define DSP_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe030000) +#define DSP_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe030000) +#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe030000) +#define DSP_QIF_STS ((0x0081 << 2) + 0xfe030000) +#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe030000) +#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe030000) +#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe030000) +#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe030000) +#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe030000) +#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe030000) +//======================================================================== +// DSPB - Registers +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe040000 +// ----------------------------------------------- +#define DSPB_CFG0 ((0x0000 << 2) + 0xfe040000) +#define DSPB_CFG1 ((0x0001 << 2) + 0xfe040000) +#define DSPB_CFG2 ((0x0002 << 2) + 0xfe040000) +#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe040000) +#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe040000) +#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe040000) +#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe040000) +#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe040000) +#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe040000) +#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe040000) +#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe040000) +#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe040000) +#define DSPB_STS0 ((0x0040 << 2) + 0xfe040000) +#define DSPB_STS1 ((0x0041 << 2) + 0xfe040000) +#define DSPB_STS2 ((0x0042 << 2) + 0xfe040000) +#define DSPB_STS3 ((0x0043 << 2) + 0xfe040000) +#define DSPB_STS4 ((0x0044 << 2) + 0xfe040000) +#define DSPB_STS5 ((0x0045 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_10 ((0x005a << 2) + 0xfe040000) +#define DSPB_MAILBOX_SET_11 ((0x005b << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe040000) +#define DSPB_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe040000) +#define DSPB_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe040000) +#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe040000) +#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe040000) +#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe040000) +#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe040000) +#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe040000) +#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe040000) +#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe040000) +#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe040000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: REG_LIST_DSP_RTL.h +// +// +// Reading file: REG_LIST_DOS_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// `define APB_DOS_VDEC_ADDR_OFFSET 6'h00 // VDEC 1 +// ----------------------------------------------- +// ----------------------------------------------- +// `define APB_DOS_HCODEC_ADDR_OFFSET 6'h10 // HCODEC 1 +// ----------------------------------------------- +// ----------------------------------------------- +// `define APB_DOS_VDEC2_ADDR_OFFSET 6'h20 // VDEC 2 // Share with HEVC2 +// ----------------------------------------------- +// ----------------------------------------------- +// `define APB_DOS_HEVC2_ADDR_OFFSET 6'h20 // HEVC 2 // Share with VDEC2 +// ----------------------------------------------- +// ----------------------------------------------- +// `define APB_DOS_HEVC_ADDR_OFFSET 6'h30 // HEVC +// ----------------------------------------------- +//======================================================================== +// DOS - Registers +//======================================================================== +// VDEC +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe060000 +// ----------------------------------------------- +// HCODEC +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe064000 +// ----------------------------------------------- +// ----------------------------------------------- +// `define DOS_HCODEC_ASSIST_CBUS_BASE 8'h00 +// ----------------------------------------------- +#define HCODEC_ASSIST_MMC_CTRL0 ((0x0001 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MMC_CTRL1 ((0x0002 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MMC_CTRL2 ((0x0003 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MMC_CTRL3 ((0x0004 << 2) + 0xfe064000) +// bit[11] canvas_blk32_wr +// bit[10] canvas_blk32 +// bit[9] Reserved +// bit[8] canvas_index_wr +// bit[7:0] canvas_index +#define HCODEC_ASSIST_CANVAS_BLK32 ((0x0005 << 2) + 0xfe064000) +//cfg_soft_rst = mfdin_reg0_crst[0]; // Soft Reset +//cfg_cg_cfe = mfdin_reg0_crst[1]; // Clock Gating Forcing Enable +//cfg_dbuf_rst = mfdin_reg0_crst[2]; // Reset DBUF information +#define HCODEC_MFDIN_REG0_CRST ((0x0008 << 2) + 0xfe064000) +//cfg_iformat = mfdin_reg1_ctrl[3:0]; // Data In Format: 0 :CANVAS 422 YCbCr<-one canvas, + // 1 :CANVAS 444 YCbCr(or RGB)<-one canvas, + // 2 :CANVAS 420 Y<-one CrCb<-one (NV21) + // 3 :CANVAS 420 Y<-one CbCr<-one (NV12) + // 4 :CANVAS 420 Y<-one Cb<-one Cr<-one + // 5 :CANVAS 444 Y<-one Cb<-one Cr<-one + // 6 : Reserved for other canvas mode + // 7 : should combine with cfg_ifmt_extra, for 10-12bits + // 8 :LINEAR RGB888 (24bit) + // 9 :LINEAR RGB565 (16bit) + // 10:LINEAR YUV422 + // 11:LINEAR YUV420 (Note:Legacy mode not supported) + // 12~15: Reserved for other linear mode +//cfg_oformat = mfdin_reg1_ctrl[5:4]; // Data Out Format: 0:420 1:422 2:444 3:reserved +//cfg_dsample_enable= mfdin_reg1_ctrl[6]; // Downsample Enable +//cfg_dsample_trunc = mfdin_reg1_ctrl[7]; // Downsample Addition Option: 0:Round 1:Truncated +//cfg_block_ysize = mfdin_reg1_ctrl[8]; // 0:block-y-size=16, 1:block-y-size=8(for JPEG's efficiency) +//cfg_interp_enable = mfdin_reg1_ctrl[9]; // Chroma Interpolation Enable +//cfg_interp_mode = mfdin_reg1_ctrl[11:10];// 0:average round 1:average truncated 2:repeat left 3:repeat right +//cfg_r2y_enable = mfdin_reg1_ctrl[12]; // RGb->YUV Enable +//cfg_r2y_mode = mfdin_reg1_ctrl[14:13];// RGb->YUV Mode +//cfg_rgb565_mode = mfdin_reg1_ctrl[15]; // RGB565 mode: 0:fill zero in tail 1:fill zero in head +//cfg_ifmt_extra = mfdin_reg1_ctrl[17:16];// when cfg_iformat==7, + // 0: CANVAS 12bit 422, YCbCr<-one canvas{...Y1[11:0],C1[11:0],Y0[11:0],C0[11:0]} + // 1: CANVAS 10bit 444, YCbCr<-one canvas{...2'b0,Y0[9:0],U0[9:0],V0[9:0]} + // 2: CANVAS 10bit 422, YCbCr<-one canvas{...Y1[9:0],C1[9:0],Y0[9:0],C0[9:0]} +//cfg_reserved1 = mfdin_reg1_ctrl[18]; // Reserved +//cfg_nr_enable = mfdin_reg1_ctrl[19]; // Noise Reduction Enable +//cfg_outofpic = mfdin_reg1_ctrl[28:20];// Out Of Picture Control: [8]mode:0:extend 1:fixed, [7:0]fixed value +//cfg_rd_blktype = mfdin_reg1_ctrl[30:29];// Block Type: 0:H264_I_PIC_ALL_4x4, 1:H264_P_PIC_Y_16x16_C_8x8, 2:JPEG_ALL_8x8, 3:Reserved +//cfg_rd_nonycintl = mfdin_reg1_ctrl[31]; // 0:YC interleaved 1:YC non-interleaved(for JPEG) +#define HCODEC_MFDIN_REG1_CTRL ((0x0009 << 2) + 0xfe064000) +//mfdin_reg2: DEBUG Only Status +#define HCODEC_MFDIN_REG2_STAT ((0x000a << 2) + 0xfe064000) +//cfg_canvas_index0 = mfdin_reg3_canv[7:0]; //canvas index 0 +//cfg_canvas_index1 = mfdin_reg3_canv[15:8]; //canvas index 1 +//cfg_canvas_index2 = mfdin_reg3_canv[23:16];//canvas index 2 +//cfg_canv_idx0_bppx = mfdin_reg3_canv[25:24];//canvas bytes per pixel in x direction for index0, 0:half 1:1 2:2 3:3 +//cfg_canv_idx1_bppx = mfdin_reg3_canv[27:26];//canvas bytes per pixel in x direction for index1, 0:half 1:1 2:2 3:3 +//cfg_canv_idx0_bppy = mfdin_reg3_canv[29:28];//canvas bytes per pixel in y direction for index0, 0:half 1:1 2:2 3:3 +//cfg_canv_idx1_bppy = mfdin_reg3_canv[31:30];//canvas bytes per pixel in y direction for index1, 0:half 1:1 2:2 3:3 +#define HCODEC_MFDIN_REG3_CANV ((0x000b << 2) + 0xfe064000) +//cfg_bytes_per_line = mfdin_reg4_lnr0[15:0]; //linear Bytes per line +//cfg_linear_bytes4p = mfdin_reg4_lnr0[17:16]; //linear (Bytes per pixel) - 1 +//cfg_linear_dbl2line = mfdin_reg4_lnr0[18]; //linear double size for odd line +#define HCODEC_MFDIN_REG4_LNR0 ((0x000c << 2) + 0xfe064000) +//cfg_base_address = mfdin_reg5_lnr1[31:0]; //linear base address +#define HCODEC_MFDIN_REG5_LNR1 ((0x000d << 2) + 0xfe064000) +//assign cfg_r2y_trunc = mfdin_reg6_dcfg[9]; //RGb->YUV Addition Option: 0:Round 1:Truncated +//assign cfg_dma_ugt = mfdin_reg6_dcfg[8]; //DMA Urgent +//assign cfg_dma_thread_id = mfdin_reg6_dcfg[7:6]; //DMA Thread ID +//assign cfg_dma_burst_num = mfdin_reg6_dcfg[5:0]; //DMA Burst Number +#define HCODEC_MFDIN_REG6_DCFG ((0x000e << 2) + 0xfe064000) +//cfg_soft_cmd = mfdin_reg7_scmd; // Soft Command [28]selfcleared start,[27:14]dmb_x,[13:0]dmb_y +#define HCODEC_MFDIN_REG7_SCMD ((0x000f << 2) + 0xfe064000) +//cfg_pic_xsize = mfdin_reg8_dmbl[23:12]; //pixel (x,y) at the begining of last dmb in the picturem, picture x size +//cfg_pic_ysize = mfdin_reg8_dmbl[11:0]; //picture y size +#define HCODEC_MFDIN_REG8_DMBL ((0x0010 << 2) + 0xfe064000) +//cfg_endian = mfdin_reg9_endn; //Endian Control +#define HCODEC_MFDIN_REG9_ENDN ((0x0011 << 2) + 0xfe064000) +//cfg_canv_biasx = mfdin_rega_cav1[23:12]; //canvas bias address x +//cfg_canv_biasy = mfdin_rega_cav1[11:0]; //canvas bias address y +#define HCODEC_MFDIN_REGA_CAV1 ((0x0012 << 2) + 0xfe064000) +//cfg_amp_en = mfdin_regb_ampc[24]; //Amplitude Enable +//cfg_amp_cy = mfdin_regb_ampc[23:16]; //Amplitude Coeff Y +//cfg_amp_cu = mfdin_regb_ampc[15:8]; //Amplitude Coeff U +//cfg_amp_cv = mfdin_regb_ampc[7:0]; //Amplitude Coeff V +#define HCODEC_MFDIN_REGB_AMPC ((0x0013 << 2) + 0xfe064000) +//cfg_mb_end = mfdin_regc_mblp; // Soft Command [28]mb end enable,[27:14]dmb_x,[13:0]dmb_y +#define HCODEC_MFDIN_REGC_MBLP ((0x0014 << 2) + 0xfe064000) +// cfg_y_snr_en = mfdin_reg0d[0]; +// cfg_y_snr_err_norm = mfdin_reg0d[1]; +// [3:0] cfg_y_snr_gau_bld_core = mfdin_reg0d[5:2]; +// [7:0] cfg_y_snr_gau_bld_ofst = mfdin_reg0d[13:6]; +// [5:0] cfg_y_snr_gau_bld_rate = mfdin_reg0d[19:14]; +// [5:0] cfg_y_snr_gau_alp0_min = mfdin_reg0d[25:20]; +// [5:0] cfg_y_snr_gau_alp0_max = mfdin_reg0d[31:26]; +#define HCODEC_MFDIN_REG0D ((0x0015 << 2) + 0xfe064000) +// cfg_y_tnr_en = mfdin_reg0e[0]; +// cfg_y_tnr_mc_en = mfdin_reg0e[1]; +// cfg_y_tnr_txt_mode = mfdin_reg0e[2]; +// [3:0] cfg_y_tnr_mot_sad_margin = mfdin_reg0e[6:3]; +// [5:0] cfg_y_tnr_alpha_min = mfdin_reg0e[12:7]; +// [5:0] cfg_y_tnr_alpha_max = mfdin_reg0e[18:13]; +// [5:0] cfg_y_tnr_deghost_os = mfdin_reg0e[24:19]; +#define HCODEC_MFDIN_REG0E ((0x0016 << 2) + 0xfe064000) +// [3:0] cfg_y_tnr_mot_cortxt_rate = mfdin_reg0f[3:0]; +// [7:0] cfg_y_tnr_mot_distxt_ofst = mfdin_reg0f[15:8]; +// [3:0] cfg_y_tnr_mot_distxt_rate = mfdin_reg0f[7:4]; +// [7:0] cfg_y_tnr_mot_dismot_ofst = mfdin_reg0f[23:16]; +// [7:0] cfg_y_tnr_mot_frcsad_lock = mfdin_reg0f[31:24]; +#define HCODEC_MFDIN_REG0F ((0x0017 << 2) + 0xfe064000) +// [7:0] cfg_y_tnr_mot2alp_frc_gain = mfdin_reg10[7:0]; +// [7:0] cfg_y_tnr_mot2alp_nrm_gain = mfdin_reg10[15:8]; +// [7:0] cfg_y_tnr_mot2alp_dis_gain = mfdin_reg10[23:16]; +// [5:0] cfg_y_tnr_mot2alp_dis_ofst = mfdin_reg10[29:24]; +#define HCODEC_MFDIN_REG10 ((0x0018 << 2) + 0xfe064000) +// [7:0] cfg_y_bld_beta2alp_rate = mfdin_reg11[7:0]; +// [5:0] cfg_y_bld_beta_min = mfdin_reg11[13:8]; +// [5:0] cfg_y_bld_beta_max = mfdin_reg11[19:14]; +#define HCODEC_MFDIN_REG11 ((0x0019 << 2) + 0xfe064000) +// REG12~16 for Chroma, same as Luma +#define HCODEC_MFDIN_REG12 ((0x001a << 2) + 0xfe064000) +#define HCODEC_MFDIN_REG13 ((0x001b << 2) + 0xfe064000) +#define HCODEC_MFDIN_REG14 ((0x001c << 2) + 0xfe064000) +#define HCODEC_MFDIN_REG15 ((0x001d << 2) + 0xfe064000) +#define HCODEC_MFDIN_REG16 ((0x001e << 2) + 0xfe064000) +#define HCODEC_MFDIN_REG17 ((0x001f << 2) + 0xfe064000) +#define HCODEC_MFDIN_REG18 ((0x0020 << 2) + 0xfe064000) +#define HCODEC_MFDIN_REG19 ((0x0021 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT0 ((0x0025 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT1 ((0x0026 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT2 ((0x0027 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT3 ((0x0028 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT4 ((0x0029 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT5 ((0x002a << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT6 ((0x002b << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT7 ((0x002c << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT8 ((0x002d << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INT9 ((0x002e << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INTA ((0x002f << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INTB ((0x0030 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INTC ((0x0031 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INTD ((0x0032 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INTE ((0x0033 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR1_INTF ((0x0034 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT0 ((0x0035 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT1 ((0x0036 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT2 ((0x0037 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT3 ((0x0038 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT4 ((0x0039 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT5 ((0x003a << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT6 ((0x003b << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT7 ((0x003c << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT8 ((0x003d << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INT9 ((0x003e << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INTA ((0x003f << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INTB ((0x0040 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INTC ((0x0041 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INTD ((0x0042 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INTE ((0x0043 << 2) + 0xfe064000) +#define HCODEC_ASSIST_AMR2_INTF ((0x0044 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBX_SSEL ((0x0045 << 2) + 0xfe064000) +#define HCODEC_ASSIST_TIMER0_LO ((0x0060 << 2) + 0xfe064000) +#define HCODEC_ASSIST_TIMER0_HI ((0x0061 << 2) + 0xfe064000) +#define HCODEC_ASSIST_TIMER1_LO ((0x0062 << 2) + 0xfe064000) +#define HCODEC_ASSIST_TIMER1_HI ((0x0063 << 2) + 0xfe064000) +#define HCODEC_ASSIST_DMA_INT ((0x0064 << 2) + 0xfe064000) +#define HCODEC_ASSIST_DMA_INT_MSK ((0x0065 << 2) + 0xfe064000) +#define HCODEC_ASSIST_DMA_INT2 ((0x0066 << 2) + 0xfe064000) +#define HCODEC_ASSIST_DMA_INT_MSK2 ((0x0067 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX0_IRQ_REG ((0x0070 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX0_CLR_REG ((0x0071 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX0_MASK ((0x0072 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX0_FIQ_SEL ((0x0073 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX1_IRQ_REG ((0x0074 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX1_CLR_REG ((0x0075 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX1_MASK ((0x0076 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX1_FIQ_SEL ((0x0077 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX2_IRQ_REG ((0x0078 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX2_CLR_REG ((0x0079 << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX2_MASK ((0x007a << 2) + 0xfe064000) +#define HCODEC_ASSIST_MBOX2_FIQ_SEL ((0x007b << 2) + 0xfe064000) +#define HCODEC_ASSIST_AXI_CTRL ((0x007c << 2) + 0xfe064000) +#define HCODEC_ASSIST_AXI_STATUS ((0x007d << 2) + 0xfe064000) +#define HCODEC_ASSIST_AXI_SETTING_VLC ((0x007e << 2) + 0xfe064000) +//------------------------------------------------------------------------------ +// HCODEC IQIDCT module level register offset +//------------------------------------------------------------------------------ +// `define DOS_HCODEC_VCPU_CBUS_BASE 8'h03 +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe064c00 +// ----------------------------------------------- +// +// Reading file: hcodec_vcpu_regs.h +// +//======================================================================== +// VCPU module level register offset +//======================================================================== +// ----------------------------------------------- +// `define DOS_HCODEC_VCPU_CBUS_BASE 8'h03 +// ----------------------------------------------- +#define HCODEC_MSP ((0x0000 << 2) + 0xfe064c00) +#define HCODEC_MPSR ((0x0001 << 2) + 0xfe064c00) +#define HCODEC_MINT_VEC_BASE ((0x0002 << 2) + 0xfe064c00) +#define HCODEC_MCPU_INTR_GRP ((0x0003 << 2) + 0xfe064c00) +#define HCODEC_MCPU_INTR_MSK ((0x0004 << 2) + 0xfe064c00) +#define HCODEC_MCPU_INTR_REQ ((0x0005 << 2) + 0xfe064c00) +//`define HCODEC_MPC_P 8'h06 +//`define HCODEC_MPC_D 8'h07 +//`define HCODEC_MPC_E 8'h08 +//`define HCODEC_MPC_W 8'h09 +//`define HCODEC_MINDEX0_REG 8'h0a +//`define HCODEC_MINDEX1_REG 8'h0b +//`define HCODEC_MINDEX2_REG 8'h0c +//`define HCODEC_MINDEX3_REG 8'h0d +//`define HCODEC_MINDEX4_REG 8'h0e +//`define HCODEC_MINDEX5_REG 8'h0f +//`define HCODEC_MINDEX6_REG 8'h10 +//`define HCODEC_MINDEX7_REG 8'h11 +//`define HCODEC_MMIN_REG 8'h12 +//`define HCODEC_MMAX_REG 8'h13 +//`define HCODEC_MBREAK0_REG 8'h14 +//`define HCODEC_MBREAK1_REG 8'h15 +//`define HCODEC_MBREAK2_REG 8'h16 +//`define HCODEC_MBREAK3_REG 8'h17 +//`define HCODEC_MBREAK_TYPE 8'h18 +//`define HCODEC_MBREAK_CTRL 8'h19 +//`define HCODEC_MBREAK_STAUTS 8'h1a +//`define HCODEC_MDB_ADDR_REG 8'h1b +//`define HCODEC_MDB_DATA_REG 8'h1c +//`define HCODEC_MDB_CTRL 8'h1d +//`define HCODEC_MSFTINT0 8'h1e +//`define HCODEC_MSFTINT1 8'h1f +// +#define HCODEC_CSP ((0x0020 << 2) + 0xfe064c00) +#define HCODEC_CPSR ((0x0021 << 2) + 0xfe064c00) +//`define HCODEC_CINT_VEC_BASE 8'h22 +//`define HCODEC_CCPU_INTR_GRP 8'h23 +//`define HCODEC_CCPU_INTR_MSK 8'h24 +//`define HCODEC_CCPU_INTR_REQ 8'h25 +//`define HCODEC_CPC_P 8'h26 +//`define HCODEC_CPC_D 8'h27 +//`define HCODEC_CPC_E 8'h28 +//`define HCODEC_CPC_W 8'h29 +//`define HCODEC_CINDEX0_REG 8'h2a +//`define HCODEC_CINDEX1_REG 8'h2b +//`define HCODEC_CINDEX2_REG 8'h2c +//`define HCODEC_CINDEX3_REG 8'h2d +//`define HCODEC_CINDEX4_REG 8'h2e +//`define HCODEC_CINDEX5_REG 8'h2f +//`define HCODEC_CINDEX6_REG 8'h30 +//`define HCODEC_CINDEX7_REG 8'h31 +//`define HCODEC_CMIN_REG 8'h32 +//`define HCODEC_CMAX_REG 8'h33 +//`define HCODEC_CBREAK0_REG 8'h34 +//`define HCODEC_CBREAK1_REG 8'h35 +//`define HCODEC_CBREAK2_REG 8'h36 +//`define HCODEC_CBREAK3_REG 8'h37 +//`define HCODEC_CBREAK_TYPE 8'h38 +//`define HCODEC_CBREAK_CTRL 8'h39 +//`define HCODEC_CBREAK_STAUTS 8'h3a +//`define HCODEC_CDB_ADDR_REG 8'h3b +//`define HCODEC_CDB_DATA_REG 8'h3c +//`define HCODEC_CDB_CTRL 8'h3d +//`define HCODEC_CSFTINT0 8'h3e +//`define HCODEC_CSFTINT1 8'h3f +// +#define HCODEC_IMEM_DMA_CTRL ((0x0040 << 2) + 0xfe064c00) +#define HCODEC_IMEM_DMA_ADR ((0x0041 << 2) + 0xfe064c00) +#define HCODEC_IMEM_DMA_COUNT ((0x0042 << 2) + 0xfe064c00) +//// bit[29:24] A_brst_num_imem +//// bit[21:16] A_id_imem +//// bit[11:0] wrrsp_count_imem (reserved) +#define HCODEC_WRRSP_IMEM ((0x0043 << 2) + 0xfe064c00) +// +//`define HCODEC_LMEM_DMA_CTRL 8'h50 +//`define HCODEC_LMEM_DMA_ADR 8'h51 +//`define HCODEC_LMEM_DMA_COUNT 8'h52 +//// bit[29:24] A_brst_num_lmem +//// bit[21:16] A_id_lmem +//// bit[11:0] wrrsp_count_lmem +//`define HCODEC_WRRSP_LMEM 8'h53 +// +//`define HCODEC_MAC_CTRL1 8'h60 +//`define HCODEC_ACC0REG1 8'h61 +//`define HCODEC_ACC1REG1 8'h62 +// +//`define HCODEC_MAC_CTRL2 8'h70 +//`define HCODEC_ACC0REG2 8'h71 +//`define HCODEC_ACC1REG2 8'h72 +//`define HCODEC_CPU_TRACE 8'h80 +// +// +// Closing file: hcodec_vcpu_regs.h +// +//------------------------------------------------------------------------------ +// ----------------------------------------------- +// `define DOS_HCODEC_HDEC_CBUS_BASE 8'h09 +// ----------------------------------------------- +//------------------------------------------------------------------------------ +// HENC module level register offset +//------------------------------------------------------------------------------ +// `define DOS_HCODEC_HENC_CBUS_BASE 8'h0a +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe066800 +// ----------------------------------------------- +// +// Reading file: henc_regs.h +// +//======================================================================== +// MDEC module level register offset +//======================================================================== +// ----------------------------------------------- +// `define DOS_HCODEC_HENC_CBUS_BASE 8'h0a +// ----------------------------------------------- +#define HENC_SCRATCH_0 ((0x00c0 << 2) + 0xfe066800) +#define HENC_SCRATCH_1 ((0x00c1 << 2) + 0xfe066800) +#define HENC_SCRATCH_2 ((0x00c2 << 2) + 0xfe066800) +#define HENC_SCRATCH_3 ((0x00c3 << 2) + 0xfe066800) +#define HENC_SCRATCH_4 ((0x00c4 << 2) + 0xfe066800) +#define HENC_SCRATCH_5 ((0x00c5 << 2) + 0xfe066800) +#define HENC_SCRATCH_6 ((0x00c6 << 2) + 0xfe066800) +#define HENC_SCRATCH_7 ((0x00c7 << 2) + 0xfe066800) +#define HENC_SCRATCH_8 ((0x00c8 << 2) + 0xfe066800) +#define HENC_SCRATCH_9 ((0x00c9 << 2) + 0xfe066800) +#define HENC_SCRATCH_A ((0x00ca << 2) + 0xfe066800) +#define HENC_SCRATCH_B ((0x00cb << 2) + 0xfe066800) +#define HENC_SCRATCH_C ((0x00cc << 2) + 0xfe066800) +#define HENC_SCRATCH_D ((0x00cd << 2) + 0xfe066800) +#define HENC_SCRATCH_E ((0x00ce << 2) + 0xfe066800) +#define HENC_SCRATCH_F ((0x00cf << 2) + 0xfe066800) +#define HENC_SCRATCH_G ((0x00d0 << 2) + 0xfe066800) +#define HENC_SCRATCH_H ((0x00d1 << 2) + 0xfe066800) +#define HENC_SCRATCH_I ((0x00d2 << 2) + 0xfe066800) +#define HENC_SCRATCH_J ((0x00d3 << 2) + 0xfe066800) +#define HENC_SCRATCH_K ((0x00d4 << 2) + 0xfe066800) +#define HENC_SCRATCH_L ((0x00d5 << 2) + 0xfe066800) +#define HENC_SCRATCH_M ((0x00d6 << 2) + 0xfe066800) +#define HENC_SCRATCH_N ((0x00d7 << 2) + 0xfe066800) +// bit [7:0] data_feed_buff_id +#define IE_DATA_FEED_BUFF_INFO ((0x00d8 << 2) + 0xfe066800) +// +// Closing file: henc_regs.h +// +//------------------------------------------------------------------------------ +// ----------------------------------------------- +// `define DOS_HCODEC_VLD_CBUS_BASE 8'h0c +// ----------------------------------------------- +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// VLC module level register offset +//------------------------------------------------------------------------------ +// `define DOS_HCODEC_VLC_CBUS_BASE 8'h0d +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe067400 +// ----------------------------------------------- +// +// Reading file: vlc_regs.h +// +//======================================================================== +// VLC module level register offset +//======================================================================== +// ----------------------------------------------- +// `define DOS_HCODEC_VLC_CBUS_BASE 8'h0d +// ----------------------------------------------- +// Bit[31:28] - henc_status +// Bit[27:9] - reserved +// Bit[8] disable_UVLC_SKIP_fix +// Bit[7] mc_hcmd_buff_enable +// Bit[6] mc_hcmd_use_mc_hcmd_buff +// Bit[5] mc_hcmd_use_mc_hcmd_hw_start +// Bit[4] no_mc_out_null_non_skipped_mb +// Bit[3] mc_out_even_skipped_mb +// Bit[2] - hcmd_enable +// Bit[1] - vlc_control_enable (0 will treat as soft_reset) +// Bit[0] - vlc_input_enable (enable input interface) +#define VLC_STATUS_CTRL ((0x0000 << 2) + 0xfe067400) +// Bit [31] - small_luma_ignore_chroma +// Bit[30:16] - Reserved +// Bit [15] - enable_free_clk_mc_hcmd_buff +// Bit [14] - enable_free_clk_reg +// Bit [13] - enable_free_clk_stream +// Bit [12] - enable_free_clk_pre_buff +// Bit [11] - enable_free_clk_vb_buff +// Bit [10] - enable_free_clk_dc_input +// Bit [9] - enable_free_clk_input +// Bit [8] - enable_free_clk_mv_cal +// Bit [7] - enable_free_clk_status +// Bit [6] - enable_free_clk_mc_dblk_cmd_if +// Bit [5] - disable_mvd_enc_finished +// Bit [4] - I16MB_share_ipred_mode_with_I4MB +// Bit [3] - fixed_picture_qp +// Bit [2] - use_set_b8_mode ( not used now) +// Bit [1] - use_set_mb_skip_run +// Bit [0] - pop_coeff_even_all_zero +#define VLC_CONFIG ((0x0001 << 2) + 0xfe067400) +// -------------------------------------------- +// Bitstream DDR Interface +// -------------------------------------------- +#define VLC_VB_START_PTR ((0x0010 << 2) + 0xfe067400) +#define VLC_VB_END_PTR ((0x0011 << 2) + 0xfe067400) +#define VLC_VB_WR_PTR ((0x0012 << 2) + 0xfe067400) +// Read Only, VLC_VB_SW_RD_PTR or VLC_VB_HW_RD_PTR +#define VLC_VB_RD_PTR ((0x0013 << 2) + 0xfe067400) +#define VLC_VB_SW_RD_PTR ((0x0014 << 2) + 0xfe067400) +// Read Only +#define VLC_VB_LEFT ((0x0015 << 2) + 0xfe067400) +// VB FIFO Control +// bit [31:24] vb_full_int_enable_cpu[7:0] +// bit [23:16] vb_full_int_enable_amrisc[7:0] +// -bit 23 Video BUFFER LEFT < 0x400 Bytes +// -bit 22 Video BUFFER LEFT < 0x200 Bytes +// -bit 21 Video BUFFER LEFT < 0x100 Bytes +// -bit 20 Video BUFFER LEFT < 0x80 Bytes +// -bit 19 Video BUFFER LEFT < 0x40 Bytes +// -bit 18 Video BUFFER LEFT < 0x20 Bytes +// -bit 17 vbfifo left < 16 double words (8x64bits) +// -bit 16 vbfifo left < 8 double words (4x64bits) +// bit [15] wr_ptr_int_enable_cpu +// bit [14] wr_ptr_int_enable_amrisc +// bit [13] wr_ptr_int (Read Only, write 1 will clear) +// bit [12] vb_full_int_enable_cpu(Read Only) +// bit [11] vb_full_int_enable_amrisc(Read Only) +// bit [10] reserved +// bit [9] use_vb_hw_rd_ptr +// bit [8] vb_always_ready Set to 1 to ignore vb_level blocking DDR write +// bit [7] vb_ready_for_transfer (Read Only) +// bit [6] data_ready_for_transfer (Read Only) +// bits [5:3] vb_endian Set VB Endian inside DDR memory +// bit [2] vb_write_busy Read Only - indicate DDR write busy +// bit [1] vb_write_en Set to 1 to enable writing data to DDR memory +// bit [0] vb_soft_reset Soft reset +#define VLC_VB_CONTROL ((0x0016 << 2) + 0xfe067400) +// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0 +// bit 30 A_urgent // default : 0 +// bit 29:24 A_brst_num // default : 0x3f +// bit 23:22 reserved +// bit 21:16 A_id // default : 0x20 +// bit 15:0 vb_left_hold // default : 0 +#define VLC_VB_MEM_CTL ((0x0017 << 2) + 0xfe067400) +// vb_wr_ptr address to generate interrupt +#define VLC_VB_INT_PTR ((0x0018 << 2) + 0xfe067400) +// bit[31:12] reserved +// bit[11:0] vlc_wrrsp_count +#define VLC_WRRSP ((0x0019 << 2) + 0xfe067400) +#define VLC_TOTAL_BYTES ((0x001a << 2) + 0xfe067400) +// bit [31:26] reserved +// bit [25] vb_flush +// bit [24] vb_reg_ready +// bit [23:16] vb_buff_left -- Read only +// bit [15:8] vb_buff_wr_point -- RW +// bit [7:0] vb_buff_rd_point -- RW +#define VLC_VB_BUFF ((0x001b << 2) + 0xfe067400) +// bit[31] flush_vlc_pre_buff +// bit[30:27] reserved +// bit[26:24] vb_pre_buff_level +// bit[23:0] vb_pre_buff_data[55:32] +#define VLC_VB_PRE_BUFF_HI ((0x001c << 2) + 0xfe067400) +// bit[31:0] vb_pre_buff_data[31:0] +#define VLC_VB_PRE_BUFF_LOW ((0x001d << 2) + 0xfe067400) +// bit[31] stream_encap_enable // 0x0000(00-03) will be changed to 0x000003(00-03) if enabled +// bit[30:29] stream_encap_delay // delay bytes for encap used +// bit[28:24] stream_buff_point +// bit[23:0] stream_buff_data +#define VLC_STREAM_BUFF ((0x001e << 2) + 0xfe067400) +// bit[31] push_stream_block - Read Only (Will set if vb_buff full) +// bit[30] push_stream_busy - Read Only (busy when output one byte from stream_buf (max 2 clocks for 8 bits push) +// bit[29:28] stream_encap_status - Read Only +// bit[27:21] reserved +// Long Mode : (Amrisc need movilo and mvihi high to set stream_info) +// bit[20:16] push_stream_long_length (0 or 31 : Mid or Short mode) +// bit[15:0] push_stream_data +// Mid Mode : (Amrisc need movi to set stream_info) +// bit[15:12]] push_stream_mid_length (1-12 : mid mode active, 0-short mode, 15 - byte align) +// bit[11:0] push_stream_data +// Short Mode : (Amrisc can use mtspi to push stream directely) +// bit[7:5] push_stream_short_length (0-5 : short length, else - invalid) +// bit[4:0] push_stream_data +#define VLC_PUSH_STREAM ((0x001f << 2) + 0xfe067400) +// bit[15:8] ELEMENT_LENGTH +// bit[7:1] reserved +// bit[0] Write - push start, Read - Push Busy +#define VLC_PUSH_ELEMENT ((0x0020 << 2) + 0xfe067400) +#define VLC_ELEMENT_DATA ((0x0021 << 2) + 0xfe067400) +// bit[9] reset_last_dquant_ne_zero +// bit[8] set_last_dquant_ne_zero +// bit[7] hcmd_intra_use_sw_info +// bit[6] hcmd_use_sw_info +// bit[5] always_use_info_0_cbp_blk +// bit[4] always_update_info_0_cbp_blk +// bit[3] reset_left_mb_wr +// bit[2] reset_top_mb_wr +// bit[1] set_left_mb_wr +// bit[0] set_top_mb_wr +#define VLC_SPECIAL_CTL ((0x0022 << 2) + 0xfe067400) +// bit[28] left_intra +// bit[27:22] left_quant +// bit[21:16] left_quant_c +// bit[12] top_intra +// bit[11:6] top_quant +// bit[5:0] top_quant_c +#define VLC_HCMD_T_L_INFO ((0x0023 << 2) + 0xfe067400) +// bit[12] cur_intra +// bit[11:6] cur_quant +// bit[5:0] cur_quant_c +#define VLC_HCMD_CUR_INFO ((0x0024 << 2) + 0xfe067400) +// bit[13] top_left_info_in_data_mv_cal +// bit[12] only_use_info_0_top_left_in_I +// bit[11] top_left_info_in_data +// bit[10] early_mix_mc_hcmd +// bit[9] update_top_left_mix +// bit[8] p_top_left_mix +// bit[7] mv_cal_mixed_type +// bit[6] mc_hcmd_mixed_type +// bit[5] use_seperate_int_control +// bit[4] hcmd_intra_use_q_info +// bit[3] hcmd_left_use_prev_info +// bit[2] hcmd_use_q_info +// bit[1] use_q_delta_quant +// bit[0] detect_I16_from_I4 +#define VLC_ADV_CONFIG ((0x0025 << 2) + 0xfe067400) +// 31 - use_hcmd_mb_xy_auto +//23:16 - hcmd_max_mb_x +//15:8 - hcmd_mb_y_auto +// 7:0 - hcmd_mb_x_auto +#define VLC_HCMD_MBXY_AUTO ((0x0026 << 2) + 0xfe067400) +// bit[31:0] vlc_int_control_inter -- will be used when use_seperate_int_control is set +#define VLC_INT_CONTROL_INTER ((0x002f << 2) + 0xfe067400) +// -------------------------------------------- +// Picture VLC +// -------------------------------------------- +// (&(int|(~AND_enable))|(|(int&OR_enable))) +// bit[31] OR interrupt Enable Reserved +// bit[30] OR interrupt Enable for mv_busy +// bit[29] OR interrupt Enable for b8_mode_busy +// bit[28] OR interrupt Enable for mb_skip_run_busy +// bit[27] OR interrupt Enable for cbp_busy +// bit[26] OR interrupt Enable for Reserved +// bit[25] OR interrupt Enable for Reserved +// bit[24] OR interrupt Enable for mb_info_busy +// bit[23] AND interrupt Enable Reserved +// bit[22] AND interrupt Enable for mv_busy +// bit[21] AND interrupt Enable for b8_mode_busy +// bit[20] AND interrupt Enable for mb_skip_run_busy +// bit[19] AND interrupt Enable for cbp_busy +// bit[18] AND interrupt Enable for Reserved +// bit[17] AND interrupt Enable for Reserved +// bit[16] AND interrupt Enable for mb_info_busy +// bit[15] OR interrupt Enable Reserved +// bit[14] OR interrupt Enable for mvd +// bit[13] OR interrupt Enable for b8_mode +// bit[12] OR interrupt Enable for mb_skip_run +// bit[11] OR interrupt Enable for cbp_ready +// bit[10] OR interrupt Enable for c_ipred_mode_ready +// bit[9] OR interrupt Enable for ipred_mode_ready +// bit[8] OR interrupt Enable for mb_info_ready +// bit[7] AND interrupt Enable Reserved +// bit[6] AND interrupt Enable for mvd +// bit[5] AND interrupt Enable for b8_mode +// bit[4] AND interrupt Enable for mb_skip_run +// bit[3] AND interrupt Enable for cbp_ready +// bit[2] AND interrupt Enable for c_ipred_mode_ready +// bit[1] AND interrupt Enable for ipred_mode_ready +// bit[0] AND interrupt Enable for mb_info_ready +#define VLC_INT_CONTROL ((0x0030 << 2) + 0xfe067400) +// Bit[31:16] picture_height +// Bit[15:0] picture_width +#define VLC_PIC_SIZE ((0x0031 << 2) + 0xfe067400) +// [31:16] Reserved +// [15:3] pic_width_in_mbs_minus1 +// [2:0] picture_type +#define VLC_PIC_INFO ((0x0032 << 2) + 0xfe067400) +// Bit[31:16] MB_NR +// Bit[15:8] MBY +// Bit[7:0] MBX +#define VLC_PIC_POSITION ((0x0033 << 2) + 0xfe067400) +// Bit[31] MV_busy +// Bit[30:6] Reserved +// Bit[15] Reserved +// Bit[14] vlc_input_MV_busy +// Bit[13] vlc_input_b8_mode_busy +// Bit[12] vlc_input_mb_skip_run_busy +// Bit[11] vlc_input_cbp_busy +// Bit[10] Reserved +// Bit[9] Reserved +// Bit[8] vlc_input_mb_info_busy +// Bit[7] Reserved +// Bit[6] mvd +// Bit[5] b8_mode +// Bit[4] mb_skip_run +// Bit[3] cbp +// Bit[2] c_ipred_mode +// Bit[1] ipred_mode +// Bit[0] mb_info ( mb_type, mb_x, mb_y) +#define VLC_INPUT_STATUS ((0x0034 << 2) + 0xfe067400) +// Bit[31:28] detected_mb_type +// Bit[27:16] mb_y +// Bit[15:4] mb_x +// Bit[3:0] mb_type +#define VLC_MB_INFO ((0x0035 << 2) + 0xfe067400) +// commnad 0 -- no pending +// normal command + 1 is pending command +// +// bit 31:28 -- pending command 7 +// bit 27:24 -- pending command 6 +// bit 23:20 -- pending command 5 +// bit 19:16 -- pending command 4 +// bit 15:12 -- pending command 3 +// bit 11:8 -- pending command 2 +// bit 7:4 -- pending command 1 +// bit 3:0 -- pending command 0 +#define VLC_ENC_PEND_CMD ((0x0036 << 2) + 0xfe067400) +// For I Slice +// Bit[31:16] Reserved +// Bit[15:0] IntraType +#define HENC_TOP_INFO_0 ((0x0037 << 2) + 0xfe067400) +#define HENC_LEFT_INFO_0 ((0x0038 << 2) + 0xfe067400) +// For I Slice +// Bit[31:24] V_nnz +// Bit[23:16] U_nnz +// Bit[15:0] Y_nnz +#define HENC_TOP_INFO_1 ((0x0039 << 2) + 0xfe067400) +#define HENC_LEFT_INFO_1 ((0x003a << 2) + 0xfe067400) +// bit[63:0] ipred_mode +#define VLC_IPRED_MODE_HI ((0x003b << 2) + 0xfe067400) +#define VLC_IPRED_MODE_LO ((0x003c << 2) + 0xfe067400) +// bit[15:8] SE delta quant +// bit[7:0] UE delta quant +#define VLC_DELTA_QP ((0x003d << 2) + 0xfe067400) +// bit[31:16] Reserved +// bit[15:12] Reserved +// bit[11:8] c_ipred_mode +// bit[7:0] cbp +#define VLC_MB_HEADER_INFO ((0x003e << 2) + 0xfe067400) +// bit[31:16] mb_skip_run +// bit[15:0] b8_mode +#define VLC_P_MB_HEADER_INFO ((0x003f << 2) + 0xfe067400) +// bit[31] write_ptr_update +// bit[30] read_ptr_update +// bit[29:20] coeff_buf_level +// bit[19:10] coeff_buf_write_ptr +// bit[9:0] coeff_buf_read_ptr +#define VLC_COEFF_BUF_STATUS ((0x0040 << 2) + 0xfe067400) +// bit[31:10] Reserved +// bit[9:0] read_req_addr +#define VLC_COEFF_RD_REQ ((0x0041 << 2) + 0xfe067400) +// bit[20] - coeff_buf_read_finished +// bit[19] - coeff_first +// bit[18:4] - coeff_level +// bit[3:0] - coeff_run +#define VLC_COEFF ((0x0042 << 2) + 0xfe067400) +// bit[31] - coeff_info_ready +// bit[30:25] - Reserved +// bit[24:15] - block_begin_addr +// bit[14:11] - trailing_one_sign +// bit[10:6] - total_coeff +// bit[5:4] - trailing_ones +// bit[3:0] - total_zeros +#define VLC_COEFF_INFO ((0x0043 << 2) + 0xfe067400) +// bit[31] write_ptr_update +// bit[30] read_ptr_update +// bit[29:25] Reserved +// bit[24:20] dc_buf_level -- 0-16 +// bit[19:15] Reserved +// bit[14:10] dc_buf_write_ptr +// bit[9:5] Reserved +// bit[4:0] dc_buf_read_ptr +#define VLC_DC_BUF_STATUS ((0x0044 << 2) + 0xfe067400) +// bit[31:10] Reserved +// bit[9:4] Reserved +// bit[3:0] read_req_addr +#define VLC_DC_RD_REQ ((0x0045 << 2) + 0xfe067400) +// bit[31:17] - Reserved +// bit[16] - dc_first +// bit[15:1] - dc_level +// bit[0] - dc_type 0 - CDC, 1 - LDC +#define VLC_DC ((0x0046 << 2) + 0xfe067400) +// bit[31] - dc_info_ready +// bit[30:25] - Reserved +// bit[24:20] - Reserved +// bit[19:15] - dc_idx_begin_addr +// bit[14:11] - dc_trailing_one_sign +// bit[10:6] - dc_total_coeff +// bit[5:4] - dc_trailing_ones +// bit[3:0] - dc_total_zeros +#define VLC_DC_INFO ((0x0047 << 2) + 0xfe067400) +// bit[31:4] - Reserved +// bit[3:0] - mv_rw_idx (auto increment when read/write VLC_MV) +#define VLC_MV_INDEX ((0x0048 << 2) + 0xfe067400) +// bit[31:16] - MVY +// bit[15:0] - MVX +#define VLC_MV ((0x0049 << 2) + 0xfe067400) +// bit[31:16] - MVY +// bitp15:0] - MVX +// Write to HENC_TOP_MV_0 will cause previous U->UL, UR->U, and UR write +// Read will read U MV only +#define HENC_TOP_MV_0 ((0x004a << 2) + 0xfe067400) +#define HENC_TOP_MV_1 ((0x004b << 2) + 0xfe067400) +#define HENC_TOP_MV_2 ((0x004c << 2) + 0xfe067400) +#define HENC_TOP_MV_3 ((0x004d << 2) + 0xfe067400) +#define HENC_LEFT_MV_0 ((0x004e << 2) + 0xfe067400) +#define HENC_LEFT_MV_1 ((0x004f << 2) + 0xfe067400) +#define HENC_LEFT_MV_2 ((0x0050 << 2) + 0xfe067400) +#define HENC_LEFT_MV_3 ((0x0051 << 2) + 0xfe067400) +// Bit[31:1] Reserved +// Bit[0] top_left_mv_ready +#define TOP_LEFT_READY ((0x0052 << 2) + 0xfe067400) +// Bit[31:16] Reserved +// Bit[15:0] mb_skip_run +#define MB_SKIP_RUN ((0x0053 << 2) + 0xfe067400) +// Bit[31:16] Reserved +// Bit[15] Reserved +// Bit[14:13] rd_struct // 00 - frame, 10 - top field, 11 - bottom field +// Bit[12:11] wr_struct // 00 - frame, 10 - top field, 11 - bottom field +// Bit[10:5] mv_buff_id +// Bit[4:0] mv_ref +#define VLC_HCMD_CONFIG ((0x0054 << 2) + 0xfe067400) +// Bit[9:0] h264_dblk_info +#define VLC_HCMD_DBLK_INFO ((0x0055 << 2) + 0xfe067400) +// Bit[3:0] vlc_dbg_idx +#define VLC_DBG_IDX ((0x0056 << 2) + 0xfe067400) +// Read Only +#define VLC_DBG_READ ((0x0057 << 2) + 0xfe067400) +// [ 29] RW jpeg_comp2_ac_table_sel. Default 0. +// [ 28] RW jpeg_comp2_dc_table_sel. Default 0. +// [26:25] RW jpeg_comp2_cnt_max. Default 0. +// [ 24] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0. +// [ 21] RW jpeg_comp1_ac_table_sel. Default 0. +// [ 20] RW jpeg_comp1_dc_table_sel. Default 0. +// [18:17] RW jpeg_comp1_cnt_max. Default 0. +// [ 16] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0. +// [ 13] RW jpeg_comp0_ac_table_sel. Default 0. +// [ 12] RW jpeg_comp0_dc_table_sel. Default 0. +// [10: 9] RW jpeg_comp0_cnt_max. Default 0. +// [ 8] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0. +// [ 1] W jpeg_coeff_init. Write 1 to this bit to initialize JPEG run length encoder. +// [ 0] RW jpeg_en. 0=Disable JPEG encoder; 1=Enable JPEG encoder. Default 0. +#define VLC_JPEG_CTRL ((0x0058 << 2) + 0xfe067400) +// [ 13] RW jpeg_coeff_buf_overfl. Write this bit to 1 to clear overfl. +// [ 12] RW jpeg_coeff_buf_undrfl. Write this bit to 1 to clear undrfl. +// [ 11] R jpeg_coeff_buf_full. +// [ 10] R jpeg_coeff_buf_empty. +// [ 8: 0] R jpeg_coeff_buf_level. +#define VLC_JPEG_COEFF_BUF_STAT ((0x0059 << 2) + 0xfe067400) +// [ 16] RW JPEG HUFFMAN table access mode. 0=Write; 1=Read. Default 1. +// [ 8: 0] RW JPEG HUFFMAN table addr. Default 0. +#define VLC_HUFFMAN_ADDR ((0x005a << 2) + 0xfe067400) +// [19: 0] RW JPEG HUFFMAN table data. +#define VLC_HUFFMAN_DATA ((0x005b << 2) + 0xfe067400) +// bit[31:0] enc_mv_bits - including b8_mode and mvd +#define VLC_ENC_MV_BITS ((0x005c << 2) + 0xfe067400) +// bit[31:0] enc_coeff_bits - including cbp, token, trailing_sign, coeff_enc, h264_totzeros, h264_run +#define VLC_ENC_COEFF_BITS ((0x005d << 2) + 0xfe067400) +#define VLC_RESERVED_5E ((0x005e << 2) + 0xfe067400) +#define VLC_RESERVED_5F ((0x005f << 2) + 0xfe067400) +// ---------------------------------------------------------- +// CABAC +// ---------------------------------------------------------- +// [15] h264_biari_init +// [14] h264_cabac_init +// [13:12] reserved +// [11:10] picture_ty +// [9:8] cabac_init_idc // should be 0 for I_SLICE +// [7] reserved +// [6] cabac_en +// [5:0] slice_quant +#define VLC_SLICE_QP ((0x0060 << 2) + 0xfe067400) +// For save mvd[12:0] {mvd_y[6:0], mvd_x[5:0]} +#define HENC_TOP_INFO_2 ((0x0061 << 2) + 0xfe067400) +#define HENC_LEFT_INFO_2 ((0x0062 << 2) + 0xfe067400) +#define HENC_TOP_INFO_3 ((0x0063 << 2) + 0xfe067400) +#define HENC_LEFT_INFO_3 ((0x0064 << 2) + 0xfe067400) +// +// Closing file: vlc_regs.h +// +//------------------------------------------------------------------------------ +// ----------------------------------------------- +// `define DOS_HCODEC_IQIDCT_CBUS_BASE 8'h0e +// ----------------------------------------------- +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// QDCT module level register offset +//------------------------------------------------------------------------------ +// `define DOS_HCODEC_QDCT_CBUS_BASE 8'h0f +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe067c00 +// ----------------------------------------------- +// +// Reading file: qdct_regs.h +// +//======================================================================== +// QDCT module level register offset +//======================================================================== +// ----------------------------------------------- +// `define DOS_HCODEC_QDCT_CBUS_BASE 8'h0f +// ----------------------------------------------- +// bit[31:28] - mb_info_state +#define QDCT_STATUS_CTRL ((0x0000 << 2) + 0xfe067c00) +// bit[18] - enable_free_clk_sad_top +// bit[17] - enable_free_clk_ie_top +// bit[16] - enable_free_clk_ie_sub +// bit[15] - enable_free_clk_mc_out +// bit[14] - enable_free_clk_i_pred_top +// bit[13] - enable_free_clk_idct_top +// bit[12] - enable_free_clk_iq_top +// bit[11] - enable_free_clk_q_top +// bit[10] - enable_free_clk_dc_buff_8 +// bit[9] - enable_free_clk_dct_top +// bit[8] - enable_free_clk_mb_info +// bit[7] - enable_free_clk_mb_buff +// bit[6] - enable_free_clk_reg +// bit[5] - ignore_1_include_2nd_half_c +// bit[4] - ignore_1_include_2nd_half +// bit[3] - ignore_t_p8x8 +// bit[2] - not_ignore_dc +// bit[1] - ignore_small_lac_intra +// bit[0] - disable_fast_zero_block +#define QDCT_CONFIG ((0x0001 << 2) + 0xfe067c00) +// bit[31] - ignore_lac_coeff_en +// bit[30:26] - ignore_lac_coeff_else +// bit[25:21] - ignore_lac_coeff_2 +// bit[20:16] - ignore_lac_coeff_1 +// bit[15] - ignore_cac_coeff_en +// bit[14:10] - ignore_cac_coeff_else +// bit[9:5] - ignore_cac_coeff_2 +// bit[4:0] - ignore_cac_coeff_1 +#define IGNORE_CONFIG ((0x0002 << 2) + 0xfe067c00) +// bit[31] - ignore_t_lac_coeff_en +// bit[30:26] - ignore_t_lac_coeff_else +// bit[25:21] - ignore_t_lac_coeff_2 +// bit[20:16] - ignore_t_lac_coeff_1 +// bit[15] - ignore_cdc_coeff_en +// bit[14] - ignore_t_lac_coeff_else_le_3 +// bit[13] - ignore_t_lac_coeff_else_le_4 +// bit[12] - ignore_cdc_only_when_empty_cac_inter +// bit[11] - ignore_cdc_only_when_one_empty_inter +// bit[10:9] - ignore_cdc_range_max_inter // 0-0, 1-1, 2,-2, 3-3 +// bit[8:7] - ignore_cdc_abs_max_inter // 0-1, 1-2, 2,-3, 3-4 +// bit[6] - reserved +// bit[5] - ignore_cdc_only_when_empty_cac_intra +// bit[4] - ignore_cdc_only_when_one_empty_intra +// bit[3:2] - ignore_cdc_range_max_intra // 0-0, 1-1, 2,-2, 3-3 +// bit[1:0] - ignore_cdc_abs_max_intra // 0-1, 1-2, 2,-3, 3-4 +#define IGNORE_CONFIG_2 ((0x0003 << 2) + 0xfe067c00) +// -------------------------------------------- +// MB DATA DDR Interface +// -------------------------------------------- +#define QDCT_MB_START_PTR ((0x0010 << 2) + 0xfe067c00) +#define QDCT_MB_END_PTR ((0x0011 << 2) + 0xfe067c00) +#define QDCT_MB_WR_PTR ((0x0012 << 2) + 0xfe067c00) +#define QDCT_MB_RD_PTR ((0x0013 << 2) + 0xfe067c00) +#define QDCT_MB_LEVEL ((0x0014 << 2) + 0xfe067c00) +// bit [31] disable_mbxy_ie_save +// bit [30] no_wait_after_q_cdc +// bit [29] ie_start_int_enable +// bit [28] ignore_t_p8x8 +// bit [27] zero_mc_out_null_non_skipped_mb +// bit [26] no_mc_out_null_non_skipped_mb +// bit [25] mc_out_even_skipped_mb +// bit [24] mc_out_wait_cbp_ready +// bit [23] mc_out_wait_mb_type_ready +// bit [22] i_pred_int_enable +// bit [21] intra_sat8_enable +// bit [20] ie_sub_enable +// bit [19] i_pred_enable +// bit [18] iq_enable +// bit [17] idct_enable +// bit [16] no_zero_coeff_mb +// bit [15] add_zero_coeff_block +// bit [14] mb_pause_enable +// bit [13] q_enable +// bit [12] dct_enable +// bit [11] ignore_magic_word +// bit [10] mb_info_en +// bit [9] mb_info_soft_reset +// bit [8] mb_always_ready Set to 1 to ignore mb_level blocking DDR read +// bit [7] mb_ready_for_transfer (Read Only) +// bit [6] data_ready_for_transfer (Read Only) +// bits [5:3] mb_endian Set MB Endian inside DDR memory +// bit [2] mb_read_busy Read Only - indicate DDR read busy +// bit [1] mb_read_en Set to 1 to enable reading data from DDR memory +// bit [0] mb_soft_reset Soft reset +#define QDCT_MB_CONTROL ((0x0015 << 2) + 0xfe067c00) +// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0 +// bit 30 A_urgent // default : 0 +// bit 29:24 A_brst_num // default : 0x3f +// bit 23 reserved +// bit 22 read_till_zero +// bit 21:16 A_id // default : 0x21 +// bit 15:0 mb_level_hold // default : 0 +#define QDCT_MB_MEM_CTL ((0x0016 << 2) + 0xfe067c00) +// bit [31:24] reserved +// bit [23:16] vb_buff_level -- Read only +// bit [15:8] vb_buff_wr_point -- RW +// bit [7:0] vb_buff_rd_point -- RW +#define QDCT_MB_BUFF ((0x0017 << 2) + 0xfe067c00) +// bit [31:0] mb infor data begin magic word - default : 0xa55aaa55 +#define QDCT_MB_MAGIC_WORD ((0x0018 << 2) + 0xfe067c00) +// Read Only Register +// bit[19] dct_ready_1 +// bit[18] dct_ready_0 +// bit[17] dct_rd_idx +// bit[16] dct_wr_idx +// bit[15] dct_srdy +// bit[14] dct_rrdy +// bit[13] Reserved +// bit[12:8] dct_block_number +// bit[7:4] dct_rw_addr +// bit[3:0] dct_status +#define QDCT_DCT_STATUS ((0x0019 << 2) + 0xfe067c00) +// bit[24:23] vlc_quant_count +// bit[22:16] vlc_delta_quant_data +// bit[15:10] vlc_quant_data +// bit[9:4] vlc_prev_quant_data +// bit[3:0] q_status +#define QDCT_Q_STATUS ((0x001a << 2) + 0xfe067c00) +// bit[31:3] Reserved +// bit[2:0] picture_type +#define QDCT_PIC_INFO ((0x001b << 2) + 0xfe067c00) +// bit[31:28] Reserved +// bit[27:22] I_pic_quant_c +// bit[21:16] I_pic_quant +// bit[15] reserved +// bit[14:12] quant_rem_c +// bit[11:8] quant_per_c +// bit[7] reserved +// bit[6:4] quant_rem +// bit[3:0] quant_per +#define QDCT_Q_QUANT_I ((0x001c << 2) + 0xfe067c00) +// bit[31:28] Reserved +// bit[27:22] P_pic_quant_c +// bit[21:16] P_pic_quant +// bit[15] reserved +// bit[14:12] quant_rem_c +// bit[11:8] quant_per_c +// bit[7] reserved +// bit[6:4] quant_rem +// bit[3:0] quant_per +#define QDCT_Q_QUANT_P ((0x001d << 2) + 0xfe067c00) +// bit[31] mb_info_pause +// bit[30:16] pause_mby +// bit[15:0] pause_mbx +#define QDCT_MB_PAUSE_CTL ((0x001e << 2) + 0xfe067c00) +// bit[31] top_control_ready_i_pred +// bit[30:28]top_dma_status +// bit[27] top_control_ready_ie +// bit[26:24]Reserved +// bit[23] ul_mb +// bit[22] right_mb +// bit[21] top_mb +// bit[20] left_mb +// bit[19:8] mb_x +// bit[7:6] i_pred_ref_idx_L +// bit[5:4] i_pred_ref_idx_UL +// bit[3:2] i_pred_ref_idx_U +// bit[1:0] i_pred_ref_idx_UR +#define QDCT_TOP_CONTROL ((0x001f << 2) + 0xfe067c00) +// bit[31:0] top_base_addr - DDR Memory start address for save top Pixel +#define QDCT_TOP_BASE_MEM ((0x0020 << 2) + 0xfe067c00) +// bit 15:13 Reserved +// bit 12 A_urgent // default : 0 +// bit 11:6 A_brst_num // default : 0x3f +// bit 5:0 A_id // default : 0x22 +#define QDCT_TOP_MEM_CTL ((0x0021 << 2) + 0xfe067c00) +// bit [11:0] top_wrrsp_count +#define QDCT_TOP_WRRSP ((0x0022 << 2) + 0xfe067c00) +// Bit[3:0] qdct_dbg_idx +#define QDCT_DBG_IDX ((0x0023 << 2) + 0xfe067c00) +// Read Only +#define QDCT_DBG_READ ((0x0024 << 2) + 0xfe067c00) +// [19:18] RW jdct_inflow_ctrl. JPEG DCT input flow control. Default 0. +// 0=No halt; +// 1=DCT halts request at end of each 8x8 block; +// 2=DCT halts request at end of each MCU. +// [17:16] RW jpeg_coeff_last_sel. Default 0. +// Select at which point to finish processing, give update to AmRISC so it can control the next step. +// 0=Mark last coeff at the end of an 8x8 block; +// 1=Mark at the end of an MCU; +// 2=Mark at the end of a scan. +// [ 15] RW jpeg_quant_sel_comp2. 0=Comp2 select Quantization table 0; 1=Select table 1. Default 0. +// [ 14] RW jpeg_v_factor_comp2. Component 2's vertical sampling factor. Default 0. +// [ 13] RW jpeg_h_factor_comp2. Component 2's horizontal sampling factor. Default 0. +// [ 12] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0. +// [ 11] RW jpeg_quant_sel_comp1. 0=Comp1 select Quantization table 0; 1=Select table 1. Default 0. +// [ 10] RW jpeg_v_factor_comp1. Component 1's vertical sampling factor. Default 0. +// [ 9] RW jpeg_h_factor_comp1. Component 1's horizontal sampling factor. Default 0. +// [ 8] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0. +// [ 7] RW jpeg_quant_sel_comp0. 0=Comp0 select Quantization table 0; 1=Select table 1. Default 0. +// [ 6] RW jpeg_v_factor_comp0. Component 0's vertical sampling factor. Default 0. +// [ 5] RW jpeg_h_factor_comp0. Component 0's horizontal sampling factor. Default 0. +// [ 4] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0. +// [ 3: 1] RW jdct_intr_sel. JPEG DCT interrupt select. Default 0. +// 0=Disable intr; +// 1=Intr at end of each 8x8 block of DCT input; +// 2=Intr at end of each MCU of DCT input; +// 3=Intr at end of a scan of DCT input; +// 4=Intr at end of each 8x8 block of DCT output; +// 5=Intr at end of each MCU of DCT output; +// 6=Intr at end of a scan of DCT output. +// [ 0] RW jpeg_en. 0=Disable JPEG QDCT; 1=Enable JPEG QDCT. Default 0. +#define QDCT_JPEG_CTRL ((0x0025 << 2) + 0xfe067c00) +// [29:16] RW jpeg_x_end. Picture X end. Default 0. +// [13: 0] RW jpeg_x_start. Picture X start. Default 0. +#define QDCT_JPEG_X_START_END ((0x0026 << 2) + 0xfe067c00) +// [29:16] RW jpeg_y_end. Picture Y end. Default 0. +// [13: 0] RW jpeg_y_start. Picture Y start. Default 0. +#define QDCT_JPEG_Y_START_END ((0x0027 << 2) + 0xfe067c00) +// [ 8] RW JPEG QUANT table access mode. 0=Write; 1=Read. Default 1. +// [ 5: 0] RW JPEG QUANT table addr. Default 0. +#define QDCT_JPEG_QUANT_ADDR ((0x0028 << 2) + 0xfe067c00) +// [31: 0] RW JPEG QUANT table data. +#define QDCT_JPEG_QUANT_DATA ((0x0029 << 2) + 0xfe067c00) +// [ 1] W resume_jdct. +// Write 1 to this bit will resume JPEG input engine when previously +// it is halted by QDCT_JPEG_CTRL.jdct_inflow_ctrl. +// [ 0] W jpeg_sof. +// Write 1 to this bit will start JPEG input engine. +#define QDCT_JPEG_SOF_RESUME ((0x002a << 2) + 0xfe067c00) +// [31:30] R dct_st. jdct_ctrl state. 0=IDLE; 1=WAIT; 2=DCT_REQ. +// [29:28] R mfdin_comp. Current component at pixel request to MFDIN. +// [27:14] R mfdin_y. Current Y at pixel request to MFDIN. +// [13: 0] R mfdin_x. Current X at pixel request to MFDIN. +#define QDCT_JPEG_DCT_STATUS0 ((0x002b << 2) + 0xfe067c00) +// [15:12] R JPEG Quant read MEM select. +// [11: 8] R JPEG DCT2 write MEM select. +// [ 7: 4] R JPEG DCT2 read MEM select. +// [ 3: 0] R JPEG DCT1 write MEM select. +#define QDCT_JPEG_DCT_STATUS1 ((0x002c << 2) + 0xfe067c00) +// [28:16] RW jdct_coeff1. Default 13'h1D90; // 7568 = 4096 * sqrt(2) * (cos(Pi/8) + sin(Pi/8)) // 7569 +// [12: 0] RW jdct_coeff0. Default 13'h16A1; // 5793 = 4096 * sqrt(2) +#define QDCT_JPEG_DCT_COEFF01 ((0x002d << 2) + 0xfe067c00) +// [28:16] RW jdct_coeff3. Default 13'h0C3F; // 3135 = 4096 * sqrt(2) * (cos(Pi/8) - sin(Pi/8)) +// [12: 0] RW jdct_coeff2. Default 13'h08A9; // 2217 = 4096 * sqrt(2) * sin(Pi/8) // 2215 +#define QDCT_JPEG_DCT_COEFF23 ((0x002e << 2) + 0xfe067c00) +// [28:16] RW jdct_coeff5. Default 13'h046A; // 1130 = 4096 * (cos(3Pi/16) - sin(3Pi/16)) +// [12: 0] RW jdct_coeff4. Default 13'h1631; // 5681 = 4096 * (cos(3Pi/16) + sin(3Pi/16)) // 5682 +#define QDCT_JPEG_DCT_COEFF45 ((0x002f << 2) + 0xfe067c00) +// [28:16] RW jdct_coeff7. Default 13'h0C92; // 3218 = 4096 * (cos(Pi/16) - sin(Pi/16)) +// [12: 0] RW jdct_coeff6. Default 13'h12D0; // 4816 = 4096 * (cos(Pi/16) + sin(Pi/16)) +#define QDCT_JPEG_DCT_COEFF67 ((0x0030 << 2) + 0xfe067c00) +// [28:16] RW jdct_coeff9. Default 13'h0FB1; // 4017 = 4096 * cos(Pi/16) +// [12: 0] RW jdct_coeff8. Default 13'h0D4E; // 3406 = 4096 * cos(3Pi/16) +#define QDCT_JPEG_DCT_COEFF89 ((0x0031 << 2) + 0xfe067c00) +#define QDCT_I_PRED_REF_WR_IDX ((0x0032 << 2) + 0xfe067c00) +#define QDCT_I_PRED_REF_WR_DATA ((0x0033 << 2) + 0xfe067c00) +// bit[29] mb_info_latch_no_I16_pred_mode +// bit[28] ie_dma_mbxy_use_i_pred +// bit[27] ie_dma_read_write_use_ip_idx +// bit[26] ie_start_use_top_dma_count +// bit[25] i_pred_top_dma_rd_mbbot +// bit[24] i_pred_top_dma_wr_disable +// bit[23] i_pred_mix +// bit[22] me_ab_rd_when_intra_in_p +// bit[21] force_mb_skip_run_when_intra +// bit[20] mc_out_mixed_type +// bit[19] ie_start_when_quant_not_full +// bit[18] mb_info_state_mix +// bit[17] mb_type_use_mix_result +// bit[16] me_cb_ie_read_enable +// bit[15] ie_cur_data_from_me +// bit[14] rem_per_use_table +// bit[13] q_latch_int_enable +// bit[12] q_use_table +// bit[11] q_start_wait +// bit[10] LUMA_16_LEFT_use_cur +// bit[9] DC_16_LEFT_SUM_use_cur +// bit[8] c_ref_ie_sel_cur +// bit[7] c_ipred_perfect_mode +// bit[6] ref_ie_ul_sel 0-old, 1-use next_set +// bit[5] mb_type_use_ie_result +// bit[4] detect_I16_from_I4 +// bit[3] ie_not_wait_ref_busy +// bit[2] ie_I16_enable +// bit[1:0] ie_done_sel (0, 1, 2, -1) +#define QDCT_ADV_CONFIG ((0x0034 << 2) + 0xfe067c00) +// bit [31:16] I16x16_weight +// bit [15:0] I4x4_weight +#define IE_WEIGHT ((0x0035 << 2) + 0xfe067c00) +// bit [31] reserved +// bit [30] q_I16MB +// bit [29] reserved +// bit [28] reserved +// bit [27:23] quant_table_addr I4MB:[0,7], I16MB:[8:15], INTER:[16:23], Reserved:[24:31] +// bit [22] quant_table_addr_update(when notupdate_rem_per) (read is arb_result : q_intra) +// bit [21:19] quant_rem_c +// bit [18:16] quant_rem_y +// bit [15:12] quant_per_c +// bit [11:8] quant_per_y +// bit [7:2] quant +// bit [1] update_rem_per +// bit [0] clear_wait_status +#define Q_QUANT_CONTROL ((0x0036 << 2) + 0xfe067c00) +#define MBBOT_EVEN_ADDR ((0x0037 << 2) + 0xfe067c00) +#define MBBOT_ODD_ADDR ((0x0038 << 2) + 0xfe067c00) +// bit [29:24] quant_table_data_3 +// bit [21:16] quant_table_data_2 +// bit [13:8] quant_table_data_1 +// bit [5:0] quant_table_data_0 +#define QUANT_TABLE_DATA ((0x0039 << 2) + 0xfe067c00) +// bit [31:16] ie_sad_offset_I16 +// bit [15:0] ie_sad_offset_I4 +#define SAD_CONTROL_0 ((0x003a << 2) + 0xfe067c00) +// bit [31] sad_soft_reset +// bit [30:27] reserved +// bit [26:24] ie_sad_shift_I16 +// bit [22:20] ie_sad_shift_I4 +// bit [18:16] me_sad_shift_INTER +// bit [15:0] me_sad_offset_INTER +#define SAD_CONTROL_1 ((0x003b << 2) + 0xfe067c00) +// bit [31] vlc_quant_rd_ptr +// bit [30] vlc_quant_rd_ptr_update +// bit [29] vlc_quant_wr_ptr +// bit [28] vlc_quant_wr_ptr_update +// bit [27:26] reserved +// bit [25:19] vlc_delta_quant_1 +// bit [18:13] vlc_quant_1 +// bit [12:6] vlc_delta_quant_0 +// bit [5:0] vlc_quant_0 +#define QDCT_VLC_QUANT_CTL_0 ((0x003c << 2) + 0xfe067c00) +// bit [31:30] me_sad_rd_idx +// bit [29] me_sad_rd_idx_update +// bit [28:27] me_sad_wr_idx +// bit [26] me_sad_wr_idx_update +// bit [25:24] ie_sad_rd_idx +// bit [23] ie_sad_rd_idx_update +// bit [22:21] ie_sad_wr_idx +// bit [20] ie_sad_wr_idx_update +// bit [19:12] Reserved +// bit [11:6] vlc_max_delta_q_neg +// bit [5:0] vlc_max_delta_q_pos +#define QDCT_VLC_QUANT_CTL_1 ((0x003d << 2) + 0xfe067c00) +// bit[4] jdct_int +// bit[3] quant_latch +// bit[2] me_done +// bit[1] ie_start +// bit[0] i_pred_start +#define QDCT_INT_STATUS ((0x003e << 2) + 0xfe067c00) +// bit[3] mix_i_pred_wait_left_en +// bit[2:0] mc_pending_mb_count +#define QDCT_MIX_I_PRED_STATUS ((0x003f << 2) + 0xfe067c00) +// IE/ME share same cbus_base as QDCT +// +// bit[31] active_ur_block +// bit[30] active_ul_block +// bit[21] disable_HENC_V_PRED_16 +// bit[20] disable_HENC_H_PRED_16 +// bit[19] disable_HENC_DC_PRED_16 +// bit[18] disable_HENC_HENC_HOR_UP_PRED +// bit[17] disable_HENC_VERT_LEFT_PRED +// bit[16] disable_HENC_HENC_HOR_DOWN_PRED +// bit[15] disable_HENC_VERT_RIGHT_PRED +// bit[14] disable_HENC_DIAG_DOWN_RIGHT_PRED +// bit[13] disable_HENC_DIAG_DOWN_LEFT_PRED +// bit[12] disable_HENC_DC_PRED +// bit[11] disable_HENC_HOR_PRED +// bit[10] disable_HENC_VERT_PRED +// bit[9] ie_c_wait_ie_pause +// bit[8:4] max_ie_result_buff_count +// bit[3] ie_wait_for_ie_result // use for (max_ie_result_buff_count == 0) to wait every block +// bit[2] reserved +// bit[1] ie_enable +// bit[0] ie_soft_reset +#define IE_CONTROL ((0x0040 << 2) + 0xfe067c00) +// bit[31:12] Reserved +// bit[11:0] mb_y +#define IE_MB_POSITION ((0x0041 << 2) + 0xfe067c00) +// bit[31:16] me_skip_run +// bit[15:8] reserved +// bit [7:4] me_b8_mode +// bit [3:0] ie_me_mb_type +#define IE_ME_MB_INFO ((0x0042 << 2) + 0xfe067c00) +// bit[3] ie_result_buff_enable +// bit[2] ie_result_buff_soft_reset +// bit[1] sad_enable +// bit[0] ie_sad_soft_reset +#define SAD_CONTROL ((0x0043 << 2) + 0xfe067c00) +// bit[31:16] - ie_result_buff_count - read only +// bit[14:12] -current_ie_result (pred_mode) - read only +// bit[11] top_control_data_buff_wr_ptr - rd/wr +// bit[10] top_control_data_buff_rd_ptr - rd/wr +// bit[9:5] ie_result_buff_wr_ptr - rd/wr +// bit[4:0] ie_result_buff_rd_ptr - rd/wr +#define IE_RESULT_BUFFER ((0x0044 << 2) + 0xfe067c00) +// bit[63:0] ie_i4_pred_mode +#define IE_I4_PRED_MODE_HI ((0x0045 << 2) + 0xfe067c00) +#define IE_I4_PRED_MODE_LO ((0x0046 << 2) + 0xfe067c00) +// bit [31:9] reserved +// bit [8:4] i_pred_block_number +// bit [3:0] ie_c_pred_mode +#define IE_C_PRED_MODE ((0x0047 << 2) + 0xfe067c00) +// 31:16 - Left, 0-select ie_pixel, 1-select mc_data_out +// 15:0 - Top, 0-select ie_pixel, 1-select mc_data_out +#define IE_CUR_REF_SEL ((0x0048 << 2) + 0xfe067c00) +// bit[31] enable_f_skip_1_step_3 +// bit[30] enable_f_skip_1_step_2 +// bit[29] enable_f_skip_1_step_1 +// bit[28] step_3_enable +// bit[27] step_2_sub_pixel +// bit[26] always_f_skip_step_3 +// bit[25] always_f_skip_step_2 +// bit[24] always_f_skip_step_1 +// bit[23] half_pixel_only +// bit[22:13] reserved +// bit[12] adv_mv_enable +// bit[11] sad_short_valid +// bit[10:9] mv_flexable_ctl 00:0x40, 01:0x80, 10:0xc0, 11 : 0x100 +// bit[8] no_md_ab_rd +// bit[7] use_dct_state +// bit[6] enable_free_clk_me_ctl +// bit[5] enable_free_clk_me_ab +// bit[4] enable_free_clk_me_cb +// bit[3] reserved +// bit[2] me_done_int_enable +// bit[1] me_enable +// bit[0] me_soft_reset +#define ME_CONTROL ((0x0049 << 2) + 0xfe067c00) +// bit[31:28] Reserved +// bit[27:16] me_start_mby +// bit[15:12] Reserved +// bit[11:0] me_start_mbx +#define ME_START_POSITION ((0x004a << 2) + 0xfe067c00) +// bit [31:28] me_status - Read only +// bit [27:24] me_cb_status // current buffer +// bit [23:20] me_ab_status // anc buffer +// bit [19] Reserved +// bit [18:16] me_ab_wr_ptr // read only +// bit [15:4] me_last_mbx +// bit [3:1] me_ab_rd_ptr // read only +// bit [0] me_action +#define ME_STATUS ((0x004b << 2) + 0xfe067c00) +// all Read-only +// bit [31:28] Reserved +// bit [27:16] me_ab_mbx +// bit [15:14] me_cb_wr_ptr +// bit [13:12] me_cb_rd_ptr +// bit [11:0] me_cb_mbx +#define ME_DEBUG ((0x004c << 2) + 0xfe067c00) +// bit[29:24] step_3_skip_line +// bit[23:18] step_2_skip_line +// bit[17:12] step_1_skip_line +// bit[11:6] step_0_skip_line +// bit[5:0] read_skip_line +#define ME_SKIP_LINE ((0x004d << 2) + 0xfe067c00) +// bit 15:13 Reserved +// bit 12 A_urgent // default : 0 +// bit 11:6 A_brst_num // default : 0x3f +// bit 5:0 A_id // default : 0x23 +#define ME_AB_MEM_CTL ((0x004e << 2) + 0xfe067c00) +// bit[31:24] anc_pic_canvas +// bit[23:12] max_me_mby_num +// bit[11:0] max_me_mbx_num +#define ME_PIC_INFO ((0x004f << 2) + 0xfe067c00) +// bit [23:12] me_sad_enough_1 +// bit [11:0] me_sad_enough_0 +#define ME_SAD_ENOUGH_01 ((0x0050 << 2) + 0xfe067c00) +// bit [25:12] adv_mv_8x8_enough +// bit [11:0] me_sad_enough_2 +#define ME_SAD_ENOUGH_23 ((0x0051 << 2) + 0xfe067c00) +// bit [21:10] me_step0_big_sad +// bit [9:5] me_step0_close_mv_y +// bit [4:0] me_step0_close_mv_x +#define ME_STEP0_CLOSE_MV ((0x0052 << 2) + 0xfe067c00) +// bit[31:24] force_skip_sad_3 +// bit[23:16] force_skip_sad_2 +// bit[15:08] force_skip_sad_1 +// bit[07:00] force_skip_sad_0 +#define ME_F_SKIP_SAD ((0x0053 << 2) + 0xfe067c00) +// bit[31:24] force_skip_weight_3 +// bit[23:16] force_skip_weight_2 +// bit[15:08] force_skip_weight_1 +// bit[07:00] force_skip_weight_0 +#define ME_F_SKIP_WEIGHT ((0x0054 << 2) + 0xfe067c00) +// Merge when ( +// (flex & me_merge_flex_en) | +// (big_sad & me_merge_sad_en)| +// ((~me_merge_flex_en)&(~me_merge_sad_en)) +// ) & +// ( small_mv_diff |(~me_merge_small_mv_en)) +// & (me_merge_flex_en | me_merge_sad_en | me_merge_small_mv_en) +// bit[31] me_merge_mv_en_16 +// bit[30] me_merge_small_mv_en_16 +// bit[29] me_merge_flex_en_16 +// bit[28] me_merge_sad_en_16 +// bit[27] me_merge_mv_en_8 +// bit[26] me_merge_small_mv_en_8 +// bit[25] me_merge_flex_en_8 +// bit[24] me_merge_sad_en_8 +// bit[23:18] me_merge_mv_diff_16 +// bit[17:12] me_merge_mv_diff_8 +// bit[11:0] me_merge_min_sad +#define ME_MV_MERGE_CTL ((0x0055 << 2) + 0xfe067c00) +// bit[31:24] mv_step_weight_1 +// bit[23:16] mv_pre_weight_1 +// bit [15:0] mv_step_weight_0 +// bit[7:0] mv_pre_weight_0 +#define ME_MV_WEIGHT_01 ((0x0056 << 2) + 0xfe067c00) +// bit[31:24] mv_step_weight_3 (mv_step_weight_1_2nd) +// bit[23:16] mv_pre_weight_3 (mv_pre_weight_1_2nd) +// bit[15:8] mv_step_weight_2 +// bit[7:0] mv_pre_weight_2 +#define ME_MV_WEIGHT_23 ((0x0057 << 2) + 0xfe067c00) +// bit[31:24] me_sad_range_inc_3 +// bit[23:16] me_sad_range_inc_2 +// bit[15:8] me_sad_range_inc_1 +// bit[7:0] me_sad_range_inc_0 +#define ME_SAD_RANGE_INC ((0x0058 << 2) + 0xfe067c00) +// bit[31:19] reserved +// bit[18] sub_relative_any_1_en +// bit[17] sub_relative_any_2_en +// bit[16] sub_relative_any_3_en +// bit[15] sub_relative_any_4_en +// bit[14] sub_relative_any_h_en +// bit[13] sub_make_non_flex_fix +// bit[12] sub_make_big_non_flex_fix +// bit[11:8] sub_normal_mv_diff_16 +// bit[7:4] sub_normal_mv_diff_8 +// bit[3:2] Reserved +// bit[1] sub_merge_enable_16 +// bit[0] sub_merge_enable_8 +#define ME_SUB_MERGE_CTL ((0x0059 << 2) + 0xfe067c00) +// bit[31:28] sub_ref_mv_diff_near +// bit[27:24] sub_ref_mv_diff_near_flex +// bit[23:20] sub_ref_mv_diff +// bit[19:16] sub_ref_mv_diff_flex +// bit[15:8] sub_ref_mv_near_weight +// bit[7:0] sub_ref_mv_weight +#define ME_SUB_REF_MV_CTL ((0x005a << 2) + 0xfe067c00) +// bit[31:24] sub_weight_max_sad +// bit[23:16] sub_any_range_sad +// bit[15:8] sub_any_min_sad +// bit[7:0] sub_any_max_sad +#define ME_SUB_ANY_WEIGHT_SAD ((0x005b << 2) + 0xfe067c00) +// bit[31:24] sub_fix_sad +// bit[23:16] sub_fix_diff_sad +// bit[15:8] sub_sad_flex_adj +// bit[7:0] sub_big_non_flex_fix_sad +#define ME_SUB_FIX_SAD ((0x005c << 2) + 0xfe067c00) +// bit[31:24] sub_fix_min_sad +// bit[23:16] sub_fix_min_diff_sad +// bit[15:8] sub_fix_min_sad_2 +// bit[7:0] sub_fix_min_diff_sad_2 +#define ME_SUB_FIX_MIN_SAD ((0x005d << 2) + 0xfe067c00) +// bit[31:24] sub_snap_to_ref_max_sad +// bit[23] sub_snap_to_ref_non_flex +// bit[22:16] sub_snap_to_ref_mv_diff +// bit[15:4] sub_glitch_mv_sad +// bit[3:0] sub_glitch_mv_diff +#define ME_SUB_SNAP_GLITCH ((0x005e << 2) + 0xfe067c00) +// bit[31:20] sad_act_limit +// bit[19:8] s_a_any_sad +// bit[7] Reserved +// bit[6:5] sub_merge_method +// bit[4] use_sub_act_result +// bit[3] s_a_rnd +// bit[2] Reserved +// bit[1] sub_act_en_16 +// bit[0] sub_act_en +#define ME_SUB_ACT_CTL ((0x005f << 2) + 0xfe067c00) +// bit[31:16] reserved +// bit[15:0] me_weight +#define ME_WEIGHT ((0x0060 << 2) + 0xfe067c00) +// bit[31] ready_update +// bit[30] data_update +// bit[29:28] reserved +// bit[27:22] me_quant_0 +// bit[21] ie_sad_ready_0 +// bit[20:18] Reserved +// bit[17:16] me_sad_mv_type_0 +// bit[15:0] me_sad_0 +#define ME_SAD_0 ((0x0061 << 2) + 0xfe067c00) +// bit[31] ready_update +// bit[30] data_update +// bit[29:28] reserved +// bit[27:22] me_quant_1 +// bit[21] me_sad_ready_1 +// bit[20:18] Reserved +// bit[17:16] me_sad_mv_type_1 +// bit[15:0] me_sad_1 +#define ME_SAD_1 ((0x0062 << 2) + 0xfe067c00) +// bit[31] ready_update +// bit[30] data_update +// bit[29:28] reserved +// bit[27:22] me_quant_2 +// bit[21] me_sad_ready_2 +// bit[20:18] Reserved +// bit[17:16] me_sad_mv_type_2 +// bit[15:0] me_sad_2 +#define ME_SAD_2 ((0x0063 << 2) + 0xfe067c00) +// bit[31] ready_update +// bit[30] data_update +// bit[29:28] reserved +// bit[27:22] me_quant_3 +// bit[21] me_sad_ready_3 +// bit[20:18] Reserved +// bit[17:16] me_sad_mv_type_3 +// bit[15:0] me_sad_3 +#define ME_SAD_3 ((0x0064 << 2) + 0xfe067c00) +// bit[31] ready_update +// bit[30] data_update +// bit[29:28] reserved +// bit[27:22] ie_quant_0 +// bit[21] ie_sad_ready_0 +// bit[20] I4/I16 (0-I4MB, 1-I16MB) +// bit[19:0] ie_sad_0 +#define IE_SAD_0 ((0x0065 << 2) + 0xfe067c00) +// bit[31] ready_update +// bit[30] data_update +// bit[29:28] reserved +// bit[27:22] ie_quant_1 +// bit[21] ie_sad_ready_1 +// bit[20] I4/I16 (0-I4MB, 1-I16MB) +// bit[19:0] ie_sad_1 +#define IE_SAD_1 ((0x0066 << 2) + 0xfe067c00) +// bit[31] ready_update +// bit[30] data_update +// bit[29:28] reserved +// bit[27:22] ie_quant_2 +// bit[21] ie_sad_ready_2 +// bit[20] I4/I16 (0-I4MB, 1-I16MB) +// bit[19:0] ie_sad_2 +#define IE_SAD_2 ((0x0067 << 2) + 0xfe067c00) +// bit[31] ready_update +// bit[30] data_update +// bit[29:28] reserved +// bit[27:22] ie_quant_3 +// bit[21] ie_sad_ready_3 +// bit[20] I4/I16 (0-I4MB, 1-I16MB) +// bit[19:0] ie_sad_3 +#define IE_SAD_3 ((0x0068 << 2) + 0xfe067c00) +// bit[31] enable_large_diff_16x8 +// bit[30] enable_large_diff_8x16 +// bit[29:16] adv_mv_8x8_weight +// bit[15:14] reserved +// bit[13:0] adv_mv_4x4x4_weight +#define ADV_MV_CTL0 ((0x0069 << 2) + 0xfe067c00) +// bit[31:16] adv_mv_16x16_weight +// bit[15] enable_large_diff_16x16 +// bit[14:0] adv_mv_16_8_weight +#define ADV_MV_CTL1 ((0x006a << 2) + 0xfe067c00) +#define ADV_MV_CTL2 ((0x006b << 2) + 0xfe067c00) +// bit[31] v3_skip_enable +// bit[30] v3_step_1_weight_enable // for step1, will only use pre_weight for block0, only step_weight for block 1,2,3 +// bit[29] v3_l2_skip_only_use_l2_sad // set to 1 may allow l1 maybe not skip +// bit[28] v3_mv_sad_weight_enable +// bit[27] v3_ipred_type_enable +// bit[25:12] force_skip_sad_1 +// bit[11:0] force_skip_sad_0 +#define V3_SKIP_CONTROL ((0x006c << 2) + 0xfe067c00) +// bit[18:16] top_ipred_type_count +// bit[15:14] Reserved +// bit[13:12] top_ipred_type_rd_idx +// bit[11:10] top_ipred_type_wr_idx +// bit[9] left_ipred_type_ready +// bit[8] top_ipred_type_ready +// bit[7:6] left_mv_idx +// bit[5:4] top_mv_idx +// bit[3] - left_mv_ready +// bit[2:0] top_mv_ready +#define V3_TOP_LEFT_CTL ((0x006d << 2) + 0xfe067c00) +#define V3_TOP_MV ((0x006e << 2) + 0xfe067c00) +#define V3_LEFT_MV ((0x006f << 2) + 0xfe067c00) +// bit[31:30] reserved +// bit[29:16] v3_skip_weight_1 +// bit[15:12] reserved +// bit[11:0] v3_skip_weight_0 +#define V3_SKIP_WEIGHT ((0x0070 << 2) + 0xfe067c00) +// bit[31:28] reserved +// bit[27:16] v3_l1_f_skip_max_sad +// bit[15:12] reserved +// bit[11:0] v3_l1_skip_max_sad +#define V3_L1_SKIP_MAX_SAD ((0x0071 << 2) + 0xfe067c00) +// bit[31:16] force_skip_sad_2 +// bit[15:0] v3_skip_weight_2 +#define V3_L2_SKIP_WEIGHT ((0x0072 << 2) + 0xfe067c00) +// bit[21:16] v3_mv_sad_table_addr 0-15 table_step_0 +// bit[11:0] v3_mv_sad +#define V3_MV_SAD_TABLE ((0x0073 << 2) + 0xfe067c00) +// [31:16] v3_ie_f_zero_sad_i16 +// [15:0] v3_ie_f_zero_sad_i4 +#define V3_F_ZERO_CTL_0 ((0x0074 << 2) + 0xfe067c00) +// [25] v3_no_ver_when_top_zero_en +// [24] v3_no_hor_when_left_zero_en +// [23:16] v3_max_I16_H_num // 0 means no break +// [15:0] v3_me_f_zero_sad +#define V3_F_ZERO_CTL_1 ((0x0075 << 2) + 0xfe067c00) +#define V3_TOP_INTRA_INFO ((0x0076 << 2) + 0xfe067c00) +#define V3_LEFT_INTRA_INFO ((0x0077 << 2) + 0xfe067c00) +// [31:24] C_ipred_weight_H +// [23:16] C_ipred_weight_V +// [15:8] I4_ipred_weight_else +// [7:0] I4_ipred_weight_most +#define V3_IPRED_TYPE_WEIGHT_0 ((0x0078 << 2) + 0xfe067c00) +// [31:24] I16_ipred_weight_DC +// [23:16] I16_ipred_weight_H +// [15:8] I16_ipred_weight_V +// [7:0] C_ipred_weight_DC +#define V3_IPRED_TYPE_WEIGHT_1 ((0x0079 << 2) + 0xfe067c00) +// [31:16] v3_left_small_max_me_sad +// [15:0] v3_left_small_max_ie_sad +#define V3_LEFT_SMALL_MAX_SAD ((0x007a << 2) + 0xfe067c00) +// (qr==7) & (qp==15) means force zero block +// [31:26] v4_force_q_r_intra +// [25:20] v4_force_q_r_inter +// [19] v4_force_q_y_enable +// [18:16] v4_force_qr_y +// [15:12] v4_force_qp_y +// [11:0] v4_force_skip_sad +#define V4_FORCE_SKIP_CFG ((0x007b << 2) + 0xfe067c00) +// v5 Complexity // Y(256 pixel per MB) and C(128 pixel per MB) +// For every 4x4 block, calculate average and Add abs(pixel-average) together +// bit[31:16] v5_diff_sum_C +// bit[15:0] v5_diff_sum_Y +#define V5_MB_DIFF_SUM ((0x007c << 2) + 0xfe067c00) +// bit[31:24] v5_small_diff_cnt_C +// bit[23:16] v5_small_diff_C +// bit[15:8] v5_small_diff_cnt_Y +// bit[7:0] v5_small_diff_Y +#define V5_SMALL_DIFF_CNT ((0x007d << 2) + 0xfe067c00) +// bit[31:29] Reserved +// bit[28:24] v5_simple_block_cnt // 0 -15 Y 16-23 C +// bit[23:20] v5_simple_pixel_cnt +// bit[19:18] v5_simple_dq_wr_ptr +// bit[17:16] v5_simple_dq_rd_ptr +// bit[15:12] v5_simple_dq (Read Only) +// bit[11:8] v5_simple_me_weight(Read Only) +// bit[7] v5_use_small_diff_cnt +// bit[6] v5_simple_mb_inter_all_en +// bit[5] v5_simple_mb_inter_8x8_en +// bit[4] v5_simple_mb_inter_16_8_en +// bit[3] v5_simple_mb_inter_16x16_en +// bit[2] v5_simple_mb_intra_en +// bit[1] v5_simple_mb_C_en +// bit[0] v5_simple_mb_Y_en +#define V5_SIMPLE_MB_CTL ((0x007e << 2) + 0xfe067c00) +// bit[31:28] v5_simple_dq_shift +// bit[27:24] v5_simple_dq_6(-7 to +7) +// bit[23:20] v5_simple_dq_5(-7 to +7) +// bit[19:16] v5_simple_dq_4(-7 to +7) +// bit[15:12] v5_simple_dq_3(-7 to +7) +// bit[11:08] v5_simple_dq_2(-7 to +7) +// bit[07:04] v5_simple_dq_1(-7 to +7) +// bit[03:00] v5_simple_dq_0(-7 to +7) +#define V5_SIMPLE_MB_DQUANT ((0x007f << 2) + 0xfe067c00) +// bit[31:28] v5_simple_me_weight_shift +// bit[27:24] v5_simple_me_weight_6(-7 to +7) +// bit[23:20] v5_simple_me_weight_5(-7 to +7) +// bit[19:16] v5_simple_me_weight_4(-7 to +7) +// bit[15:12] v5_simple_me_weight_3(-7 to +7) +// bit[11:08] v5_simple_me_weight_2(-7 to +7) +// bit[07:04] v5_simple_me_weight_1(-7 to +7) +// bit[03:00] v5_simple_me_weight_0(-7 to +7) +#define V5_SIMPLE_MB_ME_WEIGHT ((0x0080 << 2) + 0xfe067c00) +// +// Closing file: qdct_regs.h +// +// HEVC +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe068000 +// ----------------------------------------------- +// HEVC2 +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe06c000 +// ----------------------------------------------- +// DOC_TOP +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe06fc00 +// ----------------------------------------------- +//------------------------------------------------------------------------------ +// DOS top-level register offset +//------------------------------------------------------------------------------ +// ----------------------------------------------- +// `define DOS_TOP_CBUS_BASE 8'h3f +// ----------------------------------------------- +// [0] reserved +// [1] Reset Dos top level registers, except sw_reset0/1/2 which is only reset by external reset_n. +// [2] VDEC1 Reset assist, mdec's CBUS +// [3] VDEC1 Reset mdec's VLD +// [4] VDEC1 Reset mdec's VLD +// [5] VDEC1 Reset mdec's VLD +// [6] VDEC1 Reset mdec's IQIDCT +// [7] VDEC1 Reset mdec's MC +// [8] VDEC1 Reset mdec's DBLK +// [9] VDEC1 Reset mdec's PIC_DC +// [10] VDEC1 Reset mdec's Pscale +// [11] VDEC1 Reset vcpu's MCPU +// [12] VDEC1 Reset vcpu's CCPU +// [13] VDEC1 Reset mmc_pre_arb +#define DOS_SW_RESET0 ((0x0000 << 2) + 0xfe06fc00) +// [31:27] reserved +// [26] hcodec clk_en for henc assist +// [25:22] reserved +// [21] hcodec clk_en for henc qdct +// [20] hcodec clk_en for henc vlc +// [19] hcodec clk_en for assist and cbus +// [18] hcodec clk_en for ddr +// [17] hcodec clk_en for vcpu +// [16] hcodec clk_en for hdec assist +// [15] hcodec clk_en for hdec dblk +// [14] reserved +// [13] hcodec clk_en for hdec mc +// [12] hcodec clk_en for hdec pic_dc +// [11:10] reserved +// [9] vdec clk_en for vdec assist and cbus +// [8] vdec clk_en for ddr +// [7] vdec clk_en for vcpu +// [6] vdec clk_en for mdec vld +// [5] vdec clk_en for mdec psc +// [4] vdec clk_en for mdec pic_dc +// [3] vdec clk_en for mdec mc +// [2] vdec clk_en for mdec iqidct +// [1] vdec clk_en for mdec dblk +// [0] vdec clk_en for mdec assist +#define DOS_GCLK_EN0 ((0x0001 << 2) + 0xfe06fc00) +#define DOS_GEN_CTRL0 ((0x0002 << 2) + 0xfe06fc00) +#define DOS_APB_ERR_CTRL ((0x0003 << 2) + 0xfe06fc00) +#define DOS_APB_ERR_STAT ((0x0004 << 2) + 0xfe06fc00) +#define DOS_VDEC_INT_EN ((0x0005 << 2) + 0xfe06fc00) +#define DOS_HCODEC_INT_EN ((0x0006 << 2) + 0xfe06fc00) +// [0] Reserved +// [1] Reserved +// [2] HCODEC Reset assist, hdec's CBUS +// [3] HCODEC Reset hdec's VLD +// [4] HCODEC Reset hdec's VLD +// [5] HCODEC Reset hdec's VLD +// [6] HCODEC Reset hdec's IQIDCT +// [7] HCODEC Reset hdec's MC +// [8] HCODEC Reset hdec's DBLK +// [9] HCODEC Reset hdec's PIC_DC +// [10] HCODEC Reset hdec's Pscale +// [11] HCODEC Reset vcpu's MCPU +// [12] HCODEC Reset vcpu's CCPU +// [13] HCODEC Reset mmc_pre_arb +// [14] HCODEC Reserved +// [15] HCODEC Reserved +// [16] HCODEC Reset henc's VLC +#define DOS_SW_RESET1 ((0x0007 << 2) + 0xfe06fc00) +// [0] Reserved +// [1] Reserved +// [2] VDEC2 Reset assist, mdec's CBUS +// [3] VDEC2 Reset mdec's VLD +// [4] VDEC2 Reset mdec's VLD +// [5] VDEC2 Reset mdec's VLD +// [6] VDEC2 Reset mdec's IQIDCT +// [7] VDEC2 Reset mdec's MC +// [8] VDEC2 Reset mdec's DBLK +// [9] VDEC2 Reset mdec's PIC_DC +// [10] VDEC2 Reset mdec's Pscale +// [11] VDEC2 Reset vcpu's MCPU +// [12] VDEC2 Reset vcpu's CCPU +// [13] VDEC2 Reset mmc_pre_arb +#define DOS_SW_RESET2 ((0x0008 << 2) + 0xfe06fc00) +// [31:10] Reserved +// [9] vdec2 clk_en for assist and cbus. +// [8] vdec2 clk_en for ddr; +// [7] vdec2 clk_en for vcpu; +// [6] vdec2 clk_en for mdec vld +// [5] vdec2 clk_en for mdec psc +// [4] vdec2 clk_en for mdec pic_dc +// [3] vdec2 clk_en for mdec mc +// [2] vdec2 clk_en for mdec iqidct +// [1] vdec2 clk_en for mdec dblk +// [0] vdec2 clk_en for mdec assist +#define DOS_GCLK_EN1 ((0x0009 << 2) + 0xfe06fc00) +#define DOS_VDEC2_INT_EN ((0x000a << 2) + 0xfe06fc00) +#define DOS_VDIN_LCNT ((0x000b << 2) + 0xfe06fc00) +#define DOS_VDIN_FCNT ((0x000c << 2) + 0xfe06fc00) +#define DOS_VDIN_CCTL ((0x000d << 2) + 0xfe06fc00) +#define DOS_SCRATCH0 ((0x0010 << 2) + 0xfe06fc00) +#define DOS_SCRATCH1 ((0x0011 << 2) + 0xfe06fc00) +#define DOS_SCRATCH2 ((0x0012 << 2) + 0xfe06fc00) +#define DOS_SCRATCH3 ((0x0013 << 2) + 0xfe06fc00) +#define DOS_SCRATCH4 ((0x0014 << 2) + 0xfe06fc00) +#define DOS_SCRATCH5 ((0x0015 << 2) + 0xfe06fc00) +#define DOS_SCRATCH6 ((0x0016 << 2) + 0xfe06fc00) +#define DOS_SCRATCH7 ((0x0017 << 2) + 0xfe06fc00) +#define DOS_SCRATCH8 ((0x0018 << 2) + 0xfe06fc00) +#define DOS_SCRATCH9 ((0x0019 << 2) + 0xfe06fc00) +#define DOS_SCRATCH10 ((0x001a << 2) + 0xfe06fc00) +#define DOS_SCRATCH11 ((0x001b << 2) + 0xfe06fc00) +#define DOS_SCRATCH12 ((0x001c << 2) + 0xfe06fc00) +#define DOS_SCRATCH13 ((0x001d << 2) + 0xfe06fc00) +#define DOS_SCRATCH14 ((0x001e << 2) + 0xfe06fc00) +#define DOS_SCRATCH15 ((0x001f << 2) + 0xfe06fc00) +#define DOS_SCRATCH16 ((0x0020 << 2) + 0xfe06fc00) +#define DOS_SCRATCH17 ((0x0021 << 2) + 0xfe06fc00) +#define DOS_SCRATCH18 ((0x0022 << 2) + 0xfe06fc00) +#define DOS_SCRATCH19 ((0x0023 << 2) + 0xfe06fc00) +#define DOS_SCRATCH20 ((0x0024 << 2) + 0xfe06fc00) +#define DOS_SCRATCH21 ((0x0025 << 2) + 0xfe06fc00) +#define DOS_SCRATCH22 ((0x0026 << 2) + 0xfe06fc00) +#define DOS_SCRATCH23 ((0x0027 << 2) + 0xfe06fc00) +#define DOS_SCRATCH24 ((0x0028 << 2) + 0xfe06fc00) +#define DOS_SCRATCH25 ((0x0029 << 2) + 0xfe06fc00) +#define DOS_SCRATCH26 ((0x002a << 2) + 0xfe06fc00) +#define DOS_SCRATCH27 ((0x002b << 2) + 0xfe06fc00) +#define DOS_SCRATCH28 ((0x002c << 2) + 0xfe06fc00) +#define DOS_SCRATCH29 ((0x002d << 2) + 0xfe06fc00) +#define DOS_SCRATCH30 ((0x002e << 2) + 0xfe06fc00) +#define DOS_SCRATCH31 ((0x002f << 2) + 0xfe06fc00) +#define DOS_MEM_PD_VDEC ((0x0030 << 2) + 0xfe06fc00) +#define DOS_MEM_PD_VDEC2 ((0x0031 << 2) + 0xfe06fc00) +#define DOS_MEM_PD_HCODEC ((0x0032 << 2) + 0xfe06fc00) +#define DOS_MEM_PD_HEVC ((0x0033 << 2) + 0xfe06fc00) +#define DOS_SW_RESET3 ((0x0034 << 2) + 0xfe06fc00) +#define DOS_GCLK_EN3 ((0x0035 << 2) + 0xfe06fc00) +#define DOS_HEVC_INT_EN ((0x0036 << 2) + 0xfe06fc00) +#define DOS_SW_RESET4 ((0x0037 << 2) + 0xfe06fc00) +#define DOS_GCLK_EN4 ((0x0038 << 2) + 0xfe06fc00) +#define DOS_MEM_PD_WAVE_0 ((0x0039 << 2) + 0xfe06fc00) +#define DOS_WAVE_CNTL_STAT ((0x003a << 2) + 0xfe06fc00) +#define DOS_MEM_PD_WAVE_1 ((0x003b << 2) + 0xfe06fc00) +#define DOS_MEM_PD_WAVE_2 ((0x003c << 2) + 0xfe06fc00) +// bit[31] mcrcc_stall_en +// bit[30:28] Reserved +// bit[27:20] target_canvas +// bit[19:10] target_mby +// bit[ 9: 0] target_mbx +#define DOS_VDEC_MCRCC_STALL_CTRL ((0x0040 << 2) + 0xfe06fc00) +#define DOS_VDEC_MCRCC_STALL2_CTRL ((0x0042 << 2) + 0xfe06fc00) +#define DOS_VDEC2_MCRCC_STALL_CTRL ((0x0041 << 2) + 0xfe06fc00) +#define DOS_VDEC2_MCRCC_STALL2_CTRL ((0x0043 << 2) + 0xfe06fc00) +#define DOS_MEM_PD_HEVC2 ((0x0044 << 2) + 0xfe06fc00) +#define DOS_HEVC2_INT_EN ((0x0045 << 2) + 0xfe06fc00) +// bit[1] s_clk off +// bit[0] m_clk off +#define DOS_CFG_CMPIF_BRIDGE ((0x0048 << 2) + 0xfe06fc00) +// bit[31] cfg_stall_en +// bit[30] co_mv_stall_en +// bit[29] cfg_stall_force +// bit[28:24] reserved +// bit[23:12] cfg_stall_tilestrt_ctb_y +// bit[11: 0] cfg_stall_tilestrt_ctb_x +#define DOS_HEVC_STALL_START ((0x0050 << 2) + 0xfe06fc00) +// bit[31:24] cfg_stall_canvas +// bit[23:12] cfg_stall_tileend_ctb_y +// bit[11: 0] cfg_stall_tileend_ctb_x +#define DOS_HEVC_STALL_END ((0x0051 << 2) + 0xfe06fc00) +// bit[31:24] reserved +// bit[23:12] cfg_stall_ctb_y +// bit[11: 0] cfg_stall_ctb_x +#define DOS_HEVC_STALL_POSITION ((0x0052 << 2) + 0xfe06fc00) +// bit[31] cfg_stall_en +// bit[30] co_mv_stall_en +// bit[29] cfg_stall_force +// bit[28:24] reserved +// bit[23:12] cfg_stall_tilestrt_ctb_y +// bit[11: 0] cfg_stall_tilestrt_ctb_x +#define DOS_HEVC2_STALL_START ((0x0053 << 2) + 0xfe06fc00) +// bit[31:24] cfg_stall_canvas +// bit[23:12] cfg_stall_tileend_ctb_y +// bit[11: 0] cfg_stall_tileend_ctb_x +#define DOS_HEVC2_STALL_END ((0x0054 << 2) + 0xfe06fc00) +// bit[31:24] reserved +// bit[23:12] cfg_stall_ctb_y +// bit[11: 0] cfg_stall_ctb_x +#define DOS_HEVC2_STALL_POSITION ((0x0055 << 2) + 0xfe06fc00) +#define DOS_SECURE_CTL_INDEX ((0x0080 << 2) + 0xfe06fc00) +#define DOS_SECURE_CTL_DATA ((0x0081 << 2) + 0xfe06fc00) +#define DOS_SECURE_REG_NULL ((0x0082 << 2) + 0xfe06fc00) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: REG_LIST_DOS_RTL.h +// +// +// Reading file: gdc_regs.h +// +//=========================================================================== +////// GDC Registers +//=========================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe008800 +// ----------------------------------------------- +#define GDC_REG_START ((0x0000 << 2) + 0xfe008800) +// +// Closing file: gdc_regs.h +// +// +// Reading file: ge2d_regs.h +// +// synopsys translate_off +// synopsys translate_on +//=========================================================================== +//GE2D Registers +//=========================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe008c00 +// ----------------------------------------------- +//Bit 31, destination bytemask only if destination bitmask is enable +//Bit 30, destination bitmask enable +//Bit 29, source2 key enable +//Bit 28, source2 key mode, 0: mask data when match, 1: mask data when unmatch +//Bit 27, source1 key enable +//Bit 26, source1 key mode, 0: mask data when match, 1: mask data when unmatch +//Bit 25:24, dst1 8bit mode component selection, +// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha +//Bit 23 dst clip mode, 0: write inside clip window, 1: write outside clip window +//Bit 22:17, reserved +//Bit 16:15, src2 8bit mode component selection, +// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha +//Bit 14 src2 fill mode, 0: repeat data, 1: fill default color +//Bit 13:12 src2 picture struct, 00: frame, 10: even, 11: odd +//Bit 11 src1 x direction yc ration, 0: 1:1, 1: 2:1 +//Bit 10 src1 y direction yc ration, 0: 1:1, 1: 2:1 +//Bit 9:7 reserved +//Bit 6:5, src1 8bit mode component selection, +// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha +//Bit 4 src1 fill mode, 0: repeat data, 1: fill default color +//Bit 3 src1 lookup table enable +//Bit 2:1 src1 picture struct, 00: frame, 10: even, 11: odd +//Bit 0 src1 separate buffer enable +#define GE2D_GEN_CTRL0 ((0x00a0 << 2) + 0xfe008c00) +//Bit 31, soft rst +//Bit 30, dst write response counter reset +//Bit 29, disable adding dst write response count to busy bit +//Bit 28:26, reserved +//bit 25:24, interrupt control, if bit[0] true, generate interrupt when one command done, +// if bit[1] true, generate interrupt when ge2d change from busy to not busy +//Bit 23:22 src2 burst size control +//Bit 21:16 src1 burst size control, 5:4, yfifo, 3:2, cbfifo, 1:0, crfifo +// each 2bit, 00: 24 64bitword, 01: 32 64bitword, 10: 48 64bitwords, 11: 64 64bitwords +//Bit 15:14, dst1 picture struct, 00: frame, 10:top, 11: bottom +//Bit 13:12, bit 13 if true, force read src1, bit 12 if true, force read src2 +//Bit 11, dst2 request urgent enable +//Bit 10, src1 request urgent enable +//Bit 9, src2 request urgent enable +//Bit 8, dst1 request urgent enable +//Bit 7:0 src1 global alpha +#define GE2D_GEN_CTRL1 ((0x00a1 << 2) + 0xfe008c00) +//Bit31 alpha conversion mode in alu, 0: alpha_out = (alpha !=0) ? alpha +1 : 0; +// otherwise, alpha_out = (alpha < 128) ? alpha: alpha + 1; +//Bit30 color conversion mode in alu, 0: color_out = (color != 0) ? color +1: 0; +// otherwise, color_out = (color < 128) ? color: color + 1; +//Bit29 src1_gb_alpha_en, As = src1_gb_alpha_en ? Asr * Ag: Asr +//Bit28 dst1_color_round_mode, 0: truncate, 1: + 0.5 rounding +//Bit27 src2_color_expand_mode, 0: add 0, 1: add MSBs +//Bit26 src2_alpha_expand_mode, 0: add 0, 1: add MSBs +//Bit25 src1_color_expand_mode, 0: add 0, 1: add MSBs +//Bit24 src1_alpha_expand_mode, 0: add 0, 1: add MSBs +//Bit 23 if true, dst little endian, otherwise big endian +//Bit 22:19 dst1 color_map +// dst1_format=0 : output 8-bit; +// dst1_format=1, dst1_color_map=1: output 16-bit YCbCr 655; +// dst1_format=1, dst1_color_map=2: output 16-bit YCbCr 844; +// dst1_format=1, dst1_color_map=3: output 16-bit YCbCrA 6442; +// dst1_format=1, dst1_color_map=4: output 16-bit YCbCrA 4444; +// dst1_format=1, dst1_color_map=5: output 16-bit YCbCr 565; +// dst1_format=1, dst1_color_map=6: output 16-bit AYCbCr 4444; +// dst1_format=1, dst1_color_map=7: output 16-bit AYCbCr 1555; +// dst1_format=1, dst1_color_map=8: output 16-bit YCbCrA 4642; +// dst1_format=1, dst1_color_map=9: output 16-bit CbCr 88; +// dst1_format=1, dst1_color_map=10:output 16-bit CrCb 88; +// dst1_format=2, dst1_color_map=0: output 24-bit YCbCr 888; +// dst1_format=2, dst1_color_map=1: output 24-bit YCbCrA 5658; +// dst1_format=2, dst1_color_map=2: output 24-bit AYCbCr 8565; +// dst1_format=2, dst1_color_map=3: output 24-bit YCbCrA 6666; +// dst1_format=2, dst1_color_map=4: output 24-bit AYCbCr 6666; +// dst1_format=2, dst1_color_map=5: output 24-bit CrCbY 888; +// dst1_format=3, dst1_color_map=0: output 32-bit YCbCrA 8888; +// dst1_format=3, dst1_color_map=1: output 32-bit AYCbCr 8888; +// dst1_format=3, dst1_color_map=2: output 32-bit ACrCbY 8888; +// dst1_format=3, dst1_color_map=3: output 32-bit CrCbYA 8888. +//Bit 17:16 dst1_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit +//Bit 15 if true, src2 little endian, otherwise big endian +//Bit 14:11 src2 color_map +// src2_format=0 : output 8-bit; +// src2_format=1, src2_color_map=1: output 16-bit YCbCr 655; +// src2_format=1, src2_color_map=2: output 16-bit YCbCr 844; +// src2_format=1, src2_color_map=3: output 16-bit YCbCrA 6442; +// src2_format=1, src2_color_map=4: output 16-bit YCbCrA 4444; +// src2_format=1, src2_color_map=5: output 16-bit YCbCr 565; +// src2_format=1, src2_color_map=6: output 16-bit AYCbCr 4444; +// src2_format=1, src2_color_map=7: output 16-bit AYCbCr 1555; +// src2_format=1, src2_color_map=8: output 16-bit YCbCrA 4642; +// src2_format=2, src2_color_map=0: output 24-bit YCbCr 888; +// src2_format=2, src2_color_map=1: output 24-bit YCbCrA 5658; +// src2_format=2, src2_color_map=2: output 24-bit AYCbCr 8565; +// src2_format=2, src2_color_map=3: output 24-bit YCbCrA 6666; +// src2_format=2, src2_color_map=4: output 24-bit AYCbCr 6666; +// src2_format=2, src2_color_map=5: output 24-bit CrCbY 888; +// src2_format=3, src2_color_map=0: output 32-bit YCbCrA 8888; +// src2_format=3, src2_color_map=1: output 32-bit AYCbCr 8888; +// src2_format=3, src2_color_map=2: output 32-bit ACrCbY 8888; +// src2_format=3, src2_color_map=3: output 32-bit CrCbYA 8888. +//Bit 9:8 src2 format, 00: 8bit, 01:16bit, 10:24bit 11: 32bit +//Bit 7 if true, src1 little endian, otherwise big endian +//Bit 6:3 src1 color_map +// src1_format=0 : output 8-bit; +// src1_format=1, src1_color_map=0: output 4:2:2 (Y0Cb0Y1Cr0); +// src1_format=1, src1_color_map=1: output 16-bit YCbCr 655; +// src1_format=1, src1_color_map=2: output 16-bit YCbCr 844; +// src1_format=1, src1_color_map=3: output 16-bit YCbCrA 6442; +// src1_format=1, src1_color_map=4: output 16-bit YCbCrA 4444; +// src1_format=1, src1_color_map=5: output 16-bit YCbCr 565; +// src1_format=1, src1_color_map=6: output 16-bit AYCbCr 4444; +// src1_format=1, src1_color_map=7: output 16-bit AYCbCr 1555; +// src1_format=1, src2_color_map=8: output 16-bit YCbCrA 4642; +// src1_format=2, src1_color_map=0: output 24-bit YCbCr 888; +// src1_format=2, src1_color_map=1: output 24-bit YCbCrA 5658; +// src1_format=2, src1_color_map=2: output 24-bit AYCbCr 8565; +// src1_format=2, src1_color_map=3: output 24-bit YCbCrA 6666; +// src1_format=2, src1_color_map=4: output 24-bit AYCbCr 6666; +// src1_format=2, src1_color_map=5: output 24-bit CrCbY 888; +// src1_format=2, src1_color_map=14:output 8-bit Y and 16-bit CbCr; +// src1_format=2, src1_color_map=15:output 8-bit Y and 16-bit CrCb; +// src1_format=3, src1_color_map=0: output 32-bit YCbCrA 8888; +// src1_format=3, src1_color_map=1: output 32-bit AYCbCr 8888; +// src1_format=3, src1_color_map=2: output 32-bit ACrCbY 8888; +// src1_format=3, src1_color_map=3: output 32-bit CrCbYA 8888. +//Bit 1:0 src1 format, 00: 8bit, 01:16bit/4:2:2, 10:24bit 11: 32bit +#define GE2D_GEN_CTRL2 ((0x00a2 << 2) + 0xfe008c00) +//Bit 9 if true, all src2 data use default color +//Bit 8 if true, all src1 data use default color +//Bit 7 if true, dst x/y swap +//Bit 6 if true, dst x direction reversely read +//Bit 5 if true, dst y direction reversely read +//Bit 4 if true, src2 x direction reversely read +//Bit 3 if true, src2 y direction reversely read +//Bit 2 if true, src1 x direction reversely read +//Bit 1 if true, src1 y direction reversely read +//Bit 0 cmd write +#define GE2D_CMD_CTRL ((0x00a3 << 2) + 0xfe008c00) +//Read only +//Bit 28:17 dst write response counter, for debug only +//Bit 16:7 ge2d_dp status, for debug only +//Bit 6 read src1 cmd ready +//Bit 5 read src2 cmd ready +//Bit 4 pre dpcmd ready +//Bit 3 ge2d dpcmd ready +//Bit 2 ge2d buffer command valid +//Bit 1 ge2d current command valid +//Bit 0 ge2d busy +#define GE2D_STATUS0 ((0x00a4 << 2) + 0xfe008c00) +// +//Read only +// Bit 29:16 ge2d_dst1_status, for debug only +// Bit 15 ge2d_rd_src2 core.fifo_empty +// Bit 14 ge2d_rd_src2 core.fifo_overflow +// Bit 13:12 ge2d_rd_src2 core.req_st +// Bit 11 ge2d_rd_src2 cmd_if.cmd_err, true if cmd_format=1 +// Bit 10 ge2d_rd_src2 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state +// Bit 9 ge2d_rd_src1 luma_core(chroma_core).fifo_empty +// Bit 8 ge2d_rd_src1 luma_core(chroma_core).fifo_overflow +// Bit 7: 6 ge2d_rd_src1 chroma_core.req_st_cr +// Bit 5: 4 ge2d_rd_src1 chroma_core.req_st_cb +// Bit 3: 2 ge2d_rd_src1 luma_core.req_st_y +// Bit 1 ge2d_rd_src1 cmd_if.stat_read_window_err, 1=reading/clipping window setting exceed limit +// Bit 0 ge2d_rd_src1 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state +#define GE2D_STATUS1 ((0x00a5 << 2) + 0xfe008c00) +//SRC1 default clolor +//{Y,Cb,Cr,A}/{R,G,B,A} +#define GE2D_SRC1_DEF_COLOR ((0x00a6 << 2) + 0xfe008c00) +//Bit 31, SRC1 clip x start extra, if true, one more data is read for chroma +//Bit 28:16, SRC1 clip x start +//Bit 15, SRC1 clip x end extra, if true, one more data is read for chroma +//Bit 12:0, SRC1 clip x end +#define GE2D_SRC1_CLIPX_START_END ((0x00a7 << 2) + 0xfe008c00) +//Bit 31, SRC1 clip y start extra, if true, one more data is read for chroma +//Bit 28:16, SRC1 clip y start +//Bit 15, SRC1 clip y end extra, if true, one more data is read for chroma +//Bit 12:0, SRC1 clip y end +#define GE2D_SRC1_CLIPY_START_END ((0x00a8 << 2) + 0xfe008c00) +//Bit 31:24, SRC1 canvas address0 +//Bit 23:16, SRC1 canvas address1 +//Bit 15:8, SRC1 canvas address2 +#define GE2D_SRC1_CANVAS ((0x00a9 << 2) + 0xfe008c00) +//Bit 31, SRC1 x start extra bit1, if true, one more chroma data is read for x even start chroma data when y/c ratio = 2 +// or x even/odd start chroma extra data when y/c ratio = 1 +//Bit 30, SRC1 x start extra bit0, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2 +//Bit 29:16, SRC1 x start, signed data +//Bit 15, SRC1 x end extra bit1, if true, one more chroma data is read for x odd end chroma data when y/c ratio = 2 +// or x even/odd end chroma extra data when y/c ratio = 1 +//Bit 14, SRC1 x end extra bit0, if true, one more chroma data is read for x even end chroma data when y/c ratio = 2 +//Bit 13:0, SRC1 x end, signed data +#define GE2D_SRC1_X_START_END ((0x00aa << 2) + 0xfe008c00) +//Bit 31, SRC1 y start extra, if true, one more chroma data is read for y even start chroma data when y/c ratio = 2 +// or y even/odd start chroma extra data when y/c ratio = 1 +//Bit 30, SRC1 y start extra, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2 +//Bit 28:16, SRC1 y start +//Bit 15, SRC1 y end extra bit1, if true, one more chroma data is read for y odd end chroma data when y/c ratio = 2 +// or y even/odd end chroma extra data when y/c ratio = 1 +//Bit 14, SRC1 y end extra bit0, if true, one more chroma data is read for y even end chroma data when y/c ratio = 2 +//Bit 12:0, SRC1 y end +#define GE2D_SRC1_Y_START_END ((0x00ab << 2) + 0xfe008c00) +// Bit 31: 9 Reserved +// Bit 8 RW, 0 = Write LUT, 1 = Read LUT +// Bit 7: 0 RW, lut_addr +#define GE2D_SRC1_LUT_ADDR ((0x00ac << 2) + 0xfe008c00) +// Bit 31:24 RW, Y or R +// Bit 23:16 RW, Cb or G +// Bit 15: 8 RW, Cr or B +// Bit 7: 0 RW, Alpha +#define GE2D_SRC1_LUT_DAT ((0x00ad << 2) + 0xfe008c00) +//Bit 19, if true, horizontal formatter using repeat to get the pixel, otherwise using interpolation +//Bit 18, horizontal formatter en +//Bit 17, if true, vertical formatter using repeat to get the pixel, otherwise using interpolation +//Bit 16, vertical formatter en +//Bit 15:8 X direction chroma phase, +// [7:4] for x direction even start/end chroma phase when y/c ratio = 2 +// or start/end even/odd chroma phase when y/c ratio = 1 +// [3:0] for x direction odd start/end chroma phase only when y/c ration = 2 +//Bit 7:0 Y direction chroma phase, +// [7:4] for y direction even start/end chroma phase when y/c ratio = 2 +// or start/end even/odd chroma phase when y/c ratio = 1 +// [3:0] for y direction odd start/end chroma phase only when y/c ration = 2 +#define GE2D_SRC1_FMT_CTRL ((0x00ae << 2) + 0xfe008c00) +//SRC2 default clolor +//{Y,Cb,Cr,A}/{R,G,B,A} +#define GE2D_SRC2_DEF_COLOR ((0x00af << 2) + 0xfe008c00) +//Bit 28:16, SRC2 clip x start +//Bit 12:0, SRC2 clip x end +#define GE2D_SRC2_CLIPX_START_END ((0x00b0 << 2) + 0xfe008c00) +//Bit 28:16, SRC2 clip y start +//Bit 12:0, SRC2 clip y end +#define GE2D_SRC2_CLIPY_START_END ((0x00b1 << 2) + 0xfe008c00) +//Bit 28:16, SRC2 x start +//Bit 12:0, SRC2 x end +#define GE2D_SRC2_X_START_END ((0x00b2 << 2) + 0xfe008c00) +//Bit 28:16, SRC2 y start +//Bit 12:0, SRC2 y end +#define GE2D_SRC2_Y_START_END ((0x00b3 << 2) + 0xfe008c00) +//Bit 28:16, DST clip x start +//Bit 12:0, DST clip x end +#define GE2D_DST_CLIPX_START_END ((0x00b4 << 2) + 0xfe008c00) +// +//Bit 28:16, DST clip y start +//Bit 12:0, DST clip y end +#define GE2D_DST_CLIPY_START_END ((0x00b5 << 2) + 0xfe008c00) +//Bit 28:16, DST x start +//Bit 12:0, DST x end +#define GE2D_DST_X_START_END ((0x00b6 << 2) + 0xfe008c00) +// +//Bit 28:16, DST x start +//Bit 12:0, DST x end +#define GE2D_DST_Y_START_END ((0x00b7 << 2) + 0xfe008c00) +//Bit 23:16 DST2 canvas address +//Bit 15:8 SRC2 canvas address +//Bit 7:0 DST1 canvas address +#define GE2D_SRC2_DST_CANVAS ((0x00b8 << 2) + 0xfe008c00) +//vertical scaler phase step +//Bit 28:0, 5.24 format +#define GE2D_VSC_START_PHASE_STEP ((0x00b9 << 2) + 0xfe008c00) +//phase slope +//Bit 24:0, bit 24 signed bit +#define GE2D_VSC_PHASE_SLOPE ((0x00ba << 2) + 0xfe008c00) +//Bit 30:29, vertical repeat line0 number +//Bit 23:0, vertical scaler initial phase +#define GE2D_VSC_INI_CTRL ((0x00bb << 2) + 0xfe008c00) +//horizontal scaler phase step +//Bit 28:0, 5.24 format +#define GE2D_HSC_START_PHASE_STEP ((0x00bc << 2) + 0xfe008c00) +//phase slope +//Bit 24:0, bit 24 signed bit +#define GE2D_HSC_PHASE_SLOPE ((0x00bd << 2) + 0xfe008c00) +//Bit 30:29, horizontal repeat line0 number +//Bit 23:0, horizontal scaler initial phase +#define GE2D_HSC_INI_CTRL ((0x00be << 2) + 0xfe008c00) +//Bit 31:24, advance number in this round, if horizontal scaler is working on dividing mode +//Bit 23:0, horizontal scaler advance phase in this round, if horizontal scaler is working on dividing mode +#define GE2D_HSC_ADV_CTRL ((0x00bf << 2) + 0xfe008c00) +//Bit 30, vertical nearest mode enable, must set vt_bank_length = 4 +//Bit 29, horizontal nearest mode enable, must set hz_bank_length = 4 +//Bit 28, horizontal scaler dividing mode enable +//Bit 27:15, horizontal dividing length, if bit 28 is enable +//Bit 14, pre horizontal scaler enable +//Bit 13, pre vertical scale enable +//Bit 12, vertical scale enable +//Bit 11, horizontal scaler enable +//Bit 9, if true, treat horizontal repeat line number(GE2D_HSC_INI_CTRL bit 30:29) as repeating line, +// otherwise using treat horizontal repeat line number as minus line number. +//Bit 8, if true, treat vertical repeat line number(GE2D_VSC_INI_CTRL bit 30:29) as repeating line, +// otherwise using treat vertical repeat line number as minus line number. +//Bit 7, if true, always use phase0 in vertical scaler +//Bit 6:4, vertical scaler bank length +//Bit 3, if true, always use phase0 in horizontal scaler +//Bit 2:0, horizontal scaler bank length +#define GE2D_SC_MISC_CTRL ((0x00c0 << 2) + 0xfe008c00) +//Read only +//vertical scaler next round integer pixel pointer, signed data +//Bit 13:0 +#define GE2D_VSC_NRND_POINT ((0x00c1 << 2) + 0xfe008c00) +//Read only +//vertical scaler next round phase +//bit 23:0 +#define GE2D_VSC_NRND_PHASE ((0x00c2 << 2) + 0xfe008c00) +//Read only +//horizontal scaler next round integer pixel pointer, signed data +//Bit 13:0 +#define GE2D_HSC_NRND_POINT ((0x00c3 << 2) + 0xfe008c00) +//Read only +//horizontal scaler next round phase +//bit 23:0 +#define GE2D_HSC_NRND_PHASE ((0x00c4 << 2) + 0xfe008c00) +// +//Bit 28:20, pre_offset0 +//Bit 18:10, pre_offset1 +//Bit 8:0, pre_offset2 +#define GE2D_MATRIX_PRE_OFFSET ((0x00c5 << 2) + 0xfe008c00) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define GE2D_MATRIX_COEF00_01 ((0x00c6 << 2) + 0xfe008c00) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define GE2D_MATRIX_COEF02_10 ((0x00c7 << 2) + 0xfe008c00) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define GE2D_MATRIX_COEF11_12 ((0x00c8 << 2) + 0xfe008c00) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define GE2D_MATRIX_COEF20_21 ((0x00c9 << 2) + 0xfe008c00) +//Bit 28:16 coef22 +//Bit 7 input y/cb/cr saturation enable +//Bit 0 conversion matrix enable +#define GE2D_MATRIX_COEF22_CTRL ((0x00ca << 2) + 0xfe008c00) +//Bit 28:20, offset0 +//Bit 18:10, offset1 +//Bit 8:0, offset2 +#define GE2D_MATRIX_OFFSET ((0x00cb << 2) + 0xfe008c00) +//Bit 26:25, SRC1 color multiplier alpha selection +// if 00, Cs = Csr +// if 01, Cs = Csr * Asr * Ag (if source is not premultiplied) +// if 10, Cs = Csr * Ag (if source is premultipied) +//Bit 24 SRC2 color multiplier alpha selection +// if 0, no multiplier, Cd = Cdr, otherwise, Cd = Cdr * Ad. +//Bit 22:12 ALU color operation +// bit10:8 Blending Mode Parameter +// 3'b000: ADD Cs*Fs + Cd*Fd +// 3'b001: SUBTRACT Cs*Fs - Cd*Fd +// 3'b010: REVERSE SUBTRACT Cd*Fd - Cs*Fs +// 3'b011: MIN min(Cs*Fs, Cd*Fd) +// 3'b100: MAX max(Cs*Fs, Cd*Fd) +// 3'b101: LOGIC OP Cs op Cd +// bit7:4 Source Color Blending Factor CFs +// 4'b0000: ZERO 0 +// 4'b0001: ONE 1 +// 4'b0010: SRC_COLOR Cs(RGBs) +// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs) +// 4'b0100: DST_COLOR Cd(RGBd) +// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd) +// 4'b0110: SRC_ALPHA As +// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As +// 4'b1000: DST_ALPHA Ad +// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad +// 4'b1010: CONST_COLOR Cc(RGBc) +// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc) +// 4'b1100: CONST_ALPHA Ac +// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac +// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad) +// bit3:0 dest Color Blending Factor CFd, when bit10:8 != LOGIC OP +// 4'b0000: ZERO 0 +// 4'b0001: ONE 1 +// 4'b0010: SRC_COLOR Cs(RGBs) +// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs) +// 4'b0100: DST_COLOR Cd(RGBd) +// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd) +// 4'b0110: SRC_ALPHA As +// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As +// 4'b1000: DST_ALPHA Ad +// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad +// 4'b1010: CONST_COLOR Cc(RGBc) +// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc) +// 4'b1100: CONST_ALPHA Ac +// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac +// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad) +// bit3:0 logic operations, when bit10:8 == LOGIC OP +// 4'b0000: CLEAR 0 +// 4'b0001: COPY s +// 4'b0010: NOOP d +// 4'b0011: SET 1 +// 4'b0100: COPY_INVERT ~s +// 4'b0101: INVERT ~d +// 4'b0110: AND_REVERSE s & ~d +// 4'b0111: OR_REVERSE s | ~d +// 4'b1000: AND s & d +// 4'b1001: OR s | d +// 4'b1010: NAND ~(s & d) +// 4'b1011: NOR ~(s | d) +// 4'b1100: XOR s ^ d +// 4'b1101: EQUIV ~(s ^ d) +// 4'b1110: AND_INVERTED ~s & d +// 4'b1111: OR_INVERTED ~s | d +//Bit 10:0 ALU alpha operation +// bit10:8 Blending Equation Math Operation +// 3'b000: ADD As*Fs + Ad*Fd +// 3'b001: SUBTRACT As*Fs - Ad*Fd +// 3'b010: REVERSE SUBTRACT Ad*Fd - As*Fs +// 3'b011: MIN min(As*Fs, Ad*Fd) +// 3'b100: MAX max(As*Fs, Ad*Fd) +// 3'b101: LOGIC OP As op Ad +// bit7:4 Source alpha Blending Factor AFs +// 4'b0000 0 +// 4'b0001 1 +// 4'b0010 As +// 4'b0011 1 - As +// 4'b0100 Ad +// 4'b0101 1 - Ad +// 4'b0110 Ac +// 4'b0111 1 - Ac +// .... reserved +// bit3:0 Destination alpha Blending Factor AFd, when bit10:8 != LOGIC OP +// 4'b0000 0 +// 4'b0001 1 +// 4'b0010 As +// 4'b0011 1 - As +// 4'b0100 Ad +// 4'b0101 1 - Ad +// 4'b0110 Ac +// 4'b0111 1 - Ac +// .... reserved +// bit3:0 logic operations, when bit10:8 == LOGIC OP +// 4'b0000: CLEAR 0 +// 4'b0001: COPY s +// 4'b0010: NOOP d +// 4'b0011: SET 1 +// 4'b0100: COPY_INVERT ~s +// 4'b0101: INVERT ~d +// 4'b0110: AND_REVERSE s & ~d +// 4'b0111: OR_REVERSE s | ~d +// 4'b1000: AND s & d +// 4'b1001: OR s | d +// 4'b1010: NAND ~(s & d) +// 4'b1011: NOR ~(s | d) +// 4'b1100: XOR s ^ d +// 4'b1101: EQUIV ~(s ^ d) +// 4'b1110: AND_INVERTED ~s & d +// 4'b1111: OR_INVERTED ~s | d +#define GE2D_ALU_OP_CTRL ((0x00cc << 2) + 0xfe008c00) +//bit 31:0 (RGBA,YCBCRA) +#define GE2D_ALU_CONST_COLOR ((0x00cd << 2) + 0xfe008c00) +//SRC1 Key +//31:0 +#define GE2D_SRC1_KEY ((0x00ce << 2) + 0xfe008c00) +//SRC1 Key Mask +//31:0 +#define GE2D_SRC1_KEY_MASK ((0x00cf << 2) + 0xfe008c00) +//SRC2 Key +//31:0 +#define GE2D_SRC2_KEY ((0x00d0 << 2) + 0xfe008c00) +//SRC2 Key Mask +//31:0 +#define GE2D_SRC2_KEY_MASK ((0x00d1 << 2) + 0xfe008c00) +//Destination Bit Mask +//31:0 +#define GE2D_DST_BITMASK ((0x00d2 << 2) + 0xfe008c00) +//Bit 31 DP onoff mode, 0: on_counter means how many pixels will output before ge2d turns off +// 1: on_counter means how many clocks will ge2d turn on before ge2d turns off +//Bit 30:16 DP on counter +//Bit 15 0: vd_format doesnt have onoff mode, 1: vd format has onoff mode +//Bit 14:0 DP off counter +#define GE2D_DP_ONOFF_CTRL ((0x00d3 << 2) + 0xfe008c00) +//Because there are many coefficients used in the vertical filter and horizontal filters, +//indirect access the coefficients of vertical filter and horizontal filter is used. +//For vertical filter, there are 33x4 coefficients +//For horizontal filter, there are 33x4 coefficients +//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2) +//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not +//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef +//Bit 8 type of index, 0: vertical coef +// 1: horizontal coef +//Bit 6:0 coef index +#define GE2D_SCALE_COEF_IDX ((0x00d4 << 2) + 0xfe008c00) +//coefficients for vertical filter and horizontal filter +#define GE2D_SCALE_COEF ((0x00d5 << 2) + 0xfe008c00) +//Bit 24 src2 alpha fill mode: together with GE2D_GEN_CTRL0[4](fill_mode), define what alpha values are used +// for the area outside the clipping window. As below: +// fill_mode=0, alpha_fill_mode=0 : use inner alpha, (or default_alpha if src data have no alpha values); +// fill_mode=0, alpha_fill_mode=1 : use outside_alpha; +// fill_mode=1, alpha_fill_mode=0 : use default_alpha; +// fill_mode=1, alpha_fill_mode=1 : use outside_alpha. +//Bit 23:16 src2 outside alpha +//Bit 8 src1 alpha fill mode, refer to src2 alpha fill mode above. +//Bit 7:0 src1 outside alpha +#define GE2D_SRC_OUTSIDE_ALPHA ((0x00d6 << 2) + 0xfe008c00) +//Bit 31 antiflick enable +//Bit 24 1: alpha value for the first line use repeated alpha, 0: use bit 23:16 as the first line alpha +//Bit 23:16 register value for the first line alpha when bit 24 is 1 +//Bit 8 1: alpha value for the last line use repeated alpha, 0: use bit 7:0 as the last line alpha +//Bit 7:0 register value for the last line alpha when bit 8 is 1 +#define GE2D_ANTIFLICK_CTRL0 ((0x00d8 << 2) + 0xfe008c00) +//Bit 25, rgb_sel, 1: antiflick RGBA, 0: antiflick YCbCrA +//Bit 24, cbcr_en, 1: also filter cbcr in case of antiflicking YCbCrA, 0: no filter on cbcr in case of antiflicking YCbCrA +//Bit 23:16, R mult coef for converting RGB to Y +//Bit 15:8, G mult coef for converting RGB to Y +//Bit 7:0, B mult coef for converting RGB to Y +//Y = (R * y_r + G * y_g + B * y_b) / 256 +#define GE2D_ANTIFLICK_CTRL1 ((0x00d9 << 2) + 0xfe008c00) +//Bit 31:24, Y threhold1, when 0<Y<=th1, use filter0; +//Bit 23:16, color antiflick filter0 n3 +//Bit 15:8, color antiflick filter0 n2 +//Bit 7:0, color antiflick filter0 n1 +//Y = (line_up * n1 + line_center * n2 + line_dn * n3) / 128 +#define GE2D_ANTIFLICK_COLOR_FILT0 ((0x00da << 2) + 0xfe008c00) +//Bit 31:24, Y threhold2, when th1<Y<=th2, use filter1; +//Bit 23:16, color antiflick filter1 n3 +//Bit 15:8, color antiflick filter1 n2 +//Bit 7:0, color antiflick filter1 n1 +#define GE2D_ANTIFLICK_COLOR_FILT1 ((0x00db << 2) + 0xfe008c00) +//Bit 31:24, Y threhold3, when th2<Y<=th3, use filter2; Y>th3, use filter3 +//Bit 23:16, color antiflick filter2 n3 +//Bit 15:8, color antiflick filter2 n2 +//Bit 7:0, color antiflick filter2 n1 +#define GE2D_ANTIFLICK_COLOR_FILT2 ((0x00dc << 2) + 0xfe008c00) +//Bit 23:16, color antiflick filter3 n3 +//Bit 15:8, color antiflick filter3 n2 +//Bit 7:0, color antiflick filter3 n1 +#define GE2D_ANTIFLICK_COLOR_FILT3 ((0x00dd << 2) + 0xfe008c00) +//Bit 31:24, Alpha threhold1, when 0<Alpha<=th1, use filter0; +//Bit 23:16, Alpha antiflick filter0 n3 +//Bit 15:8, Alpha antiflick filter0 n2 +//Bit 7:0, Alpha antiflick filter0 n1 +//Alpha = (line_up * n1 + line_center * n2 + line_dn * n3) / 128 +#define GE2D_ANTIFLICK_ALPHA_FILT0 ((0x00de << 2) + 0xfe008c00) +//Bit 31:24, Alpha threhold2, when th1<Alpha<=th2, use filter1; +//Bit 23:16, Alpha antiflick filter1 n3 +//Bit 15:8, Alpha antiflick filter1 n2 +//Bit 7:0, Alpha antiflick filter1 n1 +#define GE2D_ANTIFLICK_ALPHA_FILT1 ((0x00df << 2) + 0xfe008c00) +//Bit 31:24, Alpha threhold3, when th2<Alpha<=th3, use filter2; Alpha>th3, use filter3 +//Bit 23:16, Alpha antiflick filter2 n3 +//Bit 15:8, Alpha antiflick filter2 n2 +//Bit 7:0, Alpha antiflick filter2 n1 +#define GE2D_ANTIFLICK_ALPHA_FILT2 ((0x00e0 << 2) + 0xfe008c00) +//Bit 23:16, Alpha antiflick filter3 n3 +//Bit 15:8, Alpha antiflick filter3 n2 +//Bit 7:0, Alpha antiflick filter3 n1 +#define GE2D_ANTIFLICK_ALPHA_FILT3 ((0x00e1 << 2) + 0xfe008c00) +//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) +//Bit 30:22 din_offset (signed data) +//Bit 21:14 map_coef (unsigned data) +//Bit 13:10 map_sr (unsigned data) +//Bit 9:1 dout_offset (signed data) +//Bit 0 enable +#define GE2D_SRC1_RANGE_MAP_Y_CTRL ((0x00e3 << 2) + 0xfe008c00) +//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) +//Bit 30:22 din_offset (signed data) +//Bit 21:14 map_coef (unsigned data) +//Bit 13:10 map_sr (unsigned data) +//Bit 9:1 dout_offset (signed data) +//Bit 0 enable +#define GE2D_SRC1_RANGE_MAP_CB_CTRL ((0x00e4 << 2) + 0xfe008c00) +//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) +//Bit 30:22 din_offset (signed data) +//Bit 21:14 map_coef (unsigned data) +//Bit 13:10 map_sr (unsigned data) +//Bit 9:1 dout_offset (signed data) +//Bit 0 enable +#define GE2D_SRC1_RANGE_MAP_CR_CTRL ((0x00e5 << 2) + 0xfe008c00) +//Bit 21:16 src1 prearbitor burst number +//Bit 13:8 src2 prearbitor burst number +//Bit 5:0 dst prearbitor burst number +#define GE2D_ARB_BURST_NUM ((0x00e6 << 2) + 0xfe008c00) +//each 6bit ID, high 4bit are thread ID, low 2bits are the token +//Bit 21:16 src1 ID +//Bit 13:8 src2 ID +//Bit 5:0 dst ID +#define GE2D_TID_TOKEN ((0x00e7 << 2) + 0xfe008c00) +//Bit 31:28 dst2_bytemask_val. 1-bit mask for each byte (8-bit). Applicable only if both dst_bitmask_en=1 and dst_bytemask_only=1. +//Bit 27:26, dst2 picture struct, 00: frame, 10:top, 11: bottom +//Bit 25:24, dst2 8bit mode component selection, +// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha +//Bit 22:19 dst2 color_map +// dst2_format=0 : output 8-bit; +// dst2_format=1, dst2_color_map=1: output 16-bit YCbCr 655; +// dst2_format=1, dst2_color_map=2: output 16-bit YCbCr 844; +// dst2_format=1, dst2_color_map=3: output 16-bit YCbCrA 6442; +// dst2_format=1, dst2_color_map=4: output 16-bit YCbCrA 4444; +// dst2_format=1, dst2_color_map=5: output 16-bit YCbCr 565; +// dst2_format=1, dst2_color_map=6: output 16-bit AYCbCr 4444; +// dst2_format=1, dst2_color_map=7: output 16-bit AYCbCr 1555; +// dst2_format=1, dst2_color_map=8: output 16-bit YCbCrA 4642; +// dst2_format=1, dst2_color_map=9: output 16-bit CbCr 88; +// dst2_format=1, dst2_color_map=10:output 16-bit CrCb 88; +// dst2_format=2, dst2_color_map=0: output 24-bit YCbCr 888; +// dst2_format=2, dst2_color_map=1: output 24-bit YCbCrA 5658; +// dst2_format=2, dst2_color_map=2: output 24-bit AYCbCr 8565; +// dst2_format=2, dst2_color_map=3: output 24-bit YCbCrA 6666; +// dst2_format=2, dst2_color_map=4: output 24-bit AYCbCr 6666; +// dst2_format=2, dst2_color_map=5: output 24-bit CrCbY 888; +// dst2_format=3, dst2_color_map=0: output 32-bit YCbCrA 8888; +// dst2_format=3, dst2_color_map=1: output 32-bit AYCbCr 8888; +// dst2_format=3, dst2_color_map=2: output 32-bit ACrCbY 8888; +// dst2_format=3, dst2_color_map=3: output 32-bit CrCbYA 8888. +//Bit 17:16 dst2_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit +//Bit 15 reserved +//Bit 14 dst2_color_round_mode, 0: truncate, 1: + 0.5 rounding +//Bit 13:12, dst2_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation. +//Bit 11:10, dst2_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation. +//Bit 9 reserved +//Bit 8, dst2_enable. 0: disable dst2 (default); 1=enable dst2. +//Bit 7: 6 reserved +//Bit 5: 4, dst1_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation. +//Bit 3: 2, dst1_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation. +//Bit 1 reserved +//Bit 0, dst1_enable. 0: disable dst1; 1=enable dst1 (default). +#define GE2D_GEN_CTRL3 ((0x00e8 << 2) + 0xfe008c00) +//Read only +// Bit 13:0 ge2d_dst2_status, for debug only +#define GE2D_STATUS2 ((0x00e9 << 2) + 0xfe008c00) +//Bit 27:26 src1 Y fifo size control, 00: 512, 01: 256, 10: 128 11: 96 +//Bit 25:24 src2 fifo size control, 00: 512, 01: 256, 10: 128 11: 96 +//Bit 23:22 dst1 fifo size control, 00: 512, 01: 256, 10: 128 11: 64 +//Bit 21:20 dst2 fifo size control, 00: 512, 01: 256, 10: 128 11: 64 +//Bit 19:18, dst1 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64 +//Bit 17:16, dst2 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64 +//Bit 15:1, top_wrap_ctrl +//bit 0, if true, disable bug fix about the dp_out_done/scale_out_done(test1823) hang issue when scaling down ratio is high. +#define GE2D_GEN_CTRL4 ((0x00ea << 2) + 0xfe008c00) +#define GE2D_GCLK_CTRL0 ((0x00ef << 2) + 0xfe008c00) +#define GE2D_GCLK_CTRL1 ((0x00f0 << 2) + 0xfe008c00) +#define GE2D_GEN_CTRL5 ((0x00f1 << 2) + 0xfe008c00) +#define GE2D_DST1_BADDR_CTRL ((0x00f2 << 2) + 0xfe008c00) +//Bit 31:0, dst1 base address in 64bits +#define GE2D_DST1_STRIDE_CTRL ((0x00f3 << 2) + 0xfe008c00) +//Bit 19:0, dst1 stride size in 64bits +#define GE2D_DST2_BADDR_CTRL ((0x00f4 << 2) + 0xfe008c00) +//Bit 31:0, dst1 base address in 64bits +#define GE2D_DST2_STRIDE_CTRL ((0x00f5 << 2) + 0xfe008c00) +//Bit 19:0, dst1 stride size in 64bits +#define GE2D_SRC1_BADDR_CTRL_Y ((0x00f6 << 2) + 0xfe008c00) +//Bit 31:0, src1 base address in 64bits +#define GE2D_SRC1_STRIDE_CTRL_Y ((0x00f7 << 2) + 0xfe008c00) +//Bit 19:0, src1 stride size in 64bits +#define GE2D_SRC1_BADDR_CTRL_CB ((0x00f8 << 2) + 0xfe008c00) +//Bit 31:0, src1 base address in 64bits +#define GE2D_SRC1_STRIDE_CTRL_CB ((0x00f9 << 2) + 0xfe008c00) +//Bit 19:0, src1 stride size in 64bits +#define GE2D_SRC1_BADDR_CTRL_CR ((0x00fa << 2) + 0xfe008c00) +//Bit 31:0, src1 base address in 64bits +#define GE2D_SRC1_STRIDE_CTRL_CR ((0x00fb << 2) + 0xfe008c00) +//Bit 19:0, src1 stride size in 64bits +#define GE2D_SRC2_BADDR_CTRL ((0x00fc << 2) + 0xfe008c00) +//Bit 31:0, src2 base address in 64bits +#define GE2D_SRC2_STRIDE_CTRL ((0x00fd << 2) + 0xfe008c00) +//Bit 19:0, src2 stride size in 64bits +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ge2d_regs.h +// +// +// Reading file: mipi_isp.h +// +//======================================================================== +// MIPI_ISP +//======================================================================== +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe023000 +// ----------------------------------------------- +#define MIPI_ADAPT_DDR_RD0_CNTL0 ((0x0000 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_CNTL1 ((0x0001 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_CNTL2 ((0x0002 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_CNTL3 ((0x0003 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_CNTL4 ((0x0004 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_ST0 ((0x0005 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_ST1 ((0x0006 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_ST2 ((0x0007 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_CNTL5 ((0x0008 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD0_CNTL6 ((0x0009 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_CNTL0 ((0x0010 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_CNTL1 ((0x0011 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_CNTL2 ((0x0012 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_CNTL3 ((0x0013 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_CNTL4 ((0x0014 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_ST0 ((0x0015 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_ST1 ((0x0016 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_ST2 ((0x0017 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_CNTL5 ((0x0018 << 2) + 0xfe023000) +#define MIPI_ADAPT_DDR_RD1_CNTL6 ((0x0019 << 2) + 0xfe023000) +#define MIPI_ADAPT_PIXEL0_CNTL0 ((0x0020 << 2) + 0xfe023000) +#define MIPI_ADAPT_PIXEL0_CNTL1 ((0x0021 << 2) + 0xfe023000) +#define MIPI_ADAPT_PIXEL1_CNTL0 ((0x0022 << 2) + 0xfe023000) +#define MIPI_ADAPT_PIXEL1_CNTL1 ((0x0023 << 2) + 0xfe023000) +#define MIPI_ADAPT_PIXEL0_ST0 ((0x002a << 2) + 0xfe023000) +#define MIPI_ADAPT_PIXEL0_ST1 ((0x002b << 2) + 0xfe023000) +#define MIPI_ADAPT_PIXEL1_ST0 ((0x002c << 2) + 0xfe023000) +#define MIPI_ADAPT_PIXEL1_ST1 ((0x002d << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL0 ((0x0030 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL1 ((0x0031 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL2 ((0x0032 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL3 ((0x0033 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL4 ((0x0034 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL5 ((0x0035 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL6 ((0x0036 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL7 ((0x0037 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL8 ((0x0038 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL9 ((0x0039 << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_ST0 ((0x003a << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_ST1 ((0x003b << 2) + 0xfe023000) +#define MIPI_ADAPT_ALIG_CNTL10 ((0x003c << 2) + 0xfe023000) +#define MIPI_OTHER_CNTL0 ((0x0040 << 2) + 0xfe023000) +#define MIPI_OTHER_CNTL1 ((0x0041 << 2) + 0xfe023000) +#define MIPI_OTHER_CNTL2 ((0x0042 << 2) + 0xfe023000) +#define MIPI_OTHER_CNTL3 ((0x0043 << 2) + 0xfe023000) +#define MIPI_OTHER_CNTL4 ((0x0044 << 2) + 0xfe023000) +#define MIPI_OTHER_ST0 ((0x004a << 2) + 0xfe023000) +#define MIPI_OTHER_ST1 ((0x004b << 2) + 0xfe023000) +#define DDR_RD0_LBUF_STATUS ((0x0050 << 2) + 0xfe023000) +#define DDR_RD1_LBUF_STATUS ((0x0051 << 2) + 0xfe023000) +#define MIPI_ADAPT_IRQ_MASK0 ((0x0060 << 2) + 0xfe023000) +#define MIPI_ADAPT_IRQ_PENDING0 ((0x0061 << 2) + 0xfe023000) +#define MIPI_ADAPT_IRQ_MASK1 ((0x0062 << 2) + 0xfe023000) +#define MIPI_ADAPT_IRQ_PENDING1 ((0x0063 << 2) + 0xfe023000) +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe023800 +// ----------------------------------------------- +#define MIPI_ISP_RDARB_MODE ((0x0000 << 2) + 0xfe023800) +#define MIPI_ISP_RDARB_REQEN_SLV ((0x0001 << 2) + 0xfe023800) +#define MIPI_ISP_RDARB_WEIGH0_SLV ((0x0002 << 2) + 0xfe023800) +#define MIPI_ISP_RDARB_WEIGH1_SLV ((0x0003 << 2) + 0xfe023800) +#define MIPI_ISP_RDARB_UGT ((0x0004 << 2) + 0xfe023800) +#define MIPI_ISP_RDARB_LIMT0 ((0x0005 << 2) + 0xfe023800) +#define MIPI_ISP_WRARB_MODE ((0x0006 << 2) + 0xfe023800) +#define MIPI_ISP_WRARB_REQEN_SLV ((0x0007 << 2) + 0xfe023800) +#define MIPI_ISP_WRARB_WEIGH0_SLV ((0x0008 << 2) + 0xfe023800) +#define MIPI_ISP_WRARB_WEIGH1_SLV ((0x0009 << 2) + 0xfe023800) +#define MIPI_ISP_WRARB_UGT ((0x000a << 2) + 0xfe023800) +#define MIPI_ISP_RDWR_ARB_STATUS ((0x000b << 2) + 0xfe023800) +#define MIPI_ISP_ARB_DBG_CTRL ((0x000c << 2) + 0xfe023800) +#define MIPI_ISP_ARB_DBG_STAT ((0x000d << 2) + 0xfe023800) +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe023a00 +// ----------------------------------------------- +#define ISP_DMA_BUS_CNTL ((0x0000 << 2) + 0xfe023a00) +#define ISP_DMA_CTL0 ((0x0001 << 2) + 0xfe023a00) +#define ISP_DMA_SRC_ADDR0 ((0x0002 << 2) + 0xfe023a00) +#define ISP_DMA_DST_ADDR0 ((0x0003 << 2) + 0xfe023a00) +#define ISP_DMA_CTL_TASK0 ((0x0004 << 2) + 0xfe023a00) +#define ISP_DMA_SRC_ADDR1 ((0x0005 << 2) + 0xfe023a00) +#define ISP_DMA_DST_ADDR1 ((0x0006 << 2) + 0xfe023a00) +#define ISP_DMA_CTL_TASK1 ((0x0007 << 2) + 0xfe023a00) +#define ISP_DMA_SRC_ADDR2 ((0x0008 << 2) + 0xfe023a00) +#define ISP_DMA_DST_ADDR2 ((0x0009 << 2) + 0xfe023a00) +#define ISP_DMA_CTL_TASK2 ((0x000a << 2) + 0xfe023a00) +#define ISP_DMA_SRC_ADDR3 ((0x000b << 2) + 0xfe023a00) +#define ISP_DMA_DST_ADDR3 ((0x000c << 2) + 0xfe023a00) +#define ISP_DMA_CTL_TASK3 ((0x000d << 2) + 0xfe023a00) +#define ISP_DMA_SRC_ADDR4 ((0x000e << 2) + 0xfe023a00) +#define ISP_DMA_DST_ADDR4 ((0x000f << 2) + 0xfe023a00) +#define ISP_DMA_CTL_TASK4 ((0x0010 << 2) + 0xfe023a00) +#define ISP_DMA_SRC_ADDR5 ((0x0011 << 2) + 0xfe023a00) +#define ISP_DMA_DST_ADDR5 ((0x0012 << 2) + 0xfe023a00) +#define ISP_DMA_CTL_TASK5 ((0x0013 << 2) + 0xfe023a00) +#define ISP_DMA_SRC_ADDR6 ((0x0014 << 2) + 0xfe023a00) +#define ISP_DMA_DST_ADDR6 ((0x0015 << 2) + 0xfe023a00) +#define ISP_DMA_CTL_TASK6 ((0x0016 << 2) + 0xfe023a00) +#define ISP_DMA_SRC_ADDR7 ((0x0017 << 2) + 0xfe023a00) +#define ISP_DMA_DST_ADDR7 ((0x0018 << 2) + 0xfe023a00) +#define ISP_DMA_CTL_TASK7 ((0x0019 << 2) + 0xfe023a00) +#define ISP_DMA_ST0 ((0x001a << 2) + 0xfe023a00) +#define ISP_DMA_ST1 ((0x001b << 2) + 0xfe023a00) +#define ISP_DMA_ST2 ((0x001c << 2) + 0xfe023a00) +#define ISP_DMA_ST3 ((0x001d << 2) + 0xfe023a00) +#define ISP_DMA_ST4 ((0x001e << 2) + 0xfe023a00) +#define ISP_DMA_ST5 ((0x001f << 2) + 0xfe023a00) +#define ISP_DMA_ST6 ((0x0020 << 2) + 0xfe023a00) +// ----------------------------------------------- +// APB_BASE: APB0_BASE_ADDR = 0xfe023c00 +// ----------------------------------------------- +#define MIPI_BL_FR_PING_ADDR0_ST ((0x0000 << 2) + 0xfe023c00) +#define MIPI_BL_FR_PING_ADDR0_ED ((0x0001 << 2) + 0xfe023c00) +#define MIPI_BL_FR_PING_ADDR1_ST ((0x0002 << 2) + 0xfe023c00) +#define MIPI_BL_FR_PING_ADDR1_ED ((0x0003 << 2) + 0xfe023c00) +#define MIPI_BL_FR_PONG_ADDR0_ST ((0x0004 << 2) + 0xfe023c00) +#define MIPI_BL_FR_PONG_ADDR0_ED ((0x0005 << 2) + 0xfe023c00) +#define MIPI_BL_FR_PONG_ADDR1_ST ((0x0006 << 2) + 0xfe023c00) +#define MIPI_BL_FR_PONG_ADDR1_ED ((0x0007 << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_TH ((0x0008 << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR0 ((0x0009 << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_SIZE0 ((0x000a << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_BUF_SIZE0 ((0x000b << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR1 ((0x000c << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_SIZE1 ((0x000d << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_BUF_SIZE1 ((0x000e << 2) + 0xfe023c00) +#define MIPI_BL_FR_CTRL0 ((0x000f << 2) + 0xfe023c00) +#define MIPI_BL_FR_CTRL1 ((0x0010 << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_COUNT ((0x0011 << 2) + 0xfe023c00) +#define MIPI_BL_FR_AWADDR_O ((0x0012 << 2) + 0xfe023c00) +#define MIPI_BL_FR_AWADDR_I ((0x0013 << 2) + 0xfe023c00) +#define MIPI_BL_FR_STAT0 ((0x0014 << 2) + 0xfe023c00) +#define MIPI_BL_FR_STAT1 ((0x0015 << 2) + 0xfe023c00) +#define MIPI_BL_FR_STAT2 ((0x0016 << 2) + 0xfe023c00) +#define MIPI_BL_FR_STAT3 ((0x0017 << 2) + 0xfe023c00) +#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR0P ((0x0018 << 2) + 0xfe023c00) +#define MIPI_BL_DS_PING_ADDR0_ST ((0x0020 << 2) + 0xfe023c00) +#define MIPI_BL_DS_PING_ADDR0_ED ((0x0021 << 2) + 0xfe023c00) +#define MIPI_BL_DS_PING_ADDR1_ST ((0x0022 << 2) + 0xfe023c00) +#define MIPI_BL_DS_PING_ADDR1_ED ((0x0023 << 2) + 0xfe023c00) +#define MIPI_BL_DS_PONG_ADDR0_ST ((0x0024 << 2) + 0xfe023c00) +#define MIPI_BL_DS_PONG_ADDR0_ED ((0x0025 << 2) + 0xfe023c00) +#define MIPI_BL_DS_PONG_ADDR1_ST ((0x0026 << 2) + 0xfe023c00) +#define MIPI_BL_DS_PONG_ADDR1_ED ((0x0027 << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_TH ((0x0028 << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR0 ((0x0029 << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_SIZE0 ((0x002a << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_BUF_SIZE0 ((0x002b << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR1 ((0x002c << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_SIZE1 ((0x002d << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_BUF_SIZE1 ((0x002e << 2) + 0xfe023c00) +#define MIPI_BL_DS_CTRL0 ((0x002f << 2) + 0xfe023c00) +#define MIPI_BL_DS_CTRL1 ((0x0030 << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_COUNT ((0x0031 << 2) + 0xfe023c00) +#define MIPI_BL_DS_AWADDR_O ((0x0032 << 2) + 0xfe023c00) +#define MIPI_BL_DS_AWADDR_I ((0x0033 << 2) + 0xfe023c00) +#define MIPI_BL_DS_STAT0 ((0x0034 << 2) + 0xfe023c00) +#define MIPI_BL_DS_STAT1 ((0x0035 << 2) + 0xfe023c00) +#define MIPI_BL_DS_STAT2 ((0x0036 << 2) + 0xfe023c00) +#define MIPI_BL_DS_STAT3 ((0x0037 << 2) + 0xfe023c00) +#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR0P ((0x0038 << 2) + 0xfe023c00) +#define MIPI_BL_WF_PING_ADDR0_ST ((0x0040 << 2) + 0xfe023c00) +#define MIPI_BL_WF_PING_ADDR0_ED ((0x0041 << 2) + 0xfe023c00) +#define MIPI_BL_WF_PING_ADDR1_ST ((0x0042 << 2) + 0xfe023c00) +#define MIPI_BL_WF_PING_ADDR1_ED ((0x0043 << 2) + 0xfe023c00) +#define MIPI_BL_WF_PONG_ADDR0_ST ((0x0044 << 2) + 0xfe023c00) +#define MIPI_BL_WF_PONG_ADDR0_ED ((0x0045 << 2) + 0xfe023c00) +#define MIPI_BL_WF_PONG_ADDR1_ST ((0x0046 << 2) + 0xfe023c00) +#define MIPI_BL_WF_PONG_ADDR1_ED ((0x0047 << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_TH ((0x0048 << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR0 ((0x0049 << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_SIZE0 ((0x004a << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_BUF_SIZE0 ((0x004b << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR1 ((0x004c << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_SIZE1 ((0x004d << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_BUF_SIZE1 ((0x004e << 2) + 0xfe023c00) +#define MIPI_BL_WF_CTRL0 ((0x004f << 2) + 0xfe023c00) +#define MIPI_BL_WF_CTRL1 ((0x0050 << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_COUNT ((0x0051 << 2) + 0xfe023c00) +#define MIPI_BL_WF_AWADDR_O ((0x0052 << 2) + 0xfe023c00) +#define MIPI_BL_WF_AWADDR_I ((0x0053 << 2) + 0xfe023c00) +#define MIPI_BL_WF_STAT0 ((0x0054 << 2) + 0xfe023c00) +#define MIPI_BL_WF_STAT1 ((0x0055 << 2) + 0xfe023c00) +#define MIPI_BL_WF_STAT2 ((0x0056 << 2) + 0xfe023c00) +#define MIPI_BL_WF_STAT3 ((0x0057 << 2) + 0xfe023c00) +#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR0P ((0x0058 << 2) + 0xfe023c00) +// +// Closing file: mipi_isp.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ./REG_LIST_RTL.h +// +#include "soc_def.h" +#endif // REGISTER_H +
diff --git a/arch/arm/include/asm/arch-c2/regs.h b/arch/arm/include/asm/arch-c2/regs.h new file mode 100644 index 0000000..df35fed --- /dev/null +++ b/arch/arm/include/asm/arch-c2/regs.h
@@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_REG_H__ +#define __AML_REG_H__ +/* + * all used regs + */ +/* +#define SYSCTRL_TIMERE_CTRL ((0x0040 << 2) + 0xfe005800) +#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe000000) +#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe000000) + */ +#define ISA_TIMERE ((0x0041 << 2) + 0xfe005800) +#define WATCHDOG_CNTL ((0x0040 << 2) + 0xfe000000) +#define WATCHDOG_TCNT ((0x0042 << 2) + 0xfe000000) +#define WATCHDOG_RST ((0x0043 << 2) + 0xfe000000) + +/* + * SEC_AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4 + * AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4 + * AO_RTI_STATUS_REG3 use SYSCTRL_SEC_STICKY_REG1 + * AO_SEC_SD_CFG15 use SYSCTRL_SEC_STATUS_REG2 + */ +#define SEC_AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800) +#define AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800) +#define AO_RTI_STATUS_REG3 ((0x00e1 << 2) + 0xfe005800) +#define AO_SEC_SD_CFG15 ((0x00c2 << 2) + 0xfe005800) + +/* PREG_STICKY_REG8 use SYSCTRL_STICKY_REG7 + * P_AO_SEC_GP_CFG12 use SYSCTRL_DEBUG_REG6 + * P_AO_SEC_GP_CFG13 use SYSCTRL_DEBUG_REG7 + */ +#define PREG_STICKY_REG8 ((0x00b7 << 2) + 0xfe005800) +#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)((0x0096 << 2) + 0xfe005800) +#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)((0x0097 << 2) + 0xfe005800) + +/* + * P_AO_RTI_PINMUX_REG0 use PADCTRL_PIN_MUX_REG0 + * P_AO_TIMEBASE_CNTL1 use CLKTREE_TIMEBASE_CTRL1 + * AO_UART_WFIFO use UART_B_WFIFO + */ +#define P_AO_RTI_PINMUX_REG0 ((0x0000 << 2) + 0xfe000400) +#define P_AO_TIMEBASE_CNTL1 ((0x0016 << 2) + 0xfe000800) +#define AO_UART_WFIFO ((0x0000 << 2) + 0xfe002000) + +/* + * Not AO watch dog + */ +#define P_WATCHDOG_CNTL (volatile uint32_t *)(WATCHDOG_CNTL) +#define P_WATCHDOG_TCNT (volatile uint32_t *)(WATCHDOG_TCNT) +#define P_WATCHDOG_RST (volatile uint32_t *)(WATCHDOG_RST) +#define P_ISA_TIMERE (volatile uint32_t *)(ISA_TIMERE) + +#endif /* __AML_REG_H__ */
diff --git a/arch/arm/include/asm/arch-c2/romboot.h b/arch/arm/include/asm/arch-c2/romboot.h new file mode 100644 index 0000000..2967fbb --- /dev/null +++ b/arch/arm/include/asm/arch-c2/romboot.h
@@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOOT_ROM_H_ +#define __BOOT_ROM_H_ +#ifndef __ASSEMBLY__ +//#include <stdint.h> +//uint8_t simple_i2c(uint8_t adr); +//void spi_pin_mux(void); +//void spi_init(void); +//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size); +//void udelay(uint32_t usec); +//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size); + +#endif /* ! __ASSEMBLY__ */ +#include "config.h" + +/* Magic number to "boot" up A53 */ +#define AO_SEC_SD_CFG10_CB 0x80000000 + +/*BOOT device and ddr size*/ +/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/ +/*19-8: ddr size, 7-0: board revision*/ +//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h +#define AO_SEC_GP_CFG7_W0_BIT 8 +#define AO_SEC_GP_CFG7_W0 0x100 + +#define BOOT_ID_RESERVED 0 +#define BOOT_ID_EMMC 1 +#define BOOT_ID_NAND 2 +#define BOOT_ID_SPI 3 +#define BOOT_ID_SDCARD 4 +#define BOOT_ID_USB 5 + +#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-c2/sd_emmc.h b/arch/arm/include/asm/arch-c2/sd_emmc.h new file mode 100644 index 0000000..82d4fb2 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/sd_emmc.h
@@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __SD_EMMC_H__ +#define __SD_EMMC_H__ + +#include <mmc.h> + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ +#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ + +#define MESON_SD_EMMC_CLOCK 0x00 +#define CLK_MAX_DIV GENMASK(5, 0) +#define CLK_MAX_SRC GENMASK(7, 6) +#define Cfg_div 0 +#define Cfg_src 6 +#define Cfg_co_phase 8 +#define Cfg_tx_phase 10 +#define Cfg_rx_phase 12 +#define Cfg_sram_pd 14 +#define Cfg_tx_delay 16 +#define Cfg_rx_delay 22 +#define Cfg_always_on 28 +#define Cfg_irq_sdio_sleep 29 +#define Cfg_irq_sdio_sleep_ds 30 + +#define MESON_SD_EMMC_DELAY1 0x4 +#define DLY_D0_MASK GENMASK(5, 0) +#define DLY_D1_MASK GENMASK(11, 6) +#define DLY_D2_MASK GENMASK(17, 12) +#define DLY_D3_MASK GENMASK(23, 18) +#define DLY_D4_MASK GENMASK(31, 24) +#define Dly_d0 0 +#define Dly_d1 6 +#define Dly_d2 12 +#define Dly_d3 18 +#define Dly_d4 24 + +#define MESON_SD_EMMC_DELAY2 0x8 +#define DLY_D5_MASK GENMASK(5, 0) +#define DLY_D6_MASK GENMASK(11, 6) +#define DLY_D7_MASK GENMASK(17, 12) +#define DLY_D8_MASK GENMASK(23, 18) +#define DLY_D9_MASK GENMASK(31, 24) +#define Dly_d5 0 +#define Dly_d6 6 +#define Dly_d7 12 +#define Dly_d8 18 +#define Dly_d9 24 + +#define MESON_SD_EMMC_ADJUST 0xC +#define CALI_SEL_MASK GENMASK(11, 8) +#define ADJ_DLY_MASK GENMASK(21, 16) +#define Cfg_cali_sel 8 +#define Cfg_cali_en 12 +#define Cfg_adj_en 13 +#define Cfg_cali_rise 14 +#define Cfg_ds_en 15 +#define Cfg_adj_dly 16 +#define Cfg_adj_auto 22 +#define Cfg_adj_init 23 + +#define MESON_SD_EMMC_START 0x40 +#define CFG_DESC_INIT BIT(0) +#define CFG_DESC_BUSY BIT(1) +#define CFG_DESC_ADDR 2 + +#define MESON_SD_EMMC_CFG 0x44 +#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) +#define CFG_BUS_WIDTH_1 0 +#define CFG_BUS_WIDTH_4 1 +#define CFG_BUS_WIDTH_8 2 +#define CFG_DDR BIT(2) +#define CFG_BL_LEN_MASK GENMASK(7, 4) +#define CFG_BL_LEN_SHIFT 4 +#define CFG_BL_LEN_512 (9 << 4) +#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) +#define CFG_RESP_TIMEOUT_256 (8 << 8) +#define CFG_RC_CC_MASK GENMASK(15, 12) +#define CFG_RC_CC_16 (4 << 12) +#define CFG_SDCLK_ALWAYS_ON BIT(18) +#define CFG_AUTO_CLK BIT(23) + +#define MESON_SD_EMMC_STATUS 0x48 +#define STATUS_MASK GENMASK(15, 0) +#define STATUS_ERR_MASK GENMASK(12, 0) +#define STATUS_RXD_ERR_MASK GENMASK(7, 0) +#define STATUS_TXD_ERR BIT(8) +#define STATUS_DESC_ERR BIT(9) +#define STATUS_RESP_ERR BIT(10) +#define STATUS_RESP_TIMEOUT BIT(11) +#define STATUS_DESC_TIMEOUT BIT(12) +#define STATUS_END_OF_CHAIN BIT(13) + +#define MESON_SD_EMMC_IRQ_EN 0x4c + +#define MESON_SD_EMMC_CMD_CFG 0x50 +#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) +#define CMD_CFG_BLOCK_MODE BIT(9) +#define CMD_CFG_R1B BIT(10) +#define CMD_CFG_END_OF_CHAIN BIT(11) +#define CMD_CFG_TIMEOUT_4S (12 << 12) +#define CMD_CFG_NO_RESP BIT(16) +#define CMD_CFG_NO_CMD BIT(17) +#define CMD_CFG_DATA_IO BIT(18) +#define CMD_CFG_DATA_WR BIT(19) +#define CMD_CFG_RESP_NOCRC BIT(20) +#define CMD_CFG_RESP_128 BIT(21) +#define CMD_CFG_RESP_NUM BIT(22) +#define CMD_CFG_DATA_NUM BIT(23) +#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) +#define CMD_CFG_CMD_INDEX_SHIFT 24 +#define CMD_CFG_ERR BIT(30) +#define CMD_CFG_OWNER BIT(31) + +#define MESON_SD_EMMC_CMD_ARG 0x54 +#define MESON_SD_EMMC_CMD_DAT 0x58 +#define MESON_SD_EMMC_CMD_RSP 0x5c +#define MESON_SD_EMMC_CMD_RSP1 0x60 +#define MESON_SD_EMMC_CMD_RSP2 0x64 +#define MESON_SD_EMMC_CMD_RSP3 0x68 + +#define SD_EMMC_RXD_ERROR (1 << 0) +#define SD_EMMC_TXD_ERROR (1 << 1) +#define SD_EMMC_DESC_ERROR (1 << 2) +#define SD_EMMC_RESP_CRC_ERROR (1 << 3) +#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4) +#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5) + +//boot from sd or emmc +#define SEC_AO_SEC_GP_CFG0 (SYSCTRL_SEC_STATUS_REG4) +#endif
diff --git a/arch/arm/include/asm/arch-c2/secure_apb.h b/arch/arm/include/asm/arch-c2/secure_apb.h new file mode 100644 index 0000000..075812b --- /dev/null +++ b/arch/arm/include/asm/arch-c2/secure_apb.h
@@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/regs.h> +#include <asm/arch/register.h> + +#define DMA_T0 (uint32_t)(0xfe006000 + 0x00) +#define DMA_T1 (uint32_t)(0xfe006000 + 0x04) +#define DMA_T2 (uint32_t)(0xfe006000 + 0x08) +#define DMA_T3 (uint32_t)(0xfe006000 + 0x0c) +#define DMA_T4 (uint32_t)(0xfe006000 + 0x10) +#define DMA_T5 (uint32_t)(0xfe006000 + 0x14) +#define DMA_STS0 (uint32_t)(0xfe006000 + 0x20) +#define DMA_STS1 (uint32_t)(0xfe006000 + 0x24) +#define DMA_STS2 (uint32_t)(0xfe006000 + 0x28) +#define DMA_STS3 (uint32_t)(0xfe006000 + 0x2c) +#define DMA_STS4 (uint32_t)(0xfe006000 + 0x30) +#define DMA_STS5 (uint32_t)(0xfe006000 + 0x34) +#define DMA_CFG (uint32_t)(0xfe006000 + 0x40) +#define DMA_SEC (uint32_t)(0xfe006000 + 0x44) +#define DMA_END (uint32_t)(0xfe006000 + 0x3ff) + +#define P_DMA_T0 (volatile uint32_t *)(0xfe006000 + 0x00) +#define P_DMA_T1 (volatile uint32_t *)(0xfe006000 + 0x04) +#define P_DMA_T2 (volatile uint32_t *)(0xfe006000 + 0x08) +#define P_DMA_T3 (volatile uint32_t *)(0xfe006000 + 0x0c) +#define P_DMA_T4 (volatile uint32_t *)(0xfe006000 + 0x10) +#define P_DMA_T5 (volatile uint32_t *)(0xfe006000 + 0x14) +#define P_DMA_STS0 (volatile uint32_t *)(0xfe006000 + 0x20) +#define P_DMA_STS1 (volatile uint32_t *)(0xfe006000 + 0x24) +#define P_DMA_STS2 (volatile uint32_t *)(0xfe006000 + 0x28) +#define P_DMA_STS3 (volatile uint32_t *)(0xfe006000 + 0x2c) +#define P_DMA_STS4 (volatile uint32_t *)(0xfe006000 + 0x30) +#define P_DMA_STS5 (volatile uint32_t *)(0xfe006000 + 0x34) +#define P_DMA_CFG (volatile uint32_t *)(0xfe006000 + 0x40) +#define P_DMA_SEC (volatile uint32_t *)(0xfe006000 + 0x44) + +/* for A/B system */ +#define P_AO_RTI_STICKY_REG0 SYSCTRL_STICKY_REG6 +#define P_AO_RTI_STICKY_REG1 SYSCTRL_STICKY_REG7
diff --git a/arch/arm/include/asm/arch-c2/soc_def.h b/arch/arm/include/asm/arch-c2/soc_def.h new file mode 100644 index 0000000..3a1af9a --- /dev/null +++ b/arch/arm/include/asm/arch-c2/soc_def.h
@@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __C2_DEF_H__ +#define __C2_DEF_H__ + +#define SEC_AO_SEC_GP_CFG2 (SYSCTRL_SEC_STATUS_REG6) + +#endif /* __C2_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-c2/timer.h b/arch/arm/include/asm/arch-c2/timer.h new file mode 100644 index 0000000..492cc8d --- /dev/null +++ b/arch/arm/include/asm/arch-c2/timer.h
@@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TIMER_H +#define __TIMER_H + +#include <asm/arch/romboot.h> +#include <asm/arch/timer.h> +#include <asm/arch/io.h> + +/** + * Get the current timestamp from the system timer. + */ +uint32_t get_time(void); + +/** + * Busy-wait. + * + * @param us Number of microseconds to delay. + */ +void _udelay(unsigned int us); + +#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-c2/timing.h b/arch/arm/include/asm/arch-c2/timing.h new file mode 100644 index 0000000..04b27f6 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/timing.h
@@ -0,0 +1,342 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_TIMING_H_ +#define __AML_TIMING_H_ + +#include <asm/arch/ddr_define.h> +//#include <asm/arch/types.h> + +#define BL2_INIT_STAGE_0 0 +#define BL2_INIT_STAGE_1 1 +#define BL2_INIT_STAGE_2 2 +#define BL2_INIT_STAGE_3 3 +#define BL2_INIT_STAGE_4 4 +#define BL2_INIT_STAGE_5 5 +#define BL2_INIT_STAGE_6 6 +#define BL2_INIT_STAGE_7 7 +#define BL2_INIT_STAGE_8 8 +#define BL2_INIT_STAGE_9 9 + +#define BL2_INIT_STAGE_PWM_PRE_INIT 0x81 +#define BL2_INIT_STAGE_PWM_CHK_HW 0x82 +#define BL2_INIT_STAGE_PWM_CFG_GROUP 0x83 +#define BL2_INIT_STAGE_PWM_INIT 0xC0 +/*bl2 efuse val flag*/ +#define BL2_INIT_STAGE_VDDCORE_CONFIG_1 0x84 +#define BL2_INIT_STAGE_VDDCORE_CONFIG_2 0x85 +#define BL2_INIT_STAGE_VDDCORE_CONFIG_3 0x86 + +#define BL2_INIT_STAGE_I2C_REGULATOR 0xD0 + +typedef struct bl2_reg { + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; +}__attribute__ ((packed)) bl2_reg_t; + +typedef struct ddr_reg { + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned short udelay; + unsigned char flag; + unsigned char rsv_0; +}__attribute__ ((packed)) ddr_reg_t; + +typedef struct training_delay_set_ps{ + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; +// */ + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + ///* + unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; +// unsigned short rever2; +}__attribute__ ((packed)) training_delay_set_ps_t; + +typedef struct ddr_mrs_reg { + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; +}__attribute__ ((packed)) ddr_mrs_reg_t; + +typedef struct ddr_timing{ + unsigned int identifier; + unsigned int cfg_ddr_mrd; + unsigned int cfg_ddr_rfcab; + unsigned int cfg_ddr_rfcpb; + unsigned int cfg_ddr_rpab; + unsigned int cfg_ddr_rppb; + unsigned int cfg_ddr_rtw; + unsigned int cfg_ddr_rl; + unsigned int cfg_ddr_wl; + unsigned int cfg_ddr_ras; + unsigned int cfg_ddr_rc; + unsigned int cfg_ddr_rcd; + unsigned int cfg_ddr_rrds; + unsigned int cfg_ddr_rrdl; + unsigned int cfg_ddr_faw; + unsigned int cfg_ddr_rtp; + unsigned int cfg_ddr_wr; + unsigned int cfg_ddr_wtrs; + unsigned int cfg_ddr_wtrl; + unsigned int cfg_ddr_ccds; + unsigned int cfg_ddr_ccdl; + unsigned int cfg_ddr_exsr; + unsigned int cfg_ddr_xs; + unsigned int cfg_ddr_xp; + unsigned int cfg_ddr_xpdll; + unsigned int cfg_ddr_zqcs; + unsigned int cfg_ddr_cksre; + unsigned int cfg_ddr_cksrx; + unsigned int cfg_ddr_cke; + unsigned int cfg_ddr_mod; + unsigned int cfg_ddr_dqs; + unsigned int cfg_ddr_rstl; + unsigned int cfg_ddr_zqlat; + unsigned int cfg_ddr_mrr; + unsigned int cfg_ddr_ckesr; + unsigned int cfg_ddr_dpd; + unsigned int cfg_ddr_ckeck; + unsigned int cfg_ddr_refi; + unsigned int cfg_ddr_sr; + unsigned int cfg_ddr_ccdmw; + unsigned int cfg_ddr_escke; + unsigned int cfg_ddr_refi_ddr3; + unsigned int cfg_ddr_dfictrldelay; + unsigned int cfg_ddr_dfiphywrdata; + unsigned int cfg_ddr_dfiphywrlat; + unsigned int cfg_ddr_dfiphyrddataen; + unsigned int cfg_ddr_dfiphyrdlat; + unsigned int cfg_ddr_dfictrlupdmin; + unsigned int cfg_ddr_dfictrlupdmax; + unsigned int cfg_ddr_dfimstrresp; + unsigned int cfg_ddr_dfirefmski; + unsigned int cfg_ddr_dfictrlupdi; + unsigned int cfg_ddr_dfidramclk; + unsigned int cfg_ddr_dfilpresp; + unsigned int cfg_ddr_dfiphymstr; + unsigned int cfg_ddr_rtodt; + unsigned int cfg_ddr_wlmrd; + unsigned int cfg_ddr_wlo; + unsigned int cfg_ddr_al; + unsigned int cfg_ddr_zqcl; + unsigned int cfg_ddr_zqcsi; + unsigned int cfg_ddr_zqreset; + unsigned int cfg_ddr_tdqsck_min; + unsigned int cfg_ddr_tdqsck_max; + //training_delay_set_ps_t cfg_ddr_training_delay_ps; + ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2]; + unsigned int dfi_odt1_config_ps[2]; + //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1; + #if 0 + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; + unsigned int cfg_ddr_reserve[5]; + #endif +}__attribute__ ((packed)) ddr_timing_t; + +typedef struct board_common_setting +{ +unsigned int timming_magic; +unsigned short timming_max_valid_configs; +unsigned short timming_struct_version; +unsigned short timming_struct_org_size; +unsigned short timming_struct_real_size; +unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test enable +unsigned int ddr_func; +unsigned char board_id; +unsigned char DramType; +unsigned char dram_rank_config; +unsigned char DisabledDbyte; +unsigned int dram_cs0_base_add; +unsigned int dram_cs1_base_add; +unsigned short dram_cs0_size_MB; +unsigned short dram_cs1_size_MB; +unsigned char dram_x4x8x16_mode; +unsigned char Is2Ttiming; +unsigned char log_level; +unsigned char ddr_rdbi_wr_enable; +unsigned int pll_ssc_mode; +unsigned short org_tdqs2dq; +unsigned char reserve1_test_function[2]; +unsigned int ddr_dmc_remap[5]; +unsigned char ac_pinmux[35]; +unsigned char ddr_dqs_swap; +unsigned char ddr_dq_remap[36]; +unsigned int ddr_vddee_setting[4];//add,default-value,default-voltage,step +}__attribute__ ((packed)) board_common_setting_t; +typedef struct board_SI_setting_ps +{ +unsigned short DRAMFreq; +unsigned char PllBypassEn; +unsigned char training_SequenceCtrl; +unsigned short ddr_odt_config; +unsigned char clk_drv_ohm; +unsigned char cs_drv_ohm; +unsigned char ac_drv_ohm; +unsigned char soc_data_drv_ohm_p; +unsigned char soc_data_drv_ohm_n; +unsigned char soc_data_odt_ohm_p; +unsigned char soc_data_odt_ohm_n; +unsigned char dram_data_drv_ohm; +unsigned char dram_data_odt_ohm; +unsigned char dram_data_wr_odt_ohm; +unsigned char dram_ac_odt_ohm; +unsigned char dram_data_drv_pull_up_calibration_ohm; +unsigned char lpddr4_dram_vout_voltage_range_setting; +unsigned char reserve2; +unsigned short vref_ac_permil; //phy +unsigned short vref_soc_data_permil; //soc +unsigned short vref_dram_data_permil; +unsigned short max_core_timmming_frequency; +unsigned short training_phase_parameter[2]; +unsigned short ac_trace_delay_org[36]; +}__attribute__ ((packed)) board_SI_setting_ps_t; +typedef struct board_phase_setting_ps +{ +unsigned short ac_trace_delay[36]; +unsigned short write_dqs_delay[8]; +unsigned short write_dq_bit_delay[72]; +unsigned short read_dqs_gate_delay[8]; +unsigned char read_dqs_delay[8]; +unsigned char read_dq_bit_delay[72]; +unsigned char soc_bit_vref[44]; +unsigned char dram_bit_vref[36]; +unsigned char reserve_training_parameter[16];//0-7 read dqs offset,8-15 write dqs offset,MSB bit 7 use 0 mean right offset +}__attribute__ ((packed)) board_phase_setting_ps_t; +typedef struct ddr_set +{ +board_common_setting_t cfg_board_common_setting; +board_SI_setting_ps_t cfg_board_SI_setting_ps[2]; +board_phase_setting_ps_t cfg_ddr_training_delay_ps[2]; +}__attribute__ ((packed)) ddr_set_t; + + +#if 0 + #define DDR_FW_TOTAL_OFFSET 0 + #define DDR_FW_TOTAL_SIZE 2 + #define DDR_FW_TOTAL_VERSION 3 + #define DDR_FW_BIN_OFFSET 4 + #define DDR_FW_BIN_SIZE 6 + #define DDR_FW_VERSION 7 + #define DDR_ACS_BIN_OFFSET 8 + #define DDR_ACS_BIN_SIZE 10 + #define DDR_ACS_VERSION 11 + #define DDR_FAST_BOOT_DATA_OFFSET 12 + #define DDR_FAST_BOOT_DATA_SIZE 14 + #define DDR_FAST_BOOT_DATA_VERSION 15 + #define DDR_STICKY_REG_ADD_OFFSET 16 + #define DDR_STICKY_REG_SIZE_OFFSET 18 + #define DDR_STICKY_REG_VERSION_OFFSET 19 + + //#define DDR_FW_HEAD_SIZE (32<<2)//>96 + //#define DDR_BL2_DDR_FW_HEAD_SIZE 256 + typedef struct ddr_fw_head_struct{ + + uint32_t ddr_all_fw_add; + uint32_t ddr_all_fw_size; + uint32_t ddr_all_fw_version; + + uint32_t ddr_fw_add; + uint32_t ddr_fw_size; + uint32_t ddr_fw_version; + + uint32_t ddr_acs_bin_add; + uint32_t ddr_acs_bin_size; + uint32_t ddr_acs_bin_version; + + uint32_t ddr_fast_boot_data_add; + uint32_t ddr_fast_boot_data_size; + uint32_t ddr_fast_boot_data_version; + + uint32_t ddr_sticky_add; + uint32_t ddr_sticky_size; + uint32_t ddr_sticky_version; + + //void (*log_info)(log_chl chl,const char *fmt, ...); + int (*serial_puts)(const char *s); + void (*serial_put_hex)(unsigned long data, int bitlen); + void (*ddr_init_return)(void); + + uint32_t ddr_bl2_ddr_fw_mail_message[12]; + + } ddr_fw_head_struct_t; +#endif +typedef struct pll_ctrl { + unsigned short delay_u; + unsigned short flag; + unsigned int clkset; + unsigned int pll_para[10]; + unsigned int reserve; + +}__attribute__ ((packed)) pll_ctrl_t; + +typedef struct pll_set_new { + pll_ctrl_t sys_pll_ctrl; + pll_ctrl_t fix_pll_cntl; + pll_ctrl_t gp0_pll_cntl; + pll_ctrl_t gp1_pll_cntl; + pll_ctrl_t hifi_pll_cntl; + +}__attribute__ ((packed)) pll_set_t_new; + +typedef struct pll_set{ + unsigned short cpu_clk; + unsigned short pxp; + unsigned int spi_ctrl; + unsigned short vddee; + unsigned short vcck; + unsigned char szPad[4]; + + unsigned long long lCustomerID; + unsigned char debug_mode; + unsigned char log_chl; + unsigned char log_ctrl; + unsigned char ddr_timming_save_mode; + unsigned int nCFGTAddr; + /* align 8Byte */ + + pll_set_t_new pll_struct; +}__attribute__ ((packed)) pll_set_t; + +typedef struct dwc_apb { + unsigned int addr; + unsigned short val; +} dwc_apb_t; + +#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-c2/tsensor.h b/arch/arm/include/asm/arch-c2/tsensor.h new file mode 100644 index 0000000..c209b0c --- /dev/null +++ b/arch/arm/include/asm/arch-c2/tsensor.h
@@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TSENSOR_H__ +#define __TSENSOR_H__ + + +struct tsensor_cali_data { + unsigned int cmd; /* R/W */ + unsigned int offset; + unsigned int size; + unsigned long buffer_phy; + unsigned long retcnt_phy; +}; + + +#define CONFIG_HIGH_TEMP_COOL 90 + +#define T_AVG_NUM 16 /*read temp cnt*/ +#define T_VER_MASK 0x80 +#define T_VALUE_MIN 0x1500 +#define T_VALUE_MAX 0x3500 +#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/ + +#define T_CONTROL_DATA 0x62b +#define T_TSCLK_DATA 0x130 + +#define ts_b 3094 +#define ts_a 9700 +#define ts_m 360 +#define ts_n 260 + +#ifdef CONFIG_AML_TSENSOR +int temp_read_entry(void); +int temp_trim_entry(int tempbase, int tempver); +int temp_cooling_entry(void); +#else +int temp_read_entry(void) +{ + return -1; +} +int temp_trim_entry(int tempbase, int tempver) +{ + return -1; +} +int temp_cooling_entry(void) +{ + return 0; +} +#endif +#endif
diff --git a/arch/arm/include/asm/arch-c2/types.h b/arch/arm/include/asm/arch-c2/types.h new file mode 100644 index 0000000..2d362b1 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/types.h
@@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TYPES_H +#define __TYPES_H + +#ifndef _INT8_T_DECLARED +typedef char int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef short int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef int int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef long int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef unsigned char uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef unsigned short uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef unsigned int uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef unsigned long uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INT8PTR_T_DECLARED +typedef char * int8ptr_t; +#define _INT8PTR_T_DECLARED +#endif + +#ifndef _INT16PTR_T_DECLARED +typedef short * int16ptr_t; +#define _INT16PTR_T_DECLARED +#endif + +#ifndef _INT32PTR_T_DECLARED +typedef int * int32ptr_t; +#define _INT32PTR_T_DECLARED +#endif + +#ifndef _INT64PTR_T_DECLARED +typedef long * int64ptr_t; +#define _INT64PTR_T_DECLARED +#endif + +#ifndef _UINT8PTR_T_DECLARED +typedef unsigned char * uint8ptr_t; +#define _UINT8PTR_T_DECLARED +#endif + +#ifndef _UINT16PTR_T_DECLARED +typedef unsigned short * uint16ptr_t; +#define _UINT16PTR_T_DECLARED +#endif + +#ifndef _UINT32PTR_T_DECLARED +typedef unsigned int * uint32ptr_t; +#define _UINT32PTR_T_DECLARED +#endif + +#ifndef _UINT64PTR_T_DECLARED +typedef unsigned long * uint64ptr_t; +#define _UINT64PTR_T_DECLARED +#endif + +#endif \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c2/uart.h b/arch/arm/include/asm/arch-c2/uart.h new file mode 100644 index 0000000..757dc91 --- /dev/null +++ b/arch/arm/include/asm/arch-c2/uart.h
@@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MESON_FIRM_UART_H_ +#define __MESON_FIRM_UART_H_ +#include <config.h> +#include <common.h> +#include "register.h" +//#include "io.h" +#include <asm/arch/secure_apb.h> + +#ifndef CONFIG_CONS_INDEX +#error Please define CONFIG_CONS_INDEX==[0|1] +#endif + +#if CONFIG_CONS_INDEX==0 +#define UART_PORT_CONS UART_PORT_0 +#elif CONFIG_CONS_INDEX==1 +#define UART_PORT_CONS UART_PORT_1 +#elif CONFIG_CONS_INDEX==2 +#define UART_PORT_CONS UART_PORT_AO +#define USE_AO_UART 1 +#else +#error Please define CONFIG_CONS_INDEX==[0|1] +#endif +/* +#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO) +#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO) +#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO) +#define UART_PORT_AO P_AO_UART_WFIFO + +#define UART_WFIFO (0<<2) +#define UART_RFIFO (1<<2) +#define UART_CONTROL (2<<2) +#define UART_STATUS (3<<2) +#define UART_MISC (4<<2) +*/ + +#include "clock.h" + +#define UART_CLK_SRC CLK81 +#define UART_PORT_0 0xfe001c00 +#define UART_PORT_1 0xfe001c00 +#define UART_PORT_AO 0xfe001c00 +#define UART_WFIFO 0 +#define UART_RFIFO 1 +#define UART_CONTROL 2 +#define UART_STATUS 3 +#define UART_MISC 4 + +#if USE_AO_UART == 1 +#define P_UART(uart_base,reg) (uart_base + (reg<<2)) +#else +#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg) +#endif +#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO) +#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO) + +#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL) + #define UART_CNTL_MASK_BAUD_RATE (0xfff) + #define UART_CNTL_MASK_TX_EN (1<<12) + #define UART_CNTL_MASK_RX_EN (1<<13) + #define UART_CNTL_MASK_2WIRE (1<<15) + #define UART_CNTL_MASK_STP_BITS (3<<16) + #define UART_CNTL_MASK_STP_1BIT (0<<16) + #define UART_CNTL_MASK_STP_2BIT (1<<16) + #define UART_CNTL_MASK_PRTY_EVEN (0<<18) + #define UART_CNTL_MASK_PRTY_ODD (1<<18) + #define UART_CNTL_MASK_PRTY_TYPE (1<<18) + #define UART_CNTL_MASK_PRTY_EN (1<<19) + #define UART_CNTL_MASK_CHAR_LEN (3<<20) + #define UART_CNTL_MASK_CHAR_8BIT (0<<20) + #define UART_CNTL_MASK_CHAR_7BIT (1<<20) + #define UART_CNTL_MASK_CHAR_6BIT (2<<20) + #define UART_CNTL_MASK_CHAR_5BIT (3<<20) + #define UART_CNTL_MASK_RST_TX (1<<22) + #define UART_CNTL_MASK_RST_RX (1<<23) + #define UART_CNTL_MASK_CLR_ERR (1<<24) + #define UART_CNTL_MASK_INV_RX (1<<25) + #define UART_CNTL_MASK_INV_TX (1<<26) + #define UART_CNTL_MASK_RINT_EN (1<<27) + #define UART_CNTL_MASK_TINT_EN (1<<28) + #define UART_CNTL_MASK_INV_CTS (1<<29) + #define UART_CNTL_MASK_MASK_ERR (1<<30) + #define UART_CNTL_MASK_INV_RTS (1<<31) +#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS ) + #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0) + #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8) + #define UART_STAT_MASK_PRTY_ERR (1<<16) + #define UART_STAT_MASK_FRAM_ERR (1<<17) + #define UART_STAT_MASK_WFULL_ERR (1<<18) + #define UART_STAT_MASK_RFIFO_FULL (1<<19) + #define UART_STAT_MASK_RFIFO_EMPTY (1<<20) + #define UART_STAT_MASK_TFIFO_FULL (1<<21) + #define UART_STAT_MASK_TFIFO_EMPTY (1<<22) + #define UART_STAT_MASK_XMIT_BUSY (1<<25) + #define UART_STAT_MASK_RECV_BUSY (1<<26) +#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC ) + + +#ifndef CONFIG_SERIAL_STP_BITS +#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2 +#endif +#if CONFIG_SERIAL_STP_BITS==1 +#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT +#elif CONFIG_SERIAL_STP_BITS==2 +#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT +#else +#error CONFIG_SERIAL_STP_BITS wrong +#endif + + +#ifndef CONFIG_SERIAL_PRTY_TYPE +#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3 +#endif +#if CONFIG_SERIAL_PRTY_TYPE==0 +#define UART_PRTY_BIT 0 +#elif CONFIG_SERIAL_PRTY_TYPE==2 +#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN) +#elif CONFIG_SERIAL_PRTY_TYPE==3 +#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD) +#else +#error CONFIG_SERIAL_PRTY_TYPE wrong +#endif + +#ifndef CONFIG_SERIAL_CHAR_LEN +#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8 +#endif +#if CONFIG_SERIAL_CHAR_LEN==5 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT +#elif CONFIG_SERIAL_CHAR_LEN==6 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT +#elif CONFIG_SERIAL_CHAR_LEN==7 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT +#elif CONFIG_SERIAL_CHAR_LEN==8 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT +#else +#error CONFIG_SERIAL_CHAR_LEN wrong +#endif +#define UART_CONTROL_SET(baud,clk81) \ + (((clk81)/(baud*4) -1) \ + | UART_STP_BIT \ + | UART_PRTY_BIT \ + | UART_CHAR_LEN \ + | UART_CNTL_MASK_TX_EN \ + | UART_CNTL_MASK_RX_EN \ + | UART_CNTL_MASK_RST_TX \ + | UART_CNTL_MASK_RST_RX \ + | UART_CNTL_MASK_CLR_ERR ) +#endif
diff --git a/arch/arm/include/asm/arch-c2/usb.h b/arch/arm/include/asm/arch-c2/usb.h new file mode 100644 index 0000000..e75cebd --- /dev/null +++ b/arch/arm/include/asm/arch-c2/usb.h
@@ -0,0 +1,287 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__ +#define __ARCH_ARM_MESON_USB_H_U_BOOT__ + +#include <common.h> +#include <asm/types.h> +#include <asm/arch/io.h> +#include <asm/arch/secure_apb.h> +#include <generic-phy.h> +#include <asm-generic/gpio.h> + +#define HOST_MODE 0 +#define DEVICE_MODE 1 + +#define USB_PHY_PORT_MAX 1 +/* Phy register MACRO definitions */ + +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) + +#define PHYUTMI_OTGDISABLE (1 << 6) +#define PHYUTMI_FORCESUSPEND (1 << 1) +#define PHYUTMI_FORCESLEEP (1 << 0) + +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) +#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) + +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) +#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) + +#define PHYCLKRST_SSC_EN (0x1 << 20) +#define PHYCLKRST_REF_SSP_EN (0x1 << 19) +#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) + +#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) + +#define PHYCLKRST_FSEL_MASK (0x3f << 5) +#define PHYCLKRST_FSEL(_x) ((_x) << 5) +#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) +#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) +#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) +#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) + +#define PHYCLKRST_RETENABLEN (0x1 << 4) + +#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) + +#define PHYCLKRST_PORTRESET (0x1 << 1) +#define PHYCLKRST_COMMONONN (0x1 << 0) + +#define PHYPARAM0_REF_USE_PAD (0x1 << 31) +#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) +#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) + +#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) +#define PHYPARAM1_PCS_TXDEEMPH (0x1c) + +#define PHYTEST_POWERDOWN_SSP (0x1 << 3) +#define PHYTEST_POWERDOWN_HSP (0x1 << 2) + +#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) + +#define FSEL_CLKSEL_24M (0x5) + +#define USB_PHY2_ENABLE (0x1 << 1) +#define USB_PHY2_RESET (0x1 << 0) +#define USBPLL_LK_OD_EN (0x1 << 16) +#define USBPLL_LOCKFLAG_BIT (31) + + +/* XHCI PHY register structure */ +#define PHY_REGISTER_SIZE 0x20 + +struct phy_aml_usb2_priv { + unsigned int base_addr; + unsigned int reset_addr; + unsigned int dwc2_a_addr; + unsigned int u2_port_num; + unsigned int usbphy_reset_bit[8]; + unsigned int clktree_usb_bus_ctrl_addr; + unsigned int usb_phy2_pll_base_addr[4]; +}; + +struct phy_aml_usb3_priv { + unsigned int base_addr; + unsigned int usb3_port_num; + struct gpio_desc desc; +}; + +/* Register definitions */ +typedef struct u2p_aml_regs { + volatile uint32_t u2p_r0; + volatile uint32_t u2p_r1; +} u2p_aml_regs_t; + +typedef union u2p_r0 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned host_device:1; + unsigned power_ok:1; + unsigned hast_mode:1; + unsigned POR:1; + unsigned IDPULLUP0:1; + unsigned DRVVBUS0:1; + unsigned reserved:26; + } b; +} u2p_r0_t; + +typedef union u2p_r1 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned phy_rdy:1; + unsigned IDDIG0:1; + unsigned OTGSESSVLD0:1; + unsigned VBUSVALID0:1; + unsigned reserved:28; + } b; +} u2p_r1_t; + + +typedef struct usb_aml_regs { + volatile uint32_t usb_r0; + volatile uint32_t usb_r1; + volatile uint32_t usb_r2; + volatile uint32_t usb_r3; + volatile uint32_t usb_r4; + volatile uint32_t usb_r5; +} usb_aml_regs_t; + +typedef union usb_r0 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved:17; + unsigned p30_lane0_tx2rx_loopback:1; + unsigned p30_lane0_ext_pclk_reg:1; + unsigned p30_pcs_rx_los_mask_val:10; + unsigned u2d_ss_scaledown_mode:2; + unsigned u2d_act:1; + } b; +} usb_r0_t; + +typedef union usb_r1 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned u3h_bigendian_gs:1; + unsigned u3h_pme_en:1; + unsigned u3h_hub_port_overcurrent:3; + unsigned reserved_1:2; + unsigned u3h_hub_port_perm_attach:3; + unsigned reserved_2:2; + unsigned u3h_host_u2_port_disable:2; + unsigned reserved_3:2; + unsigned u3h_host_u3_port_disable:1; + unsigned u3h_host_port_power_control_present:1; + unsigned u3h_host_msi_enable:1; + unsigned u3h_fladj_30mhz_reg:6; + unsigned p30_pcs_tx_swing_full:7; + } b; +} usb_r1_t; + +typedef union usb_r2 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved:20; + unsigned p30_pcs_tx_deemph_3p5db:6; + unsigned p30_pcs_tx_deemph_6db:6; + } b; +} usb_r2_t; + +typedef union usb_r3 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned p30_ssc_en:1; + unsigned p30_ssc_range:3; + unsigned p30_ssc_ref_clk_sel:9; + unsigned p30_ref_ssp_en:1; + unsigned reserved:18; + } b; +} usb_r3_t; + +typedef union usb_r4 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned p21_PORTRESET0:1; + unsigned p21_SLEEPM0:1; + unsigned mem_pd:2; + unsigned p21_only:1; + unsigned reserved:27; + } b; +} usb_r4_t; + +typedef union usb_r5 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned iddig_sync:1; + unsigned iddig_reg:1; + unsigned iddig_cfg:2; + unsigned iddig_en0:1; + unsigned iddig_en1:1; + unsigned iddig_curr:1; + unsigned usb_iddig_irq:1; + unsigned iddig_th:8; + unsigned iddig_cnt:8; + unsigned reserved:8; + } b; +} usb_r5_t; + +/* usb id mode, only after M2 + mode = 0 : HARDWARE + mode = 1 : SW_HOST + mode = 2 : SW_DEVICE + */ +#define USB_ID_MODE_HARDWARE (1) +#define USB_ID_MODE_SW_HOST (2) +#define USB_ID_MODE_SW_DEVICE (3) +int usb2_phy_tuning(uint32_t phy2_pll_base, int port); +void set_usb_pll(uint32_t phy2_pll_base); +int usb_save_phy_dev (unsigned int number, struct phy *phy); +int usb2_phy_init (struct phy *phy); +unsigned int usb_get_dwc_a_base_addr(void); +unsigned int usb_get_device_mode_phy_base(void); +void usb_phy_tuning_reset(void); +void usb_device_mode_init(void); + +/******************************************************/ +/* bc regist list */ +/******************************************************/ +typedef struct bc_reg_list { + volatile uint32_t bc_ctrl; + volatile uint32_t bc_status; + volatile uint32_t bc_otp; + volatile uint32_t bc_reg0; + volatile uint32_t bc_reg1; + volatile uint32_t bc_cnt_l; + volatile uint32_t bc_cnt_h; +} bc_reg_list_t; + +typedef union bc_ctrl { + uint32_t d32; + struct { + unsigned bc_det_clean:1; + unsigned bc_int_clean:1; + unsigned bc_en:1; + unsigned reserved:29; + } b; +} bc_ctrl_t; + +typedef union bc_status { + uint32_t d32; + struct { + unsigned bc_det_end:1; + unsigned port_status:4; + unsigned bc_state:3; + unsigned analog_out_signal:8; + unsigned reserved:16; + } b; +} bc_status_t; + +#endif
diff --git a/arch/arm/include/asm/arch-g12a/bl31_apis.h b/arch/arm/include/asm/arch-g12a/bl31_apis.h index 32ca95c..abe6c8d 100644 --- a/arch/arm/include/asm/arch-g12a/bl31_apis.h +++ b/arch/arm/include/asm/arch-g12a/bl31_apis.h
@@ -78,6 +78,17 @@ /*viu probe en*/ #define VIU_PREOBE_EN 0x82000080 + +/* KEYMASTER */ +#define SET_BOOT_PARAMS 0x82000072 +#define SHA256_DIGEST_SIZE 32 +typedef struct { + uint32_t device_locked; + uint32_t verified_boot_state; + uint8_t verified_boot_key[SHA256_DIGEST_SIZE]; + uint8_t verified_boot_hash[SHA256_DIGEST_SIZE]; +} keymaster_boot_params; + /* Secure HAL APIs */ #define TRUSTZONE_HAL_API_SRAM 0x400 @@ -100,6 +111,7 @@ #define JTAG_A53_EE 3 #define CLUSTER_BIT 2 +#define GET_AVBKEY_FROM_FIP 0x820000b0 ///////////////////////////////////////////////////////////////////////////////// #define AML_DATA_PROCESS (0x820000FF) @@ -133,4 +145,6 @@ void bl31_get_chipid(unsigned int *, unsigned int *, unsigned int *, unsigned int *); void set_viu_probe_enable(void); +int32_t set_boot_params(const keymaster_boot_params*); +int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen); #endif
diff --git a/arch/arm/include/asm/arch-g12a/cpu.h b/arch/arm/include/asm/arch-g12a/cpu.h index 9f66e3f..b381ee5 100644 --- a/arch/arm/include/asm/arch-g12a/cpu.h +++ b/arch/arm/include/asm/arch-g12a/cpu.h
@@ -21,7 +21,7 @@ #endif /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#define CONFIG_SYS_MALLOC_LEN (96*1024*1024) /* for uboot envrionment use */ /* #define CONFIG_DDR_SIZE 1024 */
diff --git a/arch/arm/include/asm/arch-g12a/regs.h b/arch/arm/include/asm/arch-g12a/regs.h index 80f4647..7978ec8 100644 --- a/arch/arm/include/asm/arch-g12a/regs.h +++ b/arch/arm/include/asm/arch-g12a/regs.h
@@ -13316,8 +13316,8 @@ #define P_WATCHDOG_CNTL1 (volatile unsigned int *)((0x3c35 << 2) + 0xffd00000) #define WATCHDOG_TCNT (0x3c36) #define P_WATCHDOG_TCNT (volatile unsigned int *)((0x3c36 << 2) + 0xffd00000) -#define WATCHDOG_RESET (0x3c37) -#define P_WATCHDOG_RESET (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000) +#define WATCHDOG_RST (0x3c37) +#define P_WATCHDOG_RST (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000) // ----------------------------------------------------------- #define AHB_ARBITER_REG (0x3c42) #define P_AHB_ARBITER_REG (volatile unsigned int *)((0x3c42 << 2) + 0xffd00000) @@ -32778,3 +32778,124 @@ // synopsys translate_on // // Closing file: dsi_regs.h +#define VD1_HDR2_CTRL 0x3800 +#define VD1_HDR2_CLK_GATE 0x3801 +#define VD1_HDR2_MATRIXI_COEF00_01 0x3802 +#define VD1_HDR2_MATRIXI_COEF02_10 0x3803 +#define VD1_HDR2_MATRIXI_COEF11_12 0x3804 +#define VD1_HDR2_MATRIXI_COEF20_21 0x3805 +#define VD1_HDR2_MATRIXI_COEF22 0x3806 +#define VD1_HDR2_MATRIXI_COEF30_31 0x3807 +#define VD1_HDR2_MATRIXI_COEF32_40 0x3808 +#define VD1_HDR2_MATRIXI_COEF41_42 0x3809 +#define VD1_HDR2_MATRIXI_OFFSET0_1 0x380a +#define VD1_HDR2_MATRIXI_OFFSET2 0x380b +#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x380c +#define VD1_HDR2_MATRIXI_PRE_OFFSET2 0x380d +#define VD1_HDR2_MATRIXO_COEF00_01 0x380e +#define VD1_HDR2_MATRIXO_COEF02_10 0x380f +#define VD1_HDR2_MATRIXO_COEF11_12 0x3810 +#define VD1_HDR2_MATRIXO_COEF20_21 0x3811 +#define VD1_HDR2_MATRIXO_COEF22 0x3812 +#define VD1_HDR2_MATRIXO_COEF30_31 0x3813 +#define VD1_HDR2_MATRIXO_COEF32_40 0x3814 +#define VD1_HDR2_MATRIXO_COEF41_42 0x3815 +#define VD1_HDR2_MATRIXO_OFFSET0_1 0x3816 +#define VD1_HDR2_MATRIXO_OFFSET2 0x3817 +#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x3818 +#define VD1_HDR2_MATRIXO_PRE_OFFSET2 0x3819 +#define VD1_HDR2_MATRIXI_CLIP 0x381a +#define VD1_HDR2_MATRIXO_CLIP 0x381b +#define VD1_HDR2_CGAIN_OFFT 0x381c +#define VD1_EOTF_LUT_ADDR_PORT 0x381e +#define VD1_EOTF_LUT_DATA_PORT 0x381f +#define VD1_OETF_LUT_ADDR_PORT 0x3820 +#define VD1_OETF_LUT_DATA_PORT 0x3821 +#define VD1_CGAIN_LUT_ADDR_PORT 0x3822 +#define VD1_CGAIN_LUT_DATA_PORT 0x3823 +#define VD1_HDR2_CGAIN_COEF0 0x3824 +#define VD1_HDR2_CGAIN_COEF1 0x3825 +#define VD1_OGAIN_LUT_ADDR_PORT 0x3826 +#define VD1_OGAIN_LUT_DATA_PORT 0x3827 +#define VD1_HDR2_ADPS_CTRL 0x3828 +#define VD1_HDR2_ADPS_ALPHA0 0x3829 +#define VD1_HDR2_ADPS_ALPHA1 0x382a +#define VD1_HDR2_ADPS_BETA0 0x382b +#define VD1_HDR2_ADPS_BETA1 0x382c +#define VD1_HDR2_ADPS_BETA2 0x382d +#define VD1_HDR2_ADPS_COEF0 0x382e +#define VD1_HDR2_ADPS_COEF1 0x382f +#define VD1_HDR2_GMUT_CTRL 0x3830 +#define VD1_HDR2_GMUT_COEF0 0x3831 +#define VD1_HDR2_GMUT_COEF1 0x3832 +#define VD1_HDR2_GMUT_COEF2 0x3833 +#define VD1_HDR2_GMUT_COEF3 0x3834 +#define VD1_HDR2_GMUT_COEF4 0x3835 +#define VD1_HDR2_PIPE_CTRL1 0x3836 +#define VD1_HDR2_PIPE_CTRL2 0x3837 +#define VD1_HDR2_PIPE_CTRL3 0x3838 +#define VD1_HDR2_PROC_WIN1 0x3839 +#define VD1_HDR2_PROC_WIN2 0x383a +#define VD1_HDR2_MATRIXI_EN_CTRL 0x383b +#define VD1_HDR2_MATRIXO_EN_CTRL 0x383c + +#define OSD1_HDR2_CTRL 0x38a0 +#define OSD1_HDR2_CLK_GATE 0x38a1 +#define OSD1_HDR2_MATRIXI_COEF00_01 0x38a2 +#define OSD1_HDR2_MATRIXI_COEF02_10 0x38a3 +#define OSD1_HDR2_MATRIXI_COEF11_12 0x38a4 +#define OSD1_HDR2_MATRIXI_COEF20_21 0x38a5 +#define OSD1_HDR2_MATRIXI_COEF22 0x38a6 +#define OSD1_HDR2_MATRIXI_COEF30_31 0x38a7 +#define OSD1_HDR2_MATRIXI_COEF32_40 0x38a8 +#define OSD1_HDR2_MATRIXI_COEF41_42 0x38a9 +#define OSD1_HDR2_MATRIXI_OFFSET0_1 0x38aa +#define OSD1_HDR2_MATRIXI_OFFSET2 0x38ab +#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x38ac +#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 0x38ad +#define OSD1_HDR2_MATRIXO_COEF00_01 0x38ae +#define OSD1_HDR2_MATRIXO_COEF02_10 0x38af +#define OSD1_HDR2_MATRIXO_COEF11_12 0x38b0 +#define OSD1_HDR2_MATRIXO_COEF20_21 0x38b1 +#define OSD1_HDR2_MATRIXO_COEF22 0x38b2 +#define OSD1_HDR2_MATRIXO_COEF30_31 0x38b3 +#define OSD1_HDR2_MATRIXO_COEF32_40 0x38b4 +#define OSD1_HDR2_MATRIXO_COEF41_42 0x38b5 +#define OSD1_HDR2_MATRIXO_OFFSET0_1 0x38b6 +#define OSD1_HDR2_MATRIXO_OFFSET2 0x38b7 +#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x38b8 +#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 0x38b9 +#define OSD1_HDR2_MATRIXI_CLIP 0x38ba +#define OSD1_HDR2_MATRIXO_CLIP 0x38bb +#define OSD1_HDR2_CGAIN_OFFT 0x38bc +#define OSD1_EOTF_LUT_ADDR_PORT 0x38be +#define OSD1_EOTF_LUT_DATA_PORT 0x38bf +#define OSD1_OETF_LUT_ADDR_PORT 0x38c0 +#define OSD1_OETF_LUT_DATA_PORT 0x38c1 +#define OSD1_CGAIN_LUT_ADDR_PORT 0x38c2 +#define OSD1_CGAIN_LUT_DATA_PORT 0x38c3 +#define OSD1_HDR2_CGAIN_COEF0 0x38c4 +#define OSD1_HDR2_CGAIN_COEF1 0x38c5 +#define OSD1_OGAIN_LUT_ADDR_PORT 0x38c6 +#define OSD1_OGAIN_LUT_DATA_PORT 0x38c7 +#define OSD1_HDR2_ADPS_CTRL 0x38c8 +#define OSD1_HDR2_ADPS_ALPHA0 0x38c9 +#define OSD1_HDR2_ADPS_ALPHA1 0x38ca +#define OSD1_HDR2_ADPS_BETA0 0x38cb +#define OSD1_HDR2_ADPS_BETA1 0x38cc +#define OSD1_HDR2_ADPS_BETA2 0x38cd +#define OSD1_HDR2_ADPS_COEF0 0x38ce +#define OSD1_HDR2_ADPS_COEF1 0x38cf +#define OSD1_HDR2_GMUT_CTRL 0x38d0 +#define OSD1_HDR2_GMUT_COEF0 0x38d1 +#define OSD1_HDR2_GMUT_COEF1 0x38d2 +#define OSD1_HDR2_GMUT_COEF2 0x38d3 +#define OSD1_HDR2_GMUT_COEF3 0x38d4 +#define OSD1_HDR2_GMUT_COEF4 0x38d5 +#define OSD1_HDR2_PIPE_CTRL1 0x38d6 +#define OSD1_HDR2_PIPE_CTRL2 0x38d7 +#define OSD1_HDR2_PIPE_CTRL3 0x38d8 +#define OSD1_HDR2_PROC_WIN1 0x38d9 +#define OSD1_HDR2_PROC_WIN2 0x38da +#define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db +#define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc
diff --git a/arch/arm/include/asm/arch-g12a/timing.h b/arch/arm/include/asm/arch-g12a/timing.h index 5378818..10152a3 100644 --- a/arch/arm/include/asm/arch-g12a/timing.h +++ b/arch/arm/include/asm/arch-g12a/timing.h
@@ -371,7 +371,7 @@ //system reserve,do not modify /* align8 */ unsigned char char_rev1; - unsigned char char_rev2; + unsigned char training_offset;//char_rev2; unsigned int ddr_dmc_remap[5]; unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify
diff --git a/arch/arm/include/asm/arch-g12a/usb.h b/arch/arm/include/asm/arch-g12a/usb.h index c01594a..f2669d5 100644 --- a/arch/arm/include/asm/arch-g12a/usb.h +++ b/arch/arm/include/asm/arch-g12a/usb.h
@@ -10,6 +10,8 @@ #include <asm/types.h> #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> +#include <generic-phy.h> +#include <asm-generic/gpio.h> #define USB_PHY_PORT_MAX 1 /* Phy register MACRO definitions */ @@ -74,6 +76,22 @@ /* XHCI PHY register structure */ #define PHY_REGISTER_SIZE 0x20 + +struct phy_aml_usb2_priv { + unsigned int base_addr; + unsigned int reset_addr; + unsigned int dwc2_a_addr; + unsigned int u2_port_num; + unsigned int usbphy_reset_bit[8]; + unsigned int usb_phy2_pll_base_addr[4]; +}; + +struct phy_aml_usb3_priv { + unsigned int base_addr; + unsigned int usb3_port_num; + struct gpio_desc desc; +}; + /* Register definitions */ typedef struct u2p_aml_regs { volatile uint32_t u2p_r0; @@ -216,5 +234,13 @@ #define USB_ID_MODE_HARDWARE (1) #define USB_ID_MODE_SW_HOST (2) #define USB_ID_MODE_SW_DEVICE (3) +int usb2_phy_tuning(uint32_t phy2_pll_base, int port); +void set_usb_pll(uint32_t phy2_pll_base); +int usb_save_phy_dev (unsigned int number, struct phy *phy); +int usb2_phy_init (struct phy *phy); +unsigned int usb_get_dwc_a_base_addr(void); +unsigned int usb_get_device_mode_phy_base(void); +void usb_phy_tuning_reset(void); +void usb_device_mode_init(void); #endif
diff --git a/arch/arm/include/asm/arch-g12b/bl31_apis.h b/arch/arm/include/asm/arch-g12b/bl31_apis.h index fdd1e43..a1c1fdd 100644 --- a/arch/arm/include/asm/arch-g12b/bl31_apis.h +++ b/arch/arm/include/asm/arch-g12b/bl31_apis.h
@@ -77,6 +77,17 @@ /*viu probe en*/ #define VIU_PREOBE_EN 0x82000080 + +/* KEYMASTER */ +#define SET_BOOT_PARAMS 0x82000072 +#define SHA256_DIGEST_SIZE 32 +typedef struct { + uint32_t device_locked; + uint32_t verified_boot_state; + uint8_t verified_boot_key[SHA256_DIGEST_SIZE]; + uint8_t verified_boot_hash[SHA256_DIGEST_SIZE]; +} keymaster_boot_params; + /* Secure HAL APIs */ #define TRUSTZONE_HAL_API_SRAM 0x400 @@ -99,6 +110,8 @@ #define JTAG_A53_EE 3 #define CLUSTER_BIT 2 +/* AVB2 */ +#define GET_AVBKEY_FROM_FIP 0x820000b0 ///////////////////////////////////////////////////////////////////////////////// #define AML_DATA_PROCESS (0x820000FF) @@ -133,4 +146,6 @@ void bl31_get_chipid(unsigned int *, unsigned int *, unsigned int *, unsigned int *); void set_viu_probe_enable(void); +int32_t set_boot_params(const keymaster_boot_params*); +int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen); #endif
diff --git a/arch/arm/include/asm/arch-g12b/cpu.h b/arch/arm/include/asm/arch-g12b/cpu.h index 9f66e3f..b381ee5 100644 --- a/arch/arm/include/asm/arch-g12b/cpu.h +++ b/arch/arm/include/asm/arch-g12b/cpu.h
@@ -21,7 +21,7 @@ #endif /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#define CONFIG_SYS_MALLOC_LEN (96*1024*1024) /* for uboot envrionment use */ /* #define CONFIG_DDR_SIZE 1024 */
diff --git a/arch/arm/include/asm/arch-g12b/regs.h b/arch/arm/include/asm/arch-g12b/regs.h index 80f4647..7978ec8 100644 --- a/arch/arm/include/asm/arch-g12b/regs.h +++ b/arch/arm/include/asm/arch-g12b/regs.h
@@ -13316,8 +13316,8 @@ #define P_WATCHDOG_CNTL1 (volatile unsigned int *)((0x3c35 << 2) + 0xffd00000) #define WATCHDOG_TCNT (0x3c36) #define P_WATCHDOG_TCNT (volatile unsigned int *)((0x3c36 << 2) + 0xffd00000) -#define WATCHDOG_RESET (0x3c37) -#define P_WATCHDOG_RESET (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000) +#define WATCHDOG_RST (0x3c37) +#define P_WATCHDOG_RST (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000) // ----------------------------------------------------------- #define AHB_ARBITER_REG (0x3c42) #define P_AHB_ARBITER_REG (volatile unsigned int *)((0x3c42 << 2) + 0xffd00000) @@ -32778,3 +32778,124 @@ // synopsys translate_on // // Closing file: dsi_regs.h +#define VD1_HDR2_CTRL 0x3800 +#define VD1_HDR2_CLK_GATE 0x3801 +#define VD1_HDR2_MATRIXI_COEF00_01 0x3802 +#define VD1_HDR2_MATRIXI_COEF02_10 0x3803 +#define VD1_HDR2_MATRIXI_COEF11_12 0x3804 +#define VD1_HDR2_MATRIXI_COEF20_21 0x3805 +#define VD1_HDR2_MATRIXI_COEF22 0x3806 +#define VD1_HDR2_MATRIXI_COEF30_31 0x3807 +#define VD1_HDR2_MATRIXI_COEF32_40 0x3808 +#define VD1_HDR2_MATRIXI_COEF41_42 0x3809 +#define VD1_HDR2_MATRIXI_OFFSET0_1 0x380a +#define VD1_HDR2_MATRIXI_OFFSET2 0x380b +#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x380c +#define VD1_HDR2_MATRIXI_PRE_OFFSET2 0x380d +#define VD1_HDR2_MATRIXO_COEF00_01 0x380e +#define VD1_HDR2_MATRIXO_COEF02_10 0x380f +#define VD1_HDR2_MATRIXO_COEF11_12 0x3810 +#define VD1_HDR2_MATRIXO_COEF20_21 0x3811 +#define VD1_HDR2_MATRIXO_COEF22 0x3812 +#define VD1_HDR2_MATRIXO_COEF30_31 0x3813 +#define VD1_HDR2_MATRIXO_COEF32_40 0x3814 +#define VD1_HDR2_MATRIXO_COEF41_42 0x3815 +#define VD1_HDR2_MATRIXO_OFFSET0_1 0x3816 +#define VD1_HDR2_MATRIXO_OFFSET2 0x3817 +#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x3818 +#define VD1_HDR2_MATRIXO_PRE_OFFSET2 0x3819 +#define VD1_HDR2_MATRIXI_CLIP 0x381a +#define VD1_HDR2_MATRIXO_CLIP 0x381b +#define VD1_HDR2_CGAIN_OFFT 0x381c +#define VD1_EOTF_LUT_ADDR_PORT 0x381e +#define VD1_EOTF_LUT_DATA_PORT 0x381f +#define VD1_OETF_LUT_ADDR_PORT 0x3820 +#define VD1_OETF_LUT_DATA_PORT 0x3821 +#define VD1_CGAIN_LUT_ADDR_PORT 0x3822 +#define VD1_CGAIN_LUT_DATA_PORT 0x3823 +#define VD1_HDR2_CGAIN_COEF0 0x3824 +#define VD1_HDR2_CGAIN_COEF1 0x3825 +#define VD1_OGAIN_LUT_ADDR_PORT 0x3826 +#define VD1_OGAIN_LUT_DATA_PORT 0x3827 +#define VD1_HDR2_ADPS_CTRL 0x3828 +#define VD1_HDR2_ADPS_ALPHA0 0x3829 +#define VD1_HDR2_ADPS_ALPHA1 0x382a +#define VD1_HDR2_ADPS_BETA0 0x382b +#define VD1_HDR2_ADPS_BETA1 0x382c +#define VD1_HDR2_ADPS_BETA2 0x382d +#define VD1_HDR2_ADPS_COEF0 0x382e +#define VD1_HDR2_ADPS_COEF1 0x382f +#define VD1_HDR2_GMUT_CTRL 0x3830 +#define VD1_HDR2_GMUT_COEF0 0x3831 +#define VD1_HDR2_GMUT_COEF1 0x3832 +#define VD1_HDR2_GMUT_COEF2 0x3833 +#define VD1_HDR2_GMUT_COEF3 0x3834 +#define VD1_HDR2_GMUT_COEF4 0x3835 +#define VD1_HDR2_PIPE_CTRL1 0x3836 +#define VD1_HDR2_PIPE_CTRL2 0x3837 +#define VD1_HDR2_PIPE_CTRL3 0x3838 +#define VD1_HDR2_PROC_WIN1 0x3839 +#define VD1_HDR2_PROC_WIN2 0x383a +#define VD1_HDR2_MATRIXI_EN_CTRL 0x383b +#define VD1_HDR2_MATRIXO_EN_CTRL 0x383c + +#define OSD1_HDR2_CTRL 0x38a0 +#define OSD1_HDR2_CLK_GATE 0x38a1 +#define OSD1_HDR2_MATRIXI_COEF00_01 0x38a2 +#define OSD1_HDR2_MATRIXI_COEF02_10 0x38a3 +#define OSD1_HDR2_MATRIXI_COEF11_12 0x38a4 +#define OSD1_HDR2_MATRIXI_COEF20_21 0x38a5 +#define OSD1_HDR2_MATRIXI_COEF22 0x38a6 +#define OSD1_HDR2_MATRIXI_COEF30_31 0x38a7 +#define OSD1_HDR2_MATRIXI_COEF32_40 0x38a8 +#define OSD1_HDR2_MATRIXI_COEF41_42 0x38a9 +#define OSD1_HDR2_MATRIXI_OFFSET0_1 0x38aa +#define OSD1_HDR2_MATRIXI_OFFSET2 0x38ab +#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x38ac +#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 0x38ad +#define OSD1_HDR2_MATRIXO_COEF00_01 0x38ae +#define OSD1_HDR2_MATRIXO_COEF02_10 0x38af +#define OSD1_HDR2_MATRIXO_COEF11_12 0x38b0 +#define OSD1_HDR2_MATRIXO_COEF20_21 0x38b1 +#define OSD1_HDR2_MATRIXO_COEF22 0x38b2 +#define OSD1_HDR2_MATRIXO_COEF30_31 0x38b3 +#define OSD1_HDR2_MATRIXO_COEF32_40 0x38b4 +#define OSD1_HDR2_MATRIXO_COEF41_42 0x38b5 +#define OSD1_HDR2_MATRIXO_OFFSET0_1 0x38b6 +#define OSD1_HDR2_MATRIXO_OFFSET2 0x38b7 +#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x38b8 +#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 0x38b9 +#define OSD1_HDR2_MATRIXI_CLIP 0x38ba +#define OSD1_HDR2_MATRIXO_CLIP 0x38bb +#define OSD1_HDR2_CGAIN_OFFT 0x38bc +#define OSD1_EOTF_LUT_ADDR_PORT 0x38be +#define OSD1_EOTF_LUT_DATA_PORT 0x38bf +#define OSD1_OETF_LUT_ADDR_PORT 0x38c0 +#define OSD1_OETF_LUT_DATA_PORT 0x38c1 +#define OSD1_CGAIN_LUT_ADDR_PORT 0x38c2 +#define OSD1_CGAIN_LUT_DATA_PORT 0x38c3 +#define OSD1_HDR2_CGAIN_COEF0 0x38c4 +#define OSD1_HDR2_CGAIN_COEF1 0x38c5 +#define OSD1_OGAIN_LUT_ADDR_PORT 0x38c6 +#define OSD1_OGAIN_LUT_DATA_PORT 0x38c7 +#define OSD1_HDR2_ADPS_CTRL 0x38c8 +#define OSD1_HDR2_ADPS_ALPHA0 0x38c9 +#define OSD1_HDR2_ADPS_ALPHA1 0x38ca +#define OSD1_HDR2_ADPS_BETA0 0x38cb +#define OSD1_HDR2_ADPS_BETA1 0x38cc +#define OSD1_HDR2_ADPS_BETA2 0x38cd +#define OSD1_HDR2_ADPS_COEF0 0x38ce +#define OSD1_HDR2_ADPS_COEF1 0x38cf +#define OSD1_HDR2_GMUT_CTRL 0x38d0 +#define OSD1_HDR2_GMUT_COEF0 0x38d1 +#define OSD1_HDR2_GMUT_COEF1 0x38d2 +#define OSD1_HDR2_GMUT_COEF2 0x38d3 +#define OSD1_HDR2_GMUT_COEF3 0x38d4 +#define OSD1_HDR2_GMUT_COEF4 0x38d5 +#define OSD1_HDR2_PIPE_CTRL1 0x38d6 +#define OSD1_HDR2_PIPE_CTRL2 0x38d7 +#define OSD1_HDR2_PIPE_CTRL3 0x38d8 +#define OSD1_HDR2_PROC_WIN1 0x38d9 +#define OSD1_HDR2_PROC_WIN2 0x38da +#define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db +#define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc
diff --git a/arch/arm/include/asm/arch-g12b/timing.h b/arch/arm/include/asm/arch-g12b/timing.h index 5378818..10152a3 100644 --- a/arch/arm/include/asm/arch-g12b/timing.h +++ b/arch/arm/include/asm/arch-g12b/timing.h
@@ -371,7 +371,7 @@ //system reserve,do not modify /* align8 */ unsigned char char_rev1; - unsigned char char_rev2; + unsigned char training_offset;//char_rev2; unsigned int ddr_dmc_remap[5]; unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify
diff --git a/arch/arm/include/asm/arch-g12b/usb.h b/arch/arm/include/asm/arch-g12b/usb.h index c01594a..f2669d5 100644 --- a/arch/arm/include/asm/arch-g12b/usb.h +++ b/arch/arm/include/asm/arch-g12b/usb.h
@@ -10,6 +10,8 @@ #include <asm/types.h> #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> +#include <generic-phy.h> +#include <asm-generic/gpio.h> #define USB_PHY_PORT_MAX 1 /* Phy register MACRO definitions */ @@ -74,6 +76,22 @@ /* XHCI PHY register structure */ #define PHY_REGISTER_SIZE 0x20 + +struct phy_aml_usb2_priv { + unsigned int base_addr; + unsigned int reset_addr; + unsigned int dwc2_a_addr; + unsigned int u2_port_num; + unsigned int usbphy_reset_bit[8]; + unsigned int usb_phy2_pll_base_addr[4]; +}; + +struct phy_aml_usb3_priv { + unsigned int base_addr; + unsigned int usb3_port_num; + struct gpio_desc desc; +}; + /* Register definitions */ typedef struct u2p_aml_regs { volatile uint32_t u2p_r0; @@ -216,5 +234,13 @@ #define USB_ID_MODE_HARDWARE (1) #define USB_ID_MODE_SW_HOST (2) #define USB_ID_MODE_SW_DEVICE (3) +int usb2_phy_tuning(uint32_t phy2_pll_base, int port); +void set_usb_pll(uint32_t phy2_pll_base); +int usb_save_phy_dev (unsigned int number, struct phy *phy); +int usb2_phy_init (struct phy *phy); +unsigned int usb_get_dwc_a_base_addr(void); +unsigned int usb_get_device_mode_phy_base(void); +void usb_phy_tuning_reset(void); +void usb_device_mode_init(void); #endif
diff --git a/arch/arm/include/asm/arch-sc2/acs.h b/arch/arm/include/asm/arch-sc2/acs.h new file mode 100644 index 0000000..7727f14 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/acs.h
@@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ACS_H +#define __ACS_H + +#define CHIP_PARAM_MAGIC 0x50696863 //"chiP" +#define DEV_PARAM_MAGIC 0x50766564 //"devP" + +#define CHIP_PARAM_VERSION 0x1 +#define DEV_PARAM_VERSION 0x1 + +#ifndef __ASSEMBLY__ + +typedef struct dev_param_hdr { + unsigned int magic; + unsigned int version; + + char bl2_regs_magic[6]; + unsigned short bl2_regs_length; + + char board_clk_magic[6]; + unsigned short board_clk_length; + + char opt_reg_magic[6]; + unsigned short opt_reg_length; + + char sto_set_magic[6]; + unsigned short sto_set_length; + + char ddr_set_magic[6]; + unsigned short ddr_set_length; + + unsigned int RFU[4]; +} __attribute__ ((packed)) dev_param_hdr_t; + +#endif +#endif
diff --git a/arch/arm/include/asm/arch-sc2/bl31_apis.h b/arch/arm/include/asm/arch-sc2/bl31_apis.h new file mode 100644 index 0000000..4143f40 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/bl31_apis.h
@@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* + * Trustzone API + * + * Copyright (C) 2012 Amlogic, Inc. + * + * Author: Platform-SH@amlogic.com + * + */ + +#ifndef __GXBB_BL31_APIS_H +#define __GXBB_BL31_APIS_H + +#include <asm/arch/io.h> + +/*#define SRAM_READ 0x82000010 +#define CORE_RD_REV1 0x82000011 +#define SRAM_ACS_READ 0x82000012 +#define SRAM_ACS_INDIRECT_READ 0x82000013*/ + +#define GET_SHARE_MEM_INPUT_BASE 0x82000020 +#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021 +#define GET_REBOOT_REASON 0x82000022 +#define GET_SHARE_STORAGE_IN_BASE 0x82000023 +#define GET_SHARE_STORAGE_OUT_BASE 0x82000024 +#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025 +#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026 +#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027 +#define SET_STORAGE_INFO 0x82000028 +#define SET_STORAGE_BOOTSEQUENCE 0x82000029 +#define SET_REBOOT_REASON 0x82000049 + +/* Set Reboot Reason then Reboot*/ +#define PSCI_SYS_REBOOT 0x84000009 + +/* SECUREOS DEFINITION*/ +/* SMC Identifiers for non-secure world functions */ +#define CALL_TRUSTZONE_HAL_API 0x5 + +/* EFUSE */ +#define EFUSE_READ 0x82000030 +#define EFUSE_WRITE 0x82000031 +#define EFUSE_WRITE_PATTERN 0x82000032 +#define EFUSE_USER_MAX 0x82000033 + +#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0 +#define DEBUG_EFUSE_READ_PATTERN 0x820000F1 + +/* JTAG*/ +#define JTAG_ON 0x82000040 +#define JTAG_OFF 0x82000041 + +#define SET_USB_BOOT_FUNC 0x82000043 + /* USB BOOT FUNC sub command list*/ + #define CLEAR_USB_BOOT 1 + #define FORCE_USB_BOOT 2 + #define RUN_COMD_USB_BOOT 3 + #define PANIC_DUMP_USB_BOOT 4 + +#define GET_CHIP_ID 0x82000044 + +/* tsensor calibration data */ +#define TSENSOR_CALI_SET 0x8200004C + +/*oscring efuse value get */ +#define OSCRING_EFUSE_GET 0x8200004D +/* Security Key*/ +#define SECURITY_KEY_QUERY 0x82000060 +#define SECURITY_KEY_READ 0x82000061 +#define SECURITY_KEY_WRITE 0x82000062 +#define SECURITY_KEY_TELL 0x82000063 +#define SECURITY_KEY_VERIFY 0x82000064 +#define SECURITY_KEY_STATUS 0x82000065 +#define SECURITY_KEY_NOTIFY 0x82000066 +#define SECURITY_KEY_LIST 0x82000067 +#define SECURITY_KEY_REMOVE 0x82000068 +#define SECURITY_KEY_NOTIFY_EX 0x82000069 +#define SECURITY_KEY_SET_ENCTYPE 0x8200006A +#define SECURITY_KEY_GET_ENCTYPE 0x8200006B +#define SECURITY_KEY_VERSION 0x8200006C + +/*viu probe en*/ +#define VIU_PREOBE_EN 0x82000080 +/*set boot first timeout*/ +#define SET_BOOT_FIRST 0x82000087 + +/* KEYMASTER */ +#define SET_BOOT_PARAMS 0x82000072 +#define SHA256_DIGEST_SIZE 32 +typedef struct { + uint32_t device_locked; + uint32_t verified_boot_state; + uint8_t verified_boot_key[SHA256_DIGEST_SIZE]; + uint8_t verified_boot_hash[SHA256_DIGEST_SIZE]; +} keymaster_boot_params; + +/* Secure HAL APIs */ +#define TRUSTZONE_HAL_API_SRAM 0x400 + +/*start hifi4 */ +#define START_HIFI4 0x82000090 +#define DSP_SEC_POWERSET 0x82000092 + + +#define SRAM_HAL_API_CHECK_EFUSE 0x403 +struct sram_hal_api_arg { + unsigned int cmd; + unsigned int req_len; + unsigned int res_len; + unsigned long req_phy_addr; + unsigned long res_phy_addr; + unsigned long ret_phy_addr; +}; + +#define JTAG_STATE_ON 0 +#define JTAG_STATE_OFF 1 +#define JTAG_M3_AO 0 +#define JTAG_M3_EE 1 +#define JTAG_A53_AO 2 +#define JTAG_A53_EE 3 +#define CLUSTER_BIT 2 + + +/* AVB2 */ +#define GET_AVBKEY_FROM_FIP 0x820000b0 + +///////////////////////////////////////////////////////////////////////////////// +#define AML_DATA_PROCESS (0x820000FF) + #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10) + #define AML_D_P_W_EFUSE_PASSWORD (0x11) + #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12) + #define AML_D_P_W_EFUSE_AMLOGIC (0x20) + #define AML_D_P_IMG_DECRYPT (0x40) + #define AML_D_P_UPGRADE_CHECK (0x80) + +#define GXB_EFUSE_PATTERN_SIZE (0x5 << 9) +#define GXB_IMG_SIZE (24<<20) +#define GXB_IMG_LOAD_ADDR (0x1080000) + #define GXB_IMG_DEC_KNL (1<<0) + #define GXB_IMG_DEC_RMD (1<<1) + #define GXB_IMG_DEC_DTB (1<<2) + #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB) + +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +void aml_set_jtag_state(unsigned state, unsigned select); +unsigned aml_get_reboot_reason(void); +unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); +void aml_set_bootsequence(uint32_t val); +void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2); +unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long ); +long get_sharemem_info(unsigned long); +void set_usb_boot_function(unsigned long command); +void aml_system_off(void); + +void bl31_get_chipid(unsigned int *, unsigned int *, + unsigned int *, unsigned int *); +void set_viu_probe_enable(void); +void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value); +void power_set_dsp(unsigned int id, unsigned int powerflag); +void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0); +void set_boot_first_timeout(uint64_t arg0); +int bl31_get_cornerinfo(uint8_t *outbuf, int size); +int32_t set_boot_params(const keymaster_boot_params*); +int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen); +#endif
diff --git a/arch/arm/include/asm/arch-sc2/board_id.h b/arch/arm/include/asm/arch-sc2/board_id.h new file mode 100644 index 0000000..6488771 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/board_id.h
@@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +unsigned int get_board_id(void); \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-sc2/clk_measure.h b/arch/arm/include/asm/arch-sc2/clk_measure.h new file mode 100644 index 0000000..3156b49 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/clk_measure.h
@@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _ARCH_MESON_SC2_MEASURE_H_ +#define _ARCH_MESON_SC2_MEASURE_H_ + +static const char* clk_msr_table[] = { + [0] = "cts_sys_clk", + [1] = "cts_axi_clk", + [2] = "cts_rtc_clk", + [3] = "cts_dspa_clk", + [5] = "cts_mali_clk", + [6] = "sys_cpu_clk_div16", + [7] = "cts_ceca_clk", + [8] = "cts_cecb_clk", + [10] = "fclk_div5", + [11] = "mp0_clk_out", + [12] = "mp1_clk_out", + [13] = "mp2_clk_out", + [14] = "mp3_clk_out", + [15] = "mpll_clk_50m", + [16] = "pcie_clk_inp", + [17] = "pcie_clk_inn", + [18] = "mpll_clk_test_out", + [19] = "hifi_pll_clk", + [20] = "gp0_pll_clk", + [21] = "gp1_pll_clk", + [22] = "eth_mppll_50m_ckout", + [23] = "sys_pll_div16", + [24] = "ddr_dpll_pt_clk", + [25] = "earcrx_pll_ckout", + [30] = "mod_eth_phy_ref_clk", + [31] = "mod_eth_tx_clk", + [32] = "cts_eth_clk125Mhz", + [33] = "cts_eth_clk_rmii", + [34] = "co_clkin_to_mac", + [35] = "mod_eth_rx_clk_rmii", + [36] = "co_rx_clk", + [37] = "co_tx_clk", + [38] = "eth_phy_rxclk", + [39] = "eth_phy_plltxclk", + [40] = "ephy_test_clk", + [50] = "vid_pll_div_clk_out", + [51] = "cts_enci_clk", + [52] = "cts_encp_clk", + [53] = "cts_encl_clk", + [54] = "cts_vdac_clk", + [55] = "cts_cdac_clk_c", + [56] = "mod_tcon_clko", + [57] = "lcd_an_clk_ph2", + [58] = "lcd_an_clk_ph3", + [59] = "cts_hdmi_tx_pixel_clk", + [60] = "cts_vdin_meas_clk", + [61] = "cts_vpu_clk", + [62] = "cts_vpu_clkb", + [63] = "cts_vpu_clkb_tmp", + [64] = "cts_vpu_clkc", + [65] = "cts_vid_lock_clk", + [66] = "cts_vapbclk", + [67] = "cts_ge2d_clk", + [68] = "cts_hdcp22_esmclk", + [69] = "cts_hdcp22_skpclk", + [76] = "hdmitx_tmds_clk", + [77] = "cts_hdmitx_sys_clk", + [78] = "cts_hdmitx_fe_clk", + [79] = "cts_rama_clk", + [93] = "cts_vdec_clk", + [94] = "cts_wave420_aclk", + [95] = "cts_wave420_cclk", + [96] = "cts_wave420_bclk", + [97] = "cts_hcodec_clk", + [98] = "cts_hevcb_clk", + [99] = "cts_hevcf_clk", + [110] = "cts_sc_clk(smartcard)", + [111] = "cts_sar_adc_clk", + [113] = "cts_sd_emmc_C_clk(nand)", + [114] = "cts_sd_emmc_B_clk", + [115] = "cts_sd_emmc_A_clk", + [116] = "gpio_msr_clk", + [117] = "cts_spicc_1_clk", + [118] = "cts_spicc_0_clk", + [121] = "cts_ts_clk(temp sensor)", + [130] = "audio_vad_clk", + [131] = "acodec_dac_clk_x128", + [132] = "audio_locker_out_clk", + [133] = "audio_locker_in_clk", + [134] = "audio_tdmout_c_sclk", + [135] = "audio_tdmout_b_sclk", + [136] = "audio_tdmout_a_sclk", + [137] = "audio_tdmin_lb_sclk", + [138] = "audio_tdmin_c_sclk", + [139] = "audio_tdmin_b_sclk", + [140] = "audio_tdmin_a_sclk", + [141] = "audio_resamplea_clk", + [142] = "audio_pdm_sysclk", + [143] = "audio_spdifoutb_mst_clk", + [144] = "audio_spdifout_mst_clk", + [145] = "audio_spdifin_mst_clk", + [146] = "audio_pdm_dclk", + [147] = "audio_resampleb_clk", + [148] = "earcrx_pll_dmac_ck", + [160] = "pwm_j_clk", + [161] = "pwm_i_clk", + [162] = "pwm_h_clk", + [163] = "pwm_g_clk", + [164] = "pwm_f_clk", + [165] = "pwm_e_clk", + [166] = "pwm_d_clk", + [167] = "pwm_c_clk", + [168] = "pwm_b_clk", + [169] = "pwm_a_clk", + [176] = "rng_ring_0", + [177] = "rng_ring_1", + [178] = "rng_ring_2", + [179] = "rng_ring_3", + [180] = "dmc_osc_ring(LVT16)", + [181] = "gpu_osc_ring0(LVT16)", + [182] = "gpu_osc_ring1(ULVT16)", + [183] = "gpu_osc_ring2(SVT16)", + [184] = "vpu_osc_ring0(SVT24)", + [185] = "vpu_osc_ring1(LVT20)", + [186] = "vpu_osc_ring2(LVT16)", + [187] = "dos_osc_ring0(SVT24)", + [188] = "dos_osc_ring1(SVT16)", + [189] = "dos_osc_ring2(LVT16)", + [190] = "dos_osc_ring3(ULVT20)", + [191] = "ddr_osc_ring(LVT16)", + [192] = "sys_cpu_osc_ring0(ULVT16)", + [193] = "sys_cpu_osc_ring1(ULVT20)", + [194] = "sys_cpu_osc_ring2(ULVT16)", + [195] = "sys_cpu_osc_ring3(LVT16)", + [196] = "axi_sram_osc_ring(SVT16)", + [197] = "dspa_osc_ring(SVT16)", +}; + +int clk_msr(int index); + +#endif
diff --git a/arch/arm/include/asm/arch-sc2/clock.h b/arch/arm/include/asm/arch-sc2/clock.h new file mode 100644 index 0000000..9c1e0d2 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/clock.h
@@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __SC2_H +#define __SC2_H + +// REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 +// ----------------------------------------------- +#define SC2_CLKCTRL_OSCIN_CTRL (0x0001 << 2) +#define SC2_CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0002 << 2) +#define SC2_CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0003 << 2) +#define SC2_CLKCTRL_RTC_CTRL (0x0004 << 2) +#define SC2_CLKCTRL_CHECK_CLK_RESULT (0x0005 << 2) +#define SC2_CLKCTRL_MBIST_ATSPEED_CTRL (0x0006 << 2) +#define SC2_CLKCTRL_LOCK_BIT_REG0 (0x0008 << 2) +#define SC2_CLKCTRL_LOCK_BIT_REG1 (0x0009 << 2) +#define SC2_CLKCTRL_LOCK_BIT_REG2 (0x000a << 2) +#define SC2_CLKCTRL_LOCK_BIT_REG3 (0x000b << 2) +#define SC2_CLKCTRL_PROT_BIT_REG0 (0x000c << 2) +#define SC2_CLKCTRL_PROT_BIT_REG1 (0x000d << 2) +#define SC2_CLKCTRL_PROT_BIT_REG2 (0x000e << 2) +#define SC2_CLKCTRL_PROT_BIT_REG3 (0x000f << 2) +#define SC2_CLKCTRL_SYS_CLK_CTRL0 (0x0010 << 2) +#define SC2_CLKCTRL_SYS_CLK_EN0_REG0 (0x0011 << 2) +#define SC2_CLKCTRL_SYS_CLK_EN0_REG1 (0x0012 << 2) +#define SC2_CLKCTRL_SYS_CLK_EN0_REG2 (0x0013 << 2) +#define SC2_CLKCTRL_SYS_CLK_EN0_REG3 (0x0014 << 2) +#define SC2_CLKCTRL_SYS_CLK_EN1_REG0 (0x0015 << 2) +#define SC2_CLKCTRL_SYS_CLK_EN1_REG1 (0x0016 << 2) +#define SC2_CLKCTRL_SYS_CLK_EN1_REG2 (0x0017 << 2) +#define SC2_CLKCTRL_SYS_CLK_EN1_REG3 (0x0018 << 2) +#define SC2_CLKCTRL_SYS_CLK_VPU_EN0 (0x0019 << 2) +#define SC2_CLKCTRL_SYS_CLK_VPU_EN1 (0x001a << 2) +#define SC2_CLKCTRL_AXI_CLK_CTRL0 (0x001b << 2) +#define SC2_CLKCTRL_TST_CTRL0 (0x0020 << 2) +#define SC2_CLKCTRL_TST_CTRL1 (0x0021 << 2) +#define SC2_CLKCTRL_CECA_CTRL0 (0x0022 << 2) +#define SC2_CLKCTRL_CECA_CTRL1 (0x0023 << 2) +#define SC2_CLKCTRL_CECB_CTRL0 (0x0024 << 2) +#define SC2_CLKCTRL_CECB_CTRL1 (0x0025 << 2) +#define SC2_CLKCTRL_SC_CLK_CTRL (0x0026 << 2) +#define SC2_CLKCTRL_DSPA_CLK_CTRL0 (0x0027 << 2) +#define SC2_CLKCTRL_DSPB_CLK_CTRL0 (0x0028 << 2) +#define SC2_CLKCTRL_RAMA_CLK_CTRL0 (0x0029 << 2) +#define SC2_CLKCTRL_CLK12_24_CTRL (0x002a << 2) +#define SC2_CLKCTRL_VID_CLK_CTRL (0x0030 << 2) +#define SC2_CLKCTRL_VID_CLK_CTRL2 (0x0031 << 2) +#define SC2_CLKCTRL_VID_CLK_DIV (0x0032 << 2) +#define SC2_CLKCTRL_VIID_CLK_DIV (0x0033 << 2) +#define SC2_CLKCTRL_VIID_CLK_CTRL (0x0034 << 2) +#define SC2_CLKCTRL_HDMI_CLK_CTRL (0x0038 << 2) +#define SC2_CLKCTRL_VID_PLL_CLK_DIV (0x0039 << 2) +#define SC2_CLKCTRL_VPU_CLK_CTRL (0x003a << 2) +#define SC2_CLKCTRL_VPU_CLKB_CTRL (0x003b << 2) +#define SC2_CLKCTRL_VPU_CLKC_CTRL (0x003c << 2) +#define SC2_CLKCTRL_VID_LOCK_CLK_CTRL (0x003d << 2) +#define SC2_CLKCTRL_VDIN_MEAS_CLK_CTRL (0x003e << 2) +#define SC2_CLKCTRL_VAPBCLK_CTRL (0x003f << 2) +#define SC2_CLKCTRL_HDCP22_CLK_CTRL (0x0040 << 2) +#define SC2_CLKCTRL_MIPIDSI_PHY_CLK_CTRL (0x0041 << 2) +#define SC2_CLKCTRL_CDAC_CLK_CTRL (0x0042 << 2) +#define SC2_CLKCTRL_MIPI_CSI_PHY_CLK_CTRL (0x0043 << 2) +#define SC2_CLKCTRL_CSI2_ADAPT_CLK_CTRL (0x0044 << 2) +#define SC2_CLKCTRL_VDEC_CLK_CTRL (0x0050 << 2) +#define SC2_CLKCTRL_VDEC2_CLK_CTRL (0x0051 << 2) +#define SC2_CLKCTRL_VDEC3_CLK_CTRL (0x0052 << 2) +#define SC2_CLKCTRL_VDEC4_CLK_CTRL (0x0053 << 2) +#define SC2_CLKCTRL_WAVE420L_CLK_CTRL (0x0054 << 2) +#define SC2_CLKCTRL_WAVE420L_CLK_CTRL2 (0x0055 << 2) +#define SC2_CLKCTRL_TS_CLK_CTRL (0x0056 << 2) +#define SC2_CLKCTRL_MALI_CLK_CTRL (0x0057 << 2) +#define SC2_CLKCTRL_VIPNANOQ_CLK_CTRL (0x0058 << 2) +#define SC2_CLKCTRL_ETH_CLK_CTRL (0x0059 << 2) +#define SC2_CLKCTRL_NAND_CLK_CTRL (0x005a << 2) +#define SC2_CLKCTRL_SD_EMMC_CLK_CTRL (0x005b << 2) +#define SC2_CLKCTRL_BT656_CLK_CTRL (0x005c << 2) +#define SC2_CLKCTRL_SPICC_CLK_CTRL (0x005d << 2) +#define SC2_CLKCTRL_GEN_CLK_CTRL (0x005e << 2) +#define SC2_CLKCTRL_SAR_CLK_CTRL0 (0x005f << 2) +#define SC2_CLKCTRL_PWM_CLK_AB_CTRL (0x0060 << 2) +#define SC2_CLKCTRL_PWM_CLK_CD_CTRL (0x0061 << 2) +#define SC2_CLKCTRL_PWM_CLK_EF_CTRL (0x0062 << 2) +#define SC2_CLKCTRL_PWM_CLK_GH_CTRL (0x0063 << 2) +#define SC2_CLKCTRL_PWM_CLK_IJ_CTRL (0x0064 << 2) +#define SC2_CLKCTRL_TIMESTAMP_CTRL (0x0100 << 2) +#define SC2_CLKCTRL_TIMESTAMP_CTRL1 (0x0101 << 2) +#define SC2_CLKCTRL_TIMESTAMP_CTRL2 (0x0103 << 2) +#define SC2_CLKCTRL_TIMESTAMP_RD0 (0x0104 << 2) +#define SC2_CLKCTRL_TIMESTAMP_RD1 (0x0105 << 2) +#define SC2_CLKCTRL_TIMEBASE_CTRL0 (0x0106 << 2) +#define SC2_CLKCTRL_TIMEBASE_CTRL1 (0x0107 << 2) +#define SC2_CLKCTRL_EFUSE_CPU_CFG01 (0x0120 << 2) +#define SC2_CLKCTRL_EFUSE_CPU_CFG2 (0x0121 << 2) +#define SC2_CLKCTRL_EFUSE_ENCP_CFG0 (0x0122 << 2) +#define SC2_CLKCTRL_EFUSE_MALI_CFG01 (0x0123 << 2) +#define SC2_CLKCTRL_EFUSE_HEVCB_CFG01 (0x0124 << 2) +#define SC2_CLKCTRL_EFUSE_HEVCB_CFG2 (0x0125 << 2) +#define SC2_CLKCTRL_EFUSE_LOCK (0x0126 << 2) +//======================================================================== + +// REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 +// ----------------------------------------------- +#define SC2_ANACTRL_SYSPLL_CTRL0 ((0x00 << 2) + 0x8000) +#define SC2_ANACTRL_SYSPLL_CTRL1 ((0x01 << 2) + 0x8000) +#define SC2_ANACTRL_SYSPLL_CTRL2 ((0x02 << 2) + 0x8000) +#define SC2_ANACTRL_SYSPLL_CTRL3 ((0x03 << 2) + 0x8000) +#define SC2_ANACTRL_SYSPLL_CTRL4 ((0x04 << 2) + 0x8000) +#define SC2_ANACTRL_SYSPLL_CTRL5 ((0x05 << 2) + 0x8000) +#define SC2_ANACTRL_SYSPLL_CTRL6 ((0x06 << 2) + 0x8000) +#define SC2_ANACTRL_SYSPLL_STS ((0x07 << 2) + 0x8000) +#define SC2_ANACTRL_FIXPLL_CTRL0 ((0x10 << 2) + 0x8000) +#define SC2_ANACTRL_FIXPLL_CTRL1 ((0x11 << 2) + 0x8000) +#define SC2_ANACTRL_FIXPLL_CTRL2 ((0x12 << 2) + 0x8000) +#define SC2_ANACTRL_FIXPLL_CTRL3 ((0x13 << 2) + 0x8000) +#define SC2_ANACTRL_FIXPLL_CTRL4 ((0x14 << 2) + 0x8000) +#define SC2_ANACTRL_FIXPLL_CTRL5 ((0x15 << 2) + 0x8000) +#define SC2_ANACTRL_FIXPLL_CTRL6 ((0x16 << 2) + 0x8000) +#define SC2_ANACTRL_FIXPLL_STS ((0x17 << 2) + 0x8000) +#define SC2_ANACTRL_GP0PLL_CTRL0 ((0x20 << 2) + 0x8000) +#define SC2_ANACTRL_GP0PLL_CTRL1 ((0x21 << 2) + 0x8000) +#define SC2_ANACTRL_GP0PLL_CTRL2 ((0x22 << 2) + 0x8000) +#define SC2_ANACTRL_GP0PLL_CTRL3 ((0x23 << 2) + 0x8000) +#define SC2_ANACTRL_GP0PLL_CTRL4 ((0x24 << 2) + 0x8000) +#define SC2_ANACTRL_GP0PLL_CTRL5 ((0x25 << 2) + 0x8000) +#define SC2_ANACTRL_GP0PLL_CTRL6 ((0x26 << 2) + 0x8000) +#define SC2_ANACTRL_GP0PLL_STS ((0x27 << 2) + 0x8000) +#define SC2_ANACTRL_GP1PLL_CTRL0 ((0x30 << 2) + 0x8000) +#define SC2_ANACTRL_GP1PLL_CTRL1 ((0x31 << 2) + 0x8000) +#define SC2_ANACTRL_GP1PLL_CTRL2 ((0x32 << 2) + 0x8000) +#define SC2_ANACTRL_GP1PLL_CTRL3 ((0x33 << 2) + 0x8000) +#define SC2_ANACTRL_GP1PLL_CTRL4 ((0x34 << 2) + 0x8000) +#define SC2_ANACTRL_GP1PLL_CTRL5 ((0x35 << 2) + 0x8000) +#define SC2_ANACTRL_GP1PLL_CTRL6 ((0x36 << 2) + 0x8000) +#define SC2_ANACTRL_GP1PLL_STS ((0x37 << 2) + 0x8000) +#define SC2_ANACTRL_HIFIPLL_CTRL0 ((0x40 << 2) + 0x8000) +#define SC2_ANACTRL_HIFIPLL_CTRL1 ((0x41 << 2) + 0x8000) +#define SC2_ANACTRL_HIFIPLL_CTRL2 ((0x42 << 2) + 0x8000) +#define SC2_ANACTRL_HIFIPLL_CTRL3 ((0x43 << 2) + 0x8000) +#define SC2_ANACTRL_HIFIPLL_CTRL4 ((0x44 << 2) + 0x8000) +#define SC2_ANACTRL_HIFIPLL_CTRL5 ((0x45 << 2) + 0x8000) +#define SC2_ANACTRL_HIFIPLL_CTRL6 ((0x46 << 2) + 0x8000) +#define SC2_ANACTRL_HIFIPLL_STS ((0x47 << 2) + 0x8000) +#define SC2_ANACTRL_PCIEPLL_CTRL0 ((0x50 << 2) + 0x8000) +#define SC2_ANACTRL_PCIEPLL_CTRL1 ((0x51 << 2) + 0x8000) +#define SC2_ANACTRL_PCIEPLL_CTRL2 ((0x52 << 2) + 0x8000) +#define SC2_ANACTRL_PCIEPLL_CTRL3 ((0x53 << 2) + 0x8000) +#define SC2_ANACTRL_PCIEPLL_CTRL4 ((0x54 << 2) + 0x8000) +#define SC2_ANACTRL_PCIEPLL_CTRL5 ((0x55 << 2) + 0x8000) +#define SC2_ANACTRL_PCIEPLL_STS ((0x56 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL0 ((0x60 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL1 ((0x61 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL2 ((0x62 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL3 ((0x63 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL4 ((0x64 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL5 ((0x65 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL6 ((0x66 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL7 ((0x67 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_CTRL8 ((0x68 << 2) + 0x8000) +#define SC2_ANACTRL_MPLL_STS ((0x69 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_CTRL0 ((0x70 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_CTRL1 ((0x71 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_CTRL2 ((0x72 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_CTRL3 ((0x73 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_CTRL4 ((0x74 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_CTRL5 ((0x75 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_CTRL6 ((0x76 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_STS ((0x77 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPLL_VLOCK ((0x79 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPHY_CTRL0 ((0x80 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPHY_CTRL1 ((0x81 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPHY_CTRL2 ((0x82 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPHY_CTRL3 ((0x83 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPHY_CTRL4 ((0x84 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPHY_CTRL5 ((0x85 << 2) + 0x8000) +#define SC2_ANACTRL_HDMIPHY_STS ((0x86 << 2) + 0x8000) +#define SC2_ANACTRL_MIPICSI_CTRL0 ((0x90 << 2) + 0x8000) +#define SC2_ANACTRL_MIPICSI_CTRL1 ((0x91 << 2) + 0x8000) +#define SC2_ANACTRL_MIPICSI_CTRL2 ((0x92 << 2) + 0x8000) +#define SC2_ANACTRL_MIPICSI_CTRL3 ((0x93 << 2) + 0x8000) +#define SC2_ANACTRL_MIPICSI_CTRL4 ((0x94 << 2) + 0x8000) +#define SC2_ANACTRL_MIPICSI_CTRL5 ((0x95 << 2) + 0x8000) +#define SC2_ANACTRL_MIPIDSI_CTRL0 ((0xa0 << 2) + 0x8000) +#define SC2_ANACTRL_MIPIDSI_CTRL1 ((0xa1 << 2) + 0x8000) +#define SC2_ANACTRL_MIPIDSI_CTRL2 ((0xa2 << 2) + 0x8000) +#define SC2_ANACTRL_MIPIDSI_STS ((0xa3 << 2) + 0x8000) +#define SC2_ANACTRL_VDAC_CTRL0 ((0xb0 << 2) + 0x8000) +#define SC2_ANACTRL_VDAC_CTRL1 ((0xb1 << 2) + 0x8000) +#define SC2_ANACTRL_POR_CTRL ((0xb6 << 2) + 0x8000) +#define SC2_ANACTRL_LOCK_BIT ((0xb8 << 2) + 0x8000) +#define SC2_ANACTRL_PROT_BIT ((0xb9 << 2) + 0x8000) +//======================================================================== + +/* + * CPU clok register offset + * APB_BASE: APB1_BASE_ADDR = 0xfe007400 + */ + +#include <dt-bindings/clock/sc2-clkc.h> +#define NR_CLKS (CLKID_END_BASE) + +#endif /* __SC2_H */
diff --git a/arch/arm/include/asm/arch-sc2/core.h b/arch/arm/include/asm/arch-sc2/core.h new file mode 100644 index 0000000..97fd220 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/core.h
@@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CORE_H__ +#define __CORE_H__ + +int get_core_mpidr(unsigned int cpuid); +int get_core_idx(unsigned int mpidr); +int get_core_max(void); + +#endif
diff --git a/arch/arm/include/asm/arch-sc2/cpu.h b/arch/arm/include/asm/arch-sc2/cpu.h new file mode 100644 index 0000000..5ab0e45 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/cpu.h
@@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _CPU_H +#define _CPU_H +/* #include <config.h> */ +/* #include <asm/plat-cpu.h> */ +/* #include <asm/arch/ddr.h> */ + +#if 0 +#define CONFIG_AML_MESON 1 +#define CONFIG_AML_MESON_GX 1 +#define CONFIG_AML_MESON_G12A 1 +#endif + +/*enable viu probe*/ +#if 0 +#define CONFIG_CMD_VIU_PROBE 1 +#endif + +/* for uboot envrionment use */ +#define CONFIG_DDR_SIZE 2048 + +/* dram */ +#define PHYS_SDRAM_1_BASE 0x00000000UL +#define PHYS_SDRAM_1_SIZE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE + +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE) + +/* define size */ +#define CONFIG_1G_SIZE (1<<30) /* 1G */ +#define CONFIG_2G_SIZE (2<<30) /* 2G */ +#define CONFIG_3G_SIZE (3<<30) /* 3G */ +#define CONFIG_DDR_MAX_SIZE (0XF1<<24) /* sc2 ddr max use interval [0~0xf1000000) */ + +/* console/print buffer */ +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + +/* use "hush" command parser */ +#if 0 +#define CONFIG_SYS_HUSH_PARSER +#endif + +#if 0 +#define CONFIG_DTB_MEM_ADDR 0x1000000 +#endif + +#if 0 +#define CONFIG_AML_CUSTOMER_ID (0) +#endif + +#define AML_CUSTOMER_ID (0) + +//#define CONFIG_SILENT_CONSOLE +//#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC +//#define CONFIG_SILENT_U_BOOT_ONLY + +/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */ +#define CONFIG_AML_BL33_COMPRESS_ENABLE 1 + +/* 2018.03.19 G12A only support v3 format for normal & secure boot */ +#define CONFIG_AML_SECURE_BOOT_V3 1 + +#define NR_CPUS 4 + +#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0 +#define PACKAGE_ID_MASK 0xFF + +/*C1 SoC secure boot solution default not support AES algorithm*/ +//#define CONFIG_AML_CRYPTO_AES 1 + + +/*Flag for enable AES key generate to EFUSE pattern, with this flag only +AES key will be generated to EFUSE pattern, it can be used for use case +like the AES key not ready when secure boot enabled for the first time. +*/ +//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1 + +#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-sc2/cpu_config.h b/arch/arm/include/asm/arch-sc2/cpu_config.h new file mode 100644 index 0000000..edf7983 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/cpu_config.h
@@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _BOOT_ROM_CONFIG_H_ +#define _BOOT_ROM_CONFIG_H_ + +/*********************************************************** + * The following constants are GXBB definition + **********************************************************/ +#define ROMBOOT_START 0xD9040000 +#define ROM_SIZE (64*1024) +#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE) + +/*********************************************************** + * AHB-SRAM Total Size 80KB, layout shown as below + * + * ROMCODE use the top 32KB + * + * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved + * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry + * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info + * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror + * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3) + * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) * + * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) * + * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS + * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer + * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved + * + **********************************************************/ +#define RAM_START 0xD9000000 +#define RAM_SIZE (80 * 1024) +#define BL1_RAM_START (RAM_START + 0xC000) +#define BL1_RAM_SIZE (32 * 1024) +#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE) +#define BSS_START (BL1_RAM_START + (2 * 1024)) +#define BSS_SIZE (18 * 1024) +#define _STACK_END (BSS_START + BSS_SIZE + 8*1024) +#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024) +#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR) +#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512) +#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256) +#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER) +#define BL1_SEC_MBX (BL1_RAM_END - 2*1024) +#define BL1_NAND_BUFF (BL1_RAM_START + 1024) +#define BL1_USB_BUFF (BL1_NAND_BUFF) + +#define MEMORY_LOC RAM_START + +#define SRAM_DEBUG_BUFF_SIZE 256 + +/* BL2 SPL size */ +#define BL2_SIZE (254 * 1024) + +//for signature test +//#define CONFIG_AML_SIG_TEST_BUILD + +/* Software SHA2 */ +#define CONFIG_SHA2_SW + +/* Hardware SHA2 */ +#define CONFIG_SHA2_HW +#define SHA2_HW_UPDATE_API + +/* Keep timer config in conf.h */ +#define CONFIG_TIMER + +/* Bootrom debug info */ +#define CONFIG_DEBUG_INFO + +/* Mincrypt RSA library */ +//#define CONFIG_MINCRYPT + +/* PolarSSL RSA library */ +#define CONFIG_POLARSSL_RSA + +#ifdef CONFIG_POLARSSL_RSA +#ifndef CONFIG_MALLOC +#define CONFIG_MALLOC +#endif /* ! CONFIG_MALLOC */ +#endif /* CONFIG_POLARSSL_RSA */ + +#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-sc2/cpu_reset.h b/arch/arm/include/asm/arch-sc2/cpu_reset.h new file mode 100644 index 0000000..46f9abf --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/cpu_reset.h
@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _BOOT_ROM_WATCHDOG_H +#define _BOOT_ROM_WATCHDOG_H +#include <asm/arch/secure_apb.h> + +void reset_system(void); + +/* uboot reset interface */ +void reset_cpu(unsigned long flag); + +#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-sc2/cpu_sdio.h b/arch/arm/include/asm/arch-sc2/cpu_sdio.h new file mode 100644 index 0000000..46f366a --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/cpu_sdio.h
@@ -0,0 +1,239 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CPU_SDIO_H__ +#define __CPU_SDIO_H__ + +#define SD_EMMC_BASE_A 0xFFE03000 +#define SD_EMMC_BASE_B 0xFFE05000 +#define SD_EMMC_BASE_C 0xFFE07000 + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +struct sd_emmc_global_regs { + volatile uint32_t gclock; // 0x00 + volatile uint32_t gdelay; // 0x04 + volatile uint32_t gdelay1; //0x08 + volatile uint32_t gadjust; // 0x0c + volatile uint32_t gcalout; // 0x10 + volatile uint32_t reserved_14[11]; // 0x14~0x3c + volatile uint32_t gstart; // 0x40 + volatile uint32_t gcfg; // 0x44 + volatile uint32_t gstatus; // 0x48 + volatile uint32_t girq_en; // 0x4c + volatile uint32_t gcmd_cfg; // 0x50 + volatile uint32_t gcmd_arg; // 0x54 + volatile uint32_t gcmd_dat; // 0x58 + volatile uint32_t gcmd_rsp0; // 0x5c + volatile uint32_t gcmd_rsp1; // 0x60 + volatile uint32_t gcmd_rsp2; // 0x64 + volatile uint32_t gcmd_rsp3; // 0x68 + volatile uint32_t reserved_6c; // 0x6c + volatile uint32_t gcurr_cfg; // 0x70 + volatile uint32_t gcurr_arg; // 0x74 + volatile uint32_t gcurr_dat; // 0x78 + volatile uint32_t gcurr_rsp; // 0x7c + volatile uint32_t gnext_cfg; // 0x80 + volatile uint32_t gnext_arg; // 0x84 + volatile uint32_t gnext_dat; // 0x88 + volatile uint32_t gnext_rsp; // 0x8c + volatile uint32_t grxd; // 0x90 + volatile uint32_t gtxd; // 0x94 + volatile uint32_t reserved_98[90]; // 0x98~0x1fc + volatile uint32_t gdesc[128]; // 0x200 + volatile uint32_t gping[128]; // 0x400 + volatile uint32_t gpong[128]; // 0x800 +}; + +union sd_emmc_setup { + uint32_t d32; + struct { + unsigned bw:3; + unsigned fast:1; + unsigned par:3; + unsigned hcs:1; + unsigned sd:1; + unsigned sdhc:1; + unsigned type:6; + unsigned rca:16; + } b; +}; + +struct sd_emmc_desc_info{ + uint32_t cmd_info; + uint32_t cmd_arg; + uint32_t data_addr; + uint32_t resp_addr; +}; + +struct cmd_cfg{ + uint32_t length:9; + uint32_t block_mode:1; + uint32_t r1b:1; + uint32_t end_of_chain:1; + uint32_t timeout:4; + uint32_t no_resp:1; + uint32_t no_cmd:1; + uint32_t data_io:1; + uint32_t data_wr:1; + uint32_t resp_nocrc:1; + uint32_t resp_128:1; + uint32_t resp_num:1; + uint32_t data_num:1; + uint32_t cmd_index:6; + uint32_t error:1; + uint32_t owner:1; +}; + +struct sd_emmc_status{ + uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/ + uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */ + uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/ + uint32_t resp_err:1; /*[10] Response CRC error.*/ + uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/ + uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/ + /* Consider the multiple block read/write, set the proper timeout limits.*/ + uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */ + uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/ + uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */ + uint32_t dat_i:8; /*[23:16] Input data signals. */ + uint32_t cmd_i:1; /*[24] nput response signal. */ + uint32_t ds:1; /*[25] Input data strobe. */ + uint32_t bus_fsm:4; /*[29:26] BUS fsm */ + uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/ + uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_clock{ + uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */ + /*Clock off: cfg_div==0, the clock is disabled */ + /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */ + uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/ + /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */ + uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/ + uint32_t reserved14:2; + uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ + uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/ + uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */ + /*Any APB3 access or descriptor execution will keep clock on.*/ + uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */ + uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/ + uint32_t reserved26:1; +}; + +struct sd_emmc_delay{ + uint32_t dat0:6; /*[3:0] Data 0 delay line. */ + uint32_t dat1:6; /*[7:4] Data 1 delay line. */ + uint32_t dat2:6; /*[11:8] Data 2 delay line. */ + uint32_t dat3:6; /*[15:12] Data 3 delay line. */ + uint32_t dat4:6; /*[19:16] Data 4 delay line. */ + uint32_t spare:2; +}; + +struct sd_emmc_delay1{ + uint32_t dat5:6; /*[23:20] Data 5 delay line. */ + uint32_t dat6:6; /*[27:24] Data 6 delay line. */ + uint32_t dat7:6; /*[31:28] Data 7 delay line. */ + uint32_t dat8:6; /*[31:28] Data 7 delay line. */ + uint32_t dat9:6; /*[31:28] Data 7 delay line. */ + uint32_t spare:2; +}; + +struct sd_emmc_adjust{ + uint32_t cmd_delay:4; /*[3:0] Command delay line. */ + uint32_t ds_delay:4; /*[7:4] DS delay line. */ + uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/ + /*Signals are labeled from 0 to 9 the same as delay lines. */ + uint32_t cali_enable:1; /*[12] Enable calibration. */ + uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */ + uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */ + uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/ + uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */ + uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */ + /*set cali_enable to 1 to use this function*/ + uint32_t reserved23:9; +}; + + +struct sd_emmc_calout{ + uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */ + uint32_t reserved6:1; + uint32_t cali_vld:1; /*[7] The reading is valid. */ + uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */ + uint32_t reserved16:16; +}; + + +struct sd_emmc_start{ + uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */ + /* 0: Read descriptor from external DDR */ + uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */ + uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */ + /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */ + /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_config{ + uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/ + uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */ + uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */ + uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */ + uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */ + uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */ + uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */ + uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/ + uint32_t spare:1; /*[18] Spare, ??? need check*/ + uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/ + uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/ + uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/ + uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/ + /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/ + /*DDR slow response, stop clock is used in voltage switch.*/ + uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/ + /* 0: core clock is always on.*/ + uint32_t txd_add_err:1; /*[24] TXD add error test*/ + /*Test feature, should not be used in normal condition.*/ + /*It will inverted the first CRC bits of the 3rd block.*/ + /*Block index starts from 0, 1, 2, ¡*/ + uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/ + /*The total number of retries of one descriptor is limited to 15, */ + /*after 15 retries, the TXD_err is set to high.*/ + uint32_t revd:8; /*[31:26] reved*/ +};//__attribute__((__may_alias__)); + + +struct sd_emmc_irq_en{ + uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/ + uint32_t txd_err:1; /*[8] TX data CRC error. */ + uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */ + uint32_t resp_err:1; /*[10] Response CRC error.*/ + uint32_t resp_timeout:1; /*[11] No response received before time limit. */ + uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */ + uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */ + uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */ + uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */ + uint32_t revd:16; /*[31:16] reved*/ +}; + +struct sd_emmc_data_info{ + uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/ + uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/ + uint32_t revd:30; /*[31:17] Reved. */ +}; + + +struct sd_emmc_card_info{ + uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */ + uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/ + uint32_t revd:30; /*[31:17] Reved. */ +}; + +#endif
diff --git a/arch/arm/include/asm/arch-sc2/ddr.h b/arch/arm/include/asm/arch-sc2/ddr.h new file mode 100644 index 0000000..ad27855 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/ddr.h
@@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <io.h> +#include <stdint.h> +#include <asm/arch/ddr_define.h> + +/* io defines */ +//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data) +//#define rd_reg(addr) (*((volatile uint32_t *)(addr))) +#define wr_reg(addr, data) writel(data, addr) +#define rd_reg(addr) readl(addr) +/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/ +#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value))) +#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc))); +#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc))); +#define wait_equal(addr, data) do{}while(data != (rd_reg(addr))); + +/* function defines */ +unsigned int ddr_init(void); +unsigned int ddr_init_pll(void); +unsigned int ddr_init_dmc(void); +unsigned int ddr_init_pctl(void); +unsigned int hot_boot(void); +void ddr_print_info(void); +void ddr_test(void); +void ddr_pre_init(void); +void ddr_debug(void); + +/* pctl status */ +#define UPCTL_STAT_MASK (7) +#define UPCTL_STAT_INIT (0) +#define UPCTL_STAT_CONFIG (1) +#define UPCTL_STAT_ACCESS (3) +#define UPCTL_STAT_LOW_POWER (5) + +/* pctl cmds */ +#define UPCTL_CMD_INIT (0) +#define UPCTL_CMD_CONFIG (1) +#define UPCTL_CMD_GO (2) +#define UPCTL_CMD_SLEEP (3) +#define UPCTL_CMD_WAKEUP (4) + +/* PUB PIR setting */ +#define PUB_PIR_INIT (1<<0) +#define PUB_PIR_ZCAL (1<<1) +#define PUB_PIR_CA (1<<2) +#define PUB_PIR_PLLINIT (1<<4) +#define PUB_PIR_DCAL (1<<5) +#define PUB_PIR_PHYRST (1<<6) +#define PUB_PIR_DRAMRST (1<<7) +#define PUB_PIR_DRAMINIT (1<<8) +#define PUB_PIR_WL (1<<9) +#define PUB_PIR_QSGATE (1<<10) +#define PUB_PIR_WLADJ (1<<11) +#define PUB_PIR_RDDSKW (1<<12) +#define PUB_PIR_WRDSKW (1<<13) +#define PUB_PIR_RDEYE (1<<14) +#define PUB_PIR_WREYE (1<<15) +#define PUB_PIR_ICPC (1<<16) +#define PUB_PIR_PLLBYP (1<<17) +#define PUB_PIR_CTLDINIT (1<<18) +#define PUB_PIR_RDIMMINIT (1<<19) +#define PUB_PIR_CLRSR (1<<27) +#define PUB_PIR_LOCKBYP (1<<28) +#define PUB_PIR_DCALBYP (1<<29) +#define PUB_PIR_ZCALBYP (1<<30) +#define PUB_PIR_INITBYP (1<<31) + +/* PHY initialize register (PIR) */ +#define DDR_PIR ((PUB_PIR_ZCAL) |\ + (PUB_PIR_PLLINIT) |\ + (PUB_PIR_DCAL) |\ + (PUB_PIR_PHYRST) |\ + (PUB_PIR_DRAMRST) |\ + (PUB_PIR_DRAMINIT) |\ + (PUB_PIR_WL) |\ + (PUB_PIR_QSGATE) |\ + (PUB_PIR_WLADJ) |\ + (PUB_PIR_RDDSKW) |\ + (PUB_PIR_WRDSKW) |\ + (PUB_PIR_RDEYE) |\ + (PUB_PIR_WREYE) \ + ) + +/* PHY general status register (PGSR0) */ +#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3) +#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \ + (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff)) +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2) +#define DDR_PGSR0_CHECK() +#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3) +#define DDR_PGSR0_CHECK() +#endif + +/* other regs */ +#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-sc2/ddr_define.h b/arch/arm/include/asm/arch-sc2/ddr_define.h new file mode 100644 index 0000000..2d2697e --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/ddr_define.h
@@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#define CONFIG_BOARD_ID_MASK 0xFF +#define CONFIG_DDR_TYPE_DDR3 0 +#define CONFIG_DDR_TYPE_DDR4 1 +#define CONFIG_DDR_TYPE_LPDDR4 2 +#define CONFIG_DDR_TYPE_LPDDR3 3 +#define CONFIG_DDR_TYPE_LPDDR2 4 +#define CONFIG_DDR_TYPE_AUTO 0xf + +/* ddr channel defines */ +#define CONFIG_DDR0_16BIT 1 +#define CONFIG_DDR0_RANK0 2 +#define CONFIG_DDR0_RANK01 3 +#define CONFIG_DDR0_16BIT_2 4 +/* CONFIG_DDR_CHL_AUTO mode support RANK0 and RANK0+1 mode auto detect */ +#define CONFIG_DDR_CHL_AUTO 0xF +#define CONFIG_DDR0_16BIT_CH0 0x1 +#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 +#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 +#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 +#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 +#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 +#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 +#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 + +#define CFG_DDR_BASE_ADDR 0X0 +#define CFG_DDR_START_OFFSET 0X00000000 //TXLX SKIP 0MB + +/* ddr type identifier */ +#define CONFIG_DDR_TIMMING_LPDDR2 0x02 +#define CONFIG_DDR_TIMMING_LPDDR3 0x03 +#define CONFIG_DDR_TIMMING_DDR3_7 0x07 +#define CONFIG_DDR_TIMMING_DDR3_9 0x09 +#define CONFIG_DDR_TIMMING_DDR3_11 0x0B +#define CONFIG_DDR_TIMMING_DDR3_12 0x0C +#define CONFIG_DDR_TIMMING_DDR3_13 0x0D +#define CONFIG_DDR_TIMMING_DDR3_14 0x0E + +#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F +#define CONFIG_DDR_TIMMING_DDR4_1866 0x10 +#define CONFIG_DDR_TIMMING_DDR4_2133 0x11 +#define CONFIG_DDR_TIMMING_DDR4_2400 0x12 +#define CONFIG_DDR_TIMMING_DDR4_2666 0x13 +#define CONFIG_DDR_TIMMING_DDR4_3200 0x14 + +#define LPDDR_DIE_ROW_COL_R13_C9 0 +#define LPDDR_DIE_ROW_COL_R14_C9 1 +#define LPDDR_DIE_ROW_COL_R14_C10 2 +#define LPDDR_DIE_ROW_COL_R13_C10 3 +#define LPDDR_DIE_ROW_COL_R14_C11 4 + +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2 +#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3 + +#define CONFIG_DDR_FUNC_TEST (1<<0) + +#define CONFIG_DDR_INIT_RETRY_TOTAL (10) +#define CONFIG_DDR_PCTL_RETRY_TOTAL (100) + +#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \ + (chl_set == CONFIG_DDR0_16BIT)) +#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01)) + +#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5 +#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4 +/* DMC_DDR_CTRL defines */ +#define DDR_DDR4_ENABLE (1<<22) +#define DDR_RANK1_ENABLE (1<<21) +#define DDR_DDR4_BG_ENABLE (1<<20) +#define DDR_16BIT_ENABLE (1<<16) + +#define DDR_RANK1_SIZE_CTRL (3) +#define DDR_RANK0_SIZE_CTRL (0) + +/* dram cfg magic */ +#define DRAM_CFG_MAGIC 0x2e676663 + +#define DMC_TEST_SLT_SCAN_FREQUENCY 1 +#define DMC_TEST_SLT_OFFSET_DELAY (1<<1) +#define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING (1<<6) +#define DMC_TEST_SLT_ENABLE_DDR_DVFS (1<<7) + +/* ddr configs */ +#define DDR_RFC_TYPE_DDR3_512Mbx1 0 +#define DDR_RFC_TYPE_DDR3_512Mbx2 1 +#define DDR_RFC_TYPE_DDR3_512Mbx4 2 +#define DDR_RFC_TYPE_DDR3_512Mbx8 3 +#define DDR_RFC_TYPE_DDR3_512Mbx16 4 +#define DDR_RFC_TYPE_DDR4_2Gbx1 5 +#define DDR_RFC_TYPE_DDR4_2Gbx2 6 +#define DDR_RFC_TYPE_DDR4_2Gbx4 7 +#define DDR_RFC_TYPE_DDR4_2Gbx8 8 + +#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 +#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 +#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 +#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12 +#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13 + +#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0) +#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1) +#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2) +#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3) +#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4) + +/* lpddr3 defines */ +#ifndef CONFIG_LPDDR_REMAP_SET +#define CONFIG_LPDDR_REMAP_SET LPDDR_DIE_ROW_COL_R14_C9 +#endif + +/* how to add a new ddr function? + 1. add CONFIG_DDR_FUNC_XXX in (config).h file + 2. add define in this file. + 2.1 add + #ifndef CONFIG_DDR_FUNC_XXX + #define CONFIG_DDR_FUNC_XXX 0 + #endif + 2.2 add + #define DDR_FUNC_XXX (CONFIG_FUNC_XXX<<X) + 2.3 add DDR_FUNC_XXX |\ in DDR_FUNC + 3. add same define and parser in bl2 code + */ +/* 2.1, 2,2, 2,3 example */ +/* +#ifndef CONFIG_CMD_DDR_D2PLL +#define CONFIG_CMD_DDR_D2PLL 0 +#endif +#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0) +#define DDR_FUNC (EXISTING_FUNCTIONS) |\ + (DDR_FUNC_D2PLL) +*/ + +/* d2pll support */ +#ifndef CONFIG_CMD_DDR_D2PLL +#define CONFIG_CMD_DDR_D2PLL 0 +#endif +#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0) + +/* ddr low power function support */ +#ifndef CONFIG_DDR_LOW_POWER +#define CONFIG_DDR_LOW_POWER 0 +#endif +#define DDR_FUNC_LP (CONFIG_DDR_LOW_POWER<<1) + +/* ddr zq power down support */ +#ifndef CONFIG_DDR_ZQ_PD +#define CONFIG_DDR_ZQ_PD 0 +#endif +#define DDR_FUNC_ZQ_PD (CONFIG_DDR_ZQ_PD<<2) + +/* ddr vref function */ +#ifndef CONFIG_DDR_USE_EXT_VREF +#define CONFIG_DDR_USE_EXT_VREF 0 +#endif +#define DDR_FUNC_EXT_VREF (CONFIG_DDR_USE_EXT_VREF<<3) + +/* ddr4 timing test function */ +#ifndef CONFIG_DDR4_TIMING_TEST +#define CONFIG_DDR4_TIMING_TEST 0 +#endif +#define DDR_FUNC_DDR4_TIMING_TEST (CONFIG_DDR4_TIMING_TEST<<4) + +/* ddr pll bypass */ +#ifndef CONFIG_DDR_PLL_BYPASS +#define CONFIG_DDR_PLL_BYPASS 0 +#endif +#define DDR_FUNC_DDR_PLL_BYPASS (CONFIG_DDR_PLL_BYPASS<<5) + +/* ddr rdbi function */ +#ifndef CONFIG_DDR_FUNC_RDBI +#define CONFIG_DDR_FUNC_RDBI 0 +#endif +#define DDR_FUNC_RDBI (CONFIG_DDR_FUNC_RDBI<<6) + +/* lpddr3 ca trainingi function */ +#ifndef CONFIG_DDR_FUNC_LPDDR3_CA +#define CONFIG_DDR_FUNC_LPDDR3_CA 0 +#endif +#define DDR_FUNC_LPDDR3_CA (CONFIG_DDR_FUNC_LPDDR3_CA<<7) + +/* print ddr training window */ +#ifndef CONFIG_DDR_FUNC_PRINT_WINDOW +#define CONFIG_DDR_FUNC_PRINT_WINDOW 0 +#endif +#define DDR_FUNC_PRINT_WINDOW (CONFIG_DDR_FUNC_PRINT_WINDOW<<8) + + +/* print ddr training window */ +//#ifndef CONFIG_DDR_FULL_TEST +//#define CONFIG_DDR_FULL_TEST 0 +//#endif +//#define DDR_FULL_TEST (CONFIG_DDR_FULL_TEST<<10) + +/* non-sec region scramble function */ +#ifndef CONFIG_DDR_NONSEC_SCRAMBLE +#define CONFIG_DDR_NONSEC_SCRAMBLE 0 +#endif +#define DDR_NONSEC_SCRAMBLE (CONFIG_DDR_NONSEC_SCRAMBLE<<11) + +#if(CONFIG_DDR_FUNC_LPDDR3_CA==1) +#if (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21) +#endif +#if (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23) +#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23) +#endif +#else /* CONFIG_DDR_FUNC_LPDDR3_CA != 1 */ +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22) +#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23) +#endif /* CONFIG_DDR_FUNC_LPDDR3_CA */ + +#if(CONFIG_DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP==1) +#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25) +#else +#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (0<<25) +#endif +#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) +#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29) +#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28) +#define DDR_FUNC (DDR_FUNC_D2PLL | \ + DDR_FUNC_LP | \ + DDR_FUNC_ZQ_PD | \ + DDR_FUNC_EXT_VREF | \ + DDR_FUNC_DDR4_TIMING_TEST | \ + DDR_FUNC_DDR_PLL_BYPASS | \ + DDR_FUNC_RDBI | \ + DDR_FUNC_LPDDR3_CA | \ + DDR_FUNC_PRINT_WINDOW | \ + DDR_FULL_TEST | \ + DDR_NONSEC_SCRAMBLE | \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \ + DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1| \ + DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP | \ + (1 << 31) \ + ) + + + + +/* bl2 reg override stages define */ +#define BL2_INIT_STAGE_0 0 +#define BL2_INIT_STAGE_1 1 +#define BL2_INIT_STAGE_2 2 +#define BL2_INIT_STAGE_3 3 +#define BL2_INIT_STAGE_4 4 +#define BL2_INIT_STAGE_5 5 +#define BL2_INIT_STAGE_6 6 +#define BL2_INIT_STAGE_7 7 +#define BL2_INIT_STAGE_8 8 +#define BL2_INIT_STAGE_9 9 + + +/* ddr reg override stages define */ +#define DDR_OVERRIDE_STAGE_DDR3_PRE_INIT 0x10 +#define DDR_OVERRIDE_STAGE_DDR3_DMC_INIT 0x11 + +#define DDR_OVERRIDE_STAGE_DDR4_PRE_INIT 0x20 +#define DDR_OVERRIDE_STAGE_DDR4_DMC_INIT 0x21 + +#define DDR_OVERRIDE_STAGE_LPDDR3_PRE_INIT 0x30 +#define DDR_OVERRIDE_STAGE_LPDDR3_DMC_INIT 0x31 + +#define DDR_OVERRIDE_STAGE_LPDDR4_PRE_INIT 0x40 +#define DDR_OVERRIDE_STAGE_LPDDR4_DMC_INIT 0x41 + + +#define DWC_AC_PINMUX_TOTAL 28 +#define DWC_DFI_PINMUX_TOTAL 26 +#define DWC_DQ_PINMUX_TOTAL 32 + +/* diagnose function defines */ +#define CONFIG_DIAGNOSE_DISABLE 0x0 +#define CONFIG_DIAGNOSE_1D 0x1 +#define CONFIG_DIAGNOSE_2D 0x2 +#define CONFIG_DIAGNOSE_1D_2D 0x3
diff --git a/arch/arm/include/asm/arch-sc2/dev_parameter.h b/arch/arm/include/asm/arch-sc2/dev_parameter.h new file mode 100644 index 0000000..40b5de9 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/dev_parameter.h
@@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __DEV_PARAMETER_H__ +#define __DEV_PARAMETER_H__ + +/* gpio/pinmux/pwm */ +typedef struct _register_ops { + /* register address*/ + uint32_t reg; + /* value to set*/ + uint32_t value; + /* bitmask of the value setting */ + uint32_t mask; + /* for HW stable consideration */ + uint16_t udelay; + /* setting stage and etc. */ + uint8_t flag; + /* reserved. */ + uint8_t rsv_0; +}__attribute__ ((packed)) register_ops_t; + +#define MAX_REG_OPS_ENTRIES (32) +typedef struct pin_pwm_parameter { + register_ops_t pin_pwm[MAX_REG_OPS_ENTRIES]; +}__attribute__ ((packed)) pin_pwm_parameter_t; + +typedef struct common_storage_parameter { + /* version info of the common storage parameter */ + uint32_t version; + /* fip sector counts */ + uint32_t device_fip_container_size; + /* fip copies */ + uint32_t device_fip_container_copies; + uint8_t reserved[20]; +}__attribute__ ((packed)) common_storage_parameter_t; + + +typedef struct nand_parameter { + /* version info of the common storage parameter */ + uint32_t version; + /* the same as bbt_start_block, tell the bbt size for scanning mechanism */ + uint32_t bbt_pages; + /* for bl2 stage, it can quickly generate the small part of the fromt bbt table. 20 for start block of bbt scanning */ + uint32_t bbt_start_block; + /* 1: bl2 and fip is stored separately in different area 0: bl2 and fip is stored in first 1024 pages. 1 for slc nand flash. */ + uint32_t discrete_mode; + /* set the setup_data the same as rom code reading from page0. see union cmdinfo in nand.h. */ + union { + uint32_t nand_setup_data; + uint32_t spi_nand_page_size; + } setup_data; + union { + uint32_t nand_reserved; + uint32_t spi_nand_planes_per_lun; + } reserved; + /* Block counts of the reserved area */ + uint32_t reserved_area_blk_cnt; + /* Page number of each block */ + uint32_t page_per_block; + /* Page list source of the bl2 NAND driver. 0: calculated in source code; 1: get from byte32~63 */ + uint8_t use_param_page_list; + /* List of page addresses, 8-bit per entry */ + uint8_t page_list[32]; + uint8_t reserved1[63]; +}__attribute__ ((packed)) nand_parameter_t; + + +typedef struct storage_parameter { + /* for all the storage media */ + common_storage_parameter_t common; + /* for NAND and SPINAND */ + nand_parameter_t nand; +}__attribute__ ((packed)) storage_parameter_t; + +#endif //__AML_TIMING_H_ \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-sc2/efuse.h b/arch/arm/include/asm/arch-sc2/efuse.h new file mode 100644 index 0000000..4a68e88 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/efuse.h
@@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __EFUSE_H +#define __EFUSE_H + +#include <config.h> +#include <common.h> + +/* efuse HAL_API arg */ +struct efuse_hal_api_arg { + unsigned int cmd; /* R/W */ + unsigned int offset; + unsigned int size; + unsigned long buffer_phy; + unsigned long retcnt_phy; +}; + + +#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */ + +#define EFUSE_HAL_API_READ 0 +#define EFUSE_HAL_API_WRITE 1 +#define EFUSE_HAL_API_WRITE_PATTERN 2 +#define EFUSE_HAL_API_USER_MAX 3 + +#define EFUSE_USER_MASK (0x1 << 16) +#define EFUSE_THERMAL_MASK (0x1 << 17) +#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18) +#define EFUSE_ENCRYPT_MASK (0x1 << 19) + +//#define ASSIST_HW_REV 0x1f53 + +int efuse_read_usr(char *buf, size_t count, loff_t *ppos); +int efuse_write_usr(char *buf, size_t count, loff_t *ppos); +uint32_t efuse_get_max(void); +ssize_t efuse_read(char *buf, size_t count, loff_t *ppos); +ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos); + +int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg); +int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg); + +#endif +
diff --git a/arch/arm/include/asm/arch-sc2/eth_setup.h b/arch/arm/include/asm/arch-sc2/eth_setup.h new file mode 100644 index 0000000..6e643f6 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/eth_setup.h
@@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/io.h> + +/* + *board configuration interface. + * */ +struct eth_clock_conf{ + int enable; + int clock_50MHZ_phase; + //add ... as you need. +}; + +struct eth_board_socket{ +char *name ; +int (*eth_clock_configure)(struct eth_clock_conf); +int (*eth_pinmux_setup)(void); +int (*eth_hw_reset)(void); + +}; + + + +/* + *clock define part + */ + +#define ETH_BASE (0xff3f0000) +#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050) + /* Ethernet ctrl */ +#define ETH_PLL_CNTL_DIVEN (1<<0) +#define ETH_PLL_CNTL_MACSPD (1<<1) +#define ETH_PLL_CNTL_DATEND (1<<2) +#define ETH_PLL_CNTL_DESEND (1<<3) + + +/* + please refer following doc for detail + @AppNote-M3-ClockTrees.docx + + select clk: -> CBUS_REG(0x1076) + + 7-sys_pll_div2 + 6-vid2_pll_clk + 5-vid_pll_clk + 4-aud_pll_clk + 3-ddr_pll_clk + 2-misc_pll_clk + 1-sys_pll_clk + 0-XTAL + + clk_freq:800MHz + output_clk:50MHz + aways,maybe changed for others? +*/ + +#define ETH_CLKSRC_XTAL (0) +#define ETH_CLKSRC_SYS_PLL_CLK (1) +#define ETH_CLKSRC_MISC_PLL_CLK (2) +#define ETH_CLKSRC_DDR_PLL_CLK (3) +#define ETH_CLKSRC_AUD_PLL_CLK ( +#define ETH_CLKSRC_VID_PLL_CLK (5) +#define ETH_CLKSRC_VID2_PLL_CLK (6) +#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7) +#define CLK_1M (1000000) + +typedef union eth_aml_reg0 { + /** raw register data */ + unsigned int d32; + /** register bits */ + struct { + unsigned phy_intf_sel:3; + unsigned rx_clk_rmii_invert:1; + unsigned rgmii_tx_clk_src:1; + unsigned rgmii_tx_clk_phase:2; + unsigned rgmii_tx_clk_ratio:3; + unsigned phy_ref_clk_enable:1; + unsigned clk_rmii_i_invert:1; + unsigned clk_en:1; + unsigned adj_enable:1; + unsigned adj_setup:1; + unsigned adj_delay:5; + unsigned adj_skew:5; + unsigned cali_start:1; + unsigned cali_rise:1; + unsigned cali_sel:3; + unsigned rgmii_rx_reuse:1; + unsigned eth_urgent:1; + } b; +} eth_aml_reg0_t; + +#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0) + +int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk); +
diff --git a/arch/arm/include/asm/arch-sc2/fixme.h b/arch/arm/include/asm/arch-sc2/fixme.h new file mode 100644 index 0000000..a8468a8 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/fixme.h
@@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _ROM_FIXME_H_ +#define _ROM_FIXME_H_ + +#define ROM_FIXME 1 + +#ifdef ROM_FIXME + +/*OTP*/ +#define OTP_LIC0 (SYSCTRL_STICKY_REG0) +#define OTP_LIC1 (SYSCTRL_STICKY_REG0) +#define OTP_LIC2 (SYSCTRL_STICKY_REG0) +#define OTP_LIC3 (SYSCTRL_STICKY_REG0) + +/*PLL*/ +#define HHI_GP1_PLL_CNTL0 (SYSCTRL_STICKY_REG0) +#define HHI_GP1_PLL_CNTL1 (SYSCTRL_STICKY_REG0) +#define HHI_GP1_PLL_CNTL2 (SYSCTRL_STICKY_REG0) +#define HHI_GP1_PLL_CNTL3 (SYSCTRL_STICKY_REG0) +#define HHI_GP1_PLL_CNTL4 (SYSCTRL_STICKY_REG0) +#define HHI_GP1_PLL_CNTL5 (SYSCTRL_STICKY_REG0) +#define HHI_GP1_PLL_CNTL6 (SYSCTRL_STICKY_REG0) + +#define HHI_SYS_CPU_CLK_CNTL0 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_CPU_CLK_CNTL1 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_CPU_CLK_CNTL2 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_CPU_CLK_CNTL3 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_CPU_CLK_CNTL4 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_CPU_CLK_CNTL5 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_CPU_CLK_CNTL6 (SYSCTRL_STICKY_REG0) + +#define HHI_FIX_PLL_CNTL0 (SYSCTRL_STICKY_REG0) +#define HHI_FIX_PLL_CNTL1 (SYSCTRL_STICKY_REG0) +#define HHI_FIX_PLL_CNTL2 (SYSCTRL_STICKY_REG0) +#define HHI_FIX_PLL_CNTL3 (SYSCTRL_STICKY_REG0) +#define HHI_FIX_PLL_CNTL4 (SYSCTRL_STICKY_REG0) +#define HHI_FIX_PLL_CNTL5 (SYSCTRL_STICKY_REG0) +#define HHI_FIX_PLL_CNTL6 (SYSCTRL_STICKY_REG0) +#define P_HHI_FIX_PLL_CNTL0 (SYSCTRL_STICKY_REG0) + +#define P_HHI_MPEG_CLK_CNTL (SYSCTRL_STICKY_REG0) + +#define HHI_SYS_PLL_CNTL0 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_PLL_CNTL1 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_PLL_CNTL2 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_PLL_CNTL3 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_PLL_CNTL4 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_PLL_CNTL5 (SYSCTRL_STICKY_REG0) +#define HHI_SYS_PLL_CNTL6 (SYSCTRL_STICKY_REG0) + +#define HHI_SYS_CPU_CLK_CNTL (SYSCTRL_STICKY_REG0) + +/*ADC*/ +#define P_AO_SAR_ADC_REG11 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_REG12 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_REG13 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_REG3 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_CLK (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_REG0 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_CHAN_LIST (volatile uint32_t *)(SYSCTRL_STICKY_REG0) + +#define P_AO_SAR_ADC_AVG_CNTL (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_DELAY (volatile uint32_t *)(SYSCTRL_STICKY_REG0) + +#define P_AO_SAR_ADC_AUX_SW (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_CHAN_10_SW (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_DETECT_IDLE_SW (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_FIFO_RD (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_AO_SAR_ADC_AVG_CNTL (volatile uint32_t *)(SYSCTRL_STICKY_REG0) + + +/*SPI*/ +#define SPI_START_ADDR (SYSCTRL_STICKY_REG0) + +#define P_PAD_PULL_UP_EN_REG0 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define AO_RTI_PINMUX_REG0 (SYSCTRL_STICKY_REG0) +#define AO_GPIO_O_EN_N (SYSCTRL_STICKY_REG0) +#define AO_GPIO_I (SYSCTRL_STICKY_REG0) +#define P_PAD_PULL_UP_REG0 (volatile uint32_t *)(SYSCTRL_STICKY_REG0) +#define AO_RTI_PULL_UP_EN_REG (SYSCTRL_STICKY_REG0) +#define AO_RTI_PULL_UP_REG (SYSCTRL_STICKY_REG0) +#define P_AO_PAD_DS_B (SYSCTRL_STICKY_REG0) + +/*TIMER*/ +#define ISA_TIMERE (SYSCTRL_STICKY_REG0) +#define P_ISA_TIMERE (SYSCTRL_STICKY_REG0) + +/*DMC*/ +#define P_PREG_STICKY_REG0 (SYSCTRL_STICKY_REG0) + +/*power*/ +#define HHI_MEM_PD_REG0 (SYSCTRL_STICKY_REG0) + +/*UART*/ +#define P_AO_TIMEBASE_CNTL1 (SYSCTRL_STICKY_REG0) +#define P_AO_RTI_PINMUX_REG0 (SYSCTRL_STICKY_REG0) + +#endif + + +#endif
diff --git a/arch/arm/include/asm/arch-sc2/gpio.h b/arch/arm/include/asm/arch-sc2/gpio.h new file mode 100644 index 0000000..2467368 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/gpio.h
@@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ASM_ARCH_MESON_GPIO_H +#define __ASM_ARCH_MESON_GPIO_H + + +#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-sc2/i2c.h b/arch/arm/include/asm/arch-sc2/i2c.h new file mode 100644 index 0000000..a93a09d --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/i2c.h
@@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_MACH_I2C__ +#define __AML_MACH_I2C__ + +#include <asm/io.h> +#include <asm/arch/secure_apb.h> + +/** + * struct i2c_msg - an I2C transaction segment beginning with START + * @addr: Slave address, either seven or ten bits. When this is a ten + * bit address, I2C_M_TEN must be set in @flags and the adapter + * must support I2C_FUNC_10BIT_ADDR. + * @flags: I2C_M_RD is handled by all adapters. No other flags may be + * provided unless the adapter exported the relevant I2C_FUNC_* + * flags through i2c_check_functionality(). + * @len: Number of data bytes in @buf being read from or written to the + * I2C slave address. For read transactions where I2C_M_RECV_LEN + * is set, the caller guarantees that this buffer can hold up to + * 32 bytes in addition to the initial length byte sent by the + * slave (plus, if used, the SMBus PEC); and this value will be + * incremented by the number of block data bytes received. + * @buf: The buffer into which data is read, or from which it's written. + * + * An i2c_msg is the low level representation of one segment of an I2C + * transaction. It is visible to drivers in the @i2c_transfer() procedure, + * to userspace from i2c-dev, and to I2C adapter drivers through the + * @i2c_adapter.@master_xfer() method. + * + * Except when I2C "protocol mangling" is used, all I2C adapters implement + * the standard rules for I2C transactions. Each transaction begins with a + * START. That is followed by the slave address, and a bit encoding read + * versus write. Then follow all the data bytes, possibly including a byte + * with SMBus PEC. The transfer terminates with a NAK, or when all those + * bytes have been transferred and ACKed. If this is the last message in a + * group, it is followed by a STOP. Otherwise it is followed by the next + * @i2c_msg transaction segment, beginning with a (repeated) START. + * + * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then + * passing certain @flags may have changed those standard protocol behaviors. + * Those flags are only for use with broken/nonconforming slaves, and with + * adapters which are known to support the specific mangling options they + * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR). + */ +struct i2c_msg { + __u16 addr; /* slave address */ + __u16 flags; +#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */ + __u16 len; /* msg length */ + __u8 *buf; /* pointer to msg data */ +}; + +#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG) +//#define MESON_I2C_MASTER_AO_END (0xc810051c+5) + +#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG) +#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG) +#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG) +#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1) + +#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG) +#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1) + +#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG) +#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1) + + +#define AML_I2C_MASTER_AO 0 +#define AML_I2C_MASTER_A 1 +#define AML_I2C_MASTER_B 2 +#define AML_I2C_MASTER_C 3 +#define AML_I2C_MASTER_D 4 + + +#define AML_I2C_SLAVE_ADDR 0x6c + +/*M1 i2c pinmux + * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE + * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13] + * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13] + * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17] + * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21] + * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6] + * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3] + * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14] + * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10] + * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29] + * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26] + * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10] + * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7] + * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28] + * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26] +*/ + +/*i2c master a*/ + + +#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9) +#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7) +#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9) +#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8) + +#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5) +#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22) +#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5) +#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23) + +/*i2c master b*/ + + +#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6) +#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7) + +#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14) +#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15) + +/*i2c master c*/ +#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4) +#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28) +#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4) +#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29) + +#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1) +#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22) +#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1) +#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23) + +/*i2c master d*/ + + +#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10) +#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10) +#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11) + +#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23) +#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7) +#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24) + +/*i2c master AO*/ + + +#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */ +#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8) +#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */ +#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9) + +/*i2c slave*/ +#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13) +#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13) + +#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14) +#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10) + +#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) +#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10) +#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) +#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7) + +#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17) +#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) +#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21) + +#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6) +#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) +#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3) + +#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) +#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29) +#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) +#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26) + +#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) +#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28) +#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) +#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26) + + +#define AML_I2C_SPPED_50K 50000 +#define AML_I2C_SPPED_100K 100000 +#define AML_I2C_SPPED_200K 200000 +#define AML_I2C_SPPED_300K 300000 +#define AML_I2C_SPPED_400K 400000 + +struct aml_pinmux_reg_bit { + unsigned long scl_reg; + unsigned long sda_reg; + unsigned int scl_bit; + unsigned int sda_bit; +}; + +struct aml_i2c_platform{ + unsigned int slave_addr;/*7bit addr*/ + unsigned int wait_count;/*i2c wait ack timeout = + wait_count * wait_ack_interval */ + unsigned int wait_ack_interval; + unsigned int wait_read_interval; + unsigned int wait_xfer_interval; + unsigned int master_no; + unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/ + unsigned int master_i2c_speed; + + /* only need 1 i2c master to comunicate with several devices, + * should I prepare 2 master interface to use simultaneously?*/ + struct resource * resource; + struct aml_pinmux_reg_bit master_ao_pinmux; + struct aml_pinmux_reg_bit master_a_pinmux; + struct aml_pinmux_reg_bit master_b_pinmux; + struct aml_pinmux_reg_bit master_c_pinmux; + struct aml_pinmux_reg_bit master_d_pinmux; + + struct aml_pinmux_reg_bit slave_reg_bit; +}; + +/**************i2c software gpio***************/ + +#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N) +#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O) +#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I) + +#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N) +#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O) +#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I) + +#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N) +#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O) +#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I) + +struct aml_sw_i2c_pins +{ + unsigned int scl_reg_out; + unsigned int scl_reg_in; + unsigned int scl_bit; + unsigned int scl_oe; + unsigned int sda_reg_out; + unsigned int sda_reg_in; + unsigned int sda_bit; + unsigned int sda_oe; +}; + + +struct aml_sw_i2c_platform { + struct aml_sw_i2c_pins sw_pins; + + /* local settings */ + int udelay; /* half clock cycle time in us, + minimum 2 us for fast-mode I2C, + minimum 5 us for standard-mode I2C and SMBus, + maximum 50 us for SMBus */ + int timeout; /* in jiffies */ +}; + + +#endif //__AML_MACH_I2C__ + +
diff --git a/arch/arm/include/asm/arch-sc2/io.h b/arch/arm/include/asm/arch-sc2/io.h new file mode 100644 index 0000000..fd3981a --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/io.h
@@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MACH_MESSON_REGS_IO_H +#define __MACH_MESSON_REGS_IO_H + +#ifndef __ASSEMBLY__ + +#include <asm/io.h> +#define IO_CBUS_BASE (0xFFD00000L) +#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */ +#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */ +#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */ +#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */ +#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */ + +#define CBUS_REG_OFFSET(reg) ((reg) << 2) +#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg)) + +#define AXI_REG_OFFSET(reg) ((reg) << 2) +#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg)) + +#define AHB_REG_OFFSET(reg) ((reg) << 2) +#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg)) + +#define VPU_REG_OFFSET(reg) ((reg) << 2) +#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg)) + + +#define APB_REG_OFFSET(reg) (reg) +#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg)) +#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) + +#define APB_HDMI_REG_OFFSET(reg) (reg) +#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg)) +#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0) + + +#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg)) +#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg))) +#define WRITE_CBUS_REG_BITS(reg, val, start, len) \ + WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_CBUS_REG_BITS(reg, start, len) \ + ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask)))) +#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask))) + +#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg)) +#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg))) +#define WRITE_AXI_REG_BITS(reg, val, start, len) \ + WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_AXI_REG_BITS(reg, start, len) \ + ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask)))) +#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask))) + +#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg)) +#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg))) +#define WRITE_AHB_REG_BITS(reg, val, start, len) \ + WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_AHB_REG_BITS(reg, start, len) \ + ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask)))) +#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask))) + +#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg)) +#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg))) +#define WRITE_APB_REG_BITS(reg, val, start, len) \ + WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_APB_REG_BITS(reg, start, len) \ + ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask)))) +#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask))) + +#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg)) +#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg))) +#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \ + WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start))) +#define READ_APB_HDMI_REG_BITS(reg, start, len) \ + ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1)) +#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask)))) +#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask))) + +/* for back compatible alias */ +#define WRITE_MPEG_REG(reg, val) \ + WRITE_CBUS_REG(reg, val) +#define READ_MPEG_REG(reg) \ + READ_CBUS_REG(reg) +#define WRITE_MPEG_REG_BITS(reg, val, start, len) \ + WRITE_CBUS_REG_BITS(reg, val, start, len) +#define READ_MPEG_REG_BITS(reg, start, len) \ + READ_CBUS_REG_BITS(reg, start, len) +#define CLEAR_MPEG_REG_MASK(reg, mask) \ + CLEAR_CBUS_REG_MASK(reg, mask) +#define SET_MPEG_REG_MASK(reg, mask) \ + SET_CBUS_REG_MASK(reg, mask) +#endif + + +#endif
diff --git a/arch/arm/include/asm/arch-sc2/mailbox.h b/arch/arm/include/asm/arch-sc2/mailbox.h new file mode 100644 index 0000000..466043c --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/mailbox.h
@@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + + /* + * + * Copyright (C) 2012 Amlogic, Inc. + * + * Author: Platform-SH@amlogic.com + * + */ + +#ifndef __MAILBOX_H__ +#define __MAILBOX_H__ +#include <asm/arch/secure_apb.h> + +#define REE2AO_SET_ADDR MAILBOX_SET_MBOX03 +#define REE2AO_STS_ADDR MAILBOX_STS_MBOX03 +#define REE2AO_CLR_ADDR MAILBOX_CLR_MBOX03 +#define REE2AO_WR_ADDR MAILBOX_WR_MBOX03 +#define REE2AO_RD_ADDR MAILBOX_RD_MBOX03 +#define REE2AO_IRQCLR_ADDR MAILBOX_IRQA_CLR + +#define MAILBOX_USER_DATA_SIZE 96 + +#define MHU_SYNC (1 << 26) +#define MHU_CMD_BUILD(command, size) \ + (((command) & 0xffff) | (((size) & 0x1ff) << 16) | MHU_SYNC) +#define MHU_ACK_MASK(mbox) (1 << ((mbox)*2 + 1)) + +#define MHU_PAYLOAD_SIZE 0x80 +#define MHU_DATA_OFFSET 0x1c +#define REE2AO_MBOX_ID 0x3 +/* ...Message composition with module(6bits), function(10bits) */ +#define __MBX_COMPOSE_MSG(mod, func) (((mod) << 10) | ((func) & 0x3FF)) + +/******************************************************************************* + * Define moudle type here, 6bits valid + ******************************************************************************/ +#define MBX_SYSTEM 0x0 + +/******************************************************************************* + * Define function here, 10bits valid + ******************************************************************************/ + /*SYSTEM*/ +#define CMD_UNDEFINE 0x0 +#define CMD_TEST 0x6 + +/******************************************************************************* + * Mssage Comopsition + ******************************************************************************/ +#define MBX_CMD_TEST __MBX_COMPOSE_MSG(MBX_SYSTEM, CMD_TEST) +enum { + HIFIA_REE_CHANNEL = 0, + HIFIB_REE_CHANNEL = 1, + SECPU_REE_CHANNEL = 2, + AOCPU_REE_CHANNEL = 3, +}; + +void mhu_init(void); +/*message max size MAILBOX_USER_DATA_SIZE 96 byte*/ +int scpi_send_data(uint32_t chan, uint32_t command, + void *sendmessage, uint32_t sendsize, + void *revmessage, uint32_t revsize); +#endif /* __SCPI_FIFO_H__ */ +
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr3.h new file mode 100644 index 0000000..c067367 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR3U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR3U_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // + // + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = DDR3 unbuffered + // 0x02 = Reserved + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A + + + + + + + + + + + + + + + + + + + + uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A + + + + uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A + // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset. + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A + + uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A + + uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A + + uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A + + uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A + + uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A + + uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A + + uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A + + uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A + + uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A + + uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A + + uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A + + uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A + + uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A + + uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A + + uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A + + uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A + + uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A + + uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A + + uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A + + uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A + + uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A + + uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A + + uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A + + uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A + + uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A + +} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4.h new file mode 100644 index 0000000..6dfd4d0 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR4U_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR4U_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D. + // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = Reserved + // 0x02 = DDR4 unbuffered + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = Run Reserved + // SequenceCtrl[11] = Run Reserved + // SequenceCtrl[12] = Run Reserved + // SequenceCtrl[13] = Run Reserved + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A + + + + + + + + + + + + + + + + + + + + uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A + + + + uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 3 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 2 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 3 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 2 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A + // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset. + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value of DDR mode register MR3 for all ranks for current pstate + uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value of DDR mode register MR4 for all ranks for current pstate + uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value of DDR mode register MR5 for all ranks for current pstate + uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0. + uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // X16 device map. Corresponds to CS[3:0]. + // X16Present[0] = CS0 is populated with X16 devices + // X16Present[1] = CS1 is populated with X16 devices + // X16Present[2] = CS2 is populated with X16 devices + // X16Present[3] = CS3 is populated with X16 devices + // X16Present[7:4] = Reserved (must be programmed to 0) + // + // Ranks may not contain mixed device types. + uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // controls timing of chip select signals when DDR4 gear-down mode is active + // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs + // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode + uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM: + // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0 + // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0 + // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0 + uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM: + // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1 + // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1 + // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1 + uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM: + // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2 + // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2 + // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2 + uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM: + // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3 + // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3 + // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3 + uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM: + // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4 + // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4 + // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4 + uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM: + // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5 + // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5 + // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5 + uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM: + // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6 + // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6 + // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6 + uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM: + // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7 + // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7 + // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7 + uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices. + uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices. + uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices. + uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices. + uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices. + uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices. + uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices. + uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices. + uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices. + uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices. + uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices. + uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices. + uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices. + uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices. + uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices. + uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices. + uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices. + uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices. + uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices. + uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices. + uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices. + uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices. + uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices. + uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices. + uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices. + uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices. + uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices. + uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices. + uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices. + uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices. + uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices. + uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices. + uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices. + uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices. + uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices. + uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices. + uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices. + uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices. + uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices. + uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices. + uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices. + uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices. + uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices. + uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices. + uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices. + uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices. + uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices. + uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices. + uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices. + uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices. + uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices. + uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices. + uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices. + uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices. + uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices. + uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices. + uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices. + uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices. + uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices. + uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices. + uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A + + uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A + + uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A + + uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A + + uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1). + // RdDBI is dynamically disabled in certain training steps, + // and so the [RdDBI disabled] CAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_CAS_L[0] == 0: use value in MR0 + // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2] + // Other bits are ignored + uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1). + // 2tCK write prambles are dynamically disabled in certain training steps, + // and so the [1tCK write preamble] WCAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_WCAS_L[0] == 0: use value in MR2 + // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3] + // Other bits are ignored + uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + // Contains various options for training DDR4 Devices. + // + // Bit fields: + // + // D4Misc[7:1] RFU, must be zero + // + // D4Misc[0] = protect memory reset + // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training. + // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training +} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4_2d.h new file mode 100644 index 0000000..35b1e23 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief DDR4U_2D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_DDR4U_2D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Train vrefDAC0 During Read Deskew + // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] = MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] = SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] = SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero) + // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D. + // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field + // + // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] = PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero) + // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte + // 0x0 = All rank populated with all the byte (tyical configuration) + // + // MsgMisc[7] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware. + // Please reference this revision ID when filing support cases with Synopsys. + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Module Type: + // 0x01 = Reserved + // 0x02 = DDR4 unbuffered + // 0x03 = Reserved + // 0x04 = Reserved + // 0x05 = Reserved + // + uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7): + // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting) + uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In + // Total number of DQ bits enabled in PHY + uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS. + // + // If the bit is set to 1, the CS is connected to DRAM. + // If the bit is set to 0, the CS is not connected to DRAM. + // + // CsPresent[0] = CS0 is populated with DRAM + // CsPresent[1] = CS1 is populated with DRAM + // CsPresent[2] = CS2 is populated with DRAM + // CsPresent[3] = CS3 is populated with DRAM + // CsPresent[7:4] = Reserved (must be programmed to 0) + // + // + uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 0 + uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // The CS signals from field CsPresent that are routed to DIMM connector 1 + uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In + // Corresponds to CS[3:0] + // 1 = Address Mirror. + // 0 = No Address Mirror. + uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In + // Additional mode bits. + // + // Bit fields: + // [0] SlowAccessMode : + // 1 = 2T Address Timing. + // 0 = 1T Address Timing. + // [7-1] RFU, must be zero + uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = RFU, must be zero + // SequenceCtrl[2] = RFU, must be zero + // SequenceCtrl[3] = RFU, must be zero + // SequenceCtrl[4] = RFU, must be zero + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = RFU, must be zero + // SequenceCtrl[9] = RFU, must be zero + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[15-14] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Bit fields, if 2D read training enabled, then use these additional options: + // [0] DFE + // 1 = Run rx2D with DFE + // 0 = Run rx2D with DFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Bit fields, if 2D write training is enabled, then use these additional options: + // [0] FFE + // 1 = Train tx2D with FFE + // 0 = Train tx2D with FFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5] FFE Decision Algorithm Control + // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy. + // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy. + // [6-7] RFU, must be zero + // + uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // Bitmap that designates the phy's vref source for every pstate + // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock. + // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training. + uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye. + uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye. + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D training in: Rd2D, Wr2D + // + // Reserved1E[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1E[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR6 + // 2 = limit to +/-4 %VDDQ from MR6 + // … + // 15 = limit to +/-30% VDDQ from MR6 + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved5D[0-3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 1 kilobit per point (legacy behavior) + // 1 = 2 kilobits per point + // 2 = 4 kilobits per point + // … + // 15 = 32 megabits per point + // + // Reserved5D[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved5D[5:7]: RFU, must be 0 + uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In + // Value of DDR mode register MR0 for all ranks for current pstate + uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Value of DDR mode register MR1 for all ranks for current pstate + uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In + // Value of DDR mode register MR2 for all ranks for current pstate + uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value of DDR mode register MR3 for all ranks for current pstate + uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value of DDR mode register MR4 for all ranks for current pstate + uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value of DDR mode register MR5 for all ranks for current pstate + uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0. + uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // X16 device map. Corresponds to CS[3:0]. + // X16Present[0] = CS0 is populated with X16 devices + // X16Present[1] = CS1 is populated with X16 devices + // X16Present[2] = CS2 is populated with X16 devices + // X16Present[3] = CS3 is populated with X16 devices + // X16Present[7:4] = Reserved (must be programmed to 0) + // + // Ranks may not contain mixed device types. + uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // controls timing of chip select signals when DDR4 gear-down mode is active + // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs + // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode + uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM: + // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0 + // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0 + // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0 + uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM: + // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1 + // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1 + // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1 + uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM: + // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2 + // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2 + // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2 + uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM: + // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3 + // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3 + // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3 + uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM: + // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4 + // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4 + // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4 + uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM: + // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5 + // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5 + // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5 + uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM: + // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6 + // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6 + // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6 + uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM: + // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care) + // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7 + // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7 + // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7 + uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In + // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In + // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In + // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In + // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT + uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut + // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices. + uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices. + uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut + // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices. + uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut + // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices. + uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices. + uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut + // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices. + uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut + // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices. + uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices. + uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut + // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices. + uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut + // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices. + uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices. + uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut + // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices. + uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut + // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices. + uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices. + uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut + // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices. + uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut + // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices. + uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices. + uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut + // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices. + uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut + // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices. + uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices. + uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut + // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices. + uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut + // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices. + uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices. + uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut + // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices. + uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut + // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices. + uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices. + uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut + // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices. + uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut + // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices. + uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices. + uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut + // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices. + uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut + // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices. + uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices. + uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut + // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices. + uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut + // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices. + uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices. + uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut + // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices. + uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut + // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices. + uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices. + uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut + // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices. + uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut + // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices. + uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices. + uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut + // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices. + uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut + // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices. + uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices. + uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut + // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices. + uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 0. Specifies MR6[6:0] + uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut + // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices. + uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices. + uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut + // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices. + uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 4. Specifies MR6[6:0] + uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut + // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices. + uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices. + uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut + // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices. + uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 8. Specifies MR6[6:0] + uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut + // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices. + uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices. + uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut + // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices. + uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 12. Specifies MR6[6:0] + uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut + // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices. + uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices. + uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut + // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices. + uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 16. Specifies MR6[6:0] + uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut + // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices. + uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices. + uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut + // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices. + uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A + + uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A + + uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A + + uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A + + uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A + + uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A + + uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A + + uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A + + uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A + + uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A + + uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A + + uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A + + uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A + + uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A + + uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A + + uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A + + uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A + + uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A + + uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A + + uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A + + uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A + + uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A + + uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A + + uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A + + uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A + + uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A + + uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A + + uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A + + uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A + + uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A + + uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A + + uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A + + uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A + + uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A + + uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A + + uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A + + uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A + + uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A + + uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A + + uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A + + uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A + + uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A + + uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A + + uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A + + uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A + + uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A + + uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A + + uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A + + uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A + + uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A + + uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A + + uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A + + uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A + + uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A + + uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A + + uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A + + uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A + + uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A + + uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A + + uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A + + uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A + + uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A + + uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A + + uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A + + uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A + + uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A + + uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A + + uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A + + uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A + + uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A + + uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A + + uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A + + uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A + + uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A + + uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A + + uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A + + uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A + + uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A + + uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A + + uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A + + uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A + + uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A + + uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A + + uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A + + uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A + + uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A + + uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A + + uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A + + uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A + + uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A + + uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A + + uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A + + uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A + + uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A + + uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A + + uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A + + uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A + + uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A + + uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A + + uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A + + uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A + + uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A + + uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A + + uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A + + uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A + + uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A + + uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A + + uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A + + uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A + + uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A + + uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A + + uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A + + uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A + + uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A + + uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A + + uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A + + uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A + + uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A + + uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A + + uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A + + uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A + + uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A + + uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A + + uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A + + uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A + + uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A + + uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A + + uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A + + uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A + + uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A + + uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A + + uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A + + uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A + + uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A + + uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A + + uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A + + uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A + + uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A + + uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A + + uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A + + uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A + + uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A + + uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A + + uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A + + uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A + + uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A + + uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A + + uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A + + uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A + + uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A + + uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A + + uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A + + uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A + + uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A + + uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A + + uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A + + uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A + + uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A + + uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A + + uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A + + uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A + + uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A + + uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A + + uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A + + uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A + + uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A + + uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A + + uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A + + uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A + + uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A + + uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A + + uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A + + uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A + + uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A + + uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A + + uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A + + uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A + + uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A + + uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A + + uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A + + uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A + + uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A + + uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A + + uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A + + uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A + + uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A + + uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A + + uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A + + uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A + + uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A + + uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A + + uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A + + uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A + + uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A + + uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A + + uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A + + uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A + + uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A + + uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A + + uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A + + uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A + + uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A + + uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A + + uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A + + uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A + + uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A + + uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A + + uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A + + uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A + + uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A + + uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A + + uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A + + uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A + + uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A + + uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A + + uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A + + uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A + + uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A + + uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A + + uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A + + uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A + + uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A + + uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A + + uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A + + uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A + + uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A + + uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A + + uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A + + uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A + + uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A + + uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A + + uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A + + uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A + + uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A + + uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A + + uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A + + uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A + + uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A + + uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A + + uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A + + uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A + + uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A + + uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A + + uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A + + uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A + + uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A + + uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A + + uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A + + uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A + + uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A + + uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A + + uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A + + uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A + + uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A + + uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A + + uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A + + uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A + + uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A + + uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A + + uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A + + uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A + + uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A + + uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A + + uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A + + uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A + + uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A + + uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A + + uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A + + uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A + + uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A + + uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A + + uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A + + uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A + + uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A + + uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A + + uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A + + uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A + + uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A + + uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A + + uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A + + uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A + + uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A + + uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A + + uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A + + uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A + + uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A + + uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A + + uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A + + uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A + + uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A + + uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A + + uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A + + uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A + + uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A + + uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A + + uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A + + uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A + + uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A + + uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A + + uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A + + uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A + + uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A + + uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A + + uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A + + uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A + + uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A + + uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A + + uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A + + uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A + + uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A + + uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A + + uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A + + uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A + + uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A + + uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A + + uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A + + uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A + + uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A + + uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A + + uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A + + uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A + + uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A + + uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A + + uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A + + uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A + + uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A + + uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A + + uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A + + uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A + + uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A + + uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A + + uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A + + uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A + + uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A + + uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A + + uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A + + uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A + + uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A + + uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A + + uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A + + uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A + + uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A + + uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A + + uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A + + uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A + + uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A + + uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A + + uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A + + uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A + + uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A + + uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A + + uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A + + uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A + + uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A + + uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A + + uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A + + uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A + + uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A + + uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A + + uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A + + uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A + + uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A + + uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A + + uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A + + uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A + + uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A + + uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A + + uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A + + uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A + + uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A + + uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A + + uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A + + uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A + + uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A + + uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A + + uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A + + uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A + + uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A + + uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A + + uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A + + uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A + + uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A + + uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A + + uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A + + uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A + + uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A + + uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A + + uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A + + uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A + + uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A + + uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A + + uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A + + uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A + + uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A + + uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A + + uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A + + uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A + + uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A + + uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A + + uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A + + uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A + + uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A + + uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in + // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1). + // RdDBI is dynamically disabled in certain training steps, + // and so the [RdDBI disabled] CAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_CAS_L[0] == 0: use value in MR0 + // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2] + // Other bits are ignored + uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In + // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1). + // 2tCK write prambles are dynamically disabled in certain training steps, + // and so the [1tCK write preamble] WCAS Latency must be provided in this field. + // The required encoding is as follows: + // ALT_WCAS_L[0] == 0: use value in MR2 + // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3] + // Other bits are ignored + uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In + // Contains various options for training DDR4 Devices. + // + // Bit fields: + // + // D4Misc[7:1] RFU, must be zero + // + // D4Misc[0] = protect memory reset + // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training. + // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training +} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr3.h new file mode 100644 index 0000000..6850d06 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR3_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR3_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:5] RFU, must be zero + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] RFU, must be zero + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.75*VDDQ, set this field to 0x60. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[10] = RFU, must be zero + // SequenceCtrl[11] = RFU, must be zero + // SequenceCtrl[12] = Run LPCA - CA Training + // SequenceCtrl[13] = RFU, must be zero + // SequenceCtrl[14] = RFU, must be zero + // SequenceCtrl[15] = RFU, must be zero + // + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // This should be set to 1 for all systems. + // + // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value: + // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0 + // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0] + uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value: + // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1 + // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0] + uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value: + // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2 + // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0] + uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value: + // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3 + // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0] + uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value: + // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4 + // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0] + uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value: + // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5 + // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0] + uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value: + // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6 + // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0] + uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value: + // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7 + // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0] + uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In + // This field is reserved and must be programmed to 0x00. + uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In + // Must be programmed the same as MR1_A0 + uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In + // Must be programmed the same as MR2_A0 + uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In + // Must be programmed the same as MR3_A0 + uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In + // Must be programmed the same as MR11_A0 + uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A + // This field is reserved and must be programmed to 0x00. +} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4.h new file mode 100644 index 0000000..d194621 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR4_1D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR4_1D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Quick Rd2D during 1D Training + // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] Disable Boot Clock + // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended) + // 0x0 = Use Boot Frequency Clock + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.25*VDDQ, set this field to 0x20. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Lp4 specific options for training. + // + // Bit fields: + // + // Lp4Misc[0] Enable dfi_reset_n + // + // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training. + // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + // + // 0x1 = Enables dfi_reset_n to control memreset after training. + // PHY Internal registers control memreset during training only. + // To ensure that no glitches occur on BP_MEMRESET at the end of training, + // The MC must drive dfi_reset_n=1'b1 _prior to starting training_ + // + // Lp4Misc[7-1] RFU, must be zero + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved0E[0:3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 288 bits per point (legacy behavior) + // 1 = 576 bits per point + // 2 = 1.125 kilobits per point + // … + // 15 = 9 megabits per point + // + // Reserved0E[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved0E[5:7]: RFU, must be 0 + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = Run WrLvl - Write leveling + // SequenceCtrl[2] = Run RxEn - Read gate training + // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training + // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training + // SequenceCtrl[5] = RFU, must be zero + // SequenceCtrl[6] = RFU, must be zero + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training + // SequenceCtrl[9] = Run MxRdLat - Max read latency training + // SequenceCtrl[11-10] = RFU, must be zero + // SequenceCtrl[12] = Run LPCA - CA Training + // SequenceCtrl[15-13] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // It is recommended in most LPDDR4 system configurations to set this to 1. + // + // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels. + // + uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In + // Enable Quickboot. + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D stages: Rd2D, Wr2D + // + // Reserved1A[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1A[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR14 + // 2 = limit to +/-4 %VDDQ from MR14 + // … + // 15 = limit to +/-30% VDDQ from MR14 + uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // CA training option bit field + // [0] CA VREF Training + // 1 = Enable CA VREF Training + // 0 = Disable CA VREF Training + // [1-7] RFU must be zero + uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // X8 mode configuration: + // 0x0 = x16 configuration for all devices + // 0xF = x8 configuration for all devices + // All other values are RFU + uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A + + + + + + + + + + + + + + + + + uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A + + + + uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A + + uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A + + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0} + uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0} + uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0} + uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0} + uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0} + uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1} + uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1} + uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1} + uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1} + uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1} + uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1} + uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1} + uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1} + uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1} + uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1} + uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In + // Terminating Rank for CA bus on Channel A + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + + uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A + + uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A + + uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A + + uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A + + uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A + + uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A + + uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A + + uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A + + uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A + + uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A + + uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0} + uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0} + uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0} + uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0} + uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0} + uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0} + uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0} + uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0} + uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0} + uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0} + uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1} + uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1} + uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1} + uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1} + uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1} + uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1} + uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1} + uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1} + uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1} + uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1} + uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + // Terminating Rank for CA bus on Channel B + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A + + uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A + + uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A + + uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A + + uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A + + uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A + + uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A + + uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A + +} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4_2d.h new file mode 100644 index 0000000..c6ab3d3 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/** \brief LPDDR4_2D training firmware message block structure + * + * Please refer to the Training Firmware App Note for futher information about + * the usage for Message Block. + */ +typedef struct _PMU_SMB_LPDDR4_2D_t { + uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In + // Reserved00[0:4] RFU, must be zero + // + // Reserved00[5] = Quick Rd2D during 1D Training + // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes. + // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes. + // + // Reserved00[6] = Enable High Effort WrDQ1D + // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns. + // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns + // + // Reserved00[7] = Optimize for the special hard macros in TSMC28. + // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node. + // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0. + uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In + // Contains various global options for training. + // + // Bit fields: + // + // MsgMisc[0] MTESTEnable + // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output. + // 0x0 = Do not pulse primary digital test output bump + // + // MsgMisc[1] SimulationOnlyReset + // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns. + // Must never be set to 1 in silicon. + // 0x0 = Use reset pulse length specifed by JEDEC standard + // + // MsgMisc[2] SimulationOnlyTraining + // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations. + // Must never be set to 1 in silicon. + // 0x0 = Use standard training duration. + // + // MsgMisc[3] Disable Boot Clock + // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended) + // 0x0 = Use Boot Frequency Clock + // + // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting. + // Stage Completion messages, as well as training completion and error messages are + // Still sent depending on HdtCtrl setting. + // + // MsgMisc[5] PerByteMaxRdLat + // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI. + // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI. + // + // MsgMisc[7-6] RFU, must be zero + // + // Notes: + // + // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset. + uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out + // PMU firmware revision ID + // After training is run, this address will contain the revision ID of the firmware + uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In + // Must be set to the target Pstate to be trained + // 0x0 = Pstate 0 + // 0x1 = Pstate 1 + // 0x2 = Pstate 2 + // 0x3 = Pstate 3 + // All other encodings are reserved + uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In + // Set according to whether target Pstate uses PHY PLL bypass + // 0x0 = PHY PLL is enabled for target Pstate + // 0x1 = PHY PLL is bypassed for target Pstate + uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In + // DDR data rate for the target Pstate in units of MT/s. + // For example enter 0x0640 for DDR1600. + uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In + // Frequency ratio betwen DfiCtlClk and SDRAM memclk. + // 0x1 = 1:1 + // 0x2 = 1:2 + // 0x4 = 1:4 + uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In + // Must be programmed to match the precision resistor connected to Phy BP_ZN + // 0x00 = Do not program. Use current CSR value. + // 0xf0 = 240 Ohm (recommended value) + // 0x78 = 120 Ohm + // 0x28 = 40 Ohm + // All other values are reserved. + // + uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In + // Must be programmed to the termination impedance in ohms used by PHY during reads. + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal termination impedance values. + // + // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In + // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS). + // + // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start) + // + // See PHY databook for legal R_on driver impedance values. + // + // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods. + uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In + // Must be programmed with the Vref level to be used by the PHY during reads + // + // The units of this field are a percentage of VDDQ according to the following equation: + // + // Receiver Vref = VDDQ*PhyVref[6:0]/128 + // + // For example to set Vref at 0.25*VDDQ, set this field to 0x20. + // + // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system. + uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In + // Lp4 specific options for training. + // + // Bit fields: + // + // Lp4Misc[0] Enable dfi_reset_n + // + // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training. + // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. + // + // 0x1 = Enables dfi_reset_n to control memreset after training. + // PHY Internal registers control memreset during training only. + // To ensure that no glitches occur on BP_MEMRESET at the end of training, + // The MC must drive dfi_reset_n=1'b1 _prior to starting training_ + // + // Lp4Misc[7-1] RFU, must be zero + uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In + // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D. + // + // Reserved0E[0:3]: bitTimeControl + // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point. + // 0 = 288 bits per point (legacy behavior) + // 1 = 576 bits per point + // 2 = 1.125 kilobits per point + // … + // 15 = 9 megabits per point + // + // Reserved0E[4]: Exhaustive2D + // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior) + // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point. + // + // Reserved0E[5:7]: RFU, must be 0 + uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out + // This field will be set if training fails on any rank. + // 0x0 = No failures + // non-zero = one or more ranks failed training + uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In + // Controls the training steps to be run. Each bit corresponds to a training step. + // + // If the bit is set to 1, the training step will run. + // If the bit is set to 0, the training step will be skipped. + // + // Training step to bit mapping: + // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set. + // SequenceCtrl[1] = RFU, must be zero + // SequenceCtrl[2] = RFU, must be zero + // SequenceCtrl[3] = RFU, must be zero + // SequenceCtrl[4] = RFU, must be zero + // SequenceCtrl[5] = Run rd2D - 2d read dqs training + // SequenceCtrl[6] = Run wr2D - 2d write dq training + // SequenceCtrl[7] = RFU, must be zero + // SequenceCtrl[8] = RFU, must be zero + // SequenceCtrl[9] = RFU, must be zero + // SequenceCtrl[11-10] = RFU, must be zero + // SequenceCtrl[12] = RFU, must be zero + // SequenceCtrl[15-13] = RFU, must be zero + uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In + // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below: + // + // 0x05 = Detailed debug messages (e.g. Eye delays) + // 0x0A = Coarse debug messages (e.g. rank information) + // 0xC8 = Stage completion + // 0xC9 = Assertion messages + // 0xFF = Firmware completion messages only + // + // See Training App Note for more detailed information on what messages are included for each threshold. + // + uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In + // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value. + // + // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system. + uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A + // This field is reserved and must be programmed to 0x00. + uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In + // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired. + // + // 0x0 = Use MR<0:17>_A0 for rank 0 channel A + // Use MR<0:17>_B0 for rank 0 channel B + // Use MR<0:17>_A1 for rank 1 channel A + // Use MR<0:17>_B1 for rank 1 channel B + // + // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks + // + // It is recommended in most LPDDR4 system configurations to set this to 1. + // + // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels. + // + uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A + + uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In + // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0. + // Used by 2D stages: Rd2D, Wr2D + // + // Reserved1A[0-3]: Rd2D Voltage Range + // 0 = Training will search all phy vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from phyVref + // 2 = limit to +/-4 %VDDQ from phyVref + // … + // 15 = limit to +/-30% VDDQ from phyVref + // + // Reserved1A[4-7]: Wr2D Voltage Range + // 0 = Training will search all dram vref(DQ) settings + // 1 = limit to +/-2 %VDDQ from MR14 + // 2 = limit to +/-4 %VDDQ from MR14 + // … + // 15 = limit to +/-30% VDDQ from MR14 + uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In + // CA training option bit field + // [0] CA VREF Setting + // 1 = Set MR12 from internal register + // 0 = Set MR12 from message block + // [1-7] RFU must be zero + uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In + // X8 mode configuration: + // 0x0 = x16 configuration for all devices + // 0xF = x8 configuration for all devices + // All other values are RFU + uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In + // Bit fields, if 2D read training enabled, then use these additional options: + // [0] DFE + // 1 = Run rx2D with DFE + // 0 = Run rx2D with DFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In + // Bit fields, if 2D write training is enabled, then use these additional options: + // [0] FFE + // 1 = Train tx2D with FFE + // 0 = Train tx2D with FFE off + // [1-2] Voltage Step Size (2^n) + // 3 = 8 DAC settings between checked values + // 2 = 4 DAC settings between checked values + // 1 = 2 DAC settings between checked values + // 0 = 1 DAC settings between checked values + // [3-4] Delay Step Size (2^n) + // 3 = 8 LCDL delays between checked values + // 2 = 4 LCDL delays between checked values + // 1 = 2 LCDL delays between checked values + // 0 = 1 LCDL delays between checked values + // [5-7] RFU, must be zero + // + uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In + // Bitmap that designates the phy's vref source for every pstate + // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock. + // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training. + uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye. + uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In + // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye. + uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In + // Override PhyConfig csr. + // 0x0: Use hardware csr value for PhyConfing (recommended) + // Other values: Use value for PhyConfig instead of Hardware value. + // + uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In + // Total number of DQ bits enabled in PHY Channel A + uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel A. + // + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel A + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0} + uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0} + uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0} + uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0} + uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0} + uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0} + uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0} + uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0} + uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0} + uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0} + uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0} + uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0} + uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1} + uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1} + uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1} + uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1} + uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1} + uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1} + uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1} + uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1} + uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1} + uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1} + uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1} + uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1} + uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In + // Terminating Rank for CA bus on Channel A + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A + + uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A + + uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out + // Trained DQ Vref setting for Ch A Rank 0 + uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out + // Trained DQ Vref setting for Ch A Rank 1 + uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In + // Total number of DQ bits enabled in PHY Channel B + uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In + // Indicates presence of DRAM at each chip select for PHY channel B. + // + // 0x0 = No chip selects are populated with DRAM + // 0x1 = CS0 is populated with DRAM + // 0x3 = CS0 and CS1 are populated with DRAM + // + // All other encodings are illegal + // + int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Read to write critical delay difference from cs01 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to read critical delay difference from cs 0 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 1 to cs 0 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out + // This is a signed integer value. + // Write to write critical delay difference from cs 0 to cs 1 on Channel B + // See PUB Databook section 8.2 for details on use of CDD values. + uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0} + uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0} + uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0} + uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0} + uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0} + uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0} + uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0} + uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0} + uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0} + uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0} + uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0} + uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0} + uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In + // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1} + uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1} + uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In + // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1} + uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1} + uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In + // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1} + uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1} + uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In + // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1} + uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1} + uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In + // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1} + uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1} + uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In + // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1} + uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In + // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1} + uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In + // Terminating Rank for CA bus on Channel B + // 0x0 = Rank 0 is terminating rank + // 0x1 = Rank 1 is terminating rank + uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A + + uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A + + uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out + // Trained DQ Vref setting for Ch B Rank 0 + uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out + // Trained DQ Vref setting for Ch B Rank 1 + uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out + // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group. + uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out + // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group. + uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out + // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group. +} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-sc2/nand.h b/arch/arm/include/asm/arch-sc2/nand.h new file mode 100644 index 0000000..91484ac --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/nand.h
@@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __NAND_H__ +#define __NAND_H__ +#include <asm/arch/cpu_config.h> + +#ifndef SD_EMMC_BASE_C +#define SD_EMMC_BASE_C 0xd0074000 +#endif + +#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11)) +#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C) +#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00) +#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04) +#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08) +#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c) +#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10) +#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14) +#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18) +#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c) +#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20) +#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24) +#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28) +#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c) + +#define CEF (0xf<<10) +#define CE0 (0xe<<10) +#define CE1 (0xd<<10) +#define CE2 (0xb<<10) +#define CE3 (0x7<<10) + +#define IO4 ((0xe<<10)|(1<<18)) +#define IO5 ((0xd<<10)|(1<<18)) +#define IO6 ((0xb<<10)|(1<<18)) + +#define CLE (0x5<<14) +#define ALE (0x6<<14) +#define DWR (0x4<<14) +#define DRD (0x8<<14) +#define IDLE (0xc<<14) +#define RB (1<<20) + +#define M2N ((0<<17) | (2<<20) | (1<<19)) +#define N2M ((1<<17) | (2<<20) | (1<<19)) +#define STS ((3<<17) | (2<<20)) +#define ADL ((0<<16) | (3<<20)) +#define ADH ((1<<16) | (3<<20)) +#define AIL ((2<<16) | (3<<20)) +#define AIH ((3<<16) | (3<<20)) +#define ASL ((4<<16) | (3<<20)) +#define ASH ((5<<16) | (3<<20)) +#define SEED ((8<<16) | (3<<20)) + +// NAND Flash Manufacturer ID Codes +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec +#define NAND_MFR_FUJITSU 0x04 +#define NAND_MFR_NATIONAL 0x8f +#define NAND_MFR_RENESAS 0x07 +#define NAND_MFR_STMICRO 0x20 +#define NAND_MFR_HYNIX 0xad +#define NAND_MFR_MICRON 0x2c +#define NAND_MFR_AMD 0x01 +#define NAND_MFR_INTEL 0x89 +#define NAND_MFR_SANDISK 0x45 +#define NAND_MFR_USER 0x100 +#define NAND_MFR_EFUSE 0x101 + +typedef struct nand_setup { + union { + uint32_t d32; + struct { + unsigned cmd:22; + unsigned large_page:1; // 22 + unsigned no_rb:1; // 23 from efuse + unsigned a2:1; // 24 + unsigned reserved25:1; // 25 + unsigned page_list:1; // 26 + unsigned sync_mode:2; // 27 from efuse + unsigned size:2; // 29 from efuse + unsigned active:1; // 31 + } b; + } cfg; + uint16_t id; + uint16_t max; // id:0x100 user, max:0 disable. +} nand_setup_t; + +typedef struct _nand_cmd{ + unsigned char type; + unsigned char val; +} nand_cmd_t; + +typedef struct _ext_info{ + uint32_t read_info; //nand_read_info; + uint32_t new_type; //new_nand_type; + uint32_t page_per_blk; //pages_in_block; + uint32_t xlc; //slc=1, mlc=2, tlc=3. + uint32_t rsv1[5]; +} ext_info_t; + +typedef struct _nand_page0 { + nand_setup_t nand_setup; //8 + unsigned char page_list[16]; //16 + nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F) + ext_info_t ext_info; //64 +} nand_page0_t; //384 bytes max. + +//#define NAND_PAGE0_BUF BL1_NAND_BUFF +#define NAND_PAGE0_BUF (0x1800000) +#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t)) +#define NAND_RETRY_USER (NAND_PAGE_LIST + 16) +#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512) +#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1) +//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1) + +#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num))) +#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) // +#define ERROR_NAND_ECC ERROR_MOD(2,2) // +#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) // +#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) // +#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) // +#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) // + +#define NAND_SECTOR_SIZE (512) +#define NAND_MAX_PAGESIZE (0x4000) //16K +#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE) + +#define INFO_BYTE_PER_ECCPAGE (8) +uint32_t nfio_init(void); +uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size); +#endif /* __NAND_H__ */ +
diff --git a/arch/arm/include/asm/arch-sc2/oscring.h b/arch/arm/include/asm/arch-sc2/oscring.h new file mode 100644 index 0000000..15e259e --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/oscring.h
@@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __OSCRING_H__ +#define __OSCRING_H__ + +#define OSCRING_CTL_REG0 SYSCTRL_OSC_RING_CTRL0 +#define OSCRING_CTL_DATA0 0x51555555 /*0:25*/ +#define OSCRING_CTL_REG1 SYSCTRL_OSC_RING_CTRL1 +#define OSCRING_CTL_DATA1 0x80000005 /*0:7*/ + +#define RING_PWM_VCCK PWMIJ_PWM_B +#define RING_PWM_EE PWMGH_PWM_B + +int ring_msr(int index); +#endif
diff --git a/arch/arm/include/asm/arch-sc2/pinctrl_init.h b/arch/arm/include/asm/arch-sc2/pinctrl_init.h new file mode 100644 index 0000000..cfbc42a --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/pinctrl_init.h
@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _MESON_PINCTRL_INIT_H_ +#define _MESON_PINCTRL_INIT_H_ + +#define PIN_CONTROLLER_NUM 2 +extern int pinctrl_devices_active(int pinctrl_num); + +#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-sc2/pll.h b/arch/arm/include/asm/arch-sc2/pll.h new file mode 100644 index 0000000..d89ab5e --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/pll.h
@@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __PLL_H +#define __PLL_H + +#define PLL_TEST_SYS_TOTAL 2 +#define PLL_TEST_HIFI_TOTAL 2 +#define PLL_TEST_GP0_TOTAL 2 +#define PLL_TEST_GP1_TOTAL 2 +#define PLL_TEST_HDMI_TOTAL 2 + +typedef struct sys_pll_set_s { + unsigned int cpu_clk; + unsigned int pll_cntl; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; +}sys_pll_set_t; + +typedef struct sys_pll_cfg_s { + sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL]; +}sys_pll_cfg_t; + +typedef struct hdmi_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; +}hdmi_pll_set_t; + +typedef struct hdmi_pll_cfg_s { + hdmi_pll_set_t hdmi_pll[PLL_TEST_HDMI_TOTAL]; +}hdmi_pll_cfg_t; + +typedef struct gpll_rate_table_s { + unsigned int rate; + unsigned int m; + unsigned int n; + unsigned int od; +}gpll_rate_table_t; + +typedef struct hifipll_rate_table_s { + unsigned int rate; + unsigned int m; + unsigned int n; + unsigned int od; +}hifipll_rate_table_t; + +typedef struct gp0_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; +}gp0_pll_set_t; + +typedef struct gp0_pll_cfg_s { + gp0_pll_set_t gp0_pll[PLL_TEST_GP0_TOTAL]; +}gp0_pll_cfg_t; + +typedef struct gp1_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; +}gp1_pll_set_t; + +typedef struct gp1_pll_cfg_s { + gp1_pll_set_t gp1_pll[PLL_TEST_GP1_TOTAL]; +}gp1_pll_cfg_t; + +typedef struct hifi_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; +}hifi_pll_set_t; + +typedef struct hifi_pll_cfg_s { + hifi_pll_set_t hifi_pll[PLL_TEST_HIFI_TOTAL]; +}hifi_pll_cfg_t; + +typedef struct pcie_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; +}pcie_pll_set_t; + +typedef struct ethphy_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; +}ethphy_pll_set_t; + +typedef struct usbphy_pll_set_s { + unsigned int pll_clk; + unsigned int pll_cntl0; + unsigned int pll_cntl1; + unsigned int pll_cntl2; + unsigned int pll_cntl3; + unsigned int pll_cntl4; + unsigned int pll_cntl5; + unsigned int pll_cntl6; + unsigned int pll_cntl7; +}usbphy_pll_set_t; + +struct pciepll_rate_table { + u16 rate; + u16 m; + u16 n; + u16 od; + u16 od2; + u16 frac; +}; + +#define PLL_RATE(_r, _m, _n, _od) \ + { \ + .rate = (_r), \ + .m = (_m), \ + .n = (_n), \ + .od = (_od), \ + } \ + +enum pll_enum { + PLL_SYS = 0, + PLL_FIX, + PLL_DDR, + PLL_HDMI, + PLL_GP0, + PLL_HIFI, + PLL_PCIE, + PLL_GP1, + PLL_USBPHY, + PLL_ENUM, + +}; + +int pll_test(int argc, char * const argv[]); + +#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-sc2/pwr_ctrl.h b/arch/arm/include/asm/arch-sc2/pwr_ctrl.h new file mode 100644 index 0000000..f264248 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/pwr_ctrl.h
@@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#define PWR_ON 1 +#define PWR_OFF 0 + +enum pm_e { + PM_DSP = 0, + PM_DOS_HCODEC, + PM_DOS_HEVC, + PM_DOS_VDEC, + PM_DOS_WAVE, + PM_VPU_HDMI, + PM_USB_COMB, + PM_PCIE, + PM_GE2D, + PM_ETH, + PM_AUDIO +}; + +unsigned long pwr_ctrl_psci_smc(enum pm_e power_domain, bool power_control); \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-sc2/reboot.h b/arch/arm/include/asm/arch-sc2/reboot.h new file mode 100644 index 0000000..8061f7b --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/reboot.h
@@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __REBOOT_H +#define __REBOOT_H + +#include "soc_def.h" + +/* +Reboot reason AND corresponding env setting: +0: Cold boot cold_boot +1: Normal boot normal +2: Factory reset factory_reset +3: Upgrade system update +4: Fastboot fastboot +5: Suspend suspend_off +6: Hibernate hibernate +7: Fastboot Bootloader bootloader +8: Shutdown reboot shutdown_reboot +9: RPMBP reboot rpmbp +10: quiescent reboot quiescent reboot +11: Crash dump crash_dump +12: Kernel panic kernel_panic +13: Watchdog reboot watchdog_reboot +14: quiescent recovery reboot quiescent recovery +15: reserved +*/ +#define AMLOGIC_COLD_BOOT 0 +#define AMLOGIC_NORMAL_BOOT 1 +#define AMLOGIC_FACTORY_RESET_REBOOT 2 +#define AMLOGIC_UPDATE_REBOOT 3 +#define AMLOGIC_FASTBOOT_REBOOT 4 +#define AMLOGIC_SUSPEND_REBOOT 5 +#define AMLOGIC_HIBERNATE_REBOOT 6 +#define AMLOGIC_BOOTLOADER_REBOOT 7 /* fastboot bootloader */ +#define AMLOGIC_SHUTDOWN_REBOOT 8 +#define AMLOGIC_RPMBP_REBOOT 9 +#define AMLOGIC_QUIESCENT_REBOOT 10 +#define AMLOGIC_CRASH_REBOOT 11 +#define AMLOGIC_KERNEL_PANIC 12 +#define AMLOGIC_WATCHDOG_REBOOT 13 +#define AMLOGIC_RECOVERY_QUIESCENT_REBOOT 14 + +/* +old version env +0x01010101, normal +0x02020202, factory_reset +0x03030303, update +0x09090909, usb_burning +0x0b0b0b0b, suspend_off +*/ + +#endif +
diff --git a/arch/arm/include/asm/arch-sc2/register.h b/arch/arm/include/asm/arch-sc2/register.h new file mode 100644 index 0000000..4d9db70 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/register.h
@@ -0,0 +1,28525 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifdef REGISTER_H +#else +#define REGISTER_H + +// +// Reading file: ./REG_LIST_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +//`define DMC_SEC_REG_BASE 32'hfe037000 +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe037000 +// ----------------------------------------------- +#define DMC_SEC_RANGE0_CTRL ((0x0000 << 2) + 0xfe037000) + //default : 32'hffff0000 + //bit 31:16 | 0 | range0_eda | range 0 end address higher 16bits. + //bit 15:0 | 0 | range0_sta | range 0 start address higher 16bits. +#define DMC_SEC_RANGE0_CTRL1 ((0x0001 << 2) + 0xfe037000) + //default : 32'h00000003 + //bit 7:5 | 0 | range0_secrity_level | range0 secruity level for DMA and DEMUX only. + //bit 4 | 0 | range0_prot_en | range0 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range0_local_des_en | range0 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not. + //bit 2 | 0 | range0_lock | lock range 0 registers. write 1 to lock range 0 register. can't change anymore. + //bit 1 | 0 | range0_key_sel | range 0 data describle key selection. 1 : key1. 0 : key0. + //bit 0 | 0 | range0_en | range 0 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE1_CTRL ((0x0002 << 2) + 0xfe037000) + //default : 32'hffffffff + //bit 31:16 | 0 | range1_eda | range 1 end address higher 16bits. + //bit 15:0 | 0 | range1_sta | range 1 start address higher 16bits. +#define DMC_SEC_RANGE1_CTRL1 ((0x0003 << 2) + 0xfe037000) + //default : 0 + //bit 7:5 | 0 | range1_secrity_level | range1 secruity level for DMA and DEMUX only. + //bit 4 | 0 | range1_prot_en | range1 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range1_local_des_en | range1 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not. + //bit 2 | 0 | range1_lock | lock range 1 registers. write 1 to lock range 1 register. can't change anymore. + //bit 1 | 0 | range1_key_sel | range 1 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | range1_en | range 0 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE2_CTRL ((0x0004 << 2) + 0xfe037000) + //default : 32'hffffffff + //bit 31:16 | 0 | range2_eda | range 2 end address higher 16bits. + //bit 15:0 | 0 | range2_sta | range 2 start address higher 16bits. +#define DMC_SEC_RANGE2_CTRL1 ((0x0005 << 2) + 0xfe037000) + //default : 0 + //bit 7:5 | 0 | range2_secrity_level | range2 secruity level for DMA and DEMUX only. + //bit 4 | 0 | range2_prot_en | range2 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range2_local_des_en | range2 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not. + //bit 2 | 0 | range2_lock | lock range 2 registers. write 1 to lock range 2 register. can't change anymore. + //bit 1 | 0 | range2_key_sel | range 2 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | range2_en | range 2 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE3_CTRL ((0x0006 << 2) + 0xfe037000) + //default : 32'hffffffff + //bit 31:16 | 0 | range3_eda | range 3 end address higher 16bits. + //bit 15:0 | 0 | range3_sta | range 3 start address higher 16bits. +#define DMC_SEC_RANGE3_CTRL1 ((0x0007 << 2) + 0xfe037000) + //default : 0 + //bit 7:5 | 0 | range3_secrity_level | range3 secruity level for DMA and DEMUX only. + //bit 4 | 0 | range3_prot_en | range3 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range3_local_des_en | range3 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not. + //bit 2 | 0 | range3_lock | lock range 3 registers. write 1 to lock range 3 related registers. can't change anymore. + //bit 1 | 0 | range3_key_sel | range 3 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | range3_en | range 3 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE4_CTRL ((0x0008 << 2) + 0xfe037000) + //default : 32'hffffffff + //bit 31:16 | 0 | range4_eda | range 4 end address higher 16bits. + //bit 15:0 | 0 | range4_sta | range 4 start address higher 16bits. +#define DMC_SEC_RANGE4_CTRL1 ((0x0009 << 2) + 0xfe037000) + //default : 0 + //bit 7:5 | 0 | range4_secrity_level | range4 secruity level for DMA and DEMUX only. + //bit 4 | 0 | range4_prot_en | range4 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range4_local_des_en | range4 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not. + //bit 2 | 0 | range4_lock | lock range 4 registers. write 1 to lock range 4 related registers. can't change anymore. + //bit 1 | 0 | range4_key_sel | range 4 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | range4_en | range 4 enable bit. 1 : enable, 0 : disable. +#define DMC_SEC_RANGE5_CTRL ((0x000a << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE5_CTRL1 ((0x000b << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_CTRL ((0x000c << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE6_CTRL1 ((0x000d << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_CTRL ((0x000e << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE7_CTRL1 ((0x000f << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_CTRL ((0x0010 << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE8_CTRL1 ((0x0011 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_CTRL ((0x0012 << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE9_CTRL1 ((0x0013 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_CTRL ((0x0014 << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE10_CTRL1 ((0x0015 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_CTRL ((0x0016 << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE11_CTRL1 ((0x0017 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_CTRL ((0x0018 << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE12_CTRL1 ((0x0019 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_CTRL ((0x001a << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE13_CTRL1 ((0x001b << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_CTRL ((0x001c << 2) + 0xfe037000) + //default : 32'hffffffff +#define DMC_SEC_RANGE14_CTRL1 ((0x001d << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_CTRL1 ((0x001f << 2) + 0xfe037000) + //default : 0 + //bit 7:5 | 0 | range1_secrity_level | range1 secruity level for DMC and DEMUX only. + //bit 4 | 0 | range1_prot_en | range1 allow protect monitor function. 1: allowed. 0: not allowed. + //bit 3 | 0 | range1_local_des_en | range1 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not. + //bit 2 | 0 | range1_lock | lock range 1 registers. write 1 to lock range 1 register. can't change anymore. + //bit 1 | 0 | range1_key_sel | range 1 data describle key selection. 1 : key1. 1 : key0. + //bit 0 | 0 | not used. range 15 is always enabled. +//per range per sub ID access enable. +//there's 128 of read id accessable control bits per range. +// this 128bit are consist of {DMC_SEC_RANGEx_RID_CTRL3, DMC_SEC_RANGEx_RID_CTRL2, DMC_SEC_RANGEx_RID_CTRL1, DMC_SEC_RANGEx_RID_CTRL0} +//there's 128 of write id accessable control bits per range. +// this 128bit are consist of {DMC_SEC_RANGEx_WID_CTRL3, DMC_SEC_RANGEx_WID_CTRL2, DMC_SEC_RANGEx_WID_CTRL1, DMC_SEC_RANGEx_WID_CTRL0} +//bit 127:112. HCODEC based 16 subids. +//bit 111:96 VDEC based 16 subids. +//bit 95:94 for RID control : VPU read axi port2 based vpu read port2 ARSEC. For WID control : not used. +//bit 93:92 for RID control : VPU read axi port1 based vpu read port2 ARSEC. For WID control : VPU write axi port1 based on AWSEC. +//bit 91:90 for RID control : VPU read axi port0 based vpu read port2 ARSEC. For WID control : VPU write axi port0 based on AWSEC. +//bit 89:88 GE2D secruity control based ARSEC/AWSEC. +//bit 87:80. Not used. Reserved for future. +//bit 79. DSPB no-secure instruction access. +//bit 78. DSPB secure instruction access. +//bit 77. DSPB no-secure data access. +//bit 76. DSPB secure data access. +//bit 75. DSPA no-secure instruction access. +//bit 74. DSPA secure instruction access. +//bit 73. DSPA no-secure data access. +//bit 72. DSPA secure data access. +//bit 71~69. Not used. Reserved for future. +//bit 68. DEMUX access enable bit. for write also need to check security level is matched. +//bit 67:66. Wave. based instuction and data. +//bit 65:64. NNA. ( not used in Sc2). +//bit 63:56. HEVC backend based subid. +//bit 55:40. Device based on subids. +//bit 39:32. Audio based on subids +//bit 31:24 DMA based on threadids. for write, also need to check security level is matched. +//bit 22. USB access enable. +//bit 21. DMC test access enable. +//bit 20~12. HEVC frondend based subids. +//bit 11:8. HDCP based subids. +//bit 7. not used. +//bit 6. PCIE access enable. +//bit 5:4. GPU access enable based on GPU protection mode. +//bit 3. CPU no-secure instruction access. +//bit 2. CPU secure instruction access. +//bit 1. CPU no-secure data access. +//bit 0. CPU secure data access. +#define DMC_SEC_RANGE0_RID_CTRL0 ((0x0020 << 2) + 0xfe037000) + //default : 0 + //range_rd_sid_en[31:0]; +#define DMC_SEC_RANGE0_RID_CTRL1 ((0x0021 << 2) + 0xfe037000) + //default : 0 + //range_rd_sid_en[63:32]; +#define DMC_SEC_RANGE0_RID_CTRL2 ((0x0022 << 2) + 0xfe037000) + //default : 0 + //range_rd_sid_en[95:64]; +#define DMC_SEC_RANGE0_RID_CTRL3 ((0x0023 << 2) + 0xfe037000) + //default : 0 + //range_rd_sid_en[127:96]; +#define DMC_SEC_RANGE0_RID_CTRL4 ((0x0024 << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE1_RID_CTRL0 ((0x0026 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE1_RID_CTRL1 ((0x0027 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE1_RID_CTRL2 ((0x0028 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE1_RID_CTRL3 ((0x0029 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE1_RID_CTRL4 ((0x002a << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE2_RID_CTRL0 ((0x002c << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE2_RID_CTRL1 ((0x002d << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE2_RID_CTRL2 ((0x002e << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE2_RID_CTRL3 ((0x002f << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE2_RID_CTRL4 ((0x0030 << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE3_RID_CTRL0 ((0x0032 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE3_RID_CTRL1 ((0x0033 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE3_RID_CTRL2 ((0x0034 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE3_RID_CTRL3 ((0x0035 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE3_RID_CTRL4 ((0x0036 << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE4_RID_CTRL0 ((0x0038 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE4_RID_CTRL1 ((0x0039 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE4_RID_CTRL2 ((0x003a << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE4_RID_CTRL3 ((0x003b << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE4_RID_CTRL4 ((0x003c << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE5_RID_CTRL0 ((0x003e << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE5_RID_CTRL1 ((0x003f << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE5_RID_CTRL2 ((0x0040 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE5_RID_CTRL3 ((0x0041 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE5_RID_CTRL4 ((0x0042 << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE6_RID_CTRL0 ((0x0044 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_RID_CTRL1 ((0x0045 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_RID_CTRL2 ((0x0046 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_RID_CTRL3 ((0x0047 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_RID_CTRL4 ((0x0048 << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE7_RID_CTRL0 ((0x004a << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_RID_CTRL1 ((0x004b << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_RID_CTRL2 ((0x004c << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_RID_CTRL3 ((0x004d << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_RID_CTRL4 ((0x004e << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE8_RID_CTRL0 ((0x0050 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_RID_CTRL1 ((0x0051 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_RID_CTRL2 ((0x0052 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_RID_CTRL3 ((0x0053 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_RID_CTRL4 ((0x0054 << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE9_RID_CTRL0 ((0x0056 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_RID_CTRL1 ((0x0057 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_RID_CTRL2 ((0x0058 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_RID_CTRL3 ((0x0059 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_RID_CTRL4 ((0x005a << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE10_RID_CTRL0 ((0x005c << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_RID_CTRL1 ((0x005d << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_RID_CTRL2 ((0x005e << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_RID_CTRL3 ((0x005f << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_RID_CTRL4 ((0x0060 << 2) + 0xfe037000) + //default : 0 not used in SC2 +#define DMC_SEC_RANGE11_RID_CTRL0 ((0x0062 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_RID_CTRL1 ((0x0063 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_RID_CTRL2 ((0x0064 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_RID_CTRL3 ((0x0065 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_RID_CTRL4 ((0x0066 << 2) + 0xfe037000) + //not used in SC2 +#define DMC_SEC_RANGE12_RID_CTRL0 ((0x0068 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_RID_CTRL1 ((0x0069 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_RID_CTRL2 ((0x006a << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_RID_CTRL3 ((0x006b << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_RID_CTRL4 ((0x006c << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE13_RID_CTRL0 ((0x006e << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_RID_CTRL1 ((0x006f << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_RID_CTRL2 ((0x0070 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_RID_CTRL3 ((0x0071 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_RID_CTRL4 ((0x0072 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE14_RID_CTRL0 ((0x0074 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_RID_CTRL1 ((0x0075 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_RID_CTRL2 ((0x0076 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_RID_CTRL3 ((0x0077 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_RID_CTRL4 ((0x0078 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE15_RID_CTRL0 ((0x007a << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_RID_CTRL1 ((0x007b << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_RID_CTRL2 ((0x007c << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_RID_CTRL3 ((0x007d << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_RID_CTRL4 ((0x007e << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +//per range per sub ID access enable. +#define DMC_SEC_RANGE0_WID_CTRL0 ((0x0080 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE0_WID_CTRL1 ((0x0081 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE0_WID_CTRL2 ((0x0082 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE0_WID_CTRL3 ((0x0083 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE0_WID_CTRL4 ((0x0084 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE1_WID_CTRL0 ((0x0086 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE1_WID_CTRL1 ((0x0087 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE1_WID_CTRL2 ((0x0088 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE1_WID_CTRL3 ((0x0089 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE1_WID_CTRL4 ((0x008a << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE2_WID_CTRL0 ((0x008c << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE2_WID_CTRL1 ((0x008d << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE2_WID_CTRL2 ((0x008e << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE2_WID_CTRL3 ((0x008f << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE2_WID_CTRL4 ((0x0090 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE3_WID_CTRL0 ((0x0092 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE3_WID_CTRL1 ((0x0093 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE3_WID_CTRL2 ((0x0094 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE3_WID_CTRL3 ((0x0095 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE3_WID_CTRL4 ((0x0096 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE4_WID_CTRL0 ((0x0098 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE4_WID_CTRL1 ((0x0099 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE4_WID_CTRL2 ((0x009a << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE4_WID_CTRL3 ((0x009b << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE4_WID_CTRL4 ((0x009c << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE5_WID_CTRL0 ((0x009e << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE5_WID_CTRL1 ((0x009f << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE5_WID_CTRL2 ((0x00a0 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE5_WID_CTRL3 ((0x00a1 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE5_WID_CTRL4 ((0x00a2 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE6_WID_CTRL0 ((0x00a4 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_WID_CTRL1 ((0x00a5 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_WID_CTRL2 ((0x00a6 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_WID_CTRL3 ((0x00a7 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE6_WID_CTRL4 ((0x00a8 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE7_WID_CTRL0 ((0x00aa << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_WID_CTRL1 ((0x00ab << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_WID_CTRL2 ((0x00ac << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_WID_CTRL3 ((0x00ad << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE7_WID_CTRL4 ((0x00ae << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE8_WID_CTRL0 ((0x00b0 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_WID_CTRL1 ((0x00b1 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_WID_CTRL2 ((0x00b2 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_WID_CTRL3 ((0x00b3 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE8_WID_CTRL4 ((0x00b4 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE9_WID_CTRL0 ((0x00b6 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_WID_CTRL1 ((0x00b7 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_WID_CTRL2 ((0x00b8 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_WID_CTRL3 ((0x00b9 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE9_WID_CTRL4 ((0x00ba << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE10_WID_CTRL0 ((0x00bc << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_WID_CTRL1 ((0x00bd << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_WID_CTRL2 ((0x00be << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_WID_CTRL3 ((0x00bf << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE10_WID_CTRL4 ((0x00c0 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE11_WID_CTRL0 ((0x00c2 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_WID_CTRL1 ((0x00c3 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_WID_CTRL2 ((0x00c4 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_WID_CTRL3 ((0x00c5 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE11_WID_CTRL4 ((0x00c6 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE12_WID_CTRL0 ((0x00c8 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_WID_CTRL1 ((0x00c9 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_WID_CTRL2 ((0x00ca << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_WID_CTRL3 ((0x00cb << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE12_WID_CTRL4 ((0x00cc << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE13_WID_CTRL0 ((0x00ce << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_WID_CTRL1 ((0x00cf << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_WID_CTRL2 ((0x00d0 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_WID_CTRL3 ((0x00d1 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE13_WID_CTRL4 ((0x00d2 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE14_WID_CTRL0 ((0x00d4 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_WID_CTRL1 ((0x00d5 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_WID_CTRL2 ((0x00d6 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_WID_CTRL3 ((0x00d7 << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE14_WID_CTRL4 ((0x00d8 << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_SEC_RANGE15_WID_CTRL0 ((0x00da << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_WID_CTRL1 ((0x00db << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_WID_CTRL2 ((0x00dc << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_WID_CTRL3 ((0x00dd << 2) + 0xfe037000) + //default : 0 +#define DMC_SEC_RANGE15_WID_CTRL4 ((0x00de << 2) + 0xfe037000) + //not used in SC2 + //default : 0 +#define DMC_DES_CTRL ((0x00e1 << 2) + 0xfe037000) + //default : 32'h00000002 + //bit 31 : range15_des_en policy : 1 range15_des_en = range15_local_des_en && GLOBAL_DES_EN. 0 : range15_des_en = range15_local_des_en || GLOBAL_DES_EN. + //bit 30 : range14_des_en policy : 1 range14_des_en = range14_local_des_en && GLOBAL_DES_EN. 0 : range14_des_en = range14_local_des_en || GLOBAL_DES_EN. + //bit 29 : range13_des_en policy : 1 range13_des_en = range13_local_des_en && GLOBAL_DES_EN. 0 : range13_des_en = range13_local_des_en || GLOBAL_DES_EN. + //bit 28 : range12_des_en policy : 1 range12_des_en = range12_local_des_en && GLOBAL_DES_EN. 0 : range12_des_en = range12_local_des_en || GLOBAL_DES_EN. + //bit 27 : range11_des_en policy : 1 range11_des_en = range11_local_des_en && GLOBAL_DES_EN. 0 : range11_des_en = range11_local_des_en || GLOBAL_DES_EN. + //bit 26 : range10_des_en policy : 1 range11_des_en = range10_local_des_en && GLOBAL_DES_EN. 0 : range10_des_en = range10_local_des_en || GLOBAL_DES_EN. + //bit 25 : range9_des_en policy : 1 range9_des_en = range9_local_des_en && GLOBAL_DES_EN. 0 : range9_des_en = range9_local_des_en || GLOBAL_DES_EN. + //bit 24 : range8_des_en policy : 1 range8_des_en = range8_local_des_en && GLOBAL_DES_EN. 0 : range8_des_en = range8_local_des_en || GLOBAL_DES_EN. + //bit 23 : range7_des_en policy : 1 range7_des_en = range7_local_des_en && GLOBAL_DES_EN. 0 : range7_des_en = range7_local_des_en || GLOBAL_DES_EN. + //bit 22 : range6_des_en policy : 1 range6_des_en = range6_local_des_en && GLOBAL_DES_EN. 0 : range6_des_en = range6_local_des_en || GLOBAL_DES_EN. + //bit 21 : range5_des_en policy : 1 range5_des_en = range5_local_des_en && GLOBAL_DES_EN. 0 : range5_des_en = range5_local_des_en || GLOBAL_DES_EN. + //bit 20 : range4_des_en policy : 1 range4_des_en = range4_local_des_en && GLOBAL_DES_EN. 0 : range4_des_en = range4_local_des_en || GLOBAL_DES_EN. + //bit 19 : range3_des_en policy : 1 range3_des_en = range3_local_des_en && GLOBAL_DES_EN. 0 : range3_des_en = range3_local_des_en || GLOBAL_DES_EN. + //bit 18 : range2_des_en policy : 1 range2_des_en = range2_local_des_en && GLOBAL_DES_EN. 0 : range2_des_en = range2_local_des_en || GLOBAL_DES_EN. + //bit 17 : range1_des_en policy : 1 range1_des_en = range1_local_des_en && GLOBAL_DES_EN. 0 : range1_des_en = range1_local_des_en || GLOBAL_DES_EN. + //bit 16 : range0_des_en policy : 1 range0_des_en = range0_local_des_en && GLOBAL_DES_EN. 0 : range0_des_en = range0_local_des_en || GLOBAL_DES_EN. + //bit 1 | 0 | GLOBAL_DES_EN | 1: Global DES enable. 0 : global DES disable. default is 0. + //bit 0 | 0 | DES_lock | one time lock bit. after write 1 to this bit, DMC_DES_CTRL itself can't change but can be read, DMC_DES_PADDING DMC_DES_KEY*_REG* can't be write and read. +//DES KEY registers and DES_PADDING can only be reset by pad reset. But it can be changed by software after watch dog reset. +#define DMC_DES_KEY0_REG0 ((0x00e2 << 2) + 0xfe037000) + //default : 0 +#define DMC_DES_KEY0_REG1 ((0x00e3 << 2) + 0xfe037000) + //default : 0 +#define DMC_DES_KEY0_REG2 ((0x00e4 << 2) + 0xfe037000) + //default : 0 +#define DMC_DES_KEY0_REG3 ((0x00e5 << 2) + 0xfe037000) + //default : 0 +#define DMC_DES_KEY1_REG0 ((0x00e6 << 2) + 0xfe037000) + //default : 0 +#define DMC_DES_KEY1_REG1 ((0x00e7 << 2) + 0xfe037000) + //default : 0 +#define DMC_DES_KEY1_REG2 ((0x00e8 << 2) + 0xfe037000) + //default : 0 +#define DMC_DES_KEY1_REG3 ((0x00e9 << 2) + 0xfe037000) + //default : 0 +#define DMC_DES_PADDING ((0x00e0 << 2) + 0xfe037000) + //default : 0 + //bit 31:0 | 0 | des_pading | 32bits address padding used for DES dkey generation. +//trap function: all the enable the port ID read access or enable PORT ID and subID read access must be in the predefine range. otherwire the read access would be blocked. +// and an error will be generated. +#define DMC_TRAP0_RANGE ((0x00ea << 2) + 0xfe037000) + //default : 0 + // address trap0 range register. + //31:16. trap0 end address + //15:0 start0 address. +#define DMC_TRAP0_CTRL ((0x00eb << 2) + 0xfe037000) + //default : 0 + //bit 31 trap0 port ID 3 enable. + //bit 30 trap0 port ID 2 enable. + //bit 29 trap0 port ID 1 enable. + //bit 28 trap0 port ID 0 enable. + //bit 27 trap0 port ID 3 subid enable. + //bit 26 trap0 port ID 2 subid enable. + //bit 25 trap0 port ID 1 subid enable. + //bit 24 trap0 port ID 0 subid enable. + //bit 16:20. trap0 port ID 1 ID number. + //bit 14:11. trap0 port ID 1 subID ID number. + //bit 8:4. trap0 port ID 0 ID number. + //bit 3:0. trap0 port ID 0 subID ID number. +#define DMC_TRAP0_CTRL2 ((0x00ec << 2) + 0xfe037000) + //default : 0 + //bit 31:17. Not used. + //bit 16:20. trap0 port ID 3 ID number. + //bit 14:11. trap0 port ID 3 subID ID number. + //bit 8:4. trap0 port ID 2 ID number. + //bit 3:0. trap0 port ID 2 subID ID number. +#define DMC_TRAP1_RANGE ((0x00ed << 2) + 0xfe037000) + //default : 0 + //address trap range register. + //31:16. trap end address + //15:0 start address. +#define DMC_TRAP1_CTRL ((0x00ee << 2) + 0xfe037000) + //default : 0 + //bit 31 trap1 port ID 3 enable. + //bit 30 trap1 port ID 2 enable. + //bit 29 trap1 port ID 1 enable. + //bit 28 trap1 port ID 0 enable. + //bit 27 trap1 port ID 3 subid enable. + //bit 26 trap1 port ID 2 subid enable. + //bit 25 trap1 port ID 1 subid enable. + //bit 24 trap1 port ID 0 subid enable. + //bit 16:20. trap1 port ID 1 ID number. + //bit 14:11. trap1 port ID 1 subID ID number. + //bit 8:4. trap1 port ID 0 ID number. + //bit 3:0. trap1 port ID 0 subID ID number. +#define DMC_TRAP1_CTRL2 ((0x00ef << 2) + 0xfe037000) + //default : 0 + //bit 31:17. Not used. + //bit 16:20. trap1 port ID 1 ID number. + //bit 14:11. trap1 port ID 1 subID ID number. + //bit 8:4. trap1 port ID 0 ID number. + //bit 3:0. trap1 port ID 0 subID ID number. +//FROM SC2, the APB bus provided Master ID through PUSER. + //bit 3. 1: lock bit to lock 3:0. if this bit = 1, the 3:0 are locked and cannot modified anymore. + //bit 7: lock bit. if this bit =1, bit[7:4] can't be modified. + //bit 5: PHY CPU IMEM disable. 1: IMEM output always = 0. 0: normal working mode. + //bit 4: PHY CPU DMEM disable. 1: DMEM output always = 0. 0: normal working mode. + //bit 3:0. APB secure control bits for DDR PHY register domain. +//FROM SC2, the APB bus provided Master ID through PUSER signals. +//there's total 8 master IDs could access DMC non-secure registers. +//we assign 1 control bit for each APB Master and each DMC non-secure register domains +//and we added one lock bits to lock this setting can't be modified any more. +#define DDR_APB_SEC_CTRL0 ((0x00f0 << 2) + 0xfe037000) + // APB access control for dmc REQUEST control register access control register. + // default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL1 ((0x00f1 << 2) + 0xfe037000) + // APB access control for DMC DRAM timing parameter and DFI inteface registers. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL2 ((0x00f2 << 2) + 0xfe037000) + // APB access control for DMC PLL clock frequency control regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL3 ((0x00f3 << 2) + 0xfe037000) + // APB access control for DMC sticky control regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL4 ((0x00f4 << 2) + 0xfe037000) + // APB access control for DMC test control regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL5 ((0x00f5 << 2) + 0xfe037000) + // APB access control for DMC clk reset control regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL6 ((0x00f6 << 2) + 0xfe037000) + // APB access control for DMC protection regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL7 ((0x00f7 << 2) + 0xfe037000) + // APB access control for DMC normal regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL8 ((0x00f8 << 2) + 0xfe037000) + // APB access control for DDR PHY group 0 regsiters. + //default : 0x0ff + //bit 10 PHY IMEM control 1: force PHY IMEM output 0. 0: normal working mode. + //bit 9 PHY DMEM control 1: force PHY DMEM output 0. 0: normal working mode. + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +#define DDR_APB_SEC_CTRL9 ((0x00f9 << 2) + 0xfe037000) + // APB access control for DMC canvas regsiter. + //default : 0x0ff + //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore. + //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable. +//registers to check the security protection and watch point error information. +#define DMC_SEC_STATUS ((0x00fb << 2) + 0xfe037000) + //default : 0 + //bit 31~2. not used. + //bit 6 + //bit 5 + //bit 4 + //bit 3 1 : normal security register write violation.( APB bus WDATA not equre the register value when APB write). write 1 to clean this bit to 0. + //bit 2 sec_alert. 1 DMC secruity register alert function triggered. can't clean. only reset DMC can clear this bit. + //bit 1 write security violation. + //bit 0. read security violation. +#define DMC_VIO_ADDR0 ((0x00fc << 2) + 0xfe037000) + //default : 0 + //ddr0 write secure violation address. +#define DMC_VIO_ADDR1 ((0x00fd << 2) + 0xfe037000) + //default : 0 + //bit 31:24 . not used. always 0. + //24 ddr0 secure check violation. + //23 not used. + //22 not used. + //21 not used. + //20. not used. + //19 ddr0 write address overflow. write out of DDR size. + //18:16. ddr0 write violation AWPROT bits. + //15:0 ddr0_write violation ID. +#define DMC_VIO_ADDR2 ((0x00fe << 2) + 0xfe037000) + //default : 0 + //ddr0 read seure violation address +#define DMC_VIO_ADDR3 ((0x00ff << 2) + 0xfe037000) + //default : 0 + //24 ddr0 read secure check violation. + //23 not used. + //22 not used. + //21 ddr0 read trap1 violation + //20 ddr0 read trap0 violation + //19 ddr 0 read address overflow. write out of DDR size. + //18:16. ddr 0 read violation ARPROT bits. + //15:0 ddr 0 read violation ID. +#define DMC_DDR_CTRL ((0x0100 << 2) + 0xfe037000) + //default : 0 + //bit 27. 0 : cavnas use 64bytes boundary + // 1 : canvas use 32bytes boundary. + //bit 24:22 3'b000 : ddr3 mode. + //3'b001 : ddr4 mode. + //3'b010 : lpddr3 mode. + //3'b011 : lpddr4 mode. + //bit 21. rank1 enable bit. if 1, rank1 used the address map is as bit 5:3 defined. + //bit 20 DDR4 BG1 enable bit. + //bit 18: ddrphy_16b, DDR PHY DDR SDRAM data bits width. 1: 16bits. 0 : 32 bits. + //bit 16. ddr_16b, 1: only use 16bits data in a 32bits DDR PHY data interface. 0 : normal data interface. + //bit 7:4 : ddr1_size. DDR rank1 size control. + //4'b0000 : DDR rank 1 is 128Mbyte. + //4'b0001 : DDR rank 1 is 256Mbyte. + //4'b0010 : DDR rank 1 is 512Mbyte. + //4'b0011 : DDR rank 1 is 1Gbyte. + //4'b0100 : DDR rank 1 is 2Gbyte. + //4'b0101 : DDR rank 1 is 4Gbyte. + //4'b1000 : DDR rank 1 is 192Mbyte. + //4'b1001 : DDR rank 1 is 374Mbyte. + //4'b1010 : DDR rank 1 is 768Mbyte. + //4'b1011 : DDR rank 1 is 1.5Gbyte. + //4'b1100 : DDR rank 1 is 3Gbyte. + //others : reserved. + //bit 3:0 : ddr0_size. DDR rank0 size control. + //4'b0000 : DDR rank 0 is 128Mbyte. + //4'b0001 : DDR rank 0 is 256Mbyte. + //4'b0010 : DDR rank 0 is 512Mbyte. + //4'b0011 : DDR rank 0 is 1Gbyte. + //4'b0100 : DDR rank 0 is 2Gbyte. + //4'b0101 : DDR rank 0 is 4Gbyte. + //4'b1000 : DDR rank 1 is 192Mbyte. + //4'b1001 : DDR rank 1 is 374Mbyte. + //4'b1010 : DDR rank 1 is 768Mbyte. + //4'b1011 : DDR rank 1 is 1.5Gbyte. + //4'b1100 : DDR rank 1 is 3Gbyte. + //others : reserved. +//DDR3/4 LPDDR3/4 SDRAM address to 32bits linear address address map: +//DDR0_ADDRMAP is used to select RANK0 bank, row, col address selection. +//DDR1_ADDRMAP is used to select RANK1 bank, row, col address selection. +#define DDR0_ADDRMAP_0 ((0x0101 << 2) + 0xfe037000) + //default : 0 + //29:25 ca8. + //24:20 ca7. + //19:15 ca6. + //14:10 ca5. + //9:5 ca4. + //4:0 ca3. +#define DDR0_ADDRMAP_1 ((0x0102 << 2) + 0xfe037000) + //default : 0 + //29:25 ra2. + //24:20 ra1. + //19:15 ra0. + //14:10 ca11. + //9:5 ca10. + //4:0 ca9. +#define DDR0_ADDRMAP_2 ((0x0103 << 2) + 0xfe037000) + //default : 0 + //29:25 ra8. + //24:20 ra7. + //19:15 ra6. + //14:10 ra5. + //9:5 ra4. + //4:0 ra3. +#define DDR0_ADDRMAP_3 ((0x0104 << 2) + 0xfe037000) + //default : 0 + //29:25 ra14. + //24:20 ra13. + //19:15 ra12. + //14:10 ra11. + //9:5 ra10. + //4:0 ra9. +#define DDR0_ADDRMAP_4 ((0x0105 << 2) + 0xfe037000) + //default : 0 + //29:25 ra16 for DDR4 SDRAM + //24:20 bg1 for DDR4 SDRAM. + //19:15 ba2. or bg0 for DDR4. + //14:10 ba1. + //9:5 ba0. + //4:0 ra15. +#define DDR1_ADDRMAP_0 ((0x0106 << 2) + 0xfe037000) + //default : 0 + //29:25 ca8. + //24:20 ca7. + //19:15 ca6. + //14:10 ca5. + //9:5 ca4. + //4:0 ca3. +#define DDR1_ADDRMAP_1 ((0x0107 << 2) + 0xfe037000) + //default : 0 + //29:25 ra2. + //24:20 ra1. + //19:15 ra0. + //14:10 ca11. + //9:5 ca10. + //4:0 ca9. +#define DDR1_ADDRMAP_2 ((0x0108 << 2) + 0xfe037000) + //default : 0 + //29:25 ra8. + //24:20 ra7. + //19:15 ra6. + //14:10 ra5. + //9:5 ra4. + //4:0 ra3. +#define DDR1_ADDRMAP_3 ((0x0109 << 2) + 0xfe037000) + //default : 0 + //29:25 ra14. + //24:20 ra13. + //19:15 ra12. + //14:10 ra11. + //9:5 ra10. + //4:0 ra9. +#define DDR1_ADDRMAP_4 ((0x010a << 2) + 0xfe037000) + //default : 0 + //29:25 ra16 for DDR4 SDRAM + //24:20 bg1 for DDR4 SDRAM. + //19:15 ba2 or bg0 for DDR4 SDRAM.. + //14:10 ba1. + //9:5 ba0. + //4:0 ra15. +#define DDR_MEM_PD_CTRL ((0x010b << 2) + 0xfe037000) + //default : 0 + //bit 31:14 not used. + //2 bit control for each mem. 00 normal working. 11 power down. + //bit 13:12 wc_fifo + //bit 11:10 wd_mem + //bit 9:8 rd_mem + //bit 7:6 dfifo + //bit 5:4 cfifo + //bit 3:2 cav_ram + //bit 1:0 sticky ram +#define DMC_AXI2DDR0 ((0x0120 << 2) + 0xfe037000) + //default : 0 + //for AXI address first 256MB AXI ADDRESS[31:28] == 4'b0000. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR1 ((0x0121 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b0001. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR2 ((0x0122 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b0010. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR3 ((0x0123 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b0011. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR4 ((0x0124 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b0100. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR5 ((0x0125 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b0101. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR6 ((0x0126 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b0110. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR7 ((0x0127 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b0111. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR8 ((0x0128 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b1000. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDR9 ((0x0129 << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b1001. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRA ((0x012a << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b1010. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRB ((0x012b << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b1011. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRC ((0x012c << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b1100. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRD ((0x012d << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b1101. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRE ((0x012e << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b1110. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_AXI2DDRF ((0x012f << 2) + 0xfe037000) + //default : 0 + //for AXI_ADDRESS[31:28] == 4'b1111. + //bit 6 range_valid 1 : valid address 0 : not valid. + //bit 5 rank_sel, 0 : rank0. 1: rank1. + //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits. + //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28] +#define DMC_DDR_CTRL1 ((0x0130 << 2) + 0xfe037000) + //default : 0 + //bit 0. DMC_DDR_LOCK. 1: LOCK DMC_DDR_CTRL, DMC_DDR_CTRL1, DMC_AXI2DDRx, DDR0/1_ADDRMAP_x registers. those register can't modified any more. + // 0: all these regsiters can be read/write by secure APB access. +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh +// +// +// Reading file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh +// +//dmc pll and freqeucy domain control registers. +//`define DMC_FREQ_REG_BASE 32'hfe036c00 +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe036c00 +// ----------------------------------------------- +#define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xfe036c00) + //bit 31 : dpll_lock + //bit 29 : dpll_reset. + //bit 28 : dpll_en. + //bit 27:26 : dpll_clk_en + //bit 25 : dpll_inv_sel + //bit 20:19 : od1; if set ddr_freq_sel, it would replaced by ddr_pll_freq1_od[2:0] + //bit 18:16 : od; if set ddr_freq_sel, it would replaced by ddr_pll_freq1_od[5:4] + //bit 14:10 : dpll_ref_div_n + //bit 8:0 : dpll_int_num +#define AM_DDR_PLL_CNTL1 ((0x0001 << 2) + 0xfe036c00) + //bit 18:0 : ddr_dpll_frac +#define AM_DDR_PLL_CNTL2 ((0x0002 << 2) + 0xfe036c00) + //bit 22:20 : fref_sel + //bit 17:16 : os_ssc + //bit 15:12 : ssc_str_m + //bit 8 : ssc_en + //bit 7:4 : ssc_dep_sel + //bit 1:0 : dpll ss_mode. +#define AM_DDR_PLL_CNTL3 ((0x0003 << 2) + 0xfe036c00) + //bit 31 : afc bypass + //bit 30 : afc clk sel + //bit 29 : code new + //bit 28 : dco_m_en + //bit 27 : dco_sdm_en + //bit 26 : div2 + //bit 25 : div mode + //bit 24 : fast_lock mode + //bit 23 : fb_pre_div + //bit 22 : filter_mode + //bit 21 : fix_en + //bit 20 : freq_shift_en + //bit 19 : load + //bit 18 : load_en + //bit 17 : lock_f + //bit 16 : pulse_width_en + //bit 15 : sdmnc_en + //bit 14 : sdmnc_mode + //bit 13 : sdmnc_range + //bit 12 : tdc_en + //bit 11 : tdc_mode_sel + //bit 10 : wait_en +#define AM_DDR_PLL_CNTL4 ((0x0004 << 2) + 0xfe036c00) + //bit 1:0 : pfd_gain + //bit 7:4 : filter_pvt1 + //bit 11:8 : filter pvt2 + //bit 13:12 : acq_gain + //bit 18:16 : lambda0 + //bit 27:24 : rou + //bit 31:28 : alpha +#define AM_DDR_PLL_CNTL5 ((0x0005 << 2) + 0xfe036c00) + //bit 15:0 : reve + //bit 21:16 : lm_s + //bit 27:24 : lm_w + //bit 30:28 : adj_vco_ldo +#define AM_DDR_PLL_CNTL6 ((0x0006 << 2) + 0xfe036c00) + //bit 31:30 : afc_hold_t + //bit 29:28 : lkw_sel + //bit 27:26 : dco_sdm_clk_sel + //bit 25:24 : afc_in + //bit 23:22 : afc_nt + //bit 21:20 : vc_in + //bit 19:18 : lock_long + //bit 17:16 : freq_shift_v + //bit 15 : not used. + //bit 14:12 : data_sel + //bit 10:8 : sdmnc_ulms + //bit 6:0 : sdmnc_power +#define AM_DDR_PLL_STS ((0x0007 << 2) + 0xfe036c00) + //bit 31 : DDR_PLL_LOCK + //bit 30 : lock_a + //bit 29 : afc_done + //bit 22:16 : sdmnc_monitor + //bit 9:0 : out_rsv +#define DDR_CLK_CNTL ((0x0008 << 2) + 0xfe036c00) + //bit 31 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion. + // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again. + //bit 30. ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin. + //bit 29. not used. + //bit 28. clock generation logic soft reset. 0 = reset. + //bit 27. phy_4xclk phase inverter.. + //bit 26. pll_freq divide/2. 1: use pll div/2 clock as the n_clk. 0: use pll clock as n_clk. this setting is used for the synopsys DDR PHY PLL fast lock mode. + //bit 25. DDRPHY DfiClk/DfiCtlClk/DMC clock selection. 1: AM_PLL clk output /2. 0: directly output from AM_PLL . + //bit 24. enable AM_PLL CLK output /2 function. 1: enable. 0: disable. if try to use this clkoutput/2 function. + //bit 4. def_clk_sel 1: select reference clock as LPDDR4-PHY clock. 0: normal. + //bit 2. enable dmc_clk. + //bit 1. enable LPDDR4-PHY DfiClk. + //bit 0. enable LPDDR4-PHY DfiCtlClk. +#define DDR_PHY_CTRL ((0x0009 << 2) + 0xfe036c00) + // LPDDR4 power on reset need to special combination of PwrOkIn and phy_reset_n. + // please check the PHY PUB data book for detail. + //bit 4. DDR PHY PwrOkIn pin. + //bit 1. DDR PHY APB soft reset_n. + //bit 0. phy_reset_n. +#define AM_DDR_PLL_FREQ1_OD ((0x000c << 2) + 0xfe036c00) + //freqency set 1 PLL OD and OD1 setting. when change to freqency 1 will use this setting. +//frequency set 0 use original DDR_PLL_CNTL0 setting. + //bit 8 currunt FREQ selection. it can forced to change to select which freqency to select, or it can auto changed by FREQ change hardware. + //bit 5:4 OD1. + //bit 2:0. OD. +// +// Closing file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +//`define DMC_REG_BASE 32'hfe036000 +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe036000 +// ----------------------------------------------- +//DMC REQ domain register. please check DMC_SEC_APB_CTRLx register for access details. +#define DMC_REQ_CTRL ((0x0000 << 2) + 0xfe036000) + //bit 23. enable dmc request of ambus chan 7. Reserved for GE2D interface. Async interface. + //bit 22. enable dmc request of ambus chan 6. DOS HCODEC interface Sync interface. + //bit 21. enable dmc request of ambus chan 5. DOS VDEC interface Sync interface. + //bit 20. enable dmc request of ambus chan 4. VPU write interface 1 Sync interface. + //bit 19. enable dmc request of ambus chan 3. VPU write interface 0 Sync interface. + //bit 18. enable dmc request of ambus chan 2. VPU read interface 2. Sync interface. + //bit 17. enable dmc request of ambus chan 1. VPU read interface 1. Sync interface. + //bit 16. enable dmc request of ambus chan 0. VPU read interface 0. Sync interface. + //bit 9 enable dmc request of axibus chan 9. wave async interface. + //bit 8. enable dmc request of axibus chan 8 hevc_b async interface. + //bit 7. enable dmc request of axibus chan 7. DEVICE. Async interface. + //bit 6. enable dmc request of axibus chan 6. USB Async interface. + //bit 5. enable dmc request of axibus chan 5. reserved for dmc_test. + //bit 4. enable dmc request of axibus chan 4. hevc front Async interface. + //bit 3. enable dmc request of axibus chan 3. HDCP/HDMI Async interface. + //bit 2. enable dmc request of axibus chan 2. pcie async + //bit 1. enable dmc request of axibus chan 1. Mali . async interface. + //bit 0. enable dmc request of axibus chan 0. CPU/A53 async interface. +//DMC CLK and RESET domain register. please check DMC_SEC_APB_CTRLx register for access details. +#define DMC_SOFT_RST ((0x0001 << 2) + 0xfe036000) + //bit 31~24. reserved for future. + //bit 23:16 8 AMBUS input interface n_clk domain reset_n signal. 0 : reset. 1: normal working mode. + //bit 15:0. 16 AXI BUS input intefaces n_clk domain reset_n signal. 0: reset. 1: normal working mode. each bit for one interface. +#define DMC_SOFT_RST1 ((0x0002 << 2) + 0xfe036000) + //To reset the Async interface, you need to disable the interface both clock domain, then reset both n_clk and m_clk domain + //bit 31~24 not used. + //bit 23.16 8 am bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode. + //bit 15:0. 16 AXI bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode. +#define DMC_SOFT_RST2 ((0x0003 << 2) + 0xfe036000) + //bit 31~11. reserved for future. + //bit 10 DMC DFI cmd soft reset_n + //bit 9 DMC DFI MISC soft reset_n + //bit 8 DMC DFI data soft reset_n + //bit 7 DMC DFI dcu soft reset_n + //bit 6 DMC siu soft reset_n + //bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode. + //bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode. + //bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode. + //bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode. + //bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode. + //bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1: +#define DMC_RST_STS1 ((0x0004 << 2) + 0xfe036000) + //31~24. not used. + //23~0. Read only. the DMC_SOFT_RST1 signal in n_clk domain. the purpose of this register is when one of the 2 clocks is too slow or too fast, we can read this register to make sure another clock domain reset is done. +#define DMC_VERSION ((0x0005 << 2) + 0xfe036000) + //read only 32'h000a0006. for TM2_REVB +#define DMC_CLKG_CTRL0 ((0x0006 << 2) + 0xfe036000) + //bit 23:16. enable the 8 ambus interfaces both main and n_clk auto clock gating function. each 1 bit for one interface. + //bit 15:0. enable the 16 axi interfaces both main and n_clk auto clock gating function. each 1 bit for one interface. +#define DMC_CLKG_CTRL1 ((0x0007 << 2) + 0xfe036000) + //bit 23:16. force to disable the 8 ambus interfaces both main and n_clk. each 1 bit for one interface. + //bit 15:0. force to disable the 16 axi interfaces both main and n_clk. each 1 bit for one interface. +#define DMC_CLKG_CTRL2 ((0x0008 << 2) + 0xfe036000) + //bit 12 enalbe auto clock gating for awcmdfifo. + //bit 11 enalbe auto clock gating for arcmdfifo. + //bit 10 enable auto clock gating for dfi command generation + //bit 9 enable auto clock gating for dram cntroller + //bit 8 enable auto clock gating for dfi data path. + //bit 7. enalbe auto clock gating for write rsp generation. + //bit 6. enalbe auto clock gating for read rsp generation. + //bit 5. enalbe auto clock gating for ddr0 command filter. + //bit 4. enalbe auto clock gating for ddr0 write reorder buffer. + //bit 3. enalbe auto clock gating for ddr0 write data buffer. + //bit 2. enalbe auto clock gating for ddr0 read reorder buffer. + //bit 1. enalbe auto clock gating for read canvas. + //bit 0. enalbe auto clock gating for write canvas. +#define DMC_CLKG_CTRL3 ((0x0009 << 2) + 0xfe036000) + //bit 12 force to disable the clock of awcmdfifo. + //bit 11 force to disable the clock of arcmdfifo. + //bit 10 force to disable the clock of dfi command generation + //bit 9 force to disable the clock of dram cntroller + //bit 8 force to disable the clock of dfi data path. + //bit 7. force to disalbe the clock of write rsp generation. + //bit 6. force to disalbe the clock of read rsp generation. + //bit 5. force to disalbe the clock of command filter. + //bit 4. force to disalbe the clock of write reorder buffer. + //bit 3. force to disalbe the clock of write data buffer. + //bit 2. force to disalbe the clock of read reorder buffer. + //bit 1. force to disalbe the clock of read canvas. + //bit 0. force to disalbe the clock of write canvas. +// DMC CANVAS setting domain control regsiters. +#define DC_CAV_LUT_DATAL ((0x0012 << 2) + 0xfe036000) + //low 32 bits of canvas data which need to be configured to canvas memory. +#define DC_CAV_LUT_DATAH ((0x0013 << 2) + 0xfe036000) + //high 32bits of cavnas data which need to be configured to canvas memory. + //64bits CANVAS look up table + //bit 60:58 Endian control. + //3'b000: no endian change. + //3'b001: + //bit 57:56. Canvas block mode. 2 : 64x32, 1: 32x32; 0 : linear mode. + //bit 55: canvas Y direction wrap control. 1: wrap back in y. 0: not wrap back. + //bit 54: canvas X direction wrap control. 1: wrap back in X. 0: not wrap back. + //bit 53:41. canvas Hight. + //bit 40:29. canvas Width, unit: 8bytes. must in 32bytes boundary. that means last 2 bits must be 0. + //bit 28:0. cavnas start address. unit. 8 bytes. must be in 32bytes boundary. that means last 2bits must be 0. +#define DC_CAV_LUT_ADDR ((0x0014 << 2) + 0xfe036000) + //bit 9:8. write 9:8 2'b10. the canvas data will saved in canvas memory with addres 7:0. + //bit 7:0. 256 canvas Look up table address. +#define DC_CAV_LUT_RDATAL ((0x0015 << 2) + 0xfe036000) + // CBUS low 32bytes canvas read back data from LUT. +#define DC_CAV_LUT_RDATAH ((0x0016 << 2) + 0xfe036000) + // Cbus high 32bytes canvas read back data from LUT. +// there are total 256 canvas table, So we added a 256bits register to record the those canvas mode. +// when we configure the canvas table and if the canvas mode is 32x32 blkmode, we'll mark this related bit. +// we will use this bit to check the VPU canvas access. if it's in 32x32 blkmode, we need break the input in 32bytes boundary. +// You can also use below register to read/write those bit. +#define DC_CAV_BLK_CTRL0 ((0x0018 << 2) + 0xfe036000) + //canvas index 31:0 blkmode. 1 : 32x32. 0 : others. +#define DC_CAV_BLK_CTRL1 ((0x0019 << 2) + 0xfe036000) + //canvas index 63:32 blkmode. 1 : 32x32. 0 : others. +#define DC_CAV_BLK_CTRL2 ((0x001a << 2) + 0xfe036000) + //canvas index 95:64 blkmode. 1 : 32x32. 0 : others. +#define DC_CAV_BLK_CTRL3 ((0x001b << 2) + 0xfe036000) + //canvas index 127:96 blkmode. 1 : 32x32. 0 : others. +#define DC_CAV_BLK_CTRL4 ((0x001c << 2) + 0xfe036000) + //canvas index 159:128 blkmode. 1 : 32x32. 0 : others. +#define DC_CAV_BLK_CTRL5 ((0x001d << 2) + 0xfe036000) + //canvas index 191:160 blkmode. 1 : 32x32. 0 : others. +#define DC_CAV_BLK_CTRL6 ((0x001e << 2) + 0xfe036000) + //canvas index 223:192 blkmode. 1 : 32x32. 0 : others. +#define DC_CAV_BLK_CTRL7 ((0x001f << 2) + 0xfe036000) + //canvas index 255:224 blkmode. 1 : 32x32. 0 : others. +//dmc normal doman regsiters. +#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfe036000) + //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. + //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. + //bit 3. qos monitor 3 enable. + //bit 2. qos monitor 2 enable. + //bit 1. qos monitor 1 enable. + //bit 0. qos monitor 0 enable. +#define DMC_MON_CTRL1 ((0x0021 << 2) + 0xfe036000) + //bit 23:0. qos monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port. +#define DMC_MON_CTRL2 ((0x0022 << 2) + 0xfe036000) + //bit 15:0. port select for the selected channel. +#define DMC_MON_CTRL3 ((0x0023 << 2) + 0xfe036000) + //bit 23:0. qos monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port. +#define DMC_MON_CTRL4 ((0x0024 << 2) + 0xfe036000) + //bit 15:0. port select for the selected channel. +#define DMC_MON_CTRL5 ((0x0025 << 2) + 0xfe036000) + //bit 23:0. qos monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port. +#define DMC_MON_CTRL6 ((0x0026 << 2) + 0xfe036000) + //bit 15:0. port select for the selected channel. +#define DMC_MON_CTRL7 ((0x0027 << 2) + 0xfe036000) + //bit 23:0. qos monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port. +#define DMC_MON_CTRL8 ((0x0028 << 2) + 0xfe036000) + //bit 15:0. port select for the selected channel. +#define DMC_MON_ALL_REQ_CNT ((0x0029 << 2) + 0xfe036000) + // at the test period, the whole MMC request time. +#define DMC_MON_ALL_GRANT_CNT ((0x002a << 2) + 0xfe036000) + // at the test period, the whole MMC granted data cycles. 64bits unit. +#define DMC_MON_ONE_GRANT_CNT ((0x002b << 2) + 0xfe036000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_SEC_GRANT_CNT ((0x002c << 2) + 0xfe036000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_THD_GRANT_CNT ((0x002d << 2) + 0xfe036000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_FOR_GRANT_CNT ((0x002e << 2) + 0xfe036000) + // at the test period, the granted data cycles for the selected channel and ports. +#define DMC_MON_TIMER ((0x002f << 2) + 0xfe036000) + // timer for the monitor period. +#define DMC_IRQ_STS ((0x003b << 2) + 0xfe036000) + //bit 31:3 Not used. + //bit 2 : QOS Monitor interrupt flag. 1: means there's QOS monitor interrup. write 1 to clean this interrupt. + //bit 1 : WRITE protection interrupt. 1: means there's write protection violation. need to write DMC_PROT_IRQ_CTRL bit 1to clean this bit. + //bit 0 : read protection interrupt. 1: means there's read protection violation. need to write DMC_PROT_IRQ_CTRL bit 0 to clean this bit. +#define DMC_CHAN_STS ((0x003c << 2) + 0xfe036000) + //AXI0 is first CPU and Mali conbined channel from CCI-400 directly. The first 2Gbyte address will go through this channel. + //AXI10 is the second CPU, Mali channel combined with NNA from NIC-400. The upper 2Gbyte address will go through this channel. + // read only regsiter. + // the second mali and NNA channel IDLE. + // the second CPU channel IDLE. + // the first mali channel IDLE. + // the first CPU channel IDLE. + //bit 27 always 1 + //bit 26 ddr0 write data buffer idle. 1 : idle 0: busy. + //bit 25 always 1. + //bit 24 ddr0 wbuf idle. 1 : idle 0: busy. + //bit 23:16 ambus channel idle. 1 : idle 0: busy. + //bit 15:0. axibus channel idle. 1 : idle 0: busy. +#define DMC_2ARB_CTRL ((0x003d << 2) + 0xfe036000) + //32:24. Waiting limit to use the highest urgent level in the pipelines. + //22. 1: allow to increase 2 urgent levels if waiting time is doubled than inc_ugt_limit. + //21:12 inc_ugt_limit. if waiting time > inc_ugt_limit, increase the urgent level by one + //11:6. the final arbitration control from AXI bus(port channel 0~7). + //5:0. the final arbitration weight control for Ambus ( port channel 8~15). +#define DMC_CMD_FILTER_CTRL1 ((0x0040 << 2) + 0xfe036000) + //not used. +#define DMC_CMD_FILTER_CTRL2 ((0x0041 << 2) + 0xfe036000) + //31:24. keep the bank active if there's urgent level 3 read bank hit request. + //23:16. keep the bank active if there's urgent level 2 read bank hit request. + //15:8. keep the bank active if there's urgent level 1 read bank hit request. + //7:0. keep the bank active if there's urgent level 0 read bank hit request. +#define DMC_CMD_FILTER_CTRL3 ((0x0042 << 2) + 0xfe036000) + //bit 31. force wbuf empty. + //bit 30:26 wbuf high level number + //bit 25:21 wbuf mid level number + //bit 20:16 wbuf low level number + //bit 14:10 rbuf high level number + //bit 9:5 rbuf middle level number + //bit 4:0 rbuf low level number +#define DMC_CMD_FILTER_CTRL4 ((0x0043 << 2) + 0xfe036000) + //bit 29:25. tITW.long + //bit 24:20. tITW. short + //bit 19:12 tAP auto precharge the bank not used if idle that long time. + //bit 11:6 write to read accesses if there write hit request. + //bit 5:0 read to write accesses if there write hit request. +#define DMC_CMD_FILTER_CTRL5 ((0x0044 << 2) + 0xfe036000) + //bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer. + //bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long. + //bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request. + //bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request. +#define DMC_CMD_FILTER_CTRL6 ((0x0045 << 2) + 0xfe036000) + //bit 31:24 write urgent 3 request pending hold num. + //bit 23:16 write urgent 2 request pending hold num. + //bit 15:8. write urgent 1 request pending hold num. + //bit 7:0. write urgent 0 request pending hold num. +#define DMC_CMD_FILTER_CTRL7 ((0x0046 << 2) + 0xfe036000) + //bit 31:24. aw_req_pedning singal assertion after wbuf full. + //bit 23:16 aw_req_pending singal hold how long if wbuf not full. + //bit 15:8 write to read waiting cycles if there write hit request. + //bit 7:0 read to write waiting cycles if there write hit request. +#define DMC_CMD_FILTER_CTRL8 ((0x0047 << 2) + 0xfe036000) + //bit 31:8 reserved. + //bit 7:0 rank limit to change to another rank. +#define DMC_CMD_BUFFER_CTRL ((0x0048 << 2) + 0xfe036000) + //bit 31:26 total write buffer number. default 32. + //bit 25:20 total read buffer number. default 32. + //bit 19:8 reserved. + //bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long. +#define DMC_CMD_BUFFER_CTRL1 ((0x0049 << 2) + 0xfe036000) + //bit 29:24 read buffer number in non-urgent request. + //bit 23:16 read buffer bank miss watch dog threshold. + //bit 15:12 read buffer urgent level 3 counter inc weight. + //bit 11:8 read buffer urgent level 2 counter inc weight. + //bit 7:4 read buffer urgent level 1 counter inc weight. + //bit 3:0 read buffer urgent level 0 counter inc weight. +#define DMC_AM0_CHAN_CTRL ((0x0060 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AM0_HOLD_CTRL ((0x0061 << 2) + 0xfe036000) + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AM0_CHAN_CTRL1 ((0x0062 << 2) + 0xfe036000) + //bit 31: side band signal used as block other request. + //bit 30 : side band urgent increase enable. + //bit 29 : side band urgent decrease urgent enable. + //bit 23:16 : when bit 31 enabled, block the ambus related bits read request. + //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request. +#define DMC_AM0_CHAN_CTRL2 ((0x0063 << 2) + 0xfe036000) + //bit 31:24 not used. + //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request. + //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request. +#define DMC_AM1_CHAN_CTRL ((0x0064 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AM1_HOLD_CTRL ((0x0065 << 2) + 0xfe036000) + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AM1_CHAN_CTRL1 ((0x0066 << 2) + 0xfe036000) + //bit 31: side band signal used as block other request. + //bit 30 : side band urgent increase enable. + //bit 29 : side band urgent decrease urgent enable. + //bit 23:16 : when bit 31 enabled, block the ambus related bits read request. + //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request. +#define DMC_AM1_CHAN_CTRL2 ((0x0067 << 2) + 0xfe036000) + //bit 31:24 not used. + //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request. + //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request. +#define DMC_AM2_CHAN_CTRL ((0x0068 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AM2_HOLD_CTRL ((0x0069 << 2) + 0xfe036000) + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AM2_CHAN_CTRL1 ((0x006a << 2) + 0xfe036000) + //bit 31: side band signal used as block other request. + //bit 30 : side band urgent increase enable. + //bit 29 : side band urgent decrease urgent enable. + //bit 23:16 : when bit 31 enabled, block the ambus related bits read request. + //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request. +#define DMC_AM2_CHAN_CTRL2 ((0x006b << 2) + 0xfe036000) + //bit 31:24 not used. + //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request. + //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request. +#define DMC_AM3_CHAN_CTRL ((0x006c << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AM3_HOLD_CTRL ((0x006d << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AM3_CHAN_CTRL1 ((0x006e << 2) + 0xfe036000) + //bit 31: side band signal used as block other request. + //bit 30 : side band urgent increase enable. + //bit 29 : side band urgent decrease urgent enable. + //bit 23:16 : when bit 31 enabled, block the ambus related bits read request. + //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request. +#define DMC_AM3_CHAN_CTRL2 ((0x006f << 2) + 0xfe036000) + //bit 31:24 not used. + //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request. + //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request. +#define DMC_AM4_CHAN_CTRL ((0x0070 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AM4_HOLD_CTRL ((0x0071 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AM4_CHAN_CTRL1 ((0x0072 << 2) + 0xfe036000) + //bit 31: side band signal used as block other request. + //bit 30 : side band urgent increase enable. + //bit 29 : side band urgent decrease urgent enable. + //bit 23:16 : when bit 31 enabled, block the ambus related bits read request. + //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request. +#define DMC_AM4_CHAN_CTRL2 ((0x0073 << 2) + 0xfe036000) + //bit 31:24 not used. + //bit 23:16 : when bit 31 enabled, block the ambus related bits write request. + //bit 15:0 : when bit 31 enabled, block the axi bus related bits write request. +#define DMC_AM5_CHAN_CTRL ((0x0074 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AM5_HOLD_CTRL ((0x0075 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AM6_CHAN_CTRL ((0x0078 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AM6_HOLD_CTRL ((0x0079 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AM7_CHAN_CTRL ((0x007c << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AM7_HOLD_CTRL ((0x007d << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI0_CHAN_CTRL ((0x0080 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi0 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 arbiter weight +#define DMC_AXI0_HOLD_CTRL ((0x0081 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI0_CHAN_CTRL1 ((0x0082 << 2) + 0xfe036000) + //bit 31:28. FIQ status + //bit 27:24. IRQ status. + //bit 22 use ACTIVE input as clock gating control. + //bit 21:20. chan0 QOS mode. + //bit 19:16. AXI0 QOS high limit. + //bit 15:12 AXI0 QOS mit limit. + //bit 11 ARM FIQ controlled super urgent enable. + //bit 10 ARM FIQ controlled urgent enable. + //bit 9. ARM IRQ controlled super urgent enable. + //bit 8. ARM IRQ controlled urgent enable. + //bit 7. IRQ/FIQ controll enable. + //bit 6:5. not used. + //bit 4. enable AXI0 auto urgent enable. When there's no other request, treat the AXI0 as super urgent request. other wise, use the bit3:0 to set the urgent. + //bit 3:2 A9 urgent if there's VIU request. + //bit 1:0 A9 urgent if there's request other than VIU +#define DMC_AXI1_CHAN_CTRL ((0x0084 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI1_HOLD_CTRL ((0x0085 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI1_CHAN_CTRL1 ((0x0086 << 2) + 0xfe036000) + //bit 31:28. FIQ status + //bit 27:24. IRQ status. + //bit 21:20. Mali QOS mode. + //bit 19:16. mail QOS high limit. + //bit 15:12 mail QOS mit limit. + //bit 11 ARM FIQ controlled super urgent enable. + //bit 10 ARM FIQ controlled urgent enable. + //bit 9. ARM IRQ controlled super urgent enable. + //bit 8. ARM IRQ controlled urgent enable. + //bit 7. IRQ/FIQ controll enable. + //bit 6:0. not used. +#define DMC_AXI2_CHAN_CTRL ((0x0088 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI2_HOLD_CTRL ((0x0089 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI3_CHAN_CTRL ((0x008c << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI3_HOLD_CTRL ((0x008d << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI4_CHAN_CTRL ((0x0090 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI4_HOLD_CTRL ((0x0091 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI5_CHAN_CTRL ((0x0094 << 2) + 0xfe036000) + //not used. +#define DMC_AXI5_HOLD_CTRL ((0x0095 << 2) + 0xfe036000) + //not used. +#define DMC_AXI6_CHAN_CTRL ((0x0098 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI6_HOLD_CTRL ((0x0099 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI7_CHAN_CTRL ((0x009c << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI7_HOLD_CTRL ((0x009d << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI8_CHAN_CTRL ((0x00a0 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI8_HOLD_CTRL ((0x00a1 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI9_CHAN_CTRL ((0x00a4 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI9_HOLD_CTRL ((0x00a5 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI10_CHAN_CTRL ((0x00a8 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI10_HOLD_CTRL ((0x00a9 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI10_CHAN_CTRL1 ((0x00aa << 2) + 0xfe036000) + //bit 11 Mali/NNA channel FIQ controlled super urgent enable. + //bit 10 Mali/NNA channel FIQ controlled urgent enable. + //bit 9. Mali/NNA channel IRQ controlled super urgent enable. + //bit 8. Mali/NNA channel IRQ controlled urgent enable. + //bit 7. IRQ/FIQ controll enable. + //bit 6:0. not used. +#define DMC_AXI11_CHAN_CTRL ((0x00ac << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI11_HOLD_CTRL ((0x00ad << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI12_CHAN_CTRL ((0x00b0 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI12_HOLD_CTRL ((0x00b1 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +#define DMC_AXI13_CHAN_CTRL ((0x00b4 << 2) + 0xfe036000) + //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled. + //bit 30 enable to incr 3 urgent levels. + //bit 29:20. write request pending cycle number to inc urgent level if not granted. + //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register.. + //bit 18. force this channel all request to be super urgent request. + //bit 17. force this channel all request to be urgent request. + //bit 16. force this channel all request to be non urgent request. + //bit 15:14 axi1 default urgent level. + //bit 13:4. read request pending cycle number to inc urgent level if not granted. + //bit 3:0 canvas arbiter arbiter weight +#define DMC_AXI13_HOLD_CTRL ((0x00b5 << 2) + 0xfe036000) + //31:24 write hold num. max outstanding request number. + //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. + //15:8 read hold num. max outstanding request number. + //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request. +//DMC protection function domain regsiter. +#define DMC_PROT0_RANGE ((0x0030 << 2) + 0xfe036000) + //protection 0 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address. + //bit 31:16 : range end address. + //bit 15:0 : range start address +#define DMC_PROT0_CTRL ((0x0031 << 2) + 0xfe036000) + //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function. + //bit 15:0 each bit to enable one of the 15 channel input for the protection function. +#define DMC_PROT0_CTRL1 ((0x0032 << 2) + 0xfe036000) + //bit 26. protection 0 read access protection enable. + //bit 25. protection 0 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR. + //bit 24. protection range 0 write access protection enable. +#define DMC_PROT1_RANGE ((0x0033 << 2) + 0xfe036000) + //protection 1 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address. + //bit 31:16 : range end address. + //bit 15:0 : range start address +#define DMC_PROT1_CTRL ((0x0034 << 2) + 0xfe036000) + //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function. + //bit 15:0 each bit to enable one of the 15 channel input for the protection function. +#define DMC_PROT1_CTRL1 ((0x0035 << 2) + 0xfe036000) + //bit 26. protection range 1 read access protection enable bit. + //bit 25. protection 1 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR. + //bit 24. protection range 1 write access protection enable bit. +#define DMC_PROT_VIO_0 ((0x0036 << 2) + 0xfe036000) + //ddr0 write proection violation address. +#define DMC_PROT_VIO_1 ((0x0037 << 2) + 0xfe036000) + //bit 31:21 . not used. always 0. + //20 ddr0 protection 1 vilation. + //19 ddr0 protection 0 vilation. + //18:16. ddr0 write violation AWPROT bits. + //15:0 ddr0_write violation ID. +#define DMC_PROT_VIO_2 ((0x0038 << 2) + 0xfe036000) + //ddr0 read prot violation address +#define DMC_PROT_VIO_3 ((0x0039 << 2) + 0xfe036000) + //bit 31:21 . not used. always 0. + //20 ddr0 read protection 1 violation. + //19 ddr0 read protection 0 violation. + //18:16. ddr0 read violation ARPROT bits. + //15:0 ddr0 read violation ID. +#define DMC_PROT_IRQ_CTRL ((0x003a << 2) + 0xfe036000) + //bit 2 : protect function IRQ enable. + //bit 1 : write protection violation. write 1 to clean write protection vio registers. + //bit 0 : read protection violation. write 1 to clean read protection vio registers. +// DMC test domain control registers. +//`define DMC_TEST_REG_BASE 32'hfe037800 +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe037800 +// ----------------------------------------------- +#define DMC_TEST_STA ((0x0000 << 2) + 0xfe037800) + //test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. + // for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0. +#define DMC_TEST_EDA ((0x0001 << 2) + 0xfe037800) + //test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary. + // for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1. +#define DMC_TEST_CTRL ((0x0002 << 2) + 0xfe037800) + //bit 31. enable test. + //bit 30. when enable test, enable the write to DDR function. + //bit 29. when enable test, enable the read from DDR function. + //bit 28. when enable test, enable the sha calculation function must be same as read enable but without write function. + //bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer. + //bit 26. 0: save sha result to test_sha_message registers. 1 : don't save. + //bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address. + // 1: test module would pick the random address from test start address and test end address. + //bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers. + // for write if the write command number == the DMC_TEST_NUM, the write is done. + // for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times. + // 1 : finshed at end address. + //bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}). + // 0 : the WDATA is the data in write register. + //bit 23. 1 compare the sha result with the test sha message registers. 0 : dont compare the result. + //bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times. + //bit 19. limit write. 0: no outstanding write request limitation. + // 1: limit the outstanding write commands to the number of bits [15:8] + //bit 18. limit read. 0. no outstanding read request limitation. + // 1. limit the read outstanding request to the number of bits[7:0]. + //bit 17:16. sha mode for sha function enabled. 00 : not used. 01 : sha1. 2: sha2-256. 3: sha2_224. not used in GXL fixed to be Sha 2. + //bit 15:8. write outstanding commands limit. + //bit 7:0. read outstanding commands limit. +#define DMC_TEST_NUM ((0x0003 << 2) + 0xfe037800) + // how many test command for the test if the DMC_TEST_CTRL bit 24 is 0. +#define DMC_TEST_WDG ((0x0004 << 2) + 0xfe037800) + //31:16. write response watch dog. + //15:0. read response watch dog. +#define DMC_TEST_COMP_MASK ((0x0005 << 2) + 0xfe037800) + //32bits for DMC TEST COMPARE bit enable. + //1 : to MASK this bit. 0: compare this bit. +#define DMC_TEST_WSTRB0 ((0x0006 << 2) + 0xfe037800) + //MPC WR FIFO command DM bit write data + //bit 31:16 the second cycle. + //bit 15:0 the first cycle. +#define DMC_TEST_WSTRB1 ((0x0007 << 2) + 0xfe037800) + //MPC WR FIFO command DM bit write data + //bit 31:16. the Forth cycle. + //bit 15:0. the third cycle. +#define DMC_TEST_WD0 ((0x0010 << 2) + 0xfe037800) + // write data 0 for write command. also for read back data comparision. +#define DMC_TEST_WD1 ((0x0011 << 2) + 0xfe037800) + // write data 1 for write command. also for read back data comparision. +#define DMC_TEST_WD2 ((0x0012 << 2) + 0xfe037800) + // write data 2 for write command. also for read back data comparision. +#define DMC_TEST_WD3 ((0x0013 << 2) + 0xfe037800) + // write data 3 for write command. also for read back data comparision. +#define DMC_TEST_WD4 ((0x0014 << 2) + 0xfe037800) + // write data 4 for write command. also for read back data comparision. +#define DMC_TEST_WD5 ((0x0015 << 2) + 0xfe037800) + // write data 5 for write command. also for read back data comparision. +#define DMC_TEST_WD6 ((0x0016 << 2) + 0xfe037800) + // write data 6 for write command. also for read back data comparision. +#define DMC_TEST_WD7 ((0x0017 << 2) + 0xfe037800) + // write data 7 for write command. also for read back data comparision. +#define DMC_TEST_WD8 ((0x0018 << 2) + 0xfe037800) + // write data 8 for write command. also for read back data comparision. +#define DMC_TEST_WD9 ((0x0019 << 2) + 0xfe037800) + // write data 9 for write command. also for read back data comparision. +#define DMC_TEST_WD10 ((0x001a << 2) + 0xfe037800) + // write data 10 for write command. also for read back data comparision. +#define DMC_TEST_WD11 ((0x001b << 2) + 0xfe037800) + // write data 11 for write command. also for read back data comparision. +#define DMC_TEST_WD12 ((0x001c << 2) + 0xfe037800) + // write data 12 for write command. also for read back data comparision. +#define DMC_TEST_WD13 ((0x001d << 2) + 0xfe037800) + // write data 13 for write command. also for read back data comparision. +#define DMC_TEST_WD14 ((0x001e << 2) + 0xfe037800) + // write data 14 for write command. also for read back data comparision. +#define DMC_TEST_WD15 ((0x001f << 2) + 0xfe037800) + // write data 15 for write command. also for read back data comparision. +#define DMC_TEST_RD0 ((0x0020 << 2) + 0xfe037800) + // the read back data 0. if error happens, it would capture the first error data. +#define DMC_TEST_RD1 ((0x0021 << 2) + 0xfe037800) + // the read back data 1. if error happens, it would capture the first error data. +#define DMC_TEST_RD2 ((0x0022 << 2) + 0xfe037800) + // the read back data 2. if error happens, it would capture the first error data. +#define DMC_TEST_RD3 ((0x0023 << 2) + 0xfe037800) + // the read back data 3. if error happens, it would capture the first error data. +#define DMC_TEST_RD4 ((0x0024 << 2) + 0xfe037800) + // the read back data 4. if error happens, it would capture the first error data. +#define DMC_TEST_RD5 ((0x0025 << 2) + 0xfe037800) + // the read back data 5. if error happens, it would capture the first error data. +#define DMC_TEST_RD6 ((0x0026 << 2) + 0xfe037800) + // the read back data 6. if error happens, it would capture the first error data. +#define DMC_TEST_RD7 ((0x0027 << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD8 ((0x0028 << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD9 ((0x0029 << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD10 ((0x002a << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD11 ((0x002b << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD12 ((0x002c << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD13 ((0x002d << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD14 ((0x002e << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_RD15 ((0x002f << 2) + 0xfe037800) + // the read back data 7. if error happens, it would capture the first error data. +#define DMC_TEST_ERR_ADDR ((0x0040 << 2) + 0xfe037800) + //read only. it capature the first error address. +#define DMC_TEST_ERR_CNT ((0x0041 << 2) + 0xfe037800) + //read only. how many data error happens in the whole test period. +#define DMC_TEST_STS ((0x0042 << 2) + 0xfe037800) + //read only. + //bit 31, test done bit. write 1 to clean. + //bit 30, indicate address err + //bit 29~7. not used. + //bit 6. read data resp error(caused by security or rd latency). + //bit 5. test MRR/MPR rd latency error. write 1 clear + //bit 4, sha done. write 1 to clean. + //bit 3, write done. write 1 to clean. + //bit 2, read done. write 1 to clean + //bit 1, write watchdog triggered. write 1 to clean + //bit 0, read watchdog triggered. write 1 to clean. +#define DMC_TEST_WRCMD_ADDR ((0x0043 << 2) + 0xfe037800) + //read only. the current write cmd address. +#define DMC_TEST_RDCMD_ADDR ((0x0044 << 2) + 0xfe037800) + //read only. the current read command address. +#define DMC_TEST_RDRSP_ADDR ((0x0045 << 2) + 0xfe037800) + //read only. the failed read response address(for error data ) +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +//DMC DDR dram timing and dfi timing domain control registers. +//`define DMC_DRAM_REG_BASE 32'hfe036400 +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe036400 +// ----------------------------------------------- +//there's 2 set of timing DDR timing parameter for 2 set of DDR freqency parameter. +//when change frequency, the hardware would automatically select one of these two set of timing parameter +//DMC_DRAM_* is for Frequency set 0. +//DMC_NFQ_* is for Freqency set 1. +#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xfe036400) + //bit 4:0. tMRD. //MR command cycles, in DDR3/4. in LPDDR4, it should be value of tMRW +#define DMC_DRAM_TRFC ((0x0001 << 2) + 0xfe036400) + //bit 9:0 tRFC +#define DMC_DRAM_TRP ((0x0002 << 2) + 0xfe036400) + //bit 21:16. tRP for precharge all banks. + //bit 5:0. tRP for precharge one bank. +#define DMC_DRAM_TRTW ((0x0003 << 2) + 0xfe036400) + //bit 5:0 tRTW + //In LPDDR4 . the total read command -> write command = RL +DQSCK_MAX + BL/2 - tODT_on + tWPRE +RD(tRPST) + tODT_on. + // tRTW = TDQSCK_MAX + tWPRE + tRD(tRPST) tODT_on + (delay margin) + //In DDR4 mode. +#define DMC_DRAM_TCL ((0x0004 << 2) + 0xfe036400) + //bit 5:0 tCL/tRL. read latency. +#define DMC_DRAM_TCWL ((0x0005 << 2) + 0xfe036400) + //bit 5:0. CWL: write latency. +#define DMC_DRAM_TRAS ((0x0006 << 2) + 0xfe036400) + //bit 7:0. tRAS. minimum active to precharge time for same bank. +#define DMC_DRAM_TRC ((0x0007 << 2) + 0xfe036400) + //bit 7:0. tRC. minimum active to active time for same bank. +#define DMC_DRAM_TRCD ((0x0008 << 2) + 0xfe036400) + //bit 7:0 tRCD active to read/write timing for same bank. +#define DMC_DRAM_TRRD ((0x0009 << 2) + 0xfe036400) + //bit 21:16. tRRD_l active bank A to active B in same band group for DDR4. + //bit 5:0. tRRD/tRRD_s active bank A to active bank b time. + //tRRD_s: active bank A to active bank b in different bank grousp for DDR4. +#define DMC_DRAM_TFAW ((0x000a << 2) + 0xfe036400) + //bit 8:0 tFAW. four active command windows +#define DMC_DRAM_TRTP ((0x000b << 2) + 0xfe036400) + //bit 5:0 tRTP. +#define DMC_DRAM_TWR ((0x000c << 2) + 0xfe036400) + //bit 5:0 tWR. +#define DMC_DRAM_TWTR ((0x000d << 2) + 0xfe036400) + //bit 5:0 tWTR. +#define DMC_DRAM_TCCD ((0x000e << 2) + 0xfe036400) + //bit 19:16. tCCD/tCCD_l. + //bit 3:0 tCCD/tCCD_s read to read command time or write to write command time. +#define DMC_DRAM_TEXSR ((0x000f << 2) + 0xfe036400) + //bit 12:0. tEXSR. EXIT SELF-REFRESH to read/write command. +#define DMC_DRAM_TXS ((0x0010 << 2) + 0xfe036400) + //bit 9:0 tXS. EXIT SELF_REFRESH to other command time +#define DMC_DRAM_TXP ((0x0011 << 2) + 0xfe036400) + //bit 3:0. tXP. EXIT power down to other command time +#define DMC_DRAM_TXPDLL ((0x0012 << 2) + 0xfe036400) + //bit 12:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL). +#define DMC_DRAM_TZQCS ((0x0013 << 2) + 0xfe036400) + //bit 11:0. ZQCS command to other command time. +#define DMC_DRAM_TCKSRE ((0x0014 << 2) + 0xfe036400) + //bit 4:0. enter self refresh to disable clock time. +#define DMC_DRAM_TCKSRX ((0x0015 << 2) + 0xfe036400) + //bit 4:0. enable clock to exit self refresh time. +#define DMC_DRAM_TCKE ((0x0016 << 2) + 0xfe036400) + //bit 4:0. CKE high or low minimum time. +#define DMC_DRAM_TMOD ((0x0017 << 2) + 0xfe036400) + //bit 4:0 tMOD. MRR/MRW to other command time. in LPDDR4, still use this register but it called tMRD. +#define DMC_DRAM_TDQS ((0x0018 << 2) + 0xfe036400) + //bit 31:28 reserved + //bit 27:24 tDQS. the delay for write after read in different rank. + //bit 23:20 reserved + //bit 19:16 tDQS. the delay for read after write in different rank. + //bit 15:12 reserved + //bit 11:8 tDQS. the delay for write after write in different rank. + //bit 7:4 reserved + //bit 3:0 tDQS. the delay for read after read in different rank. +#define DMC_DRAM_TRSTL ((0x0019 << 2) + 0xfe036400) + //not used. +#define DMC_DRAM_TZQLAT ((0x001a << 2) + 0xfe036400) + //bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode. +#define DMC_DRAM_TMRR ((0x001b << 2) + 0xfe036400) + //bit 7:0 tMRR not used in DMC. +#define DMC_DRAM_TCKESR ((0x001c << 2) + 0xfe036400) + //bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode. +#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfe036400) + //not support. +#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfe036400) + //bit 3:0. DFI_t_ctrldealy +#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfe036400) + //bit 5:0. dfi_t_phy_wrdata. +#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfe036400) + //bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2. +#define DMC_DRAM_DFITRDDATAEN ((0x0021 << 2) + 0xfe036400) + //bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1. +#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfe036400) + //bit 5:0. dfi_t_rdlat. +#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfe036400) + //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ. +#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfe036400) + //bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response. +#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfe036400) + //not used. +#define DMC_DRAM_DFITCTRLUPDI ((0x0027 << 2) + 0xfe036400) + //not used. +#define DMC_DRAM_DFITDRAMCLK ((0x0028 << 2) + 0xfe036400) +//bit 17 dram clk1 enable. +//bit 16 dram clk0 enable. +//bit 15:8 DRAM CLK disable waiting time +//bit 7:0 DRAM CLK enable enable timer +#define DMC_DRAM_DFITLPRESP ((0x002a << 2) + 0xfe036400) + //bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req. +#define DMC_DRAM_TCKECK ((0x002c << 2) + 0xfe036400) + //bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay +#define DMC_DRAM_TREFI ((0x002d << 2) + 0xfe036400) + //write this register will update the auto refresh related register to the auto refresh control logic. + //bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period. + //bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period. + //bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns. + //bit 7:0. t100ns period. unit is dmc clock cycles +#define DMC_DRAM_TSR ((0x002e << 2) + 0xfe036400) + //bit 5:0 tSR. self resfresh enter to exit time. +#define DMC_DRAM_TCCDMW ((0x002f << 2) + 0xfe036400) + //bit 5:0. 4*tCCD in LPDDR4 mask write. +#define DMC_DRAM_TESCKE ((0x0030 << 2) + 0xfe036400) + //bit 5:0 tESCKE. enter self refresh to power time for LPDDR4. +#define DMC_DRAM_TREFI_DDR3 ((0x0031 << 2) + 0xfe036400) + //7:0. DDR3 SDRAM tREFI single auto refresh time . the unit is t100ns. + //use this to check in 8*tREFI time, the DMC should not sent more than 16 auto REFRESH command. +#define DMC_DRAM_TZQCAL ((0x0032 << 2) + 0xfe036400) + //11:0. ZQCAL for LPDDR4. ZQINIT/ZQoper for DDR3/4 ZQCL command. +#define DMC_DRAM_T10US ((0x0033 << 2) + 0xfe036400) + //10us clock cycle number used for LP2 mode. +#define DMC_DRAM_TMRRI ((0x0034 << 2) + 0xfe036400) +//bit 7:0 tMRRI for MRR +#define DMC_DRAM_TXS_FAST ((0x0035 << 2) + 0xfe036400) + //bit 9:0 DDR4 mode XS_FAST exit self_refrest to zqcl/zqcs/mrs command. +#define DMC_DRAM_DFIODTCFG ((0x0036 << 2) + 0xfe036400) + //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. + //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. + //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0. + //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1. + //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0. + //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity. + //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0. + //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. + //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. + //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. +#define DMC_DRAM_DFIODTCFG1 ((0x0037 << 2) + 0xfe036400) + //bit 27:24 ODT length for BL8 read transfer. + //bit 19:16. ODT length for BL8 write transfer. + //bit 12:8. ODT latency for reads. suppose to be 0. + //bit 4:0. ODT latency for writes. suppose to be 0. +#define DMC_DRAM_TWODTON ((0x0038 << 2) + 0xfe036400) + //bit 5:0 DRAM write access ODT on time. + // in DDR3/4 should be same as WL. + // in LPDDR4 = tODTLon + tODTon.min +//timing paramter for frequency set 1. +#define DMC_NFQ_TMRD ((0x0040 << 2) + 0xfe036400) +#define DMC_NFQ_TRFC ((0x0041 << 2) + 0xfe036400) +#define DMC_NFQ_TRP ((0x0042 << 2) + 0xfe036400) +#define DMC_NFQ_TRTW ((0x0043 << 2) + 0xfe036400) +#define DMC_NFQ_TCL ((0x0044 << 2) + 0xfe036400) +#define DMC_NFQ_TCWL ((0x0045 << 2) + 0xfe036400) +#define DMC_NFQ_TRAS ((0x0046 << 2) + 0xfe036400) +#define DMC_NFQ_TRC ((0x0047 << 2) + 0xfe036400) +#define DMC_NFQ_TRCD ((0x0048 << 2) + 0xfe036400) +#define DMC_NFQ_TRRD ((0x0049 << 2) + 0xfe036400) +#define DMC_NFQ_TFAW ((0x004a << 2) + 0xfe036400) +#define DMC_NFQ_TRTP ((0x004b << 2) + 0xfe036400) +#define DMC_NFQ_TWR ((0x004c << 2) + 0xfe036400) +#define DMC_NFQ_TWTR ((0x004d << 2) + 0xfe036400) +#define DMC_NFQ_TCCD ((0x004e << 2) + 0xfe036400) +#define DMC_NFQ_TEXSR ((0x004f << 2) + 0xfe036400) +#define DMC_NFQ_TXS ((0x0050 << 2) + 0xfe036400) +#define DMC_NFQ_TXP ((0x0051 << 2) + 0xfe036400) +#define DMC_NFQ_TXPDLL ((0x0052 << 2) + 0xfe036400) +#define DMC_NFQ_TZQCS ((0x0053 << 2) + 0xfe036400) +#define DMC_NFQ_TCKSRE ((0x0054 << 2) + 0xfe036400) +#define DMC_NFQ_TCKSRX ((0x0055 << 2) + 0xfe036400) +#define DMC_NFQ_TCKE ((0x0056 << 2) + 0xfe036400) +#define DMC_NFQ_TMOD ((0x0057 << 2) + 0xfe036400) +#define DMC_NFQ_TDQS ((0x0058 << 2) + 0xfe036400) +#define DMC_NFQ_TRSTL ((0x0059 << 2) + 0xfe036400) +#define DMC_NFQ_TZQLAT ((0x005a << 2) + 0xfe036400) +#define DMC_NFQ_TMRR ((0x005b << 2) + 0xfe036400) +#define DMC_NFQ_TCKESR ((0x005c << 2) + 0xfe036400) +#define DMC_NFQ_TDPD ((0x005d << 2) + 0xfe036400) +#define DMC_NFQ_DFITCTRLDELAY ((0x005e << 2) + 0xfe036400) +#define DMC_NFQ_DFITPHYWRDATA ((0x005f << 2) + 0xfe036400) +#define DMC_NFQ_DFITPHYWRLAT ((0x0060 << 2) + 0xfe036400) +#define DMC_NFQ_DFITRDDATAEN ((0x0061 << 2) + 0xfe036400) +#define DMC_NFQ_DFITPHYRDLAT ((0x0062 << 2) + 0xfe036400) +#define DMC_NFQ_DFITCTRLUPDMIN ((0x0063 << 2) + 0xfe036400) +#define DMC_NFQ_DFITCTRLUPDMAX ((0x0064 << 2) + 0xfe036400) +#define DMC_NFQ_DFITREFMSKI ((0x0066 << 2) + 0xfe036400) +#define DMC_NFQ_DFITCTRLUPDI ((0x0067 << 2) + 0xfe036400) +#define DMC_NFQ_DFITDRAMCLK ((0x0068 << 2) + 0xfe036400) +#define DMC_NFQ_DFITLPRESP ((0x006a << 2) + 0xfe036400) +#define DMC_NFQ_TCKECK ((0x006c << 2) + 0xfe036400) +#define DMC_NFQ_TREFI ((0x006d << 2) + 0xfe036400) +#define DMC_NFQ_TSR ((0x006e << 2) + 0xfe036400) +#define DMC_NFQ_TCCDMW ((0x006f << 2) + 0xfe036400) +#define DMC_NFQ_TESCKE ((0x0070 << 2) + 0xfe036400) +#define DMC_NFQ_TREFI_DDR3 ((0x0071 << 2) + 0xfe036400) +#define DMC_NFQ_TZQCAL ((0x0072 << 2) + 0xfe036400) +#define DMC_NFQ_T10US ((0x0073 << 2) + 0xfe036400) +#define DMC_NFQ_TMRRI ((0x0074 << 2) + 0xfe036400) +#define DMC_NFQ_TXS_FAST ((0x0075 << 2) + 0xfe036400) +#define DMC_NFQ_DFIODTCFG ((0x0076 << 2) + 0xfe036400) +#define DMC_NFQ_DFIODTCFG1 ((0x0077 << 2) + 0xfe036400) +#define DMC_NFQ_TWODTON ((0x0078 << 2) + 0xfe036400) +//end of second frequency timing parameter +#define DMC_DRAM_DFITPHYUPDTYPE0 ((0x0080 << 2) + 0xfe036400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 0. +#define DMC_DRAM_DFITPHYUPDTYPE1 ((0x0081 << 2) + 0xfe036400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 1. +#define DMC_DRAM_DFITPHYUPDTYPE2 ((0x0082 << 2) + 0xfe036400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 2. +#define DMC_DRAM_DFITPHYUPDTYPE3 ((0x0083 << 2) + 0xfe036400) + //dfi_phyupd_ack hold time for dfi_phyupd_req type = 3. +#define DMC_DRAM_MCFG ((0x0086 << 2) + 0xfe036400) + //bit 17. in DDR3/4 mode, send ZQCL command after exit register triggered self refresh. + //bit 16. send refresh command after finish frequency change. 1 : enable. 0 : disable. + //bit 15. send refresh command after finish LPDDR4 retraining. 1 : enable. 0 : disable. + //bit 14. 1: cke init low. 0 : cke init high. + //bit 13 1: dbi write enable only for LPDDR4. + //bit 12. 1: dbi read inversion. 0: dbi read high inversion. + //bit 11. 1: dbi read enable. 0: dbi not enabled. + //bit 10 1: enable staggered chip select for 2 ranks DRAM. + //bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state. + //bit 8 send auto refr cmd before enter register triggered self refresh + //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode. + //bit 6 disable dram clock after enter register triggered self refresh. + //bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode. + //bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4. + //bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh. + //bit 2 send ZQCS command after exit register triggered self refresh. + //bit 1 enable PHY triggered DFI_PHYUPD_REQ. + //bit 0 2T mode. always 1 in DDR3/4 mode. +#define DMC_DRAM_DFI_CTRL ((0x0089 << 2) + 0xfe036400) + //bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable. + //bit 15 siu_dfi1_lp_en + //bit 14 siu_dfi_lp_ack_and + //bit 13 siu_dfi_lp_ack_or + //bit 12 siu_dfi1_init_start_en + //bit 11 siu_dfi_init_com_and + //bit 10 siu_dfi_init_com_or + //bit 9 siu_dfi1_freq_en + //bit 8 siu_dfi1_dram_clk_dis_en + //bit 7 siu_dfi_phyupd_type_sel + //bit 6 siu_dfi1_phyupd_ack_en + //bit 5 siu_dfi_phyupd_req_and + //bit 4 siu_dfi_phyupd_req_or + //bit 3 siu_dfi_ctrlupd_ack_and + //bit 2 siu_dfi_ctrlupd_ack_or + //bit 1 siu_dfi1_ctrlupd_req_en + //bit 0 siu_dfi1_cmd_en +#define DMC_DRAM_DFIINITCFG ((0x008a << 2) + 0xfe036400) + //bit 31. dfi_init_complete status. read only. + //bit 15:14. Frequency set 1 dfi_freq_ratio value. + //bit 12:8 Frequency set 1 dfi_freq value. + //bit 7:6 Frequency set 0 dfi_freq_ratio value. + //bit 5:1 Frequency set 0 dfi_freq value. + //bit 0. dfi_init_start value can be use manually config dfi_init_start signal. +#define DMC_DRAM_ZQ_CTRL ((0x008b << 2) + 0xfe036400) + // only 1 bit can be enabled at same time. + //bit 2 send ZQCS command to RANK0 then send comand to RANK1. + //bit 1. send ZQCS command to both RANK0 and RANK1 together. + //bit 0. send ZQCS command to only rank0. +#define DMC_DRAM_APD_CTRL ((0x008c << 2) + 0xfe036400) + //bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode + //bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode. + //bit 11 enable DFI_LP_REQ when enter Auto power down mode. + //bit 10 disable DFI_clk_disable when enter auto power down mode. + //bit 9:0 0 disable auto power down mode. + //non zero value to enable auto power down when DMC is in idle state for this number of clock cycles. +#define DMC_DRAM_ASR_CTRL ((0x008d << 2) + 0xfe036400) + //bit 30. in DDR3/4 mode, send ZQCL command after exit from auto self refresh mode. + //bit 29. enable PHY clock in LP2 mode. 1: enable. 0 : disable. + //bit 28. enable dmc wait 10us after LP2 mode exit if it's long time the PHY in LP2 mode.. + //bit [27:24] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode. + //bit 23 : send REFRESH command after exit from auto self refersh mode(ASR). + //bit 22 : send REFERSH command before enter to Auto self refresh mode(ASR). + //bit 21 : send ZQCS command after exit from Auto self refresh mode(ASR). + //bit 20 : send dfi_ctrl_upd after exit from ASR mode + //bit 19 : send power down command when enter ASR mode. //for LPDDR4 only. + //bit 18 : set the PHY enter LP2 mode after enter ASR mode. + //bit 17 : send DFI_LP_REQ after enter ASR mode. + //bit 16 : set DFI_CLK_DISABLE after enter ASR mode. + //bit 15:0. 0 disable auto ASR mode. + // Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode. +#define DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xfe036400) + //bit 17:8 auto refresh request pending cnt if there's page hit request. + //bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period + //bit 5 enable dmc send ZQCS command . + //bit 4. enable dmc send DFI_CTRUPD_REQ. + //bit 3:1. how many refresh command send for one period. = this number + 1 + //bit 0. enable dmc send auto refresh command. +#define DMC_DRAM_FREQ_CTRL ((0x0093 << 2) + 0xfe036400) +//bit 31 . wiret 1 to change freqency read 0: finished. +//bit 30:9. not used. +//bit 15. freq pre config_en. Before freq enter stop state let DMC configure DDR SDRAM. +//bit 14. freq post config_en. After freq enter stop state let DMC configure DDR SDRAM. +//bit 13. send zqcl after freq change in DDR3/4 mode. +//bit 12. send zqcs after freq change. 1: enable. 0 not send. +//bit 11. in AUTO MRW fucntion: the data format. 1: use USR_CMD format. 0: MRW format. +//bit 10. AUTO MRW function: 1 use hardware auto MRW function. 0: don't do auto MRW. +//bit 9. 1 : FREQ MRW done. let FREQ change machine continue. +//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle. + // 0 after freq change finishes the state machine go back to access state. +//bit 7 when change PLL setting, disable dmc clock +//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk. +//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait. +//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0. +//bit 3:1. not used. +//bit 0. current frequency selection. +#define DMC_DRAM_SCFG ((0x0094 << 2) + 0xfe036400) + // bit 2:0 only one bit can be high at same time. + // bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request. + // bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request. + // bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request. +#define DMC_DRAM_STAT ((0x0095 << 2) + 0xfe036400) + //bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back. + //bit 28:24 dram_sr_state + //bit 23:20 stop_st + //bit 19:15 sleep_st + //bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode. + //1 : ACCESS sending precharege command. + //2 : ACCESS sending AUTO REFESH command. + //3 : ACCESS sending DIF_CTRLUPD_REQ command. + //4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4). + //5 : ACCESS sending ZQLATCH command to LPDDR4 only. + //bit 11:8 APD STATUS: 0 : APD_IDLE + //1 : APD sending PRECHARGE command + //2 : APD sending CKE low command + //3 : APD sending DISABLE DRAM CLOCK command + //4 : APD sending DFI_LP_CTRL_REQ + //5 : APD in Auto Power down mode. + //6 : APD deassert DFI_LP_CTRL_REQ + //7 : APD sending enable DRAM CLOCK command + //8 : APD sending out CKE high command. + //bit 7:4: DRAM_STATUS: 0 : DRAM IDLE + //1 : DRAM_STOP/DRAM_CFG + //2 : DRAM_ACCESS + //3 : DRAM_SLEEP + //4 : DRAM APD(AUTO POWER DOWN). + //5 : IDLE -> STOP/CONFIG + //6 : STOP -> SLEEP + //7 : STOP -> ACCESS + //8 : ACCESS -> SLEEP. + //9 : ACCESS -> STOP + //A : ACCESS -> APD + //B : SLEEP -> STOP + //C : SLEEP -> ACCESS + //D : APD -> ACCESS + //bit 3 reserved. + //bit 2 1 : DRAM enter normal working state. + //bit 1 1 : DRAM enter sleep state. self refresh state. + //bit 0 1 : dram enter cfg state. +#define DMC_DRAM_STAT1 ((0x0096 << 2) + 0xfe036400) + //bit 11:8 freq_st. + //4'h0 : IDLE + //4'h1 : FREQ_CHECK_VPU + //4'h2 : FREQ_WAITING_STOP + //4'h3 : FREQ_DRAM_CFG. waiting DMC/software to send special MRW/MPC command to configure DDR SDRAM either before Freq change or after freq change. + //4'h4 : FREQ_SELF_REFR_ST. + //4'h5 : FREQ_SET_DFI_FREQ. + //4'h6 : FREQ_DFI_INIT_START_HIGH. + //4'h7 : FREQ_CHANGE PLL_ST. + //4'h8 : FREQ_UPDATA REG. + //4'h9 : FREQ_DFI_INIT_START_LOW. + //4'ha : FREQ_WAITING_FINISH + //bit 7:5 train_st + //bit 4:0 dram_phy_st +#define DMC_PHY_RETRAINING_CTRL ((0x0097 << 2) + 0xfe036400) + //bit 31 : phy_retraining enable. + //bit 30 : check vpu sleep_en. + //bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency. + //bit 23:0: retraining period unit : 100ns. +#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfe036400) + //LPDDR4 PHY DFI error infomation. + //bit 31:20. not used. + //bit 9. ddr0_dfi_error + //bit 8:5 ddr0_dfi_error_info. + //bit 4. ddr1_dfi_error. + //bit 3:0. ddr1_dfi_error_info. +#define DMC_LP2_TIMER ((0x009a << 2) + 0xfe036400) +//bit 15:0. timer setting to measure how long the chip is entered LP2 mode. +//this timer is 40bits counter with DMC PCLK. +//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode. +#define DMC_DRAM_DFI_SWAP_0 ((0x00a0 << 2) + 0xfe036400) + //bit 5:0. dfi_act_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_1 ((0x00a1 << 2) + 0xfe036400) + //bit 5:0. dfi_ras_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_2 ((0x00a2 << 2) + 0xfe036400) + //bit 5:0. dfi_cas_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_3 ((0x00a3 << 2) + 0xfe036400) + //bit 5:0. dfi_we_n function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_4 ((0x00a4 << 2) + 0xfe036400) + //bit 5:0. dfi_bg0 function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_5 ((0x00a5 << 2) + 0xfe036400) + //bit 5:0. dfi_bg[1] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_6 ((0x00a6 << 2) + 0xfe036400) + //bit 5:0. dfi_ba[0] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_7 ((0x00a7 << 2) + 0xfe036400) + //bit 5:0. dfi_ba[1] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_8 ((0x00a8 << 2) + 0xfe036400) + //bit 5:0. dfi_ba[2] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_9 ((0x00a9 << 2) + 0xfe036400) + //bit 5:0. dfi_a[0] function select + // 6'h00 : the function itself. + // 6'h01 : act_n. + // 6'h02 : ras_n. + // 6'h03 : cas_n. + // 6'h04 : we_n. + // 6'h05 : bg[0]. + // 6'h06 : bg[1]. + // 6'h07 : ba[0]. + // 6'h08 : ba[1]. + // 6'h09 : ba[2]. + // 6'h0a : a[0]. + // 6'h0b : a[1]. + // 6'h0c : a[2]. + // 6'h0d : a[3]. + // 6'h0e : a[4]. + // 6'h0f : a[5]. + // 6'h10 : a[6]. + // 6'h11 : a[7]. + // 6'h12 : a[8]. + // 6'h13 : a[9]. + // 6'h14 : a[10]. + // 6'h15 : a[11]. + // 6'h16 : a[12]. + // 6'h17 : a[13]. + // 6'h18 : a[14]. + // 6'h19 : a[15]. + // 6'h1a : a[16]. + // 6'h1b : a[17]. +#define DMC_DRAM_DFI_SWAP_10 ((0x00aa << 2) + 0xfe036400) + //bit 5:0. dfi_a[1] function select +#define DMC_DRAM_DFI_SWAP_11 ((0x00ab << 2) + 0xfe036400) + //bit 5:0. dfi_a[2] function select +#define DMC_DRAM_DFI_SWAP_12 ((0x00ac << 2) + 0xfe036400) + //bit 5:0. dfi_a[3] function select +#define DMC_DRAM_DFI_SWAP_13 ((0x00ad << 2) + 0xfe036400) + //bit 5:0. dfi_a[4] function select +#define DMC_DRAM_DFI_SWAP_14 ((0x00ae << 2) + 0xfe036400) + //bit 5:0. dfi_a[5] function select +#define DMC_DRAM_DFI_SWAP_15 ((0x00af << 2) + 0xfe036400) + //bit 5:0. dfi_a[6] function select +#define DMC_DRAM_DFI_SWAP_16 ((0x00b0 << 2) + 0xfe036400) + //bit 5:0. dfi_a[7] function select +#define DMC_DRAM_DFI_SWAP_17 ((0x00b1 << 2) + 0xfe036400) + //bit 5:0. dfi_a[8] function select +#define DMC_DRAM_DFI_SWAP_18 ((0x00b2 << 2) + 0xfe036400) + //bit 5:0. dfi_a[9] function select +#define DMC_DRAM_DFI_SWAP_19 ((0x00b3 << 2) + 0xfe036400) + //bit 5:0. dfi_a[10] function select +#define DMC_DRAM_DFI_SWAP_20 ((0x00b4 << 2) + 0xfe036400) + //bit 5:0. dfi_a[11] function select +#define DMC_DRAM_DFI_SWAP_21 ((0x00b5 << 2) + 0xfe036400) + //bit 5:0. dfi_a[12] function select +#define DMC_DRAM_DFI_SWAP_22 ((0x00b6 << 2) + 0xfe036400) + //bit 5:0. dfi_a[13] function select +#define DMC_DRAM_DFI_SWAP_23 ((0x00b7 << 2) + 0xfe036400) + //bit 5:0. dfi_a[14] function select +#define DMC_DRAM_DFI_SWAP_24 ((0x00b8 << 2) + 0xfe036400) + //bit 5:0. dfi_a[15] function select +#define DMC_DRAM_DFI_SWAP_25 ((0x00b9 << 2) + 0xfe036400) + //bit 5:0. dfi_a[16] function select +#define DMC_DRAM_DFI_SWAP_26 ((0x00ba << 2) + 0xfe036400) + //bit 5:0. dfi_a[17] function select +#define DMC_DRAM_CMD ((0x00d0 << 2) + 0xfe036400) + //bit 31. cmd done. write 0 to clean. + //bit 30. data done. write 0 to clean. + //bit 5. user defined command. + //bit 4. LPDDR4 MPC write data command( MPC WR FIFO). + //bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO). + //bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....) + //bit 1. mrr comand. + //bit 0. mrw command. +#define DMC_DRAM_CMD_CODE ((0x00d1 << 2) + 0xfe036400) + //bit 31:28 user command case: = {act_n, ras_n, cas_n, we_n} + //bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles. + // LPDDR4 4 clock cycles; + // DDR3/4/LPDDR3 : 2 clock cycles. + //bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. + //bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select. + //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0]. + //bit 15:0 opcode. +#define DMC_DRAM_CMD_TIME ((0x00d2 << 2) + 0xfe036400) +//bit 31:16 PRE CMD timer. //delay how many cycle to start the command. +//bit 15:0 POST CMD timer //delay how many cycle after the command execute. +#define DMC_DRAM_WSTRB0 ((0x00d3 << 2) + 0xfe036400) +#define DMC_DRAM_WSTRB1 ((0x00d4 << 2) + 0xfe036400) +#define DMC_DRAM_RDBI0 ((0x00d5 << 2) + 0xfe036400) + //MPC RD FIFO command DBI read back data + //bit 31:16 the second cycle. + //bit 15:0 the first cycle. +#define DMC_DRAM_RDBI1 ((0x00d6 << 2) + 0xfe036400) + //MPC RD FIFO command DBI read back data + //bit 31:16. the Forth cycle. + //bit 15:0. the third cycle. +//WD0~16 and RD0~16 can be used as MRW command as Frequency change . +//WD0~16 is for Freq1 DRAM MR setting, it would send to DRAM right before FREQ0-> FREQ1 +//RD0_16 is for Freq0 DRAM MR setting. it would send to DRAM right before FREQ1-> FREQ0. +//each register can be one MRW command. So total 16 MRW command can be sent to DRAM. +//The register formats: +//bit 31. MRW/USER comand enable. 1: enabled command. 0 not enabled. +//bit 30. last MRW/USER command. if this bit =1, After send this command, the DRAM controller will contine frequency next stage. +//bit 29:26. USER COMMAND parameter: in DDR3/DDR4. {act_n, ras_n, cas_n, we_n} value for user command + //in LPDDR4. bit 16: 1 4 cycles command. 0 2 cycles command. +//bit 25 MRW/USER command rank 1 select. 1: select. 0: not select. +//bit 24. MRW/USER command rank 0 select. 1: select. 0: not select. +//bit 23:0. USER command. + //DDR3: 18:16 bank address. 15:0: address. + //DDR4: 20:19 bank group address. 18:16: bank address. 15:0 address. + //LPDDR3: 9:0. rising edge address. 19:10. falling edge address. + //LPDDR4. 5:0, first edge address, 11:6 second edge address, 17:12: third edge address. 23:18, forth edge address. + //MRW command format: + //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0]. + //bit 15:0 opcode. +#define DMC_DRAM_WD0 ((0x00e0 << 2) + 0xfe036400) +#define DMC_DRAM_WD1 ((0x00e1 << 2) + 0xfe036400) +#define DMC_DRAM_WD2 ((0x00e2 << 2) + 0xfe036400) +#define DMC_DRAM_WD3 ((0x00e3 << 2) + 0xfe036400) +#define DMC_DRAM_WD4 ((0x00e4 << 2) + 0xfe036400) +#define DMC_DRAM_WD5 ((0x00e5 << 2) + 0xfe036400) +#define DMC_DRAM_WD6 ((0x00e6 << 2) + 0xfe036400) +#define DMC_DRAM_WD7 ((0x00e7 << 2) + 0xfe036400) +#define DMC_DRAM_WD8 ((0x00e8 << 2) + 0xfe036400) +#define DMC_DRAM_WD9 ((0x00e9 << 2) + 0xfe036400) +#define DMC_DRAM_WD10 ((0x00ea << 2) + 0xfe036400) +#define DMC_DRAM_WD11 ((0x00eb << 2) + 0xfe036400) +#define DMC_DRAM_WD12 ((0x00ec << 2) + 0xfe036400) +#define DMC_DRAM_WD13 ((0x00ed << 2) + 0xfe036400) +#define DMC_DRAM_WD14 ((0x00ee << 2) + 0xfe036400) +#define DMC_DRAM_WD15 ((0x00ef << 2) + 0xfe036400) +#define DMC_DRAM_RD0 ((0x00f0 << 2) + 0xfe036400) +#define DMC_DRAM_RD1 ((0x00f1 << 2) + 0xfe036400) +#define DMC_DRAM_RD2 ((0x00f2 << 2) + 0xfe036400) +#define DMC_DRAM_RD3 ((0x00f3 << 2) + 0xfe036400) +#define DMC_DRAM_RD4 ((0x00f4 << 2) + 0xfe036400) +#define DMC_DRAM_RD5 ((0x00f5 << 2) + 0xfe036400) +#define DMC_DRAM_RD6 ((0x00f6 << 2) + 0xfe036400) +#define DMC_DRAM_RD7 ((0x00f7 << 2) + 0xfe036400) +#define DMC_DRAM_RD8 ((0x00f8 << 2) + 0xfe036400) +#define DMC_DRAM_RD9 ((0x00f9 << 2) + 0xfe036400) +#define DMC_DRAM_RD10 ((0x00fa << 2) + 0xfe036400) +#define DMC_DRAM_RD11 ((0x00fb << 2) + 0xfe036400) +#define DMC_DRAM_RD12 ((0x00fc << 2) + 0xfe036400) +#define DMC_DRAM_RD13 ((0x00fd << 2) + 0xfe036400) +#define DMC_DRAM_RD14 ((0x00fe << 2) + 0xfe036400) +#define DMC_DRAM_RD15 ((0x00ff << 2) + 0xfe036400) +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh +// +// +// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//dmc sticky domain regsiters. +//`define DMC_STICKY_REG_BASE 32'hfe036800 +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe036800 +// ----------------------------------------------- +//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted. +//total DMC_STICKY registers is DMC_STICKY_0 ~ DMC_STICKY_127 total 128 regsiter. the address is from 0x00 ~0x80. here only list 64. +#define DMC_STICKY_0 ((0x0000 << 2) + 0xfe036800) +#define DMC_STICKY_1 ((0x0001 << 2) + 0xfe036800) +#define DMC_STICKY_2 ((0x0002 << 2) + 0xfe036800) +#define DMC_STICKY_3 ((0x0003 << 2) + 0xfe036800) +#define DMC_STICKY_4 ((0x0004 << 2) + 0xfe036800) +#define DMC_STICKY_5 ((0x0005 << 2) + 0xfe036800) +#define DMC_STICKY_6 ((0x0006 << 2) + 0xfe036800) +#define DMC_STICKY_7 ((0x0007 << 2) + 0xfe036800) +#define DMC_STICKY_8 ((0x0008 << 2) + 0xfe036800) +#define DMC_STICKY_9 ((0x0009 << 2) + 0xfe036800) +#define DMC_STICKY_10 ((0x000a << 2) + 0xfe036800) +#define DMC_STICKY_11 ((0x000b << 2) + 0xfe036800) +#define DMC_STICKY_12 ((0x000c << 2) + 0xfe036800) +#define DMC_STICKY_13 ((0x000d << 2) + 0xfe036800) +#define DMC_STICKY_14 ((0x000e << 2) + 0xfe036800) +#define DMC_STICKY_15 ((0x000f << 2) + 0xfe036800) +#define DMC_STICKY_16 ((0x0010 << 2) + 0xfe036800) +#define DMC_STICKY_17 ((0x0011 << 2) + 0xfe036800) +#define DMC_STICKY_18 ((0x0012 << 2) + 0xfe036800) +#define DMC_STICKY_19 ((0x0013 << 2) + 0xfe036800) +#define DMC_STICKY_20 ((0x0014 << 2) + 0xfe036800) +#define DMC_STICKY_21 ((0x0015 << 2) + 0xfe036800) +#define DMC_STICKY_22 ((0x0016 << 2) + 0xfe036800) +#define DMC_STICKY_23 ((0x0017 << 2) + 0xfe036800) +#define DMC_STICKY_24 ((0x0018 << 2) + 0xfe036800) +#define DMC_STICKY_25 ((0x0019 << 2) + 0xfe036800) +#define DMC_STICKY_26 ((0x001a << 2) + 0xfe036800) +#define DMC_STICKY_27 ((0x001b << 2) + 0xfe036800) +#define DMC_STICKY_28 ((0x001c << 2) + 0xfe036800) +#define DMC_STICKY_29 ((0x001d << 2) + 0xfe036800) +#define DMC_STICKY_30 ((0x001e << 2) + 0xfe036800) +#define DMC_STICKY_31 ((0x001f << 2) + 0xfe036800) +#define DMC_STICKY_32 ((0x0020 << 2) + 0xfe036800) +#define DMC_STICKY_33 ((0x0021 << 2) + 0xfe036800) +#define DMC_STICKY_34 ((0x0022 << 2) + 0xfe036800) +#define DMC_STICKY_35 ((0x0023 << 2) + 0xfe036800) +#define DMC_STICKY_36 ((0x0024 << 2) + 0xfe036800) +#define DMC_STICKY_37 ((0x0025 << 2) + 0xfe036800) +#define DMC_STICKY_38 ((0x0026 << 2) + 0xfe036800) +#define DMC_STICKY_39 ((0x0027 << 2) + 0xfe036800) +#define DMC_STICKY_40 ((0x0028 << 2) + 0xfe036800) +#define DMC_STICKY_41 ((0x0029 << 2) + 0xfe036800) +#define DMC_STICKY_42 ((0x002a << 2) + 0xfe036800) +#define DMC_STICKY_43 ((0x002b << 2) + 0xfe036800) +#define DMC_STICKY_44 ((0x002c << 2) + 0xfe036800) +#define DMC_STICKY_45 ((0x002d << 2) + 0xfe036800) +#define DMC_STICKY_46 ((0x002e << 2) + 0xfe036800) +#define DMC_STICKY_47 ((0x002f << 2) + 0xfe036800) +#define DMC_STICKY_48 ((0x0030 << 2) + 0xfe036800) +#define DMC_STICKY_49 ((0x0031 << 2) + 0xfe036800) +#define DMC_STICKY_50 ((0x0032 << 2) + 0xfe036800) +#define DMC_STICKY_51 ((0x0033 << 2) + 0xfe036800) +#define DMC_STICKY_52 ((0x0034 << 2) + 0xfe036800) +#define DMC_STICKY_53 ((0x0035 << 2) + 0xfe036800) +#define DMC_STICKY_54 ((0x0036 << 2) + 0xfe036800) +#define DMC_STICKY_55 ((0x0037 << 2) + 0xfe036800) +#define DMC_STICKY_56 ((0x0038 << 2) + 0xfe036800) +#define DMC_STICKY_57 ((0x0039 << 2) + 0xfe036800) +#define DMC_STICKY_58 ((0x003a << 2) + 0xfe036800) +#define DMC_STICKY_59 ((0x003b << 2) + 0xfe036800) +#define DMC_STICKY_60 ((0x003c << 2) + 0xfe036800) +#define DMC_STICKY_61 ((0x003d << 2) + 0xfe036800) +#define DMC_STICKY_62 ((0x003e << 2) + 0xfe036800) +#define DMC_STICKY_63 ((0x003f << 2) + 0xfe036800) +// +// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh +// +//======================================================================== +// STARTUP +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe02e000 +// ----------------------------------------------- +#define STARTUP_CTRL0 ((0x0000 << 2) + 0xfe02e000) +#define STARTUP_CTRL1 ((0x0001 << 2) + 0xfe02e000) +#define STARTUP_CTRL2 ((0x0002 << 2) + 0xfe02e000) +//======================================================================== +// MIPI_DSI_PHY +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe01c000 +// ----------------------------------------------- +//`define MIPI_DSI_PHY_START 8'h00 +//`define MIPI_DSI_PHY_END 16'hffff +#define MIPI_DSI_PHY_CTRL ((0x0000 << 2) + 0xfe01c000) + //bit 31. soft reset for the phy. 1 = reset. 0 = dessert the reset. + //bit 30. clock lane soft reset. + //bit 29. data byte lane 3 soft reset. + //bit 28. data byte lane 2 soft reset. + //bit 27. data byte lane 1 soft reset. + //bit 26. data byte lane 0 soft reset. + //bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first. + //bit 4. HS data endian. + //bit 3. force data byte lane in stop mode. + //bit 2. force data byte lane 0 in reciever mode. + //bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready. + //bit 0. enalbe the MIPI DSI PHY TxDDRClk. +#define MIPI_DSI_CHAN_CTRL ((0x0001 << 2) + 0xfe01c000) + //bit 31. clk lane tx_hs_en control selection. 1 = from register. 0 use clk lane state machine. + //bit 30. register bit for clock lane tx_hs_en. + //bit 29. clk lane tx_lp_en contrl selection. 1 = from register. 0 from clk lane state machine. + //bit 28. register bit for clock lane tx_lp_en. + //bit 27. chan0 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 26. register bit for chan0 tx_hs_en. + //bit 25. chan0 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 24. register bit from chan0 tx_lp_en. + //bit 23. chan0 rx_lp_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 22. register bit from chan0 rx_lp_en. + //bit 21. chan0 contention detection enable control selection. 1 = from register. 0 from chan0 state machine. + //bit 20. register bit from chan0 contention dectection enable. + //bit 19. chan1 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 18. register bit for chan1 tx_hs_en. + //bit 17. chan1 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 16. register bit from chan1 tx_lp_en. + //bit 15. chan2 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 14. register bit for chan2 tx_hs_en. + //bit 13. chan2 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 12. register bit from chan2 tx_lp_en. + //bit 11. chan3 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 10. register bit for chan3 tx_hs_en. + //bit 9. chan3 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine. + //bit 8. register bit from chan3 tx_lp_en. + //bit 4. clk chan power down. this bit is also used as the power down of the whole MIPI_DSI_PHY. + //bit 3. chan3 power down. + //bit 2. chan2 power down. + //bit 1. chan1 power down. + //bit 0. chan0 power down. +#define MIPI_DSI_CHAN_STS ((0x0002 << 2) + 0xfe01c000) + //bit 24. chan0 TX->RX turn can't accept the ACK command from slave watch dog triggered. write 1 to clear the status bit. + //bit 23. chan0 RX ESC command watch dog triggered. write 1 to clean this bit. + //bit +#define MIPI_DSI_CLK_TIM ((0x0003 << 2) + 0xfe01c000) + //bit 31:24. TCLK_PREPARE. + //bit 23:16. TCLK_ZERO. + //bit 15:8. TCLK_POST. + //bit 7:0. TCLK_TRAIL. +#define MIPI_DSI_HS_TIM ((0x0004 << 2) + 0xfe01c000) + //bit 31:24. THS_PREPARE. + //bit 23:16. THS_ZERO. + //bit 15:8. THS_TRAIL. + //bit 7:0. THS_EXIT. +#define MIPI_DSI_LP_TIM ((0x0005 << 2) + 0xfe01c000) + //bit 31:24. tTA_GET. + //bit 23:16. tTA_GO. + //bit 15:8. tTA_SURE. + //bit 7:0. tLPX. +#define MIPI_DSI_ANA_UP_TIM ((0x0006 << 2) + 0xfe01c000) + //wait time to MIPI DIS analog ready. +#define MIPI_DSI_INIT_TIM ((0x0007 << 2) + 0xfe01c000) + // TINIT. +#define MIPI_DSI_WAKEUP_TIM ((0x0008 << 2) + 0xfe01c000) + //TWAKEUP. +#define MIPI_DSI_LPOK_TIM ((0x0009 << 2) + 0xfe01c000) + //bit 31:0 when in RxULPS state, RX reciever is in sleep mode. + //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input. +#define MIPI_DSI_LP_WCHDOG ((0x000a << 2) + 0xfe01c000) + //bit 31:0 watch dog timer for MIPI DSI LP receive state. +#define MIPI_DSI_ANA_CTRL ((0x000b << 2) + 0xfe01c000) + //bit 31:0 tMBIAS. timer to wait for analog mBIAS voltage stable. +#define MIPI_DSI_CLK_TIM1 ((0x000c << 2) + 0xfe01c000) + //bit 31:8 not used. + //bit 7:0 tCLK_PRE +#define MIPI_DSI_TURN_WCHDOG ((0x000d << 2) + 0xfe01c000) + //bit 31:0 watch dog timer for lane 0 LP turn around waiting time. +#define MIPI_DSI_ULPS_CHECK ((0x000e << 2) + 0xfe01c000) + //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not. +#define MIPI_DSI_TEST_CTRL0 ((0x000f << 2) + 0xfe01c000) +#define MIPI_DSI_TEST_CTRL1 ((0x0010 << 2) + 0xfe01c000) +//======================================================================== +// Temp sensor PLL +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe020000 +// ----------------------------------------------- +#define TS_PLL_CFG_REG1 ((0x0001 << 2) + 0xfe020000) +#define TS_PLL_CFG_REG2 ((0x0002 << 2) + 0xfe020000) +#define TS_PLL_CFG_REG3 ((0x0003 << 2) + 0xfe020000) +#define TS_PLL_CFG_REG4 ((0x0004 << 2) + 0xfe020000) +#define TS_PLL_CFG_REG5 ((0x0005 << 2) + 0xfe020000) +#define TS_PLL_CFG_REG6 ((0x0006 << 2) + 0xfe020000) +#define TS_PLL_CFG_REG7 ((0x0007 << 2) + 0xfe020000) +#define TS_PLL_STAT0 ((0x0010 << 2) + 0xfe020000) +#define TS_PLL_STAT1 ((0x0011 << 2) + 0xfe020000) +#define TS_PLL_STAT2 ((0x0012 << 2) + 0xfe020000) +#define TS_PLL_STAT3 ((0x0013 << 2) + 0xfe020000) +#define TS_PLL_STAT4 ((0x0014 << 2) + 0xfe020000) +#define TS_PLL_STAT5 ((0x0015 << 2) + 0xfe020000) +#define TS_PLL_STAT6 ((0x0016 << 2) + 0xfe020000) +#define TS_PLL_STAT7 ((0x0017 << 2) + 0xfe020000) +#define TS_PLL_STAT8 ((0x0018 << 2) + 0xfe020000) +#define TS_PLL_STAT9 ((0x0019 << 2) + 0xfe020000) +//======================================================================== +// Temp sensor DDR +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe022000 +// ----------------------------------------------- +#define TS_DDR_CFG_REG1 ((0x0001 << 2) + 0xfe022000) +#define TS_DDR_CFG_REG2 ((0x0002 << 2) + 0xfe022000) +#define TS_DDR_CFG_REG3 ((0x0003 << 2) + 0xfe022000) +#define TS_DDR_CFG_REG4 ((0x0004 << 2) + 0xfe022000) +#define TS_DDR_CFG_REG5 ((0x0005 << 2) + 0xfe022000) +#define TS_DDR_CFG_REG6 ((0x0006 << 2) + 0xfe022000) +#define TS_DDR_CFG_REG7 ((0x0007 << 2) + 0xfe022000) +#define TS_DDR_STAT0 ((0x0010 << 2) + 0xfe022000) +#define TS_DDR_STAT1 ((0x0011 << 2) + 0xfe022000) +#define TS_DDR_STAT2 ((0x0012 << 2) + 0xfe022000) +#define TS_DDR_STAT3 ((0x0013 << 2) + 0xfe022000) +#define TS_DDR_STAT4 ((0x0014 << 2) + 0xfe022000) +#define TS_DDR_STAT5 ((0x0015 << 2) + 0xfe022000) +#define TS_DDR_STAT6 ((0x0016 << 2) + 0xfe022000) +#define TS_DDR_STAT7 ((0x0017 << 2) + 0xfe022000) +#define TS_DDR_STAT8 ((0x0018 << 2) + 0xfe022000) +#define TS_DDR_STAT9 ((0x0019 << 2) + 0xfe022000) +//======================================================================== +// Temp sensor GPU +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe035000 +// ----------------------------------------------- +//`define TS_GPU_CFG_REG1 8'h01 +//`define TS_GPU_CFG_REG2 8'h02 +//`define TS_GPU_CFG_REG3 8'h03 +//`define TS_GPU_CFG_REG4 8'h04 +//`define TS_GPU_CFG_REG5 8'h05 +//`define TS_GPU_CFG_REG6 8'h06 +//`define TS_GPU_CFG_REG7 8'h07 +//`define TS_GPU_STAT0 8'h10 +//`define TS_GPU_STAT1 8'h11 +//`define TS_GPU_STAT2 8'h12 +//`define TS_GPU_STAT3 8'h13 +//`define TS_GPU_STAT4 8'h14 +//`define TS_GPU_STAT5 8'h15 +//`define TS_GPU_STAT6 8'h16 +//`define TS_GPU_STAT7 8'h17 +//`define TS_GPU_STAT8 8'h18 +//`define TS_GPU_STAT9 8'h19 +//======================================================================== +// RNG +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe034000 +// ----------------------------------------------- +//======================================================================== +// ACODEC +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe01a000 +// ----------------------------------------------- +#define ACODEC_0 ((0x0000 << 2) + 0xfe01a000) +#define ACODEC_1 ((0x0001 << 2) + 0xfe01a000) +#define ACODEC_2 ((0x0002 << 2) + 0xfe01a000) +#define ACODEC_3 ((0x0003 << 2) + 0xfe01a000) +#define ACODEC_4 ((0x0004 << 2) + 0xfe01a000) +#define ACODEC_5 ((0x0005 << 2) + 0xfe01a000) +#define ACODEC_6 ((0x0006 << 2) + 0xfe01a000) +#define ACODEC_7 ((0x0007 << 2) + 0xfe01a000) +//======================================================================== +// AML USB PHY A +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe03c000 +// ----------------------------------------------- +#define AMLUSB_A0 ((0x0000 << 2) + 0xfe03c000) +#define AMLUSB_A1 ((0x0001 << 2) + 0xfe03c000) +#define AMLUSB_A2 ((0x0002 << 2) + 0xfe03c000) +#define AMLUSB_A3 ((0x0003 << 2) + 0xfe03c000) +#define AMLUSB_A4 ((0x0004 << 2) + 0xfe03c000) +#define AMLUSB_A5 ((0x0005 << 2) + 0xfe03c000) +#define AMLUSB_A6 ((0x0006 << 2) + 0xfe03c000) +#define AMLUSB_A7 ((0x0007 << 2) + 0xfe03c000) +#define AMLUSB_A8 ((0x0008 << 2) + 0xfe03c000) +#define AMLUSB_A9 ((0x0009 << 2) + 0xfe03c000) +#define AMLUSB_A10 ((0x000a << 2) + 0xfe03c000) +#define AMLUSB_A11 ((0x000b << 2) + 0xfe03c000) +#define AMLUSB_A12 ((0x000c << 2) + 0xfe03c000) +#define AMLUSB_A13 ((0x000d << 2) + 0xfe03c000) +#define AMLUSB_A14 ((0x000e << 2) + 0xfe03c000) +#define AMLUSB_A15 ((0x000f << 2) + 0xfe03c000) +#define AMLUSB_A16 ((0x0010 << 2) + 0xfe03c000) +#define AMLUSB_A17 ((0x0011 << 2) + 0xfe03c000) +#define AMLUSB_A18 ((0x0012 << 2) + 0xfe03c000) +#define AMLUSB_A19 ((0x0013 << 2) + 0xfe03c000) +#define AMLUSB_A20 ((0x0014 << 2) + 0xfe03c000) +#define AMLUSB_A21 ((0x0015 << 2) + 0xfe03c000) +#define AMLUSB_A22 ((0x0016 << 2) + 0xfe03c000) +#define AMLUSB_A23 ((0x0017 << 2) + 0xfe03c000) +#define AMLUSB_A24 ((0x0018 << 2) + 0xfe03c000) +#define AMLUSB_A25 ((0x0019 << 2) + 0xfe03c000) +#define AMLUSB_A26 ((0x001a << 2) + 0xfe03c000) +#define AMLUSB_A27 ((0x001b << 2) + 0xfe03c000) +#define AMLUSB_A28 ((0x001c << 2) + 0xfe03c000) +#define AMLUSB_A29 ((0x001d << 2) + 0xfe03c000) +#define AMLUSB_A30 ((0x001e << 2) + 0xfe03c000) +#define AMLUSB_A31 ((0x001f << 2) + 0xfe03c000) +//======================================================================== +// AML USB PHY B +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe03e000 +// ----------------------------------------------- +#define AMLUSB_B0 ((0x0000 << 2) + 0xfe03e000) +#define AMLUSB_B1 ((0x0001 << 2) + 0xfe03e000) +#define AMLUSB_B2 ((0x0002 << 2) + 0xfe03e000) +#define AMLUSB_B3 ((0x0003 << 2) + 0xfe03e000) +#define AMLUSB_B4 ((0x0004 << 2) + 0xfe03e000) +#define AMLUSB_B5 ((0x0005 << 2) + 0xfe03e000) +#define AMLUSB_B6 ((0x0006 << 2) + 0xfe03e000) +#define AMLUSB_B7 ((0x0007 << 2) + 0xfe03e000) +#define AMLUSB_B8 ((0x0008 << 2) + 0xfe03e000) +#define AMLUSB_B9 ((0x0009 << 2) + 0xfe03e000) +#define AMLUSB_B10 ((0x000a << 2) + 0xfe03e000) +#define AMLUSB_B11 ((0x000b << 2) + 0xfe03e000) +#define AMLUSB_B12 ((0x000c << 2) + 0xfe03e000) +#define AMLUSB_B13 ((0x000d << 2) + 0xfe03e000) +#define AMLUSB_B14 ((0x000e << 2) + 0xfe03e000) +#define AMLUSB_B15 ((0x000f << 2) + 0xfe03e000) +#define AMLUSB_B16 ((0x0010 << 2) + 0xfe03e000) +#define AMLUSB_B17 ((0x0011 << 2) + 0xfe03e000) +#define AMLUSB_B18 ((0x0012 << 2) + 0xfe03e000) +#define AMLUSB_B19 ((0x0013 << 2) + 0xfe03e000) +#define AMLUSB_B20 ((0x0014 << 2) + 0xfe03e000) +#define AMLUSB_B21 ((0x0015 << 2) + 0xfe03e000) +#define AMLUSB_B22 ((0x0016 << 2) + 0xfe03e000) +#define AMLUSB_B23 ((0x0017 << 2) + 0xfe03e000) +#define AMLUSB_B24 ((0x0018 << 2) + 0xfe03e000) +#define AMLUSB_B25 ((0x0019 << 2) + 0xfe03e000) +#define AMLUSB_B26 ((0x001a << 2) + 0xfe03e000) +#define AMLUSB_B27 ((0x001b << 2) + 0xfe03e000) +#define AMLUSB_B28 ((0x001c << 2) + 0xfe03e000) +#define AMLUSB_B29 ((0x001d << 2) + 0xfe03e000) +#define AMLUSB_B30 ((0x001e << 2) + 0xfe03e000) +#define AMLUSB_B31 ((0x001f << 2) + 0xfe03e000) +//======================================================================== +// PAD_CTRL +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe004000 +// ----------------------------------------------- +#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGG ((0x0010 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGH ((0x0011 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGI ((0x0012 << 2) + 0xfe004000) +#define PADCTRL_PIN_MUX_REGJ ((0x0013 << 2) + 0xfe004000) +#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0020 << 2) + 0xfe004000) +#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0021 << 2) + 0xfe004000) +#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0022 << 2) + 0xfe004000) +#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0023 << 2) + 0xfe004000) +#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0024 << 2) + 0xfe004000) +#define PADCTRL_GPIO_IRQ_CTRL5 ((0x0025 << 2) + 0xfe004000) +#define PADCTRL_GPIO_IRQ_CTRL6 ((0x0026 << 2) + 0xfe004000) +#define PADCTRL_GPIO_IRQ_CTRL7 ((0x0027 << 2) + 0xfe004000) +#define PADCTRL_WORLD_SYNC_CTRL0 ((0x0028 << 2) + 0xfe004000) +#define PADCTRL_GPIO_MSR_CTRL0 ((0x0029 << 2) + 0xfe004000) +#define PADCTRL_MISC_CTRL0 ((0x002a << 2) + 0xfe004000) +#define PADCTRL_GPIOZ_I ((0x0030 << 2) + 0xfe004000) +#define PADCTRL_GPIOZ_O ((0x0031 << 2) + 0xfe004000) +#define PADCTRL_GPIOZ_OEN ((0x0032 << 2) + 0xfe004000) +#define PADCTRL_GPIOZ_PULL_EN ((0x0033 << 2) + 0xfe004000) +#define PADCTRL_GPIOZ_PULL_UP ((0x0034 << 2) + 0xfe004000) +#define PADCTRL_GPIOZ_LOCK ((0x0035 << 2) + 0xfe004000) +#define PADCTRL_GPIOZ_PROT ((0x0036 << 2) + 0xfe004000) +#define PADCTRL_GPIOZ_DS ((0x0037 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_I ((0x0040 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_O ((0x0041 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_OEN ((0x0042 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_PULL_EN ((0x0043 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_PULL_UP ((0x0044 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_LOCK ((0x0045 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_PROT ((0x0046 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_DS ((0x0047 << 2) + 0xfe004000) +#define PADCTRL_GPIOX_DS_EXT ((0x0048 << 2) + 0xfe004000) +#define PADCTRL_GPIOH_I ((0x0050 << 2) + 0xfe004000) +#define PADCTRL_GPIOH_O ((0x0051 << 2) + 0xfe004000) +#define PADCTRL_GPIOH_OEN ((0x0052 << 2) + 0xfe004000) +#define PADCTRL_GPIOH_PULL_EN ((0x0053 << 2) + 0xfe004000) +#define PADCTRL_GPIOH_PULL_UP ((0x0054 << 2) + 0xfe004000) +#define PADCTRL_GPIOH_LOCK ((0x0055 << 2) + 0xfe004000) +#define PADCTRL_GPIOH_PROT ((0x0056 << 2) + 0xfe004000) +#define PADCTRL_GPIOH_DS ((0x0057 << 2) + 0xfe004000) +#define PADCTRL_GPIOD_I ((0x0060 << 2) + 0xfe004000) +#define PADCTRL_GPIOD_O ((0x0061 << 2) + 0xfe004000) +#define PADCTRL_GPIOD_OEN ((0x0062 << 2) + 0xfe004000) +#define PADCTRL_GPIOD_PULL_EN ((0x0063 << 2) + 0xfe004000) +#define PADCTRL_GPIOD_PULL_UP ((0x0064 << 2) + 0xfe004000) +#define PADCTRL_GPIOD_LOCK ((0x0065 << 2) + 0xfe004000) +#define PADCTRL_GPIOD_PROT ((0x0066 << 2) + 0xfe004000) +#define PADCTRL_GPIOD_DS ((0x0067 << 2) + 0xfe004000) +#define PADCTRL_GPIOE_I ((0x0070 << 2) + 0xfe004000) +#define PADCTRL_GPIOE_O ((0x0071 << 2) + 0xfe004000) +#define PADCTRL_GPIOE_OEN ((0x0072 << 2) + 0xfe004000) +#define PADCTRL_GPIOE_PULL_EN ((0x0073 << 2) + 0xfe004000) +#define PADCTRL_GPIOE_PULL_UP ((0x0074 << 2) + 0xfe004000) +#define PADCTRL_GPIOE_LOCK ((0x0075 << 2) + 0xfe004000) +#define PADCTRL_GPIOE_PROT ((0x0076 << 2) + 0xfe004000) +#define PADCTRL_GPIOE_DS ((0x0077 << 2) + 0xfe004000) +#define PADCTRL_GPIOC_I ((0x0080 << 2) + 0xfe004000) +#define PADCTRL_GPIOC_O ((0x0081 << 2) + 0xfe004000) +#define PADCTRL_GPIOC_OEN ((0x0082 << 2) + 0xfe004000) +#define PADCTRL_GPIOC_PULL_EN ((0x0083 << 2) + 0xfe004000) +#define PADCTRL_GPIOC_PULL_UP ((0x0084 << 2) + 0xfe004000) +#define PADCTRL_GPIOC_LOCK ((0x0085 << 2) + 0xfe004000) +#define PADCTRL_GPIOC_PROT ((0x0086 << 2) + 0xfe004000) +#define PADCTRL_GPIOC_DS ((0x0087 << 2) + 0xfe004000) +#define PADCTRL_GPIOB_I ((0x0090 << 2) + 0xfe004000) +#define PADCTRL_GPIOB_O ((0x0091 << 2) + 0xfe004000) +#define PADCTRL_GPIOB_OEN ((0x0092 << 2) + 0xfe004000) +#define PADCTRL_GPIOB_PULL_EN ((0x0093 << 2) + 0xfe004000) +#define PADCTRL_GPIOB_PULL_UP ((0x0094 << 2) + 0xfe004000) +#define PADCTRL_GPIOB_LOCK ((0x0095 << 2) + 0xfe004000) +#define PADCTRL_GPIOB_PROT ((0x0096 << 2) + 0xfe004000) +#define PADCTRL_GPIOB_DS ((0x0097 << 2) + 0xfe004000) +#define PADCTRL_GPIOA_I ((0x00a0 << 2) + 0xfe004000) +#define PADCTRL_GPIOA_O ((0x00a1 << 2) + 0xfe004000) +#define PADCTRL_GPIOA_OEN ((0x00a2 << 2) + 0xfe004000) +#define PADCTRL_GPIOA_PULL_EN ((0x00a3 << 2) + 0xfe004000) +#define PADCTRL_GPIOA_PULL_UP ((0x00a4 << 2) + 0xfe004000) +#define PADCTRL_GPIOA_LOCK ((0x00a5 << 2) + 0xfe004000) +#define PADCTRL_GPIOA_PROT ((0x00a6 << 2) + 0xfe004000) +#define PADCTRL_GPIOA_DS ((0x00a7 << 2) + 0xfe004000) +#define PADCTRL_TESTN_I ((0x00b0 << 2) + 0xfe004000) +#define PADCTRL_TESTN_O ((0x00b1 << 2) + 0xfe004000) +#define PADCTRL_TESTN_OEN ((0x00b2 << 2) + 0xfe004000) +#define PADCTRL_TESTN_PULL_EN ((0x00b3 << 2) + 0xfe004000) +#define PADCTRL_TESTN_PULL_UP ((0x00b4 << 2) + 0xfe004000) +#define PADCTRL_TESTN_LOCK ((0x00b5 << 2) + 0xfe004000) +#define PADCTRL_TESTN_PROT ((0x00b6 << 2) + 0xfe004000) +#define PADCTRL_TESTN_DS ((0x00b7 << 2) + 0xfe004000) +#define PADCTRL_LOCK_PIN_MUX0 ((0x00d0 << 2) + 0xfe004000) +#define PADCTRL_LOCK_PIN_MUX1 ((0x00d1 << 2) + 0xfe004000) +#define PADCTRL_LOCK_PIN_MUX2 ((0x00d2 << 2) + 0xfe004000) +#define PADCTRL_LOCK_PIN_MUX3 ((0x00d3 << 2) + 0xfe004000) +#define PADCTRL_LOCK_PIN_MUX4 ((0x00d4 << 2) + 0xfe004000) +#define PADCTRL_PROT_PIN_MUX0 ((0x00d8 << 2) + 0xfe004000) +#define PADCTRL_PROT_PIN_MUX1 ((0x00d9 << 2) + 0xfe004000) +#define PADCTRL_PROT_PIN_MUX2 ((0x00da << 2) + 0xfe004000) +#define PADCTRL_PROT_PIN_MUX3 ((0x00db << 2) + 0xfe004000) +#define PADCTRL_PROT_PIN_MUX4 ((0x00dc << 2) + 0xfe004000) +#define PADCTRL_MUTE_CTRL ((0x00e0 << 2) + 0xfe004000) +#define PADCTRL_MUTE_TDM_DISA ((0x00e1 << 2) + 0xfe004000) +#define PADCTRL_DEBUG_SEL ((0x00e2 << 2) + 0xfe004000) +//======================================================================== +// SYS_CTRL +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe010000 +// ----------------------------------------------- +#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe010000) +#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe010000) +#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe010000) +#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe010000) +#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe010000) +#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe010000) +#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe010000) +#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe010000) +#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe010000) +#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe010000) +#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe010000) +#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe010000) +#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe010000) +#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe010000) +#define SYSCTRL_TIMERE_CTRL ((0x003a << 2) + 0xfe010000) +#define SYSCTRL_TIMERE ((0x003b << 2) + 0xfe010000) +#define SYSCTRL_TIMERE_HI ((0x003c << 2) + 0xfe010000) +#define SYSCTRL_TIMERF_CTRL ((0x003d << 2) + 0xfe010000) +#define SYSCTRL_TIMERF ((0x003e << 2) + 0xfe010000) +#define SYSCTRL_TIMERF_HI ((0x003f << 2) + 0xfe010000) +#define SYSCTRL_TIMERG_CTRL ((0x0040 << 2) + 0xfe010000) +#define SYSCTRL_TIMERG ((0x0041 << 2) + 0xfe010000) +#define SYSCTRL_TIMERH_CTRL ((0x0042 << 2) + 0xfe010000) +#define SYSCTRL_TIMERH ((0x0043 << 2) + 0xfe010000) +#define SYSCTRL_TIMERI_CTRL ((0x0044 << 2) + 0xfe010000) +#define SYSCTRL_TIMERI ((0x0045 << 2) + 0xfe010000) +#define SYSCTRL_TIMERJ_CTRL ((0x0046 << 2) + 0xfe010000) +#define SYSCTRL_TIMERJ ((0x0047 << 2) + 0xfe010000) +#define SYSCTRL_SEC_TIMERE_CTRL ((0x0048 << 2) + 0xfe010000) +#define SYSCTRL_SEC_TIMERE ((0x0049 << 2) + 0xfe010000) +#define SYSCTRL_SEC_TIMERE_HI ((0x004a << 2) + 0xfe010000) +#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe010000) +#define SYSCTRL_OSC_RING_CTRL1 ((0x0051 << 2) + 0xfe010000) +#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe010000) +#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe010000) +#define SYSCTRL_AXI_PIPE_CTRL0 ((0x0055 << 2) + 0xfe010000) +#define SYSCTRL_AXI_PIPE_CTRL1 ((0x0056 << 2) + 0xfe010000) +#define SYSCTRL_TIMER90K ((0x0057 << 2) + 0xfe010000) +#define SYSCTRL_SCR ((0x0058 << 2) + 0xfe010000) +#define SYSCTRL_HPG_TIMER ((0x0059 << 2) + 0xfe010000) +//`define SYSCTRL_VIPNANOQ_CTRL0 10'h5A +#define SYSCTRL_AHB2DDR_CTRL0 ((0x005b << 2) + 0xfe010000) +#define SYSCTRL_AHB2DDR_CTRL1 ((0x005c << 2) + 0xfe010000) +#define SYSCTRL_POC ((0x0060 << 2) + 0xfe010000) +#define SYSCTRL_VPU_SECURE_REG0 ((0x0061 << 2) + 0xfe010000) +#define SYSCTRL_VPU_SECURE_REG1 ((0x0062 << 2) + 0xfe010000) +//`define SYSCTRL_NIC_CFG0 10'h63 +#define SYSCTRL_ALERT_STS ((0x0064 << 2) + 0xfe010000) +#define SYSCTRL_ALERT_ENABLE ((0x0066 << 2) + 0xfe010000) +#define SYSCTRL_ENABLE_SPIFC ((0x0068 << 2) + 0xfe010000) +#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe010000) +#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe010000) +#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe010000) +#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe010000) +#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe010000) +#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe010000) +#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe010000) +#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe010000) +#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe010000) +#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe010000) +#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe010000) +#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe010000) +#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe010000) +#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe010000) +#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe010000) +#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe010000) +#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe010000) +#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe010000) +#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe010000) +#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe010000) +#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe010000) +#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe010000) +#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe010000) +#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG24 ((0x00d8 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG25 ((0x00d9 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG26 ((0x00da << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG27 ((0x00db << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG28 ((0x00dc << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG29 ((0x00dd << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG30 ((0x00de << 2) + 0xfe010000) +#define SYSCTRL_SEC_STATUS_REG31 ((0x00df << 2) + 0xfe010000) +#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe010000) +#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe010000) +#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe010000) +#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe010000) +#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe010000) +#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe010000) +//======================================================================== +// CLK_CTRL +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 +// ----------------------------------------------- +#define CLKCTRL_OSCIN_CTRL ((0x0001 << 2) + 0xfe000000) +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 ((0x0002 << 2) + 0xfe000000) +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 ((0x0003 << 2) + 0xfe000000) +#define CLKCTRL_RTC_CTRL ((0x0004 << 2) + 0xfe000000) +#define CLKCTRL_CHECK_CLK_RESULT ((0x0005 << 2) + 0xfe000000) +#define CLKCTRL_MBIST_ATSPEED_CTRL ((0x0006 << 2) + 0xfe000000) +#define CLKCTRL_LOCK_BIT_REG0 ((0x0008 << 2) + 0xfe000000) +#define CLKCTRL_LOCK_BIT_REG1 ((0x0009 << 2) + 0xfe000000) +#define CLKCTRL_LOCK_BIT_REG2 ((0x000a << 2) + 0xfe000000) +#define CLKCTRL_LOCK_BIT_REG3 ((0x000b << 2) + 0xfe000000) +#define CLKCTRL_PROT_BIT_REG0 ((0x000c << 2) + 0xfe000000) +#define CLKCTRL_PROT_BIT_REG1 ((0x000d << 2) + 0xfe000000) +#define CLKCTRL_PROT_BIT_REG2 ((0x000e << 2) + 0xfe000000) +#define CLKCTRL_PROT_BIT_REG3 ((0x000f << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_CTRL0 ((0x0010 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_EN0_REG0 ((0x0011 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_EN0_REG1 ((0x0012 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_EN0_REG2 ((0x0013 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_EN0_REG3 ((0x0014 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_EN1_REG0 ((0x0015 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_EN1_REG1 ((0x0016 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_EN1_REG2 ((0x0017 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_EN1_REG3 ((0x0018 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_VPU_EN0 ((0x0019 << 2) + 0xfe000000) +#define CLKCTRL_SYS_CLK_VPU_EN1 ((0x001a << 2) + 0xfe000000) +#define CLKCTRL_AXI_CLK_CTRL0 ((0x001b << 2) + 0xfe000000) +#define CLKCTRL_TST_CTRL0 ((0x0020 << 2) + 0xfe000000) +#define CLKCTRL_TST_CTRL1 ((0x0021 << 2) + 0xfe000000) +#define CLKCTRL_CECA_CTRL0 ((0x0022 << 2) + 0xfe000000) +#define CLKCTRL_CECA_CTRL1 ((0x0023 << 2) + 0xfe000000) +#define CLKCTRL_CECB_CTRL0 ((0x0024 << 2) + 0xfe000000) +#define CLKCTRL_CECB_CTRL1 ((0x0025 << 2) + 0xfe000000) +#define CLKCTRL_SC_CLK_CTRL ((0x0026 << 2) + 0xfe000000) +#define CLKCTRL_DSPA_CLK_CTRL0 ((0x0027 << 2) + 0xfe000000) +#define CLKCTRL_DSPB_CLK_CTRL0 ((0x0028 << 2) + 0xfe000000) +#define CLKCTRL_RAMA_CLK_CTRL0 ((0x0029 << 2) + 0xfe000000) +#define CLKCTRL_VID_CLK_CTRL ((0x0030 << 2) + 0xfe000000) +#define CLKCTRL_VID_CLK_CTRL2 ((0x0031 << 2) + 0xfe000000) +#define CLKCTRL_VID_CLK_DIV ((0x0032 << 2) + 0xfe000000) +#define CLKCTRL_VIID_CLK_DIV ((0x0033 << 2) + 0xfe000000) +#define CLKCTRL_VIID_CLK_CTRL ((0x0034 << 2) + 0xfe000000) +#define CLKCTRL_HDMI_CLK_CTRL ((0x0038 << 2) + 0xfe000000) +#define CLKCTRL_VID_PLL_CLK_DIV ((0x0039 << 2) + 0xfe000000) +#define CLKCTRL_VPU_CLK_CTRL ((0x003a << 2) + 0xfe000000) +#define CLKCTRL_VPU_CLKB_CTRL ((0x003b << 2) + 0xfe000000) +#define CLKCTRL_VPU_CLKC_CTRL ((0x003c << 2) + 0xfe000000) +#define CLKCTRL_VID_LOCK_CLK_CTRL ((0x003d << 2) + 0xfe000000) +#define CLKCTRL_VDIN_MEAS_CLK_CTRL ((0x003e << 2) + 0xfe000000) +#define CLKCTRL_VAPBCLK_CTRL ((0x003f << 2) + 0xfe000000) +#define CLKCTRL_HDCP22_CLK_CTRL ((0x0040 << 2) + 0xfe000000) +#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL ((0x0041 << 2) + 0xfe000000) +#define CLKCTRL_CDAC_CLK_CTRL ((0x0042 << 2) + 0xfe000000) +#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL ((0x0043 << 2) + 0xfe000000) +#define CLKCTRL_CSI2_ADAPT_CLK_CTRL ((0x0044 << 2) + 0xfe000000) +#define CLKCTRL_VDEC_CLK_CTRL ((0x0050 << 2) + 0xfe000000) +#define CLKCTRL_VDEC2_CLK_CTRL ((0x0051 << 2) + 0xfe000000) +#define CLKCTRL_VDEC3_CLK_CTRL ((0x0052 << 2) + 0xfe000000) +#define CLKCTRL_VDEC4_CLK_CTRL ((0x0053 << 2) + 0xfe000000) +#define CLKCTRL_WAVE420L_CLK_CTRL ((0x0054 << 2) + 0xfe000000) +#define CLKCTRL_WAVE420L_CLK_CTRL2 ((0x0055 << 2) + 0xfe000000) +#define CLKCTRL_TS_CLK_CTRL ((0x0056 << 2) + 0xfe000000) +#define CLKCTRL_MALI_CLK_CTRL ((0x0057 << 2) + 0xfe000000) +#define CLKCTRL_VIPNANOQ_CLK_CTRL ((0x0058 << 2) + 0xfe000000) +#define CLKCTRL_ETH_CLK_CTRL ((0x0059 << 2) + 0xfe000000) +#define CLKCTRL_NAND_CLK_CTRL ((0x005a << 2) + 0xfe000000) +#define CLKCTRL_SD_EMMC_CLK_CTRL ((0x005b << 2) + 0xfe000000) +#define CLKCTRL_BT656_CLK_CTRL ((0x005c << 2) + 0xfe000000) +#define CLKCTRL_SPICC_CLK_CTRL ((0x005d << 2) + 0xfe000000) +#define CLKCTRL_GEN_CLK_CTRL ((0x005e << 2) + 0xfe000000) +#define CLKCTRL_SAR_CLK_CTRL0 ((0x005f << 2) + 0xfe000000) +#define CLKCTRL_PWM_CLK_AB_CTRL ((0x0060 << 2) + 0xfe000000) +#define CLKCTRL_PWM_CLK_CD_CTRL ((0x0061 << 2) + 0xfe000000) +#define CLKCTRL_PWM_CLK_EF_CTRL ((0x0062 << 2) + 0xfe000000) +#define CLKCTRL_PWM_CLK_GH_CTRL ((0x0063 << 2) + 0xfe000000) +#define CLKCTRL_PWM_CLK_IJ_CTRL ((0x0064 << 2) + 0xfe000000) +#define CLKCTRL_TIMESTAMP_CTRL ((0x0100 << 2) + 0xfe000000) +#define CLKCTRL_TIMESTAMP_CTRL1 ((0x0101 << 2) + 0xfe000000) +#define CLKCTRL_TIMESTAMP_CTRL2 ((0x0103 << 2) + 0xfe000000) +#define CLKCTRL_TIMESTAMP_RD0 ((0x0104 << 2) + 0xfe000000) +#define CLKCTRL_TIMESTAMP_RD1 ((0x0105 << 2) + 0xfe000000) +#define CLKCTRL_TIMEBASE_CTRL0 ((0x0106 << 2) + 0xfe000000) +#define CLKCTRL_TIMEBASE_CTRL1 ((0x0107 << 2) + 0xfe000000) +#define CLKCTRL_EFUSE_CPU_CFG01 ((0x0120 << 2) + 0xfe000000) +#define CLKCTRL_EFUSE_CPU_CFG2 ((0x0121 << 2) + 0xfe000000) +#define CLKCTRL_EFUSE_ENCP_CFG0 ((0x0122 << 2) + 0xfe000000) +#define CLKCTRL_EFUSE_MALI_CFG01 ((0x0123 << 2) + 0xfe000000) +#define CLKCTRL_EFUSE_HEVCB_CFG01 ((0x0124 << 2) + 0xfe000000) +#define CLKCTRL_EFUSE_HEVCB_CFG2 ((0x0125 << 2) + 0xfe000000) +#define CLKCTRL_EFUSE_LOCK ((0x0126 << 2) + 0xfe000000) +//======================================================================== +// PWR_CTRL +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000 +// ----------------------------------------------- +#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe00c000) +#define PWRCTRL_PWR_ACK1 ((0x0001 << 2) + 0xfe00c000) +#define PWRCTRL_PWR_OFF0 ((0x0004 << 2) + 0xfe00c000) +#define PWRCTRL_PWR_OFF1 ((0x0005 << 2) + 0xfe00c000) +#define PWRCTRL_ISO_EN0 ((0x0008 << 2) + 0xfe00c000) +#define PWRCTRL_ISO_EN1 ((0x0009 << 2) + 0xfe00c000) +#define PWRCTRL_FOCRST0 ((0x000c << 2) + 0xfe00c000) +#define PWRCTRL_FOCRST1 ((0x000d << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD0 ((0x0010 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD1 ((0x0011 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD2 ((0x0012 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD3 ((0x0013 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD4 ((0x0014 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD5 ((0x0015 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD6 ((0x0016 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD7 ((0x0017 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD8 ((0x0018 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD9 ((0x0019 << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD10 ((0x001a << 2) + 0xfe00c000) +#define PWRCTRL_MEM_PD11 ((0x001b << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL0 ((0x0040 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL1 ((0x0041 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL2 ((0x0042 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL3 ((0x0043 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_AUTO_OFF_CTRL4 ((0x0044 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_TIMER_TH_01 ((0x0048 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_TIMER_TH_23 ((0x0049 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_TIMER_TH_45 ((0x004a << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_TIMER_TH_67 ((0x004b << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_TIMER_TH_89 ((0x004c << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_IRQ_MASK0 ((0x0050 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_IRQ_MASK1 ((0x0051 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_IRQ_MASK2 ((0x0052 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_IRQ_MASK3 ((0x0053 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_IRQ_MASK4 ((0x0054 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_IRQ_MASK5 ((0x0055 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_IRQ_MASK6 ((0x0056 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_IRQ_MASK7 ((0x0057 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_MEMPD_INIT_SET ((0x0060 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_MEMPD_OFF_SET ((0x0061 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_MEMPD_ON_A_SET ((0x0062 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_MEMPD_ON_B_SET ((0x0063 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_MEMPD_ON_C_SET ((0x0064 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_MEMPD_ON_D_SET ((0x0065 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_MEMPD_STS ((0x0066 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_FSM_STS0 ((0x0067 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_FSM_STS1 ((0x0068 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_FSM_STS2 ((0x0069 << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_FSM_START_OFF ((0x006d << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_FSM_START_ON ((0x006e << 2) + 0xfe00c000) +#define PWRCTRL_CPU0_FSM_JUMP ((0x006f << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL0 ((0x0070 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL1 ((0x0071 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL2 ((0x0072 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL3 ((0x0073 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_AUTO_OFF_CTRL4 ((0x0074 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_TIMER_TH_01 ((0x0078 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_TIMER_TH_23 ((0x0079 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_TIMER_TH_45 ((0x007a << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_TIMER_TH_67 ((0x007b << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_TIMER_TH_89 ((0x007c << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_IRQ_MASK0 ((0x0080 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_IRQ_MASK1 ((0x0081 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_IRQ_MASK2 ((0x0082 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_IRQ_MASK3 ((0x0083 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_IRQ_MASK4 ((0x0084 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_IRQ_MASK5 ((0x0085 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_IRQ_MASK6 ((0x0086 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_IRQ_MASK7 ((0x0087 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_MEMPD_INIT_SET ((0x0090 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_MEMPD_OFF_SET ((0x0091 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_MEMPD_ON_A_SET ((0x0092 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_MEMPD_ON_B_SET ((0x0093 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_MEMPD_ON_C_SET ((0x0094 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_MEMPD_ON_D_SET ((0x0095 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_MEMPD_STS ((0x0096 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_FSM_STS0 ((0x0097 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_FSM_STS1 ((0x0098 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_FSM_STS2 ((0x0099 << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_FSM_START_OFF ((0x009d << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_FSM_START_ON ((0x009e << 2) + 0xfe00c000) +#define PWRCTRL_CPU1_FSM_JUMP ((0x009f << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL0 ((0x00a0 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL1 ((0x00a1 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL2 ((0x00a2 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL3 ((0x00a3 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_AUTO_OFF_CTRL4 ((0x00a4 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_TIMER_TH_01 ((0x00a8 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_TIMER_TH_23 ((0x00a9 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_TIMER_TH_45 ((0x00aa << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_TIMER_TH_67 ((0x00ab << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_TIMER_TH_89 ((0x00ac << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_IRQ_MASK0 ((0x00b0 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_IRQ_MASK1 ((0x00b1 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_IRQ_MASK2 ((0x00b2 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_IRQ_MASK3 ((0x00b3 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_IRQ_MASK4 ((0x00b4 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_IRQ_MASK5 ((0x00b5 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_IRQ_MASK6 ((0x00b6 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_IRQ_MASK7 ((0x00b7 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_MEMPD_INIT_SET ((0x00c0 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_MEMPD_OFF_SET ((0x00c1 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_MEMPD_ON_A_SET ((0x00c2 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_MEMPD_ON_B_SET ((0x00c3 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_MEMPD_ON_C_SET ((0x00c4 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_MEMPD_ON_D_SET ((0x00c5 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_MEMPD_STS ((0x00c6 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_FSM_STS0 ((0x00c7 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_FSM_STS1 ((0x00c8 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_FSM_STS2 ((0x00c9 << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_FSM_START_OFF ((0x00cd << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_FSM_START_ON ((0x00ce << 2) + 0xfe00c000) +#define PWRCTRL_CPU2_FSM_JUMP ((0x00cf << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL0 ((0x00d0 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL1 ((0x00d1 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL2 ((0x00d2 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL3 ((0x00d3 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_AUTO_OFF_CTRL4 ((0x00d4 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_TIMER_TH_01 ((0x00d8 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_TIMER_TH_23 ((0x00d9 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_TIMER_TH_45 ((0x00da << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_TIMER_TH_67 ((0x00db << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_TIMER_TH_89 ((0x00dc << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_IRQ_MASK0 ((0x00e0 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_IRQ_MASK1 ((0x00e1 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_IRQ_MASK2 ((0x00e2 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_IRQ_MASK3 ((0x00e3 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_IRQ_MASK4 ((0x00e4 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_IRQ_MASK5 ((0x00e5 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_IRQ_MASK6 ((0x00e6 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_IRQ_MASK7 ((0x00e7 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_MEMPD_INIT_SET ((0x00f0 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_MEMPD_OFF_SET ((0x00f1 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_MEMPD_ON_A_SET ((0x00f2 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_MEMPD_ON_B_SET ((0x00f3 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_MEMPD_ON_C_SET ((0x00f4 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_MEMPD_ON_D_SET ((0x00f5 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_MEMPD_STS ((0x00f6 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_FSM_STS0 ((0x00f7 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_FSM_STS1 ((0x00f8 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_FSM_STS2 ((0x00f9 << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_FSM_START_OFF ((0x00fd << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_FSM_START_ON ((0x00fe << 2) + 0xfe00c000) +#define PWRCTRL_CPU3_FSM_JUMP ((0x00ff << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL0 ((0x0100 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL1 ((0x0101 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL2 ((0x0102 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL3 ((0x0103 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL4 ((0x0104 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_TIMER_TH_01 ((0x0108 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_TIMER_TH_23 ((0x0109 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_TIMER_TH_45 ((0x010a << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_TIMER_TH_67 ((0x010b << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_TIMER_TH_89 ((0x010c << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_IRQ_MASK0 ((0x0110 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_IRQ_MASK1 ((0x0111 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_IRQ_MASK2 ((0x0112 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_IRQ_MASK3 ((0x0113 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_IRQ_MASK4 ((0x0114 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_IRQ_MASK5 ((0x0115 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_IRQ_MASK6 ((0x0116 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_IRQ_MASK7 ((0x0117 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_MEMPD_INIT_SET ((0x0120 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_MEMPD_OFF_SET ((0x0121 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_MEMPD_ON_A_SET ((0x0122 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_MEMPD_ON_B_SET ((0x0123 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_MEMPD_ON_C_SET ((0x0124 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_MEMPD_ON_D_SET ((0x0125 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_MEMPD_STS ((0x0126 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_FSM_STS0 ((0x0127 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_FSM_STS1 ((0x0128 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_FSM_STS2 ((0x0129 << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_FSM_START_OFF ((0x012d << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_FSM_START_ON ((0x012e << 2) + 0xfe00c000) +#define PWRCTRL_CPUTOP_FSM_JUMP ((0x012f << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL0 ((0x0130 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL1 ((0x0131 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL2 ((0x0132 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL3 ((0x0133 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_AUTO_OFF_CTRL4 ((0x0134 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_TIMER_TH_01 ((0x0138 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_TIMER_TH_23 ((0x0139 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_TIMER_TH_45 ((0x013a << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_TIMER_TH_67 ((0x013b << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_TIMER_TH_89 ((0x013c << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_IRQ_MASK0 ((0x0140 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_IRQ_MASK1 ((0x0141 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_IRQ_MASK2 ((0x0142 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_IRQ_MASK3 ((0x0143 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_IRQ_MASK4 ((0x0144 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_IRQ_MASK5 ((0x0145 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_IRQ_MASK6 ((0x0146 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_IRQ_MASK7 ((0x0147 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_MEMPD_INIT_SET ((0x0150 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_MEMPD_OFF_SET ((0x0151 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_MEMPD_ON_A_SET ((0x0152 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_MEMPD_ON_B_SET ((0x0153 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_MEMPD_ON_C_SET ((0x0154 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_MEMPD_ON_D_SET ((0x0155 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_MEMPD_STS ((0x0156 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_FSM_STS0 ((0x0157 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_FSM_STS1 ((0x0158 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_FSM_STS2 ((0x0159 << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_FSM_START_OFF ((0x015d << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_FSM_START_ON ((0x015e << 2) + 0xfe00c000) +#define PWRCTRL_DSPA_FSM_JUMP ((0x015f << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL0 ((0x0160 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL1 ((0x0161 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL2 ((0x0162 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL3 ((0x0163 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_AUTO_OFF_CTRL4 ((0x0164 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_TIMER_TH_01 ((0x0168 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_TIMER_TH_23 ((0x0169 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_TIMER_TH_45 ((0x016a << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_TIMER_TH_67 ((0x016b << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_TIMER_TH_89 ((0x016c << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_IRQ_MASK0 ((0x0170 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_IRQ_MASK1 ((0x0171 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_IRQ_MASK2 ((0x0172 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_IRQ_MASK3 ((0x0173 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_IRQ_MASK4 ((0x0174 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_IRQ_MASK5 ((0x0175 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_IRQ_MASK6 ((0x0176 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_IRQ_MASK7 ((0x0177 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_MEMPD_INIT_SET ((0x0180 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_MEMPD_OFF_SET ((0x0181 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_MEMPD_ON_A_SET ((0x0182 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_MEMPD_ON_B_SET ((0x0183 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_MEMPD_ON_C_SET ((0x0184 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_MEMPD_ON_D_SET ((0x0185 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_MEMPD_STS ((0x0186 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_FSM_STS0 ((0x0187 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_FSM_STS1 ((0x0188 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_FSM_STS2 ((0x0189 << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_FSM_START_OFF ((0x018d << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_FSM_START_ON ((0x018e << 2) + 0xfe00c000) +#define PWRCTRL_DSPB_FSM_JUMP ((0x018f << 2) + 0xfe00c000) +//======================================================================== +// RSA +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe042000 +// ----------------------------------------------- +//======================================================================== +// AOCPU +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe09c000 +// ----------------------------------------------- +#define AOCPU_CPU_CTRL0 ((0x0000 << 2) + 0xfe09c000) +#define AOCPU_CPU_CTRL1 ((0x0001 << 2) + 0xfe09c000) +#define AOCPU_CPU_CTRL2 ((0x0002 << 2) + 0xfe09c000) +#define AOCPU_CPU_CTRL3 ((0x0003 << 2) + 0xfe09c000) +#define AOCPU_CPU_CTRL4 ((0x0004 << 2) + 0xfe09c000) +#define AOCPU_CPU_CTRL5 ((0x0005 << 2) + 0xfe09c000) +#define AOCPU_CPU_STS0 ((0x000a << 2) + 0xfe09c000) +#define AOCPU_CPU_STS1 ((0x000b << 2) + 0xfe09c000) +#define AOCPU_CPU_STS2 ((0x000c << 2) + 0xfe09c000) +#define AOCPU_CPU_STS3 ((0x000d << 2) + 0xfe09c000) +#define AOCPU_CPU_VECTOR ((0x000f << 2) + 0xfe09c000) +#define AOCPU_IRQ_SEL0 ((0x0010 << 2) + 0xfe09c000) +#define AOCPU_IRQ_SEL1 ((0x0011 << 2) + 0xfe09c000) +#define AOCPU_IRQ_SEL2 ((0x0012 << 2) + 0xfe09c000) +#define AOCPU_IRQ_SEL3 ((0x0013 << 2) + 0xfe09c000) +#define AOCPU_IRQ_SEL4 ((0x0014 << 2) + 0xfe09c000) +#define AOCPU_IRQ_SEL5 ((0x0015 << 2) + 0xfe09c000) +#define AOCPU_IRQ_SEL6 ((0x0016 << 2) + 0xfe09c000) +#define AOCPU_IRQ_SEL7 ((0x0017 << 2) + 0xfe09c000) +#define AOCPU_STS00_BYCPU ((0x0018 << 2) + 0xfe09c000) +#define AOCPU_STS01_BYCPU ((0x0019 << 2) + 0xfe09c000) +#define AOCPU_STS02_BYCPU ((0x001a << 2) + 0xfe09c000) +#define AOCPU_STS03_BYCPU ((0x001b << 2) + 0xfe09c000) +#define AOCPU_STS04_BYCPU ((0x001c << 2) + 0xfe09c000) +#define AOCPU_STS05_BYCPU ((0x001d << 2) + 0xfe09c000) +#define AOCPU_STS06_BYCPU ((0x001e << 2) + 0xfe09c000) +#define AOCPU_STS07_BYCPU ((0x001f << 2) + 0xfe09c000) +//======================================================================== +// AUCPU +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe09e000 +// ----------------------------------------------- +#define AUCPU_CPU_CTRL0 ((0x0000 << 2) + 0xfe09e000) +#define AUCPU_CPU_CTRL1 ((0x0001 << 2) + 0xfe09e000) +#define AUCPU_CPU_CTRL2 ((0x0002 << 2) + 0xfe09e000) +#define AUCPU_CPU_CTRL3 ((0x0003 << 2) + 0xfe09e000) +#define AUCPU_CPU_CTRL4 ((0x0004 << 2) + 0xfe09e000) +#define AUCPU_CPU_CTRL5 ((0x0005 << 2) + 0xfe09e000) +#define AUCPU_CPU_STS0 ((0x000a << 2) + 0xfe09e000) +#define AUCPU_CPU_STS1 ((0x000b << 2) + 0xfe09e000) +#define AUCPU_CPU_STS2 ((0x000c << 2) + 0xfe09e000) +#define AUCPU_CPU_STS3 ((0x000d << 2) + 0xfe09e000) +#define AUCPU_DMA_APB_SEL ((0x0010 << 2) + 0xfe09e000) +#define AUCPU_IRQ_AP2RISCV ((0x0011 << 2) + 0xfe09e000) +#define AUCPU_IRQ_RISCV2AP ((0x0012 << 2) + 0xfe09e000) +#define AUCPU_STS00_BY_AP ((0x0020 << 2) + 0xfe09e000) +#define AUCPU_STS01_BY_AP ((0x0021 << 2) + 0xfe09e000) +#define AUCPU_STS02_BY_AP ((0x0022 << 2) + 0xfe09e000) +#define AUCPU_STS03_BY_AP ((0x0023 << 2) + 0xfe09e000) +#define AUCPU_STS04_BY_AP ((0x0024 << 2) + 0xfe09e000) +#define AUCPU_STS05_BY_AP ((0x0025 << 2) + 0xfe09e000) +#define AUCPU_STS06_BY_AP ((0x0026 << 2) + 0xfe09e000) +#define AUCPU_STS07_BY_AP ((0x0027 << 2) + 0xfe09e000) +#define AUCPU_STS08_BY_AP ((0x0028 << 2) + 0xfe09e000) +#define AUCPU_STS09_BY_AP ((0x0029 << 2) + 0xfe09e000) +#define AUCPU_STS10_BY_AP ((0x002a << 2) + 0xfe09e000) +#define AUCPU_STS11_BY_AP ((0x002b << 2) + 0xfe09e000) +#define AUCPU_STS12_BY_AP ((0x002c << 2) + 0xfe09e000) +#define AUCPU_STS13_BY_AP ((0x002d << 2) + 0xfe09e000) +#define AUCPU_STS14_BY_AP ((0x002e << 2) + 0xfe09e000) +#define AUCPU_STS15_BY_AP ((0x002f << 2) + 0xfe09e000) +#define AUCPU_STS16_BY_AP ((0x0030 << 2) + 0xfe09e000) +#define AUCPU_STS17_BY_AP ((0x0031 << 2) + 0xfe09e000) +#define AUCPU_STS18_BY_AP ((0x0032 << 2) + 0xfe09e000) +#define AUCPU_STS19_BY_AP ((0x0033 << 2) + 0xfe09e000) +#define AUCPU_STS20_BY_AP ((0x0034 << 2) + 0xfe09e000) +#define AUCPU_STS21_BY_AP ((0x0035 << 2) + 0xfe09e000) +#define AUCPU_STS22_BY_AP ((0x0036 << 2) + 0xfe09e000) +#define AUCPU_STS23_BY_AP ((0x0037 << 2) + 0xfe09e000) +#define AUCPU_STS24_BY_AP ((0x0038 << 2) + 0xfe09e000) +#define AUCPU_STS25_BY_AP ((0x0039 << 2) + 0xfe09e000) +#define AUCPU_STS26_BY_AP ((0x003a << 2) + 0xfe09e000) +#define AUCPU_STS27_BY_AP ((0x003b << 2) + 0xfe09e000) +#define AUCPU_STS28_BY_AP ((0x003c << 2) + 0xfe09e000) +#define AUCPU_STS29_BY_AP ((0x003d << 2) + 0xfe09e000) +#define AUCPU_STS30_BY_AP ((0x003e << 2) + 0xfe09e000) +#define AUCPU_STS31_BY_AP ((0x003f << 2) + 0xfe09e000) +#define AUCPU_STS00_BY_RISCV ((0x0040 << 2) + 0xfe09e000) +#define AUCPU_STS01_BY_RISCV ((0x0041 << 2) + 0xfe09e000) +#define AUCPU_STS02_BY_RISCV ((0x0042 << 2) + 0xfe09e000) +#define AUCPU_STS03_BY_RISCV ((0x0043 << 2) + 0xfe09e000) +#define AUCPU_STS04_BY_RISCV ((0x0044 << 2) + 0xfe09e000) +#define AUCPU_STS05_BY_RISCV ((0x0045 << 2) + 0xfe09e000) +#define AUCPU_STS06_BY_RISCV ((0x0046 << 2) + 0xfe09e000) +#define AUCPU_STS07_BY_RISCV ((0x0047 << 2) + 0xfe09e000) +#define AUCPU_STS08_BY_RISCV ((0x0048 << 2) + 0xfe09e000) +#define AUCPU_STS09_BY_RISCV ((0x0049 << 2) + 0xfe09e000) +#define AUCPU_STS10_BY_RISCV ((0x004a << 2) + 0xfe09e000) +#define AUCPU_STS11_BY_RISCV ((0x004b << 2) + 0xfe09e000) +#define AUCPU_STS12_BY_RISCV ((0x004c << 2) + 0xfe09e000) +#define AUCPU_STS13_BY_RISCV ((0x004d << 2) + 0xfe09e000) +#define AUCPU_STS14_BY_RISCV ((0x004e << 2) + 0xfe09e000) +#define AUCPU_STS15_BY_RISCV ((0x004f << 2) + 0xfe09e000) +#define AUCPU_STS16_BY_RISCV ((0x0050 << 2) + 0xfe09e000) +#define AUCPU_STS17_BY_RISCV ((0x0051 << 2) + 0xfe09e000) +#define AUCPU_STS18_BY_RISCV ((0x0052 << 2) + 0xfe09e000) +#define AUCPU_STS19_BY_RISCV ((0x0053 << 2) + 0xfe09e000) +#define AUCPU_STS20_BY_RISCV ((0x0054 << 2) + 0xfe09e000) +#define AUCPU_STS21_BY_RISCV ((0x0055 << 2) + 0xfe09e000) +#define AUCPU_STS22_BY_RISCV ((0x0056 << 2) + 0xfe09e000) +#define AUCPU_STS23_BY_RISCV ((0x0057 << 2) + 0xfe09e000) +#define AUCPU_STS24_BY_RISCV ((0x0058 << 2) + 0xfe09e000) +#define AUCPU_STS25_BY_RISCV ((0x0059 << 2) + 0xfe09e000) +#define AUCPU_STS26_BY_RISCV ((0x005a << 2) + 0xfe09e000) +#define AUCPU_STS27_BY_RISCV ((0x005b << 2) + 0xfe09e000) +#define AUCPU_STS28_BY_RISCV ((0x005c << 2) + 0xfe09e000) +#define AUCPU_STS29_BY_RISCV ((0x005d << 2) + 0xfe09e000) +#define AUCPU_STS30_BY_RISCV ((0x005e << 2) + 0xfe09e000) +#define AUCPU_STS31_BY_RISCV ((0x005f << 2) + 0xfe09e000) +#define AUCPU_DEMUX_STS_BY_RISCV ((0x0060 << 2) + 0xfe09e000) +#define AUCPU_DEMUX_STS0 ((0x0061 << 2) + 0xfe09e000) +#define AUCPU_DEMUX_STS1 ((0x0062 << 2) + 0xfe09e000) +//======================================================================== +// AXI_SRAM +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe090000 +// ----------------------------------------------- +#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfe090000) +#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfe090000) +#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfe090000) +#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfe090000) +#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfe090000) +#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfe090000) +#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfe090000) +#define SRAM_RANGE7_STA ((0x0007 << 2) + 0xfe090000) +#define SRAM_RANGE8_STA ((0x0008 << 2) + 0xfe090000) +#define SRAM_RANGE9_STA ((0x0009 << 2) + 0xfe090000) +#define SRAM_RANGE10_STA ((0x000a << 2) + 0xfe090000) +#define SRAM_RANGE11_STA ((0x000b << 2) + 0xfe090000) +#define SRAM_RANGE12_STA ((0x000c << 2) + 0xfe090000) +#define SRAM_RANGE13_STA ((0x000d << 2) + 0xfe090000) +#define SRAM_RANGE14_STA ((0x000e << 2) + 0xfe090000) +#define SRAM_RANGE0_EDA ((0x000f << 2) + 0xfe090000) +#define SRAM_RANGE1_EDA ((0x0010 << 2) + 0xfe090000) +#define SRAM_RANGE2_EDA ((0x0011 << 2) + 0xfe090000) +#define SRAM_RANGE3_EDA ((0x0012 << 2) + 0xfe090000) +#define SRAM_RANGE4_EDA ((0x0013 << 2) + 0xfe090000) +#define SRAM_RANGE5_EDA ((0x0014 << 2) + 0xfe090000) +#define SRAM_RANGE6_EDA ((0x0015 << 2) + 0xfe090000) +#define SRAM_RANGE7_EDA ((0x0016 << 2) + 0xfe090000) +#define SRAM_RANGE8_EDA ((0x0017 << 2) + 0xfe090000) +#define SRAM_RANGE9_EDA ((0x0018 << 2) + 0xfe090000) +#define SRAM_RANGE10_EDA ((0x0019 << 2) + 0xfe090000) +#define SRAM_RANGE11_EDA ((0x001a << 2) + 0xfe090000) +#define SRAM_RANGE12_EDA ((0x001b << 2) + 0xfe090000) +#define SRAM_RANGE13_EDA ((0x001c << 2) + 0xfe090000) +#define SRAM_RANGE14_EDA ((0x001d << 2) + 0xfe090000) +#define SRAM_RANGE0_READ_CTRL0 ((0x001e << 2) + 0xfe090000) +#define SRAM_RANGE1_READ_CTRL0 ((0x001f << 2) + 0xfe090000) +#define SRAM_RANGE2_READ_CTRL0 ((0x0020 << 2) + 0xfe090000) +#define SRAM_RANGE3_READ_CTRL0 ((0x0021 << 2) + 0xfe090000) +#define SRAM_RANGE4_READ_CTRL0 ((0x0022 << 2) + 0xfe090000) +#define SRAM_RANGE5_READ_CTRL0 ((0x0023 << 2) + 0xfe090000) +#define SRAM_RANGE6_READ_CTRL0 ((0x0024 << 2) + 0xfe090000) +#define SRAM_RANGE7_READ_CTRL0 ((0x0025 << 2) + 0xfe090000) +#define SRAM_RANGE8_READ_CTRL0 ((0x0026 << 2) + 0xfe090000) +#define SRAM_RANGE9_READ_CTRL0 ((0x0027 << 2) + 0xfe090000) +#define SRAM_RANGE10_READ_CTRL0 ((0x0028 << 2) + 0xfe090000) +#define SRAM_RANGE11_READ_CTRL0 ((0x0029 << 2) + 0xfe090000) +#define SRAM_RANGE12_READ_CTRL0 ((0x002a << 2) + 0xfe090000) +#define SRAM_RANGE13_READ_CTRL0 ((0x002b << 2) + 0xfe090000) +#define SRAM_RANGE14_READ_CTRL0 ((0x002c << 2) + 0xfe090000) +#define SRAM_RANGE15_READ_CTRL0 ((0x002d << 2) + 0xfe090000) +#define SRAM_RANGE0_WRITE_CTRL0 ((0x002e << 2) + 0xfe090000) +#define SRAM_RANGE1_WRITE_CTRL0 ((0x002f << 2) + 0xfe090000) +#define SRAM_RANGE2_WRITE_CTRL0 ((0x0030 << 2) + 0xfe090000) +#define SRAM_RANGE3_WRITE_CTRL0 ((0x0031 << 2) + 0xfe090000) +#define SRAM_RANGE4_WRITE_CTRL0 ((0x0032 << 2) + 0xfe090000) +#define SRAM_RANGE5_WRITE_CTRL0 ((0x0033 << 2) + 0xfe090000) +#define SRAM_RANGE6_WRITE_CTRL0 ((0x0034 << 2) + 0xfe090000) +#define SRAM_RANGE7_WRITE_CTRL0 ((0x0035 << 2) + 0xfe090000) +#define SRAM_RANGE8_WRITE_CTRL0 ((0x0036 << 2) + 0xfe090000) +#define SRAM_RANGE9_WRITE_CTRL0 ((0x0037 << 2) + 0xfe090000) +#define SRAM_RANGE10_WRITE_CTRL0 ((0x0038 << 2) + 0xfe090000) +#define SRAM_RANGE11_WRITE_CTRL0 ((0x0039 << 2) + 0xfe090000) +#define SRAM_RANGE12_WRITE_CTRL0 ((0x003a << 2) + 0xfe090000) +#define SRAM_RANGE13_WRITE_CTRL0 ((0x003b << 2) + 0xfe090000) +#define SRAM_RANGE14_WRITE_CTRL0 ((0x003c << 2) + 0xfe090000) +#define SRAM_RANGE15_WRITE_CTRL0 ((0x003d << 2) + 0xfe090000) +#define SRAM_RANGE0_READ_CTRL1 ((0x003e << 2) + 0xfe090000) +#define SRAM_RANGE1_READ_CTRL1 ((0x003f << 2) + 0xfe090000) +#define SRAM_RANGE2_READ_CTRL1 ((0x0040 << 2) + 0xfe090000) +#define SRAM_RANGE3_READ_CTRL1 ((0x0041 << 2) + 0xfe090000) +#define SRAM_RANGE4_READ_CTRL1 ((0x0042 << 2) + 0xfe090000) +#define SRAM_RANGE5_READ_CTRL1 ((0x0043 << 2) + 0xfe090000) +#define SRAM_RANGE6_READ_CTRL1 ((0x0044 << 2) + 0xfe090000) +#define SRAM_RANGE7_READ_CTRL1 ((0x0045 << 2) + 0xfe090000) +#define SRAM_RANGE8_READ_CTRL1 ((0x0046 << 2) + 0xfe090000) +#define SRAM_RANGE9_READ_CTRL1 ((0x0047 << 2) + 0xfe090000) +#define SRAM_RANGE10_READ_CTRL1 ((0x0048 << 2) + 0xfe090000) +#define SRAM_RANGE11_READ_CTRL1 ((0x0049 << 2) + 0xfe090000) +#define SRAM_RANGE12_READ_CTRL1 ((0x004a << 2) + 0xfe090000) +#define SRAM_RANGE13_READ_CTRL1 ((0x004b << 2) + 0xfe090000) +#define SRAM_RANGE14_READ_CTRL1 ((0x004c << 2) + 0xfe090000) +#define SRAM_RANGE15_READ_CTRL1 ((0x004d << 2) + 0xfe090000) +#define SRAM_RANGE0_WRITE_CTRL1 ((0x004e << 2) + 0xfe090000) +#define SRAM_RANGE1_WRITE_CTRL1 ((0x004f << 2) + 0xfe090000) +#define SRAM_RANGE2_WRITE_CTRL1 ((0x0050 << 2) + 0xfe090000) +#define SRAM_RANGE3_WRITE_CTRL1 ((0x0051 << 2) + 0xfe090000) +#define SRAM_RANGE4_WRITE_CTRL1 ((0x0052 << 2) + 0xfe090000) +#define SRAM_RANGE5_WRITE_CTRL1 ((0x0053 << 2) + 0xfe090000) +#define SRAM_RANGE6_WRITE_CTRL1 ((0x0054 << 2) + 0xfe090000) +#define SRAM_RANGE7_WRITE_CTRL1 ((0x0055 << 2) + 0xfe090000) +#define SRAM_RANGE8_WRITE_CTRL1 ((0x0056 << 2) + 0xfe090000) +#define SRAM_RANGE9_WRITE_CTRL1 ((0x0057 << 2) + 0xfe090000) +#define SRAM_RANGE10_WRITE_CTRL1 ((0x0058 << 2) + 0xfe090000) +#define SRAM_RANGE11_WRITE_CTRL1 ((0x0059 << 2) + 0xfe090000) +#define SRAM_RANGE12_WRITE_CTRL1 ((0x005a << 2) + 0xfe090000) +#define SRAM_RANGE13_WRITE_CTRL1 ((0x005b << 2) + 0xfe090000) +#define SRAM_RANGE14_WRITE_CTRL1 ((0x005c << 2) + 0xfe090000) +#define SRAM_RANGE15_WRITE_CTRL1 ((0x005d << 2) + 0xfe090000) +#define SRAM_GLOBAL_READ_CTRL0 ((0x005e << 2) + 0xfe090000) +#define SRAM_GLOBAL_READ_CTRL1 ((0x005f << 2) + 0xfe090000) +#define SRAM_GLOBAL_WRITE_CTRL0 ((0x0060 << 2) + 0xfe090000) +#define SRAM_GLOBAL_WRITE_CTRL1 ((0x0061 << 2) + 0xfe090000) +#define SRAM_SEC_CTRL0 ((0x0062 << 2) + 0xfe090000) +#define SRAM_REG_LOCK0 ((0x0063 << 2) + 0xfe090000) +#define SRAM_REG_LOCK1 ((0x0064 << 2) + 0xfe090000) +#define SRAM_REG_LOCK2 ((0x0065 << 2) + 0xfe090000) +#define SRAM_GLOBAL_READ_CTRL0_LOCK ((0x0066 << 2) + 0xfe090000) +#define SRAM_GLOBAL_READ_CTRL1_LOCK ((0x0067 << 2) + 0xfe090000) +#define SRAM_GLOBAL_WRITE_CTRL0_LOCK ((0x0068 << 2) + 0xfe090000) +#define SRAM_GLOBAL_WRITE_CTRL1_LOCK ((0x0069 << 2) + 0xfe090000) +#define SRAM_SEC_CTRL0_LOCK ((0x006a << 2) + 0xfe090000) +//======================================================================== +// MAILBOX +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe006000 +// ----------------------------------------------- +#define MAILBOX_WR_MBOX00 ((0x0000 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX01 ((0x0020 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX02 ((0x0040 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX03 ((0x0060 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX04 ((0x0080 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX05 ((0x00a0 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX06 ((0x00c0 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX07 ((0x00e0 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX08 ((0x0100 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX09 ((0x0120 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX10 ((0x0140 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX11 ((0x0160 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX12 ((0x0180 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX13 ((0x01a0 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX14 ((0x01c0 << 2) + 0xfe006000) +#define MAILBOX_WR_MBOX15 ((0x01e0 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX00 ((0x0200 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX01 ((0x0220 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX02 ((0x0240 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX03 ((0x0260 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX04 ((0x0280 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX05 ((0x02a0 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX06 ((0x02c0 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX07 ((0x02e0 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX08 ((0x0300 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX09 ((0x0320 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX10 ((0x0340 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX11 ((0x0360 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX12 ((0x0380 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX13 ((0x03a0 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX14 ((0x03c0 << 2) + 0xfe006000) +#define MAILBOX_RD_MBOX15 ((0x03e0 << 2) + 0xfe006000) +#define MAILBOX_LOCK_BIT0 ((0x0400 << 2) + 0xfe006000) +#define MAILBOX_LOCK_BIT1 ((0x0401 << 2) + 0xfe006000) +#define MAILBOX_PROT_BIT0 ((0x0402 << 2) + 0xfe006000) +#define MAILBOX_PROT_BIT1 ((0x0403 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_IRQA_CLR ((0x0404 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_IRQB_CLR ((0x0405 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_IRQC_CLR ((0x0406 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_IRQD_CLR ((0x0407 << 2) + 0xfe006000) +#define MAILBOX_IRQA_MASK ((0x0408 << 2) + 0xfe006000) +#define MAILBOX_IRQB_MASK ((0x0409 << 2) + 0xfe006000) +#define MAILBOX_IRQC_MASK ((0x040a << 2) + 0xfe006000) +#define MAILBOX_IRQD_MASK ((0x040b << 2) + 0xfe006000) +#define MAILBOX_IRQ_TYPE ((0x040c << 2) + 0xfe006000) +#define MAILBOX_IRQA_CLR ((0x0410 << 2) + 0xfe006000) +#define MAILBOX_IRQB_CLR ((0x0411 << 2) + 0xfe006000) +#define MAILBOX_IRQC_CLR ((0x0412 << 2) + 0xfe006000) +#define MAILBOX_IRQD_CLR ((0x0413 << 2) + 0xfe006000) +#define MAILBOX_IRQA_STS ((0x0414 << 2) + 0xfe006000) +#define MAILBOX_IRQB_STS ((0x0415 << 2) + 0xfe006000) +#define MAILBOX_IRQC_STS ((0x0416 << 2) + 0xfe006000) +#define MAILBOX_IRQD_STS ((0x0417 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX00 ((0x0420 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX01 ((0x0421 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX02 ((0x0422 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX03 ((0x0423 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX04 ((0x0424 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX05 ((0x0425 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX06 ((0x0426 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX07 ((0x0427 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX08 ((0x0428 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX09 ((0x0429 << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX10 ((0x042a << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX11 ((0x042b << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX12 ((0x042c << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX13 ((0x042d << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX14 ((0x042e << 2) + 0xfe006000) +#define MAILBOX_ACCESS_EN_MBOX15 ((0x042f << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX00 ((0x0430 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX01 ((0x0431 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX02 ((0x0432 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX03 ((0x0433 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX04 ((0x0434 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX05 ((0x0435 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX06 ((0x0436 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX07 ((0x0437 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX08 ((0x0438 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX09 ((0x0439 << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX10 ((0x043a << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX11 ((0x043b << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX12 ((0x043c << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX13 ((0x043d << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX14 ((0x043e << 2) + 0xfe006000) +#define MAILBOX_SET_MBOX15 ((0x043f << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX00 ((0x0440 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX01 ((0x0441 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX02 ((0x0442 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX03 ((0x0443 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX04 ((0x0444 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX05 ((0x0445 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX06 ((0x0446 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX07 ((0x0447 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX08 ((0x0448 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX09 ((0x0449 << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX10 ((0x044a << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX11 ((0x044b << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX12 ((0x044c << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX13 ((0x044d << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX14 ((0x044e << 2) + 0xfe006000) +#define MAILBOX_CLR_MBOX15 ((0x044f << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX00 ((0x0450 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX01 ((0x0451 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX02 ((0x0452 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX03 ((0x0453 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX04 ((0x0454 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX05 ((0x0455 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX06 ((0x0456 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX07 ((0x0457 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX08 ((0x0458 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX09 ((0x0459 << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX10 ((0x045a << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX11 ((0x045b << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX12 ((0x045c << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX13 ((0x045d << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX14 ((0x045e << 2) + 0xfe006000) +#define MAILBOX_STS_MBOX15 ((0x045f << 2) + 0xfe006000) +//======================================================================== +// IRQ_CTRL +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe00a000 +// ----------------------------------------------- +#define IRQCTRL_IRQ_INV0 ((0x0000 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_INV1 ((0x0001 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_INV2 ((0x0002 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_INV3 ((0x0003 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_INV4 ((0x0004 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_INV5 ((0x0005 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_INV6 ((0x0006 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_INV7 ((0x0007 << 2) + 0xfe00a000) +#define IRQCTRL_MASK0_GIC ((0x0010 << 2) + 0xfe00a000) +#define IRQCTRL_MASK1_GIC ((0x0011 << 2) + 0xfe00a000) +#define IRQCTRL_MASK2_GIC ((0x0012 << 2) + 0xfe00a000) +#define IRQCTRL_MASK3_GIC ((0x0013 << 2) + 0xfe00a000) +#define IRQCTRL_MASK4_GIC ((0x0014 << 2) + 0xfe00a000) +#define IRQCTRL_MASK5_GIC ((0x0015 << 2) + 0xfe00a000) +#define IRQCTRL_MASK6_GIC ((0x0016 << 2) + 0xfe00a000) +#define IRQCTRL_MASK7_GIC ((0x0017 << 2) + 0xfe00a000) +#define IRQCTRL_MASK0_DSP ((0x0020 << 2) + 0xfe00a000) +#define IRQCTRL_MASK1_DSP ((0x0021 << 2) + 0xfe00a000) +#define IRQCTRL_MASK2_DSP ((0x0022 << 2) + 0xfe00a000) +#define IRQCTRL_MASK3_DSP ((0x0023 << 2) + 0xfe00a000) +#define IRQCTRL_MASK4_DSP ((0x0024 << 2) + 0xfe00a000) +#define IRQCTRL_MASK5_DSP ((0x0025 << 2) + 0xfe00a000) +#define IRQCTRL_MASK6_DSP ((0x0026 << 2) + 0xfe00a000) +#define IRQCTRL_MASK7_DSP ((0x0027 << 2) + 0xfe00a000) +#define IRQCTRL_MASK0_PWRCTRL ((0x0030 << 2) + 0xfe00a000) +#define IRQCTRL_MASK1_PWRCTRL ((0x0031 << 2) + 0xfe00a000) +#define IRQCTRL_MASK2_PWRCTRL ((0x0032 << 2) + 0xfe00a000) +#define IRQCTRL_MASK3_PWRCTRL ((0x0033 << 2) + 0xfe00a000) +#define IRQCTRL_MASK4_PWRCTRL ((0x0034 << 2) + 0xfe00a000) +#define IRQCTRL_MASK5_PWRCTRL ((0x0035 << 2) + 0xfe00a000) +#define IRQCTRL_MASK6_PWRCTRL ((0x0036 << 2) + 0xfe00a000) +#define IRQCTRL_MASK7_PWRCTRL ((0x0037 << 2) + 0xfe00a000) +#define IRQCTRL_MASK0_AOCPU ((0x0040 << 2) + 0xfe00a000) +#define IRQCTRL_MASK1_AOCPU ((0x0041 << 2) + 0xfe00a000) +#define IRQCTRL_MASK2_AOCPU ((0x0042 << 2) + 0xfe00a000) +#define IRQCTRL_MASK3_AOCPU ((0x0043 << 2) + 0xfe00a000) +#define IRQCTRL_MASK4_AOCPU ((0x0044 << 2) + 0xfe00a000) +#define IRQCTRL_MASK5_AOCPU ((0x0045 << 2) + 0xfe00a000) +#define IRQCTRL_MASK6_AOCPU ((0x0046 << 2) + 0xfe00a000) +#define IRQCTRL_MASK7_AOCPU ((0x0047 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_MODE0 ((0x0050 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_MODE1 ((0x0051 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_MODE2 ((0x0052 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_MODE3 ((0x0053 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_MODE4 ((0x0054 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_MODE5 ((0x0055 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_MODE6 ((0x0056 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_MODE7 ((0x0057 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH0 ((0x0060 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH1 ((0x0061 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH2 ((0x0062 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH3 ((0x0063 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH4 ((0x0064 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH5 ((0x0065 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH6 ((0x0066 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH7 ((0x0067 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH_CLR0 ((0x0070 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH_CLR1 ((0x0071 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH_CLR2 ((0x0072 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH_CLR3 ((0x0073 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH_CLR4 ((0x0074 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH_CLR5 ((0x0075 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH_CLR6 ((0x0076 << 2) + 0xfe00a000) +#define IRQCTRL_IRQ_LATCH_CLR7 ((0x0077 << 2) + 0xfe00a000) +#define IRQCTRL_LOCK_BIT ((0x0080 << 2) + 0xfe00a000) +#define IRQCTRL_PROT_BIT ((0x0081 << 2) + 0xfe00a000) +//======================================================================== +// RESET_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe002000 +// ----------------------------------------------- +#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe002000) +#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe002000) +#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe002000) +#define RESETCTRL_RESET3 ((0x0003 << 2) + 0xfe002000) +#define RESETCTRL_RESET4 ((0x0004 << 2) + 0xfe002000) +#define RESETCTRL_RESET5 ((0x0005 << 2) + 0xfe002000) +#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe002000) +#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe002000) +#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe002000) +#define RESETCTRL_RESET3_LEVEL ((0x0013 << 2) + 0xfe002000) +#define RESETCTRL_RESET4_LEVEL ((0x0014 << 2) + 0xfe002000) +#define RESETCTRL_RESET5_LEVEL ((0x0015 << 2) + 0xfe002000) +#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe002000) +#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe002000) +#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe002000) +#define RESETCTRL_RESET3_MASK ((0x0023 << 2) + 0xfe002000) +#define RESETCTRL_RESET4_MASK ((0x0024 << 2) + 0xfe002000) +#define RESETCTRL_RESET5_MASK ((0x0025 << 2) + 0xfe002000) +#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe002000) +#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe002000) +#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe002000) +#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe002000) +#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe002000) +#define RESETCTRL_SEC_WATCHDOG_CTRL0 ((0x0044 << 2) + 0xfe002000) +#define RESETCTRL_SEC_WATCHDOG_CTRL1 ((0x0045 << 2) + 0xfe002000) +#define RESETCTRL_SEC_WATCHDOG_CNT ((0x0046 << 2) + 0xfe002000) +#define RESETCTRL_SEC_WATCHDOG_CLR ((0x0047 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET1 ((0x0051 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET0_LEVEL ((0x0060 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET1_LEVEL ((0x0061 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET0_MASK ((0x0070 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET1_MASK ((0x0071 << 2) + 0xfe002000) +#define RESETCTRL_RESET0_LOCK ((0x0080 << 2) + 0xfe002000) +#define RESETCTRL_RESET1_LOCK ((0x0081 << 2) + 0xfe002000) +#define RESETCTRL_RESET2_LOCK ((0x0082 << 2) + 0xfe002000) +#define RESETCTRL_RESET3_LOCK ((0x0083 << 2) + 0xfe002000) +#define RESETCTRL_RESET4_LOCK ((0x0084 << 2) + 0xfe002000) +#define RESETCTRL_RESET5_LOCK ((0x0085 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET0_LOCK ((0x0088 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET1_LOCK ((0x0089 << 2) + 0xfe002000) +#define RESETCTRL_RESET0_PROT ((0x0090 << 2) + 0xfe002000) +#define RESETCTRL_RESET1_PROT ((0x0091 << 2) + 0xfe002000) +#define RESETCTRL_RESET2_PROT ((0x0092 << 2) + 0xfe002000) +#define RESETCTRL_RESET3_PROT ((0x0093 << 2) + 0xfe002000) +#define RESETCTRL_RESET4_PROT ((0x0094 << 2) + 0xfe002000) +#define RESETCTRL_RESET5_PROT ((0x0095 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET0_PROT ((0x0098 << 2) + 0xfe002000) +#define RESETCTRL_SEC_RESET1_PROT ((0x0099 << 2) + 0xfe002000) +//======================================================================== +// CPU_CTRL +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe00e000 +// ----------------------------------------------- +#define CPUCTRL_SYS_CPU_RESET_CNTL ((0x0050 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CLK_CTRL ((0x0051 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CLK_CTRL1 ((0x0052 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CLK_CTRL2 ((0x0053 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CLK_CTRL3 ((0x0054 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CLK_CTRL4 ((0x0055 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CLK_CTRL5 ((0x0056 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CLK_CTRL6 ((0x0057 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CLK_RESULT ((0x0058 << 2) + 0xfe00e000) +#define CPUCTRL_ROM_DISABLE ((0x0060 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_POR_CFG0 ((0x0090 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_POR_CFG1 ((0x0091 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG0 ((0x0092 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG1 ((0x0093 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG2 ((0x0094 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG3 ((0x0095 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG4 ((0x0096 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG5 ((0x0097 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG6 ((0x0098 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG7 ((0x0099 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG8 ((0x009a << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG9 ((0x009b << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG10 ((0x009c << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG11 ((0x009d << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG12 ((0x009e << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_CFG13 ((0x009f << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_STATUS0 ((0x00a0 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_STATUS1 ((0x00a1 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_STATUS2 ((0x00a2 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_STATUS3 ((0x00a3 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_STATUS4 ((0x00a4 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_STATUS5 ((0x00a5 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_STATUS6 ((0x00a6 << 2) + 0xfe00e000) +#define CPUCTRL_SYS_CPU_STATUS7 ((0x00a7 << 2) + 0xfe00e000) +//======================================================================== +// SAR_ADC +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe026000 +// ----------------------------------------------- +#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe026000) +#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe026000) +#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe026000) +#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe026000) +#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe026000) +#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe026000) +#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe026000) +#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe026000) +#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe026000) +#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe026000) +#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe026000) +#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe026000) +#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe026000) +#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe026000) +#define SAR_ADC_CHNL01 ((0x000e << 2) + 0xfe026000) +#define SAR_ADC_CHNL23 ((0x000f << 2) + 0xfe026000) +#define SAR_ADC_CHNL45 ((0x0010 << 2) + 0xfe026000) +#define SAR_ADC_CHNL67 ((0x0011 << 2) + 0xfe026000) +//======================================================================== +// ANA_CTRL - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 +// ----------------------------------------------- +#define ANACTRL_SYSPLL_CTRL0 ((0x0000 << 2) + 0xfe008000) +#define ANACTRL_SYSPLL_CTRL1 ((0x0001 << 2) + 0xfe008000) +#define ANACTRL_SYSPLL_CTRL2 ((0x0002 << 2) + 0xfe008000) +#define ANACTRL_SYSPLL_CTRL3 ((0x0003 << 2) + 0xfe008000) +#define ANACTRL_SYSPLL_CTRL4 ((0x0004 << 2) + 0xfe008000) +#define ANACTRL_SYSPLL_CTRL5 ((0x0005 << 2) + 0xfe008000) +#define ANACTRL_SYSPLL_CTRL6 ((0x0006 << 2) + 0xfe008000) +#define ANACTRL_SYSPLL_STS ((0x0007 << 2) + 0xfe008000) +#define ANACTRL_FIXPLL_CTRL0 ((0x0010 << 2) + 0xfe008000) +#define ANACTRL_FIXPLL_CTRL1 ((0x0011 << 2) + 0xfe008000) +#define ANACTRL_FIXPLL_CTRL2 ((0x0012 << 2) + 0xfe008000) +#define ANACTRL_FIXPLL_CTRL3 ((0x0013 << 2) + 0xfe008000) +#define ANACTRL_FIXPLL_CTRL4 ((0x0014 << 2) + 0xfe008000) +#define ANACTRL_FIXPLL_CTRL5 ((0x0015 << 2) + 0xfe008000) +#define ANACTRL_FIXPLL_CTRL6 ((0x0016 << 2) + 0xfe008000) +#define ANACTRL_FIXPLL_STS ((0x0017 << 2) + 0xfe008000) +#define ANACTRL_GP0PLL_CTRL0 ((0x0020 << 2) + 0xfe008000) +#define ANACTRL_GP0PLL_CTRL1 ((0x0021 << 2) + 0xfe008000) +#define ANACTRL_GP0PLL_CTRL2 ((0x0022 << 2) + 0xfe008000) +#define ANACTRL_GP0PLL_CTRL3 ((0x0023 << 2) + 0xfe008000) +#define ANACTRL_GP0PLL_CTRL4 ((0x0024 << 2) + 0xfe008000) +#define ANACTRL_GP0PLL_CTRL5 ((0x0025 << 2) + 0xfe008000) +#define ANACTRL_GP0PLL_CTRL6 ((0x0026 << 2) + 0xfe008000) +#define ANACTRL_GP0PLL_STS ((0x0027 << 2) + 0xfe008000) +#define ANACTRL_GP1PLL_CTRL0 ((0x0030 << 2) + 0xfe008000) +#define ANACTRL_GP1PLL_CTRL1 ((0x0031 << 2) + 0xfe008000) +#define ANACTRL_GP1PLL_CTRL2 ((0x0032 << 2) + 0xfe008000) +#define ANACTRL_GP1PLL_CTRL3 ((0x0033 << 2) + 0xfe008000) +#define ANACTRL_GP1PLL_CTRL4 ((0x0034 << 2) + 0xfe008000) +#define ANACTRL_GP1PLL_CTRL5 ((0x0035 << 2) + 0xfe008000) +#define ANACTRL_GP1PLL_CTRL6 ((0x0036 << 2) + 0xfe008000) +#define ANACTRL_GP1PLL_STS ((0x0037 << 2) + 0xfe008000) +#define ANACTRL_HIFIPLL_CTRL0 ((0x0040 << 2) + 0xfe008000) +#define ANACTRL_HIFIPLL_CTRL1 ((0x0041 << 2) + 0xfe008000) +#define ANACTRL_HIFIPLL_CTRL2 ((0x0042 << 2) + 0xfe008000) +#define ANACTRL_HIFIPLL_CTRL3 ((0x0043 << 2) + 0xfe008000) +#define ANACTRL_HIFIPLL_CTRL4 ((0x0044 << 2) + 0xfe008000) +#define ANACTRL_HIFIPLL_CTRL5 ((0x0045 << 2) + 0xfe008000) +#define ANACTRL_HIFIPLL_CTRL6 ((0x0046 << 2) + 0xfe008000) +#define ANACTRL_HIFIPLL_STS ((0x0047 << 2) + 0xfe008000) +#define ANACTRL_PCIEPLL_CTRL0 ((0x0050 << 2) + 0xfe008000) +#define ANACTRL_PCIEPLL_CTRL1 ((0x0051 << 2) + 0xfe008000) +#define ANACTRL_PCIEPLL_CTRL2 ((0x0052 << 2) + 0xfe008000) +#define ANACTRL_PCIEPLL_CTRL3 ((0x0053 << 2) + 0xfe008000) +#define ANACTRL_PCIEPLL_CTRL4 ((0x0054 << 2) + 0xfe008000) +#define ANACTRL_PCIEPLL_CTRL5 ((0x0055 << 2) + 0xfe008000) +#define ANACTRL_PCIEPLL_STS ((0x0056 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL0 ((0x0060 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL1 ((0x0061 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL2 ((0x0062 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL3 ((0x0063 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL4 ((0x0064 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL5 ((0x0065 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL6 ((0x0066 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL7 ((0x0067 << 2) + 0xfe008000) +#define ANACTRL_MPLL_CTRL8 ((0x0068 << 2) + 0xfe008000) +#define ANACTRL_MPLL_STS ((0x0069 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_CTRL0 ((0x0070 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_CTRL1 ((0x0071 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_CTRL2 ((0x0072 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_CTRL3 ((0x0073 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_CTRL4 ((0x0074 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_CTRL5 ((0x0075 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_CTRL6 ((0x0076 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_STS ((0x0077 << 2) + 0xfe008000) +#define ANACTRL_HDMIPLL_VLOCK ((0x0079 << 2) + 0xfe008000) +#define ANACTRL_HDMIPHY_CTRL0 ((0x0080 << 2) + 0xfe008000) +#define ANACTRL_HDMIPHY_CTRL1 ((0x0081 << 2) + 0xfe008000) +#define ANACTRL_HDMIPHY_CTRL2 ((0x0082 << 2) + 0xfe008000) +#define ANACTRL_HDMIPHY_CTRL3 ((0x0083 << 2) + 0xfe008000) +#define ANACTRL_HDMIPHY_CTRL4 ((0x0084 << 2) + 0xfe008000) +#define ANACTRL_HDMIPHY_CTRL5 ((0x0085 << 2) + 0xfe008000) +#define ANACTRL_HDMIPHY_STS ((0x0086 << 2) + 0xfe008000) +#define ANACTRL_MIPICSI_CTRL0 ((0x0090 << 2) + 0xfe008000) +#define ANACTRL_MIPICSI_CTRL1 ((0x0091 << 2) + 0xfe008000) +#define ANACTRL_MIPICSI_CTRL2 ((0x0092 << 2) + 0xfe008000) +#define ANACTRL_MIPICSI_CTRL3 ((0x0093 << 2) + 0xfe008000) +#define ANACTRL_MIPICSI_CTRL4 ((0x0094 << 2) + 0xfe008000) +#define ANACTRL_MIPICSI_CTRL5 ((0x0095 << 2) + 0xfe008000) +#define ANACTRL_MIPIDSI_CTRL0 ((0x00a0 << 2) + 0xfe008000) +#define ANACTRL_MIPIDSI_CTRL1 ((0x00a1 << 2) + 0xfe008000) +#define ANACTRL_MIPIDSI_CTRL2 ((0x00a2 << 2) + 0xfe008000) +#define ANACTRL_MIPIDSI_STS ((0x00a3 << 2) + 0xfe008000) +#define ANACTRL_VDAC_CTRL0 ((0x00b0 << 2) + 0xfe008000) +#define ANACTRL_VDAC_CTRL1 ((0x00b1 << 2) + 0xfe008000) +#define ANACTRL_POR_CTRL ((0x00b6 << 2) + 0xfe008000) +#define ANACTRL_LOCK_BIT ((0x00b8 << 2) + 0xfe008000) +#define ANACTRL_PROT_BIT ((0x00b9 << 2) + 0xfe008000) +//======================================================================== +// Ethernet Phy +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe028000 +// ----------------------------------------------- +#define ETH_PHY_DBG_CTL0 ((0x0000 << 2) + 0xfe028000) +#define ETH_PHY_DBG_CTL1 ((0x0001 << 2) + 0xfe028000) +#define ETH_PHY_DBG_CFG0 ((0x0002 << 2) + 0xfe028000) +#define ETH_PHY_DBG_CFG1 ((0x0003 << 2) + 0xfe028000) +#define ETH_PHY_DBG_CFG2 ((0x0004 << 2) + 0xfe028000) +#define ETH_PHY_DBG_CFG3 ((0x0005 << 2) + 0xfe028000) +#define ETH_PHY_DBG_CFG4 ((0x0006 << 2) + 0xfe028000) +#define ETH_PLL_STS ((0x0010 << 2) + 0xfe028000) +#define ETH_PLL_CTL0 ((0x0011 << 2) + 0xfe028000) +#define ETH_PLL_CTL1 ((0x0012 << 2) + 0xfe028000) +#define ETH_PLL_CTL2 ((0x0013 << 2) + 0xfe028000) +#define ETH_PLL_CTL3 ((0x0014 << 2) + 0xfe028000) +#define ETH_PLL_CTL4 ((0x0015 << 2) + 0xfe028000) +#define ETH_PLL_CTL5 ((0x0016 << 2) + 0xfe028000) +#define ETH_PLL_CTL6 ((0x0017 << 2) + 0xfe028000) +#define ETH_PLL_CTL7 ((0x0018 << 2) + 0xfe028000) +#define ETH_PHY_CNTL0 ((0x0020 << 2) + 0xfe028000) +#define ETH_PHY_CNTL1 ((0x0021 << 2) + 0xfe028000) +#define ETH_PHY_CNTL2 ((0x0022 << 2) + 0xfe028000) +#define ETH_PHY_CNTL3 ((0x0023 << 2) + 0xfe028000) +#define ETH_PHY_STS0 ((0x0025 << 2) + 0xfe028000) +#define ETH_PHY_STS1 ((0x0026 << 2) + 0xfe028000) +#define ETH_PHY_STS2 ((0x0027 << 2) + 0xfe028000) +#define ETH_PHY_DBG_REG ((0x0028 << 2) + 0xfe028000) +//======================================================================== +// Ethernet TOP +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe024000 +// ----------------------------------------------- +#define ETHTOP_CNTL0 ((0x0000 << 2) + 0xfe024000) +#define ETHTOP_CNTL1 ((0x0001 << 2) + 0xfe024000) +//======================================================================== +// I2C Slave A +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe064000 +// ----------------------------------------------- +#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe064000) +#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe064000) +#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe064000) +#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe064000) +//======================================================================== +// IR RX/TX +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe084000 +// ----------------------------------------------- +#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe084000) +#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe084000) +#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe084000) +#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe084000) +#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe084000) +#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe084000) +#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe084000) +//======================================================================== +// I2C Master A +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe066000 +// ----------------------------------------------- +#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe066000) +#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe066000) +#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe066000) +#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe066000) +#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe066000) +#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe066000) +#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe066000) +#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe066000) +#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe066000) +#define I2C_M_A_CNTL_DELY1 ((0x0009 << 2) + 0xfe066000) +#define I2C_M_A_CNTL_DELY2 ((0x000a << 2) + 0xfe066000) +#define I2C_M_A_LOW_DELY ((0x000b << 2) + 0xfe066000) +#define I2C_M_A_HIGH_DELY ((0x000c << 2) + 0xfe066000) +#define I2C_M_A_FIFO_CTRL_REG ((0x000d << 2) + 0xfe066000) +#define I2C_M_A_STATE_REG ((0x000e << 2) + 0xfe066000) +//======================================================================== +// I2C Master B +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe068000 +// ----------------------------------------------- +#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe068000) +#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe068000) +#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe068000) +#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe068000) +#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe068000) +#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe068000) +#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe068000) +#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe068000) +#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe068000) +#define I2C_M_B_CNTL_DELY1 ((0x0009 << 2) + 0xfe068000) +#define I2C_M_B_CNTL_DELY2 ((0x000a << 2) + 0xfe068000) +#define I2C_M_B_LOW_DELY ((0x000b << 2) + 0xfe068000) +#define I2C_M_B_HIGH_DELY ((0x000c << 2) + 0xfe068000) +#define I2C_M_B_FIFO_CTRL_REG ((0x000d << 2) + 0xfe068000) +#define I2C_M_B_STATE_REG ((0x000e << 2) + 0xfe068000) +//======================================================================== +// I2C Master C +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe06a000 +// ----------------------------------------------- +#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe06a000) +#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe06a000) +#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06a000) +#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06a000) +#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe06a000) +#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe06a000) +#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe06a000) +#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe06a000) +#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe06a000) +#define I2C_M_C_CNTL_DELY1 ((0x0009 << 2) + 0xfe06a000) +#define I2C_M_C_CNTL_DELY2 ((0x000a << 2) + 0xfe06a000) +#define I2C_M_C_LOW_DELY ((0x000b << 2) + 0xfe06a000) +#define I2C_M_C_HIGH_DELY ((0x000c << 2) + 0xfe06a000) +#define I2C_M_C_FIFO_CTRL_REG ((0x000d << 2) + 0xfe06a000) +#define I2C_M_C_STATE_REG ((0x000e << 2) + 0xfe06a000) +//======================================================================== +// I2C Master D +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe06c000 +// ----------------------------------------------- +#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe06c000) +#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe06c000) +#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06c000) +#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06c000) +#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe06c000) +#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe06c000) +#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe06c000) +#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe06c000) +#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe06c000) +#define I2C_M_D_CNTL_DELY1 ((0x0009 << 2) + 0xfe06c000) +#define I2C_M_D_CNTL_DELY2 ((0x000a << 2) + 0xfe06c000) +#define I2C_M_D_LOW_DELY ((0x000b << 2) + 0xfe06c000) +#define I2C_M_D_HIGH_DELY ((0x000c << 2) + 0xfe06c000) +#define I2C_M_D_FIFO_CTRL_REG ((0x000d << 2) + 0xfe06c000) +#define I2C_M_D_STATE_REG ((0x000e << 2) + 0xfe06c000) +//======================================================================== +// I2C Master E +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe06e000 +// ----------------------------------------------- +#define I2C_M_E_CONTROL_REG ((0x0000 << 2) + 0xfe06e000) +#define I2C_M_E_SLAVE_ADDR ((0x0001 << 2) + 0xfe06e000) +#define I2C_M_E_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06e000) +#define I2C_M_E_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06e000) +#define I2C_M_E_WDATA_REG0 ((0x0004 << 2) + 0xfe06e000) +#define I2C_M_E_WDATA_REG1 ((0x0005 << 2) + 0xfe06e000) +#define I2C_M_E_RDATA_REG0 ((0x0006 << 2) + 0xfe06e000) +#define I2C_M_E_RDATA_REG1 ((0x0007 << 2) + 0xfe06e000) +#define I2C_M_E_TIMEOUT_TH ((0x0008 << 2) + 0xfe06e000) +#define I2C_M_E_CNTL_DELY1 ((0x0009 << 2) + 0xfe06e000) +#define I2C_M_E_CNTL_DELY2 ((0x000a << 2) + 0xfe06e000) +#define I2C_M_E_LOW_DELY ((0x000b << 2) + 0xfe06e000) +#define I2C_M_E_HIGH_DELY ((0x000c << 2) + 0xfe06e000) +#define I2C_M_E_FIFO_CTRL_REG ((0x000d << 2) + 0xfe06e000) +#define I2C_M_E_STATE_REG ((0x000e << 2) + 0xfe06e000) +//======================================================================== +// I2C Master F +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe070000 +// ----------------------------------------------- +#define I2C_M_F_CONTROL_REG ((0x0000 << 2) + 0xfe070000) +#define I2C_M_F_SLAVE_ADDR ((0x0001 << 2) + 0xfe070000) +#define I2C_M_F_TOKEN_LIST0 ((0x0002 << 2) + 0xfe070000) +#define I2C_M_F_TOKEN_LIST1 ((0x0003 << 2) + 0xfe070000) +#define I2C_M_F_WDATA_REG0 ((0x0004 << 2) + 0xfe070000) +#define I2C_M_F_WDATA_REG1 ((0x0005 << 2) + 0xfe070000) +#define I2C_M_F_RDATA_REG0 ((0x0006 << 2) + 0xfe070000) +#define I2C_M_F_RDATA_REG1 ((0x0007 << 2) + 0xfe070000) +#define I2C_M_F_TIMEOUT_TH ((0x0008 << 2) + 0xfe070000) +#define I2C_M_F_CNTL_DELY1 ((0x0009 << 2) + 0xfe070000) +#define I2C_M_F_CNTL_DELY2 ((0x000a << 2) + 0xfe070000) +#define I2C_M_F_LOW_DELY ((0x000b << 2) + 0xfe070000) +#define I2C_M_F_HIGH_DELY ((0x000c << 2) + 0xfe070000) +#define I2C_M_F_FIFO_CTRL_REG ((0x000d << 2) + 0xfe070000) +#define I2C_M_F_STATE_REG ((0x000e << 2) + 0xfe070000) +//======================================================================== +// APB0_UART_A - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe078000 +// ----------------------------------------------- +#define UART_A_WFIFO ((0x0000 << 2) + 0xfe078000) +#define UART_A_RFIFO ((0x0001 << 2) + 0xfe078000) +#define UART_A_CONTROL ((0x0002 << 2) + 0xfe078000) +#define UART_A_STATUS ((0x0003 << 2) + 0xfe078000) +#define UART_A_MISC ((0x0004 << 2) + 0xfe078000) +#define UART_A_REG5 ((0x0005 << 2) + 0xfe078000) +//======================================================================== +// APB0_UART_B - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe07a000 +// ----------------------------------------------- +#define UART_B_WFIFO ((0x0000 << 2) + 0xfe07a000) +#define UART_B_RFIFO ((0x0001 << 2) + 0xfe07a000) +#define UART_B_CONTROL ((0x0002 << 2) + 0xfe07a000) +#define UART_B_STATUS ((0x0003 << 2) + 0xfe07a000) +#define UART_B_MISC ((0x0004 << 2) + 0xfe07a000) +#define UART_B_REG5 ((0x0005 << 2) + 0xfe07a000) +//======================================================================== +// APB0_UART_C - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe07c000 +// ----------------------------------------------- +#define UART_C_WFIFO ((0x0000 << 2) + 0xfe07c000) +#define UART_C_RFIFO ((0x0001 << 2) + 0xfe07c000) +#define UART_C_CONTROL ((0x0002 << 2) + 0xfe07c000) +#define UART_C_STATUS ((0x0003 << 2) + 0xfe07c000) +#define UART_C_MISC ((0x0004 << 2) + 0xfe07c000) +#define UART_C_REG5 ((0x0005 << 2) + 0xfe07c000) +//======================================================================== +// APB0_UART_D - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe07e000 +// ----------------------------------------------- +#define UART_D_WFIFO ((0x0000 << 2) + 0xfe07e000) +#define UART_D_RFIFO ((0x0001 << 2) + 0xfe07e000) +#define UART_D_CONTROL ((0x0002 << 2) + 0xfe07e000) +#define UART_D_STATUS ((0x0003 << 2) + 0xfe07e000) +#define UART_D_MISC ((0x0004 << 2) + 0xfe07e000) +#define UART_D_REG5 ((0x0005 << 2) + 0xfe07e000) +//======================================================================== +// APB0_UART_E - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe080000 +// ----------------------------------------------- +#define UART_E_WFIFO ((0x0000 << 2) + 0xfe080000) +#define UART_E_RFIFO ((0x0001 << 2) + 0xfe080000) +#define UART_E_CONTROL ((0x0002 << 2) + 0xfe080000) +#define UART_E_STATUS ((0x0003 << 2) + 0xfe080000) +#define UART_E_MISC ((0x0004 << 2) + 0xfe080000) +#define UART_E_REG5 ((0x0005 << 2) + 0xfe080000) +//======================================================================== +// PWM_AB - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe058000 +// ----------------------------------------------- +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe058000) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe058000) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe058000) +#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe058000) +#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe058000) +#define PWMAB_A2 ((0x0005 << 2) + 0xfe058000) +#define PWMAB_B2 ((0x0006 << 2) + 0xfe058000) +#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe058000) +#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe058000) +//======================================================================== +// PWM_CD - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe05a000 +// ----------------------------------------------- +#define PWMCD_PWM_A ((0x0000 << 2) + 0xfe05a000) +#define PWMCD_PWM_B ((0x0001 << 2) + 0xfe05a000) +#define PWMCD_MISC_REG_AB ((0x0002 << 2) + 0xfe05a000) +#define PWMCD_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05a000) +#define PWMCD_TIME_AB ((0x0004 << 2) + 0xfe05a000) +#define PWMCD_A2 ((0x0005 << 2) + 0xfe05a000) +#define PWMCD_B2 ((0x0006 << 2) + 0xfe05a000) +#define PWMCD_BLINK_AB ((0x0007 << 2) + 0xfe05a000) +#define PWMCD_LOCK_AB ((0x0008 << 2) + 0xfe05a000) +//======================================================================== +// PWM_EF - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe05c000 +// ----------------------------------------------- +#define PWMEF_PWM_A ((0x0000 << 2) + 0xfe05c000) +#define PWMEF_PWM_B ((0x0001 << 2) + 0xfe05c000) +#define PWMEF_MISC_REG_AB ((0x0002 << 2) + 0xfe05c000) +#define PWMEF_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05c000) +#define PWMEF_TIME_AB ((0x0004 << 2) + 0xfe05c000) +#define PWMEF_A2 ((0x0005 << 2) + 0xfe05c000) +#define PWMEF_B2 ((0x0006 << 2) + 0xfe05c000) +#define PWMEF_BLINK_AB ((0x0007 << 2) + 0xfe05c000) +#define PWMEF_LOCK_AB ((0x0008 << 2) + 0xfe05c000) +//======================================================================== +// PWM_GH - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe05e000 +// ----------------------------------------------- +#define PWMGH_PWM_A ((0x0000 << 2) + 0xfe05e000) +#define PWMGH_PWM_B ((0x0001 << 2) + 0xfe05e000) +#define PWMGH_MISC_REG_AB ((0x0002 << 2) + 0xfe05e000) +#define PWMGH_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05e000) +#define PWMGH_TIME_AB ((0x0004 << 2) + 0xfe05e000) +#define PWMGH_A2 ((0x0005 << 2) + 0xfe05e000) +#define PWMGH_B2 ((0x0006 << 2) + 0xfe05e000) +#define PWMGH_BLINK_AB ((0x0007 << 2) + 0xfe05e000) +#define PWMGH_LOCK_AB ((0x0008 << 2) + 0xfe05e000) +//======================================================================== +// PWM_IJ - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe060000 +// ----------------------------------------------- +#define PWMIJ_PWM_A ((0x0000 << 2) + 0xfe060000) +#define PWMIJ_PWM_B ((0x0001 << 2) + 0xfe060000) +#define PWMIJ_MISC_REG_AB ((0x0002 << 2) + 0xfe060000) +#define PWMIJ_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe060000) +#define PWMIJ_TIME_AB ((0x0004 << 2) + 0xfe060000) +#define PWMIJ_A2 ((0x0005 << 2) + 0xfe060000) +#define PWMIJ_B2 ((0x0006 << 2) + 0xfe060000) +#define PWMIJ_BLINK_AB ((0x0007 << 2) + 0xfe060000) +#define PWMIJ_LOCK_AB ((0x0008 << 2) + 0xfe060000) +//======================================================================== +// SPICC_0 +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe050000 +// ----------------------------------------------- +#define SPICC0_RXDATA ((0x0000 << 2) + 0xfe050000) +#define SPICC0_TXDATA ((0x0001 << 2) + 0xfe050000) +#define SPICC0_CONREG ((0x0002 << 2) + 0xfe050000) +#define SPICC0_INTREG ((0x0003 << 2) + 0xfe050000) +#define SPICC0_DMAREG ((0x0004 << 2) + 0xfe050000) +#define SPICC0_STATREG ((0x0005 << 2) + 0xfe050000) +#define SPICC0_PERIODREG ((0x0006 << 2) + 0xfe050000) +#define SPICC0_TESTREG ((0x0007 << 2) + 0xfe050000) +#define SPICC0_DRADDR ((0x0008 << 2) + 0xfe050000) +#define SPICC0_DWADDR ((0x0009 << 2) + 0xfe050000) +#define SPICC0_LD_CNTL0 ((0x000a << 2) + 0xfe050000) +#define SPICC0_LD_CNTL1 ((0x000b << 2) + 0xfe050000) +#define SPICC0_LD_RADDR ((0x000c << 2) + 0xfe050000) +#define SPICC0_LD_WADDR ((0x000d << 2) + 0xfe050000) +#define SPICC0_ENHANCE_CNTL ((0x000e << 2) + 0xfe050000) +#define SPICC0_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe050000) +#define SPICC0_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe050000) +//======================================================================== +// SPICC_1 +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe052000 +// ----------------------------------------------- +#define SPICC1_RXDATA ((0x0000 << 2) + 0xfe052000) +#define SPICC1_TXDATA ((0x0001 << 2) + 0xfe052000) +#define SPICC1_CONREG ((0x0002 << 2) + 0xfe052000) +#define SPICC1_INTREG ((0x0003 << 2) + 0xfe052000) +#define SPICC1_DMAREG ((0x0004 << 2) + 0xfe052000) +#define SPICC1_STATREG ((0x0005 << 2) + 0xfe052000) +#define SPICC1_PERIODREG ((0x0006 << 2) + 0xfe052000) +#define SPICC1_TESTREG ((0x0007 << 2) + 0xfe052000) +#define SPICC1_DRADDR ((0x0008 << 2) + 0xfe052000) +#define SPICC1_DWADDR ((0x0009 << 2) + 0xfe052000) +#define SPICC1_LD_CNTL0 ((0x000a << 2) + 0xfe052000) +#define SPICC1_LD_CNTL1 ((0x000b << 2) + 0xfe052000) +#define SPICC1_LD_RADDR ((0x000c << 2) + 0xfe052000) +#define SPICC1_LD_WADDR ((0x000d << 2) + 0xfe052000) +#define SPICC1_ENHANCE_CNTL ((0x000e << 2) + 0xfe052000) +#define SPICC1_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe052000) +#define SPICC1_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe052000) +//======================================================================== +// AIFIFO - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe046000 +// ----------------------------------------------- +#define AIU_AIFIFO_CTRL ((0x0000 << 2) + 0xfe046000) +#define AIU_AIFIFO_STATUS ((0x0001 << 2) + 0xfe046000) +#define AIU_AIFIFO_GBIT ((0x0002 << 2) + 0xfe046000) +#define AIU_AIFIFO_CLB ((0x0003 << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_START_PTR ((0x0004 << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_CURR_PTR ((0x0005 << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_END_PTR ((0x0006 << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_BYTES_AVAIL ((0x0007 << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_CONTROL ((0x0008 << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_MAN_WP ((0x0009 << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_MAN_RP ((0x000a << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_LEVEL ((0x000b << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_BUF_CNTL ((0x000c << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT ((0x000d << 2) + 0xfe046000) +#define AIU_MEM_AIFIFO_MEM_CTL ((0x000f << 2) + 0xfe046000) +#define AIFIFO_TIME_STAMP_CNTL ((0x0010 << 2) + 0xfe046000) +#define AIFIFO_TIME_STAMP_SYNC_0 ((0x0011 << 2) + 0xfe046000) +#define AIFIFO_TIME_STAMP_SYNC_1 ((0x0012 << 2) + 0xfe046000) +#define AIFIFO_TIME_STAMP_0 ((0x0013 << 2) + 0xfe046000) +#define AIFIFO_TIME_STAMP_1 ((0x0014 << 2) + 0xfe046000) +#define AIFIFO_TIME_STAMP_2 ((0x0015 << 2) + 0xfe046000) +#define AIFIFO_TIME_STAMP_3 ((0x0016 << 2) + 0xfe046000) +#define AIFIFO_TIME_STAMP_LENGTH ((0x0017 << 2) + 0xfe046000) +//======================================================================== +// MSR_CLK - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe048000 +// ----------------------------------------------- +#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe048000) +#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe048000) +#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe048000) +#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe048000) +#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe048000) +#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe048000) +#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe048000) +//======================================================================== +// SPIFC - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe056000 +// ----------------------------------------------- +#define SPI_FLASH_CMD ((0x0000 << 2) + 0xfe056000) + // SPI_FLASH_READ 31 + // SPI_FLASH_WREN 30 + // SPI_FLASH_WRDI 29 + // SPI_FLASH_RDID 28 + // SPI_FLASH_RDSR 27 + // SPI_FLASH_WRSR 26 + // SPI_FLASH_PP 25 + // SPI_FLASH_SE 24 + // SPI_FLASH_BE 23 + // SPI_FLASH_CE 22 + // SPI_FLASH_DP 21 + // SPI_FLASH_RES 20 + // SPI_HPM 19 + // SPI_FLASH_USR 18 + // SPI_FLASH_USR_ADDR 15 + // SPI_FLASH_USR_DUMMY 14 + // SPI_FLASH_USR_DIN 13 + // SPI_FLASH_USR_DOUT 12 + // SPI_FLASH_USR_DUMMY_BLEN 10 + // SPI_FLASH_USR_CMD 0 +#define SPI_FLASH_ADDR ((0x0001 << 2) + 0xfe056000) + // SPI_FLASH_BYTES_LEN 24 + // SPI_FLASH_ADDR_START 0 +#define SPI_FLASH_CTRL ((0x0002 << 2) + 0xfe056000) + // SPI_ENABLE_AHB 17 + // SPI_SST_AAI 16 + // SPI_RES_RID 15 + // SPI_FREAD_DUAL 14 + // SPI_READ_READ_EN 13 + // SPI_CLK_DIV0 12 + // SPI_CLKCNT_N 8 + // SPI_CLKCNT_H 4 + // SPI_CLKCNT_L 0 +#define SPI_FLASH_CTRL1 ((0x0003 << 2) + 0xfe056000) +#define SPI_FLASH_STATUS ((0x0004 << 2) + 0xfe056000) +#define SPI_FLASH_CTRL2 ((0x0005 << 2) + 0xfe056000) +#define SPI_FLASH_CLOCK ((0x0006 << 2) + 0xfe056000) +#define SPI_FLASH_USER ((0x0007 << 2) + 0xfe056000) +#define SPI_FLASH_USER1 ((0x0008 << 2) + 0xfe056000) +#define SPI_FLASH_USER2 ((0x0009 << 2) + 0xfe056000) +#define SPI_FLASH_USER3 ((0x000a << 2) + 0xfe056000) +#define SPI_FLASH_USER4 ((0x000b << 2) + 0xfe056000) +#define SPI_FLASH_SLAVE ((0x000c << 2) + 0xfe056000) +#define SPI_FLASH_SLAVE1 ((0x000d << 2) + 0xfe056000) +#define SPI_FLASH_SLAVE2 ((0x000e << 2) + 0xfe056000) +#define SPI_FLASH_SLAVE3 ((0x000f << 2) + 0xfe056000) +#define SPI_FLASH_C0 ((0x0010 << 2) + 0xfe056000) +#define SPI_FLASH_C1 ((0x0011 << 2) + 0xfe056000) +#define SPI_FLASH_C2 ((0x0012 << 2) + 0xfe056000) +#define SPI_FLASH_C3 ((0x0013 << 2) + 0xfe056000) +#define SPI_FLASH_C4 ((0x0014 << 2) + 0xfe056000) +#define SPI_FLASH_C5 ((0x0015 << 2) + 0xfe056000) +#define SPI_FLASH_C6 ((0x0016 << 2) + 0xfe056000) +#define SPI_FLASH_C7 ((0x0017 << 2) + 0xfe056000) +#define SPI_FLASH_B8 ((0x0018 << 2) + 0xfe056000) +#define SPI_FLASH_B9 ((0x0019 << 2) + 0xfe056000) +#define SPI_FLASH_B10 ((0x001a << 2) + 0xfe056000) +#define SPI_FLASH_B11 ((0x001b << 2) + 0xfe056000) +#define SPI_FLASH_B12 ((0x001c << 2) + 0xfe056000) +#define SPI_FLASH_B13 ((0x001d << 2) + 0xfe056000) +#define SPI_FLASH_B14 ((0x001e << 2) + 0xfe056000) +#define SPI_FLASH_B15 ((0x001f << 2) + 0xfe056000) +//======================================================================== +// CEC - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe044000 +// ----------------------------------------------- +#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe044000) +#define CECA_RW_REG ((0x0001 << 2) + 0xfe044000) +#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe044000) +#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe044000) +#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe044000) +#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe044000) +#define CECB_RW_REG ((0x0011 << 2) + 0xfe044000) +#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe044000) +#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe044000) +#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe044000) +//======================================================================== +// SMART CARD - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe038000 +// ----------------------------------------------- +#define SMARTCARD_REG0 ((0x0000 << 2) + 0xfe038000) +#define SMARTCARD_REG1 ((0x0001 << 2) + 0xfe038000) +#define SMARTCARD_REG2 ((0x0002 << 2) + 0xfe038000) +#define SMARTCARD_STATUS ((0x0003 << 2) + 0xfe038000) +#define SMARTCARD_INTR ((0x0004 << 2) + 0xfe038000) +#define SMARTCARD_REG5 ((0x0005 << 2) + 0xfe038000) +#define SMARTCARD_REG6 ((0x0006 << 2) + 0xfe038000) +#define SMARTCARD_FIFO ((0x0007 << 2) + 0xfe038000) +#define SMARTCARD_REG8 ((0x0008 << 2) + 0xfe038000) +//======================================================================== +// CAPU +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe012000 +// ----------------------------------------------- +#define CAPU_ACCESS_EN_AHB_ETH ((0x00c2 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_AHB_USB0 ((0x00c1 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_AHB_USB1 ((0x00c0 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_16M_SLOT0 ((0x00b0 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_256K_SLOT1 ((0x00a1 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_256K_SLOT0 ((0x00a0 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_64K_SLOT5 ((0x0085 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_64K_SLOT4 ((0x0084 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_64K_SLOT3 ((0x0083 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_64K_SLOT2 ((0x0082 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_64K_SLOT1 ((0x0081 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_64K_SLOT0 ((0x0080 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT4F ((0x004f << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT4E ((0x004e << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT4D ((0x004d << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT4C ((0x004c << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT4B ((0x004b << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT4A ((0x004a << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT49 ((0x0049 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT48 ((0x0048 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT47 ((0x0047 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT46 ((0x0046 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT45 ((0x0045 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT44 ((0x0044 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT43 ((0x0043 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT42 ((0x0042 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT41 ((0x0041 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT40 ((0x0040 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT3F ((0x003f << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT3E ((0x003e << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT3D ((0x003d << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT3C ((0x003c << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT3B ((0x003b << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT3A ((0x003a << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT39 ((0x0039 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT38 ((0x0038 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT37 ((0x0037 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT36 ((0x0036 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT35 ((0x0035 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT34 ((0x0034 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT33 ((0x0033 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT32 ((0x0032 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT31 ((0x0031 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT30 ((0x0030 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT2F ((0x002f << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT2E ((0x002e << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT2D ((0x002d << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT2C ((0x002c << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT2B ((0x002b << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT2A ((0x002a << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT29 ((0x0029 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT28 ((0x0028 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT27 ((0x0027 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT26 ((0x0026 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT25 ((0x0025 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT24 ((0x0024 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT23 ((0x0023 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT22 ((0x0022 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT21 ((0x0021 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT20 ((0x0020 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT1F ((0x001f << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT1E ((0x001e << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT1D ((0x001d << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT1C ((0x001c << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT1B ((0x001b << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT1A ((0x001a << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT19 ((0x0019 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT18 ((0x0018 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT17 ((0x0017 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT16 ((0x0016 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT15 ((0x0015 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT14 ((0x0014 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT13 ((0x0013 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT12 ((0x0012 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT11 ((0x0011 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT10 ((0x0010 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT0F ((0x000f << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT0E ((0x000e << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT0D ((0x000d << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT0C ((0x000c << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT0B ((0x000b << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT0A ((0x000a << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT09 ((0x0009 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT08 ((0x0008 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT07 ((0x0007 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT06 ((0x0006 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT05 ((0x0005 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT04 ((0x0004 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT03 ((0x0003 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT02 ((0x0002 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT01 ((0x0001 << 2) + 0xfe012000) +#define CAPU_ACCESS_EN_8K_SLOT00 ((0x0000 << 2) + 0xfe012000) +//======================================================================== +// BT656 +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe030000 +// ----------------------------------------------- +#define BT_CTRL ((0x0000 << 2) + 0xfe030000) + #define BT_SOFT_RESET 31 // Soft reset + #define BT_JPEG_START 30 + #define BT_JPEG_IGNORE_BYTES 18 //20:18 + #define BT_JPEG_IGNORE_LAST 17 + #define BT_UPDATE_ST_SEL 16 + #define BT_COLOR_REPEAT 15 + #define BT_VIDEO_MODE 13 // 14:13 + #define BT_AUTO_FMT 12 + #define BT_PROG_MODE 11 + #define BT_JPEG_MODE 10 + #define BT_XCLK27_EN_BIT 9 // 1 : xclk27 is input. 0 : xclk27 is output. + #define BT_FID_EN_BIT 8 // 1 : enable use FID port. + #define BT_CLK27_SEL_BIT 7 // 1 : external xclk27 0 : internal clk27. + #define BT_CLK27_PHASE_BIT 6 // 1 : no inverted 0 : inverted. + #define BT_ACE_MODE_BIT 5 // 1 : auto cover error by hardware. + #define BT_SLICE_MODE_BIT 4 // 1 : no ancillay flag 0 : with ancillay flag. + #define BT_FMT_MODE_BIT 3 // 1 : ntsc 0 : pal. + #define BT_REF_MODE_BIT 2 // 1 : from bit stream. 0 : from ports. + #define BT_MODE_BIT 1 // 1 : BT656 model 0 : SAA7118 mode. + #define BT_EN_BIT 0 // 1 : enable. +#define BT_VBISTART ((0x0001 << 2) + 0xfe030000) +#define BT_VBIEND ((0x0002 << 2) + 0xfe030000) +#define BT_FIELDSADR ((0x0003 << 2) + 0xfe030000) +#define BT_LINECTRL ((0x0004 << 2) + 0xfe030000) +#define BT_VIDEOSTART ((0x0005 << 2) + 0xfe030000) +#define BT_VIDEOEND ((0x0006 << 2) + 0xfe030000) +#define BT_SLICELINE0 ((0x0007 << 2) + 0xfe030000) +#define BT_SLICELINE1 ((0x0008 << 2) + 0xfe030000) +#define BT_PORT_CTRL ((0x0009 << 2) + 0xfe030000) + #define BT_HSYNC_PHASE 0 + #define BT_VSYNC_PHASE 1 + #define BT_HSYNC_PULSE 2 + #define BT_VSYNC_PULSE 3 + #define BT_FID_PHASE 4 + #define BT_FID_HSVS 5 + #define BT_IDQ_EN 6 + #define BT_IDQ_PHASE 7 + #define BT_D8B 8 + #define BT_10BTO8B 9 + #define BT_FID_DELAY 10 //12:10 + #define BT_VSYNC_DELAY 13 // + #define BT_HSYNC_DELAY 16 + #define BT_FID_HSVS_PCNT 19 + #define BT_FID_HSVS_VS_RISING 20 + #define BT_FID_HSVS_VS_FALLING 21 + #define BT_VREF_FROM_VS_ONLY 22 + #define BT_PORT_ACTIVE_HMODE 23 + #define BT_DUAL_EDGE_CLK_EN 24 + #define BT_CLK_INV_SEL 25 + #define BT_DATA_ENDIAN 26 +#define BT_SWAP_CTRL ((0x000a << 2) + 0xfe030000) +#define BT_601_CTRL0 ((0x000e << 2) + 0xfe030000) +#define BT_601_CTRL1 ((0x000f << 2) + 0xfe030000) +#define BT_601_CTRL2 ((0x0010 << 2) + 0xfe030000) +#define BT_601_CTRL3 ((0x0011 << 2) + 0xfe030000) +#define BT_FIELD_LUMA ((0x0012 << 2) + 0xfe030000) +#define BT_RAW_CTRL ((0x0013 << 2) + 0xfe030000) +#define BT_STATUS ((0x0014 << 2) + 0xfe030000) +#define BT_INT_CTRL ((0x0015 << 2) + 0xfe030000) +#define BT_VLINE_STATUS ((0x0017 << 2) + 0xfe030000) +#define BT_ERR_CNT ((0x0019 << 2) + 0xfe030000) +#define BT_LCNT_STATUS ((0x001a << 2) + 0xfe030000) +#define BT_PCNT_STATUS ((0x001c << 2) + 0xfe030000) +#define BT_DELAY_CTRL ((0x001d << 2) + 0xfe030000) +#define BT_REF_000 ((0x0020 << 2) + 0xfe030000) +#define BT_REF_001 ((0x0021 << 2) + 0xfe030000) +#define BT_REF_010 ((0x0022 << 2) + 0xfe030000) +#define BT_REF_011 ((0x0023 << 2) + 0xfe030000) +#define BT_REF_100 ((0x0024 << 2) + 0xfe030000) +#define BT_REF_101 ((0x0025 << 2) + 0xfe030000) +#define BT_REF_110 ((0x0026 << 2) + 0xfe030000) +#define BT_REF_111 ((0x0027 << 2) + 0xfe030000) +//======================================================================== +// PDM +//======================================================================== +//`include "../audio/rtl/pdm_reg.vh" +// +// Reading file: REG_LIST_AUDIO_RTL.h +// +//======================================================================== +// AUDIO - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe330000 +// ----------------------------------------------- +#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe330000) +#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe330000) +#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe330000) +#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe330000) +#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe330000) +#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe330000) +#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe330000) +#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe330000) +#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe330000) +#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe330000) +#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe330000) +#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe330000) +#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe330000) +#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe330000) +#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe330000) +#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe330000) +#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe330000) +#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe330000) +#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe330000) +#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe330000) +#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe330000) +#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe330000) +#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe330000) +#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe330000) +#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe330000) +#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe330000) +#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe330000) +#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe330000) +#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe330000) +#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe330000) +#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe330000) +#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe330000) +#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe330000) +#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe330000) +#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe330000) +#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe330000) +#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe330000) +#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe330000) +#define EE_AUDIO_ARB_CTRL0 ((0x00a0 << 2) + 0xfe330000) +#define EE_AUDIO_ARB_CTRL1 ((0x00a1 << 2) + 0xfe330000) +#define EE_AUDIO_ARB_STS ((0x00a8 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_CHSYNC_CTRL_INSERT ((0x00bd << 2) + 0xfe330000) +#define EE_AUDIO_LB_A_CHSYNC_CTRL_ORIG ((0x00be << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_CTRL7 ((0x010b << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_GAIN2 ((0x0134 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_GAIN3 ((0x0135 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_GAIN_EN ((0x0136 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_GAIN_CTRL ((0x0137 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe330000) +//`define EE_AUDIO_POW_DET_CTRL0 10'h180 +//`define EE_AUDIO_POW_DET_CTRL1 10'h181 +//`define EE_AUDIO_POW_DET_TH_HI 10'h182 +//`define EE_AUDIO_POW_DET_TH_LO 10'h183 +//`define EE_AUDIO_POW_DET_VALUE 10'h184 +#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe330000) +#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe330000) +#define EE_AUDIO_IRQ_FIFO_CNT ((0x0192 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_GAIN2 ((0x01b4 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_GAIN3 ((0x01b5 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_GAIN_EN ((0x01b6 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFOUT_B_GAIN_CTRL ((0x01b7 << 2) + 0xfe330000) +#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe330000) +#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe330000) +#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe330000) +#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe330000) +#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe330000) +#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe330000) +#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe330000) +#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe330000) +#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe330000) +#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe330000) +#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe330000) +#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe330000) +#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe330000) +#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_CTRL6 ((0x0206 << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_CTRL7 ((0x0207 << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe330000) +#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_CHSYNC_CTRL_INSERT ((0x023d << 2) + 0xfe330000) +#define EE_AUDIO_LB_B_CHSYNC_CTRL_ORIG ((0x023e << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe330000) +#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe330000) +#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_GAIN_EN ((0x02ac << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_A_GAIN_CTRL ((0x02ad << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_GAIN_EN ((0x02bc << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_B_GAIN_CTRL ((0x02bd << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_GAIN_EN ((0x02cc << 2) + 0xfe330000) +#define EE_AUDIO_TDMOUT_C_GAIN_CTRL ((0x02cd << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHNUM_ID0 ((0x0300 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHNUM_ID1 ((0x0301 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHNUM_ID2 ((0x0302 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHNUM_ID3 ((0x0303 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHNUM_ID4 ((0x0304 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHNUM_ID5 ((0x0305 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHNUM_ID6 ((0x0306 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHNUM_ID7 ((0x0307 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_A_CHSYNC_CTRL ((0x030f << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHNUM_ID0 ((0x0310 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHNUM_ID1 ((0x0311 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHNUM_ID2 ((0x0312 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHNUM_ID3 ((0x0313 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHNUM_ID4 ((0x0314 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHNUM_ID5 ((0x0315 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHNUM_ID6 ((0x0316 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHNUM_ID7 ((0x0317 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_B_CHSYNC_CTRL ((0x031f << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHNUM_ID0 ((0x0320 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHNUM_ID1 ((0x0321 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHNUM_ID2 ((0x0322 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHNUM_ID3 ((0x0323 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHNUM_ID4 ((0x0324 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHNUM_ID5 ((0x0325 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHNUM_ID6 ((0x0326 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHNUM_ID7 ((0x0327 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_C_CHSYNC_CTRL ((0x032f << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHNUM_ID0 ((0x0330 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHNUM_ID1 ((0x0331 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHNUM_ID2 ((0x0332 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHNUM_ID3 ((0x0333 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHNUM_ID4 ((0x0334 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHNUM_ID5 ((0x0335 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHNUM_ID6 ((0x0336 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHNUM_ID7 ((0x0337 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_D_CHSYNC_CTRL ((0x033f << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHNUM_ID0 ((0x0340 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHNUM_ID1 ((0x0341 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHNUM_ID2 ((0x0342 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHNUM_ID3 ((0x0343 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHNUM_ID4 ((0x0344 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHNUM_ID5 ((0x0345 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHNUM_ID6 ((0x0346 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHNUM_ID7 ((0x0347 << 2) + 0xfe330000) +#define EE_AUDIO_TODDR_E_CHSYNC_CTRL ((0x034f << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID0 ((0x0350 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID1 ((0x0351 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID2 ((0x0352 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID3 ((0x0353 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID4 ((0x0354 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID5 ((0x0355 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID6 ((0x0356 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHNUM_ID7 ((0x0357 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_CHSYNC_MASK ((0x035e << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_A_CHSYNC_CTRL ((0x035f << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHNUM_ID0 ((0x0360 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHNUM_ID1 ((0x0361 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHNUM_ID2 ((0x0362 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHNUM_ID3 ((0x0363 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHNUM_ID4 ((0x0364 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHNUM_ID5 ((0x0365 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHNUM_ID6 ((0x0366 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHNUM_ID7 ((0x0367 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_B_CHSYNC_CTRL ((0x036f << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHNUM_ID0 ((0x0370 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHNUM_ID1 ((0x0371 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHNUM_ID2 ((0x0372 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHNUM_ID3 ((0x0373 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHNUM_ID4 ((0x0374 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHNUM_ID5 ((0x0375 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHNUM_ID6 ((0x0376 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHNUM_ID7 ((0x0377 << 2) + 0xfe330000) +#define EE_AUDIO_RSAMP_C_CHSYNC_CTRL ((0x037f << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_STS0 ((0x0380 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_STS1 ((0x0381 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_MASK0 ((0x0382 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_MASK1 ((0x0383 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_MODE0 ((0x0384 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_MODE1 ((0x0385 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_CLR0 ((0x0386 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_CLR1 ((0x0387 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_INV0 ((0x0388 << 2) + 0xfe330000) +#define EE_AUDIO_EXCEPTION_IRQ_INV1 ((0x0389 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL0 ((0x0390 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL1 ((0x0391 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL2 ((0x0392 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL3 ((0x0393 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL4 ((0x0394 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL5 ((0x0395 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL6 ((0x0396 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL7 ((0x0397 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL8 ((0x0398 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRL9 ((0x0399 << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRLA ((0x039a << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRLB ((0x039b << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRLC ((0x039c << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRLD ((0x039d << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRLE ((0x039e << 2) + 0xfe330000) +#define EE_AUDIO_DAT_PAD_CTRLF ((0x039f << 2) + 0xfe330000) +#define EE_AUDIO_MCLK_PAD_CTRL0 ((0x03a0 << 2) + 0xfe330000) +#define EE_AUDIO_MCLK_PAD_CTRL1 ((0x03a1 << 2) + 0xfe330000) +#define EE_AUDIO_SCLK_PAD_CTRL0 ((0x03a2 << 2) + 0xfe330000) +#define EE_AUDIO_LRCLK_PAD_CTRL0 ((0x03a3 << 2) + 0xfe330000) +//======================================================================== +// PDM - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe331000 +// ----------------------------------------------- +#define PDM_CTRL ((0x0000 << 2) + 0xfe331000) + //bit 31: PDM enable. + //bit 30: invert the PDM_DCLK. + //bit 29: output mode: 1: 24bits. 0: 32 bits. + //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode. + //bit 27~9: not used. + //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO. + //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode. + //bit 7:0. PDM channel enable. each bit for one channel. +#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe331000) + //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output. + //bit 29:24. hcic final gain shift parameter. + //bit 23:16 hcic final gain multiplier. + //bit 8:4 hcic down sample rate. + //bit 3:0 hcic stage number. must be between 3 to 9. +#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe331000) + //Not used. +#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe331000) + //bit 31 . filter 1 enable. + //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26] + // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26] + // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26]. + //bit 15:12. filter 1 down sample rate. + //bit 8:0. filter 1 stage number. +#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe331000) + //bit 31 . filter 2 enable. + //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. + //bit 15:12. filter 2 down sample rate. + //bit 8:0. filter 2 stage number. +#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe331000) + //bit 31 . filter 3 enable. + //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23. + //bit 15:12. filter 3 down sample rate. + //bit 8:0. filter 3 stage number. +#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe331000) + //bit 31 High pass filter enable. + //bit 20:16 high pass filter shift steps. 6~19 steps. + //bit 15:0 high pass filter output factor. +#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe331000) + //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK. + //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK. + //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK. + //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK. +#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe331000) + //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK. + //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK. + //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK. + //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK. +#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe331000) + // address of the write/read of coeff data. +#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe331000) + //write/read data to coeff memory. +#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe331000) + // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating. + //31:7 not used. + //bit 6 filt_ctrl module auto clock gating control. + //bit 5 sinc fifo module auto clock gating control. + //bit 4 filter module auto clock gating control. + //bit 3 apb module auto clock gating control. + //bit 2 coeff memory module auto clock gating control. + //bit 1 each channel module auto clock gating control. + //bit 0 cts_pdm_clk auto clock gating control. +#define PDM_STS ((0x000c << 2) + 0xfe331000) +//bit 1 HPF filter output overflow. means the PCLK is too slow. +//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function. +#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe331000) +#define PDM_MASK_NUM ((0x000e << 2) + 0xfe331000) +//======================================================================== +// EQ DRC - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe332000 +// ----------------------------------------------- +#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe332000) +#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe332000) +#define AED_EQ_EN ((0x0002 << 2) + 0xfe332000) +#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe332000) +#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe332000) +#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe332000) +#define AED_MUTE ((0x0006 << 2) + 0xfe332000) +#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe332000) +#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe332000) +#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe332000) +#define AED_DRC_THD0 ((0x000a << 2) + 0xfe332000) +#define AED_DRC_THD1 ((0x000b << 2) + 0xfe332000) +#define AED_DRC_THD2 ((0x000c << 2) + 0xfe332000) +#define AED_DRC_THD3 ((0x000d << 2) + 0xfe332000) +#define AED_DRC_THD4 ((0x000e << 2) + 0xfe332000) +#define AED_DRC_K0 ((0x000f << 2) + 0xfe332000) +#define AED_DRC_K1 ((0x0010 << 2) + 0xfe332000) +#define AED_DRC_K2 ((0x0011 << 2) + 0xfe332000) +#define AED_DRC_K3 ((0x0012 << 2) + 0xfe332000) +#define AED_DRC_K4 ((0x0013 << 2) + 0xfe332000) +#define AED_DRC_K5 ((0x0014 << 2) + 0xfe332000) +#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe332000) +#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe332000) +#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe332000) +#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe332000) +#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe332000) +#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe332000) +#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe332000) +#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe332000) +#define AED_MDRC_K0 ((0x003b << 2) + 0xfe332000) +#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe332000) +#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe332000) +#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe332000) +#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe332000) +#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe332000) +#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe332000) +#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe332000) +#define AED_MDRC_K2 ((0x004f << 2) + 0xfe332000) +#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe332000) +#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe332000) +#define AED_ED_CNTL ((0x0052 << 2) + 0xfe332000) +#define AED_DC_EN ((0x0053 << 2) + 0xfe332000) +#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe332000) +#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe332000) +#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe332000) +#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe332000) +#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe332000) +#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe332000) +#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe332000) +#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe332000) +#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe332000) +#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe332000) +#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe332000) +#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe332000) +#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe332000) +#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe332000) +#define AED_ND_CNTL ((0x0062 << 2) + 0xfe332000) +#define AED_MIX0_LL ((0x0063 << 2) + 0xfe332000) +#define AED_MIX0_RL ((0x0064 << 2) + 0xfe332000) +#define AED_MIX0_LR ((0x0065 << 2) + 0xfe332000) +#define AED_MIX0_RR ((0x0066 << 2) + 0xfe332000) +#define AED_CLIP_THD ((0x0067 << 2) + 0xfe332000) +#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe332000) +#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe332000) +#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe332000) +#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe332000) +#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe332000) +#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe332000) +#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe332000) +#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe332000) +#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe332000) +#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe332000) +#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe332000) +#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe332000) +#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe332000) +#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe332000) +#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe332000) +#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe332000) +#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe332000) +#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe332000) +#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe332000) +#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe332000) +#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe332000) +#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe332000) +#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe332000) +#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe332000) +#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe332000) +#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe332000) +#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe332000) +#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe332000) +#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe332000) +#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe332000) +#define AED_TOP_ST ((0x0086 << 2) + 0xfe332000) +#define AED_EQDRC_DYNAMIC_CNTL ((0x0090 << 2) + 0xfe332000) +#define AED_COEF_RAM_CNTL_B ((0x0091 << 2) + 0xfe332000) +#define AED_COEF_RAM_DATA_B ((0x0092 << 2) + 0xfe332000) +#define AED_DRC_RMS_COEF0_B ((0x0093 << 2) + 0xfe332000) +#define AED_DRC_RMS_COEF1_B ((0x0094 << 2) + 0xfe332000) +#define AED_DRC_THD0_B ((0x0095 << 2) + 0xfe332000) +#define AED_DRC_THD1_B ((0x0096 << 2) + 0xfe332000) +#define AED_DRC_THD2_B ((0x0097 << 2) + 0xfe332000) +#define AED_DRC_THD3_B ((0x0098 << 2) + 0xfe332000) +#define AED_DRC_THD4_B ((0x0099 << 2) + 0xfe332000) +#define AED_DRC_K0_B ((0x009a << 2) + 0xfe332000) +#define AED_DRC_K1_B ((0x009b << 2) + 0xfe332000) +#define AED_DRC_K2_B ((0x009c << 2) + 0xfe332000) +#define AED_DRC_K3_B ((0x009d << 2) + 0xfe332000) +#define AED_DRC_K4_B ((0x009e << 2) + 0xfe332000) +#define AED_DRC_K5_B ((0x009f << 2) + 0xfe332000) +#define AED_DRC_THD_OUT0_B ((0x00a0 << 2) + 0xfe332000) +#define AED_DRC_THD_OUT1_B ((0x00a1 << 2) + 0xfe332000) +#define AED_DRC_THD_OUT2_B ((0x00a2 << 2) + 0xfe332000) +#define AED_DRC_THD_OUT3_B ((0x00a3 << 2) + 0xfe332000) +#define AED_DRC_OFFSET_B ((0x00a4 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF00_B ((0x00a5 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF01_B ((0x00a6 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF10_B ((0x00a7 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF11_B ((0x00a8 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF20_B ((0x00a9 << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF21_B ((0x00aa << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF30_B ((0x00ab << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF31_B ((0x00ac << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF40_B ((0x00ad << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF41_B ((0x00ae << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF50_B ((0x00af << 2) + 0xfe332000) +#define AED_DRC_RELEASE_COEF51_B ((0x00b0 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF00_B ((0x00b1 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF01_B ((0x00b2 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF10_B ((0x00b3 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF11_B ((0x00b4 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF20_B ((0x00b5 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF21_B ((0x00b6 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF30_B ((0x00b7 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF31_B ((0x00b8 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF40_B ((0x00b9 << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF41_B ((0x00ba << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF50_B ((0x00bb << 2) + 0xfe332000) +#define AED_DRC_ATTACK_COEF51_B ((0x00bc << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF00_B ((0x00bd << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF01_B ((0x00be << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF10_B ((0x00bf << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF11_B ((0x00c0 << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF20_B ((0x00c1 << 2) + 0xfe332000) +#define AED_MDRC_RMS_COEF21_B ((0x00c2 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF00_B ((0x00c3 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF01_B ((0x00c4 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF10_B ((0x00c5 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF11_B ((0x00c6 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF20_B ((0x00c7 << 2) + 0xfe332000) +#define AED_MDRC_RELEASE_COEF21_B ((0x00c8 << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF00_B ((0x00c9 << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF01_B ((0x00ca << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF10_B ((0x00cb << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF11_B ((0x00cc << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF20_B ((0x00cd << 2) + 0xfe332000) +#define AED_MDRC_ATTACK_COEF21_B ((0x00ce << 2) + 0xfe332000) +#define AED_MDRC_THD0_B ((0x00cf << 2) + 0xfe332000) +#define AED_MDRC_THD1_B ((0x00d0 << 2) + 0xfe332000) +#define AED_MDRC_THD2_B ((0x00d1 << 2) + 0xfe332000) +#define AED_MDRC_K0_B ((0x00d2 << 2) + 0xfe332000) +#define AED_MDRC_K1_B ((0x00d3 << 2) + 0xfe332000) +#define AED_MDRC_K2_B ((0x00d4 << 2) + 0xfe332000) +#define AED_MDRC_OFFSET0_B ((0x00d5 << 2) + 0xfe332000) +#define AED_MDRC_OFFSET1_B ((0x00d6 << 2) + 0xfe332000) +#define AED_MDRC_OFFSET2_B ((0x00d7 << 2) + 0xfe332000) +#define AED_MDRC_LOW_GAIN_B ((0x00d8 << 2) + 0xfe332000) +#define AED_MDRC_MID_GAIN_B ((0x00d9 << 2) + 0xfe332000) +#define AED_MDRC_HIGH_GAIN_B ((0x00da << 2) + 0xfe332000) +#define AED_DRC_CNTL_B ((0x00db << 2) + 0xfe332000) +#define AED_DRC_LOOPBACK_CNTL_B ((0x00dc << 2) + 0xfe332000) +#define AED_MDRC_CNTL_B ((0x00dd << 2) + 0xfe332000) +#define AED_STATUS_REG ((0x00de << 2) + 0xfe332000) +//======================================================================== +// AUDIO locker - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe331400 +// ----------------------------------------------- +#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe331400) +#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe331400) +#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe331400) +#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe331400) +#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe331400) +#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe331400) +#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe331400) +#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe331400) +#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe331400) +#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe331400) +#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe331400) +#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe331400) +#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe331400) +#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe331400) +#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe331400) +#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe331400) +#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe331400) +#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe331400) +#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe331400) +#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe331400) +#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe331400) +#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe331400) +#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe331400) +#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe331400) +#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe331400) +#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe331400) +//======================================================================== +// AUDIO VAD - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe331800 +// ----------------------------------------------- +// +// Reading file: VAD_REG.h +// +#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe331800) +#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe331800) +#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe331800) +#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe331800) +#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe331800) +#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe331800) +#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe331800) +#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe331800) +#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe331800) +#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe331800) +#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe331800) +#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe331800) +#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe331800) +#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe331800) +#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe331800) +#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe331800) +#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe331800) +#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe331800) +#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe331800) +#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe331800) +#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe331800) +#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe331800) +#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe331800) +#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe331800) +#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe331800) +#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe331800) +#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe331800) +#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe331800) +#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe331800) +#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe331800) +#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe331800) +#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe331800) +#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe331800) +#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe331800) +#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe331800) +#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe331800) +#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe331800) +#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe331800) +#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe331800) +#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe331800) +#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe331800) +#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe331800) +#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe331800) +#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe331800) +#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe331800) +#define VAD_LUT_WR ((0x002d << 2) + 0xfe331800) +#define VAD_LUT_RD ((0x002e << 2) + 0xfe331800) +#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe331800) +#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe331800) +#define VAD_TO_DDR ((0x0031 << 2) + 0xfe331800) +#define VAD_SYNC_CTRL0 ((0x0032 << 2) + 0xfe331800) +#define VAD_SYNC_CHNUM_ID0 ((0x0033 << 2) + 0xfe331800) +#define VAD_SYNC_CHNUM_ID1 ((0x0034 << 2) + 0xfe331800) +#define VAD_SYNC_CHNUM_ID2 ((0x0035 << 2) + 0xfe331800) +#define VAD_SYNC_CHNUM_ID3 ((0x0036 << 2) + 0xfe331800) +#define VAD_SYNC_CHNUM_ID4 ((0x0037 << 2) + 0xfe331800) +#define VAD_SYNC_CHNUM_ID5 ((0x0038 << 2) + 0xfe331800) +#define VAD_SYNC_CHNUM_ID6 ((0x0039 << 2) + 0xfe331800) +#define VAD_SYNC_CHNUM_ID7 ((0x003a << 2) + 0xfe331800) +// +// Closing file: VAD_REG.h +// +//======================================================================== +// AUDIO RESAMPLEA - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe331c00 +// ----------------------------------------------- +// +// Reading file: RESAMPLE.h +// +#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe331c00) +//Bit 31:3 reserved +//Bit 2 reg_lock_rst //unsigned , default =0; +//Bit 1 reg_rsamp_rst //unsigned , default =0; +//Bit 0 reg_sw_rst //unsigned , default =0; +#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe331c00) +//Bit 31:27 reserved //unsigned , default =0; +//Bit 26 reg_watchdog_en //unsigned , default =0; +//Bit 25 reg_rsamp_rst_sel //unsigned , default =0; +//Bit 24 reg_module_bypas //unsigned , default =0; +//Bit 23:18 reg_gclk_ctrl //unsigned , default =0; +//Bit 17:13 reg_in_msb //unsigned , default =23; +//Bit 12 reg_output_en //unsigned , default =0; +//Bit 11 reg_rsamp_en //unsigned , default =0; +//Bit 10 reg_filt_en //unsigned , default =0; +//Bit 9 reg_post_en //unsigned , default =0; +//Bit 8 reg_inp_mux_mode //unsigned , default =0; +//Bit 7:4 reserved //unsigned , default =2; +//Bit 3:0 reg_inp_mux //unsigned , default =0; +#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe331c00) +//Bit 31:30 reserved //unsigned , default =0; +//Bit 29:24 reg_chx_size //unsigned , default =2; +//Bit 23:18 reserved //unsigned , default =0; +//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4 +//Bit 15:8 reg_filt_tap //unsigned , default =63; +//Bit 7:0 reg_intp_tap //unsigned , default =63; +#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe331c00) +//Bit 31:28 reserved //unsigned , default = 0; +//Bit 27:0 reg_init_phs //unsigned , default = 0; +#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe331c00) +//Bit 31 reserved //unsigned , default = 0; +//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000 +#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe331c00) +//Bit 31:24 reg_rsft_iir //unsigned , default = 23; +//Bit 23:16 reg_rsft_blnd //unsigned , default = 21; +//Bit 15:8 reg_rsft_sinc //unsigned , default = 31; +//Bit 7:0 reg_rsft_aa //unsigned , default = 31; +#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe331c00) +//Bit 31:3 reserved //unsigned +//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0; +//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0; +//Bit 0 reg_rsamp_adj_en //unsigned , default = 0; +#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe331c00) +//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8; +//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768; +#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe331c00) +//Bit 31:30 reserved //unsigned , default = 0; +//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0; +//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9; +//Bit 23:21 reserved //unsigned , default = 0; +//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1; +//Bit 15:13 reserved //unsigned , default = 0; +//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6; +//Bit 7:6 reserved //unsigned , default = 0; +//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12; +#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe331c00) +//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000; +#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe331c00) +//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8; +#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe331c00) +//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0; +#define AUDIO_RSAMP_WATCHDOG_THRD ((0x000c << 2) + 0xfe331c00) +//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000; +#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe331c00) +//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]} +#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe331c00) +//Bit 31:0 ro_rsamp_adj_freq +#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe331c00) +//Bit 31:0 ro_det_diff_bak +#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe331c00) +//Bit 31:0 ro_det_diff_dlt +#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe331c00) +//Bit 31:0 ro_det_phase_err +#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe331c00) +//Bit 31:0 ro_rsamp_ki_out +#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe331c00) +//Bit 31:0 ro_rsamp_in_cnt +#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe331c00) +//Bit 31:0 ro_rsamp_out_cnt +#define AUDIO_RSAMP_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe331c00) +//Bit 31:0 ro_det_phase_err_var +#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe331c00) +//Bit 31:0 reg_post_coef0 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe331c00) +//Bit 31:0 reg_post_coef1 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe331c00) +//Bit 31:0 reg_post_coef2 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe331c00) +//Bit 31:0 reg_post_coef3 //signed , default = 0; +#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe331c00) +//Bit 31:0 reg_post_coef4 //signed , default = 0; +#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe331c00) +//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe331c00) +//Bit 31:0 reg_aa_coef_data //signed , default = 0; +#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe331c00) +//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe331c00) +//Bit 31:0 reg_sinc_coef_data //signed , default = 0; +// +// Closing file: RESAMPLE.h +// +//======================================================================== +// AUDIO EARCTX_CMDC - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe333000 +// ----------------------------------------------- +// +// Reading file: earc_tx_cmdc.h +// +#define EARC_TX_CMDC_TOP_CTRL0 ((0x0030 << 2) + 0xfe333000) +//Bit 31 , idle2_int unsigned, default = 0, 1: enable +//Bit 30 , idle1_int unsigned, default = 0, 1: enable +//Bit 29 , disc2_int unsigned, default = 0, 1: enable +//Bit 28 , disc1_int unsigned, default = 0, 1: enable +//Bit 27 , earc_int unsigned, default = 0, 1: enable +//Bit 26 , hb_status_int unsigned, default = 0, 1: enable +//Bit 25 , losthb_int unsigned, default = 0, 1: enable +//Bit 24 , timeout_int unsigned, default = 0, 1: enable +//Bit 23 , status_ch_int unsigned, default = 0, 1: enable +//Bit 22 , int_recv_finished unsigned, default = 0, 1: enable +//Bit 21 , int_rdata unsigned, default = 0, 1: enable +//Bit 20 , int_recv_nack unsigned, default = 0, 1: enable +//Bit 19 , int_recv_norsp unsigned, default = 0, 1: enable +//Bit 18 , int_recv_unexp unsigned, default = 0, 1: enable +//Bit 17 , int_recv_data unsigned, default = 0, 1: enable +//Bit 16 , int_recv_ack unsigned, default = 0, 1: enable +//Bit 15 , int_recv_ecc_err unsigned, default = 0, 1: enable +//Bit 14 , int_recv_packet unsigned, default = 0, 1: enable +//Bit 13:0 , reserved +#define EARC_TX_CMDC_TOP_CTRL1 ((0x0031 << 2) + 0xfe333000) +//Bit 31:0, cmdc_top_ctrl1 //unsigned, RW, default = 0, +#define EARC_TX_CMDC_TOP_CTRL2 ((0x0032 << 2) + 0xfe333000) +//Bit 31 , reset_idle2_int unsigned, default = 0, 1: enable +//Bit 30 , reset_idle1_int unsigned, default = 0, 1: enable +//Bit 29 , reset_disc2_int unsigned, default = 0, 1: enable +//Bit 28 , reset_disc1_int unsigned, default = 0, 1: enable +//Bit 27 , reset_earc_int unsigned, default = 0, 1: enable +//Bit 26 , reset_hb_status_int unsigned, default = 0, 1: enable +//Bit 25 , reset_losthb_int unsigned, default = 0, 1: enable +//Bit 24 , reset_timeout_int unsigned, default = 0, 1: enable +//Bit 23 , reset_status_ch_int unsigned, default = 0, 1: enable +//Bit 22 , reset_int_recv_finished unsigned, default = 0, 1: enable +//Bit 21 , reset_int_rdata unsigned, default = 0, 1: enable +//Bit 20 , reset_int_recv_nack unsigned, default = 0, 1: enable +//Bit 19 , reset_int_recv_norsp unsigned, default = 0, 1: enable +//Bit 18 , reset_int_recv_unexp unsigned, default = 0, 1: enable +//Bit 17 , reset_int_recv_data unsigned, default = 0, 1: enable +//Bit 16 , reset_int_recv_ack unsigned, default = 0, 1: enable +//Bit 15 , reset_int_recv_ecc_err unsigned, default = 0, 1: enable +//Bit 14 , reset_int_recv_packet unsigned, default = 0, 1: enable +//Bit 13:0 , reserved +#define EARC_TX_CMDC_TIMER_CTRL0 ((0x0033 << 2) + 0xfe333000) +//Bit 31:0, cmdc_timer_ctrl0 //unsigned, RW, default = 0, +#define EARC_TX_CMDC_TIMER_CTRL1 ((0x0034 << 2) + 0xfe333000) +//Bit 31:0, cmdc_timer_ctrl1 //unsigned, RW, default = 0, +#define EARC_TX_CMDC_TIMER_CTRL2 ((0x0035 << 2) + 0xfe333000) +//Bit 31:0, cmdc_timer_ctrl2 //unsigned, RW, default = 0, +#define EARC_TX_CMDC_TIMER_CTRL3 ((0x0036 << 2) + 0xfe333000) +//Bit 31:0, cmdc_timer_ctrl3 //unsigned, RW, default = 0, +#define EARC_TX_CMDC_VSM_CTRL0 ((0x0037 << 2) + 0xfe333000) +//Bit 31, sw_state_update unsigned, default = 0, XX +//Bit 30:28, sw_state unsigned, default = 0, XX +//Bit 27, arc_initiated unsigned, default = 0, XX +//Bit 26, arc_terminated unsigned, default = 0, XX +//Bit 25, arc_enable unsigned, default = 1, XX +//Bit 24, man_hpd unsigned, default = 0, XX +//Bit 23:22, hpd_sel unsigned, default = 0, XX +//Bit 21:20, hpd_sel_earc unsigned, default = 0, XX +//Bit 19, comma_cnt_rst unsigned, default = 0, XX +//Bit 18, timeout_status_rst unsigned, default = 0, XX +//Bit 17, losthb_status_rst unsigned, default = 0, XX +//Bit 16, force_rst unsigned, default = 0, XX +//Bit 15, auto_state_en unsigned, default = 0, XX +//Bit 14, cmdc_state_en unsigned, default = 0, XX +//Bit 13, noack_repeat_en unsigned, default = 0, XX +//Bit 12:0, reserved +#define EARC_TX_CMDC_VSM_CTRL1 ((0x0038 << 2) + 0xfe333000) +//Bit 31:9, reserved +//Bit 8, cntl_hpd_sel unsigned, default = 0, 0:sel hd_hpd,1:sel hdmirx_hpd +//Bit 7:0, comma_cnt_th unsigned, default = 0, should bigger than 3 and small than 10 +#define EARC_TX_CMDC_VSM_CTRL2 ((0x0039 << 2) + 0xfe333000) +//Bit 31:12, max_count_th unsigned, default = 0, disc1 hpd_val timing +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, disc1 hpd_val timing +//Bit 6:4, time_sel unsigned, default = 0, disc1 hpd_val timing +//Bit 3:2, soft_rst_sel unsigned, default = 0, disc1 hpd_val timing +//Bit 1:0, enable_ctrl unsigned, default = 0, disc1 hpd_val timing +#define EARC_TX_CMDC_VSM_CTRL3 ((0x003a << 2) + 0xfe333000) +//Bit 31:12, max_count_th unsigned, default = 0, disc2 heartbeat act timing +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, disc2 heartbeat act timing +//Bit 6:4, time_sel unsigned, default = 0, disc2 heartbeat act timing +//Bit 3:2, soft_rst_sel unsigned, default = 0, disc2 heartbeat act timing +//Bit 1:0, enable_ctrl unsigned, default = 0, disc2 heartbeat act timing +#define EARC_TX_CMDC_VSM_CTRL4 ((0x003b << 2) + 0xfe333000) +//Bit 31:12, max_count_th unsigned, default = 0, in disc2, no heartbeat ack timing +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, in disc2, no heartbeat ack timing +//Bit 6:4, time_sel unsigned, default = 0, in disc2, no heartbeat ack timing +//Bit 3:2, soft_rst_sel unsigned, default = 0, in disc2, no heartbeat ack timing +//Bit 1:0, enable_ctrl unsigned, default = 0, in disc2, no heartbeat ack timing +#define EARC_TX_CMDC_VSM_CTRL5 ((0x003c << 2) + 0xfe333000) +//Bit 31:12, max_count_th unsigned, default = 0, in disc1 and disc2 timing out +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, in disc1 and disc2 timing out +//Bit 6:4, time_sel unsigned, default = 0, in disc1 and disc2 timing out +//Bit 3:2, soft_rst_sel unsigned, default = 0, in disc1 and disc2 timing out +//Bit 1:0, enable_ctrl unsigned, default = 0, in disc1 and disc2 timing out +#define EARC_TX_CMDC_VSM_CTRL6 ((0x003d << 2) + 0xfe333000) +//Bit 31:12, max_count_th unsigned, default = 0, in earc heartbeat act timing +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat act timing +//Bit 6:4, time_sel unsigned, default = 0, in earc heartbeat act timing +//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat act timing +//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat act timing +#define EARC_TX_CMDC_VSM_CTRL7 ((0x003e << 2) + 0xfe333000) +//Bit 31:16, reserved +//Bit 15:8, status_soft_val unsigned, default = 0, in earc heartbeat det timing +//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat det timing +//Bit 6, status_rst unsigned, default = 0, in earc heartbeat det timing +//Bit 5:4, reserved +//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat det timing +//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat det timing +#define EARC_TX_CMDC_VSM_CTRL8 ((0x003f << 2) + 0xfe333000) +//Bit 31:0, cmdc_vsm_ctrl8 //unsigned, RW, default = 0, +#define EARC_TX_CMDC_VSM_CTRL9 ((0x0041 << 2) + 0xfe333000) +//Bit 31:0, cmdc_vsm_ctrl9 //unsigned, RW, default = 0 +#define EARC_TX_CMDC_SENDER_CTRL0 ((0x0042 << 2) + 0xfe333000) +//Bit 31:2, sender_ctrl0 unsigned, default = 0, +//Bit 1, hb_chg_conf_auto unsigned, default = 1, +//Bit 0, hb_chg_auto unsigned, default = 0, +#define EARC_TX_CMDC_PACKET_CTRL0 ((0x0043 << 2) + 0xfe333000) +//Bit 31, packet_mode_enable unsigned, default = 0, packet control +//Bit 30, free_enable unsigned, default = 0, packet control +//Bit 29, soft_rst unsigned, default = 0, packet control +//Bit 28:24, tx_ready_threshold unsigned, default = 0, packet control +//Bit 23:20, reserved +//Bit 19:8, send_pre_threshold unsigned, default = 0, packet control +//Bit 7:6, reserved +//Bit 5, state_auto_en unsigned, default = 0, packet control +//Bit 4, sw_state_update_en unsigned, default = 0, packet control +//Bit 3:0, sw_state_value unsigned, default = 0, packet control +#define EARC_TX_CMDC_PACKET_CTRL1 ((0x0044 << 2) + 0xfe333000) +//Bit 31, ecc_endian unsigned, default = 0, send +//Bit 30, pre_start_value unsigned, default = 0, send +//Bit 29:21, reserved +//Bit 20:16, post_threshold unsigned, default = 0, send +//Bit 15:14, reserved +//Bit 13:8, pre_threshold unsigned, default = 0, XX +//Bit 7:0, post_flag unsigned, default = 0, XX +#define EARC_TX_CMDC_PACKET_CTRL2 ((0x0045 << 2) + 0xfe333000) +//Bit 31:0, pre_flag unsigned, default = 0, XX +#define EARC_TX_CMDC_PACKET_CTRL3 ((0x0046 << 2) + 0xfe333000) +//Bit 31, recv_en unsigned, default = 0, XX +//Bit 30, recv_parity_mask unsigned, default = 0, XX +//Bit 29, recv_timeout_en unsigned, default = 0, XX +//Bit 28, bch_ecc_en unsigned, default = 0, xx +//Bit 27:16, reserved +//Bit 15:0, recv_timeout_threshold unsigned, default = 0, XX +#define EARC_TX_CMDC_PACKET_CTRL4 ((0x0047 << 2) + 0xfe333000) +//Bit 31:20, reserved +//Bit 19:0, recv_packet_head unsigned, default = 0, XX +#define EARC_TX_CMDC_PACKET_CTRL5 ((0x0048 << 2) + 0xfe333000) +//Bit 31:20, reserved +//Bit 19:0, recv_packet_head_mask unsigned, default = 0, XX +#define EARC_TX_CMDC_PACKET_CTRL6 ((0x0049 << 2) + 0xfe333000) +//Bit 31:20, recv_pre_threshold unsigned, default = 0, packet control +//Bit 19:7, reserved +//Bit 6, recv_finished_int unsigned, default = 0, XX +//Bit 5, recv_ecc_err_int unsigned, default = 0, XX +//Bit 4, recv_ack_int unsigned, default = 0, XX +//Bit 3, recv_data_int unsigned, default = 0, XX +//Bit 2, recv_unexp_int unsigned, default = 0, XX +//Bit 1, recv_norsp_int unsigned, default = 0, XX +//Bit 0, recv_nack_int unsigned, default = 0, XX +#define EARC_TX_CMDC_BIPHASE_CTRL0 ((0x004a << 2) + 0xfe333000) +//Bit 31:24, reserved +//Bit 23:16, ack delay threshold unsigned, default = 0, xx +//Bit 15:10, reserved +//Bit 9, send_ack_en unsigned, default = 0, xx +//Bit 8, sq_val_en unsigned, default = 0, XX +//Bit 7, biphase_send_soft_rst unsigned, default = 0, XX +//Bit 6, comma_soft_rst unsigned, default = 0, XX +//Bit 5, fifo_rst unsigned, default = 0, XX +//Bit 4, receiver_no_sender unsigned, default = 0, XX +//Bit 3, sender_free unsigned, default = 0, XX +//Bit 2, receiver_send unsigned, default = 0, XX +//Bit 1, receiver_earc unsigned, default = 0, XX +//Bit 0, receiver_free unsigned, default = 0, XX +#define EARC_TX_CMDC_BIPHASE_CTRL1 ((0x004b << 2) + 0xfe333000) +//Bit 31:16, reserved +//Bit 15, ack_enable unsigned, default = 0, send +//Bit 14:8, reserved +//Bit 7:0, wait_threshold before ack unsigned, default = 0, send +#define EARC_TX_CMDC_BIPHASE_CTRL2 ((0x004c << 2) + 0xfe333000) +//Bit 31, comma_detection_enable unsigned, default = 0, comma detection +//Bit 30, manual_reset_enable unsigned, default = 0, manual reset select, 1: manual +//Bit 29, manual_reset_value unsigned, default = 0, manual reset control +//Bit 28:16, reserved +//Bit 15:0, comma_detection_threshold unsigned, default = 0, +#define EARC_TX_CMDC_BIPHASE_CTRL3 ((0x004d << 2) + 0xfe333000) +//Bit 31:0, cmdc_biphase_ctrl3 unsigned, default = 0, +#define EARC_TX_CMDC_DEVICE_ID_CTRL ((0x004e << 2) + 0xfe333000) +//Bit 31, apb_write unsigned, default = 0, apb bus wr/read +//Bit 30, apb_read unsigned, default = 0, apb bus wr/read +//Bit 29, apb_rw_done unsigned, default = 0, apb bus wr/read +//Bit 28, apb_rw_reset unsigned, default = 0, apb bus wr/read +//Bit 27:17, reserved +//Bit 16, hpb_rst_enable unsigned, default = 1, hpd rst enable +//Bit 15:8, apb_rwid unsigned, default = 0, apb bus wr/read +//Bit 7:0, apbrw_start_addr unsigned, default = 0, apb bus wr/read +#define EARC_TX_CMDC_DEVICE_WDATA ((0x004f << 2) + 0xfe333000) +//Bit 31:8, reserved +//Bit 7:0, apb_write_data unsigned, default = 0, apb bus wr/read +#define EARC_TX_CMDC_DEVICE_RDATA ((0x0050 << 2) + 0xfe333000) +//Bit 31:8, reserved +//Bit 7:0, apb_read_data unsigned, default = 0, apb bus wr/read +#define EARC_TX_CMDC_MASTER_CTRL ((0x0051 << 2) + 0xfe333000) +//Bit 31, master_cmd_rw unsigned, default = 0, 1 write 0 read +//Bit 30, master_hb_ignore unsigned, default =0, 0:wait hb issued before pkt cmd, 1: pkt cmd issued immediately +//Bit 29, master_idle unsigned, default = 0, master status +//Bit 28, master_cmd_soft_rst unsigned, default= 0, +//Bit 27:24, hb_cmd_cal_th unsigned, default= 0, +//Bit 23:16, master_cmd_count unsigned, default = 0, cmd count -1 +//Bit 15:8, master_cmd_id unsigned, default = 0, +//Bit 7:0, master_cmd_address unsigned, default = 0, +#define EARC_TX_ANA_CTRL0 ((0x0052 << 2) + 0xfe333000) +//Bit 31:0, reg_earctx_ana_ctrl0 //unsigned, RW, default = 0, +#define EARC_TX_ANA_CTRL1 ((0x0053 << 2) + 0xfe333000) +//Bit 31:0, reg_earctx_ana_ctrl1 //unsigned, RW, default = 0, +#define EARC_TX_ANA_CTRL2 ((0x0054 << 2) + 0xfe333000) +//Bit 31:0, reg_earctx_ana_ctrl2 //unsigned, RW, default = 0, +#define EARC_TX_ANA_CTRL3 ((0x0055 << 2) + 0xfe333000) +//Bit 31:0, reg_earctx_ana_ctrl3 //unsigned, RW, default = 0, +#define EARC_TX_ANA_CTRL4 ((0x0056 << 2) + 0xfe333000) +//Bit 31:0, reg_earctx_ana_ctrl4 //unsigned, RW, default = 0, +#define EARC_TX_ANA_CTRL5 ((0x0057 << 2) + 0xfe333000) +//Bit 31:0, reg_earctx_ana_ctrl5 //unsigned, RW, default = 0, +#define EARC_TX_ANA_STAT0 ((0x0058 << 2) + 0xfe333000) +//Bit 31:0, ro_ANA_status0 //unsigned, RO, default = 0, +#define EARC_TX_CMDC_STATUS0 ((0x0059 << 2) + 0xfe333000) +//Bit 31:0, ro_cmdc_status0 //unsigned, RO, default = 0, +#define EARC_TX_CMDC_STATUS1 ((0x005a << 2) + 0xfe333000) +//Bit 31:0, ro_cmdc_status1 ///unsigned, RO, default = 0, +#define EARC_TX_CMDC_STATUS2 ((0x005b << 2) + 0xfe333000) +//Bit 31:0, ro_cmdc_status2 ///unsigned, RO, default = 0, +#define EARC_TX_CMDC_STATUS3 ((0x005c << 2) + 0xfe333000) +//Bit 31:0, ro_cmdc_status3 ///unsigned, RO, default = 0, +#define EARC_TX_CMDC_STATUS4 ((0x005d << 2) + 0xfe333000) +//Bit 31:0, ro_cmdc_status4 ///unsigned, RO, default = 0, +#define EARC_TX_CMDC_STATUS5 ((0x005e << 2) + 0xfe333000) +//Bit 31:0, ro_cmdc_status5 ///unsigned, RO, default = 0, +#define EARC_TX_CMDC_STATUS6 ((0x005f << 2) + 0xfe333000) +//Bit 31 , ro_idle2_int unsigned, RO, default = 0 +//Bit 30 , ro_idle1_int unsigned, RO, default = 0 +//Bit 29 , ro_disc2_int unsigned, RO, default = 0 +//Bit 28 , ro_disc1_int unsigned, RO, default = 0 +//Bit 27 , ro_earc_int unsigned, RO, default = 0 +//Bit 26 , ro_hb_status_int unsigned, RO, default = 0 +//Bit 25 , ro_losthb_int unsigned, RO, default = 0 +//Bit 24 , ro_timeout_int unsigned, RO, default = 0 +//Bit 23 , ro_status_ch_int unsigned, RO, default = 0 +//Bit 22 , ro_int_recv_finished unsigned, RO, default = 0 +//Bit 21 , ro_int_rdata unsigned, RO, default = 0 +//Bit 20 , ro_int_recv_nack unsigned, RO, default = 0 +//Bit 19 , ro_int_recv_norsp unsigned, RO, default = 0 +//Bit 18 , ro_int_recv_unexp unsigned, RO, default = 0 +//Bit 17 , ro_int_recv_data unsigned, RO, default = 0 +//Bit 16 , ro_int_recv_ack unsigned, RO, default = 0 +//Bit 15 , ro_int_recv_ecc_err unsigned, RO, default = 0 +//Bit 14 , ro_int_recv_packet unsigned, RO, default = 0 +//Bit 13:0 , reserved +// +// Closing file: earc_tx_cmdc.h +// +//======================================================================== +// AUDIO EARCTX_DMAC - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe333400 +// ----------------------------------------------- +// +// Reading file: earctx_dmac.h +// +#define EARCTX_DMAC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333400) +//Bit 31, reg_top_reg_sync ,default = 0,Bit 3:0 sync to clk10m,pluse auto clear +//Bit 30, reg_top_soft_rst ,default = 0 +//Bit 29:26, reserved +//Bit 25:24, reg_debug_mux ,default = 0 +//Bit 23:21, reserved +//Bit 20, reg_slow_sync_scan_reg ,default = 0 +//Bit 19, reg_fe_sf_scan_reg ,default = 0 +//Bit 18, reg_fe_slow_sync_scan_reg ,default = 0 +//Bit 17, reg_top_sf_scan_reg ,default = 0 +//Bit 16, reg_top_slow_sync_scan_reg ,default = 0 +//Bit 15:4, reserved +//Bit 3, reg_spdif_tx_en_force ,default = 0,spdif_tx_en force enable +//Bit 2, reg_spdif_tx_en_force_value ,default = 0,spdif_tx_en force value +//Bit 1, reg_dmac_tx_en_force ,default = 0,dmac_tx_en force enable +//Bit 0, reg_dmac_tx_en_force_value ,default = 0,dmac_tx_en force value +#define EARCTX_MUTE_VAL ((0x0001 << 2) + 0xfe333400) +//Bit 31:0, reg_spdif_mute_val ,default = 0,when biahpase encode mute,the channel value,with reg_mute_l/reg_mute_r +#define EARCTX_SPDIFOUT_GAIN0 ((0x0002 << 2) + 0xfe333400) +//Bit 31:24, reg_gain_ch3 ,default = 0,channel 3 gain +//Bit 23:16, reg_gain_ch2 ,default = 0,channel 2 gain +//Bit 15:8, reg_gain_ch1 ,default = 0,channel 1 gain +//Bit 7:0, reg_gain_ch0 ,default = 0,channel 0 gain +#define EARCTX_SPDIFOUT_GAIN1 ((0x0003 << 2) + 0xfe333400) +//Bit 31:24, reg_gain_ch7 ,default = 0,channel 7 gain +//Bit 23:16, reg_gain_ch6 ,default = 0,channel 6 gain +//Bit 15:8, reg_gain_ch5 ,default = 0,channel 5 gain +//Bit 7:0, reg_gain_ch4 ,default = 0,channel 4 gain +#define EARCTX_SPDIFOUT_CTRL0 ((0x0004 << 2) + 0xfe333400) +//Bit 31, reg_work_start ,default = 0,biphase work start,pluse +//Bit 30, reg_work_clr ,default = 0,biphase work clear,pluse +//Bit 29, reg_rst_afifo_out_n ,default = 0,afifo out reset +//Bit 28, reg_rst_afifo_in_n ,default = 0,afifo in reset +//Bit 27, reg_hold_for_tdm ,default = 0,add delay to mathc TDM out when share buff +//Bit 26, reg_userdata_sel ,default = 0,user Bit select : 0 from reg_userdata_set 1 from data[29] +//Bit 25, reg_userdata_set ,default = 0 +//Bit 24, reg_chdata_sel ,default = 0,0 :from reg_chstst 1 from data[30] +//Bit 23, reserved +//Bit 22, reg_mute_l ,default = 0,r channel mute ,with reg_mute_val +//Bit 21, reg_mute_r ,default = 0,l channel mute ,with reg_mute_val +//Bit 20, reg_data_sel ,default = 0,0 data from 31Bit 1 data from 27bit +//Bit 19, reg_out_msb_first ,default = 0,0 lsb first 1 msb first +//Bit 18, reg_valid_sel ,default = 0,biphase encode valid Bit value sel : 0 from data 1 from reg_valid_set +//Bit 17, reg_valid_set ,default = 0,biphase encode valid Bit value +//Bit 16, reg_mute_hold_init_en ,default = 0,when c_mute_hold_last_err_corrt valid,clear work enable, initial biphase encode +//Bit 15:12, reserved +//Bit 0, reg_parity_mask ,default = 0,Bit 0 is initial parity value +#define EARCTX_SPDIFOUT_CTRL1 ((0x0005 << 2) + 0xfe333400) +//Bit 31, reg_eq_drc_sel ,default = 0,set 1 select eq_drc data +//Bit 30, reg_keep_req_ddr_init ,default = 0,reg_keep_req_ddr_init +//Bit 29:28, reserved +//Bit 27, reg_gain_en ,default = 0,gain enable +//Bit 26:24, reg_frddr_sel ,default = 0,from ddr selet +//Bit 23:16, reg_wait_cnt ,default = 0,wait some time when enalble set to 1 +//Bit 15:13, reserved +//Bit 12:8, reg_frddr_msb ,default = 0,msb position of data +//Bit 7, reg_force_start ,default = 0,set 1 no need ack from frddr to transmit channel status +//Bit 6:4, reg_frddr_type ,default = 0 +//Bit 3:0, reserved +#define EARCTX_SPDIFOUT_PREAMB ((0x0006 << 2) + 0xfe333400) +//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0 +//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8 +//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16 +//Bit 28:24, reserved +//Bit 23:16, reg_premable_X_value ,default = 0 +//Bit 15:8, reg_premable_Y_value ,default = 0 +//Bit 7:0, reg_premable_Z_value ,default = 0 +#define EARCTX_SPDIFOUT_SWAP ((0x0007 << 2) + 0xfe333400) +//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1 +//Bit 15, reg_init_send_en ,default = 0,send 01 squence some times after intial done from frddr set +//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 squence time ,valid when reg_init_send_en set 1 +#define EARCTX_ERR_CORRT_CTRL0 ((0x0008 << 2) + 0xfe333400) +//Bit 31:24, reserved +//Bit 23, reg_bch_in_reverse ,default = 0,bch input data generate in 24it data reverse +//Bit 22, reg_bch_out_ecc_reverse ,default = 0,bch output ecc reverse +//Bit 21, reg_bch_out_data_reverse ,default = 0,bch output data reverse +//Bit 20, reg_bch_out_ecc_msb ,default = 0,bch output ecc position +//Bit 19:17, reserved +//Bit 16, reg_ubit_fifo_init_n,default = 0,fifo in initial +//Bit 15:14, reserved +//Bit 13:12, reg_gain_shift ,default = 0,gain x 1/2/4/8 +//Bit 11, reg_mix_lr ,default = 0,l/r mix +//Bit 10:8, reg_spdifout_r_sel ,default = 0,r channel select +//Bit 7, reserved +//Bit 6:4, reg_spdifout_l_sel ,default = 0,l channel select +//Bit 3:0, reg_iu_interval ,default = 0,iu transmit interval +#define EARCTX_ERR_CORRT_CTRL1 ((0x0009 << 2) + 0xfe333400) +//Bit 31, reg_ubit_fifo_wr ,default = 0,iu data write enable,pluse,auto clr in reg.v +//Bit 30:8, reserved +//Bit 7:0, reg_ubit_fifo_wdata ,default = 0,iu data +#define EARCTX_ERR_CORRT_CTRL2 ((0x000a << 2) + 0xfe333400) +//Bit 31, reg_mute_clear ,default = 0,mute clear,pluse,auto clr in reg.v +//Bit 30, reg_mute_start ,default = 0,mute start,pluse,auto clr in reg.v +//Bit 29:28, reserved +//Bit 27:16, reg_mute_block_num ,default = 0,mute block number +//Bit 15:8, reg_mute_ch_Bit ,default = 0,mute Bit at channel statue which bit +//Bit 7:3, reserved +//Bit 2, reg_mute_data_sel ,default = 0,mute data sel: 0 data 1 reg_mute_data_value +//Bit 1:0, reg_mute_mode ,default = 0,0:always mute 1:mute block number and dis mute 2:mute bolck number and hold bus +#define EARCTX_ERR_CORRT_CTRL3 ((0x000b << 2) + 0xfe333400) +//Bit 31:30, reserved +//Bit 29, reg_bch_en ,default = 0,bch generate enable +//Bit 28:24, reg_bch_msb ,default = 0,bch data msb position in audio data +//Bit 23:0, reg_mute_data_value ,default = 0,mute value,only for audio data part +#define EARCTX_ERR_CORRT_CTRL4 ((0x000c << 2) + 0xfe333400) +//Bit 31, reg_ubit_fifo_lr_swap ,default = 0,//user Bit lr swap +//Bit 30, reg_ubit_fifo_lr_same ,default = 0,//l/r channel use same Bit user bit +//Bit 29:25, reg_data_msb ,default = 0,audio data msb postion in input data +//Bit 24, reg_data_rsv ,default = 0,audio data msb/lsb +//Bit 23, reg_ubit_value ,default = 0,user Bit value +//Bit 22, reg_vbit_value ,default = 0,valid Bit value +//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value +//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data +//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value +//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value +//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable +//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value +//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value +#define EARCTX_ERR_CORRT_STAT0 ((0x000d << 2) + 0xfe333400) +//Bit 31:0, ro_err_corrt_stat0 ,default = 0, +#define EARCTX_SPDIFOUT_CHSTS0 ((0x000e << 2) + 0xfe333400) +//Bit 31:0, reg_changel_a_status ,default =0,channel A status[31:0] +#define EARCTX_SPDIFOUT_CHSTS1 ((0x000f << 2) + 0xfe333400) +//Bit 31:0, reg_changel_a_status ,default =0,channel A status[63:32] +#define EARCTX_SPDIFOUT_CHSTS2 ((0x0010 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_a_status ,default =0,channel A status[95:64] +#define EARCTX_SPDIFOUT_CHSTS3 ((0x0011 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_a_status ,default =0,channel A status[127:96] +#define EARCTX_SPDIFOUT_CHSTS4 ((0x0012 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_a_status ,default =0,channel A status[159:128] +#define EARCTX_SPDIFOUT_CHSTS5 ((0x0013 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_a_status ,default =0,channel A status[191:160] +#define EARCTX_SPDIFOUT_CHSTS6 ((0x0014 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_b_status ,default =0,channel B status[31:0] +#define EARCTX_SPDIFOUT_CHSTS7 ((0x0015 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_b_status ,default =0,channel B status[63:32] +#define EARCTX_SPDIFOUT_CHSTS8 ((0x0016 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_b_status ,default =0,channel B status[95:64] +#define EARCTX_SPDIFOUT_CHSTS9 ((0x0017 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_b_status ,default =0,channel B status[127:96] +#define EARCTX_SPDIFOUT_CHSTSA ((0x0018 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_b_status ,default =0,channel B status[159:128] +#define EARCTX_SPDIFOUT_CHSTSB ((0x0019 << 2) + 0xfe333400) +//Bit 31:0, reg_changel_b_status ,default =0,channel B status[191:160] +#define EARCTX_FE_CTRL0 ((0x001a << 2) + 0xfe333400) +//Bit 31, reg_mute_hold_clr ,default = 0,clear mute hold statues,pluse, auto clr +//Bit 30, reg_work_enable ,default = 0,wore enable +//Bit 29, reg_dmac_invt ,default = 0,fe out invent +//Bit 28, reg_hold_time_en ,default = 0,hold min time enable +//Bit 27, reg_hold_soft_clr_en ,default = 0,0 auto clear hold at next valid 1 clear hold with reg_mute_hold_clr +//Bit 26:24, reg_hold_time_tick_sel ,default = 0,hold min time tick select +//Bit 23:0, reg_hold_min_time ,default = 0,hold min time +#define EARCTX_FE_STAT0 ((0x001b << 2) + 0xfe333400) +//Bit 31:0, ro_fe_stat0 ,default = 0, +#define EARCTX_SPDIFOUT_STAT ((0x001c << 2) + 0xfe333400) +//Bit 31:0, ro_spdifout_stat ,default = 0, +#define EARCTX_SPDIFOUT_CTRL2 ((0x001d << 2) + 0xfe333400) +//Bit 31:28, reserved +//Bit 27:16, reg_clr_by_init ,default = 0,reg_clr_by_init +//Bit 15:0 , reg_mask ,default = 0,reg_mask +#define EARCTX_SPDIFOUT_GAIN2 ((0x001e << 2) + 0xfe333400) +//Bit 31:0, spdifout_gain2 ,default = 0,spdifout gain2 +#define EARCTX_SPDIFOUT_GAIN3 ((0x001f << 2) + 0xfe333400) +//Bit 31:0, spdifout_gain3 ,default = 0,spdifout gain3 +#define EARCTX_SPDIFOUT_GAIN4 ((0x0020 << 2) + 0xfe333400) +//Bit 31:0, spdifout_gain4 ,default = 0,spdifout gain4 +#define EARCTX_SPDIFOUT_GAIN5 ((0x0021 << 2) + 0xfe333400) +//Bit 31:0, spdifout_gain5 ,default = 0,spdifout gain5 +// +// +// Closing file: earctx_dmac.h +// +//======================================================================== +// AUDIO EARCTX_TOP - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xff603600 +// ----------------------------------------------- +// +// Reading file: earctx_top.h +// +#define EARCTX_TOP_CTRL0 ((0x0000 << 2) + 0xff603600) +//Bit 31:18, reserved +//Bit 17:16, reg_earctx_debug_mux unsigned, default = 0, debug mux +//Bit 15, reg_slow_sync_scan_reg unsigned, default = 0, reg_slow_sync_scan_reg +//Bit 14:12, reserved +//Bit 11, reg_hdmi_hpd_invt unsigned, default = 0, hdmi_hpd invent +//Bit 10, reg_hdmi_hpd_value unsigned, default = 0, hdmi_hpd mux = 3,register value +//Bit 9:8, reg_hdmi_hpd_mux unsigned, default = 0, hdmi_hpd mux +//Bit 7, reg_earctx_hd_hpd_invt unsigned, default = 0, earctx_hd_hdp invent +//Bit 6, reg_earctx_hd_hpd_value unsigned, default = 0, earctx_hd_hdp mux = 3,register value +//Bit 5:4, reg_earctx_hd_hdp_mux unsigned, default = 0, earctx_hd_hdp mux +//Bit 3:2, reserved +//Bit 1, reg_earctx_force_mode_en unsigned, default = 0, force mode enale +//Bit 0, reg_earctx_force_mode unsigned, default = 0, force mode value +#define EARCTX_DMAC_INT_MASK ((0x0001 << 2) + 0xff603600) +//Bit 31:6, reserved +//Bit 5:0, reg_dmac_int_mask unsigned, default = 0, dmac int mask +#define EARCTX_DMAC_INT_PENDING ((0x0002 << 2) + 0xff603600) +//Bit 31:6, reserved +//Bit 5:0, reg_dmac_int_mask unsigned, default = 0, dmac int pending,read only +#define EARCTX_CMDC_INT_MASK ((0x0003 << 2) + 0xff603600) +//Bit 31:18, reserved +//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int mask +#define EARCTX_CMDC_INT_PENDING ((0x0004 << 2) + 0xff603600) +//Bit 31:18, reserved +//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int pending,read only +#define EARCTX_ANA_CTRL0 ((0x0005 << 2) + 0xff603600) +//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0 +#define EARCTX_ANA_CTRL1 ((0x0006 << 2) + 0xff603600) +//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0 +#define EARCTX_ANA_CTRL2 ((0x0007 << 2) + 0xff603600) +//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0 +#define EARCTX_ANA_STAT0 ((0x0008 << 2) + 0xff603600) +//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0 +// +// Closing file: earctx_top.h +// +//======================================================================== +// AUDIO EARCRX_CMDC - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe333800 +// ----------------------------------------------- +// +// Reading file: earc_rx_cmdc.h +// +#define EARC_RX_CMDC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333800) +//Bit 31 , idle2_int unsigned, default = 0, 1: enable +//Bit 30 , idle1_int unsigned, default = 0, 1: enable +//Bit 29 , disc2_int unsigned, default = 0, 1: enable +//Bit 28 , disc1_int unsigned, default = 0, 1: enable +//Bit 27 , earc_int unsigned, default = 0, 1: enable +//Bit 26 , hb_status_int unsigned, default = 0, 1: enable +//Bit 25 , losthb_int unsigned, default = 0, 1: enable +//Bit 24 , timeout_int unsigned, default = 0, 1: enable +//Bit 23 , status_ch_int unsigned, default = 0, 1: enable +//Bit 22 , int_rec_invalid_id unsigned, default = 0, 1: enable +//Bit 21 , int_rec_invalid_offset unsigned, default = 0, 1: enable +//Bit 20 , int_rec_unexp unsigned, default = 0, 1: enable +//Bit 19 , int_rec_ecc_err unsigned, default = 0, 1: enable +//Bit 18 , int_rec_parity_err unsigned, default = 0, 1: enable +//Bit 17 , int_recv_packet unsigned, default = 0, 1: enable +//Bit 16 , int_rec_time_out unsigned, default = 0, 1: enable +//Bit 15 , cmdc_debug0 unsigned, default = 0, 1: enable +//Bit 14 , cmdc_debug1 unsigned, default = 0, 1: enable +//Bit 13 , cmdc_debug2 unsigned, default = 0, 1: enable +//Bit 12:7 , reserved +//Bit 6 , mute_select unsigned, default = 0, 1: use bit5, 0: earc off +//Bit 5 , mute_contrl unsigned, default = 0, value of mannul mute control +//Bit 4:0 , reserved +#define EARC_RX_CMDC_TOP_CTRL1 ((0x0001 << 2) + 0xfe333800) +//Bit 31:13, reserved +//Bit 12:8, reg_scan_reg unsigned, RW, default = 0, +//Bit 7:5, reserved +//Bit 4:0, reg_top_soft_rst unsigned, RW, default = 0, +#define EARC_RX_CMDC_TOP_CTRL2 ((0x0002 << 2) + 0xfe333800) +//Bit 31, reset_idle2_int unsigned, default =0 +//Bit 30, reset_idle1_int unsigned, default =0 +//Bit 29, reset_disc2_int unsigned, default =0 +//Bit 28, reset_disc1_int unsigned, default =0 +//Bit 27, reset_earc_int unsigned, default =0 +//Bit 26, reset_hb_status_int unsigned, default =0 +//Bit 25, reset_losthb_int unsigned, default =0 +//Bit 24, reset_timeout_int unsigned, default =0 +//Bit 23, reset_status_ch_int unsigned, default =0 +//Bit 22, reset_int_rec_invalid_id unsigned, default =0 +//Bit 21, reset_int_rec_invalid_offset unsigned, default =0 +//Bit 20, reset_int_rec_unexp unsigned, default =0 +//Bit 19, reset_int_rec_ecc_err unsigned, default =0 +//Bit 18, reset_int_rec_parity_err unsigned, default =0 +//Bit 17, reset_int_recv_packet unsigned, default =0 +//Bit 16, reset_int_rec_time_out unsigned, default =0 +//Bit 15:0, reserved +#define EARC_RX_CMDC_TIMER_CTRL0 ((0x0003 << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0, +#define EARC_RX_CMDC_TIMER_CTRL1 ((0x0004 << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0, +#define EARC_RX_CMDC_TIMER_CTRL2 ((0x0005 << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0, +#define EARC_RX_CMDC_TIMER_CTRL3 ((0x0006 << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0, +#define EARC_RX_CMDC_VSM_CTRL0 ((0x0007 << 2) + 0xfe333800) +//Bit 31, sw_state_update unsigned, default = 0, XX +//Bit 30:28, sw_state unsigned, default = 0, XX +//Bit 27, arc_initiated unsigned, default = 0, XX +//Bit 26, arc_terminated unsigned, default = 0, XX +//Bit 25, arc_enable unsigned, default = 0, XX +//Bit 24, man_hpd unsigned, default = 0, XX +//Bit 23:22, hpd_sel unsigned, default = 0, XX +//Bit 21:20, hpd_sel_earc unsigned, default = 0, XX +//Bit 19, comma_cnt_rst unsigned, default = 0, XX +//Bit 18, timeout_status_rst unsigned, default = 0, XX +//Bit 17, losthb_status_rst unsigned, default = 0, XX +//Bit 16, force_rst unsigned, default = 0, XX +//Bit 15, auto_state unsigned, default = 0, XX +//Bit 14, cmdc_state_en unsigned, default = 0, XX +//Bit 13:0, reserved +#define EARC_RX_CMDC_VSM_CTRL1 ((0x0008 << 2) + 0xfe333800) +//Bit 31:12, max_count_th unsigned, default = 0, idle done timing +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, idle done timing +//Bit 6:4, time_sel unsigned, default = 0, idle done timing +//Bit 3:2, soft_rst_sel unsigned, default = 0, idle done timing +//Bit 1:0, enable_ctrl unsigned, default = 0, idle done timing +#define EARC_RX_CMDC_VSM_CTRL2 ((0x0009 << 2) + 0xfe333800) +//Bit 31:12, max_count_th unsigned, default = 0, comma off done timing +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, comma off done timing +//Bit 6:4, time_sel unsigned, default = 0, comma off done timing +//Bit 3:2, soft_rst_sel unsigned, default = 0, comma off done timing +//Bit 1:0, enable_ctrl unsigned, default = 0, comma off done timing +#define EARC_RX_CMDC_VSM_CTRL3 ((0x000a << 2) + 0xfe333800) +//Bit 31:12, max_count_th unsigned, default = 0, earc_time out timing +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, earc_time out timing +//Bit 6:4, time_sel unsigned, default = 0, earc_time out timing +//Bit 3:2, soft_rst_sel unsigned, default = 0, earc_time out timing +//Bit 1:0, enable_ctrl unsigned, default = 0, earc_time out timing +#define EARC_RX_CMDC_VSM_CTRL4 ((0x000b << 2) + 0xfe333800) +//Bit 31:12, max_count_th unsigned, default = 0, heartbeat lost timing +//Bit 11:8, reserved +//Bit 7, reg_soft_rst unsigned, default = 0, heartbeat lost timing +//Bit 6:4, time_sel unsigned, default = 0, heartbeat lost timing +//Bit 3:2, soft_rst_sel unsigned, default = 0, heartbeat lost timing +//Bit 1:0, enable_ctrl unsigned, default = 0, heartbeat lost timing +#define EARC_RX_CMDC_VSM_CTRL5 ((0x000c << 2) + 0xfe333800) +//Bit 31:16, reserved +//Bit 15:8, status_soft unsigned, default = 0, in earc heartbeat det timing +//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat det timing +//Bit 6, status_rst unsigned, default = 0, in earc heartbeat det timing +//Bit 5:4, reserved +//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat det timing +//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat det timing +#define EARC_RX_CMDC_VSM_CTRL6 ((0x000d << 2) + 0xfe333800) +//Bit 31:17, reserved +//Bit 16, cntl_hpd_sel unsigned, default = 0, in earc heartbeat det timing +//Bit 15:4, cntl_hpd_valid_width unsigned, default = 0, in earc heartbeat det timing +//Bit 3:0, cntl_hpd_glitch_width unsigned, default = 0, in earc heartbeat det timing +#define EARC_RX_CMDC_VSM_CTRL7 ((0x000e << 2) + 0xfe333800) +//Bit 31:0, vsm_ctrl7 unsigned, default = 0, +#define EARC_RX_CMDC_VSM_CTRL8 ((0x000f << 2) + 0xfe333800) +//Bit 31:0, vsm_ctrl8 unsigned, default = 0, +#define EARC_RX_CMDC_VSM_CTRL9 ((0x0010 << 2) + 0xfe333800) +//Bit 31:0, vsm_ctrl9 unsigned, default = 0, +#define EARC_RX_CMDC_SENDER_CTRL0 ((0x0011 << 2) + 0xfe333800) +//Bit 31:2, reserved +//Bit 1, hb_chg_conf_auto unsigned, default = 0, +//Bit 0, hb_chg_auto unsigned, default = 1, +#define EARC_RX_CMDC_PACKET_CTRL0 ((0x0012 << 2) + 0xfe333800) +//Bit 31, packet_mode_enable unsigned, default = 0, packet control +//Bit 30, free_enable unsigned, default = 0, packet control +//Bit 29, soft_rst_man unsigned, default = 0, packet control +//Bit 28:24, ready_th unsigned, default = 0, packet control +//Bit 23:20, reserved +//Bit 19:8, send_pre_th unsigned, default = 0, packet control +//Bit 7:5, reserved +//Bit 4, sw_state_update unsigned, default = 0, packet control +//Bit 3:0, sw_state unsigned, default = 0, packet control +#define EARC_RX_CMDC_PACKET_CTRL1 ((0x0013 << 2) + 0xfe333800) +//Bit 31, ecc_endian unsigned, default = 0, send +//Bit 30, pre_reg_st unsigned, default = 0, send +//Bit 29:21, reserved +//Bit 20:16, post_th unsigned, default = 0, send +//Bit 15:14, reserved +//Bit 13:8, pre_th unsigned, default = 0, +//Bit 7:0, post_flag unsigned, default = 0, +#define EARC_RX_CMDC_PACKET_CTRL2 ((0x0014 << 2) + 0xfe333800) +//Bit 31:0, pre_flag unsigned, default = 0, X +#define EARC_RX_CMDC_PACKET_CTRL3 ((0x0015 << 2) + 0xfe333800) +//Bit 31, cmdc_en unsigned, default = 0, XX +//Bit 30, cmdc_parity_mask unsigned, default = 0, XX +//Bit 29, imeout_en unsigned, default = 0, XX +//Bit 28, ecc_check_en unsigned, default = 0, XX +//Bit 27, rev_debug_en unsigned, default = 0, XX +//Bit 26:16, reserved +//Bit 15:0, timeout_th unsigned, default = 0, X +#define EARC_RX_CMDC_PACKET_CTRL4 ((0x0016 << 2) + 0xfe333800) +//Bit 31, ack_ignore unsigned, default = 0, XX +//Bit 30, cmdc_tail_check_mask unsigned, default = 0, XX +//Bit 29:20, reserved +//Bit 19:0, cmdc_packet_head unsigned, default = 0, XX +#define EARC_RX_CMDC_PACKET_CTRL5 ((0x0017 << 2) + 0xfe333800) +//Bit 31:24, rev_debug_mask unsigned, default = 0, XX +//Bit 23:20, reserved +//Bit 19:0, cmdc_packet_head_mask unsigned, default = 0, XX +#define EARC_RX_CMDC_PACKET_CTRL6 ((0x0018 << 2) + 0xfe333800) +//Bit 31:20, recv_pre_threshold unsigned, default = 0, packet control +//Bit 19:9, reserved +//Bit 8, rec_packet_d unsigned, default = 0, XX +//Bit 7, rec_parity_err_cnt unsigned, default = 0, XX +//Bit 6, rec_ecc_err_cnt unsigned, default = 0, XX +//Bit 5, rec_unexp_cnt unsigned, default = 0, XX +//Bit 4, rec_invalid_offset_cnt unsigned, default = 0, XX +//Bit 3, rec_invalid_id_cnt unsigned, default = 0, XX +//Bit 2, rec_timeout_cnt unsigned, default = 0, XX +//Bit 1, rec_w_cnt unsigned, default = 0, XX +//Bit 0, rec_r_cnt unsigned, default = 0, X +#define EARC_RX_CMDC_BIPHASE_CTRL0 ((0x0019 << 2) + 0xfe333800) +//Bit 31:24, reg_tns unsigned, default = 7, xx +//Bit 23:16, delay_th unsigned, default = 0, xx +//Bit 15:10, reserved +//Bit 9, send_ack_en unsigned, default = 0, xx +//Bit 8, sq_val_en unsigned, default = 0, XX +//Bit 7, biphase_send_soft_rst unsigned, default = 0, XX +//Bit 6, comma_soft_rst unsigned, default = 0, XX +//Bit 5, fifo_rst unsigned, default = 0, XX +//Bit 4, receiver_no_sender unsigned, default = 0, XX +//Bit 3, sender_free unsigned, default = 0, XX +//Bit 2, receiver_send unsigned, default = 0, XX +//Bit 1, receiver_earc unsigned, default = 0, XX +//Bit 0, receiver_free unsigned, default = 0, XX +#define EARC_RX_CMDC_BIPHASE_CTRL1 ((0x001a << 2) + 0xfe333800) +//Bit 31:16, reserved +//Bit 15, ack_val_en unsigned, default = 0, send +//Bit 14:8, reserved +//Bit 7:0, width unsigned, default = 0, send +#define EARC_RX_CMDC_BIPHASE_CTRL2 ((0x001b << 2) + 0xfe333800) +//Bit 31, ack_val_en unsigned, default = 0, send +//Bit 30:20, reserved +//Bit 19:16, ack_rate unsigned, default = 0, comma send +//Bit 15:0, width unsigned, default = 0, comma sen +#define EARC_RX_CMDC_BIPHASE_CTRL3 ((0x001c << 2) + 0xfe333800) +//Bit 31:0, biphase_ctrl3 unsigned, default = 0, +#define EARC_RX_CMDC_DEVICE_ID_CTRL ((0x001d << 2) + 0xfe333800) +//Bit 31, apb_write unsigned, default = 0, apb bus wr/read +//Bit 30, apb_read unsigned, default = 0, apb bus wr/read +//Bit 29, apb_w_r_done unsigned, default = 0, apb bus wr/read +//Bit 28, apb_w_r_reset unsigned, default = 0, apb bus wr/read +//Bit 27:16, reserved +//Bit 15:8, apb_w_r_id unsigned, default = 0, apb bus wr/read +//Bit 7:0, apb_w_r_start_addr unsigned, default = 0, apb bus wr/read +#define EARC_RX_CMDC_DEVICE_WDATA ((0x001e << 2) + 0xfe333800) +//Bit 31:8, reserved +//Bit 7:0, apb_write_data unsigned, default = 0, apb bus wr/rea +#define EARC_RX_CMDC_DEVICE_RDATA ((0x001f << 2) + 0xfe333800) +//Bit 31:8, reserved +//Bit 7:0, apb_read_data unsigned, default = 0, apb bus wr/rea +#define EARC_RX_ANA_CTRL0 ((0x0020 << 2) + 0xfe333800) +//Bit 31:0, ana_ctrl0 unsigned, default = 0, +#define EARC_RX_ANA_CTRL1 ((0x0021 << 2) + 0xfe333800) +//Bit 31:0, ana_ctrl1 unsigned, default = 0, +#define EARC_RX_ANA_CTRL2 ((0x0022 << 2) + 0xfe333800) +//Bit 31:0, ana_ctrl2 unsigned, default = 0, +#define EARC_RX_ANA_CTRL3 ((0x0023 << 2) + 0xfe333800) +//Bit 31:0, ana_ctrl3 unsigned, default = 0, +#define EARC_RX_ANA_CTRL4 ((0x0024 << 2) + 0xfe333800) +//Bit 31:0, ana_ctrl4 unsigned, default = 0, +#define EARC_RX_ANA_CTRL5 ((0x0025 << 2) + 0xfe333800) +//Bit 31:0, ana_ctrl5 unsigned, default = 0, +#define EARC_RX_ANA_STAT0 ((0x0026 << 2) + 0xfe333800) +//Bit 31:0, ro_ANA_status0 unsigned, RO, default = 0, +#define EARC_RX_CMDC_STATUS0 ((0x0027 << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0, +#define EARC_RX_CMDC_STATUS1 ((0x0028 << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status1 unsigned, RO, default = 0, +#define EARC_RX_CMDC_STATUS2 ((0x0029 << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status2 unsigned, RO, default = 0, +#define EARC_RX_CMDC_STATUS3 ((0x002a << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status3 unsigned, RO, default = 0, +#define EARC_RX_CMDC_STATUS4 ((0x002b << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status4 unsigned, RO, default = 0, +#define EARC_RX_CMDC_STATUS5 ((0x002c << 2) + 0xfe333800) +//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0, +#define EARC_RX_CMDC_STATUS6 ((0x002d << 2) + 0xfe333800) +//Bit 31, ro_idle2_int unsigned, RO, dfault =0 +//Bit 30, ro_idle1_int unsigned, RO, dfault =0 +//Bit 29, ro_disc2_int unsigned, RO, dfault =0 +//Bit 28, ro_disc1_int unsigned, RO, dfault =0 +//Bit 27, ro_earc_int unsigned, RO, dfault =0 +//Bit 26, ro_hb_status_int unsigned, RO, dfault =0 +//Bit 25, ro_losthb_int unsigned, RO, dfault =0 +//Bit 24, ro_timeout_int unsigned, RO, dfault =0 +//Bit 23, ro_status_ch_int unsigned, RO, dfault =0 +//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0 +//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0 +//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0 +//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0 +//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0 +//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0 +//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0 +//Bit 15:0, reserved +// +// Closing file: earc_rx_cmdc.h +// +//======================================================================== +// AUDIO EARCRX_DMAC - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe333c00 +// ----------------------------------------------- +// +// Reading file: earcrx_dmac.h +// +#define EARCRX_DMAC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333c00) +//Bit 31, reg_top_work_en unsigned, default = 0, top work enable +//Bit 30, reg_top_soft_rst unsigned, default = 0, top soft reset +//Bit 29:23, reserved +//Bit 22:20, reg_dmac_debug_sel unsigned, default = 0, dmac debug select +//Bit 19:18, reserved +//Bit 17, reg_dmac_valid_sel unsigned, default = 0, dmac sync without clk +//Bit 16, reg_dmac_without_clk unsigned, default = 0, dmac sync without clk +//Bit 15, reg_sf_sync_scan_reg unsigned, default = 0, rst_n soft reset scan reg +//Bit 14, reserved +//Bit 13, reg_slow_sync_scan_reg unsigned, default = 0, rst_n sync clk_slow scan reg +//Bit 12, reg_a_sync_scan_reg unsigned, default = 0, rst_n sync clk_analog scan reg +//Bit 11, reg_slow_auto_gate unsigned, default = 0, clk_slow auto gate +//Bit 10, reg_a_auto_gate unsigned, default = 0, clk_analog auto gate +//Bit 9:0, reserved +#define EARCRX_DMAC_SYNC_CTRL0 ((0x0001 << 2) + 0xfe333c00) +//Bit 31, reg_work_enable unsigned, default = 0, dmac sync module work enable +//Bit 30, reg_rst_afifo_out_n unsigned, default = 0, afifo out reset +//Bit 29, reg_rst_afifo_in_n unsigned, default = 0, afifo in reset +//Bit 28:17, reserved +//Bit 16, reg_ana_buf_data_sel_en unsigned, default = 0, data from analog delay enable +//Bit 15, reserved +//Bit 14:12, reg_ana_buf_data_sel unsigned, default = 0, delay cycles +//Bit 11, reserved +//Bit 10:8, reg_ana_clr_cnt unsigned, default = 0, valid last how many 0 will clear +//Bit 7, reserved +//Bit 6:4, reg_ana_set_cnt unsigned, default = 0, valid last how may 1 will set +//Bit 3:1, reserved +//Bit 0, reg_dmacin_phase unsigned, default = 0, dmac data invert +#define EARCRX_DMAC_SYNC_STAT0 ((0x0002 << 2) + 0xfe333c00) +//Bit 31:0, reg_dmac_sync_stat0 unsigned, default = 0 +#define EARCRX_SPDIFIN_SAMPLE_CTRL0 ((0x0003 << 2) + 0xfe333c00) +//Bit 31, reg_work_enable unsigned, default = 0, spdif in sample enable +//Bit 30, reg_spdifin_phase unsigned, default = 0, spdif in invert +//Bit 29, reg_debug_en unsigned, default = 0, debug single enable +//Bit 28, reg_width_sel unsigned, default = 0, 0 detect by max_width 1 detect by min_width +//Bit 27:23, reserved +//Bit 22:20, reg_sample_mode unsigned, default = 0, value +//Bit 19:0, reg_base_timer unsigned, default = 0, base timer to detect sample mode change +#define EARCRX_SPDIFIN_SAMPLE_CTRL1 ((0x0004 << 2) + 0xfe333c00) +//Bit 31, reg_force_sample_mode unsigned, default = 0, 0 auto detect sample mode 1 force a fixed sample mode with reg_sample_mode +//Bit 30, reserved +//Bit 29:20, reg_sample_mode0_timer_th unsigned, default = 0, mode0 threathold time +//Bit 19:10, reg_sample_mode1_timer_th unsigned, default = 0, mode1 threathold time +//Bit 9:0, reg_sample_mode2_timer_th unsigned, default = 0, mode2 threathold time +#define EARCRX_SPDIFIN_SAMPLE_CTRL2 ((0x0005 << 2) + 0xfe333c00) +//Bit 31:30, reserved +//Bit 29:20, reg_sample_mode3_timer_th unsigned, default = 0, mode3 threathold time +//Bit 19:10, reg_sample_mode4_timer_th unsigned, default = 0, mode4 threathold time +//Bit 9:0, reg_sample_mode5_timer_th unsigned, default = 0, mode5 threathold time +#define EARCRX_SPDIFIN_SAMPLE_CTRL3 ((0x0006 << 2) + 0xfe333c00) +//Bit 31:24, reg_sample_mode0_timer unsigned, default = 0, mode0 sample time +//Bit 23:16, reg_sample_mode1_timer unsigned, default = 0, mode1 sample time +//Bit 15:8, reg_sample_mode2_timer unsigned, default = 0, mode2 sample time +//Bit 7:0, reg_sample_mode3_timer unsigned, default = 0, mode3 sample time +#define EARCRX_SPDIFIN_SAMPLE_CTRL4 ((0x0007 << 2) + 0xfe333c00) +//Bit 31:24, reg_sample_mode4_timer unsigned, default = 0, mode4 sample time +//Bit 23:16, reg_sample_mode5_timer unsigned, default = 0, mode5 sample time +//Bit 15:8, reg_sample_mode6_timer unsigned, default = 0, mode6 sample time +//Bit 7:0, reserved +#define EARCRX_SPDIFIN_SAMPLE_CTRL5 ((0x0008 << 2) + 0xfe333c00) +//Bit 31, reg_sq_filt_en unsigned, default = 0, dmac_sqout filter enable +//Bit 30, reg_spdif_sqout_phase unsigned, default = 0, dmac_sqout invert +//Bit 29:27, reg_filter_tick_sel unsigned, default = 0, dmac_sqout filter tick select +//Bit 26:24, reg_filter_sel unsigned, default = 0, dmac_sqout filter select +//Bit 23:20, reserved +//Bit 19:0, reg_sq_filt_timer unsigned, default = 0, dmac_sqout filter tick +#define EARCRX_SPDIFIN_SAMPLE_STAT0 ((0x0009 << 2) + 0xfe333c00) +//Bit 31:0, reg_spdifin_sample_stat0 unsigned, default = 0 +#define EARCRX_SPDIFIN_SAMPLE_STAT1 ((0x000a << 2) + 0xfe333c00) +//Bit 31:0, reg_spdifin_sample_stat1 unsigned, default = 0 +#define EARCRX_SPDIFIN_MUTE_VAL ((0x000b << 2) + 0xfe333c00) +//Bit 31:0, reg_spdifin_mute_val unsigned, default = 0, spdif in mute value +#define EARCRX_SPDIFIN_CTRL0 ((0x000c << 2) + 0xfe333c00) +//Bit 31, reg_work_enable unsigned, default = 0, spdifin wore enable +//Bit 30, reg_chnum_sel unsigned, default = 0, 0 ch_num = 0~383 1 ch_num = 0~1 +//Bit 29:28, reserved +//Bit 27, reg_debug_en unsigned, default = 0, debug enable +//Bit 26, reg_chnum_en unsigned, default = 0, star add ch_cnt to ch_num +//Bit 25, reg_findpapb_en unsigned, default = 0, papb check enalbe +//Bit 24, reg_nonpcm2pcm_en unsigned, default = 0, nonpcm2pcm_th enable +//Bit 23:12, reg_nonpcm2pcm_th unsigned, default = 0, if long time didn't detect PaPb again,will generate irq +//Bit 11:8, reg_ch_status_sel unsigned, default = 0, for stat1/stat2 +//Bit 7, reg_mute_l unsigned, default = 0, mute channel l +//Bit 6, reg_mute_r unsigned, default = 0, mute channel r +//Bit 5:4, reserved +//Bit 3, reg_check_valid unsigned, default = 0, valid check enable +//Bit 2, reg_check_parity unsigned, default = 0, parity check enable +//Bit 1, reg_invert_data unsigned, default = 0, spdif data invert +//Bit 0, reserved +#define EARCRX_SPDIFIN_CTRL1 ((0x000d << 2) + 0xfe333c00) +//Bit 31:24, reserved +//Bit 31:24, reg_clr_internal_sts unsigned, default = 0, internal irq status clear +//Bit 23:12, reg_mute_block_check_thd unsigned, default = 0, mute block check time thd +//Bit 11:9, reg_mute_block_check_tick_sel unsigned, default = 0, mute block check tick sel +//Bit 8, reg_papb_ext_sync unsigned, default = 0, ext 0 sync check for papb +//Bit 7:0, reg_papb_ext_mask unsigned, default = 0, sync 0 mask +#define EARCRX_SPDIFIN_CTRL2 ((0x000e << 2) + 0xfe333c00) +//Bit 31:24, reg_mute_bit unsigned, default = 0, mute bit in channel st +//Bit 23:19, reg_mute_block_num unsigned, default = 0, mute min block number to declare +//Bit 18, reg_mute_lr_ch_sel unsigned, default = 0, mute bit in channel st L or R +//Bit 17, reg_mute_block_check_en unsigned, default = 0, mute block number check enable +//Bit 16, reg_earc_cps_chst_clr_en unsigned, default = 0, auto clear compress mode when channel status not compress +//Bit 15, reg_earc_cps_nonpcm2pcm_clr_en unsigned, default = 0, auto clear compress mode when nonpcm2pcm +//Bit 14, reg_earc_auto unsigned, default = 0, auto change earc/arc +//Bit 13, reg_earcin_papb_lr unsigned, default = 0, user l or r channle status to check papb +//Bit 12, reg_earcin_check_papb unsigned, default = 0, 0:data valid after 1 block;1: in 1st block if exit papb ,data valid after papb +//Bit 11, reg_earcin_start_papb unsigned, default = 0, start write toddr 1:from papb check,0 from preamble Z,valid when reg_earcin_check_papb set +//Bit 10, reg_formatchange_auto_rst unsigned, default = 0, auto reset will detect format change +//Bit 9, reg_earcin_cpsb_pcpd_sel unsigned, default = 0, compress B pcpd select : 1:next 4th subframe data 0:next sub frame data +//Bit 8:4, reg_earc_papb_msb unsigned, default = 0, papb msb position in data +//Bit 3, reg_earcin_spdif_force unsigned, default = 0, when in arc mode,spdif on force enable +//Bit 2, reg_earcin_spdif_force_set unsigned, default = 0, force value +//Bit 1, reg_earcin_mode_force unsigned, default = 0, earc mode force enable +//Bit 0, reg_earcin_mode_force_set unsigned, default = 0, force value +#define EARCRX_SPDIFIN_CTRL3 ((0x000f << 2) + 0xfe333c00) +//Bit 31:16, reg_earc_pa_value unsigned, default = 0, earc mode pa value +//Bit 15:0, reg_earc_pb_value unsigned, default = 0, earc mode pb value +#define EARCRX_SPDIFIN_STAT0 ((0x0010 << 2) + 0xfe333c00) +//Bit 31:0, reg_spdifin_stat0 unsigned, default = 0 +#define EARCRX_SPDIFIN_STAT1 ((0x0011 << 2) + 0xfe333c00) +//Bit 31:0, reg_spdifin_stat1 unsigned, default = 0 +#define EARCRX_SPDIFIN_STAT2 ((0x0012 << 2) + 0xfe333c00) +//Bit 31:0, reg_spdifin_stat2 unsigned, default = 0 +#define EARCRX_DMAC_UBIT_CTRL0 ((0x0013 << 2) + 0xfe333c00) +//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable +//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value +//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threthold +//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost +//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo +//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit +//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value +//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable +//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo +//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial +//Bit 4:0, reg_data_bit unsigned, default = 0, user bit position in data +#define EARCRX_IU_RDATA ((0x0014 << 2) + 0xfe333c00) +//Bit 31:8, reserved +//Bit 7:0, i_iu_rdata unsigned, default = 0, iu data,read only +#define EARCRX_DMAC_UBIT_STAT0 ((0x0015 << 2) + 0xfe333c00) +//Bit 31:0, reg_dmac_ubit_stat0 unsigned, default = 0 +#define EARCRX_ERR_CORRECT_CTRL0 ((0x0016 << 2) + 0xfe333c00) +//Bit 31, reg_work_enable unsigned, default = 0, err correct work enable +//Bit 30, reserved +//Bit 29, reg_rst_afifo_out_n unsigned, default = 0, reset afifo out side +//Bit 28, reg_rst_afifo_in_n unsigned, default = 0, reset afifo in side +//Bit 27, reg_lr_check unsigned, default = 0, enable lr_check +//Bit 26:7, reserved +//Bit 6, reg_bchout_data_ml unsigned, default = 0, bch output 16bit data msb is 27 or 19 +//Bit 5, reg_bchout_data_rsv unsigned, default = 0, bch output data revers +//Bit 4, reg_bchin_ecc_ml unsigned, default = 0, bch input ecc msb/lsb +//Bit 3, reg_bchin_ecc_rsv unsigned, default = 0, bch input ecc revers +//Bit 2, reg_bchin_data_rsv unsigned, default = 0, bch input data revers +//Bit 1, reg_force_set unsigned, default = 0, 0 off 1 compress audio mode +//Bit 0, reg_force_en unsigned, default = 0, force work mode enable +#define EARCRX_ERR_CORRECT_STAT0 ((0x0017 << 2) + 0xfe333c00) +//Bit 31:0, reg_err_correct_stat0 unsigned, default = 0 +#define EARCRX_ANA_RST_CTRL0 ((0x0018 << 2) + 0xfe333c00) +//Bit 31, reg_work_enable unsigned, default = 0, analog reset check work enable +//Bit 30, reg_ana_rst_sf_en unsigned, default = 0, analog reset from register enable +//Bit 29, reg_ana_rst_sf unsigned, default = 0, soft reset value +//Bit 28, reserved +//Bit 27:23, reg_new_format_pos_num unsigned, default = 0, when new format data in, hold reset after N posedge +//Bit 22:20, reg_dmacrx_div2_thd_tick_sel unsigned, default = 0, earcrx_div2 hold thresthold tick select +//Bit 19:0, reg_earcrx_div2_thd unsigned, default = 0, earcrx_div2 hold thresthold +#define EARCRX_ANA_RST_CTRL1 ((0x0019 << 2) + 0xfe333c00) +//Bit 31, reg_dmacrx_data_filt_en unsigned, default = 0, filter enable +//Bit 30:28, reg_dmacrx_data_filter_sel unsigned, default = 0, filter select +//Bit 27:25, reg_dmacrx_data_tick_sel unsigned, default = 0, filter tick sel +//Bit 24:16, reg_dmacrx_data_time unsigned, default = 0, filter tick time +//Bit 15, reg_dmacrx_sqout_filt_en unsigned, default = 0, filter enable +//Bit 14:12, reg_dmacrx_sqout_filter_sel unsigned, default = 0, filter select +//Bit 11:9, reg_dmacrx_sqout_tick_sel unsigned, default = 0, filter tick sel +//Bit 8:0, reg_dmacrx_sqout_time unsigned, default = 0, filter tick time +#define EARCRX_SPDIFIN_CTRL4 ((0x0020 << 2) + 0xfe333c00) +//Bit 31, reserved +//Bit 30, reg_add_ch_r unsigned, default = 0, reg_add_ch_r +//Bit 30, reg_bc_val0_en unsigned, default = 0, reg_bc_val0_en +//Bit 28:20, reg_stable_mask unsigned, default = 0, reg_stable_mask +//Bit 19:16, reg_stable_zcnt unsigned, default = 0, reg_stable_zcnt +//Bit 15:0 , reserved +#define EARCRX_SPDIFIN_CTRL5 ((0x0021 << 2) + 0xfe333c00) +//Bit 31, reg_st_timeout_sts_clr unsigned, default = 0, reg_st_timeout_sts_clr +//Bit 30:28, reserved +//Bit 27:16, reg_st_timeout_check_thd unsigned, default = 0, reg_st_timeout_check_thd +//Bit 15, reserved +//Bit 14:12, reg_st_timeout_check_tick_sel unsigned, default = 0, reg_st_timeout_check_tick_sel +//Bit 11, reg_st_timeout_check_en unsigned, default = 0, reg_st_timeout_check_en +//Bit 8:0, reg_stable_int_mask unsigned, default = 0, reg_stable_int_mask +#define EARCRX_SPDIFIN_CTRL6 ((0x0022 << 2) + 0xfe333c00) +//Bit 31:17, reserved +//Bit 16, reg_check_time_en unsigned, default = 0, reg_check_time_en +//Bit 15:0, reg_check_time_thd unsigned, default = 0, reg_check_time_thd +#define EARCRX_DMAC_SYNC_CTRL1 ((0x0023 << 2) + 0xfe333c00) +//Bit 31:19, reserved +//Bit 18, reg_auto_neg_int_en unsigned, default = 0, reg_auto_neg_int_en +//Bit 17, reg_auto_stable_clr unsigned, default = 0, reg_auto_stable_clr +//Bit 16, reg_auto_stable_en unsigned, default = 0, reg_auto_stable_en +//Bit 15:0, reg_auto_stable_thd unsigned, default = 0, reg_auto_stable_thd +#define EARCRX_SPDIFIN_SAMPLE_CTRL6 ((0x0024 << 2) + 0xfe333c00) +//Bit 31:18, reserved +//Bit 17, reg_hold_tri_sample unsigned, default = 0, reg_hold_tri_sample +//Bit 16, reg_sample_mode_filter_en unsigned, default = 0, reg_sample_mode_filter_en +//Bit 15:8, reg_stable_cyc_min unsigned, default = 0, reg_stable_cyc_min +//Bit 7:0, reg_stable_cyc_max unsigned, default = 0, reg_stable_cyc_max +// +// Closing file: earcrx_dmac.h +// +//======================================================================== +// AUDIO EARCRX_TOP - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe333e00 +// ----------------------------------------------- +// +// Reading file: earcrx_top.h +// +#define EARCRX_TOP_CTRL0 ((0x0000 << 2) + 0xfe333e00) +//Bit 31:10, reserved +//Bit 9:8, reg_top_debug_sel unsigned, default = 0, top debug select +//Bit 7, reg_spdif_rx_en_force unsigned, default = 0, force spdif_rx_en to reg_spdif_rx_en_force_value +//Bit 6, reg_spdif_rx_en_force_value unsigned, default = 0, value +//Bit 5, reg_spdif_rx_sqen_force unsigned, default = 0, force spdif_rx_sqen to reg_spdif_rx_sqe +//Bit 4, reg_spdif_rx_sqen_force_value unsigned, default = 0, value +//Bit 3, reg_dmacrx_en_force unsigned, default = 0, force dmacrx_en to reg_dmacrx_en_force_value +//Bit 2, reg_dmacrx_en_force_value unsigned, default = 0, value +//Bit 1, reg_dmacrx_sqen_force unsigned, default = 0, force dmacrx_sqen to reg_dmacrx_sqen_force_value +//Bit 0, reg_dmacrx_sqen_force_value unsigned, default = 0, value +#define EARCRX_DMAC_INT_MASK ((0x0001 << 2) + 0xfe333e00) +//Bit 31:30, reserved +//Bit 29:0, reg_dmac_int_mask unsigned, default = 0, dmac int mask +#define EARCRX_DMAC_INT_PENDING ((0x0002 << 2) + 0xfe333e00) +//Bit 31:30, reserved +//Bit 29:0, reg_dmac_int_mask unsigned, default = 0, dmac int pending,read only +#define EARCRX_CMDC_INT_MASK ((0x0003 << 2) + 0xfe333e00) +//Bit 31:16, reserved +//Bit 15:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int mask +#define EARCRX_CMDC_INT_PENDING ((0x0004 << 2) + 0xfe333e00) +//Bit 31:18, reserved +//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int pending,read only +#define EARCRX_ANA_CTRL0 ((0x0005 << 2) + 0xfe333e00) +//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0 +#define EARCRX_ANA_CTRL1 ((0x0006 << 2) + 0xfe333e00) +//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0 +#define EARCRX_ANA_STAT0 ((0x0007 << 2) + 0xfe333e00) +//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0 +#define EARCRX_PLL_CTRL0 ((0x0008 << 2) + 0xfe333e00) +//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0 +#define EARCRX_PLL_CTRL1 ((0x0009 << 2) + 0xfe333e00) +//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0 +#define EARCRX_PLL_CTRL2 ((0x000a << 2) + 0xfe333e00) +//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0 +#define EARCRX_PLL_CTRL3 ((0x000b << 2) + 0xfe333e00) +//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0 +#define EARCRX_PLL_STAT0 ((0x000c << 2) + 0xfe333e00) +//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0 +// +// Closing file: earcrx_top.h +// +//======================================================================== +// AUDIO RESAMPLEB - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe334000 +// ----------------------------------------------- +// +// Reading file: RESAMPLEB.h +// +#define AUDIO_RSAMPB_CTRL0 ((0x0000 << 2) + 0xfe334000) +//Bit 31:3 reserved +//Bit 2 reg_lock_rst //unsigned , default =0; +//Bit 1 reg_rsamp_rst //unsigned , default =0; +//Bit 0 reg_sw_rst //unsigned , default =0; +#define AUDIO_RSAMPB_CTRL1 ((0x0001 << 2) + 0xfe334000) +//Bit 31:27 reserved //unsigned , default =0; +//Bit 26 reg_watchdog_en //unsigned , default =0; +//Bit 25 reg_rsamp_rst_sel //unsigned , default =0; +//Bit 24 reg_module_bypas //unsigned , default =0; +//Bit 23:18 reg_gclk_ctrl //unsigned , default =0; +//Bit 17:13 reg_in_msb //unsigned , default =23; +//Bit 12 reg_output_en //unsigned , default =0; +//Bit 11 reg_rsamp_en //unsigned , default =0; +//Bit 10 reg_filt_en //unsigned , default =0; +//Bit 9 reg_post_en //unsigned , default =0; +//Bit 8 reg_inp_mux_mode //unsigned , default =0; +//Bit 7:4 reserved //unsigned , default =2; +//Bit 3:0 reg_inp_mux //unsigned , default =0; +#define AUDIO_RSAMPB_CTRL2 ((0x0002 << 2) + 0xfe334000) +//Bit 31:30 reserved //unsigned , default =0; +//Bit 29:24 reg_chx_size //unsigned , default =2; +//Bit 23:18 reserved //unsigned , default =0; +//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4 +//Bit 15:8 reg_filt_tap //unsigned , default =63; +//Bit 7:0 reg_intp_tap //unsigned , default =63; +#define AUDIO_RSAMPB_PHSINIT ((0x0003 << 2) + 0xfe334000) +//Bit 31:28 reserved //unsigned , default = 0; +//Bit 27:0 reg_init_phs //unsigned , default = 0; +#define AUDIO_RSAMPB_PHSSTEP ((0x0004 << 2) + 0xfe334000) +//Bit 31 reserved //unsigned , default = 0; +//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000 +#define AUDIO_RSAMPB_SHIFT ((0x0005 << 2) + 0xfe334000) +//Bit 31:24 reg_rsft_iir //unsigned , default = 23; +//Bit 23:16 reg_rsft_blnd //unsigned , default = 21; +//Bit 15:8 reg_rsft_sinc //unsigned , default = 31; +//Bit 7:0 reg_rsft_aa //unsigned , default = 31; +#define AUDIO_RSAMPB_ADJ_CTRL0 ((0x0006 << 2) + 0xfe334000) +//Bit 31:3 reserved //unsigned +//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0; +//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0; +//Bit 0 reg_rsamp_adj_en //unsigned , default = 0; +#define AUDIO_RSAMPB_ADJ_CTRL1 ((0x0007 << 2) + 0xfe334000) +//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8; +//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768; +#define AUDIO_RSAMPB_ADJ_SFT ((0x0008 << 2) + 0xfe334000) +//Bit 31:30 reserved //unsigned , default = 0; +//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0; +//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9; +//Bit 23:21 reserved //unsigned , default = 0; +//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1; +//Bit 15:13 reserved //unsigned , default = 0; +//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6; +//Bit 7:6 reserved //unsigned , default = 0; +//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12; +#define AUDIO_RSAMPB_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe334000) +//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000; +#define AUDIO_RSAMPB_ADJ_FORCE ((0x000a << 2) + 0xfe334000) +//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8; +#define AUDIO_RSAMPB_ADJ_KI_FORCE ((0x000b << 2) + 0xfe334000) +//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0; +#define AUDIO_RSAMPB_WATCHDOG_THRD ((0x000c << 2) + 0xfe334000) +//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000; +#define AUDIO_RSAMPB_RO_STATUS ((0x0010 << 2) + 0xfe334000) +//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]} +#define AUDIO_RSAMPB_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe334000) +//Bit 31:0 ro_rsamp_adj_freq +#define AUDIO_RSAMPB_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe334000) +//Bit 31:0 ro_det_diff_bak +#define AUDIO_RSAMPB_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe334000) +//Bit 31:0 ro_det_diff_dlt +#define AUDIO_RSAMPB_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe334000) +//Bit 31:0 ro_det_phase_err +#define AUDIO_RSAMPB_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe334000) +//Bit 31:0 ro_rsamp_ki_out +#define AUDIO_RSAMPB_RO_IN_CNT ((0x0016 << 2) + 0xfe334000) +//Bit 31:0 ro_rsamp_in_cnt +#define AUDIO_RSAMPB_RO_OUT_CNT ((0x0017 << 2) + 0xfe334000) +//Bit 31:0 ro_rsamp_out_cnt +#define AUDIO_RSAMPB_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe334000) +//Bit 31:0 ro_det_phase_err_var +#define AUDIO_RSAMPB_POST_COEF0 ((0x0020 << 2) + 0xfe334000) +//Bit 31:0 reg_post_coef0 //signed , default = 0; +#define AUDIO_RSAMPB_POST_COEF1 ((0x0021 << 2) + 0xfe334000) +//Bit 31:0 reg_post_coef1 //signed , default = 0; +#define AUDIO_RSAMPB_POST_COEF2 ((0x0022 << 2) + 0xfe334000) +//Bit 31:0 reg_post_coef2 //signed , default = 0; +#define AUDIO_RSAMPB_POST_COEF3 ((0x0023 << 2) + 0xfe334000) +//Bit 31:0 reg_post_coef3 //signed , default = 0; +#define AUDIO_RSAMPB_POST_COEF4 ((0x0024 << 2) + 0xfe334000) +//Bit 31:0 reg_post_coef4 //signed , default = 0; +#define AUDIO_RSAMPB_AA_COEF_ADDR ((0x0030 << 2) + 0xfe334000) +//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMPB_AA_COEF_DATA ((0x0031 << 2) + 0xfe334000) +//Bit 31:0 reg_aa_coef_data //signed , default = 0; +#define AUDIO_RSAMPB_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe334000) +//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0; +#define AUDIO_RSAMPB_SINC_COEF_DATA ((0x0041 << 2) + 0xfe334000) +//Bit 31:0 reg_sinc_coef_data //signed , default = 0; +// +// Closing file: RESAMPLEB.h +// +// +// Closing file: REG_LIST_AUDIO_RTL.h +// +// +// Reading file: REG_LIST_DSP_RTL.h +// +// synopsys translate_off +// synopsys translate_on +//======================================================================== +// DSPA - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe340000 +// ----------------------------------------------- +#define DSP_CFG0 ((0x0000 << 2) + 0xfe340000) +#define DSP_CFG1 ((0x0001 << 2) + 0xfe340000) +#define DSP_CFG2 ((0x0002 << 2) + 0xfe340000) +#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe340000) +#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe340000) +#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe340000) +#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe340000) +#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe340000) +#define DSP_IRQ_STS ((0x001f << 2) + 0xfe340000) +#define DSP_REMAP0 ((0x0020 << 2) + 0xfe340000) +#define DSP_REMAP1 ((0x0021 << 2) + 0xfe340000) +#define DSP_REMAP2 ((0x0022 << 2) + 0xfe340000) +#define DSP_STS0 ((0x0040 << 2) + 0xfe340000) +#define DSP_STS1 ((0x0041 << 2) + 0xfe340000) +#define DSP_STS2 ((0x0042 << 2) + 0xfe340000) +#define DSP_STS3 ((0x0043 << 2) + 0xfe340000) +#define DSP_STS4 ((0x0044 << 2) + 0xfe340000) +#define DSP_STS5 ((0x0045 << 2) + 0xfe340000) +#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe340000) +#define DSP_QIF_STS ((0x0081 << 2) + 0xfe340000) +#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe340000) +#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe340000) +#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe340000) +#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe340000) +#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe340000) +#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe340000) +//======================================================================== +// DSPB - Registers +//======================================================================== +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe350000 +// ----------------------------------------------- +#define DSPB_CFG0 ((0x0000 << 2) + 0xfe350000) +#define DSPB_CFG1 ((0x0001 << 2) + 0xfe350000) +#define DSPB_CFG2 ((0x0002 << 2) + 0xfe350000) +#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe350000) +#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe350000) +#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe350000) +#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe350000) +#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe350000) +#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe350000) +#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe350000) +#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe350000) +#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe350000) +#define DSPB_STS0 ((0x0040 << 2) + 0xfe350000) +#define DSPB_STS1 ((0x0041 << 2) + 0xfe350000) +#define DSPB_STS2 ((0x0042 << 2) + 0xfe350000) +#define DSPB_STS3 ((0x0043 << 2) + 0xfe350000) +#define DSPB_STS4 ((0x0044 << 2) + 0xfe350000) +#define DSPB_STS5 ((0x0045 << 2) + 0xfe350000) +#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe350000) +#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe350000) +#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe350000) +#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe350000) +#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe350000) +#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe350000) +#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe350000) +#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe350000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: REG_LIST_DSP_RTL.h +// +// +// Reading file: REG_LIST_DEMUX_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: REGISTER_BASE_ADDR = 0xfe034000 +// ----------------------------------------------- +// There are two instantiations under one CBUS slave. Each CBUS slave can support +// 256 registers. Each demux is allocated 128 registers so set the offset in +// the middle +// Copy this define but don't add a base address +#define SECOND_DEMUX_OFFSET_0 0x50 +#define THIRD_DEMUX_OFFSET_0 0xa0 +//======================================================================== +// STB TOP Registers (8'hf0 - 8'hf7) +//======================================================================== +// Bit 5:4 -- fec_sel_demux_2 +// Bit 3:2 -- fec_sel_demux_1 +// Bit 1:0 -- fec_sel_demux_0 +#define TS_TOP_CONFIG1 ((0x004f << 2) + 0xfe034000) +// Bit 31:24 -- file_m2ts_skip_bytes_hiu1 +// Bit 23:22 -- reserved +// Bit 21 -- ts_hiu_enable_hiu1 +// Bit 20:16 -- fec_clk_div_hiu1 +// Bit 15:8 -- TS_package_length_sub_1_hiu1 (default : 187) +// Bit 7:0 -- fec_sync_byte_hiu1 (default : 0x47) +#define TS_HIU1_CONFIG ((0x004e << 2) + 0xfe034000) +//bit[1:0]-- stb_recorder2_sel +#define STB_RECORDER2_CNTL ((0x00ee << 2) + 0xfe034000) +// bit [11]-- s2p2_disable +// bit [10:7]-- s2p2_clk_div +// bit [6:0]-- fec_serial_control_2 +#define STB_S2P2_CONFIG ((0x00ef << 2) + 0xfe034000) +// bit 30:28 -- ciplus_o_sel +// bit 27:26 -- ciplus_i_sel +// bit 25 -- use FAIL fro TS2 +// bit 24 -- use FAIL fro TS1 +// bit 23 -- use FAIL fro TS0 +// bit 22 -- invert fec_error for S2P1 +// bit 21 -- invert fec_data for S2P1 +// bit 20 -- invert fec_sync for S2P1 +// bit 19 -- invert fec_valid for S2P1 +// bit 18 -- invert fec_clk for S2P1 +// bit 17:16 -- fec_s_sel for S2P1 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved +// Bit 15 -- enable_des_pl_clk +// Bit 14 -- ts_out_select[3] +// Bit 13 -- use FAIL for TS3 +// Bit 12:10 -- ts_out_select[2:0], 0-TS0, 1-TS1, 2-TS2, 3-TS3, 4-S2P2, 5-S2P1, 6-S2P0, 7-File, 8-File1 +// bit 9:8 -- des_i_sel 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved +// bit 7 -- enable_des_pl +// bit 6 -- invert fec_error for S2P0 +// bit 5 -- invert fec_data for S2P0 +// bit 4 -- invert fec_sync for S2P0 +// bit 3 -- invert fec_valid for S2P0 +// bit 2 -- invert fec_clk for S2P0 +// bit 1:0 -- fec_s_sel for S2P0 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved +#define STB_TOP_CONFIG ((0x00f0 << 2) + 0xfe034000) +// 31:28 - s2p1_clk_div +// 27:24 - s2p0_clk_div +// 23 - s2p1_disable +// 22 - s2p0_disable +// 21 - Reserved +// 20 -- TS_OUT_error_INVERT +// 19 -- TS_OUT_data_INVERT +// 18 -- TS_OUT_sync_INVERT +// 17 -- TS_OUT_valid_INVERT +// 16 -- TS_OUT_clk_INVERT +// 15:8 -- TS_package_length_sub_1 (default : 187) +// 7:0 -- fec_sync_byte (default : 0x47) +#define TS_TOP_CONFIG ((0x00f1 << 2) + 0xfe034000) +// Bit 25:24 -- transport_scrambling_control_odd_2 // should be 3 +// Bit 23:16 -- file_m2ts_skip_bytes +// Bit 15:8 -- des_out_dly +// Bit 7:6 -- transport_scrambling_control_odd // should be 3 +// Bit 5 -- ts_hiu_enable +// Bit 4:0 -- fec_clk_div +#define TS_FILE_CONFIG ((0x00f2 << 2) + 0xfe034000) +// Bit 19:14 -- des_2 ts pl state -- Read Only +// Bit 13:8 -- des ts pl state -- Read Only +// Bit 3:0 PID index to 8 PID to get key-set +// auto increse after TS_PL_PID_DATA read/write +#define TS_PL_PID_INDEX ((0x00f3 << 2) + 0xfe034000) +// Bit 13 -- PID match disble +// Bit 12:0 -- PID +#define TS_PL_PID_DATA ((0x00f4 << 2) + 0xfe034000) +#define COMM_DESC_KEY0 ((0x00f5 << 2) + 0xfe034000) +#define COMM_DESC_KEY1 ((0x00f6 << 2) + 0xfe034000) +#define COMM_DESC_KEY_RW ((0x00f7 << 2) + 0xfe034000) +// CI+ Register defines +// Bits[31:0] of the key +#define CIPLUS_KEY0 ((0x00f8 << 2) + 0xfe034000) +// Bits[63:32] of the key +#define CIPLUS_KEY1 ((0x00f9 << 2) + 0xfe034000) +// Bits[95:64] of the key +#define CIPLUS_KEY2 ((0x00fa << 2) + 0xfe034000) +// Bits[127:96] of the key +#define CIPLUS_KEY3 ((0x00fb << 2) + 0xfe034000) +// bit[5] write AES IV B value +// bit[4] write AES IV A value +// bit[3] write AES B key +// bit[2] write AES A key +// bit[1] write DES B key +// bit[0] write DES A key +#define CIPLUS_KEY_WR ((0x00fc << 2) + 0xfe034000) +// [15:8] TS out delay. This controls the rate at which the CIplus module drives TS out +// [3] General enable for the ciplus module +// [2] AES CBC disable (default should be 0 to enable AES CBC) +// [1] AES Enable +// [0] DES Eanble +#define CIPLUS_CONFIG ((0x00fd << 2) + 0xfe034000) +// bit[31:28] AES IV endian +// bit[27:24] AES message out endian +// bit[23:20] AES message in endian +// bit[19:16] AES key endian +// bit[15:11] unused +// bit[10:8] DES message out endian +// bit[6:4] DES message in endian +// bit[2:0] DES key endian +#define CIPLUS_ENDIAN ((0x00fe << 2) + 0xfe034000) +// bit 15:8 - des_out_dly_2 +// bit 7 - reserved +// Bit 6-- enable_des_pl_clk_2 +// bit 5 - enable_des_pl_2 +// bit 4:2 -- use_des_2 bit[2] -- demux0, bit[3] -- demux1, bit[4] -- demux2 +// bit 1:0 -- des_i_sel_2 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved +#define COMM_DESC_2_CTL ((0x00ff << 2) + 0xfe034000) +// +// NOTE: Don't process the demux registers using the standard create_headers.... perl script. +// Instead, since the demux has multiple instances (and many registers) use a separate +// script to create a separate stb_define.h for C-code. +//======================================================================== +// STB Registers (8'h00 - 8'h4f) +// +//======================================================================== +// STB registers are 8'h0x +// Bit 15:0 -- version number : 0x0002 (v0.01) +// Bit 16 -- fec_select[3] +// Bit 15 -- fec_core_select 1 - select descramble output +// Bit 14:12 - fec_select[2:0] 0-TS0, 1-TS1, 2-TS2, 3-TS3, 4-S2P2, 5-S2P1, 6-S2P0, 7-File, 8-File1 +// Bit 11 -- FEC_CLK +// Bit 10 -- SOP +// Bit 9 -- D_VALID +// Bit 8 -- D_FAIL +// Bit 7:0 -- D_DATA 7:0 +// bit 31 -- enable_free_clk_fec_data_valid +// bit 30 -- enable_free_clk_stb_reg +// bit 29 -- always_use_pes_package_length +// bit 28 -- disable_pre_incomplete_section_fix +// bit 27 -- pointer_field_multi_pre_en +// bit 26 -- ignore_pre_incomplete_section +// bit 25 -- video2_enable +// bit 24:22 -- video2_type +// bit 21 -- do_not_trust_pes_package_length +// bit 20 (bit 4) -- Bypass use recoder path +// bit 19 (bit 3) -- clear_PID_continuity_counter_valid +// bit 18 (bit 2) -- Disable Splicing +// bit 17 (bit 1) -- Insert PES_STRONG_SYNC in Audio PES +// bit 16 (bit 0) -- Insert PES_STRONG_SYNC in Video PES +// Bit 15 - do not trust section length +// Bit 14 - om cmd push even zero +// Bit 13 - set_buff_ready_even_not_busy +// Bit 12 - SUB, OTHER PES interrupt at beginning of PES +// Bit 11 - discard_av_package -- for ts_recorder use only +// Bit 10 - ts_recorder_select 0:after PID filter 1:before PID filter +// Bit 9 - ts_recorder_enable +// Bit 8 - (table_id == 0xff) means section_end +// Bit 7 - do not send uncomplete section +// Bit 6 - do not discard duplicate package +// Bit 5 - search SOP when trasport_error_indicator +// Bit 4 - stb demux enable +// Bit 3 - do not reset state machine on SOP +// Bit 2 - search SOP when error happened ( when ignore_fail_n_sop, will have this case) +// Bit 1 - do not use SOP input ( check FEC sync byte instead ) +// Bit 0 - ignore fec_error bit when non sop ( check error on SOP only) +// bit 15:8 demux package length - 1 ( default : 187 ) +// bit 7:0 default is 0x47 +// bit 31:16 -- filter memory write data hi[31:16] +// bit 15:0 -- filter memory write data low [15:0] +// bit 31:24 -- advanced setting hi +// bit 23:16 -- advanced setting low +// bit 15 -- filter memory write data request +// bit 7:0 -- filter memory write addr +// bit 13:8 demux state -- read only +// bit 7:4 -- maxnum section filter compare address +// bit 3:0 -- maxnum PID filter compare address +// bit 15 - transport_error_indicator +// bit 14 - payload_unit_start_indicator +// bit 13 - transport_priority +// bit 12:0 - PID +// bit 7:6 transport_scrambling_control +// bit 5:4 adaptation_field_control +// bit 3:0 continuity_counter +// bit 15:12 -- om_cmd_count (read only) +// bit 11:9 -- overflow_count // bit 11:9 -- om_cmd_wr_ptr (read only) +// bit 8:6 -- om_overwrite_count // bit 8:6 -- om_cmd_rd_ptr (read only) +// bit 5:3 -- type_stb_om_w_rd (read only) +// bit 2 -- unit_start_stb_om_w_rd (read only) +// bit 1 -- om_cmd_overflow (read only) +// bit 0 -- om_cmd_pending (read) +// bit 0 -- om_cmd_read_finished (write) +// bit 15:9 // bit 14:8 -- count_stb_om_w_rd (read only) +// bit 8:0 // bit 7:0 -- start_stb_om_wa_rd (read only) +// bit 11:0 -- offset for section data +// bit 31:16 -- base address for section buffer group 0 (*0x400 to get real address) +// bit 15:0 -- base address for section buffer group 1 (*0x400 to get real address) +// bit 31:16 -- ba2e address for section buffer group 2 (*0x400 to get real address) +// bit 15:0 -- base address for section buffer group 3 (*0x400 to get real address) +// bit 3:0 -- section buffer size for group 0 (bit used, for example, 10 means 1K) +// bit 7:4 -- section buffer size for group 1 +// bit 11:8 -- section buffer size for group 2 +// bit 15:12 -- section buffer size for group 3 +// section buffer busy status for buff 31:0 ( Read Only ) +// section buffer write status for buff 31:0 -- Read +// clear buffer status ( buff READY and BUSY ) -- write +// bit 4:0 -- SEC_BUFFER_INDEX RW +// bit 12:8 -- SEC_BUFFER_NUMBER for the INDEX buffer Read_Only +// bit 14 -- output_section_buffer_valid +// bit 15 -- section_reset_busy (Read Only) +// bit 9:5 -- BYPASS PID number +// bit 4:0 -- PCR PID number +// bit 15:0 -- stream_id filter bit enable +// bit 7:0 -- stream_id filter target +// bit 12 -- PCR_EN +// bit 11:0 -- PCR90K_DIV +// bit 31:0 -- PCR[31:0] R/W +// bit 31:0 -- VPTS[31:0] R/W +// bit 31:0 -- VDTS[31:0] R/W +// bit 31:0 -- APTS[31:0] R/W +// bit 31:0 -- SPTS[31:0] R/W +// read -- status, write 1 clear status +// bit 15 -- SUB_PTS[32] +// bit 14 -- AUDIO_PTS[32] +// bit 13 -- VIDEO_DTS[32] +// bit 12 -- VIDEO_PTS[32] +// bit 3 -- sub_pts_ready +// bit 2 -- audio_pts_ready +// bit 1 -- video_dts_ready +// bit 0 -- video_pts_ready +// bit 3:0 -- +// 0 -- adaptation_field_length[7:0], adaption_field_byte_1[7:0] +// 1 -- stream_id[7:0], pes_header_bytes_left[7:0] +// 2 -- pes_package_bytes_left[15:0] +// 3 -- pes_ctr_byte[7:0], pes_flag_byte[7:0] +// +// read only +// bit[31] -- no_match_record_en +// bit[30:16] - reserved +// default : 0x807f +// bit 15:9 -- MAX OM DMA COUNT (default: 0x40) +// bit 8:0 -- LAST ADDR OF OM ADDR (default: 127) +// 15:0 WRITE 1 CLEAR to clear interrupt source +//12 -- INPUT_TIME_OUT +//11 -- PCR_ready +//10 -- audio_splicing_point +// 9 -- video_splicing_point +// 8 -- other_PES_int +// 7 -- sub_PES_int +// 6 -- discontinuity +// 5 -- duplicated_pack_found +// 4 -- New PDTS ready +// 3 -- om_cmd_buffer ready for access +// 2 -- section buffer ready +// 1 -- transport_error_indicator +// 0 -- TS ERROR PIN +// Bit 5:3 - demux om write endian control for bypass +// Bit 2:0 - demux om write endian control for section +// When Bit 31 - 1 write will indicate all type use sepertate endian (Write Only) +// Bit 23:21 - demux om write endian control for OTHER_PES_PACKET +// Bit 20:18 - demux om write endian control for SCR_ONLY_PACKET +// Bit 17:15 - demux om write endian control for SUB_PACKET +// Bit 14:12 - demux om write endian control for AUDIO_PACKET +// Bit 11:9 - demux om write endian control for VIDEO_PACKET +// +// When Bit 31 - 0 write will indicate all type else use Bit 8:6 +// Bit 8:6 - demux om write endian control for else +// Bit 10:9 -- sel DPTS_wr_ptr: 00 from parserA ; 01 from parserB +// Bit 8:7 -- use hi_bsf interface: 01 sel hiu0; 10 sel hiu1 +// Bit 6:2 - Reserved +// Bit 1 - enable_halt_ts_hiu_fix +// Bit 0 - enable_halt_ts_hiu +// bit 15:0 -- base address for section buffer start (*0x10000 to get real base) +// bit 11 -- mask bit for OTHER_PES_AHB_DMA_EN +// bit 10 -- mask bit for SUB_AHB_DMA_EN +// bit 9 -- mask bit for BYPASS_AHB_DMA_EN +// bit 8 -- mask bit for SECTION_AHB_DMA_EN +// bit 7 -- mask bit for recoder stream +// bit 6:0 -- mask bit for each type +// bit 31:0 -- vb_wr_ptr for video PDTS +// bit 31:0 -- ab_wr_ptr for audio PDTS +// bit 20:0 -- SB_WRITE_PTR (sb_wr_ptr << 3 == byte write position) +// bit 19:0 -- SB_START (sb_start << 12 == byte address); +// bit 20:0 -- SB_SIZE (sb_size << 3 == byte size, 16M maximun) +// bit 31:0 -- sb_wr_ptr for sub PES +// bit 31:16 -- ob_wr_ptr for other PES +// bit 20:0 -- OB_WRITE_PTR (ob_wr_ptr << 3 == byte write position) +// bit 19:0 -- OB_START (ob_start << 12 == byte address); +// bit 20:0 -- OB_SIZE (ob_size << 3 == byte size, 16M maximun) +// bit 31:0 -- ob_wr_ptr for sub PES +// 15:0 DEMUX interrupt MASK +// 9 -- splicing_point +// 8 -- other_PES_int +// 7 -- sub_PES_int +// 6 -- discontinuity +// 5 -- duplicated_pack_found +// 4 -- New PDTS ready +// 3 -- om_cmd_buffer ready for access +// 2 -- section buffer ready +// 1 -- transport_error_indicator +// 0 -- TS ERROR PIN +// 31:16 VIDEO PID filter data +//15 -- splicing VIDEO PID change enable +//14:10 -- VIDEO PID FILTER ADDRESS +// 9 -- PES splicing active (Read Only) +// 8 -- splicing active (Read Only) +// 7:0 splicing countdown (Read Only) +// 31:16 AUDIO PID filter data +//15 -- splicing AUDIO PID change enable +//14:10 -- AUDIO PID FILTER ADDRESS +// 9 -- PES splicing active (Read Only) +// 8 -- splicing active (Read Only) +// 7:0 splicing countdown (Read Only) +// 23:16 M2TS_SKIP_BYTES +// 15:8 LAST TS PACKAGE BYTE COUNT (Read Only) +// 7:0 PACKAGE BYTE COUNT (Read Only) +// 15:0 2 bytes strong sync add to PES +// bit 15 -- stb_om_ren +// bit 14:11 -- reserved +// bit 10:0 -- OM_DATA_RD_ADDR +// bit 15:0 -- OM_DATA_RD +// AUTO STOP SETTING for 32 channels +// 4-nbits per channel +// when write +// bit 3 -- set section active +// bit 2:0 -- auto stop after count (0 means never stop) +// when read +// bit 3 -- current active status (1 - active, 0 - stopped ) +// bit 2:0 -- count down to auto stop +// section 31:24 +// section 23:16 +// section 15:8 +// section 7:0 +// bit 31:0 reset channel status - each bit reset each channel +// read -- 32 channel status +// bit 4 -- video_stamp_use_dts +// bit 3 -- audio_stamp_sync_1_en +// bit 2 -- audio_stamp_insert_en +// bit 1 -- video_stamp_sync_1_en +// bit 0 -- video_stamp_insert_en +// Write : Bit[4:0] secter filter number for reset +// Read : select according to output_section_buffer_valid : +// per bit per section buffer valid status +// or section_buffer_ignore +// bit[31:0] - channel_reset_timeout_disable +// bit[31] - no_match_reset_timeout_disable +// bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count +// bit[31:0] - channel_packet_count_disable +// bit[31] - no_match_packet_count_disable +// bit[30:0] input_packet_count +// bit[31:0] channel_record_enable +// bit[31:0] channel_process_enable +// bit[31:24] small_sec_size ((n+1) * 256 Bytes) +// bit[23:16] small_sec_rd_ptr +// bit[15:8] small_sec_wr_ptr +// bit[7:2] reserved +// bit[1] small_sec_wr_ptr_wr_enable +// bit[0] small_section_enable +// bit[31:0] small_sec_start_addr +// synopsys translate_off +// synopsys translate_on +// +// Closing file: REG_LIST_DEMUX_RTL.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ./REG_LIST_RTL.h +// +// +// Reading file: ./vcbus_regs.h +// +// synopsys translate_off +// synopsys translate_on +//=========================================================================== +//=========================================================================== +// +// Reading file: rdma_regs.h +// +//=========================================================================== +// RDMA registers 0x00 - 0xff +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: RDMA_VCBUS_BASE = 0x11 +// ----------------------------------------------- +// Bit 31: 0 RW AHB start address for manual start DMA +#define RDMA_AHB_START_ADDR_MAN ((0x1100 << 2) + 0xff000000) +// Bit 31: 0 RW AHB end address for manual start DMA +#define RDMA_AHB_END_ADDR_MAN ((0x1101 << 2) + 0xff000000) +// Bit 31: 0 RW AHB start address for auto start source 1 +#define RDMA_AHB_START_ADDR_1 ((0x1102 << 2) + 0xff000000) +// Bit 31: 0 RW AHB end address for auto start source 1 +#define RDMA_AHB_END_ADDR_1 ((0x1103 << 2) + 0xff000000) +// Bit 31: 0 RW AHB start address for auto start source 2 +#define RDMA_AHB_START_ADDR_2 ((0x1104 << 2) + 0xff000000) +// Bit 31: 0 RW AHB end address for auto start source 2 +#define RDMA_AHB_END_ADDR_2 ((0x1105 << 2) + 0xff000000) +// Bit 31: 0 RW AHB start address for auto start source 3 +#define RDMA_AHB_START_ADDR_3 ((0x1106 << 2) + 0xff000000) +// Bit 31: 0 RW AHB end address for auto start source 3 +#define RDMA_AHB_END_ADDR_3 ((0x1107 << 2) + 0xff000000) +// Bit 31: 0 RW AHB start address for auto start source 4 +#define RDMA_AHB_START_ADDR_4 ((0x1108 << 2) + 0xff000000) +// Bit 31: 0 RW AHB end address for auto start source 4 +#define RDMA_AHB_END_ADDR_4 ((0x1109 << 2) + 0xff000000) +// Bit 31: 0 RW AHB start address for auto start source 5 +#define RDMA_AHB_START_ADDR_5 ((0x110a << 2) + 0xff000000) +// Bit 31: 0 RW AHB end address for auto start source 5 +#define RDMA_AHB_END_ADDR_5 ((0x110b << 2) + 0xff000000) +// Bit 31: 0 RW AHB start address for auto start source 6 +#define RDMA_AHB_START_ADDR_6 ((0x110c << 2) + 0xff000000) +// Bit 31: 0 RW AHB end address for auto start source 6 +#define RDMA_AHB_END_ADDR_6 ((0x110d << 2) + 0xff000000) +// Bit 31: 0 RW AHB start address for auto start source 7 +#define RDMA_AHB_START_ADDR_7 ((0x110e << 2) + 0xff000000) +// Bit 31: 0 RW AHB end address for auto start source 7 +#define RDMA_AHB_END_ADDR_7 ((0x110f << 2) + 0xff000000) +// Auto start DMA control: +// Bit 31:24 RW ctrl_enable_int_3. Interrupt inputs enable mask for source 3. +// Bit 23:16 RW ctrl_enable_int_2. Interrupt inputs enable mask for source 2. +// Bit 15: 8 RW ctrl_enable_int_1. Interrupt inputs enable mask for source 1. +// Bit 7 RW ctrl_cbus_write_3. Register read/write mode for auto-start 3. 1=Register write; 0=Register read. +// Bit 6 RW ctrl_cbus_write_3. Register read/write mode for auto-start 2. 1=Register write; 0=Register read. +// Bit 5 RW ctrl_cbus_write_3. Register read/write mode for auto-start 1. 1=Register write; 0=Register read. +// Bit 4 R Rsrv. +// Bit 3 RW ctrl_cbus_addr_incr_3. 1=Incremental register access for auto-start 3; 0=Non-incremental (individual) register access. +// Bit 2 RW ctrl_cbus_addr_incr_2. 1=Incremental register access for auto-start 2; 0=Non-incremental (individual) register access. +// Bit 1 RW ctrl_cbus_addr_incr_1. 1=Incremental register access for auto-start 1; 0=Non-incremental (individual) register access. +// Bit 0 R Rsrv. +#define RDMA_ACCESS_AUTO ((0x1110 << 2) + 0xff000000) +#define RDMA_ACCESS_AUTO2 ((0x1111 << 2) + 0xff000000) +// Manual start DMA control: +// Bit 31: 3 R Rsrv. +// Bit 2 RW ctrl_cbus_write_man. Register read/write mode for manual-start. 1=Register write; 0=Register read. +// Bit 1 RW ctrl_cbus_addr_incr_man. 1=Incremental register access for manual-start; 0=Non-incremental (individual) register access. +// Bit 0 W ctrl_start_man. Write 1 to this bit to manual-start DMA. This bit always read back 0. +#define RDMA_ACCESS_MAN ((0x1113 << 2) + 0xff000000) +// RDMA general control: +// Bit 31:25 R Rsrv. +// Bit 24 W ctrl_clr_rdma_done_int. Write 1 to reset rdma_int level to 0. No need to clear this bit. +// Bit 23:19 R Rsrv. +// Bit 18:13 R Rsrv. +// Bit 12: 7 R Rsrv. +// Bit 6 RW ctrl_ddr_urgent. +// Bit 5: 4 RW ctrl_ahb_wr_burst_size. 0=ABH write request burst size 16; +// 1=ABH write request burst size 24; +// 2=ABH write request burst size 32; +// 3=ABH write request burst size 48. +// Bit 3: 2 RW ctrl_ahb_rd_burst_size. 0=ABH read request burst size 16; +// 1=ABH read request burst size 24; +// 2=ABH read request burst size 32; +// 3=ABH read request burst size 48. +// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register. +// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock. +#define RDMA_CTRL ((0x1114 << 2) + 0xff000000) +// Read only. +// Bit 31:29 R Rsrv. +// Bit 28 R rdma_done_int. +// Bit 27:25 R Rsrv. +// Bit 24:18 R ahb_wrfifo_cnt. FIFO for buffering CBus read data to be sent to AHB +// Bit 17:11 R ahb_rdfifo_cnt. FIFO for buffering data read from AHB. +// Bit 10: 8 R ddr_req_st. =0 -- Idle; !=0 -- AHB interfacing ongoing. +// Bit 7: 4 R curr_req. Latest requests that is being/been serviced. E.g. 0000=Idle; 0010=Latest serviced request is Req 1. +// Bit 3: 0 R req_latch. Requests that are yet to be serviced. E.g. 0000=No request; 0001=Req 0 waiting; 1100=Req 2 and 3 waiting. +#define RDMA_STATUS ((0x1115 << 2) + 0xff000000) +#define RDMA_STATUS2 ((0x1116 << 2) + 0xff000000) +#define RDMA_STATUS3 ((0x1117 << 2) + 0xff000000) +#define RDMA_ACCESS_AUTO4 ((0x1118 << 2) + 0xff000000) +#define RDMA_SRAM_CNTL ((0x1120 << 2) + 0xff000000) +#define RDMA_SRAM_REGADDR ((0x1121 << 2) + 0xff000000) +#define RDMA_SRAM_REGDATA ((0x1122 << 2) + 0xff000000) +#define RDMA_AUTO_SRC1_SEL ((0x1123 << 2) + 0xff000000) +#define RDMA_AUTO_SRC2_SEL ((0x1124 << 2) + 0xff000000) +#define RDMA_AUTO_SRC3_SEL ((0x1125 << 2) + 0xff000000) +#define RDMA_AUTO_SRC4_SEL ((0x1126 << 2) + 0xff000000) +#define RDMA_AUTO_SRC5_SEL ((0x1127 << 2) + 0xff000000) +#define RDMA_AUTO_SRC6_SEL ((0x1128 << 2) + 0xff000000) +#define RDMA_AUTO_SRC7_SEL ((0x1129 << 2) + 0xff000000) +// +// Closing file: rdma_regs.h +// +// +// Reading file: vpu_vdin0_regs.h +// +// synopsys translate_off +// synopsys translate_on +//=========================================================================== +// VDIN +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: VDIN0_VCBUS_BASE = 0x12 +// ----------------------------------------------- +// +// Reading file: vpu_vdin_regs.h +// +// synopsys translate_off +// synopsys translate_on +//=========================================================================== +// VDIN +//=========================================================================== +#define VDIN_SCALE_COEF_IDX ((0x1200 << 2) + 0xff000000) +#define VDIN_SCALE_COEF ((0x1201 << 2) + 0xff000000) +//bit 31, mpeg_to_vdin_sel, 0: mpeg source to NR directly, 1: mpeg source pass through here +//bit 30, mpeg_field info which can be written by software +//Bit 29, force go_field, pulse signal +//Bit 28, force go_line, pulse signal +//Bit 27, enable mpeg_go_field input signal +//Bit 26:20, hold lines +//Bit 19, delay go_field function enable +//Bit 18:12, delay go_field line number +//Bit 11:10, component2 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in +//Bit 9:8, component1 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in +//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in +//Bit 5, input window selection function enable +//Bit 4, enable VDIN common data input, otherwise there will be no video data input +//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI. +#define VDIN_COM_CTRL0 ((0x1202 << 2) + 0xff000000) +//Bit 28:16 active_max_pix_cnt, readonly +//Bit 12:0 active_max_pix_cnt_shadow, readonly +#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS ((0x1203 << 2) + 0xff000000) +//Bit 28:16 go_line_cnt, readonly +//Bit 12:0 active_line_cnt, readonly +#define VDIN_LCNT_STATUS ((0x1204 << 2) + 0xff000000) +//Readonly +//Bit [14:3] lfifo_buf_cnt +//Bit 2, vdin_direct_done status +//Bit 1, vdin_nr_done status +//Bit 0, field +#define VDIN_COM_STATUS0 ((0x1205 << 2) + 0xff000000) +//Readonly +//Bit 31, vdi4 fifo overflow +//Bit 29:24, vdi3_asfifo_cnt +//Bit 23, vdi3 fifo overflow +//Bit 21:16, vdi3_asfifo_cnt +//Bit 15, vdi2 fifo overflow +//Bit 13:8, vdi2_asfifo_cnt +//Bit 7, vdi1 fifo overflow +//Bit 5:0, vdi1_asfifo_cnt +#define VDIN_COM_STATUS1 ((0x1206 << 2) + 0xff000000) +//Bit 28:16 go_line_cnt_shadow, readonly +//Bit 12:0 active_line_cnt_shadow, readonly +#define VDIN_LCNT_SHADOW_STATUS ((0x1207 << 2) + 0xff000000) +//each 8bit asfifo_ctrl is following: +//Bit 7, DE enable +//Bit 6, go field enable +//Bit 5, go line enable +//Bit 4, if true, negative active input vsync +//Bit 3, if true, negative active input hsync +//Bit 2, vsync soft reset fifo enable +//Bit 1, overflow status clear +//Bit 0 asfifo soft reset, level signal +//Bit 7:0 vdi1 asfifo_ctrl +//Bit 23:16 vdi2 asfifo_ctrl +#define VDIN_ASFIFO_CTRL0 ((0x1208 << 2) + 0xff000000) +//Bit 7:0 vdi3 asfifo_ctrl +//Bit 23:16 vdi4 asfifo_ctrl +#define VDIN_ASFIFO_CTRL1 ((0x1209 << 2) + 0xff000000) +//Bit 28:16 input width minus 1, after the window function +//Bit 12:0 output width minus 1 +#define VDIN_WIDTHM1I_WIDTHM1O ((0x120a << 2) + 0xff000000) +//Bit 20:17 prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode, +// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0 +//Bit 16:15 sp422_mode, special mode for the component1 and component2, 00: normal case, 01: 32 64 32, 10: 0 64 64 0, 11: 16 96 16 +//Bit 14:8, hsc_ini_pixi_ptr, signed data, only useful when short_lineo_en is true +//Bit 7, prehsc_en +//Bit 6, hsc_en, +//Bit 5, hsc_short_lineo_en, short line output enable +//Bit 4, hsc_nearest_en +//Bit 3, hsc_phase0_always_en +//Bit 2:0, hsc_bank_length +#define VDIN_SC_MISC_CTRL ((0x120b << 2) + 0xff000000) +//Bit 28:24, integer portion +//Bit 23:0, fraction portion +#define VDIN_HSC_PHASE_STEP ((0x120c << 2) + 0xff000000) +//Bit 30:29 hscale rpt_p0_num +//Bit 28:24 hscale ini_rcv_num +//Bit 23:0 hscale ini_phase +#define VDIN_HSC_INI_CTRL ((0x120d << 2) + 0xff000000) +//Read only +//Bit 23, vdi7 fifo overflow +//Bit 21:16, vdi7_asfifo_cnt +//Bit 15, vdi6 fifo overflow +//Bit 13:8, vdi6_asfifo_cnt +//Bit 7, vdi5 fifo overflow +//Bit 5:0, vdi5_asfifo_cnt +#define VDIN_COM_STATUS2 ((0x120e << 2) + 0xff000000) +//Bit 25:16 asfifo decimate control +//Bit 25, if true, decimation counter sync with first valid DE in the field, +//otherwise the decimation counter is not sync with external signal +//Bit 24, decimation de enable +//Bit 23:20, decimation phase, which counter value use to decimate, +//Bit 19:16, decimation number, 0: not decimation, 1: decimation 2, 2: decimation 3 .... +//Bit 7:0 vdi5 asfifo_ctrl +#define VDIN_ASFIFO_CTRL2 ((0x120f << 2) + 0xff000000) +//Bit 7, highlight_en +//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix +//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing +//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing +//Bit 1 mat1 conversion matrix enable +//Bit 0 mat0 conversion matrix enable +#define VDIN_MATRIX_CTRL ((0x1210 << 2) + 0xff000000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define VDIN_MATRIX_COEF00_01 ((0x1211 << 2) + 0xff000000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define VDIN_MATRIX_COEF02_10 ((0x1212 << 2) + 0xff000000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define VDIN_MATRIX_COEF11_12 ((0x1213 << 2) + 0xff000000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define VDIN_MATRIX_COEF20_21 ((0x1214 << 2) + 0xff000000) +//BIt 18:16 conv_rs +//Bit 12:0 coef22 +#define VDIN_MATRIX_COEF22 ((0x1215 << 2) + 0xff000000) +//Bit 26:16 offset0 +//Bit 10:0 offset1 +#define VDIN_MATRIX_OFFSET0_1 ((0x1216 << 2) + 0xff000000) +//Bit 10:0 offset2 +#define VDIN_MATRIX_OFFSET2 ((0x1217 << 2) + 0xff000000) +//Bit 26:16 pre_offset0 +//Bit 10:0 pre_offset1 +#define VDIN_MATRIX_PRE_OFFSET0_1 ((0x1218 << 2) + 0xff000000) +//Bit 10:0 pre_offset2 +#define VDIN_MATRIX_PRE_OFFSET2 ((0x1219 << 2) + 0xff000000) +//12:0 lfifo_buf_size +#define VDIN_LFIFO_CTRL ((0x121a << 2) + 0xff000000) +#define VDIN_COM_GCLK_CTRL ((0x121b << 2) + 0xff000000) +//12:0 VDIN input interface width minus 1, before the window function, after the de decimation +#define VDIN_INTF_WIDTHM1 ((0x121c << 2) + 0xff000000) +//Bit 15 //default== 0, urgent_ctrl_en +//Bit 14 //default== 0, urgent_wr, if true for write buffer +//Bit 13 //default== 0, out_inv_en +//Bit 12 //default == 0, urgent_ini_value +//Bit 11:6 //default == 0, up_th up threshold +//Bit 5:0 //default == 0, dn_th dn threshold +#define VDIN_LFIFO_URG_CTRL ((0x121e << 2) + 0xff000000) +//Bit 8, 1: discard data before line fifo, 0: normal mode +//Bit 7:0 Write chroma canvas address +#define VDIN_WR_CTRL2 ((0x121f << 2) + 0xff000000) +//Bit 31:30 hconv_mode, Applicable only to bit[13:12]=0 or 2. 0: Output every even pixels' CbCr; +// 1: Output every odd pixels' CbCr; +// 2: Output an average value per even&odd pair of pixels; +// 3: Output all CbCr. (This does NOT apply to bit[13:12]=0 -- 4:2:2 mode.) +//Bit 29 no_clk_gate: disable vid_wr_mif clock gating function. +//Bit 28 clear write response counter in the vdin write memory interface +//Bit 27 eol_sel, 1: use eol as the line end indication, 0: use width as line end indication in the vdin write memory interface +//Bit 26 vcp_nr_en. Only used in VDIN0. NOT used in VDIN1. +//Bit 25 vcp_wr_en. Only used in VDIN0. NOT used in VDIN1. +//Bit 24 vcp_in_en. Only used in VDIN0. NOT used in VDIN1. +//Bit 23 vdin frame reset enble, if true, it will provide frame reset during go_field(vsync) to the modules after that +//Bit 22 vdin line fifo soft reset enable, meaning, if true line fifo will reset during go_field (vsync) +//Bit 21 vdin direct write done status clear bit +//Bit 20 vdin NR write done status clear bit +//Bit 18 swap_cbcr. Applicable only to bit[13:12]=2. 0: Output CbCr (NV12); 1: Output CrCb (NV21). +//Bit 17:16 vconv_mode, Applicable only to bit[13:12]=2. 0: Output every even lines' CbCr; +// 1: Output every odd lines' CbCr; +// 2: Reserved; +// 3: Output all CbCr. +//Bit 13:12 vdin write format, 0: 4:2:2 to luma canvas, 1: 4:4:4 to luma canvas, +// 2: Y to luma canvas, CbCr to chroma canvas. For NV12/21, also define Bit 31:30, 17:16, and bit 18. +//Bit 11 vdin write canvas double buffer enable, means the canvas address will be latched by vsync before using +//Bit 10 1: disable ctrl_reg write pulse which will reset internal counter. when bit 11 is 1, this bit should be 1. +//Bit 9 vdin write request urgent +//Bit 8 vdin write request enable +//Bit 7:0 Write luma canvas address +#define VDIN_WR_CTRL ((0x1220 << 2) + 0xff000000) +//Bit 29, if true, horizontal reverse +//Bit 28:16 start +//Bit 12:0 end +#define VDIN_WR_H_START_END ((0x1221 << 2) + 0xff000000) +//Bit 29, if true, vertical reverse +//Bit 28:16 start +//Bit 15:13 field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode +//Bit 12:0 end +#define VDIN_WR_V_START_END ((0x1222 << 2) + 0xff000000) +//Bit 24:20, integer portion +//Bit 19:0, fraction portion +#define VDIN_VSC_PHASE_STEP ((0x1223 << 2) + 0xff000000) +//Bit 23, vsc_en, vertical scaler enable +//Bit 22 if true, repeat last line while scaling, otherwise use the dummy data to extend the input picture +//Bit 21 vsc_phase0_always_en, when scale up, you have to set it to 1 +//Bit 20:16 ini skip_line_num +//Bit 15:0 vscaler ini_phase +#define VDIN_VSC_INI_CTRL ((0x1224 << 2) + 0xff000000) +//Bit 28:16, vshrink input height minus 1 +//Bit 12:0, scaler input height minus 1 +#define VDIN_SCIN_HEIGHTM1 ((0x1225 << 2) + 0xff000000) +//Bit 23:16, dummy component 0 +//Bit 15:8, dummy component 1 +//Bit 7:0, dummy component 2 +#define VDIN_DUMMY_DATA ((0x1226 << 2) + 0xff000000) +//Read only +//Bit 29:20 component 0 +//Bit 19:10 component 1 +//Bit 9:0 component 2 +#define VDIN_MATRIX_PROBE_COLOR ((0x1228 << 2) + 0xff000000) +//Bit 23:16 component 0 +//Bit 15:8 component 1 +//Bit 7:0 component 2 +#define VDIN_MATRIX_HL_COLOR ((0x1229 << 2) + 0xff000000) +//28:16 probe x, postion +//12:0 probe y, position +#define VDIN_MATRIX_PROBE_POS ((0x122a << 2) + 0xff000000) +#define VDIN_CHROMA_ADDR_PORT ((0x122b << 2) + 0xff000000) +#define VDIN_CHROMA_DATA_PORT ((0x122c << 2) + 0xff000000) +// +#define VDIN_CM_BRI_CON_CTRL ((0x122d << 2) + 0xff000000) +//Bit 17 clk_cyc_cnt_clr, if true, clear this register +//Bit 16 if true, use vpu clock to count one line, otherwise use actually hsync to count line_cnt +//Bit 15:0 line width using vpu clk +#define VDIN_GO_LINE_CTRL ((0x122f << 2) + 0xff000000) +//Bit 31:24 hist_pix_white_th, larger than this th is counted as white pixel +//Bit 23:16 hist_pix_black_th, less than this th is counted as black pixel +//Bit 11 hist_34bin_only, 34 bin only mode, including white/black +//Bit 10:9 ldim_stts_din_sel, 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din +//Bit 8 ldim_stts_en +//Bit 6:5 hist_dnlp_low the real pixels in each bins got by VDIN_DNLP_HISTXX should multiple with 2^(dnlp_low+3) +//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din +//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window +//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback +#define VDIN_HIST_CTRL ((0x1230 << 2) + 0xff000000) +//Bit 28:16 hist_hstart horizontal start value to define hist window +//Bit 12:0 hist_hend horizontal end value to define hist window +#define VDIN_HIST_H_START_END ((0x1231 << 2) + 0xff000000) +//Bit 28:16 hist_vstart vertical start value to define hist window +//Bit 12:0 hist_vend vertical end value to define hist window +#define VDIN_HIST_V_START_END ((0x1232 << 2) + 0xff000000) +//Bit 15:8 hist_max maximum value +//Bit 7:0 hist_min minimum value +//read only +#define VDIN_HIST_MAX_MIN ((0x1233 << 2) + 0xff000000) +//Bit 31:0 hist_spl_rd +//counts for the total luma value +//read only +#define VDIN_HIST_SPL_VAL ((0x1234 << 2) + 0xff000000) +//Bit 21:0 hist_spl_pixel_count +//counts for the total calculated pixels +//read only +#define VDIN_HIST_SPL_PIX_CNT ((0x1235 << 2) + 0xff000000) +//Bit 31:0 hist_chroma_sum +//counts for the total chroma value +//read only +#define VDIN_HIST_CHROMA_SUM ((0x1236 << 2) + 0xff000000) +//Bit 31:16 higher hist bin +//Bit 15:0 lower hist bin +//0-255 are splited to 64 bins evenly, and VDIN_DNLP_HISTXX +//are the statistic number of pixels that within each bin. +//VDIN_DNLP_HIST00[15:0] counts for the first bin +//VDIN_DNLP_HIST00[31:16] counts for the second bin +//VDIN_DNLP_HIST01[15:0] counts for the third bin +//VDIN_DNLP_HIST01[31:16] counts for the fourth bin +//etc... +//read only +#define VDIN_DNLP_HIST00 ((0x1237 << 2) + 0xff000000) +#define VDIN_DNLP_HIST01 ((0x1238 << 2) + 0xff000000) +#define VDIN_DNLP_HIST02 ((0x1239 << 2) + 0xff000000) +#define VDIN_DNLP_HIST03 ((0x123a << 2) + 0xff000000) +#define VDIN_DNLP_HIST04 ((0x123b << 2) + 0xff000000) +#define VDIN_DNLP_HIST05 ((0x123c << 2) + 0xff000000) +#define VDIN_DNLP_HIST06 ((0x123d << 2) + 0xff000000) +#define VDIN_DNLP_HIST07 ((0x123e << 2) + 0xff000000) +#define VDIN_DNLP_HIST08 ((0x123f << 2) + 0xff000000) +#define VDIN_DNLP_HIST09 ((0x1240 << 2) + 0xff000000) +#define VDIN_DNLP_HIST10 ((0x1241 << 2) + 0xff000000) +#define VDIN_DNLP_HIST11 ((0x1242 << 2) + 0xff000000) +#define VDIN_DNLP_HIST12 ((0x1243 << 2) + 0xff000000) +#define VDIN_DNLP_HIST13 ((0x1244 << 2) + 0xff000000) +#define VDIN_DNLP_HIST14 ((0x1245 << 2) + 0xff000000) +#define VDIN_DNLP_HIST15 ((0x1246 << 2) + 0xff000000) +#define VDIN_DNLP_HIST16 ((0x1247 << 2) + 0xff000000) +#define VDIN_DNLP_HIST17 ((0x1248 << 2) + 0xff000000) +#define VDIN_DNLP_HIST18 ((0x1249 << 2) + 0xff000000) +#define VDIN_DNLP_HIST19 ((0x124a << 2) + 0xff000000) +#define VDIN_DNLP_HIST20 ((0x124b << 2) + 0xff000000) +#define VDIN_DNLP_HIST21 ((0x124c << 2) + 0xff000000) +#define VDIN_DNLP_HIST22 ((0x124d << 2) + 0xff000000) +#define VDIN_DNLP_HIST23 ((0x124e << 2) + 0xff000000) +#define VDIN_DNLP_HIST24 ((0x124f << 2) + 0xff000000) +#define VDIN_DNLP_HIST25 ((0x1250 << 2) + 0xff000000) +#define VDIN_DNLP_HIST26 ((0x1251 << 2) + 0xff000000) +#define VDIN_DNLP_HIST27 ((0x1252 << 2) + 0xff000000) +#define VDIN_DNLP_HIST28 ((0x1253 << 2) + 0xff000000) +#define VDIN_DNLP_HIST29 ((0x1254 << 2) + 0xff000000) +#define VDIN_DNLP_HIST30 ((0x1255 << 2) + 0xff000000) +#define VDIN_DNLP_HIST31 ((0x1256 << 2) + 0xff000000) +//Bit 31, local dimming statistic enable +//Bit 28, eol enable +//Bit 27:25, vertical line overlap number for max finding +//Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix +//Bit 20, 1,2,1 low pass filter enable before max/hist statistic +//Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION +//Bit 15, 1: region read index auto increase per read to VDIN_LDIM_STTS_HIST_READ_REGION +//Bit 6:0, region read index +//`define VDIN_LDIM_STTS_HIST_REGION_IDX 8'h57 +//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89 +//hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart +//hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend +//vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend +//hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend +//vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend +//hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend +//vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend +//hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend +//vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend +//hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend +//vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend +//`define VDIN_LDIM_STTS_HIST_SET_REGION 8'h58 +//REGION STATISTIC DATA READ OUT PORT, bit 29:20 max_comp2, bit 19:10 max_comp1, bit 9:0 max_comp0 +//`define VDIN_LDIM_STTS_HIST_READ_REGION 8'h59 +//Bit 18, reset bit, high active +//Bit 17, if true, widen hs/vs pulse +//Bit 16 vsync total counter always accumulating enable +//Bit 14:12, select hs/vs of video input channel to measure, 0: no selection, 1: vdi1, 2: vid2, 3: vid3, 4:vid4, 5:vdi5, 6:vid6, 7:vdi7, 8: vdi8 +//Bit 11:4, vsync_span, define how many vsync span need to measure +//Bit 2:0 meas_hs_index, index to select which HS counter/range +#define VDIN_MEAS_CTRL0 ((0x125a << 2) + 0xff000000) +//Read only +//19:16 meas_ind_total_count_n, every number of sync_span vsyncs, this count add 1 +//15:0 high bit portion of vsync total counter +#define VDIN_MEAS_VS_COUNT_HI ((0x125b << 2) + 0xff000000) +//Read only +//31:0, low bit portion of vsync total counter +#define VDIN_MEAS_VS_COUNT_LO ((0x125c << 2) + 0xff000000) +//according to the meas_hs_index in register VDIN_MEAS_CTRL0 +//meas_hs_index == 0, first hs range +//meas_hs_index == 1, second hs range +//meas_hs_index == 2, third hs range +//meas_hs_index == 3, fourth hs range +//bit 28:16 count_start +//bit 12:0 count_end +#define VDIN_MEAS_HS_RANGE ((0x125d << 2) + 0xff000000) +//Read only +//according to the meas_hs_index in register VDIN_MEAS_CTRL0, +//meas_hs_index == 0, first range hs counter, +//meas_hs_index == 1, second range hs coutner +//meas_hs_index == 2, third range hs coutner +//meas_hs_index == 3, fourth range hs coutner +//23:0 +#define VDIN_MEAS_HS_COUNT ((0x125e << 2) + 0xff000000) +//Bit 8 white_enable +//Bit 7:0 blkbar_white_level +#define VDIN_BLKBAR_CTRL1 ((0x125f << 2) + 0xff000000) +// Bit 31:24 blkbar_black_level threshold to judge a black point +// Bit 23:21 Reserved +// Bit 20:8 blkbar_hwidth left and right region width +// Bit 7:5 blkbar_comp_sel select yin or uin or vin to be the valid input +// Bit 4 blkbar_sw_statistic_en enable software statistic of each block black points number +// Bit 3 blkbar_det_en +// Bit 2:1 blkbar_din_sel +// bit blkbar_det_top_en +#define VDIN_BLKBAR_CTRL0 ((0x1260 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 blkbar_hstart. Left region start +// Bit 15:13 Reserved +// Bit 12:0 blkbar_hend. Right region end +#define VDIN_BLKBAR_H_START_END ((0x1261 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 blkbar_vstart +// Bit 15:13 Reserved +// Bit 12:0 blkbar_vend +#define VDIN_BLKBAR_V_START_END ((0x1262 << 2) + 0xff000000) +// Bit 31:20 Reserved +// Bit 19:0 blkbar_cnt_threshold. threshold to judge whether a block is totally black +#define VDIN_BLKBAR_CNT_THRESHOLD ((0x1263 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 blkbar_row_th1. //threshold of the top blackbar +// Bit 15:13 Reserved +// bit 12:0 blkbar_row_th2 //threshold of the bottom blackbar +#define VDIN_BLKBAR_ROW_TH1_TH2 ((0x1264 << 2) + 0xff000000) +//Readonly +// Bit 31:29 Reserved +// Bit 28:16 blkbar_ind_left_start. horizontal start of the left region in the current searching +// Bit 15:13 Reserved +// Bit 12:0 blkbar_ind_left_end. horizontal end of the left region in the current searching +#define VDIN_BLKBAR_IND_LEFT_START_END ((0x1265 << 2) + 0xff000000) +//Readonly +// Bit 31:29 Reserved +// Bit 28:16 blkbar_ind_right_start.horizontal start of the right region in the current searching +// Bit 15:13 Reserved +// Bit 12:0 blkbar_ind_right_end. horizontal end of the right region in the current searching +#define VDIN_BLKBAR_IND_RIGHT_START_END ((0x1266 << 2) + 0xff000000) +//Readonly +// Bit 31:20 Reserved +// Bit 19:0 blkbar_ind_left1_cnt. Black pixel counter. left part of the left region +#define VDIN_BLKBAR_IND_LEFT1_CNT ((0x1267 << 2) + 0xff000000) +//Readonly +// Bit 31:20 Reserved +// Bit 19:0 blkbar_ind_left2_cnt. Black pixel counter. right part of the left region +#define VDIN_BLKBAR_IND_LEFT2_CNT ((0x1268 << 2) + 0xff000000) +//Readonly +// Bit 31:20 Reserved +// Bit 19:0 blkbar_ind_right1_cnt. Black pixel counter. left part of the right region +#define VDIN_BLKBAR_IND_RIGHT1_CNT ((0x1269 << 2) + 0xff000000) +//Readonly +// Bit 31:20 Reserved +// Bit 19:0 blkbar_ind_right2_cnt. Black pixel counter. right part of the right region +#define VDIN_BLKBAR_IND_RIGHT2_CNT ((0x126a << 2) + 0xff000000) +//Readonly +// Bit 31:30 Resersed +// Bit 29 blkbar_ind_black_det_done. LEFT/RIGHT Black detection done +// Bit 28:16 blkbar_top_pos. Top black bar position +// Bit 15:13 Reserved. +// Bit 12:0 blkbar_bot_pos. Bottom black bar position +#define VDIN_BLKBAR_STATUS0 ((0x126b << 2) + 0xff000000) +//Readonly +// Bit 31:29 Reserved +// Bit 28:16 blkbar_left_pos. Left black bar posiont +// Bit 15:13 Reserved +// Bit 12:0 blkbar_right_pos. Right black bar position +#define VDIN_BLKBAR_STATUS1 ((0x126c << 2) + 0xff000000) +//Bit 28:16 input window H start +//Bit 12:0 input window H end +#define VDIN_WIN_H_START_END ((0x126d << 2) + 0xff000000) +//Bit 28:16 input window H start +//Bit 12:0 input window V start +#define VDIN_WIN_V_START_END ((0x126e << 2) + 0xff000000) +//Bit 23:16 vdi8 asfifo_ctrl +//Bit 15:8 vdi7 asfifo_ctrl +//Bit 7:0 vdi6 asfifo_ctrl +#define VDIN_ASFIFO_CTRL3 ((0x126f << 2) + 0xff000000) +//Bit 3:2 vshrk_clk2_ctrl +//Bit 1:0 vshrk_clk1_ctrl +#define VDIN_COM_GCLK_CTRL2 ((0x1270 << 2) + 0xff000000) +//Bit 27 vshrk_en +//Bit 26:25 vshrk_mode +//Bit 24 vshrk_lpf_mode +//Bit 23:0 vshrk_dummy +#define VDIN_VSHRK_CTRL ((0x1271 << 2) + 0xff000000) +#define VDIN_DNLP_HIST32 ((0x1272 << 2) + 0xff000000) +//Read only +//Bit 7, vdi9 fifo overflow +//Bit 5:0, vdi9_asfifo_cnt +#define VDIN_COM_STATUS3 ((0x1273 << 2) + 0xff000000) +#define VDIN_SYNC_MASK ((0x1274 << 2) + 0xff000000) +//Bit 7:0, hsync_mask_num +//Bit 15:8, vsync_mask_num +//Bit 16, hsync_mask_enable +//Bit 17, vsync_mask_num +//dolby vdin +#define VDIN_DOLBY_DSC_CTRL0 ((0x1275 << 2) + 0xff000000) +#define VDIN_DOLBY_DSC_CTRL1 ((0x1276 << 2) + 0xff000000) +#define VDIN_DOLBY_DSC_CTRL2 ((0x1277 << 2) + 0xff000000) +#define VDIN_DOLBY_DSC_CTRL3 ((0x1278 << 2) + 0xff000000) +#define VDIN_DOLBY_AXI_CTRL0 ((0x1279 << 2) + 0xff000000) +#define VDIN_DOLBY_AXI_CTRL1 ((0x127a << 2) + 0xff000000) +#define VDIN_DOLBY_AXI_CTRL2 ((0x127b << 2) + 0xff000000) +#define VDIN_DOLBY_AXI_CTRL3 ((0x127c << 2) + 0xff000000) +#define VDIN_DOLBY_DSC_STATUS0 ((0x127d << 2) + 0xff000000) +#define VDIN_DOLBY_DSC_STATUS1 ((0x127e << 2) + 0xff000000) +#define VDIN_DOLBY_DSC_STATUS2 ((0x127f << 2) + 0xff000000) +#define VDIN_DOLBY_DSC_STATUS3 ((0x121d << 2) + 0xff000000) +//hdr2 0x80 - -0xc0 +#define VDIN_HDR2_CTRL ((0x1280 << 2) + 0xff000000) +#define VDIN_HDR2_CLK_GATE ((0x1281 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_COEF00_01 ((0x1282 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_COEF02_10 ((0x1283 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_COEF11_12 ((0x1284 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_COEF20_21 ((0x1285 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_COEF22 ((0x1286 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_COEF30_31 ((0x1287 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_COEF32_40 ((0x1288 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_COEF41_42 ((0x1289 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_OFFSET0_1 ((0x128a << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_OFFSET2 ((0x128b << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x128c << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_PRE_OFFSET2 ((0x128d << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_COEF00_01 ((0x128e << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_COEF02_10 ((0x128f << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_COEF11_12 ((0x1290 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_COEF20_21 ((0x1291 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_COEF22 ((0x1292 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_COEF30_31 ((0x1293 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_COEF32_40 ((0x1294 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_COEF41_42 ((0x1295 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_OFFSET0_1 ((0x1296 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_OFFSET2 ((0x1297 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x1298 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_PRE_OFFSET2 ((0x1299 << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_CLIP ((0x129a << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_CLIP ((0x129b << 2) + 0xff000000) +#define VDIN_HDR2_CGAIN_OFFT ((0x129c << 2) + 0xff000000) +#define VDIN_EOTF_LUT_ADDR_PORT ((0x129e << 2) + 0xff000000) +#define VDIN_EOTF_LUT_DATA_PORT ((0x129f << 2) + 0xff000000) +#define VDIN_OETF_LUT_ADDR_PORT ((0x12a0 << 2) + 0xff000000) +#define VDIN_OETF_LUT_DATA_PORT ((0x12a1 << 2) + 0xff000000) +#define VDIN_CGAIN_LUT_ADDR_PORT ((0x12a2 << 2) + 0xff000000) +#define VDIN_CGAIN_LUT_DATA_PORT ((0x12a3 << 2) + 0xff000000) +#define VDIN_HDR2_CGAIN_COEF0 ((0x12a4 << 2) + 0xff000000) +#define VDIN_HDR2_CGAIN_COEF1 ((0x12a5 << 2) + 0xff000000) +#define VDIN_OGAIN_LUT_ADDR_PORT ((0x12a6 << 2) + 0xff000000) +#define VDIN_OGAIN_LUT_DATA_PORT ((0x12a7 << 2) + 0xff000000) +#define VDIN_HDR2_ADPS_CTRL ((0x12a8 << 2) + 0xff000000) +#define VDIN_HDR2_ADPS_ALPHA0 ((0x12a9 << 2) + 0xff000000) +#define VDIN_HDR2_ADPS_ALPHA1 ((0x12aa << 2) + 0xff000000) +#define VDIN_HDR2_ADPS_BETA0 ((0x12ab << 2) + 0xff000000) +#define VDIN_HDR2_ADPS_BETA1 ((0x12ac << 2) + 0xff000000) +#define VDIN_HDR2_ADPS_BETA2 ((0x12ad << 2) + 0xff000000) +#define VDIN_HDR2_ADPS_COEF0 ((0x12ae << 2) + 0xff000000) +#define VDIN_HDR2_ADPS_COEF1 ((0x12af << 2) + 0xff000000) +#define VDIN_HDR2_GMUT_CTRL ((0x12b0 << 2) + 0xff000000) +#define VDIN_HDR2_GMUT_COEF0 ((0x12b1 << 2) + 0xff000000) +#define VDIN_HDR2_GMUT_COEF1 ((0x12b2 << 2) + 0xff000000) +#define VDIN_HDR2_GMUT_COEF2 ((0x12b3 << 2) + 0xff000000) +#define VDIN_HDR2_GMUT_COEF3 ((0x12b4 << 2) + 0xff000000) +#define VDIN_HDR2_GMUT_COEF4 ((0x12b5 << 2) + 0xff000000) +#define VDIN_HDR2_PIPE_CTRL1 ((0x12b6 << 2) + 0xff000000) +#define VDIN_HDR2_PIPE_CTRL2 ((0x12b7 << 2) + 0xff000000) +#define VDIN_HDR2_PIPE_CTRL3 ((0x12b8 << 2) + 0xff000000) +#define VDIN_HDR2_PROC_WIN1 ((0x12b9 << 2) + 0xff000000) +#define VDIN_HDR2_PROC_WIN2 ((0x12ba << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXI_EN_CTRL ((0x12bb << 2) + 0xff000000) +#define VDIN_HDR2_MATRIXO_EN_CTRL ((0x12bc << 2) + 0xff000000) +#define VDIN_HDR2_HIST_CTRL ((0x12bd << 2) + 0xff000000) +#define VDIN_HDR2_HIST_H_START_END ((0x12be << 2) + 0xff000000) +#define VDIN_HDR2_HIST_V_START_END ((0x12bf << 2) + 0xff000000) +#define VDIN_HDR2_HIST_RD ((0x129d << 2) + 0xff000000) +#define VDIN_WRARB_MODE ((0x12c0 << 2) + 0xff000000) +#define VDIN_WRARB_REQEN_SLV ((0x12c1 << 2) + 0xff000000) +#define VDIN_WRARB_WEIGH0_SLV ((0x12c2 << 2) + 0xff000000) +#define VDIN_WRARB_WEIGH1_SLV ((0x12c3 << 2) + 0xff000000) +#define VDIN_RDWR_ARB_STATUS ((0x12c4 << 2) + 0xff000000) +#define VDIN_ARB_DBG_CTRL ((0x12c5 << 2) + 0xff000000) +#define VDIN_ARB_DBG_STAT ((0x12c6 << 2) + 0xff000000) +#define VDIN_DBG_AXI_CMD_CNT ((0x12c7 << 2) + 0xff000000) +#define VDIN_DBG_AXI_DAT_CNT ((0x12c8 << 2) + 0xff000000) +#define VDIN_CRC_CTRL ((0x12c9 << 2) + 0xff000000) +#define VDIN_RO_CRC ((0x12ca << 2) + 0xff000000) +#define VDIN_LINE_INT ((0x12cb << 2) + 0xff000000) +#define VDIN_WR_URGENT_CTRL ((0x1257 << 2) + 0xff000000) +#define VDIN_RO_WRMIF_STATUS ((0x1258 << 2) + 0xff000000) +//for vdin dolby descramble start +#define VDIN_DSC_CTRL ((0x12d0 << 2) + 0xff000000) +//Bit 31:10 reserved +//Bit 9:4 reg_dithout_switch ,uns, default = 36;//{2'h2,2'h1,2'h0} +//Bit 3, reg_detunnel_en ,uns, default = 1; +//Bit 2, reg_detunnel_u_start,uns, default = 0; +//Bit 1, reg_vdin_dith_en ,uns, default = 1; +//Bit 0, reg_descramble_en ,uns, default = 1; +#define VDIN_CFMT_CTRL ((0x12d1 << 2) + 0xff000000) +//Bit 31:9 reserved +//Bit 8 reg_chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation +//Bit 7:4 reg_chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase +//Bit 3 reg_chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable +//Bit 2:1 reg_chfmt_yc_ratio uns, default = 1 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 +//Bit 0 reg_chfmt_en uns, default = 1 ; // horizontal formatter enable +#define VDIN_CFMT_W ((0x12d2 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_chfmt_w uns, default = 1920 ;horizontal formatter width +//Bit 15:13 reserved +//Bit 12:0 reg_cvfmt_w uns, default = 960 ;vertical formatter width +#define VDIN_SCB_CTRL0 ((0x12d3 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11 reg_444c422_gofield_en uns, default = 1; +//Bit 10 reg_tunnel_en uns, default = 1; +//Bit 9:4 reg_tunnel_outswitch uns, default = 36;//{2'h2,2'h1,2'h0} +//Bit 3:2 reg_444c422_mode uns, default = 0; //0:left 1:right 2,3:avg +//Bit 1 reg_444c422_bypass uns, default = 0; 1:bypass +//Bit 0 reserved //pulse for frm_en +#define VDIN_SCB_CTRL1 ((0x12d4 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_444c422_hsize uns, default = 1920 ;horizontal size +//Bit 15:13 reserved +//Bit 12:0 reg_444c422_vsize uns, default = 960 ;vertical size +#define VDIN_DSC_HSIZE ((0x12d5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_detunnel_hsize uns, default = 1920 ; +//Bit 15:13 reserved +//Bit 12:0 reg_dither_hsize uns, default = 1920 ; +#define VDIN_DSC_DETUNNEL_SEL ((0x12d6 << 2) + 0xff000000) +//Bit 31:18 reserved +//Bit 17:0 reg_detunnel_sel uns, default = 34658; //{3'h1,3'h0,3'h3 ,3'h5,3'h4,3'h2} +#define VDIN_DSC_TUNNEL_SEL ((0x12d7 << 2) + 0xff000000) +//Bit 31:18 reserved +//Bit 17:0 reg_tunnel_sel uns, default = 69868; //= {3'h2,3'h1 ,3'h0,3'h3 ,3'h5,3'h4}; +#define VDIN_HDR2_SIZE ((0x12d8 << 2) + 0xff000000) +#define VDIN_VSHRK_SIZE_M1 ((0x12d9 << 2) + 0xff000000) +//dither +#define VDIN_DITH_CTRL ((0x12e0 << 2) + 0xff000000) +#define VDIN_DITH_LUT_1 ((0x12e1 << 2) + 0xff000000) +#define VDIN_DITH_LUT_2 ((0x12e2 << 2) + 0xff000000) +#define VDIN_DITH_LUT_3 ((0x12e3 << 2) + 0xff000000) +#define VDIN_DITH_LUT_4 ((0x12e4 << 2) + 0xff000000) +#define VDIN_DITH_LUT_5 ((0x12e5 << 2) + 0xff000000) +#define VDIN_DITH_LUT_6 ((0x12e6 << 2) + 0xff000000) +#define VDIN_DITH_LUT_7 ((0x12e7 << 2) + 0xff000000) +#define VDIN_DITH_LUT_8 ((0x12e8 << 2) + 0xff000000) +#define VDIN_DITH_LUT_9 ((0x12e9 << 2) + 0xff000000) +#define VDIN_DITH_LUT_10 ((0x12ea << 2) + 0xff000000) +#define VDIN_DITH_LUT_11 ((0x12eb << 2) + 0xff000000) +#define VDIN_DITH_LUT_12 ((0x12ec << 2) + 0xff000000) +//for vdin dolby descramble end +#define VDIN_HSK_CTRL ((0x12ef << 2) + 0xff000000) +//Bit 31:23 reserved +//Bit 22:16 reg_hsk_size ,uns, default = 4; +//Bit 15:13 reserved +//Bit 12:0 reg_frm_hsize ,uns, default = 1920; +#define VDIN_HSK_COEF_0 ((0x12f0 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef00 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_1 ((0x12f1 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef01 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_2 ((0x12f2 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef02 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_3 ((0x12f3 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef03 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +// +#define VDIN_HSK_COEF_4 ((0x12f4 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef04 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_5 ((0x12f5 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef05 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_6 ((0x12f6 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef06 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_7 ((0x12f7 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef07 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +// +#define VDIN_HSK_COEF_8 ((0x12f8 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef08 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_9 ((0x12f9 << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef09 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_A ((0x12fa << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef10 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_B ((0x12fb << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef11 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +// +#define VDIN_HSK_COEF_C ((0x12fc << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef12 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_D ((0x12fd << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef13 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_E ((0x12fe << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef14 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +#define VDIN_HSK_COEF_F ((0x12ff << 2) + 0xff000000) +//Bit 31:0 reg_hsk_coef15 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_vdin_regs.h +// + +//8'h72 occupied by histogram 32 +//VDIN0 8'h00 - 8'h7f +#define VDIN0_SCALE_COEF_IDX (VDIN_SCALE_COEF_IDX ) +#define VDIN0_SCALE_COEF (VDIN_SCALE_COEF ) +#define VDIN0_COM_CTRL0 (VDIN_COM_CTRL0 ) +#define VDIN0_ACTIVE_MAX_PIX_CNT_STATUS (VDIN_ACTIVE_MAX_PIX_CNT_STATUS ) +#define VDIN0_LCNT_STATUS (VDIN_LCNT_STATUS ) +#define VDIN0_COM_STATUS0 (VDIN_COM_STATUS0 ) +#define VDIN0_COM_STATUS1 (VDIN_COM_STATUS1 ) +#define VDIN0_LCNT_SHADOW_STATUS (VDIN_LCNT_SHADOW_STATUS ) +#define VDIN0_ASFIFO_CTRL0 (VDIN_ASFIFO_CTRL0 ) +#define VDIN0_ASFIFO_CTRL1 (VDIN_ASFIFO_CTRL1 ) +#define VDIN0_WIDTHM1I_WIDTHM1O (VDIN_WIDTHM1I_WIDTHM1O ) +#define VDIN0_SC_MISC_CTRL (VDIN_SC_MISC_CTRL ) +#define VDIN0_HSC_PHASE_STEP (VDIN_HSC_PHASE_STEP ) +#define VDIN0_HSC_INI_CTRL (VDIN_HSC_INI_CTRL ) +#define VDIN0_COM_STATUS2 (VDIN_COM_STATUS2 ) +#define VDIN0_COM_STATUS3 (VDIN_COM_STATUS3 ) +#define VDIN0_ASFIFO_CTRL2 (VDIN_ASFIFO_CTRL2 ) +#define VDIN0_MATRIX_CTRL (VDIN_MATRIX_CTRL ) +#define VDIN0_MATRIX_COEF00_01 (VDIN_MATRIX_COEF00_01 ) +#define VDIN0_MATRIX_COEF02_10 (VDIN_MATRIX_COEF02_10 ) +#define VDIN0_MATRIX_COEF11_12 (VDIN_MATRIX_COEF11_12 ) +#define VDIN0_MATRIX_COEF20_21 (VDIN_MATRIX_COEF20_21 ) +#define VDIN0_MATRIX_COEF22 (VDIN_MATRIX_COEF22 ) +#define VDIN0_MATRIX_OFFSET0_1 (VDIN_MATRIX_OFFSET0_1 ) +#define VDIN0_MATRIX_OFFSET2 (VDIN_MATRIX_OFFSET2 ) +#define VDIN0_MATRIX_PRE_OFFSET0_1 (VDIN_MATRIX_PRE_OFFSET0_1 ) +#define VDIN0_MATRIX_PRE_OFFSET2 (VDIN_MATRIX_PRE_OFFSET2 ) +#define VDIN0_LFIFO_CTRL (VDIN_LFIFO_CTRL ) +#define VDIN0_COM_GCLK_CTRL (VDIN_COM_GCLK_CTRL ) +#define VDIN0_INTF_WIDTHM1 (VDIN_INTF_WIDTHM1 ) +#define VDIN0_WR_CTRL2 (VDIN_WR_CTRL2 ) +#define VDIN0_WR_CTRL (VDIN_WR_CTRL ) +#define VDIN0_WR_H_START_END (VDIN_WR_H_START_END ) +#define VDIN0_WR_V_START_END (VDIN_WR_V_START_END ) +#define VDIN0_VSC_PHASE_STEP (VDIN_VSC_PHASE_STEP ) +#define VDIN0_VSC_INI_CTRL (VDIN_VSC_INI_CTRL ) +#define VDIN0_SCIN_HEIGHTM1 (VDIN_SCIN_HEIGHTM1 ) +#define VDIN0_DUMMY_DATA (VDIN_DUMMY_DATA ) +#define VDIN0_MATRIX_PROBE_COLOR (VDIN_MATRIX_PROBE_COLOR ) +#define VDIN0_MATRIX_HL_COLOR (VDIN_MATRIX_HL_COLOR ) +#define VDIN0_MATRIX_PROBE_POS (VDIN_MATRIX_PROBE_POS ) +#define VDIN0_CHROMA_ADDR_PORT (VDIN_CHROMA_ADDR_PORT ) +#define VDIN0_CHROMA_DATA_PORT (VDIN_CHROMA_DATA_PORT ) +#define VDIN0_CM_BRI_CON_CTRL (VDIN_CM_BRI_CON_CTRL ) +#define VDIN0_GO_LINE_CTRL (VDIN_GO_LINE_CTRL ) +#define VDIN0_HIST_CTRL (VDIN_HIST_CTRL ) +#define VDIN0_HIST_H_START_END (VDIN_HIST_H_START_END ) +#define VDIN0_HIST_V_START_END (VDIN_HIST_V_START_END ) +#define VDIN0_HIST_MAX_MIN (VDIN_HIST_MAX_MIN ) +#define VDIN0_HIST_SPL_VAL (VDIN_HIST_SPL_VAL ) +#define VDIN0_HIST_SPL_PIX_CNT (VDIN_HIST_SPL_PIX_CNT ) +#define VDIN0_HIST_CHROMA_SUM (VDIN_HIST_CHROMA_SUM ) +#define VDIN0_DNLP_HIST00 (VDIN_DNLP_HIST00 ) +#define VDIN0_DNLP_HIST01 (VDIN_DNLP_HIST01 ) +#define VDIN0_DNLP_HIST02 (VDIN_DNLP_HIST02 ) +#define VDIN0_DNLP_HIST03 (VDIN_DNLP_HIST03 ) +#define VDIN0_DNLP_HIST04 (VDIN_DNLP_HIST04 ) +#define VDIN0_DNLP_HIST05 (VDIN_DNLP_HIST05 ) +#define VDIN0_DNLP_HIST06 (VDIN_DNLP_HIST06 ) +#define VDIN0_DNLP_HIST07 (VDIN_DNLP_HIST07 ) +#define VDIN0_DNLP_HIST08 (VDIN_DNLP_HIST08 ) +#define VDIN0_DNLP_HIST09 (VDIN_DNLP_HIST09 ) +#define VDIN0_DNLP_HIST10 (VDIN_DNLP_HIST10 ) +#define VDIN0_DNLP_HIST11 (VDIN_DNLP_HIST11 ) +#define VDIN0_DNLP_HIST12 (VDIN_DNLP_HIST12 ) +#define VDIN0_DNLP_HIST13 (VDIN_DNLP_HIST13 ) +#define VDIN0_DNLP_HIST14 (VDIN_DNLP_HIST14 ) +#define VDIN0_DNLP_HIST15 (VDIN_DNLP_HIST15 ) +#define VDIN0_DNLP_HIST16 (VDIN_DNLP_HIST16 ) +#define VDIN0_DNLP_HIST17 (VDIN_DNLP_HIST17 ) +#define VDIN0_DNLP_HIST18 (VDIN_DNLP_HIST18 ) +#define VDIN0_DNLP_HIST19 (VDIN_DNLP_HIST19 ) +#define VDIN0_DNLP_HIST20 (VDIN_DNLP_HIST20 ) +#define VDIN0_DNLP_HIST21 (VDIN_DNLP_HIST21 ) +#define VDIN0_DNLP_HIST22 (VDIN_DNLP_HIST22 ) +#define VDIN0_DNLP_HIST23 (VDIN_DNLP_HIST23 ) +#define VDIN0_DNLP_HIST24 (VDIN_DNLP_HIST24 ) +#define VDIN0_DNLP_HIST25 (VDIN_DNLP_HIST25 ) +#define VDIN0_DNLP_HIST26 (VDIN_DNLP_HIST26 ) +#define VDIN0_DNLP_HIST27 (VDIN_DNLP_HIST27 ) +#define VDIN0_DNLP_HIST28 (VDIN_DNLP_HIST28 ) +#define VDIN0_DNLP_HIST29 (VDIN_DNLP_HIST29 ) +#define VDIN0_DNLP_HIST30 (VDIN_DNLP_HIST30 ) +#define VDIN0_DNLP_HIST31 (VDIN_DNLP_HIST31 ) +#define VDIN0_DNLP_HIST32 (VDIN_DNLP_HIST32 ) +#define VDIN0_MEAS_CTRL0 (VDIN_MEAS_CTRL0 ) +#define VDIN0_MEAS_VS_COUNT_HI (VDIN_MEAS_VS_COUNT_HI ) +#define VDIN0_MEAS_VS_COUNT_LO (VDIN_MEAS_VS_COUNT_LO ) +#define VDIN0_MEAS_HS_RANGE (VDIN_MEAS_HS_RANGE ) +#define VDIN0_MEAS_HS_COUNT (VDIN_MEAS_HS_COUNT ) +#define VDIN0_BLKBAR_CTRL1 (VDIN_BLKBAR_CTRL1 ) +#define VDIN0_BLKBAR_CTRL0 (VDIN_BLKBAR_CTRL0 ) +#define VDIN0_BLKBAR_H_START_END (VDIN_BLKBAR_H_START_END ) +#define VDIN0_BLKBAR_V_START_END (VDIN_BLKBAR_V_START_END ) +#define VDIN0_BLKBAR_CNT_THRESHOLD (VDIN_BLKBAR_CNT_THRESHOLD ) +#define VDIN0_BLKBAR_ROW_TH1_TH2 (VDIN_BLKBAR_ROW_TH1_TH2 ) +#define VDIN0_BLKBAR_IND_LEFT_START_END (VDIN_BLKBAR_IND_LEFT_START_END ) +#define VDIN0_BLKBAR_IND_RIGHT_START_END (VDIN_BLKBAR_IND_RIGHT_START_END ) +#define VDIN0_BLKBAR_IND_LEFT1_CNT (VDIN_BLKBAR_IND_LEFT1_CNT ) +#define VDIN0_BLKBAR_IND_LEFT2_CNT (VDIN_BLKBAR_IND_LEFT2_CNT ) +#define VDIN0_BLKBAR_IND_RIGHT1_CNT (VDIN_BLKBAR_IND_RIGHT1_CNT ) +#define VDIN0_BLKBAR_IND_RIGHT2_CNT (VDIN_BLKBAR_IND_RIGHT2_CNT ) +#define VDIN0_BLKBAR_STATUS0 (VDIN_BLKBAR_STATUS0 ) +#define VDIN0_BLKBAR_STATUS1 (VDIN_BLKBAR_STATUS1 ) +#define VDIN0_WIN_H_START_END (VDIN_WIN_H_START_END ) +#define VDIN0_WIN_V_START_END (VDIN_WIN_V_START_END ) +#define VDIN0_ASFIFO_CTRL3 (VDIN_ASFIFO_CTRL3 ) +#define VDIN0_LFIFO_URG_CTRL (VDIN_LFIFO_URG_CTRL ) +#define VDIN0_COM_GCLK_CTRL2 (VDIN_COM_GCLK_CTRL2 ) +#define VDIN0_VSHRK_CTRL (VDIN_VSHRK_CTRL ) +#define VDIN0_SYNC_MASK (VDIN_SYNC_MASK ) +#define VDIN0_DOLBY_DSC_CTRL0 (VDIN_DOLBY_DSC_CTRL0 ) +#define VDIN0_DOLBY_DSC_CTRL1 (VDIN_DOLBY_DSC_CTRL1 ) +#define VDIN0_DOLBY_DSC_CTRL2 (VDIN_DOLBY_DSC_CTRL2 ) +#define VDIN0_DOLBY_DSC_CTRL3 (VDIN_DOLBY_DSC_CTRL3 ) +#define VDIN0_DOLBY_AXI_CTRL0 (VDIN_DOLBY_AXI_CTRL0 ) +#define VDIN0_DOLBY_AXI_CTRL1 (VDIN_DOLBY_AXI_CTRL1 ) +#define VDIN0_DOLBY_AXI_CTRL2 (VDIN_DOLBY_AXI_CTRL2 ) +#define VDIN0_DOLBY_AXI_CTRL3 (VDIN_DOLBY_AXI_CTRL3 ) +#define VDIN0_DOLBY_DSC_STATUS0 (VDIN_DOLBY_DSC_STATUS0) +#define VDIN0_DOLBY_DSC_STATUS1 (VDIN_DOLBY_DSC_STATUS1) +#define VDIN0_DOLBY_DSC_STATUS2 (VDIN_DOLBY_DSC_STATUS2) +#define VDIN0_DOLBY_DSC_STATUS3 (VDIN_DOLBY_DSC_STATUS3) +#define VDIN0_HDR2_CTRL VDIN_HDR2_CTRL +#define VDIN0_HDR2_CLK_GATE VDIN_HDR2_CLK_GATE +#define VDIN0_HDR2_MATRIXI_COEF00_01 VDIN_HDR2_MATRIXI_COEF00_01 +#define VDIN0_HDR2_MATRIXI_COEF02_10 VDIN_HDR2_MATRIXI_COEF02_10 +#define VDIN0_HDR2_MATRIXI_COEF11_12 VDIN_HDR2_MATRIXI_COEF11_12 +#define VDIN0_HDR2_MATRIXI_COEF20_21 VDIN_HDR2_MATRIXI_COEF20_21 +#define VDIN0_HDR2_MATRIXI_COEF22 VDIN_HDR2_MATRIXI_COEF22 +#define VDIN0_HDR2_MATRIXI_COEF30_31 VDIN_HDR2_MATRIXI_COEF30_31 +#define VDIN0_HDR2_MATRIXI_COEF32_40 VDIN_HDR2_MATRIXI_COEF32_40 +#define VDIN0_HDR2_MATRIXI_COEF41_42 VDIN_HDR2_MATRIXI_COEF41_42 +#define VDIN0_HDR2_MATRIXI_OFFSET0_1 VDIN_HDR2_MATRIXI_OFFSET0_1 +#define VDIN0_HDR2_MATRIXI_OFFSET2 VDIN_HDR2_MATRIXI_OFFSET2 +#define VDIN0_HDR2_MATRIXI_PRE_OFFSET0_1 VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 +#define VDIN0_HDR2_MATRIXI_PRE_OFFSET2 VDIN_HDR2_MATRIXI_PRE_OFFSET2 +#define VDIN0_HDR2_MATRIXO_COEF00_01 VDIN_HDR2_MATRIXO_COEF00_01 +#define VDIN0_HDR2_MATRIXO_COEF02_10 VDIN_HDR2_MATRIXO_COEF02_10 +#define VDIN0_HDR2_MATRIXO_COEF11_12 VDIN_HDR2_MATRIXO_COEF11_12 +#define VDIN0_HDR2_MATRIXO_COEF20_21 VDIN_HDR2_MATRIXO_COEF20_21 +#define VDIN0_HDR2_MATRIXO_COEF22 VDIN_HDR2_MATRIXO_COEF22 +#define VDIN0_HDR2_MATRIXO_COEF30_31 VDIN_HDR2_MATRIXO_COEF30_31 +#define VDIN0_HDR2_MATRIXO_COEF32_40 VDIN_HDR2_MATRIXO_COEF32_40 +#define VDIN0_HDR2_MATRIXO_COEF41_42 VDIN_HDR2_MATRIXO_COEF41_42 +#define VDIN0_HDR2_MATRIXO_OFFSET0_1 VDIN_HDR2_MATRIXO_OFFSET0_1 +#define VDIN0_HDR2_MATRIXO_OFFSET2 VDIN_HDR2_MATRIXO_OFFSET2 +#define VDIN0_HDR2_MATRIXO_PRE_OFFSET0_1 VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 +#define VDIN0_HDR2_MATRIXO_PRE_OFFSET2 VDIN_HDR2_MATRIXO_PRE_OFFSET2 +#define VDIN0_HDR2_MATRIXI_CLIP VDIN_HDR2_MATRIXI_CLIP +#define VDIN0_HDR2_MATRIXO_CLIP VDIN_HDR2_MATRIXO_CLIP +#define VDIN0_HDR2_CGAIN_OFFT VDIN_HDR2_CGAIN_OFFT +#define VDIN0_EOTF_LUT_ADDR_PORT VDIN_EOTF_LUT_ADDR_PORT +#define VDIN0_EOTF_LUT_DATA_PORT VDIN_EOTF_LUT_DATA_PORT +#define VDIN0_OETF_LUT_ADDR_PORT VDIN_OETF_LUT_ADDR_PORT +#define VDIN0_OETF_LUT_DATA_PORT VDIN_OETF_LUT_DATA_PORT +#define VDIN0_OGAIN_LUT_ADDR_PORT VDIN_OGAIN_LUT_ADDR_PORT +#define VDIN0_OGAIN_LUT_DATA_PORT VDIN_OGAIN_LUT_DATA_PORT +#define VDIN0_CGAIN_LUT_ADDR_PORT VDIN_CGAIN_LUT_ADDR_PORT +#define VDIN0_CGAIN_LUT_DATA_PORT VDIN_CGAIN_LUT_DATA_PORT +#define VDIN0_HDR2_CGAIN_COEF0 VDIN_HDR2_CGAIN_COEF0 +#define VDIN0_HDR2_CGAIN_COEF1 VDIN_HDR2_CGAIN_COEF1 +#define VDIN0_HDR2_ADPS_CTRL VDIN_HDR2_ADPS_CTRL +#define VDIN0_HDR2_ADPS_ALPHA0 VDIN_HDR2_ADPS_ALPHA0 +#define VDIN0_HDR2_ADPS_ALPHA1 VDIN_HDR2_ADPS_ALPHA1 +#define VDIN0_HDR2_ADPS_BETA0 VDIN_HDR2_ADPS_BETA0 +#define VDIN0_HDR2_ADPS_BETA1 VDIN_HDR2_ADPS_BETA1 +#define VDIN0_HDR2_ADPS_BETA2 VDIN_HDR2_ADPS_BETA2 +#define VDIN0_HDR2_ADPS_COEF0 VDIN_HDR2_ADPS_COEF0 +#define VDIN0_HDR2_ADPS_COEF1 VDIN_HDR2_ADPS_COEF1 +#define VDIN0_HDR2_GMUT_CTRL VDIN_HDR2_GMUT_CTRL +#define VDIN0_HDR2_GMUT_COEF0 VDIN_HDR2_GMUT_COEF0 +#define VDIN0_HDR2_GMUT_COEF1 VDIN_HDR2_GMUT_COEF1 +#define VDIN0_HDR2_GMUT_COEF2 VDIN_HDR2_GMUT_COEF2 +#define VDIN0_HDR2_GMUT_COEF3 VDIN_HDR2_GMUT_COEF3 +#define VDIN0_HDR2_GMUT_COEF4 VDIN_HDR2_GMUT_COEF4 +#define VDIN0_HDR2_PIPE_CTRL1 VDIN_HDR2_PIPE_CTRL1 +#define VDIN0_HDR2_PIPE_CTRL2 VDIN_HDR2_PIPE_CTRL2 +#define VDIN0_HDR2_PIPE_CTRL3 VDIN_HDR2_PIPE_CTRL3 +#define VDIN0_HDR2_PROC_WIN1 VDIN_HDR2_PROC_WIN1 +#define VDIN0_HDR2_PROC_WIN2 VDIN_HDR2_PROC_WIN2 +#define VDIN0_HDR2_MATRIXI_EN_CTRL VDIN_HDR2_MATRIXI_EN_CTRL +#define VDIN0_HDR2_MATRIXO_EN_CTRL VDIN_HDR2_MATRIXO_EN_CTRL +#define VDIN0_HDR2_HIST_CTRL VDIN_HDR2_HIST_CTRL +#define VDIN0_HDR2_HIST_H_START_END VDIN_HDR2_HIST_H_START_END +#define VDIN0_HDR2_HIST_V_START_END VDIN_HDR2_HIST_V_START_END +#define VDIN0_HDR2_HIST_RD VDIN_HDR2_HIST_RD + + +#define VDIN0_CRC_CTRL (VDIN_CRC_CTRL) +#define VDIN0_RO_CRC (VDIN_RO_CRC ) +#define VDIN0_LINE_INT (VDIN_LINE_INT) +#define VDIN0_WR_URGENT_CTRL (VDIN_WR_URGENT_CTRL) +#define VDIN0_RO_WRMIF_STATUS (VDIN_RO_WRMIF_STATUS) + +#define VDIN0_DSC_CTRL VDIN_DSC_CTRL +#define VDIN0_CFMT_CTRL VDIN_CFMT_CTRL +#define VDIN0_CFMT_W VDIN_CFMT_W +#define VDIN0_SCB_CTRL0 VDIN_SCB_CTRL0 +#define VDIN0_SCB_CTRL1 VDIN_SCB_CTRL1 +#define VDIN0_DSC_HSIZE VDIN_DSC_HSIZE +#define VDIN0_DSC_DETUNNEL_SEL VDIN_DSC_DETUNNEL_SEL +#define VDIN0_DSC_TUNNEL_SEL VDIN_DSC_TUNNEL_SEL +#define VDIN0_DITH_CTRL VDIN_DITH_CTRL +#define VDIN0_DITH_LUT_1 VDIN_DITH_LUT_1 +#define VDIN0_DITH_LUT_2 VDIN_DITH_LUT_2 +#define VDIN0_DITH_LUT_3 VDIN_DITH_LUT_3 +#define VDIN0_DITH_LUT_4 VDIN_DITH_LUT_4 +#define VDIN0_DITH_LUT_5 VDIN_DITH_LUT_5 +#define VDIN0_DITH_LUT_6 VDIN_DITH_LUT_6 +#define VDIN0_DITH_LUT_7 VDIN_DITH_LUT_7 +#define VDIN0_DITH_LUT_8 VDIN_DITH_LUT_8 +#define VDIN0_DITH_LUT_9 VDIN_DITH_LUT_9 +#define VDIN0_DITH_LUT_10 VDIN_DITH_LUT_10 +#define VDIN0_DITH_LUT_11 VDIN_DITH_LUT_11 +#define VDIN0_DITH_LUT_12 VDIN_DITH_LUT_12 + +#define VDIN0_HSK_CTRL VDIN_HSK_CTRL +#define VDIN0_HSK_COEF_0 VDIN_HSK_COEF_0 +#define VDIN0_HSK_COEF_1 VDIN_HSK_COEF_1 +#define VDIN0_HSK_COEF_2 VDIN_HSK_COEF_2 +#define VDIN0_HSK_COEF_3 VDIN_HSK_COEF_3 +#define VDIN0_HSK_COEF_4 VDIN_HSK_COEF_4 +#define VDIN0_HSK_COEF_5 VDIN_HSK_COEF_5 +#define VDIN0_HSK_COEF_6 VDIN_HSK_COEF_6 +#define VDIN0_HSK_COEF_7 VDIN_HSK_COEF_7 +#define VDIN0_HSK_COEF_8 VDIN_HSK_COEF_8 +#define VDIN0_HSK_COEF_9 VDIN_HSK_COEF_9 +#define VDIN0_HSK_COEF_A VDIN_HSK_COEF_A +#define VDIN0_HSK_COEF_B VDIN_HSK_COEF_B +#define VDIN0_HSK_COEF_C VDIN_HSK_COEF_C +#define VDIN0_HSK_COEF_D VDIN_HSK_COEF_D +#define VDIN0_HSK_COEF_E VDIN_HSK_COEF_E +#define VDIN0_HSK_COEF_F VDIN_HSK_COEF_F + +#define VDIN0_HDR2_SIZE VDIN_HDR2_SIZE +#define VDIN0_VSHRK_SIZE_M1 VDIN_VSHRK_SIZE_M1 + +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_vdin0_regs.h +// +// +// Reading file: vpu_vdin1_regs.h +// +// synopsys translate_off +// synopsys translate_on +//=========================================================================== +// VDIN +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: VDIN1_VCBUS_BASE = 0x13 +// ----------------------------------------------- +#define VDIN1_OFFSET (0x100) +// `include "vpu_vdin_regs.h" +//8'h72 occupied by histogram 32 +//VDIN1 8'h00 - 8'h7f +#define VDIN1_SCALE_COEF_IDX ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF_IDX ) +#define VDIN1_SCALE_COEF ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF ) +#define VDIN1_COM_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_COM_CTRL0 ) +#define VDIN1_ACTIVE_MAX_PIX_CNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_ACTIVE_MAX_PIX_CNT_STATUS ) +#define VDIN1_LCNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_STATUS ) +#define VDIN1_COM_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS0 ) +#define VDIN1_COM_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS1 ) +#define VDIN1_LCNT_SHADOW_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_SHADOW_STATUS ) +#define VDIN1_ASFIFO_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL0 ) +#define VDIN1_ASFIFO_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL1 ) +#define VDIN1_WIDTHM1I_WIDTHM1O ((VDIN1_OFFSET << 2) + VDIN_WIDTHM1I_WIDTHM1O ) +#define VDIN1_SC_MISC_CTRL ((VDIN1_OFFSET << 2) + VDIN_SC_MISC_CTRL ) +#define VDIN1_HSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_HSC_PHASE_STEP ) +#define VDIN1_HSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSC_INI_CTRL ) +#define VDIN1_COM_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS2 ) +#define VDIN1_COM_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS3 ) +#define VDIN1_ASFIFO_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL2 ) +#define VDIN1_MATRIX_CTRL ((VDIN1_OFFSET << 2) + VDIN_MATRIX_CTRL ) +#define VDIN1_MATRIX_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF00_01 ) +#define VDIN1_MATRIX_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF02_10 ) +#define VDIN1_MATRIX_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF11_12 ) +#define VDIN1_MATRIX_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF20_21 ) +#define VDIN1_MATRIX_COEF22 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF22 ) +#define VDIN1_MATRIX_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET0_1 ) +#define VDIN1_MATRIX_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET2 ) +#define VDIN1_MATRIX_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET0_1 ) +#define VDIN1_MATRIX_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET2 ) +#define VDIN1_LFIFO_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_CTRL ) +#define VDIN1_COM_GCLK_CTRL ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL ) +#define VDIN1_INTF_WIDTHM1 ((VDIN1_OFFSET << 2) + VDIN_INTF_WIDTHM1 ) +#define VDIN1_WR_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL2 ) +#define VDIN1_WR_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL ) +#define VDIN1_WR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_H_START_END ) +#define VDIN1_WR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_V_START_END ) +#define VDIN1_VSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_VSC_PHASE_STEP ) +#define VDIN1_VSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSC_INI_CTRL ) +#define VDIN1_SCIN_HEIGHTM1 ((VDIN1_OFFSET << 2) + VDIN_SCIN_HEIGHTM1 ) +#define VDIN1_DUMMY_DATA ((VDIN1_OFFSET << 2) + VDIN_DUMMY_DATA ) +#define VDIN1_MATRIX_PROBE_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_COLOR ) +#define VDIN1_MATRIX_HL_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_HL_COLOR ) +#define VDIN1_MATRIX_PROBE_POS ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_POS ) +#define VDIN1_CHROMA_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_ADDR_PORT ) +#define VDIN1_CHROMA_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_DATA_PORT ) +#define VDIN1_CM_BRI_CON_CTRL ((VDIN1_OFFSET << 2) + VDIN_CM_BRI_CON_CTRL ) +#define VDIN1_GO_LINE_CTRL ((VDIN1_OFFSET << 2) + VDIN_GO_LINE_CTRL ) +#define VDIN1_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HIST_CTRL ) +#define VDIN1_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_H_START_END ) +#define VDIN1_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_V_START_END ) +#define VDIN1_HIST_MAX_MIN ((VDIN1_OFFSET << 2) + VDIN_HIST_MAX_MIN ) +#define VDIN1_HIST_SPL_VAL ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_VAL ) +#define VDIN1_HIST_SPL_PIX_CNT ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_PIX_CNT ) +#define VDIN1_HIST_CHROMA_SUM ((VDIN1_OFFSET << 2) + VDIN_HIST_CHROMA_SUM ) +#define VDIN1_DNLP_HIST00 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST00 ) +#define VDIN1_DNLP_HIST01 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST01 ) +#define VDIN1_DNLP_HIST02 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST02 ) +#define VDIN1_DNLP_HIST03 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST03 ) +#define VDIN1_DNLP_HIST04 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST04 ) +#define VDIN1_DNLP_HIST05 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST05 ) +#define VDIN1_DNLP_HIST06 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST06 ) +#define VDIN1_DNLP_HIST07 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST07 ) +#define VDIN1_DNLP_HIST08 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST08 ) +#define VDIN1_DNLP_HIST09 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST09 ) +#define VDIN1_DNLP_HIST10 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST10 ) +#define VDIN1_DNLP_HIST11 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST11 ) +#define VDIN1_DNLP_HIST12 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST12 ) +#define VDIN1_DNLP_HIST13 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST13 ) +#define VDIN1_DNLP_HIST14 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST14 ) +#define VDIN1_DNLP_HIST15 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST15 ) +#define VDIN1_DNLP_HIST16 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST16 ) +#define VDIN1_DNLP_HIST17 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST17 ) +#define VDIN1_DNLP_HIST18 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST18 ) +#define VDIN1_DNLP_HIST19 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST19 ) +#define VDIN1_DNLP_HIST20 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST20 ) +#define VDIN1_DNLP_HIST21 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST21 ) +#define VDIN1_DNLP_HIST22 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST22 ) +#define VDIN1_DNLP_HIST23 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST23 ) +#define VDIN1_DNLP_HIST24 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST24 ) +#define VDIN1_DNLP_HIST25 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST25 ) +#define VDIN1_DNLP_HIST26 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST26 ) +#define VDIN1_DNLP_HIST27 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST27 ) +#define VDIN1_DNLP_HIST28 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST28 ) +#define VDIN1_DNLP_HIST29 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST29 ) +#define VDIN1_DNLP_HIST30 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST30 ) +#define VDIN1_DNLP_HIST31 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST31 ) +#define VDIN1_DNLP_HIST32 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST32 ) +#define VDIN1_MEAS_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_MEAS_CTRL0 ) +#define VDIN1_MEAS_VS_COUNT_HI ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_HI ) +#define VDIN1_MEAS_VS_COUNT_LO ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_LO ) +#define VDIN1_MEAS_HS_RANGE ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_RANGE ) +#define VDIN1_MEAS_HS_COUNT ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_COUNT ) +#define VDIN1_BLKBAR_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL1 ) +#define VDIN1_BLKBAR_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL0 ) +#define VDIN1_BLKBAR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_H_START_END ) +#define VDIN1_BLKBAR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_V_START_END ) +#define VDIN1_BLKBAR_CNT_THRESHOLD ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CNT_THRESHOLD ) +#define VDIN1_BLKBAR_ROW_TH1_TH2 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_ROW_TH1_TH2 ) +#define VDIN1_BLKBAR_IND_LEFT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT_START_END ) +#define VDIN1_BLKBAR_IND_RIGHT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT_START_END ) +#define VDIN1_BLKBAR_IND_LEFT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT1_CNT ) +#define VDIN1_BLKBAR_IND_LEFT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT2_CNT ) +#define VDIN1_BLKBAR_IND_RIGHT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT1_CNT ) +#define VDIN1_BLKBAR_IND_RIGHT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT2_CNT ) +#define VDIN1_BLKBAR_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS0 ) +#define VDIN1_BLKBAR_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS1 ) +#define VDIN1_WIN_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_H_START_END ) +#define VDIN1_WIN_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_V_START_END ) +#define VDIN1_ASFIFO_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL3 ) +#define VDIN1_LFIFO_URG_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_URG_CTRL ) +#define VDIN1_COM_GCLK_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL2 ) +#define VDIN1_VSHRK_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSHRK_CTRL ) +#define VDIN1_SYNC_MASK ((VDIN1_OFFSET << 2) + VDIN_SYNC_MASK ) +#define VDIN1_DOLBY_DSC_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL0 ) +#define VDIN1_DOLBY_DSC_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL1 ) +#define VDIN1_DOLBY_DSC_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL2 ) +#define VDIN1_DOLBY_DSC_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL3 ) +#define VDIN1_DOLBY_AXI_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL0 ) +#define VDIN1_DOLBY_AXI_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL1 ) +#define VDIN1_DOLBY_AXI_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL2 ) +#define VDIN1_DOLBY_AXI_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL3 ) +#define VDIN1_DOLBY_DSC_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS0) +#define VDIN1_DOLBY_DSC_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS1) +#define VDIN1_DOLBY_DSC_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS2) +#define VDIN1_DOLBY_DSC_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS3) + +#define VDIN1_HDR2_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_CTRL ) +#define VDIN1_HDR2_CLK_GATE ((VDIN1_OFFSET << 2) + VDIN_HDR2_CLK_GATE ) +#define VDIN1_HDR2_MATRIXI_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF00_01 ) +#define VDIN1_HDR2_MATRIXI_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF02_10 ) +#define VDIN1_HDR2_MATRIXI_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF11_12 ) +#define VDIN1_HDR2_MATRIXI_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF20_21 ) +#define VDIN1_HDR2_MATRIXI_COEF22 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF22 ) +#define VDIN1_HDR2_MATRIXI_COEF30_31 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF30_31 ) +#define VDIN1_HDR2_MATRIXI_COEF32_40 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF32_40 ) +#define VDIN1_HDR2_MATRIXI_COEF41_42 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF41_42 ) +#define VDIN1_HDR2_MATRIXI_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_OFFSET0_1 ) +#define VDIN1_HDR2_MATRIXI_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_OFFSET2 ) +#define VDIN1_HDR2_MATRIXI_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 ) +#define VDIN1_HDR2_MATRIXI_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_PRE_OFFSET2 ) +#define VDIN1_HDR2_MATRIXO_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF00_01 ) +#define VDIN1_HDR2_MATRIXO_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF02_10 ) +#define VDIN1_HDR2_MATRIXO_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF11_12 ) +#define VDIN1_HDR2_MATRIXO_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF20_21 ) +#define VDIN1_HDR2_MATRIXO_COEF22 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF22 ) +#define VDIN1_HDR2_MATRIXO_COEF30_31 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF30_31 ) +#define VDIN1_HDR2_MATRIXO_COEF32_40 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF32_40 ) +#define VDIN1_HDR2_MATRIXO_COEF41_42 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF41_42 ) +#define VDIN1_HDR2_MATRIXO_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_OFFSET0_1 ) +#define VDIN1_HDR2_MATRIXO_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_OFFSET2 ) +#define VDIN1_HDR2_MATRIXO_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 ) +#define VDIN1_HDR2_MATRIXO_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_PRE_OFFSET2 ) +#define VDIN1_HDR2_MATRIXI_CLIP ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_CLIP ) +#define VDIN1_HDR2_MATRIXO_CLIP ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_CLIP ) +#define VDIN1_HDR2_CGAIN_OFFT ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_OFFT ) +#define VDIN1_EOTF_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_EOTF_LUT_ADDR_PORT ) +#define VDIN1_EOTF_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_EOTF_LUT_DATA_PORT ) +#define VDIN1_OETF_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_OETF_LUT_ADDR_PORT ) +#define VDIN1_OETF_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_OETF_LUT_DATA_PORT ) +#define VDIN1_OGAIN_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_OGAIN_LUT_ADDR_PORT ) +#define VDIN1_OGAIN_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_OGAIN_LUT_DATA_PORT ) +#define VDIN1_CGAIN_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CGAIN_LUT_ADDR_PORT ) +#define VDIN1_CGAIN_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CGAIN_LUT_DATA_PORT ) +#define VDIN1_HDR2_CGAIN_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_COEF0 ) +#define VDIN1_HDR2_CGAIN_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_COEF1 ) +#define VDIN1_HDR2_ADPS_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_CTRL ) +#define VDIN1_HDR2_ADPS_ALPHA0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_ALPHA0 ) +#define VDIN1_HDR2_ADPS_ALPHA1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_ALPHA1 ) +#define VDIN1_HDR2_ADPS_BETA0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA0 ) +#define VDIN1_HDR2_ADPS_BETA1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA1 ) +#define VDIN1_HDR2_ADPS_BETA2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA2 ) +#define VDIN1_HDR2_ADPS_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_COEF0 ) +#define VDIN1_HDR2_ADPS_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_COEF1 ) +#define VDIN1_HDR2_GMUT_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_CTRL ) +#define VDIN1_HDR2_GMUT_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF0 ) +#define VDIN1_HDR2_GMUT_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF1 ) +#define VDIN1_HDR2_GMUT_COEF2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF2 ) +#define VDIN1_HDR2_GMUT_COEF3 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF3 ) +#define VDIN1_HDR2_GMUT_COEF4 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF4 ) +#define VDIN1_HDR2_PIPE_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL1 ) +#define VDIN1_HDR2_PIPE_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL2 ) +#define VDIN1_HDR2_PIPE_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL3 ) +#define VDIN1_HDR2_PROC_WIN1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PROC_WIN1 ) +#define VDIN1_HDR2_PROC_WIN2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PROC_WIN2 ) +#define VDIN1_HDR2_MATRIXI_EN_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_EN_CTRL ) +#define VDIN1_HDR2_MATRIXO_EN_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_EN_CTRL ) +#define VDIN1_HDR2_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_CTRL ) +#define VDIN1_HDR2_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_H_START_END ) +#define VDIN1_HDR2_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_V_START_END ) +#define VDIN1_HDR2_HIST_RD ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_RD ) + + + +#define VDIN1_CRC_CTRL ((VDIN1_OFFSET << 2) + VDIN_CRC_CTRL) +#define VDIN1_RO_CRC ((VDIN1_OFFSET << 2) + VDIN_RO_CRC ) +#define VDIN1_LINE_INT ((VDIN1_OFFSET << 2) + VDIN_LINE_INT) +#define VDIN1_WR_URGENT_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_URGENT_CTRL) +#define VDIN1_RO_WRMIF_STATUS ((VDIN1_OFFSET << 2) + VDIN_RO_WRMIF_STATUS) + +#define VDIN1_DSC_CTRL ((VDIN1_OFFSET << 2) + VDIN_DSC_CTRL ) +#define VDIN1_CFMT_CTRL ((VDIN1_OFFSET << 2) + VDIN_CFMT_CTRL ) +#define VDIN1_CFMT_W ((VDIN1_OFFSET << 2) + VDIN_CFMT_W ) +#define VDIN1_SCB_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL0 ) +#define VDIN1_SCB_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL1 ) +#define VDIN1_DSC_HSIZE ((VDIN1_OFFSET << 2) + VDIN_DSC_HSIZE ) +#define VDIN1_DSC_DETUNNEL_SEL ((VDIN1_OFFSET << 2) + VDIN_DSC_DETUNNEL_SEL) +#define VDIN1_DSC_TUNNEL_SEL ((VDIN1_OFFSET << 2) + VDIN_DSC_TUNNEL_SEL) +#define VDIN1_DITH_CTRL ((VDIN1_OFFSET << 2) + VDIN_DITH_CTRL ) +#define VDIN1_DITH_LUT_1 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_1 ) +#define VDIN1_DITH_LUT_2 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_2 ) +#define VDIN1_DITH_LUT_3 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_3 ) +#define VDIN1_DITH_LUT_4 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_4 ) +#define VDIN1_DITH_LUT_5 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_5 ) +#define VDIN1_DITH_LUT_6 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_6 ) +#define VDIN1_DITH_LUT_7 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_7 ) +#define VDIN1_DITH_LUT_8 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_8 ) +#define VDIN1_DITH_LUT_9 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_9 ) +#define VDIN1_DITH_LUT_10 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_10 ) +#define VDIN1_DITH_LUT_11 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_11 ) +#define VDIN1_DITH_LUT_12 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_12 ) + +#define VDIN1_HSK_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSK_CTRL ) +#define VDIN1_HSK_COEF_0 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_0 ) +#define VDIN1_HSK_COEF_1 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_1 ) +#define VDIN1_HSK_COEF_2 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_2 ) +#define VDIN1_HSK_COEF_3 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_3 ) +#define VDIN1_HSK_COEF_4 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_4 ) +#define VDIN1_HSK_COEF_5 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_5 ) +#define VDIN1_HSK_COEF_6 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_6 ) +#define VDIN1_HSK_COEF_7 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_7 ) +#define VDIN1_HSK_COEF_8 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_8 ) +#define VDIN1_HSK_COEF_9 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_9 ) +#define VDIN1_HSK_COEF_A ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_A ) +#define VDIN1_HSK_COEF_B ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_B ) +#define VDIN1_HSK_COEF_C ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_C ) +#define VDIN1_HSK_COEF_D ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_D ) +#define VDIN1_HSK_COEF_E ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_E ) +#define VDIN1_HSK_COEF_F ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_F ) + +#define VDIN1_HDR2_SIZE ((VDIN1_OFFSET << 2) + VDIN_HDR2_SIZE ) +#define VDIN1_VSHRK_SIZE_M1 ((VDIN1_OFFSET << 2) + VDIN_VSHRK_SIZE_M1) + + + +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_vdin1_regs.h +// +// +// Reading file: lcd_regs.h +// +// ----------------------------------------------- +// REG_BASE: LCD_VCBUS_BASE = 0x14 +// ----------------------------------------------- +//======================================================================== +//LCD DRV 12'h480~12'h4ef +//======================================================================= +#define L_GAMMA_CNTL_PORT ((0x1400 << 2) + 0xff000000) +#define L_GAMMA_DATA_PORT ((0x1401 << 2) + 0xff000000) +#define L_GAMMA_ADDR_PORT ((0x1402 << 2) + 0xff000000) +#define L_GAMMA_VCOM_HSWITCH_ADDR ((0x1403 << 2) + 0xff000000) +#define L_RGB_BASE_ADDR ((0x1405 << 2) + 0xff000000) +#define L_RGB_COEFF_ADDR ((0x1406 << 2) + 0xff000000) +#define L_POL_CNTL_ADDR ((0x1407 << 2) + 0xff000000) +#define L_DITH_CNTL_ADDR ((0x1408 << 2) + 0xff000000) +#define L_GAMMA_PROBE_CTRL ((0x1409 << 2) + 0xff000000) +//read only +#define L_GAMMA_PROBE_COLOR_L ((0x140a << 2) + 0xff000000) +#define L_GAMMA_PROBE_COLOR_H ((0x140b << 2) + 0xff000000) +#define L_GAMMA_PROBE_HL_COLOR ((0x140c << 2) + 0xff000000) +#define L_GAMMA_PROBE_POS_X ((0x140d << 2) + 0xff000000) +#define L_GAMMA_PROBE_POS_Y ((0x140e << 2) + 0xff000000) +#define L_STH1_HS_ADDR ((0x1410 << 2) + 0xff000000) +#define L_STH1_HE_ADDR ((0x1411 << 2) + 0xff000000) +#define L_STH1_VS_ADDR ((0x1412 << 2) + 0xff000000) +#define L_STH1_VE_ADDR ((0x1413 << 2) + 0xff000000) +#define L_STH2_HS_ADDR ((0x1414 << 2) + 0xff000000) +#define L_STH2_HE_ADDR ((0x1415 << 2) + 0xff000000) +#define L_STH2_VS_ADDR ((0x1416 << 2) + 0xff000000) +#define L_STH2_VE_ADDR ((0x1417 << 2) + 0xff000000) +#define L_OEH_HS_ADDR ((0x1418 << 2) + 0xff000000) +#define L_OEH_HE_ADDR ((0x1419 << 2) + 0xff000000) +#define L_OEH_VS_ADDR ((0x141a << 2) + 0xff000000) +#define L_OEH_VE_ADDR ((0x141b << 2) + 0xff000000) +#define L_VCOM_HSWITCH_ADDR ((0x141c << 2) + 0xff000000) +#define L_VCOM_VS_ADDR ((0x141d << 2) + 0xff000000) +#define L_VCOM_VE_ADDR ((0x141e << 2) + 0xff000000) +#define L_CPV1_HS_ADDR ((0x141f << 2) + 0xff000000) +#define L_CPV1_HE_ADDR ((0x1420 << 2) + 0xff000000) +#define L_CPV1_VS_ADDR ((0x1421 << 2) + 0xff000000) +#define L_CPV1_VE_ADDR ((0x1422 << 2) + 0xff000000) +#define L_CPV2_HS_ADDR ((0x1423 << 2) + 0xff000000) +#define L_CPV2_HE_ADDR ((0x1424 << 2) + 0xff000000) +#define L_CPV2_VS_ADDR ((0x1425 << 2) + 0xff000000) +#define L_CPV2_VE_ADDR ((0x1426 << 2) + 0xff000000) +#define L_STV1_HS_ADDR ((0x1427 << 2) + 0xff000000) +#define L_STV1_HE_ADDR ((0x1428 << 2) + 0xff000000) +#define L_STV1_VS_ADDR ((0x1429 << 2) + 0xff000000) +#define L_STV1_VE_ADDR ((0x142a << 2) + 0xff000000) +#define L_STV2_HS_ADDR ((0x142b << 2) + 0xff000000) +#define L_STV2_HE_ADDR ((0x142c << 2) + 0xff000000) +#define L_STV2_VS_ADDR ((0x142d << 2) + 0xff000000) +#define L_STV2_VE_ADDR ((0x142e << 2) + 0xff000000) +#define L_OEV1_HS_ADDR ((0x142f << 2) + 0xff000000) +#define L_OEV1_HE_ADDR ((0x1430 << 2) + 0xff000000) +#define L_OEV1_VS_ADDR ((0x1431 << 2) + 0xff000000) +#define L_OEV1_VE_ADDR ((0x1432 << 2) + 0xff000000) +#define L_OEV2_HS_ADDR ((0x1433 << 2) + 0xff000000) +#define L_OEV2_HE_ADDR ((0x1434 << 2) + 0xff000000) +#define L_OEV2_VS_ADDR ((0x1435 << 2) + 0xff000000) +#define L_OEV2_VE_ADDR ((0x1436 << 2) + 0xff000000) +#define L_OEV3_HS_ADDR ((0x1437 << 2) + 0xff000000) +#define L_OEV3_HE_ADDR ((0x1438 << 2) + 0xff000000) +#define L_OEV3_VS_ADDR ((0x1439 << 2) + 0xff000000) +#define L_OEV3_VE_ADDR ((0x143a << 2) + 0xff000000) +#define L_LCD_PWR_ADDR ((0x143b << 2) + 0xff000000) +#define L_LCD_PWM0_LO_ADDR ((0x143c << 2) + 0xff000000) +#define L_LCD_PWM0_HI_ADDR ((0x143d << 2) + 0xff000000) +#define L_LCD_PWM1_LO_ADDR ((0x143e << 2) + 0xff000000) +#define L_LCD_PWM1_HI_ADDR ((0x143f << 2) + 0xff000000) +#define L_INV_CNT_ADDR ((0x1440 << 2) + 0xff000000) +#define L_TCON_MISC_SEL_ADDR ((0x1441 << 2) + 0xff000000) +#define L_DUAL_PORT_CNTL_ADDR ((0x1442 << 2) + 0xff000000) +#define MLVDS_CLK_CTL1_HI ((0x1443 << 2) + 0xff000000) +#define MLVDS_CLK_CTL1_LO ((0x1444 << 2) + 0xff000000) +// [31:30] enable mlvds clocks +// [24] mlvds_clk_half_delay 24 // Bit 0 +// [23:0] mlvds_clk_pattern 0 // Bit 23:0 +#define L_TCON_DOUBLE_CTL ((0x1449 << 2) + 0xff000000) +#define L_TCON_PATTERN_HI ((0x144a << 2) + 0xff000000) +#define L_TCON_PATTERN_LO ((0x144b << 2) + 0xff000000) +#define LDIM_BL_ADDR_PORT ((0x144e << 2) + 0xff000000) +#define LDIM_BL_DATA_PORT ((0x144f << 2) + 0xff000000) +#define L_DE_HS_ADDR ((0x1451 << 2) + 0xff000000) +#define L_DE_HE_ADDR ((0x1452 << 2) + 0xff000000) +#define L_DE_VS_ADDR ((0x1453 << 2) + 0xff000000) +#define L_DE_VE_ADDR ((0x1454 << 2) + 0xff000000) +#define L_HSYNC_HS_ADDR ((0x1455 << 2) + 0xff000000) +#define L_HSYNC_HE_ADDR ((0x1456 << 2) + 0xff000000) +#define L_HSYNC_VS_ADDR ((0x1457 << 2) + 0xff000000) +#define L_HSYNC_VE_ADDR ((0x1458 << 2) + 0xff000000) +#define L_VSYNC_HS_ADDR ((0x1459 << 2) + 0xff000000) +#define L_VSYNC_HE_ADDR ((0x145a << 2) + 0xff000000) +#define L_VSYNC_VS_ADDR ((0x145b << 2) + 0xff000000) +#define L_VSYNC_VE_ADDR ((0x145c << 2) + 0xff000000) +// bit 8 -- vfifo_mcu_enable +// bit 7 -- halt_vs_de +// bit 6 -- R8G8B8_format +// bit 5 -- R6G6B6_format (round to 6 bits) +// bit 4 -- R5G6B5_format +// bit 3 -- dac_dith_sel +// bit 2 -- lcd_mcu_enable_de -- ReadOnly +// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly +// bit 0 -- lcd_mcu_enable +#define L_LCD_MCU_CTL ((0x145d << 2) + 0xff000000) +//************************************************************************** +//* Dual port mLVDS registers +//************************************************************************** +// bit 3 - enable_u_dual_mlvds_dp_clk +// bit 2 - enable_u_map_mlvds_r_clk +// bit 1 - enable_u_map_mlvds_l_clk +// bit 0 - dual_mlvds_en +//`define DUAL_MLVDS_CTL 8'h60 +// bit[12:0] - dual_mlvds_line_start +//`define DUAL_MLVDS_LINE_START 8'h61 +// bit[12:0] - dual_mlvds_line_end +//`define DUAL_MLVDS_LINE_END 8'h62 +// bit[12:0] - dual_mlvds_w_pixel_start_l +//`define DUAL_MLVDS_PIXEL_W_START_L 8'h63 +// bit[12:0] - dual_mlvds_w_pixel_end_l +//`define DUAL_MLVDS_PIXEL_W_END_L 8'h64 +// bit[12:0] - dual_mlvds_w_pixel_start_r +//`define DUAL_MLVDS_PIXEL_W_START_R 8'h65 +// bit[12:0] - dual_mlvds_w_pixel_end_r +//`define DUAL_MLVDS_PIXEL_W_END_R 8'h66 +// bit[12:0] - dual_mlvds_r_pixel_start_l +//`define DUAL_MLVDS_PIXEL_R_START_L 8'h67 +// bit[12:0] - dual_mlvds_r_pixel_cnt_l +//`define DUAL_MLVDS_PIXEL_R_CNT_L 8'h68 +// bit[12:0] - dual_mlvds_r_pixel_start_r +//`define DUAL_MLVDS_PIXEL_R_START_R 8'h69 +// bit[12:0] - dual_mlvds_r_pixel_cnt_r +//`define DUAL_MLVDS_PIXEL_R_CNT_R 8'h6a +// bit[15] - v_inversion_en +// bit[12:0] - v_inversion_pixel +//`define V_INVERSION_PIXEL 8'h70 +// bit[15] - v_inversion_sync_en +// bit[12:0] - v_inversion_line +//`define V_INVERSION_LINE 8'h71 +// bit[15:12] - v_loop_r +// bit[11:10] - v_pattern_1_r +// bit[9:8] - v_pattern_0_r +// bit[7:4] - v_loop_l +// bit[3:2] - v_pattern_1_l +// bit[1:0] - v_pattern_0_l +//`define V_INVERSION_CONTROL 8'h72 +//`define MLVDS2_CONTROL 8'h74 + #define mLVDS2_RESERVED 15 // 15 + #define mLVDS2_double_pattern 14 // 14 + #define mLVDS2_ins_reset 8 // 13:8 // each channel has one bit + #define mLVDS2_dual_gate 7 + #define mLVDS2_bit_num 6 // 0-6Bits, 1-8Bits + #define mLVDS2_pair_num 5 // 0-3Pairs, 1-6Pairs + #define mLVDS2_msb_first 4 + #define mLVDS2_PORT_SWAP 3 + #define mLVDS2_MLSB_SWAP 2 + #define mLVDS2_PN_SWAP 1 + #define mLVDS2_en 0 +//`define MLVDS2_CONFIG_HI 8'h75 +//`define MLVDS2_CONFIG_LO 8'h76 + #define mLVDS2_reset_offset 29 // Bit 31:29 + #define mLVDS2_reset_length 23 // Bit 28:23 + #define mLVDS2_config_reserved 20 // Bit 22:20 + #define mLVDS2_reset_start_bit12 19 // Bit 19 + #define mLVDS2_data_write_toggle 18 + #define mLVDS2_data_write_ini 17 + #define mLVDS2_data_latch_1_toggle 16 + #define mLVDS2_data_latch_1_ini 15 + #define mLVDS2_data_latch_0_toggle 14 + #define mLVDS2_data_latch_0_ini 13 + #define mLVDS2_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0 + #define mLVDS2_reset_start 0 // Bit 11:0 +//`define MLVDS2_DUAL_GATE_WR_START 8'h77 +// `define mlvds2_dual_gate_wr_start 0 // Bit 12:0 +//`define MLVDS2_DUAL_GATE_WR_END 8'h78 +// `define mlvds2_dual_gate_wr_end 0 // Bit 12:0 +// +//`define MLVDS2_DUAL_GATE_RD_START 8'h79 +// `define mlvds2_dual_gate_rd_start 0 // Bit 12:0 +//`define MLVDS2_DUAL_GATE_RD_END 8'h7a +// `define mlvds2_dual_gate_rd_end 0 // Bit 12:0 +//`define MLVDS2_SECOND_RESET_CTL 8'h7b +// `define mLVDS2_2nd_reset_start 0 // Bit 12:0 +// +//`define MLVDS2_DUAL_GATE_CTL_HI 8'h7c +//`define MLVDS2_DUAL_GATE_CTL_LO 8'h7d +// `define mlvds2_tcon_field_en 24 // Bit 7:0 +// `define mlvds2_dual_gate_reserved 21 // Bit 2:0 +// `define mlvds2_scan_mode_start_line_bit12 20 // Bit 0 +// `define mlvds2_scan_mode_odd 16 // Bit 3:0 +// `define mlvds2_scan_mode_even 12 // Bit 3:0 +// `define mlvds2_scan_mode_start_line 0 // Bit 11:0 +// +//`define MLVDS2_RESET_CONFIG_HI 8'h7e +//`define MLVDS2_RESET_CONFIG_LO 8'h7f +// `define mLVDS2_reset_range_enable 31 // Bit 0 +// `define mLVDS2_reset_range_inv 30 // Bit 0 +// `define mLVDS2_reset_config_res1 29 // Bit 0 +// `define mLVDS2_reset_range_line_0 16 // Bit 11:0 +// `define mLVDS2_reset_config_res3 13 // Bit 2:0 +// `define mLVDS2_reset_range_line_1 0 // Bit 11:0 +// +//************************************************************************** +//* Vbyone registers (Note: no MinLVDS in G9tv, share the register) +//************************************************************************** +#define VBO_CTRL_L ((0x1460 << 2) + 0xff000000) +#define VBO_CTRL_H ((0x1461 << 2) + 0xff000000) +#define VBO_SOFT_RST ((0x1462 << 2) + 0xff000000) +#define VBO_LANES ((0x1463 << 2) + 0xff000000) +#define VBO_VIN_CTRL ((0x1464 << 2) + 0xff000000) +#define VBO_ACT_VSIZE ((0x1465 << 2) + 0xff000000) +#define VBO_REGION_00 ((0x1466 << 2) + 0xff000000) +#define VBO_REGION_01 ((0x1467 << 2) + 0xff000000) +#define VBO_REGION_02 ((0x1468 << 2) + 0xff000000) +#define VBO_REGION_03 ((0x1469 << 2) + 0xff000000) +#define VBO_VBK_CTRL_0 ((0x146a << 2) + 0xff000000) +#define VBO_VBK_CTRL_1 ((0x146b << 2) + 0xff000000) +#define VBO_HBK_CTRL ((0x146c << 2) + 0xff000000) +#define VBO_PXL_CTRL ((0x146d << 2) + 0xff000000) +#define VBO_LANE_SKEW_L ((0x146e << 2) + 0xff000000) +#define VBO_LANE_SKEW_H ((0x146f << 2) + 0xff000000) +#define VBO_GCLK_LANE_L ((0x1470 << 2) + 0xff000000) +#define VBO_GCLK_LANE_H ((0x1471 << 2) + 0xff000000) +#define VBO_GCLK_MAIN ((0x1472 << 2) + 0xff000000) +#define VBO_STATUS_L ((0x1473 << 2) + 0xff000000) +#define VBO_STATUS_H ((0x1474 << 2) + 0xff000000) +#define VBO_LANE_OUTPUT ((0x1475 << 2) + 0xff000000) +#define LCD_PORT_SWAP ((0x1476 << 2) + 0xff000000) +#define VBO_TMCHK_THRD_L ((0x1478 << 2) + 0xff000000) +#define VBO_TMCHK_THRD_H ((0x1479 << 2) + 0xff000000) +#define VBO_FSM_HOLDER_L ((0x147a << 2) + 0xff000000) +#define VBO_FSM_HOLDER_H ((0x147b << 2) + 0xff000000) +#define VBO_INTR_STATE_CTRL ((0x147c << 2) + 0xff000000) +#define VBO_INTR_UNMASK ((0x147d << 2) + 0xff000000) +#define VBO_TMCHK_HSYNC_STATE_L ((0x147e << 2) + 0xff000000) +#define VBO_TMCHK_HSYNC_STATE_H ((0x147f << 2) + 0xff000000) +#define VBO_TMCHK_VSYNC_STATE_L ((0x14f4 << 2) + 0xff000000) +#define VBO_TMCHK_VSYNC_STATE_H ((0x14f5 << 2) + 0xff000000) +#define VBO_TMCHK_VDE_STATE_L ((0x14f6 << 2) + 0xff000000) +#define VBO_TMCHK_VDE_STATE_H ((0x14f7 << 2) + 0xff000000) +#define VBO_INTR_STATE ((0x14f8 << 2) + 0xff000000) +#define VBO_INFILTER_CTRL ((0x14f9 << 2) + 0xff000000) +#define VBO_INSGN_CTRL ((0x14fa << 2) + 0xff000000) +#define VBO_INFILTER_CTRL_H ((0x1477 << 2) + 0xff000000) +//************************************************************************** +//* NOTE:: When Programming the Gamma, please turn off the IRQ service * +//************************************************************************** +#define GAMMA_CNTL_PORT ((0x1480 << 2) + 0xff000000) + #define GAMMA_VCOM_POL 7 //RW + #define GAMMA_RVS_OUT 6 //RW + #define ADR_RDY 5 //Read Only + #define WR_RDY 4 //Read Only + #define RD_RDY 3 //Read Only + #define GAMMA_TR 2 //RW + #define GAMMA_SET 1 //RW + #define GAMMA_EN 0 //RW +#define GAMMA_DATA_PORT ((0x1481 << 2) + 0xff000000) +#define GAMMA_ADDR_PORT ((0x1482 << 2) + 0xff000000) + #define H_RD 12 + #define H_AUTO_INC 11 + #define H_SEL_R 10 + #define H_SEL_G 9 + #define H_SEL_B 8 + #define HADR_MSB 7 //7:0 + #define HADR 0 //7:0 +#define GAMMA_VCOM_HSWITCH_ADDR ((0x1483 << 2) + 0xff000000) +#define RGB_BASE_ADDR ((0x1485 << 2) + 0xff000000) +#define RGB_COEFF_ADDR ((0x1486 << 2) + 0xff000000) +#define POL_CNTL_ADDR ((0x1487 << 2) + 0xff000000) + #define DCLK_SEL 14 //FOR DCLK OUTPUT + #define TCON_VSYNC_SEL_DVI 11 //FOR RGB format DVI output + #define TCON_HSYNC_SEL_DVI 10 //FOR RGB format DVI output + #define TCON_DE_SEL_DVI 9 //FOR RGB format DVI output + #define CPH3_POL 8 + #define CPH2_POL 7 + #define CPH1_POL 6 + #define TCON_DE_SEL 5 + #define TCON_VS_SEL 4 + #define TCON_HS_SEL 3 + #define DE_POL 2 + #define VS_POL 1 + #define HS_POL 0 +#define DITH_CNTL_ADDR ((0x1488 << 2) + 0xff000000) + #define DITH10_EN 10 + #define DITH8_EN 9 + #define DITH_MD 8 + #define DITH10_CNTL_MSB 7 //7:4 + #define DITH10_CNTL 4 //7:4 + #define DITH8_CNTL_MSB 3 //3:0 + #define DITH8_CNTL 0 //3:0 +//Bit 1 highlight_en +//Bit 0 probe_en +#define GAMMA_PROBE_CTRL ((0x1489 << 2) + 0xff000000) +//read only +//Bit [15:0] probe_color[15:0] +#define GAMMA_PROBE_COLOR_L ((0x148a << 2) + 0xff000000) +//Read only +//Bit 15: if true valid probed color +//Bit [13:0] probe_color[29:16] +#define GAMMA_PROBE_COLOR_H ((0x148b << 2) + 0xff000000) +//bit 15:0, 5:6:5 color +#define GAMMA_PROBE_HL_COLOR ((0x148c << 2) + 0xff000000) +//12:0 pos_x +#define GAMMA_PROBE_POS_X ((0x148d << 2) + 0xff000000) +//12:0 pos_y +#define GAMMA_PROBE_POS_Y ((0x148e << 2) + 0xff000000) +#define STH1_HS_ADDR ((0x1490 << 2) + 0xff000000) +#define STH1_HE_ADDR ((0x1491 << 2) + 0xff000000) +#define STH1_VS_ADDR ((0x1492 << 2) + 0xff000000) +#define STH1_VE_ADDR ((0x1493 << 2) + 0xff000000) +#define STH2_HS_ADDR ((0x1494 << 2) + 0xff000000) +#define STH2_HE_ADDR ((0x1495 << 2) + 0xff000000) +#define STH2_VS_ADDR ((0x1496 << 2) + 0xff000000) +#define STH2_VE_ADDR ((0x1497 << 2) + 0xff000000) +#define OEH_HS_ADDR ((0x1498 << 2) + 0xff000000) +#define OEH_HE_ADDR ((0x1499 << 2) + 0xff000000) +#define OEH_VS_ADDR ((0x149a << 2) + 0xff000000) +#define OEH_VE_ADDR ((0x149b << 2) + 0xff000000) +#define VCOM_HSWITCH_ADDR ((0x149c << 2) + 0xff000000) +#define VCOM_VS_ADDR ((0x149d << 2) + 0xff000000) +#define VCOM_VE_ADDR ((0x149e << 2) + 0xff000000) +#define CPV1_HS_ADDR ((0x149f << 2) + 0xff000000) +#define CPV1_HE_ADDR ((0x14a0 << 2) + 0xff000000) +#define CPV1_VS_ADDR ((0x14a1 << 2) + 0xff000000) +#define CPV1_VE_ADDR ((0x14a2 << 2) + 0xff000000) +#define CPV2_HS_ADDR ((0x14a3 << 2) + 0xff000000) +#define CPV2_HE_ADDR ((0x14a4 << 2) + 0xff000000) +#define CPV2_VS_ADDR ((0x14a5 << 2) + 0xff000000) +#define CPV2_VE_ADDR ((0x14a6 << 2) + 0xff000000) +#define STV1_HS_ADDR ((0x14a7 << 2) + 0xff000000) +#define STV1_HE_ADDR ((0x14a8 << 2) + 0xff000000) +#define STV1_VS_ADDR ((0x14a9 << 2) + 0xff000000) +#define STV1_VE_ADDR ((0x14aa << 2) + 0xff000000) +#define STV2_HS_ADDR ((0x14ab << 2) + 0xff000000) +#define STV2_HE_ADDR ((0x14ac << 2) + 0xff000000) +#define STV2_VS_ADDR ((0x14ad << 2) + 0xff000000) +#define STV2_VE_ADDR ((0x14ae << 2) + 0xff000000) +#define OEV1_HS_ADDR ((0x14af << 2) + 0xff000000) +#define OEV1_HE_ADDR ((0x14b0 << 2) + 0xff000000) +#define OEV1_VS_ADDR ((0x14b1 << 2) + 0xff000000) +#define OEV1_VE_ADDR ((0x14b2 << 2) + 0xff000000) +#define OEV2_HS_ADDR ((0x14b3 << 2) + 0xff000000) +#define OEV2_HE_ADDR ((0x14b4 << 2) + 0xff000000) +#define OEV2_VS_ADDR ((0x14b5 << 2) + 0xff000000) +#define OEV2_VE_ADDR ((0x14b6 << 2) + 0xff000000) +#define OEV3_HS_ADDR ((0x14b7 << 2) + 0xff000000) +#define OEV3_HE_ADDR ((0x14b8 << 2) + 0xff000000) +#define OEV3_VS_ADDR ((0x14b9 << 2) + 0xff000000) +#define OEV3_VE_ADDR ((0x14ba << 2) + 0xff000000) +#define LCD_PWR_ADDR ((0x14bb << 2) + 0xff000000) + #define LCD_VDD 5 + #define LCD_VBL 4 + #define LCD_GPI_MSB 3 + #define LCD_GPIO 0 +#define LCD_PWM0_LO_ADDR ((0x14bc << 2) + 0xff000000) +#define LCD_PWM0_HI_ADDR ((0x14bd << 2) + 0xff000000) +#define LCD_PWM1_LO_ADDR ((0x14be << 2) + 0xff000000) +#define LCD_PWM1_HI_ADDR ((0x14bf << 2) + 0xff000000) +#define INV_CNT_ADDR ((0x14c0 << 2) + 0xff000000) + #define INV_EN 4 + #define INV_CNT_MSB 3 + #define INV_CNT 0 +#define TCON_MISC_SEL_ADDR ((0x14c1 << 2) + 0xff000000) + #define STH2_SEL 12 + #define STH1_SEL 11 + #define OEH_SEL 10 + #define VCOM_SEL 9 + #define DB_LINE_SW 8 + #define CPV2_SEL 7 + #define CPV1_SEL 6 + #define STV2_SEL 5 + #define STV1_SEL 4 + #define OEV_UNITE 3 + #define OEV3_SEL 2 + #define OEV2_SEL 1 + #define OEV1_SEL 0 +#define DUAL_PORT_CNTL_ADDR ((0x14c2 << 2) + 0xff000000) + #define OUTPUT_YUV 15 + #define DUAL_IDF 12 // 14:12 + #define DUAL_ISF 9 // 11:9 + #define LCD_ANALOG_SEL_CPH3 8 + #define LCD_ANALOG_3PHI_CLK_SEL 7 + #define LCD_LVDS_SEL54 6 + #define LCD_LVDS_SEL27 5 + #define LCD_TTL_SEL 4 + #define DUAL_LVDC_EN 3 + #define PORT_SWP 2 + #define RGB_SWP 1 + #define BIT_SWP 0 +#define MLVDS_CONTROL ((0x14c3 << 2) + 0xff000000) + #define mLVDS_RESERVED 15 // 15 + #define mLVDS_double_pattern 14 // 14 + #define mLVDS_ins_reset 8 // 13:8 // each channel has one bit + #define mLVDS_dual_gate 7 + #define mLVDS_bit_num 6 // 0-6Bits, 1-8Bits + #define mLVDS_pair_num 5 // 0-3Pairs, 1-6Pairs + #define mLVDS_msb_first 4 + #define mLVDS_PORT_SWAP 3 + #define mLVDS_MLSB_SWAP 2 + #define mLVDS_PN_SWAP 1 + #define mLVDS_en 0 +#define MLVDS_RESET_PATTERN_HI ((0x14c4 << 2) + 0xff000000) +#define MLVDS_RESET_PATTERN_LO ((0x14c5 << 2) + 0xff000000) + #define mLVDS_reset_pattern 0 // Bit 47:16 +#define MLVDS_RESET_PATTERN_EXT ((0x14c6 << 2) + 0xff000000) + #define mLVDS_reset_pattern_ext 0 // Bit 15:0 +#define MLVDS_CONFIG_HI ((0x14c7 << 2) + 0xff000000) +#define MLVDS_CONFIG_LO ((0x14c8 << 2) + 0xff000000) + #define mLVDS_reset_offset 29 // Bit 31:29 + #define mLVDS_reset_length 23 // Bit 28:23 + #define mLVDS_config_reserved 20 // Bit 22:20 + #define mLVDS_reset_start_bit12 19 // Bit 19 + #define mLVDS_data_write_toggle 18 + #define mLVDS_data_write_ini 17 + #define mLVDS_data_latch_1_toggle 16 + #define mLVDS_data_latch_1_ini 15 + #define mLVDS_data_latch_0_toggle 14 + #define mLVDS_data_latch_0_ini 13 + #define mLVDS_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0 + #define mLVDS_reset_start 0 // Bit 11:0 +#define TCON_DOUBLE_CTL ((0x14c9 << 2) + 0xff000000) + #define tcon_double_ini 8 // Bit 7:0 + #define tcon_double_inv 0 // Bit 7:0 +#define TCON_PATTERN_HI ((0x14ca << 2) + 0xff000000) +#define TCON_PATTERN_LO ((0x14cb << 2) + 0xff000000) + #define tcon_pattern_loop_data 16 // Bit 15:0 + #define tcon_pattern_loop_start 12 // Bit 3:0 + #define tcon_pattern_loop_end 8 // Bit 3:0 + #define tcon_pattern_enable 0 // Bit 7:0 +#define TCON_CONTROL_HI ((0x14cc << 2) + 0xff000000) +#define TCON_CONTROL_LO ((0x14cd << 2) + 0xff000000) + #define tcon_pclk_enable 26 // Bit 5:0 (enable pclk on TCON channel 7 to 2) + #define tcon_pclk_div 24 // Bit 1:0 (control phy clok divide 2,4,6,8) + #define tcon_delay 0 // Bit 23:0 (3 bit for each channel) +#define LVDS_BLANK_DATA_HI ((0x14ce << 2) + 0xff000000) +#define LVDS_BLANK_DATA_LO ((0x14cf << 2) + 0xff000000) + #define LVDS_blank_data_reserved 30 // 31:30 + #define LVDS_blank_data_r 20 // 29:20 + #define LVDS_blank_data_g 10 // 19:10 + #define LVDS_blank_data_b 0 // 9:0 +#define LVDS_PACK_CNTL_ADDR ((0x14d0 << 2) + 0xff000000) + #define LVDS_USE_TCON 7 + #define LVDS_DUAL 6 + #define PN_SWP 5 + #define LSB_FIRST 4 + #define LVDS_RESV 3 + #define ODD_EVEN_SWP 2 + #define LVDS_REPACK 0 +// New from M3 : +// Bit 15:12 -- Enable OFFSET Double Generate(TOCN7-TCON4) +// Bit 11:0 -- de_hs(old tcon) second offset_hs (new tcon) +#define DE_HS_ADDR ((0x14d1 << 2) + 0xff000000) +// New from M3 : +// Bit 15:12 -- Enable OFFSET Double Generate(TOCN3-TCON0) +#define DE_HE_ADDR ((0x14d2 << 2) + 0xff000000) +#define DE_VS_ADDR ((0x14d3 << 2) + 0xff000000) +#define DE_VE_ADDR ((0x14d4 << 2) + 0xff000000) +#define HSYNC_HS_ADDR ((0x14d5 << 2) + 0xff000000) +#define HSYNC_HE_ADDR ((0x14d6 << 2) + 0xff000000) +#define HSYNC_VS_ADDR ((0x14d7 << 2) + 0xff000000) +#define HSYNC_VE_ADDR ((0x14d8 << 2) + 0xff000000) +#define VSYNC_HS_ADDR ((0x14d9 << 2) + 0xff000000) +#define VSYNC_HE_ADDR ((0x14da << 2) + 0xff000000) +#define VSYNC_VS_ADDR ((0x14db << 2) + 0xff000000) +#define VSYNC_VE_ADDR ((0x14dc << 2) + 0xff000000) +// bit 8 -- vfifo_mcu_enable +// bit 7 -- halt_vs_de +// bit 6 -- R8G8B8_format +// bit 5 -- R6G6B6_format (round to 6 bits) +// bit 4 -- R5G6B5_format +// bit 3 -- dac_dith_sel +// bit 2 -- lcd_mcu_enable_de -- ReadOnly +// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly +// bit 0 -- lcd_mcu_enable +#define LCD_MCU_CTL ((0x14dd << 2) + 0xff000000) +// ReadOnly +// R5G6B5 when R5G6B5_format +// G8R8 when R8G8B8_format +// G5R10 Other +#define LCD_MCU_DATA_0 ((0x14de << 2) + 0xff000000) +// ReadOnly +// G8B8 when R8G8B8_format +// G5B10 Other +#define LCD_MCU_DATA_1 ((0x14df << 2) + 0xff000000) +// LVDS +#define LVDS_GEN_CNTL ((0x14e0 << 2) + 0xff000000) +//`define LVDS_PHY_CNTL0 8'he1 +//`define LVDS_PHY_CNTL1 8'he2 +//`define LVDS_PHY_CNTL2 8'he3 +//`define LVDS_PHY_CNTL3 8'he4 +//`define LVDS_PHY_CNTL4 8'he5 +//`define LVDS_PHY_CNTL5 8'he6 +#define LVDS_SRG_TEST ((0x14e8 << 2) + 0xff000000) +#define LVDS_BIST_MUX0 ((0x14e9 << 2) + 0xff000000) +#define LVDS_BIST_MUX1 ((0x14ea << 2) + 0xff000000) +#define LVDS_BIST_FIXED0 ((0x14eb << 2) + 0xff000000) +#define LVDS_BIST_FIXED1 ((0x14ec << 2) + 0xff000000) +#define LVDS_BIST_CNTL0 ((0x14ed << 2) + 0xff000000) +#define LVDS_CLKB_CLKA ((0x14ee << 2) + 0xff000000) +#define LVDS_PHY_CLK_CNTL ((0x14ef << 2) + 0xff000000) +#define LVDS_SER_EN ((0x14f0 << 2) + 0xff000000) +//`define LVDS_PHY_CNTL6 8'hf1 +//`define LVDS_PHY_CNTL7 8'hf2 +//`define LVDS_PHY_CNTL8 8'hf3 +#define LVDS_CH_SWAP0 ((0x14e1 << 2) + 0xff000000) +#define LVDS_CH_SWAP1 ((0x14e2 << 2) + 0xff000000) +#define LVDS_CH_SWAP2 ((0x14e3 << 2) + 0xff000000) +//`define MLVDS_CLK_CTL0_HI 8'hf4 +//`define MLVDS_CLK_CTL0_LO 8'hf5 +// `define mlvds_clk_pattern_reserved 31 // Bit 31 +// `define mpclk_dly 28 // Bit 2:0 +// `define mpclk_div 26 // Bit 1:0 (control phy clok divide 2,4,6,8) +// `define use_mpclk 25 // Bit 0 +// `define mlvds_clk_half_delay 24 // Bit 0 +// `define mlvds_clk_pattern 0 // Bit 23:0 +//`define MLVDS_DUAL_GATE_WR_START 8'hf6 +// `define mlvds_dual_gate_wr_start 0 // Bit 12:0 +//`define MLVDS_DUAL_GATE_WR_END 8'hf7 +// `define mlvds_dual_gate_wr_end 0 // Bit 12:0 +// +//`define MLVDS_DUAL_GATE_RD_START 8'hf8 +// `define mlvds_dual_gate_rd_start 0 // Bit 12:0 +//`define MLVDS_DUAL_GATE_RD_END 8'hf9 +// `define mlvds_dual_gate_rd_end 0 // Bit 12:0 +//`define MLVDS_SECOND_RESET_CTL 8'hfa +// `define mLVDS_2nd_reset_start 0 // Bit 12:0 +// +#define MLVDS_DUAL_GATE_CTL_HI ((0x14fb << 2) + 0xff000000) +#define MLVDS_DUAL_GATE_CTL_LO ((0x14fc << 2) + 0xff000000) +// `define mlvds_tcon_field_en 24 // Bit 7:0 +// `define mlvds_dual_gate_reserved 21 // Bit 2:0 +// `define mlvds_scan_mode_start_line_bit12 20 // Bit 0 +// `define mlvds_scan_mode_odd 16 // Bit 3:0 +// `define mlvds_scan_mode_even 12 // Bit 3:0 +// `define mlvds_scan_mode_start_line 0 // Bit 11:0 +// +//`define MLVDS_RESET_CONFIG_HI 8'hfd +//`define MLVDS_RESET_CONFIG_LO 8'hfe +// `define mLVDS_reset_range_enable 31 // Bit 0 +// `define mLVDS_reset_range_inv 30 // Bit 0 +// `define mLVDS_reset_config_res1 29 // Bit 0 +// `define mLVDS_reset_range_line_0 16 // Bit 11:0 +// `define mLVDS_reset_config_res3 13 // Bit 2:0 +// `define mLVDS_reset_range_line_1 0 // Bit 11:0 +//=============================================================== +//LCD DRIVER BASE END +//=============================================================== +// +// Closing file: lcd_regs.h +// +// +// Reading file: vpu_mad_regs.h +// +//DEINTERLACE module start from 8'h90 end to 8'hff +// ----------------------------------------------- +// REG_BASE: MAD_VCBUS_BASE = 0x17 +// ----------------------------------------------- +#define DI_PRE_CTRL ((0x1700 << 2) + 0xff000000) +// bit 31, cbus_pre_frame_rst +// bit 30, cbus_pre_soft_rst +// bit 29, pre_field_num +// bit 27:26, mode_444c422 +// bit 25, di_cont_read_en +// bit 24:23, mode_422c444 +// bit 22, mtn_after_nr +// bit 21:16, pre_hold_fifo_lines +// bit 15, nr_wr_by +// bit 14, use_vdin_go_line +// bit 13, di_prevdin_en +// bit 12, di_pre_viu_link +// bit 11, di_pre_repeat +// bit 10, di_pre_drop_1st +// bit 9, di_buf2_en +// bit 8, di_chan2_en +// bit 7, prenr_hist_en +// bit 6, chan2_hist_en +// bit 5, hist_check_en +// bit 4, check_after_nr +// bit 3, check222p_en +// bit 2, check322p_en +// bit 1, mtn_en +// bit 0, nr_en +#define DI_POST_CTRL ((0x1701 << 2) + 0xff000000) +// bit 31, cbus_post_frame_rst +// bit 30, cbus_post_soft_rst +// bit 29, post_field_num +// bit 21:16, post_hold_fifo_lines +// bit 13, prepost_link +// bit 12, di_post_viu_link +// bit 11, di_post_repeat +// bit 10, di_post_drop_1st +// bit 9, mif0_to_vpp_en +// bit 8, di_vpp_out_en +// bit 7, di_wr_bk_en +// bit 6, di_mux_en +// bit 5, di_blend_en +// bit 4, di_mtnp_read_en +// bit 3, di_mtn_buf_en +// bit 2, di_ei_en +// bit 1, di_buf1_en +// bit 0, di_buf0_en +#define DI_POST_SIZE ((0x1702 << 2) + 0xff000000) +//bit 31:29, diwr_field_mode field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode +//bit 28:16, vsize1post +//bit 12:0, hsize1post +#define DI_PRE_SIZE ((0x1703 << 2) + 0xff000000) +//bit 31:29, nrwr_field_mode field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode +//bit 28:16, vsize1pre +//bit 12:0, hsize1pre +#define DI_EI_CTRL0 ((0x1704 << 2) + 0xff000000) +//bit 23:16, ei0_filter[2:+] abs_diff_left>filter && ...right>filter && ...top>filter && ...bot>filter -> filter +//bit 15:8, ei0_threshold[2:+] +//bit 3, ei0_vertical +//bit 2, ei0_bpscf2 +//bit 1, ei0_bpsfar1 +#define DI_EI_CTRL1 ((0x1705 << 2) + 0xff000000) +//bit 31:24, ei0_diff +//bit 23:16, ei0_angle45 +//bit 15:8, ei0_peak +//bit 7:0, ei0_cross +#define DI_EI_CTRL2 ((0x1706 << 2) + 0xff000000) +//bit 31:24, ei0_close2 +//bit 23:16, ei0_close1 +//bit 15:8, ei0_far2 +//bit 7:0, ei0_far1 +//`define DI_NR_CTRL0 8'h07 +//bit 26, nr_cue_en +//bit 25, nr2_en +#define DI_NR_CTRL1 ((0x1708 << 2) + 0xff000000) +//bit 31:30, mot_p1txtcore_mode +//bit 29:24, mot_p1txtcore_clmt +//bit 21:16, mot_p1txtcore_ylmt +//bit 15:8, mot_p1txtcore_crate +//bit 7:0, mot_p1txtcore_yrate +#define DI_NR_CTRL2 ((0x1709 << 2) + 0xff000000) +//bit 29:24, mot_curtxtcore_clmt +//bit 21:16, mot_curtxtcore_ylmt +//bit 15:8, mot_curtxtcore_crate +//bit 7:0, mot_curtxtcore_yrate +//`define DI_NR_CTRL3 8'h0a +//no use +//`define DI_MTN_CTRL 8'h0b +//`define DI_CANVAS_URGENT0 8'h0a +//`define DI_CANVAS_URGENT1 8'h0b +#define DI_MTN_CTRL1 ((0x170c << 2) + 0xff000000) +//bit 11:8, mtn_paramtnthd +//bit 7:0, mtn_parafltthd +#define DI_BLEND_CTRL ((0x170d << 2) + 0xff000000) +//bit 31, blend_1_en +//bit 30, blend_mtn_lpf +//bit 28, post_mb_en +//bit 27, blend_mtn3p_max +//bit 26, blend_mtn3p_min +//bit 25, blend_mtn3p_ave +//bit 24, blend_mtn3p_maxtb +//bit 23, blend_mtn_flt_en +//bit 22, blend_data_flt_en +//bit 21:20, blend_top_mode +//bit 19, blend_reg3_enable +//bit 18, blend_reg2_enable +//bit 17, blend_reg1_enable +//bit 16, blend_reg0_enable +//bit 15:14, blend_reg3_mode +//bit 13:12, blend_reg2_mode +//bit 11:10, blend_reg1_mode +//bit 9:8, blend_reg0_mode +//bit 7:0, kdeint +//`define DI_BLEND_CTRL1 8'h0e +//no use +//`define DI_CANVAS_URGENT2 8'h0e +//`define DI_BLEND_CTRL2 8'h0f +//no use +#define DI_ARB_CTRL ((0x170f << 2) + 0xff000000) +//bit 31:26, di_arb_thd1 +//bit 25:20, di_arb_thd0 +//bit 19, di_arb_tid_mode +//bit 18, di_arb_arb_mode +//bit 17, di_arb_acq_en +//bit 16, di_arb_disable_clk +//bit 15:0, di_arb_req_en +#define DI_BLEND_REG0_X ((0x1710 << 2) + 0xff000000) +//bit 27:16, blend_reg0_startx +//bit 11:0, blend_reg0_endx +#define DI_BLEND_REG0_Y ((0x1711 << 2) + 0xff000000) +#define DI_BLEND_REG1_X ((0x1712 << 2) + 0xff000000) +#define DI_BLEND_REG1_Y ((0x1713 << 2) + 0xff000000) +#define DI_BLEND_REG2_X ((0x1714 << 2) + 0xff000000) +#define DI_BLEND_REG2_Y ((0x1715 << 2) + 0xff000000) +#define DI_BLEND_REG3_X ((0x1716 << 2) + 0xff000000) +#define DI_BLEND_REG3_Y ((0x1717 << 2) + 0xff000000) +#define DI_CLKG_CTRL ((0x1718 << 2) + 0xff000000) +//bit 31:24, pre_gclk_ctrl no clk gate control. if ==1, module clk is not gated (always on). [3] for pulldown,[2] for mtn_1,[1] for mtn_0,[0] for nr +//bit 23:16, post_gclk_ctrl no clk gate control. [4] for ei_1, [3] for ei_0,[2] for ei_top, [1] for blend_1, [0] for blend_0 +//bit 1, di_gate_all clk shut down. if ==1 , all di clock shut down +//bit 0, di_no_clk_gate no clk gate control. if di_gated_all==0 and di_no_clk_gate ==1, all di clock is always working. +#define DI_EI_CTRL3 ((0x1719 << 2) + 0xff000000) +//bit 31, reg_ei_1 +//bit 30, reg_demon_en +//bit 26:24, reg_demon_mux +//bit 23:20, reg_right_win +//bit 19:16, reg_left_win +//bit 7:4, reg_ei_sadm_quatize_margin +//bit 1:0, reg_ei_sad_relative_mode +#define DI_EI_CTRL4 ((0x171a << 2) + 0xff000000) +//bit 29, reg_ei_caldrt_ambliike2_biasvertical +//bit 28:24, reg_ei_caldrt_addxla2list_drtmax +//bit 22:20, reg_ei_caldrt_addxla2list_signm0th +//bit 19, reg_ei_caldrt_addxla2list_mode +//bit 18:16, reg_ei_signm_sad_cor_rate +//bit 15:12, reg_ei_signm_sadi_cor_rate +//bit 11:6, reg_ei_signm_sadi_cor_ofst +//bit 5:0, reg_ei_signm_sad_ofst +#define DI_EI_CTRL5 ((0x171b << 2) + 0xff000000) +//bit 30:28, reg_ei_caldrt_cnflcctchk_frcverthrd +//bit 26:24, reg_ei_caldrt_cnflctchk_mg +//bit 23:22, reg_ei_caldrt_cnflctchk_ws +//bit 21, reg_ei_caldrt_cnflctchk_en +//bit 20, reg_ei_caldrt_verfrc_final_en +//bit 19, reg_ei_caldrt_verfrc_retimflt_en +//bit 18:16, reg_ei_caldrt_verftc_eithratemth +//bit 15, reg_ei_caldrt_verfrc_retiming_en +//bit 14:12, reg_ei_caldrt_verfrc_bothratemth +//bit 11:9, reg_ei_caldrt_ver_thrd +//bit 8:4, reg_ei_caldrt_addxla2list_drtmin +//bit 3:0, reg_ei_caldrt_addxla2list_drtlimit +#define DI_EI_CTRL6 ((0x171c << 2) + 0xff000000) +//bit 31:24, reg_ei_caldrt_abext_sad12thhig +//bit 23:16, reg_ei_caldrt_abext_sad00thlow +//bit 15:8, reg_ei_caldrt_abext_sad12thlow +//bit 6:4, reg_ei_caldrt_abext_ratemth +//bit 2:0, reg_ei_caldrt_abext_drtthrd +#define DI_EI_CTRL7 ((0x171d << 2) + 0xff000000) +//bit 29, reg_ei_caldrt_xlanopeak_codien +//bit 28:24, reg_ei_caldrt_xlanopeak_drtmax +//bit 23, reg_ei_caldrt_xlanopeak_en +//bit 28:24, reg_ei_caldrt_abext_monotrnd_alpha +//bit 28:24, reg_ei_caldrt_abext_mononum12_thrd +//bit 28:24, reg_ei_caldrt_abext_mononum00_thrd +//bit 28:24, reg_ei_caldrt_abext_sad00rate +//bit 28:24, reg_ei_caldrt_abext_sad12rate +//bit 28:24, reg_ei_caldrt_abext_sad00thhig +#define DI_EI_CTRL8 ((0x171e << 2) + 0xff000000) +//bit 30:28, reg_ei_assign_headtail_magin +//bit 26:24, reg_ei_retime_lastcurpncnfltchk_mode +//bit 22:21, reg_ei_retime_lastcurpncnfltchk_drtth +//bit 20, reg_ei_caldrt_histchk_cnfid +//bit 19:16, reg_ei_caldrt_histchk_thrd +//bit 15, reg_ei_caldrt_histchk_abext +//bit 14, reg_ei_caldrt_histchk_npen +//bit 13:11, reg_ei_caldrt_amblike2_drtmg +//bit 10:8, reg_ei_caldrt_amblike2_valmg +//bit 7:4, reg_ei_caldrt_amblike2_alpha +//bit 3:0, reg_ei_caldrt_amblike2_drtth +#define DI_EI_CTRL9 ((0x171f << 2) + 0xff000000) +//bit 31:28, reg_ei_caldrt_hcnfcheck_frcvert_xla_th3 +//bit 27, reg_ei_caldrt_hcnfcheck_frcvert_xla_en +//bit 26:24, reg_ei_caldrt_conf_drtth +//bit 23:20, reg_ei_caldrt_conf_absdrtth +//bit 19:18, reg_ei_caldrt_abcheck_mode1 +//bit 17:16, reg_ei_caldrt_abcheck_mode0 +//bit 15:12, reg_ei_caldrt_abcheck_drth1 +//bit 11:8, reg_ei_caldrt_abcheck_drth0 +//bit 6:4, reg_ei_caldrt_abpnchk1_th +//bit 1, reg_ei_caldrt_abpnchk1_en +//bit 0, reg_ei_caldrt_abpnchk0_en +// DEINTERLACE mode check. +#define DI_MC_REG0_X ((0x1720 << 2) + 0xff000000) +//bit 27:16, mc_reg0_start_x +//bit 11:0, mc_reg0_end_x +#define DI_MC_REG0_Y ((0x1721 << 2) + 0xff000000) +#define DI_MC_REG1_X ((0x1722 << 2) + 0xff000000) +#define DI_MC_REG1_Y ((0x1723 << 2) + 0xff000000) +#define DI_MC_REG2_X ((0x1724 << 2) + 0xff000000) +#define DI_MC_REG2_Y ((0x1725 << 2) + 0xff000000) +#define DI_MC_REG3_X ((0x1726 << 2) + 0xff000000) +#define DI_MC_REG3_Y ((0x1727 << 2) + 0xff000000) +#define DI_MC_REG4_X ((0x1728 << 2) + 0xff000000) +#define DI_MC_REG4_Y ((0x1729 << 2) + 0xff000000) +#define DI_MC_32LVL0 ((0x172a << 2) + 0xff000000) +//bit 31:24, mc_reg2_32lvl +//bit 23:16, mc_reg1_32lvl +//bit 15:8, mc_reg0_32lvl +//bit 7:0, field_32lvl +#define DI_MC_32LVL1 ((0x172b << 2) + 0xff000000) +//bit 15:8, mc_reg3_32lvl +//bit 7:0, mc_reg4_32lvl +#define DI_MC_22LVL0 ((0x172c << 2) + 0xff000000) +//bit 31:16, mc_reg0_22lvl +//bit 15:0, field_22lvl +#define DI_MC_22LVL1 ((0x172d << 2) + 0xff000000) +//bit 31:16, mc_reg2_22lvl +//bit 15:0, mc_reg1_22lvl +#define DI_MC_22LVL2 ((0x172e << 2) + 0xff000000) +//bit 31:16, mc_reg4_22lvl +//bit 15:0, mc_reg3_22lvl +#define DI_MC_CTRL ((0x172f << 2) + 0xff000000) +//bit 4, mc_reg4_en +//bit 3, mc_reg3_en +//bit 2, mc_reg2_en +//bit 1, mc_reg1_en +//bit 0, mc_reg0_en +#define DI_INTR_CTRL ((0x1730 << 2) + 0xff000000) +#define DI_INFO_ADDR ((0x1731 << 2) + 0xff000000) +#define DI_INFO_DATA ((0x1732 << 2) + 0xff000000) +#define DI_PRE_HOLD ((0x1733 << 2) + 0xff000000) +//// DET 3D REG DEFINE BEGIN //// +//// 8'h34~8'h3f +// `define DET3D_MOTN_CFG 8'h34 +// //Bit 16, reg_det3d_intr_en Det3d interrupt enable +// //Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma: +// // 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2) +// //Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32 +// //Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection. +// +// `define DET3D_CB_CFG 8'h35 +// //Bit 7:4, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection. +// //Bit 3:0, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection. +// +// `define DET3D_SPLT_CFG 8'h36 +// //Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection. +// // The smaller of this value, the easier of the split line detected. +// //Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation. +// // The smaller of this value, the more samples will be added to the estimation. +// +// `define DET3D_HV_MUTE 8'h37 +// //Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part. +// //Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part. +// //Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part +// //Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part +// //Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block. +// //Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block. +// +// `define DET3D_MAT_STA_P1M1 8'h38 +// //Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8) +// //Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5) +// //Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1) +// //Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8) +// +// `define DET3D_MAT_STA_P1TH 8'h39 +// //Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100) +// //Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80) +// //Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48) +// +// `define DET3D_MAT_STA_M1TH 8'h3a +// //Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100) +// //Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80) +// //Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64) +// +// `define DET3D_MAT_STA_RSFT 8'h3b +// //Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: +// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions +// //Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: +// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions +// //Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: +// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions +// +// `define DET3D_MAT_SYMTC_TH 8'h3c +// //Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric. +// //Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric. +// //Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric. +// //Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric. +// +// `define DET3D_RO_DET_CB_HOR 8'h3d +// //Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern. +// //Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern. +// +// `define DET3D_RO_DET_CB_VER 8'h3e +// //Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern. +// //Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern. +// +// `define DET3D_RO_SPLT_HT 8'h3f +// //Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture +// //Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture +// //Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture +// +// //// DET 3D REG DEFINE END //// +#define DI_MTN_1_CTRL1 ((0x1740 << 2) + 0xff000000) +//bit 31, mtn_1_en +//bit 30, mtn_init +//bit 29, di2nr_txt_en +//bit 28, reserved +//bit 27:24, mtn_def +//bit 23:16, mtn_adp_yc +//bit 15:8, mtn_adp_2c +//bit 7:0, mtn_adp_2y +#define DI_MTN_1_CTRL2 ((0x1741 << 2) + 0xff000000) +//bit 31:24, mtn_ykinter +//bit 23:16, mtn_ckinter +//bit 15:8, mtn_ykintra +//bit 7:0, mtn_ckintra +#define DI_MTN_1_CTRL3 ((0x1742 << 2) + 0xff000000) +//bit 31:24, mtn_tyrate +//bit 23:16, mtn_tcrate +//bit 15: 8, mtn_mxcmby +//bit 7: 0, mtn_mxcmbc +#define DI_MTN_1_CTRL4 ((0x1743 << 2) + 0xff000000) +//bit 31:24, mtn_tcorey +//bit 23:16, mtn_tcorec +//bit 15: 8, mtn_minth +//bit 7: 0, mtn_maxth +#define DI_MTN_1_CTRL5 ((0x1744 << 2) + 0xff000000) +//bit 31:28, mtn_m1b_extnd +//bit 27:24, mtn_m1b_errod +//bit 21:20, mtn_mot_txt_mode +//bit 19:18, mtn_replace_cbyy +//bit 17:16, mtn_replace_ybyc +//bit 15: 8, mtn_core_ykinter +//bit 7: 0, mtn_core_ckinter +//// NR2 REG DEFINE BEGIN//// +#define NR2_MET_NM_CTRL ((0x1745 << 2) + 0xff000000) +//Bit 28, reg_NM_reset Reset to the status of the Loop filter. +//Bit 27:24, reg_NM_calc_length Length mode of the Noise measurement sample number for statistics. +// 0: 256 samples; 1: 512 samples; 2: 1024 samples; ¡X: 2^(8+x) samples +//Bit 23:20, reg_NM_inc_step Loop filter input gain increase step. +//Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step. +//Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion for condition of pixels included in Luma Noise measurement. +//Bit 7:0, reg_NM_CHPmot_thrd Chroma channel HP portion motion for condition of pixels included in Chroma Noise measurement. +#define NR2_MET_NM_YCTRL ((0x1746 << 2) + 0xff000000) +//Bit 31:28, reg_NM_YPLL_target Target rate of NM_Ynoise_thrd to mean of the Luma Noise +//Bit 27:24, reg_NM_YLPmot_thrd Luma channel LP portion motion for condition of pixels included in Luma Noise measurement. +//Bit 23:16, reg_NM_YHPmot_thrd_min Minimum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement. +//Bit 15:8, reg_NM_YHPmot_thrd_max Maximum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement. +//Bit 7:0, reg_NM_Ylock_rate Rate to decide whether the Luma noise measurement is lock or not. +#define NR2_MET_NM_CCTRL ((0x1747 << 2) + 0xff000000) +//Bit 31:28, reg_NM_CPLL_target Target rate of NM_Cnoise_thrd to mean of the Chroma Noise +//Bit 27:24, reg_NM_CLPmot_thrd Chroma channel LP portion motion for condition of pixels included in Chroma Noise measurement. +//Bit 23:16, reg_NM_CHPmot_thrd_min Minimum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement. +//Bit 15:8, reg_NM_CHPmot_thrd_max Maximum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement. +//Bit 7:0, reg_NM_Clock_rate Rate to decide whether the Chroma noise measurement is lock or not; +#define NR2_MET_NM_TNR ((0x1748 << 2) + 0xff000000) +//Bit 25, ro_NM_TNR_Ylock Read-only register to tell ifLuma channel noise measurement is locked or not. +//Bit 24, ro_NM_TNR_Clock Read-only register to tell if Chroma channel noise measurement is locked or not. +//Bit 23:12, ro_NM_TNR_Ylevel Read-only register to give Luma channel noise level. It was 16x of pixel difference in 8 bits of YHPmot. +//Bit 11:0, ro_NM_TNR_Clevel Read-only register to give Chroma channel noise level. It was 16x of pixel difference in 8 bits of CHPmot. +#define NR2_MET_NMFRM_TNR_YLEV ((0x1749 << 2) + 0xff000000) +//Bit 28:0, ro_NMFrm_TNR_Ylevel Frame based Read-only register to give Luma channel noise level within one frame/field. +#define NR2_MET_NMFRM_TNR_YCNT ((0x174a << 2) + 0xff000000) +//Bit 23:0, ro_NMFrm_TNR_Ycount Number ofLuma channel pixels included in Frame/Field based noise level measurement. +#define NR2_MET_NMFRM_TNR_CLEV ((0x174b << 2) + 0xff000000) +//Bit 28:0, ro_NMFrm_TNR_Clevel Frame based Read-only register to give Chroma channel noise level within one frame/field. +#define NR2_MET_NMFRM_TNR_CCNT ((0x174c << 2) + 0xff000000) +//Bit 23:0, ro_NMFrm_TNR_Ccount Number of Chroma channel pixels included in Frame/Field based noise level measurement. +#define NR2_3DEN_MODE ((0x174d << 2) + 0xff000000) +//Bit 6:4, Blend_3dnr_en_r +//Bit 2:0, Blend_3dnr_en_l +// `define NR2_IIR_CTRL 8'h4e +// //Bit 15:14, reg_LP_IIR_8bit_mode LP IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory; +// // 2: 8bits will be store in memory;3: 7bits will be store in memory; +// //Bit 13:12, reg_LP_IIR_mute_mode Mode for the LP IIR mute, +// //Bit 11:8, reg_LP_IIR_mute_thrd Threshold of LP IIR mute to avoid ghost: +// //Bit 7:6, reg_HP_IIR_8bit_mode IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory; +// // 2: 8bits will be store in memory;3: 7bits will be store in memory; +// //Bit 5:4, reg_HP_IIR_mute_mode Mode for theLP IIR mute +// //Bit 3:0, reg_HP_IIR_mute_thrd Threshold of HP IIR mute to avoid ghost +// // +#define NR2_SW_EN ((0x174f << 2) + 0xff000000) +//Bit 17:8, Clk_gate_ctrl +//Bit 7, Cfr_enable +//Bit 5, Det3d_en +//Bit 4, Nr2_proc_en +//Bit 0, Nr2_sw_en +#define NR2_FRM_SIZE ((0x1750 << 2) + 0xff000000) +//Bit 27:16, Frm_heigh Frame/field height +//Bit 11: 0, Frm_width Frame/field width +// `define NR2_SNR_SAD_CFG 8'h51 +// //Bit 12, reg_MATNR_SNR_SAD_CenRPL U1, Enable signal for Current pixel position SAD to be replaced by SAD_min.0: do not replace Current pixel position SAD by SAD_min;1: do replacements +// //Bit 11:8, reg_MATNR_SNR_SAD_coring Coring value of the intra-frame SAD. sum = (sum - reg_MATNR_SNR_SAD_coring);sum = (sum<0) ? 0: (sum>255)? 255: sum; +// //Bit 6:5, reg_MATNR_SNR_SAD_WinMod Unsigned, Intra-frame SAD matching window mode:0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1]; +// //Bit 4:0, Sad_coef_num Sad coeffient +// +// `define NR2_MATNR_SNR_OS 8'h52 +// //Bit 7:4, reg_MATNR_SNR_COS SNR Filter overshoot control margin for UV channel (X2 to u10 scale) +// //Bit 3:0, reg_MATNR_SNR_YOS SNR Filter overshoot control margin for luma channel (X2 to u10 scale) +// +// `define NR2_MATNR_SNR_NRM_CFG 8'h53 +// //Bit 23:16, reg_MATNR_SNR_NRM_ofst Edge based SNR boosting normalization offset to SAD_max ; +// //Bit 15:8, reg_MATNR_SNR_NRM_max Edge based SNR boosting normalization Max value +// //Bit 7:0, reg_MATNR_SNR_NRM_min Edge based SNR boosting normalization Min value +// +// `define NR2_MATNR_SNR_NRM_GAIN 8'h54 +// //Bit 15:8, reg_MATNR_SNR_NRM_Cgain Edge based SNR boosting normalization Gain for Chrm channel (norm 32 as 1) +// //Bit 7:0, reg_MATNR_SNR_NRM_Ygain Edge based SNR boosting normalization Gain for Luma channel (norm 32 as 1) +// +// `define NR2_MATNR_SNR_LPF_CFG 8'h55 +// //Bit 23:16,reg_MATNR_SNRLPF_SADmaxTH U8, Threshold to SADmax to use TNRLPF to replace SNRLPF. i.e.if (SAD_max<reg_MATNR_SNRLPF_SADmaxTH) SNRLPF_yuv[k] = TNRLPF_yuv[k]; +// //Bit 13:11,reg_MATNR_SNRLPF_Cmode LPF based SNR filtering mode on CHRM channel: +// // 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 4 4 3]/16; +// // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[] +// //Bit 10:8, reg_MATNR_SNRLPF_Ymode LPF based SNR filtering mode on LUMA channel: +// // 0: gradient LPF //Bit [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8;3: gradient LPF [5 4 4 3]/16; +// // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[] +// //Bit 7:4, reg_MATNR_SNRLPF_SADmin3TH Offset threshold to SAD_min to Discard SAD_min3 corresponding pixel in LPF SNR filtering. (X8 to u8 scale) +// //Bit 3:0, reg_MATNR_SNRLPF_SADmin2TH Offset threshold to SAD_min to Discard SAD_min2 corresponding pixel in LPF SNR filtering. (X8 to u8 scale) +// +// `define NR2_MATNR_SNR_USF_GAIN 8'h56 +// //Bit 15:8, reg_MATNR_SNR_USF_Cgain Un-sharp (HP) compensate back Chrm portion gain, (norm 64 as 1) +// //Bit 7:0, reg_MATNR_SNR_USF_Ygain Un-sharp (HP) compensate back Luma portion gain, (norm 64 as 1) +// +// `define NR2_MATNR_SNR_EDGE2B 8'h57 +// //Bit 15:8, reg_MATNR_SNR_Edge2Beta_ofst U8, Offset for Beta based on Edge. +// //Bit 7:0, reg_MATNR_SNR_Edge2Beta_gain U8. Gain to SAD_min for Beta based on Edge. (norm 16 as 1) +// +// `define NR2_MATNR_BETA_EGAIN 8'h58 +// //Bit 15:8, reg_MATNR_CBeta_Egain U8, Gain to Edge based Beta for Chrm channel. (normalized to 32 as 1) +// //Bit 7:0, reg_MATNR_YBeta_Egain U8, Gain to Edge based Beta for Luma channel. (normalized to 32 as 1) +// +// `define NR2_MATNR_BETA_BRT 8'h59 +// //Bit 31:28, reg_MATNR_beta_BRT_limt_hi U4, Beta adjustment based on Brightness high side Limit. (X16 to u8 scale) +// //Bit 27:24, reg_MATNR_beta_BRT_slop_hi U4, Beta adjustment based on Brightness high side slope. Normalized to 16 as 1 +// //Bit 23:16, reg_MATNR_beta_BRT_thrd_hi U8, Beta adjustment based on Brightness high threshold.(u8 scale) +// //Bit 15:12, reg_MATNR_beta_BRT_limt_lo U4, Beta adjustment based on Brightness low side Limit. (X16 to u8 scale) +// //Bit 11:8, reg_MATNR_beta_BRT_slop_lo U4, Beta adjustment based on Brightness low side slope. Normalized to 16 as 1 +// //Bit 7:0, reg_MATNR_beta_BRT_thrd_lo U8, Beta adjustment based on Brightness low threshold.(u8 scale) +// `define NR2_MATNR_XBETA_CFG 8'h5a +// //Bit 19:18, reg_MATNR_CBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Chrm channel; +// //Bit 17:16, reg_MATNR_YBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Luma channel; +// //Bit 15: 8, reg_MATNR_CBeta_Ofst U8, Offset to Beta for Chrm channel.(after beta_edge and beta_motion mux) +// //Bit 7: 0, reg_MATNR_YBeta_Ofst U8, Offset to Beta for Luma channel.(after beta_edge and beta_motion mux) +// `define NR2_MATNR_YBETA_SCL 8'h5b +// //Bit 31:24, reg_MATNR_YBeta_scale_min U8, Final step Beta scale low limit for Luma channel; +// //Bit 23:16, reg_MATNR_YBeta_scale_max U8, Final step Beta scale high limit for Luma channe; +// //Bit 15: 8, reg_MATNR_YBeta_scale_gain U8, Final step Beta scale Gain for Luma channel (normalized 32 to 1); +// //Bit 7 : 0, reg_MATNR_YBeta_scale_ofst S8, Final step Beta scale offset for Luma channel ; +// `define NR2_MATNR_CBETA_SCL 8'h5c +// //Bit 31:24, reg_MATNR_CBeta_scale_min Final step Beta scale low limit for Chrm channel.Similar to Y +// //Bit 23:16, reg_MATNR_CBeta_scale_max U8, Final step Beta scale high limit for Chrm channel.Similar to Y +// //Bit 15: 8, reg_MATNR_CBeta_scale_gain U8, Final step Beta scale Gain for Chrm channel Similar to Y +// //Bit 7: 0, reg_MATNR_CBeta_scale_ofst S8, Final step Beta scale offset for Chrm channel Similar to Y +// `define NR2_SNR_MASK 8'h5d +// //Bit 20:0, SAD_MSK Valid signal in the 3x7 SAD surface +// `define NR2_SAD2NORM_LUT0 8'h5e +// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_3 SAD convert normal LUT node 3 +// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_2 SAD convert normal LUT node 2 +// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_1 SAD convert normal LUT node 1 +// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_0 SAD convert normal LUT node 0 +// `define NR2_SAD2NORM_LUT1 8'h5f +// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_7 SAD convert normal LUT node 7 +// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_6 SAD convert normal LUT node 6 +// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_5 SAD convert normal LUT node 5 +// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_4 SAD convert normal LUT node 4 +// `define NR2_SAD2NORM_LUT2 8'h60 +// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_11 SAD convert normal LUT node 11 +// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_10 SAD convert normal LUT node 10 +// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_9 SAD convert normal LUT node 9 +// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_8 SAD convert normal LUT node 8 +// `define NR2_SAD2NORM_LUT3 8'h61 +// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_15 SAD convert normal LUT node 15 +// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_14 SAD convert normal LUT node 14 +// //Bit 15:8, reg_MATNR_SAD2Norm_LUT_13 SAD convert normal LUT node 13 +// //Bit 7:0, reg_MATNR_SAD2Norm_LUT_12 SAD convert normal LUT node 12 +// `define NR2_EDGE2BETA_LUT0 8'h62 +// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_3 Edge convert beta LUT node 3 +// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_2 Edge convert beta LUT node 2 +// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_1 Edge convert beta LUT node 1 +// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_0 Edge convert beta LUT node 0 +// `define NR2_EDGE2BETA_LUT1 8'h63 +// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_7 Edge convert beta LUT node 7 +// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_6 Edge convert beta LUT node 6 +// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_5 Edge convert beta LUT node 5 +// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_4 Edge convert beta LUT node 4 +// `define NR2_EDGE2BETA_LUT2 8'h64 +// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_11 Edge convert beta LUT node 11 +// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_10 Edge convert beta LUT node 10 +// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_9 Edge convert beta LUT node 9 +// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_8 Edge convert beta LUT node 8 +// `define NR2_EDGE2BETA_LUT3 8'h65 +// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_15 Edge convert beta LUT node 15 +// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_14 Edge convert beta LUT node 14 +// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_13 Edge convert beta LUT node 13 +// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_12 Edge convert beta LUT node 12 +// `define NR2_MOTION2BETA_LUT0 8'h66 +// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_3 Motion convert beta LUT node 3 +// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_2 Motion convert beta LUT node 2 +// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_1 Motion convert beta LUT node 1 +// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_0 Motion convert beta LUT node 0 +// `define NR2_MOTION2BETA_LUT1 8'h67 +// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_7 Motion convert beta LUT node 7 +// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_6 Motion convert beta LUT node 6 +// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_5 Motion convert beta LUT node 5 +// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_4 Motion convert beta LUT node 4 +// `define NR2_MOTION2BETA_LUT2 8'h68 +// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_11 Motion convert beta LUT node 11 +// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_10 Motion convert beta LUT node 10 +// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_9 Motion convert beta LUT node 9 +// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_8 Motion convert beta LUT node 8 +// `define NR2_MOTION2BETA_LUT3 8'h69 +// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_15 Motion convert beta LUT node 15 +// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_14 Motion convert beta LUT node 14 +// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_13 Motion convert beta LUT node 13 +// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_12 Motion convert beta LUT node 12 +// `define NR2_MATNR_MTN_CRTL 8'h6a +// //Bit 25:24, reg_MATNR_Vmtn_use_mode Motion_yuvV channel motion selection mode:0: Vmot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot) +// //Bit 21:20, reg_MATNR_Umtn_use_mode Motion_yuvU channel motion selection mode:0:Umot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot) +// //Bit 17:16, reg_MATNR_Ymtn_use_mode Motion_yuvLuma channel motion selection mode:0: Ymot, 1: Ymot/2 + (Umot+Vmot)/4; 2: Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot) +// //Bit 13:12, reg_MATNR_mtn_txt_mode Texture detection mode for adaptive coring of HP motion +// //Bit 9: 8, reg_MATNR_mtn_cor_mode Coring selection mode based on texture detection; +// //Bit 6: 4, reg_MATNR_mtn_hpf_mode video mode of current and previous frame/field for MotHPF_yuv[k] calculation: +// //Bit 2: 0, reg_MATNR_mtn_lpf_mode LPF video mode of current and previous frame/field for MotLPF_yuv[k] calculation: +// `define NR2_MATNR_MTN_CRTL2 8'h6b +// //Bit 18:16, reg_MATNR_iir_BS_Ymode IIR TNR filter Band split filter mode for Luma LPF result generation (Cur and Prev); +// //Bit 15: 8, reg_MATNR_mtnb_alpLP_Cgain Scale of motion_brthp_uv to motion_brtlp_uv, normalized to 32 as 1 +// //Bit 7: 0, reg_MATNR_mtnb_alpLP_Ygain Scale of motion_brthp_y to motion_brtlp_y, normalized to 32 as 1 +// `define NR2_MATNR_MTN_COR 8'h6c +// //Bit 15:12, reg_MATNR_mtn_cor_Cofst Coring Offset for Chroma Motion. +// //Bit 11: 8, reg_MATNR_mtn_cor_Cgain Gain to texture based coring for Chroma Motion. Normalized to 16 as 1 +// //Bit 7: 4, reg_MATNR_mtn_cor_Yofst Coring Offset for Luma Motion. +// //Bit 3: 0, reg_MATNR_mtn_cor_Ygain Gain to texture based coring for Luma Motion. Normalized to 16 as 1 +// `define NR2_MATNR_MTN_GAIN 8'h6d +// //Bit 31:24, reg_MATNR_mtn_hp_Cgain Gain to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1 +// //Bit 23:16, reg_MATNR_mtn_hp_Ygain Gain to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1 +// //Bit 15: 8, reg_MATNR_mtn_lp_Cgain Gain to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1 +// //Bit 7: 0, reg_MATNR_mtn_lp_Ygain Gain to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1 +// `define NR2_MATNR_DEGHOST 8'h6e +// //Bit 8, reg_MATNR_DeGhost_En Enable signal for DeGhost function:0: disable; 1: enable +// //Bit 7:4, reg_MATNR_DeGhost_COS DeGhost Overshoot margin for UV channel, (X2 to u10 scale) +// //Bit 3:0, reg_MATNR_DeGhost_YOS DeGhost Overshoot margin for Luma channel, (X2 to u10 scale) +// +// `define NR2_MATNR_ALPHALP_LUT0 8'h6f +// //Bit 31:24, reg_MATNR_AlphaLP_LUT_3 Matnr low-pass filter alpha LUT node 3 +// //Bit 23:16, reg_MATNR_AlphaLP_LUT_2 Matnr low-pass filter alpha LUT node 2 +// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_1 Matnr low-pass filter alpha LUT node 1 +// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_0 Matnr low-pass filter alpha LUT node 0 +// `define NR2_MATNR_ALPHALP_LUT1 8'h70 +// //Bit 31:24, reg_MATNR_AlphaLP_LUT_7 Matnr low-pass filter alpha LUT node 7 +// //Bit 23:16, reg_MATNR_AlphaLP_LUT_6 Matnr low-pass filter alpha LUT node 6 +// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_5 Matnr low-pass filter alpha LUT node 5 +// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_4 Matnr low-pass filter alpha LUT node 4 +// `define NR2_MATNR_ALPHALP_LUT2 8'h71 +// //Bit 31:24, reg_MATNR_AlphaLP_LUT_11 Matnr low-pass filter alpha LUT node 11 +// //Bit 23:16, reg_MATNR_AlphaLP_LUT_10 Matnr low-pass filter alpha LUT node 10 +// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_9 Matnr low-pass filter alpha LUT node 9 +// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_8 Matnr low-pass filter alpha LUT node 8 +// `define NR2_MATNR_ALPHALP_LUT3 8'h72 +// //Bit 31:24, reg_MATNR_AlphaLP_LUT_15 Matnr low-pass filter alpha LUT node 15 +// //Bit 23:16, reg_MATNR_AlphaLP_LUT_14 Matnr low-pass filter alpha LUT node 14 +// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_13 Matnr low-pass filter alpha LUT node 13 +// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_12 Matnr low-pass filter alpha LUT node 12 +// `define NR2_MATNR_ALPHAHP_LUT0 8'h73 +// //Bit 31:24, reg_MATNR_AlphaHP_LUT_3 Matnr high-pass filter alpha LUT node 3 +// //Bit 23:16, reg_MATNR_AlphaHP_LUT_2 Matnr high-pass filter alpha LUT node 2 +// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_1 Matnr high-pass filter alpha LUT node 1 +// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_0 Matnr high-pass filter alpha LUT node 0 +// `define NR2_MATNR_ALPHAHP_LUT1 8'h74 +// //Bit 31:24, reg_MATNR_AlphaHP_LUT_7 Matnr high-pass filter alpha LUT node 7 +// //Bit 23:16, reg_MATNR_AlphaHP_LUT_6 Matnr high-pass filter alpha LUT node 6 +// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_5 Matnr high-pass filter alpha LUT node 5 +// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_4 Matnr high-pass filter alpha LUT node 4 +// `define NR2_MATNR_ALPHAHP_LUT2 8'h75 +// //Bit 31:24, reg_MATNR_AlphaHP_LUT_11 Matnr high-pass filter alpha LUT node 11 +// //Bit 23:16, reg_MATNR_AlphaHP_LUT_10 Matnr high-pass filter alpha LUT node 10 +// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_9 Matnr high-pass filter alpha LUT node 9 +// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_8 Matnr high-pass filter alpha LUT node 8 +// `define NR2_MATNR_ALPHAHP_LUT3 8'h76 +// //Bit 31:24, reg_MATNR_AlphaHP_LUT_15 Matnr high-pass filter alpha LUT node 15 +// //Bit 23:16, reg_MATNR_AlphaHP_LUT_14 Matnr high-pass filter alpha LUT node 14 +// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_13 Matnr high-pass filter alpha LUT node 13 +// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_12 Matnr high-pass filter alpha LUT node 12 +// +// `define NR2_MATNR_MTNB_BRT 8'h77 +// //Bit 31:28, reg_MATNR_mtnb_BRT_limt_hi Motion adjustment based on Brightness high side Limit. (X16 to u8 scale) +// //Bit 27:24, reg_MATNR_mtnb_BRT_slop_hi Motion adjustment based on Brightness high side slope. Normalized to 16 as 1 +// //Bit 23:16, reg_MATNR_mtnb_BRT_thrd_hi Motion adjustment based on Brightness high threshold.(u8 scale) +// //Bit 15:12, reg_MATNR_mtnb_BRT_limt_lo Motion adjustment based on Brightness low side Limit. (X16 to u8 scale) +// //Bit 11: 8, reg_MATNR_mtnb_BRT_slop_lo Motion adjustment based on Brightness low side slope. Normalized to 16 as 1 +// //Bit 7: 0, reg_MATNR_mtnb_BRT_thrd_lo Motion adjustment based on Brightness low threshold.(u8 scale) +// 0x51 - 0x69 | 0x4e | 0x6a - 0x77 +// +// Reading file: vpu_nr2_regs.h +// +// synopsys translate_off +// synopsys translate_on +//========== nr2_snr_regs register begin ==========// +#define NR2_SNR_SAD_CFG ((0x1751 << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12 reg_matnr_snr_sad_cenrpl // unsigned , default = 1 +//Bit 11: 8 reg_matnr_snr_sad_coring // unsigned , default = 3 +//Bit 7 reserved +//Bit 6: 5 reg_matnr_snr_sad_winmod // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1]; +//Bit 4: 0 sad_coef_num // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1]; +#define NR2_MATNR_SNR_OS ((0x1752 << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7: 4 reg_matnr_snr_cos // unsigned , default = 8 +//Bit 3: 0 reg_matnr_snr_yos // unsigned , default = 13 +#define NR2_MATNR_SNR_NRM_CFG ((0x1753 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_matnr_snr_nrm_ofst // signed , default = 64 +//Bit 15: 8 reg_matnr_snr_nrm_max // unsigned , default = 255 +//Bit 7: 0 reg_matnr_snr_nrm_min // unsigned , default = 0 +#define NR2_MATNR_SNR_NRM_GAIN ((0x1754 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_matnr_snr_nrm_cgain // unsigned , default = 0 norm 32 +//Bit 7: 0 reg_matnr_snr_nrm_ygain // unsigned , default = 32 norm 32 +#define NR2_MATNR_SNR_LPF_CFG ((0x1755 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_matnr_snrlpf_sadmaxth // unsigned , default = 12 +//Bit 15:14 reserved +//Bit 13:11 reg_matnr_snrlpf_cmode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16; +//Bit 10: 8 reg_matnr_snrlpf_ymode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16; +//Bit 7: 4 reg_matnr_snrlpf_sadmin3th // unsigned , default = 6 X8 +//Bit 3: 0 reg_matnr_snrlpf_sadmin2th // unsigned , default = 4 X8 +#define NR2_MATNR_SNR_USF_GAIN ((0x1756 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_matnr_snr_usf_cgain // unsigned , default = 0 norm 64 +//Bit 7: 0 reg_matnr_snr_usf_ygain // unsigned , default = 0 norm 64 +#define NR2_MATNR_SNR_EDGE2B ((0x1757 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_matnr_snr_edge2beta_ofst // unsigned , default = 128 +//Bit 7: 0 reg_matnr_snr_edge2beta_gain // unsigned , default = 16 +#define NR2_MATNR_BETA_EGAIN ((0x1758 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_matnr_cbeta_egain // unsigned , default = 32 normalized to 32 +//Bit 7: 0 reg_matnr_ybeta_egain // unsigned , default = 32 normalized to 32 +#define NR2_MATNR_BETA_BRT ((0x1759 << 2) + 0xff000000) +//Bit 31:28 reg_matnr_beta_brt_limt_hi // unsigned , default = 0 +//Bit 27:24 reg_matnr_beta_brt_slop_hi // unsigned , default = 0 +//Bit 23:16 reg_matnr_beta_brt_thrd_hi // unsigned , default = 160 +//Bit 15:12 reg_matnr_beta_brt_limt_lo // unsigned , default = 6 +//Bit 11: 8 reg_matnr_beta_brt_slop_lo // unsigned , default = 6 +//Bit 7: 0 reg_matnr_beta_brt_thrd_lo // unsigned , default = 100 +#define NR2_MATNR_XBETA_CFG ((0x175a << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19:18 reg_matnr_cbeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2 +//Bit 17:16 reg_matnr_ybeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2; +//Bit 15: 8 reg_matnr_cbeta_ofst // unsigned , default = 0 +//Bit 7: 0 reg_matnr_ybeta_ofst // unsigned , default = 0 +#define NR2_MATNR_YBETA_SCL ((0x175b << 2) + 0xff000000) +//Bit 31:24 reg_matnr_ybeta_scale_min // unsigned , default = 60 +//Bit 23:16 reg_matnr_ybeta_scale_max // unsigned , default = 255 +//Bit 15: 8 reg_matnr_ybeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0 +//Bit 7: 0 reg_matnr_ybeta_scale_ofst // signed , default = 0 +#define NR2_MATNR_CBETA_SCL ((0x175c << 2) + 0xff000000) +//Bit 31:24 reg_matnr_cbeta_scale_min // unsigned , default = 0 +//Bit 23:16 reg_matnr_cbeta_scale_max // unsigned , default = 255 +//Bit 15: 8 reg_matnr_cbeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0 +//Bit 7: 0 reg_matnr_cbeta_scale_ofst // signed , default = 0 +#define NR2_SNR_MASK ((0x175d << 2) + 0xff000000) +//Bit 31:21 reserved +//Bit 20: 0 sad_msk // unsigned , default = 0x0f9f3e +#define NR2_SAD2NORM_LUT0 ((0x175e << 2) + 0xff000000) +//Bit 31:24 reg_matnr_sad2norm_lut3 // unsigned , default = 114 +//Bit 23:16 reg_matnr_sad2norm_lut2 // unsigned , default = 146 +//Bit 15: 8 reg_matnr_sad2norm_lut1 // unsigned , default = 171 +//Bit 7: 0 reg_matnr_sad2norm_lut0 // unsigned , default = 205 +#define NR2_SAD2NORM_LUT1 ((0x175f << 2) + 0xff000000) +//Bit 31:24 reg_matnr_sad2norm_lut7 // unsigned , default = 28 +//Bit 23:16 reg_matnr_sad2norm_lut6 // unsigned , default = 35 +//Bit 15: 8 reg_matnr_sad2norm_lut5 // unsigned , default = 49 +//Bit 7: 0 reg_matnr_sad2norm_lut4 // unsigned , default = 79 +#define NR2_SAD2NORM_LUT2 ((0x1760 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_sad2norm_lut11 // unsigned , default = 15 +//Bit 23:16 reg_matnr_sad2norm_lut10 // unsigned , default = 17 +//Bit 15: 8 reg_matnr_sad2norm_lut9 // unsigned , default = 19 +//Bit 7: 0 reg_matnr_sad2norm_lut8 // unsigned , default = 23 +#define NR2_SAD2NORM_LUT3 ((0x1761 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_sad2norm_lut15 // unsigned , default = 8 +//Bit 23:16 reg_matnr_sad2norm_lut14 // unsigned , default = 9 +//Bit 15: 8 reg_matnr_sad2norm_lut13 // unsigned , default = 10 +//Bit 7: 0 reg_matnr_sad2norm_lut12 // unsigned , default = 12 +#define NR2_EDGE2BETA_LUT0 ((0x1762 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_edge2beta_lut3 // unsigned , default = 128 +//Bit 23:16 reg_matnr_edge2beta_lut2 // unsigned , default = 160 +//Bit 15: 8 reg_matnr_edge2beta_lut1 // unsigned , default = 224 +//Bit 7: 0 reg_matnr_edge2beta_lut0 // unsigned , default = 255 +#define NR2_EDGE2BETA_LUT1 ((0x1763 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_edge2beta_lut7 // unsigned , default = 4 +//Bit 23:16 reg_matnr_edge2beta_lut6 // unsigned , default = 16 +//Bit 15: 8 reg_matnr_edge2beta_lut5 // unsigned , default = 32 +//Bit 7: 0 reg_matnr_edge2beta_lut4 // unsigned , default = 80 +#define NR2_EDGE2BETA_LUT2 ((0x1764 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_edge2beta_lut11 // unsigned , default = 0 +//Bit 23:16 reg_matnr_edge2beta_lut10 // unsigned , default = 0 +//Bit 15: 8 reg_matnr_edge2beta_lut9 // unsigned , default = 0 +//Bit 7: 0 reg_matnr_edge2beta_lut8 // unsigned , default = 2 +#define NR2_EDGE2BETA_LUT3 ((0x1765 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_edge2beta_lut15 // unsigned , default = 0 +//Bit 23:16 reg_matnr_edge2beta_lut14 // unsigned , default = 0 +//Bit 15: 8 reg_matnr_edge2beta_lut13 // unsigned , default = 0 +//Bit 7: 0 reg_matnr_edge2beta_lut12 // unsigned , default = 0 +#define NR2_MOTION2BETA_LUT0 ((0x1766 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_mot2beta_lut3 // unsigned , default = 32 +//Bit 23:16 reg_matnr_mot2beta_lut2 // unsigned , default = 16 +//Bit 15: 8 reg_matnr_mot2beta_lut1 // unsigned , default = 4 +//Bit 7: 0 reg_matnr_mot2beta_lut0 // unsigned , default = 0 +#define NR2_MOTION2BETA_LUT1 ((0x1767 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_mot2beta_lut7 // unsigned , default = 196 +//Bit 23:16 reg_matnr_mot2beta_lut6 // unsigned , default = 128 +//Bit 15: 8 reg_matnr_mot2beta_lut5 // unsigned , default = 64 +//Bit 7: 0 reg_matnr_mot2beta_lut4 // unsigned , default = 48 +#define NR2_MOTION2BETA_LUT2 ((0x1768 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_mot2beta_lut11 // unsigned , default = 255 +//Bit 23:16 reg_matnr_mot2beta_lut10 // unsigned , default = 255 +//Bit 15: 8 reg_matnr_mot2beta_lut9 // unsigned , default = 240 +//Bit 7: 0 reg_matnr_mot2beta_lut8 // unsigned , default = 224 +#define NR2_MOTION2BETA_LUT3 ((0x1769 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_mot2beta_lut15 // unsigned , default = 255 +//Bit 23:16 reg_matnr_mot2beta_lut14 // unsigned , default = 255 +//Bit 15: 8 reg_matnr_mot2beta_lut13 // unsigned , default = 255 +//Bit 7: 0 reg_matnr_mot2beta_lut12 // unsigned , default = 255 +//========== nr2_snr_regs register end ==========// +//========== nr2_tnr_regs register begin ==========// +#define NR2_IIR_CTRL ((0x174e << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15:14 reg_lp_iir_8bit_mode // unsigned , default = 0 10bits; 1: 9bits; 2: 8bits 3: 7bits +//Bit 13:12 reg_hp_iir_mute_mode // unsigned , default = 0 +//Bit 11: 8 reg_hp_iir_mute_thrd // unsigned , default = 0 +//Bit 7: 6 reg_hp_iir_8bit_mode // unsigned , default = 0 +//Bit 5: 4 reg_lp_iir_mute_mode // unsigned , default = 0 +//Bit 3: 0 reg_lp_iir_mute_thrd // unsigned , default = 0 +#define NR2_MATNR_MTN_CRTL ((0x176a << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19:18 reg_matnr_vmtn_use_mode // unsigned , default = 0 0- Vmot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot) +//Bit 17:16 reg_matnr_umtn_use_mode // unsigned , default = 0 0- Umot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot) +//Bit 15:14 reg_matnr_ymtn_use_mode // unsigned , default = 0 0- Ymot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot) +//Bit 13:12 reg_matnr_mtn_txt_mode // unsigned , default = 1 +//Bit 11 reserved +//Bit 10: 8 reg_matnr_mtn_cor_mode // unsigned , default = 1 changes) +//Bit 7: 4 reg_matnr_mtn_hpf_mode // unsigned , default = 8 extend to u4 for nr4, 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6:3x3 SAD, 7: 5x3 SAD, 8-15: drt adaptive +//Bit 3 reserved +//Bit 2: 0 reg_matnr_mtn_lpf_mode // unsigned , default = 6 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6,7: drt adaptive +#define NR2_MATNR_MTN_CRTL2 ((0x176b << 2) + 0xff000000) +//Bit 31:19 reserved +//Bit 18:16 reg_matnr_iir_bs_ymode // unsigned , default = 6 LPF~~ 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5; 6/7: 0 +//Bit 15: 8 reg_matnr_mtnb_alplp_cgain // unsigned , default = 64 to 32 +//Bit 7: 0 reg_matnr_mtnb_alplp_ygain // unsigned , default = 64 to 32 +#define NR2_MATNR_MTN_COR ((0x176c << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15:12 reg_matnr_mtn_cor_cofst // unsigned , default = 3 Offset for Chroma Motion. +//Bit 11: 8 reg_matnr_mtn_cor_cgain // unsigned , default = 3 to texture based coring for Chroma Motion. Normalized to 16 as 1 +//Bit 7: 4 reg_matnr_mtn_cor_yofst // unsigned , default = 3 Offset for Luma Motion. +//Bit 3: 0 reg_matnr_mtn_cor_ygain // unsigned , default = 3 to texture based coring for Luma Motion. Normalized to 16 as 1 +#define NR2_MATNR_MTN_GAIN ((0x176d << 2) + 0xff000000) +//Bit 31:24 reg_matnr_mtn_hp_cgain // unsigned , default = 64 to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1 +//Bit 23:16 reg_matnr_mtn_hp_ygain // unsigned , default = 64 to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1 +//Bit 15: 8 reg_matnr_mtn_lp_cgain // unsigned , default = 64 to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1 +//Bit 7: 0 reg_matnr_mtn_lp_ygain // unsigned , default = 64 to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1 +#define NR2_MATNR_DEGHOST ((0x176e << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_matnr_deghost_mode // unsigned , default = 0 0:old_deghost; 1:soft_denoise & strong_deghost; 2:strong_denoise & soft_deghost; 3:strong_denoise & strong_deghost +//Bit 27:25 reserved +//Bit 24:20 reg_matnr_deghost_ygain // unsigned , default = 4 +//Bit 19:17 reserved +//Bit 16:12 reg_matnr_deghost_cgain // unsigned , default = 4 +//Bit 11: 9 reserved +//Bit 8 reg_matnr_deghost_en // unsigned , default = 1 0: disable; 1: enable Enable signal for DeGhost function:0: disable; 1: enable +//Bit 7: 4 reg_matnr_deghost_cos // unsigned , default = 3 DeGhost Overshoot margin for UV channel, (X2 to u10 scale) +//Bit 3: 0 reg_matnr_deghost_yos // unsigned , default = 3 DeGhost Overshoot margin for Luma channel, (X2 to u10 scale) +#define NR2_MATNR_ALPHALP_LUT0 ((0x176f << 2) + 0xff000000) +//Bit 31:24 reg_matnr_alphalp_lut3 // unsigned , default = 64 low-pass filter alpha LUT +//Bit 23:16 reg_matnr_alphalp_lut2 // unsigned , default = 128 low-pass filter alpha LUT +//Bit 15: 8 reg_matnr_alphalp_lut1 // unsigned , default = 128 low-pass filter alpha LUT +//Bit 7: 0 reg_matnr_alphalp_lut0 // unsigned , default = 128 low-pass filter alpha LUT +#define NR2_MATNR_ALPHALP_LUT1 ((0x1770 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_alphalp_lut7 // unsigned , default = 255 low-pass filter alpha LUT +//Bit 23:16 reg_matnr_alphalp_lut6 // unsigned , default = 128 low-pass filter alpha LUT +//Bit 15: 8 reg_matnr_alphalp_lut5 // unsigned , default = 80 low-pass filter alpha LUT +//Bit 7: 0 reg_matnr_alphalp_lut4 // unsigned , default = 64 low-pass filter alpha LUT +#define NR2_MATNR_ALPHALP_LUT2 ((0x1771 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_alphalp_lut11 // unsigned , default = 255 low-pass filter alpha LUT +//Bit 23:16 reg_matnr_alphalp_lut10 // unsigned , default = 255 low-pass filter alpha LUT +//Bit 15: 8 reg_matnr_alphalp_lut9 // unsigned , default = 255 low-pass filter alpha LUT +//Bit 7: 0 reg_matnr_alphalp_lut8 // unsigned , default = 255 low-pass filter alpha LUT +#define NR2_MATNR_ALPHALP_LUT3 ((0x1772 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_alphalp_lut15 // unsigned , default = 255 low-pass filter alpha LUT +//Bit 23:16 reg_matnr_alphalp_lut14 // unsigned , default = 255 low-pass filter alpha LUT +//Bit 15: 8 reg_matnr_alphalp_lut13 // unsigned , default = 255 low-pass filter alpha LUT +//Bit 7: 0 reg_matnr_alphalp_lut12 // unsigned , default = 255 low-pass filter alpha LUT +#define NR2_MATNR_ALPHAHP_LUT0 ((0x1773 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_alphahp_lut3 // unsigned , default = 64 high-pass filter alpha LUT +//Bit 23:16 reg_matnr_alphahp_lut2 // unsigned , default = 128 high-pass filter alpha LUT +//Bit 15: 8 reg_matnr_alphahp_lut1 // unsigned , default = 128 high-pass filter alpha LUT +//Bit 7: 0 reg_matnr_alphahp_lut0 // unsigned , default = 128 high-pass filter alpha LUT +#define NR2_MATNR_ALPHAHP_LUT1 ((0x1774 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_alphahp_lut7 // unsigned , default = 255 high-pass filter alpha LUT +//Bit 23:16 reg_matnr_alphahp_lut6 // unsigned , default = 128 high-pass filter alpha LUT +//Bit 15: 8 reg_matnr_alphahp_lut5 // unsigned , default = 80 high-pass filter alpha LUT +//Bit 7: 0 reg_matnr_alphahp_lut4 // unsigned , default = 64 high-pass filter alpha LUT +#define NR2_MATNR_ALPHAHP_LUT2 ((0x1775 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_alphahp_lut11 // unsigned , default = 255 high-pass filter alpha LUT +//Bit 23:16 reg_matnr_alphahp_lut10 // unsigned , default = 255 high-pass filter alpha LUT +//Bit 15: 8 reg_matnr_alphahp_lut9 // unsigned , default = 255 high-pass filter alpha LUT +//Bit 7: 0 reg_matnr_alphahp_lut8 // unsigned , default = 255 high-pass filter alpha LUT +#define NR2_MATNR_ALPHAHP_LUT3 ((0x1776 << 2) + 0xff000000) +//Bit 31:24 reg_matnr_alphahp_lut15 // unsigned , default = 255 high-pass filter alpha LUT +//Bit 23:16 reg_matnr_alphahp_lut14 // unsigned , default = 255 high-pass filter alpha LUT +//Bit 15: 8 reg_matnr_alphahp_lut13 // unsigned , default = 255 high-pass filter alpha LUT +//Bit 7: 0 reg_matnr_alphahp_lut12 // unsigned , default = 255 high-pass filter alpha LUT +#define NR2_MATNR_MTNB_BRT ((0x1777 << 2) + 0xff000000) +//Bit 31:28 reg_matnr_mtnb_brt_limt_hi // unsigned , default = 0 +//Bit 27:24 reg_matnr_mtnb_brt_slop_hi // unsigned , default = 0 +//Bit 23:16 reg_matnr_mtnb_brt_thrd_hi // unsigned , default = 160 +//Bit 15:12 reg_matnr_mtnb_brt_limt_lo // unsigned , default = 6 +//Bit 11: 8 reg_matnr_mtnb_brt_slop_lo // unsigned , default = 6 +//Bit 7: 0 reg_matnr_mtnb_brt_thrd_lo // unsigned , default = 100 +//========== nr2_tnr_regs register end ==========// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_nr2_regs.h +// +// +// Reading file: nr2_cue_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define NR2_CUE_MODE ((0x1778 << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19 reg_cue2_isabv_org_invert1 // unsigned , default = 0 +//Bit 18 reg_cue2_valid_condition // unsigned , default = 1 +//Bit 17:16 reg_cue2_orgline_flt_sel // unsigned , default = 1 +//Bit 15:12 reg_cue2_orgline_flt_alph // unsigned , default = 4 +//Bit 11 reg_cue2_isabv_org_invert // unsigned , default = 0 +//Bit 10 reg_cue2_iscur_org_invert // unsigned , default = 0 +//Bit 9 reg_cue_enable_r // unsigned , default = 1 right half frame enable +//Bit 8 reg_cue_enable_l // unsigned , default = 1 left half frame enable +//Bit 7 reserved +//Bit 6: 4 reg_cue_con_rplc_mode // unsigned , default = 7 pixel chroma replace mode; +//Bit 3: 0 reg_cue_chrm_flt_mode // unsigned , default = 5 improvement filter mode, +#define NR2_CUE_CON_MOT_TH ((0x1779 << 2) + 0xff000000) +//Bit 31:24 reg_cue_con_cmot_thrd2 // unsigned , default = 20 Detection threshold of up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection (tighter). +//Bit 23:16 reg_cue_con_ymot_thrd2 // unsigned , default = 20 Detection threshold of up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE) Detection (tighter). +//Bit 15: 8 reg_cue_con_cmot_thrd // unsigned , default = 20 Detection threshold of up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection. +//Bit 7: 0 reg_cue_con_ymot_thrd // unsigned , default = 20 Detection threshold of up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE) Detection. +#define NR2_CUE_CON_DIF0 ((0x177a << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_cue_con_difp1_thrd // unsigned , default = 20 field Intra-Field top/below line chroma difference threshold, +//Bit 7: 0 reg_cue_con_difcur_thrd // unsigned , default = 0 Field/Frame Intra-Field up/down line chroma difference threshold, +#define NR2_CUE_CON_DIF1 ((0x177b << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19:16 reg_cue_con_rate0 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_diflG and CUE_difEG +//Bit 15: 8 reg_cue_con_difeg_thrd // unsigned , default = 0 to the difference between current Field/Frame middle line to down line color channel(CUE_difEG). +//Bit 7: 0 reg_cue_con_diflg_thrd // unsigned , default = 100 to the difference between P1 field top line to current Field/Frame down line color channel (CUE_diflG). +#define NR2_CUE_CON_DIF2 ((0x177c << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19:16 reg_cue_con_rate1 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_difnC and CUE_difEC +//Bit 15: 8 reg_cue_con_difec_thrd // unsigned , default = 0 to the difference between current Field/Frame middle line to up line color channel(CUE_difEC). +//Bit 7: 0 reg_cue_con_difnc_thrd // unsigned , default = 100 to the difference between P1 field bot line to current Field/Frame up line color channel (CUE_difnC). +#define NR2_CUE_CON_DIF3 ((0x177d << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19:16 reg_cue_con_rate2 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_difP1 and CUE_difEP1 +//Bit 15: 8 reg_cue_con_difep1_thrd // unsigned , default = 10 top/below line to current field/frame middle line chroma difference (CUE_difEP1) threshold. +//Bit 7: 0 reg_cue_con_difp1_thrd2 // unsigned , default = 10 field Intra-Field top/below line chroma difference threshold (tighter), +#define NR2_CUE_PRG_DIF ((0x177e << 2) + 0xff000000) +//Bit 31:21 reserved +//Bit 20 reg_cue_prg_enable // unsigned , default = 0 bit for progressive video CUE detection.If interlace input video, +//Bit 19:16 reg_cue_prg_rate // unsigned , default = 4 Krate to decide CUE by relationship between CUE_difCur and (CUE_difEC+CUE_difEG) +//Bit 15: 8 reg_cue_prg_difceg_thrd // unsigned , default = 40 Frame Intra-Field up-mid and mid-down line chroma difference threshold for progressive video CUE detection, +//Bit 7: 0 reg_cue_prg_difcur_thrd // unsigned , default = 30 Frame Intra-Field up/down line chroma difference threshold, +// synopsys translate_off +// synopsys translate_on +// +// Closing file: nr2_cue_regs.h +// +#define NR2_CONV_MODE ((0x177f << 2) + 0xff000000) +//Bit 3:2, Conv_c444_mode The format convert mode about 422 to 444 when data read out line buffer +//Bit 1:0, Conv_c422_mode the format convert mode about 444 to 422 when data write to line buffer +//// NR2 REG DEFINE END //// +//// DET 3D REG DEFINE BEGIN //// +//// 8'h34~8'h3f | 8'h80~8'h8f | 0x9a-0x9b +// +// Reading file: vpu_det3d_regs.h +// +//// DET 3D REG DEFINE BEGIN //// +//// 8'h34~8'h3f +//// DET 3D REG DEFINE END //// +#define DET3D_MOTN_CFG ((0x1734 << 2) + 0xff000000) +//Bit 16, reg_det3d_intr_en Det3d interrupt enable +//Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma: +// 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2) +//Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32 +//Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection. +#define DET3D_CB_CFG ((0x1735 << 2) + 0xff000000) +//Bit 7:4, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection. +//Bit 3:0, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection. +#define DET3D_SPLT_CFG ((0x1736 << 2) + 0xff000000) +//Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection. +// The smaller of this value, the easier of the split line detected. +//Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation. +// The smaller of this value, the more samples will be added to the estimation. +#define DET3D_HV_MUTE ((0x1737 << 2) + 0xff000000) +//Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part. +//Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part. +//Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part +//Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part +//Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block. +//Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block. +#define DET3D_MAT_STA_P1M1 ((0x1738 << 2) + 0xff000000) +//Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8) +//Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5) +//Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1) +//Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8) +#define DET3D_MAT_STA_P1TH ((0x1739 << 2) + 0xff000000) +//Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100) +//Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80) +//Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48) +#define DET3D_MAT_STA_M1TH ((0x173a << 2) + 0xff000000) +//Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100) +//Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80) +//Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64) +#define DET3D_MAT_STA_RSFT ((0x173b << 2) + 0xff000000) +//Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: +// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions +//Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: +// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions +//Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping: +// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions +#define DET3D_MAT_SYMTC_TH ((0x173c << 2) + 0xff000000) +//Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric. +//Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric. +//Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric. +//Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric. +#define DET3D_RO_DET_CB_HOR ((0x173d << 2) + 0xff000000) +//Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern. +//Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern. +#define DET3D_RO_DET_CB_VER ((0x173e << 2) + 0xff000000) +//Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern. +//Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern. +#define DET3D_RO_SPLT_HT ((0x173f << 2) + 0xff000000) +//Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture +//Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture +//Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture +//// DET 3D REG DEFINE BEGIN //// +//// 8'h80~8'h8f +#define DET3D_RO_SPLT_HB ((0x1780 << 2) + 0xff000000) +//Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture +//Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture +//Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture +#define DET3D_RO_SPLT_VL ((0x1781 << 2) + 0xff000000) +//Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture +//Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture +//Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture +#define DET3D_RO_SPLT_VR ((0x1782 << 2) + 0xff000000) +//Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture +//Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture +//Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture +#define DET3D_RO_MAT_LUMA_LR ((0x1783 << 2) + 0xff000000) +//Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically), +// it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric +//Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically), +// it can be 0/1: 0: not sure 1: most likely LR is pure symmetric +//Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision, +// the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7] +#define DET3D_RO_MAT_LUMA_TB ((0x1784 << 2) + 0xff000000) +//Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally), +//Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally), +//Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision, +#define DET3D_RO_MAT_CHRU_LR ((0x1785 << 2) + 0xff000000) +//Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically), +//Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically), +//Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision, +#define DET3D_RO_MAT_CHRU_TB ((0x1786 << 2) + 0xff000000) +//Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally) +//Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally) +//Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision +#define DET3D_RO_MAT_CHRV_LR ((0x1787 << 2) + 0xff000000) +//Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically) +//Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically) +//Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision +#define DET3D_RO_MAT_CHRV_TB ((0x1788 << 2) + 0xff000000) +//Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally) +//Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally) +//Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision +#define DET3D_RO_MAT_HEDG_LR ((0x1789 << 2) + 0xff000000) +//Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically) +//Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically) +//Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision +#define DET3D_RO_MAT_HEDG_TB ((0x178a << 2) + 0xff000000) +//Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally) +//Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally) +//Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision +#define DET3D_RO_MAT_VEDG_LR ((0x178b << 2) + 0xff000000) +//Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically) +//Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically) +//Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision +#define DET3D_RO_MAT_VEDG_TB ((0x178c << 2) + 0xff000000) +//Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally) +//Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally) +//Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision +#define DET3D_RO_MAT_MOTN_LR ((0x178d << 2) + 0xff000000) +//Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically) +//Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically) +//Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision +#define DET3D_RO_MAT_MOTN_TB ((0x178e << 2) + 0xff000000) +//Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally) +//Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally) +//Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision +#define DET3D_RO_FRM_MOTN ((0x178f << 2) + 0xff000000) +//Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW. +/// mat ram read enter addr +#define DET3D_RAMRD_ADDR_PORT ((0x179a << 2) + 0xff000000) +#define DET3D_RAMRD_DATA_PORT ((0x179b << 2) + 0xff000000) +// +// Closing file: vpu_det3d_regs.h +// +// `define DET3D_RO_SPLT_HB 8'h80 +// //Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture +// //Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture +// //Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture +// `define DET3D_RO_SPLT_VL 8'h81 +// //Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture +// //Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture +// //Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture +// `define DET3D_RO_SPLT_VR 8'h82 +// //Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture +// //Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture +// //Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture +// `define DET3D_RO_MAT_LUMA_LR 8'h83 +// //Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically), +// // it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric +// //Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically), +// // it can be 0/1: 0: not sure 1: most likely LR is pure symmetric +// //Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision, +// // the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7] +// `define DET3D_RO_MAT_LUMA_TB 8'h84 +// //Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally), +// //Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally), +// //Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision, +// `define DET3D_RO_MAT_CHRU_LR 8'h85 +// //Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically), +// //Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically), +// //Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision, +// `define DET3D_RO_MAT_CHRU_TB 8'h86 +// //Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally) +// //Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally) +// //Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision +// `define DET3D_RO_MAT_CHRV_LR 8'h87 +// //Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically) +// //Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically) +// //Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision +// `define DET3D_RO_MAT_CHRV_TB 8'h88 +// //Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally) +// //Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally) +// //Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision +// `define DET3D_RO_MAT_HEDG_LR 8'h89 +// //Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically) +// //Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically) +// //Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision +// `define DET3D_RO_MAT_HEDG_TB 8'h8a +// //Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally) +// //Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally) +// //Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision +// `define DET3D_RO_MAT_VEDG_LR 8'h8b +// //Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically) +// //Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically) +// //Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision +// `define DET3D_RO_MAT_VEDG_TB 8'h8c +// //Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally) +// //Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally) +// //Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision +// `define DET3D_RO_MAT_MOTN_LR 8'h8d +// //Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically) +// //Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically) +// //Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision +// `define DET3D_RO_MAT_MOTN_TB 8'h8e +// //Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally) +// //Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally) +// //Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision +// `define DET3D_RO_FRM_MOTN 8'h8f +// //Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW. +#define DI_EI_CTRL10 ((0x1793 << 2) + 0xff000000) +//bit 31:28, reg_ei_caldrt_hstrrgchk_drtth +//bit 27:24, reg_ei_caldrt_hstrrgchk_frcverthrd +//bit 23:20, reg_ei_caldrt_hstrrgchk_mg +//bit 19, reg_ei_caldrt_hstrrgchk_1sidnul +//bit 18, reg_ei_caldrt_hstrrgchk_excpcnf +//bit 17:16, reg_ei_caldrt_hstrrgchk_ws +//bit 15, reg_ei_caldrt_hstrrgchk_en +//bit 14:13, reg_ei_caldrt_hpncheck_mode +//bit 12, reg_ei_caldrt_hpncheck_mute +//bit 11:9, reg_ei_caldrt_hcnfcheck_mg2 +//bit 8:6, reg_ei_caldrt_hcnfcheck_mg1 +//bit 5:4, reg_ei_caldrt_hcnfcheck_mode +//bit 3:0, reg_ei_caldrt_hcnfcheck_mg2 +#define DI_NR_1_CTRL0 ((0x1794 << 2) + 0xff000000) +#define DI_NR_1_CTRL1 ((0x1795 << 2) + 0xff000000) +#define DI_NR_1_CTRL2 ((0x1796 << 2) + 0xff000000) +#define DI_NR_1_CTRL3 ((0x1797 << 2) + 0xff000000) +#define DI_EI_XWIN0 ((0x1798 << 2) + 0xff000000) +//bit 27:16, ei_xend0 +//bit 11:0, ei_xstart0 +#define DI_EI_XWIN1 ((0x1799 << 2) + 0xff000000) +/// mat ram read enter addr +// `define DET3D_RAMRD_ADDR_PORT 8'h9a +// `define DET3D_RAMRD_DATA_PORT 8'h9b +#define NR2_CFR_PARA_CFG0 ((0x179c << 2) + 0xff000000) +//Bit 8, reg_CFR_CurDif_luma_mode Current Field Top/Bot line Luma difference calculation mode +//Bit 7:6, reg_MACFR_frm_phase U2 This will be a field based phase register that need to be set by FW phase to phase: +// this will be calculated based on dbdr_phase of the specific line of this frame. +// u1: dbdr_phase=1, center line is DB in current line; dbdr_phase=2, center line is Dr in current line; +//Bit 5:4, reg_CFR_CurDif_tran_mode U2 Current Field Top/Bot line Luma/Chroma transition level calculation mode, +//Bit 3:2, reg_CFR_alpha_mode U2 Alpha selection mode for CFR block from curAlp and motAlp i.e. 0: motAlp; 1: (motAlp+curAlp)/2; 2: min(motAlp,curAlp); 3: max(motAlp,curAlp); +//Bit 1:0, reg_CFR_Motion_Luma_mode U2 LumaMotion Calculation mode for MA-CFR. 0: top/bot Lumma motion; 1: middle Luma Motion 2: top/bot + middle motion; 3: max(top/tot motion, middle motion) +#define NR2_CFR_PARA_CFG1 ((0x179d << 2) + 0xff000000) +//Bit 23:16, reg_CFR_alpha_gain gain to map muxed curAlp and motAlp to alpha that will be used for final blending. +//Bit 15: 8, reg_CFR_Motion_ofst Offset to Motion to calculate the motAlp, e,g:motAlp= reg_CFR_Motion_ofst- Motion;This register can be seen as the level of motion that we consider it at moving. +//Bit 7: 0, reg_CFR_CurDif_gain gain to CurDif to map to alpha, normalized to 32; +//// DET 3D REG DEFINE END //// +#define DI_EI_CTRL11 ((0x179e << 2) + 0xff000000) +//bit 30:29, reg_ei_amb_detect_mode +//bit 28:24, reg_ei_amb_detect_winth +//bit 23:21, reg_ei_amb_decide_rppth +//bit 20:19, reg_ei_retime_lastmappncnfltchk_drtth +//bit 18:16, reg_ei_retime_lastmappncnfltchk_mode +//bit 15:14, reg_ei_retime_lastmapvertfrcchk_mode +//bit 13:12, reg_ei_retime_lastvertfrcchk_mode +//bit 11:8, reg_ei_retime_lastpnchk_drtth +//bit 6, reg_ei_retime_lastpnchk_en +//bit 5:4, reg_ei_retime_mode +//bit 3, reg_ei_retime_last_en +//bit 2, reg_ei_retime_ab_en +//bit 1, reg_ei_caldrt_hstrvertfrcchk_en +//bit 0, reg_ei_caldrt_hstrrgchk_mode +#define DI_EI_CTRL12 ((0x179f << 2) + 0xff000000) +//bit 31:28, reg_ei_drtdelay2_lmt +//bit 27:26, reg_ei_drtdelay2_notver_lrwin +//bit 25:24, reg_ei_drtdelay_mode +//bit 23, reg_ei_drtdelay2_mode +//bit 22:20, reg_ei_assign_xla_signm0th +//bit 19, reg_ei_assign_pkbiasvert_en +//bit 18, reg_ei_assign_xla_en +//bit 17:16, reg_ei_assign_xla_mode +//bit 15:12, reg_ei_assign_nlfilter_magin +//bit 11:8, reg_ei_localsearch_maxrange +//bit 7:4, reg_ei_xla_drtth +//bit 3:0, reg_ei_flatmsad_thrd +//`define DI_DIWR_CANVAS 8'ha0 +//`define DI_DIWR_URGENT 8'ha1 +//`define DI_NRWR_CANVAS 8'ha2 +//`define DI_NRWR_URGENT 8'ha7 +//`define DI_CONTWR_X 8'ha0 +//`define DI_CONTWR_Y 8'ha1 +//`define DI_CONTWR_CTRL 8'ha2 +//`define DI_CONTPRD_X 8'ha3 +//`define DI_CONTPRD_Y 8'ha4 +//`define DI_CONTP2RD_X 8'ha5 +//`define DI_CONTP2RD_Y 8'ha6 +#define DI_RO_PRE_FIELD_CNT0 ((0x17a3 << 2) + 0xff000000) +#define DI_RO_PRE_FIELD_CNT1 ((0x17a4 << 2) + 0xff000000) +#define DI_RO_POS_FRAME_CNT0 ((0x17a5 << 2) + 0xff000000) +#define DI_RO_POS_FRAME_CNT1 ((0x17a6 << 2) + 0xff000000) +//`define DI_CONTRD_CTRL 8'ha7 +#define DI_EI_CTRL13 ((0x17a8 << 2) + 0xff000000) +//bit 27:24, reg_ei_int_drt2x_chrdrt_limit +//bit 23:20, reg_ei_int_drt16x_core +//bit 19:16, reg_ei_int_drtdelay2_notver_cancv +//bit 15:8, reg_ei_int_drtdelay2_notver_sadth +//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth +#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff000000) +//bit 31:24, mtn_m1b_extnd +//bit 23:16, mtn_m1b_errod +//bit 15: 8, mtn_core_ykinter +//bit 7: 0, mtn_core_ckinter +#define DI_MTN_1_CTRL7 ((0x17aa << 2) + 0xff000000) +//bit 31:24, mtn_core_mxcmby +//bit 23:16, mtn_core_mxcmbc +//bit 15: 8, mtn_core_y +//bit 7: 0, mtn_core_c +#define DI_MTN_1_CTRL8 ((0x17ab << 2) + 0xff000000) +//bit 31:24, mtn_fcore_ykinter +//bit 23:16, mtn_fcore_ckinter +//bit 15: 8, mtn_fcore_ykintra +//bit 7: 0, mtn_fcore_ckintra +#define DI_MTN_1_CTRL9 ((0x17ac << 2) + 0xff000000) +//bit 31:24, mtn_fcore_2yrate +//bit 23:16, mtn_fcore_2crate +//bit 15: 8, mtn_fcore_y +//bit 7: 0, mtn_fcore_c +#define DI_MTN_1_CTRL10 ((0x17ad << 2) + 0xff000000) +//bit 27:24, mtn_motfld0 +//bit 19:16, mtn_stlfld0 +//bit 11: 8, mtn_motfld1 +//bit 3: 0, mtn_stlfld1 +#define DI_MTN_1_CTRL11 ((0x17ae << 2) + 0xff000000) +//bit 27:24, mtn_smotevn +//bit 20:16, mtn_smotodd +//bit 11: 8, mtn_sstlevn +//bit 4: 0, mtn_sstlodd +#define DI_MTN_1_CTRL12 ((0x17af << 2) + 0xff000000) +//bit 31:24, mtn_mgain +//bit 17:16, mtn_mmode +//bit 15: 8, mtn_sthrd +//bit 4: 0, mtn_sgain +//`define DI_NRWR_X 8'hc0 +//`define DI_NRWR_Y 8'hc1 +//bit 31:30 nrwr_words_lim +//bit 29 nrwr_rev_y +//bit 28:16 nrwr_start_y +//bit 15 nrwr_ext_en +//bit 12:0 nrwr_end_y +//`define DI_NRWR_CTRL 8'hc2 +//bit 31 pending_ddr_wrrsp_diwr +//bit 30 nrwr_reg_swap +//bit 29:26 nrwr_burst_lim +//bit 25 nrwr_canvas_syncen +//bit 24 nrwr_no_clk_gate +//bit 23:22 nrwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas; + //2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved +//bit 21:20 nrwr_hconv_mode +//bit 19:18 nrwr_vconv_mode +//bit 17 nrwr_swap_cbcr +//bit 16 nrwr_urgent +//bit 15:8 nrwr_canvas_index_chroma +//bit 7:0 nrwr_canvas_index_luma +//`define DI_MTNWR_X 8'hc3 +//`define DI_MTNWR_Y 8'hc4 +//`define DI_MTNWR_CTRL 8'hc5 +#define DI_RO_CRC_NRWR ((0x17c0 << 2) + 0xff000000) +#define DI_RO_CRC_MTNWR ((0x17c1 << 2) + 0xff000000) +#define DI_RO_CRC_DEINT ((0x17c2 << 2) + 0xff000000) +#define DI_CRC_CHK0 ((0x17c3 << 2) + 0xff000000) +#define DI_CRC_CHK1 ((0x17c4 << 2) + 0xff000000) +//`define DI_DIWR_X 8'hc6 +//`define DI_DIWR_Y 8'hc7 +//bit 31:30 diwr_words_lim +//bit 29 diwr_rev_y +//bit 28:16 diwr_start_y +//bit 15 diwr_ext_en +//bit 12:0 diwr_end_y +//`define DI_DIWR_CTRL 8'hc8 +//bit 31 pending_ddr_wrrsp_diwr +//bit 30 diwr_reg_swap +//bit 29:26 diwr_burst_lim +//bit 25 diwr_canvas_syncen +//bit 24 diwr_no_clk_gate +//bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas; + //2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved +//bit 21:20 diwr_hconv_mode +//bit 19:18 diwr_vconv_mode +//bit 17 diwr_swap_cbcr +//bit 16 diwr_urgent +//bit 15:8 diwr_canvas_index_chroma +//bit 7:0 diwr_canvas_index_luma +//`define DI_MTNCRD_X 8'hc9 +//`define DI_MTNCRD_Y 8'hca +//`define DI_MTNPRD_X 8'hcb +//`define DI_MTNPRD_Y 8'hcc +//`define DI_MTNRD_CTRL 8'hcd +#define DI_TOP_PRE_CTRL ((0x17c5 << 2) + 0xff000000) +#define DI_TOP_POST_CTRL ((0x17c6 << 2) + 0xff000000) +#define DI_PRE_GL_CTRL ((0x17c7 << 2) + 0xff000000) +#define DI_PRE_GL_THD ((0x17c8 << 2) + 0xff000000) +#define DI_POST_GL_CTRL ((0x17c9 << 2) + 0xff000000) +#define DI_POST_GL_THD ((0x17ca << 2) + 0xff000000) +#define DI_RO_PRE_DBG ((0x17cb << 2) + 0xff000000) +#define DI_RO_POST_DBG ((0x17cc << 2) + 0xff000000) +#define DI_TOP_CTRL ((0x17cd << 2) + 0xff000000) +#define DI_AFBCD_GCLK0 ((0x17ce << 2) + 0xff000000) +#define DI_AFBCD_GCLK1 ((0x17cf << 2) + 0xff000000) +#define DI_RDMIF_DEPTH0 ((0x17d0 << 2) + 0xff000000) +#define DI_RDMIF_DEPTH1 ((0x17d1 << 2) + 0xff000000) +#define DI_RDMIF_DEPTH2 ((0x17d2 << 2) + 0xff000000) +//`define DI_INP_GEN_REG 8'hce +//`define DI_INP_CANVAS0 8'hcf +//`define DI_INP_LUMA_X0 8'hd0 +//`define DI_INP_LUMA_Y0 8'hd1 +//`define DI_INP_CHROMA_X0 8'hd2 +//`define DI_INP_CHROMA_Y0 8'hd3 +//`define DI_INP_RPT_LOOP 8'hd4 +//`define DI_INP_LUMA0_RPT_PAT 8'hd5 +//`define DI_INP_CHROMA0_RPT_PAT 8'hd6 +//`define DI_INP_DUMMY_PIXEL 8'hd7 +//`define DI_INP_LUMA_FIFO_SIZE 8'hd8 +//`define DI_INP_RANGE_MAP_Y 8'hba +//`define DI_INP_RANGE_MAP_CB 8'hbb +//`define DI_INP_RANGE_MAP_CR 8'hbc +//`define DI_INP_GEN_REG2 8'h91 +// +//`define DI_INP_FMT_CTRL 8'hd9 +//`define DI_INP_FMT_W 8'hda +//// +//`define DI_MEM_GEN_REG 8'hdb +//`define DI_MEM_CANVAS0 8'hdc +//`define DI_MEM_LUMA_X0 8'hdd +//`define DI_MEM_LUMA_Y0 8'hde +//`define DI_MEM_CHROMA_X0 8'hdf +//`define DI_MEM_CHROMA_Y0 8'he0 +//`define DI_MEM_RPT_LOOP 8'he1 +//`define DI_MEM_LUMA0_RPT_PAT 8'he2 +//`define DI_MEM_CHROMA0_RPT_PAT 8'he3 +//`define DI_MEM_DUMMY_PIXEL 8'he4 +//`define DI_MEM_LUMA_FIFO_SIZE 8'he5 +//`define DI_MEM_RANGE_MAP_Y 8'hbd +//`define DI_MEM_RANGE_MAP_CB 8'hbe +//`define DI_MEM_RANGE_MAP_CR 8'hbf +//`define DI_MEM_GEN_REG2 8'h92 +// +//`define DI_MEM_FMT_CTRL 8'he6 +//`define DI_MEM_FMT_W 8'he7 +// +//`define DI_IF1_GEN_REG 8'he8 +//`define DI_IF1_CANVAS0 8'he9 +//`define DI_IF1_LUMA_X0 8'hea +//`define DI_IF1_LUMA_Y0 8'heb +//`define DI_IF1_CHROMA_X0 8'hec +//`define DI_IF1_CHROMA_Y0 8'hed +//`define DI_IF1_RPT_LOOP 8'hee +//`define DI_IF1_LUMA0_RPT_PAT 8'hef +//`define DI_IF1_CHROMA0_RPT_PAT 8'hf0 +//`define DI_IF1_DUMMY_PIXEL 8'hf1 +//`define DI_IF1_LUMA_FIFO_SIZE 8'hf2 +//`define DI_IF1_RANGE_MAP_Y 8'hfc +//`define DI_IF1_RANGE_MAP_CB 8'hfd +//`define DI_IF1_RANGE_MAP_CR 8'hfe +//`define DI_IF1_GEN_REG2 8'h90 +// +//`define DI_IF1_FMT_CTRL 8'hf3 +//`define DI_IF1_FMT_W 8'hf4 +// +// +//`define DI_CHAN2_GEN_REG 8'hf5 +//`define DI_CHAN2_CANVAS0 8'hf6 +//`define DI_CHAN2_LUMA_X0 8'hf7 +//`define DI_CHAN2_LUMA_Y0 8'hf8 +//`define DI_CHAN2_CHROMA_X0 8'hf9 +//`define DI_CHAN2_CHROMA_Y0 8'hfa +//`define DI_CHAN2_RPT_LOOP 8'hfb +//`define DI_CHAN2_LUMA0_RPT_PAT 8'hb0 +//`define DI_CHAN2_CHROMA0_RPT_PAT 8'hb1 +//`define DI_CHAN2_DUMMY_PIXEL 8'hb2 +//`define DI_CHAN2_LUMA_FIFO_SIZE 8'hb3 +//`define DI_CHAN2_RANGE_MAP_Y 8'hb4 +//`define DI_CHAN2_RANGE_MAP_CB 8'hb5 +//`define DI_CHAN2_RANGE_MAP_CR 8'hb6 +//`define DI_CHAN2_GEN_REG2 8'hb7 +//`define DI_CHAN2_FMT_CTRL 8'hb8 +//`define DI_CHAN2_FMT_W 8'hb9 +// +// Closing file: vpu_mad_regs.h +// +// ----------------------------------------------- +// REG_BASE: MADD_VCBUS_BASE = 0x18 +// ----------------------------------------------- +// +// Reading file: di_dolby_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DOLBY_CORE1C_REG_START ((0x1800 << 2) + 0xff000000) +#define DOLBY_CORE1C_CLKGATE_CTRL ((0x18f2 << 2) + 0xff000000) +#define DOLBY_CORE1C_SWAP_CTRL0 ((0x18f3 << 2) + 0xff000000) +#define DOLBY_CORE1C_SWAP_CTRL1 ((0x18f4 << 2) + 0xff000000) +#define DOLBY_CORE1C_SWAP_CTRL2 ((0x18f5 << 2) + 0xff000000) +#define DOLBY_CORE1C_SWAP_CTRL3 ((0x18f6 << 2) + 0xff000000) +#define DOLBY_CORE1C_SWAP_CTRL4 ((0x18f7 << 2) + 0xff000000) +#define DOLBY_CORE1C_SWAP_CTRL5 ((0x18f8 << 2) + 0xff000000) +#define DOLBY_CORE1C_DMA_CTRL ((0x18f9 << 2) + 0xff000000) +#define DOLBY_CORE1C_DMA_STATUS ((0x18fa << 2) + 0xff000000) +#define DOLBY_CORE1C_STATUS0 ((0x18fb << 2) + 0xff000000) +#define DOLBY_CORE1C_STATUS1 ((0x18fc << 2) + 0xff000000) +#define DOLBY_CORE1C_STATUS2 ((0x18fd << 2) + 0xff000000) +#define DOLBY_CORE1C_STATUS3 ((0x18fe << 2) + 0xff000000) +#define DOLBY_CORE1C_DMA_PORT ((0x18ff << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: di_dolby_regs.h +// +//`include "di_inp_afbc_dec_regs.h" +//`include "di_mem_afbc_dec_regs.h" +//`include "fgrain_di_regs.h" +// ----------------------------------------------- +// REG_BASE: VPP2_VCBUS_BASE = 0x19 +// ----------------------------------------------- +//`include "vpp2_regs.h" +// +// Reading file: vregs_clk2.h +// +//=========================================================================== +// Video Interface Registers 0xa00 - 0xaff +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: VIU_VCBUS_BASE = 0x1a +// ----------------------------------------------- +#define VIU_ADDR_START ((0x1a00 << 2) + 0xff000000) +#define VIU_ADDR_END ((0x1aff << 2) + 0xff000000) +//`define TRACE_REG 8'ff +//------------------------------------------------------------------------------ +// VIU top-level registers +//------------------------------------------------------------------------------ +// Bit 0 RW, osd1_reset +// Bit 1 RW, osd2_reset +// Bit 2 RW, vd1_reset +// Bit 3 RW, vd1_fmt_reset +// Bit 4 RW, vd2_reset +// Bit 5 RW, vd2_fmt_reset +// Bit 6 RW, di_dsr1to2_reset +// Bit 7 RW, vpp_reset +// Bit 8 RW, di_if1_reset +// Bit 9 RW, di_if1_fmt_reset +// Bit 10 RW, di_inp_reset +// Bit 11 RW, di_inp_fmt_reset +// Bit 12 RW, di_mem_reset +// Bit 13 RW, di_mem_fmt_reset +// Bit 14 RW, di_nr_wr_mif_reset +// Bit 15 RW, dein_wr_mif_reset +// Bit 16 RW, di_chan2_mif_reset +// Bit 17 RW, di_mtn_wr_mif_reset +// Bit 18 RW, di_mtn_rd_mif_reset +// Bit 19 RW, di_mad_reset +// Bit 20 RW, vdin0_reset +// Bit 21 RW, vdin1_reset +// Bit 22 RW, nrin_mux_reset +// Bit 23 RW, vdin0_wr_reset +// Bit 24 RW, vdin1_wr_reset +// Bit 25 RW, reserved +// Bit 26 RW, d2d3_reset +// Bit 27 RW, di_cont_wr_mif_reset +// Bit 28 RW, di_cont_rd_mif_reset +#define VIU_SW_RESET ((0x1a01 << 2) + 0xff000000) +#define VIU_SW_RESET0 ((0x1a02 << 2) + 0xff000000) +// Bit 0 RW, software reset for mcvecrd_mif +// Bit 1 RW, software reset for mcinfowr_mif +// Bit 2 RW, software reset for mcinford_mif +#define VIU_SECURE_REG ((0x1a04 << 2) + 0xff000000) +// Bit 0 RW, dolby core1_tv secure w and r +// Bit 1 RW, dolby core2 secure w and r +// Bit 2 RW, dolby core3 secure w and r +// Bit 3 RW, for osd1 secure read +// Bit 4 RW, for osd2 secure read +#define DOLBY_INT_STAT ((0x1a05 << 2) + 0xff000000) +// todo +//bit 15:12 osdbld_gclk_ctrl 3:2 regclk ctrl 1:0 blending clk control +//bit 8 if true, vsync interrup is generate only field == 0 +//bit 7:0 fix_disable +#define VIU_MISC_CTRL0 ((0x1a06 << 2) + 0xff000000) +#define VIU_MISC_CTRL1 ((0x1a07 << 2) + 0xff000000) +// Bit 15:14 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[5:4] +// Bit 12 osd1_afbcd_axi_mux 0 : use the osd mif as input; 1 : use afbcd as input +// Bit 11:8 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[3:0] +// Bit 7:2 vd2_afbcd_gclk_ctrl vd2_afbcd clock gate control +// Bit 1 vpp_vd2_din_sel 0: vpp vd2 sel the mif input; 1: vpp vd2 sel the dos afbcd +// Bit 0 vd2_afbcd_out_sel 0: vd2_afbcd output to vpp; 1 : vd2_afbcd output to di inp +#define VIU_SECURE_DUMMY ((0x1a08 << 2) + 0xff000000) +#define VIU_SECURE_ST_RO ((0x1a09 << 2) + 0xff000000) +// Bit 31:30 vdin0 dout splitter, bit 0 turns on vdin0 to old path, bit 1 turns on vdin0 to d2d3_intf vdin0 input path +// Bit 29:28 vdin1 dout splitter, bit 0 turns on vdin1 to old path, bit 1 turns on vdin1 to d2d3_intf vdin1 input path +// Bit 27:26 NR write dout splitter, bit 0 turns on NR write to old path, bit 1 turns on NR WR to d2d3_intf NR WR input path +// Bit 23 if true, turn on clk_d2d3_reg (register clock) +// Bit 22 if true, turn on clk_d2d3 +// Bit 21 reg_v1_go_line +// Bit 20 reg_v1_go_field +// Bit 19 reg_v0_go_field +// Bit 18:16 v1_gofld_sel, 000: display go_field/go_line, 001: DI pre_frame_rst/go_line, 010: vdin0 go_field/go_line, +//011: vdin1 go_field/go_line, otherwise: force go_field by reg_v1_go_field(bit20), force go_line by reg_v1_go_line(bit21) +// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by +// reg_v0_go_field(bit19) +// Bit 12:6 hole_lines for d2d3 depth read interface +// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1 +// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol +// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output +// +// `define D2D3_INTF_CTRL0 8'h09 +#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000) +#define VD2_AFBCD1_MISC_CTRL ((0x1a0b << 2) + 0xff000000) +#define DOLBY_PATH_CTRL ((0x1a0c << 2) + 0xff000000) +#define WR_BACK_MISC_CTRL ((0x1a0d << 2) + 0xff000000) +#define OSD_PATH_MISC_CTRL ((0x1a0e << 2) + 0xff000000) +#define MALI_AFBCD_TOP_CTRL ((0x1a0f << 2) + 0xff000000) +#define VIU_DATA_SEC ((0x1a50 << 2) + 0xff000000) +#define VIU_FRM_CTRL ((0x1a51 << 2) + 0xff000000) +#define VIU_RDMIF_DEPTH ((0x1a52 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// OSD1 registers +//------------------------------------------------------------------------------ +// Bit 31 Reserved +// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics; +// 0=use gated clock for low power. +// Bit 29 R, test_rd_dsr +// Bit 28 R, osd_done +// Bit 27:24 R, osd_blk_mode +// Bit 23:22 R, osd_blk_ptr +// Bit 21 R, osd_enable +// +// Bit 20:12 RW, global_alpha +// Bit 11 RW, test_rd_en +// Bit 10: 9 Reserved for control signals +// Bit 8: 5 RW, ctrl_mtch_y +// Bit 4 RW, ctrl_422to444 +// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable; +// Bit 1 to enable block 1, and so on. +#define VIU_OSD1_CTRL_STAT ((0x1a10 << 2) + 0xff000000) +// Bit 31:26 Reserved +// Bit 25:16 R, fifo_count +// Bit 15 RW, osd_dpath_sel 0-osd1 mif 1-vpu mali afbcd +// Bit 14 RW, replaced_alpha_en +// Bit 13: 6 RW, replaced_alpha +// Bit 5: 4 RW, hold_fifo_lines[6:5] +// Bit 3 RW, rgb2yuv_full_range +// Bit 2 RW, alpha_9b_mode +// Bit 1 RW, reserved +// Bit 0 RW, color_expand_mode +#define VIU_OSD1_CTRL_STAT2 ((0x1a2d << 2) + 0xff000000) +// Bit 31: 9 Reserved +// Bit 8 RW, 0 = Write LUT, 1 = Read LUT +// Bit 7: 0 RW, lut_addr +#define VIU_OSD1_COLOR_ADDR ((0x1a11 << 2) + 0xff000000) +// Bit 31:24 RW, Y or R +// Bit 23:16 RW, Cb or G +// Bit 15: 8 RW, Cr or B +// Bit 7: 0 RW, Alpha +#define VIU_OSD1_COLOR ((0x1a12 << 2) + 0xff000000) +// Bit 31:24 RW, Y or R +// Bit 23:16 RW, Cb or G +// Bit 15: 8 RW, Cr or B +// Bit 7: 0 RW, Alpha +#define VIU_OSD1_TCOLOR_AG0 ((0x1a17 << 2) + 0xff000000) +#define VIU_OSD1_TCOLOR_AG1 ((0x1a18 << 2) + 0xff000000) +#define VIU_OSD1_TCOLOR_AG2 ((0x1a19 << 2) + 0xff000000) +#define VIU_OSD1_TCOLOR_AG3 ((0x1a1a << 2) + 0xff000000) +// Bit 31:30 Reserved +// Bit 29 RW, y_rev: 0=normal read, 1=reverse read in Y direction +// Bit 28 RW, x_rev: 0=normal read, 1=reverse read in X direction +// Bit 27:24 Reserved +// Bit 23:16 RW, tbl_addr +// Bit 15 RW, little_endian: 0=big endian, 1=little endian +// Bit 14 RW, rpt_y +// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous +// pixel; 11=Interpolate with the average value +// between previous and next pixel. +// Bit 11: 8 RW, osd_blk_mode +// Bit 7 RW, rgb_en +// Bit 6 RW, tc_alpha_en +// Bit 5: 2 RW, color_matrix +// Bit 1 RW, interlace_en +// Bit 0 RW, interlace_sel_odd +#define VIU_OSD1_BLK0_CFG_W0 ((0x1a1b << 2) + 0xff000000) +#define VIU_OSD1_BLK1_CFG_W0 ((0x1a1f << 2) + 0xff000000) +#define VIU_OSD1_BLK2_CFG_W0 ((0x1a23 << 2) + 0xff000000) +#define VIU_OSD1_BLK3_CFG_W0 ((0x1a27 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 RW, x_end +// Bit 15:13 Reserved +// Bit 12: 0 RW, x_start +#define VIU_OSD1_BLK0_CFG_W1 ((0x1a1c << 2) + 0xff000000) +#define VIU_OSD1_BLK1_CFG_W1 ((0x1a20 << 2) + 0xff000000) +#define VIU_OSD1_BLK2_CFG_W1 ((0x1a24 << 2) + 0xff000000) +#define VIU_OSD1_BLK3_CFG_W1 ((0x1a28 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 RW, y_end +// Bit 15:13 Reserved +// Bit 12: 0 RW, y_start +#define VIU_OSD1_BLK0_CFG_W2 ((0x1a1d << 2) + 0xff000000) +#define VIU_OSD1_BLK1_CFG_W2 ((0x1a21 << 2) + 0xff000000) +#define VIU_OSD1_BLK2_CFG_W2 ((0x1a25 << 2) + 0xff000000) +#define VIU_OSD1_BLK3_CFG_W2 ((0x1a29 << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, h_end +// Bit 15:12 Reserved +// Bit 11: 0 RW, h_start +#define VIU_OSD1_BLK0_CFG_W3 ((0x1a1e << 2) + 0xff000000) +#define VIU_OSD1_BLK1_CFG_W3 ((0x1a22 << 2) + 0xff000000) +#define VIU_OSD1_BLK2_CFG_W3 ((0x1a26 << 2) + 0xff000000) +#define VIU_OSD1_BLK3_CFG_W3 ((0x1a2a << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, v_end +// Bit 15:12 Reserved +// Bit 11: 0 RW, v_start +#define VIU_OSD1_BLK0_CFG_W4 ((0x1a13 << 2) + 0xff000000) +#define VIU_OSD1_BLK1_CFG_W4 ((0x1a14 << 2) + 0xff000000) +#define VIU_OSD1_BLK2_CFG_W4 ((0x1a15 << 2) + 0xff000000) +#define VIU_OSD1_BLK3_CFG_W4 ((0x1a16 << 2) + 0xff000000) +// Bit 31 RW, burst_len_sel[2] of [2:0] +// Bit 30 RW, byte_swap: In addition to endian control, further define +// whether to swap upper and lower byte within a 16-bit mem word. +// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]} +// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word +// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif +// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved +// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT +// Bit 19 R, fifo_overflow +// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8. +// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128. +// Bit 9: 5 RW, hold_fifo_lines[4:0] +// Bit 4 RW, clear_err: one pulse to clear fifo_overflow +// Bit 3 RW, fifo_sync_rst +// Bit 2: 1 RW, endian +// Bit 0 RW, urgent +#define VIU_OSD1_FIFO_CTRL_STAT ((0x1a2b << 2) + 0xff000000) +// Bit 31:24 R, Y or R +// Bit 23:16 R, Cb or G +// Bit 15: 8 R, Cr or B +// Bit 7: 0 R, Output Alpha[8:1] +#define VIU_OSD1_TEST_RDDATA ((0x1a2c << 2) + 0xff000000) +// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate. +// Bit 12: 0 RW, effective FIFO size when prot_en=1. +#define VIU_OSD1_PROT_CTRL ((0x1a2e << 2) + 0xff000000) +//Bit 7, highlight_en +//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix +//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing +//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing +//Bit 1 mat1 conversion matrix enable +//Bit 0 mat0 conversion matrix enable +#define VIU_OSD1_MATRIX_CTRL ((0x1a90 << 2) + 0xff000000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define VIU_OSD1_MATRIX_COEF00_01 ((0x1a91 << 2) + 0xff000000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define VIU_OSD1_MATRIX_COEF02_10 ((0x1a92 << 2) + 0xff000000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define VIU_OSD1_MATRIX_COEF11_12 ((0x1a93 << 2) + 0xff000000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define VIU_OSD1_MATRIX_COEF20_21 ((0x1a94 << 2) + 0xff000000) +//Bit 31:30 mat_clmod +//Bit 18:16 mat_convrs +//Bit 12:0 mat_coef42 +#define VIU_OSD1_MATRIX_COLMOD_COEF42 ((0x1a95 << 2) + 0xff000000) +//Bit 26:16 offset0 +//Bit 10:0 offset1 +#define VIU_OSD1_MATRIX_OFFSET0_1 ((0x1a96 << 2) + 0xff000000) +//Bit 10:0 offset2 +#define VIU_OSD1_MATRIX_OFFSET2 ((0x1a97 << 2) + 0xff000000) +//Bit 26:16 pre_offset0 +//Bit 10:0 pre_offset1 +#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 ((0x1a98 << 2) + 0xff000000) +//Bit 10:0 pre_offset2 +#define VIU_OSD1_MATRIX_PRE_OFFSET2 ((0x1a99 << 2) + 0xff000000) +//Read only +//Bit 29:20 component 0 +//Bit 19:10 component 1 +//Bit 9:0 component 2 +#define VIU_OSD1_MATRIX_PROBE_COLOR ((0x1a9a << 2) + 0xff000000) +//Bit 23:16 component 0 +//Bit 15:8 component 1 +//Bit 7:0 component 2 +#define VIU_OSD1_MATRIX_HL_COLOR ((0x1a9b << 2) + 0xff000000) +//28:16 probe x, postion +//12:0 probe y, position +#define VIU_OSD1_MATRIX_PROBE_POS ((0x1a9c << 2) + 0xff000000) +//Bit 28:16 coef22 +//Bit 12:0 coef30 +#define VIU_OSD1_MATRIX_COEF22_30 ((0x1a9d << 2) + 0xff000000) +//Bit 28:16 coef31 +//Bit 12:0 coef32 +#define VIU_OSD1_MATRIX_COEF31_32 ((0x1a9e << 2) + 0xff000000) +//Bit 28:16 coef40 +//Bit 12:0 coef41 +#define VIU_OSD1_MATRIX_COEF40_41 ((0x1a9f << 2) + 0xff000000) +//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3 +//Bit 17:6 for clock gating +//Bit 5:4 pscale_mode ch2 +//Bit 3:2 pscale_mode ch1 +//Bit 1:0 pscale_mode ch0 +#define VIU_OSD1_EOTF_CTL ((0x1ad4 << 2) + 0xff000000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define VIU_OSD1_EOTF_COEF00_01 ((0x1ad5 << 2) + 0xff000000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define VIU_OSD1_EOTF_COEF02_10 ((0x1ad6 << 2) + 0xff000000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define VIU_OSD1_EOTF_COEF11_12 ((0x1ad7 << 2) + 0xff000000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define VIU_OSD1_EOTF_COEF20_21 ((0x1ad8 << 2) + 0xff000000) +//Bit 28:16 coef22 +//Bit 2:0 coef_rs +#define VIU_OSD1_EOTF_COEF22_RS ((0x1ad9 << 2) + 0xff000000) +#define VIU_OSD1_EOTF_LUT_ADDR_PORT ((0x1ada << 2) + 0xff000000) +#define VIU_OSD1_EOTF_LUT_DATA_PORT ((0x1adb << 2) + 0xff000000) +//Bit 31:29 for OETF ch0~ch2 +//Bit 21:12 for clock gating +//Bit 11:8 for oetf_scl_ch2 +//Bit 7:4 for oetf_scl_ch1 +//Bit 3:0 for oetf_scl_ch0 +#define VIU_OSD1_OETF_CTL ((0x1adc << 2) + 0xff000000) +#define VIU_OSD1_OETF_LUT_ADDR_PORT ((0x1add << 2) + 0xff000000) +#define VIU_OSD1_OETF_LUT_DATA_PORT ((0x1ade << 2) + 0xff000000) +#define VIU_OSD1_OETF_3X3_OFST_0 ((0x1aa0 << 2) + 0xff000000) +#define VIU_OSD1_OETF_3X3_OFST_1 ((0x1aa1 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// OSD2 registers +//------------------------------------------------------------------------------ +// Bit 31 Reserved +// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics; +// 0=use gated clock for low power. +// Bit 29 R, test_rd_dsr +// Bit 28 R, osd_done +// Bit 27:24 R, osd_blk_mode +// Bit 23:22 R, osd_blk_ptr +// Bit 21 R, osd_enable +// +// Bit 20:12 RW, global_alpha +// Bit 11 RW, test_rd_en +// Bit 10 RW, hl2_en +// Bit 9 RW, hl1_en +// Bit 8: 5 RW, ctrl_mtch_y +// Bit 4 RW, ctrl_422to444 +// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable; +// Bit 1 to enable block 1, and so on. +#define VIU_OSD2_CTRL_STAT ((0x1a30 << 2) + 0xff000000) +// Bit 31:26 Reserved +// Bit 25:16 R, fifo_count +// Bit 15 Reserved +// Bit 14 RW, replaced_alpha_en +// Bit 13: 6 RW, replaced_alpha +// Bit 5: 4 RW, hold_fifo_lines[6:5] +// Bit 3 RW, rgb2yuv_full_range +// Bit 2 RW, alpha_9b_mode +// Bit 1 RW, reserved +// Bit 0 RW, color_expand_mode +#define VIU_OSD2_CTRL_STAT2 ((0x1a4d << 2) + 0xff000000) +// Bit 31: 9 Reserved +// Bit 8 RW, 0 = Write LUT, 1 = Read LUT +// Bit 7: 0 RW, lut_addr +#define VIU_OSD2_COLOR_ADDR ((0x1a31 << 2) + 0xff000000) +// Bit 31:24 RW, Y or R +// Bit 23:16 RW, Cb or G +// Bit 15: 8 RW, Cr or B +// Bit 7: 0 RW, Alpha +#define VIU_OSD2_COLOR ((0x1a32 << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, hl[1-2]_h/v_start +// Bit 15:12 Reserved +// Bit 11: 0 RW, hl[1-2]_h/v_end +#define VIU_OSD2_HL1_H_START_END ((0x1a33 << 2) + 0xff000000) +#define VIU_OSD2_HL1_V_START_END ((0x1a34 << 2) + 0xff000000) +#define VIU_OSD2_HL2_H_START_END ((0x1a35 << 2) + 0xff000000) +#define VIU_OSD2_HL2_V_START_END ((0x1a36 << 2) + 0xff000000) +// Bit 31:24 RW, Y or R +// Bit 23:16 RW, Cb or G +// Bit 15: 8 RW, Cr or B +// Bit 7: 0 RW, Alpha +#define VIU_OSD2_TCOLOR_AG0 ((0x1a37 << 2) + 0xff000000) +#define VIU_OSD2_TCOLOR_AG1 ((0x1a38 << 2) + 0xff000000) +#define VIU_OSD2_TCOLOR_AG2 ((0x1a39 << 2) + 0xff000000) +#define VIU_OSD2_TCOLOR_AG3 ((0x1a3a << 2) + 0xff000000) +// Bit 31:24 Reserved +// Bit 23:16 RW, tbl_addr +// Bit 15 RW, little_endian: 0=big endian, 1=little endian +// Bit 14 RW, rpt_y +// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous +// pixel; 11=Interpolate with the average value +// between previous and next pixel. +// Bit 11: 8 RW, osd_blk_mode +// Bit 7 RW, rgb_en +// Bit 6 RW, tc_alpha_en +// Bit 5: 2 RW, color_matrix +// Bit 1 RW, interlace_en +// Bit 0 RW, interlace_sel_odd +#define VIU_OSD2_BLK0_CFG_W0 ((0x1a3b << 2) + 0xff000000) +#define VIU_OSD2_BLK1_CFG_W0 ((0x1a3f << 2) + 0xff000000) +#define VIU_OSD2_BLK2_CFG_W0 ((0x1a43 << 2) + 0xff000000) +#define VIU_OSD2_BLK3_CFG_W0 ((0x1a47 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 RW, x_end +// Bit 15:13 Reserved +// Bit 12: 0 RW, x_start +#define VIU_OSD2_BLK0_CFG_W1 ((0x1a3c << 2) + 0xff000000) +#define VIU_OSD2_BLK1_CFG_W1 ((0x1a40 << 2) + 0xff000000) +#define VIU_OSD2_BLK2_CFG_W1 ((0x1a44 << 2) + 0xff000000) +#define VIU_OSD2_BLK3_CFG_W1 ((0x1a48 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 RW, y_end +// Bit 15:13 Reserved +// Bit 12: 0 RW, y_start +#define VIU_OSD2_BLK0_CFG_W2 ((0x1a3d << 2) + 0xff000000) +#define VIU_OSD2_BLK1_CFG_W2 ((0x1a41 << 2) + 0xff000000) +#define VIU_OSD2_BLK2_CFG_W2 ((0x1a45 << 2) + 0xff000000) +#define VIU_OSD2_BLK3_CFG_W2 ((0x1a49 << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, h_end +// Bit 15:12 Reserved +// Bit 11: 0 RW, h_start +#define VIU_OSD2_BLK0_CFG_W3 ((0x1a3e << 2) + 0xff000000) +#define VIU_OSD2_BLK1_CFG_W3 ((0x1a42 << 2) + 0xff000000) +#define VIU_OSD2_BLK2_CFG_W3 ((0x1a46 << 2) + 0xff000000) +#define VIU_OSD2_BLK3_CFG_W3 ((0x1a4a << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, v_end +// Bit 15:12 Reserved +// Bit 11: 0 RW, v_start +#define VIU_OSD2_BLK0_CFG_W4 ((0x1a64 << 2) + 0xff000000) +#define VIU_OSD2_BLK1_CFG_W4 ((0x1a65 << 2) + 0xff000000) +#define VIU_OSD2_BLK2_CFG_W4 ((0x1a66 << 2) + 0xff000000) +#define VIU_OSD2_BLK3_CFG_W4 ((0x1a67 << 2) + 0xff000000) +// Bit 31 RW, burst_len_sel[2] of [2:0] +// Bit 30 RW, byte_swap: In addition to endian control, further define +// whether to swap upper and lower byte within a 16-bit mem word. +// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]} +// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word +// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif +// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved +// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT +// Bit 19 R, fifo_overflow +// +// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8. +// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128. +// Bit 9: 5 RW, hold_fifo_lines[4:0] +// Bit 4 RW, clear_err: one pulse to clear fifo_overflow +// Bit 3 RW, fifo_sync_rst +// Bit 2: 1 RW, endian +// Bit 0 RW, urgent +#define VIU_OSD2_FIFO_CTRL_STAT ((0x1a4b << 2) + 0xff000000) +// Bit 31:24 R, Y or R +// Bit 23:16 R, Cb or G +// Bit 15: 8 R, Cr or B +// Bit 7: 0 R, Output Alpha[8:1] +#define VIU_OSD2_TEST_RDDATA ((0x1a4c << 2) + 0xff000000) +// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate. +// Bit 12: 0 RW, effective FIFO size when prot_en=1. +#define VIU_OSD2_PROT_CTRL ((0x1a4e << 2) + 0xff000000) +// //todo add comment +#define LDIM_STTS_GCLK_CTRL0 ((0x1ac0 << 2) + 0xff000000) +#define LDIM_STTS_CTRL0 ((0x1ac1 << 2) + 0xff000000) +#define LDIM_STTS_WIDTHM1_HEIGHTM1 ((0x1ac2 << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_COEF00_01 ((0x1ac3 << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_COEF02_10 ((0x1ac4 << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_COEF11_12 ((0x1ac5 << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_COEF20_21 ((0x1ac6 << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_COEF22 ((0x1ac7 << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_OFFSET0_1 ((0x1ac8 << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_OFFSET2 ((0x1ac9 << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_PRE_OFFSET0_1 ((0x1aca << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_PRE_OFFSET2 ((0x1acb << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_HL_COLOR ((0x1acc << 2) + 0xff000000) +#define LDIM_STTS_MATRIX_PROBE_POS ((0x1acd << 2) + 0xff000000) +// +// //read only +#define LDIM_STTS_MATRIX_PROBE_COLOR ((0x1ace << 2) + 0xff000000) +// +// //Bit 31, local dimming statistic enable +// //Bit 29, 1: output region histogram 16bit 0:output region histogram 20bit +// //Bit 28, eol enable +// //Bit 27:25, vertical line overlap number for max finding +// //Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix +// //Bit 20, 1,2,1 low pass filter enable before max/hist statistic +// //Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION +// //Bit 15:14, 1: region read index auto increase per block read finished to VDIN_LDIM_STTS_HIST_READ_REGION +// // 2: region read index auto increase per read finished to VDIN_LDIM_STTS_HIST_READ_REGION +// // 0/3: disable read index self increase +// //Bit 13:8, region read sub index, which mux the hist & max-finding result to cbus port, refer to LDIM_STTS_HIST_READ_REGION +// //Bit 6:0, region read index +#define LDIM_STTS_HIST_REGION_IDX ((0x1ad0 << 2) + 0xff000000) +//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89 +// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89 +// //hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart +// //hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend +// //vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend +// //hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend +// //vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend +// //hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend +// //vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend +// //hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend +// //vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend +// //hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend +// //vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend +#define LDIM_STTS_HIST_SET_REGION ((0x1ad1 << 2) + 0xff000000) +// +// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data. +// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0. +// //output sequence as rd_sub_idx from 0~47: {max_comp2, comp0_hist0}, {max_comp1, comp0_hist1}, {max_comp0, comp0_hist2}, +// // comp0_hist3 ... comp2_hist16 +// //if LDIM_STTS_HIST_REGION_IDX[29] == 1, that is output hist with 16bit data. +// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0. +// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2 +// // comp0_hist3 ... comp2_hist16 +// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data. +// //if LDIM_STTS_HIST_REGION_IDX[21] == 1, that is output 32hist bins in comp 0. +// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2 +// // comp0_hist3 ...comp0_hist31 ... comp1_hist16 +// +#define LDIM_STTS_HIST_READ_REGION ((0x1ad2 << 2) + 0xff000000) +#define LDIM_STTS_HIST_START_RD_REGION ((0x1ad3 << 2) + 0xff000000) +#define LDIM_STTS_PCTL_TH ((0x1aaf << 2) + 0xff000000) +// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di if1 chroma path +// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di if1 luma path +// `define DI_IF1_URGENT_CTRL 8'ha3 +// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path +// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path +// `define DI_INP_URGENT_CTRL 8'ha4 +// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path +// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path +// `define DI_MEM_URGENT_CTRL 8'ha5 +// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path +// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path +// `define DI_CHAN2_URGENT_CTRL 8'ha6 +#define OSD_BLENDO_H_START_END ((0x1aa9 << 2) + 0xff000000) +//OSD blending output horizontal start and end +//Bit 28:16 start +//Bit 12:0 end +#define OSD_BLENDO_V_START_END ((0x1aaa << 2) + 0xff000000) +//OSD blending output vertical start and end +//Bit 28:16 start +//Bit 12:0 end +#define OSD_BLEND_GEN_CTRL0 ((0x1aab << 2) + 0xff000000) +//Bit 31:23 const_out_alpha +//Bit 22:14 const_op_alpha +//Bit 13 if true, OSD2 foreground otherwise OSD1 foreground +//Bit 12 OSD BLENDing enable +//Bit 9:8 alpha_op_sel 00: output alpha use osd1_alpha, 01: use osd2_alpha, else use const_out_alpha +//Bit 5:4 color_op_sel 00: use osd1_alpha, 01: use osd2_alpha, else use const_op_alpha +//Bit 1 OSD2 enable +//Bit 0 OSD1 enable +#define OSD_BLEND_GEN_CTRL1 ((0x1aac << 2) + 0xff000000) +//Bit 31 osd1_alpha_premult, if true, osd1 alpha is premultipiled +//Bit 30 osd2_alpha_premult, if true, osd2 alpha is premultipiled +//Bit 23:16 osd blending hold lines +//Bit 13:0 osd blending h_size +#define OSD_BLEND_DUMMY_DATA ((0x1aad << 2) + 0xff000000) +//Bit 29:20 Y/R +//Bit 19:10 CB/G +//Bit 9:0 Cr/B +#define OSD_BLEND_CURRENT_XY ((0x1aae << 2) + 0xff000000) +//Bit 28:16 current_x +//Bit 12:0 current_y +//Bit 7, highlight_en +//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix +//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing +//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing +//Bit 1 mat1 conversion matrix enable +//Bit 0 mat0 conversion matrix enable +#define VIU_OSD2_MATRIX_CTRL ((0x1ab0 << 2) + 0xff000000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define VIU_OSD2_MATRIX_COEF00_01 ((0x1ab1 << 2) + 0xff000000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define VIU_OSD2_MATRIX_COEF02_10 ((0x1ab2 << 2) + 0xff000000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define VIU_OSD2_MATRIX_COEF11_12 ((0x1ab3 << 2) + 0xff000000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define VIU_OSD2_MATRIX_COEF20_21 ((0x1ab4 << 2) + 0xff000000) +#define VIU_OSD2_MATRIX_COEF22 ((0x1ab5 << 2) + 0xff000000) +//Bit 26:16 offset0 +//Bit 10:0 offset1 +#define VIU_OSD2_MATRIX_OFFSET0_1 ((0x1ab6 << 2) + 0xff000000) +//Bit 10:0 offset2 +#define VIU_OSD2_MATRIX_OFFSET2 ((0x1ab7 << 2) + 0xff000000) +//Bit 26:16 pre_offset0 +//Bit 10:0 pre_offset1 +#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 ((0x1ab8 << 2) + 0xff000000) +//Bit 10:0 pre_offset2 +#define VIU_OSD2_MATRIX_PRE_OFFSET2 ((0x1ab9 << 2) + 0xff000000) +//Read only +//Bit 29:20 component 0 +//Bit 19:10 component 1 +//Bit 9:0 component 2 +#define VIU_OSD2_MATRIX_PROBE_COLOR ((0x1aba << 2) + 0xff000000) +//Bit 23:16 component 0 +//Bit 15:8 component 1 +//Bit 7:0 component 2 +#define VIU_OSD2_MATRIX_HL_COLOR ((0x1abb << 2) + 0xff000000) +//28:16 probe x, postion +//12:0 probe y, position +#define VIU_OSD2_MATRIX_PROBE_POS ((0x1abc << 2) + 0xff000000) +////add for OSD1/2 mali_unpack +#define VIU_OSD1_MALI_UNPACK_CTRL ((0x1a2f << 2) + 0xff000000) +//`define VIU_OSD1_MALI_UNPACK_CTRL 8'h4f //todo +//`define VIU_OSD1_MALI_UNPACK_CTRL 8'haf //todo +#define VIU_OSD2_MALI_UNPACK_CTRL ((0x1abd << 2) + 0xff000000) +//`define VIU_OSD2_MATRIX_HL_COLOR 8'hbe +//`define VIU_OSD2_MATRIX_PROBE_POS 8'hbf +//can use 8'hdf 8'hcf +#define VIU_OSD1_DIMM_CTRL ((0x1adf << 2) + 0xff000000) +#define VIU_OSD2_DIMM_CTRL ((0x1acf << 2) + 0xff000000) +#define VIU_GCLK_CTRL ((0x1a4f << 2) + 0xff000000) +//the segment of afbc dec is 8'he0-8'hfe +//`define AFBC_DEC_OFFSET 8'he0 +// +// Reading file: afbc_dec_regs.h +// +// synopsys translate_off +// synopsys translate_on +////===============================//// +//// reg +////===============================//// +#define AFBC_ENABLE ((0x1ae0 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0 +//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size +//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable +//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb +//Bit 19, reg_dos_uncomp_mode unsigned , default = 0 +//Bit 18:16, soft_rst unsigned , default = 4 +//Bit 15:14, reserved +//Bit 13:12, ddr_blk_size unsigned , default = 1 +//Bit 11:9, cmd_blk_size unsigend , default = 3 +//Bit 8, dec_enable unsigned , default = 0 +//Bit 7:2, reserved +//Bit 1, head_len_sel unsigned , default = 1 +//Bit 0, dec_frm_start unsigned , default = 0 +#define AFBC_MODE ((0x1ae1 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size; +//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size +//Bit 27:26, rev_mode uns, default = 0 , reverse mode +//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent +//Bit 23, reserved +//Bit 22:16, hold_line_num uns, default = 4 , +//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4 +//Bit 13:8, compbits_yuv uns, default = 0 , +// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +#define AFBC_SIZE_IN ((0x1ae2 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel +#define AFBC_DEC_DEF_COLOR ((0x1ae3 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value +//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value +//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value +#define AFBC_CONV_CTRL ((0x1ae4 << 2) + 0xff000000) +//Bit 31:14, reserved +//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420 +//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n +#define AFBC_LBUF_DEPTH ((0x1ae5 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel +//Bit 15:12, reserved +//Bit 11:0, mif_lbuf_depth uns, default = 128; +#define AFBC_HEAD_BADDR ((0x1ae6 << 2) + 0xff000000) +//Bit 31:0, mif_info_baddr uns, default = 32'h0; +#define AFBC_BODY_BADDR ((0x1ae7 << 2) + 0xff000000) +//Bit 31:0, mif_data_baddr uns, default = 32'h00010000; +#define AFBC_SIZE_OUT ((0x1ae8 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel +#define AFBC_OUT_YSCOPE ((0x1ae9 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel +//Bit 15:13, reserved +//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel +#define AFBC_STAT ((0x1aea << 2) + 0xff000000) +//Bit 31:0, ro_dbg_top_info uns, +#define AFBC_VD_CFMT_CTRL ((0x1aeb << 2) + 0xff000000) +//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock +//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit +//Bit 29 reserved +//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation +//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase +//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable +//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 +//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable +//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always +// repeat data, no interpolation +//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line +//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable +//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable +//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning +//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase +//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4) +//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable +#define AFBC_VD_CFMT_W ((0x1aec << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width +//Bit 15:13 reserved +//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width +#define AFBC_MIF_HOR_SCOPE ((0x1aed << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor +//Bit 15:10, reserved +//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor +#define AFBC_MIF_VER_SCOPE ((0x1aee << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver +//Bit 15:12, reserved +//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver +#define AFBC_PIXEL_HOR_SCOPE ((0x1aef << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel +//Bit 15:13, reserved +//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel +#define AFBC_PIXEL_VER_SCOPE ((0x1af0 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel +//Bit 15:13, reserved +//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel +#define AFBC_VD_CFMT_H ((0x1af1 << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height +#define AFBCDEC_IQUANT_ENABLE ((0x1af2 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11 reg_quant_expand_en_1 //unsigned, RW, enable for quantization value expansion +//Bit 10 reg_quant_expand_en_0 //unsigned, RW, enable for quantization value expansion +//Bit 9: 8 reg_bcleav_ofst //signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1; +//Bit 7: 5 reserved +//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy +//Bit 3: 1 reserved +//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy +#define AFBCDEC_IQUANT_LUT_1 ((0x1af3 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCDEC_IQUANT_LUT_2 ((0x1af4 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCDEC_IQUANT_LUT_3 ((0x1af5 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCDEC_IQUANT_LUT_4 ((0x1af6 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: afbc_dec_regs.h +// +// +// Closing file: vregs_clk2.h +// +// +// Reading file: venc_regs.h +// +//=========================================================================== +// Video Interface Registers 0xa00 - 0xbff +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: VENC_VCBUS_BASE = 0x1b +// ----------------------------------------------- +// bit 15:8 -- vfifo2vd_vd_sel +// bit 0 -- vfifo2vd_en +#define ENCP_VFIFO2VD_CTL ((0x1b58 << 2) + 0xff000000) +// bit 12:0 -- vfifo2vd_pixel_start +#define ENCP_VFIFO2VD_PIXEL_START ((0x1b59 << 2) + 0xff000000) +// bit 12:00 -- vfifo2vd_pixel_end +#define ENCP_VFIFO2VD_PIXEL_END ((0x1b5a << 2) + 0xff000000) +// bit 10:0 -- vfifo2vd_line_top_start +#define ENCP_VFIFO2VD_LINE_TOP_START ((0x1b5b << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_top_end +#define ENCP_VFIFO2VD_LINE_TOP_END ((0x1b5c << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_bot_start +#define ENCP_VFIFO2VD_LINE_BOT_START ((0x1b5d << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_bot_end +#define ENCP_VFIFO2VD_LINE_BOT_END ((0x1b5e << 2) + 0xff000000) +// Route the hsync and vsync signals round the chip. There are three +// sources and users of these signals: VIU, internal video encoder, and +// the pins on the chip. Some muxing is still being done in the VIU. It +// was not moved to the venc module so that the same exact VIU code could +// be used both in Twister and Twister2000. +// Bit 2: venc_sync_source (1=>pins, 0=>viu) +// Bit 1: viu_sync_source (1=>pins, 0=>venc) +// Bit 0: vpins_sync_source (1=>venc, 0=>viu) +#define VENC_SYNC_ROUTE ((0x1b60 << 2) + 0xff000000) + // encoder address space is assigned + // to the video encoder interface status + // register +#define VENC_VIDEO_EXSRC ((0x1b61 << 2) + 0xff000000) +#define VENC_DVI_SETTING ((0x1b62 << 2) + 0xff000000) +#define VENC_C656_CTRL ((0x1b63 << 2) + 0xff000000) +#define VENC_UPSAMPLE_CTRL0 ((0x1b64 << 2) + 0xff000000) +#define VENC_UPSAMPLE_CTRL1 ((0x1b65 << 2) + 0xff000000) +#define VENC_UPSAMPLE_CTRL2 ((0x1b66 << 2) + 0xff000000) +// Invert control for tcon output +// bit[15:14] -- vsync, hsync, +// bit[13:0] -- oev3, oev2, cpv2, cph3, cph2, cph1, oeh, vcom, stv2, stv1, cpv1, oev1, sth1, sth2 +#define TCON_INVERT_CTL ((0x1b67 << 2) + 0xff000000) +#define VENC_VIDEO_PROG_MODE ((0x1b68 << 2) + 0xff000000) +//---- Venc pixel/line info +#define VENC_ENCI_LINE ((0x1b69 << 2) + 0xff000000) +#define VENC_ENCI_PIXEL ((0x1b6a << 2) + 0xff000000) +#define VENC_ENCP_LINE ((0x1b6b << 2) + 0xff000000) +#define VENC_ENCP_PIXEL ((0x1b6c << 2) + 0xff000000) +//---- Status +#define VENC_STATA ((0x1b6d << 2) + 0xff000000) +//---- Interrupt setting +#define VENC_INTCTRL ((0x1b6e << 2) + 0xff000000) +#define VENC_INTFLAG ((0x1b6f << 2) + 0xff000000) +//--------- Video test configuration +#define VENC_VIDEO_TST_EN ((0x1b70 << 2) + 0xff000000) +#define VENC_VIDEO_TST_MDSEL ((0x1b71 << 2) + 0xff000000) +#define VENC_VIDEO_TST_Y ((0x1b72 << 2) + 0xff000000) +#define VENC_VIDEO_TST_CB ((0x1b73 << 2) + 0xff000000) +#define VENC_VIDEO_TST_CR ((0x1b74 << 2) + 0xff000000) +#define VENC_VIDEO_TST_CLRBAR_STRT ((0x1b75 << 2) + 0xff000000) +#define VENC_VIDEO_TST_CLRBAR_WIDTH ((0x1b76 << 2) + 0xff000000) +#define VENC_VIDEO_TST_VDCNT_STSET ((0x1b77 << 2) + 0xff000000) +//----- Video dac setting +#define VENC_VDAC_DACSEL0 ((0x1b78 << 2) + 0xff000000) +#define VENC_VDAC_DACSEL1 ((0x1b79 << 2) + 0xff000000) +#define VENC_VDAC_DACSEL2 ((0x1b7a << 2) + 0xff000000) +#define VENC_VDAC_DACSEL3 ((0x1b7b << 2) + 0xff000000) +#define VENC_VDAC_DACSEL4 ((0x1b7c << 2) + 0xff000000) +#define VENC_VDAC_DACSEL5 ((0x1b7d << 2) + 0xff000000) +#define VENC_VDAC_SETTING ((0x1b7e << 2) + 0xff000000) +#define VENC_VDAC_TST_VAL ((0x1b7f << 2) + 0xff000000) +#define VENC_VDAC_DAC0_GAINCTRL ((0x1bf0 << 2) + 0xff000000) +#define VENC_VDAC_DAC0_OFFSET ((0x1bf1 << 2) + 0xff000000) +#define VENC_VDAC_DAC1_GAINCTRL ((0x1bf2 << 2) + 0xff000000) +#define VENC_VDAC_DAC1_OFFSET ((0x1bf3 << 2) + 0xff000000) +#define VENC_VDAC_DAC2_GAINCTRL ((0x1bf4 << 2) + 0xff000000) +#define VENC_VDAC_DAC2_OFFSET ((0x1bf5 << 2) + 0xff000000) +#define VENC_VDAC_DAC3_GAINCTRL ((0x1bf6 << 2) + 0xff000000) +#define VENC_VDAC_DAC3_OFFSET ((0x1bf7 << 2) + 0xff000000) +#define VENC_VDAC_DAC4_GAINCTRL ((0x1bf8 << 2) + 0xff000000) +#define VENC_VDAC_DAC4_OFFSET ((0x1bf9 << 2) + 0xff000000) +#define VENC_VDAC_DAC5_GAINCTRL ((0x1bfa << 2) + 0xff000000) +#define VENC_VDAC_DAC5_OFFSET ((0x1bfb << 2) + 0xff000000) +#define VENC_VDAC_FIFO_CTRL ((0x1bfc << 2) + 0xff000000) +#define ENCL_TCON_INVERT_CTL ((0x1bfd << 2) + 0xff000000) +// +// Closing file: venc_regs.h +// +// +// Reading file: enc480p_regs.h +// +// synopsys translate_off +// synopsys translate_on +//=========================================================================== +// Video Encoder 480p Registers 0xb80 - 0xbef +//=========================================================================== +//-------- Video basic setting +#define ENCP_VIDEO_EN ((0x1b80 << 2) + 0xff000000) +#define ENCP_VIDEO_SYNC_MODE ((0x1b81 << 2) + 0xff000000) +#define ENCP_MACV_EN ((0x1b82 << 2) + 0xff000000) +#define ENCP_VIDEO_Y_SCL ((0x1b83 << 2) + 0xff000000) +#define ENCP_VIDEO_PB_SCL ((0x1b84 << 2) + 0xff000000) +#define ENCP_VIDEO_PR_SCL ((0x1b85 << 2) + 0xff000000) +#define ENCP_VIDEO_SYNC_SCL ((0x1b86 << 2) + 0xff000000) +#define ENCP_VIDEO_MACV_SCL ((0x1b87 << 2) + 0xff000000) +#define ENCP_VIDEO_Y_OFFST ((0x1b88 << 2) + 0xff000000) +#define ENCP_VIDEO_PB_OFFST ((0x1b89 << 2) + 0xff000000) +#define ENCP_VIDEO_PR_OFFST ((0x1b8a << 2) + 0xff000000) +#define ENCP_VIDEO_SYNC_OFFST ((0x1b8b << 2) + 0xff000000) +#define ENCP_VIDEO_MACV_OFFST ((0x1b8c << 2) + 0xff000000) +//----- Video mode +#define ENCP_VIDEO_MODE ((0x1b8d << 2) + 0xff000000) +#define ENCP_VIDEO_MODE_ADV ((0x1b8e << 2) + 0xff000000) +//--------------- Debug pins +#define ENCP_DBG_PX_RST ((0x1b90 << 2) + 0xff000000) +#define ENCP_DBG_LN_RST ((0x1b91 << 2) + 0xff000000) +#define ENCP_DBG_PX_INT ((0x1b92 << 2) + 0xff000000) +#define ENCP_DBG_LN_INT ((0x1b93 << 2) + 0xff000000) +//----------- Video Advanced setting +#define ENCP_VIDEO_YFP1_HTIME ((0x1b94 << 2) + 0xff000000) +#define ENCP_VIDEO_YFP2_HTIME ((0x1b95 << 2) + 0xff000000) +#define ENCP_VIDEO_YC_DLY ((0x1b96 << 2) + 0xff000000) +#define ENCP_VIDEO_MAX_PXCNT ((0x1b97 << 2) + 0xff000000) +#define ENCP_VIDEO_HSPULS_BEGIN ((0x1b98 << 2) + 0xff000000) +#define ENCP_VIDEO_HSPULS_END ((0x1b99 << 2) + 0xff000000) +#define ENCP_VIDEO_HSPULS_SWITCH ((0x1b9a << 2) + 0xff000000) +#define ENCP_VIDEO_VSPULS_BEGIN ((0x1b9b << 2) + 0xff000000) +#define ENCP_VIDEO_VSPULS_END ((0x1b9c << 2) + 0xff000000) +#define ENCP_VIDEO_VSPULS_BLINE ((0x1b9d << 2) + 0xff000000) +#define ENCP_VIDEO_VSPULS_ELINE ((0x1b9e << 2) + 0xff000000) +#define ENCP_VIDEO_EQPULS_BEGIN ((0x1b9f << 2) + 0xff000000) +#define ENCP_VIDEO_EQPULS_END ((0x1ba0 << 2) + 0xff000000) +#define ENCP_VIDEO_EQPULS_BLINE ((0x1ba1 << 2) + 0xff000000) +#define ENCP_VIDEO_EQPULS_ELINE ((0x1ba2 << 2) + 0xff000000) +#define ENCP_VIDEO_HAVON_END ((0x1ba3 << 2) + 0xff000000) +#define ENCP_VIDEO_HAVON_BEGIN ((0x1ba4 << 2) + 0xff000000) +#define ENCP_VIDEO_VAVON_ELINE ((0x1baf << 2) + 0xff000000) +#define ENCP_VIDEO_VAVON_BLINE ((0x1ba6 << 2) + 0xff000000) +#define ENCP_VIDEO_HSO_BEGIN ((0x1ba7 << 2) + 0xff000000) +#define ENCP_VIDEO_HSO_END ((0x1ba8 << 2) + 0xff000000) +#define ENCP_VIDEO_VSO_BEGIN ((0x1ba9 << 2) + 0xff000000) +#define ENCP_VIDEO_VSO_END ((0x1baa << 2) + 0xff000000) +#define ENCP_VIDEO_VSO_BLINE ((0x1bab << 2) + 0xff000000) +#define ENCP_VIDEO_VSO_ELINE ((0x1bac << 2) + 0xff000000) +#define ENCP_VIDEO_SYNC_WAVE_CURVE ((0x1bad << 2) + 0xff000000) +#define ENCP_VIDEO_MAX_LNCNT ((0x1bae << 2) + 0xff000000) +#define ENCP_VIDEO_SY_VAL ((0x1bb0 << 2) + 0xff000000) +#define ENCP_VIDEO_SY2_VAL ((0x1bb1 << 2) + 0xff000000) +#define ENCP_VIDEO_BLANKY_VAL ((0x1bb2 << 2) + 0xff000000) +#define ENCP_VIDEO_BLANKPB_VAL ((0x1bb3 << 2) + 0xff000000) +#define ENCP_VIDEO_BLANKPR_VAL ((0x1bb4 << 2) + 0xff000000) +#define ENCP_VIDEO_HOFFST ((0x1bb5 << 2) + 0xff000000) +#define ENCP_VIDEO_VOFFST ((0x1bb6 << 2) + 0xff000000) +#define ENCP_VIDEO_RGB_CTRL ((0x1bb7 << 2) + 0xff000000) +#define ENCP_VIDEO_FILT_CTRL ((0x1bb8 << 2) + 0xff000000) +#define ENCP_VIDEO_OFLD_VPEQ_OFST ((0x1bb9 << 2) + 0xff000000) +#define ENCP_VIDEO_OFLD_VOAV_OFST ((0x1bba << 2) + 0xff000000) +#define ENCP_VIDEO_MATRIX_CB ((0x1bbb << 2) + 0xff000000) +#define ENCP_VIDEO_MATRIX_CR ((0x1bbc << 2) + 0xff000000) +#define ENCP_VIDEO_RGBIN_CTRL ((0x1bbd << 2) + 0xff000000) +//------------------Macrovision advanced setting +#define ENCP_MACV_BLANKY_VAL ((0x1bc0 << 2) + 0xff000000) +#define ENCP_MACV_MAXY_VAL ((0x1bc1 << 2) + 0xff000000) +#define ENCP_MACV_1ST_PSSYNC_STRT ((0x1bc2 << 2) + 0xff000000) +#define ENCP_MACV_PSSYNC_STRT ((0x1bc3 << 2) + 0xff000000) +#define ENCP_MACV_AGC_STRT ((0x1bc4 << 2) + 0xff000000) +#define ENCP_MACV_AGC_END ((0x1bc5 << 2) + 0xff000000) +#define ENCP_MACV_WAVE_END ((0x1bc6 << 2) + 0xff000000) +#define ENCP_MACV_STRTLINE ((0x1bc7 << 2) + 0xff000000) +#define ENCP_MACV_ENDLINE ((0x1bc8 << 2) + 0xff000000) +#define ENCP_MACV_TS_CNT_MAX_L ((0x1bc9 << 2) + 0xff000000) +#define ENCP_MACV_TS_CNT_MAX_H ((0x1bca << 2) + 0xff000000) +#define ENCP_MACV_TIME_DOWN ((0x1bcb << 2) + 0xff000000) +#define ENCP_MACV_TIME_LO ((0x1bcc << 2) + 0xff000000) +#define ENCP_MACV_TIME_UP ((0x1bcd << 2) + 0xff000000) +#define ENCP_MACV_TIME_RST ((0x1bce << 2) + 0xff000000) +//---------------- VBI control ------------------- +#define ENCP_VBI_CTRL ((0x1bd0 << 2) + 0xff000000) +#define ENCP_VBI_SETTING ((0x1bd1 << 2) + 0xff000000) +#define ENCP_VBI_BEGIN ((0x1bd2 << 2) + 0xff000000) +#define ENCP_VBI_WIDTH ((0x1bd3 << 2) + 0xff000000) +#define ENCP_VBI_HVAL ((0x1bd4 << 2) + 0xff000000) +#define ENCP_VBI_DATA0 ((0x1bd5 << 2) + 0xff000000) +#define ENCP_VBI_DATA1 ((0x1bd6 << 2) + 0xff000000) +//----------------C656 OUT Control------------- Grant +#define C656_HS_ST ((0x1be0 << 2) + 0xff000000) +#define C656_HS_ED ((0x1be1 << 2) + 0xff000000) +#define C656_VS_LNST_E ((0x1be2 << 2) + 0xff000000) +#define C656_VS_LNST_O ((0x1be3 << 2) + 0xff000000) +#define C656_VS_LNED_E ((0x1be4 << 2) + 0xff000000) +#define C656_VS_LNED_O ((0x1be5 << 2) + 0xff000000) +#define C656_FS_LNST ((0x1be6 << 2) + 0xff000000) +#define C656_FS_LNED ((0x1be7 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: enc480p_regs.h +// +// +// Reading file: enci_regs.h +// +//=========================================================================== +// Video Interface Registers 0xb00 - 0xb57 +//=========================================================================== +#define ENCI_VIDEO_MODE ((0x1b00 << 2) + 0xff000000) +#define ENCI_VIDEO_MODE_ADV ((0x1b01 << 2) + 0xff000000) +#define ENCI_VIDEO_FSC_ADJ ((0x1b02 << 2) + 0xff000000) +#define ENCI_VIDEO_BRIGHT ((0x1b03 << 2) + 0xff000000) +#define ENCI_VIDEO_CONT ((0x1b04 << 2) + 0xff000000) +#define ENCI_VIDEO_SAT ((0x1b05 << 2) + 0xff000000) +#define ENCI_VIDEO_HUE ((0x1b06 << 2) + 0xff000000) +#define ENCI_VIDEO_SCH ((0x1b07 << 2) + 0xff000000) +#define ENCI_SYNC_MODE ((0x1b08 << 2) + 0xff000000) +#define ENCI_SYNC_CTRL ((0x1b09 << 2) + 0xff000000) +#define ENCI_SYNC_HSO_BEGIN ((0x1b0a << 2) + 0xff000000) +#define ENCI_SYNC_HSO_END ((0x1b0b << 2) + 0xff000000) +#define ENCI_SYNC_VSO_EVN ((0x1b0c << 2) + 0xff000000) +#define ENCI_SYNC_VSO_ODD ((0x1b0d << 2) + 0xff000000) +#define ENCI_SYNC_VSO_EVNLN ((0x1b0e << 2) + 0xff000000) +#define ENCI_SYNC_VSO_ODDLN ((0x1b0f << 2) + 0xff000000) +#define ENCI_SYNC_HOFFST ((0x1b10 << 2) + 0xff000000) +#define ENCI_SYNC_VOFFST ((0x1b11 << 2) + 0xff000000) +#define ENCI_SYNC_ADJ ((0x1b12 << 2) + 0xff000000) +#define ENCI_RGB_SETTING ((0x1b13 << 2) + 0xff000000) +//`define ENCI_CMPN_MATRIX_CB 8'h14 +//`define ENCI_CMPN_MATRIX_CR 8'h15 +#define ENCI_DE_H_BEGIN ((0x1b16 << 2) + 0xff000000) +#define ENCI_DE_H_END ((0x1b17 << 2) + 0xff000000) +#define ENCI_DE_V_BEGIN_EVEN ((0x1b18 << 2) + 0xff000000) +#define ENCI_DE_V_END_EVEN ((0x1b19 << 2) + 0xff000000) +#define ENCI_DE_V_BEGIN_ODD ((0x1b1a << 2) + 0xff000000) +#define ENCI_DE_V_END_ODD ((0x1b1b << 2) + 0xff000000) +#define ENCI_VBI_SETTING ((0x1b20 << 2) + 0xff000000) +#define ENCI_VBI_CCDT_EVN ((0x1b21 << 2) + 0xff000000) +#define ENCI_VBI_CCDT_ODD ((0x1b22 << 2) + 0xff000000) +#define ENCI_VBI_CC525_LN ((0x1b23 << 2) + 0xff000000) +#define ENCI_VBI_CC625_LN ((0x1b24 << 2) + 0xff000000) +#define ENCI_VBI_WSSDT ((0x1b25 << 2) + 0xff000000) +#define ENCI_VBI_WSS_LN ((0x1b26 << 2) + 0xff000000) +#define ENCI_VBI_CGMSDT_L ((0x1b27 << 2) + 0xff000000) +#define ENCI_VBI_CGMSDT_H ((0x1b28 << 2) + 0xff000000) +#define ENCI_VBI_CGMS_LN ((0x1b29 << 2) + 0xff000000) +#define ENCI_VBI_TTX_HTIME ((0x1b2a << 2) + 0xff000000) +#define ENCI_VBI_TTX_LN ((0x1b2b << 2) + 0xff000000) +#define ENCI_VBI_TTXDT0 ((0x1b2c << 2) + 0xff000000) +#define ENCI_VBI_TTXDT1 ((0x1b2d << 2) + 0xff000000) +#define ENCI_VBI_TTXDT2 ((0x1b2e << 2) + 0xff000000) +#define ENCI_VBI_TTXDT3 ((0x1b2f << 2) + 0xff000000) +#define ENCI_MACV_N0 ((0x1b30 << 2) + 0xff000000) +#define ENCI_MACV_N1 ((0x1b31 << 2) + 0xff000000) +#define ENCI_MACV_N2 ((0x1b32 << 2) + 0xff000000) +#define ENCI_MACV_N3 ((0x1b33 << 2) + 0xff000000) +#define ENCI_MACV_N4 ((0x1b34 << 2) + 0xff000000) +#define ENCI_MACV_N5 ((0x1b35 << 2) + 0xff000000) +#define ENCI_MACV_N6 ((0x1b36 << 2) + 0xff000000) +#define ENCI_MACV_N7 ((0x1b37 << 2) + 0xff000000) +#define ENCI_MACV_N8 ((0x1b38 << 2) + 0xff000000) +#define ENCI_MACV_N9 ((0x1b39 << 2) + 0xff000000) +#define ENCI_MACV_N10 ((0x1b3a << 2) + 0xff000000) +#define ENCI_MACV_N11 ((0x1b3b << 2) + 0xff000000) +#define ENCI_MACV_N12 ((0x1b3c << 2) + 0xff000000) +#define ENCI_MACV_N13 ((0x1b3d << 2) + 0xff000000) +#define ENCI_MACV_N14 ((0x1b3e << 2) + 0xff000000) +#define ENCI_MACV_N15 ((0x1b3f << 2) + 0xff000000) +#define ENCI_MACV_N16 ((0x1b40 << 2) + 0xff000000) +#define ENCI_MACV_N17 ((0x1b41 << 2) + 0xff000000) +#define ENCI_MACV_N18 ((0x1b42 << 2) + 0xff000000) +#define ENCI_MACV_N19 ((0x1b43 << 2) + 0xff000000) +#define ENCI_MACV_N20 ((0x1b44 << 2) + 0xff000000) +#define ENCI_MACV_N21 ((0x1b45 << 2) + 0xff000000) +#define ENCI_MACV_N22 ((0x1b46 << 2) + 0xff000000) +//`define ENCI_MACV_P_AGC 8'h47 +#define ENCI_DBG_PX_RST ((0x1b48 << 2) + 0xff000000) +#define ENCI_DBG_FLDLN_RST ((0x1b49 << 2) + 0xff000000) +#define ENCI_DBG_PX_INT ((0x1b4a << 2) + 0xff000000) +#define ENCI_DBG_FLDLN_INT ((0x1b4b << 2) + 0xff000000) +#define ENCI_DBG_MAXPX ((0x1b4c << 2) + 0xff000000) +#define ENCI_DBG_MAXLN ((0x1b4d << 2) + 0xff000000) +#define ENCI_MACV_MAX_AMP ((0x1b50 << 2) + 0xff000000) +#define ENCI_MACV_PULSE_LO ((0x1b51 << 2) + 0xff000000) +#define ENCI_MACV_PULSE_HI ((0x1b52 << 2) + 0xff000000) +#define ENCI_MACV_BKP_MAX ((0x1b53 << 2) + 0xff000000) +#define ENCI_CFILT_CTRL ((0x1b54 << 2) + 0xff000000) +#define ENCI_CFILT7 ((0x1b55 << 2) + 0xff000000) +#define ENCI_YC_DELAY ((0x1b56 << 2) + 0xff000000) +#define ENCI_VIDEO_EN ((0x1b57 << 2) + 0xff000000) +// +// Closing file: enci_regs.h +// +// +// Reading file: venc2_regs.h +// +//=========================================================================== +// Venc Registers (Cont.) 0xc00 - 0xcff (VENC registers 0xc00 - 0xcef) +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: VENC2_VCBUS_BASE = 0x1c +// ----------------------------------------------- +// Program video control signals from ENCI core to DVI/HDMI interface +#define ENCI_DVI_HSO_BEGIN ((0x1c00 << 2) + 0xff000000) +#define ENCI_DVI_HSO_END ((0x1c01 << 2) + 0xff000000) +#define ENCI_DVI_VSO_BLINE_EVN ((0x1c02 << 2) + 0xff000000) +#define ENCI_DVI_VSO_BLINE_ODD ((0x1c03 << 2) + 0xff000000) +#define ENCI_DVI_VSO_ELINE_EVN ((0x1c04 << 2) + 0xff000000) +#define ENCI_DVI_VSO_ELINE_ODD ((0x1c05 << 2) + 0xff000000) +#define ENCI_DVI_VSO_BEGIN_EVN ((0x1c06 << 2) + 0xff000000) +#define ENCI_DVI_VSO_BEGIN_ODD ((0x1c07 << 2) + 0xff000000) +#define ENCI_DVI_VSO_END_EVN ((0x1c08 << 2) + 0xff000000) +#define ENCI_DVI_VSO_END_ODD ((0x1c09 << 2) + 0xff000000) +// Define cmpt and cvbs cb/cr delay after ENCI chroma filters +// Bit 15:12 RW, enci_cb_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved. +// Bit 11: 8 RW, enci_cr_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved. +// Bit 7: 4 RW, enci_cb_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved. +// Bit 3: 0 RW, enci_cr_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved. +#define ENCI_CFILT_CTRL2 ((0x1c0a << 2) + 0xff000000) +#define ENCI_DACSEL_0 ((0x1c0b << 2) + 0xff000000) +#define ENCI_DACSEL_1 ((0x1c0c << 2) + 0xff000000) +#define ENCP_DACSEL_0 ((0x1c0d << 2) + 0xff000000) +#define ENCP_DACSEL_1 ((0x1c0e << 2) + 0xff000000) +#define ENCP_MAX_LINE_SWITCH_POINT ((0x1c0f << 2) + 0xff000000) +#define ENCI_TST_EN ((0x1c10 << 2) + 0xff000000) +#define ENCI_TST_MDSEL ((0x1c11 << 2) + 0xff000000) +#define ENCI_TST_Y ((0x1c12 << 2) + 0xff000000) +#define ENCI_TST_CB ((0x1c13 << 2) + 0xff000000) +#define ENCI_TST_CR ((0x1c14 << 2) + 0xff000000) +#define ENCI_TST_CLRBAR_STRT ((0x1c15 << 2) + 0xff000000) +#define ENCI_TST_CLRBAR_WIDTH ((0x1c16 << 2) + 0xff000000) +#define ENCI_TST_VDCNT_STSET ((0x1c17 << 2) + 0xff000000) +// bit 15:8 -- vfifo2vd_vd_sel +// bit 7 -- vfifo2vd_drop +// bit 6:1 -- vfifo2vd_delay +// bit 0 -- vfifo2vd_en +#define ENCI_VFIFO2VD_CTL ((0x1c18 << 2) + 0xff000000) +// bit 12:0 -- vfifo2vd_pixel_start +#define ENCI_VFIFO2VD_PIXEL_START ((0x1c19 << 2) + 0xff000000) +// bit 12:00 -- vfifo2vd_pixel_end +#define ENCI_VFIFO2VD_PIXEL_END ((0x1c1a << 2) + 0xff000000) +// bit 10:0 -- vfifo2vd_line_top_start +#define ENCI_VFIFO2VD_LINE_TOP_START ((0x1c1b << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_top_end +#define ENCI_VFIFO2VD_LINE_TOP_END ((0x1c1c << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_bot_start +#define ENCI_VFIFO2VD_LINE_BOT_START ((0x1c1d << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_bot_end +#define ENCI_VFIFO2VD_LINE_BOT_END ((0x1c1e << 2) + 0xff000000) +#define ENCI_VFIFO2VD_CTL2 ((0x1c1f << 2) + 0xff000000) +// bit 15:8 -- vfifo2vd_vd_sel +// bit 7 -- vfifo2vd_drop +// bit 6:1 -- vfifo2vd_delay +// bit 0 -- vfifo2vd_en +#define ENCT_VFIFO2VD_CTL ((0x1c20 << 2) + 0xff000000) +// bit 12:0 -- vfifo2vd_pixel_start +#define ENCT_VFIFO2VD_PIXEL_START ((0x1c21 << 2) + 0xff000000) +// bit 12:00 -- vfifo2vd_pixel_end +#define ENCT_VFIFO2VD_PIXEL_END ((0x1c22 << 2) + 0xff000000) +// bit 10:0 -- vfifo2vd_line_top_start +#define ENCT_VFIFO2VD_LINE_TOP_START ((0x1c23 << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_top_end +#define ENCT_VFIFO2VD_LINE_TOP_END ((0x1c24 << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_bot_start +#define ENCT_VFIFO2VD_LINE_BOT_START ((0x1c25 << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_bot_end +#define ENCT_VFIFO2VD_LINE_BOT_END ((0x1c26 << 2) + 0xff000000) +#define ENCT_VFIFO2VD_CTL2 ((0x1c27 << 2) + 0xff000000) +#define ENCT_TST_EN ((0x1c28 << 2) + 0xff000000) +#define ENCT_TST_MDSEL ((0x1c29 << 2) + 0xff000000) +#define ENCT_TST_Y ((0x1c2a << 2) + 0xff000000) +#define ENCT_TST_CB ((0x1c2b << 2) + 0xff000000) +#define ENCT_TST_CR ((0x1c2c << 2) + 0xff000000) +#define ENCT_TST_CLRBAR_STRT ((0x1c2d << 2) + 0xff000000) +#define ENCT_TST_CLRBAR_WIDTH ((0x1c2e << 2) + 0xff000000) +#define ENCT_TST_VDCNT_STSET ((0x1c2f << 2) + 0xff000000) +// Program video control signals from ENCP core to DVI/HDMI interface +#define ENCP_DVI_HSO_BEGIN ((0x1c30 << 2) + 0xff000000) +#define ENCP_DVI_HSO_END ((0x1c31 << 2) + 0xff000000) +#define ENCP_DVI_VSO_BLINE_EVN ((0x1c32 << 2) + 0xff000000) +#define ENCP_DVI_VSO_BLINE_ODD ((0x1c33 << 2) + 0xff000000) +#define ENCP_DVI_VSO_ELINE_EVN ((0x1c34 << 2) + 0xff000000) +#define ENCP_DVI_VSO_ELINE_ODD ((0x1c35 << 2) + 0xff000000) +#define ENCP_DVI_VSO_BEGIN_EVN ((0x1c36 << 2) + 0xff000000) +#define ENCP_DVI_VSO_BEGIN_ODD ((0x1c37 << 2) + 0xff000000) +#define ENCP_DVI_VSO_END_EVN ((0x1c38 << 2) + 0xff000000) +#define ENCP_DVI_VSO_END_ODD ((0x1c39 << 2) + 0xff000000) +#define ENCP_DE_H_BEGIN ((0x1c3a << 2) + 0xff000000) +#define ENCP_DE_H_END ((0x1c3b << 2) + 0xff000000) +#define ENCP_DE_V_BEGIN_EVEN ((0x1c3c << 2) + 0xff000000) +#define ENCP_DE_V_END_EVEN ((0x1c3d << 2) + 0xff000000) +#define ENCP_DE_V_BEGIN_ODD ((0x1c3e << 2) + 0xff000000) +#define ENCP_DE_V_END_ODD ((0x1c3f << 2) + 0xff000000) +// Bit 15:11 - sync length +// Bit 10:0 - sync start line +#define ENCI_SYNC_LINE_LENGTH ((0x1c40 << 2) + 0xff000000) +// Bit 15 - sync_pulse_enable +// Bit 12:0 - sync start pixel +#define ENCI_SYNC_PIXEL_EN ((0x1c41 << 2) + 0xff000000) +// Bit 15 - enci_sync_enable +// Bit 14 - encp_sync_enable +// Bit 13 - enct_sync_enable +// Bit 12 - short_fussy_sync +// Bit 11 - fussy_sync_enable +// Bit 10:0 - sync target line +#define ENCI_SYNC_TO_LINE_EN ((0x1c42 << 2) + 0xff000000) +// Bit 12:0 - sync target pixel +#define ENCI_SYNC_TO_PIXEL ((0x1c43 << 2) + 0xff000000) +// Bit 15:11 - sync length +// Bit 10:0 - sync start line +#define ENCP_SYNC_LINE_LENGTH ((0x1c44 << 2) + 0xff000000) +// Bit 15 - sync_pulse_enable +// Bit 12:0 - sync start pixel +#define ENCP_SYNC_PIXEL_EN ((0x1c45 << 2) + 0xff000000) +// Bit 15 - enci_sync_enable +// Bit 14 - encp_sync_enable +// Bit 13 - enct_sync_enable +// Bit 12 - short_fussy_sync +// Bit 11 - fussy_sync_enable +// Bit 10:0 - sync target line +#define ENCP_SYNC_TO_LINE_EN ((0x1c46 << 2) + 0xff000000) +// Bit 12:0 - sync target pixel +#define ENCP_SYNC_TO_PIXEL ((0x1c47 << 2) + 0xff000000) +// Bit 15:11 - sync length +// Bit 10:0 - sync start line +#define ENCT_SYNC_LINE_LENGTH ((0x1c48 << 2) + 0xff000000) +// Bit 15 - sync_pulse_enable +// Bit 12:0 - sync start pixel +#define ENCT_SYNC_PIXEL_EN ((0x1c49 << 2) + 0xff000000) +// Bit 15 - enci_sync_enable +// Bit 14 - encp_sync_enable +// Bit 13 - enct_sync_enable +// Bit 12 - short_fussy_sync +// Bit 11 - fussy_sync_enable +// Bit 10:0 - sync target line +#define ENCT_SYNC_TO_LINE_EN ((0x1c4a << 2) + 0xff000000) +// Bit 12:0 - sync target pixel +#define ENCT_SYNC_TO_PIXEL ((0x1c4b << 2) + 0xff000000) +// Bit 15:11 - sync length +// Bit 10:0 - sync start line +#define ENCL_SYNC_LINE_LENGTH ((0x1c4c << 2) + 0xff000000) +// Bit 15 - sync_pulse_enable +// Bit 12:0 - sync start pixel +#define ENCL_SYNC_PIXEL_EN ((0x1c4d << 2) + 0xff000000) +// Bit 15 - enci_sync_enable +// Bit 14 - encp_sync_enable +// Bit 13 - enct_sync_enable +// Bit 12 - short_fussy_sync +// Bit 11 - fussy_sync_enable +// Bit 10:0 - sync target line +#define ENCL_SYNC_TO_LINE_EN ((0x1c4e << 2) + 0xff000000) +// Bit 12:0 - sync target pixel +#define ENCL_SYNC_TO_PIXEL ((0x1c4f << 2) + 0xff000000) +// bit 3 cfg_encp_lcd_scaler_bypass. 1=Do not scale LCD input data; +// 0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4]. +// bit 2 cfg_encp_vadj_scaler_bypass. 1=Do not scale data to enc480p_vadj; +// 0=Scale enc480p_vadj input data to y [16*4,235*4], c [16*4,240*4]. +// bit 1 cfg_vfifo2vd_out_scaler_bypass. 1=Do not scale vfifo2vd's output vdata; +// 0=Scale vfifo2vd's output vdata to y [16,235], c [16,240]. +// bit 0 cfg_vfifo_din_full_range. 1=Data from viu fifo is full range [0,1023]; +// 0=Data from viu fifo is y [16*4,235*4], c [16*4,240*4]. +#define ENCP_VFIFO2VD_CTL2 ((0x1c50 << 2) + 0xff000000) +// bit 15:1 Reserved. +// bit 0 cfg_int_dvi_sel_rgb. Applicable for using on-chip hdmi tx module only. This bit controls correct bit-mapping from +// Venc to hdmi_tx depending on whether YCbCr or RGB mode. +// 1=Map data bit from Venc to hdmi_tx for RGB mode; +// 0=Default. Map data bit from Venc to hdmi_tx for YCbCr mode. +#define VENC_DVI_SETTING_MORE ((0x1c51 << 2) + 0xff000000) +#define VENC_VDAC_DAC4_FILT_CTRL0 ((0x1c54 << 2) + 0xff000000) +#define VENC_VDAC_DAC4_FILT_CTRL1 ((0x1c55 << 2) + 0xff000000) +#define VENC_VDAC_DAC5_FILT_CTRL0 ((0x1c56 << 2) + 0xff000000) +#define VENC_VDAC_DAC5_FILT_CTRL1 ((0x1c57 << 2) + 0xff000000) +//Bit 0 filter_en +#define VENC_VDAC_DAC0_FILT_CTRL0 ((0x1c58 << 2) + 0xff000000) +//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6 +//Bit 15:8, coef1, +//Bit 7:0, coef0, +#define VENC_VDAC_DAC0_FILT_CTRL1 ((0x1c59 << 2) + 0xff000000) +//Bit 0 filter_en +#define VENC_VDAC_DAC1_FILT_CTRL0 ((0x1c5a << 2) + 0xff000000) +//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6 +//Bit 15:8, coef1, +//Bit 7:0, coef0, +#define VENC_VDAC_DAC1_FILT_CTRL1 ((0x1c5b << 2) + 0xff000000) +//Bit 0 filter_en +#define VENC_VDAC_DAC2_FILT_CTRL0 ((0x1c5c << 2) + 0xff000000) +//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6 +//Bit 15:8, coef1, +//Bit 7:0, coef0, +#define VENC_VDAC_DAC2_FILT_CTRL1 ((0x1c5d << 2) + 0xff000000) +//Bit 0 filter_en +#define VENC_VDAC_DAC3_FILT_CTRL0 ((0x1c5e << 2) + 0xff000000) +//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6 +//Bit 15:8, coef1, +//Bit 7:0, coef0, +#define VENC_VDAC_DAC3_FILT_CTRL1 ((0x1c5f << 2) + 0xff000000) +//=========================================================================== +// ENCT registers +#define ENCT_VIDEO_EN ((0x1c60 << 2) + 0xff000000) +#define ENCT_VIDEO_Y_SCL ((0x1c61 << 2) + 0xff000000) +#define ENCT_VIDEO_PB_SCL ((0x1c62 << 2) + 0xff000000) +#define ENCT_VIDEO_PR_SCL ((0x1c63 << 2) + 0xff000000) +#define ENCT_VIDEO_Y_OFFST ((0x1c64 << 2) + 0xff000000) +#define ENCT_VIDEO_PB_OFFST ((0x1c65 << 2) + 0xff000000) +#define ENCT_VIDEO_PR_OFFST ((0x1c66 << 2) + 0xff000000) +//----- Video mode +#define ENCT_VIDEO_MODE ((0x1c67 << 2) + 0xff000000) +#define ENCT_VIDEO_MODE_ADV ((0x1c68 << 2) + 0xff000000) +//--------------- Debug pins +#define ENCT_DBG_PX_RST ((0x1c69 << 2) + 0xff000000) +#define ENCT_DBG_LN_RST ((0x1c6a << 2) + 0xff000000) +#define ENCT_DBG_PX_INT ((0x1c6b << 2) + 0xff000000) +#define ENCT_DBG_LN_INT ((0x1c6c << 2) + 0xff000000) +//----------- Video Advanced setting +#define ENCT_VIDEO_YFP1_HTIME ((0x1c6d << 2) + 0xff000000) +#define ENCT_VIDEO_YFP2_HTIME ((0x1c6e << 2) + 0xff000000) +#define ENCT_VIDEO_YC_DLY ((0x1c6f << 2) + 0xff000000) +#define ENCT_VIDEO_MAX_PXCNT ((0x1c70 << 2) + 0xff000000) +#define ENCT_VIDEO_HAVON_END ((0x1c71 << 2) + 0xff000000) +#define ENCT_VIDEO_HAVON_BEGIN ((0x1c72 << 2) + 0xff000000) +#define ENCT_VIDEO_VAVON_ELINE ((0x1c73 << 2) + 0xff000000) +#define ENCT_VIDEO_VAVON_BLINE ((0x1c74 << 2) + 0xff000000) +#define ENCT_VIDEO_HSO_BEGIN ((0x1c75 << 2) + 0xff000000) +#define ENCT_VIDEO_HSO_END ((0x1c76 << 2) + 0xff000000) +#define ENCT_VIDEO_VSO_BEGIN ((0x1c77 << 2) + 0xff000000) +#define ENCT_VIDEO_VSO_END ((0x1c78 << 2) + 0xff000000) +#define ENCT_VIDEO_VSO_BLINE ((0x1c79 << 2) + 0xff000000) +#define ENCT_VIDEO_VSO_ELINE ((0x1c7a << 2) + 0xff000000) +#define ENCT_VIDEO_MAX_LNCNT ((0x1c7b << 2) + 0xff000000) +#define ENCT_VIDEO_BLANKY_VAL ((0x1c7c << 2) + 0xff000000) +#define ENCT_VIDEO_BLANKPB_VAL ((0x1c7d << 2) + 0xff000000) +#define ENCT_VIDEO_BLANKPR_VAL ((0x1c7e << 2) + 0xff000000) +#define ENCT_VIDEO_HOFFST ((0x1c7f << 2) + 0xff000000) +#define ENCT_VIDEO_VOFFST ((0x1c80 << 2) + 0xff000000) +#define ENCT_VIDEO_RGB_CTRL ((0x1c81 << 2) + 0xff000000) +#define ENCT_VIDEO_FILT_CTRL ((0x1c82 << 2) + 0xff000000) +#define ENCT_VIDEO_OFLD_VPEQ_OFST ((0x1c83 << 2) + 0xff000000) +#define ENCT_VIDEO_OFLD_VOAV_OFST ((0x1c84 << 2) + 0xff000000) +#define ENCT_VIDEO_MATRIX_CB ((0x1c85 << 2) + 0xff000000) +#define ENCT_VIDEO_MATRIX_CR ((0x1c86 << 2) + 0xff000000) +#define ENCT_VIDEO_RGBIN_CTRL ((0x1c87 << 2) + 0xff000000) +#define ENCT_MAX_LINE_SWITCH_POINT ((0x1c88 << 2) + 0xff000000) +#define ENCT_DACSEL_0 ((0x1c89 << 2) + 0xff000000) +#define ENCT_DACSEL_1 ((0x1c8a << 2) + 0xff000000) +#define ENCT_INBUF_CNTL0 ((0x1c8b << 2) + 0xff000000) +#define ENCT_INBUF_CNTL1 ((0x1c8c << 2) + 0xff000000) +#define ENCT_INBUF_CNT ((0x1c8d << 2) + 0xff000000) +#define ENCT_INBUF_HOLD_CNT ((0x1c8e << 2) + 0xff000000) +#define ENCT_INBUF_FIX_PIX_NUM ((0x1c8f << 2) + 0xff000000) +//=========================================================================== +// For ENCL +//=========================================================================== +// bit 15:8 -- vfifo2vd_vd_sel +// bit 7 -- vfifo2vd_drop +// bit 6:1 -- vfifo2vd_delay +// bit 0 -- vfifo2vd_en +#define ENCL_VFIFO2VD_CTL ((0x1c90 << 2) + 0xff000000) +// bit 12:0 -- vfifo2vd_pixel_start +#define ENCL_VFIFO2VD_PIXEL_START ((0x1c91 << 2) + 0xff000000) +// bit 12:00 -- vfifo2vd_pixel_end +#define ENCL_VFIFO2VD_PIXEL_END ((0x1c92 << 2) + 0xff000000) +// bit 10:0 -- vfifo2vd_line_top_start +#define ENCL_VFIFO2VD_LINE_TOP_START ((0x1c93 << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_top_end +#define ENCL_VFIFO2VD_LINE_TOP_END ((0x1c94 << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_bot_start +#define ENCL_VFIFO2VD_LINE_BOT_START ((0x1c95 << 2) + 0xff000000) +// bit 10:00 -- vfifo2vd_line_bot_end +#define ENCL_VFIFO2VD_LINE_BOT_END ((0x1c96 << 2) + 0xff000000) +#define ENCL_VFIFO2VD_CTL2 ((0x1c97 << 2) + 0xff000000) +#define ENCL_TST_EN ((0x1c98 << 2) + 0xff000000) +#define ENCL_TST_MDSEL ((0x1c99 << 2) + 0xff000000) +#define ENCL_TST_Y ((0x1c9a << 2) + 0xff000000) +#define ENCL_TST_CB ((0x1c9b << 2) + 0xff000000) +#define ENCL_TST_CR ((0x1c9c << 2) + 0xff000000) +#define ENCL_TST_CLRBAR_STRT ((0x1c9d << 2) + 0xff000000) +#define ENCL_TST_CLRBAR_WIDTH ((0x1c9e << 2) + 0xff000000) +#define ENCL_TST_VDCNT_STSET ((0x1c9f << 2) + 0xff000000) +//=========================================================================== +// ENCL registers +#define ENCL_VIDEO_EN ((0x1ca0 << 2) + 0xff000000) +#define ENCL_VIDEO_Y_SCL ((0x1ca1 << 2) + 0xff000000) +#define ENCL_VIDEO_PB_SCL ((0x1ca2 << 2) + 0xff000000) +#define ENCL_VIDEO_PR_SCL ((0x1ca3 << 2) + 0xff000000) +#define ENCL_VIDEO_Y_OFFST ((0x1ca4 << 2) + 0xff000000) +#define ENCL_VIDEO_PB_OFFST ((0x1ca5 << 2) + 0xff000000) +#define ENCL_VIDEO_PR_OFFST ((0x1ca6 << 2) + 0xff000000) +//----- Video mode +#define ENCL_VIDEO_MODE ((0x1ca7 << 2) + 0xff000000) +#define ENCL_VIDEO_MODE_ADV ((0x1ca8 << 2) + 0xff000000) +//--------------- Debug pins +#define ENCL_DBG_PX_RST ((0x1ca9 << 2) + 0xff000000) +#define ENCL_DBG_LN_RST ((0x1caa << 2) + 0xff000000) +#define ENCL_DBG_PX_INT ((0x1cab << 2) + 0xff000000) +#define ENCL_DBG_LN_INT ((0x1cac << 2) + 0xff000000) +//----------- Video Advanced setting +#define ENCL_VIDEO_YFP1_HTIME ((0x1cad << 2) + 0xff000000) +#define ENCL_VIDEO_YFP2_HTIME ((0x1cae << 2) + 0xff000000) +#define ENCL_VIDEO_YC_DLY ((0x1caf << 2) + 0xff000000) +#define ENCL_VIDEO_MAX_PXCNT ((0x1cb0 << 2) + 0xff000000) +#define ENCL_VIDEO_HAVON_END ((0x1cb1 << 2) + 0xff000000) +#define ENCL_VIDEO_HAVON_BEGIN ((0x1cb2 << 2) + 0xff000000) +#define ENCL_VIDEO_VAVON_ELINE ((0x1cb3 << 2) + 0xff000000) +#define ENCL_VIDEO_VAVON_BLINE ((0x1cb4 << 2) + 0xff000000) +#define ENCL_VIDEO_HSO_BEGIN ((0x1cb5 << 2) + 0xff000000) +#define ENCL_VIDEO_HSO_END ((0x1cb6 << 2) + 0xff000000) +#define ENCL_VIDEO_VSO_BEGIN ((0x1cb7 << 2) + 0xff000000) +#define ENCL_VIDEO_VSO_END ((0x1cb8 << 2) + 0xff000000) +#define ENCL_VIDEO_VSO_BLINE ((0x1cb9 << 2) + 0xff000000) +#define ENCL_VIDEO_VSO_ELINE ((0x1cba << 2) + 0xff000000) +#define ENCL_VIDEO_MAX_LNCNT ((0x1cbb << 2) + 0xff000000) +#define ENCL_VIDEO_BLANKY_VAL ((0x1cbc << 2) + 0xff000000) +#define ENCL_VIDEO_BLANKPB_VAL ((0x1cbd << 2) + 0xff000000) +#define ENCL_VIDEO_BLANKPR_VAL ((0x1cbe << 2) + 0xff000000) +#define ENCL_VIDEO_HOFFST ((0x1cbf << 2) + 0xff000000) +#define ENCL_VIDEO_VOFFST ((0x1cc0 << 2) + 0xff000000) +#define ENCL_VIDEO_RGB_CTRL ((0x1cc1 << 2) + 0xff000000) +#define ENCL_VIDEO_FILT_CTRL ((0x1cc2 << 2) + 0xff000000) +#define ENCL_VIDEO_OFLD_VPEQ_OFST ((0x1cc3 << 2) + 0xff000000) +#define ENCL_VIDEO_OFLD_VOAV_OFST ((0x1cc4 << 2) + 0xff000000) +#define ENCL_VIDEO_MATRIX_CB ((0x1cc5 << 2) + 0xff000000) +#define ENCL_VIDEO_MATRIX_CR ((0x1cc6 << 2) + 0xff000000) +#define ENCL_VIDEO_RGBIN_CTRL ((0x1cc7 << 2) + 0xff000000) +#define ENCL_MAX_LINE_SWITCH_POINT ((0x1cc8 << 2) + 0xff000000) +#define ENCL_DACSEL_0 ((0x1cc9 << 2) + 0xff000000) +#define ENCL_DACSEL_1 ((0x1cca << 2) + 0xff000000) +#define ENCT_VIDEO_H_PRE_DE_END ((0x1ccb << 2) + 0xff000000) +#define ENCT_VIDEO_H_PRE_DE_BEGIN ((0x1ccc << 2) + 0xff000000) +#define ENCT_VIDEO_V_PRE_DE_ELINE ((0x1ccd << 2) + 0xff000000) +#define ENCT_VIDEO_V_PRE_DE_BLINE ((0x1cce << 2) + 0xff000000) +#define ENCL_VIDEO_H_PRE_DE_END ((0x1ccf << 2) + 0xff000000) +#define ENCL_VIDEO_H_PRE_DE_BEGIN ((0x1cd0 << 2) + 0xff000000) +#define ENCL_VIDEO_V_PRE_DE_ELINE ((0x1cd1 << 2) + 0xff000000) +#define ENCL_VIDEO_V_PRE_DE_BLINE ((0x1cd2 << 2) + 0xff000000) +#define ENCL_INBUF_CNTL0 ((0x1cd3 << 2) + 0xff000000) +#define ENCL_INBUF_CNTL1 ((0x1cd4 << 2) + 0xff000000) +#define ENCL_INBUF_CNT ((0x1cd5 << 2) + 0xff000000) +#define ENCL_INBUF_HOLD_CNT ((0x1cd6 << 2) + 0xff000000) +#define ENCL_INBUF_FIX_PIX_NUM ((0x1cd7 << 2) + 0xff000000) +// +// Closing file: venc2_regs.h +// +// +// Reading file: vpp_regs.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: VPP_VCBUS_BASE = 0x1d +// ----------------------------------------------- +#define VPP_VD1_SC_OFFSET 0x00 //just used in vpp_vd1_scale +//=========================================================================== +// Video postprocesing Registers +//=========================================================================== +// dummy data used in the VPP preblend and scaler +// Bit 23:16 Y +// Bit 15:8 CB +// Bit 7:0 CR +#define VPP_DUMMY_DATA ((0x1d00 << 2) + 0xff000000) +//input line length used in VPP +#define VPP_LINE_IN_LENGTH ((0x1d01 << 2) + 0xff000000) +//input Picture height used in VPP +#define VPP_PIC_IN_HEIGHT ((0x1d02 << 2) + 0xff000000) +//Because there are many coefficients used in the vertical filter and horizontal filters, +//indirect access the coefficients of vertical filter and horizontal filter is used. +//For vertical filter, there are 33x4 coefficients +//For horizontal filter, there are 33x4 coefficients +//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2) +//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not +//Bit 13 if true, vertical separated coef enable +//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef +//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered +//Bit 6:0 coef index +#define VPP_SCALE_COEF_IDX ((0x1d03 << 2) + 0xff000000) +//coefficients for vertical filter and horizontal filter +#define VPP_SCALE_COEF ((0x1d04 << 2) + 0xff000000) +//these following registers are the absolute line address pointer for output divided screen +//The output divided screen is shown in the following: +// +// -------------------------- <------ line zero +// . +// . +// . region0 <---------- nonlinear region or nonscaling region +// . +// --------------------------- +// --------------------------- <------ region1_startp +// . +// . region1 <---------- nonlinear region +// . +// . +// --------------------------- +// --------------------------- <------ region2_startp +// . +// . region2 <---------- linear region +// . +// . +// --------------------------- +// --------------------------- <------ region3_startp +// . +// . region3 <---------- nonlinear region +// . +// . +// --------------------------- +// --------------------------- <------ region4_startp +// . +// . region4 <---------- nonlinear region or nonoscaling region +// . +// . +// --------------------------- <------ region4_endp +//Bit 28:16 region1 startp +//Bit 12:0 region2 startp +#define VPP_VSC_REGION12_STARTP ((0x1d05 << 2) + 0xff000000) +//Bit 28:16 region3 startp +//Bit 12:0 region4 startp +#define VPP_VSC_REGION34_STARTP ((0x1d06 << 2) + 0xff000000) +#define VPP_VSC_REGION4_ENDP ((0x1d07 << 2) + 0xff000000) +//vertical start phase step, (source/dest)*(2^24) +//Bit 27:24 integer part +//Bit 23:0 fraction part +#define VPP_VSC_START_PHASE_STEP ((0x1d08 << 2) + 0xff000000) +//vertical scaler region0 phase slope, Bit24 signed bit +#define VPP_VSC_REGION0_PHASE_SLOPE ((0x1d09 << 2) + 0xff000000) +//vertical scaler region1 phase slope, Bit24 signed bit +#define VPP_VSC_REGION1_PHASE_SLOPE ((0x1d0a << 2) + 0xff000000) +//vertical scaler region3 phase slope, Bit24 signed bit +#define VPP_VSC_REGION3_PHASE_SLOPE ((0x1d0b << 2) + 0xff000000) +//vertical scaler region4 phase slope, Bit24 signed bit +#define VPP_VSC_REGION4_PHASE_SLOPE ((0x1d0c << 2) + 0xff000000) +//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X, +// so only 2 line buffer in this case, use for 3D line by line interleave scaling +// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines +//Bit 16 0: progressive output, 1: interlace output +//Bit 15 vertical scaler output line0 in advance or not for bottom field +//Bit 14:13 vertical scaler initial repeat line0 number for bottom field +//Bit 11:8 vertical scaler initial receiving number for bottom field +//Bit 7 vertical scaler output line0 in advance or not for top field +//Bit 6:5 vertical scaler initial repeat line0 number for top field +//Bit 3:0 vertical scaler initial receiving number for top field +#define VPP_VSC_PHASE_CTRL ((0x1d0d << 2) + 0xff000000) +//Bit 31:16 vertical scaler field initial phase for bottom field +//Bit 15:0 vertical scaler field initial phase for top field +#define VPP_VSC_INI_PHASE ((0x1d0e << 2) + 0xff000000) +//Bit 28:16 region1 startp +//Bit 12:0 region2 startp +#define VPP_HSC_REGION12_STARTP ((0x1d10 << 2) + 0xff000000) +//Bit 28:16 region3 startp +//Bit 12:0 region4 startp +#define VPP_HSC_REGION34_STARTP ((0x1d11 << 2) + 0xff000000) +#define VPP_HSC_REGION4_ENDP ((0x1d12 << 2) + 0xff000000) +//horizontal start phase step, (source/dest)*(2^24) +//Bit 27:24 integer part +//Bit 23:0 fraction part +#define VPP_HSC_START_PHASE_STEP ((0x1d13 << 2) + 0xff000000) +//horizontal scaler region0 phase slope, Bit24 signed bit +#define VPP_HSC_REGION0_PHASE_SLOPE ((0x1d14 << 2) + 0xff000000) +//horizontal scaler region1 phase slope, Bit24 signed bit +#define VPP_HSC_REGION1_PHASE_SLOPE ((0x1d15 << 2) + 0xff000000) +//horizontal scaler region3 phase slope, Bit24 signed bit +#define VPP_HSC_REGION3_PHASE_SLOPE ((0x1d16 << 2) + 0xff000000) +//horizontal scaler region4 phase slope, Bit24 signed bit +#define VPP_HSC_REGION4_PHASE_SLOPE ((0x1d17 << 2) + 0xff000000) +//Bit 22:21 horizontal scaler initial repeat pixel0 number0 +//Bit 19:16 horizontal scaler initial receiving number0 +//Bit 15:0 horizontal scaler top field initial phase0 +#define VPP_HSC_PHASE_CTRL ((0x1d18 << 2) + 0xff000000) +// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length, +// just for special usage, more flexibility +// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en +// Bit 20 prehsc_en +// Bit 19 prevsc_en +// Bit 18 vsc_en +// Bit 17 hsc_en +// Bit 16 scale_top_en +// Bit 15 video1 scale out enable +// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler +// Bit 10:8 horizontal scaler bank length +// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i +// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler +// Bit 2:0 vertical scaler bank length +#define VPP_SC_MISC ((0x1d19 << 2) + 0xff000000) +// preblend video1 horizontal start and end +//Bit 28:16 start +//Bit 12:0 end +#define VPP_PREBLEND_VD1_H_START_END ((0x1d1a << 2) + 0xff000000) +// preblend video1 vertical start and end +//Bit 28:16 start +//Bit 12:0 end +#define VPP_PREBLEND_VD1_V_START_END ((0x1d1b << 2) + 0xff000000) +// postblend video1 horizontal start and end +//Bit 28:16 start +//Bit 12:0 end +#define VPP_POSTBLEND_VD1_H_START_END ((0x1d1c << 2) + 0xff000000) +// postblend video1 vertical start and end +//Bit 28:16 start +//Bit 12:0 end +#define VPP_POSTBLEND_VD1_V_START_END ((0x1d1d << 2) + 0xff000000) +// preblend/postblend video2 horizontal start and end +//Bit 28:16 start +//Bit 12:0 end +#define VPP_BLEND_VD2_H_START_END ((0x1d1e << 2) + 0xff000000) +// preblend/postblend video2 vertical start and end +//Bit 28:16 start +//Bit 12:0 end +#define VPP_BLEND_VD2_V_START_END ((0x1d1f << 2) + 0xff000000) +// preblend horizontal size +#define VPP_PREBLEND_H_SIZE ((0x1d20 << 2) + 0xff000000) +// postblend horizontal size +#define VPP_POSTBLEND_H_SIZE ((0x1d21 << 2) + 0xff000000) +//VPP hold lines +//Bit 29:24 +//Bit 21:16 +//Bit 15:8 preblend hold lines +//Bit 7:0 postblend hold lines +#define VPP_HOLD_LINES ((0x1d22 << 2) + 0xff000000) +//Bit 26 if true, automatic change post blend output to one color if field ==1 +//Bit 25 if true, change screen to one color value for preblender +//Bit 24 if true, change screen to one color value for postblender +// Bit 23:16 one color Y +// Bit 15:8 one color Cb +// Bit 7:0 one color Cr +#define VPP_BLEND_ONECOLOR_CTRL ((0x1d23 << 2) + 0xff000000) +//Read Only, VPP preblend current_x, current_y +//Bit 28:16 current_x +//Bit 12:0 current_y +#define VPP_PREBLEND_CURRENT_XY ((0x1d24 << 2) + 0xff000000) +//Read Only, VPP postblend current_x, current_y +//Bit 28:16 current_x +//Bit 12:0 current_y +#define VPP_POSTBLEND_CURRENT_XY ((0x1d25 << 2) + 0xff000000) +// Bit 31 vd1_bgosd_exchange_en for preblend +// Bit 30 vd1_bgosd_exchange_en for postblend +// Bit 28 color management enable +// Bit 27, if true, vd2 use viu2 output as the input, otherwise use normal vd2 from memory +// Bit 26:18, vd2 alpha +// Bit 17, osd2 enable for preblend +// Bit 16, osd1 enable for preblend +// Bit 15, vd2 enable for preblend +// Bit 14, vd1 enable for preblend +// Bit 13, osd2 enable for postblend +// Bit 12, osd1 enable for postblend +// Bit 11, vd2 enable for postblend +// Bit 10, vd1 enable for postblend +// Bit 9, if true, osd1 is alpha premultipiled +// Bit 8, if true, osd2 is alpha premultipiled +// Bit 7, postblend module enable +// Bit 6, preblend module enable +// Bit 5, if true, osd2 foreground compared with osd1 in preblend +// Bit 4, if true, osd2 foreground compared with osd1 in postblend +// Bit 3, +// Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync +// the aync fifo will be reseted. +// Bit 1, +// Bit 0 if true, the output result of VPP is saturated +#define VPP_MISC ((0x1d26 << 2) + 0xff000000) +//Bit 31:20 ofifo line length minus 1 +//Bit 19 if true invert input vs +//Bit 18 if true invert input hs +//Bit 17 force top/bottom field, enable +//Bit 16 force top/bottom field, 0: top, 1: bottom +//Bit 15 force one go_field, one pluse, write only +//Bit 14 force one go_line, one pluse, write only +//Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number +#define VPP_OFIFO_SIZE ((0x1d27 << 2) + 0xff000000) +//Read only +//Bit 28:18 current scale out fifo counter +//Bit 17:13 current afifo counter +//Bit 12:0 current ofifo counter +#define VPP_FIFO_STATUS ((0x1d28 << 2) + 0xff000000) +// Bit 5 SMOKE3 postblend enable only when postblend vd2 is not enable +// Bit 4 SMOKE3 preblend enable only when preblend vd2 is not enable +// Bit 3 SMOKE2 postblend enable only when postblend osd2 is not enable +// Bit 2 SMOKE2 preblend enable only when preblend osd2 is not enable +// Bit 1 SMOKE1 postblend enable only when postblend osd1 is not enable +// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable +#define VPP_SMOKE_CTRL ((0x1d29 << 2) + 0xff000000) +//smoke can be used only when that blending is disable and then be used as smoke function +//smoke1 for OSD1 chanel +//smoke2 for OSD2 chanel +//smoke3 for VD2 chanel +//31:24 Y +//23:16 Cb +//15:8 Cr +//7:0 Alpha +#define VPP_SMOKE1_VAL ((0x1d2a << 2) + 0xff000000) +#define VPP_SMOKE2_VAL ((0x1d2b << 2) + 0xff000000) +#define VPP_SMOKE3_VAL ((0x1d2c << 2) + 0xff000000) +//Bit 28:16 start +//Bit 12:0 end +#define VPP_SMOKE1_H_START_END ((0x1d2d << 2) + 0xff000000) +//Bit 28:16 start +//Bit 12:0 end +#define VPP_SMOKE1_V_START_END ((0x1d2e << 2) + 0xff000000) +//Bit 28:16 start +//Bit 12:0 end +#define VPP_SMOKE2_H_START_END ((0x1d2f << 2) + 0xff000000) +//Bit 28:16 start +//Bit 12:0 end +#define VPP_SMOKE2_V_START_END ((0x1d30 << 2) + 0xff000000) +//Bit 28:16 start +//Bit 12:0 end +#define VPP_SMOKE3_H_START_END ((0x1d31 << 2) + 0xff000000) +//Bit 28:16 start +//Bit 12:0 end +#define VPP_SMOKE3_V_START_END ((0x1d32 << 2) + 0xff000000) +//Bit 27:16 scale out fifo line length minus 1 +//Bit 12:0 scale out fifo size (actually only bit 11:1 is valid, 11:1, max 1024), always even number +#define VPP_SCO_FIFO_CTRL ((0x1d33 << 2) + 0xff000000) +//for 3D quincunx sub-sampling and horizontal pixel by pixel 3D interleaving +//Bit 27:24, prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode, +// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0 +//Bit 23 horizontal scaler double pixel mode +//Bit 22:21 horizontal scaler initial repeat pixel0 number1 +//Bit 19:16 horizontal scaler initial receiving number1 +//Bit 15:0 horizontal scaler top field initial phase1 +#define VPP_HSC_PHASE_CTRL1 ((0x1d34 << 2) + 0xff000000) +//for 3D quincunx sub-sampling +//31:24 prehsc pattern, each patten 1 bit, from lsb -> msb +//22:20 prehsc pattern start +//18:16 prehsc pattern end +//15:8 hsc pattern, each patten 1 bit, from lsb -> msb +//6:4 hsc pattern start +//2:0 hsc pattern end +#define VPP_HSC_INI_PAT_CTRL ((0x1d35 << 2) + 0xff000000) +#define VPP_SC_GCLK_CTRL1 ((0x1d36 << 2) + 0xff000000) +//Bit 3 minus black level enable for vadj2 +//Bit 2 Video adjustment enable for vadj2 +//Bit 1 minus black level enable for vadj1 +//Bit 0 Video adjustment enable for vadj1 +#define VPP_VADJ_CTRL ((0x1d40 << 2) + 0xff000000) +//Bit 16:8 brightness, signed value +//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2 +//`define VPP_VADJ1_Y 8'h41 //'h00080 +//cb' = cb*ma + cr*mb +//cr' = cb*mc + cr*md +//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2 +//`define VPP_VADJ1_MA_MB 8'h42 //26'h100_0000 +//`define VPP_VADJ1_MC_MD 8'h43 //26'h000_0100 +//Bit 16:8 brightness, signed value +//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2 +//`define VPP_VADJ2_Y 8'h44 //'h00080 +//cb' = cb*ma + cr*mb +//cr' = cb*mc + cr*md +//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2 +//`define VPP_VADJ2_MA_MB 8'h45 //26'h100_0000 +//`define VPP_VADJ2_MC_MD 8'h46 //26'h000_0100 +//Bit 2 horizontal chroma sharp/blur selection, 0:sharp, 1: blur +//Bit 1 horizontal luma sharp/blur selection, 0:sharp, 1: blur +//Bit 0 horizontal sharpness enable +#define VPP_HSHARP_CTRL ((0x1d50 << 2) + 0xff000000) +//{1'b0,threhsold} < diff +//Bit 26:16 luma threshold0 +//Bit 10:0 luma threshold1 +#define VPP_HSHARP_LUMA_THRESH01 ((0x1d51 << 2) + 0xff000000) +// +//Bit 26:16 luma threshold2 +//Bit 10:0 luma threshold3 +#define VPP_HSHARP_LUMA_THRESH23 ((0x1d52 << 2) + 0xff000000) +//Bit 26:16 chroma threshold0 +//Bit 10:0 chroma threshold1 +#define VPP_HSHARP_CHROMA_THRESH01 ((0x1d53 << 2) + 0xff000000) +//Bit 26:16 chroma threshold2 +//Bit 10:0 chroma threshold3 +#define VPP_HSHARP_CHROMA_THRESH23 ((0x1d54 << 2) + 0xff000000) +//Bit 23:16 luma gain2 +//Bit 15:8 luma gain1 +//Bit 7:0 luma gain0 +#define VPP_HSHARP_LUMA_GAIN ((0x1d55 << 2) + 0xff000000) +// +//Bit 23:16 chroma gain2 +//Bit 15:8 chroma gain1 +//Bit 7:0 chroma gain0 +#define VPP_HSHARP_CHROMA_GAIN ((0x1d56 << 2) + 0xff000000) +//Read only +//Bit 31, if it is true, it means this probe is valid in the last field/frame +//Bit 29:20 component 0 +//Bit 19:10 component 1 +//Bit 9:0 component 2 +#define VPP_MATRIX_PROBE_COLOR ((0x1d5c << 2) + 0xff000000) +#define VPP_MATRIX_PROBE_COLOR1 ((0x1dd7 << 2) + 0xff000000) +//Bit 23:16 component 0 +//Bit 15:8 component 1 +//Bit 7:0 component 2 +#define VPP_MATRIX_HL_COLOR ((0x1d5d << 2) + 0xff000000) +//28:16 probe x, postion +//12:0 probe y, position +#define VPP_MATRIX_PROBE_POS ((0x1d5e << 2) + 0xff000000) +//Bit 16, highlight_en +//Bit 15 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix +//Bit 14:12 probe_sel, 000: select post matrix, 001: select vd1 matrix, 010: select vd2 matrix +//Bit 9:8 matrix coef idx selection, 00: select post matrix, 01: select vd1 matrix, 10: select vd2 matrix +//Bit 5 vd1 conversion matrix enable +//Bit 4 vd2 conversion matrix enable +//Bit 2 output y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240) +//Bit 1 input y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240) +//Bit 0 post conversion matrix enable +#define VPP_MATRIX_CTRL ((0x1d5f << 2) + 0xff000000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define VPP_MATRIX_COEF00_01 ((0x1d60 << 2) + 0xff000000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define VPP_MATRIX_COEF02_10 ((0x1d61 << 2) + 0xff000000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define VPP_MATRIX_COEF11_12 ((0x1d62 << 2) + 0xff000000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define VPP_MATRIX_COEF20_21 ((0x1d63 << 2) + 0xff000000) +#define VPP_MATRIX_COEF22 ((0x1d64 << 2) + 0xff000000) +//Bit 26:16 offset0 +//Bit 10:0 offset1 +#define VPP_MATRIX_OFFSET0_1 ((0x1d65 << 2) + 0xff000000) +//Bit 10:0 offset2 +#define VPP_MATRIX_OFFSET2 ((0x1d66 << 2) + 0xff000000) +//Bit 26:16 pre_offset0 +//Bit 10:0 pre_offset1 +#define VPP_MATRIX_PRE_OFFSET0_1 ((0x1d67 << 2) + 0xff000000) +//Bit 10:0 pre_offset2 +#define VPP_MATRIX_PRE_OFFSET2 ((0x1d68 << 2) + 0xff000000) +// dummy data used in the VPP postblend +// Bit 23:16 Y +// Bit 15:8 CB +// Bit 7:0 CR +#define VPP_DUMMY_DATA1 ((0x1d69 << 2) + 0xff000000) +//Bit 31 gainoff module enable +//Bit 26:16 gain0, 1.10 unsigned data +//Bit 10:0 gain1, 1.10 unsigned dat +#define VPP_GAINOFF_CTRL0 ((0x1d6a << 2) + 0xff000000) +//Bit 26:16 gain2, 1.10 unsigned data +//Bit 10:0, offset0, signed data +#define VPP_GAINOFF_CTRL1 ((0x1d6b << 2) + 0xff000000) +//Bit 26:16, offset1, signed data +//Bit 10:0, offset2, signed data +#define VPP_GAINOFF_CTRL2 ((0x1d6c << 2) + 0xff000000) +//Bit 26:16, pre_offset0, signed data +//Bit 10:0, pre_offset1, signed data +#define VPP_GAINOFF_CTRL3 ((0x1d6d << 2) + 0xff000000) +//Bit 10:0, pre_offset2, signed data +#define VPP_GAINOFF_CTRL4 ((0x1d6e << 2) + 0xff000000) +#define VPP_GAINOFF_GCLK_CTRL ((0x1d6f << 2) + 0xff000000) +//only two registers used in the color management, which are defined in the chroma_reg.h +//`define VPP_CHROMA_ADDR_PORT 8'h70 +//`define VPP_CHROMA_DATA_PORT 8'h71 +// +// Reading file: chroma_reg.h +// +//********************************************************************************** +//* Copyright (c) 2008, AMLOGIC Inc. +//* All rights reserved +//********************************************************************************** +//* File : chroma_reg.v +//* Author : Terrence Wang +//* Date : Dec 2008 +//* Description : +//* +//********************************************************************************** +//* Modification History: +//* Date Modified By Reason +//********************************************************************************** +// synopsys translate_off +// synopsys translate_on +#define VPP_CHROMA_ADDR_PORT ((0x1d70 << 2) + 0xff000000) +#define VPP_CHROMA_DATA_PORT ((0x1d71 << 2) + 0xff000000) +//`define CHROMA_ADDR_PORT 8'h67 +//`define CHROMA_DATA_PORT 8'h68 + +// CHROMA_GAIN_REG_XX(00-07) +// hue gain, sat gain function control +// Bit 31 reg_sat_en enable sat adjustment in current region +// Bit 27 reg_sat_increase sat adjustment increase or decrease +// 1'b1: increase 1'b0: decrease +// Bit 26:25 reg_sat_central_en sat adjustment with central biggest or one side biggest +// 2'b01 central biggest 2'b00 one side biggest +// Bit 24 reg_sat_shape when sat adjustment one side biggest, define left or right +// 1'b1: left side biggest 1'b0 right side biggest +// Bit 23:16 reg_sat_gain define the sat gain when sat adjustment +// 0x00-0xff +// Bit 15 reg_hue_en enable hue adjustment in current region +// Bit 11 reg_hue_clockwise hue adjustment clockwise or anti-clockwise +// 1'b1: clockwise 1'b0: anti-clockwise +// Bit 10:9 reg_hue_central_en when hue adjustment, parabola curve or non-symmetry curve +// 1'b1: parabola curve 1'b0: non-symmetry curve +// Bit 8 reg_hue_shape when non-symmetry curve, define which side change more +// 1'b1: right side change more 1'b0: left side change more +// Bit 7:0 reg_hue_gain define the hue gain when hue adjustment +// 0x00-0x80, note: should be no bigger than 0x80 + + #define CHROMA_GAIN_REG00 0x00 + + +// HUE_HUE_RANGE_REG_XX(00-07) +// hue range select +// Bit 31:24 no use now +// Bit 23:16 reg_hue_shift_range define the angle of target region +// 0x00-0xff,(0x100 means 120 degree though it can not be set) +// must be greater or equal than 8'd8 +// Bit 15 reg_symmetry_en this is used for create one symmetry region +// the symmetry region hue_shift_start = reg_hue_hue_shift_start + reg_hue_shift_range<<5 +// the symmetry region hue_shift_range = reg_hue_shift_range +// in symmetry region, all the sat and hue setting will be same with original region, +// except reg_hue_shape, reg_sat_shape, reg_hue_clockwise will be reversed +// Bit 14:0 reg_hue_hue_shift_start define the start angle of target region +// 0x6000 means 360 degree +// only region 0 and 1 can exceed 360 degrees. + + #define HUE_HUE_RANGE_REG00 0x01 + + +// HUE_RANGE_INV_REG_XX +// Calculation should be follow +// HUE_RANGE_INV_REG0X[15:0] = ((1<<20)/HUE_HUE_RANGE_REG0X[23:16]+1)>>1 +// HUE_RANGE_INV_REG_XX is to used to save divider + + #define HUE_RANGE_INV_REG00 0x02 + + + +// for belowing each low, high, low_slope, high_slope group: +// a_____________b +// / \ a = low + 2^low_slope +// / \ b = high - 2^high_slope +// / \ low_slope <= 7; high_slope <= 7 +// / \ b >= a +// ______/_____________________\________ +// low high +// +// +// HUE_LUM_RANGE_REG_XX(00-07) +// luma range selection for hue adjustment +// Bit 31:24 reg_sat_lum_low define the low level of luma value for sat adjustment +// 0x00-0xff +// Bit 23:20 reg_hue_lum_high_slope define the slope area below high level of luma value for hue adjustment +// 0x00-0x07 +// Bit 19:16 reg_hue_lum_low_slope define the slope area above low level of luma value for hue adjustment +// 0x00-0x07 +// Bit 15:8 reg_hue_lum_high define the high level of luma value for hue adjustment +// 0x00-0xff +// Bit 7:0 reg_hue_lum_low define the low level of luma value for hue adjustment +// 0x00-0xff + + #define HUE_LUM_RANGE_REG00 0x03 + +// HUE_SAT_RANGE_REG_XX(00-07) +// sat range selection for hue adjustment +// Bit 31:24 reg_sat_lum_high define the high level of luma value for sat adjustment +// 0x00-0xff +// Bit 23:20 reg_hue_sat_high_slope define the slope area below high level of sat value for hue adjustment +// 0x00-0x07 +// Bit 19:16 reg_hue_sat_low_slope define the slope area above low level of sat value for hue adjustment +// 0x00-0x07 +// Bit 15:8 reg_hue_sat_high define the high level of sat value for hue adjustment +// 0x00-0xff +// Bit 7:0 reg_hue_sat_low define the low level of sat value for hue adjustment +// 0x00-0xff + + #define HUE_SAT_RANGE_REG00 0x04 + +// SAT_SAT_RANGE_REG_XX(00-07) +// sat range selection for hue adjustment +// Bit 31:28 reg_sat_lum_high_slope define the slope area below high level of luma value for sat adjustment +// 0x00-0x07 +// Bit 27:24 reg_sat_lum_low_slope define the slope area above low level of luma value for sat adjustment +// 0x00-0x07 +// Bit 23:20 reg_sat_sat_high_slope define the slope area below high level of sat value for sat adjustment +// 0x00-0x07 +// Bit 19:16 reg_sat_sat_low_slope define the slope area above low level of sat value for sat adjustment +// 0x00-0x07 +// Bit 15:8 reg_sat_sat_high define the high level of sat value for sat adjustment +// 0x00-0xff +// Bit 7:0 reg_sat_sat_low define the low level of sat value for sat adjustment +// 0x00-0xff + + #define SAT_SAT_RANGE_REG00 0x05 + + + #define CHROMA_GAIN_REG01 0x06 + #define HUE_HUE_RANGE_REG01 0x07 + #define HUE_RANGE_INV_REG01 0x08 + #define HUE_LUM_RANGE_REG01 0x09 + #define HUE_SAT_RANGE_REG01 0x0a + #define SAT_SAT_RANGE_REG01 0x0b + + #define CHROMA_GAIN_REG02 0x0c + #define HUE_HUE_RANGE_REG02 0x0d + #define HUE_RANGE_INV_REG02 0x0e + #define HUE_LUM_RANGE_REG02 0x0f + #define HUE_SAT_RANGE_REG02 0x10 + #define SAT_SAT_RANGE_REG02 0x11 + + + #define CHROMA_GAIN_REG03 0x12 + #define HUE_HUE_RANGE_REG03 0x13 + #define HUE_RANGE_INV_REG03 0x14 + #define HUE_LUM_RANGE_REG03 0x15 + #define HUE_SAT_RANGE_REG03 0x16 + #define SAT_SAT_RANGE_REG03 0x17 + + #define CHROMA_GAIN_REG04 0x18 + #define HUE_HUE_RANGE_REG04 0x19 + #define HUE_RANGE_INV_REG04 0x1a + #define HUE_LUM_RANGE_REG04 0x1b + #define HUE_SAT_RANGE_REG04 0x1c + #define SAT_SAT_RANGE_REG04 0x1d + + #define CHROMA_GAIN_REG05 0x1e + #define HUE_HUE_RANGE_REG05 0x1f + #define HUE_RANGE_INV_REG05 0x20 + #define HUE_LUM_RANGE_REG05 0x21 + #define HUE_SAT_RANGE_REG05 0x22 + #define SAT_SAT_RANGE_REG05 0x23 + + #define CHROMA_GAIN_REG06 0x24 + #define HUE_HUE_RANGE_REG06 0x25 + #define HUE_RANGE_INV_REG06 0x26 + #define HUE_LUM_RANGE_REG06 0x27 + #define HUE_SAT_RANGE_REG06 0x28 + #define SAT_SAT_RANGE_REG06 0x29 + + #define CHROMA_GAIN_REG07 0x2a + #define HUE_HUE_RANGE_REG07 0x2b + #define HUE_RANGE_INV_REG07 0x2c + #define HUE_LUM_RANGE_REG07 0x2d + #define HUE_SAT_RANGE_REG07 0x2e + #define SAT_SAT_RANGE_REG07 0x2f + +// REG_CHROMA_CONTROL +// Bit 31 reg_chroma_en enable color manage function +// 1'b1: enable 1'b0: bypass +// Bit 6 sat_sel uv_max or u^2+v^2 selected as sat for reference +// 1'b1: uv_max(default) 1'b0: u^2+v^2 +// Bit 5 uv_adj_en final uv_adjust enable +// 1'b1: enable 1'b0: bypass +// Bit 2 hue_en rgb to hue enable +// 1'b1: enable(default) 1'b0: bypass +// Bit 1:0 csc_sel define input YUV with different color type +// 2'b00: 601(16-235) 2'b01: 709(16-235) +// 2'b10: 601(0-255) 2'b11: 709(0-255) + #define REG_CHROMA_CONTROL 0x30 // default 32h'80000024 + #define REG_DEMO_CENTER_BAR 0x31 // default 32h'0 + #define REG_DEMO_HLIGHT_MODE 0x32 // default 32h'0 + #define REG_DEMO_OWR_DATA 0x33 // default 32h'0 + + +////===========================================//// +//// CM2 ADDR +////===========================================//// + + #define SAT_BYYB_NODE_REG0 0x200 // default 32'h0 +//Bit 31:24, sat_byyb_node3 the 4th node +//Bit 23:16, sat_byyb_node2 the 3th node +//Bit 15: 8, sat_byyb_node1 signed, the 2th node about saturation +//Bit 7: 0, sat_byyb_node0 signed, the 1th node about saturation +//gain offset along y coordinate,the gain normalized to 128 as "1" + + #define SAT_BYYB_NODE_REG1 0x201 // default 32'h0 +//Bit 31:24, sat_byyb_node7 the 8th node +//Bit 23:16, sat_byyb_node6 the 7th node +//Bit 15: 8, sat_byyb_node5 signed, the 6th node about saturation +//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation +//gain offset along y coordinate,the gain normalized to 128 as "1" + + #define SAT_BYYB_NODE_REG2 0x202 // default 32'h0 +//Bit 31: 8, reserved +//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation + + + #define SAT_SRC_NODE_REG 0x203 // default 32'h0 +//Bit 31:28, reserved +//Bit 27:16, sat_src_node1 +//Bit 15:12, reserved +//Bit 11: 0, sat_src_node0 usigned, threshold of input saturation for first and second piece + + #define CM_ENH_SFT_MODE_REG 0x204 // default 32'h0 +//Bit 31: 9, reserved +//Bit 8: 6, hue_lsft_mode hue offset adjustments scale +//Bit 5: 4, luma_lsft_mode luma offset adjustments scale for reg_cm2_adj_luma_via_hue +//Bit 3: 2, sat_byy_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_y +//Bit 1: 0, sat_byhs_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_hs[:][:] 0:no scale up/down 1:dnscale by 2(-128,127)/2 + + #define FRM_SIZE_REG 0x205 // default 32'h0 +//Bit 31:29, reserved +//Bit 28:16, reg_frm_height the frame height size +//Bit 15:13, reserved +//Bit 12: 0, reg_frm_width the frame width size + + #define FITLER_CFG_REG 0x206 // default 32'h0 +//Bit 31: 5, reserved +//Bit 4: 4, inteleav_mod horizontal interleave filter(zero-padding) for 3D considerations 0:using non-zero padding lpf 1:using zero-padding lpf +//Bit 3: 2, lpf_slt_uv apply cm on lp portion or original video pixels options +//Bit 1: 0, lpf_slt_y apply cm on lp portion or original video pixels options + + #define CM_GLOBAL_GAIN_REG 0x207 // default 32'h0 +//Bit 31:28, reserved +//Bit 27:16, cm2_global_sat global saturation gain for general color adjustments(0~4095 <=> 0~8),512 normalized to "1" +//Bit 15:12, reserved +//Bit 11: 0, cm2_global_hue global hue offsets for general color adjustments(0~4095 <=> 0~360 degree) + + #define CM_ENH_CTL_REG 0x208 // default 32'h0 +//Bit 31:7, reserved +//Bit 6, hue_adj_en cm2 hue adjustments +//Bit 5, sat_adj_en cm2 saturation adjustments +//Bit 4, luma_adj_en enable siganl for cm2 luma adjustments +//Bit 3, reserved +//Bit 2, cm2_filt_en apply cm on lp portion enable +//Bit 1, cm2_en cm2 enable siganl +//Bit 0, cm1_en + + #define ROI_X_SCOPE_REG 0x209 // default 32'h0 +//Bit 31:29, reserved +//Bit 28:16, roi_x_end ending col index of the region of interest +//Bit 15:13, reserved +//Bit 12: 0, roi_x_beg start col index of the region of interest + + #define ROI_Y_SCOPE_REG 0x20a // default 32'h0 +//Bit 31:29, reserved +//Bit 28:16, roi_y_end ending row index of the region of interest +//Bit 15:13, reserved +//Bit 12: 0, roi_y_beg start row index of the region of interest + + #define POI_XY_DIR_REG 0x20b // default 32'h0 +//Bit 31:29, reserved +//Bit 28:16, poi_y_dir ending row index of the region of interest +//Bit 15:13, reserved +//Bit 12: 0, poi_x_dir start row index of the region of interest + + #define COI_Y_SCOPE_REG 0x20c // default 32'h0 +//Bit 31:16, reserved +//Bit 15: 8, coi_y_end +//Bit 7: 0, coi_y_beg + + #define COI_H_SCOPE_REG 0x20d // default 32'h0 +//Bit 31:28, reserved +//Bit 27:16, coi_h_end +//Bit 15:12, reserved +//Bit 11: 0, coi_h_beg lower bound of hue value for color of interest ,12 bits precision + + #define COI_S_SCOPE_REG 0x20e // default 32'h0 +//Bit 31:28, reserved +//Bit 27:16, coi_s_end +//Bit 15:12, reserved +//Bit 11: 0, coi_s_beg lower bound of sat value for color of interest ,12 bits precision + #define IFO_MODE_REG 0x20f // default 32'h0 +//Bit 31:8, reserved +//Bit 7:6, ifo_mode3 +//Bit 5:4, ifo_mode2 +//Bit 3:2, ifo_mode1 +//Bit 1:0, ifo_mode0 + #define POI_RPL_MODE_REG 0x210 // default 32'h0 +//Bit 31:4, reserved +//Bit 3:0, poi_rpl_mode enhance mode control of pixels inside and outside region of interest bit[3:2]control roi + #define DEMO_OWR_YHS_REG 0x211 // default 32'h0 +//Bit 31: 0, demo_owr_yhs + + #define DEMO_POI_Y_REG 0x212 // default 32'h0 +//Bit 31: 8, reserved +//Bit 7: 0, luma_data_poi_r only get locked higher 8bits + #define DEMO_POI_H_REG 0x213 // default 32'h0 +//Bit 31: 12, reserved +//Bit 11: 0, hue_data_poi_r only get locked higher 12bits + #define DEMO_POI_S_REG 0x214 // default 32'h0 +//Bit 31: 12, reserved +//Bit 11: 0, sat_data_poi_r only get locked higher 12bits + //`define LUMA_BYH_LIMT_REG 10'h215 // default 32'h0 + #define LUMA_ADJ_LIMT_REG 0x215 // default 32'h0 +//Bit 31:24, reserved +//Bit 23:16, luma_lmt_satslp slope to do the luma adjustment degrade +//Bit 15:12, reserved +//Bit 11:0, luma_lmt_satth threshold to saturation + #define SAT_ADJ_LIMT_REG 0x216 // default 32'h0 +//Bit 31:24, reserved +//Bit 23:16, sat_lmt_satslp slope to do the adjustment degrade +//Bit 15:12, reserved +//Bit 11:0, sat_lmt_satth threshold to saturation + #define HUE_ADJ_LIMT_REG 0x217 // default 32'h0 +//Bit 31: 24, reserved +//Bit 23: 16, hue_lmt_satslp slope to do the adjustment degrade +//Bit 15: 12, reserved +//Bit 11: 0, hue_lmt_satth threshold to saturation + #define UVHS_OFST_REG 0x218 // default 32'h0 +//Bit 31: 24, hs2uv_v_ofst +//Bit 23: 16, hs2uv_u_ofst +//Bit 15: 8, uv2hs_v_ofst +//Bit 7: 0, uv2hs_u_ofst + #define HUE_CFG_PARA_REG 0x219 // default 32'h0 +//Bit 31: 17, reserved +//Bit 16, hue_protect_en +//Bit 15: 13, cm2_hue_byhs_mode +//Bit 12, cm2_hue_div_mode +//Bit 11: 0, cm2_before_hue_ofst + #define DEMO_SPLT_CFG_REG 0x21a // default 32'h0 +//Bit 31: 22, reserved +//Bit 21: 20, demo_split_mode +//Bit 19: 16, demo_split_width slope to do the adjustment degrade +//Bit 15: 13, reserved +//Bit 12: 0, demo_split_post threshold to saturation + #define DEMO_SPLT_YHS_REG 0x21b // default 32'h0 +//Bit 31: 0, demo_splt_yhs threshold to saturation + + #define XVYCC_YSCP_REG 0x21c // default 32'h0 +//Bit 31: 28, reserved +//Bit 27: 16, xvycc_y_max +//Bit 15: 12, reserved +//Bit 11: 0, xvycc_y_min + #define XVYCC_USCP_REG 0x21d // default 32'h0 +//Bit 31: 28, reserved +//Bit 27: 16, xvycc_u_max +//Bit 15: 12, reserved +//Bit 11: 0, xvycc_u_min + #define XVYCC_VSCP_REG 0x21e // default 32'h0 +//Bit 31: 28, reserved +//Bit 27: 16, xvycc_v_max +//Bit 15: 12, reserved +//Bit 11: 0, xvycc_v_min + #define LUMA_ADJ0_REG 0x21f // default 32'h0 +//Bit 21: 12, reg_cm_luma_blacklevel +//Bit 11: 0, reg_cm_luma_contrast + #define LUMA_ADJ1_REG 0x220 // default 32'h0 + + #define STA_WIN_XYXY0_REG 0x221 // default 32'h0 + #define STA_WIN_XYXY1_REG 0x222 // default 32'h0 + #define STA_CFG_REG 0x223 // default 32'h0 + #define STA_SAT_HIST0_REG 0x224 // default 32'h0 + #define STA_SAT_HIST1_REG 0x225 // default 32'h0 + #define RO_CM_HUE_HIST_BIN0 0x226 // default 32'h0 + #define RO_CM_HUE_HIST_BIN1 0x227 // default 32'h0 + #define RO_CM_HUE_HIST_BIN2 0x228 // default 32'h0 + #define RO_CM_HUE_HIST_BIN3 0x229 // default 32'h0 + #define RO_CM_HUE_HIST_BIN4 0x22a // default 32'h0 + #define RO_CM_HUE_HIST_BIN5 0x22b // default 32'h0 + #define RO_CM_HUE_HIST_BIN6 0x22c // default 32'h0 + #define RO_CM_HUE_HIST_BIN7 0x22d // default 32'h0 + #define RO_CM_HUE_HIST_BIN8 0x22e // default 32'h0 + #define RO_CM_HUE_HIST_BIN9 0x22f // default 32'h0 + #define RO_CM_HUE_HIST_BIN10 0x230 // default 32'h0 + #define RO_CM_HUE_HIST_BIN11 0x231 // default 32'h0 + #define RO_CM_HUE_HIST_BIN12 0x232 // default 32'h0 + #define RO_CM_HUE_HIST_BIN13 0x233 // default 32'h0 + #define RO_CM_HUE_HIST_BIN14 0x234 // default 32'h0 + #define RO_CM_HUE_HIST_BIN15 0x235 // default 32'h0 + #define RO_CM_HUE_HIST_BIN16 0x236 // default 32'h0 + #define RO_CM_HUE_HIST_BIN17 0x237 // default 32'h0 + #define RO_CM_HUE_HIST_BIN18 0x238 // default 32'h0 + #define RO_CM_HUE_HIST_BIN19 0x239 // default 32'h0 + #define RO_CM_HUE_HIST_BIN20 0x23a // default 32'h0 + #define RO_CM_HUE_HIST_BIN21 0x23b // default 32'h0 + #define RO_CM_HUE_HIST_BIN22 0x23c // default 32'h0 + #define RO_CM_HUE_HIST_BIN23 0x23d // default 32'h0 + #define RO_CM_HUE_HIST_BIN24 0x23e // default 32'h0 + #define RO_CM_HUE_HIST_BIN25 0x23f // default 32'h0 + #define RO_CM_HUE_HIST_BIN26 0x240 // default 32'h0 + #define RO_CM_HUE_HIST_BIN27 0x241 // default 32'h0 + #define RO_CM_HUE_HIST_BIN28 0x242 // default 32'h0 + #define RO_CM_HUE_HIST_BIN29 0x243 // default 32'h0 + #define RO_CM_HUE_HIST_BIN30 0x244 // default 32'h0 + #define RO_CM_HUE_HIST_BIN31 0x245 // default 32'h0 + #define RO_CM_SAT_HIST_BIN0 0x246 // default 32'h0 + #define RO_CM_SAT_HIST_BIN1 0x247 // default 32'h0 + #define RO_CM_SAT_HIST_BIN2 0x248 // default 32'h0 + #define RO_CM_SAT_HIST_BIN3 0x249 // default 32'h0 + #define RO_CM_SAT_HIST_BIN4 0x24a // default 32'h0 + #define RO_CM_SAT_HIST_BIN5 0x24b // default 32'h0 + #define RO_CM_SAT_HIST_BIN6 0x24c // default 32'h0 + #define RO_CM_SAT_HIST_BIN7 0x24d // default 32'h0 + #define RO_CM_SAT_HIST_BIN8 0x24e // default 32'h0 + #define RO_CM_SAT_HIST_BIN9 0x24f // default 32'h0 + #define RO_CM_SAT_HIST_BIN10 0x250 // default 32'h0 + #define RO_CM_SAT_HIST_BIN11 0x251 // default 32'h0 + #define RO_CM_SAT_HIST_BIN12 0x252 // default 32'h0 + #define RO_CM_SAT_HIST_BIN13 0x253 // default 32'h0 + #define RO_CM_SAT_HIST_BIN14 0x254 // default 32'h0 + #define RO_CM_SAT_HIST_BIN15 0x255 // default 32'h0 + #define RO_CM_SAT_HIST_BIN16 0x256 // default 32'h0 + #define RO_CM_SAT_HIST_BIN17 0x257 // default 32'h0 + #define RO_CM_SAT_HIST_BIN18 0x258 // default 32'h0 + #define RO_CM_SAT_HIST_BIN19 0x259 // default 32'h0 + #define RO_CM_SAT_HIST_BIN20 0x25a // default 32'h0 + #define RO_CM_SAT_HIST_BIN21 0x25b // default 32'h0 + #define RO_CM_SAT_HIST_BIN22 0x25c // default 32'h0 + #define RO_CM_SAT_HIST_BIN23 0x25d // default 32'h0 + #define RO_CM_SAT_HIST_BIN24 0x25e // default 32'h0 + #define RO_CM_SAT_HIST_BIN25 0x25f // default 32'h0 + #define RO_CM_SAT_HIST_BIN26 0x260 // default 32'h0 + #define RO_CM_SAT_HIST_BIN27 0x261 // default 32'h0 + #define RO_CM_SAT_HIST_BIN28 0x262 // default 32'h0 + #define RO_CM_SAT_HIST_BIN29 0x263 // default 32'h0 + #define RO_CM_SAT_HIST_BIN30 0x264 // default 32'h0 + #define RO_CM_SAT_HIST_BIN31 0x265 // default 32'h0 + #define RO_CM_BLK_BIN 0x266 // default 32'h0 + #define RO_CM_BRT_BIN 0x267 // default 32'h0 + +////========= NODE 0 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H00 0x100 // default 32'H0 +//Bit 31: 24, reg_cm2_adj_sat_via_hs_2 +//Bit 23: 16, reg_cm2_adj_sat_via_hs_1 +//Bit 15: 8, reg_cm2_adj_sat_via_hs_0 +//Bit 7: 0, reg_cm2_adj_luma_via_h + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H00 0x101 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H00 0x102 // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H00 0x103 // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H00 0x104 // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 1 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H01 0x108 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H01 0x109 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H01 0x10a // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H01 0x10b // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H01 0x10c // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 2 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H02 0x110 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H02 0x111 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H02 0x112 // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H02 0x113 // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H02 0x114 // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 3 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H03 0x118 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H03 0x119 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H03 0x11a // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H03 0x11b // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H03 0x11c // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 4 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H04 0x120 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H04 0x121 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H04 0x122 // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H04 0x123 // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H04 0x124 // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 5 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H05 0x128 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H05 0x129 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H05 0x12a // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H05 0x12b // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H05 0x12c // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 6 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H06 0x130 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H06 0x131 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H06 0x132 // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H06 0x133 // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H06 0x134 // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 7 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H07 0x138 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H07 0x139 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H07 0x13a // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H07 0x13b // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H07 0x13c // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 8 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H08 0x140 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H08 0x141 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H08 0x142 // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H08 0x143 // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H08 0x144 // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 9 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H09 0x148 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H09 0x149 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H09 0x14a // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H09 0x14b // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H09 0x14c // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 10 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H10 0x150 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H10 0x151 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H10 0x152 // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H10 0x153 // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H10 0x154 // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 11 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H11 0x158 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H11 0x159 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H11 0x15a // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H11 0x15b // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H11 0x15c // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 12 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H12 0x160 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H12 0x161 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H12 0x162 // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H12 0x163 // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H12 0x164 // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + +////========= NODE 13 COEFFICIENT ==============//// + + #define REG_CM2_ENH_COEFF0_H13 0x168 // default 32'H0 + // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx + // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx + #define REG_CM2_ENH_COEFF1_H13 0x169 // default 32'H0 + // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx + // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx + #define REG_CM2_ENH_COEFF2_H13 0x16a // default 32'H0 + // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx + // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx + #define REG_CM2_ENH_COEFF3_H13 0x16b // default 32'H0 + // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx + // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx + #define REG_CM2_ENH_COEFF4_H13 0x16c // default 32'H0 + // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx + // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx + + +/* Constraints +0) + there are 16 regions totally. 8 regions are for hue adjustment, 8 regions are for sat adjustment. + the hue range of the 16 regions can be set to overlap, but if overlap, the hue range(start and end) must be same. + the 8 regions for hue adjustment should not overlap. if corresponding reg_hue_en_00 - 07 == 1 + the 8 regions for hue adjustment are defined by: (example are for region 0) + a) hue: + start: reg_hue_hue_shift_start_00[14:0] + end: + if reg_symmetry_en_00 == 0 + reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5) + if reg_symmetry_en_00 == 1 + reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6) + b) sat: + start: reg_hue_sat_low_00 + end: reg_hue_sat_high_00 + + the 8 regions for sat adjustment should not overlap. if corresponding reg_sat_en_00 - 07 == 1 + the 8 regions for sat adjustment are defined by: (example are for region 0) + a) hue: same as that for hue adjustment. + start: reg_hue_hue_shift_start_00[14:0] + end: + if reg_symmetry_en_00 == 0 + reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5) + if reg_symmetry_en_00 == 1 + reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6) + b) sat: + start: reg_sat_sat_low_00 + end: reg_sat_sat_high_00 + +1) + reg_hue_hue_shift_range_00[7:0]: + reg_hue_hue_shift_range_01[7:0]: + reg_hue_hue_shift_range_02[7:0]: + reg_hue_hue_shift_range_03[7:0]: + reg_hue_hue_shift_range_04[7:0]: + reg_hue_hue_shift_range_05[7:0]: + reg_hue_hue_shift_range_06[7:0]: + reg_hue_hue_shift_range_07[7:0]: + must be greater or equal than 8'd8, so as reg_hue_range_inv_regxx can be represented by 0.0000_0000_xxxx_xxxx_xxxx_xxxx + +2) + all regions of 0-7 should meet below requirement. below is just an example for region 7. + (reg_hue_lum_high_07 - reg_hue_lum_low_07) >= + (1<<reg_hue_lum_low_slope_07) + (1<<reg_hue_lum_high_slope_07) + + (reg_hue_sat_high_07 - reg_hue_sat_low_07) >= + (1<<reg_hue_sat_low_slope_07) + (1<<reg_hue_sat_high_slope_07) + + (reg_sat_lum_high_07 - reg_sat_lum_low_07) >= + (1<<reg_sat_lum_low_slope_07) + (1<<reg_sat_lum_high_slope_07) + + (reg_sat_sat_high_07 - reg_sat_sat_low_07) >= + (1<<reg_sat_sat_low_slope_07) + (1<<reg_sat_sat_high_slope_07) + +3) + all of reg_hue_hue_shift_start_00[14:0] ~ 07[14:0] < 0x6000. + only region 0 and 1 can exceed 360 degrees. ie: + reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) can greater than 0x6000. + reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_01<<5) can greater than 0x6000. + but below should be met: + reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0 + reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0 + reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1 + reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1 + + others could not exceed 360 degrees. ie: + reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<5) < 0x6000. if reg_symmetry_en_02 (to 7) == 0. + reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<6) < 0x6000. if reg_symmetry_en_02 (to 7) == 1. + +4) + reg_hue_gain_00[7:0] <= 0x80. + reg_hue_gain_01[7:0] <= 0x80. + reg_hue_gain_02[7:0] <= 0x80. + reg_hue_gain_03[7:0] <= 0x80. + reg_hue_gain_04[7:0] <= 0x80. + reg_hue_gain_05[7:0] <= 0x80. + reg_hue_gain_06[7:0] <= 0x80. + reg_hue_gain_07[7:0] <= 0x80. + +5) + below registers can only have two setting: 00 and 01. + reg_hue_central_en_00[1:0] .. _07[1:0] + reg_sat_central_en_00[1:0] .. _07[1:0] + +6) + all reg_..._slope_00-07 should not be greater than 7, ie: maximum value is 7. + for example: below is for region 0: + reg_hue_lum_low_slope_00[3:0] <= 7 + reg_hue_lum_high_slope_00[3:0] <= 7 + reg_hue_sat_low_slope_00[3:0] <= 7 + reg_hue_sat_high_slope_00[3:0] <= 7 + reg_sat_lum_low_slope_00[3:0] <= 7 + reg_sat_lum_high_slope_00[3:0] <= 7 + reg_sat_sat_low_slope_00[3:0] <= 7 + reg_sat_sat_high_slope_00[3:0] <= 7 +*/ + +// synopsys translate_off +// synopsys translate_on +// +// Closing file: chroma_reg.h +// +//(hsvsharp), (blue), gainoff, mat_vd1,mat_vd2, mat_post, prebld, postbld,(hsharp),sco_ff, vadj1, vadj2, ofifo, (chroma1), clk0(free_clk) vpp_reg +//each item 2bits, for each 2bits, if bit 2*i+1 == 1, free clk, else if bit 2*i == 1 no clk, else auto gated clock +//bit1 is not used, because I can not turn off vpp_reg clk because I can not turn on again +//because the register itself canot be set again without clk +//Bit 31:0 +#define VPP_GCLK_CTRL0 ((0x1d72 << 2) + 0xff000000) +//(front_lti), (front_cti), Chroma2_filter, Chroma2, (Ccoring), (blackext), dnlp +//Bit 13:0 +#define VPP_GCLK_CTRL1 ((0x1d73 << 2) + 0xff000000) +//prehsc_clk, line_buf, prevsc, vsc, hsc_clk, clk0(free_clk) +//Bit 11:0 +#define VPP_SC_GCLK_CTRL ((0x1d74 << 2) + 0xff000000) +//Bit 17:9 VD1 alpha for preblend +//Bit 8:0 VD1 alpha for postblend +#define VPP_MISC1 ((0x1d76 << 2) + 0xff000000) +//Bit 31:0 super scalar clock control +#define VPP_SRSCL_GCLK_CTRL ((0x1d77 << 2) + 0xff000000) +//Bit 31:0 OSD super scalar clock control +#define VPP_OSDSR_GCLK_CTRL ((0x1d78 << 2) + 0xff000000) +//Bit 31:0 vvycc clock control +#define VPP_XVYCC_GCLK_CTRL ((0x1d79 << 2) + 0xff000000) +//Bit 31:24 blackext_start +//Bit 23:16 blackext_slope1 +//Bit 15:8 blackext_midpt +//Bit 7:0 blackext_slope2 +#define VPP_BLACKEXT_CTRL ((0x1d80 << 2) + 0xff000000) +//Bit 31:24 bottom of region03 output value +//Bit 23:16 bottom of region02 output value +//Bit 15:8 bottom of region01 output value +//Bit 7:0 bottom of region00 output value +#define VPP_DNLP_CTRL_00 ((0x1d81 << 2) + 0xff000000) +//Bit 31:24 bottom of region07 output value +//Bit 23:16 bottom of region06 output value +//Bit 15:8 bottom of region05 output value +//Bit 7:0 bottom of region04 output value +#define VPP_DNLP_CTRL_01 ((0x1d82 << 2) + 0xff000000) +//Bit 31:24 bottom of region11 output value +//Bit 23:16 bottom of region10 output value +//Bit 15:8 bottom of region09 output value +//Bit 7:0 bottom of region08 output value +#define VPP_DNLP_CTRL_02 ((0x1d83 << 2) + 0xff000000) +//Bit 31:24 bottom of region15 output value +//Bit 23:16 bottom of region14 output value +//Bit 15:8 bottom of region13 output value +//Bit 7:0 bottom of region12 output value +#define VPP_DNLP_CTRL_03 ((0x1d84 << 2) + 0xff000000) +//Bit 31:24 bottom of region19 output value +//Bit 23:16 bottom of region18 output value +//Bit 15:8 bottom of region17 output value +//Bit 7:0 bottom of region16 output value +#define VPP_DNLP_CTRL_04 ((0x1d85 << 2) + 0xff000000) +//Bit 31:24 bottom of region23 output value +//Bit 23:16 bottom of region22 output value +//Bit 15:8 bottom of region21 output value +//Bit 7:0 bottom of region20 output value +#define VPP_DNLP_CTRL_05 ((0x1d86 << 2) + 0xff000000) +//Bit 31:24 bottom of region27 output value +//Bit 23:16 bottom of region26 output value +//Bit 15:8 bottom of region25 output value +//Bit 7:0 bottom of region24 output value +#define VPP_DNLP_CTRL_06 ((0x1d87 << 2) + 0xff000000) +//Bit 31:24 bottom of region31 output value +//Bit 23:16 bottom of region30 output value +//Bit 15:8 bottom of region29 output value +//Bit 7:0 bottom of region28 output value +#define VPP_DNLP_CTRL_07 ((0x1d88 << 2) + 0xff000000) +//Bit 31:24 bottom of region35 output value +//Bit 23:16 bottom of region34 output value +//Bit 15:8 bottom of region33 output value +//Bit 7:0 bottom of region32 output value +#define VPP_DNLP_CTRL_08 ((0x1d89 << 2) + 0xff000000) +//Bit 31:24 bottom of region39 output value +//Bit 23:16 bottom of region38 output value +//Bit 15:8 bottom of region37 output value +//Bit 7:0 bottom of region36 output value +#define VPP_DNLP_CTRL_09 ((0x1d8a << 2) + 0xff000000) +//Bit 31:24 bottom of region43 output value +//Bit 23:16 bottom of region42 output value +//Bit 15:8 bottom of region41 output value +//Bit 7:0 bottom of region40 output value +#define VPP_DNLP_CTRL_10 ((0x1d8b << 2) + 0xff000000) +//Bit 31:24 bottom of region47 output value +//Bit 23:16 bottom of region46 output value +//Bit 15:8 bottom of region45 output value +//Bit 7:0 bottom of region44 output value +#define VPP_DNLP_CTRL_11 ((0x1d8c << 2) + 0xff000000) +//Bit 31:24 bottom of region51 output value +//Bit 23:16 bottom of region50 output value +//Bit 15:8 bottom of region49 output value +//Bit 7:0 bottom of region48 output value +#define VPP_DNLP_CTRL_12 ((0x1d8d << 2) + 0xff000000) +//Bit 31:24 bottom of region55 output value +//Bit 23:16 bottom of region54 output value +//Bit 15:8 bottom of region53 output value +//Bit 7:0 bottom of region52 output value +#define VPP_DNLP_CTRL_13 ((0x1d8e << 2) + 0xff000000) +//Bit 31:24 bottom of region59 output value +//Bit 23:16 bottom of region58 output value +//Bit 15:8 bottom of region57 output value +//Bit 7:0 bottom of region56 output value +#define VPP_DNLP_CTRL_14 ((0x1d8f << 2) + 0xff000000) +//Bit 31:24 bottom of region63 output value +//Bit 23:16 bottom of region62 output value +//Bit 15:8 bottom of region61 output value +//Bit 7:0 bottom of region60 output value +#define VPP_DNLP_CTRL_15 ((0x1d90 << 2) + 0xff000000) +// `define VPP_PEAKING_HGAIN 8'h91 //32'h0 +// `define VPP_PEAKING_VGAIN 8'h92 //32'h0 +// `define VPP_PEAKING_NLP_1 8'h93 //32'h0 +// `define VPP_PEAKING_NLP_2 8'h94 //32'h0 +// `define VPP_PEAKING_NLP_3 8'h95 //32'h0 +// `define VPP_PEAKING_NLP_4 8'h96 //32'h0 +// `define VPP_PEAKING_NLP_5 8'h97 //32'h0 +// `define VPP_SHARP_LIMIT 8'h98 //32'h0 +// `define VPP_VLTI_CTRL 8'h99 //32'h0 +// `define VPP_HLTI_CTRL 8'h9a //32'h0 +// `define VPP_CTI_CTRL 8'h9b //32'h0 +#define VPP_SRSHARP0_CTRL ((0x1d91 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width +//Bit 15:6 reserved +//Bit 5:4 srsharp_demo_disp_post srsharp demo display postion +//Bit 3 srsharp_demo_en srsharp demo enable +//Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable +//Bit 1, srsharp_buf_en srsharp buffer enable +//Bit 0, srsharp_en srsharp enable +#define VPP_SRSHARP1_CTRL ((0x1d92 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width +//Bit 15:6 reserved +//Bit 5:4 srsharp_demo_disp_post srsharp demo display postion +//Bit 3 srsharp_demo_en srsharp demo enable +//Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable +//Bit 1, srsharp_buf_en srsharp buffer enable +//Bit 0, srsharp_en srsharp enable +#define VPP_DOLBY_CTRL ((0x1d93 << 2) + 0xff000000) +//todo +#define VPP_DAT_CONV_PARA0 ((0x1d94 << 2) + 0xff000000) +#define VPP_DAT_CONV_PARA1 ((0x1d95 << 2) + 0xff000000) +//todo +#define VPP_SYNC_SEL0 ((0x1d96 << 2) + 0xff000000) +//`define VPP_VADJ1_BLACK_VAL 8'h97 //32'h0 +//`define VPP_VADJ2_BLACK_VAL 8'h98 //32'h0 +//Bit 29 blue_stretch_cb_inc +//Bit 28 blue_stretch_cr_inc +//Bit 27 the MSB of blue_stretch_error_crp_inv[11:0] +//Bit 26 the MSB of blue_stretch_error_crn_inv[11:0] +//Bit 25 the MSB of blue_stretch_error_cbp_inv[11:0] +//Bit 24 the MSB of blue_stretch_error_cbn_inv[11:0] +//Bit 23:16 blue_stretch_gain +//Bit 15:8 blue_stretch_gain_cb4cr +//Bit 7:0 blue_stretch_luma_high +#define VPP_BLUE_STRETCH_1 ((0x1d9c << 2) + 0xff000000) +//Bit 31:27 blue_stretch_error_crp +//Bit 26:16 the 11 LSB of blue_stretch_error_crp_inv[11:0] +//Bit 15:11 blue_stretch_error_crn +//Bit 10:0 the 11 LSB of blue_stretch_error_crn_inv[11:0] +#define VPP_BLUE_STRETCH_2 ((0x1d9d << 2) + 0xff000000) +//Bit 31:27 blue_stretch_error_cbp +//Bit 26:16 the 11 LSB of blue_stretch_error_cbp_inv[11:0] +//Bit 15:11 blue_stretch_error_cbn +//Bit 10:0 the 11 LSB of blue_stretch_error_cbn_inv[11:0] +#define VPP_BLUE_STRETCH_3 ((0x1d9e << 2) + 0xff000000) +#define VPP_CCORING_CTRL ((0x1da0 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 reg_bypass_ccoring_ythd // unsigned , default = 0 bypass_ccoring_ythd +//Bit 15:8 ccoring_th // unsigned , default = 0 Chroma coring threshold +//Bit 7:0 reserved +//Bit 3:0 ccoring_slope // unsigned , default = 0 Chroma coring slope +#define VPP_VE_ENABLE_CTRL ((0x1da1 << 2) + 0xff000000) +//Bit 31:21 reserved +//Bit 20 demo_ccoring_enable // unsigned , default = 0 demo chroma coring enable +//Bit 19 demo_blackext_enable // unsigned , default = 0 demo black enxtension enable +//Bit 18 demo_dnlp_enable // unsigned , default = 0 demo dynamic nonlinear luma processing enable +//Bit 17 demo_hsvsharp_enable // unsigned , default = 0 demo hsvsharp enable +//Bit 16 demo_bluestretch_enable // unsigned , default = 0 demo bluestretch enable +//Bit 15:14 demo_disp_position // unsigned , default = 0 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, 2'b10: demo adjust on left, 2'b11: demo adjust on right +//Bit 13:7 reserved +//Bit 6 sr4c0_path_sel // unsigned , default = 0 +//Bit 5 srscl_path_sel // unsigned , default = 0 +//Bit 4 ccoring_en // unsigned , default = 0 chroma coring enable +//Bit 3 blackext_en // unsigned , default = 0 black enxtension enable +//Bit 2 dnlp_en // unsigned , default = 0 dynamic nonlinear luma processing enable +//Bit 1 hsvsharp_en // unsigned , default = 0 hsvsharp enable +//Bit 0 blue_stretch_en // unsigned , default = 0 bluestretch enable +#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH ((0x1da2 << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 ve_demo_left_top_screen_width // unsigned , default = 0 demo left or top screen width +#define VPP_VE_DEMO_CENTER_BAR ((0x1da3 << 2) + 0xff000000) + //Bit 31 ve_demo_center_bar // unsigned , default = 0 center bar enable + //Bit 27:24 ve_demo_center_bar // unsigned , default = 0 center bar width (*2) + //Bit 23:16 ve_demo_center_bar // unsigned , default = 0 center bar Cr (*4) + //Bit 15:8 ve_demo_center_bar // unsigned , default = 0 center bar Cb (*4) + //Bit 7:0 ve_demo_center_bar // unsigned , default = 0 center bar y (*4) +#define VPP_VE_H_V_SIZE ((0x1da4 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 ve_line_length // unsigned , default = 780 ve_line_length +//Bit 15:13 reserved +//Bit 12:0 ve_pic_height // unsigned , default = 438 ve_pic_height +#define VPP_OUT_H_V_SIZE ((0x1da5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 vppout_line_length / unsigned , default = 780 vppout_line_length +//Bit 15:13 reserved +//Bit 12:0 vppout_pic_height // unsigned , default = 438 vppout_pic_height +#define VPP_IN_H_V_SIZE ((0x1da6 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 vppin_line_length / unsigned , default = 780 vppout_line_length +//Bit 15:13 reserved +//Bit 12:0 vppin_pic_height // unsigned , default = 438 vppout_pic_height +#define VPP_VDO_MEAS_CTRL ((0x1da8 << 2) + 0xff000000) +//Bit 31:11 reserved +//Bit 10:0 vdo_meas_ctrl // unsigned , default = 0 vdo_meas_ctrl +//Read only +//19:16 ind_meas_count_n, every number of sync_span vsyncs, this counter add 1 +//15:0, high bit portion of counter +#define VPP_VDO_MEAS_VS_COUNT_HI ((0x1da9 << 2) + 0xff000000) +//Read only +//31:0, low bit portion of counter +#define VPP_VDO_MEAS_VS_COUNT_LO ((0x1daa << 2) + 0xff000000) +//bit 11:9 vd2_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection +//bit 8:6 vd1_l_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection +//bit 5:3 vd1_r_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection +//note: the source vd1_l_sel selected cannot be used as the source of vd1_r_sel or vd2_sel +// vd1_r_sel is useful only vd1_interleave_mode is not 00. And the source vd1_r_sel used can not used for the vd2_sel any more. +//bit 2:0 vd1_interleave_mode, 000: no interleave, 001: pixel interleaving, 010: line interleaving, 011: 2 pixel interleaving, +// 100: 2 line interleaving +#define VPP_INPUT_CTRL ((0x1dab << 2) + 0xff000000) +//bit 25:24 cti_bpf_sel +//bit 20:16 cti_blend_factor_gama +//bit 12:8 cti_blend_factor_beta +//bit 4:0 cti_blend_factor_alpha +#define VPP_CTI_CTRL2 ((0x1dac << 2) + 0xff000000) +// `define VPP_PEAKING_SAT_THD1 8'had +// `define VPP_PEAKING_SAT_THD2 8'hae +// `define VPP_PEAKING_SAT_THD3 8'haf +// `define VPP_PEAKING_SAT_THD4 8'hb0 +// `define VPP_PEAKING_SAT_THD5 8'hb1 +// `define VPP_PEAKING_SAT_THD6 8'hb2 +// `define VPP_PEAKING_SAT_THD7 8'hb3 +// `define VPP_PEAKING_SAT_THD8 8'hb4 +// `define VPP_PEAKING_SAT_THD9 8'hb5 +// `define VPP_PEAKING_GAIN_ADD1 8'hb6 +// `define VPP_PEAKING_GAIN_ADD2 8'hb7 +#define VPP_WRBAK_CTRL_SEC ((0x1dad << 2) + 0xff000000) +#define VD1_BLEND_SRC_CTRL_SEC ((0x1dae << 2) + 0xff000000) +#define VD2_BLEND_SRC_CTRL_SEC ((0x1daf << 2) + 0xff000000) +#define OSD1_BLEND_SRC_CTRL_SEC ((0x1db0 << 2) + 0xff000000) +#define OSD2_BLEND_SRC_CTRL_SEC ((0x1db1 << 2) + 0xff000000) +//crc check , new add +#define VPP_RO_CRCSUM ((0x1db2 << 2) + 0xff000000) +#define VPP_CRC_CHK ((0x1db3 << 2) + 0xff000000) +//bit 23:16 peaking_dnlp_gain, u5.3, DNLP effect +//bit 15:8 peaking_factor +//bit 5 peaking_dnlp_demo_en +//bit 4 peaking_dnlp_en +//bit 3:0 peaking_filter_sel +#define VPP_PEAKING_DNLP ((0x1db8 << 2) + 0xff000000) +//bit 24 sharp_demo_win_en +//bit 23:12 sharp_demo_win_vend +//bit 11:0 sharp_demo_win_vstart +#define VPP_SHARP_DEMO_WIN_CTRL1 ((0x1db9 << 2) + 0xff000000) +//bit 23:12 sharp_demo_win_hend +//bit 11:0 sharp_demo_win_hstart +#define VPP_SHARP_DEMO_WIN_CTRL2 ((0x1dba << 2) + 0xff000000) +//Bit 31:24 front_hlti_neg_gain +//Bit 23:16 front_hlti_pos_gain +//Bit 15:8 front_hlti_threshold +//Bit 7:0 front_hlti_blend_factor +#define VPP_FRONT_HLTI_CTRL ((0x1dbb << 2) + 0xff000000) +//Bit 31 front_enable, enable the front LTI&CTI before scaler +//Bit 26:24 front_cti_step2 +//Bit 23:21 front_cti_step +//Bit 20:16 front_cti_blend_factor +//Bit 15 front_cti_median_mode +//Bit 14:8 front_cti_threshold +//Bit 7:0 front_cti_gain +#define VPP_FRONT_CTI_CTRL ((0x1dbc << 2) + 0xff000000) +//bit 29:28 front_hlti_step +//bit 25:24 front_cti_bpf_sel +//bit 20:16 front_cti_blend_factor_gama +//bit 12:8 front_cti_blend_factor_beta +//bit 4:0 front_cti_blend_factor_alpha +#define VPP_FRONT_CTI_CTRL2 ((0x1dbd << 2) + 0xff000000) +//vertical scaler phase step +//Bit 27:0, 4.24 format +#define VPP_OSD_VSC_PHASE_STEP ((0x1dc0 << 2) + 0xff000000) +//Bit 31:16, botttom vertical scaler initial phase +//Bit 15:0, top vertical scaler initial phase +#define VPP_OSD_VSC_INI_PHASE ((0x1dc1 << 2) + 0xff000000) +//Bit 24 osd vertical Scaler enable +//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace +//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines +//Bit 20 osd_vsc_phase0_always_en +//Bit 19 osd_vsc_nearest_en +//Bit 17:16 osd_vsc_bot_rpt_l0_num +//Bit 14:11 osd_vsc_bot_ini_rcv_num +//Bit 9:8 osd_vsc_top_rpt_l0_num +//Bit 6:3 osd_vsc_top_ini_rcv_num +//Bit 2:0 osd_vsc_bank_length +#define VPP_OSD_VSC_CTRL0 ((0x1dc2 << 2) + 0xff000000) +//horizontal scaler phase step +//Bit 27:0, 4.24 format +#define VPP_OSD_HSC_PHASE_STEP ((0x1dc3 << 2) + 0xff000000) +//Bit 31:16, horizontal scaler initial phase1 +//Bit 15:0, horizontal scaler initial phase0 +#define VPP_OSD_HSC_INI_PHASE ((0x1dc4 << 2) + 0xff000000) +//Bit 22 osd horizontal scaler enable +//Bit 21 osd_hsc_double_pix_mode +//Bit 20 osd_hsc_phase0_always_en +//Bit 19 osd_hsc_nearest_en +//Bit 17:16 osd_hsc_rpt_p0_num1 +//Bit 14:11 osd_hsc_ini_rcv_num1 +//Bit 9:8 osd_hsc_rpt_p0_num0 +//Bit 6:3 osd_hsc_ini_rcv_num0 +//Bit 2:0 osd_hsc_bank_length +#define VPP_OSD_HSC_CTRL0 ((0x1dc5 << 2) + 0xff000000) +//for 3D quincunx sub-sampling +//bit 15:8 pattern, each patten 1 bit, from lsb -> msb +//bit 6:4 pattern start +//bit 2:0 pattern end +#define VPP_OSD_HSC_INI_PAT_CTRL ((0x1dc6 << 2) + 0xff000000) +//bit 31:24, componet 0 +//bit 23:16, component 1 +//bit 15:8, component 2 +//bit 7:0 component 3, alpha +#define VPP_OSD_SC_DUMMY_DATA ((0x1dc7 << 2) + 0xff000000) +//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. +//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. +//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. +//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. +//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source +//Bit 3 osd scaler path enable +//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix +#define VPP_OSD_SC_CTRL0 ((0x1dc8 << 2) + 0xff000000) +//Bit 28:16 OSD scaler input width minus 1 +//Bit 12:0 OSD scaler input height minus 1 +#define VPP_OSD_SCI_WH_M1 ((0x1dc9 << 2) + 0xff000000) +//Bit 28:16 OSD scaler output horizontal start +//Bit 12:0 OSD scaler output horizontal end +#define VPP_OSD_SCO_H_START_END ((0x1dca << 2) + 0xff000000) +//Bit 28:16 OSD scaler output vertical start +//Bit 12:0 OSD scaler output vertical end +#define VPP_OSD_SCO_V_START_END ((0x1dcb << 2) + 0xff000000) +//Because there are many coefficients used in the vertical filter and horizontal filters, +//indirect access the coefficients of vertical filter and horizontal filter is used. +//For vertical filter, there are 33x4 coefficients +//For horizontal filter, there are 33x4 coefficients +//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2) +//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not +//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef +//Bit 8 type of index, 0: vertical coef, 1: horizontal coef +//Bit 6:0 coef index +#define VPP_OSD_SCALE_COEF_IDX ((0x1dcc << 2) + 0xff000000) +//coefficients for vertical filter and horizontal filter +#define VPP_OSD_SCALE_COEF ((0x1dcd << 2) + 0xff000000) +//Bit 12:0 line number use to generate interrupt when line == this number +#define VPP_INT_LINE_NUM ((0x1dce << 2) + 0xff000000) +#define VPP_XVYCC_MISC ((0x1dcf << 2) + 0xff000000) +// new add lti/cti in 120924 +//Bit 3: 0 //default== 0 reg_hlti_dn_flt_coe[0] +//Bit 7: 4 //default== 0 reg_hlti_dn_flt_coe[1] +//Bit 11: 8 //default== 0 reg_hlti_dn_flt_coe[2] +//Bit 15:12 //default== 2 reg_hlti_dn_flt_coe[3] +//Bit 19:16 //default== 4 reg_hlti_dn_flt_coe[4] +//Bit 22:20 //default== 3 reg_hlti_dn_flt_nrm u3: 3~7 +#define VPP_HLTI_DN_FLT ((0x1dd0 << 2) + 0xff000000) +//Bit 7: 0 //default== 8 reg_hlti_bst_gain u8, norm 16 as "1" +//Bit 15: 8 //default== 20 reg_hlti_bst_core u8, norm 32 as "1" +//Bit 23:16 //default== 32 reg_hlti_oob_gain u8, norm 32 as "1" +//Bit 28:24 //default== 0 reg_hlti_oob_core u5 +#define VPP_HLTI_GAIN ((0x1dd1 << 2) + 0xff000000) +//Bit 7: 0 //default== 2 reg_hlti_clp_ofst u8, +//Bit 8 //default== 0 reg_hlti_clp_mode u1, +//Bit 11: 9 //default== 1 reg_hlti_clp_wind u3, +//Bit 14:12 //default== 1 reg_hlti_bst_fltr u3, +//Bit 15 //default== 1 reg_hlti_enable u1, +#define VPP_HLTI_PARA ((0x1dd2 << 2) + 0xff000000) +//Bit 3: 0 //default== 0 reg_hcti_dn_flt_coe[0] +//Bit 7: 4 //default== 0 reg_hcti_dn_flt_coe[1] +//Bit 11: 8 //default== 1 reg_hcti_dn_flt_coe[2] +//Bit 15:12 //default== 2 reg_hcti_dn_flt_coe[3] +//Bit 19:16 //default== 2 reg_hcti_dn_flt_coe[4] +//Bit 22:20 //default== 3 reg_hcti_dn_flt_nrm u3: 3~7 +#define VPP_HCTI_DN_FLT ((0x1dd3 << 2) + 0xff000000) +//Bit 7: 0 //default== 48 reg_hcti_bst_gain u8, norm 16 as "1" +//Bit15: 8 //default== 17 reg_hcti_bst_core u8, norm 32 as "1" +//Bit23:16 //default== 16 reg_hcti_oob_gain u8, norm 32 as "1" +//Bit28:24 //default== 0 reg_hcti_oob_core u5 +#define VPP_HCTI_GAIN ((0x1dd4 << 2) + 0xff000000) +//Bit 7: 0 //default== 0 reg_hcti_clp_ofst u8, +//Bit 8 //default== 1 reg_hcti_clp_mode u1, +//Bit 11: 9 //default== 3 reg_hcti_clp_wind u3, +//Bit 14:12 //default== 6 reg_hcti_bst_fltr u3, +//Bit 15 //default== 1 reg_hcti_enable u1, +#define VPP_HCTI_PARA ((0x1dd5 << 2) + 0xff000000) +//Bit 7: 0 //default== 48 reg_vcti_bst_gain u8, normalize 16 as "1" +//Bit 15: 8 //default== 10 reg_vcti_bst_core u8 +//Bit 19:16 //default== 10 reg_vcti_clp_ofst u4 +//Bit 20 //default== 1 reg_vcti_clp_wind u1, 0: wind 3, 1: wind5 +#define VPP_VCTI_PARA ((0x1dd6 << 2) + 0xff000000) +//`define VPP_MATRIX_PROBE_COLOR1 8'hd7 //defined before +//Bit 31 //default== 0, urgent fifo hold enable +//Bit 28:12 //default== 0, urgent fifo hold line threshold +//Bit 15 //default== 0, urgent_ctrl_en +//Bit 14 //default== 0, urgent_wr, if true for write buffer +//Bit 13 //default== 0, out_inv_en +//Bit 12 //default == 0, urgent_ini_value +//Bit 11:6 //default == 0, up_th up threshold +//Bit 5:0 //default == 0, dn_th dn threshold +#define VPP_OFIFO_URG_CTRL ((0x1dd8 << 2) + 0xff000000) +#define VPP_CLIP_MISC0 ((0x1dd9 << 2) + 0xff000000) +//Bit 29:20 // default == 1023, final clip r channel top +//Bit 19:10 // default == 1023, final clip g channel top +//Bit 9: 0 // default == 1023, final clip b channel top +#define VPP_CLIP_MISC1 ((0x1dda << 2) + 0xff000000) +//Bit 29:20 // default == 0, final clip r channel bottom +//Bit 19:10 // default == 0, final clip g channel bottom +//Bit 9: 0 // default == 0, final clip b channel bottom +#define VPP_MATRIX_COEF13_14 ((0x1ddb << 2) + 0xff000000) +//Bit 28:16 // default == 0, matrix coef13 +//Bit 12:0 // default == 0, matrix coef14 +#define VPP_MATRIX_COEF23_24 ((0x1ddc << 2) + 0xff000000) +//Bit 28:16 // default == 0, matrix coef23 +//Bit 12:0 // default == 0, matrix coef24 +#define VPP_MATRIX_COEF15_25 ((0x1ddd << 2) + 0xff000000) +//Bit 28:16 // default == 0, matrix coef15 +//Bit 12:0 // default == 0, matrix coef25 +#define VPP_MATRIX_CLIP ((0x1dde << 2) + 0xff000000) +//Bit 7:5 // default == 0, mat rs +//Bit 4:3 // default == 0, mat clmod +//Bit 2:0 // default == 0, mat clip enable +#define VPP_XVYCC_MISC0 ((0x1ddf << 2) + 0xff000000) +//Bit 29:20 // default == 1023, xvycc clip r channel top +//Bit 19:10 // default == 1023, xvycc clip g channel top +//Bit 9: 0 // default == 1023, xvycc clip b channel top +#define VPP_XVYCC_MISC1 ((0x1de0 << 2) + 0xff000000) +//Bit 29:20 // default == 0, xvycc clip r channel bottom +//Bit 19:10 // default == 0, xvycc clip g channel bottom +//Bit 9: 0 // default == 0, xvycc clip b channel bottom +#define VPP_VD1_CLIP_MISC0 ((0x1de1 << 2) + 0xff000000) +//Bit 29:20 // default == 1023, vd1 clip r channel top +//Bit 19:10 // default == 1023, vd1 clip g channel top +//Bit 9: 0 // default == 1023, vd1 clip b channel top +#define VPP_VD1_CLIP_MISC1 ((0x1de2 << 2) + 0xff000000) +//Bit 29:20 // default == 0, vd1 clip r channel bottom +//Bit 19:10 // default == 0, vd1 clip g channel bottom +//Bit 9: 0 // default == 0, vd1 clip b channel bottom +#define VPP_VD2_CLIP_MISC0 ((0x1de3 << 2) + 0xff000000) +//Bit 29:20 // default == 1023, vd2 clip r channel top +//Bit 19:10 // default == 1023, vd2 clip g channel top +//Bit 9: 0 // default == 1023, vd2 clip b channel top +#define VPP_VD2_CLIP_MISC1 ((0x1de4 << 2) + 0xff000000) +//Bit 29:20 // default == 0, vd2 clip r channel bottom +//Bit 19:10 // default == 0, vd2 clip g channel bottom +//Bit 9: 0 // default == 0, vd2 clip b channel bottom +#define VPP_VD2_HDR_IN_SIZE ((0x1df0 << 2) + 0xff000000) +//Bit 31:16 // default == 0 +//Bit 15:0 // default == 0 +#define VPP_OSD1_IN_SIZE ((0x1df1 << 2) + 0xff000000) +//Bit 31:16 // default == 0 +//Bit 15:0 // default == 0 +#define VPP_GCLK_CTRL2 ((0x1df2 << 2) + 0xff000000) +//`define VPP_BLEND_SRC_SEL 8'hf3 +#define VD2_PPS_DUMMY_DATA ((0x1df4 << 2) + 0xff000000) +#define VPP_OSD1_BLD_H_SCOPE ((0x1df5 << 2) + 0xff000000) +#define VPP_OSD1_BLD_V_SCOPE ((0x1df6 << 2) + 0xff000000) +#define VPP_OSD2_BLD_H_SCOPE ((0x1df7 << 2) + 0xff000000) +#define VPP_OSD2_BLD_V_SCOPE ((0x1df8 << 2) + 0xff000000) +#define VPP_WRBAK_CTRL ((0x1df9 << 2) + 0xff000000) +#define VPP_SLEEP_CTRL ((0x1dfa << 2) + 0xff000000) +#define VD1_BLEND_SRC_CTRL ((0x1dfb << 2) + 0xff000000) +#define VD2_BLEND_SRC_CTRL ((0x1dfc << 2) + 0xff000000) +#define OSD1_BLEND_SRC_CTRL ((0x1dfd << 2) + 0xff000000) +#define OSD2_BLEND_SRC_CTRL ((0x1dfe << 2) + 0xff000000) +#define VPP_OSD_SCALE_CTRL ((0x1dff << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_regs.h +// +//`include "v2regs.h" +// +// Reading file: viu2_regs.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: VIU2_VCBUS_BASE = 0x1e +// ----------------------------------------------- +//------------------------------------------------------------------------------ +// VIU2 top-level registers +//------------------------------------------------------------------------------ +// Bit 0 RW, osd1_reset +// Bit 1 RW, OSD1_reset +// Bit 2 RW, vd1_reset +// Bit 3 RW, vd1_fmt_reset +// Bit 7 RW, vpp_reset +#define VIU2_SW_RESET ((0x1e01 << 2) + 0xff000000) +#define VIU2_SW_RESET0 ((0x1e02 << 2) + 0xff000000) +// Bit 0 RW, software reset for mcvecrd_mif +// Bit 1 RW, software reset for mcinfowr_mif +// Bit 2 RW, software reset for mcinford_mif +#define VIU2_SECURE_REG ((0x1e05 << 2) + 0xff000000) +//bit 8 if true, vsync interrup is generate only field == 0 +//bit 7:0 fix_disable +#define VIU2_MISC_CTRL0 ((0x1e06 << 2) + 0xff000000) +#define VIU2_DATA_SEC_IN ((0x1e07 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// VPP2 top-level registers +//------------------------------------------------------------------------------ +// Bit 31 vd1_bgosd_exchange_en for preblend +// Bit 30 vd1_bgosd_exchange_en for postblend +// bit 28 color management enable +// Bit 27, reserved +// Bit 26:18, reserved +// Bit 17, OSD1 enable for preblend +// Bit 16, osd1 enable for preblend +// Bit 15, reserved +// Bit 14, vd1 enable for preblend +// Bit 13, OSD1 enable for postblend +// Bit 12, osd1 enable for postblend +// Bit 11, reserved +// Bit 10, vd1 enable for postblend +// Bit 9, if true, osd1 is alpha premultipiled +// Bit 8, if true, OSD1 is alpha premultipiled +// Bit 7, postblend module enable +// Bit 6, preblend module enable +// Bit 5, if true, OSD1 foreground compared with osd1 in preblend +// Bit 4, if true, OSD1 foreground compared with osd1 in postblend +// Bit 3, +// Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync +// the aync fifo will be reseted. +// Bit 1, +// Bit 0 if true, the output result of VPP is saturated +#define VPP2_MISC ((0x1e26 << 2) + 0xff000000) +//Bit 31:20 ofifo line length minus 1 +//Bit 19 if true invert input vs +//Bit 18 if true invert input hs +//Bit 17 force top/bottom field, enable +//Bit 16 force top/bottom field, 0: top, 1: bottom +//Bit 15 force one go_field, one pluse, write only +//Bit 14 force one go_line, one pluse, write only +//Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number +#define VPP2_OFIFO_SIZE ((0x1e27 << 2) + 0xff000000) +//Read only +//Bit 28:17 current scale out fifo counter +//Bit 16:12 current afifo counter +//Bit 11:0 current ofifo counter +#define VPP2_FIFO_STATUS ((0x1e28 << 2) + 0xff000000) +//Bit 12:0 line number use to generate interrupt when line == this number +#define VPP2_INT_LINE_NUM ((0x1e20 << 2) + 0xff000000) +#define VPP2_OFIFO_URG_CTRL ((0x1e21 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// OSD1 registers +//------------------------------------------------------------------------------ +// Bit 31 Reserved +// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics; +// 0=use gated clock for low power. +// Bit 29 R, test_rd_dsr +// Bit 28 R, osd_done +// Bit 27:24 R, osd_blk_mode +// Bit 23:22 R, osd_blk_ptr +// Bit 21 R, osd_enable +// +// Bit 20:12 RW, global_alpha +// Bit 11 RW, test_rd_en +// Bit 10 RW, hl2_en +// Bit 9 RW, hl1_en +// Bit 8: 5 RW, ctrl_mtch_y +// Bit 4 RW, ctrl_422to444 +// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable; +// Bit 1 to enable block 1, and so on. +#define VIU2_OSD1_CTRL_STAT ((0x1e30 << 2) + 0xff000000) +// Bit 31:26 Reserved +// Bit 25:16 R, fifo_count +// Bit 15: 6 Reserved +// Bit 5: 4 RW, hold_fifo_lines[6:5] +// Bit 3 RW, rgb2yuv_full_range +// Bit 2 RW, alpha_9b_mode +// Bit 1 RW, reserved +// Bit 0 RW, color_expand_mode +#define VIU2_OSD1_CTRL_STAT2 ((0x1e4d << 2) + 0xff000000) +// Bit 31: 9 Reserved +// Bit 8 RW, 0 = Write LUT, 1 = Read LUT +// Bit 7: 0 RW, lut_addr +#define VIU2_OSD1_COLOR_ADDR ((0x1e31 << 2) + 0xff000000) +// Bit 31:24 RW, Y or R +// Bit 23:16 RW, Cb or G +// Bit 15: 8 RW, Cr or B +// Bit 7: 0 RW, Alpha +#define VIU2_OSD1_COLOR ((0x1e32 << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, hl[1-2]_h/v_start +// Bit 15:12 Reserved +// Bit 11: 0 RW, hl[1-2]_h/v_end +#define VIU2_OSD1_HL1_H_START_END ((0x1e33 << 2) + 0xff000000) +#define VIU2_OSD1_HL1_V_START_END ((0x1e34 << 2) + 0xff000000) +#define VIU2_OSD1_HL2_H_START_END ((0x1e35 << 2) + 0xff000000) +#define VIU2_OSD1_HL2_V_START_END ((0x1e36 << 2) + 0xff000000) +// Bit 31:24 RW, Y or R +// Bit 23:16 RW, Cb or G +// Bit 15: 8 RW, Cr or B +// Bit 7: 0 RW, Alpha +#define VIU2_OSD1_TCOLOR_AG0 ((0x1e37 << 2) + 0xff000000) +#define VIU2_OSD1_TCOLOR_AG1 ((0x1e38 << 2) + 0xff000000) +#define VIU2_OSD1_TCOLOR_AG2 ((0x1e39 << 2) + 0xff000000) +#define VIU2_OSD1_TCOLOR_AG3 ((0x1e3a << 2) + 0xff000000) +// Bit 31:24 Reserved +// Bit 23:16 RW, tbl_addr +// Bit 15 RW, little_endian: 0=big endian, 1=little endian +// Bit 14 RW, rpt_y +// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous +// pixel; 11=Interpolate with the average value +// between previous and next pixel. +// Bit 11: 8 RW, osd_blk_mode +// Bit 7 RW, rgb_en +// Bit 6 RW, tc_alpha_en +// Bit 5: 2 RW, color_matrix +// Bit 1 RW, interlace_en +// Bit 0 RW, interlace_sel_odd +#define VIU2_OSD1_BLK0_CFG_W0 ((0x1e3b << 2) + 0xff000000) +#define VIU2_OSD1_BLK1_CFG_W0 ((0x1e3f << 2) + 0xff000000) +#define VIU2_OSD1_BLK2_CFG_W0 ((0x1e43 << 2) + 0xff000000) +#define VIU2_OSD1_BLK3_CFG_W0 ((0x1e47 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 RW, x_end +// Bit 15:13 Reserved +// Bit 12: 0 RW, x_start +#define VIU2_OSD1_BLK0_CFG_W1 ((0x1e3c << 2) + 0xff000000) +#define VIU2_OSD1_BLK1_CFG_W1 ((0x1e40 << 2) + 0xff000000) +#define VIU2_OSD1_BLK2_CFG_W1 ((0x1e44 << 2) + 0xff000000) +#define VIU2_OSD1_BLK3_CFG_W1 ((0x1e48 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 RW, y_end +// Bit 15:13 Reserved +// Bit 12: 0 RW, y_start +#define VIU2_OSD1_BLK0_CFG_W2 ((0x1e3d << 2) + 0xff000000) +#define VIU2_OSD1_BLK1_CFG_W2 ((0x1e41 << 2) + 0xff000000) +#define VIU2_OSD1_BLK2_CFG_W2 ((0x1e45 << 2) + 0xff000000) +#define VIU2_OSD1_BLK3_CFG_W2 ((0x1e49 << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, h_end +// Bit 15:12 Reserved +// Bit 11: 0 RW, h_start +#define VIU2_OSD1_BLK0_CFG_W3 ((0x1e3e << 2) + 0xff000000) +#define VIU2_OSD1_BLK1_CFG_W3 ((0x1e42 << 2) + 0xff000000) +#define VIU2_OSD1_BLK2_CFG_W3 ((0x1e46 << 2) + 0xff000000) +#define VIU2_OSD1_BLK3_CFG_W3 ((0x1e4a << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, v_end +// Bit 15:12 Reserved +// Bit 11: 0 RW, v_start +#define VIU2_OSD1_BLK0_CFG_W4 ((0x1e64 << 2) + 0xff000000) +#define VIU2_OSD1_BLK1_CFG_W4 ((0x1e65 << 2) + 0xff000000) +#define VIU2_OSD1_BLK2_CFG_W4 ((0x1e66 << 2) + 0xff000000) +#define VIU2_OSD1_BLK3_CFG_W4 ((0x1e67 << 2) + 0xff000000) +// Bit 31 RW, burst_len_sel[2] of [2:0] +// Bit 30 RW, byte_swap: In addition to endian control, further define +// whether to swap upper and lower byte within a 16-bit mem word. +// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]} +// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word +// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif +// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved +// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT +// Bit 19 R, fifo_overflow +// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8. +// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128. +// Bit 9: 5 RW, hold_fifo_lines[4:0] +// Bit 4 RW, clear_err: one pulse to clear fifo_overflow +// Bit 3 RW, fifo_sync_rst +// Bit 2: 1 RW, endian +// Bit 0 RW, urgent +#define VIU2_OSD1_FIFO_CTRL_STAT ((0x1e4b << 2) + 0xff000000) +// Bit 31:24 R, Y or R +// Bit 23:16 R, Cb or G +// Bit 15: 8 R, Cr or B +// Bit 7: 0 R, Output Alpha[8:1] +#define VIU2_OSD1_TEST_RDDATA ((0x1e4c << 2) + 0xff000000) +// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate. +// Bit 12: 0 RW, effective FIFO size when prot_en=1. +#define VIU2_OSD1_PROT_CTRL ((0x1e4e << 2) + 0xff000000) +#define VIU2_OSD1_MALI_UNPACK_CTRL ((0x1e4f << 2) + 0xff000000) +#define VIU2_OSD1_DIMM_CTRL ((0x1e50 << 2) + 0xff000000) +//`define VIU2_MATRIX_CTRL 8'h70 +#define VIU2_OSD1_MATRIX_COEF00_01 ((0x1e70 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_COEF02_10 ((0x1e71 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_COEF11_12 ((0x1e72 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_COEF20_21 ((0x1e73 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_COEF22 ((0x1e74 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_COEF13_14 ((0x1e75 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_COEF23_24 ((0x1e76 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_COEF15_25 ((0x1e77 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_CLIP ((0x1e78 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_OFFSET0_1 ((0x1e79 << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_OFFSET2 ((0x1e7a << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 ((0x1e7b << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_PRE_OFFSET2 ((0x1e7c << 2) + 0xff000000) +#define VIU2_OSD1_MATRIX_EN_CTRL ((0x1e7d << 2) + 0xff000000) +#define VIU2_RMIF_CTRL0 ((0x1e80 << 2) + 0xff000000) +#define VIU2_RMIF_CTRL1 ((0x1e81 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst +//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num +//Bit 15 reserved +//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd, + // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64 +//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64 +//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4 +//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable +//Bit 6 reg_big_endian // unsigned , default = 0, big endian enable +//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable +//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable +//Bit 3 reserved +//Bit 2:0 reg_pack_mode // unsigned , default = 1, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit +#define VIU2_RMIF_CTRL2 ((0x1e82 << 2) + 0xff000000) +//Bit 31 reg_sw_rst // unsigned , default = 0, +//Bit 30:17 reserved +//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg : + // 16 reg_ugt_init : urgent initial value + // 15 reg_ugt_en : urgent enable + // 14 reg_ugt_type : 1= wrmif 0=rdmif + // 7:4 reg_ugt_top_th: urgent top threshold + // 3:0 reg_ugt_bot_th: urgent bottom threshold +#define VIU2_RMIF_SCOPE_X ((0x1e83 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_x_end // unsigned , default = 0, the canvas hor end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position +#define VIU2_RMIF_SCOPE_Y ((0x1e84 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio +#define VIU2_ROT_BLK_SIZE ((0x1e85 << 2) + 0xff000000) +#define VIU2_ROT_LBUF_SIZE ((0x1e86 << 2) + 0xff000000) +#define VIU2_ROT_FMT_CTRL ((0x1e87 << 2) + 0xff000000) +#define VIU2_ROT_WIND_CTRL ((0x1e88 << 2) + 0xff000000) +#define VIU2_ROT_OUT_VCROP ((0x1e89 << 2) + 0xff000000) +#define VIU2_ROT_BUF_SIZE ((0x1e8a << 2) + 0xff000000) +#define VIU2_ROT_RO_MIF0_STAT ((0x1e8b << 2) + 0xff000000) +//Bit 15:0 reg_status // unsigned , +#define VIU2_ROT_RO_MIF1_STAT ((0x1e8c << 2) + 0xff000000) +#define VIU2_ROT_RO_STAT ((0x1e8d << 2) + 0xff000000) +#define VIU2_GAINOFF_GCLK_CTRL ((0x1ea0 << 2) + 0xff000000) +#define VIU2_GAINOFF_CTRL0 ((0x1ea1 << 2) + 0xff000000) +#define VIU2_GAINOFF_CTRL1 ((0x1ea2 << 2) + 0xff000000) +#define VIU2_GAINOFF_CTRL2 ((0x1ea3 << 2) + 0xff000000) +#define VIU2_GAINOFF_CTRL3 ((0x1ea4 << 2) + 0xff000000) +#define VIU2_GAINOFF_CTRL4 ((0x1ea5 << 2) + 0xff000000) +#define VPP2_CRC_CHK ((0x1eb0 << 2) + 0xff000000) +#define VPP2_RO_CRCSUM ((0x1eb1 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: viu2_regs.h +// +// +// Reading file: vregs_clk1.h +// +//=========================================================================== +// Video Interface Registers 0xa00 - 0xaff +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: VIUB_VCBUS_BASE = 0x20 +// ----------------------------------------------- +#define VIUB_ADDR_START ((0x2000 << 2) + 0xff000000) +#define VIUB_ADDR_END ((0x20ff << 2) + 0xff000000) +//`define TRACE_REG 8'ff +//------------------------------------------------------------------------------ +// VIU top-level registers +//------------------------------------------------------------------------------ +// Bit 0 RW, osd1_reset +// Bit 1 RW, osd2_reset +// Bit 2 RW, vd1_reset +// Bit 3 RW, vd1_fmt_reset +// Bit 4 RW, vd2_reset +// Bit 5 RW, vd2_fmt_reset +// Bit 6 RW, di_dsr1to2_reset +// Bit 7 RW, vpp_reset +// Bit 8 RW, di_if1_reset +// Bit 9 RW, di_if1_fmt_reset +// Bit 10 RW, di_inp_reset +// Bit 11 RW, di_inp_fmt_reset +// Bit 12 RW, di_mem_reset +// Bit 13 RW, di_mem_fmt_reset +// Bit 14 RW, di_nr_wr_mif_reset +// Bit 15 RW, dein_wr_mif_reset +// Bit 16 RW, di_chan2_mif_reset +// Bit 17 RW, di_mtn_wr_mif_reset +// Bit 18 RW, di_mtn_rd_mif_reset +// Bit 19 RW, di_mad_reset +// Bit 20 RW, vdin0_reset +// Bit 21 RW, vdin1_reset +// Bit 22 RW, nrin_mux_reset +// Bit 23 RW, vdin0_wr_reset +// Bit 24 RW, vdin1_wr_reset +// Bit 25 RW, reserved +// Bit 26 RW, d2d3_reset +// Bit 27 RW, di_cont_wr_mif_reset +// Bit 28 RW, di_cont_rd_mif_reset +#define VIUB_SW_RESET ((0x2001 << 2) + 0xff000000) +#define VIUB_SW_RESET0 ((0x2002 << 2) + 0xff000000) +// Bit 0 RW, software reset for mcvecrd_mif +// Bit 1 RW, software reset for mcinfowr_mif +// Bit 2 RW, software reset for mcinford_mif +#define DI_AFBCE_CTRL ((0x2003 << 2) + 0xff000000) +#define VIUB_SECURE_ST_RO ((0x2004 << 2) + 0xff000000) +//bit 8 if true, vsync interrup is generate only field == 0 +//bit 7:0 fix_disable +#define VIUB_MISC_CTRL0 ((0x2006 << 2) + 0xff000000) +#define VIUB_GCLK_CTRL0 ((0x2007 << 2) + 0xff000000) +//// gclk_ctrl0_gl[ 0] : def=1 di_top_wrap clk enable +//// +//// gclk_ctrl0_gl[ 8] : def=0 mad pre clock enable, from mad clock +//// gclk_ctrl0_gl[ 9] : def=0 mad post clock enable, from mad clock +//// gclk_ctrl0_gl[10] : def=0 div clock enable, di slow clock including di&mcdi +//// gclk_ctrl0_gl[11] : def=0 mcdi clock enable, from div clock +//// gclk_ctrl0_gl[12] : def=0 di post clock enable, from div clock +//// gclk_ctrl0_gl[13] : def=0 reserved +//// gclk_ctrl0_gl[14] : def=1 di_no_clk_gate, for old di +//// gclk_ctrl0_gl[15] : def=0 di_gate_all, for old di +#define VIUB_GCLK_CTRL1 ((0x2008 << 2) + 0xff000000) +//// gclk_ctrl1_gl[ 1: 0] : def=2'b00 mif-sub-arb clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[ 3: 2] : def=2'b00 if1 rdmif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[ 5: 4] : def=2'b00 if2 rdmif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[ 7: 6] : def=2'b00 de wrmif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[ 9: 8] : def=2'b00 mtnrd post mif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[11:10] : def=2'b00 mcdi post mif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[17:16] : def=2'b00 inp rdmif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[19:18] : def=2'b00 mem rdmif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[21:20] : def=2'b00 chan rdmif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[23:22] : def=2'b00 nr wrmif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[25:24] : def=2'b00 mtn mif clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl1_gl[27:26] : def=2'b00 mcdi pre mif clock gate ctrl [1]: clock valid, [0]: clock close +//// +#define VIUB_GCLK_CTRL2 ((0x2009 << 2) + 0xff000000) +//// gclk_ctrl_pre[ 1: 0] : def=2'b00 nr clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl_pre[ 3: 2] : def=2'b00 pd clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl_pre[ 5: 4] : def=2'b00 mtn det clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl_pre[ 7: 6] : def=2'b00 debanding clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl_pre[ 9: 8] : def=2'b00 dnr clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl_pre[11:10] : def=2'b00 nr&dnr blend clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl_pre[13:12] : def=2'b00 mcdi clock gate ctrl [1]: clock valid, [0]: clock close +#define VIUB_GCLK_CTRL3 ((0x200a << 2) + 0xff000000) +//// gclk_ctrl_post[ 1: 0] : def=2'b00 di blend clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl_post[ 3: 2] : def=2'b00 ei clock gate ctrl [1]: clock valid, [0]: clock close +//// gclk_ctrl_post[ 5: 4] : def=2'b00 ei_0 clock gate ctrl [1]: clock valid, [0]: clock close +#define DI_DBG_CTRL ((0x200b << 2) + 0xff000000) +#define DI_DBG_CTRL1 ((0x200c << 2) + 0xff000000) +#define DI_DBG_SRDY_INF ((0x200d << 2) + 0xff000000) +#define DI_DBG_RRDY_INF ((0x200e << 2) + 0xff000000) +#define VIUB_SECURE_REG ((0x200f << 2) + 0xff000000) +#define DI_PRE_SEC_IN ((0x2010 << 2) + 0xff000000) +#define DI_POST_SEC_IN ((0x2011 << 2) + 0xff000000) +//`define DI_IF2_GEN_REG 8'h10 +//`define DI_IF2_CANVAS0 8'h11 +//`define DI_IF2_LUMA_X0 8'h12 +//`define DI_IF2_LUMA_Y0 8'h13 +//`define DI_IF2_CHROMA_X0 8'h14 +//`define DI_IF2_CHROMA_Y0 8'h15 +//`define DI_IF2_RPT_LOOP 8'h16 +//`define DI_IF2_LUMA0_RPT_PAT 8'h17 +//`define DI_IF2_CHROMA0_RPT_PAT 8'h18 +//`define DI_IF2_DUMMY_PIXEL 8'h19 +//`define DI_IF2_LUMA_FIFO_SIZE 8'h1a +//`define DI_IF2_RANGE_MAP_Y 8'h1b +//`define DI_IF2_RANGE_MAP_CB 8'h1c +//`define DI_IF2_RANGE_MAP_CR 8'h1d +//`define DI_IF2_GEN_REG2 8'h1e +//`define DI_IF2_FMT_CTRL 8'h1f +//`define DI_IF2_FMT_W 8'h20 +// +//`define DI_IF2_URGENT_CTRL 8'h21 +//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path +//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path +//`define DI_IF2_GEN_REG3 8'h22 +//bit 31:1, reversed +//bit 0, cntl_64bit_rev +//================================== +#define DI_EI_DRT_CTRL ((0x2028 << 2) + 0xff000000) +//Bit 31, reg_rectg_en ;u1 +//Bit 30, reg_recbld_en ;u1 +//Bit 29:28, reg_rectg_ws ;u2 +//Bit 27, reserved +//Bit 26:24, reg_abq_margin ;u3 +//Bit 23, reserved +//Bit 22:20, reg_trend_mg ;u3 +//Bit 19:16, reg_int_d16xc1 ;u4 +//Bit 15:14, reserved +//Bit 13: 8, reg_int_chlmt1 ;u6 +//Bit 7, reserved +//Bit 6: 4, reg_nscheck_thrd ;u3 +//Bit 3, reserved +//Bit 2: 0, reg_horsl_ws ;u3 +#define DI_EI_DRT_PIXTH ((0x2029 << 2) + 0xff000000) +//Bit 31:24, reg_min_pix ;u8 +//Bit 23:16, reg_max_pix ;u8 +//Bit 15: 8, reg_dmaxmin_thrdma ;u8 +//Bit 7: 0, reg_dmaxmin_thrdmi ;u8 +#define DI_EI_DRT_CORRPIXTH ((0x202a << 2) + 0xff000000) +//Bit 31:24, reg_newcorrpix_maxthrd ;u8 +//Bit 23:16, reg_corrpix_diffthrd ;u8 +//Bit 15: 8, reg_corrpix_minthrd ;u8 +//Bit 7: 0, reg_corrpix_maxthrd ;u8 +#define DI_EI_DRT_RECTG_WAVE ((0x202b << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:24, reg_max_pixwave ;u5 +//Bit 23:21, reserved +//Bit 20:16, reg_pix_wave ;u5 +//Bit 15:14, reserved +//Bit 13: 8, reg_maxdrt_thrd ;u6 +//Bit 7: 0, reg_wave_thrd ;u8 +#define DI_EI_DRT_PIX_DIFFTH ((0x202c << 2) + 0xff000000) +//Bit 31:24, reg_newraw_thrd ;u8 +//Bit 23:16, reg_tb_max_thrd ;u8 +//Bit 15: 8, reg_diffpix_thrd ;u8 +//Bit 7: 6, reserved +//Bit 5: 0, reg_bilt_trendnumt ;u8 +#define DI_EI_DRT_UNBITREND_TH ((0x202d << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:24, reg_trend_numb ;u5 +//Bit 23:21, reserved +//Bit 20:16, reg_bilt_trendnum ;u5 +//Bit 15:13, reserved +//Bit 12: 8, reg_unil_trendnumt ;u5 +//Bit 7: 5, reserved +//Bit 4: 0, reg_trend_num ;u5 +//`define DI_IF0_GEN_REG 8'h30 +//`define DI_IF0_CANVAS0 8'h31 +//`define DI_IF0_LUMA_X0 8'h32 +//`define DI_IF0_LUMA_Y0 8'h33 +//`define DI_IF0_CHROMA_X0 8'h34 +//`define DI_IF0_CHROMA_Y0 8'h35 +//`define DI_IF0_RPT_LOOP 8'h36 +//`define DI_IF0_LUMA0_RPT_PAT 8'h37 +//`define DI_IF0_CHROMA0_RPT_PAT 8'h38 +//`define DI_IF0_DUMMY_PIXEL 8'h39 +//`define DI_IF0_LUMA_FIFO_SIZE 8'h3a +//`define DI_IF0_RANGE_MAP_Y 8'h3b +//`define DI_IF0_RANGE_MAP_CB 8'h3c +//`define DI_IF0_RANGE_MAP_CR 8'h3d +//`define DI_IF0_GEN_REG2 8'h3e +//`define DI_IF0_FMT_CTRL 8'h3f +//`define DI_IF0_FMT_W 8'h40 +// +//`define DI_IF0_URGENT_CTRL 8'h41 +//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path +//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path +//`define DI_IF0_GEN_REG3 8'h42 +//bit 31:1, reversed +//bit 0, cntl_64bit_rev +// di arbtration : +// the segment is 8'h50-8'h5f +// +// Reading file: di_arb_axi_regs.h +// +// synopsys translate_off +// synopsys translate_on +////===============================//// +//// reg +////===============================//// +#define DI_RDARB_MODE_L1C1 ((0x2050 << 2) + 0xff000000) +//Bit 31:22, reserved +//Bit 21:16, rdarb_sel uns, default = 0 , +// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1 +// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1 +// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1 +// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1 +// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1 +// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1 +//Bit 15:10, reserved +//Bit 9:8, rdarb_arb_mode uns, default = 0 , +// rdarb_arb_mode[0] master port0 arb way, +// rdarb_arb_mode[1] master port1 arb way, +//Bit 7:4, reserved +//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 , +// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control +// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control +#define DI_RDARB_REQEN_SLV_L1C1 ((0x2051 << 2) + 0xff000000) +//Bit 31:12, reserved +//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff +// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable, +// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable, +// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable, +// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable, +// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable, +// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable, +// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable, +// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable, +// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable, +// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable, +// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable, +// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable, +#define DI_RDARB_WEIGH0_SLV_L1C1 ((0x2052 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:0, rddc_weigh_sxn unsigned , default = 0 +// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number +// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number +// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number +// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number +// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number +#define DI_RDARB_WEIGH1_SLV_L1C1 ((0x2053 << 2) + 0xff000000) +//Bit 31:6, reserved +//Bit 5:0, rddc_weigh_sxn unsigned , default = 0 +// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number +#define DI_WRARB_MODE_L1C1 ((0x2054 << 2) + 0xff000000) +//Bit 31:22, reserved +//Bit 21:16, wrarb_sel uns, default = 0 , +// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1 +// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1 +// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1 +// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1 +// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1 +// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1 +//Bit 15:10, reserved +//Bit 9:8, wrarb_arb_mode uns, default = 0 , +// wrarb_arb_mode[0] master port0 arb way, +// wrarb_arb_mode[1] master port1 arb way, +//Bit 7:4, reserved +//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 , +// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control +// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control +#define DI_WRARB_REQEN_SLV_L1C1 ((0x2055 << 2) + 0xff000000) +//Bit 31:12, reserved +//Bit 11:0, wrarb_dc_req_en unsigned , default = 0 +// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable, +// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable, +// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable, +// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable, +// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable, +// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable, +// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable, +// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable, +// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable, +// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable, +// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable, +// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable, +#define DI_WRARB_WEIGH0_SLV_L1C1 ((0x2056 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0 +// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number +// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number +// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number +// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number +// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number +#define DI_WRARB_WEIGH1_SLV_L1C1 ((0x2057 << 2) + 0xff000000) +//Bit 31:6, reserved +//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0 +// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number +#define DI_RDWR_ARB_STATUS_L1C1 ((0x2058 << 2) + 0xff000000) +//Bit 31:4, reserved +//Bit 3:2, wrarb_arb_busy unsigned , default = 0 +//Bit 1:0, rdarb_arb_busy unsigned , default = 0 +#define DI_ARB_DBG_CTRL_L1C1 ((0x2059 << 2) + 0xff000000) +#define DI_ARB_DBG_STAT_L1C1 ((0x205a << 2) + 0xff000000) +#define DI_RDARB_UGT_L1C1 ((0x205b << 2) + 0xff000000) +#define DI_RDARB_LIMT0_L1C1 ((0x205c << 2) + 0xff000000) +#define DI_WRARB_UGT_L1C1 ((0x205d << 2) + 0xff000000) +#define DI_ARB_AXIWR_PROT ((0x205e << 2) + 0xff000000) +#define DI_ARB_AXIRD0_PROT ((0x205f << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: di_arb_axi_regs.h +// +// di afbc_enc +// the segment is 8'h60-8'h8f +// +// Reading file: di_afbc_enc0_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DI_AFBCE_ENABLE ((0x2060 << 2) + 0xff000000) +//Bit 31:20, gclk_ctrl unsigned , default = 0, +//Bit 19:16, di_afbce_sync_sel unsigned , default = 0, +//Bit 15:14, reserved +//Bit 13, enc_rst_mode unsigned , default = 0, +//Bit 12, enc_en_mode unsigned , default = 0, +//Bit 11:9, reserved +//Bit 8, enc_enable unsigned , default = 0, +//Bit 7:1, reserved +//Bit 0, reserved enc_frm_start pulse use this bit don't use +#define DI_AFBCE_MODE ((0x2061 << 2) + 0xff000000) +//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field +//Bit 28, reserved +//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode +//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent +//Bit 23, reserved +//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4 +//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4 +//Bit 13:1, reserved +//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb +#define DI_AFBCE_SIZE_IN ((0x2062 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel +#define DI_AFBCE_BLK_SIZE_IN ((0x2063 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel +#define DI_AFBCE_HEAD_BADDR ((0x2064 << 2) + 0xff000000) +//Bit 31:0, head_baddr unsigned, default = 32'h00; +#define DI_AFBCE_MIF_SIZE ((0x2065 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:28, ddr_blk_size unsigned, default = 1; +//Bit 27, reserved +//Bit 26:24, cmd_blk_size unsigned, default = 3; +//Bit 23:21, reserved +//Bit 20:16, uncmp_size unsigned, default = 20; +//Bit 15:0, mmu_page_size unsigned, default = 4096; +#define DI_AFBCE_PIXEL_IN_HOR_SCOPE ((0x2066 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; // +//Bit 15:13, reserved +//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; // +#define DI_AFBCE_PIXEL_IN_VER_SCOPE ((0x2067 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; // +//Bit 15:13, reserved +//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; // +#define DI_AFBCE_CONV_CTRL ((0x2068 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048 +//Bit 15:12, reserved +//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n +#define DI_AFBCE_MIF_HOR_SCOPE ((0x2069 << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25:16, blk_end_h unsigned, default = 0 ; // +//Bit 15:10, reserved +//Bit 9:0, blk_bgn_h unsigned, default = 59 ; // +#define DI_AFBCE_MIF_VER_SCOPE ((0x206a << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, blk_end_v unsigned, default = 0 ; // +//Bit 15:12, reserved +//Bit 11:0, blk_bgn_v unsigned, default = 269 ; // +#define DI_AFBCE_STAT1 ((0x206b << 2) + 0xff000000) +//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status +//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ; +#define DI_AFBCE_STAT2 ((0x206c << 2) + 0xff000000) +//Bit 31, reserved +//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ; +#define DI_AFBCE_FORMAT ((0x206d << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11:10 reserved +//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB +//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth +//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth +#define DI_AFBCE_MODE_EN ((0x206e << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:26 reserved +//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation +//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation +//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride +//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride +//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride +//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride +//Bit 19 reserved +//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 11 reserved +//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss +//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block +//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split +//Bit 7: 6 reserved +//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128 +//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128 +//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7 +//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value +#define DI_AFBCE_DWSCALAR ((0x206f << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +#define DI_AFBCE_DEFCOLOR_1 ((0x2070 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr] +//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr] +#define DI_AFBCE_DEFCOLOR_2 ((0x2071 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr] +//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr] +#define DI_AFBCE_QUANT_ENABLE ((0x2072 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion +//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion +//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1; +//Bit 7: 5 reserved +//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy +//Bit 3: 1 reserved +//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy +#define DI_AFBCE_IQUANT_LUT_1 ((0x2073 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define DI_AFBCE_IQUANT_LUT_2 ((0x2074 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define DI_AFBCE_IQUANT_LUT_3 ((0x2075 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define DI_AFBCE_IQUANT_LUT_4 ((0x2076 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define DI_AFBCE_RQUANT_LUT_1 ((0x2077 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting) +//Bit 27 reserved +//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5 +//Bit 23 reserved +//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4 +//Bit 19 reserved +//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4 +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2 +#define DI_AFBCE_RQUANT_LUT_2 ((0x2078 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0 +#define DI_AFBCE_RQUANT_LUT_3 ((0x2079 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting) +//Bit 27 reserved +//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5 +//Bit 23 reserved +//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4 +//Bit 19 reserved +//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4 +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2 +#define DI_AFBCE_RQUANT_LUT_4 ((0x207a << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0 +#define DI_AFBCE_YUV_FORMAT_CONV_MODE ((0x207b << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7 reserved +//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0 +#define DI_AFBCE_DUMMY_DATA ((0x207c << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ; +#define DI_AFBCE_CLR_FLAG ((0x207d << 2) + 0xff000000) +//Bit 31:0 reg_di_afbce_clr_flag // unsigned, default = 0 ; +#define DI_AFBCE_STA_FLAGT ((0x207e << 2) + 0xff000000) +//Bit 31:0 ro_di_afbce__sta_flag // unsigned, RO,default = 0 ; +#define DI_AFBCE_MMU_NUM ((0x207f << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ; +#define DI_AFBCE_MMU_RMIF_CTRL1 ((0x2080 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst +//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num +//Bit 15 reserved +//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd, + // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64 +//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64 +//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4 +//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable +//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable +//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable +//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable +//Bit 3 reserved +//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit +#define DI_AFBCE_MMU_RMIF_CTRL2 ((0x2081 << 2) + 0xff000000) +//Bit 31:30 reg_sw_rst // unsigned , default = 0, +//Bit 29:24 reserved +//Bit 23:18 reg_gclk_ctrl +//Bit 17 reserved +//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg : + // 16 reg_ugt_init : urgent initial value + // 15 reg_ugt_en : urgent enable + // 14 reg_ugt_type : 1= wrmif 0=rdmif + // 7:4 reg_ugt_top_th: urgent top threshold + // 3:0 reg_ugt_bot_th: urgent bottom threshold +#define DI_AFBCE_MMU_RMIF_CTRL3 ((0x2082 << 2) + 0xff000000) +//Bit 31:17 reserved +//Bit 16 reg_acc_mode // unsigned , default = 1, +//Bit 15:13 reserved +//Bit 12:0 reg_stride // unsigned , default = 4096, +#define DI_AFBCE_MMU_RMIF_CTRL4 ((0x2083 << 2) + 0xff000000) +//Bit 31:0 reg_baddr // unsigned , default = 0, +#define DI_AFBCE_MMU_RMIF_SCOPE_X ((0x2084 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position +#define DI_AFBCE_MMU_RMIF_SCOPE_Y ((0x2085 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio +#define DI_AFBCE_MMU_RMIF_RO_STAT ((0x2086 << 2) + 0xff000000) +//Bit 15:0 reg_status // unsigned , +#define DI_AFBCE_PIP_CTRL ((0x208a << 2) + 0xff000000) +//Bit 31:3 reserved +//Bit 2 reg_enc_align_en //unsigned , RW,default = 1, +//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0, +//Bit 0 reg_pip_mode //unsigned , RW,default = 0, +#define DI_AFBCE_ROT_CTRL ((0x208b << 2) + 0xff000000) +//Bit 31:5 reserved +//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable +//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode +#define DI_AFBCE_DIMM_CTRL ((0x208c << 2) + 0xff000000) +//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal +//Bit 30 reserved +//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data +// synopsys translate_off +// synopsys translate_on +// +// Closing file: di_afbc_enc0_regs.h +// +// the segment is 8'h90-8'h9f +// +// Reading file: di_wrmif0_regs.h +// +#define NRWR_DBG_AXI_CMD_CNT ((0x2090 << 2) + 0xff000000) +#define NRWR_DBG_AXI_DAT_CNT ((0x2091 << 2) + 0xff000000) +#define DI_NRWR_CANVAS ((0x2092 << 2) + 0xff000000) +#define DI_NRWR_URGENT ((0x2093 << 2) + 0xff000000) +#define DI_NRWR_X ((0x2094 << 2) + 0xff000000) +#define DI_NRWR_Y ((0x2095 << 2) + 0xff000000) +//bit 31:30 NRWR_words_lim +//bit 29 NRWR_rev_y +//bit 28:16 NRWR_start_y +//bit 15 NRWR_ext_en +//bit 12:0 NRWR_end_y +#define DI_NRWR_CTRL ((0x2096 << 2) + 0xff000000) +//bit 31 pending_ddr_wrrsp_NRWR +//bit 30 NRWR_reg_swap +//bit 29:26 NRWR_burst_lim +//bit 25 NRWR_canvas_syncen +//bit 24 NRWR_no_clk_gate +//bit 23:22 NRWR_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas 2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved +//bit 21:20 NRWR_hconv_mode +//bit 19:18 NRWR_vconv_mode +//bit 17 NRWR_swap_cbcr +//bit 16 NRWR_urgent +//bit 15:8 NRWR_canvas_index_chroma +//bit 7:0 NRWR_canvas_index_luma +#define DI_NRWR_SHRK_CTRL ((0x2097 << 2) + 0xff000000) +//bit 31:10 reserved +//bit 9:8 reg_vshrk_mode unsigned, default = 0, 0:1/2 horizonal shrink 1:1/4 horizonal shrink 2:1/8 horizonal shrink +//bit 7:6 reg_hshrk_mode unsigned, default = 0, 0:1/2 vertical shrink 1:1/4 vertical shrink 2:1/8 vertical shrink +//bit 5:2 reg_gclk_ctrl unsigned, default = 0 +//bit 1 reg_frm_rst unsigned, default = 0 +//bit 0 reg_shrk_en unsigned, default = 0 +#define DI_NRWR_SHRK_SIZE ((0x2098 << 2) + 0xff000000) +//bit 31:26 reserved +//bit 25:13 reg_frm_hsize unsigned, default = 1920, hsize in +//bit 12:0 reg_frm_vsize unsigned, default = 1080, vsize in +#define DI_NRWR_CROP_CTRL ((0x209a << 2) + 0xff000000) +//Bit 31 reg_crop_en unsigned , RW,default = 0,dimm_layer enable singal +//Bit 30:4 reserved +//Bit 3:0 reg_hold_line unsigned , RW,default = 4,dimm_layer data +#define DI_NRWR_CROP_DIMM_CTRL ((0x209b << 2) + 0xff000000) +//Bit 31 reg_dimm_layer_en unsigned , RW,default = 0,dimm_layer enable singal +//Bit 30 reserved +//Bit 29:0 reg_dimm_data unsigned , RW,default = 29'h00080200,dimm_layer data +#define DI_NRWR_CROP_SIZE_IN ((0x209c << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 reg_crop_hsize unsigned, default = 1920 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, reg_crop_vsize unsigned, default = 1080 , pic vert size in unit: pixel +#define DI_NRWR_CROP_HSCOPE ((0x209d << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_cropwin_end_h unsigned, default = 1919 ; +//Bit 15:13, reserved +//Bit 12:0, reg_cropwin_bgn_h unsigned, default = 0 ; +#define DI_NRWR_CROP_VSCOPE ((0x209e << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ; +//Bit 15:13, reserved +//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ; +// +// Closing file: di_wrmif0_regs.h +// +// the segment is 8'ha0-8'hbf +//`define DI_IF1_URGENT_CTRL 8'ha3 +//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path +//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path +//`define DI_INP_URGENT_CTRL 8'ha4 +//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path +//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path +//`define DI_MEM_URGENT_CTRL 8'ha5 +//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path +//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path +//`define DI_CHAN2_URGENT_CTRL 8'ha6 +//`define DI_IF1_GEN_REG3 8'ha7 +//bit 31:1, reversed +//bit 0, cntl_64bit_rev +//`define DI_INP_GEN_REG3 8'ha8 +//bit 31:1, reversed +//bit 0, cntl_64bit_rev +//`define DI_MEM_GEN_REG3 8'ha9 +//bit 31:1, reversed +//bit 0, cntl_64bit_rev +//`define DI_CHAN2_GEN_REG3 8'haa +//bit 31:1, reversed +//bit 0, cntl_64bit_rev +//`define DI_PRE_GL_CTRL 8'hab +//bit 31,pre go field cnt enable +//bit 30,pre go field cnt reset +//bit 29:16, total pre go line +//bit 13:0, total pre go frame +//`define DI_PRE_GL_THD 8'hac +//bit 31:0 go line size +//`define DI_POST_GL_CTRL 8'had +//bit 31,post go field cnt enable +//bit 30,post go field cnt reset +//bit 28:16, total post go line +//bit 13:0, total post go frame +//`define DI_POST_GL_THD 8'hae +//bit 31:0 go line size +//`define DI_IF0_AXI_CMD_CNT 8'hb0 +//`define DI_IF0_AXI_RDAT_CNT 8'hb1 +// +//`define DI_IF1_AXI_CMD_CNT 8'hb2 +//`define DI_IF1_AXI_RDAT_CNT 8'hb3 +// +//`define DI_IF2_AXI_CMD_CNT 8'hb4 +//`define DI_IF2_AXI_RDAT_CNT 8'hb5 +// +//`define DI_INP_AXI_CMD_CNT 8'hb6 +//`define DI_INP_AXI_RDAT_CNT 8'hb7 +// +//`define DI_MEM_AXI_CMD_CNT 8'hb8 +//`define DI_MEM_AXI_RDAT_CNT 8'hb9 +// +//`define DI_CHAN2_AXI_CMD_CNT 8'hba +//`define DI_CHAN2_AXI_RDAT_CNT 8'hbb +// di afbc_enc +// the segment is 8'hc0-8'hef +// +// Reading file: di_afbc_enc1_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DI_AFBCE1_ENABLE ((0x20c0 << 2) + 0xff000000) +//Bit 31:20, gclk_ctrl unsigned , default = 0, +//Bit 19:16, di_AFBCE1_sync_sel unsigned , default = 0, +//Bit 15:14, reserved +//Bit 13, enc_rst_mode unsigned , default = 0, +//Bit 12, enc_en_mode unsigned , default = 0, +//Bit 11:9, reserved +//Bit 8, enc_enable unsigned , default = 0, +//Bit 7:1, reserved +//Bit 0, reserved enc_frm_start pulse use this bit don't use +#define DI_AFBCE1_MODE ((0x20c1 << 2) + 0xff000000) +//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field +//Bit 28, reserved unsigned, default = 0 , enable singal of crop +//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode +//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent +//Bit 23, reserved +//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4 +//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4 +//Bit 13:1, reserved +//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb +#define DI_AFBCE1_SIZE_IN ((0x20c2 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel +#define DI_AFBCE1_BLK_SIZE_IN ((0x20c3 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel +#define DI_AFBCE1_HEAD_BADDR ((0x20c4 << 2) + 0xff000000) +//Bit 31:0, head_baddr unsigned, default = 32'h00; +#define DI_AFBCE1_MIF_SIZE ((0x20c5 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:28, ddr_blk_size unsigned, default = 1; +//Bit 27, reserved +//Bit 26:24, cmd_blk_size unsigned, default = 3; +//Bit 23:21, reserved +//Bit 20:16, uncmp_size unsigned, default = 20; +//Bit 15:0, mmu_page_size unsigned, default = 4096; +#define DI_AFBCE1_PIXEL_IN_HOR_SCOPE ((0x20c6 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; // +//Bit 15:13, reserved +//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; // +#define DI_AFBCE1_PIXEL_IN_VER_SCOPE ((0x20c7 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; // +//Bit 15:13, reserved +//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; // +#define DI_AFBCE1_CONV_CTRL ((0x20c8 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048 +//Bit 15:12, reserved +//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n +#define DI_AFBCE1_MIF_HOR_SCOPE ((0x20c9 << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25:16, blk_end_h unsigned, default = 0 ; // +//Bit 15:10, reserved +//Bit 9:0, blk_bgn_h unsigned, default = 59 ; // +#define DI_AFBCE1_MIF_VER_SCOPE ((0x20ca << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, blk_end_v unsigned, default = 0 ; // +//Bit 15:12, reserved +//Bit 11:0, blk_bgn_v unsigned, default = 269 ; // +#define DI_AFBCE1_STAT1 ((0x20cb << 2) + 0xff000000) +//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status +//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ; +#define DI_AFBCE1_STAT2 ((0x20cc << 2) + 0xff000000) +//Bit 31, reserved +//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ; +#define DI_AFBCE1_FORMAT ((0x20cd << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11:10 reserved +//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB +//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth +//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth +#define DI_AFBCE1_MODE_EN ((0x20ce << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:26 reserved +//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation +//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation +//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride +//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride +//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride +//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride +//Bit 19 reserved +//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 11 reserved +//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss +//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block +//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split +//Bit 7: 6 reserved +//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128 +//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128 +//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7 +//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value +#define DI_AFBCE1_DWSCALAR ((0x20cf << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +#define DI_AFBCE1_DEFCOLOR_1 ((0x20d0 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr] +//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr] +#define DI_AFBCE1_DEFCOLOR_2 ((0x20d1 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr] +//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr] +#define DI_AFBCE1_QUANT_ENABLE ((0x20d2 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion +//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion +//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1; +//Bit 7: 5 reserved +//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy +//Bit 3: 1 reserved +//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy +#define DI_AFBCE1_IQUANT_LUT_1 ((0x20d3 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define DI_AFBCE1_IQUANT_LUT_2 ((0x20d4 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define DI_AFBCE1_IQUANT_LUT_3 ((0x20d5 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define DI_AFBCE1_IQUANT_LUT_4 ((0x20d6 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define DI_AFBCE1_RQUANT_LUT_1 ((0x20d7 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting) +//Bit 27 reserved +//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5 +//Bit 23 reserved +//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4 +//Bit 19 reserved +//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4 +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2 +#define DI_AFBCE1_RQUANT_LUT_2 ((0x20d8 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0 +#define DI_AFBCE1_RQUANT_LUT_3 ((0x20d9 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting) +//Bit 27 reserved +//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5 +//Bit 23 reserved +//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4 +//Bit 19 reserved +//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4 +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2 +#define DI_AFBCE1_RQUANT_LUT_4 ((0x20da << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0 +#define DI_AFBCE1_YUV_FORMAT_CONV_MODE ((0x20db << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7 reserved +//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0 +#define DI_AFBCE1_DUMMY_DATA ((0x20dc << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ; +#define DI_AFBCE1_CLR_FLAG ((0x20dd << 2) + 0xff000000) +//Bit 31:0 reg_di_AFBCE1_clr_flag // unsigned, default = 0 ; +#define DI_AFBCE1_STA_FLAGT ((0x20de << 2) + 0xff000000) +//Bit 31:0 ro_di_AFBCE1__sta_flag // unsigned, RO,default = 0 ; +#define DI_AFBCE1_MMU_NUM ((0x20df << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ; +#define DI_AFBCE1_MMU_RMIF_CTRL1 ((0x20e0 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst +//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num +//Bit 15 reserved +//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd, + // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64 +//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64 +//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4 +//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable +//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable +//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable +//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable +//Bit 3 reserved +//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit +#define DI_AFBCE1_MMU_RMIF_CTRL2 ((0x20e1 << 2) + 0xff000000) +//Bit 31:30 reg_sw_rst // unsigned , default = 0, +//Bit 29:24 reserved +//Bit 23:18 reg_gclk_ctrl +//Bit 17 reserved +//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg : + // 16 reg_ugt_init : urgent initial value + // 15 reg_ugt_en : urgent enable + // 14 reg_ugt_type : 1= wrmif 0=rdmif + // 7:4 reg_ugt_top_th: urgent top threshold + // 3:0 reg_ugt_bot_th: urgent bottom threshold +#define DI_AFBCE1_MMU_RMIF_CTRL3 ((0x20e2 << 2) + 0xff000000) +//Bit 31:17 reserved +//Bit 16 reg_acc_mode // unsigned , default = 1, +//Bit 15:13 reserved +//Bit 12:0 reg_stride // unsigned , default = 4096, +#define DI_AFBCE1_MMU_RMIF_CTRL4 ((0x20e3 << 2) + 0xff000000) +//Bit 31:0 reg_baddr // unsigned , default = 0, +#define DI_AFBCE1_MMU_RMIF_SCOPE_X ((0x20e4 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position +#define DI_AFBCE1_MMU_RMIF_SCOPE_Y ((0x20e5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio +#define DI_AFBCE1_MMU_RMIF_RO_STAT ((0x20e6 << 2) + 0xff000000) +//Bit 15:0 reg_status // unsigned , +#define DI_AFBCE1_PIP_CTRL ((0x20ea << 2) + 0xff000000) +//Bit 31:3 reserved +//Bit 2 reg_enc_align_en //unsigned , RW,default = 1, +//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0, +//Bit 0 reg_pip_mode //unsigned , RW,default = 0, +#define DI_AFBCE1_ROT_CTRL ((0x20eb << 2) + 0xff000000) +//Bit 31:5 reserved +//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable +//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode +#define DI_AFBCE1_DIMM_CTRL ((0x20ec << 2) + 0xff000000) +//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal +//Bit 30 reserved +//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data +// synopsys translate_off +// synopsys translate_on +// +// Closing file: di_afbc_enc1_regs.h +// +// the segment is 8'hf0-8'hff +// +// Reading file: di_wrmif1_regs.h +// +#define DIWR_DBG_AXI_CMD_CNT ((0x20f0 << 2) + 0xff000000) +#define DIWR_DBG_AXI_DAT_CNT ((0x20f1 << 2) + 0xff000000) +#define DI_DIWR_CANVAS ((0x20f2 << 2) + 0xff000000) +#define DI_DIWR_URGENT ((0x20f3 << 2) + 0xff000000) +#define DI_DIWR_X ((0x20f4 << 2) + 0xff000000) +#define DI_DIWR_Y ((0x20f5 << 2) + 0xff000000) +//bit 31:30 diwr_words_lim +//bit 29 diwr_rev_y +//bit 28:16 diwr_start_y +//bit 15 diwr_ext_en +//bit 12:0 diwr_end_y +#define DI_DIWR_CTRL ((0x20f6 << 2) + 0xff000000) +//bit 31 pending_ddr_wrrsp_diwr +//bit 30 diwr_reg_swap +//bit 29:26 diwr_burst_lim +//bit 25 diwr_canvas_syncen +//bit 24 diwr_no_clk_gate +//bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas 2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved +//bit 21:20 diwr_hconv_mode +//bit 19:18 diwr_vconv_mode +//bit 17 diwr_swap_cbcr +//bit 16 diwr_urgent +//bit 15:8 diwr_canvas_index_chroma +//bit 7:0 diwr_canvas_index_luma +#define DI_DIWR_SHRK_CTRL ((0x20f7 << 2) + 0xff000000) +//bit 31:10 reserved +//bit 9:8 reg_vshrk_mode unsigned, default = 0, 0:1/2 horizonal shrink 1:1/4 horizonal shrink 2:1/8 horizonal shrink +//bit 7:6 reg_hshrk_mode unsigned, default = 0, 0:1/2 vertical shrink 1:1/4 vertical shrink 2:1/8 vertical shrink +//bit 5:2 reg_gclk_ctrl unsigned, default = 0 +//bit 1 reg_frm_rst unsigned, default = 0 +//bit 0 reg_shrk_en unsigned, default = 0 +#define DI_DIWR_SHRK_SIZE ((0x20f8 << 2) + 0xff000000) +//bit 31:26 reserved +//bit 25:13 reg_frm_hsize unsigned, default = 1920, hsize in +//bit 12:0 reg_frm_vsize unsigned, default = 1080, vsize in +#define DI_DIWR_CROP_CTRL ((0x20fa << 2) + 0xff000000) +//Bit 31 reg_crop_en unsigned , RW,default = 0,dimm_layer enable singal +//Bit 30:4 reserved +//Bit 3:0 reg_hold_line unsigned , RW,default = 4,dimm_layer data +#define DI_DIWR_CROP_DIMM_CTRL ((0x20fb << 2) + 0xff000000) +//Bit 31 reg_dimm_layer_en unsigned , RW,default = 0,dimm_layer enable singal +//Bit 30 reserved +//Bit 29:0 reg_dimm_data unsigned , RW,default = 29'h00080200,dimm_layer data +#define DI_DIWR_CROP_SIZE_IN ((0x20fc << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 reg_crop_hsize unsigned, default = 1920 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, reg_crop_vsize unsigned, default = 1080 , pic vert size in unit: pixel +#define DI_DIWR_CROP_HSCOPE ((0x20fd << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_cropwin_end_h unsigned, default = 1919 ; +//Bit 15:13, reserved +//Bit 12:0, reg_cropwin_bgn_h unsigned, default = 0 ; +#define DI_DIWR_CROP_VSCOPE ((0x20fe << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ; +//Bit 15:13, reserved +//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ; +// +// Closing file: di_wrmif1_regs.h +// +// +// Closing file: vregs_clk1.h +// +//====================================================================== +// vpu register. +//====================================================================== +// +// Reading file: vpu_top_regs.h +// +// synopsys translate_off +// synopsys translate_on +//====================================================================== +// vpu register. +//====================================================================== +// ----------------------------------------------- +// REG_BASE: VPU_VCBUS_BASE = 0x27 +// ----------------------------------------------- +//`define VPU_OSD1_MMC_CTRL 8'h01 +#define VPU_CRC_CTRL ((0x2701 << 2) + 0xff000000) +#define VPU_RO_CRC0 ((0x2702 << 2) + 0xff000000) +#define VPU_RO_CRC1 ((0x2703 << 2) + 0xff000000) +#define VPU_RO_CRC2 ((0x2704 << 2) + 0xff000000) +#define VPU_RO_CRC3 ((0x2705 << 2) + 0xff000000) +#define VPU_RO_CRC4 ((0x2706 << 2) + 0xff000000) +#define VPU_RO_CRC5 ((0x2707 << 2) + 0xff000000) +#define VPU_RO_CRC6 ((0x2708 << 2) + 0xff000000) +#define VPU_INTF_CTRL ((0x270a << 2) + 0xff000000) +#define VPU_APB_PROT_CTRL ((0x270b << 2) + 0xff000000) +#define VPU_ENC_ERROR ((0x270c << 2) + 0xff000000) +#define VPU_SECURE_REG ((0x270d << 2) + 0xff000000) +#define VPU_SECURE_ST_RO ((0x270e << 2) + 0xff000000) +#define VPU_VDIN_SEC_IN ((0x270f << 2) + 0xff000000) +//`define VPU_OSD2_MMC_CTRL 8'h02 +//`define VPU_VD1_MMC_CTRL 8'h03 +//`define VPU_VD2_MMC_CTRL 8'h04 +//`define VPU_DI_IF1_MMC_CTRL 8'h05 +//`define VPU_DI_MEM_MMC_CTRL 8'h06 +//`define VPU_DI_INP_MMC_CTRL 8'h07 +//`define VPU_DI_MTNRD_MMC_CTRL 8'h08 +//`define VPU_DI_CHAN2_MMC_CTRL 8'h09 +//`define VPU_DI_MTNWR_MMC_CTRL 8'h0a +//`define VPU_DI_NRWR_MMC_CTRL 8'h0b +//`define VPU_DI_DIWR_MMC_CTRL 8'h0c +//`define VPU_VDIN0_MMC_CTRL 8'h0d +//`define VPU_VDIN1_MMC_CTRL 8'h0e +//`define VPU_BT656_MMC_CTRL 8'h0f +//`define VPU_TVD3D_MMC_CTRL 8'h10 +//`define VPU_TVDVBI_MMC_CTRL 8'h11 +//Read only +//`define VPU_TVDVBI_VSLATCH_ADDR 8'h12 +//Read only +//`define VPU_TVDVBI_WRRSP_ADDR 8'h13 +#define VPU_VDIN_PRE_ARB_CTRL ((0x2714 << 2) + 0xff000000) +#define VPU_VDISP_PRE_ARB_CTRL ((0x2715 << 2) + 0xff000000) +#define VPU_VPUARB2_PRE_ARB_CTRL ((0x2716 << 2) + 0xff000000) +#define VPU_OSD3_MMC_CTRL ((0x2717 << 2) + 0xff000000) +#define VPU_OSD4_MMC_CTRL ((0x2718 << 2) + 0xff000000) +#define VPU_VD3_MMC_CTRL ((0x2719 << 2) + 0xff000000) +// [31:21] Reserved. +// [20:18] cntl_encx_clk_sel +// [17:16] cntl_vencl_dpi_sel_clk +// [15: 8] Reserved +// [ 6: 4] Reserved +// [ 3: 2] cntl_viu2_sel_venc. Select which one of the encI/P/T that VIU2 connects to: +// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT. +// [ 1: 0] cntl_viu1_sel_venc. Select which one of the encI/P/T that VIU1 connects to: +// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT. +#define VPU_VIU_VENC_MUX_CTRL ((0x271a << 2) + 0xff000000) +// [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2. +// [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1. +// [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format: +// 0=output CrYCb(BRG); +// 1=output YCbCr(RGB); +// 2=output YCrCb(RBG); +// 3=output CbCrY(GBR); +// 4=output CbYCr(GRB); +// 5=output CrCbY(BGR); +// 6,7=Rsrv. +// [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI). +// [ 3] inv_vsync. 1=Invert Vsync polarity. +// [ 2] inv_hsync. 1=Invert Hsync polarity. +// [ 1: 0] src_sel. 0=Disable output to HDMI; 1=Select VENC_I output to HDMI; 2=Select VENC_P output. +#define VPU_HDMI_SETTING ((0x271b << 2) + 0xff000000) +#define ENCI_INFO_READ ((0x271c << 2) + 0xff000000) +#define ENCP_INFO_READ ((0x271d << 2) + 0xff000000) +#define ENCT_INFO_READ ((0x271e << 2) + 0xff000000) +#define ENCL_INFO_READ ((0x271f << 2) + 0xff000000) +// Bit 0 RW, viu_rst_n +// Bit 1 RW, vdin_mmc_arb_rst_n +// Bit 2 RW, vdisp_mmc_arb_rst_n +// Bit 3 RW, vpuarb2_mmc_arb_rst_n +#define VPU_SW_RESET ((0x2720 << 2) + 0xff000000) +//Bit 30 d2d3_depr_req_sel, 0:vdisp_pre_arb, 1: vpuarb2_pre_arb +//Bit 27:22 d2d3_depr_brst_num +//Bit 21:16 d2d3_depr_id +//Bit 14 d2d3_depw_req_sel, 0: vdin_pre_arb, 1: vdisp_pre_arb +//Bit 11:6 d2d3_depw_brst_num +//Bit 5:0 d2d3_depw_id +#define VPU_D2D3_MMC_CTRL ((0x2721 << 2) + 0xff000000) +//Bit 30 mtn_contrd_req_pre, 0:disp1_arb, 1: vdin_pre_arb +//Bit 27:22 mtn_contrd_brst_num +//Bit 21:16 mtn_contrd_id +//Bit 14 mtn_contwr_req_pre, 0: vdisp1_arb, 1: vdin_pre_arb +//Bit 11:6 mtn_contwr_brst_num +//Bit 5:0 mtn_contwr_id +#define VPU_CONT_MMC_CTRL ((0x2722 << 2) + 0xff000000) +// Bit 6 RW, gclk_mpeg_vpu_misc +// Bit 5 RW, gclk_mpeg_venc_l_top +// Bit 4 RW, gclk_mpeg_vencl_int +// Bit 3 RW, gclk_mpeg_vencp_int +// Bit 2 RW, gclk_mpeg_vi2_top +// Bit 1 RW, gclk_mpeg_vi_top +// Bit 0 RW, gclk_mpeg_venc_p_top +#define VPU_CLK_GATE ((0x2723 << 2) + 0xff000000) +//Bit 12 RW, rdma_pre +//Bit 11: 6 RW, rdma_num +//Bit 5: 0 RW, rdma_id +#define VPU_RDMA_MMC_CTRL ((0x2724 << 2) + 0xff000000) +#define VPU_MEM_PD_REG0 ((0x2725 << 2) + 0xff000000) +#define VPU_MEM_PD_REG1 ((0x2726 << 2) + 0xff000000) +// [ 31] hdmi_data_ovr_en: 1=Enable overriding data input to HDMI TX with hdmi_data_ovr[29:0]. 0=No override. Default 0. +// [ 30] Reserved. Default 0 +// [29: 0] hdmi_data_ovr. Default 0. +#define VPU_HDMI_DATA_OVR ((0x2727 << 2) + 0xff000000) +//Bit 15 RW, prot1_sel_osd4 +//Bit 14 RW, prot1_sel_osd3 +//Bit 13 RW, prot1_sel_osd2 +//Bit 12 RW, prot1_sel_osd1 +//Bit 11: 6 RW, prot1_brst_num +//Bit 5: 0 RW, prot1_id +#define VPU_PROT1_MMC_CTRL ((0x2728 << 2) + 0xff000000) +//Bit 14 RW, prot2_sel_vd3 +//Bit 13 RW, prot2_sel_vd2 +//Bit 12 RW, prot2_sel_vd1 +//Bit 11: 6 RW, prot2_brst_num +//Bit 5: 0 RW, prot2_id +#define VPU_PROT2_MMC_CTRL ((0x2729 << 2) + 0xff000000) +//Bit 14 RW, prot3_sel_vd3 +//Bit 13 RW, prot3_sel_vd2 +//Bit 12 RW, prot3_sel_vd1 +//Bit 11: 6 RW, prot3_brst_num +//Bit 5: 0 RW, prot3_id +#define VPU_PROT3_MMC_CTRL ((0x272a << 2) + 0xff000000) +//Bit 29:24 RW, s3_brst_num +//Bit 21:16 RW, s2_brst_num +//Bit 13: 8 RW, s1_brst_num +//Bit 5: 0 RW, s0_brst_num +#define VPU_ARB4_V1_MMC_CTRL ((0x272b << 2) + 0xff000000) +//Bit 29:24 RW, s3_brst_num +//Bit 21:16 RW, s2_brst_num +//Bit 13: 8 RW, s1_brst_num +//Bit 5: 0 RW, s0_brst_num +#define VPU_ARB4_V2_MMC_CTRL ((0x272c << 2) + 0xff000000) +//Bit 27:22 RW, mcvecwr_num +//Bit 21:16 RW, mcvecwr_id +//Bit 11:6 RW, mcvecrd_num +//Bit 5:0 RW, mcvecrd_id +#define VPU_MCVEC_MMC_CTRL ((0x272d << 2) + 0xff000000) +//Bit 27:22 RW, mcinfwr_num +//Bit 21:16 RW, mcinfwr_id +//Bit 11:6 RW, mcinfrd_num +//Bit 5:0 RW, mcinfrd_id +#define VPU_MCINF_MMC_CTRL ((0x272e << 2) + 0xff000000) +//Bit 31 reg_vpu_pwm_inv, 1: invert the pwm signal, active low +//Bit 30:29 reg_vpu_pwm_src_sel, 00: encl, enct, encp +//Bit 28:16 reg_vpu_pwm_v_end0 +//Bit 12:0 reg_vpu_pwm_v_start0 +#define VPU_VPU_PWM_V0 ((0x2730 << 2) + 0xff000000) +//Bit 28:16 reg_vpu_pwm_v_end1 +//Bit 12:0 reg_vpu_pwm_v_start1 +#define VPU_VPU_PWM_V1 ((0x2731 << 2) + 0xff000000) +//Bit 28:16 reg_vpu_pwm_v_end2 +//Bit 12:0 reg_vpu_pwm_v_start2 +#define VPU_VPU_PWM_V2 ((0x2732 << 2) + 0xff000000) +//Bit 28:16 reg_vpu_pwm_v_end3 +//Bit 12:0 reg_vpu_pwm_v_start3 +#define VPU_VPU_PWM_V3 ((0x2733 << 2) + 0xff000000) +//Bit 28:16 reg_vpu_pwm_h_end0 +//Bit 12:0 reg_vpu_pwm_h_start0 +#define VPU_VPU_PWM_H0 ((0x2734 << 2) + 0xff000000) +//Bit 28:16 reg_vpu_pwm_h_end1 +//Bit 12:0 reg_vpu_pwm_h_start1 +#define VPU_VPU_PWM_H1 ((0x2735 << 2) + 0xff000000) +//Bit 28:16 reg_vpu_pwm_h_end2 +//Bit 12:0 reg_vpu_pwm_h_start2 +#define VPU_VPU_PWM_H2 ((0x2736 << 2) + 0xff000000) +//Bit 28:16 reg_vpu_pwm_h_end3 +//Bit 12:0 reg_vpu_pwm_h_start3 +#define VPU_VPU_PWM_H3 ((0x2737 << 2) + 0xff000000) +//Bit 18 reg_vpu_3d_go_high_fld_pol: 0: go high at field 0, 1: go high at field 1 +//Bit 17 reg_vpu_3d_sync_setting_vsync_latch +//Bit 16 reg_vpu_3d_sync_enable +//Bit 14:8 reg_vpu_3d_sync_v_end +//Bit 6:0 reg_vpu_3d_sync_v_start +#define VPU_VPU_3D_SYNC1 ((0x2738 << 2) + 0xff000000) +//Bit 28:16 reg_vpu_3d_sync_h_end +//Bit 12:0 reg_vpu_3d_sync_h_start +#define VPU_VPU_3D_SYNC2 ((0x2739 << 2) + 0xff000000) +//Bit 0, if true, force vencl clk enable, otherwise, it might auto turn off by mipi DSI +#define VPU_MISC_CTRL ((0x2740 << 2) + 0xff000000) +#define VPU_ISP_GCLK_CTRL0 ((0x2741 << 2) + 0xff000000) +#define VPU_ISP_GCLK_CTRL1 ((0x2742 << 2) + 0xff000000) +#define VPU_HDMI_FMT_CTRL ((0x2743 << 2) + 0xff000000) +#define VPU_VDIN_ASYNC_HOLD_CTRL ((0x2744 << 2) + 0xff000000) +#define VPU_VDISP_ASYNC_HOLD_CTRL ((0x2745 << 2) + 0xff000000) +#define VPU_VPUARB2_ASYNC_HOLD_CTRL ((0x2746 << 2) + 0xff000000) +// arb0_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[0] | +// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[1] +// ; +// +// arb1_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[2] | +// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[3] +// ; +// +// arb2_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[4] | +// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[5] +// ; +// +// arb0_wr_urg_ctrl_o <= vdin0_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[6] | +// vdin1_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[7] +// ; +// +// arb1_wr_urg_ctrl_o <= vdin0_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[8] | +// vdin1_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[9] +// +#define VPU_ARB_URG_CTRL ((0x2747 << 2) + 0xff000000) +#define VPU_SECURE_DUMMY ((0x2748 << 2) + 0xff000000) +#define VPU_VENCL_DITH_EN ((0x2749 << 2) + 0xff000000) +// todo : +#define VPU_422TO444_RST ((0x274a << 2) + 0xff000000) +// todo : +#define VPU_422TO444_CTRL0 ((0x274b << 2) + 0xff000000) +// todo : +#define VPU_422TO444_CTRL1 ((0x274c << 2) + 0xff000000) +// todo : +#define VPU_422TO444_CTRL2 ((0x274d << 2) + 0xff000000) +// Picture Rotate (PROT) module 1 (for OSD) registers: +#define VPU_PROT1_CLK_GATE ((0x2750 << 2) + 0xff900000) +#define VPU_PROT1_GEN_CNTL ((0x2751 << 2) + 0xff900000) +#define VPU_PROT1_X_START_END ((0x2752 << 2) + 0xff900000) +#define VPU_PROT1_Y_START_END ((0x2753 << 2) + 0xff900000) +#define VPU_PROT1_Y_LEN_STEP ((0x2754 << 2) + 0xff900000) +#define VPU_PROT1_RPT_LOOP ((0x2755 << 2) + 0xff900000) +#define VPU_PROT1_RPT_PAT ((0x2756 << 2) + 0xff900000) +#define VPU_PROT1_DDR ((0x2757 << 2) + 0xff900000) +#define VPU_PROT1_RBUF_ROOM ((0x2758 << 2) + 0xff900000) +#define VPU_PROT1_STAT_0 ((0x2759 << 2) + 0xff900000) +#define VPU_PROT1_STAT_1 ((0x275a << 2) + 0xff900000) +#define VPU_PROT1_STAT_2 ((0x275b << 2) + 0xff900000) +#define VPU_PROT1_REQ_ONOFF ((0x275c << 2) + 0xff900000) +// Picture Rotate (PROT) module 2 (for VD) registers: +#define VPU_PROT2_CLK_GATE ((0x2760 << 2) + 0xff900000) +#define VPU_PROT2_GEN_CNTL ((0x2761 << 2) + 0xff900000) +#define VPU_PROT2_X_START_END ((0x2762 << 2) + 0xff900000) +#define VPU_PROT2_Y_START_END ((0x2763 << 2) + 0xff900000) +#define VPU_PROT2_Y_LEN_STEP ((0x2764 << 2) + 0xff900000) +#define VPU_PROT2_RPT_LOOP ((0x2765 << 2) + 0xff900000) +#define VPU_PROT2_RPT_PAT ((0x2766 << 2) + 0xff900000) +#define VPU_PROT2_DDR ((0x2767 << 2) + 0xff900000) +#define VPU_PROT2_RBUF_ROOM ((0x2768 << 2) + 0xff900000) +#define VPU_PROT2_STAT_0 ((0x2769 << 2) + 0xff900000) +#define VPU_PROT2_STAT_1 ((0x276a << 2) + 0xff900000) +#define VPU_PROT2_STAT_2 ((0x276b << 2) + 0xff900000) +#define VPU_PROT2_REQ_ONOFF ((0x276c << 2) + 0xff900000) +// Picture Rotate (PROT) module 3 (for VD) registers: +#define VPU_PROT3_CLK_GATE ((0x2770 << 2) + 0xff900000) +#define VPU_PROT3_GEN_CNTL ((0x2771 << 2) + 0xff900000) +#define VPU_PROT3_X_START_END ((0x2772 << 2) + 0xff900000) +#define VPU_PROT3_Y_START_END ((0x2773 << 2) + 0xff900000) +#define VPU_PROT3_Y_LEN_STEP ((0x2774 << 2) + 0xff900000) +#define VPU_PROT3_RPT_LOOP ((0x2775 << 2) + 0xff900000) +#define VPU_PROT3_RPT_PAT ((0x2776 << 2) + 0xff900000) +#define VPU_PROT3_DDR ((0x2777 << 2) + 0xff900000) +#define VPU_PROT3_RBUF_ROOM ((0x2778 << 2) + 0xff900000) +#define VPU_PROT3_STAT_0 ((0x2779 << 2) + 0xff900000) +#define VPU_PROT3_STAT_1 ((0x277a << 2) + 0xff900000) +#define VPU_PROT3_STAT_2 ((0x277b << 2) + 0xff900000) + +//Bit 20 reg_viu2vdin0_sw_reset: software reset +//Bit 19:18 reg_viu2vdin0_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved +//Bit 17:16 reg_viu2vdin0_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8 +//Bit 15:14 reversed +//Bit 13:0 reg_viu2vdin0_hsize: source horizontal size +#define VPU_VIU2VDIN0_HDN_CTRL ((0x2780 << 2) + 0xff000000) +#define VPU_VIU_ASYNC_MASK ((0x2781 << 2) + 0xff000000) +#define VPU_VDIN_MISC_CTRL ((0x2782 << 2) + 0xff000000) +// [31:29] Reserved. +// [28:24] cntl_viu2vdin1_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection: +// 5'b00000=Disable VIU to VDIN path; +// 5'b00001=Enable VIU of ENC_I domain to VDIN; +// 5'b00010=Enable VIU of ENC_P domain to VDIN; +// 5'b00100=Enable VIU of ENC_T domain to VDIN; +// 5'b01000=Enable VIU WriteBack 1 domain to VDIN; +// 5'b10000=Enable VIU WriteBack 2 domain to VDIN; +// [23:21] Reserved. +// [20:16] cntl_viu2vdin1_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock: +// 5'b00000=Disable VIU to VDIN clock; +// 5'b00001=Select encI clock to VDIN; +// 5'b00010=Select encP clock to VDIN; +// 5'b00100=Select encT clock to VDIN; +// 5'b01000=Select VIU WriteBack 1 clock to VDIN; +// 5'b10000=Select VIU WriteBack 2 clock to VDIN; +// [15:13] Reserved. +// [12: 8] cntl_viu2vdin0_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection: +// 5'b00000=Disable VIU to VDIN path; +// 5'b00001=Enable VIU of ENC_I domain to VDIN; +// 5'b00010=Enable VIU of ENC_P domain to VDIN; +// 5'b00100=Enable VIU of ENC_T domain to VDIN; +// 5'b01000=Enable VIU WriteBack 1 domain to VDIN; +// 5'b10000=Enable VIU WriteBack 2 domain to VDIN; +// [ 7:5] Reserved. +// [ 4: 0] cntl_viu2vdin0_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock: +// 5'b00000=Disable VIU to VDIN clock; +// 5'b00001=Select encI clock to VDIN; +// 5'b00010=Select encP clock to VDIN; +// 5'b00100=Select encT clock to VDIN; +// 5'b01000=Select VIU WriteBack 1 clock to VDIN; +// 5'b10000=Select VIU WriteBack 2 clock to VDIN; +#define VPU_VIU_VDIN_IF_MUX_CTRL ((0x2783 << 2) + 0xff000000) +//Bit 20 reg_viu2vdin1_sw_reset: software reset +//Bit 19:18 reg_viu2vdin1_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved +//Bit 17:16 reg_viu2vdin1_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8 +//Bit 15:14 reversed +//Bit 13:0 reg_viu2vdin1_hsize: source horizontal size +#define VPU_VIU2VDIN1_HDN_CTRL ((0x2784 << 2) + 0xff000000) +#define VPU_VENCX_CLK_CTRL ((0x2785 << 2) + 0xff000000) +//Bit 0 encp_afifo_clk +//Bit 1 encl_afifo_clk +//Bit 2 enci_afifo_clk +// vpu arbtration : +// the segment is 8'h90-8'hc8 +// +// Reading file: vpu_arb_axi_regs.h +// +// synopsys translate_off +// synopsys translate_on +////===============================//// +//// reg +////===============================//// +#define VPU_RDARB_MODE_L1C1 ((0x2790 << 2) + 0xff000000) +//Bit 31:22, reserved +//Bit 21:16, rdarb_sel uns, default = 0 , +// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1 +// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1 +// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1 +// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1 +// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1 +// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1 +//Bit 15:10, reserved +//Bit 9:8, rdarb_arb_mode uns, default = 0 , +// rdarb_arb_mode[0] master port0 arb way, +// rdarb_arb_mode[1] master port1 arb way, +//Bit 7:4, reserved +//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 , +// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control +// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control +#define VPU_RDARB_REQEN_SLV_L1C1 ((0x2791 << 2) + 0xff000000) +//Bit 31:12, reserved +//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff +// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable, +// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable, +// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable, +// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable, +// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable, +// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable, +// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable, +// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable, +// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable, +// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable, +// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable, +// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable, +#define VPU_RDARB_WEIGH0_SLV_L1C1 ((0x2792 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:0, rddc_weigh_sxn unsigned , default = 0 +// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number +// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number +// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number +// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number +// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number +#define VPU_RDARB_WEIGH1_SLV_L1C1 ((0x2793 << 2) + 0xff000000) +//Bit 31:6, reserved +//Bit 5:0, rddc_weigh_sxn unsigned , default = 0 +// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number +#define VPU_WRARB_MODE_L1C1 ((0x2794 << 2) + 0xff000000) +//Bit 31:22, reserved +//Bit 21:16, wrarb_sel uns, default = 0 , +// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1 +// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1 +// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1 +// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1 +// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1 +// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1 +//Bit 15:10, reserved +//Bit 9:8, wrarb_arb_mode uns, default = 0 , +// wrarb_arb_mode[0] master port0 arb way, +// wrarb_arb_mode[1] master port1 arb way, +//Bit 7:4, reserved +//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 , +// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control +// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control +#define VPU_WRARB_REQEN_SLV_L1C1 ((0x2795 << 2) + 0xff000000) +//Bit 31:12, reserved +//Bit 11:0, wrarb_dc_req_en unsigned , default = 0 +// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable, +// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable, +// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable, +// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable, +// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable, +// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable, +// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable, +// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable, +// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable, +// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable, +// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable, +// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable, +#define VPU_WRARB_WEIGH0_SLV_L1C1 ((0x2796 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0 +// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number +// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number +// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number +// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number +// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number +#define VPU_WRARB_WEIGH1_SLV_L1C1 ((0x2797 << 2) + 0xff000000) +//Bit 31:6, reserved +//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0 +// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number +#define VPU_RDWR_ARB_STATUS_L1C1 ((0x2798 << 2) + 0xff000000) +//Bit 31:4, reserved +//Bit 3:2, wrarb_arb_busy unsigned , default = 0 +//Bit 1:0, rdarb_arb_busy unsigned , default = 0 +#define VPU_RDARB_MODE_L1C2 ((0x2799 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, rdarb_sel uns, default = 0 , +// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1 +// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1 +// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1 +// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1 +// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1 +//Bit 15:10, reserved +//Bit 9:8, rdarb_arb_mode uns, default = 0 , +// rdarb_arb_mode[0] master port0 arb way, +// rdarb_arb_mode[1] master port1 arb way, +//Bit 7:4, reserved +//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 , +// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control +// rdarb_gate_clk_ctrl[3:2] master port0 clk gate control +#define VPU_RDARB_REQEN_SLV_L1C2 ((0x279a << 2) + 0xff000000) +//Bit 31:10, reserved +//Bit 9:0, rdarb_dc_req_en unsigned , default = 0 +// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable, +// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable, +// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable, +// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable, +// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable, +// rdarb_dc_req_en[5]: the slv0 req to mst port1 enable, +// rdarb_dc_req_en[6]: the slv1 req to mst port1 enable, +// rdarb_dc_req_en[7]: the slv2 req to mst port1 enable, +// rdarb_dc_req_en[8]: the slv3 req to mst port1 enable, +// rdarb_dc_req_en[9]: the slv4 req to mst port1 enable, +#define VPU_RDARB_WEIGH0_SLV_L1C2 ((0x279b << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:0, rddc_weigh_sxn unsigned , default = 0 +// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number +// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number +// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number +// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number +// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number +#define VPU_RDWR_ARB_STATUS_L1C2 ((0x279c << 2) + 0xff000000) +//Bit 31:3, reserved +//Bit 2, wrarb_arb_busy unsigned , default = 0 +//Bit 1:0, rdarb_arb_busy unsigned , default = 0 +#define VPU_RDARB_MODE_L2C1 ((0x279d << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, rdarb_sel uns, default = 0 , +// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1 +// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1 +// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1 +// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1 +// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1 +// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1 +//Bit 15:11, reserved +//Bit 10:8, rdarb_arb_mode uns, default = 0 , +// rdarb_arb_mode[0] master port0 arb way, +// rdarb_arb_mode[1] master port1 arb way, +//Bit 7:6, reserved +//Bit 5:0, rdarb_gate_clk_ctrl uns, default = 0 , +// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control +// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control +// rdarb_gate_clk_ctrl[5:4] master port2 clk gate control +#define VPU_RDARB_REQEN_SLV_L2C1 ((0x279e << 2) + 0xff000000) +//Bit 31:18, reserved +//Bit 17:0, rdarb_dc_req_en unsigned , default = 0 +// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable, +// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable, +// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable, +// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable, +// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable, +// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable, +// rdarb_dc_req_en[0]: the slv0 req to mst port1 enable, +// rdarb_dc_req_en[1]: the slv1 req to mst port1 enable, +// rdarb_dc_req_en[2]: the slv2 req to mst port1 enable, +// rdarb_dc_req_en[3]: the slv3 req to mst port1 enable, +// rdarb_dc_req_en[4]: the slv4 req to mst port1 enable, +// rdarb_dc_req_en[5]: the slv5 req to mst port1 enable, +#define VPU_RDARB_WEIGH0_SLV_L2C1 ((0x279f << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:0, rddc_weigh_sxn unsigned , default = 0 +// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number +// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number +// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number +// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number +// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number +#define VPU_RDARB_WEIGH1_SLV_L2C1 ((0x27a0 << 2) + 0xff000000) +//Bit 31:6, reserved +//Bit 5:0, rddc_weigh_sxn unsigned , default = 0 +// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number +#define VPU_RDWR_ARB_STATUS_L2C1 ((0x27a1 << 2) + 0xff000000) +//Bit 31:4, reserved +//Bit 3:2, wrarb_arb_busy unsigned , default = 0 +//Bit 1:0, rdarb_arb_busy unsigned , default = 0 +#define VPU_WRARB_MODE_L2C1 ((0x27a2 << 2) + 0xff000000) +//Bit 31:20, reserved +//Bit 19:16, wrarb_sel uns, default = 0 , +// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1 +// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1 +// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1 +// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1 +//Bit 15:10, reserved +//Bit 9:8, wrarb_arb_mode uns, default = 0 , +// wrarb_arb_mode[0] master port0 arb way, +// wrarb_arb_mode[1] master port1 arb way, +//Bit 7:4, reserved +//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 , +// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control +// wrarb_gate_clk_ctrl[3:2] master port0 clk gate control +#define VPU_WRARB_REQEN_SLV_L2C1 ((0x27a3 << 2) + 0xff000000) +//Bit 31:8, reserved +//Bit 7:0, wrarb_dc_req_en unsigned , default = 0 +// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable, +// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable, +// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable, +// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable, +// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable, +// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable, +// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable, +// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable, +#define VPU_WRARB_WEIGH0_SLV_L2C1 ((0x27a4 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:0, wrdc_weigh_sxn unsigned , default = 0 +// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number +// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number +// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number +// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number +#define VPU_ASYNC_RD_MODE0 ((0x27a5 << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, req_en unsigned , default = 0 async enable +//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control +//Bit 15:12, auto_arugt_weight unsigned , default = 4 +//Bit 11, reserved +//Bit 10:9, arugt_sel unsigned , default = 0 +// 00 : use auto fifo arugt generate the output arugt. +// 01 : use the register bit control +// 00 : use the input arguent +//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit +//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold +//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold +#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, req_en unsigned , default = 0 async enable +//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control +//Bit 15:12, auto_arugt_weight unsigned , default = 4 +//Bit 11, reserved +//Bit 10:9, arugt_sel unsigned , default = 0 +// 00 : use auto fifo arugt generate the output arugt. +// 01 : use the register bit control +// 00 : use the input arguent +//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit +//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold +//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold +#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, req_en unsigned , default = 0 async enable +//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control +//Bit 15:12, auto_arugt_weight unsigned , default = 4 +//Bit 11, reserved +//Bit 10:9, arugt_sel unsigned , default = 0 +// 00 : use auto fifo arugt generate the output arugt. +// 01 : use the register bit control +// 00 : use the input arguent +//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit +//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold +//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold +#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, req_en unsigned , default = 0 async enable +//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control +//Bit 15:12, auto_arugt_weight unsigned , default = 4 +//Bit 11, reserved +//Bit 10:9, arugt_sel unsigned , default = 0 +// 00 : use auto fifo arugt generate the output arugt. +// 01 : use the register bit control +// 00 : use the input arguent +//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit +//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold +//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold +#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, req_en unsigned , default = 0 async enable +//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control +//Bit 15:12, auto_arugt_weight unsigned , default = 4 +//Bit 11, reserved +//Bit 10:9, arugt_sel unsigned , default = 0 +// 00 : use auto fifo arugt generate the output arugt. +// 01 : use the register bit control +// 00 : use the input arguent +//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit +//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold +//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold +#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, req_en unsigned , default = 0 async enable +//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control +//Bit 15:12, auto_arugt_weight unsigned , default = 4 +//Bit 11, reserved +//Bit 10:9, arugt_sel unsigned , default = 0 +// 00 : use auto fifo arugt generate the output arugt. +// 01 : use the register bit control +// 00 : use the input arguent +//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit +//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold +//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold +#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, req_en unsigned , default = 0 async enable +//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control +//Bit 15:12, auto_arugt_weight unsigned , default = 4 +//Bit 11, reserved +//Bit 10:9, arugt_sel unsigned , default = 0 +// 00 : use auto fifo arugt generate the output arugt. +// 01 : use the register bit control +// 00 : use the input arguent +//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit +//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold +//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold +#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, req_en unsigned , default = 0 async enable +//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control +//Bit 15:12, auto_arugt_weight unsigned , default = 4 +//Bit 11, reserved +//Bit 10:9, arugt_sel unsigned , default = 0 +// 00 : use auto fifo arugt generate the output arugt. +// 01 : use the register bit control +// 00 : use the input arguent +//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit +//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold +//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold +#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18, axiwr2_chan_idle unsigned , RO, axi write channel2 idle state +//Bit 17, axiwr1_chan_idle unsigned , RO, axi write channel1 idle state +//Bit 16, axiwr0_chan_idle unsigned , RO, axi write channel0 idle state +//Bit 15:5, reserved +//Bit 4, axird4_chan_idle unsigned , RO, axi read channel4 idle state +//Bit 3, axird3_chan_idle unsigned , RO, axi read channel3 idle state +//Bit 2, axird2_chan_idle unsigned , RO, axi read channel2 idle state +//Bit 1, axird1_chan_idle unsigned , RO, axi read channel1 idle state +//Bit 0, axird0_chan_idle unsigned , RO, axi read channel0 idle state +#define VPU_WRARB_MODE_L1C2 ((0x27ae << 2) + 0xff000000) +//Bit 31:18, reserved +//Bit 17:16, wrarb_sel uns, default = 0 , +// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1 +// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1 +//Bit 15:9, reserved +//Bit 8, wrarb_arb_mode uns, default = 0 , +// wrarb_arb_mode[0] master port0 arb way, +//Bit 7:2, reserved +//Bit 1:0, wrarb_gate_clk_ctrl uns, default = 0 , +// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control +#define VPU_WRARB_REQEN_SLV_L1C2 ((0x27af << 2) + 0xff000000) +//Bit 31:2, reserved +//Bit 1:0, wrarb_dc_req_en unsigned , default = 0 +// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable, +// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable, +#define VPU_WRARB_WEIGH0_SLV_L1C2 ((0x27b0 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0 +// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number +// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number +// wrdc_weigh_sxn[2*6+:6]: the slv1 req weigh number +// wrdc_weigh_sxn[3*6+:6]: the slv1 req weigh number +// wrdc_weigh_sxn[4*6+:6]: the slv1 req weigh number +#define VPU_WRARB_WEIGH1_SLV_L1C2 ((0x27b1 << 2) + 0xff000000) +//Bit 31:18, reserved +//Bit 17:0, wrdc_weigh_sxn unsigned , default = 0 +// wrdc_weigh_sxn[5*6+:6]: the slv0 req weigh number +// wrdc_weigh_sxn[6*6+:6]: the slv1 req weigh number +// wrdc_weigh_sxn[7*6+:6]: the slv1 req weigh number +#define VPU_RDARB_WEIGH1_SLV_L1C2 ((0x27b2 << 2) + 0xff000000) +//Bit 31:18, reserved +//Bit 17:0, rddc_weigh_sxn unsigned , default = 0 +// rddc_weigh_sxn[5*6+:6]: the slv0 req weigh number +// rddc_weigh_sxn[6*6+:6]: the slv1 req weigh number +// rddc_weigh_sxn[7*6+:6]: the slv2 req weigh number +#define VPU_ARB_DBG_CTRL_L1C1 ((0x27b3 << 2) + 0xff000000) +#define VPU_ARB_DBG_STAT_L1C1 ((0x27b4 << 2) + 0xff000000) +#define VPU_ARB_DBG_CTRL_L1C2 ((0x27b5 << 2) + 0xff000000) +#define VPU_ARB_DBG_STAT_L1C2 ((0x27b6 << 2) + 0xff000000) +#define VPU_ARB_DBG_CTRL_L2C1 ((0x27b7 << 2) + 0xff000000) +#define VPU_ARB_DBG_STAT_L2C1 ((0x27b8 << 2) + 0xff000000) +#define VPU_ARB_PATH_CTRL ((0x27b9 << 2) + 0xff000000) +#define VPU_ARB_PATH_MAP00 ((0x27ba << 2) + 0xff000000) +#define VPU_ARB_PATH_MAP01 ((0x27bb << 2) + 0xff000000) +#define VPU_ARB_PATH_MAP02 ((0x27bc << 2) + 0xff000000) +#define VPU_ARB_PATH_MAP03 ((0x27bd << 2) + 0xff000000) +#define VPU_ARB_PATH_MAP10 ((0x27be << 2) + 0xff000000) +#define VPU_ARB_PATH_MAP11 ((0x27bf << 2) + 0xff000000) +#define VPU_ARB_PATH_MAP12 ((0x27c0 << 2) + 0xff000000) +#define VPU_ARB_PATH_MAP13 ((0x27c1 << 2) + 0xff000000) +#define VPU_RDARB_UGT_L2C1 ((0x27c2 << 2) + 0xff000000) +#define VPU_WRARB_UGT_L2C1 ((0x27c3 << 2) + 0xff000000) +#define VPU_RDARB_LIMT0_L2C1 ((0x27c4 << 2) + 0xff000000) +#define VPU_RDARB_LIMT1_L2C1 ((0x27c5 << 2) + 0xff000000) +#define VPU_ARB_AXIWR_PROT ((0x27c6 << 2) + 0xff000000) +#define VPU_ARB_AXIRD0_PROT ((0x27c7 << 2) + 0xff000000) +#define VPU_ARB_AXIRD1_PROT ((0x27c8 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_arb_axi_regs.h +// +// vpu lut dma +// the segment is 8'h50~8'h7f & 8'hca-8'hdf +// +// Reading file: vpu_lut_dma_regs.h +// +// synopsys translate_off +// synopsys translate_on +// 0x50~0x7f +// +// Reading file: viu_dma_top.h +// +#define VPU_DMA_RDMIF0_CTRL ((0x2750 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_rd0_frm_ctrl // unsigned , RW , default = 0 +//Bit 26 reg_rd0_frm_froce // unsigned , RW , default = 0 +//Bit 25:24 reg_rd0_frm_ini // unsigned , RW , default = 0 +//Bit 23:16 reg_rd0_enable_int // unsigned , RW , default = 0 channel0 select interrupt source +//Bit 15:13 reserved +//Bit 12:0 reg_rd0_stride // unsigned , RW , default = 512 channel0 send number +#define VPU_DMA_RDMIF1_CTRL ((0x2751 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_rd1_frm_ctrl // unsigned , RW , default = 0 +//Bit 26 reg_rd1_frm_froce // unsigned , RW , default = 0 +//Bit 25:24 reg_rd1_frm_ini // unsigned , RW , default = 0 +//Bit 23:16 reg_rd1_enable_int // unsigned , RW , default = 0 channel1 select interrupt source +//Bit 15:13 reserved +//Bit 12:0 reg_rd1_stride // unsigned , RW , default = 512 channel1 send number +#define VPU_DMA_RDMIF2_CTRL ((0x2752 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_rd2_frm_ctrl // unsigned , RW , default = 0 +//Bit 26 reg_rd2_frm_froce // unsigned , RW , default = 0 +//Bit 25:24 reg_rd2_frm_ini // unsigned , RW , default = 0 +//Bit 23:16 reg_rd2_enable_int // unsigned , RW , default = 0 channel2 select interrupt source +//Bit 15:13 reserved +//Bit 12:0 reg_rd2_stride // unsigned , RW , default = 512 channel2 send number +#define VPU_DMA_RDMIF3_CTRL ((0x2753 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_rd3_frm_ctrl // unsigned , RW , default = 0 +//Bit 26 reg_rd3_frm_froce // unsigned , RW , default = 0 +//Bit 25:24 reg_rd3_frm_ini // unsigned , RW , default = 0 +//Bit 23:16 reg_rd3_enable_int // unsigned , RW , default = 0 channel3 select interrupt source +//Bit 15:13 reserved +//Bit 12:0 reg_rd3_stride // unsigned , RW , default = 512 channel3 send number +#define VPU_DMA_RDMIF4_CTRL ((0x2754 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_rd4_frm_ctrl // unsigned , RW , default = 0 +//Bit 26 reg_rd4_frm_froce // unsigned , RW , default = 0 +//Bit 25:24 reg_rd4_frm_ini // unsigned , RW , default = 0 +//Bit 23:16 reg_rd4_enable_int // unsigned , RW , default = 0 channel4 select interrupt source +//Bit 15:13 reserved +//Bit 12:0 reg_rd4_stride // unsigned , RW , default = 512 channel4 send number +#define VPU_DMA_RDMIF5_CTRL ((0x2755 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_rd5_frm_ctrl // unsigned , RW , default = 0 +//Bit 26 reg_rd5_frm_froce // unsigned , RW , default = 0 +//Bit 25:24 reg_rd5_frm_ini // unsigned , RW , default = 0 +//Bit 23:16 reg_rd5_enable_int // unsigned , RW , default = 0 channel5 select interrupt source +//Bit 15:13 reserved +//Bit 12:0 reg_rd5_stride // unsigned , RW , default = 512 channel5 send number +#define VPU_DMA_RDMIF6_CTRL ((0x2756 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_rd6_frm_ctrl // unsigned , RW , default = 0 +//Bit 26 reg_rd6_frm_froce // unsigned , RW , default = 0 +//Bit 25:24 reg_rd6_frm_ini // unsigned , RW , default = 0 +//Bit 23:16 reg_rd6_enable_int // unsigned , RW , default = 0 channel6 select interrupt source +//Bit 15:13 reserved +//Bit 12:0 reg_rd6_stride // unsigned , RW , default = 512 channel6 send number +#define VPU_DMA_RDMIF7_CTRL ((0x2757 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_rd7_frm_ctrl // unsigned , RW , default = 0 +//Bit 26 reg_rd7_frm_froce // unsigned , RW , default = 0 +//Bit 25:24 reg_rd7_frm_ini // unsigned , RW , default = 0 +//Bit 23:16 reg_rd7_enable_int // unsigned , RW , default = 0 channel7 select interrupt source +//Bit 15:13 reserved +//Bit 12:0 reg_rd7_stride // unsigned , RW , default = 512 channel7 send number +#define VPU_DMA_RDMIF0_BADR0 ((0x2758 << 2) + 0xff000000) +//Bit 31:0 lut0_reg_baddr0 +#define VPU_DMA_RDMIF0_BADR1 ((0x2759 << 2) + 0xff000000) +//Bit 31:0 lut0_reg_baddr1 +#define VPU_DMA_RDMIF0_BADR2 ((0x275a << 2) + 0xff000000) +//Bit 31:0 lut0_reg_baddr2 +#define VPU_DMA_RDMIF0_BADR3 ((0x275b << 2) + 0xff000000) +//Bit 31:0 lut0_reg_baddr3 +#define VPU_DMA_RDMIF1_BADR0 ((0x275c << 2) + 0xff000000) +//Bit 31:0 lut1_reg_baddr0 +#define VPU_DMA_RDMIF1_BADR1 ((0x275d << 2) + 0xff000000) +//Bit 31:0 lut1_reg_baddr1 +#define VPU_DMA_RDMIF1_BADR2 ((0x275e << 2) + 0xff000000) +//Bit 31:0 lut1_reg_baddr2 +#define VPU_DMA_RDMIF1_BADR3 ((0x275f << 2) + 0xff000000) +//Bit 31:0 lut1_reg_baddr3 +#define VPU_DMA_RDMIF2_BADR0 ((0x2760 << 2) + 0xff000000) +//Bit 31:0 lut2_reg_baddr0 +#define VPU_DMA_RDMIF2_BADR1 ((0x2761 << 2) + 0xff000000) +//Bit 31:0 lut2_reg_baddr1 +#define VPU_DMA_RDMIF2_BADR2 ((0x2762 << 2) + 0xff000000) +//Bit 31:0 lut2_reg_baddr2 +#define VPU_DMA_RDMIF2_BADR3 ((0x2763 << 2) + 0xff000000) +//Bit 31:0 lut2_reg_baddr3 +#define VPU_DMA_RDMIF3_BADR0 ((0x2764 << 2) + 0xff000000) +//Bit 31:0 lut3_reg_baddr0 +#define VPU_DMA_RDMIF3_BADR1 ((0x2765 << 2) + 0xff000000) +//Bit 31:0 lut3_reg_baddr1 +#define VPU_DMA_RDMIF3_BADR2 ((0x2766 << 2) + 0xff000000) +//Bit 31:0 lut3_reg_baddr2 +#define VPU_DMA_RDMIF3_BADR3 ((0x2767 << 2) + 0xff000000) +//Bit 31:0 lut3_reg_baddr3 +#define VPU_DMA_RDMIF4_BADR0 ((0x2768 << 2) + 0xff000000) +//Bit 31:0 lut4_reg_baddr0 +#define VPU_DMA_RDMIF4_BADR1 ((0x2769 << 2) + 0xff000000) +//Bit 31:0 lut4_reg_baddr1 +#define VPU_DMA_RDMIF4_BADR2 ((0x276a << 2) + 0xff000000) +//Bit 31:0 lut4_reg_baddr2 +#define VPU_DMA_RDMIF4_BADR3 ((0x276b << 2) + 0xff000000) +//Bit 31:0 lut4_reg_baddr3 +#define VPU_DMA_RDMIF5_BADR0 ((0x276c << 2) + 0xff000000) +//Bit 31:0 lut5_reg_baddr0 +#define VPU_DMA_RDMIF5_BADR1 ((0x276d << 2) + 0xff000000) +//Bit 31:0 lut5_reg_baddr1 +#define VPU_DMA_RDMIF5_BADR2 ((0x276e << 2) + 0xff000000) +//Bit 31:0 lut5_reg_baddr2 +#define VPU_DMA_RDMIF5_BADR3 ((0x276f << 2) + 0xff000000) +//Bit 31:0 lut5_reg_baddr3 +#define VPU_DMA_RDMIF6_BADR0 ((0x2770 << 2) + 0xff000000) +//Bit 31:0 lut6_reg_baddr0 +#define VPU_DMA_RDMIF6_BADR1 ((0x2771 << 2) + 0xff000000) +//Bit 31:0 lut6_reg_baddr1 +#define VPU_DMA_RDMIF6_BADR2 ((0x2772 << 2) + 0xff000000) +//Bit 31:0 lut6_reg_baddr2 +#define VPU_DMA_RDMIF6_BADR3 ((0x2773 << 2) + 0xff000000) +//Bit 31:0 lut6_reg_baddr3 +#define VPU_DMA_RDMIF7_BADR0 ((0x2774 << 2) + 0xff000000) +//Bit 31:0 lut7_reg_baddr0 +#define VPU_DMA_RDMIF7_BADR1 ((0x2775 << 2) + 0xff000000) +//Bit 31:0 lut7_reg_baddr1 +#define VPU_DMA_RDMIF7_BADR2 ((0x2776 << 2) + 0xff000000) +//Bit 31:0 lut7_reg_baddr2 +#define VPU_DMA_RDMIF7_BADR3 ((0x2777 << 2) + 0xff000000) +//Bit 31:0 lut7_reg_baddr3 +// +// Closing file: viu_dma_top.h +// +// 0x00~0x06 +//`include"viu_com_rdmif_regs.h" +#define VPU_DMA_RDMIF_CTRL1 ((0x27ca << 2) + 0xff000000) +#define VPU_DMA_RDMIF_CTRL2 ((0x27cb << 2) + 0xff000000) +#define VPU_DMA_RDMIF_RO_STAT ((0x27d0 << 2) + 0xff000000) +//0x07~0x0d +//`include"viu_com_wrmif_regs.h" +#define VPU_DMA_WRMIF_CTRL1 ((0x27d1 << 2) + 0xff000000) +#define VPU_DMA_WRMIF_CTRL2 ((0x27d2 << 2) + 0xff000000) +#define VPU_DMA_WRMIF_CTRL3 ((0x27d3 << 2) + 0xff000000) +#define VPU_DMA_WRMIF_BADDR0 ((0x27d4 << 2) + 0xff000000) +#define VPU_DMA_WRMIF_RO_STAT ((0x27d7 << 2) + 0xff000000) +#define VPU_DMA_RDMIF_CTRL ((0x27d8 << 2) + 0xff000000) +#define VPU_DMA_RDMIF_BADDR1 ((0x27d9 << 2) + 0xff000000) +#define VPU_DMA_RDMIF_BADDR2 ((0x27da << 2) + 0xff000000) +#define VPU_DMA_RDMIF_BADDR3 ((0x27db << 2) + 0xff000000) +#define VPU_DMA_WRMIF_CTRL ((0x27dc << 2) + 0xff000000) +#define VPU_DMA_WRMIF_BADDR1 ((0x27dd << 2) + 0xff000000) +#define VPU_DMA_WRMIF_BADDR2 ((0x27de << 2) + 0xff000000) +#define VPU_DMA_WRMIF_BADDR3 ((0x27df << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_lut_dma_regs.h +// +// the segment is 8'he0-8'hef +#define VPU_VENCL_DITH_CTRL ((0x27e0 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_1 ((0x27e1 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_2 ((0x27e2 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_3 ((0x27e3 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_4 ((0x27e4 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_5 ((0x27e5 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_6 ((0x27e6 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_7 ((0x27e7 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_8 ((0x27e8 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_9 ((0x27e9 << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_10 ((0x27ea << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_11 ((0x27eb << 2) + 0xff000000) +#define VPU_VENCL_DITH_LUT_12 ((0x27ec << 2) + 0xff000000) +//new added 4x4 dither +// the segment is 8'hf0 +#define VPU_HDMI_DITH_01_04 ((0x27f0 << 2) + 0xff000000) +#define VPU_HDMI_DITH_01_15 ((0x27f1 << 2) + 0xff000000) +#define VPU_HDMI_DITH_01_26 ((0x27f2 << 2) + 0xff000000) +#define VPU_HDMI_DITH_01_37 ((0x27f3 << 2) + 0xff000000) +#define VPU_HDMI_DITH_10_04 ((0x27f4 << 2) + 0xff000000) +#define VPU_HDMI_DITH_10_15 ((0x27f5 << 2) + 0xff000000) +#define VPU_HDMI_DITH_10_26 ((0x27f6 << 2) + 0xff000000) +#define VPU_HDMI_DITH_10_37 ((0x27f7 << 2) + 0xff000000) +#define VPU_HDMI_DITH_11_04 ((0x27f8 << 2) + 0xff000000) +#define VPU_HDMI_DITH_11_15 ((0x27f9 << 2) + 0xff000000) +#define VPU_HDMI_DITH_11_26 ((0x27fa << 2) + 0xff000000) +#define VPU_HDMI_DITH_11_37 ((0x27fb << 2) + 0xff000000) +#define VPU_HDMI_DITH_CNTL ((0x27fc << 2) + 0xff000000) +#define VPU_HDMI_TIMING_STAT ((0x27fd << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_top_regs.h +// +//======================================================================== +// MIPI CSI2 Controller Adaptor (16'h2a00 - 16'h2aff) +// +//======================================================================== +//`include "csi2_regs.h" +//====================================================================== +// D2D3 registers +//====================================================================== +// +// Reading file: d2d3_regs.h +// +//=========================================================================== +// D2D3 Registers 0x - 0x +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: D2D3_VCBUS_BASE = 0x2b +// ----------------------------------------------- +//------------------------------------------------------------------------------ +// D2D3 top-level registers +//------------------------------------------------------------------------------ +// Bit 31 RW, rd_lock_en, 1 to allow update some read-only registers based on filed +// Bit 30 RW, sw_rst_nobuf, 1 to reset the whole d2d3 unit +// Bit 29:28 RW, clk_auto_dis, [29] DBR clock disable +// [28] DPG clock disable +// Bit 27:16 RW, clk_ctrl, [27:26] gated clock control for register unit +// [25:24] gated clock control for DBR unit +// [23:22] gated clock control for LBDG unit +// [21:20] gated clock control for MBDG unit +// [19:18] gated clock control for CBDG unit +// [17:16] gated clock control for DBLD unit and SCD81 unit +// Bit 15:12 Reserved +// Bit 11 RW, lo_chroma_sign, 0: negate the u/v component of DBR left channel video output, 1: bypass +// Bit 10 RW, ro_chroma_sign, 0: negate the u/v component of DBR right channel video output, 1: bypass +// Bit 9 RW, vi0_chroma_sign, 0: negate the u/v component of DPG video input, 1: bypass +// Bit 8 RW, vi1_chroma_sign, 0: negate the u/v component of DBR video input, 1: bypass +// Bit 7:5 Reserved +// Bit 4 RW, lg_en, Enable the LBDG unit and LBDG clock +// Bit 3 RW, mg_en, Enable the MBDG unit and MBDG clock +// Bit 2 RW, cg_en, Enable the CBDG unit and CBDG clock +// Bit 1 RW, dbr_en, Enable the DBR unit and DBR clock +// Bit 0 RW, dpg_en, Enable the DPG unit and clock except sub-unit CBDG, MBDG and LBDG +#define D2D3_GLB_CTRL ((0x2b00 << 2) + 0xff000000) +// Indicate the input picture size in DPG unit +// Bit 31:16 RW, szx_vi_m1, The horizontal size minus 1 +// Bit 15:0 RW, szy_vi_m1, The vertical size minus 1 +#define D2D3_DPG_INPIC_SIZE ((0x2b01 << 2) + 0xff000000) +// Indicate the output picture size in DBR unit +// Bit 31:16 RW, szx_vo_m1, The horizontal size minus 1 +// Bit 15:0 RW, szy_vo_m1, The vertical size minus 1 +#define D2D3_DBR_OUTPIC_SIZE ((0x2b02 << 2) + 0xff000000) +// Indicate the rectangular window to generate the "depth" in DPG unit +// Bit 31:16 RW, dg_win_x_start, Horizontal start position, count from 0 +// Bit 15:0 RW, dg_win_x_end, Horizontal end position, count from 0 +#define D2D3_DGEN_WIN_HOR ((0x2b03 << 2) + 0xff000000) +// Indicate the rectangular window to generate the "depth" in DPG unit +// Bit 31:16 RW, dg_win_y_start, Vertical start position, count from 0 +// Bit 15:0 RW, dg_win_y_end, Vertical end position, count from 0 +#define D2D3_DGEN_WIN_VER ((0x2b04 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// CBDG SCU18 SCD81 SCD81_PRE registers +// cg: color based depth generate module +// scu18: scale up module +// scd81: scale down module +// scd81_pre: scd81 pre-scale-down module +//------------------------------------------------------------------------------ +// Indicate parameters of pre-scale-down unit +// Bit 31:16 RW, scd81_hphs_step, horizontal step +// Bit 15:0 RW, scd81_hphs_ini, horizontal initial phase +#define D2D3_PRE_SCD_H ((0x2b05 << 2) + 0xff000000) +// Bit 31:16 RW, scu18_iniph, initial phase in SCU18, +// [23:16] indicate the horizontal phase offset from the first data of every line +// [31:24] indicate the vertical phase offset from the first line of every frame +// Bit 15:12 Reserved +// Bit 11 RW, scd81_predrop_en, 1 to enable scd81 pre-scale-down function +// Bit 10:9 RW, cg_csc_sel, Color Space Conversion(CSC) matrix mode selector in CBDG +// 0: BT.601 (16-235/240) +// 1: BT.709 (16-235/240) +// 2: BT.601 (0-255) +// 3: BT.709 (0-255) +// Bit 8 RW, scu18_rep_en, 1 to double each line of the SCU18 output +// Bit 7:4 RW, scu18_factor, up-scale factor in SCU18 on DBR input depth data +// [7:6] for vertical, 0->1:1, 1->1:2, 2->1:4, 3->1:8 +// [5:4] for horizontal, 0->1:1, 1->1:2, 2->1:4, 3->1:8 +// Bit 3:0 RW, scd81_factor, down-scale factor in SCD81 on DPG source video +// [3:2] for vertical, 0->1:1, 1->2:1, 2->4:1, 3->8:1 +// [1:0] for horizontal, 0->1:1, 1->2:1, 2->4:1, 3->8:1 +#define D2D3_SCALER_CTRL ((0x2b06 << 2) + 0xff000000) +// Bit 31:24 RW, cg_rpg_dth, the down |r-g| threshold for sky detect +// Bit 23:16 RW, cg_rpg_uth, the up |r-g| threshold for sky detect +// Bit 15:8 RW, cg_lum_dth, the down Y threshold for sky detect +// Bit 7:0 RW, cg_lum_uth, the up Y threshold for sky detect +#define D2D3_CG_THRESHOLD_1 ((0x2b07 << 2) + 0xff000000) +// Bit 31:24 RW, cg_rpb_dth, the down |r-b| threshold for sky detect +// Bit 23:16 RW, cg_rpb_uth, the up |r-b| threshold for sky detect +// Bit 15:8 RW, cg_bpg_dth, the down |b-g| threshold for sky detect +// Bit 7:0 RW, cg_bpg_uth, the up |b-g| threshold for sky detect +#define D2D3_CG_THRESHOLD_2 ((0x2b08 << 2) + 0xff000000) +// Bit 31:24 RW, cg_vp_rel_k, parameter to calculate vanish point reliability +// Bit 23:16 RW, cg_vp_y_thr, the max limitation to calculate the vanish-point's vertical position +// Bit 15:8 RW, cg_meet_dval, signed depth value in the sky-bitmap +// Bit 7:0 RW, cg_unmt_dval, signed depth value not in the sky-bitmap +#define D2D3_CG_PARAM_1 ((0x2b09 << 2) + 0xff000000) +// Bit 31:16 RW, cg_vpos_thr, Maximal vertical limitation for sky-bit map when cg_vpos_en=1 and cg_vpos_adpt_en=0 +// Bit 15:8 Reserved +// Bit 7 RW, cg_vpos_en, 1 to enable the max vertical limitation for sky-bitmap +// Bit 6 RW, cg_vpos_adpt_en, 1 to enable the adaptive max vertical limitation for sky-bitmap. +// It is only valid when cg_vpos_en=1. +// The max vertical limitation is the previous field's vanish-point (vertical position) if cg_vpos_adpt_en=1. +// Bit 5:4 RW, cg_lpf_bypass, bypass of low pass filter +// [5]:Vertical bypass, 1: bypass the vertical LPF on the CBDG depth +// [4]:Horizontal bypass, 1: bypass the horizontal LPF on the CBDG depth +// Bit 3:0 RW, cg_vp_rel_s, parameter to calculate vanish point reliability +#define D2D3_CG_PARAM_2 ((0x2b0a << 2) + 0xff000000) +// Indicate parameters of pre-scale-down unit +// Bit 31:16 RW, scd81_vphs_step, vertical step +// Bit 15:0 RW, scd81_vphs_ini, vertical initial phase +#define D2D3_PRE_SCD_V ((0x2b0b << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// D2P registers +// d2p: depth to parallax transform module +//------------------------------------------------------------------------------ +// Bit 31:24 RW, d2p_brdwid, Horizontal boundary width for parallax, the parallax value would be forced to 0 in boundary, +// the d2p_brdwid should not 0 when D2P_WRAP is enabled +// Bit 23:22 Reserved +// Bit 21:20 RW, d2p_lomode, line output mode, +// 0:whole line is left or right; 1:whole line is left or right; +// 2:left/right pixel interleaved; 3:left/right half-line interleaved +// Bit 19 RW, d2p_neg, 1 to exchange the left and right parallax value +// Bit 18 Reserved +// Bit 17 RW, d2p_wrap_en, 1 to enable D2P_WRAP unit +// Bit 16 RW, d2p_lar, Indicate the first output for left or right, 0: left; 1: right +// Bit 15 RW, d2p_lr_switch, enable left/right flag filed switch automatically, only valid when parallax output mode is field interleaved +// Bit 14 RW, d2p_1dtolr, enable to generate 2 parallax data (left and right) from one depth +// Bit 13:12 RW, d2p_out_mode, Parallax output mode +// 0:left/right pixel interleaved; 1:line or half line interleaved; 2:field interleaved +// Bit 11:8 RW, d2p_smode, Shift mode, +// 0: no shift; 1: enable left shift; +// 2: enable right shift; 3: both left and right shift are enabled +// Bit 7:0 RW, d2p_offset, depth offset, signed, +#define D2D3_D2P_PARAM_1 ((0x2b0c << 2) + 0xff000000) +// Bit 31:24 RW, d2p_pg0, positive parallax gain when Parallax value < pt +// Bit 23:16 RW, d2p_pg1, positive parallax gain when Parallax value >= pt +// Bit 15:8 RW, d2p_pt, unsigned value used to separate the positive parallax range +// Bit 7:0 RW, d2p_plimit, The limitation for positive parallax +#define D2D3_D2P_PARAM_2 ((0x2b0d << 2) + 0xff000000) +// Bit 31:24 RW, d2p_ng0, negative parallax gain when Parallax value > -nt +// Bit 23:16 RW, d2p_ng1, negative parallax gain when Parallax value <= -nt +// Bit 15:8 RW, d2p_nt, unsigned value used to separate the negative parallax range +// Bit 7:0 RW, d2p_nlimit, The limitation for negative parallax +#define D2D3_D2P_PARAM_3 ((0x2b0e << 2) + 0xff000000) +// Indicate step parameters of SCU18 unit +// Bit 31:17 Reserved +// Bit 16 RW, scu18_step_en, step set enable in SCU18 +// Bit 15:8 RW, scu18_hphs_step, horizontal step in SCU18 +// Bit 7:0 RW, scu18_vphs_step, vertical step in SCU18 +#define D2D3_SCU18_STEP ((0x2b0f << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// LBDG and DBLD registers +// lg: luma based depth generate module +// db: depth blending module +//------------------------------------------------------------------------------ +// Bit 31:22 Reserved +// Bit 21:20 RW, db_lpf_bpcoeff, [21]:Vertical factor of low pass filter, +// 1: Vfactor = 0/0/64/0/0, 0: Vfactor = {db_vf_a,db_vf_b,db_vf_c,db_vf_b,db_vf_a}, see D2D3_CTRL_15 +// [20]:Horizontal factor of low pass filter, +// 1: Hfactor = 0/0/64/0/0, 0: Hfactor = {db_hf_a,db_hf_b,db_hf_c,db_hf_b,db_hf_a}, see D2D3_CTRL_14 +// Bit 19:18 RW, lg_lpf_bpcoeff, [19]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20 +// [18]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16 +// Bit 17:16 RW, cg_lpf_bpcoeff, [17]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20 +// [16]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16 +// Bit 15:10 Reserved +// Bit 9:8 RW, db_lpf_bypass, [9] 1 to bypass the vertical LPF on the DBLD depth +// [8] 1 to bypass the horizontal LPF on the DBLD depth +// Bit 7:6 RW, lg_lpf_bypass, [7] 1 to bypass the vertical LPF on the LBDG depth +// [6] 1 to bypass the horizontal LPF on the LBDG depth +// Bit 5:0 RW, lg_kc, gain of CPL(v-u+256-y) to calculate the depth in LBDG +#define D2D3_DPF_LPF_CTRL ((0x2b10 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// DBLD registers +// db: depth blending module +//------------------------------------------------------------------------------ +// Bit 31:24 RW, db_g2_cg, gain of CBDG depth in DBLD +// Bit 23:16 RW, db_o2_cg, offset of CBDG depth in DBLD +// Bit 15:8 RW, db_g1_cg, gain of CBDG depth using for summary in DBLD +// Bit 7:0 RW, db_o1_cg, offset of CBDG depth using for summary in DBLD +#define D2D3_DBLD_CG_PARAM ((0x2b11 << 2) + 0xff000000) +// Bit 31:24 RW, db_g2_mg, gain of MBDG depth in DBLD +// Bit 23:16 RW, db_o2_mg, offset of MBDG depth in DBLD +// Bit 15:8 RW, db_g1_mg, gain of MBDG depth using for summary in DBLD +// Bit 7:0 RW, db_o1_mg, offset of MBDG depth using for summary in DBLD +#define D2D3_DBLD_MG_PARAM ((0x2b12 << 2) + 0xff000000) +// Bit 31:24 RW, db_g2_lg, gain of LBDG depth in DBLD +// Bit 23:16 RW, db_o2_lg, offset of LBDG depth in DBLD +// Bit 15:8 RW, db_g1_lg, gain of LBDG depth using for summary in DBLD +// Bit 7:0 RW, db_o1_lg, offset of LBDG depth using for summary in DBLD +#define D2D3_DBLD_LG_PARAM ((0x2b13 << 2) + 0xff000000) +// Bit 31:24 RW, db_factor, unsigned gain of difference in DBLD +// Bit 23:16 RW, db_hf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign +// Bit 15:8 RW, db_hf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign +// Bit 7:0 RW, db_hf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign +#define D2D3_DBLD_LPF_HCOEFF ((0x2b14 << 2) + 0xff000000) +// Bit 31:24 RW, db_owin_fill, signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER +// Bit 23:16 RW, db_vf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign +// Bit 15:8 RW, db_vf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign +// Bit 7:0 RW, db_vf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign +#define D2D3_DBLD_LPF_VCOEFF ((0x2b15 << 2) + 0xff000000) +// Bit 31:28 RW, hist_depth_idx, +// Bit 27:26 Reserved +// Bit 25 RW, mbdg_dep_neg, 1 to negate the output data of MBDG +// Bit 24 RW, lbdg_dep_neg, 1 to negate the output data of LBDG +// Bit 23:16 RW, db_f1_ctrl, MUX1 selector +// [1:0] MUX1 path1 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG +// [3:2] MUX1 path2 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG +// [6:4] MUX1 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX1out0, others:summary +// [7] MUX1OUT0 selector, 0:MIN (MUX1PATH1,MUX1Path2), 1:MAX (MUX1Path1,MUX1Path2) +// Bit 15:8 RW, db_f2_ctrl, MUX2 selector +// [1:0] MUX2 path1 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG +// [3:2] MUX2 path2 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG +// [6:4] MUX2 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX2out0, others:MUX2out0 +// [7] MUX2OUT0 selector, 0:MIN (MUX2PATH1,MUX2Path2), 1:MAX (MUX2Path1,MUX2Path2) +// Bit 7:4 RW, db_fifo0_sel, the source input of FIFO0 +// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG others:reserved +// Bit 3:0 RW, db_fifo1_sel, the source input of FIFO1 +// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG 4: from FIFO0; others:reserved +#define D2D3_DBLD_PATH_CTRL ((0x2b16 << 2) + 0xff000000) +// Indicate the input picture size in SCU18 unit +// Bit 31:16 RW, szy_scui, The vertical size +// Bit 15:0 RW, szx_scui, The horizontal size +#define D2D3_SCU18_INPIC_SIZE ((0x2b17 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// MBDG registers +// mg: model based depth generate module +//------------------------------------------------------------------------------ +// Bit 31:18 Reserved +// Bit 17 RW, mg_vp_en, mdg vanish point enable, not used +// Bit 16 RW, mg_sw_en, 1 to use the software forced parameter for the point D, U and C in MBDG +// Bit 15:8 RW, mg_owin_fill, Signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER +// Bit 7 RW, mg_iir_en, 1 to enable the 2-taps IIR filter in MBDG +// Bit 6:0 RW, mg_iir, [6]: 1 to bypass the 2-taps IIR filter in MBDG +// [5:0]:Unsigned coefficient of the 2-taps IIR filter in MBDG +// [6]:bypass, 1:bypass, 0:not bypass +#define D2D3_MBDG_CTRL ((0x2b18 << 2) + 0xff000000) +// Bit 31:28 RW, mg_dtl_pxl_left, Max pixel number (1<< mg_dtl_pxl_left) using in the left window for activities in MBDG +// Bit 27:24 RW, mg_dtl_pxl_right, Max pixel number (1<< mg_dtl_pxl_right) using in the right window for activities in MBDG +// Bit 23:16 RW, mg_cx_sw, Depth of point C in horizontal curve in MBDG for software forced +// Bit 15:8 RW, mg_ux_sw, Depth of point U in horizontal curve in MBDG for software forced +// Bit 7:0 RW, mg_dx_sw, Depth of point D in horizontal curve in MBDG for software forced +#define D2D3_MBDG_PARAM_0 ((0x2b19 << 2) + 0xff000000) +// Bit 31:28 RW, mg_dtl_pxl_up, Max pixel number (1<< mg_dtl_pxl_up) using in the top window for activities in MBDG +// Bit 27:24 RW, mg_dtl_pxl_dn, Max pixel number (1<< mg_dtl_pxl_dn) using in the bottom window for activities in MBDG +// Bit 23:16 RW, mg_cy_sw, Depth of point C in vertical curve in MBDG for software forced +// Bit 15:8 RW, mg_uy_sw, Depth of point U in vertical curve in MBDG for software forced +// Bit 7:0 RW, mg_dy_sw, Depth of point D in vertical curve in MBDG for software forced +#define D2D3_MBDG_PARAM_1 ((0x2b1a << 2) + 0xff000000) +// Bit 31:24 RW, mg_dtl_ln_up, Line number in the top window for activities in MBDG +// Bit 23:16 RW, mg_dtl_ln_dn, Line number in the bottom window for activities in MBDG +// Bit 15:8 RW, mg_dtl_ln_left, Column number in the left window for activities in MBDG +// Bit 7:0 RW, mg_dtl_ln_right,Column number in the right window for activities in MBDG +#define D2D3_MBDG_PARAM_2 ((0x2b1b << 2) + 0xff000000) +// Bit 31:24 RW, mg_y_max, Software initial depth of point D and U in vertical curve +// Bit 23:16 RW, mg_y_min, Software initial depth of point C in vertical curve +// Bit 15:8 RW, mg_x_max, Software initial depth of point D and U in horizontal curve +// Bit 7:0 RW, mg_x_min, Software initial depth of point C in horizontal curve +#define D2D3_MBDG_PARAM_3 ((0x2b1c << 2) + 0xff000000) +// Bit 31:27 Reserved +// Bit 26 RW, mg_y_adapt_en, 1 to enable the adaptive mode for point U/D in vertical curve calculation +// Bit 25 RW, mg_xmm_adapt_en, 1 to enable the XMM adaptive mode for point U/D in horizontal curve calculation +// Bit 24 RW, mg_x_adapt_en, 1 to enable the adaptive mode for point U/D in horizontal curve calculation +// Bit 23:20 RW, mg_ytrans_1, Shifter controller in vertical curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits +// Bit 19:16 RW, mg_xtrans_1, Shifter controller in horizontal curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits +// Bit 15:8 RW, mg_yk_0, The based activities value of the ACT for vertical curve +// Bit 7:0 RW, mg_xk_0, The based activities value of the ACT for horizontal curve +#define D2D3_MBDG_PARAM_4 ((0x2b1d << 2) + 0xff000000) +// Bit 31:24 RW, mg_ysu3, Quantized value 3 in vertical curve adaptive calculation +// Bit 23:16 RW, mg_ysu2, Quantized value 2 in vertical curve adaptive calculation +// Bit 15:8 RW, mg_ysu1, Quantized value 1 in vertical curve adaptive calculation +// Bit 7:0 RW, mg_ysu0, Quantized value 0 in vertical curve adaptive calculation +#define D2D3_MBDG_PARAM_5 ((0x2b1e << 2) + 0xff000000) +// Bit 31:24 RW, mg_xsu3, Quantized value 3 in horizontal curve adaptive calculation +// Bit 23:16 RW, mg_xsu2, Quantized value 2 in horizontal curve adaptive calculation +// Bit 15:8 RW, mg_xsu1, Quantized value 1 in horizontal curve adaptive calculation +// Bit 7:0 RW, mg_xsu0, Quantized value 0 in horizontal curve adaptive calculation +#define D2D3_MBDG_PARAM_6 ((0x2b1f << 2) + 0xff000000) +// Bit 31:16 Reserved +// Bit 15:8 RW, mg_xsu4, Quantized value 4 in horizontal curve adaptive calculation +// Bit 7:0 RW, mg_ysu4, Quantized value 4 in vertical curve adaptive calculation +#define D2D3_MBDG_PARAM_7 ((0x2b20 << 2) + 0xff000000) +// Bit 31:28 RW, dbg_hscnt_sel see DBG_STATUS_2 +// Bit 27:25 Reserved +// Bit 24 RW, dbg_dbr_en, 1 to enable debug mode in DBR +// Bit 23:16 RW, dbg_force_data, Forced data in debug mode +// Bit 15:12 RW, dbg_bld_ctrl, debug controller for DBLD +// [12]:enable; [13]: 0 for passive mode, 0 for handshake mode +// [15:14]: 0 for constant mode, 1 for step1 mode +// Bit 11:8 RW, dbg_mg_ctrl, debug controller for MBDG +// [8]:enable; [9]: 0 for passive mode, 0 for handshake mode +// [11:10]: 0 for constant mode, 1 for step1 mode +// Bit 7:4 RW, dbg_cg_ctrl, debug controller for CBDG +// [4]:enable; [5]: 0 for passive mode, 0 for handshake mode +// [7:6]: 0 for constant mode, 1 for step1 mode +// Bit 3:0 RW, dbg_lg_ctrl, debug controller for LBDG +// [0]:enable; [1]: 0 for passive mode, 0 for handshake mode +// [3:2]: 0 for constant mode, 1 for step1 mode +#define D2D3_DBG_CTRL ((0x2b23 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// DWMIF registers +//------------------------------------------------------------------------------ +// Bit 31:18 Reserved +// Bit 17 RW, dw_x_rev 0: Normal write data from left to right in horizontal +// 1: Reversed write data from left to right in horizontal +// Bit 16 RW, dw_y_rev 0: Normal write data from top to bottom in horizontal +// 1: Reversed write data from bottom to top in horizontal +// Bit 15 RW, dw_done_clr 1 to clear register depw_done (DWMIF_STATUS) +// Bit 14 RW, dw_little_endian, 0: data is ordered in big-endian, 1: little endian +// Bit 13:12 RW, dw_pic_struct, 0:read every line, 1:reserved, 2:read even line, 3:read odd line +// Bit 11 RW, dw_urgent, urgent index +// Bit 10 RW, dw_clr_wrrsp, 1:clear the write fifo counter +// Bit 9 RW, dw_canvas_wr, canvas write initialization again +// Bit 8 RW, dw_req_en, 1 to enable write request +// Bit 7:0 RW, dw_canvas_index,Canvas index for the MSB of memory address for memory write +#define D2D3_DWMIF_CTRL ((0x2b24 << 2) + 0xff000000) +// Bit 31 Reserved +// Bit 30:16 RW, dw_end_x, Horizontal end position for memory write, count by BYTE +// Bit 15 Reserved +// Bit 14:0 RW, dw_start_x, Horizontal start position for memory write, count by BYTE +#define D2D3_DWMIF_HPOS ((0x2b25 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 RW, dw_end_y, Vertical end position for memory write, count by BYTE +// Bit 15:13 Reserved +// Bit 12:0 RW, dw_start_y, Vertical start position for memory write, count by BYTE +#define D2D3_DWMIF_VPOS ((0x2b26 << 2) + 0xff000000) +// Bit 31:28 Reserved +// Bit 27:16 RW, dw_vsizem1, Vertical size for memory write, equal the size minus 1 +// Bit 15:12 Reserved +// Bit 11:0 RW, dw_hsizem1, Horizontal size for memory write, equal the size minus 1 +#define D2D3_DWMIF_SIZE ((0x2b27 << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// DRMIF registers +//------------------------------------------------------------------------------ +// Bit 31:18 Reserved +// Bit 17 RW, dr_y_rev, 0: Normal Read data from top to bottom in horizontal +// 1: Reversed read data from bottom to top in horizontal +// Bit 16 RW, dr_x_rev, 0: Normal Read data from left to right in horizontal +// 1: Reversed read data from right to left in horizontal +// Bit 15 RW, dr_clr_fifo_error, 1 to clear the overflow flag of the sticky FIFO +// Bit 14 RW, dr_little_endian, 0: data is ordered in big-endian; 1: little-endian +// Bit 13:12 RW, dr_pic_struct, 0: progressive; 1: Reserved; +// 2: interlaced, even line; 3: interlaced, odd line +// Bit 11 RW, dr_urgent, urgent index, no use in this system +// Bit 10:9 RW, dr_burst_size, Burst read length for each request; 0=24,1=32,2=48,3=64 +// Bit 8 RW, dr_req_en, 1 to enable read request +// Bit 7:0 RW, dr_canvas_index, Canvas index for the MSB of memory address for memory read +#define D2D3_DRMIF_CTRL ((0x2b28 << 2) + 0xff000000) +// Bit 31 Reserved +// Bit 30:16 RW, dr_end_x, Horizontal end position for memory read, count by BYTE +// Bit 15 Reserved +// Bit 14:0 RW, dr_start_x, Horizontal start position for memory read, count by BYTE +#define D2D3_DRMIF_HPOS ((0x2b29 << 2) + 0xff000000) +// Bit 31:29 Reserved +// Bit 28:16 RW, dr_end_y, Vertical end position for memory read, count by BYTE +// Bit 15:13 Reserved +// Bit 12:0 RW, dr_start_y, Vertical start position for memory read, count by BYTE +#define D2D3_DRMIF_VPOS ((0x2b2a << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// PDR registers +// ddd: parallax based render +//------------------------------------------------------------------------------ +// Bit 31:8 Reserved +// Bit 7 RW, ddd_brdlpf_en, 1 to enable the smooth filter on the depth around the boundary +// Bit 6 RW, ddd_extn_black, 1 to enable the function to fill black colour when interpolated pixels is outside the picture in DBR +// Bit 5 RW, ddd_wrap_en, Reserved +// Bit 4 RW, ddd_hhalf, 1 to indicate the left/right line length is a half of original line. +// Bit 3:2 RW, ddd_out_mode, Reserved +// Bit 1:0 RW, ddd_lomode, wrap & pbr interleave mode: +// 2'b0x: whole line is left or right; +// 2'b10: d2p_lar=1(D2P_PARAM_1), rlrlrlrl inteleave in one line, +// d2p_lar=0(D2P_PARAM_1), lrlrlrlr inteleave in one line, +// 2'b11: d2p_lar=1(D2P_PARAM_1), rrrrrlllll, half line is right, another half is left, +// d2p_lar=0(D2P_PARAM_1), lllllrrrrr, half line is left, another half is right, +#define D2D3_DBR_DDD_CTRL ((0x2b2c << 2) + 0xff000000) +// Bit 31:0 RW, ddd_dbg_ctrl, no use +#define D2D3_DBR_DDD_DBG ((0x2b2d << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// LRDMX registers +//------------------------------------------------------------------------------ +// Bit 31:9 Reserved +// Bit 8 RW, lr_merge, 1: all the left/right input go to the left channel output +// Bit 7:6 RW, lrd_ff0_sel, FF0 source selector +// 0:from left input; 1:from right input; 2:from FF0; 3:no used +// Bit 5:4 RW, lrd_ff1_sel, FF1 source selector +// 0:from left input; 1:from right input; 2:from FF0; 3:no used +// Bit 3:2 RW, lrd_lout_sel, left channel DEMUX +// 00: ff0 01:ff1 10: left input 11:right input +// Bit 1:0 RW, lrd_rout_sel, right channel DEMUX +// 00: ff1 01:ff0 10: left input 11:right input +#define D2D3_DBR_LRDMX_CTRL ((0x2b2f << 2) + 0xff000000) +//------------------------------------------------------------------------------ +// Read Only registers +//------------------------------------------------------------------------------ +// Bit 31:24 RO, ro_cg_vprel, vanish point's reliability in CBDG +// Bit 23:12 RO, ro_cg_vpx, vanish point's X-Axis in CBDG +// Bit 11:0 RO, ro_cg_vpy, vanish point's Y-Axis in CBDG +#define D2D3_CBDG_STATUS_1 ((0x2b30 << 2) + 0xff000000) +// Bit 31:24 RO, ro_mg_cx[7:0], X-Axis of point C in horizontal curve in MBDG +// Bit 23:16 RO, ro_mg_ux, Depth value of point U in horizontal curve in MBDG +// Bit 15:8 RO, ro_mg_dx, Depth value of point D in horizontal curve in MBDG +// Bit 7:0 RO, ro_mg_minx, Depth value of point C in horizontal curve in MBDG +#define D2D3_MBDG_STATUS_1 ((0x2b31 << 2) + 0xff000000) +// Bit 31:24 RO, ro_mg_cy[7:0], X-Axis of point C in vertical curve in MBDG +// Bit 23:16 RO, ro_mg_uy, Depth value of point U in vertical curve in MBDG +// Bit 15:8 RO, ro_mg_dy, Depth value of point D in vertical curve in MBDG +// Bit 7:0 RO, ro_mg_miny, Depth value of point C in vertical curve in MBDG +#define D2D3_MBDG_STATUS_2 ((0x2b32 << 2) + 0xff000000) +// Bit 31 RO, ro_wrap_status, 1 indicate the D2P_WRAP is busy to perform the initialization +// Bit 30:8 Reserved +// Bit 7:4 RO, ro_mg_cy[11:8], X-Axis of point C in vertical curve in MBDG +// Bit 3:0 RO, ro_mg_cx[11:8], X-Axis of point C in horizontal curve in MBDG +#define D2D3_MBDG_STATUS_3 ((0x2b33 << 2) + 0xff000000) +// Bit 31:21 Reserved +// Bit 20:0 RO, ro_mg_sum_u, ACT(top): activities of the top part +#define D2D3_MBDG_STATUS_4 ((0x2b34 << 2) + 0xff000000) +// Bit 31:21 Reserved +// Bit 20:0 RO, ro_mg_sum_d, ACT(bottom): activities of the bottom part +#define D2D3_MBDG_STATUS_5 ((0x2b35 << 2) + 0xff000000) +// Bit 31:21 Reserved +// Bit 20:0 RO, ro_mg_sum_l, ACT(left): activities of the left part +#define D2D3_MBDG_STATUS_6 ((0x2b36 << 2) + 0xff000000) +// Bit 31:21 Reserved +// Bit 20:0 RO, ro_mg_sum_r, ACT(right): activities of the right part +#define D2D3_MBDG_STATUS_7 ((0x2b37 << 2) + 0xff000000) +// Bit 31:0 dbg_handshake_ro0, handshake signal for debug, internal srdy and rrdy +#define D2D3_DBG_STATUS_1 ((0x2b38 << 2) + 0xff000000) +// Bit 31:0 dbg_hscnt, dbg_hscnt_sel == 4'h0, output lg hscnt +// dbg_hscnt_sel == 4'h1, output cg hscnt +// dbg_hscnt_sel == 4'h2, output mg hscnt +// dbg_hscnt_sel == 4'h3, output bld hscnt +// dbg_hscnt_sel == other value, output 32'h0 +#define D2D3_DBG_STATUS_2 ((0x2b39 << 2) + 0xff000000) +// Bit 31:0 RO, drmif_status, drmif module internal status +#define D2D3_DRMIF_STATUS ((0x2b3a << 2) + 0xff000000) +// Bit 31:2 RO, Reserved +// Bit 1:0 RO, d2d3_status0, [1]: depw_done, one field depth write to ddr has done +// [0]: dwmif_pending_ddr_wrrsp, 1 to indicate write response from ddr +#define D2D3_DWMIF_STATUS ((0x2b3b << 2) + 0xff000000) +// Bit 31:24 Reserved +// Bit 23:0 RO, ro_meet_sum, register sumxy_sum_dbg in CBDG +#define D2D3_CBDG_STATUS_2 ((0x2b3c << 2) + 0xff000000) +// Bit 31:20 Reserved +// Bit 19:0 RO, ro_hist_depth, +#define D2D3_DBLD_STATUS ((0x2b3d << 2) + 0xff000000) +// Bit 31:0 Reserved +#define D2D3_RESEV_STATUS1 ((0x2b3e << 2) + 0xff000000) +// Bit 31:0 Reserved +#define D2D3_RESEV_STATUS2 ((0x2b3f << 2) + 0xff000000) +// +// Closing file: d2d3_regs.h +// +//======================================================================== +// MIPI DSI Host Controller (16'h2c00 - 16'h2cff) +// +//======================================================================== +//`include "dsi_regs.h" +//======================================================================== +// ISP register (16'h2d00 - 16'h2dff) +//======================================================================== +//`include "isp_reg.h" +// +// Reading file: vpu_dnr_regs.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: MADB_VCBUS_BASE = 0x2d +// ----------------------------------------------- +#define DNR_CTRL ((0x2d00 << 2) + 0xff000000) +//Bit 31:17, reserved +//Bit 16, reg_dnr_en , dnr enable . unsigned , default = 1 +//Bit 15, reg_dnr_db_vdbstep , vdb step, 0: 4, 1: 8 . unsigned , default = 1 +//Bit 14, reg_dnr_db_vdbprten , vdb protectoin enable . unsigned , default = 1 +//Bit 13, reg_dnr_gbs_difen , enable dif (between LR and LL/RR) condition for gbs stat.. unsigned , default = 0 +//Bit 12, reg_dnr_luma_en , enable ycbcr2luma module . unsigned , default = 1 +//Bit 11:10, reg_dnr_db_mod , deblocking mode, 0: disable, 1: horizontal deblocking, 2: vertical deblocking, 3: horizontal & vertical deblocking. unsigned , default = 3 +//Bit 9, reg_dnr_db_chrmen , enable chroma deblocking . unsigned , default = 1 +//Bit 8, reg_dnr_hvdif_mod , 0: calc. difs by original Y, 1: by new luma. unsigned , default = 1 +//Bit 7, reserved +//Bit 6: 4, reg_dnr_demo_lften , b0: Y b1:U b2:V . unsigned , default = 7 +//Bit 3, reserved +//Bit 2: 0, reg_dnr_demo_rgten , b0: Y b1:U b2:V . unsigned , default = 7 +#define DNR_HVSIZE ((0x2d01 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_dnr_hsize , hsize . unsigned , default = 0 +//Bit 15:13, reserved +//Bit 12: 0, reg_dnr_vsize , vsize . unsigned , default = 0 +#define DNR_DBLK_BLANK_NUM ((0x2d02 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_dblk_hblank_num , deblock hor blank num . unsigned , default = 16 +//Bit 7: 0, reg_dblk_vblank_num , deblock ver blank num . unsigned , default = 45 +#define DNR_BLK_OFFST ((0x2d03 << 2) + 0xff000000) +//Bit 31: 7, reserved +//Bit 6: 4, reg_dnr_hbofst , horizontal block offset may provide by software calc.. unsigned , default = 0 +//Bit 3, reserved +//Bit 2: 0, reg_dnr_vbofst , vertical block offset may provide by software calc.. unsigned , default = 0 +#define DNR_GBS ((0x2d04 << 2) + 0xff000000) +//Bit 31: 2, reserved +//Bit 1: 0, reg_dnr_gbs , global block strength may update by software calc.. unsigned , default = 0 +#define DNR_HBOFFST_STAT ((0x2d05 << 2) + 0xff000000) +//Bit 31:24, reg_dnr_hbof_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2 +//Bit 23:16, reg_dnr_hbof_edgethd , edge threshold (<=) for LR . unsigned , default = 32 +//Bit 15: 8, reg_dnr_hbof_flatthd , flat threshold (>=) for LR . unsigned , default = 0 +//Bit 7, reserved +//Bit 6: 4, reg_dnr_hbof_delta , delta for weighted bin accumulator. unsigned , default = 1 +//Bit 3, reserved +//Bit 2: 0, reg_dnr_hbof_statmod , statistic mode for horizontal block offset, 0: count flags for 8-bin, 1: count LRs for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count LRs for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2 +#define DNR_VBOFFST_STAT ((0x2d06 << 2) + 0xff000000) +//Bit 31:24, reg_dnr_vbof_difthd , dif threshold (>=) between Up and Dw. unsigned , default = 1 +//Bit 23:16, reg_dnr_vbof_edgethd , edge threshold (<=) for Up/Dw. unsigned , default = 16 +//Bit 15: 8, reg_dnr_vbof_flatthd , flat threshold (>=) for Up/Dw. unsigned , default = 0 +//Bit 7, reserved +//Bit 6: 4, reg_dnr_vbof_delta , delta for weighted bin accumulator. unsigned , default = 1 +//Bit 3, reserved +//Bit 2: 0, reg_dnr_vbof_statmod , statistic mode for vertical block offset, 0: count flags for 8-bin, 1: count Ups for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count Ups for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2 +#define DNR_GBS_STAT ((0x2d07 << 2) + 0xff000000) +//Bit 31:24, reg_dnr_gbs_edgethd , edge threshold (<=) for LR . unsigned , default = 32 +//Bit 23:16, reg_dnr_gbs_flatthd , flat threshold (>=) for LR . unsigned , default = 0 +//Bit 15: 8, reg_dnr_gbs_varthd , variation threshold (<=) for Lvar/Rvar. unsigned , default = 16 +//Bit 7: 0, reg_dnr_gbs_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2 +#define DNR_STAT_X_START_END ((0x2d08 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:16, reg_dnr_stat_xst . unsigned , default = 24 +//Bit 15:14, reserved +//Bit 13: 0, reg_dnr_stat_xed . unsigned , default = HSIZE - 25 +#define DNR_STAT_Y_START_END ((0x2d09 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:16, reg_dnr_stat_yst . unsigned , default = 24 +//Bit 15:14, reserved +//Bit 13: 0, reg_dnr_stat_yed . unsigned , default = VSIZE - 25 +#define DNR_LUMA ((0x2d0a << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:24, reg_dnr_luma_sqrtshft , left shift for fast squart of chroma, [0, 4]. unsigned , default = 2 +//Bit 23:21, reserved +//Bit 20:16, reg_dnr_luma_sqrtoffst , offset for fast squart of chroma. signed , default = 0 +//Bit 15, reserved +//Bit 14:12, reg_dnr_luma_wcmod , theta related to warm/cool segment line, 0: 0, 1: 45, 2: 90, 3: 135, 4: 180, 5: 225, 6: 270, 7: 315. . unsigned , default = 3 +//Bit 11: 8, reg_dnr_luma_cshft , shift for calc. delta part, 0~8, . unsigned , default = 8 +//Bit 7: 6, reserved +//Bit 5: 0, reg_dnr_luma_cgain , final gain for delta part, 32 normalized to "1". unsigned , default = 4 +#define DNR_DB_YEDGE_THD ((0x2d0b << 2) + 0xff000000) +//Bit 31:24, reg_dnr_db_yedgethd0 , edge threshold0 for luma . unsigned , default = 12 +//Bit 23:16, reg_dnr_db_yedgethd1 , edge threshold1 for luma . unsigned , default = 15 +//Bit 15: 8, reg_dnr_db_yedgethd2 , edge threshold2 for luma . unsigned , default = 18 +//Bit 7: 0, reg_dnr_db_yedgethd3 , edge threshold3 for luma . unsigned , default = 25 +#define DNR_DB_CEDGE_THD ((0x2d0c << 2) + 0xff000000) +//Bit 31:24, reg_dnr_db_cedgethd0 , edge threshold0 for chroma . unsigned , default = 12 +//Bit 23:16, reg_dnr_db_cedgethd1 , edge threshold1 for chroma . unsigned , default = 15 +//Bit 15: 8, reg_dnr_db_cedgethd2 , edge threshold2 for chroma . unsigned , default = 18 +//Bit 7: 0, reg_dnr_db_cedgethd3 , edge threshold3 for chroma . unsigned , default = 25 +#define DNR_DB_HGAP ((0x2d0d << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_dnr_db_hgapthd , horizontal gap thd (<=) for very sure blockiness . unsigned , default = 8 +//Bit 15: 8, reg_dnr_db_hgapdifthd , dif thd between hgap and lft/rgt hdifs. unsigned , default = 1 +//Bit 7: 1, reserved +//Bit 0, reg_dnr_db_hgapmod , horizontal gap calc. mode, 0: just use current col x, 1: find max between (x-1, x, x+1) . unsigned , default = 0 +#define DNR_DB_HBS ((0x2d0e << 2) + 0xff000000) +//Bit 31: 6, reserved +//Bit 5: 4, reg_dnr_db_hbsup , horizontal bs up value . unsigned , default = 1 +//Bit 3: 2, reg_dnr_db_hbsmax , max value of hbs for global control. unsigned , default = 3 +//Bit 1: 0, reg_dnr_db_hgbsthd , gbs thd (>=) for hbs calc. . unsigned , default = 1 +#define DNR_DB_HACT ((0x2d0f << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_dnr_db_hactthd0 , thd0 of hact, for block classification. unsigned , default = 10 +//Bit 7: 0, reg_dnr_db_hactthd1 , thd1 of hact, for block classification. unsigned , default = 32 +#define DNR_DB_YHDELTA_GAIN ((0x2d10 << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:24, reg_dnr_db_yhdeltagain1 , (p1-q1) gain for Y's delta calc. when bs=1, normalized 8 as "1" . unsigned , default = 2 +//Bit 23, reserved +//Bit 22:20, reg_dnr_db_yhdeltagain2 , (p1-q1) gain for Y's delta calc. when bs=2, normalized 8 as "1" . unsigned , default = 0 +//Bit 19, reserved +//Bit 18:16, reg_dnr_db_yhdeltagain3 , (p1-q1) gain for Y's delta calc. when bs=3, normalized 8 as "1" . unsigned , default = 0 +//Bit 15, reserved +//Bit 14: 8, reg_dnr_db_yhdeltaadjoffst , offset for adjust Y's hdelta (-64, 63). signed , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_dnr_db_yhdeltaadjgain , gain for adjust Y's hdelta, normalized 32 as "1" . unsigned , default = 32 +#define DNR_DB_YHDELTA2_GAIN ((0x2d11 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_dnr_db_yhdelta2gain2 , gain for bs=2's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 8 +//Bit 23:21, reserved +//Bit 20:16, reg_dnr_db_yhdelta2offst2 , offset for bs=2's adjust Y's hdelta2 (-16, 15). signed , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_dnr_db_yhdelta2gain3 , gain for bs=3's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 4 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_db_yhdelta2offst3 , offset for bs=3's adjust Y's hdelta2 (-16, 15). signed , default = 0 +#define DNR_DB_CHDELTA_GAIN ((0x2d12 << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:24, reg_dnr_db_chdeltagain1 , (p1-q1) gain for UV's delta calc. when bs=1, normalized 8 as "1". unsigned , default = 2 +//Bit 23, reserved +//Bit 22:20, reg_dnr_db_chdeltagain2 , (p1-q1) gain for UV's delta calc. when bs=2, normalized 8 as "1". unsigned , default = 0 +//Bit 19, reserved +//Bit 18:16, reg_dnr_db_chdeltagain3 , (p1-q1) gain for UV's delta calc. when bs=3, normalized 8 as "1". unsigned , default = 0 +//Bit 15, reserved +//Bit 14: 8, reg_dnr_db_chdeltaadjoffst , offset for adjust UV's hdelta (-64, 63). signed , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_dnr_db_chdeltaadjgain , gain for adjust UV's hdelta, normalized 32 as "1". unsigned , default = 32 +#define DNR_DB_CHDELTA2_GAIN ((0x2d13 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_dnr_db_chdelta2gain2 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 8 +//Bit 23:21, reserved +//Bit 20:16, reg_dnr_db_chdelta2offst2 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_dnr_db_chdelta2gain3 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 4 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_db_chdelta2offst3 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0 +#define DNR_DB_YC_VEDGE_THD ((0x2d14 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_dnr_db_yvedgethd , special Y's edge thd for vdb. unsigned , default = 12 +//Bit 7: 0, reg_dnr_db_cvedgethd , special UV's edge thd for vdb. unsigned , default = 12 +#define DNR_DB_VBS_MISC ((0x2d15 << 2) + 0xff000000) +//Bit 31:24, reg_dnr_db_vgapthd , vertical gap thd (<=) for very sure blockiness . unsigned , default = 8 +//Bit 23:16, reg_dnr_db_vactthd , thd of vact, for block classification . unsigned , default = 10 +//Bit 15: 8, reg_dnr_db_vgapdifthd , dif thd between vgap and vact. unsigned , default = 4 +//Bit 7: 4, reserved +//Bit 3: 2, reg_dnr_db_vbsmax , max value of vbs for global control. unsigned , default = 2 +//Bit 1: 0, reg_dnr_db_vgbsthd , gbs thd (>=) for vbs calc. . unsigned , default = 1 +#define DNR_DB_YVDELTA_GAIN ((0x2d16 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_dnr_db_yvdeltaadjgain , gain for adjust Y's vdelta, normalized 32 as "1". unsigned , default = 32 +//Bit 23, reserved +//Bit 22:16, reg_dnr_db_yvdeltaadjoffst , offset for adjust Y's vdelta (-64, 63). signed , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_dnr_db_yvdelta2gain , gain for adjust Y's vdelta2, normalized 64 as "1". unsigned , default = 8 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_db_yvdelta2offst , offset for adjust Y's vdelta2 (-16, 15). signed , default = 0 +#define DNR_DB_CVDELTA_GAIN ((0x2d17 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_dnr_db_cvdeltaadjgain , gain for adjust UV's vdelta, normalized 32 as "1". unsigned , default = 32 +//Bit 23, reserved +//Bit 22:16, reg_dnr_db_cvdeltaadjoffst , offset for adjust UV's vdelta (-64, 63). signed , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_dnr_db_cvdelta2gain , gain for adjust UV's vdelta2, normalized 64 as "1". unsigned , default = 8 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_db_cvdelta2offst , offset for adjust UV's vdelta2 (-16, 15). signed , default = 0 +#define DNR_RO_GBS_STAT_LR ((0x2d18 << 2) + 0xff000000) +//Bit 31: 0, ro_gbs_stat_lr . unsigned , default = 0 +#define DNR_RO_GBS_STAT_LL ((0x2d19 << 2) + 0xff000000) +//Bit 31: 0, ro_gbs_stat_ll . unsigned , default = 0 +#define DNR_RO_GBS_STAT_RR ((0x2d1a << 2) + 0xff000000) +//Bit 31: 0, ro_gbs_stat_rr . unsigned , default = 0 +#define DNR_RO_GBS_STAT_DIF ((0x2d1b << 2) + 0xff000000) +//Bit 31: 0, ro_gbs_stat_dif . unsigned , default = 0 +#define DNR_RO_GBS_STAT_CNT ((0x2d1c << 2) + 0xff000000) +//Bit 31: 0, ro_gbs_stat_cnt . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_0 ((0x2d1d << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt0 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_1 ((0x2d1e << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt1 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_2 ((0x2d1f << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt2 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_3 ((0x2d20 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt3 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_4 ((0x2d21 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt4 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_5 ((0x2d22 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt5 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_6 ((0x2d23 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt6 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_7 ((0x2d24 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt7 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_8 ((0x2d25 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt8 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_9 ((0x2d26 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt9 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_10 ((0x2d27 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt10 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_11 ((0x2d28 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt11 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_12 ((0x2d29 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt12 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_13 ((0x2d2a << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt13 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_14 ((0x2d2b << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt14 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_15 ((0x2d2c << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt15 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_16 ((0x2d2d << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt16 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_17 ((0x2d2e << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt17 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_18 ((0x2d2f << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt18 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_19 ((0x2d30 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt19 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_20 ((0x2d31 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt20 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_21 ((0x2d32 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt21 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_22 ((0x2d33 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt22 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_23 ((0x2d34 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt23 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_24 ((0x2d35 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt24 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_25 ((0x2d36 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt25 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_26 ((0x2d37 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt26 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_27 ((0x2d38 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt27 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_28 ((0x2d39 << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt28 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_29 ((0x2d3a << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt29 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_30 ((0x2d3b << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt30 . unsigned , default = 0 +#define DNR_RO_HBOF_STAT_CNT_31 ((0x2d3c << 2) + 0xff000000) +//Bit 31: 0, ro_hbof_stat_cnt31 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_0 ((0x2d3d << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt0 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_1 ((0x2d3e << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt1 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_2 ((0x2d3f << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt2 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_3 ((0x2d40 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt3 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_4 ((0x2d41 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt4 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_5 ((0x2d42 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt5 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_6 ((0x2d43 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt6 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_7 ((0x2d44 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt7 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_8 ((0x2d45 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt8 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_9 ((0x2d46 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt9 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_10 ((0x2d47 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt10 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_11 ((0x2d48 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt11 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_12 ((0x2d49 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt12 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_13 ((0x2d4a << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt13 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_14 ((0x2d4b << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt14 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_15 ((0x2d4c << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt15 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_16 ((0x2d4d << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt16 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_17 ((0x2d4e << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt17 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_18 ((0x2d4f << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt18 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_19 ((0x2d50 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt19 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_20 ((0x2d51 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt20 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_21 ((0x2d52 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt21 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_22 ((0x2d53 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt22 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_23 ((0x2d54 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt23 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_24 ((0x2d55 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt24 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_25 ((0x2d56 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt25 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_26 ((0x2d57 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt26 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_27 ((0x2d58 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt27 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_28 ((0x2d59 << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt28 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_29 ((0x2d5a << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt29 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_30 ((0x2d5b << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt30 . unsigned , default = 0 +#define DNR_RO_VBOF_STAT_CNT_31 ((0x2d5c << 2) + 0xff000000) +//Bit 31: 0, ro_vbof_stat_cnt31 . unsigned , default = 0 +#define DNR_DM_ADP_EN ((0x2d5d << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7 reg_dnr_scene_change_flg // unsigned , default = 1 , scence change flag for dnr(dm); +//Bit 6 reg_dnr_dm_lpf_en // unsigned , default = 1 , enable lpf for demosquito filter +//Bit 5 reg_dnr_dm_adp_level_en // unsigned , default = 1 , enable adptive demosquito level +//Bit 4 reg_dnr_dm_flg2bdif_en // unsigned , default = 1 , enable edge flg to blkdif calc. +//Bit 3: 2 reg_dnr_dm_edgeiir // unsigned , default = 1 , edge flag iir mode, 0: cur, 1: max(pre, cur), 2: choice 0/1 by org mtn, 3: choice 0/1 by ref mtn +//Bit 1 reg_dnr_dm_dirdifmod // unsigned , default = 1 , dif mode for direction calc, 0: abs(dif02), 1: (abs(dif01)+abs(dif21))/2 +//Bit 0 reg_dnr_dm_sur_dir_mod // unsigned , default = 0 , sure direction mode for cordif calc. +#define DNR_DM_EDGE_DIR ((0x2d5e << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_dnr_dm_dirdifcor // unsigned , default = 2 , dif coring threshold for direction calc +//Bit 15: 8 reg_dnr_dm_edgecordifthd // unsigned , default = 160 , edge flg down when cordif is large than threshold +//Bit 7: 0 reg_dnr_dm_mtnrt // unsigned , default = 60 , motion ratio for mtn decision +#define DNR_DM_CTRL ((0x2d60 << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12, reg_dnr_dm_fedgeflg_en , enable edge flag calc. of each frame. unsigned , default = 1 +//Bit 11, reg_dnr_dm_fedgeflg_cl , clear frame edge flag if needed. unsigned , default = 1 +//Bit 10, reg_dnr_dm_fedgeflg_df , user defined edge when reg_dnr_dm_fedgeflg_en=0, default = 1 +//Bit 9, reg_dnr_dm_en , enable demosquito function . unsigned , default = 1 +//Bit 8, reg_dnr_dm_chrmen , enable chrome processing for demosquito. unsigned , default = 1 +//Bit 7: 6, reg_dnr_dm_level , demosquito level . unsigned , default = 3 +//Bit 5: 4, reg_dnr_dm_leveldw0 , level down when gbs is small. unsigned , default = 1 +//Bit 3: 2, reg_dnr_dm_leveldw1 , level down for no edge/flat blocks. unsigned , default = 1 +//Bit 1: 0, reg_dnr_dm_gbsthd , small/large threshold for gbs (<=). unsigned , default = 0 +#define DNR_DM_NR_BLND ((0x2d61 << 2) + 0xff000000) +//Bit 31:25, reserved +//Bit 24, reg_dnr_dm_defalpen , enable user define alpha for dm & nr blend. unsigned , default = 0 +//Bit 23:16, reg_dnr_dm_defalp , user define alpha for dm & nr blend if enable. unsigned , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_dnr_dm_alpgain , gain for nr/dm alpha, normalized 32 as "1". unsigned , default = 32 +//Bit 7: 0, reg_dnr_dm_alpoffst , (-128, 127), offset for nr/dm alpha. signed , default = 0 +#define DNR_DM_RNG_THD ((0x2d62 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_dnr_dm_rngminthd . unsigned , default = 2 +//Bit 15: 8, reg_dnr_dm_rngmaxthd . unsigned , default = 64 +//Bit 7: 0, reg_dnr_dm_rngdifthd . unsigned , default = 4 +#define DNR_DM_RNG_GAIN_OFST ((0x2d63 << 2) + 0xff000000) +//Bit 31:14, reserved +//Bit 13: 8, reg_dnr_dm_rnggain , normalized 16 as "1" . unsigned , default = 16 +//Bit 7: 6, reserved +//Bit 5: 0, reg_dnr_dm_rngofst . unsigned , default = 0 +#define DNR_DM_DIR_MISC ((0x2d64 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29, reg_dnr_dm_diralpen . unsigned , default = 1 +//Bit 28:24, reg_dnr_dm_diralpgain . unsigned , default = 0 +//Bit 23:22, reserved +//Bit 21:16, reg_dnr_dm_diralpofst . unsigned , default = 0 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_diralpmin . unsigned , default = 0 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_diralpmax . unsigned , default = 31 +#define DNR_DM_COR_DIF ((0x2d65 << 2) + 0xff000000) +//Bit 31: 4, reserved +//Bit 3: 1, reg_dnr_dm_cordifshft . unsigned , default = 3 +//Bit 0, reg_dnr_dm_cordifmod , 0:use max dir dif as cordif, 1: use max3x3 - min3x3 as cordif. unsigned , default = 1 +#define DNR_DM_FLT_THD ((0x2d66 << 2) + 0xff000000) +//Bit 31:24, reg_dnr_dm_fltthd00 , block flat threshold0 for block average difference when gbs is small, for flat block detection. unsigned , default = 4 +//Bit 23:16, reg_dnr_dm_fltthd01 , block flat threshold1 for block average difference when gbs is small, for flat block detection. unsigned , default = 6 +//Bit 15: 8, reg_dnr_dm_fltthd10 , block flat threshold0 for block average difference when gbs is large, for flat block detection. unsigned , default = 9 +//Bit 7: 0, reg_dnr_dm_fltthd11 , block flat threshold1 for block average difference when gbs is large, for flat block detection. unsigned , default = 12 +#define DNR_DM_VAR_THD ((0x2d67 << 2) + 0xff000000) +//Bit 31:24, reg_dnr_dm_varthd00 , block variance threshold0 (>=) when gbs is small, for flat block detection. unsigned , default = 2 +//Bit 23:16, reg_dnr_dm_varthd01 , block variance threshold1 (<=) when gbs is small, for flat block detection. unsigned , default = 15 +//Bit 15: 8, reg_dnr_dm_varthd10 , block variance threshold0 (>=) when gbs is large, for flat block detection. unsigned , default = 3 +//Bit 7: 0, reg_dnr_dm_varthd11 , block variance threshold1 (<=) when gbs is large, for flat block detection. unsigned , default = 24 +#define DNR_DM_EDGE_DIF_THD ((0x2d68 << 2) + 0xff000000) +//Bit 31:24, reg_dnr_dm_edgethd0 , block edge threshold (<=) when gbs is small, for flat block detection. unsigned , default = 32 +//Bit 23:16, reg_dnr_dm_edgethd1 , block edge threshold (<=) when gbs is large, for flat block detection. unsigned , default = 48 +//Bit 15: 8, reg_dnr_dm_difthd0 , block dif threshold (<=) when gbs is small, for flat block detection. unsigned , default = 48 +//Bit 7: 0, reg_dnr_dm_difthd1 , block dif threshold (<=) when gbs is large, for flat block detection. unsigned , default = 64 +#define DNR_DM_AVG_THD ((0x2d69 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_dnr_dm_avgthd0 , block average threshold (>=), for flat block detection. unsigned , default = 160 +//Bit 7: 0, reg_dnr_dm_avgthd1 , block average threshold (<=), for flat block detection. unsigned , default = 128 +#define DNR_DM_AVG_VAR_DIF_THD ((0x2d6a << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_dnr_dm_avgdifthd , block average dif threshold (<) between cur and up block, for flat block detection. unsigned , default = 12 +//Bit 7: 0, reg_dnr_dm_vardifthd , block variance dif threshold (>=) between cur and up block, for flat block detection. unsigned , default = 1 +#define DNR_DM_VAR_EDGE_DIF_THD2 ((0x2d6b << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_dnr_dm_varthd2 , block variance threshold (>=), for edge block detection. unsigned , default = 24 +//Bit 15: 8, reg_dnr_dm_edgethd2 , block edge threshold (>=), for edge block detection. unsigned , default = 40 +//Bit 7: 0, reg_dnr_dm_difthd2 , block dif threshold (>=), for edge block detection. unsigned , default = 80 +#define DNR_DM_DIF_FLT_MISC ((0x2d6c << 2) + 0xff000000) +//Bit 31:28, reg_dnr_dm_ldifoob , pre-defined large dif when pixel out of blocks. unsigned , default = 0 +//Bit 27:24, reg_dnr_dm_bdifoob , pre-defined block dif when pixel out of blocks;. unsigned , default = 0 +//Bit 23:16, reg_dnr_dm_fltalp , pre-defined alpha for dm and nr blending, when block is flat with mos.. unsigned , default = 200 +//Bit 15:12, reserved +//Bit 11: 8, reg_dnr_dm_fltminbdif , pre-defined min block dif for dm filter, when block is flat with mos.. unsigned , default = 12 +//Bit 7, reserved +//Bit 6: 2, reg_dnr_dm_difnormgain , gain for pixel dif normalization for dm filter, normalized 16 as "1". unsigned , default = 16 +//Bit 1, reg_dnr_dm_difnormen , enable pixel dif normalization for dm filter. unsigned , default = 1 +//Bit 0, reg_dnr_dm_difupden , enable block dif update using max of left, cur, right difs. unsigned , default = 0 +#define DNR_DM_SDIF_LUT0_2 ((0x2d6d << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_sdiflut0 , normally 0-16 . unsigned , default = 16 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_sdiflut1 , normally 0-16 . unsigned , default = 14 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_sdiflut2 , normally 0-16 . unsigned , default = 13 +#define DNR_DM_SDIF_LUT3_5 ((0x2d6e << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_sdiflut3 , normally 0-16 . unsigned , default = 10 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_sdiflut4 , normally 0-16 . unsigned , default = 7 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_sdiflut5 , normally 0-16 . unsigned , default = 5 +#define DNR_DM_SDIF_LUT6_8 ((0x2d6f << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_sdiflut6 , normally 0-16 . unsigned , default = 3 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_sdiflut7 , normally 0-16 . unsigned , default = 1 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_sdiflut8 , normally 0-16 . unsigned , default = 0 +#define DNR_DM_LDIF_LUT0_2 ((0x2d70 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_ldiflut0 , normally 0-16 . unsigned , default = 0 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_ldiflut1 , normally 0-16 . unsigned , default = 4 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_ldiflut2 , normally 0-16 . unsigned , default = 12 +#define DNR_DM_LDIF_LUT3_5 ((0x2d71 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_ldiflut3 , normally 0-16 . unsigned , default = 14 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_ldiflut4 , normally 0-16 . unsigned , default = 15 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_ldiflut5 , normally 0-16 . unsigned , default = 16 +#define DNR_DM_LDIF_LUT6_8 ((0x2d72 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_ldiflut6 , normally 0-16 . unsigned , default = 16 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_ldiflut7 , normally 0-16 . unsigned , default = 16 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_ldiflut8 , normally 0-16 . unsigned , default = 16 +#define DNR_DM_DIF2NORM_LUT0_2 ((0x2d73 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_dif2normlut0 , normally 0-16 . unsigned , default = 16 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_dif2normlut1 , normally 0-16 . unsigned , default = 5 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_dif2normlut2 , normally 0-16 . unsigned , default = 3 +#define DNR_DM_DIF2NORM_LUT3_5 ((0x2d74 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_dif2normlut3 , normally 0-16 . unsigned , default = 2 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_dif2normlut4 , normally 0-16 . unsigned , default = 2 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_dif2normlut5 , normally 0-16 . unsigned , default = 1 +#define DNR_DM_DIF2NORM_LUT6_8 ((0x2d75 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_dnr_dm_dif2normlut6 , normally 0-16 . unsigned , default = 1 +//Bit 15:13, reserved +//Bit 12: 8, reg_dnr_dm_dif2normlut7 , normally 0-16 . unsigned , default = 1 +//Bit 7: 5, reserved +//Bit 4: 0, reg_dnr_dm_dif2normlut8 , normally 0-16 . unsigned , default = 1 +#define DNR_DM_GMS_THD ((0x2d76 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_gms_stat_thd0 . unsigned , default = 0 +//Bit 7: 0, reg_gms_stat_thd1 . unsigned , default = 128 +#define DNR_RO_DM_GMS_STAT_CNT ((0x2d77 << 2) + 0xff000000) +//Bit 31: 0, ro_dm_gms_stat_cnt . unsigned , default = 0 +#define DNR_RO_DM_GMS_STAT_MS ((0x2d78 << 2) + 0xff000000) +//Bit 31: 0, ro_dm_gms_stat_ms . unsigned , default = 0 +#define DNR_DM_EDGE_GAIN ((0x2d79 << 2) + 0xff000000) +//Bit 31:24 reg_dnr_dm_alpedgegain0 // unsigned , default = 8 , edge based gain for alpha, normalized 16 as "1" +//Bit 23:16 reg_dnr_dm_alpedgegain1 // unsigned , default = 16 , edge based gain for alpha, normalized 16 as "1" +//Bit 15: 8 reg_dnr_dm_alpedgegain2 // unsigned , default = 24 , edge based gain for alpha, normalized 16 as "1" +//Bit 7: 0 reg_dnr_dm_alpedgegain3 // unsigned , default = 32 , edge based gain for alpha, normalized 16 as "1" +#define DNR_DM_FLG_BDIF ((0x2d7a << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:24 reg_dnr_dm_flg2bdif0 // unsigned , default = 0 , (0-16), edge flg to blkdif calc. +//Bit 23:21 reserved +//Bit 20:16 reg_dnr_dm_flg2bdif1 // unsigned , default = 6 , (0-16), edge flg to blkdif calc. +//Bit 15:13 reserved +//Bit 12: 8 reg_dnr_dm_flg2bdif2 // unsigned , default = 10 , (0-16), edge flg to blkdif calc. +//Bit 7: 5 reserved +//Bit 4: 0 reg_dnr_dm_flg2bdif3 // unsigned , default = 12 , (0-16), edge flg to blkdif calc. +#define DNR_DM_GBS_RORM ((0x2d7b << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15:12 reg_dnr_dm_gbs4difnorm0 // unsigned , default = 0 , gbs=0 for dif norm calc. +//Bit 11: 8 reg_dnr_dm_gbs4difnorm1 // unsigned , default = 1 , gbs=1 for dif norm calc. +//Bit 7: 4 reg_dnr_dm_gbs4difnorm2 // unsigned , default = 4 , gbs=2 for dif norm calc. +//Bit 3: 0 reg_dnr_dm_gbs4difnorm3 // unsigned , default = 6 , gbs=3 for dif norm calc. +#define DNR_DM_FLG_LEV ((0x2d7c << 2) + 0xff000000) +//Bit 31:14 reserved +//Bit 13:12 reg_dnr_dm_flg2lev0 // unsigned , default = 1 , edge flg to filter level calc. +//Bit 11:10 reserved +//Bit 9: 8 reg_dnr_dm_flg2lev1 // unsigned , default = 3 , edge flg to filter level calc. +//Bit 7: 6 reserved +//Bit 5: 4 reg_dnr_dm_flg2lev2 // unsigned , default = 3 , edge flg to filter level calc. +//Bit 3: 2 reserved +//Bit 1: 0 reg_dnr_dm_flg2lev3 // unsigned , default = 3 , edge flg to filter level calc. +#define DNR_DM_DIF_FLG_TH ((0x2d7d << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_dnr_dm_dif2flgthd1 // unsigned , default = 128 , dif to edge flg threshold 1 +//Bit 7: 0 reg_dnr_dm_dif2flgthd2 // unsigned , default = 192 , dif to edge flg threshold 2 +#define DNR_DM_CALP_GAIN_OFST ((0x2d7e << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:16 reg_dnr_dm_calpgain // unsigned , default = 16 , chroma gain for nr/dm alpha, normalized 32 as "1" +//Bit 15: 9 reserved +//Bit 8: 0 reg_dnr_dm_calpoffst // signed , default = -64 , (-255, 255), chroma offset for nr/dm alpha +// 0x80-0x90 +// +// Reading file: vpu_decomb_regs.h +// + // defined registers +#define DECOMB_DET_VERT_CON0 ((0x2d80 << 2) + 0xff000000) +//Bit 31:24 reg_di_dcmb_det_vcon_thd0 default = 60 // u8 +//Bit 23:16 reg_di_dcmb_det_vcon_thd1 default = 80 // u8 +//Bit 15: 8 reg_di_dcmb_det_valp_lmt0 default = 63 // u8 +//Bit 7: 0 reg_di_dcmb_det_valp_lmt1 default = 4 // u8 +#define DECOMB_DET_VERT_CON1 ((0x2d81 << 2) + 0xff000000) +//Bit 23:16 reg_di_dcmb_det_valp_lmt2 default = 0 // u8 +//Bit 15: 8 reg_di_dcmb_det_vrate0 default = 32 // u8 +//Bit 7: 0 reg_di_dcmb_det_vrate1 default = 4 // u8 +#define DECOMB_DET_EDGE_CON0 ((0x2d82 << 2) + 0xff000000) +//Bit 31:24 reg_di_dcmb_det_econ_thd0 default = 60 // u8 +//Bit 23:16 reg_di_dcmb_det_econ_thd1 default = 80 // u8 +//Bit 15: 8 reg_di_dcmb_det_ealp_lmt0 default = 63 // u8 +//Bit 7: 0 reg_di_dcmb_det_ealp_lmt1 default = 4 // u8 +#define DECOMB_DET_EDGE_CON1 ((0x2d83 << 2) + 0xff000000) +//Bit 23:16 reg_di_dcmb_det_ealp_lmt2 default = 0 // u8 +//Bit 15: 8 reg_di_dcmb_det_erate0 default = 32 // u8 +//Bit 7: 0 reg_di_dcmb_det_erate1 default = 4 // u8 +#define DECOMB_PARA ((0x2d84 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:28 reg_di_dcmb_cmb_lpf default = 1 // u2, 0:no lpf, 1:[1 2 1], 2,3: [1 2 2 2 1] +//Bit 27:26 reg_di_dcmb_vedge_chk default = 0 // u2, vertical edge check, 0: no check, 1: vrt!=0, 2: vrt==3 +//Bit 25:24 reg_di_dcmb_nedge_chk default = 0 // u2, no idea edge check, 0, no check, 1, check +//Bit 23:20 reg_di_dcmb_edge_min default = 0 // u4, min edge for edge cmb +//Bit 19:16 reg_di_dcmb_edge_max default = 15 // u4, min edge for edge cmb +//Bit 15:8 reg_di_dcmb_bld_alp default = 255 // u8, user defined alpha for di & decmb blend +//Bit 7:0 reg_di_dcmb_bld_alp_beta default = 40 // u8, beta for mtn & cmb blend, for bld alpha calc. +#define DECOMB_BLND_CON0 ((0x2d85 << 2) + 0xff000000) +//Bit 31:24 reg_di_dcmb_bld_con_thd0 default = 100 // u8 +//Bit 23:16 reg_di_dcmb_bld_con_thd1 default = 120 // u8 +//Bit 15: 8 reg_di_dcmb_bld_alp_lmt0 default = 0 // u8 +//Bit 7: 0 reg_di_dcmb_bld_alp_lmt1 default = 128 // u8 +#define DECOMB_BLND_CON1 ((0x2d86 << 2) + 0xff000000) +//Bit 23:16 reg_di_dcmb_bld_alp_lmt2 default = 255 // u8 +//Bit 15: 8 reg_di_dcmb_bld_rate0 default = 32 // u8 +//Bit 7: 0 reg_di_dcmb_bld_rate1 default = 32 // u8 +#define DECOMB_YC_THRD ((0x2d87 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_di_dcmb_ythd default = 2 // u8, default = 2 +//Bit 7: 0 reg_di_dcmb_cthd default = 2 // u8, default = 2 +#define DECOMB_MTN_GAIN_OFST ((0x2d88 << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:16 reg_di_dcmb_mtn_alp_gain default = 16 // u6, 16 is normalized to '1' +//Bit 15:9 reserved +//Bit 8:0 reg_di_dcmb_mtn_alp_ofst default = 0 // s9, [-256, 255] +#define DECOMB_CMB_SEL_GAIN_OFST ((0x2d89 << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:16 reg_di_dcmb_cmb_sel_gain default = 48 // u6, 16 is normalized to '1' +//Bit 15:9 reserved +//Bit 8:0 reg_di_dcmb_cmb_sel_ofst default = 0 // s9, [-256, 255] +#define DECOMB_WIND00 ((0x2d8a << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_di_dcmb_wnd00 default = 0 // u13, x0 for window 0, software control +//Bit 15:13 reserved +//Bit 12:0 reg_di_dcmb_wnd01 default = 719 // u13, x1 for window 0, HSIZE-1, software control +#define DECOMB_WIND01 ((0x2d8b << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_di_dcmb_wnd02 default = 0 // u13, y0 for window 0, software control +//Bit 15:13 reserved +//Bit 12:0 reg_di_dcmb_wnd03 default = 39 // u13, y1 for window 0, software control +#define DECOMB_WIND10 ((0x2d8c << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_di_dcmb_wnd10 default = 0 // u13, x0 for window 1, software control +//Bit 15:13 reserved +//Bit 12:0 reg_di_dcmb_wnd11 default = 719 // u13, x1 for window 1, HSIZE-1, software control +#define DECOMB_WIND11 ((0x2d8d << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_di_dcmb_wnd12 default = 40 // u13, y0 for window 1, software control +//Bit 15:13 reserved +//Bit 12:0 reg_di_dcmb_wnd13 default = 239 // u13, y1 for window 1, VSIZE-1-40, software control +#define DECOMB_MODE ((0x2d8e << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reg_di_dcmb_is_cmb_bef default = 1 // u1, 1: decide is_cmb before cmbing refine, 0: decide is_cmb after cmbing refine +//Bit 14 reg_di_dcmb_en0 default = 1 // u1, enable decmobing for wind0 +//Bit 13 reg_di_dcmb_en1 default = 1 // u1, enable decmobing for wind1 +//Bit 12 reg_di_dcmb_en2 default = 1 // u1, enable decmobing for wind2 +//Bit 11:10 reg_di_dcmb_lpf_mod0 default = 2 // u2, get combing free pixels of wind0 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data +//Bit 9:8 reg_di_dcmb_lpf_mod1 default = 2 // u2, get combing free pixels of wind1 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data +//Bit 7:6 reg_di_dcmb_lpf_mod2 default = 0 // u2, get combing free pixels of wind2 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data +//Bit 5 reg_di_dcmb_cmb_sel0 default = 1 // u1, wind0 decmb based on: 0, vert cmb, 1, edge cmb +//Bit 4 reg_di_dcmb_cmb_sel1 default = 1 // u1, wind1 decmb based on: 0, vert cmb, 1, edge cmb +//Bit 3 reg_di_dcmb_cmb_sel2 default = 0 // u1, wind2 decmb based on: 0, vert cmb, 1, edge cmb +//Bit 2 reg_di_dcmb_alp_mod0 default = 1 // u1, wind0 decmb alpha based on: 0, user-defined, 1, motion adaptive +//Bit 1 reg_di_dcmb_alp_mod1 default = 1 // u1, wind1 decmb alpha based on: 0, user-defined, 1, motion adaptive +//Bit 0 reg_di_dcmb_alp_mod2 default = 1 // u1, wind2 decmb alpha based on: 0, user-defined, 1, motion adaptive +#define DECOMB_FRM_SIZE ((0x2d8f << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 hsize_in default = 1920 // u13, pic horz size in unit: pixel +//Bit 15:13 reserved +//Bit 12:0 vsize_in default = 1080 // u13, pic vert size in unit: pixel +#define DECOMB_HV_BLANK ((0x2d90 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15:8 hblank_num default = 20 // u8, hor blank time +//Bit 7:0 vblank_num default = 50 // u8, ver blank time +// +// Closing file: vpu_decomb_regs.h +// +// 0x98-0xa3 +// +// Reading file: vpu_nr2_dpolar_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define NR2_POLAR3_MODE ((0x2d98 << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19:18 reg_polar3_f02lpf_mod0 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf +//Bit 17:16 reg_polar3_f02lpf_mod1 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf +//Bit 15: 8 reg_polar3_dif02_thrd0 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma +//Bit 7: 0 reg_polar3_dif02_thrd1 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma +#define NR2_POLAR3_THRD ((0x2d99 << 2) + 0xff000000) +//Bit 31:24 reg_polar3_txtf02_thrd0 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision. +//Bit 23:16 reg_polar3_txtf02_thrd1 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision. +//Bit 15: 8 reg_polar3_txtf1_thrd0 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision. +//Bit 7: 0 reg_polar3_txtf1_thrd1 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision. +#define NR2_POLAR3_PARA0 ((0x2d9a << 2) + 0xff000000) +//Bit 31:28 reg_polar3_rate00 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2<f0, if f1 within((f0+f2)/2 - delt), ((f0+f2)/2 + delt), then polar3_smoothmv++; +//Bit 27:24 reg_polar3_rate01 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2<f0, if f1 within((f0+f2)/2 - delt), ((f0+f2)/2 + delt), then polar3_smoothmv++; +//Bit 23:20 reg_polar3_rate10 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1<f0, if f1<((f0+f2)/2 - delt), then polar3_m1++; if f1>((f0+f2)/2 + delt), then polar3_p1++; +//Bit 19:16 reg_polar3_rate11 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1<f0, if f1<((f0+f2)/2 - delt), then polar3_m1++; if f1>((f0+f2)/2 + delt), then polar3_p1++; +//Bit 15:12 reg_polar3_rate20 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++; +//Bit 11: 8 reg_polar3_rate21 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++; +//Bit 7: 1 reserved +//Bit 0 reg_polar3_ro_reset // unsigned , default = 0 reset signal of the polar3 read only registers +#define NR2_POLAR3_PARA1 ((0x2d9b << 2) + 0xff000000) +//Bit 31:24 reg_polar3_rate30 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset3) or f1>((f0 + delt+ofst3), then polar3_32++; +//Bit 23:16 reg_polar3_rate31 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset3) or f1>((f0 + delt+ofst3), then polar3_32++; +//Bit 15:12 reg_polar3_ofst30 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt-ofst3) or f1>((f0 + delt+ofst3), then polar3_32++; +//Bit 11: 8 reg_polar3_ofst31 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt-ofst3) or f1>((f0 + delt+ofst3), then polar3_32++; +//Bit 7: 4 reg_polar3_ofst20 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++; +//Bit 3: 0 reg_polar3_ofst21 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++; +#define NR2_POLAR3_CTRL ((0x2d9c << 2) + 0xff000000) +//Bit 31:24 reg_polar3_ofst10 // signed , default = 1 +//Bit 23:16 reg_polar3_ofst11 // signed , default = 1 +//Bit 15: 8 reg_polar3_h_mute // unsigned , default = 10 horizontal pixels to mute for left right sides for polar3 detection; +//Bit 7: 0 reg_polar3_v_mute // unsigned , default = 10 vertical pixels to mute for top and bottom sides for polar3 detection; +#define NR2_RO_POLAR3_NUMOFPIX ((0x2d9d << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23: 0 ro_polar3_numofpix // unsigned , default = 0 number of pixels detected as polar3 +#define NR2_RO_POLAR3_SMOOTHMV ((0x2d9e << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23: 0 ro_polar3_smoothmv // unsigned , default = 0 number of pixels with smooth mv, F(t) is close between avg of f(t-1) and f(t+1); +#define NR2_RO_POLAR3_M1 ((0x2d9f << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23: 0 ro_polar3_m1 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but in between [f(t-1), f(t+1)]; +#define NR2_RO_POLAR3_P1 ((0x2da0 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23: 0 ro_polar3_p1 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but in between [f(t-1), f(t+1)]; +#define NR2_RO_POLAR3_M2 ((0x2da1 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23: 0 ro_polar3_m2 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but out side of (f(t-1), f(t+1)); +#define NR2_RO_POLAR3_P2 ((0x2da2 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23: 0 ro_polar3_p2 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but out side of (f(t-1), f(t+1)); +#define NR2_RO_POLAR3_32 ((0x2da3 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23: 0 ro_polar3_32 // unsigned , default = 0 number of pixels with F(t) far from [f(t-1),f(t+1)] and f(t-1) is close to f(t+1); +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_nr2_dpolar_regs.h +// +// 0xa4-0xf7 / 0xff +// +// Reading file: vpu_nr4_regs.h +// +// synopsys translate_off +// synopsys translate_on +//========== nr4_drt_regs register begin ==========// +#define NR4_DRT_CTRL ((0x2da4 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_ydrt_3line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1' +//Bit 23:16 reg_nr4_ydrt_5line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1' +//Bit 15 reserved +//Bit 14:13 reg_nr4_drt_yhsad_mode // unsigned , default = 1 mode for luma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines +//Bit 12:11 reg_nr4_drt_chsad_mode // unsigned , default = 1 mode for chroma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines +//Bit 10 reg_nr4_drt_yhsad_hlpf // unsigned , default = 1 hlpf for luma hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf +//Bit 9 reg_nr4_drt_yvsad_hlpf // unsigned , default = 1 hlpf for luma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf +//Bit 8 reg_nr4_drt_ydsad_hlpf // unsigned , default = 1 hlpf for luma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf +//Bit 7 reg_nr4_drt_chsad_hlpf // unsigned , default = 1 hlpf for chrome hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf +//Bit 6 reg_nr4_drt_cvsad_hlpf // unsigned , default = 1 hlpf for chroma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf +//Bit 5 reg_nr4_drt_cdsad_hlpf // unsigned , default = 1 hlpf for chroma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf +//Bit 4 reg_nr4_ydrt_dif_mode // unsigned , default = 1 0:y_dif, 1: y_dif + (u_dif + v_dif)/2 +//Bit 3: 2 reg_nr4_cdrt_dif_mode // unsigned , default = 2 0:(u_dif + v_dif), 1: y_dif/4 + (u_dif + v_dif)*3/4, 2:y_dif/2 + (u_dif + v_dif)/2, 3: y_dif (not recommended) +//Bit 1: 0 reserved +#define NR4_DRT_YSAD_GAIN ((0x2da5 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_ysad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1" +//Bit 23:16 reg_nr4_ysad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1" +//Bit 15: 8 reg_nr4_ysad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1" +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_drt_ysad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 +#define NR4_DRT_CSAD_GAIN ((0x2da6 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_csad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1" +//Bit 23:16 reg_nr4_csad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1" +//Bit 15: 8 reg_nr4_csad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1" +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_drt_csad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 +#define NR4_DRT_SAD_ALP_CORE ((0x2da7 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:20 reg_nr4_ydrt_alp_core_rate // unsigned , default = 0 luma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32 +//Bit 19:16 reg_nr4_cdrt_alp_core_rate // unsigned , default = 0 chroma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32 +//Bit 15:14 reserved +//Bit 13: 8 reg_nr4_ydrt_alp_core_ofst // unsigned , default = 10 luma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_cdrt_alp_core_ofst // unsigned , default = 10 chroma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10 +#define NR4_DRT_ALP_MINMAX ((0x2da8 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nr4_ydrt_alp_min // unsigned , default = 0 luma min value of alpha, dft = 0 +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_ydrt_alp_max // unsigned , default = 63 luma max value of alpha, dft = 63 +//Bit 15:14 reserved +//Bit 13: 8 reg_nr4_cdrt_alp_min // unsigned , default = 0 chroma min value of alpha, dft = 0 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_cdrt_alp_max // unsigned , default = 63 chroma max value of alpha, dft = 63 +//========== nr4_drt_regs register end ==========// +//========== nr4_snr_regs register begin ==========// +#define NR4_SNR_CTRL_REG ((0x2da9 << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12 reg_nr4_bet2_sel // unsigned , default = 1 +//Bit 11: 9 reg_nr4_snr2_sel_mode // unsigned , default = 0 0: no filter, 1: adpgau, adp_drt_lpf blend; 2: adpgau, drt4_lpf blend; 3: adp_drt_lpf method, 4: drt4_lpf method, 5: adp_drt_ //original image blend, 6: drt4_lpf, original image blend, 7: adpgau method; dft=1 +//Bit 8 reg_nr4_snr2_gaulpf_mode // unsigned , default = 1 0: 3*5 or 5*5 gaussian lpf; 1: 3*3 (window size) gaussian lpf; dft=1 +//Bit 7: 6 reg_nr4_snr2_alpha0_sad_mode // unsigned , default = 3 0: max_sad*max_ssd; 1: max_sad*max_sad; 2: adp_max_sad*max_ssd; 3: adp_max_sad*adp_max_sad dft=3 +//Bit 5: 4 reg_nr4_snr2_alpha1_sad_mode // unsigned , default = 2 0: max_sad; 1: cross_max_sad; 2 or 3: adp_sad dft=2 +//Bit 3: 2 reserved +//Bit 1: 0 reg_nr4_snr2_adp_drtlpf_mode // unsigned , default = 3 0: adp_drtlpf [2 1 1]/4, 1: adp_drtlpf [4 2 1 1]/8; 2: adp_drtlpf [2 2 2 1 1]/8; 3: adp_drtlpf [7 7 7 6 5]/32; dft=3; +#define NR4_SNR_ALPHA0_MAX_MIN ((0x2daa << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:23 reg_nr4_snr2_alp0_ymin // unsigned , default = 127 normalized to 128 as '1' +//Bit 22:16 reg_nr4_snr2_alp0_ymax // unsigned , default = 127 normalized to 128 as '1' +//Bit 15:14 reserved +//Bit 13: 7 reg_nr4_snr2_alp0_cmin // unsigned , default = 127 normalized to 128 as '1' +//Bit 6: 0 reg_nr4_snr2_alp0_cmax // unsigned , default = 127 normalized to 128 as '1' +#define NR4_ALP0C_ERR2CURV_LIMIT0 ((0x2dab << 2) + 0xff000000) +//Bit 31:24 reg_nr4_snr2_alp0_minerr_cpar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur. +//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur. +//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar5 // unsigned , default = 40 rate0 (for mierr<th0) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255. +//Bit 7: 0 reg_nr4_snr2_alp0_minerr_cpar6 // unsigned , default = 40 rate1 (for mierr>th1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255. +#define NR4_ALP0C_ERR2CURV_LIMIT1 ((0x2dac << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar2 // unsigned , default = 127 level limit(for mierr<th0) of curve to map mierr to alp0 for chroma channel, that we can do for flat region. 0~255. +//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar3 // unsigned , default = 0 level limit(for th0<mierr<th1) of curve to map mierr to alp0 for chroma channel, that we can do for misc region. 0~255. +//Bit 7: 0 reg_nr4_snr2_alp0_minerr_cpar4 // unsigned , default = 127 level limit(for mierr>th1) of curve to map mierr to alp0 for chroma channel, that we can do for texture region. 0~255. +#define NR4_ALP0Y_ERR2CURV_LIMIT0 ((0x2dad << 2) + 0xff000000) +//Bit 31:24 reg_nr4_snr2_alp0_minerr_ypar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255. +//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur. +//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar5 // unsigned , default = 40 rate0 (for mierr<th0) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255. +//Bit 7: 0 reg_nr4_snr2_alp0_minerr_ypar6 // unsigned , default = 40 rate1 (for mierr>th1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255. +#define NR4_ALP0Y_ERR2CURV_LIMIT1 ((0x2dae << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar2 // unsigned , default = 127 level limit(for mierr<th0) of curve to map mierr to alp0 for luma channel, set to alp0 that we can do for flat region. 0~255. +//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar3 // unsigned , default = 0 level limit(for th0<mierr<th1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for misc region. 0~255. +//Bit 7: 0 reg_nr4_snr2_alp0_minerr_ypar4 // unsigned , default = 127 level limit(for mierr>th1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for texture region. 0~255. +#define NR4_SNR_ALPA1_RATE_AND_OFST ((0x2daf << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:18 reg_nr4_snr2_alp1_ycore_rate // unsigned , default = 0 normalized 64 as "1" +//Bit 17:12 reg_nr4_snr2_alp1_ccore_rate // unsigned , default = 0 normalized 64 as "1" +//Bit 11: 6 reg_nr4_snr2_alp1_ycore_ofst // signed , default = 3 normalized 64 as "1" +//Bit 5: 0 reg_nr4_snr2_alp1_ccore_ofst // signed , default = 3 normalized 64 as "1" +#define NR4_SNR_ALPHA1_MAX_MIN ((0x2db0 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:18 reg_nr4_snr2_alp1_ymin // unsigned , default = 0 normalized to 64 as '1' +//Bit 17:12 reg_nr4_snr2_alp1_ymax // unsigned , default = 63 normalized to 64 as '1' +//Bit 11: 6 reg_nr4_snr2_alp1_cmin // unsigned , default = 0 normalized to 64 as '1' +//Bit 5: 0 reg_nr4_snr2_alp1_cmax // unsigned , default = 63 normalized to 64 as '1' +#define NR4_ALP1C_ERR2CURV_LIMIT0 ((0x2db1 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_snr2_alp1_minerr_cpar0 // unsigned , default = 0 annel, this will be set value of flat region mierr that no need directional NR. 0~255. +//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar1 // unsigned , default = 24 hannel,this will be set value of texture region mierr that can not do directional NR. 0~255. +//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar5 // unsigned , default = 0 a/chroma channel. the larger of the value, the deep of the slope. +//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar6 // unsigned , default = 20 a/chroma channel. the larger of the value, the deep of the slope. 0~255 +#define NR4_ALP1C_ERR2CURV_LIMIT1 ((0x2db2 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar2 // unsigned , default = 0 will be set to alp1 that we can do for flat region. 0~255. +//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar3 // unsigned , default = 16 this will be set to alp1 that we can do for misc region. 0~255. +//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar4 // unsigned , default = 63 will be set to alp1 that we can do for texture region. 0~255.255 before +#define NR4_ALP1Y_ERR2CURV_LIMIT0 ((0x2db3 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_snr2_alp1_minerr_ypar0 // unsigned , default = 0 thra/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255. +//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar1 // unsigned , default = 24 thra/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255. +//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar5 // unsigned , default = 0 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope. +//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar6 // unsigned , default = 20 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255 +#define NR4_ALP1Y_ERR2CURV_LIMIT1 ((0x2db4 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar2 // unsigned , default = 0 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255. +//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar3 // unsigned , default = 16 levierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255. +//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar4 // unsigned , default = 63 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before +//========== nr4_snr_regs register end ==========// +//========== nr4_tnr_regs register begin ==========// +#define NR4_MTN_CTRL ((0x2db5 << 2) + 0xff000000) +//Bit 31: 2 reserved +//Bit 1 reg_nr4_mtn_ref_en // unsigned , default = 1 enable motion refinement, dft = 1 +//Bit 0 reg_nr4_mtn_ref_bet_sel // unsigned , default = 0 beta selection mode for motion refinement, 0: beta1, 1: beta2, dft = 0 +#define NR4_MTN_REF_PAR0 ((0x2db6 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_mtn_ref_par0 // unsigned , default = 24 par0 for beta to gain, dft = +//Bit 23:16 reg_nr4_mtn_ref_par1 // unsigned , default = 60 par1 for beta to gain, dft = +//Bit 15: 8 reg_nr4_mtn_ref_par2 // unsigned , default = 4 par2 for beta to gain, dft = +//Bit 7: 0 reg_nr4_mtn_ref_par3 // unsigned , default = 32 par3 for beta to gain, dft = +#define NR4_MTN_REF_PAR1 ((0x2db7 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_mtn_ref_par4 // unsigned , default = 128 par4 for beta to gain, dft = +//Bit 15: 8 reg_nr4_mtn_ref_par5 // unsigned , default = 40 par5 for beta to gain, dft = +//Bit 7: 0 reg_nr4_mtn_ref_par6 // unsigned , default = 20 par6 for beta to gain, dft = +//========== nr4_tnr_regs register end ==========// +//========== nr4_mcnr_regs register begin ==========// +#define NR4_MCNR_LUMA_ENH_CTRL ((0x2db8 << 2) + 0xff000000) +//Bit 31: 4 reserved +//Bit 3 reg_nr4_luma_plus_en // unsigned , default = 1 enable luma enhancement, dft = 1 +//Bit 2 reg_nr4_luma_plus_wt_mode // unsigned , default = 1 luma weight calc mode, 0:sqrt(1+x^2), 1: 1+abs(x), dft = 0 +//Bit 1: 0 reg_nr4_luma_plus_orient_mode // unsigned , default = 1 0: only use previous orient for pre and cur luma plus, 1: 0: only use current orient for pre and cur luma plus +#define NR4_MCNR_LUMA_STAT_LIMTX ((0x2db9 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_nr4_luma_plus_xst // unsigned , default = 8 start for luma plus statistic, dft = 8 +//Bit 15:14 reserved +//Bit 13: 0 reg_nr4_luma_plus_xed // unsigned , default = 711 end for luma plus statistic, dft = HSIZE-8-1; +#define NR4_MCNR_LUMA_STAT_LIMTY ((0x2dba << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_nr4_luma_plus_yst // unsigned , default = 8 start for luma plus statistic, dft = 8 +//Bit 15:14 reserved +//Bit 13: 0 reg_nr4_luma_plus_yed // unsigned , default = 231 end for luma plus statistic, dft = VSIZE-8-1 +#define NR4_MCNR_LUMA_DIF_CALC ((0x2dbb << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nr4_luma_plus_ugain // unsigned , default = 8 U's gain for luma enhancement, 16 normalized as '1' +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_luma_plus_vgain // unsigned , default = 8 V's gain for luma enhancement, 16 normalized as '1' +//Bit 15: 8 reg_nr4_luma_plus_ycor_thd // unsigned , default = 2 Y coring threshold for difference calc., dft = 0 +//Bit 7: 0 reg_nr4_luma_plus_ccor_thd // unsigned , default = 0 C coring threshold for difference calc., dft = 0 +#define NR4_MCNR_LUMAPRE_CAL_PRAM ((0x2dbc << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_nr4_pre_u_orient // signed , default = 0 orientation of previous U, initial to 0, and will be updated by software +//Bit 23:18 reserved +//Bit 17:16 reg_nr4_pre_v_orient // signed , default = 0 orientation of previous V, initial to 0, and will be updated by software +//Bit 15: 8 reg_nr4_pre_u_mean // unsigned , default = 0 mean of previous U, initial to 0, and will be updated by software +//Bit 7: 0 reg_nr4_pre_v_mean // unsigned , default = 0 mean of previousV, initial to 0, and will be updated by software +#define NR4_MCNR_LUMACUR_CAL_PRAM ((0x2dbd << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_nr4_cur_u_orient // signed , default = 0 orientation of current U, initial to 0, and will be updated by software +//Bit 23:18 reserved +//Bit 17:16 reg_nr4_cur_v_orient // signed , default = 0 orientation of current V, initial to 0, and will be updated by software +//Bit 15: 8 reg_nr4_cur_u_mean // unsigned , default = 0 mean of current U, initial to 0, and will be updated by software +//Bit 7: 0 reg_nr4_cur_v_mean // unsigned , default = 0 mean of current, initial to 0, and will be updated by software +#define NR4_MCNR_MV_CTRL_REG ((0x2dbe << 2) + 0xff000000) +//Bit 31:14 reserved +//Bit 13:12 reg_nr4_sad_bitw // unsigned , default = 2 sad bit width (8 + x) before clip to u8, dft = 1 +//Bit 11: 4 reg_nr4_glb_gain // unsigned , default = 64 global gain calc. by software, 64 is normalized as '1' +//Bit 3: 0 reg_nr4_mv_err_rsft // unsigned , default = 8 right shift for mv err calc., dft = 9 +#define NR4_MCNR_MV_GAIN0 ((0x2dbf << 2) + 0xff000000) +//Bit 31:28 reg_nr4_lftmvx_gain // unsigned , default = 1 left mvx gain for err calc., dft = 1 +//Bit 27:24 reg_nr4_lftmvy_gain // unsigned , default = 1 left mvy gain for err calc., dft = 1 +//Bit 23:20 reg_nr4_zmvx_gain // unsigned , default = 5 zero mvx gain for err calc., dft = 2 +//Bit 19:16 reg_nr4_zmvy_gain // unsigned , default = 5 zero mvy gain for err calc., dft = 4 +//Bit 15:12 reg_nr4_lmvx0_gain // unsigned , default = 2 line mvx0 gain for err calc., dft = 1 +//Bit 11: 8 reg_nr4_lmvx1_gain // unsigned , default = 2 line mvx1 gain for err calc., dft = 1 +//Bit 7: 4 reg_nr4_lmvy0_gain // unsigned , default = 2 line mvy0 gain for err calc., dft = 1 +//Bit 3: 0 reg_nr4_lmvy1_gain // unsigned , default = 2 line mvy1 gain for err calc., dft = 1 +#define NR4_MCNR_LMV_PARM ((0x2dc0 << 2) + 0xff000000) +//Bit 31:28 reg_nr4_lmv_rt0 // unsigned , default = 3 ratio of max lmv +//Bit 27:24 reg_nr4_lmv_rt1 // unsigned , default = 3 ratio of second max lmv +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_lmv_num_lmt0 // unsigned , default = 16 lmv0 least/limit number of (total number - zero_bin) +//Bit 15:14 reserved +//Bit 13: 8 reg_nr4_lmv_num_lmt1 // unsigned , default = 8 lmv1 least/limit number of (total number - zero_bin - max0) +//Bit 7: 2 reserved +//Bit 1: 0 reg_nr4_max_sad_rng // unsigned , default = 1 search range of max2 sad in small region, dft = 1 +#define NR4_MCNR_ALP0_REG ((0x2dc1 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25 reg_nr4_alp0_fail_chk // unsigned , default = 1 enable check for alp0 fail status +//Bit 24 reg_nr4_bet0_coef_ref_en // unsigned , default = 1 bet1 refinement by coef_blt +//Bit 23:16 reg_nr4_alp0_posad_gain // unsigned , default = 255 the sad (norm) gain for pixel pointed by MV; +//Bit 15:10 reserved +//Bit 9: 8 reg_nr4_alp0_norm_mode // unsigned , default = 0 alp0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_alp0_norm_gain // unsigned , default = 16 alp0 gain for sad norm, '32' as '1', dft = 1 +#define NR4_MCNR_ALP1_AND_BET0_REG ((0x2dc2 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_nr4_alp1_norm_mode // unsigned , default = 3 alp1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_alp1_norm_gain // unsigned , default = 3 alp1 gain for sad norm, '32' as '1', dft = 1 +//Bit 15:10 reserved +//Bit 9: 8 reg_nr4_bet0_norm_mode // unsigned , default = 3 bet0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_bet0_norm_gain // unsigned , default = 8 bet0 gain for sad norm, '32' as '1', dft = 1 +#define NR4_MCNR_BET1_AND_BET2_REG ((0x2dc3 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_nr4_bet1_norm_mode // unsigned , default = 3 bet1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_bet1_norm_gain // unsigned , default = 8 bet1 gain for sad norm, '32' as '1', dft = 1 +//Bit 15:10 reserved +//Bit 9: 8 reg_nr4_bet2_norm_mode // unsigned , default = 0 bet2 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_bet2_norm_gain // unsigned , default = 16 bet2 gain for sad norm, '32' as '1', dft = 1 +#define NR4_MCNR_AC_DC_CRTL ((0x2dc4 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15:12 reserved +//Bit 11 reg_nr4_dc_mode // unsigned , default = 1 mode for dc selection,0: Y_lpf, 1: Y_lpf + (U_Lpf+V_lpf)/2, +//Bit 10 reg_nr4_ac_mode // unsigned , default = 1 mode for ac selection, 0: Y_abs_dif, 1: Y_abs_dif + (U_abs_dif + V_abs_dif)/2 +//Bit 9 reg_nr4_dc_sel // unsigned , default = 0 selection mode for dc value, 0: 3x5, 1: 5x5, dft = 1 +//Bit 8 reg_nr4_ac_sel // unsigned , default = 0 selection mode for ac value, 0: 3x5, 1: 5x5, dft = 1 +//Bit 7 reserved +//Bit 6: 4 reg_nr4_dc_shft // unsigned , default = 2 right shift for dc value, dft = 2 +//Bit 3 reserved +//Bit 2: 0 reg_nr4_ac_shft // unsigned , default = 0 right shift for ac value, dft = 2 +#define NR4_MCNR_CM_CTRL0 ((0x2dc5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28 reg_nr4_cm_skin_prc_bet0 // unsigned , default = 0 enable skin tone processing for mcnr bet0 calc., dft = 1 +//Bit 27:26 reg_nr4_cm_chrm_sel // unsigned , default = 1 chrome selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3 +//Bit 25:24 reg_nr4_cm_luma_sel // unsigned , default = 1 luma selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3 +//Bit 23:21 reg_nr4_cm_skin_rshft_bet0 // unsigned , default = 3 right shift for bet0's skin color gains, dft = 3 +//Bit 20 reg_nr4_cm_var_sel // unsigned , default = 1 variation selection for color match, 0: 3x5, 1: 5x5 for 5lines, 3x5 for 3lines, dft = 1 +//Bit 19 reg_nr4_cm_green_prc_bet0 // unsigned , default = 1 enable green processing for mcnr bet0 calc., dft = 1 +//Bit 18:16 reg_nr4_cm_green_rshft_bet0 // unsigned , default = 4 right shift for bet0's green color gains, dft = 4 +//Bit 15:14 reg_nr4_preflt_mod // unsigned , default = 2 pre filter mode in mcnr, 0: mv pointed pixel, 1: bilater filter +//Bit 13:12 reg_nr4_alp1_mode // unsigned , default = 1 mode for alpha1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad +//Bit 11:10 reserved +//Bit 9: 8 reg_nr4_bet0_mode // unsigned , default = 0 mode for bet0's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad) +//Bit 7: 6 reserved +//Bit 5: 4 reg_nr4_bet1_mode // unsigned , default = 2 mode for bet1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad) +//Bit 3: 2 reserved +//Bit 1: 0 reg_nr4_bet2_mode // unsigned , default = 1 mode for bet2's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad) +#define NR4_MCNR_CM_PRAM ((0x2dc6 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29 reg_nr4_cm_blue_prc_alp0 // unsigned , default = 1 enable blue processing for mcnr alpha0 calc., dft = 1 +//Bit 28 reg_nr4_cm_blue_prc_alp1 // unsigned , default = 1 enable blue processing for mcnr alpha1 calc., dft = 1 +//Bit 27 reg_nr4_cm_skin_prc_alp0 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1 +//Bit 26 reg_nr4_cm_green_prc_alp0 // unsigned , default = 1 enable green processing for mcnr alpha0 clac., dft = 1 +//Bit 25 reg_nr4_cm_skin_prc_alp1 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1 +//Bit 24 reg_nr4_cm_green_prc_alp1 // unsigned , default = 1 enable green processing for mcnr alpha1 clac., dft = 1 +//Bit 23:20 reg_nr4_cm_blue_hue_st // unsigned , default = 13 hue start of blue, dft = +//Bit 19:16 reg_nr4_cm_blue_hue_ed // unsigned , default = 15 hue end of blue, dft = +//Bit 15:12 reg_nr4_cm_green_hue_st // unsigned , default = 7 hue start of green, dft = +//Bit 11: 8 reg_nr4_cm_green_hue_ed // unsigned , default = 10 hue end of green, dft = +//Bit 7: 4 reg_nr4_cm_skin_hue_st // unsigned , default = 5 hue start of skin, dft = +//Bit 3: 0 reg_nr4_cm_skin_hue_ed // unsigned , default = 6 hue end of skin, dft = +#define NR4_MCNR_CM_RSHFT_ALP0 ((0x2dc7 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:25 reg_nr4_cm_blue_rshft_bet0 // unsigned , default = 5 right shift for bet0's blue color gains, dft = 5 +//Bit 24 reg_nr4_cm_blue_prc_bet0 // unsigned , default = 1 enable blue processing for mcnr bet0 calc., dft = 1 +//Bit 23 reserved +//Bit 22:20 reg_nr4_cm_blue_rshft_alp0 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5 +//Bit 19 reserved +//Bit 18:16 reg_nr4_cm_blue_rshft_alp1 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5 +//Bit 15 reserved +//Bit 14:12 reg_nr4_cm_green_rshft_alp0 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4 +//Bit 11 reserved +//Bit 10: 8 reg_nr4_cm_green_rshft_alp1 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4 +//Bit 7 reserved +//Bit 6: 4 reg_nr4_cm_skin_rshft_alp0 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3 +//Bit 3 reserved +//Bit 2: 0 reg_nr4_cm_skin_rshft_alp1 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3 +#define NR4_MCNR_BLUE_CENT ((0x2dc8 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_blue_centx // unsigned , default = 157 x coordinate of center of blue, dft = +//Bit 15: 8 reserved +//Bit 7: 0 reg_nr4_cm_blue_centy // unsigned , default = 110 y coordinate of center of blue, dft = +#define NR4_MCNR_BLUE_GAIN_PAR0 ((0x2dc9 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_cm_blue_gain_par0 // unsigned , default = 32 par0 for blue gain, dft = +//Bit 23:16 reg_nr4_cm_blue_gain_par1 // unsigned , default = 255 par1 for blue gain, dft = +//Bit 15: 8 reg_nr4_cm_blue_gain_par2 // unsigned , default = 4 par2 for blue gain, dft = +//Bit 7: 0 reg_nr4_cm_blue_gain_par3 // unsigned , default = 32 par3 for blue gain, dft = +#define NR4_MCNR_BLUE_GAIN_PAR1 ((0x2dca << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_blue_gain_par4 // unsigned , default = 32 par4 for blue gain, dft = +//Bit 15: 8 reg_nr4_cm_blue_gain_par5 // unsigned , default = 32 par5 for blue gain, dft = +//Bit 7: 0 reg_nr4_cm_blue_gain_par6 // unsigned , default = 0 par6 for blue gain, dft = +#define NR4_MCNR_CM_BLUE_CLIP0 ((0x2dcb << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_blue_luma_min // unsigned , default = 40 luma min for blue color matching, dft = +//Bit 15: 8 reserved +//Bit 7: 0 reg_nr4_cm_blue_luma_max // unsigned , default = 180 luma max for blue color matching, dft = +#define NR4_MCNR_CM_BLUE_CLIP1 ((0x2dcc << 2) + 0xff000000) +//Bit 31:24 reg_nr4_cm_blue_sat_min // unsigned , default = 5 saturation min for blue color matching, dft = +//Bit 23:16 reg_nr4_cm_blue_sat_max // unsigned , default = 255 saturation max for blue color matching, dft = +//Bit 15: 8 reg_nr4_cm_blue_var_min // unsigned , default = 0 variation min for blue color matching, dft = +//Bit 7: 0 reg_nr4_cm_blue_var_max // unsigned , default = 12 variation max for blue color matching, dft = +#define NR4_MCNR_GREEN_CENT ((0x2dcd << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_green_centx // unsigned , default = 114 x coordinate of center of green, dft = +//Bit 15: 8 reserved +//Bit 7: 0 reg_nr4_cm_green_centy // unsigned , default = 126 y coordinate of center of green, dft = +#define NR4_MCNR_GREEN_GAIN_PAR0 ((0x2dce << 2) + 0xff000000) +//Bit 31:24 reg_nr4_cm_green_gain_par0 // unsigned , default = 16 par0 for green gain, dft = +//Bit 23:16 reg_nr4_cm_green_gain_par1 // unsigned , default = 255 par1 for green gain, dft = +//Bit 15: 8 reg_nr4_cm_green_gain_par2 // unsigned , default = 255 par2 for green gain, dft = +//Bit 7: 0 reg_nr4_cm_green_gain_par3 // unsigned , default = 16 par3 for green gain, dft = +#define NR4_MCNR_GREEN_GAIN_PAR1 ((0x2dcf << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_green_gain_par4 // unsigned , default = 16 par4 for green gain, dft = +//Bit 15: 8 reg_nr4_cm_green_gain_par5 // unsigned , default = 128 par5 for green gain, dft = +//Bit 7: 0 reg_nr4_cm_green_gain_par6 // unsigned , default = 0 par6 for green gain, dft = +#define NR4_MCNR_GREEN_CLIP0 ((0x2dd0 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_green_luma_min // unsigned , default = 40 luma min for green color matching, dft = +//Bit 15: 8 reserved +//Bit 7: 0 reg_nr4_cm_green_luma_max // unsigned , default = 160 luma max for green color matching, dft = +#define NR4_MCNR_GREEN_CLIP2 ((0x2dd1 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_cm_green_sat_min // unsigned , default = 4 saturation min for green color matching, dft = +//Bit 23:16 reg_nr4_cm_green_sat_max // unsigned , default = 255 saturation max for green color matching, dft = +//Bit 15: 8 reg_nr4_cm_green_var_min // unsigned , default = 0 variation min for green color matching, dft = +//Bit 7: 0 reg_nr4_cm_green_var_max // unsigned , default = 12 variation max for green color matching, dft = +#define NR4_MCNR_SKIN_CENT ((0x2dd2 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_skin_centx // unsigned , default = 112 x coordinate of center of skin tone, dft = +//Bit 15: 8 reserved +//Bit 7: 0 reg_nr4_cm_skin_centy // unsigned , default = 149 y coordinate of center of skin tone, dft = +#define NR4_MCNR_SKIN_GAIN_PAR0 ((0x2dd3 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_cm_skin_gain_par0 // unsigned , default = 20 par0 for skin gain, dft = +//Bit 23:16 reg_nr4_cm_skin_gain_par1 // unsigned , default = 255 par1 for skin gain, dft = +//Bit 15: 8 reg_nr4_cm_skin_gain_par2 // unsigned , default = 255 par2 for skin gain, dft = +//Bit 7: 0 reg_nr4_cm_skin_gain_par3 // unsigned , default = 8 par3 for skin gain, dft = +#define NR4_MCNR_SKIN_GAIN_PAR1 ((0x2dd4 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_skin_gain_par4 // unsigned , default = 8 par4 for skin gain, dft = +//Bit 15: 8 reg_nr4_cm_skin_gain_par5 // unsigned , default = 128 par5 for skin gain, dft = +//Bit 7: 0 reg_nr4_cm_skin_gain_par6 // unsigned , default = 0 par6 for skin gain, dft = +#define NR4_MCNR_SKIN_CLIP0 ((0x2dd5 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_cm_skin_luma_min // unsigned , default = 40 luma min for skin color matching, dft = +//Bit 15: 8 reserved +//Bit 7: 0 reg_nr4_cm_skin_luma_max // unsigned , default = 180 luma max for skin color matching, dft = +#define NR4_MCNR_SKIN_CLIP1 ((0x2dd6 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_cm_skin_sat_min // unsigned , default = 5 saturation min for skin color matching, dft = +//Bit 23:16 reg_nr4_cm_skin_sat_max // unsigned , default = 255 saturation max for skin color matching, dft = +//Bit 15: 8 reg_nr4_cm_skin_var_min // unsigned , default = 0 variation min for skin color matching, dft = +//Bit 7: 0 reg_nr4_cm_skin_var_max // unsigned , default = 12 variation max for skin color matching, dft = +#define NR4_MCNR_ALP1_GLB_CTRL ((0x2dd7 << 2) + 0xff000000) +//Bit 31 reg_nr4_alp1_glb_gain_en // unsigned , default = 0 alp1 adjust by global gain, dft = 1 +//Bit 30:28 reg_nr4_alp1_glb_gain_lsft // unsigned , default = 6 alp1 left shift before combine with global gain +//Bit 27 reg_nr4_bet0_glb_gain_en // unsigned , default = 1 bet0 adjust by global gain, dft = 1 +//Bit 26:24 reg_nr4_bet0_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain +//Bit 23 reg_nr4_bet1_glb_gain_en // unsigned , default = 0 bet1 adjust by global gain, dft = 0 +//Bit 22:20 reg_nr4_bet1_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain +//Bit 19 reg_nr4_bet2_glb_gain_en // unsigned , default = 1 bet2 adjust by global gain, dft = 1 +//Bit 18:16 reg_nr4_bet2_glb_gain_lsft // unsigned , default = 6 bet2 left shift before combine with global gain +//Bit 15 reg_nr4_alp1_ac_en // unsigned , default = 1 alp1 adjust by ac, dft = 1 +//Bit 14:12 reg_nr4_alp1_ac_lsft // unsigned , default = 5 alp1 left shift before combine with ac +//Bit 11 reg_nr4_bet0_ac_en // unsigned , default = 0 bet0 adjust by ac, dft = 1 +//Bit 10: 8 reg_nr4_bet0_ac_lsft // unsigned , default = 5 bet0 left shift before combine with ac +//Bit 7 reg_nr4_bet1_ac_en // unsigned , default = 0 bet1 adjust by ac, dft = 1 +//Bit 6: 4 reg_nr4_bet1_ac_lsft // unsigned , default = 5 bet1 left shift before combine with ac +//Bit 3 reg_nr4_bet2_ac_en // unsigned , default = 0 bet2 adjust by ac, dft = 1 +//Bit 2: 0 reg_nr4_bet2_ac_lsft // unsigned , default = 5 bet2 left shift before combine with ac +#define NR4_MCNR_DC2NORM_LUT0 ((0x2dd8 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:24 reg_nr4_dc2norm_lut0 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = +//Bit 23:21 reserved +//Bit 20:16 reg_nr4_dc2norm_lut1 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = +//Bit 15:13 reserved +//Bit 12: 8 reg_nr4_dc2norm_lut2 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = +//Bit 7: 5 reserved +//Bit 4: 0 reg_nr4_dc2norm_lut3 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = +#define NR4_MCNR_DC2NORM_LUT1 ((0x2dd9 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:24 reg_nr4_dc2norm_lut4 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = +//Bit 23:21 reserved +//Bit 20:16 reg_nr4_dc2norm_lut5 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = +//Bit 15:13 reserved +//Bit 12: 8 reg_nr4_dc2norm_lut6 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft = +//Bit 7: 5 reserved +//Bit 4: 0 reg_nr4_dc2norm_lut7 // unsigned , default = 12 normal 0~16, dc to norm for alpha adjust, dft = +#define NR4_MCNR_DC2NORM_LUT2 ((0x2dda << 2) + 0xff000000) +//Bit 31: 5 reserved +//Bit 4: 0 reg_nr4_dc2norm_lut8 // unsigned , default = 8 normal 0~16, dc to norm for alpha adjust, dft = +#define NR4_MCNR_AC2NORM_LUT0 ((0x2ddb << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:24 reg_nr4_ac2norm_lut0 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft = +//Bit 23:21 reserved +//Bit 20:16 reg_nr4_ac2norm_lut1 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft = +//Bit 15:13 reserved +//Bit 12: 8 reg_nr4_ac2norm_lut2 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft = +//Bit 7: 5 reserved +//Bit 4: 0 reg_nr4_ac2norm_lut3 // unsigned , default = 12 normal 0~16, ac to norm for alpha adjust, dft = +#define NR4_MCNR_AC2NORM_LUT1 ((0x2ddc << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:24 reg_nr4_ac2norm_lut4 // unsigned , default = 4 normal 0~16, ac to norm for alpha adjust, dft = +//Bit 23:21 reserved +//Bit 20:16 reg_nr4_ac2norm_lut5 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft = +//Bit 15:13 reserved +//Bit 12: 8 reg_nr4_ac2norm_lut6 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft = +//Bit 7: 5 reserved +//Bit 4: 0 reg_nr4_ac2norm_lut7 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft = +#define NR4_MCNR_AC2NORM_LUT2 ((0x2ddd << 2) + 0xff000000) +//Bit 31: 5 reserved +//Bit 4: 0 reg_nr4_ac2norm_lut8 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft = +#define NR4_MCNR_SAD2ALP0_LUT0 ((0x2dde << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2alp0_lut0 // unsigned , default = 255 sad to alpha0 for temporal pixel value, dft = 255 +//Bit 23:16 reg_nr4_sad2alp0_lut1 // unsigned , default = 252 sad to alpha0 for temporal pixel value, dft = 252 +//Bit 15: 8 reg_nr4_sad2alp0_lut2 // unsigned , default = 249 sad to alpha0 for temporal pixel value, dft = 249 +//Bit 7: 0 reg_nr4_sad2alp0_lut3 // unsigned , default = 235 sad to alpha0 for temporal pixel value, dft = 70 +#define NR4_MCNR_SAD2ALP0_LUT1 ((0x2ddf << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2alp0_lut4 // unsigned , default = 185 sad to alpha0 for temporal pixel value, dft = 12 +//Bit 23:16 reg_nr4_sad2alp0_lut5 // unsigned , default = 70 sad to alpha0 for temporal pixel value, dft = 1 +//Bit 15: 8 reg_nr4_sad2alp0_lut6 // unsigned , default = 14 sad to alpha0 for temporal pixel value, dft = 0 +//Bit 7: 0 reg_nr4_sad2alp0_lut7 // unsigned , default = 1 sad to alpha0 for temporal pixel value, dft = 0 +#define NR4_MCNR_SAD2ALP0_LUT2 ((0x2de0 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2alp0_lut8 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 +//Bit 23:16 reg_nr4_sad2alp0_lut9 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 +//Bit 15: 8 reg_nr4_sad2alp0_lut10 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 +//Bit 7: 0 reg_nr4_sad2alp0_lut11 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 +#define NR4_MCNR_SAD2ALP0_LUT3 ((0x2de1 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2alp0_lut12 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 +//Bit 23:16 reg_nr4_sad2alp0_lut13 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 +//Bit 15: 8 reg_nr4_sad2alp0_lut14 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 +//Bit 7: 0 reg_nr4_sad2alp0_lut15 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0 +#define NR4_MCNR_SAD2ALP1_LUT0 ((0x2de2 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2alp1_lut0 // unsigned , default = 192 sad to alpha1 for temporal blending, dft = 128 +//Bit 23:16 reg_nr4_sad2alp1_lut1 // unsigned , default = 160 sad to alpha1 for temporal blending, dft = 128 +//Bit 15: 8 reg_nr4_sad2alp1_lut2 // unsigned , default = 128 sad to alpha1 for temporal blending, dft = 128 +//Bit 7: 0 reg_nr4_sad2alp1_lut3 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 64 +#define NR4_MCNR_SAD2ALP1_LUT1 ((0x2de3 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2alp1_lut4 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 64 +//Bit 23:16 reg_nr4_sad2alp1_lut5 // unsigned , default = 32 sad to alpha1 for temporal blending, dft = 128 +//Bit 15: 8 reg_nr4_sad2alp1_lut6 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255 +//Bit 7: 0 reg_nr4_sad2alp1_lut7 // unsigned , default = 8 sad to alpha1 for temporal blending, dft = 255 +#define NR4_MCNR_SAD2ALP1_LUT2 ((0x2de4 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2alp1_lut8 // unsigned , default = 4 sad to alpha1 for temporal blending, dft = 255 +//Bit 23:16 reg_nr4_sad2alp1_lut9 // unsigned , default = 0 sad to alpha1 for temporal blending, dft = 255 +//Bit 15: 8 reg_nr4_sad2alp1_lut10 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255 +//Bit 7: 0 reg_nr4_sad2alp1_lut11 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 255 +#define NR4_MCNR_SAD2ALP1_LUT3 ((0x2de5 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2alp1_lut12 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 255 +//Bit 23:16 reg_nr4_sad2alp1_lut13 // unsigned , default = 224 sad to alpha1 for temporal blending, dft = 255 +//Bit 15: 8 reg_nr4_sad2alp1_lut14 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255 +//Bit 7: 0 reg_nr4_sad2alp1_lut15 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255 +#define NR4_MCNR_SAD2BET0_LUT0 ((0x2de6 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet0_lut0 // unsigned , default = 0 sad to beta0 for tnr and mcnr blending, dft = 0 +//Bit 23:16 reg_nr4_sad2bet0_lut1 // unsigned , default = 2 sad to beta0 for tnr and mcnr blending, dft = 2 +//Bit 15: 8 reg_nr4_sad2bet0_lut2 // unsigned , default = 4 sad to beta0 for tnr and mcnr blending, dft = 4 +//Bit 7: 0 reg_nr4_sad2bet0_lut3 // unsigned , default = 8 sad to beta0 for tnr and mcnr blending, dft = 8 +#define NR4_MCNR_SAD2BET0_LUT1 ((0x2de7 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet0_lut4 // unsigned , default = 16 sad to beta0 for tnr and mcnr blending, dft = 16 +//Bit 23:16 reg_nr4_sad2bet0_lut5 // unsigned , default = 32 sad to beta0 for tnr and mcnr blending, dft = 32 +//Bit 15: 8 reg_nr4_sad2bet0_lut6 // unsigned , default = 48 sad to beta0 for tnr and mcnr blending, dft = 48 +//Bit 7: 0 reg_nr4_sad2bet0_lut7 // unsigned , default = 64 sad to beta0 for tnr and mcnr blending, dft = 64 +#define NR4_MCNR_SAD2BET0_LUT2 ((0x2de8 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet0_lut8 // unsigned , default = 80 sad to beta0 for tnr and mcnr blending, dft = 80 +//Bit 23:16 reg_nr4_sad2bet0_lut9 // unsigned , default = 96 sad to beta0 for tnr and mcnr blending, dft = 96 +//Bit 15: 8 reg_nr4_sad2bet0_lut10 // unsigned , default = 112 sad to beta0 for tnr and mcnr blending, dft = 112 +//Bit 7: 0 reg_nr4_sad2bet0_lut11 // unsigned , default = 128 sad to beta0 for tnr and mcnr blending, dft = 128 +#define NR4_MCNR_SAD2BET0_LUT3 ((0x2de9 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet0_lut12 // unsigned , default = 196 sad to beta0 for tnr and mcnr blending, dft = 160 +//Bit 23:16 reg_nr4_sad2bet0_lut13 // unsigned , default = 224 sad to beta0 for tnr and mcnr blending, dft = 192 +//Bit 15: 8 reg_nr4_sad2bet0_lut14 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 224 +//Bit 7: 0 reg_nr4_sad2bet0_lut15 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 255 +#define NR4_MCNR_SAD2BET1_LUT0 ((0x2dea << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet1_lut0 // unsigned , default = 0 sad to beta1 for deghost blending, dft = 0 +//Bit 23:16 reg_nr4_sad2bet1_lut1 // unsigned , default = 2 sad to beta1 for deghost blending, dft = 2 +//Bit 15: 8 reg_nr4_sad2bet1_lut2 // unsigned , default = 4 sad to beta1 for deghost blending, dft = 4 +//Bit 7: 0 reg_nr4_sad2bet1_lut3 // unsigned , default = 8 sad to beta1 for deghost blending, dft = 8 +#define NR4_MCNR_SAD2BET1_LUT1 ((0x2deb << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet1_lut4 // unsigned , default = 16 sad to beta1 for deghost blending, dft = 16 +//Bit 23:16 reg_nr4_sad2bet1_lut5 // unsigned , default = 32 sad to beta1 for deghost blending, dft = 32 +//Bit 15: 8 reg_nr4_sad2bet1_lut6 // unsigned , default = 48 sad to beta1 for deghost blending, dft = 48 +//Bit 7: 0 reg_nr4_sad2bet1_lut7 // unsigned , default = 64 sad to beta1 for deghost blending, dft = 64 +#define NR4_MCNR_SAD2BET1_LUT2 ((0x2dec << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet1_lut8 // unsigned , default = 80 sad to beta1 for deghost blending, dft = 80 +//Bit 23:16 reg_nr4_sad2bet1_lut9 // unsigned , default = 96 sad to beta1 for deghost blending, dft = 96 +//Bit 15: 8 reg_nr4_sad2bet1_lut10 // unsigned , default = 112 sad to beta1 for deghost blending, dft = 112 +//Bit 7: 0 reg_nr4_sad2bet1_lut11 // unsigned , default = 128 sad to beta1 for deghost blending, dft = 128 +#define NR4_MCNR_SAD2BET1_LUT3 ((0x2ded << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet1_lut12 // unsigned , default = 160 sad to beta1 for deghost blending, dft = 160 +//Bit 23:16 reg_nr4_sad2bet1_lut13 // unsigned , default = 192 sad to beta1 for deghost blending, dft = 192 +//Bit 15: 8 reg_nr4_sad2bet1_lut14 // unsigned , default = 224 sad to beta1 for deghost blending, dft = 224 +//Bit 7: 0 reg_nr4_sad2bet1_lut15 // unsigned , default = 255 sad to beta1 for deghost blending, dft = 255 +#define NR4_MCNR_SAD2BET2_LUT0 ((0x2dee << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet2_lut0 // unsigned , default = 0 sad to beta2 for snr and mcnr blending, dft = 0 +//Bit 23:16 reg_nr4_sad2bet2_lut1 // unsigned , default = 1 sad to beta2 for snr and mcnr blending, dft = 2 +//Bit 15: 8 reg_nr4_sad2bet2_lut2 // unsigned , default = 2 sad to beta2 for snr and mcnr blending, dft = 4 +//Bit 7: 0 reg_nr4_sad2bet2_lut3 // unsigned , default = 4 sad to beta2 for snr and mcnr blending, dft = 8 +#define NR4_MCNR_SAD2BET2_LUT1 ((0x2def << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet2_lut4 // unsigned , default = 8 sad to beta2 for snr and mcnr blending, dft = 16 +//Bit 23:16 reg_nr4_sad2bet2_lut5 // unsigned , default = 16 sad to beta2 for snr and mcnr blending, dft = 32 +//Bit 15: 8 reg_nr4_sad2bet2_lut6 // unsigned , default = 32 sad to beta2 for snr and mcnr blending, dft = 48 +//Bit 7: 0 reg_nr4_sad2bet2_lut7 // unsigned , default = 48 sad to beta2 for snr and mcnr blending, dft = 64 +#define NR4_MCNR_SAD2BET2_LUT2 ((0x2df0 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet2_lut8 // unsigned , default = 64 sad to beta2 for snr and mcnr blending, dft = 80 +//Bit 23:16 reg_nr4_sad2bet2_lut9 // unsigned , default = 80 sad to beta2 for snr and mcnr blending, dft = 96 +//Bit 15: 8 reg_nr4_sad2bet2_lut10 // unsigned , default = 96 sad to beta2 for snr and mcnr blending, dft = 112 +//Bit 7: 0 reg_nr4_sad2bet2_lut11 // unsigned , default = 112 sad to beta2 for snr and mcnr blending, dft = 128 +#define NR4_MCNR_SAD2BET2_LUT3 ((0x2df1 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_sad2bet2_lut12 // unsigned , default = 128 sad to beta2 for snr and mcnr blending, dft = 160 +//Bit 23:16 reg_nr4_sad2bet2_lut13 // unsigned , default = 160 sad to beta2 for snr and mcnr blending, dft = 192 +//Bit 15: 8 reg_nr4_sad2bet2_lut14 // unsigned , default = 224 sad to beta2 for snr and mcnr blending, dft = 224 +//Bit 7: 0 reg_nr4_sad2bet2_lut15 // unsigned , default = 255 sad to beta2 for snr and mcnr blending, dft = 255 +#define NR4_MCNR_RO_U_SUM ((0x2df2 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_u_sum // unsigned , default = 0 sum of U of current field/frame +#define NR4_MCNR_RO_V_SUM ((0x2df3 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_v_sum // unsigned , default = 0 sum of V of current field/frame +#define NR4_MCNR_RO_GRDU_SUM ((0x2df4 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_grdu_sum // unsigned , default = 0 sum of gradient U of current field/frame +#define NR4_MCNR_RO_GRDV_SUM ((0x2df5 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_grdv_sum // unsigned , default = 0 sum of gradient V of current field/frame +#define NR4_TOP_CTRL ((0x2dff << 2) + 0xff000000) +//Bit 31:20 reg_gclk_ctrl // unsigned , default = 0 +//Bit 19 reserved +//Bit 18 reg_nr4_mcnr_en // unsigned , default = 1 ncnr enable or bypass, dft = 1 +//Bit 17 reg_nr2_en // unsigned , default = 1 nr2 enable, dft = 1 +//Bit 16 reg_nr4_en // unsigned , default = 1 nr4 enable, dft = 1 +//Bit 15 reg_nr2_proc_en // unsigned , default = 1 +//Bit 14 reg_det3d_en // unsigned , default = 1 +//Bit 13 di_polar_en // unsigned , default = 1 do does not have in C +//Bit 12 reg_cfr_enable // unsigned , default = 0 0-disable; 1:enable +//Bit 11: 9 reg_3dnr_enable_l // unsigned , default = 7 b0: Y b1:U b2:V +//Bit 8: 6 reg_3dnr_enable_r // unsigned , default = 7 b0: Y b1:U b2:V +//Bit 5 reg_nr4_lnbuf_ctrl // unsigned , default = 1 line buf ctrl for nr4: 0, 3lines, 1, 5lines, dft = 1 +//Bit 4 reg_nr4_snr2_en // unsigned , default = 0 snr2 enable, 0: use old snr, 1: use new snr2, dft = 1 +//Bit 3 reg_nr4_scene_change_en // unsigned , default = 1 enable scene change proc. dft = 1 +//Bit 2 nr2_sw_en // unsigned , default = 1 do does not have in C +//Bit 1 reserved +//Bit 0 reg_nr4_scene_change_flg // unsigned , default = 0 flags for scene change, dft = 0 +//========== nr4_mcnr_regs register end ==========// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_nr4_regs.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_dnr_regs.h +// +//======================================================================== +// VI_HIST_SPL register (16'h2e00 - 16'h2eff) +//======================================================================== +// +// Reading file: vi_hist_spl_reg.h +// +// synopsys translate_off +// synopsys translate_on +// ---------------------------- +// VI_HIST_SPL 0x2e +// ---------------------------- +// ----------------------------------------------- +// REG_BASE: VI_HIST_SPL_VCBUS_BASE = 0x2e +// ----------------------------------------------- +//BIT 14: 34bin only, 0&255 and other 32bins +//Bit 13:11 hist_din_sel, 00: from vdin0 dout, 1: from vdin1, 2: from nr dout, 3: di output, 4: vpp output, 5: vd1_din, 6: vd2_din, 7:osd1_dout +//Bit 10:8 hist_din_comp_mux, mux of [29:22], [19:12], [9:2] for hist detect +//Bit 7:5 hist_dnlp_low the real pixels in each bins got by VI_DNLP_HISTXX should multiple with 2^(dnlp_low+3) +//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din +//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window +//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback +#define VI_HIST_CTRL ((0x2e00 << 2) + 0xff000000) +//Bit 28:16 hist_hstart horizontal start value to define hist window +//Bit 12:0 hist_hend horizontal end value to define hist window +#define VI_HIST_H_START_END ((0x2e01 << 2) + 0xff000000) +//Bit 28:16 hist_vstart vertical start value to define hist window +//Bit 12:0 hist_vend vertical end value to define hist window +#define VI_HIST_V_START_END ((0x2e02 << 2) + 0xff000000) +//Bit 15:8 hist_max maximum value +//Bit 7:0 hist_min minimum value +//read only +#define VI_HIST_MAX_MIN ((0x2e03 << 2) + 0xff000000) +//Bit 31:0 hist_spl_rd +//counts for the total luma value +//read only +#define VI_HIST_SPL_VAL ((0x2e04 << 2) + 0xff000000) +//Bit 21:0 hist_spl_pixel_count +//counts for the total calculated pixels +//read only +#define VI_HIST_SPL_PIX_CNT ((0x2e05 << 2) + 0xff000000) +//Bit 31:0 hist_chroma_sum +//counts for the total chroma value +//read only +#define VI_HIST_CHROMA_SUM ((0x2e06 << 2) + 0xff000000) +//Bit 31:16 higher hist bin +//Bit 15:0 lower hist bin +//0-255 are splited to 64 bins evenly, and VI_DNLP_HISTXX +//are the statistic number of pixels that within each bin. +//VI_DNLP_HIST00[15:0] counts for the first bin +//VI_DNLP_HIST00[31:16] counts for the second bin +//VI_DNLP_HIST01[15:0] counts for the third bin +//VI_DNLP_HIST01[31:16] counts for the fourth bin +//etc... +//read only +#define VI_DNLP_HIST00 ((0x2e07 << 2) + 0xff000000) +#define VI_DNLP_HIST01 ((0x2e08 << 2) + 0xff000000) +#define VI_DNLP_HIST02 ((0x2e09 << 2) + 0xff000000) +#define VI_DNLP_HIST03 ((0x2e0a << 2) + 0xff000000) +#define VI_DNLP_HIST04 ((0x2e0b << 2) + 0xff000000) +#define VI_DNLP_HIST05 ((0x2e0c << 2) + 0xff000000) +#define VI_DNLP_HIST06 ((0x2e0d << 2) + 0xff000000) +#define VI_DNLP_HIST07 ((0x2e0e << 2) + 0xff000000) +#define VI_DNLP_HIST08 ((0x2e0f << 2) + 0xff000000) +#define VI_DNLP_HIST09 ((0x2e10 << 2) + 0xff000000) +#define VI_DNLP_HIST10 ((0x2e11 << 2) + 0xff000000) +#define VI_DNLP_HIST11 ((0x2e12 << 2) + 0xff000000) +#define VI_DNLP_HIST12 ((0x2e13 << 2) + 0xff000000) +#define VI_DNLP_HIST13 ((0x2e14 << 2) + 0xff000000) +#define VI_DNLP_HIST14 ((0x2e15 << 2) + 0xff000000) +#define VI_DNLP_HIST15 ((0x2e16 << 2) + 0xff000000) +#define VI_DNLP_HIST16 ((0x2e17 << 2) + 0xff000000) +#define VI_DNLP_HIST17 ((0x2e18 << 2) + 0xff000000) +#define VI_DNLP_HIST18 ((0x2e19 << 2) + 0xff000000) +#define VI_DNLP_HIST19 ((0x2e1a << 2) + 0xff000000) +#define VI_DNLP_HIST20 ((0x2e1b << 2) + 0xff000000) +#define VI_DNLP_HIST21 ((0x2e1c << 2) + 0xff000000) +#define VI_DNLP_HIST22 ((0x2e1d << 2) + 0xff000000) +#define VI_DNLP_HIST23 ((0x2e1e << 2) + 0xff000000) +#define VI_DNLP_HIST24 ((0x2e1f << 2) + 0xff000000) +#define VI_DNLP_HIST25 ((0x2e20 << 2) + 0xff000000) +#define VI_DNLP_HIST26 ((0x2e21 << 2) + 0xff000000) +#define VI_DNLP_HIST27 ((0x2e22 << 2) + 0xff000000) +#define VI_DNLP_HIST28 ((0x2e23 << 2) + 0xff000000) +#define VI_DNLP_HIST29 ((0x2e24 << 2) + 0xff000000) +#define VI_DNLP_HIST30 ((0x2e25 << 2) + 0xff000000) +#define VI_DNLP_HIST31 ((0x2e26 << 2) + 0xff000000) +#define VI_DNLP_HIST32 ((0x2e27 << 2) + 0xff000000) +//Bit 28:16 hist_pic_height active input data window height +//Bit 12:0 hist_pic_width active input data window width +#define VI_HIST_PIC_SIZE ((0x2e28 << 2) + 0xff000000) +//Bit 15:8 hist_pix_white_value: >= this value will be white pixel +//Bit 7:0 hist_pix_black_value: <= this value will be black pixel +#define VI_HIST_BLACK_WHITE_VALUE ((0x2e29 << 2) + 0xff000000) +#define VI_HIST_GCLK_CTRL ((0x2e2a << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vi_hist_spl_reg.h +// +// +// Reading file: mcdi_regs.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: MCDI_VCBUS_BASE = 0x2f +// ----------------------------------------------- +////=================================================================//// +//// memc di core 0 +////=================================================================//// +#define MCDI_HV_SIZEIN ((0x2f00 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_mcdi_hsize image horizontal size (number of cols) default=1024 +//Bit 15:13, reserved +//Bit 12: 0, reg_mcdi_vsize image vertical size (number of rows) default=1024 +#define MCDI_HV_BLKSIZEIN ((0x2f01 << 2) + 0xff000000) +//Bit 31, reg_mcdi_vrev default = 0 +//Bit 30, reg_mcdi_hrev default = 0 +//Bit 29:28, reserved +//Bit 27:16, reg_mcdi_blkhsize image horizontal blk size (number of cols) default=1024 +//Bit 15:13, reserved +//Bit 11: 0, reg_mcdi_blkvsize image vertical blk size (number of rows) default=1024 +#define MCDI_BLKTOTAL ((0x2f02 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23: 0, reg_mcdi_blktotal +#define MCDI_MOTINEN ((0x2f03 << 2) + 0xff000000) +//Bit 31: 2, reserved +//Bit 1, reg_mcdi_motionrefen. enable motion refinement of MA, default = 1 +//Bit 0, reg_mcdi_motionparadoxen. enable motion paradox detection, default = 1 +#define MCDI_CTRL_MODE ((0x2f04 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:26, reg_mcdi_lmvlocken 0:disable, 1: use max Lmv, 2: use no-zero Lmv, lmv lock enable mode, default = 2 +//Bit 25, reg_mcdi_reldetrptchken +// 0: unable; 1: enable, enable repeat pattern check (not repeat mv detection) in rel det part, default = 1 +//Bit 24, reg_mcdi_reldetgmvpd22chken +// 0: unable; 1: enable, enable pull-down 22 mode check in gmv lock mode for rel det, default = 1 +//Bit 23, reg_mcdi_pd22chken +// 0: unable; 1: enable, enable pull-down 22 mode check (lock) function, default = 1 +//Bit 22, reg_mcdi_reldetlpfen +// 0: unable; 1: enable, enable det value lpf, default = 1 +//Bit 21, reg_mcdi_reldetlmvpd22chken +// 0: unable; 1: enable, enable pull-down 22 mode check in lmv lock mode for rel det, default = 1 +//Bit 20, reg_mcdi_reldetlmvdifchken +// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1 +//Bit 19, reg_mcdi_reldetgmvdifchken +// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1 +//Bit 18, reg_mcdi_reldetpd22chken +// 0: unable; 1: enable, enable pull-down 22 mode check for rel det refinement, default = 1 +//Bit 17, reg_mcdi_reldetfrqchken +// 0: unable; 1: enable, enable mv frequency check in rel det, default = 1 +//Bit 16, reg_mcdi_qmeen +// 0: unable; 1: enable, enable quarter motion estimation, defautl = 1 +//Bit 15, reg_mcdi_refrptmven +// 0: unable; 1: enable, use repeat mv in refinement, default = 1 +//Bit 14, reg_mcdi_refgmven +// 0: unable; 1: enable, use gmv in refinement, default = 1 +//Bit 13, reg_mcdi_reflmven +// 0: unable; 1: enable, use lmvs in refinement, default = 1 +//Bit 12, reg_mcdi_refnmven +// 0: unable; 1: enable, use neighoring mvs in refinement, default = 1 +//Bit 11, reserved +//Bit 10, reg_mcdi_referrfrqchken +// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1 +//Bit 9, reg_mcdi_refen +// 0: unable; 1: enable, enable mv refinement, default = 1 +//Bit 8, reg_mcdi_horlineen +// 0: unable; 1: enable,enable horizontal lines detection by sad map, default = 1 +//Bit 7, reg_mcdi_highvertfrqdeten +// 0: unable; 1: enable, enable high vertical frequency pattern detection, default = 1 +//Bit 6, reg_mcdi_gmvlocken +// 0: unable; 1: enable, enable gmv lock mode, default = 1 +//Bit 5, reg_mcdi_rptmven +// 0: unable; 1: enable, enable repeat pattern detection, default = 1 +//Bit 4, reg_mcdi_gmven +// 0: unable; 1: enable, enable global motion estimation, default = 1 +//Bit 3, reg_mcdi_lmven +// 0: unable; 1: enable, enable line mv estimation for hme, default = 1 +//Bit 2, reg_mcdi_chkedgeen +// 0: unable; 1: enable, enable check edge function, default = 1 +//Bit 1, reg_mcdi_txtdeten +// 0: unable; 1: enable, enable texture detection, default = 1 +//Bit 0, reg_mcdi_memcen +// 0: unable; 1: enable, enable of memc di, default = 1 +#define MCDI_UNI_MVDST ((0x2f05 << 2) + 0xff000000) +//Bit 31:20, reserved +//Bit 19:17, reg_mcdi_unimvdstabsseg0 segment0 for uni-mv abs, default = 1 +//Bit 16:12, reg_mcdi_unimvdstabsseg1 segment1 for uni-mv abs, default = 15 +//Bit 11: 8, reg_mcdi_unimvdstabsdifgain0 2/2, gain0 of uni-mv abs dif for segment0, normalized 2 to '1', default = 2 +//Bit 7: 5, reg_mcdi_unimvdstabsdifgain1 2/2, gain1 of uni-mv abs dif for segment1, normalized 2 to '1', default = 2 +//Bit 4: 2, reg_mcdi_unimvdstabsdifgain2 2/2, gain2 of uni-mv abs dif beyond segment1, normalized 2 to '1', default = 2 +//Bit 1: 0, reg_mcdi_unimvdstsgnshft shift for neighboring distance of uni-mv, default = 0 +#define MCDI_BI_MVDST ((0x2f06 << 2) + 0xff000000) +//Bit 31:20, reserved +//Bit 19:17, reg_mcdi_bimvdstabsseg0 segment0 for bi-mv abs, default = 1 +//Bit 16:12, reg_mcdi_bimvdstabsseg1 segment1 for bi-mv abs, default = 9 +//Bit 11: 8, reg_mcdi_bimvdstabsdifgain0 6/2, gain0 of bi-mv abs dif for segment0, normalized 2 to '1', default = 6 +//Bit 7: 5, reg_mcdi_bimvdstabsdifgain1 3/2, gain1 of bi-mvabs dif for segment1, normalized 2 to '1', default = 3 +//Bit 4: 2, reg_mcdi_bimvdstabsdifgain2 2/2, gain2 of bi-mvabs dif beyond segment1, normalized 2 to '1', default = 2 +//Bit 1: 0, reg_mcdi_bimvdstsgnshft shift for neighboring distance of bi-mv, default = 0 +#define MCDI_SAD_GAIN ((0x2f07 << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18:17, reg_mcdi_unisadcorepxlgain uni-sad core pixels gain, default = 3 +//Bit 16, reg_mcdi_unisadcorepxlnormen enable uni-sad core pixels normalization, default = 0 +//Bit 15:11, reserved +//Bit 10: 9, reg_mcdi_bisadcorepxlgain bi-sad core pixels gain, default = 3 +//Bit 8, reg_mcdi_bisadcorepxlnormen enable bi-sad core pixels normalization, default = 1 +//Bit 7: 3, reserved +//Bit 2: 1, reg_mcdi_biqsadcorepxlgain bi-qsad core pixels gain, default = 3 +//Bit 0, reg_mcdi_biqsadcorepxlnormen enable bi-qsad core pixels normalization, default = 1 +#define MCDI_TXT_THD ((0x2f08 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_mcdi_txtminmaxdifthd, min max dif threshold (>=) for texture detection, default = 24 +//Bit 15: 8, reg_mcdi_txtmeandifthd, mean dif threshold (<) for texture detection, default = 9 +//Bit 7: 3, reserved +//Bit 2: 0, reg_mcdi_txtdetthd, texture detecting threshold, 0~4, default = 2 +#define MCDI_FLT_MODESEL ((0x2f09 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28, reg_mcdi_flthorlineselmode mode for horizontal line detecting flat calculation, default = 1, same as below +//Bit 27 reserved +//Bit 26:24, reg_mcdi_fltgmvselmode mode for gmv flat calculation, default = 4, same as below +//Bit 23, reserved +//Bit 22:20, reg_mcdi_fltsadselmode mode for sad flat calculation, default = 2, same as below +//Bit 19, reserved +//Bit 18:16, reg_mcdi_fltbadwselmode mode for badw flat calculation, default = 3, same as below +//Bit 15, reserved +//Bit 14:12, reg_mcdi_fltrptmvselmode mode for repeat mv flat calculation, default = 4, same as below +//Bit 11, reserved +//Bit 10: 8, reg_mcdi_fltbadrelselmode mode for bad rel flat calculation, default = 4, same as below +//Bit 7, reserved +//Bit 6: 4, reg_mcdi_fltcolcfdselmode mode for col cfd flat calculation, default = 2, same as below +//Bit 3, reserved +//Bit 2: 0, reg_mcdi_fltpd22chkselmode mode for pd22 check flat calculation, default = 2, # 0:cur dif h, 1: cur dif v, 2: pre dif h, 3: pre dif v, 4: cur flt, 5: pre flt, 6: cur+pre, 7: max all(cur,pre) +#define MCDI_CHK_EDGE_THD ((0x2f0a << 2) + 0xff000000) +//Bit 23:28, reserved. +//Bit 27:24, reg_mcdi_chkedgedifsadthd. thd (<=) for sad dif check, 0~8, default = 1 +//Bit 23:16, reserved. +//Bit 15:12, reg_mcdi_chkedgemaxedgethd. max drt of edge, default = 15 +//Bit 11: 8, reg_mcdi_chkedgeminedgethd. min drt of edge, default = 2 +//Bit 7, reserved. +//Bit 6: 0, reg_mcdi_chkedgevdifthd. thd for vertical dif in check edge, default = 14 +#define MCDI_CHK_EDGE_GAIN_OFFST ((0x2f0b << 2) + 0xff000000) +//Bit 31:24, reserved. +//Bit 23:20, reg_mcdi_chkedgedifthd1. thd1 for edge dif check (<=), default = 4 +//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15 +//Bit :15, reserved. +//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24 +//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1 +//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4 +//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, defautl = 1 +//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, defautl = 0 +//Bit 0, reg_mcdi_chkedgeedgelpf. edge lpf mode, 0:[0,2,4,2,0], 1:[1,2,2,2,1], default = 0 +#define MCDI_LMV_RT ((0x2f0c << 2) + 0xff000000) +//BIt 31:15, reserved +//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg +//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calucluation, default = 1 +// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2); +//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0 +//Bit 8, reserved +//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5 +//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5 +#define MCDI_LMV_GAINTHD ((0x2f0d << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_lmvvxmaxgain max gain of lmv weight, default = 96 +//Bit 23, reserved +//Bit 22:20, reg_mcdi_lmvdifthd0 dif threshold 0 (<) for small lmv, default = 1 +//Bit 19:17, reg_mcdi_lmvdifthd1 dif threshold 1 (<) for median lmv, default = 2 +//Bit 16:14, reg_mcdi_lmvdifthd2 dif threshold 2 (<) for large lmv, default = 3 +//Bit 13: 8, reg_mcdi_lmvnumlmt least/limit number of (total number - max0), default = 20 +//Bit 7: 0, reg_mcdi_lmvfltthd flt cnt thd (<) for lmv, default = 9 +#define MCDI_RPTMV_THD0 ((0x2f0e << 2) + 0xff000000) +//Bit 31:25, reg_mcdi_rptmvslpthd2 slope thd (>=) between i and i+3/i-3 (i+4/i-4), default = 64 +//Bit 24:20, reg_mcdi_rptmvslpthd1 slope thd (>=) between i and i+2/i-2, default = 4 +//Bit 19:10, reg_mcdi_rptmvampthd2 amplitude thd (>=) between max and min, when count cycles, default = 300 +//Bit 9: 0, reg_mcdi_rptmvampthd1 amplitude thd (>=) between average of max and min, default = 400 +#define MCDI_RPTMV_THD1 ((0x2f0f << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:25, reg_mcdi_rptmvcyccntthd thd (>=) of total cycles count, default = 2 +//Bit 24:21, reg_mcdi_rptmvcycdifthd dif thd (<) of cycles length, default = 3 +//Bit 20:18, reg_mcdi_rptmvcycvldthd thd (>) of valid cycles number, default = 1 +//Bit 17:15, reg_mcdi_rptmvhalfcycminthd min length thd (>=) of half cycle, default = 2 +//Bit 14:11, reg_mcdi_rptmvhalfcycdifthd neighboring half cycle length dif thd (<), default = 5 +//Bit 10: 8, reg_mcdi_rptmvminmaxcntthd least number of valid max and min, default = 2 +//Bit 7: 5, reg_mcdi_rptmvcycminthd min length thd (>=) of cycles, default = 2 +//Bit 4: 0, reg_mcdi_rptmvcycmaxthd max length thd (<) of cycles, default = 17 +#define MCDI_RPTMV_THD2 ((0x2f10 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_mcdi_rptmvhdifthd0 higher hdif thd (>=) (vertical edge) for rpt detection, default = 8 +//Bit 15: 8, reg_mcdi_rptmvhdifthd1 hdif thd (>=) (slope edge) for rpt detection, default = 4 +//Bit 7: 0, reg_mcdi_rptmvvdifthd vdif thd (>=) (slope edge) for rpt detection, default = 1 +#define MCDI_RPTMV_SAD ((0x2f11 << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25:16, reg_mcdi_rptmvsaddifthdgain 7x3x(16/16), gain for sad dif thd in rpt mv detection, 0~672, normalized 16 as '1', default = 336 +//Bit 15:10, reserved +//Bit 9: 0, reg_mcdi_rptmvsaddifthdoffst offset for sad dif thd in rpt mv detection, -512~511, default = 16 +#define MCDI_RPTMV_FLG ((0x2f12 << 2) + 0xff000000) +//Bit 31:18, reserved +//Bit 17:16, reg_mcdi_rptmvmode select mode of mvs for repeat motion estimation, 0: hmv, 1: qmv/2, 2 or 3: qmv/4, default = 2 +//Bit 15: 8, reg_mcdi_rptmvflgcntthd thd (>=) of min count number for rptmv of whole field, for rptmv estimation, default = 64 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_rptmvflgcntrt 4/32, ratio for repeat mv flag count, normalized 32 as '1', set 31 to 32, +#define MCDI_RPTMV_GAIN ((0x2f13 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_rptmvlftgain up repeat mv gain for hme, default = 96 +//Bit 23:16, reg_mcdi_rptmvuplftgain up left repeat mv gain for hme, default = 32 +//Bit 15: 8, reg_mcdi_rptmvupgain up repeat mv gain for hme, default = 64 +//Bit 7: 0, reg_mcdi_rptmvuprightgain up right repeat mv gain for hme, default = 32 +#define MCDI_GMV_RT ((0x2f14 << 2) + 0xff000000) +//Bit 31, reserved +//Bit 30:24, reg_mcdi_gmvmtnrt0 ratio 0 for motion senario, set 127 to 128, normalized 128 as '1', default =32 +//Bit 23, reserved +//Bit 22:16, reg_mcdi_gmvmtnrt1 ratio 1 for motion senario, set 127 to 128, normalized 128 as '1', default = 56 +//Bit 15, reserved +//Bit 14: 8, reg_mcdi_gmvstlrt0 ratio 0 for still senario, set 127 to 128, normalized 128 as '1', default = 56 +//Bit 7, reserved +//Bit 6: 0, reg_mcdi_gmvstlrt1 ratio 1 for still senario, set 127 to 128, normalized 128 as '1', default = 80 +#define MCDI_GMV_GAIN ((0x2f15 << 2) + 0xff000000) +//Bit 31:25, reg_mcdi_gmvzeromvlockrt0 ratio 0 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 100 +//Bit 24:18, reg_mcdi_gmvzeromvlockrt1 ratio 1 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 112 +//Bit 17:16, reg_mcdi_gmvvalidmode valid mode for gmv calc., 10b: use flt, 01b: use hori flg, default = 3 +//Bit 15: 8, reg_mcdi_gmvvxgain gmv's vx gain when gmv locked for hme, default = 0 +//Bit 7: 0, reg_mcdi_gmvfltthd flat thd (<) for gmv calc. default = 3 +#define MCDI_HOR_SADOFST ((0x2f16 << 2) + 0xff000000) +//Bit 31:25, reserved +//Bit 24:16, reg_mcdi_horsaddifthdgain 21*1/8, gain/divisor for sad dif threshold in hor line detection, normalized 8 as '1', default = 21 +//Bit 15: 8, reg_mcdi_horsaddifthdoffst offset for sad dif threshold in hor line detection, -128~127, default = 0 +//Bit 7: 0, reg_mcdi_horvdifthd threshold (>=) of vertical dif of next block for horizontal line detection, default = 24 +#define MCDI_REF_MV_NUM ((0x2f17 << 2) + 0xff000000) +//Bit 31: 2, reserved +//Bit 1: 0, reg_mcdi_refmcmode. motion compensated mode used in refinement, 0: pre, 1: next, 2: (pre+next)/2, default = 0 +#define MCDI_REF_BADW_THD_GAIN ((0x2f18 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:24, reg_mcdi_refbadwcnt2gain. gain for badwv count num==3, default = 6 +//Bit 23:20, reg_mcdi_refbadwcnt1gain. gain for badwv count num==2, default = 3 +//Bit 19:16, reg_mcdi_refbadwcnt0gain. gain for badwv count num==1, default = 1 +//Bit 15:12, reg_mcdi_refbadwthd3. threshold 3 for detect badweave with largest average luma, default = 4 +//Bit 11: 8, reg_mcdi_refbadwthd2. threshold 2 for detect badweave with third smallest average luma, default = 3 +//Bit 7: 4, reg_mcdi_refbadwthd1. threshold 1 for detect badweave with second smallest average luma, default = 2 +//Bit 3: 0, reg_mcdi_refbadwthd0. threshold 0 for detect badweave with smallest average luma, default = 1 +#define MCDI_REF_BADW_SUM_GAIN ((0x2f19 << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12: 8, reg_mcdi_refbadwsumgain0. sum gain for r channel, 0~16, default = 8 +//Bit 7: 5, reserved +//Bit 4, reg_mcdi_refbadwcalcmode. mode for badw calculation, 0:sum, 1:max, default = 0 +//Bit 3: 0, reserved +#define MCDI_REF_BS_THD_GAIN ((0x2f1a << 2) + 0xff000000) +//Bit 31:28, reg_mcdi_refbsudgain1. up & down block stregth gain1, normalized to 8 as '1', default = 2 +//Bit 27:24, reg_mcdi_refbsudgain0. up & down block stregth gain0, normalized to 8 as '1', default = 4 +//Bit 23:19, reserved +//Bit 18:16, reg_mcdi_refbslftgain. left block strength gain, default = 0 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_refbsthd1. threshold 1 for detect block stregth in refinment, default = 16 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_refbsthd0. threshold 0 for detect block stregth in refinment, default = 8 +#define MCDI_REF_ERR_GAIN0 ((0x2f1b << 2) + 0xff000000) +//Bit 31, reserved +//Bit 30:24, reg_mcdi_referrnbrdstgain. neighoring mv distances gain for err calc. in ref, normalized to 8 as '1', default = 48 +//Bit 23:20, reserved +//Bit 19:16, reg_mcdi_referrbsgain. bs gain for err calc. in ref, normalized to 8 as '1', default = 4 +//Bit 15, reserved +//Bit 14: 8, reg_mcdi_referrbadwgain. badw gain for err calc. in ref, normalized to 8 as '1', default = 64 +//Bit 7: 4, reserved +//Bit 3: 0, reg_mcdi_referrsadgain. sad gain for err calc. in ref, normalized to 8 as '1', default = 4 +#define MCDI_REF_ERR_GAIN1 ((0x2f1c << 2) + 0xff000000) +//Bit 31:20, reserved +//Bit 19:16, reg_mcdi_referrchkedgegain. check edge gain for err calc. in ref, normalized to 8 as '1', default = 4 +//Bit 15:12, reserved +//Bit 11: 8, reg_mcdi_referrlmvgain. (locked) lmv gain for err calc. in ref, normalized to 8 as '1', default = 0 +//Bit 7: 4, reserved +//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0 +#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10 +//Bit 23:21, reserved +//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31 +//Bit 15, reserved +//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3 +//Bit 11, reserved +//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2 +//Bit 7, reserved +//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1 +//Bit 3: 0, reserved +#define MCDI_QME_LPF_MSK ((0x2f1e << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:24, reg_mcdi_qmechkedgelpfmsk0. lpf mask0 for chk edge in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7 +//Bit 23:20, reserved +//Bit 19:16, reg_mcdi_qmebslpfmsk0. lpf mask0 for bs in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7 +//Bit 15:12, reserved +//Bit 11: 8, reg_mcdi_qmebadwlpfmsk0. lpf mask0 for badw in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7 +//Bit 7: 4, reserved +//Bit 3: 0, reg_mcdi_qmesadlpfmsk0. lpf mask0 for sad in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7 +#define MCDI_REL_DIF_THD_02 ((0x2f1f << 2) + 0xff000000) +//Bit 31:24, reserved. +//Bit 23:16, reg_mcdi_reldifthd2. thd (<) for (hdif+vdif), default = 9 +//Bit 15: 8, reg_mcdi_reldifthd1. thd (<) for (vdif), default = 5 +//Bit 7: 0, reg_mcdi_reldifthd0. thd (>=) for (hdif-vdif), default = 48 +#define MCDI_REL_DIF_THD_34 ((0x2f20 << 2) + 0xff000000) +//Bit 31:16, reserved. +//Bit 15: 8, reg_mcdi_reldifthd4. thd (<) for (hdif), default = 255 +//Bit 7: 0, reg_mcdi_reldifthd3. thd (>=) for (vdif-hdif), default = 48 +#define MCDI_REL_BADW_GAIN_OFFST_01 ((0x2f21 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_relbadwoffst1. offset for badw adj, for flat block, -128~127, default = 0 +//Bit 23:16, reg_mcdi_relbadwgain1. gain for badw adj, for flat block, default = 128 +//Bit 15: 8, reg_mcdi_relbadwoffst0. offset for badw adj, for vertical block, -128~127, default = 0 +//Bit 7: 0, reg_mcdi_relbadwgain0. gain for badw adj, for vertical block, default = 160 +#define MCDI_REL_BADW_GAIN_OFFST_23 ((0x2f22 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_relbadwoffst3. offset for badw adj, for other block, -128~127, default = 0 +//Bit 23:16, reg_mcdi_relbadwgain3. gain for badw adj, for other block, default = 48 +//Bit 15: 8, reg_mcdi_relbadwoffst2. offset for badw adj, for horizontal block, -128~127, default = 0 +//Bit 7: 0, reg_mcdi_relbadwgain2. gain for badw adj, for horizontal block, default = 48 +#define MCDI_REL_BADW_THD_GAIN_OFFST ((0x2f23 << 2) + 0xff000000) +//Bit 31:23, reserved. +//Bit 22:16, reg_mcdi_relbadwoffst. offset for badw thd adj, -64~63, default = 0 +//Bit 15: 8, reserved. +//Bit 7: 0, reg_mcdi_relbadwthdgain. gain0 for badw thd adj, normalized to 16 as '1', default = 16 +#define MCDI_REL_BADW_THD_MIN_MAX ((0x2f24 << 2) + 0xff000000) +//Bit 31:18, reserved. +//Bit 17: 8, reg_mcdi_relbadwthdmax. max for badw thd adj, default = 256 +//Bit 7: 0, reg_mcdi_relbadwthdmin. min for badw thd adj, default = 16 +#define MCDI_REL_SAD_GAIN_OFFST_01 ((0x2f25 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_relsadoffst1. offset for sad adj, for flat block, -128~127, default = 0 +//Bit 23:20, reserved. +//Bit 19:16, reg_mcdi_relsadgain1. gain for sad adj, for flat block, normalized to 8 as '1', default = 8 +//Bit 15: 8, reg_mcdi_relsadoffst0. offset for sad adj, for vertical block, -128~127, default = 0 +//Bit 7: 4, reserved. +//Bit 3: 0, reg_mcdi_relsadgain0. gain for sad adj, for vertical block, normalized to 8 as '1', default = 6 +#define MCDI_REL_SAD_GAIN_OFFST_23 ((0x2f26 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_relsadoffst3. offset for sad adj, for other block, -128~127, default = 0 +//Bit 23:20, reserved. +//Bit 19:16, reg_mcdi_relsadgain3. gain for sad adj, for other block, normalized to 8 as '1', default = 8 +//Bit 15: 8, reg_mcdi_relsadoffst2. offset for sad adj, for horizontal block, -128~127, default = 0 +//Bit 7: 4, reserved. +//Bit 3: 0, reg_mcdi_relsadgain2. gain for sad adj, for horizontal block, normalized to 8 as '1', default = 12 +#define MCDI_REL_SAD_THD_GAIN_OFFST ((0x2f27 << 2) + 0xff000000) +//Bit 31:24, reserved. +//Bit 23:16, reg_mcdi_relsadoffst. offset for sad thd adj, -128~127, default = 0 +//Bit 15:10, reserved. +//Bit 9: 0, reg_mcdi_relsadthdgain. gain for sad thd adj, 21*2/16, normalized to 16 as '1', default = 42 +#define MCDI_REL_SAD_THD_MIN_MAX ((0x2f28 << 2) + 0xff000000) +//Bit 31:27, reserved. +//Bit 26:16, reg_mcdi_relsadthdmax. max for sad thd adj, 21*32, default = 672 +//Bit 15: 9, reserved. +//Bit 8: 0, reg_mcdi_relsadthdmin. min for sad thd adj, 21*2, default = 42 +#define MCDI_REL_DET_GAIN_00 ((0x2f29 << 2) + 0xff000000) +//Bit 31:21, reserved. +//Bit 20:16, reg_mcdi_reldetbsgain0. gain0 (gmv locked) for bs, for det. calc. normalized to 16 as '1', default = 8 +//Bit 15:14, reserved. +//Bit 13: 8, reg_mcdi_reldetbadwgain0. gain0 (gmv locked) for badw, for det. calc. normalized to 16 as '1', default = 12 +//Bit 7: 5, reserved. +//Bit 4: 0, reg_mcdi_reldetsadgain0. gain0 (gmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8 +#define MCDI_REL_DET_GAIN_01 ((0x2f2a << 2) + 0xff000000) +//Bit 31:14, reserved. +//Bit 12: 8, reg_mcdi_reldetchkedgegain0. gain0 (gmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 2 +//Bit 7, reserved. +//Bit 6: 0, reg_mcdi_reldetnbrdstgain0. gain0 (gmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24 +#define MCDI_REL_DET_GAIN_10 ((0x2f2b << 2) + 0xff000000) +//Bit 31:21, reserved. +//Bit 20:16, reg_mcdi_reldetbsgain1. gain1 (lmv locked) for bs, for det. calc. normalized to 16 as '1', default = 0 +//Bit 15:14, reserved. +//Bit 13: 8, reg_mcdi_reldetbadwgain1. gain1 (lmv locked) for badw, for det. calc. normalized to 16 as '1', default = 8 +//Bit 7: 5, reserved. +//Bit 4: 0, reg_mcdi_reldetsadgain1. gain1 (lmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8 +#define MCDI_REL_DET_GAIN_11 ((0x2f2c << 2) + 0xff000000) +//Bit 31:14, reserved. +//Bit 12: 8, reg_mcdi_reldetchkedgegain1. gain1 (lmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 0 +//Bit 7, reserved. +//Bit 6: 0, reg_mcdi_reldetnbrdstgain1. gain1 (lmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24 +#define MCDI_REL_DET_GAIN_20 ((0x2f2d << 2) + 0xff000000) +//Bit 31:21, reserved. +//Bit 20:16, reg_mcdi_reldetbsgain2. gain2 (no locked) for bs, for det. calc. normalized to 16 as '1', default = 12 +//Bit 15:14, reserved. +//Bit 13: 8, reg_mcdi_reldetbadwgain2. gain2 (no locked) for badw, for det. calc. normalized to 16 as '1', default = 32 +//Bit 7: 5, reserved. +//Bit 4: 0, reg_mcdi_reldetsadgain2. gain2 (no locked) for qsad, for det. calc. normalized to 16 as '1', default = 16 +#define MCDI_REL_DET_GAIN_21 ((0x2f2e << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25:16, reg_mcdi_reldetoffst. offset for rel calculation, for det. calc. -512~511, default = 0 +//Bit 15:14, reserved. +//Bit 12: 8, reg_mcdi_reldetchkedgegain2. gain2 (no locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 10 +//Bit 7, reserved. +//Bit 6: 0, reg_mcdi_reldetnbrdstgain2. gain2 (no locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 32 +#define MCDI_REL_DET_GMV_DIF_CHK ((0x2f2f << 2) + 0xff000000) +//Bit 31:24, reserved. +//Bit 23:16, reg_mcdi_reldetgmvfltthd. flat thd (>=) for gmv lock decision, default = 0 +//Bit 15, reserved. +//Bit 14:12, reg_mcdi_reldetgmvdifthd. dif thd (>=) for current mv different from gmv for gmv dif check, actually used in Lmv lock check, default = 3 +//Bit 11, reserved. +//Bit 10: 8, reg_mcdi_reldetgmvdifmin. min mv dif for gmv dif check, default = 1, note: dif between reg_mcdi_rel_det_gmv_dif_max and reg_mcdi_rel_det_gmv_dif_min should be; 0,1,3,7, not work for others +//Bit 7: 4, reg_mcdi_reldetgmvdifmax. max mv dif for gmv dif check, default = 4 +//Bit 3: 1, reserved +//Bit 0, reg_mcdi_reldetgmvdifmvmode. mv mode used for gmv dif check, 0: use refmv, 1: use qmv, default = 0 +#define MCDI_REL_DET_LMV_DIF_CHK ((0x2f30 << 2) + 0xff000000) +//Bit 31:24, reserved. +//Bit 23:16, reg_mcdi_reldetlmvfltthd. flat thd (>=) for lmv lock decision, default = 12 +//Bit 15:14, reserved. +//Bit 13:12, reg_mcdi_reldetlmvlockchkmode. lmv lock check mode, 0:cur Lmv, 1: cur & (last | next), 2: last & cur & next Lmv, default = 1 +//Bit 11, reserved. +//Bit 10: 8, reg_mcdi_reldetlmvdifmin. min mv dif for lmv dif check, default = 1, note: dif between reg_mcdi_rel_det_lmv_dif_max and reg_mcdi_rel_det_lmv_dif_min should be; 0,1,3,7, not work for others +//Bit 7: 4, reg_mcdi_reldetlmvdifmax. max mv dif for lmv dif check, default = 4 +//Bit 3: 1, reserved +//Bit 0, reg_mcdi_reldetlmvdifmvmode. mv mode used for lmv dif check, 0: use refmv, 1: use qmv, default = 0 +#define MCDI_REL_DET_FRQ_CHK ((0x2f31 << 2) + 0xff000000) +//Bit 31:12, reserved. +//Bit 11: 8, reg_mcdi_reldetfrqgain. gain for frequency check, normalized to 4 as '1', default = 10 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_reldetfrqmax. max value for frequency check, default = 31 +#define MCDI_REL_DET_PD22_CHK ((0x2f32 << 2) + 0xff000000) +//Bit 31:18, reserved. +//Bit 17: 8, reg_mcdi_reldetpd22chkoffst. offset for pd22 check happened, default = 512 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_reldetpd22chkgain. gain for pd22 check happened, normalized to 8 as '1', default = 12 +#define MCDI_REL_DET_RPT_CHK_ROW ((0x2f33 << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:16, reg_mcdi_reldetrptchkendrow. end row (<) number for repeat check, default = 2047 +//Bit 15:11, reserved +//Bit 10: 0, reg_mcdi_reldetrptchkstartrow. start row (>=) number for repeat check, default = 0 +#define MCDI_REL_DET_RPT_CHK_GAIN_QMV ((0x2f34 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_mcdi_reldetrptchkqmvmax. max thd (<) of abs qmv for repeat check, default = 15, note that quarter mv's range is -63~63 +//Bit 23:22, reserved +//Bit 21:16, reg_mcdi_reldetrptchkqmvmin. min thd (>=) of abs qmv for repeat check, default = 10, note that quarter mv's range is -63~63 +//Bit 15, reserved/ +//Bit 14: 4, reg_mcdi_reldetrptchkoffst. offset for repeat check, default = 512 +//Bit 3: 0, reg_mcdi_reldetrptchkgain. gain for repeat check, normalized to 8 as '1', default = 4 +#define MCDI_REL_DET_RPT_CHK_THD_0 ((0x2f35 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_mcdi_reldetrptchkzerosadthd. zero sad thd (<) for repeat check, default = 255 +//Bit 15:14, reserved. +//Bit 13: 8, reg_mcdi_reldetrptchkzerobadwthd. zero badw thd (>=) for repeat check, default = 16 +//Bit 7: 4, reserved +//Bit 3: 0, reg_mcdi_reldetrptchkfrqdifthd. frequency dif thd (<) for repeat check, 0~10, default = 5 +#define MCDI_REL_DET_RPT_CHK_THD_1 ((0x2f36 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_mcdi_reldetrptchkvdifthd. vertical dif thd (<) for repeat check, default = 16 +//Bit 7: 0, reg_mcdi_reldetrptchkhdifthd. horizontal dif thd (>=) for repeat check, default = 16 +#define MCDI_REL_DET_LPF_DIF_THD ((0x2f37 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_reldetlpfdifthd3. hdif thd (<) for lpf selection of horizontal block, default = 9 +//Bit 23:16, reg_mcdi_reldetlpfdifthd2. vdif-hdif thd (>=) for lpf selection of horizontal block, default = 48 +//Bit 15: 8, reg_mcdi_reldetlpfdifthd1. vdif thd (<) for lpf selection of vertical block, default = 9 +//Bit 7: 0, reg_mcdi_reldetlpfdifthd0. hdif-vdif thd (>=) for lpf selection of vertical block, default = 48 +#define MCDI_REL_DET_LPF_MSK_00_03 ((0x2f38 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:24, reg_mcdi_reldetlpfmsk03. det lpf mask03 for gmv/lmv locked mode, 0~16, default = 1 +//Bit 23:21, reserved +//Bit 20:16, reg_mcdi_reldetlpfmsk02. det lpf mask02 for gmv/lmv locked mode, 0~16, default = 1 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_reldetlpfmsk01. det lpf mask01 for gmv/lmv locked mode, 0~16, default = 5 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_reldetlpfmsk00. det lpf mask00 for gmv/lmv locked mode, 0~16, default = 8 +#define MCDI_REL_DET_LPF_MSK_04_12 ((0x2f39 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:24, reg_mcdi_reldetlpfmsk12. det lpf mask12 for vertical blocks, 0~16, default = 0 +//Bit 23:21, reserved +//Bit 20:16, reg_mcdi_reldetlpfmsk11. det lpf mask11 for vertical blocks, 0~16, default = 0 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_reldetlpfmsk10. det lpf mask10 for vertical blocks, 0~16, default = 16 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_reldetlpfmsk04. det lpf mask04 for gmv/lmv locked mode, 0~16, default = 1 +#define MCDI_REL_DET_LPF_MSK_13_21 ((0x2f3a << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:24, reg_mcdi_reldetlpfmsk21. det lpf mask21 for horizontal blocks, 0~16, default = 6 +//Bit 23:21, reserved +//Bit 20:16, reg_mcdi_reldetlpfmsk20. det lpf mask20 for horizontal blocks, 0~16, default = 8 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_reldetlpfmsk14. det lpf mask14 for vertical blocks, 0~16, default = 0 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_reldetlpfmsk13. det lpf mask13 for vertical blocks, 0~16, default = 0 +#define MCDI_REL_DET_LPF_MSK_22_30 ((0x2f3b << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:24, reg_mcdi_reldetlpfmsk30. det lpf mask30 for other blocks, 0~16, default = 16 +//Bit 23:21, reserved +//Bit 20:16, reg_mcdi_reldetlpfmsk24. det lpf mask24 for horizontal blocks, 0~16, default = 1 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_reldetlpfmsk23. det lpf mask23 for horizontal blocks, 0~16, default = 0 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_reldetlpfmsk22. det lpf mask22 for horizontal blocks, 0~16, default = 1 +#define MCDI_REL_DET_LPF_MSK_31_34 ((0x2f3c << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:24, reg_mcdi_reldetlpfmsk34. det lpf mask34 for other blocks, 0~16, default = 0 +//Bit 23:21, reserved +//Bit 20:16, reg_mcdi_reldetlpfmsk33. det lpf mask33 for other blocks, 0~16, default = 0 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_reldetlpfmsk32. det lpf mask32 for other blocks, 0~16, default = 0 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_reldetlpfmsk31. det lpf mask31 for other blocks, 0~16, default = 0 +//Note: there are four group lpf masks from addr 37~3b, each group sum equal to 16. +#define MCDI_REL_DET_MIN ((0x2f3d << 2) + 0xff000000) +//Bit 31: 7, reserved +//Bit 6: 0, reg_mcdi_reldetmin. min of detected value, default = 16 +#define MCDI_REL_DET_LUT_0_3 ((0x2f3e << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_reldetmaplut3. default = 8 +//Bit 23:16, reg_mcdi_reldetmaplut2. default = 4 +//Bit 15: 8, reg_mcdi_reldetmaplut1. default = 2 +//Bit 7: 0, reg_mcdi_reldetmaplut0. default = 0 +#define MCDI_REL_DET_LUT_4_7 ((0x2f3f << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_reldetmaplut7. default = 64 +//Bit 23:16, reg_mcdi_reldetmaplut6. default = 48 +//Bit 15: 8, reg_mcdi_reldetmaplut5. default = 32 +//Bit 7: 0, reg_mcdi_reldetmaplut4. default = 16 +#define MCDI_REL_DET_LUT_8_11 ((0x2f40 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_reldetmaplut11. default = 160 +//Bit 23:16, reg_mcdi_reldetmaplut10. default = 128 +//Bit 15: 8, reg_mcdi_reldetmaplut9. default = 96 +//Bit 7: 0, reg_mcdi_reldetmaplut8. default = 80 +#define MCDI_REL_DET_LUT_12_15 ((0x2f41 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_reldetmaplut15. default = 255 +//Bit 23:16, reg_mcdi_reldetmaplut14. default = 240 +//Bit 15: 8, reg_mcdi_reldetmaplut13. default = 224 +//Bit 7: 0, reg_mcdi_reldetmaplut12. default = 192 +#define MCDI_REL_DET_COL_CFD_THD ((0x2f42 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_reldetcolcfdfltthd. thd for flat smaller than (<) of column cofidence, default = 5 +//Bit 23:16, reg_mcdi_reldetcolcfdthd1. thd for rel larger than (>=) in rel calc. mode col confidence without gmv locking, default = 160 +//Bit 15: 8, reg_mcdi_reldetcolcfdthd0. thd for rel larger than (>=) in rel calc. mode col confidence when gmv locked, default = 100 +//Bit 7: 2, reg_mcdi_reldetcolcfdbadwthd. thd for badw larger than (>=) in qbadw calc. mode of column cofidence, default = 16 +//Bit 1, reserved +//Bit 0, reg_mcdi_reldetcolcfdcalcmode. calc. mode for column cofidence, 0: use rel, 1: use qbadw, default = 0 +#define MCDI_REL_DET_COL_CFD_AVG_LUMA ((0x2f43 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_reldetcolcfdavgmin1. avg luma min1 (>=) for column cofidence, valid between 16~235, default = 235 +//Bit 23:16, reg_mcdi_reldetcolcfdavgmax1. avg luma max1 (<) for column cofidence, valid between 16~235, default = 235 +//Bit 15: 8, reg_mcdi_reldetcolcfdavgmin0. avg luma min0 (>=) for column cofidence, valid between 16~235, default = 16 +//Bit 7: 0, reg_mcdi_reldetcolcfdavgmax0. avg luma max0 (<) for column cofidence, valid between 16~235, default = 21 +#define MCDI_REL_DET_BAD_THD_0 ((0x2f44 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_mcdi_reldetbadsadthd. thd (>=) for bad sad, default = 120 (480/4) +//Bit 7: 6, reserved +//Bit 5: 0, reg_mcdi_reldetbadbadwthd. thd (>=) for bad badw, 0~42, default = 12 +#define MCDI_REL_DET_BAD_THD_1 ((0x2f45 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_mcdi_reldetbadrelfltthd. thd (>=) of flat for bad rel detection, default = 4 +//Bit 15: 8, reg_mcdi_reldetbadrelthd1. thd (>=) for bad rel without gmv/lmv locked, default = 160 +//Bit 7: 0, reg_mcdi_reldetbadrelthd0. thd (>=) for bad rel with gmv/lmv locked, default = 120 +#define MCDI_PD22_CHK_THD ((0x2f46 << 2) + 0xff000000) +//Bit 31:25, reserved +//Bit 24:16, reg_mcdi_pd22chksaddifthd. sad dif thd (>=) for (pd22chksad - qsad) for pd22 check, default = 64 +//Bit 15:14, reserved +//Bit 13: 8, reg_mcdi_pd22chkqmvthd. thd (>=) of abs qmv for pd22 check, default = 2 +//Bit 7: 0, reg_mcdi_pd22chkfltthd. thd (>=) of flat for pd22 check, default = 4 +#define MCDI_PD22_CHK_GAIN_OFFST_0 ((0x2f47 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_pd22chkedgeoffst0. offset0 of pd22chkedge from right film22 phase, -128~127, default = 0 +//Bit 23:21, reserved +//Bit 20:16, reg_mcdi_pd22chkedgegain0. gain0 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16 +//Bit 15:12, reserved +//Bit 11: 8, reg_mcdi_pd22chkbadwoffst0. offset0 of pd22chkbadw from right film22 phase, -8~7, default = 0 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_pd22chkbadwgain0. gain0 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 8 +#define MCDI_PD22_CHK_GAIN_OFFST_1 ((0x2f48 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_pd22chkedgeoffst1. offset1 of pd22chkedge from right film22 phase, -128~127, default = 0 +//Bit 23:21, reserved +//Bit 20:16, reg_mcdi_pd22chkedgegain1. gain1 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16 +//Bit 15:12, reserved +//Bit 11: 8, reg_mcdi_pd22chkbadwoffst1. offset1 of pd22chkbadw from right film22 phase, -8~7, default = 0 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_pd22chkbadwgain1. gain1 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 12 +#define MCDI_LMV_LOCK_CNT_THD_GAIN ((0x2f49 << 2) + 0xff000000) +//Bit 31:20, reserved +//Bit 19:16, reg_mcdi_lmvlockcntmax. max lmv lock count number, default = 6 +//Bit 15:12, reg_mcdi_lmvlockcntoffst. offset for lmv lock count, -8~7, default = 0 +//Bit 11: 8, reg_mcdi_lmvlockcntgain. gain for lmv lock count, normalized 8 as '1', 15 is set to 16, default = 8 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_lmvlockcntthd. lmv count thd (>=) before be locked, 1~31, default = 4 +#define MCDI_LMV_LOCK_ABS_DIF_THD ((0x2f4a << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:24, reg_mcdi_lmvlockdifthd2. lmv dif thd for third part, before locked, default = 1 +//Bit 23, reserved +//Bit 22:20, reg_mcdi_lmvlockdifthd1. lmv dif thd for second part, before locked, default = 1 +//Bit 19, reserved +//Bit 18:16, reg_mcdi_lmvlockdifthd0. lmv dif thd for first part, before locked, default = 1 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_lmvlockabsmax. max abs (<) of lmv to be locked, default = 24 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_lmvlockabsmin. min abs (>=) of lmv to be locked, default = 1 +#define MCDI_LMV_LOCK_ROW ((0x2f4b << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:16, reg_mcdi_lmvlockendrow. end row (<) for lmv lock, default = 2047 +//Bit 15:11, reserved +//Bit 10: 0, reg_mcdi_lmvlockstartrow. start row (>=) for lmv lock, default = 0 +#define MCDI_LMV_LOCK_RT_MODE ((0x2f4c << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:24, reg_mcdi_lmvlockextmode. extend lines for lmv lock check, check how many lines for lmv locking, default = 2 +//Bit 23:16, reg_mcdi_lmvlockfltcntrt. ratio of flt cnt for lock check, normalized 256 as '1', 255 is set to 256, default = 32 +//Bit 15: 8, reg_mcdi_lmvlocklmvcntrt1. ratio when use non-zero lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 48 +//Bit 7: 0, reg_mcdi_lmvlocklmvcntrt0. ratio when use max lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 106 +#define MCDI_GMV_LOCK_CNT_THD_GAIN ((0x2f4d << 2) + 0xff000000) +//Bit 31:20, reserved +//Bit 19:16, reg_mcdi_gmvlockcntmax. max gmv lock count number, default = 6 +//Bit 15:12, reg_mcdi_gmvlockcntoffst. offset for gmv lock count, -8~7, default = 0 +//Bit 11: 8, reg_mcdi_gmvlockcntgain. gain for gmv lock count, normalized 8 as '1', 15 is set to 16, default = 8 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_gmvlockcntthd. gmv count thd (>=) before be locked, 1~31, default = 4 +#define MCDI_GMV_LOCK_ABS_DIF_THD ((0x2f4e << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:24, reg_mcdi_gmvlockdifthd2. gmv dif thd for third part, before locked, default = 3 +//Bit 23, reserved +//Bit 22:20, reg_mcdi_gmvlockdifthd1. gmv dif thd for second part, before locked, default = 2 +//Bit 19, reserved +//Bit 18:16, reg_mcdi_gmvlockdifthd0. gmv dif thd for first part, before locked, default = 1 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_gmvlockabsmax. max abs of gmv to be locked, default = 15 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_gmvlockabsmin. min abs of gmv to be locked, default = 1 +#define MCDI_HIGH_VERT_FRQ_DIF_THD ((0x2f4f << 2) + 0xff000000) +//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifthd. high_vert_frq field average luma dif thd (>=), 3*Blk_Width*Blk_Height, set by software, default = 103680 +#define MCDI_HIGH_VERT_FRQ_DIF_DIF_THD ((0x2f50 << 2) + 0xff000000) +//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifdifthd. high_vert_frq field average luma dif's dif thd (<), 3*Blk_Width*Blk_Height, set by software, default = 103680 +#define MCDI_HIGH_VERT_FRQ_RT_GAIN ((0x2f51 << 2) + 0xff000000) +//Bit 31:20, reserved +//Bit 19:16, reg_mcdi_highvertfrqcntthd. high_vert_frq count thd (>=) before locked, 1~31, default = 4 +//Bit 15: 8, reg_mcdi_highvertfrqbadsadrt. ratio for high_vert_frq bad sad count, normalized 256 as '1', 255 is set to 256, default = 24 +//Bit 7: 0, reg_mcdi_highvertfrqbadbadwrt. ratio for high_vert_frq badw count, normalized 256 as '1', 255 is set to 256, default = 130 +#define MCDI_MOTION_PARADOX_THD ((0x2f52 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:24, reg_mcdi_motionparadoxcntthd. motion paradox count thd (>=) before locked, 1~31, default = 4 +//Bit 23:22, reserved +//Bit 21:16, reg_mcdi_motionparadoxgmvthd. abs gmv thd (<) of motion paradox, 0~32, note that 32 means invalid gmv, be careful, default = 32 +//Bit 15: 0, reserved +#define MCDI_MOTION_PARADOX_RT ((0x2f53 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_mcdi_motionparadoxbadsadrt. ratio for field bad sad count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 24 +//Bit 15: 8, reg_mcdi_motionparadoxbadrelrt. ratio for field bad reliabilty count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 120 +//Bit 7: 0, reg_mcdi_motionparadoxmtnrt. ratio for field motion count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 218 +#define MCDI_MOTION_REF_THD ((0x2f54 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:20, reg_mcdi_motionrefoffst. motion ref additive offset, default = 15 +//Bit 19:16, reg_mcdi_motionrefgain. motion ref gain, normalized 8 as '1', default = 8 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_motionrefrptmvthd. abs thd (>=) of rpt mv (0~31, 32 means invalid) for motion ref, default = 1 +//Bit 7: 2, reg_mcdi_motionrefqmvthd. min thd (>=) of abs qmv for motion ref, note that quarter mv's range is -63~63, default = 2 +//Bit 1: 0, reg_mcdi_motionreflpfmode. Mv and (8 x repeat flg) 's lpf mode of motion refinement, 0: no lpf, 1: [1 2 1], 2: [1 2 2 2 1], default = 1 +#define MCDI_REL_COL_REF_RT ((0x2f55 << 2) + 0xff000000) +//Bit 31: 8, reserved +//Bit 7: 0, reg_mcdi_relcolrefrt. ratio for column cofidence level against column number, for refinement, default = 135 +#define MCDI_PD22_CHK_THD_RT ((0x2f56 << 2) + 0xff000000) +//Bit 31:27, reserved +//Bit 26:16, reg_mcdi_pd22chkfltcntrt. ratio for flat count of field pulldown 22 check, normalized 2048 as '1', 2047 is set to 2048, default = 1 +//Bit 15: 8, reg_mcdi_pd22chkcntrt. ratio of pulldown 22 check count, normalized 256 as '1', 255 is set to 256, default = 100 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_pd22chkcntthd. thd (>=) for pd22 count before locked, 1~31, default = 4 +#define MCDI_CHAR_DET_DIF_THD ((0x2f57 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_mcdi_chardetminmaxdifthd. thd (>=) for dif between min and max value, default = 64 +//Bit 15: 8, reg_mcdi_chardetmaxdifthd. thd (<) for dif between max value, default = 17 +//Bit 7: 0, reg_mcdi_chardetmindifthd. thd (<) for dif between min value, default = 17 +#define MCDI_CHAR_DET_CNT_THD ((0x2f58 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_mcdi_chardettotcntthd. thd (>=) for total count, 0~21, default = 18 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_chardetmaxcntthd. thd (>=) for max count, 0~21, default = 1 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_chardetmincntthd. thd (>=) for min count, 0~21, default = 1 +//new add +#define MCDI_PD_22_CHK_WND0_X ((0x2f59 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_mcdi_pd22chkwnd0_x1 u13, x1 for window 0, HSIZE-1, software control, default = 719 +//Bit 15:13, reserved +//Bit 12: 0, reg_mcdi_pd22chkwnd0_x0 u13, x0 for window 0, software control, default = 0 +#define MCDI_PD_22_CHK_WND0_Y ((0x2f5a << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_mcdi_pd22chkwnd0_y1 u13, y1 for window 0 software control, default = 39 +//Bit 15:13, reserved +//Bit 12: 0, reg_mcdi_pd22chkwnd0_y0 u13, y0 for window 0, software control, default = 0 +#define MCDI_PD_22_CHK_WND1_X ((0x2f5b << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_mcdi_pd22chkwnd1_x1 u13, x1 for window 1, HSIZE-1, software control, default = 719 +//Bit 15:13, reserved +//Bit 12: 0, reg_mcdi_pd22chkwnd1_x0 u13, x0 for window 1, software control, default = 0 +#define MCDI_PD_22_CHK_WND1_Y ((0x2f5c << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_mcdi_pd22chkwnd1_y1 u13, y1 for window 1 software control, default = 199 +//Bit 15:13, reserved +//Bit 12: 0, reg_mcdi_pd22chkwnd1_y0 u13, y0 for window 1, software control, default = 40 +#define MCDI_PD_22_CHK_FRC_LMV ((0x2f5d << 2) + 0xff000000) +//Bit 31:11, reserved +//Bit 10, reg_mcdi_pd22chklmvchk2 u1, lmv lock check while force vof for each windows, default = 1 +//Bit 9, reg_mcdi_pd22chklmvchk1 u1, lmv lock check while force vof for each windows, default = 0 +//Bit 8, reg_mcdi_pd22chklmvchk0 u1, lmv lock check while force vof for each windows, default = 0 +//Bit 7, reserved +//Bit 6, reg_mcdi_pd22chkfrcpd2 u1, force pd flags for each windows, default = 0 +//Bit 5, reg_mcdi_pd22chkfrcpd1 u1, force pd flags for each windows, default = 0 +//Bit 4, reg_mcdi_pd22chkfrcpd0 u1, force pd flags for each windows, default = 0 +//Bit 3, reserved +//Bit 2, reg_mcdi_pd22chkfrcvof2 u1, force vof flags for each windows, default = 1 +//Bit 1, reg_mcdi_pd22chkfrcvof1 u1, force vof flags for each windows, default = 0 +//Bit 0, reg_mcdi_pd22chkfrcvof0 u1, force vof flags for each windows, default = 0 +#define MCDI_PD_22_CHK_FLG_CNT ((0x2f5e << 2) + 0xff000000) +//Bit 31:27, reserved. +//Bit 26, reg_mcdi_pd22chkflg2. pull down 22 flag of prevoius one field. initial = 0 +//Bit 25, reg_mcdi_pd22chkflg1. pull down 22 flag of prevoius one field. initial = 0 +//Bit 24, reg_mcdi_pd22chkflg. pull down 22 flag of prevoius one field. initial = 0 +//Bit 23:16, reg_mcdi_pd22chkcnt2. pull down 22 count till prevoius one field. initial = 0 +//Bit 15: 8, reg_mcdi_pd22chkcnt1. pull down 22 count till prevoius one field. initial = 0 +//Bit 7: 0, reg_mcdi_pd22chkcnt. pull down 22 count till prevoius one field. initial = 0 +#define MCDI_RO_FLD_PD_22_PRE_CNT1 ((0x2fca << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22precnt1. prevoius pd22 check count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_PD_22_FOR_CNT1 ((0x2fcb << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22forcnt1. forward pd22 check count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_PD_22_FLT_CNT1 ((0x2fcc << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22fltcnt1. flat count (for pd22 check) of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_PD_22_PRE_CNT2 ((0x2fcd << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22precnt2. prevoius pd22 check count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_PD_22_FOR_CNT2 ((0x2fce << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22forcnt2. forward pd22 check count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_PD_22_FLT_CNT2 ((0x2fcf << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22fltcnt2. flat count (for pd22 check) of whole pre one field (block based). initial = 0 +#define MCDI_FIELD_MV ((0x2f60 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_pd22chkcnt +//Bit 23:16, reg_mcdi_fieldgmvcnt +//Bit 15, reg_mcdi_pd22chkflg +//Bit 14, reg_mcdi_fieldgmvlock +//Bit 13: 8, reg_mcdi_fieldrptmv. last field rpt mv +//Bit 7: 6, reserved +//Bit 5: 0, reg_mcdi_fieldgmv. last field gmv +#define MCDI_FIELD_HVF_PRDX_CNT ((0x2f61 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_motionparadoxcnt. +//Bit 23:17, reserved +//Bit 16, reg_mcdi_motionparadoxflg. +//Bit 15: 8, reg_mcdi_highvertfrqcnt. +//Bit 7: 4, reserved +//Bit 3: 2, reg_mcdi_highvertfrqphase. +//Bit 1, reserved +//Bit 0, reg_mcdi_highvertfrqflg. +#define MCDI_FIELD_LUMA_AVG_SUM_0 ((0x2f62 << 2) + 0xff000000) +//Bit 31: 0, reg_mcdi_fld_luma_avg_sum0. +#define MCDI_FIELD_LUMA_AVG_SUM_1 ((0x2f63 << 2) + 0xff000000) +//Bit 31: 0, reg_mcdi_fld_luma_avg_sum1. +#define MCDI_YCBCR_BLEND_CRTL ((0x2f64 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_mcdi_ycbcrblendgain. ycbcr blending gain for cbcr in ycbcr. default = 0 +//Bit 7: 2, reserved. +//Bit 1: 0, reg_mcdi_ycbcrblendmode. 0:y+cmb(cb,cr), 1:med(r,g,b), 2:max(r,g,b), default = 2 +#define MCDI_MCVECWR_CANVAS_SIZE ((0x2f65 << 2) + 0xff000000) +#define MCDI_MCVECRD_CANVAS_SIZE ((0x2f66 << 2) + 0xff000000) +#define MCDI_MCINFOWR_CANVAS_SIZE ((0x2f67 << 2) + 0xff000000) +#define MCDI_MCINFORD_CANVAS_SIZE ((0x2f68 << 2) + 0xff000000) +#define MCDI_MCVECWR_X ((0x2f92 << 2) + 0xff000000) +#define MCDI_MCVECWR_Y ((0x2f93 << 2) + 0xff000000) +#define MCDI_MCVECWR_CTRL ((0x2f94 << 2) + 0xff000000) +#define MCDI_MCVECRD_X ((0x2f95 << 2) + 0xff000000) +#define MCDI_MCVECRD_Y ((0x2f96 << 2) + 0xff000000) +#define MCDI_MCVECRD_CTRL ((0x2f97 << 2) + 0xff000000) +#define MCDI_MCINFOWR_X ((0x2f98 << 2) + 0xff000000) +#define MCDI_MCINFOWR_Y ((0x2f99 << 2) + 0xff000000) +#define MCDI_MCINFOWR_CTRL ((0x2f9a << 2) + 0xff000000) +#define MCDI_MCINFORD_X ((0x2f9b << 2) + 0xff000000) +#define MCDI_MCINFORD_Y ((0x2f9c << 2) + 0xff000000) +#define MCDI_MCINFORD_CTRL ((0x2f9d << 2) + 0xff000000) +#define MCDI_LMVLCKSTEXT_0 ((0x2f69 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, mcdi_lmvlckstext_1 lmv lck blog 1 line start +//Bit 15:12, reserved +//Bit 11: 0, mcdi_lmvlckstext_0 lmv lck blog 0 line start +#define MCDI_LMVLCKSTEXT_1 ((0x2f6a << 2) + 0xff000000) +//Bit 31 , mcdi_refnewmode new ref me mv array order +//Bit 30 , mcdi_ref_lmv_lck_en use locked line mvs for ref +//Bit 29:28, mcdi_lmvlckupdw_ext up/down extend lines for locked lmv line's +//Bit 27:12, mcdi_lmvlckmin lmv lck blog height limit +//Bit 15:12, reserved +//Bit 11: 0, mcdi_lmvlckstext_2 lmv lck blog 2 line start +#define MCDI_LMVLCKEDEXT_0 ((0x2f6b << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, mcdi_lmvlckedext_1 lmv lck blog 1 line end +//Bit 15:12, reserved +//Bit 11: 0, mcdi_lmvlckedext_0 lmv lck blog 0 line end +#define MCDI_LMVLCKEDEXT_1 ((0x2f6c << 2) + 0xff000000) +//Bit 31:12, reserved +//Bit 11: 0, mcdi_lmvlckedext_2 lmv lck blog 2 line end +// ================================================================== MC registers ======================================================================================================== +#define MCDI_MC_CRTL ((0x2f70 << 2) + 0xff000000) +//Bit 31: 9, reserved +//Bit 8, reg_mcdi_mcpreflg. flag to use previous field for MC, 0:forward field, 1: previous field, default = 1 +//Bit 7, reg_mcdi_mcrelrefbycolcfden. enable rel refinement by column cofidence in mc blending, default = 1 +//Bit 6: 5, reg_mcdi_mclpfen. enable mc pixles/rel lpf, 0:disable, 1: lpf rel, 2: lpf mc pxls, 3: lpf both rel and mc pxls, default = 0 +//Bit 4: 2, reg_mcdi_mcdebugmode. enable mc debug mode, 0:disable, 1: split left/right, 2: split top/bottom, 3: debug mv, 4: debug rel, default = 0 +//Bit 1: 0, reg_mcdi_mcen. mcdi enable mode, 0:disable, 1: blend with ma, 2: full mc, default = 1 +#define MCDI_MC_LPF_MSK_0 ((0x2f71 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_mcdi_mclpfmsk02. mc lpf coef. 2 for pixel 0 of current block, normalized 16 as '1', default = 0 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_mclpfmsk01. mc lpf coef. 1 for pixel 0 of current block, normalized 16 as '1', default = 9 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_mclpfmsk00. mc lpf coef. 0 for pixel 0 of current block, normalized 16 as '1', default = 7 +#define MCDI_MC_LPF_MSK_1 ((0x2f72 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_mcdi_mclpfmsk12. mc lpf coef. 2 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 0 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_mclpfmsk11. mc lpf coef. 1 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 11 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_mclpfmsk10. mc lpf coef. 0 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 5 +#define MCDI_MC_LPF_MSK_2 ((0x2f73 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_mcdi_mclpfmsk22. mc lpf coef. 2 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_mclpfmsk21. mc lpf coef. 1 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 14 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_mclpfmsk20. mc lpf coef. 0 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1 +#define MCDI_MC_LPF_MSK_3 ((0x2f74 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_mcdi_mclpfmsk32. mc lpf coef. 2 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 5 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_mclpfmsk31. mc lpf coef. 1 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 11 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_mclpfmsk30. mc lpf coef. 0 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 0 +#define MCDI_MC_LPF_MSK_4 ((0x2f75 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:16, reg_mcdi_mclpfmsk42. mc lpf coef. 2 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 7 +//Bit 15:13, reserved +//Bit 12: 8, reg_mcdi_mclpfmsk41. mc lpf coef. 1 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 9 +//Bit 7: 5, reserved +//Bit 4: 0, reg_mcdi_mclpfmsk40. mc lpf coef. 0 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 0 +#define MCDI_MC_REL_GAIN_OFFST_0 ((0x2f76 << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25, reg_mcdi_mcmotionparadoxflg. flag of motion paradox, initial with 0 and read from software, default = 0 +//Bit 24, reg_mcdi_mchighvertfrqflg. flag of high vert frq, initial with 0 and read from software, default = 0 +//Bit 23:16, reg_mcdi_mcmotionparadoxoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 128 +//Bit 15:12, reserved +//Bit 11: 8, reg_mcdi_mcmotionparadoxgain. gain for rel (MC blending coef.) refinement if motion paradox detected before MC blending, normalized 8 as '1', set 15 to 16, default = 8 +//Bit 7: 4, reg_mcdi_mchighvertfrqoffst. minus offset (alpha - offset) for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, default = 15 +//Bit 3: 0, reg_mcdi_mchighvertfrqgain. gain for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, normalized 8 as '1', set 15 to 16, default = 8 +#define MCDI_MC_REL_GAIN_OFFST_1 ((0x2f77 << 2) + 0xff000000) +//Bit 31:24, reg_mcdi_mcoutofboundrayoffst. offset (rel + offset) for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending before MC blending, default = 255 +//Bit 23:20, reserved +//Bit 19:16, reg_mcdi_mcoutofboundraygain. gain for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending, normalized 8 as '1', set 15 to 16, default = 8 +//Bit 15: 8, reg_mcdi_mcrelrefbycolcfdoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 255 +//Bit 7: 4, reserved. +//Bit 3: 0, reg_mcdi_mcrelrefbycolcfdgain. gain for rel (MC blending coef.) refinement if column cofidence failed before MC blending, normalized 8 as '1', set 15 to 16, default = 8 +#define MCDI_MC_COL_CFD_0 ((0x2f78 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_0. column cofidence value 0 read from software. initial = 0 +#define MCDI_MC_COL_CFD_1 ((0x2f79 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_1. column cofidence value 1 read from software. initial = 0 +#define MCDI_MC_COL_CFD_2 ((0x2f7a << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_2. column cofidence value 2 read from software. initial = 0 +#define MCDI_MC_COL_CFD_3 ((0x2f7b << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_3. column cofidence value 3 read from software. initial = 0 +#define MCDI_MC_COL_CFD_4 ((0x2f7c << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_4. column cofidence value 4 read from software. initial = 0 +#define MCDI_MC_COL_CFD_5 ((0x2f7d << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_5. column cofidence value 5 read from software. initial = 0 +#define MCDI_MC_COL_CFD_6 ((0x2f7e << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_6. column cofidence value 6 read from software. initial = 0 +#define MCDI_MC_COL_CFD_7 ((0x2f7f << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_7. column cofidence value 7 read from software. initial = 0 +#define MCDI_MC_COL_CFD_8 ((0x2f80 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_8. column cofidence value 8 read from software. initial = 0 +#define MCDI_MC_COL_CFD_9 ((0x2f81 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_9. column cofidence value 9 read from software. initial = 0 +#define MCDI_MC_COL_CFD_10 ((0x2f82 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_10. column cofidence value 10 read from software. initial = 0 +#define MCDI_MC_COL_CFD_11 ((0x2f83 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_11. column cofidence value 11 read from software. initial = 0 +#define MCDI_MC_COL_CFD_12 ((0x2f84 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_12. column cofidence value 12 read from software. initial = 0 +#define MCDI_MC_COL_CFD_13 ((0x2f85 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_13. column cofidence value 13 read from software. initial = 0 +#define MCDI_MC_COL_CFD_14 ((0x2f86 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_14. column cofidence value 14 read from software. initial = 0 +#define MCDI_MC_COL_CFD_15 ((0x2f87 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_15. column cofidence value 15 read from software. initial = 0 +#define MCDI_MC_COL_CFD_16 ((0x2f88 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_16. column cofidence value 16 read from software. initial = 0 +#define MCDI_MC_COL_CFD_17 ((0x2f89 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_17. column cofidence value 17 read from software. initial = 0 +#define MCDI_MC_COL_CFD_18 ((0x2f8a << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_18. column cofidence value 18 read from software. initial = 0 +#define MCDI_MC_COL_CFD_19 ((0x2f8b << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_19. column cofidence value 19 read from software. initial = 0 +#define MCDI_MC_COL_CFD_20 ((0x2f8c << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_20. column cofidence value 20 read from software. initial = 0 +#define MCDI_MC_COL_CFD_21 ((0x2f8d << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_21. column cofidence value 21 read from software. initial = 0 +#define MCDI_MC_COL_CFD_22 ((0x2f8e << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_22. column cofidence value 22 read from software. initial = 0 +#define MCDI_MC_COL_CFD_23 ((0x2f8f << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_23. column cofidence value 23 read from software. initial = 0 +#define MCDI_MC_COL_CFD_24 ((0x2f90 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_24. column cofidence value 24 read from software. initial = 0 +#define MCDI_MC_COL_CFD_25 ((0x2f91 << 2) + 0xff000000) +//Bit 31: 0, mcdi_mc_col_cfd_25. column cofidence value 25 read from software. initial = 0 +// ===================================================================================== PRE RO Registers ========================================================================================== +#define MCDI_RO_FLD_LUMA_AVG_SUM ((0x2fa0 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldlumaavgsum. block's luma avg sum of current filed (block based). initial = 0 +#define MCDI_RO_GMV_VLD_CNT ((0x2fa1 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_gmvvldcnt. valid gmv's count of pre one filed (block based). initial = 0 +#define MCDI_RO_RPT_FLG_CNT ((0x2fa2 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_rptflgcnt. repeat mv's count of pre one filed (block based). initial = 0 +#define MCDI_RO_FLD_BAD_SAD_CNT ((0x2fa3 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldbadsadcnt. bad sad count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_BAD_BADW_CNT ((0x2fa4 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldbadbadwcnt. bad badw count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_BAD_REL_CNT ((0x2fa5 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldbadrelcnt. bad rel count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_MTN_CNT ((0x2fa6 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldmtncnt. motion count of whole pre one field (pixel based). initial = 0 +#define MCDI_RO_FLD_VLD_CNT ((0x2fa7 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldvldcnt. valid motion count of whole pre one field (pixel based). initial = 0 +#define MCDI_RO_FLD_PD_22_PRE_CNT ((0x2fa8 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22precnt. prevoius pd22 check count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_PD_22_FOR_CNT ((0x2fa9 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22forcnt. forward pd22 check count of whole pre one field (block based). initial = 0 +#define MCDI_RO_FLD_PD_22_FLT_CNT ((0x2faa << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_fldpd22fltcnt. flat count (for pd22 check) of whole pre one field (block based). initial = 0 +#define MCDI_RO_HIGH_VERT_FRQ_FLG ((0x2fab << 2) + 0xff000000) +//Bit 31:16, reserved. +//Bit 15: 8, ro_mcdi_highvertfrqcnt. high vertical frequency count till prevoius one field. initial = 0 +//Bit 7: 3, reserved. +//Bit 2: 1, ro_mcdi_highvertfrqphase. high vertical frequency phase of prevoius one field. initial = 2 +//Bit 0, ro_mcdi_highvertfrqflg. high vertical frequency flag of prevoius one field. initial = 0 +#define MCDI_RO_GMV_LOCK_FLG ((0x2fac << 2) + 0xff000000) +//Bit 31:16, reserved. +//Bit 15: 8, ro_mcdi_gmvlckcnt. global mv lock count till prevoius one field. initial = 0 +//Bit 7: 2, ro_mcdi_gmv. global mv of prevoius one field. -31~31, initial = 32 (invalid value) +//Bit 1, ro_mcdi_zerogmvlckflg. zero global mv lock flag of prevoius one field. initial = 0 +//Bit 0, ro_mcdi_gmvlckflg. global mv lock flag of prevoius one field. initial = 0 +#define MCDI_RO_RPT_MV ((0x2fad << 2) + 0xff000000) +//Bit 5: 0, ro_mcdi_rptmv. repeate mv of prevoius one field. -31~31, initial = 32 (invalid value) +#define MCDI_RO_MOTION_PARADOX_FLG ((0x2fae << 2) + 0xff000000) +//Bit 31:16, reserved. +//Bit 15: 8, ro_mcdi_motionparadoxcnt. motion paradox count till prevoius one field. initial = 0 +//Bit 7: 1, reserved. +//Bit 0, ro_mcdi_motionparadoxflg. motion paradox flag of prevoius one field. initial = 0 +#define MCDI_RO_PD_22_FLG ((0x2faf << 2) + 0xff000000) +//Bit 31:27, reserved. +//Bit 26, ro_mcdi_pd22flg2. pull down 22 flag of prevoius one field. initial = 0 +//Bit 25, ro_mcdi_pd22flg1. pull down 22 flag of prevoius one field. initial = 0 +//Bit 24, ro_mcdi_pd22flg. pull down 22 flag of prevoius one field. initial = 0 +//Bit 23:16, ro_mcdi_pd22cnt2. pull down 22 count till prevoius one field. initial = 0 +//Bit 15: 8, ro_mcdi_pd22cnt1. pull down 22 count till prevoius one field. initial = 0 +//Bit 7: 0, ro_mcdi_pd22cnt. pull down 22 count till prevoius one field. initial = 0 +#define MCDI_RO_COL_CFD_0 ((0x2fb0 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_0. column cofidence value 0. initial = 0 +#define MCDI_RO_COL_CFD_1 ((0x2fb1 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_1. column cofidence value 1. initial = 0 +#define MCDI_RO_COL_CFD_2 ((0x2fb2 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_2. column cofidence value 2. initial = 0 +#define MCDI_RO_COL_CFD_3 ((0x2fb3 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_3. column cofidence value 3. initial = 0 +#define MCDI_RO_COL_CFD_4 ((0x2fb4 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_4. column cofidence value 4. initial = 0 +#define MCDI_RO_COL_CFD_5 ((0x2fb5 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_5. column cofidence value 5. initial = 0 +#define MCDI_RO_COL_CFD_6 ((0x2fb6 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_6. column cofidence value 6. initial = 0 +#define MCDI_RO_COL_CFD_7 ((0x2fb7 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_7. column cofidence value 7. initial = 0 +#define MCDI_RO_COL_CFD_8 ((0x2fb8 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_8. column cofidence value 8. initial = 0 +#define MCDI_RO_COL_CFD_9 ((0x2fb9 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_9. column cofidence value 9. initial = 0 +#define MCDI_RO_COL_CFD_10 ((0x2fba << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_10. column cofidence value 10. initial = 0 +#define MCDI_RO_COL_CFD_11 ((0x2fbb << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_11. column cofidence value 11. initial = 0 +#define MCDI_RO_COL_CFD_12 ((0x2fbc << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_12. column cofidence value 12. initial = 0 +#define MCDI_RO_COL_CFD_13 ((0x2fbd << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_13. column cofidence value 13. initial = 0 +#define MCDI_RO_COL_CFD_14 ((0x2fbe << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_14. column cofidence value 14. initial = 0 +#define MCDI_RO_COL_CFD_15 ((0x2fbf << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_15. column cofidence value 15. initial = 0 +#define MCDI_RO_COL_CFD_16 ((0x2fc0 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_16. column cofidence value 16. initial = 0 +#define MCDI_RO_COL_CFD_17 ((0x2fc1 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_17. column cofidence value 17. initial = 0 +#define MCDI_RO_COL_CFD_18 ((0x2fc2 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_18. column cofidence value 18. initial = 0 +#define MCDI_RO_COL_CFD_19 ((0x2fc3 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_19. column cofidence value 19. initial = 0 +#define MCDI_RO_COL_CFD_20 ((0x2fc4 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_20. column cofidence value 20. initial = 0 +#define MCDI_RO_COL_CFD_21 ((0x2fc5 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_21. column cofidence value 21. initial = 0 +#define MCDI_RO_COL_CFD_22 ((0x2fc6 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_22. column cofidence value 22. initial = 0 +#define MCDI_RO_COL_CFD_23 ((0x2fc7 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_23. column cofidence value 23. initial = 0 +#define MCDI_RO_COL_CFD_24 ((0x2fc8 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_24. column cofidence value 24. initial = 0 +#define MCDI_RO_COL_CFD_25 ((0x2fc9 << 2) + 0xff000000) +//Bit 31: 0, ro_mcdi_col_cfd_25. column cofidence value 25. initial = 0 +// add space 8'hd0-8'hef +// +// Reading file: dipd_regs.h +// +// synopsys translate_off +// synopsys translate_on +// using 8'he0-8'hef +#define DIPD_COMB_CTRL0 ((0x2fd0 << 2) + 0xff000000) +//Bit 31:0, reg_pd_comb_ctrl0 +#define DIPD_COMB_CTRL1 ((0x2fd1 << 2) + 0xff000000) +//Bit 31:0, reg_pd_comb_ctrl1 +#define DIPD_COMB_CTRL2 ((0x2fd2 << 2) + 0xff000000) +//Bit 31:0, reg_pd_comb_ctrl2 +#define DIPD_COMB_CTRL3 ((0x2fd3 << 2) + 0xff000000) +//Bit 31:0, reg_pd_comb_ctrl3 +#define DIPD_COMB_CTRL4 ((0x2fd4 << 2) + 0xff000000) +//Bit 31:0, reg_pd_comb_ctrl4 +#define DIPD_COMB_CTRL5 ((0x2fd5 << 2) + 0xff000000) +//Bit 31:0, reg_pd_comb_ctrl5 +#define DIPD_RO_COMB_0 ((0x2fd6 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_0 +#define DIPD_RO_COMB_1 ((0x2fd7 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_1 +#define DIPD_RO_COMB_2 ((0x2fd8 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_2 +#define DIPD_RO_COMB_3 ((0x2fd9 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_3 +#define DIPD_RO_COMB_4 ((0x2fda << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_4 +#define DIPD_RO_COMB_5 ((0x2fdb << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_5 +#define DIPD_RO_COMB_6 ((0x2fdc << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_6 +#define DIPD_RO_COMB_7 ((0x2fdd << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_7 +#define DIPD_RO_COMB_8 ((0x2fde << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_8 +#define DIPD_RO_COMB_9 ((0x2fdf << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_9 +#define DIPD_RO_COMB_10 ((0x2fe0 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_10 +#define DIPD_RO_COMB_11 ((0x2fe1 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_11 +#define DIPD_RO_COMB_12 ((0x2fe2 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_12 +#define DIPD_RO_COMB_13 ((0x2fe3 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_13 +#define DIPD_RO_COMB_14 ((0x2fe4 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_14 +#define DIPD_RO_COMB_15 ((0x2fe5 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_15 +#define DIPD_RO_COMB_16 ((0x2fe6 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_16 +#define DIPD_RO_COMB_17 ((0x2fe7 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_17 +#define DIPD_RO_COMB_18 ((0x2fe8 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_18 +#define DIPD_RO_COMB_19 ((0x2fe9 << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_19 +#define DIPD_RO_COMB_20 ((0x2fea << 2) + 0xff000000) +//Bit 31:0, ro_pd_comb_20 +#define DIPD_COMB_CTRL6 ((0x2feb << 2) + 0xff000000) +//Bit 31:0, reg_pd_comb_ctrl6 +// synopsys translate_off +// synopsys translate_on +// +// Closing file: dipd_regs.h +// +// addr space 8'hf0-8'hff +// +// Reading file: nr3_tnr_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define NR3_MODE ((0x2ff0 << 2) + 0xff000000) +//Bit 31: 6 reserved +//Bit 5 reg_nr3_vtxt_mode // unsigned , default = 0 0: avg; 1:MAX +//Bit 4 reg_3dnr_nr3_cbyy_ignor_coop // unsigned , default = 0 ignore coop condition for cbyy motion decision +//Bit 3 reg_3dnr_nr3_ybyc_ignor_cnoop // unsigned , default = 0 ignore cnoop condition for ybyc motion decision +//Bit 2: 0 reg_3dnr_nr3_suremot_txt_mode // unsigned , default = 3 0: cur, 1:p2; 2: (cur+p2)/2; 3/up: min(cur,p2) +#define NR3_COOP_PARA ((0x2ff1 << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:20 reg_3dnr_nr3_coop_mode // unsigned , default = 2 0 original pixel 1: [1 2 1]/4 lpf; 2: [1 2 2 2 1]/8; 3: 3x3 lpf +//Bit 19:16 reg_3dnr_nr3_coop_ratio // unsigned , default = 8 cur and p2 color oop decision ratio: (avg1<(dif1*ratio/8 + ofst)); +//Bit 15: 8 reg_3dnr_nr3_coop_ofset // signed , default = -1 cur and p2 color oop decision ofst: (avg1<(dif1*ratio/8 + ofst)); +//Bit 7: 0 reg_3dnr_nr3_coop_sat_thrd // unsigned , default = 0 cur and p2 color oop decision min(sat0,sat1) threshold; +#define NR3_CNOOP_GAIN ((0x2ff2 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:20 reg_3dnr_nr3_cnoop_ratio0 // unsigned , default = 8 cur and p2 color noop decision ratio0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0)); +//Bit 19:16 reg_3dnr_nr3_cnoop_ratio1 // unsigned , default = 8 cur and p2 color noop decision ratio1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1)); +//Bit 15: 8 reg_3dnr_nr3_cnoop_ofset0 // signed , default = 25 cur and p2 color noop decision ofset0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0)); +//Bit 7: 0 reg_3dnr_nr3_cnoop_ofset1 // signed , default = 0 cur and p2 color noop decision ofset1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1)); +#define NR3_YMOT_PARA ((0x2ff3 << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19 reg_3dnr_nr3_ymot_only_en // unsigned , default = 1 enable signal for ignor chroma motion: (ytxt &coop) +//Bit 18 reg_3dnr_nr3_ymot_only_cmtmode // unsigned , default = 1 0: cmot=ymot; 1: cmot = MIN(ymot, cmot) +//Bit 17:16 reg_3dnr_nr3_ymot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2) +//Bit 15: 8 reg_3dnr_nr3_ymot_only_txtthrd // unsigned , default = 10 threshold to luma texture to decide use ymot only +//Bit 7: 0 reg_3dnr_nr3_ymot_only_motthrd // unsigned , default = 30 threshold to luma motion to decide use ymot only +#define NR3_CMOT_PARA ((0x2ff4 << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19 reg_3dnr_nr3_cmot_only_en // unsigned , default = 1 enable signal for ignor luma motion: (ctxt &cnoop) +//Bit 18 reg_3dnr_nr3_cmot_only_ymtmode // unsigned , default = 0 0: ymot=cmot+ymot/4; 1: ymot = MIN(ymot, cmot) +//Bit 17:16 reg_3dnr_nr3_cmot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2) +//Bit 15: 8 reg_3dnr_nr3_cmot_only_txtthrd // unsigned , default = 20 threshold to chroma texture to decide use cmot only +//Bit 7: 0 reg_3dnr_nr3_cmot_only_motthrd // unsigned , default = 15 threshold to chroma motion to decide use cmot only +#define NR3_SUREMOT_YGAIN ((0x2ff5 << 2) + 0xff000000) +//Bit 31:24 reg_3dnr_nr3_suremot_dec_yrate // unsigned , default = 16 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset +//Bit 23:16 reg_3dnr_nr3_suremot_dec_yofst // unsigned , default = 12 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset +//Bit 15: 8 reg_3dnr_nr3_suremot_frc_ygain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset +//Bit 7: 0 reg_3dnr_nr3_suremot_frc_yofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset +#define NR3_SUREMOT_CGAIN ((0x2ff6 << 2) + 0xff000000) +//Bit 31:24 reg_3dnr_nr3_suremot_dec_crate // unsigned , default = 34 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset +//Bit 23:16 reg_3dnr_nr3_suremot_dec_cofst // unsigned , default = 38 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset +//Bit 15: 8 reg_3dnr_nr3_suremot_frc_cgain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset +//Bit 7: 0 reg_3dnr_nr3_suremot_frc_cofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset +// synopsys translate_off +// synopsys translate_on +// +// Closing file: nr3_tnr_regs.h +// +#define LBUF_TOP_CTRL ((0x2fff << 2) + 0xff000000) +//bit 23:22 mode_444c422 +//bit 21:20 mode_422c444 +//bit 17 lbuf_fmt444_mode +//bit 16 lbuf_line5_mode +//bit 12:0 pre_lbuf_size +// synopsys translate_off +// synopsys translate_on +// +// Closing file: mcdi_regs.h +// +// VPU_VLOCK register (16'h3000 - 16'h30ff) +//======================================================================== +// +// Reading file: vpu_vlock_reg.h +// +// synopsys translate_off +// synopsys translate_on +// ---------------------------- +// VPU_VLOCK 0x30 +// ---------------------------- +// ----------------------------------------------- +// REG_BASE: VPU_VLOCK_VCBUS_BASE = 0x30 +// ----------------------------------------------- +#define VPU_VLOCK_CTRL ((0x3000 << 2) + 0xff000000) +#define VPU_VLOCK_MISC_CTRL ((0x3001 << 2) + 0xff000000) +#define VPU_VLOCK_LOOP0_ACCUM_LMT ((0x3002 << 2) + 0xff000000) +#define VPU_VLOCK_LOOP0_CTRL0 ((0x3003 << 2) + 0xff000000) +#define VPU_VLOCK_LOOP1_CTRL0 ((0x3004 << 2) + 0xff000000) +#define VPU_VLOCK_LOOP1_IMISSYNC_MAX ((0x3005 << 2) + 0xff000000) +#define VPU_VLOCK_LOOP1_IMISSYNC_MIN ((0x3006 << 2) + 0xff000000) +#define VPU_VLOCK_OVWRITE_ACCUM0 ((0x3007 << 2) + 0xff000000) +#define VPU_VLOCK_OVWRITE_ACCUM1 ((0x3008 << 2) + 0xff000000) +#define VPU_VLOCK_OUTPUT0_CAPT_LMT ((0x3009 << 2) + 0xff000000) +#define VPU_VLOCK_OUTPUT0_PLL_LMT ((0x300a << 2) + 0xff000000) +#define VPU_VLOCK_OUTPUT1_CAPT_LMT ((0x300b << 2) + 0xff000000) +#define VPU_VLOCK_OUTPUT1_PLL_LMT ((0x300c << 2) + 0xff000000) +#define VPU_VLOCK_LOOP1_PHSDIF_TGT ((0x300d << 2) + 0xff000000) +#define VPU_VLOCK_RO_LOOP0_ACCUM ((0x300e << 2) + 0xff000000) +#define VPU_VLOCK_RO_LOOP1_ACCUM ((0x300f << 2) + 0xff000000) +#define VPU_VLOCK_OROW_OCOL_MAX ((0x3010 << 2) + 0xff000000) +#define VPU_VLOCK_RO_VS_I_DIST ((0x3011 << 2) + 0xff000000) +#define VPU_VLOCK_RO_VS_O_DIST ((0x3012 << 2) + 0xff000000) +#define VPU_VLOCK_RO_LINE_PIX_ADJ ((0x3013 << 2) + 0xff000000) +#define VPU_VLOCK_RO_OUTPUT_00_01 ((0x3014 << 2) + 0xff000000) +#define VPU_VLOCK_RO_OUTPUT_10_11 ((0x3015 << 2) + 0xff000000) +#define VPU_VLOCK_MX4096 ((0x3016 << 2) + 0xff000000) +#define VPU_VLOCK_STBDET_WIN0_WIN1 ((0x3017 << 2) + 0xff000000) +#define VPU_VLOCK_STBDET_CLP ((0x3018 << 2) + 0xff000000) +#define VPU_VLOCK_STBDET_ABS_WIN0 ((0x3019 << 2) + 0xff000000) +#define VPU_VLOCK_STBDET_ABS_WIN1 ((0x301a << 2) + 0xff000000) +#define VPU_VLOCK_STBDET_SGN_WIN0 ((0x301b << 2) + 0xff000000) +#define VPU_VLOCK_STBDET_SGN_WIN1 ((0x301c << 2) + 0xff000000) +#define VPU_VLOCK_ADJ_EN_SYNC_CTRL ((0x301d << 2) + 0xff000000) +#define VPU_VLOCK_GCLK_EN ((0x301e << 2) + 0xff000000) +#define VPU_VLOCK_LOOP1_ACCUM_LMT ((0x301f << 2) + 0xff000000) +#define VPU_VLOCK_RO_M_INT_FRAC ((0x3020 << 2) + 0xff000000) +#define VPU_VLOCK_RO_PH_DIS ((0x3021 << 2) + 0xff000000) +#define VPU_VLOCK_RO_PH_ERR ((0x3022 << 2) + 0xff000000) +#define VPU_VLOCK_LOCK_TH ((0x3023 << 2) + 0xff000000) +#define VPU_VLOCK_RO_LCK_FRM ((0x3024 << 2) + 0xff000000) +#define VPU_VLOCK_WIN0_TH ((0x3025 << 2) + 0xff000000) +#define VPU_VLOCK_WIN0_RATIO ((0x3026 << 2) + 0xff000000) +#define VPU_VLOCK_WIN0_FILTER_CNTL ((0x3027 << 2) + 0xff000000) +#define VPU_VLOCK_WIN1_TH ((0x3028 << 2) + 0xff000000) +#define VPU_VLOCK_WIN1_RATIO ((0x3029 << 2) + 0xff000000) +#define VPU_VLOCK_WIN1_FILTER_CNTL ((0x302a << 2) + 0xff000000) +#define VPU_VLOCK_LOCK_TH1 ((0x302b << 2) + 0xff000000) +#define VPU_VLOCK_LOOP0_ERR_LMT ((0x302c << 2) + 0xff000000) +#define VPU_VLOCK_LOOP1_ERR_LMT ((0x302d << 2) + 0xff000000) +#define VPU_VLOCK_ERR_CTRL0 ((0x302e << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_vlock_reg.h +// +// +// Reading file: vpp_partb_reg.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: VPPB_VCBUS_BASE = 0x31 +// ----------------------------------------------- +////=================================================================//// +//// vkeystone +////=================================================================//// +// 8'h00-8'h17 +// +// Reading file: vkstone_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define VKS_CTRL ((0x3100 << 2) + 0xff000000) +//Bit 31 reg_vks_en // unsigned , default = 1 enable signal of the vks function +//Bit 30 reg_vks_scl_mode0 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale; +//Bit 29 reg_vks_scl_mode1 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale; +//Bit 28 reg_vks_fill_mode // unsigned , default = 1 mode of out-of-boundary fill, 0 extension, 1: fill with the fill_value +//Bit 27:26 reg_vks_row_inp_mode // unsigned , default = 1 , interpolation mode from 16pieces ofset/step to each line ofset and step; 0: linear interpolation; 1: cubic interpolation (using ccoef) +//Bit 25 reg_vks_border_ext_mode0 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one +//Bit 24 reg_vks_border_ext_mode1 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one +//Bit 23 reg_vks_obuf_mode0 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions +//Bit 22 reg_vks_obuf_mode1 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions +//Bit 21:20 reg_vks_obuf_mrgn0 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump +//Bit 19:18 reg_vks_obuf_mrgn1 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump +//Bit 17:16 reg_vks_phs_qmode // unsigned , default = 2 , interpolation mode of the phase, 0: floor to 1/64 phase; 1: round to 1/64 phase; 2/3 linear intp +//Bit 15: 0 reg_vks_row_scl // unsigned , default = 11651 , scale of row to make it fit to the 16 pieces, scl = (2^23)/RowMax +#define VKS_OUT_WIN_SIZE ((0x3101 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_vks_ocolmax // unsigned , default = 1280 output outer window col number, decided by the projector +//Bit 15:14 reserved +//Bit 13: 0 reg_vks_orowmax // unsigned , default = 720 output outer window row number, decided by the projector +#define VKS_PRELPF_YCOEF0 ((0x3102 << 2) + 0xff000000) +//Bit 31:24 reg_vks_prelpf_ycoef0 // signed , default = -128 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' +//Bit 23:16 reg_vks_prelpf_ycoef1 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' +//Bit 15: 8 reg_vks_prelpf_ycoef2 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' +//Bit 7: 0 reg_vks_prelpf_ycoef3 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' +#define VKS_PRELPF_YCOEF1 ((0x3103 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_vks_prelpf_ycoef4 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' +//Bit 7: 0 reg_vks_prelpf_ycoef5 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1' +#define VKS_PRELPF_CCOEF0 ((0x3104 << 2) + 0xff000000) +//Bit 31:24 reg_vks_prelpf_ccoef0 // signed , default = -128 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' +//Bit 23:16 reg_vks_prelpf_ccoef1 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' +//Bit 15: 8 reg_vks_prelpf_ccoef2 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' +//Bit 7: 0 reg_vks_prelpf_ccoef3 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' +#define VKS_PRELPF_CCOEF1 ((0x3105 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 8 reg_vks_prelpf_ccoef4 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' +//Bit 7: 0 reg_vks_prelpf_ccoef5 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1' +#define VKS_FILL_VAL ((0x3106 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_vks_fill_value0 // unsigned , default = 0 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0] +//Bit 15: 8 reg_vks_fill_value1 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0] +//Bit 7: 0 reg_vks_fill_value2 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0] +#define VKS_IWIN_HSIZE ((0x3107 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_vks_iwinx0 // unsigned , default = 160 , input start-col and end-col; +//Bit 15:14 reserved +//Bit 13: 0 reg_vks_iwinx1 // unsigned , default = 1279 , input start-col and end-col; +#define VKS_IWIN_VSIZE ((0x3108 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_vks_iwiny0 // unsigned , default = 0 , input start-row and end-row; +//Bit 15:14 reserved +//Bit 13: 0 reg_vks_iwiny1 // unsigned , default = 719 , input start-row and end-row; +#define VKS_TOP_MISC ((0x3109 << 2) + 0xff000000) +//Bit 31:19 reserved +//Bit 18 reg_flt_en // unsigned , default = 1 +//Bit 17 reg_frm_rst // unsigned , default = 0 +//Bit 16 reg_ctrl_sync // unsigned , default = 0 +//Bit 15: 8 blank_num // unsigned , default = 4 +//Bit 7: 0 flt_blank_num // unsigned , default = 9 +#define VKS_START_CTRL ((0x310a << 2) + 0xff000000) +//Bit 31:17 reserved +//Bit 16 reg_vks_en_mode // unsigned , default = 0 +//Bit 15: 0 reg_hold_phnum // unsigned , default = 5 +#define VKS_LBUF_SIZE ((0x310b << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11: 0 reg_lbuf_depth // unsigned , default = 1024 +#define VKS_PARA_ADDR_PORT ((0x310e << 2) + 0xff000000) +#define VKS_PARA_DATA_PORT ((0x310f << 2) + 0xff000000) + + #define VKS_SCL_OFSET00 0x9 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset0 // unsigned , default = 118534 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET01 0xa // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset1 // unsigned , default = 111450 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET02 0xb // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset2 // unsigned , default = 104366 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET03 0xc // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset3 // unsigned , default = 97283 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET04 0xd // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset4 // unsigned , default = 90199 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET05 0xe // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset5 // unsigned , default = 83115 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET06 0xf // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset6 // unsigned , default = 76031 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET07 0x10 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset7 // unsigned , default = 68947 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET08 0x11 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset8 // unsigned , default = 61864 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET09 0x12 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset9 // unsigned , default = 54780 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET10 0x13 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset10 // unsigned , default = 47696 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET11 0x14 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset11 // unsigned , default = 40612 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET12 0x15 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset12 // unsigned , default = 33528 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET13 0x16 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset13 // unsigned , default = 26444 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET14 0x17 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset14 // unsigned , default = 19361 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET15 0x18 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset15 // unsigned , default = 12277 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_OFSET16 0x19 // +//Bit 31:20 reserved +//Bit 19: 0 reg_vks_scl_ofset16 // unsigned , default = 5193 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase + #define VKS_SCL_STEP00 0x1a // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step0 // unsigned , default = 331378 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP01 0x1b // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step1 // unsigned , default = 383191 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP02 0x1c // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step2 // unsigned , default = 435004 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP03 0x1d // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step3 // unsigned , default = 486818 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP04 0x1e // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step4 // unsigned , default = 538631 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP05 0x1f // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step5 // unsigned , default = 590444 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP06 0x20 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step6 // unsigned , default = 642257 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP07 0x21 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step7 // unsigned , default = 694070 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP08 0x22 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step8 // unsigned , default = 745884 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP09 0x23 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step9 // unsigned , default = 797697 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP10 0x24 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step10 // unsigned , default = 849510 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP11 0x25 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step11 // unsigned , default = 901323 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP12 0x26 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step12 // unsigned , default = 953136 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP13 0x27 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step13 // unsigned , default = 1004949 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP14 0x28 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step14 // unsigned , default = 1056763 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP15 0x29 // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step15 // unsigned , default = 1108576 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_SCL_STEP16 0x2a // +//Bit 31:24 reserved +//Bit 23: 0 reg_vks_scl_step16 // unsigned , default = 1160389 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step + #define VKS_PPS_YCOEF00 0x2b // +//Bit 31:24 reg_vks_ycoef0 // signed , default = 0 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef1 // signed , default = 128 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef2 // signed , default = 0 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef3 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF01 0x2c // +//Bit 31:24 reg_vks_ycoef4 // signed , default = 0 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef5 // signed , default = 127 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef6 // signed , default = 1 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef7 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF02 0x2d // +//Bit 31:24 reg_vks_ycoef8 // signed , default = -1 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef9 // signed , default = 127 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef10 // signed , default = 2 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef11 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF03 0x2e // +//Bit 31:24 reg_vks_ycoef12 // signed , default = -2 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef13 // signed , default = 127 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef14 // signed , default = 3 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef15 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF04 0x2f // +//Bit 31:24 reg_vks_ycoef16 // signed , default = -3 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef17 // signed , default = 126 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef18 // signed , default = 5 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef19 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF05 0x30 // +//Bit 31:24 reg_vks_ycoef20 // signed , default = -4 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef21 // signed , default = 126 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef22 // signed , default = 6 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef23 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF06 0x31 // +//Bit 31:24 reg_vks_ycoef24 // signed , default = -5 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef25 // signed , default = 125 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef26 // signed , default = 8 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef27 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF07 0x32 // +//Bit 31:24 reg_vks_ycoef28 // signed , default = -5 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef29 // signed , default = 124 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef30 // signed , default = 9 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef31 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF08 0x33 // +//Bit 31:24 reg_vks_ycoef32 // signed , default = -6 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef33 // signed , default = 123 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef34 // signed , default = 11 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef35 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_YCOEF09 0x34 // +//Bit 31:24 reg_vks_ycoef36 // signed , default = -6 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef37 // signed , default = 122 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef38 // signed , default = 13 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef39 // signed , default = -1 poly-phase scalar coefs + #define VKS_PPS_YCOEF10 0x35 // +//Bit 31:24 reg_vks_ycoef40 // signed , default = -7 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef41 // signed , default = 121 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef42 // signed , default = 15 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef43 // signed , default = -1 poly-phase scalar coefs + #define VKS_PPS_YCOEF11 0x36 // +//Bit 31:24 reg_vks_ycoef44 // signed , default = -7 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef45 // signed , default = 119 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef46 // signed , default = 17 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef47 // signed , default = -1 poly-phase scalar coefs + #define VKS_PPS_YCOEF12 0x37 // +//Bit 31:24 reg_vks_ycoef48 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef49 // signed , default = 118 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef50 // signed , default = 19 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef51 // signed , default = -1 poly-phase scalar coefs + #define VKS_PPS_YCOEF13 0x38 // +//Bit 31:24 reg_vks_ycoef52 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef53 // signed , default = 116 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef54 // signed , default = 22 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef55 // signed , default = -2 poly-phase scalar coefs + #define VKS_PPS_YCOEF14 0x39 // +//Bit 31:24 reg_vks_ycoef56 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef57 // signed , default = 114 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef58 // signed , default = 24 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef59 // signed , default = -2 poly-phase scalar coefs + #define VKS_PPS_YCOEF15 0x3a // +//Bit 31:24 reg_vks_ycoef60 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef61 // signed , default = 112 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef62 // signed , default = 26 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef63 // signed , default = -2 poly-phase scalar coefs + #define VKS_PPS_YCOEF16 0x3b // +//Bit 31:24 reg_vks_ycoef64 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef65 // signed , default = 111 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef66 // signed , default = 29 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef67 // signed , default = -3 poly-phase scalar coefs + #define VKS_PPS_YCOEF17 0x3c // +//Bit 31:24 reg_vks_ycoef68 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef69 // signed , default = 109 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef70 // signed , default = 31 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef71 // signed , default = -3 poly-phase scalar coefs + #define VKS_PPS_YCOEF18 0x3d // +//Bit 31:24 reg_vks_ycoef72 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef73 // signed , default = 107 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef74 // signed , default = 33 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef75 // signed , default = -3 poly-phase scalar coefs + #define VKS_PPS_YCOEF19 0x3e // +//Bit 31:24 reg_vks_ycoef76 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef77 // signed , default = 104 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef78 // signed , default = 36 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef79 // signed , default = -3 poly-phase scalar coefs + #define VKS_PPS_YCOEF20 0x3f // +//Bit 31:24 reg_vks_ycoef80 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef81 // signed , default = 102 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef82 // signed , default = 39 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef83 // signed , default = -4 poly-phase scalar coefs + #define VKS_PPS_YCOEF21 0x40 // +//Bit 31:24 reg_vks_ycoef84 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef85 // signed , default = 100 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef86 // signed , default = 41 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef87 // signed , default = -4 poly-phase scalar coefs + #define VKS_PPS_YCOEF22 0x41 // +//Bit 31:24 reg_vks_ycoef88 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef89 // signed , default = 97 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef90 // signed , default = 44 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef91 // signed , default = -4 poly-phase scalar coefs + #define VKS_PPS_YCOEF23 0x42 // +//Bit 31:24 reg_vks_ycoef92 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef93 // signed , default = 95 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef94 // signed , default = 47 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef95 // signed , default = -5 poly-phase scalar coefs + #define VKS_PPS_YCOEF24 0x43 // +//Bit 31:24 reg_vks_ycoef96 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef97 // signed , default = 93 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef98 // signed , default = 49 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef99 // signed , default = -5 poly-phase scalar coefs + #define VKS_PPS_YCOEF25 0x44 // +//Bit 31:24 reg_vks_ycoef100 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef101 // signed , default = 90 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef102 // signed , default = 52 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef103 // signed , default = -5 poly-phase scalar coefs + #define VKS_PPS_YCOEF26 0x45 // +//Bit 31:24 reg_vks_ycoef104 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef105 // signed , default = 88 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef106 // signed , default = 55 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef107 // signed , default = -6 poly-phase scalar coefs + #define VKS_PPS_YCOEF27 0x46 // +//Bit 31:24 reg_vks_ycoef108 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef109 // signed , default = 85 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef110 // signed , default = 58 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef111 // signed , default = -6 poly-phase scalar coefs + #define VKS_PPS_YCOEF28 0x47 // +//Bit 31:24 reg_vks_ycoef112 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef113 // signed , default = 82 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef114 // signed , default = 60 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef115 // signed , default = -6 poly-phase scalar coefs + #define VKS_PPS_YCOEF29 0x48 // +//Bit 31:24 reg_vks_ycoef116 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef117 // signed , default = 80 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef118 // signed , default = 63 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef119 // signed , default = -7 poly-phase scalar coefs + #define VKS_PPS_YCOEF30 0x49 // +//Bit 31:24 reg_vks_ycoef120 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef121 // signed , default = 77 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef122 // signed , default = 66 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef123 // signed , default = -7 poly-phase scalar coefs + #define VKS_PPS_YCOEF31 0x4a // +//Bit 31:24 reg_vks_ycoef124 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef125 // signed , default = 74 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef126 // signed , default = 69 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef127 // signed , default = -7 poly-phase scalar coefs + #define VKS_PPS_YCOEF32 0x4b // +//Bit 31:24 reg_vks_ycoef128 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ycoef129 // signed , default = 72 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ycoef130 // signed , default = 72 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ycoef131 // signed , default = -8 poly-phase scalar coefs + #define VKS_PPS_CCOEF00 0x4c // +//Bit 31:24 reg_vks_ccoef0 // signed , default = 0 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef1 // signed , default = 128 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef2 // signed , default = 0 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef3 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF01 0x4d // +//Bit 31:24 reg_vks_ccoef4 // signed , default = 0 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef5 // signed , default = 127 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef6 // signed , default = 1 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef7 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF02 0x4e // +//Bit 31:24 reg_vks_ccoef8 // signed , default = -1 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef9 // signed , default = 127 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef10 // signed , default = 2 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef11 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF03 0x4f // +//Bit 31:24 reg_vks_ccoef12 // signed , default = -2 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef13 // signed , default = 127 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef14 // signed , default = 3 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef15 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF04 0x50 // +//Bit 31:24 reg_vks_ccoef16 // signed , default = -3 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef17 // signed , default = 126 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef18 // signed , default = 5 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef19 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF05 0x51 // +//Bit 31:24 reg_vks_ccoef20 // signed , default = -4 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef21 // signed , default = 126 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef22 // signed , default = 6 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef23 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF06 0x52 // +//Bit 31:24 reg_vks_ccoef24 // signed , default = -5 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef25 // signed , default = 125 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef26 // signed , default = 8 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef27 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF07 0x53 // +//Bit 31:24 reg_vks_ccoef28 // signed , default = -5 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef29 // signed , default = 124 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef30 // signed , default = 9 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef31 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF08 0x54 // +//Bit 31:24 reg_vks_ccoef32 // signed , default = -6 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef33 // signed , default = 123 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef34 // signed , default = 11 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef35 // signed , default = 0 poly-phase scalar coefs + #define VKS_PPS_CCOEF09 0x55 // +//Bit 31:24 reg_vks_ccoef36 // signed , default = -6 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef37 // signed , default = 122 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef38 // signed , default = 13 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef39 // signed , default = -1 poly-phase scalar coefs + #define VKS_PPS_CCOEF10 0x56 // +//Bit 31:24 reg_vks_ccoef40 // signed , default = -7 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef41 // signed , default = 121 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef42 // signed , default = 15 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef43 // signed , default = -1 poly-phase scalar coefs + #define VKS_PPS_CCOEF11 0x57 // +//Bit 31:24 reg_vks_ccoef44 // signed , default = -7 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef45 // signed , default = 119 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef46 // signed , default = 17 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef47 // signed , default = -1 poly-phase scalar coefs + #define VKS_PPS_CCOEF12 0x58 // +//Bit 31:24 reg_vks_ccoef48 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef49 // signed , default = 118 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef50 // signed , default = 19 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef51 // signed , default = -1 poly-phase scalar coefs + #define VKS_PPS_CCOEF13 0x59 // +//Bit 31:24 reg_vks_ccoef52 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef53 // signed , default = 116 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef54 // signed , default = 22 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef55 // signed , default = -2 poly-phase scalar coefs + #define VKS_PPS_CCOEF14 0x5a // +//Bit 31:24 reg_vks_ccoef56 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef57 // signed , default = 114 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef58 // signed , default = 24 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef59 // signed , default = -2 poly-phase scalar coefs + #define VKS_PPS_CCOEF15 0x5b // +//Bit 31:24 reg_vks_ccoef60 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef61 // signed , default = 112 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef62 // signed , default = 26 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef63 // signed , default = -2 poly-phase scalar coefs + #define VKS_PPS_CCOEF16 0x5c // +//Bit 31:24 reg_vks_ccoef64 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef65 // signed , default = 111 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef66 // signed , default = 29 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef67 // signed , default = -3 poly-phase scalar coefs + #define VKS_PPS_CCOEF17 0x5d // +//Bit 31:24 reg_vks_ccoef68 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef69 // signed , default = 109 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef70 // signed , default = 31 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef71 // signed , default = -3 poly-phase scalar coefs + #define VKS_PPS_CCOEF18 0x5e // +//Bit 31:24 reg_vks_ccoef72 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef73 // signed , default = 107 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef74 // signed , default = 33 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef75 // signed , default = -3 poly-phase scalar coefs + #define VKS_PPS_CCOEF19 0x5f // +//Bit 31:24 reg_vks_ccoef76 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef77 // signed , default = 104 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef78 // signed , default = 36 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef79 // signed , default = -3 poly-phase scalar coefs + #define VKS_PPS_CCOEF20 0x60 // +//Bit 31:24 reg_vks_ccoef80 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef81 // signed , default = 102 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef82 // signed , default = 39 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef83 // signed , default = -4 poly-phase scalar coefs + #define VKS_PPS_CCOEF21 0x61 // +//Bit 31:24 reg_vks_ccoef84 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef85 // signed , default = 100 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef86 // signed , default = 41 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef87 // signed , default = -4 poly-phase scalar coefs + #define VKS_PPS_CCOEF22 0x62 // +//Bit 31:24 reg_vks_ccoef88 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef89 // signed , default = 97 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef90 // signed , default = 44 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef91 // signed , default = -4 poly-phase scalar coefs + #define VKS_PPS_CCOEF23 0x63 // +//Bit 31:24 reg_vks_ccoef92 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef93 // signed , default = 95 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef94 // signed , default = 47 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef95 // signed , default = -5 poly-phase scalar coefs + #define VKS_PPS_CCOEF24 0x64 // +//Bit 31:24 reg_vks_ccoef96 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef97 // signed , default = 93 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef98 // signed , default = 49 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef99 // signed , default = -5 poly-phase scalar coefs + #define VKS_PPS_CCOEF25 0x65 // +//Bit 31:24 reg_vks_ccoef100 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef101 // signed , default = 90 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef102 // signed , default = 52 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef103 // signed , default = -5 poly-phase scalar coefs + #define VKS_PPS_CCOEF26 0x66 // +//Bit 31:24 reg_vks_ccoef104 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef105 // signed , default = 88 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef106 // signed , default = 55 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef107 // signed , default = -6 poly-phase scalar coefs + #define VKS_PPS_CCOEF27 0x67 // +//Bit 31:24 reg_vks_ccoef108 // signed , default = -9 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef109 // signed , default = 85 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef110 // signed , default = 58 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef111 // signed , default = -6 poly-phase scalar coefs + #define VKS_PPS_CCOEF28 0x68 // +//Bit 31:24 reg_vks_ccoef112 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef113 // signed , default = 82 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef114 // signed , default = 60 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef115 // signed , default = -6 poly-phase scalar coefs + #define VKS_PPS_CCOEF29 0x69 // +//Bit 31:24 reg_vks_ccoef116 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef117 // signed , default = 80 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef118 // signed , default = 63 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef119 // signed , default = -7 poly-phase scalar coefs + #define VKS_PPS_CCOEF30 0x6a // +//Bit 31:24 reg_vks_ccoef120 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef121 // signed , default = 77 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef122 // signed , default = 66 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef123 // signed , default = -7 poly-phase scalar coefs + #define VKS_PPS_CCOEF31 0x6b // +//Bit 31:24 reg_vks_ccoef124 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef125 // signed , default = 74 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef126 // signed , default = 69 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef127 // signed , default = -7 poly-phase scalar coefs + #define VKS_PPS_CCOEF32 0x6c // +//Bit 31:24 reg_vks_ccoef128 // signed , default = -8 poly-phase scalar coefs +//Bit 23:16 reg_vks_ccoef129 // signed , default = 72 poly-phase scalar coefs +//Bit 15: 8 reg_vks_ccoef130 // signed , default = 72 poly-phase scalar coefs +//Bit 7: 0 reg_vks_ccoef131 // signed , default = -8 poly-phase scalar coefs + + +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vkstone_regs.h +// +////=================================================================//// +//// vpp dither +////=================================================================//// +// 8'h20-8'h3f +// +// Reading file: vpp_dither_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define VPP_VE_DITHER_CTRL ((0x3120 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_1 ((0x3121 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_2 ((0x3122 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_3 ((0x3123 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_4 ((0x3124 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_5 ((0x3125 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_6 ((0x3126 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_7 ((0x3127 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_8 ((0x3128 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_9 ((0x3129 << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_10 ((0x312a << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_11 ((0x312b << 2) + 0xff000000) +#define VPP_VE_DITHER_LUT_12 ((0x312c << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_CTRL ((0x3130 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_1 ((0x3131 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_2 ((0x3132 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_3 ((0x3133 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_4 ((0x3134 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_5 ((0x3135 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_6 ((0x3136 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_7 ((0x3137 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_8 ((0x3138 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_9 ((0x3139 << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_10 ((0x313a << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_11 ((0x313b << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_12 ((0x313c << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_13 ((0x313d << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_14 ((0x313e << 2) + 0xff000000) +#define VPP_OSDSC_DITHER_LUT_15 ((0x313f << 2) + 0xff000000) + +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_dither_regs.h +// +// 8'h40-8'h4f +// +// Reading file: osdsc_deband_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define OSD_DB_FLT_CTRL ((0x3140 << 2) + 0xff000000) +//Bit 31:27 reserved +//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed +//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed +//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB +//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below +//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below +//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y; +//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m]) +//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6 +//Bit 16 reserved +//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6 +//Bit 12 reserved +//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6 +//Bit 8 reserved +//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma +//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma +//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma +//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma +//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +#define OSD_DB_FLT_CTRL1 ((0x3141 << 2) + 0xff000000) +//Bit 31:18 reserved +//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2 +//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8 +//Bit 11 reserved +//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6 +//Bit 7 reserved +//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6 +//Bit 3 reserved +//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6 +#define OSD_DB_FLT_LUMA_THRD ((0x3142 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 23:22 reserved +//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4 +//Bit 15:14 reserved +//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else +#define OSD_DB_FLT_CHRM_THRD ((0x3143 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 23:22 reserved +//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4 +//Bit 15:14 reserved +//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif +#define OSD_DB_FLT_RANDLUT ((0x3144 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7 +//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6 +//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5 +//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4 +//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3 +//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2 +//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1 +//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0 +#define OSD_DB_FLT_PXI_THRD ((0x3145 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise +//Bit 15:10 reserved +//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise +#define OSD_DB_FLT_SEED_Y ((0x3146 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default +#define OSD_DB_FLT_SEED_U ((0x3147 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default +#define OSD_DB_FLT_SEED_V ((0x3148 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD_DB_FLT_SEED3 ((0x3149 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD_DB_FLT_SEED4 ((0x314a << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD_DB_FLT_SEED5 ((0x314b << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +// synopsys translate_off +// synopsys translate_on +// +// Closing file: osdsc_deband_regs.h +// +//register definition for xvycc +// 8'h50-8'h7f +// +// Reading file: xvycc_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define XVYCC_INV_LUT_Y_ADDR_PORT ((0x3158 << 2) + 0xff000000) +//Bit 31:7, reserved +//Bit 6:0, xvycc_inv_lut_y_addr; +#define XVYCC_INV_LUT_Y_DATA_PORT ((0x3159 << 2) + 0xff000000) +//Bit 31:12, reserved +//Bit 11:0, xvycc_inv_lut_y_data; +#define XVYCC_INV_LUT_U_ADDR_PORT ((0x315a << 2) + 0xff000000) +//Bit 31:6, reserved +//Bit 5:0, xvycc_inv_lut_u_addr; +#define XVYCC_INV_LUT_U_DATA_PORT ((0x315b << 2) + 0xff000000) +//Bit 31:12, reserved +//Bit 11:0, xvycc_inv_lut_u_data; +#define XVYCC_INV_LUT_V_ADDR_PORT ((0x315c << 2) + 0xff000000) +//Bit 31:6, reserved +//Bit 5:0, xvycc_inv_lut_v_addr; +#define XVYCC_INV_LUT_V_DATA_PORT ((0x315d << 2) + 0xff000000) +//Bit 31:12, reserved +//Bit 11:0, xvycc_inv_lut_v_data; +#define XVYCC_LUT_R_ADDR_PORT ((0x315e << 2) + 0xff000000) +//Bit 31:7, reserved +//Bit 6:0, xvycc_lut_r_addr; +#define XVYCC_LUT_R_DATA_PORT ((0x315f << 2) + 0xff000000) +//Bit 31:10, reserved +//Bit 9:0, xvycc_lut_r_data; +#define XVYCC_LUT_G_ADDR_PORT ((0x3160 << 2) + 0xff000000) +//Bit 31:7, reserved +//Bit 6:0, xvycc_lut_g_addr; +#define XVYCC_LUT_G_DATA_PORT ((0x3161 << 2) + 0xff000000) +//Bit 31:10, reserved +//Bit 9:0, xvycc_lut_g_data; +#define XVYCC_LUT_B_ADDR_PORT ((0x3162 << 2) + 0xff000000) +//Bit 31:7, reserved +//Bit 6:0, xvycc_lut_b_addr; +#define XVYCC_LUT_B_DATA_PORT ((0x3163 << 2) + 0xff000000) +//Bit 31:10, reserved +//Bit 9:0, xvycc_lut_b_data; +#define XVYCC_INV_LUT_CTL ((0x3164 << 2) + 0xff000000) +//Bit 31:15, reserved +//Bit 14:12, reg_xvycc_cmpr_invlut_enable enable for xvycc compression inverse-lut [2] for Y, [1] for U, [0] for V default=0 +//Bit 11:10, reg_xvycc_cmpr_invlut_vscl_1 v LUT input scale for positive portion default=0 +//Bit 9: 8, reg_xvycc_cmpr_invlut_vscl_0 v LUT input scale for negative portion default=0 +//Bit 7: 6, reg_xvycc_cmpr_invlut_uscl_1 u LUT input scale for positive portion default=0 +//Bit 5: 4, reg_xvycc_cmpr_invlut_uscl_0 u LUT input scale for negative portion default=0 +//Bit 3: 2, reg_xvycc_cmpr_invlut_yscl_1 y LUT input scale for positive portion default=0 +//Bit 1: 0, reg_xvycc_cmpr_invlut_yscl_0 y LUT input scale for negative portion default=0 +#define XVYCC_LUT_CTL ((0x3165 << 2) + 0xff000000) +//Bit 31: 7, reserved +//Bit 6: 4, reg_xvycc_lut_enable LUT enable [6] for R, [5] for G, [4] for B default=0 +//Bit 3: 2, reg_xvycc_lut_scl_1 LUT input scale for positive portion default=0 +//Bit 1: 0, reg_xvycc_lut_scl_0 LUT input scale for negative portion default=0 +#define XVYCC_VADJ1_CURV_0 ((0x3166 << 2) + 0xff000000) +//Bit 31:24, vadj1_softcon_curv0_ci default=0 +//Bit 23:12, vadj1_softcon_curv0_b default=0 +//Bit 11: 0, vadj1_softcon_curv0_a default=0 +#define XVYCC_VADJ1_CURV_1 ((0x3167 << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12: 4, vadj1_softcon_curv0_g default=0 +//Bit 3, reserved +//Bit 2: 0, vadj1_softcon_curv0_cs default=0 +#define XVYCC_VADJ1_CURV_2 ((0x3168 << 2) + 0xff000000) +//Bit 31:24, vadj1_softcon_curv1_ci default=0 +//Bit 23:12, vadj1_softcon_curv1_b default=0 +//Bit 11: 0, vadj1_softcon_curv1_a default=0 +#define XVYCC_VADJ1_CURV_3 ((0x3169 << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12: 4, vadj1_softcon_curv1_g default=0 +//Bit 3, reserved +//Bit 2: 0, vadj1_softcon_curv1_cs default=0 +#define XVYCC_VADJ2_CURV_0 ((0x316a << 2) + 0xff000000) +//Bit 31:24, vadj2_softcon_curv0_ci default=0 +//Bit 23:12, vadj2_softcon_curv0_b default=0 +//Bit 11: 0, vadj2_softcon_curv0_a default=0 +#define XVYCC_VADJ2_CURV_1 ((0x316b << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12: 4, vadj2_softcon_curv0_g default=0 +//Bit 3, reserved +//Bit 2: 0, vadj2_softcon_curv0_cs default=0 +#define XVYCC_VADJ2_CURV_2 ((0x316c << 2) + 0xff000000) +//Bit 31:24, vadj2_softcon_curv1_ci default=0 +//Bit 23:12, vadj2_softcon_curv1_b default=0 +//Bit 11: 0, vadj2_softcon_curv1_a default=0 +#define XVYCC_VADJ2_CURV_3 ((0x316d << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12: 4, vadj2_softcon_curv1_g default=0 +//Bit 3, reserved +//Bit 2: 0, vadj2_softcon_curv1_cs default=0 +#define XVYCC_VD1_RGB_CTRST ((0x3170 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, reg_vd1_rgb_ctrst u12, contrast in rgb. default=1024 +//Bit 15:14, reserved +//Bit 13: 4, reg_vd1_rgb_ctrst_blklvl u10, contrast blacklevel default=64 +//Bit 3: 2, reserved +//Bit 1, reg_vd1_rgbbst_en u1, enable rgbbst default=0 +//Bit 0, reg_vd1_rgb_ctrst_prt u1, enable signal to protect saturation in rgb. default=1 +#define XVYCC_VD1_RGB_BRGHT ((0x3171 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 4, reg_vd1_rgb_brght s12, brightness level in rgb domain default=0 +//Bit 3: 2, reserved +//Bit 1, reg_vd1_rgb_brght_prt u1, enalbe signal to protect saturation in rgb default=1 +//Bit 0, reg_vd1_rgbbst_dlut_x2 u1, enable signal to do x2 to the dlut cells before subtracting default=0 +#define XVYCC_VD1_RGB_DLUT_0_3 ((0x3172 << 2) + 0xff000000) +//Bit 31:24, reg_vd1_rgbbst_dlut0 u8, default = 255 +//Bit 23:16, reg_vd1_rgbbst_dlut1 u8, default = 205 +//Bit 15: 8, reg_vd1_rgbbst_dlut2 u8, default = 171 +//Bit 7: 0, reg_vd1_rgbbst_dlut3 u8, default = 147 +#define XVYCC_VD1_RGB_DLUT_4_7 ((0x3173 << 2) + 0xff000000) +//Bit 31:24, reg_vd1_rgbbst_dlut4 u8, default = 128 +//Bit 23:16, reg_vd1_rgbbst_dlut5 u8, default = 113 +//Bit 15: 8, reg_vd1_rgbbst_dlut6 u8, default = 102 +//Bit 7: 0, reg_vd1_rgbbst_dlut7 u8, default = 93 +#define XVYCC_VD1_RGB_DLUT_8_11 ((0x3174 << 2) + 0xff000000) +//Bit 31:24, reg_vd1_rgbbst_dlut8 u8, default = 85 +//Bit 23:16, reg_vd1_rgbbst_dlut9 u8, default = 78 +//Bit 15: 8, reg_vd1_rgbbst_dlut10 u8, default = 73 +//Bit 7: 0, reg_vd1_rgbbst_dlut11 u8, default = 68 +#define XVYCC_POST_RGB_CTRST ((0x3175 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, reg_post_rgb_ctrst u12, contrast in rgb. default=1024 +//Bit 15:14, reserved +//Bit 13: 4, reg_post_rgb_ctrst_blklvl u10, contrast blacklevel default=64 +//Bit 3: 2, reserved +//Bit 1, reg_post_rgbbst_en u1, enable rgbbst default=0 +//Bit 0, reg_post_rgb_ctrst_prt u1, enable signal to protect saturation in rgb. default=1 +#define XVYCC_POST_RGB_BRGHT ((0x3176 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 4, reg_post_rgb_brght s12, brightness level in rgb domain default=0 +//Bit 3: 2, reserved +//Bit 1, reg_post_rgb_brght_prt u1, enalbe signal to protect saturation in rgb default=1 +//Bit 0, reg_post_rgbbst_dlut_x2 u1, enable signal to do x2 to the dlut cells before subtracting default=0 +#define XVYCC_POST_RGB_DLUT_0_3 ((0x3177 << 2) + 0xff000000) +//Bit 31:24, reg_post_rgbbst_dlut0 u8, default = 255 +//Bit 23:16, reg_post_rgbbst_dlut1 u8, default = 205 +//Bit 15: 8, reg_post_rgbbst_dlut2 u8, default = 171 +//Bit 7: 0, reg_post_rgbbst_dlut3 u8, default = 147 +#define XVYCC_POST_RGB_DLUT_4_7 ((0x3178 << 2) + 0xff000000) +//Bit 31:24, reg_post_rgbbst_dlut4 u8, default = 128 +//Bit 23:16, reg_post_rgbbst_dlut5 u8, default = 113 +//Bit 15: 8, reg_post_rgbbst_dlut6 u8, default = 102 +//Bit 7: 0, reg_post_rgbbst_dlut7 u8, default = 93 +#define XVYCC_POST_RGB_DLUT_8_11 ((0x3179 << 2) + 0xff000000) +//Bit 31:24, reg_post_rgbbst_dlut8 u8, default = 85 +//Bit 23:16, reg_post_rgbbst_dlut9 u8, default = 78 +//Bit 15: 8, reg_post_rgbbst_dlut10 u8, default = 73 +//Bit 7: 0, reg_post_rgbbst_dlut11 u8, default = 68 +#define ADAPTIVE_SCALE_REG0 ((0x3150 << 2) + 0xff000000) +//Bit 31, reg_adaptive_scale_enable u1, default = 1 +//Bit 27:16, reg_adpscl_ys_coef_0 u12, default = 538 +//Bit 11: 0, reg_adpscl_ys_coef_1 u12, default = 1389 +#define ADAPTIVE_SCALE_REG1 ((0x3151 << 2) + 0xff000000) +//Bit 27:16, reg_adpscl_ys_coef_2 u12, default = 121 +//Bit 11: 0, reg_adpscl_alpha_0 u12, default = 1024 +#define ADAPTIVE_SCALE_REG2 ((0x3152 << 2) + 0xff000000) +//Bit 27:16, reg_adpscl_alpha_1 u12, default = 1024 +//Bit 11: 0, reg_adpscl_alpha_2 u12, default = 1024 +#define ADAPTIVE_SCALE_REG3 ((0x3153 << 2) + 0xff000000) +//Bit 31:16, reg_adpscl_beta_0 u16, default = 0 +//Bit 15: 0, reg_adpscl_beta_1 u16, default = 0 +#define ADAPTIVE_SCALE_REG4 ((0x3154 << 2) + 0xff000000) +//Bit 31:16, reg_adpscl_beta_2 u16, default = 0 +#define ADAPTIVE_SCALE_ADDR ((0x3155 << 2) + 0xff000000) +//Bit 6:0, reg_lut_addr u7, default = 0 +#define ADAPTIVE_SCALE_DATA ((0x3156 << 2) + 0xff000000) +//Bit 11:0, reg_lut_data u12, default = 0 +// synopsys translate_off +// synopsys translate_on +// +// Closing file: xvycc_regs.h +// +//register definition for vd2 afbc dec +// 8'h80-8'h9f +// +// Reading file: vd2_afbc_dec_regs.h +// +// synopsys translate_off +// synopsys translate_on +////===============================//// +//// reg +////===============================//// +#define VD2_AFBC_ENABLE ((0x3180 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0 +//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size +//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable +//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb +//Bit 19, reg_dos_uncomp_mode unsigned , default = 0 +//Bit 18:16, soft_rst unsigned , default = 4 +//Bit 15:14, reserved +//Bit 13:12, ddr_blk_size unsigned , default = 1 +//Bit 11:9, cmd_blk_size unsigend , default = 3 +//Bit 8, dec_enable unsigned , default = 0 +//Bit 7:2, reserved +//Bit 1, head_len_sel unsigned , default = 1 +//Bit 0, dec_frm_start unsigned , default = 0 +#define VD2_AFBC_MODE ((0x3181 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size; +//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size +//Bit 27:26, rev_mode uns, default = 0 , reverse mode +//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent +//Bit 23, reserved +//Bit 22:16, hold_line_num uns, default = 4 , +//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4 +//Bit 13:8, compbits_yuv uns, default = 0 , +// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +#define VD2_AFBC_SIZE_IN ((0x3182 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel +#define VD2_AFBC_DEC_DEF_COLOR ((0x3183 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value +//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value +//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value +#define VD2_AFBC_CONV_CTRL ((0x3184 << 2) + 0xff000000) +//Bit 31:14, reserved +//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420 +//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n +#define VD2_AFBC_LBUF_DEPTH ((0x3185 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel +//Bit 15:12, reserved +//Bit 11:0, mif_lbuf_depth uns, default = 128; +#define VD2_AFBC_HEAD_BADDR ((0x3186 << 2) + 0xff000000) +//Bit 31:0, mif_info_baddr uns, default = 32'h0; +#define VD2_AFBC_BODY_BADDR ((0x3187 << 2) + 0xff000000) +//Bit 31:0, mif_data_baddr uns, default = 32'h00010000; +#define VD2_AFBC_SIZE_OUT ((0x3188 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel +#define VD2_AFBC_OUT_YSCOPE ((0x3189 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel +//Bit 15:13, reserved +//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel +#define VD2_AFBC_STAT ((0x318a << 2) + 0xff000000) +//Bit 31:0, ro_dbg_top_info uns +#define VD2_AFBC_VD_CFMT_CTRL ((0x318b << 2) + 0xff000000) +//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock +//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit +//Bit 29 reserved +//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation +//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase +//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable +//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 +//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable +//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always +// repeat data, no interpolation +//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line +//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable +//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable +//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning +//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase +//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4) +//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable +#define VD2_AFBC_VD_CFMT_W ((0x318c << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width +//Bit 15:13 reserved +//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width +#define VD2_AFBC_MIF_HOR_SCOPE ((0x318d << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor +//Bit 15:10, reserved +//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor +#define VD2_AFBC_MIF_VER_SCOPE ((0x318e << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver +//Bit 15:12, reserved +//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver +#define VD2_AFBC_PIXEL_HOR_SCOPE ((0x318f << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel +//Bit 15:13, reserved +//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel +#define VD2_AFBC_PIXEL_VER_SCOPE ((0x3190 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel +//Bit 15:13, reserved +//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel +#define VD2_AFBC_VD_CFMT_H ((0x3191 << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height +#define VD2_AFBCDEC_IQUANT_ENABLE ((0x3192 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11 reg_quant_expand_en_1 //unsigned, RW, enable for quantization value expansion +//Bit 10 reg_quant_expand_en_0 //unsigned, RW, enable for quantization value expansion +//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1; +//Bit 7: 5 reserved +//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy +//Bit 3: 1 reserved +//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy +#define VD2_AFBCDEC_IQUANT_LUT_1 ((0x3193 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define VD2_AFBCDEC_IQUANT_LUT_2 ((0x3194 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define VD2_AFBCDEC_IQUANT_LUT_3 ((0x3195 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define VD2_AFBCDEC_IQUANT_LUT_4 ((0x3196 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vd2_afbc_dec_regs.h +// +//register definition for osd1 afbcd dec +// 8'ha0-8'haf +// +// Reading file: osd1_afbcd_regs.h +// +// synopsys translate_off +// synopsys translate_on +////===============================//// +//// reg +////===============================//// +#define OSD1_AFBCD_ENABLE ((0x31a0 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:9, id_fifo_thrd unsigned , default = 64, axi id fifo threshold +//Bit 8, dec_enable unsigned , default = 0 +//Bit 7:1, reserved +//Bit 0, frm_start unsigned , default = 0 +#define OSD1_AFBCD_MODE ((0x31a1 << 2) + 0xff000000) +//Bit 31, soft_reset the use as go_field +//Bit 30:29, reserved +//Bit 28, axi_reorder_mode default=0, the axi reorder mode, note : don't seting +//Bit 27:26, reserved +//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent +//Bit 22:16, hold_line_num +//Bit 15:8, rgba_exchan_ctrl +//Bit 7, reserved +//Bit 6, hreg_block_split uns, default = 1 , Enable/disable block split mode in sparse allocation +//Bit 5, hreg_half_block uns, default = 1 , Enable/disable half block decoding. 1=half block, 0=full block +//Bit 4:0, hreg_pixel_packing_fmt uns, default = 5 , Pixel format +#define OSD1_AFBCD_SIZE_IN ((0x31a2 << 2) + 0xff000000) +//Bit 31:16 hreg_hsize_in uns, default = 1920 , pic horz size in unit: pixel +//Bit 15:0, hreg_vsize_in uns, default = 1080 , pic vert size in unit: pixel +#define OSD1_AFBCD_HDR_PTR ((0x31a3 << 2) + 0xff000000) +//Bit 31:0 hreg_hdr_ptr uns, default = 0 , +#define OSD1_AFBCD_FRAME_PTR ((0x31a4 << 2) + 0xff000000) +//Bit 31:0 hreg_frame_ptr uns, default = 0 , The start address of the target frame buffer. +// For YUV format, this pointer specifies the luma buffer. +#define OSD1_AFBCD_CHROMA_PTR ((0x31a5 << 2) + 0xff000000) +//Bit 31:0 hreg_chroma_ptr uns, default = 0 , Only valid in YUV format, to specify the target chroma buffer. +#define OSD1_AFBCD_CONV_CTRL ((0x31a6 << 2) + 0xff000000) +//Bit 31:15, reserved +//Bit 15: 0, conv_lbuf_len uns, default = 1024, unit=16 pixel need to set = 2^n +#define OSD1_AFBCD_STATUS ((0x31a8 << 2) + 0xff000000) +//Bit 30:4, reserved +//Bit 3, hreg_dec_resp uns, default = 0 , Decoder error flage from the dec4x4 core +//Bit 2, hreg_axi_bresp uns, default = 0 , Bus error flag for AXI write error +//Bit 1, hreg_axi_rresp uns, default = 0 , Bus error flag for AXI read error +//Bit 0, hreg_idle_n uns, default = 0 , Idle output, value 0 indicates the standalone decoder is free now and can start the next frame. +#define OSD1_AFBCD_PIXEL_HSCOPE ((0x31a9 << 2) + 0xff000000) +//Bit 31:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel +//Bit 15: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel +#define OSD1_AFBCD_PIXEL_VSCOPE ((0x31aa << 2) + 0xff000000) +//Bit 31:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel +//Bit 15: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel +// synopsys translate_off +// synopsys translate_on +// +// Closing file: osd1_afbcd_regs.h +// +//register definition for osd1 afbcd dec +// 8'hb0-8'hca +// +// Reading file: vpp_vmx_wm_regs.h +// +//// synopsys translate_off +//`ifdef VPP_WM_REGS_H +//`else +// `define VPP_WM_REGS_H +//// synopsys translate_on +#define WM_CTRL ((0x31b0 << 2) + 0xff000000) +//Bit 31, int_mask default = 0 +//Bit 30:16, reserved +//Bit 15:8, strength_multiply default =1 +//Bit 7:6, reserved +//Bit 5, shift_en default = 0 +//Bit 4, background_embedding_on default =0 +//Bit 3, mark_en default =0 +//Bit 2, noise_en default =0 +//Bit 1, blend_en default =0 +//Bit 0, wm_en default =0 +#define WM_SPACE_RESOLUTION ((0x31b1 << 2) + 0xff000000) +//Bit 31:25, reserved +//Bit 24:16, spacing_horz default =10 +//Bit 15:9, reserved +//Bit 8:0, spacing_vert default =12 +#define WM_SYMBOLS_NUM ((0x31b2 << 2) + 0xff000000) +//Bit 31:8, reserved +//Bit 7:4, symbols_cols 1~10; default =5 +//Bit 3:0, symbols_rows 1~10; default =2 +#define WM_MARK_RESOLUTION ((0x31b3 << 2) + 0xff000000) +//Bit 31:20, mark_hsize mark_buffer_width; default =1820 +//Bit 19:8, mark_vsize mark_buffer_height; default =1820 t =780 +//Bit 7:6, reserved +//Bit 5:0, scale default =13 // scale up +#define WM_FREQ_DIST_LEFT ((0x31b4 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:0, freq_dist_left default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist +#define WM_FREQ_DIST_RIGHT ((0x31b5 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:0, freq_dist_right default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist +#define WM_FREQ_DIST_TOP ((0x31b6 << 2) + 0xff000000) +//Bit 31:21, reserved +//Bit 20:0, freq_dist_top default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist +#define WM_SYMBOLS_XPOS ((0x31b7 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, symbols_xpos_start default =1536 // SYMBOLS_XPOS * h_res +//Bit 15:13, reserved +//Bit 12:0, symbols_xpos_end default =3356 // SYMBOLS_XPOS * h_res + mark_hsize +#define WM_SYMBOLS_YPOS ((0x31b8 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, symbols_ypos_start default =756 // SYMBOLS_yPOS * y_res +//Bit 15:13, reserved +//Bit 12:0, symbols_ypos_end default =1536 // SYMBOLS_yPOS * y_res + mark_vsize +#define WM_STORAGE_SETTING ((0x31b9 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, direction_max default = 80 +//Bit 15, reserved +//Bit 14:8, storage_s default =18 // biggest is 72 S +//Bit 7, reserved +//Bit 6:0, storage_max_distance default =36 // biggest is 72 max_distance +#define WM_VIDEO_RESOLUTION ((0x31ba << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, h_res default =3840 // video hsize +//Bit 15:13, reserved +//Bit 12:0, v_res default =2160 // video vsize +#define WM_EMBEDDING_STRENGTH_THRESHOLD0 ((0x31bb << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_0 default =48 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_1 default =60 +#define WM_EMBEDDING_STRENGTH_THRESHOLD1 ((0x31bc << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_2 default = 68 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_3 default = 80 +#define WM_EMBEDDING_STRENGTH_THRESHOLD2 ((0x31bd << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_4 default = 88 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_5 default = 96 +#define WM_EMBEDDING_STRENGTH_THRESHOLD3 ((0x31be << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_6 default = 100 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_7 default = 108 +#define WM_EMBEDDING_STRENGTH_THRESHOLD4 ((0x31bf << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_8 default = 112 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_9 default = 116 +#define WM_EMBEDDING_STRENGTH_THRESHOLD5 ((0x31c0 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_10 default = 120 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_11 default = 124 +#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG0 ((0x31c1 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_bg_0 default =320 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_bg_1 default = 328 +#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG1 ((0x31c2 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_bg_2 default = 332 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_bg_3 default = 340 +#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG2 ((0x31c3 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_bg_4 default = 344 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_bg_5 default = 348 +#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG3 ((0x31c4 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_bg_6 default = 352 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_bg_7 default = 356 +#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG4 ((0x31c5 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_bg_8 default = 360 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_bg_9 default = 368 +#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG5 ((0x31c6 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, embedding_strength_threshold_bg_10 default = 372 +//Bit 15:12, reserved +//Bit 11:0, embedding_strength_threshold_bg_11 default = 380 +#define WM_AM_LUT_DATA_PORT ((0x31c7 << 2) + 0xff000000) +#define WM_AM_LUT_ADDR_PORT ((0x31c8 << 2) + 0xff000000) +#define WM_STATUS_RO ((0x31c9 << 2) + 0xff000000) +//Bit 31, ro_resolution_changed +//Bit 30:29, reserved +//Bit 30:16, ro_hsize_in +//Bit 15:13, reserved +//Bit 8:0, ro_vsize_in +#define WM_STATUS_RAM_RO ((0x31ca << 2) + 0xff000000) +//Bit 31:9, reserved +//Bit 8:0, ro_ram_addr +#define WM_THRES_ADDR_PORT ((0x31cb << 2) + 0xff000000) +#define WM_THRES_DATA_PORT ((0x31cd << 2) + 0xff000000) +// +// Closing file: vpp_vmx_wm_regs.h +// +// +// Reading file: ngptv_reg.h +// +//// synopsys translate_off +//`ifdef VPP_WM_REGS_H +//`else +// `define VPP_WM_REGS_H +//// synopsys translate_on +#define REG_NGPTV_CTRL0 ((0x31ab << 2) + 0xff000000) +//Bit 31:25, reserved +//Bit 24, bypass_latch +//Bit 23, count_enable deafult=1 +//Bit 22, soft_rst +//Bit 21, count_rst +//Bit 20, bypass run +//Bit 19:14, ochannel_sel deafult=0x24 +//Bit 13:8, ichannel_sel deafult=0x24 +//Bit 3, 8bit mode +//Bit 2, 10bit mode +//Bit 1, reg_sync enable +//Bit 0, bypass +#define REG_NGPTV_CTRL1 ((0x31ac << 2) + 0xff000000) +//Bit 31:7 reserved +//Bit 6 reset sw default=0 +//Bit 5:0 gclk_ctrl +#define REG_NGPTV_CTRL2 ((0x31ad << 2) + 0xff000000) +//Bit 31:8 reserved +//Bit 7 SpareIn +//Bit 6 NG_EnableServiceIn +//Bit 5:4 reserved +//Bit 3 NG_DebugEnableIn +//Bit 2 reserved +//Bit 1 NG_Payload24_56n +//Bit 0 NG_YUVnRGBIn +#define REG_NGPTV_CTRL3 ((0x31ce << 2) + 0xff000000) +//Bit 31:0 NG_KeyIn default=0x01ac7f33 +#define REG_NGPTV_CTRL4 ((0x31cf << 2) + 0xff000000) +//Bit 31:0 NG_PayloadDataIn[31:0] default=0x6789abcd +#define REG_NGPTV_CTRL5 ((0x31f0 << 2) + 0xff000000) +//Bit 31:26 Reserved +//Bit 25:24 NG_FrameTypeIn default=3 +//Bit 23:0 NG_PayloadDataIn default=0x012345 +#define REG_NGPTV_CTRL6 ((0x31f1 << 2) + 0xff000000) +//Bit 31:0 NG_SettingIn[31:0] default=0x18c6318c +#define REG_NGPTV_CTRL7 ((0x31f2 << 2) + 0xff000000) +//Bit 31:0 NG_SettingIn[63:32] default=0x84210842 +#define REG_NGPTV_CTRL8 ((0x31f3 << 2) + 0xff000000) +//Bit 31:0 NG_SettingIn[95:64] default=0x21084210 +#define REG_NGPTV_CTRL9 ((0x31f4 << 2) + 0xff000000) +//Bit 31:0 NG_SettingIn[127:96] default=0x8c631084 +#define REG_NGPTV_CTRL10 ((0x31f5 << 2) + 0xff000000) +//Bit 31:0 NG_SettingIn[159:128] default=0x84210631 +#define REG_NGPTV_CTRL11 ((0x31f6 << 2) + 0xff000000) +//Bit 31:16 Reserved +//Bit 15:8 NG_FrameRateIn default=0x18 +//Bit 7 Reserved +//Bit 6:5 NG_CoreIDIn default=0 +//Bit 4:0 NG_SettingIn[165:160] default=0x10 +#define REG_NGPTV_CTRL12 ((0x31f7 << 2) + 0xff000000) +//Bit 31:29 Reserved +//Bit 28:16 vsize default=0x438 +//Bit 16:13 Reserved +//Bit 12:0 hsize default=0x780 +#define REG_NGPTV_CTRL13 ((0x31f8 << 2) + 0xff000000) +//Bit 31:29 Reserved +//Bit 28:16 reg_vphstart default=0x0 +//Bit 16:13 Reserved +//Bit 12:0 reg_vphend default=0x437 +#define REG_NGPTV_CTRL14 ((0x31f9 << 2) + 0xff000000) +//Bit 31:13 Reserved +//Bit 12:0 reg_3d_right_st default=0x3c0 +#define REG_NGPTV_CTRL15 ((0x31fa << 2) + 0xff000000) +//Bit 31:29 Reserved +//Bit 28:16 reg_vpvstart0 default=0x0 +//Bit 16:13 Reserved +//Bit 12:0 reg_vpvend0 default=0x437 +#define REG_NGPTV_CTRL16 ((0x31fb << 2) + 0xff000000) +//Bit 31:29 Reserved +//Bit 28:16 reg_vpvstart1 default=0 +//Bit 16:13 Reserved +//Bit 12:0 reg_vpvend1 default=0 +#define REG_NGPTV_CTRL17 ((0x31fc << 2) + 0xff000000) +//Bit 31:29 Reserved +//Bit 28:16 reg_vpvstart2 default=0 +//Bit 16:13 Reserved +//Bit 12:0 reg_vpvend2 default=0 +#define REG_NGPTV_CTRL18 ((0x31fd << 2) + 0xff000000) +//Bit 31:29 Reserved +//Bit 28:16 reg_vpvstart3 default=0 +//Bit 16:13 Reserved +//Bit 12:0 reg_vpvend3 default=0 +#define RO_NGPTV_CTRL19 ((0x31fe << 2) + 0xff000000) +//Bit 31 dat_val_in +//Bit 30 in_hold +//Bit 29 out_hold +//Bit 28:16 vcnt +//Bit 15:12 NG_ErrorOut +//Bit 11:0 NG_VersionOut +// +// Closing file: ngptv_reg.h +// +// 8'hd0-8hef +// +// Reading file: bt2020_regs.h +// +// synopsys translate_off +// synopsys translate_on +//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3 +//Bit 17:6 for clock gating +//Bit 5:4 pscale_mode ch2 +//Bit 3:2 pscale_mode ch1 +//Bit 1:0 pscale_mode ch0 +#define VPP_EOTF_CTL ((0x31d0 << 2) + 0xff000000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define VPP_EOTF_COEF00_01 ((0x31d1 << 2) + 0xff000000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define VPP_EOTF_COEF02_10 ((0x31d2 << 2) + 0xff000000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define VPP_EOTF_COEF11_12 ((0x31d3 << 2) + 0xff000000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define VPP_EOTF_COEF20_21 ((0x31d4 << 2) + 0xff000000) +//Bit 28:16 coef22 +//Bit 2:0 coef_rs +#define VPP_EOTF_COEF22_RS ((0x31d5 << 2) + 0xff000000) +#define VPP_EOTF_LUT_ADDR_PORT ((0x31d6 << 2) + 0xff000000) +#define VPP_EOTF_LUT_DATA_PORT ((0x31d7 << 2) + 0xff000000) +#define VPP_EOTF_3X3_OFST_0 ((0x31d8 << 2) + 0xff000000) +#define VPP_EOTF_3X3_OFST_1 ((0x31d9 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: bt2020_regs.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_partb_reg.h +// +// ----------------------------------------------- +// REG_BASE: VPPD_VCBUS_BASE = 0x32 +// ----------------------------------------------- +// +// Reading file: vpp_vadj_regs.h +// +// synopsys translate_off +// synopsys translate_on +//------------------------------------------------------------------------------ +// VD1 path +//------------------------------------------------------------------------------ +//`define VD1_IF0_GEN_REG 8'h0 +//`define VD1_IF0_CANVAS0 8'h1 +//`define VD1_IF0_CANVAS1 8'h2 +//`define VD1_IF0_LUMA_X0 8'h3 +//`define VD1_IF0_LUMA_Y0 8'h4 +//`define VD1_IF0_CHROMA_X0 8'h5 +//`define VD1_IF0_CHROMA_Y0 8'h6 +//`define VD1_IF0_LUMA_X1 8'h7 +//`define VD1_IF0_LUMA_Y1 8'h8 +//`define VD1_IF0_CHROMA_X1 8'h9 +//`define VD1_IF0_CHROMA_Y1 8'ha +//`define VD1_IF0_RPT_LOOP 8'hb +//`define VD1_IF0_LUMA0_RPT_PAT 8'hc +//`define VD1_IF0_CHROMA0_RPT_PAT 8'hd +//`define VD1_IF0_LUMA1_RPT_PAT 8'he +//`define VD1_IF0_CHROMA1_RPT_PAT 8'hf +//`define VD1_IF0_LUMA_PSEL 8'h10 +//`define VD1_IF0_CHROMA_PSEL 8'h11 +//`define VD1_IF0_DUMMY_PIXEL 8'h12 +//`define VD1_IF0_LUMA_FIFO_SIZE 8'h13 +//`define VD1_IF0_AXI_CMD_CNT 8'h14 +//`define VD1_IF0_AXI_RDAT_CNT 8'h15 +//`define VD1_IF0_GEN_REG3 8'h16 +//Bit 31 it true, disable clock, otherwise enable clock +//Bit 30 soft rst bit +//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation +//Bit 27:24 horizontal formatter initial phase +//Bit 23 horizontal formatter repeat pixel 0 enable +//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 +//Bit 20 horizontal formatter enable +//Bit 19 if true, always use phase0 while vertical formater, meaning always +// repeat data, no interpolation +//Bit 18 if true, disable vertical formatter chroma repeat last line +//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable +//Bit 16 veritcal formatter repeat line 0 enable +//Bit 15:12 vertical formatter skip line num at the beginning +//Bit 11:8 vertical formatter initial phase +//Bit 7:1 vertical formatter phase step (3.4) +//Bit 0 vertical formatter enable +//`define VIU_VD1_FMT_CTRL 8'h18 //29'h0 +//Bit 27:16 horizontal formatter width +//Bit 11:0 vertical formatter width +//`define VIU_VD1_FMT_W 8'h19 //28'h0 +//`define VD1_IF0_RANGE_MAP_Y 8'h1a +//`define VD1_IF0_RANGE_MAP_CB 8'h1b +//`define VD1_IF0_RANGE_MAP_CR 8'h1c +//`define VD1_IF0_GEN_REG2 8'h1d +//`define VD1_IF0_PROT_CNTL 8'h1e +//`define VD1_IF0_URGENT_CTRL 8'h1f +//------------------------------------------------------------------------------ +// VD2 path +//------------------------------------------------------------------------------ +//`define VD2_IF0_GEN_REG 8'h20 +//`define VD2_IF0_CANVAS0 8'h21 +//`define VD2_IF0_CANVAS1 8'h22 +//`define VD2_IF0_LUMA_X0 8'h23 +//`define VD2_IF0_LUMA_Y0 8'h24 +//`define VD2_IF0_CHROMA_X0 8'h25 +//`define VD2_IF0_CHROMA_Y0 8'h26 +//`define VD2_IF0_LUMA_X1 8'h27 +//`define VD2_IF0_LUMA_Y1 8'h28 +//`define VD2_IF0_CHROMA_X1 8'h29 +//`define VD2_IF0_CHROMA_Y1 8'h2a +//`define VD2_IF0_RPT_LOOP 8'h2b +//`define VD2_IF0_LUMA0_RPT_PAT 8'h2c +//`define VD2_IF0_CHROMA0_RPT_PAT 8'h2d +//`define VD2_IF0_LUMA1_RPT_PAT 8'h2e +//`define VD2_IF0_CHROMA1_RPT_PAT 8'h2f +//`define VD2_IF0_LUMA_PSEL 8'h30 +//`define VD2_IF0_CHROMA_PSEL 8'h31 +//`define VD2_IF0_DUMMY_PIXEL 8'h32 +//`define VD2_IF0_LUMA_FIFO_SIZE 8'h33 +//`define VD2_IF0_AXI_CMD_CNT 8'h34 +//`define VD2_IF0_AXI_RDAT_CNT 8'h35 +//`define VD2_IF0_GEN_REG3 8'h36 +//Bit 31 it true, disable clock, otherwise enable clock +//Bit 30 soft rst bit +//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation +//Bit 27:24 horizontal formatter initial phase +//Bit 23 horizontal formatter repeat pixel 0 enable +//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 +//Bit 20 horizontal formatter enable +//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable +//Bit 16 veritcal formatter repeat line 0 enable +//Bit 15:12 vertical formatter skip line num at the beginning +//Bit 11:8 vertical formatter initial phase +//Bit 7:1 vertical formatter phase step (3.4) +//Bit 0 vertical formatter enable +//`define VIU_VD2_FMT_CTRL 8'h38 //29'h0 +//Bit 27:16 horizontal formatter width +//Bit 11:0 vertical formatter width +//`define VIU_VD2_FMT_W 8'h39 //28'h0 +//`define VD2_IF0_RANGE_MAP_Y 8'h3a +//`define VD2_IF0_RANGE_MAP_CB 8'h3b +//`define VD2_IF0_RANGE_MAP_CR 8'h3c +//`define VD2_IF0_GEN_REG2 8'h3d +//`define VD2_IF0_PROT_CNTL 8'h3e +//`define VD2_IF0_URGENT_CTRL 8'h3f +#define VPP_VADJ1_MISC ((0x3280 << 2) + 0xff000000) +#define VPP_VADJ1_BLACK_VAL ((0x3281 << 2) + 0xff000000) +#define VPP_VADJ1_Y ((0x3282 << 2) + 0xff000000) +#define VPP_VADJ1_MA_MB ((0x3283 << 2) + 0xff000000) +#define VPP_VADJ1_MC_MD ((0x3284 << 2) + 0xff000000) +#define VPP_VADJ1_CURV_0 ((0x3285 << 2) + 0xff000000) +#define VPP_VADJ1_CURV_1 ((0x3286 << 2) + 0xff000000) +#define VPP_VADJ1_CURV_2 ((0x3287 << 2) + 0xff000000) +#define VPP_VADJ1_CURV_3 ((0x3288 << 2) + 0xff000000) +#define VPP_VD1_RGB_CTRST ((0x3289 << 2) + 0xff000000) +#define VPP_VD1_RGB_BRGHT ((0x328a << 2) + 0xff000000) +#define VPP_VD1_RGB_DLUT_0_3 ((0x328b << 2) + 0xff000000) +#define VPP_VD1_RGB_DLUT_4_7 ((0x328c << 2) + 0xff000000) +#define VPP_VD1_RGB_DLUT_8_11 ((0x328d << 2) + 0xff000000) +#define VPP_VD1_MATRIX_COEF00_01 ((0x3290 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_COEF02_10 ((0x3291 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_COEF11_12 ((0x3292 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_COEF20_21 ((0x3293 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_COEF22 ((0x3294 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_COEF13_14 ((0x3295 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_COEF23_24 ((0x3296 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_COEF15_25 ((0x3297 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_CLIP ((0x3298 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_OFFSET0_1 ((0x3299 << 2) + 0xff000000) +#define VPP_VD1_MATRIX_OFFSET2 ((0x329a << 2) + 0xff000000) +#define VPP_VD1_MATRIX_PRE_OFFSET0_1 ((0x329b << 2) + 0xff000000) +#define VPP_VD1_MATRIX_PRE_OFFSET2 ((0x329c << 2) + 0xff000000) +#define VPP_VD1_MATRIX_EN_CTRL ((0x329d << 2) + 0xff000000) +#define VPP_VADJ2_MISC ((0x32a0 << 2) + 0xff000000) +#define VPP_VADJ2_BLACK_VAL ((0x32a1 << 2) + 0xff000000) +#define VPP_VADJ2_Y ((0x32a2 << 2) + 0xff000000) +#define VPP_VADJ2_MA_MB ((0x32a3 << 2) + 0xff000000) +#define VPP_VADJ2_MC_MD ((0x32a4 << 2) + 0xff000000) +#define VPP_VADJ2_CURV_0 ((0x32a5 << 2) + 0xff000000) +#define VPP_VADJ2_CURV_1 ((0x32a6 << 2) + 0xff000000) +#define VPP_VADJ2_CURV_2 ((0x32a7 << 2) + 0xff000000) +#define VPP_VADJ2_CURV_3 ((0x32a8 << 2) + 0xff000000) +#define VPP_POST_RGB_CTRST ((0x32a9 << 2) + 0xff000000) +#define VPP_POST_RGB_BRGHT ((0x32aa << 2) + 0xff000000) +#define VPP_POST_RGB_DLUT_0_3 ((0x32ab << 2) + 0xff000000) +#define VPP_POST_RGB_DLUT_4_7 ((0x32ac << 2) + 0xff000000) +#define VPP_POST_RGB_DLUT_8_11 ((0x32ad << 2) + 0xff000000) +#define VPP_POST_MATRIX_COEF00_01 ((0x32b0 << 2) + 0xff000000) +#define VPP_POST_MATRIX_COEF02_10 ((0x32b1 << 2) + 0xff000000) +#define VPP_POST_MATRIX_COEF11_12 ((0x32b2 << 2) + 0xff000000) +#define VPP_POST_MATRIX_COEF20_21 ((0x32b3 << 2) + 0xff000000) +#define VPP_POST_MATRIX_COEF22 ((0x32b4 << 2) + 0xff000000) +#define VPP_POST_MATRIX_COEF13_14 ((0x32b5 << 2) + 0xff000000) +#define VPP_POST_MATRIX_COEF23_24 ((0x32b6 << 2) + 0xff000000) +#define VPP_POST_MATRIX_COEF15_25 ((0x32b7 << 2) + 0xff000000) +#define VPP_POST_MATRIX_CLIP ((0x32b8 << 2) + 0xff000000) +#define VPP_POST_MATRIX_OFFSET0_1 ((0x32b9 << 2) + 0xff000000) +#define VPP_POST_MATRIX_OFFSET2 ((0x32ba << 2) + 0xff000000) +#define VPP_POST_MATRIX_PRE_OFFSET0_1 ((0x32bb << 2) + 0xff000000) +#define VPP_POST_MATRIX_PRE_OFFSET2 ((0x32bc << 2) + 0xff000000) +#define VPP_POST_MATRIX_EN_CTRL ((0x32bd << 2) + 0xff000000) +#define VPP_VD1_MATRIX_SAT ((0x32c0 << 2) + 0xff000000) +#define VPP_POST_MATRIX_SAT ((0x32c1 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_vadj_regs.h +// +// ----------------------------------------------- +// REG_BASE: DOLBY1A_VCBUS_BASE = 0x33 +// ----------------------------------------------- +// +// Reading file: dolby1a_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DOLBY_CORE1A_REG_START ((0x3300 << 2) + 0xff000000) +#define DOLBY_CORE1A_CLKGATE_CTRL ((0x33f2 << 2) + 0xff000000) +#define DOLBY_CORE1A_SWAP_CTRL0 ((0x33f3 << 2) + 0xff000000) +#define DOLBY_CORE1A_SWAP_CTRL1 ((0x33f4 << 2) + 0xff000000) +#define DOLBY_CORE1A_SWAP_CTRL2 ((0x33f5 << 2) + 0xff000000) +#define DOLBY_CORE1A_SWAP_CTRL3 ((0x33f6 << 2) + 0xff000000) +#define DOLBY_CORE1A_SWAP_CTRL4 ((0x33f7 << 2) + 0xff000000) +#define DOLBY_CORE1A_SWAP_CTRL5 ((0x33f8 << 2) + 0xff000000) +#define DOLBY_CORE1A_DMA_CTRL ((0x33f9 << 2) + 0xff000000) +#define DOLBY_CORE1A_DMA_STATUS ((0x33fa << 2) + 0xff000000) +#define DOLBY_CORE1A_STATUS0 ((0x33fb << 2) + 0xff000000) +#define DOLBY_CORE1A_STATUS1 ((0x33fc << 2) + 0xff000000) +#define DOLBY_CORE1A_STATUS2 ((0x33fd << 2) + 0xff000000) +#define DOLBY_CORE1A_STATUS3 ((0x33fe << 2) + 0xff000000) +#define DOLBY_CORE1A_DMA_PORT ((0x33ff << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: dolby1a_regs.h +// +// ----------------------------------------------- +// REG_BASE: DOLBY2A_VCBUS_BASE = 0x34 +// ----------------------------------------------- +// +// Reading file: dolby2a_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DOLBY_CORE2A_REG_START ((0x3400 << 2) + 0xff000000) +#define DOLBY_CORE2A_CTRL ((0x3401 << 2) + 0xff000000) +#define DOLBY_CORE2A_Metadata_Start ((0x3402 << 2) + 0xff000000) +#define DOLBY_CORE2A_Metadata_End ((0x3403 << 2) + 0xff000000) +#define DOLBY_CORE2A_Interrupt_Raw ((0x3404 << 2) + 0xff000000) +#define DOLBY_CORE2A_Interrupt_Enable ((0x3405 << 2) + 0xff000000) +#define DOLBY_CORE2A_CLKGATE_CTRL ((0x3432 << 2) + 0xff000000) +#define DOLBY_CORE2A_SWAP_CTRL0 ((0x3433 << 2) + 0xff000000) +#define DOLBY_CORE2A_SWAP_CTRL1 ((0x3434 << 2) + 0xff000000) +#define DOLBY_CORE2A_SWAP_CTRL2 ((0x3435 << 2) + 0xff000000) +#define DOLBY_CORE2A_SWAP_CTRL3 ((0x3436 << 2) + 0xff000000) +#define DOLBY_CORE2A_SWAP_CTRL4 ((0x3437 << 2) + 0xff000000) +#define DOLBY_CORE2A_SWAP_CTRL5 ((0x3438 << 2) + 0xff000000) +#define DOLBY_CORE2A_DMA_CTRL ((0x3439 << 2) + 0xff000000) +#define DOLBY_CORE2A_DMA_STATUS ((0x343a << 2) + 0xff000000) +#define DOLBY_CORE2A_STATUS0 ((0x343b << 2) + 0xff000000) +#define DOLBY_CORE2A_STATUS1 ((0x343c << 2) + 0xff000000) +#define DOLBY_CORE2A_STATUS2 ((0x343d << 2) + 0xff000000) +#define DOLBY_CORE2A_STATUS3 ((0x343e << 2) + 0xff000000) +#define DOLBY_CORE2A_DMA_PORT ((0x343f << 2) + 0xff000000) +#define DOLBY_CORE2A_AXI2DMA_CTRL0 ((0x3440 << 2) + 0xff000000) +#define DOLBY_CORE2A_AXI2DMA_CTRL1 ((0x3441 << 2) + 0xff000000) +#define DOLBY_CORE2A_AXI2DMA_CTRL2 ((0x3442 << 2) + 0xff000000) +#define DOLBY_CORE2A_AXI2DMA_CTRL3 ((0x3443 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: dolby2a_regs.h +// +// ----------------------------------------------- +// REG_BASE: DOLBY2B_VCBUS_BASE = 0x35 +// ----------------------------------------------- +//`include "dolby2b_regs.h" +// ----------------------------------------------- +// REG_BASE: DOLBY3_VCBUS_BASE = 0x36 +// ----------------------------------------------- +// +// Reading file: dolby3_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DOLBY_CORE3_REG_START ((0x3600 << 2) + 0xff000000) +#define DOLBY_CORE3_CTRL ((0x3601 << 2) + 0xff000000) +#define DOLBY_CORE3_Metadata_Start ((0x3602 << 2) + 0xff000000) +#define DOLBY_CORE3_Metadata_End ((0x3603 << 2) + 0xff000000) +#define DOLBY_CORE3_Interrupt_Raw ((0x3604 << 2) + 0xff000000) +#define DOLBY_CORE3_Interrupt_Enable ((0x3605 << 2) + 0xff000000) +#define DOLBY_CORE3_CLKGATE_CTRL ((0x36f0 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL0 ((0x36f1 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL1 ((0x36f2 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL2 ((0x36f3 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL3 ((0x36f4 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL4 ((0x36f5 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL5 ((0x36f6 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL6 ((0x36f7 << 2) + 0xff000000) +#define DOLBY_CORE3_DIAG_CTRL ((0x36f8 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL8 ((0x36f9 << 2) + 0xff000000) +#define DOLBY_CORE3_SWAP_CTRL9 ((0x36fa << 2) + 0xff000000) +#define DOLBY_CORE3_CRC_CTRL ((0x36fb << 2) + 0xff000000) +#define DOLBY_CORE3_INPUT_CSC_CRC ((0x36fc << 2) + 0xff000000) +#define DOLBY_CORE3_OUTPUT_CSC_CRC ((0x36fd << 2) + 0xff000000) +#define DOLBY_CORE3_STATUS3 ((0x36fe << 2) + 0xff000000) + +// synopsys translate_off +// synopsys translate_on +// +// Closing file: dolby3_regs.h +// +// +// Reading file: vpu_madc_regs.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: MADC_VCBUS_BASE = 0x37 +// ----------------------------------------------- +// 0x00-0x28 +// +// Reading file: nr4_nm_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define NR4_MCNR_SAD_GAIN ((0x3700 << 2) + 0xff000000) +//Bit 31:25 reserved +//Bit 24 reg_nr4_bld12vs3_usemaxsad // unsigned , default = 0 use minsad/maxsad instead of minsad/avgsad to decision if it was texture or flat region, 1: use minsad/maxsad +//Bit 23:16 reg_nr4_bld12vs3_rate_gain // unsigned , default = 64 gain to minsad/maxsad or minsad/avgsad before LUT, 64 normalized as "1" +//Bit 15: 8 reg_nr4_bld1vs2_rate_gain // unsigned , default = 32 gain to minsad/maxsad or minsad/avgsad before the LUT, 64 normalized as"1" +//Bit 7: 0 reg_nr4_coefblt_gain // unsigned , default = 64 gain to final coefblt, normalized 64 as "1" +#define NR4_MCNR_LPF_CTRL ((0x3701 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:22 reg_nr4_preflt_alpofst // signed , default = 0 pre filter alpha ofst +//Bit 21:16 reg_nr4_preflt_alpgain // unsigned , default = 16 pre filter alpha gain +//Bit 15:14 reg_nr4_preflt_alpsel // unsigned , default = 3 pre filter alpha selection for adaptive blending, 0: mv pointed sad, 1: weighted mv pointed sad, 2or3: coefblt +//Bit 13: 8 reg_nr4_avgsad_gain // unsigned , default = 8 gain for avg sad before luts +//Bit 7 reserved +//Bit 6 reg_nr4_maxsad_mod // unsigned , default = 1 max sad select mode, 0: mx2_sad, 1: max sad +//Bit 5 reg_nr4_minsad_mod // unsigned , default = 1 min sad select mode, 0: sad with min err, 1: min sad +//Bit 4 reg_nr4_minmaxsad_lpf // unsigned , default = 1 mode of lpf for minmaxsad, 0: no LPF, 1: [1 2 1]/4 +//Bit 3 reg_nr4_avgsad_lpf // unsigned , default = 1 mode of lpf for avgsad, 0: no LPF, 1: [1 2 1]/4 +//Bit 2 reg_nr4_minavgsad_ratio_lpf // unsigned , default = 1 mode of lpf for minsad/avgsad and zmvsad/avgsad, 0: no LPF, 1: [1 2 1]/4 +//Bit 1 reg_nr4_bldvs_lut_lpf // unsigned , default = 1 mode of lpf for bld12vs3 and bld1vs2 LUT results, 0: no LPF, 1: [1 2 1]/4 +//Bit 0 reg_nr4_final_coef_lpf // unsigned , default = 1 mode of lpf for final coef_blt_blend123, 0: no LPF, 1: [1 2 1]/4 +#define NR4_MCNR_BLD_VS3LUT0 ((0x3702 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nr4_bld12vs3_lut0 // unsigned , default = 0 +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_bld12vs3_lut1 // unsigned , default = 8 +//Bit 15:14 reserved +//Bit 13: 8 reg_nr4_bld12vs3_lut2 // unsigned , default = 10 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_bld12vs3_lut3 // unsigned , default = 11 +#define NR4_MCNR_BLD_VS3LUT1 ((0x3703 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nr4_bld12vs3_lut4 // unsigned , default = 12 +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_bld12vs3_lut5 // unsigned , default = 14 +//Bit 15:14 reserved +//Bit 13: 8 reg_nr4_bld12vs3_lut6 // unsigned , default = 16 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_bld12vs3_lut7 // unsigned , default = 24 +#define NR4_MCNR_BLD_VS3LUT2 ((0x3704 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nr4_bld12vs3_lut8 // unsigned , default = 50 +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_bld12vs3_lut9 // unsigned , default = 58 +//Bit 15:14 reserved +//Bit 13: 8 reg_nr4_bld12vs3_lut10 // unsigned , default = 63 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_bld12vs3_lut11 // unsigned , default = 63 +#define NR4_MCNR_BLD_VS2LUT0 ((0x3705 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nr4_bld1vs2_lut0 // unsigned , default = 63 +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_bld1vs2_lut1 // unsigned , default = 32 +//Bit 15:14 reserved +//Bit 13: 8 reg_nr4_bld1vs2_lut2 // unsigned , default = 16 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_bld1vs2_lut3 // unsigned , default = 8 +#define NR4_MCNR_BLD_VS2LUT1 ((0x3706 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nr4_bld1vs2_lut4 // unsigned , default = 4 +//Bit 23:22 reserved +//Bit 21:16 reg_nr4_bld1vs2_lut5 // unsigned , default = 2 +//Bit 15:14 reserved +//Bit 13: 8 reg_nr4_bld1vs2_lut6 // unsigned , default = 1 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nr4_bld1vs2_lut7 // unsigned , default = 0 +#define NR4_COEFBLT_LUT10 ((0x3707 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut10 // signed , default = -128 +//Bit 23:16 reg_nr4_coefblt_lut11 // signed , default = -128 +//Bit 15: 8 reg_nr4_coefblt_lut12 // signed , default = -126 +//Bit 7: 0 reg_nr4_coefblt_lut13 // signed , default = -124 +#define NR4_COEFBLT_LUT11 ((0x3708 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut14 // signed , default = -120 +//Bit 23:16 reg_nr4_coefblt_lut15 // signed , default = -110 +//Bit 15: 8 reg_nr4_coefblt_lut16 // signed , default = -100 +//Bit 7: 0 reg_nr4_coefblt_lut17 // signed , default = -90 +#define NR4_COEFBLT_LUT12 ((0x3709 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut18 // signed , default = -56 +//Bit 23:16 reg_nr4_coefblt_lut19 // signed , default = -32 +//Bit 15: 8 reg_nr4_coefblt_lut110 // signed , default = -64 +//Bit 7: 0 reg_nr4_coefblt_lut111 // signed , default = -128 +#define NR4_COEFBLT_LUT20 ((0x370a << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut20 // signed , default = -128 +//Bit 23:16 reg_nr4_coefblt_lut21 // signed , default = -120 +//Bit 15: 8 reg_nr4_coefblt_lut22 // signed , default = -112 +//Bit 7: 0 reg_nr4_coefblt_lut23 // signed , default = -104 +#define NR4_COEFBLT_LUT21 ((0x370b << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut24 // signed , default = -96 +//Bit 23:16 reg_nr4_coefblt_lut25 // signed , default = -88 +//Bit 15: 8 reg_nr4_coefblt_lut26 // signed , default = -76 +//Bit 7: 0 reg_nr4_coefblt_lut27 // signed , default = -64 +#define NR4_COEFBLT_LUT22 ((0x370c << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut28 // signed , default = -48 +//Bit 23:16 reg_nr4_coefblt_lut29 // signed , default = -32 +//Bit 15: 8 reg_nr4_coefblt_lut210 // signed , default = -64 +//Bit 7: 0 reg_nr4_coefblt_lut211 // signed , default = -108 +#define NR4_COEFBLT_LUT30 ((0x370d << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut30 // signed , default = 8 +//Bit 23:16 reg_nr4_coefblt_lut31 // signed , default = 16 +//Bit 15: 8 reg_nr4_coefblt_lut32 // signed , default = 24 +//Bit 7: 0 reg_nr4_coefblt_lut33 // signed , default = 30 +#define NR4_COEFBLT_LUT31 ((0x370e << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut34 // signed , default = 36 +//Bit 23:16 reg_nr4_coefblt_lut35 // signed , default = 48 +//Bit 15: 8 reg_nr4_coefblt_lut36 // signed , default = 70 +//Bit 7: 0 reg_nr4_coefblt_lut37 // signed , default = 96 +#define NR4_COEFBLT_LUT32 ((0x370f << 2) + 0xff000000) +//Bit 31:24 reg_nr4_coefblt_lut38 // signed , default = 120 +//Bit 23:16 reg_nr4_coefblt_lut39 // signed , default = 64 +//Bit 15: 8 reg_nr4_coefblt_lut310 // signed , default = 16 +//Bit 7: 0 reg_nr4_coefblt_lut311 // signed , default = -8 +#define NR4_COEFBLT_CONV ((0x3710 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_nr4_coefblt_convmin // unsigned , default = 0 minimum of coef. bilateral conversion +//Bit 15: 8 reg_nr4_coefblt_convmax // unsigned , default = 255 maximum of coef. bilateral conversion +//Bit 7: 0 reg_nr4_coefblt_convmid // unsigned , default = 128 value at midpoint of coef. bilateral conversion +#define NR4_DBGWIN_YX0 ((0x3711 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_nr4_dgbwin_yx0 // unsigned , default = 100 ystart for debug window +//Bit 15:14 reserved +//Bit 13: 0 reg_nr4_dgbwin_yx1 // unsigned , default = 160 yend for debug window +#define NR4_DBGWIN_YX1 ((0x3712 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_nr4_dgbwin_yx2 // unsigned , default = 200 xstart for debug window +//Bit 15:14 reserved +//Bit 13: 0 reg_nr4_dgbwin_yx3 // unsigned , default = 300 xend for debug window +#define NR4_NM_X_CFG ((0x3713 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_nr4_nm_xst // unsigned , default = 8 start for noise meter statistic, dft = 8 +//Bit 15:14 reserved +//Bit 13: 0 reg_nr4_nm_xed // unsigned , default = 711 end for noise meter statistic, dft = HSIZE-8-1; +#define NR4_NM_Y_CFG ((0x3714 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:16 reg_nr4_nm_yst // unsigned , default = 8 start for noise meter statistic, dft = 8; +//Bit 15:14 reserved +//Bit 13: 0 reg_nr4_nm_yed // unsigned , default = 231 end for noise meter statistic, dft = VSIZE-8-1; +#define NR4_NM_SAD_THD ((0x3715 << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7: 0 reg_nr4_nm_sad_thd // unsigned , default = 255 threshold for (flat region) sad count, dft = 4 +#define NR4_MCNR_BANDSPLIT_PRAM ((0x3716 << 2) + 0xff000000) +//Bit 31: 5 reserved +//Bit 4 reg_nr4_mc_use_bandsplit // unsigned , default = 1 separate lp and us for mc IIR filter, 0: no BS used; 1: use BS +//Bit 3 reg_nr4_mc_apply_on_lp // unsigned , default = 1 use mcnr only on lowpass portion; +//Bit 2 reg_nr4_mc_apply_on_us // unsigned , default = 1 use mcnr only on lp complimentary portion; +//Bit 1: 0 reg_nr4_mc_zmvbs_use_adplpf // unsigned , default = 1 use adapptive LPF for the zmv pointing data for MCNR, for abs(mvx)<th +#define NR4_MCNR_ALP1_SGN_COR ((0x3717 << 2) + 0xff000000) +//Bit 31:24 reg_nr4_mc_aph1_sgn_coring0 // unsigned , default = 10 coring to cur-pre before do sgn decision +//Bit 23:16 reg_nr4_mc_aph1_sgn_coring1 // unsigned , default = 7 coring to cur-pre before do sgn decision +//Bit 15: 8 reg_nr4_mc_aph1_sgn_core_max0 // unsigned , default = 90 maximum of coring, default = 30/15 +//Bit 7: 0 reg_nr4_mc_aph1_sgn_core_max1 // unsigned , default = 15 maximum of coring, default = 30/15 +#define NR4_MCNR_ALP1_SGN_PRAM ((0x3718 << 2) + 0xff000000) +//Bit 31:11 reserved +//Bit 10 reg_nr4_mc_alp1_sgn_half // unsigned , default = 1 half block sgn sum mode enable, 0: only use 3x5 whole block sum of sgns; 1: use max(sgn_3x5, sqrt(sgn_left+sgn_righ)) +//Bit 9 reg_nr4_mc_alp1_sgn_frczmv // unsigned , default = 1 force zmv to calculate the sign_sum; +//Bit 8 reg_nr4_mc_alp1_sgnmvx_mode // unsigned , default = 1 blend mode of sgnlut and mvxlut blend mode: 0: sgnlut+ mvxlut; 1: max(sgnlut, mvxlut), default =1 +//Bit 7: 4 reg_nr4_mc_aph1_sgn_crate0 // unsigned , default = 4 rate to var, norm to 16 as 1, default = 2 +//Bit 3: 0 reg_nr4_mc_aph1_sgn_crate1 // unsigned , default = 2 rate to var, norm to 16 as 1, default = 2 +#define NR4_MCNR_ALP1_MVX_LUT1 ((0x3719 << 2) + 0xff000000) +//Bit 31:28 reg_nr4_mc_alp1_mvx_luty3 // unsigned , default = 14 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 27:24 reg_nr4_mc_alp1_mvx_lutc3 // unsigned , default = 14 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 23:20 reg_nr4_mc_alp1_mvx_luty2 // unsigned , default = 12 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 19:16 reg_nr4_mc_alp1_mvx_lutc2 // unsigned , default = 12 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 15:12 reg_nr4_mc_alp1_mvx_luty1 // unsigned , default = 5 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 11: 8 reg_nr4_mc_alp1_mvx_lutc1 // unsigned , default = 5 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty0 // unsigned , default = 3 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc0 // unsigned , default = 3 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +#define NR4_MCNR_ALP1_MVX_LUT2 ((0x371a << 2) + 0xff000000) +//Bit 31:28 reg_nr4_mc_alp1_mvx_luty7 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 27:24 reg_nr4_mc_alp1_mvx_lutc7 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 23:20 reg_nr4_mc_alp1_mvx_luty6 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 19:16 reg_nr4_mc_alp1_mvx_lutc6 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 15:12 reg_nr4_mc_alp1_mvx_luty5 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 11: 8 reg_nr4_mc_alp1_mvx_lutc5 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty4 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc4 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +#define NR4_MCNR_ALP1_MVX_LUT3 ((0x371b << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty8 // unsigned , default = 6 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1) +//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc8 // unsigned , default = 6 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1) +#define NR4_MCNR_ALP1_LP_PRAM ((0x371c << 2) + 0xff000000) +//Bit 31:18 reserved +//Bit 17:16 reg_nr4_mc_alp1_lp_sel // unsigned , default = 1 mode for alp1_lp for lp portion IIR, 0: apha1, 1:dc_dif vs ac analysis; 2: gain/ofst of alp1; 3: max of #1/#2 results +//Bit 15: 8 reg_nr4_mc_alp1_lp_gain // unsigned , default = 64 gain to alp1 to get the alp1_lp = alp1*gain/32 + ofset, default =64; +//Bit 7: 0 reg_nr4_mc_alp1_lp_ofst // signed , default = 0 offset to alp1 to get the alp1_lp = alp1*gain/32 + ofset, default =10; +#define NR4_MCNR_ALP1_SGN_LUT1 ((0x371d << 2) + 0xff000000) +//Bit 31:28 reg_nr4_mc_alp1_sgn_lut0 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 27:24 reg_nr4_mc_alp1_sgn_lut1 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 23:20 reg_nr4_mc_alp1_sgn_lut2 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 19:16 reg_nr4_mc_alp1_sgn_lut3 // unsigned , default = 4 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 15:12 reg_nr4_mc_alp1_sgn_lut4 // unsigned , default = 5 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 11: 8 reg_nr4_mc_alp1_sgn_lut5 // unsigned , default = 6 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 7: 4 reg_nr4_mc_alp1_sgn_lut6 // unsigned , default = 7 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 3: 0 reg_nr4_mc_alp1_sgn_lut7 // unsigned , default = 8 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +#define NR4_MCNR_ALP1_SGN_LUT2 ((0x371e << 2) + 0xff000000) +//Bit 31:28 reg_nr4_mc_alp1_sgn_lut8 // unsigned , default = 9 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 27:24 reg_nr4_mc_alp1_sgn_lut9 // unsigned , default = 10 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 23:20 reg_nr4_mc_alp1_sgn_lut10 // unsigned , default = 11 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 19:16 reg_nr4_mc_alp1_sgn_lut11 // unsigned , default = 12 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 15:12 reg_nr4_mc_alp1_sgn_lut12 // unsigned , default = 13 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 11: 8 reg_nr4_mc_alp1_sgn_lut13 // unsigned , default = 14 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 7: 4 reg_nr4_mc_alp1_sgn_lut14 // unsigned , default = 15 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +//Bit 3: 0 reg_nr4_mc_alp1_sgn_lut15 // unsigned , default = 15 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move +#define NR4_RO_NM_SAD_SUM ((0x371f << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_nm_sad_sum // unsigned , default = 0 sum of sad, for scene change detectcion, in noise meter +#define NR4_RO_NM_SAD_CNT ((0x3720 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_nm_sad_cnt // unsigned , default = 0 cnt of sad, for scene change detectcion, in noise meter +#define NR4_RO_NM_VAR_SUM ((0x3721 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_nm_var_sum // unsigned , default = 0 sum of var, for noise level detection, in noise meter +#define NR4_RO_NM_VAR_SCNT ((0x3722 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_nm_var_cnt // unsigned , default = 0 cnt of var, for noise level detection, in noise meter +#define NR4_RO_NM_VAR_MIN_MAX ((0x3723 << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:12 ro_nr4_nm_min_var // unsigned , default = 1023 min of var, for noise level detection, in noise meter +//Bit 11:10 reserved +//Bit 9: 0 ro_nr4_nm_max_var // unsigned , default = 0 max of var, for noise level detection, in noise meter +#define NR4_RO_NR4_DBGPIX_NUM ((0x3724 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27: 0 ro_nr4_dbgpix_num // unsigned , default = 0 number of pixels statistic invoved (removed?) +#define NR4_RO_NR4_BLDVS2_SUM ((0x3725 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_bld1vs2_sum // unsigned , default = 0 sum of blend_1vs2 with the debug window +#define NR4_BLDVS3_SUM ((0x3726 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_bld12vs3_sum // unsigned , default = 0 sum of blend_12vs3 with the debug window +#define NR4_COEF12_SUM ((0x3727 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_coef12_sum // signed , default = 0 sum of coef_blt_blend12 with the debug window, under 8 bits precision +#define NR4_COEF123_SUM ((0x3728 << 2) + 0xff000000) +//Bit 31: 0 ro_nr4_coef123_sum // signed , default = 0 sum of coef_final with the debug window, under 8 bits precision +// synopsys translate_off +// synopsys translate_on +// +// Closing file: nr4_nm_regs.h +// +// 0x30-0x32 +// +// Reading file: vpu_xlr_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define XLR_CTRL ((0x3730 << 2) + 0xff000000) +//Bit 31:23 reserved +//Bit 22 reg_xlr_en // unsigned , default = 1 enable bits for xlr function, 1: enable, 0: disable default = 1 +//Bit 21 reg_xlr_side_en // unsigned , default = 1 enable to filter the above and below lines with xlr filter, default = 1 +//Bit 20 reg_xlr_3lines // unsigned , default = 1 3 lines version enable default= 0 +//Bit 19:16 reg_xlr_simlp_gain // unsigned , default = 12 gain to simlp to decide if need the XLR, default= 12 +//Bit 15:14 reserved +//Bit 13: 8 reg_xlr_ooplp_gain // unsigned , default = 6 gain to out-of-phase lp error to decide if need the XLR, birn to 16 as 1, default= 3 +//Bit 7: 0 reg_xlr_dislp_thrd // unsigned , default = 64 threshold to lp error to discard XLR. default= 80 +#define XLR_THRD ((0x3731 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:24 reg_xlr_txt_core // unsigned , default = 3 coring to texture default = 3, (3/32) +//Bit 23:16 reg_xlr_err_thrd2 // unsigned , default = 5 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5} +//Bit 15: 8 reg_xlr_err_thrd1 // unsigned , default = 10 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5} +//Bit 7: 0 reg_xlr_err_thrd0 // unsigned , default = 20 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5} +#define XLR_HCT_THRD ((0x3732 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:26 reg_xlr_hct_step // unsigned , default = 1 horizontal chroma diff steps, 0: abs[-1 (2) -1]; 1: abs[-1 0 (2) 0 -1], 2: abs[-1 0 0 (2) 0 0 -1]; 3:abs[-1 0 0 0 (2) 0 0 0 -1] +//Bit 25:24 reg_xlr_hct_lpf // unsigned , default = 1 horizontal chroma diff low-pass filter enable, 0: no HLPF; 1: [1 2 1]; 2: max[-1:1]; 3: max[-2:2] +//Bit 23:16 reg_xlr_hct_thr // unsigned , default = 20 horizontal chroma diff threshold for xlr enable, to save the horozontal no color tran mode +//Bit 15: 8 reg_xlr_sat_thr // unsigned , default = 8 saturation threshold for xlr enable, the smaller of the threshold , the more will do xlr; +//Bit 7: 2 reg_xlr_hmargin // unsigned , default = 3 left/right number of pixels without xlr; +//Bit 1 reserved +//Bit 0 reg_xlr_hpf_only // unsigned , default = 0 enable for only do xlr filter on high pass portion of the data, instead full data +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_xlr_regs.h +// +// 0x38-0x3f +// +// Reading file: nr_deband_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define NR_DB_FLT_CTRL ((0x3738 << 2) + 0xff000000) +//Bit 31:27 reserved +//Bit 26 reg_nrdeband_reset1 // unsigned , default = 0 0 : no reset seed 1: reload chroma seed +//Bit 25 reg_nrdeband_reset0 // unsigned , default = 0 0 : no reset seed 1: reload luma seed +//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0 : yuv 1: RGB +//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below +//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below +//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y; +//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m]) +//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6 +//Bit 16 reserved +//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6 +//Bit 12 reserved +//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6 +//Bit 8 reserved +//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma +//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma +//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma +//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma +//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +#define NR_DB_FLT_YC_THRD ((0x3739 << 2) + 0xff000000) +//Bit 31:28 reg_nrdeband_luma_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 27:24 reg_nrdeband_luma_th2 // unsigned , default = 7 elseif <th[1] use (lpf*3 + y)/4 +//Bit 23:20 reg_nrdeband_luma_th1 // unsigned , default = 6 elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 19:16 reg_nrdeband_luma_th0 // unsigned , default = 5 elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else +//Bit 15:12 reg_nrdeband_chrm_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 11: 8 reg_nrdeband_chrm_th2 // unsigned , default = 7 elseif <th[1] use (lpf*3 + y)/4 +//Bit 7: 4 reg_nrdeband_chrm_th1 // unsigned , default = 6 elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 3: 0 reg_nrdeband_chrm_th0 // unsigned , default = 5 elseif <th[1] use (lpf*3 + y)/4elseif elseif +#define NR_DB_FLT_RANDLUT ((0x373a << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 lut0 +//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 lut0 +//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 lut0 +//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 lut0 +//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 lut0 +//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 lut0 +//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 lut0 +//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 lut0 +#define NR_DB_FLT_PXI_THRD ((0x373b << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 to luma/|u/v| for using the denoise +//Bit 15:10 reserved +//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 to luma/|u/v| for using the denoise +#define NR_DB_FLT_SEED_Y ((0x373c << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 noise adding seed for Y. seed[0]= 0x60a52f20; as default +#define NR_DB_FLT_SEED_U ((0x373d << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 noise adding seed for U. seed[0]= 0x60a52f27; as default +#define NR_DB_FLT_SEED_V ((0x373e << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default +#define NR_DB_FLT_SEED3 ((0x373f << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default +// synopsys translate_off +// synopsys translate_on +// +// Closing file: nr_deband_regs.h +// +// 0x40-0x43 +// +// Reading file: nr_downscale_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define NR_DS_BUF_SIZE ((0x3740 << 2) + 0xff000000) +//Bit 31:24 dsbuf_rowmax // unsigned , default = 96 +//Bit 23:16 dsbuf_colmax // unsigned , default = 128 +//Bit 15: 8 dsbuf_orow // unsigned , default = 128 +//Bit 7: 0 dsbuf_ocol // unsigned , default = 128 +#define NR_DS_CTRL ((0x3741 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_h_step // unsigned , default = 8 rand lut0 +//Bit 23:22 reserved +//Bit 21:16 reg_v_step // unsigned , default = 8 rand lut0 +//Bit 15 reserved +//Bit 14:12 reg_haa_sel // unsigned , default = 4 +//Bit 11 reserved +//Bit 10: 8 reg_vaa_sel // unsigned , default = 4 +//Bit 7 reserved +//Bit 6: 4 reg_use_hphase // unsigned , default = 1 +//Bit 3: 1 reserved +//Bit 0 reg_yuv_bldmode // unsigned , default = 0 +#define NR_DS_OFFSET ((0x3742 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 reg_h_ofst // signed , default = 0 +//Bit 15:10 reserved +//Bit 9: 0 reg_v_ofst // signed , default = 0 +#define NR_DS_BLD_COEF ((0x3743 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_yuv_bldcoef2 // unsigned , default = 128 +//Bit 15: 8 reg_yuv_bldcoef1 // unsigned , default = 64 +//Bit 7: 0 reg_yuv_bldcoef0 // unsigned , default = 64 +// synopsys translate_off +// synopsys translate_on +// +// Closing file: nr_downscale_regs.h +// +// 0x44-0xbf +// +// Reading file: di_scale_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DI_SCO_FIFO_CTRL ((0x374e << 2) + 0xff000000) +#define DI_SC_TOP_CTRL ((0x374f << 2) + 0xff000000) +// dummy data used in the DI preblend and scaler +// Bit 23:16 Y +// Bit 15:8 CB +// Bit 7:0 CR +#define DI_SC_DUMMY_DATA ((0x3750 << 2) + 0xff000000) +//input line length used in DI +#define DI_SC_LINE_IN_LENGTH ((0x3751 << 2) + 0xff000000) +//input Picture height used in DI +#define DI_SC_PIC_IN_HEIGHT ((0x3752 << 2) + 0xff000000) +//Because there are many coefficients used in the vertical filter and horizontal filters, +//indirect access the coefficients of vertical filter and horizontal filter is used. +//For vertical filter, there are 33x4 coefficients +//For horizontal filter, there are 33x4 coefficients +//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2) +//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not +//Bit 13 if true, vertical separated coef enable +//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef +//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered +//Bit 6:0 coef index +#define DI_SC_COEF_IDX ((0x3753 << 2) + 0xff000000) +//coefficients for vertical filter and horizontal filter +#define DI_SC_COEF ((0x3754 << 2) + 0xff000000) +//these following registers are the absolute line address pointer for output divided screen +//The output divided screen is shown in the following: +// +// -------------------------- <------ line zero +// . +// . +// . region0 <---------- nonlinear region or nonscaling region +// . +// --------------------------- +// --------------------------- <------ region1_startp +// . +// . region1 <---------- nonlinear region +// . +// . +// --------------------------- +// --------------------------- <------ region2_startp +// . +// . region2 <---------- linear region +// . +// . +// --------------------------- +// --------------------------- <------ region3_startp +// . +// . region3 <---------- nonlinear region +// . +// . +// --------------------------- +// --------------------------- <------ region4_startp +// . +// . region4 <---------- nonlinear region or nonoscaling region +// . +// . +// --------------------------- <------ region4_endp +//Bit 28:16 region1 startp +//Bit 12:0 region2 startp +#define DI_VSC_REGION12_STARTP ((0x3755 << 2) + 0xff000000) +//Bit 28:16 region3 startp +//Bit 12:0 region4 startp +#define DI_VSC_REGION34_STARTP ((0x3756 << 2) + 0xff000000) +#define DI_VSC_REGION4_ENDP ((0x3757 << 2) + 0xff000000) +//vertical start phase step, (source/dest)*(2^24) +//Bit 27:24 integer part +//Bit 23:0 fraction part +#define DI_VSC_START_PHASE_STEP ((0x3758 << 2) + 0xff000000) +//vertical scaler region0 phase slope, Bit24 signed bit +#define DI_VSC_REGION0_PHASE_SLOPE ((0x3759 << 2) + 0xff000000) +//vertical scaler region1 phase slope, Bit24 signed bit +#define DI_VSC_REGION1_PHASE_SLOPE ((0x375a << 2) + 0xff000000) +//vertical scaler region3 phase slope, Bit24 signed bit +#define DI_VSC_REGION3_PHASE_SLOPE ((0x375b << 2) + 0xff000000) +//vertical scaler region4 phase slope, Bit24 signed bit +#define DI_VSC_REGION4_PHASE_SLOPE ((0x375c << 2) + 0xff000000) +//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X, +// so only 2 line buffer in this case, use for 3D line by line interleave scaling +// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines +//Bit 16 0: progressive output, 1: interlace output +//Bit 15 vertical scaler output line0 in advance or not for bottom field +//Bit 14:13 vertical scaler initial repeat line0 number for bottom field +//Bit 11:8 vertical scaler initial receiving number for bottom field +//Bit 7 vertical scaler output line0 in advance or not for top field +//Bit 6:5 vertical scaler initial repeat line0 number for top field +//Bit 3:0 vertical scaler initial receiving number for top field +#define DI_VSC_PHASE_CTRL ((0x375d << 2) + 0xff000000) +//Bit 31:16 vertical scaler field initial phase for bottom field +//Bit 15:0 vertical scaler field initial phase for top field +#define DI_VSC_INI_PHASE ((0x375e << 2) + 0xff000000) +//Bit 28:16 region1 startp +//Bit 12:0 region2 startp +#define DI_HSC_REGION12_STARTP ((0x3760 << 2) + 0xff000000) +//Bit 28:16 region3 startp +//Bit 12:0 region4 startp +#define DI_HSC_REGION34_STARTP ((0x3761 << 2) + 0xff000000) +#define DI_HSC_REGION4_ENDP ((0x3762 << 2) + 0xff000000) +//horizontal start phase step, (source/dest)*(2^24) +//Bit 27:24 integer part +//Bit 23:0 fraction part +#define DI_HSC_START_PHASE_STEP ((0x3763 << 2) + 0xff000000) +//horizontal scaler region0 phase slope, Bit24 signed bit +#define DI_HSC_REGION0_PHASE_SLOPE ((0x3764 << 2) + 0xff000000) +//horizontal scaler region1 phase slope, Bit24 signed bit +#define DI_HSC_REGION1_PHASE_SLOPE ((0x3765 << 2) + 0xff000000) +//horizontal scaler region3 phase slope, Bit24 signed bit +#define DI_HSC_REGION3_PHASE_SLOPE ((0x3766 << 2) + 0xff000000) +//horizontal scaler region4 phase slope, Bit24 signed bit +#define DI_HSC_REGION4_PHASE_SLOPE ((0x3767 << 2) + 0xff000000) +//Bit 22:21 horizontal scaler initial repeat pixel0 number0 +//Bit 19:16 horizontal scaler initial receiving number0 +//Bit 15:0 horizontal scaler top field initial phase0 +#define DI_HSC_PHASE_CTRL ((0x3768 << 2) + 0xff000000) +// Bit 31 if false, di_scale swap layer bypass +// bit 30 if true, scale before diwr, else scaler before nrwr +// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length, +// just for special usage, more flexibility +// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en +// Bit 20 prehsc_en +// Bit 19 prevsc_en +// Bit 18 vsc_en +// Bit 17 hsc_en +// Bit 16 scale_top_en +// Bit 15 video1 scale out enable +// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler +// Bit 10:8 horizontal scaler bank length +// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i +// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler +// Bit 2:0 vertical scaler bank length +#define DI_SC_MISC ((0x3769 << 2) + 0xff000000) +#define DI_HSC_PHASE_CTRL1 ((0x376a << 2) + 0xff000000) +#define DI_HSC_INI_PAT_CTRL ((0x376b << 2) + 0xff000000) +#define DI_SC_GCLK_CTRL ((0x376c << 2) + 0xff000000) +#define DI_SC_HOLD_LINE ((0x376d << 2) + 0xff000000) +#define DI_HDR_IN_HSIZE ((0x376e << 2) + 0xff000000) +#define DI_HDR_IN_VSIZE ((0x376f << 2) + 0xff000000) +#define DI_HDR_OFFSET 0x70 +#define DI_HDR2_CTRL ((0x3770 << 2) + 0xff000000) +#define DI_HDR2_CLK_GATE ((0x3771 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_COEF00_01 ((0x3772 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_COEF02_10 ((0x3773 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_COEF11_12 ((0x3774 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_COEF20_21 ((0x3775 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_COEF22 ((0x3776 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_COEF30_31 ((0x3777 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_COEF32_40 ((0x3778 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_COEF41_42 ((0x3779 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_OFFSET0_1 ((0x377a << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_OFFSET2 ((0x377b << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x377c << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_PRE_OFFSET2 ((0x377d << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_COEF00_01 ((0x377e << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_COEF02_10 ((0x377f << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_COEF11_12 ((0x3780 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_COEF20_21 ((0x3781 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_COEF22 ((0x3782 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_COEF30_31 ((0x3783 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_COEF32_40 ((0x3784 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_COEF41_42 ((0x3785 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_OFFSET0_1 ((0x3786 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_OFFSET2 ((0x3787 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3788 << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_PRE_OFFSET2 ((0x3789 << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_CLIP ((0x378a << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_CLIP ((0x378b << 2) + 0xff000000) +#define DI_HDR2_CGAIN_OFFT ((0x378c << 2) + 0xff000000) +#define DI_EOTF_LUT_ADDR_PORT ((0x378e << 2) + 0xff000000) +#define DI_EOTF_LUT_DATA_PORT ((0x378f << 2) + 0xff000000) +#define DI_OETF_LUT_ADDR_PORT ((0x3790 << 2) + 0xff000000) +#define DI_OETF_LUT_DATA_PORT ((0x3791 << 2) + 0xff000000) +#define DI_CGAIN_LUT_ADDR_PORT ((0x3792 << 2) + 0xff000000) +#define DI_CGAIN_LUT_DATA_PORT ((0x3793 << 2) + 0xff000000) +#define DI_HDR2_CGAIN_COEF0 ((0x3794 << 2) + 0xff000000) +#define DI_HDR2_CGAIN_COEF1 ((0x3795 << 2) + 0xff000000) +#define DI_OGAIN_LUT_ADDR_PORT ((0x3796 << 2) + 0xff000000) +#define DI_OGAIN_LUT_DATA_PORT ((0x3797 << 2) + 0xff000000) +#define DI_HDR2_ADPS_CTRL ((0x3798 << 2) + 0xff000000) +#define DI_HDR2_ADPS_ALPHA0 ((0x3799 << 2) + 0xff000000) +#define DI_HDR2_ADPS_ALPHA1 ((0x379a << 2) + 0xff000000) +#define DI_HDR2_ADPS_BETA0 ((0x379b << 2) + 0xff000000) +#define DI_HDR2_ADPS_BETA1 ((0x379c << 2) + 0xff000000) +#define DI_HDR2_ADPS_BETA2 ((0x379d << 2) + 0xff000000) +#define DI_HDR2_ADPS_COEF0 ((0x379e << 2) + 0xff000000) +#define DI_HDR2_ADPS_COEF1 ((0x379f << 2) + 0xff000000) +#define DI_HDR2_GMUT_CTRL ((0x37a0 << 2) + 0xff000000) +#define DI_HDR2_GMUT_COEF0 ((0x37a1 << 2) + 0xff000000) +#define DI_HDR2_GMUT_COEF1 ((0x37a2 << 2) + 0xff000000) +#define DI_HDR2_GMUT_COEF2 ((0x37a3 << 2) + 0xff000000) +#define DI_HDR2_GMUT_COEF3 ((0x37a4 << 2) + 0xff000000) +#define DI_HDR2_GMUT_COEF4 ((0x37a5 << 2) + 0xff000000) +#define DI_HDR2_PIPE_CTRL1 ((0x37a6 << 2) + 0xff000000) +#define DI_HDR2_PIPE_CTRL2 ((0x37a7 << 2) + 0xff000000) +#define DI_HDR2_PIPE_CTRL3 ((0x37a8 << 2) + 0xff000000) +#define DI_HDR2_PROC_WIN1 ((0x37a9 << 2) + 0xff000000) +#define DI_HDR2_PROC_WIN2 ((0x37aa << 2) + 0xff000000) +#define DI_HDR2_MATRIXI_EN_CTRL ((0x37ab << 2) + 0xff000000) +#define DI_HDR2_MATRIXO_EN_CTRL ((0x37ac << 2) + 0xff000000) +#define DI_HDR2_HIST_CTRL ((0x37ad << 2) + 0xff000000) +#define DI_HDR2_HIST_H_START_END ((0x37ae << 2) + 0xff000000) +#define DI_HDR2_HIST_V_START_END ((0x37af << 2) + 0xff000000) +#define DI_HDR2_HIST_RD ((0x378d << 2) + 0xff000000) +#define DI_VIU_HSC_WIDTHM1 ((0x37b0 << 2) + 0xff000000) +#define DI_VIU_HSC_PHASE_STEP ((0x37b1 << 2) + 0xff000000) +#define DI_VIU_HSC_CTRL ((0x37b2 << 2) + 0xff000000) +#define DI_VIU_HSC_PHASE_CTRL ((0x37b3 << 2) + 0xff000000) +#define DI_VIU_HSC_COEF ((0x37b4 << 2) + 0xff000000) +#define DI_VIU_HSC_COEF_IDX ((0x37b5 << 2) + 0xff000000) +#define DI_DITH_CTRL ((0x3744 << 2) + 0xff000000) +#define DI_DITH_LUT_1 ((0x3745 << 2) + 0xff000000) +#define DI_DITH_LUT_2 ((0x3746 << 2) + 0xff000000) +#define DI_DITH_LUT_3 ((0x3747 << 2) + 0xff000000) +#define DI_DITH_LUT_4 ((0x3748 << 2) + 0xff000000) +#define DI_DITH_LUT_5 ((0x3749 << 2) + 0xff000000) +#define DI_DITH_LUT_6 ((0x374a << 2) + 0xff000000) +#define DI_DITH_LUT_7 ((0x374b << 2) + 0xff000000) +#define DI_DITH_LUT_8 ((0x374c << 2) + 0xff000000) +#define DI_DITH_LUT_9 ((0x374d << 2) + 0xff000000) +#define DI_DITH_LUT_10 ((0x37b6 << 2) + 0xff000000) +#define DI_DITH_LUT_11 ((0x37b7 << 2) + 0xff000000) +#define DI_DITH_LUT_12 ((0x37b8 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: di_scale_regs.h +// +// 0xc0~0xff +// +// Reading file: di_arb_sub_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DI_SUB_RDARB_MODE ((0x37c0 << 2) + 0xff000000) +#define DI_SUB_RDARB_REQEN_SLV ((0x37c1 << 2) + 0xff000000) +#define DI_SUB_RDARB_WEIGH0_SLV ((0x37c2 << 2) + 0xff000000) +#define DI_SUB_RDARB_WEIGH1_SLV ((0x37c3 << 2) + 0xff000000) +#define DI_SUB_RDARB_UGT ((0x37c4 << 2) + 0xff000000) +#define DI_SUB_RDARB_LIMT0 ((0x37c5 << 2) + 0xff000000) +#define DI_SUB_WRARB_MODE ((0x37c6 << 2) + 0xff000000) +#define DI_SUB_WRARB_REQEN_SLV ((0x37c7 << 2) + 0xff000000) +#define DI_SUB_WRARB_WEIGH0_SLV ((0x37c8 << 2) + 0xff000000) +#define DI_SUB_WRARB_WEIGH1_SLV ((0x37c9 << 2) + 0xff000000) +#define DI_SUB_WRARB_UGT ((0x37ca << 2) + 0xff000000) +#define DI_SUB_RDWR_ARB_STATUS ((0x37cb << 2) + 0xff000000) +#define DI_SUB_ARB_DBG_CTRL ((0x37cc << 2) + 0xff000000) +#define DI_SUB_ARB_DBG_STAT ((0x37cd << 2) + 0xff000000) +#define CONTRD_CTRL1 ((0x37d0 << 2) + 0xff000000) +#define CONTRD_CTRL2 ((0x37d1 << 2) + 0xff000000) +#define CONTRD_SCOPE_X ((0x37d2 << 2) + 0xff000000) +#define CONTRD_SCOPE_Y ((0x37d3 << 2) + 0xff000000) +#define CONTRD_RO_STAT ((0x37d4 << 2) + 0xff000000) +#define CONT2RD_CTRL1 ((0x37d5 << 2) + 0xff000000) +#define CONT2RD_CTRL2 ((0x37d6 << 2) + 0xff000000) +#define CONT2RD_SCOPE_X ((0x37d7 << 2) + 0xff000000) +#define CONT2RD_SCOPE_Y ((0x37d8 << 2) + 0xff000000) +#define CONT2RD_RO_STAT ((0x37d9 << 2) + 0xff000000) +#define MTNRD_CTRL1 ((0x37da << 2) + 0xff000000) +#define MTNRD_CTRL2 ((0x37db << 2) + 0xff000000) +#define MTNRD_SCOPE_X ((0x37dc << 2) + 0xff000000) +#define MTNRD_SCOPE_Y ((0x37dd << 2) + 0xff000000) +#define MTNRD_RO_STAT ((0x37de << 2) + 0xff000000) +#define MCVECRD_CTRL1 ((0x37df << 2) + 0xff000000) +#define MCVECRD_CTRL2 ((0x37e0 << 2) + 0xff000000) +#define MCVECRD_SCOPE_X ((0x37e1 << 2) + 0xff000000) +#define MCVECRD_SCOPE_Y ((0x37e2 << 2) + 0xff000000) +#define MCVECRD_RO_STAT ((0x37e3 << 2) + 0xff000000) +#define MCINFRD_CTRL1 ((0x37e4 << 2) + 0xff000000) +#define MCINFRD_CTRL2 ((0x37e5 << 2) + 0xff000000) +#define MCINFRD_SCOPE_X ((0x37e6 << 2) + 0xff000000) +#define MCINFRD_SCOPE_Y ((0x37e7 << 2) + 0xff000000) +#define MCINFRD_RO_STAT ((0x37e8 << 2) + 0xff000000) +#define CONTWR_X ((0x37e9 << 2) + 0xff000000) +#define CONTWR_Y ((0x37ea << 2) + 0xff000000) +#define CONTWR_CTRL ((0x37eb << 2) + 0xff000000) +#define CONTWR_CAN_SIZE ((0x37ec << 2) + 0xff000000) +#define MTNWR_X ((0x37ed << 2) + 0xff000000) +#define MTNWR_Y ((0x37ee << 2) + 0xff000000) +#define MTNWR_CTRL ((0x37ef << 2) + 0xff000000) +#define MTNWR_CAN_SIZE ((0x37f0 << 2) + 0xff000000) +#define MCVECWR_X ((0x37f1 << 2) + 0xff000000) +#define MCVECWR_Y ((0x37f2 << 2) + 0xff000000) +#define MCVECWR_CTRL ((0x37f3 << 2) + 0xff000000) +#define MCVECWR_CAN_SIZE ((0x37f4 << 2) + 0xff000000) +#define MCINFWR_X ((0x37f5 << 2) + 0xff000000) +#define MCINFWR_Y ((0x37f6 << 2) + 0xff000000) +#define MCINFWR_CTRL ((0x37f7 << 2) + 0xff000000) +#define MCINFWR_CAN_SIZE ((0x37f8 << 2) + 0xff000000) +#define NRDSWR_X ((0x37f9 << 2) + 0xff000000) +#define NRDSWR_Y ((0x37fa << 2) + 0xff000000) +#define NRDSWR_CTRL ((0x37fb << 2) + 0xff000000) +#define NRDSWR_CAN_SIZE ((0x37fc << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: di_arb_sub_regs.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_madc_regs.h +// +// +// Reading file: vpp_hdr2_regs.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: VPP_HDR2_VCBUS_BASE = 0x38 +// ----------------------------------------------- +#define VD1_HDR2_OFFSET 0x00 +#define VD2_HDR2_OFFSET 0x50 +#define OSD1_HDR2_OFFSET 0xa0 +//`include "hdr2_top_reg.h" +//vd1 0x00 - -x35 +#define VD1_HDR2_CTRL ((0x3800 << 2) + 0xff000000) +#define VD1_HDR2_CLK_GATE ((0x3801 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_COEF00_01 ((0x3802 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_COEF02_10 ((0x3803 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_COEF11_12 ((0x3804 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_COEF20_21 ((0x3805 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_COEF22 ((0x3806 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_COEF30_31 ((0x3807 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_COEF32_40 ((0x3808 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_COEF41_42 ((0x3809 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_OFFSET0_1 ((0x380a << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_OFFSET2 ((0x380b << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x380c << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_PRE_OFFSET2 ((0x380d << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_COEF00_01 ((0x380e << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_COEF02_10 ((0x380f << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_COEF11_12 ((0x3810 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_COEF20_21 ((0x3811 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_COEF22 ((0x3812 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_COEF30_31 ((0x3813 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_COEF32_40 ((0x3814 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_COEF41_42 ((0x3815 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_OFFSET0_1 ((0x3816 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_OFFSET2 ((0x3817 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3818 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_PRE_OFFSET2 ((0x3819 << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_CLIP ((0x381a << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_CLIP ((0x381b << 2) + 0xff000000) +#define VD1_HDR2_CGAIN_OFFT ((0x381c << 2) + 0xff000000) +#define VD1_EOTF_LUT_ADDR_PORT ((0x381e << 2) + 0xff000000) +#define VD1_EOTF_LUT_DATA_PORT ((0x381f << 2) + 0xff000000) +#define VD1_OETF_LUT_ADDR_PORT ((0x3820 << 2) + 0xff000000) +#define VD1_OETF_LUT_DATA_PORT ((0x3821 << 2) + 0xff000000) +#define VD1_CGAIN_LUT_ADDR_PORT ((0x3822 << 2) + 0xff000000) +#define VD1_CGAIN_LUT_DATA_PORT ((0x3823 << 2) + 0xff000000) +#define VD1_HDR2_CGAIN_COEF0 ((0x3824 << 2) + 0xff000000) +#define VD1_HDR2_CGAIN_COEF1 ((0x3825 << 2) + 0xff000000) +#define VD1_OGAIN_LUT_ADDR_PORT ((0x3826 << 2) + 0xff000000) +#define VD1_OGAIN_LUT_DATA_PORT ((0x3827 << 2) + 0xff000000) +#define VD1_HDR2_ADPS_CTRL ((0x3828 << 2) + 0xff000000) +#define VD1_HDR2_ADPS_ALPHA0 ((0x3829 << 2) + 0xff000000) +#define VD1_HDR2_ADPS_ALPHA1 ((0x382a << 2) + 0xff000000) +#define VD1_HDR2_ADPS_BETA0 ((0x382b << 2) + 0xff000000) +#define VD1_HDR2_ADPS_BETA1 ((0x382c << 2) + 0xff000000) +#define VD1_HDR2_ADPS_BETA2 ((0x382d << 2) + 0xff000000) +#define VD1_HDR2_ADPS_COEF0 ((0x382e << 2) + 0xff000000) +#define VD1_HDR2_ADPS_COEF1 ((0x382f << 2) + 0xff000000) +#define VD1_HDR2_GMUT_CTRL ((0x3830 << 2) + 0xff000000) +#define VD1_HDR2_GMUT_COEF0 ((0x3831 << 2) + 0xff000000) +#define VD1_HDR2_GMUT_COEF1 ((0x3832 << 2) + 0xff000000) +#define VD1_HDR2_GMUT_COEF2 ((0x3833 << 2) + 0xff000000) +#define VD1_HDR2_GMUT_COEF3 ((0x3834 << 2) + 0xff000000) +#define VD1_HDR2_GMUT_COEF4 ((0x3835 << 2) + 0xff000000) +#define VD1_HDR2_PIPE_CTRL1 ((0x3836 << 2) + 0xff000000) +#define VD1_HDR2_PIPE_CTRL2 ((0x3837 << 2) + 0xff000000) +#define VD1_HDR2_PIPE_CTRL3 ((0x3838 << 2) + 0xff000000) +#define VD1_HDR2_PROC_WIN1 ((0x3839 << 2) + 0xff000000) +#define VD1_HDR2_PROC_WIN2 ((0x383a << 2) + 0xff000000) +#define VD1_HDR2_MATRIXI_EN_CTRL ((0x383b << 2) + 0xff000000) +#define VD1_HDR2_MATRIXO_EN_CTRL ((0x383c << 2) + 0xff000000) +#define VD1_HDR2_HIST_CTRL ((0x383d << 2) + 0xff000000) +#define VD1_HDR2_HIST_H_START_END ((0x383e << 2) + 0xff000000) +#define VD1_HDR2_HIST_V_START_END ((0x383f << 2) + 0xff000000) +#define VD1_HDR2_HIST_RD ((0x381d << 2) + 0xff000000) +//vd2 0x50 - 0x85 +#define VD2_HDR2_CTRL ((0x3850 << 2) + 0xff000000) +#define VD2_HDR2_CLK_GATE ((0x3851 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_COEF00_01 ((0x3852 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_COEF02_10 ((0x3853 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_COEF11_12 ((0x3854 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_COEF20_21 ((0x3855 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_COEF22 ((0x3856 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_COEF30_31 ((0x3857 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_COEF32_40 ((0x3858 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_COEF41_42 ((0x3859 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_OFFSET0_1 ((0x385a << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_OFFSET2 ((0x385b << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x385c << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_PRE_OFFSET2 ((0x385d << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_COEF00_01 ((0x385e << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_COEF02_10 ((0x385f << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_COEF11_12 ((0x3860 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_COEF20_21 ((0x3861 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_COEF22 ((0x3862 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_COEF30_31 ((0x3863 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_COEF32_40 ((0x3864 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_COEF41_42 ((0x3865 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_OFFSET0_1 ((0x3866 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_OFFSET2 ((0x3867 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3868 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_PRE_OFFSET2 ((0x3869 << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_CLIP ((0x386a << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_CLIP ((0x386b << 2) + 0xff000000) +#define VD2_HDR2_CGAIN_OFFT ((0x386c << 2) + 0xff000000) +#define VD2_EOTF_LUT_ADDR_PORT ((0x386e << 2) + 0xff000000) +#define VD2_EOTF_LUT_DATA_PORT ((0x386f << 2) + 0xff000000) +#define VD2_OETF_LUT_ADDR_PORT ((0x3870 << 2) + 0xff000000) +#define VD2_OETF_LUT_DATA_PORT ((0x3871 << 2) + 0xff000000) +#define VD2_CGAIN_LUT_ADDR_PORT ((0x3872 << 2) + 0xff000000) +#define VD2_CGAIN_LUT_DATA_PORT ((0x3873 << 2) + 0xff000000) +#define VD2_HDR2_CGAIN_COEF0 ((0x3874 << 2) + 0xff000000) +#define VD2_HDR2_CGAIN_COEF1 ((0x3875 << 2) + 0xff000000) +#define VD2_OGAIN_LUT_ADDR_PORT ((0x3876 << 2) + 0xff000000) +#define VD2_OGAIN_LUT_DATA_PORT ((0x3877 << 2) + 0xff000000) +#define VD2_HDR2_ADPS_CTRL ((0x3878 << 2) + 0xff000000) +#define VD2_HDR2_ADPS_ALPHA0 ((0x3879 << 2) + 0xff000000) +#define VD2_HDR2_ADPS_ALPHA1 ((0x387a << 2) + 0xff000000) +#define VD2_HDR2_ADPS_BETA0 ((0x387b << 2) + 0xff000000) +#define VD2_HDR2_ADPS_BETA1 ((0x387c << 2) + 0xff000000) +#define VD2_HDR2_ADPS_BETA2 ((0x387d << 2) + 0xff000000) +#define VD2_HDR2_ADPS_COEF0 ((0x387e << 2) + 0xff000000) +#define VD2_HDR2_ADPS_COEF1 ((0x387f << 2) + 0xff000000) +#define VD2_HDR2_GMUT_CTRL ((0x3880 << 2) + 0xff000000) +#define VD2_HDR2_GMUT_COEF0 ((0x3881 << 2) + 0xff000000) +#define VD2_HDR2_GMUT_COEF1 ((0x3882 << 2) + 0xff000000) +#define VD2_HDR2_GMUT_COEF2 ((0x3883 << 2) + 0xff000000) +#define VD2_HDR2_GMUT_COEF3 ((0x3884 << 2) + 0xff000000) +#define VD2_HDR2_GMUT_COEF4 ((0x3885 << 2) + 0xff000000) +#define VD2_HDR2_PIPE_CTRL1 ((0x3886 << 2) + 0xff000000) +#define VD2_HDR2_PIPE_CTRL2 ((0x3887 << 2) + 0xff000000) +#define VD2_HDR2_PIPE_CTRL3 ((0x3888 << 2) + 0xff000000) +#define VD2_HDR2_PROC_WIN1 ((0x3889 << 2) + 0xff000000) +#define VD2_HDR2_PROC_WIN2 ((0x388a << 2) + 0xff000000) +#define VD2_HDR2_MATRIXI_EN_CTRL ((0x388b << 2) + 0xff000000) +#define VD2_HDR2_MATRIXO_EN_CTRL ((0x388c << 2) + 0xff000000) +#define VD2_HDR2_HIST_CTRL ((0x388d << 2) + 0xff000000) +#define VD2_HDR2_HIST_H_START_END ((0x388e << 2) + 0xff000000) +#define VD2_HDR2_HIST_V_START_END ((0x388f << 2) + 0xff000000) +#define VD2_HDR2_HIST_RD ((0x386d << 2) + 0xff000000) +//osd1 0xa0 - 0xd5 +#define OSD1_HDR2_CTRL ((0x38a0 << 2) + 0xff000000) +#define OSD1_HDR2_CLK_GATE ((0x38a1 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_COEF00_01 ((0x38a2 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_COEF02_10 ((0x38a3 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_COEF11_12 ((0x38a4 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_COEF20_21 ((0x38a5 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_COEF22 ((0x38a6 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_COEF30_31 ((0x38a7 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_COEF32_40 ((0x38a8 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_COEF41_42 ((0x38a9 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_OFFSET0_1 ((0x38aa << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_OFFSET2 ((0x38ab << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x38ac << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 ((0x38ad << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_COEF00_01 ((0x38ae << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_COEF02_10 ((0x38af << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_COEF11_12 ((0x38b0 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_COEF20_21 ((0x38b1 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_COEF22 ((0x38b2 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_COEF30_31 ((0x38b3 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_COEF32_40 ((0x38b4 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_COEF41_42 ((0x38b5 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_OFFSET0_1 ((0x38b6 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_OFFSET2 ((0x38b7 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x38b8 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 ((0x38b9 << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_CLIP ((0x38ba << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_CLIP ((0x38bb << 2) + 0xff000000) +#define OSD1_HDR2_CGAIN_OFFT ((0x38bc << 2) + 0xff000000) +#define OSD1_EOTF_LUT_ADDR_PORT ((0x38be << 2) + 0xff000000) +#define OSD1_EOTF_LUT_DATA_PORT ((0x38bf << 2) + 0xff000000) +#define OSD1_OETF_LUT_ADDR_PORT ((0x38c0 << 2) + 0xff000000) +#define OSD1_OETF_LUT_DATA_PORT ((0x38c1 << 2) + 0xff000000) +#define OSD1_CGAIN_LUT_ADDR_PORT ((0x38c2 << 2) + 0xff000000) +#define OSD1_CGAIN_LUT_DATA_PORT ((0x38c3 << 2) + 0xff000000) +#define OSD1_HDR2_CGAIN_COEF0 ((0x38c4 << 2) + 0xff000000) +#define OSD1_HDR2_CGAIN_COEF1 ((0x38c5 << 2) + 0xff000000) +#define OSD1_OGAIN_LUT_ADDR_PORT ((0x38c6 << 2) + 0xff000000) +#define OSD1_OGAIN_LUT_DATA_PORT ((0x38c7 << 2) + 0xff000000) +#define OSD1_HDR2_ADPS_CTRL ((0x38c8 << 2) + 0xff000000) +#define OSD1_HDR2_ADPS_ALPHA0 ((0x38c9 << 2) + 0xff000000) +#define OSD1_HDR2_ADPS_ALPHA1 ((0x38ca << 2) + 0xff000000) +#define OSD1_HDR2_ADPS_BETA0 ((0x38cb << 2) + 0xff000000) +#define OSD1_HDR2_ADPS_BETA1 ((0x38cc << 2) + 0xff000000) +#define OSD1_HDR2_ADPS_BETA2 ((0x38cd << 2) + 0xff000000) +#define OSD1_HDR2_ADPS_COEF0 ((0x38ce << 2) + 0xff000000) +#define OSD1_HDR2_ADPS_COEF1 ((0x38cf << 2) + 0xff000000) +#define OSD1_HDR2_GMUT_CTRL ((0x38d0 << 2) + 0xff000000) +#define OSD1_HDR2_GMUT_COEF0 ((0x38d1 << 2) + 0xff000000) +#define OSD1_HDR2_GMUT_COEF1 ((0x38d2 << 2) + 0xff000000) +#define OSD1_HDR2_GMUT_COEF2 ((0x38d3 << 2) + 0xff000000) +#define OSD1_HDR2_GMUT_COEF3 ((0x38d4 << 2) + 0xff000000) +#define OSD1_HDR2_GMUT_COEF4 ((0x38d5 << 2) + 0xff000000) +#define OSD1_HDR2_PIPE_CTRL1 ((0x38d6 << 2) + 0xff000000) +#define OSD1_HDR2_PIPE_CTRL2 ((0x38d7 << 2) + 0xff000000) +#define OSD1_HDR2_PIPE_CTRL3 ((0x38d8 << 2) + 0xff000000) +#define OSD1_HDR2_PROC_WIN1 ((0x38d9 << 2) + 0xff000000) +#define OSD1_HDR2_PROC_WIN2 ((0x38da << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXI_EN_CTRL ((0x38db << 2) + 0xff000000) +#define OSD1_HDR2_MATRIXO_EN_CTRL ((0x38dc << 2) + 0xff000000) +#define OSD1_HDR2_HIST_CTRL ((0x38dd << 2) + 0xff000000) +#define OSD1_HDR2_HIST_H_START_END ((0x38de << 2) + 0xff000000) +#define OSD1_HDR2_HIST_V_START_END ((0x38df << 2) + 0xff000000) +#define OSD1_HDR2_HIST_RD ((0x38bd << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_hdr2_regs.h +// +// +// Reading file: vpp_misc_regs.h +// +// synopsys translate_off +// synopsys translate_on +// ----------------------------------------------- +// REG_BASE: VPP_MISC_VCBUS_BASE = 0x39 +// ----------------------------------------------- +//0x01-0a +// +// Reading file: vpp_vd2_mat_3x3_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define VPP_VD2_MATRIX_COEF00_01 ((0x3901 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_COEF02_10 ((0x3902 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_COEF11_12 ((0x3903 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_COEF20_21 ((0x3904 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_COEF22 ((0x3905 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_OFFSET0_1 ((0x3906 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_OFFSET2 ((0x3907 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_CLIP ((0x3908 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_PRE_OFFSET0_1 ((0x3909 << 2) + 0xff000000) +#define VPP_VD2_MATRIX_PRE_OFFSET2 ((0x390a << 2) + 0xff000000) +#define VPP_VD2_MATRIX_EN_CTRL ((0x390b << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_vd2_mat_3x3_regs.h +// +//0x10-1c +// +// Reading file: vpp_osd1_mat_3x5_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define VPP_OSD1_MATRIX_COEF00_01 ((0x3910 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef00 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef01 //signed , default = 0 +#define VPP_OSD1_MATRIX_COEF02_10 ((0x3911 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef02 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef10 //signed , default = 0 +#define VPP_OSD1_MATRIX_COEF11_12 ((0x3912 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef11 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef12 //signed , default = 0 +#define VPP_OSD1_MATRIX_COEF20_21 ((0x3913 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef20 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef21 //signed , default = 0 +#define VPP_OSD1_MATRIX_COEF22 ((0x3914 << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 coef22 //signed , default = 0 +#define VPP_OSD1_MATRIX_COEF13_14 ((0x3915 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef13 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef14 //signed , default = 0 +#define VPP_OSD1_MATRIX_COEF23_24 ((0x3916 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef23 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef24 //signed , default = 0 +#define VPP_OSD1_MATRIX_COEF15_25 ((0x3917 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef15 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef25 //signed , default = 0 +#define VPP_OSD1_MATRIX_CLIP ((0x3918 << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable +//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs +//Bit 4:3 clmod // unsigned ,default == 0, mat clmod +#define VPP_OSD1_MATRIX_OFFSET0_1 ((0x3919 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 offset0 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 offset1 //signed , default = 0 +#define VPP_OSD1_MATRIX_OFFSET2 ((0x391a << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 offset2 //signed , default = 0 +#define VPP_OSD1_MATRIX_PRE_OFFSET0_1 ((0x391b << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 pre_offset0 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 pre_offset1 //signed , default = 0 +#define VPP_OSD1_MATRIX_PRE_OFFSET2 ((0x391c << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 pre_offset2 //signed , default = 0 +#define VPP_OSD1_MATRIX_EN_CTRL ((0x391d << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_osd1_mat_3x5_regs.h +// +//0x20-2c +// +// Reading file: vpp_osd2_mat_3x5_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define VPP_OSD2_MATRIX_COEF00_01 ((0x3920 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef00 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef01 //signed , default = 0 +#define VPP_OSD2_MATRIX_COEF02_10 ((0x3921 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef02 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef10 //signed , default = 0 +#define VPP_OSD2_MATRIX_COEF11_12 ((0x3922 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef11 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef12 //signed , default = 0 +#define VPP_OSD2_MATRIX_COEF20_21 ((0x3923 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef20 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef21 //signed , default = 0 +#define VPP_OSD2_MATRIX_COEF22 ((0x3924 << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 coef22 //signed , default = 0 +#define VPP_OSD2_MATRIX_COEF13_14 ((0x3925 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef13 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef14 //signed , default = 0 +#define VPP_OSD2_MATRIX_COEF23_24 ((0x3926 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef23 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef24 //signed , default = 0 +#define VPP_OSD2_MATRIX_COEF15_25 ((0x3927 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef15 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef25 //signed , default = 0 +#define VPP_OSD2_MATRIX_CLIP ((0x3928 << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable +//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs +//Bit 4:3 clmod // unsigned ,default == 0, mat clmod +#define VPP_OSD2_MATRIX_OFFSET0_1 ((0x3929 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 offset0 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 offset1 //signed , default = 0 +#define VPP_OSD2_MATRIX_OFFSET2 ((0x392a << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 offset2 //signed , default = 0 +#define VPP_OSD2_MATRIX_PRE_OFFSET0_1 ((0x392b << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 pre_offset0 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 pre_offset1 //signed , default = 0 +#define VPP_OSD2_MATRIX_PRE_OFFSET2 ((0x392c << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 pre_offset2 //signed , default = 0 +#define VPP_OSD2_MATRIX_EN_CTRL ((0x392d << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_osd2_mat_3x5_regs.h +// +//0x30-3c +//`include "vpp_post_mat_3x5_regs.h" +//0x43-0x5b +// +// Reading file: vpp_vd2_scale_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define VD2_SCALE_COEF_IDX ((0x3943 << 2) + 0xff000000) +#define VD2_SCALE_COEF ((0x3944 << 2) + 0xff000000) +#define VD2_VSC_REGION12_STARTP ((0x3945 << 2) + 0xff000000) +#define VD2_VSC_REGION34_STARTP ((0x3946 << 2) + 0xff000000) +#define VD2_VSC_REGION4_ENDP ((0x3947 << 2) + 0xff000000) +#define VD2_VSC_START_PHASE_STEP ((0x3948 << 2) + 0xff000000) +#define VD2_VSC_REGION0_PHASE_SLOPE ((0x3949 << 2) + 0xff000000) +#define VD2_VSC_REGION1_PHASE_SLOPE ((0x394a << 2) + 0xff000000) +#define VD2_VSC_REGION3_PHASE_SLOPE ((0x394b << 2) + 0xff000000) +#define VD2_VSC_REGION4_PHASE_SLOPE ((0x394c << 2) + 0xff000000) +#define VD2_VSC_PHASE_CTRL ((0x394d << 2) + 0xff000000) +#define VD2_VSC_INI_PHASE ((0x394e << 2) + 0xff000000) +#define VD2_HSC_REGION12_STARTP ((0x394f << 2) + 0xff000000) +#define VD2_HSC_REGION34_STARTP ((0x3950 << 2) + 0xff000000) +#define VD2_HSC_REGION4_ENDP ((0x3951 << 2) + 0xff000000) +#define VD2_HSC_START_PHASE_STEP ((0x3952 << 2) + 0xff000000) +#define VD2_HSC_REGION0_PHASE_SLOPE ((0x3953 << 2) + 0xff000000) +#define VD2_HSC_REGION1_PHASE_SLOPE ((0x3954 << 2) + 0xff000000) +#define VD2_HSC_REGION3_PHASE_SLOPE ((0x3955 << 2) + 0xff000000) +#define VD2_HSC_REGION4_PHASE_SLOPE ((0x3956 << 2) + 0xff000000) +#define VD2_HSC_PHASE_CTRL ((0x3957 << 2) + 0xff000000) +#define VD2_SC_MISC ((0x3958 << 2) + 0xff000000) +#define VD2_SCO_FIFO_CTRL ((0x3959 << 2) + 0xff000000) +#define VD2_HSC_PHASE_CTRL1 ((0x395a << 2) + 0xff000000) +#define VD2_HSC_INI_PAT_CTRL ((0x395b << 2) + 0xff000000) +#define VD2_SC_GCLK_CTRL ((0x395c << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_vd2_scale_regs.h +// +#define VPP_PRE_BLEND_CTRL ((0x3960 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:20 hold_lines //unsigned , default = 8'h4 +//Bit 19:16 din_premult_en //unsigned , default = 4'h0 +//Bit 15:0 din_reoder_sel //unsigned , default = 16'h1 +#define VPP_PRE_BLEND_BLEND_DUMMY_DATA ((0x3961 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:16 blend0_dummy_data_y //unsigned , default = 8'h10 +//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80 +//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h0 +#define VPP_PRE_BLEND_DUMMY_ALPHA ((0x3962 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0 +//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0 +//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0 +#define VPP_PRE_BLEND2_RO_CURRENT_XY ((0x3963 << 2) + 0xff000000) +//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0 +#define VPP_POST_BLEND_CTRL ((0x3967 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:20 hold_lines //unsigned , default = 8'h4 +//Bit 19:16 din_premult_en //unsigned , default = 4'h0 +//Bit 15:0 din_reoder_sel //unsigned , default = 16'h1 +#define VPP_POST_BLEND_BLEND_DUMMY_DATA ((0x3968 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:16 blend0_dummy_data_y //unsigned , default = 8'h10 +//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80 +//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h0 +#define VPP_POST_BLEND_DUMMY_ALPHA ((0x3969 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0 +//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0 +//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0 +#define VPP_POST_BLEND2_RO_CURRENT_XY ((0x396a << 2) + 0xff000000) +//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0 +#define VPP_AFBC_RDARB_MODE ((0x3970 << 2) + 0xff000000) +#define VPP_AFBC_RDARB_REQEN_SLV ((0x3971 << 2) + 0xff000000) +#define VPP_AFBC_RDARB_WEIGH0_SLV ((0x3972 << 2) + 0xff000000) +#define VPP_AFBC_RDWR_ARB_STATUS ((0x3973 << 2) + 0xff000000) +#define VPP_AFBC_ARB_DBG_CTRL ((0x3974 << 2) + 0xff000000) +#define VPP_AFBC_ARB_DBG_STAT ((0x3975 << 2) + 0xff000000) +#define VPP_RDARB_MODE ((0x3978 << 2) + 0xff000000) +#define VPP_RDARB_REQEN_SLV ((0x3979 << 2) + 0xff000000) +#define VPP_RDARB_WEIGH0_SLV ((0x397a << 2) + 0xff000000) +#define VPP_RDARB_WEIGH1_SLV ((0x397b << 2) + 0xff000000) +#define VPP_RDWR_ARB_STATUS ((0x397c << 2) + 0xff000000) +#define VPP_ARB_DBG_CTRL ((0x397e << 2) + 0xff000000) +#define VPP_ARB_DBG_STAT ((0x397f << 2) + 0xff000000) +//ox80-0x9f & 0xe0-0xef +// +// Reading file: vpu_primesl_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define PRIMESL_LUTC_ADDR_PORT ((0x3980 << 2) + 0xff000000) +#define PRIMESL_LUTC_DATA_PORT ((0x3981 << 2) + 0xff000000) +#define PRIMESL_LUTP_ADDR_PORT ((0x3982 << 2) + 0xff000000) +#define PRIMESL_LUTP_DATA_PORT ((0x3983 << 2) + 0xff000000) +#define PRIMESL_LUTD_ADDR_PORT ((0x3984 << 2) + 0xff000000) +#define PRIMESL_LUTD_DATA_PORT ((0x3985 << 2) + 0xff000000) +#define PRIMESL_CTRL0 ((0x3990 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29 legacy_mode_en // unsigned , default = 0 = 'h0 +//Bit 28 clip_en // unsigned , default = 1 = 'h0 +//Bit 27 reserved +//Bit 26:16 inv_chroma_ratio // unsigned , default = 0 = 'h0, +//Bit 15 reserved +//Bit 14: 4 inv_y_ratio // unsigned , default = 0 = 'h0, +//Bit 3 reg_gclk_ctrl // unsigned , default = 0 = 'h0, +//Bit 2: 1 gclk_ctrl // unsigned , default = 0 = 'h0, +//Bit 0 primesl_en // unsigned , default = 0 = 'h0, +#define PRIMESL_CTRL1 ((0x3991 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 l_headroom // unsigned , default = 0 = 'h0, +//Bit 15:10 reserved +//Bit 9: 0 footroom // unsigned , default = 0 = 'h0, +#define PRIMESL_CTRL2 ((0x3992 << 2) + 0xff000000) +//Bit 31:10 reserved +//Bit 9: 0 c_headroom // unsigned , default = 0 = 'h0, +#define PRIMESL_CTRL3 ((0x3993 << 2) + 0xff000000) +//Bit 31:16 mub // unsigned , default = 0 = 'h0, +//Bit 15: 0 mua // unsigned , default = 0 = 'h0, +#define PRIMESL_CTRL4 ((0x3994 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 oct_7_1 // signed , default = 0 = 'h0, +//Bit 15:10 reserved +//Bit 9: 0 oct_7_0 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL5 ((0x3995 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 oct_7_3 // signed , default = 0 = 'h0, +//Bit 15:10 reserved +//Bit 9: 0 oct_7_2 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL6 ((0x3996 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 oct_7_5 // signed , default = 0 = 'h0, +//Bit 15:10 reserved +//Bit 9: 0 oct_7_4 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL7 ((0x3997 << 2) + 0xff000000) +//Bit 31:10 reserved +//Bit 9: 0 oct_7_6 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL8 ((0x3998 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 d_lut_threshold_3_1 // unsigned , default = 0 = 'h0, +//Bit 15:13 reserved +//Bit 12: 0 d_lut_threshold_3_0 // unsigned , default = 0 = 'h0, +#define PRIMESL_CTRL9 ((0x3999 << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12: 0 d_lut_threshold_3_2 // unsigned , default = 0 = 'h0, +#define PRIMESL_CTRL10 ((0x399a << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15:12 d_lut_step_4_3 // unsigned , default = 0 = 'h0, +//Bit 11: 8 d_lut_step_4_2 // unsigned , default = 0 = 'h0, +//Bit 7: 4 d_lut_step_4_1 // unsigned , default = 0 = 'h0, +//Bit 3: 0 d_lut_step_4_0 // unsigned , default = 0 = 'h0, +#define PRIMESL_CTRL11 ((0x399b << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 rgb2yuv_9_0 // signed , default = 0 = 'h0, +//Bit 15:13 reserved +//Bit 12: 0 rgb2yuv_9_1 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL12 ((0x399c << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 rgb2yuv_9_2 // signed , default = 0 = 'h0, +//Bit 15:13 reserved +//Bit 12: 0 rgb2yuv_9_3 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL13 ((0x399d << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 rgb2yuv_9_4 // signed , default = 0 = 'h0, +//Bit 15:13 reserved +//Bit 12: 0 rgb2yuv_9_5 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL14 ((0x399e << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 rgb2yuv_9_6 // signed , default = 0 = 'h0, +//Bit 15:13 reserved +//Bit 12: 0 rgb2yuv_9_7 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL15 ((0x399f << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12: 0 rgb2yuv_9_8 // signed , default = 0 = 'h0, +#define PRIMESL_CTRL16 ((0x39e0 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30 byp_s_lut // unsigned , default = 0 = 'h0, +//Bit 29 byp_d_lut // unsigned , default = 0 = 'h0, +//Bit 28 byp_mat // unsigned , default = 0 = 'h0, +//Bit 27 rgb_swap // unsigned , default = 0 = 'h0, +//Bit 26:24 uv_shift // unsigned , default = 0 = 'h0, +//Bit 23:22 rgb_shift // unsigned , default = 0 = 'h0, +//Bit 21:20 rgb_clip // unsigned , default = 3 = 'h3, +//Bit 19:18 reserved +//Bit 17:16 rgb_rs // unsigned , default = 0 = 'h0, +//Bit 15:14 reserved +//Bit 13: 0 reg_s // signed , default = 1024 = 'h1024, +#define PRIMESL_OMAT_OFFSET0 ((0x39e1 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:16 pre_offset0 // unsigned , default = 512 = 'h512 +//Bit 15:12 reserved +//Bit 11: 0 pre_offset1 // unsigned , default = 512 = 'h512 +#define PRIMESL_OMAT_OFFSET1 ((0x39e2 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:16 pre_offset2 // unsigned , default = 512 = 'h512 +//Bit 15:12 reserved +//Bit 11: 0 offset0 // unsigned , default = 256 = 'h256 +#define PRIMESL_OMAT_OFFSET2 ((0x39e3 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:16 offset1 // unsigned , default = 2048 = 'h2048 +//Bit 15:12 reserved +//Bit 11: 0 offset2 // unsigned , default = 2048 = 'h2048 +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_primesl_regs.h +// +//oxa0-0xaf +// +// Reading file: vpp_post2_mat_3x5_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define VPP_POST2_MATRIX_COEF00_01 ((0x39a0 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef00 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef01 //signed , default = 0 +#define VPP_POST2_MATRIX_COEF02_10 ((0x39a1 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef02 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef10 //signed , default = 0 +#define VPP_POST2_MATRIX_COEF11_12 ((0x39a2 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef11 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef12 //signed , default = 0 +#define VPP_POST2_MATRIX_COEF20_21 ((0x39a3 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef20 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef21 //signed , default = 0 +#define VPP_POST2_MATRIX_COEF22 ((0x39a4 << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 coef22 //signed , default = 0 +#define VPP_POST2_MATRIX_COEF13_14 ((0x39a5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef13 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef14 //signed , default = 0 +#define VPP_POST2_MATRIX_COEF23_24 ((0x39a6 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef23 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef24 //signed , default = 0 +#define VPP_POST2_MATRIX_COEF15_25 ((0x39a7 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 coef15 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 coef25 //signed , default = 0 +#define VPP_POST2_MATRIX_CLIP ((0x39a8 << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable +//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs +//Bit 4:3 clmod // unsigned ,default == 0, mat clmod +#define VPP_POST2_MATRIX_OFFSET0_1 ((0x39a9 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 offset0 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 offset1 //signed , default = 0 +#define VPP_POST2_MATRIX_OFFSET2 ((0x39aa << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 offset2 //signed , default = 0 +#define VPP_POST2_MATRIX_PRE_OFFSET0_1 ((0x39ab << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 pre_offset0 //signed , default = 0 +//Bit 15:13 reserved +//Bit 12:0 pre_offset1 //signed , default = 0 +#define VPP_POST2_MATRIX_PRE_OFFSET2 ((0x39ac << 2) + 0xff000000) +//Bit 31:13 reserved +//Bit 12:0 pre_offset2 //signed , default = 0 +#define VPP_POST2_MATRIX_EN_CTRL ((0x39ad << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_post2_mat_3x5_regs.h +// +//0xb0-0xcf +// +// Reading file: osd_blend_reg.h +// +// synopsys translate_off +// synopsys translate_on +#define VIU_OSD_BLEND_CTRL ((0x39b0 << 2) + 0xff000000) +//Bit 31:29 hold_lines //unsigned , default = 3'h0 +//Bit 28:27 blend2_premult_en //unsigned , default = 2'h3 +//Bit 26 din0_byp_blend //unsigned , default = 1'h1 +//Bit 25 din2_osd_sel //unsigned , default = 1'h1 +//Bit 24 din3_osd_sel //unsigned , default = 1'h1 +//Bit 23:20 blend_din_en //unsigned , default = 4'h5 +//Bit 19:16 din_premult_en //unsigned , default = 4'h0 +//Bit 15:0 din_reoder_sel //unsigned , default = 16'h2341 +#define VIU_OSD_BLEND_CTRL1 ((0x39c0 << 2) + 0xff000000) +//Bit 31:6 reserved +//Bit 5:4 reg_alp_mapping_mode +//Bit 2:1 reg_div_gclk_en +//Bit 0 reg_div_alpha_en +#define VIU_OSD_BLEND_DIN0_SCOPE_H ((0x39b1 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 bld_din0_h_end ///unsigned , default = 13'h2d0 +//Bit 15:13 reserved +//Bit 12:0 bld_din0_h_start ///unsigned , default = 13'h0 +#define VIU_OSD_BLEND_DIN0_SCOPE_V ((0x39b2 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 bld_din0_v_end ///unsigned , default = 13'h1e0 +//Bit 15:13 reserved +//Bit 12:0 bld_din0_v_start ///unsigned , default = 13'h0 +#define VIU_OSD_BLEND_DIN1_SCOPE_H ((0x39b3 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 bld_din1_h_end ///unsigned , default = 13'h2d0 +//Bit 15:13 reserved +//Bit 12:0 bld_din1_h_start ///unsigned , default = 13'h0 +#define VIU_OSD_BLEND_DIN1_SCOPE_V ((0x39b4 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 bld_din1_v_end ///unsigned , default = 13'h1e0 +//Bit 15:13 reserved +//Bit 12:0 bld_din1_v_start ///unsigned , default = 13'h0 +#define VIU_OSD_BLEND_DIN2_SCOPE_H ((0x39b5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 bld_din2_h_end ///unsigned , default = 13'h2d0 +//Bit 15:13 reserved +//Bit 12:0 bld_din2_h_start ///unsigned , default = 13'h0 +#define VIU_OSD_BLEND_DIN2_SCOPE_V ((0x39b6 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 bld_din2_v_end ///unsigned , default = 13'h1e0 +//Bit 15:13 reserved +//Bit 12:0 bld_din2_v_start ///unsigned , default = 13'h0 +#define VIU_OSD_BLEND_DIN3_SCOPE_H ((0x39b7 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 bld_din3_h_end ///unsigned , default = 13'h2d0 +//Bit 15:13 reserved +//Bit 12:0 bld_din3_h_start ///unsigned , default = 13'h0 +#define VIU_OSD_BLEND_DIN3_SCOPE_V ((0x39b8 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 bld_din3_v_end ///unsigned , default = 13'h1e0 +//Bit 15:13 reserved +//Bit 12:0 bld_din3_v_start ///unsigned , default = 13'h0 +#define VIU_OSD_BLEND_DUMMY_DATA0 ((0x39b9 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 23:16 blend0_dummy_data_y //unsigned , default = 8'h00 +//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80 +//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h80 +#define VIU_OSD_BLEND_DUMMY_ALPHA ((0x39ba << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0 +//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0 +//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0 +#define VIU_OSD_BLEND_BLEND0_SIZE ((0x39bb << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 blend0_vsize //unsigned , default = 13'h1e0 +//Bit 15:13 reserved +//Bit 12:0 blend0_hsize //unsigned , default = 13'h2d0 +#define VIU_OSD_BLEND_BLEND1_SIZE ((0x39bc << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 blend1_vsize //unsigned , default = 13'h1e0 +//Bit 15:13 reserved +//Bit 12:0 blend1_hsize ///unsigned , default = 13'h2d0 +//`define VIU_OSD_BLEND_DOUT0_HV_START 8'hbd +//Bit 31:29 reserved +//Bit 28:0 osd_blend_dout0_hv_start //unsigned , default = 29'h0 +//`define VIU_OSD_BLEND_DOUT1_HV_START 8'hbe +//Bit 31:29 reserved +//Bit 28:0 osd_blend_dout1_hv_start //unsigned , default = 29'h0 +#define VIU_OSD_HOLD_LINE_HIGH_BITS ((0x39c1 << 2) + 0xff000000) +//Bit 31:8 reserved +//Bit 7:0 hold_line_high_bits //unsigned , default = 32'h0 +#define VIU_OSD_BLEND_RO_CURRENT_XY ((0x39bf << 2) + 0xff000000) +//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0 +// synopsys translate_off +// synopsys translate_on +// +// Closing file: osd_blend_reg.h +// +#define VPP_LUT3D_CTRL ((0x39d0 << 2) + 0xff000000) +#define VPP_LUT3D_CBUS2RAM_CTRL ((0x39d1 << 2) + 0xff000000) +#define VPP_LUT3D_RAM_ADDR ((0x39d2 << 2) + 0xff000000) +#define VPP_LUT3D_RAM_DATA ((0x39d3 << 2) + 0xff000000) +#define VPP_GAMMA_CTRL ((0x39d4 << 2) + 0xff000000) +#define VPP_GAMMA_BIN_ADDR ((0x39d5 << 2) + 0xff000000) +#define VPP_GAMMA_BIN_DATA ((0x39d6 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_misc_regs.h +// +//======================================================================== +// MALI AFBCD +//======================================================================== +// ----------------------------------------------- +// REG_BASE: VPP_AFBCD0_VCBUS_BASE = 0x3a +// ----------------------------------------------- +// +// Reading file: vpp_mali_tx300_afbc_regs.h +// +// synopsys translate_off +// synopsys translate_on + //0x00 - 0x80 +#define VPU_MAFBC_BLOCK_ID ((0x3a00 << 2) + 0xff000000) +#define VPU_MAFBC_IRQ_RAW_STATUS ((0x3a01 << 2) + 0xff000000) +#define VPU_MAFBC_IRQ_CLEAR ((0x3a02 << 2) + 0xff000000) +#define VPU_MAFBC_IRQ_MASK ((0x3a03 << 2) + 0xff000000) +#define VPU_MAFBC_IRQ_STATUS ((0x3a04 << 2) + 0xff000000) +#define VPU_MAFBC_COMMAND ((0x3a05 << 2) + 0xff000000) +#define VPU_MAFBC_STATUS ((0x3a06 << 2) + 0xff000000) +#define VPU_MAFBC_SURFACE_CFG ((0x3a07 << 2) + 0xff000000) +#define VPU_MAFBC_AXI_CFG ((0x3a08 << 2) + 0xff000000) +#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 ((0x3a10 << 2) + 0xff000000) +#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 ((0x3a11 << 2) + 0xff000000) +#define VPU_MAFBC_FORMAT_SPECIFIER_S0 ((0x3a12 << 2) + 0xff000000) +#define VPU_MAFBC_BUFFER_WIDTH_S0 ((0x3a13 << 2) + 0xff000000) +#define VPU_MAFBC_BUFFER_HEIGHT_S0 ((0x3a14 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 ((0x3a15 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 ((0x3a16 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 ((0x3a17 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 ((0x3a18 << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 ((0x3a19 << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 ((0x3a1a << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 ((0x3a1b << 2) + 0xff000000) +#define VPU_MAFBC_PREFETCH_CFG_S0 ((0x3a1c << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MIN_LOW_S0 ((0x3a1d << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S0 ((0x3a1e << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MAX_LOW_S0 ((0x3a1f << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S0 ((0x3a20 << 2) + 0xff000000) +#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 ((0x3a30 << 2) + 0xff000000) +#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 ((0x3a31 << 2) + 0xff000000) +#define VPU_MAFBC_FORMAT_SPECIFIER_S1 ((0x3a32 << 2) + 0xff000000) +#define VPU_MAFBC_BUFFER_WIDTH_S1 ((0x3a33 << 2) + 0xff000000) +#define VPU_MAFBC_BUFFER_HEIGHT_S1 ((0x3a34 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 ((0x3a35 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 ((0x3a36 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 ((0x3a37 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 ((0x3a38 << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 ((0x3a39 << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 ((0x3a3a << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 ((0x3a3b << 2) + 0xff000000) +#define VPU_MAFBC_PREFETCH_CFG_S1 ((0x3a3c << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MIN_LOW_S1 ((0x3a3d << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S1 ((0x3a3e << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MAX_LOW_S1 ((0x3a3f << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S1 ((0x3a40 << 2) + 0xff000000) +#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 ((0x3a50 << 2) + 0xff000000) +#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 ((0x3a51 << 2) + 0xff000000) +#define VPU_MAFBC_FORMAT_SPECIFIER_S2 ((0x3a52 << 2) + 0xff000000) +#define VPU_MAFBC_BUFFER_WIDTH_S2 ((0x3a53 << 2) + 0xff000000) +#define VPU_MAFBC_BUFFER_HEIGHT_S2 ((0x3a54 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 ((0x3a55 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 ((0x3a56 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 ((0x3a57 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 ((0x3a58 << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 ((0x3a59 << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 ((0x3a5a << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 ((0x3a5b << 2) + 0xff000000) +#define VPU_MAFBC_PREFETCH_CFG_S2 ((0x3a5c << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MIN_LOW_S2 ((0x3a5d << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S2 ((0x3a5e << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MAX_LOW_S2 ((0x3a5f << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S2 ((0x3a60 << 2) + 0xff000000) +#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 ((0x3a70 << 2) + 0xff000000) +#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 ((0x3a71 << 2) + 0xff000000) +#define VPU_MAFBC_FORMAT_SPECIFIER_S3 ((0x3a72 << 2) + 0xff000000) +#define VPU_MAFBC_BUFFER_WIDTH_S3 ((0x3a73 << 2) + 0xff000000) +#define VPU_MAFBC_BUFFER_HEIGHT_S3 ((0x3a74 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 ((0x3a75 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 ((0x3a76 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 ((0x3a77 << 2) + 0xff000000) +#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 ((0x3a78 << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 ((0x3a79 << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 ((0x3a7a << 2) + 0xff000000) +#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 ((0x3a7b << 2) + 0xff000000) +#define VPU_MAFBC_PREFETCH_CFG_S3 ((0x3a7c << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MIN_LOW_S3 ((0x3a7d << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S3 ((0x3a7e << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MAX_LOW_S3 ((0x3a7f << 2) + 0xff000000) +#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S3 ((0x3a80 << 2) + 0xff000000) + // synopsys translate_off +// synopsys translate_on +// +// Closing file: vpp_mali_tx300_afbc_regs.h +// +// ----------------------------------------------- +// REG_BASE: VPP_AFBCD1_VCBUS_BASE = 0x3b +// ----------------------------------------------- +// ----------------------------------------------- +// REG_BASE: VPP_AFBCD2_VCBUS_BASE = 0x3c +// ----------------------------------------------- +// ----------------------------------------------- +// REG_BASE: VPU_OSDSC_BLD_VCBUS_BASE = 0x3d +// ----------------------------------------------- +// +// Reading file: vpu_osdsc_bld_regs.h +// +// synopsys translate_off +// synopsys translate_on +//vertical scaler phase step +//Bit 27:0, 4.24 format +#define OSD2_VSC_PHASE_STEP ((0x3d00 << 2) + 0xff000000) +//Bit 31:16, botttom vertical scaler initial phase +//Bit 15:0, top vertical scaler initial phase +#define OSD2_VSC_INI_PHASE ((0x3d01 << 2) + 0xff000000) +//Bit 24 osd vertical Scaler enable +//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace +//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines +//Bit 20 osd_vsc_phase0_always_en +//Bit 19 osd_vsc_nearest_en +//Bit 17:16 osd_vsc_bot_rpt_l0_num +//Bit 14:11 osd_vsc_bot_ini_rcv_num +//Bit 9:8 osd_vsc_top_rpt_l0_num +//Bit 6:3 osd_vsc_top_ini_rcv_num +//Bit 2:0 osd_vsc_bank_length +#define OSD2_VSC_CTRL0 ((0x3d02 << 2) + 0xff000000) +//horizontal scaler phase step +//Bit 27:0, 4.24 format +#define OSD2_HSC_PHASE_STEP ((0x3d03 << 2) + 0xff000000) +//Bit 31:16, horizontal scaler initial phase1 +//Bit 15:0, horizontal scaler initial phase0 +#define OSD2_HSC_INI_PHASE ((0x3d04 << 2) + 0xff000000) +//Bit 22 osd horizontal scaler enable +//Bit 21 osd_hsc_double_pix_mode +//Bit 20 osd_hsc_phase0_always_en +//Bit 19 osd_hsc_nearest_en +//Bit 17:16 osd_hsc_rpt_p0_num1 +//Bit 14:11 osd_hsc_ini_rcv_num1 +//Bit 9:8 osd_hsc_rpt_p0_num0 +//Bit 6:3 osd_hsc_ini_rcv_num0 +//Bit 2:0 osd_hsc_bank_length +#define OSD2_HSC_CTRL0 ((0x3d05 << 2) + 0xff000000) +//for 3D quincunx sub-sampling +//bit 15:8 pattern, each patten 1 bit, from lsb -> msb +//bit 6:4 pattern start +//bit 2:0 pattern end +#define OSD2_HSC_INI_PAT_CTRL ((0x3d06 << 2) + 0xff000000) +//bit 31:24, componet 0 +//bit 23:16, component 1 +//bit 15:8, component 2 +//bit 7:0 component 3, alpha +#define OSD2_SC_DUMMY_DATA ((0x3d07 << 2) + 0xff000000) +//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. +//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. +//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. +//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. +//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source +//Bit 3 osd scaler path enable +//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix +#define OSD2_SC_CTRL0 ((0x3d08 << 2) + 0xff000000) +//Bit 28:16 OSD scaler input width minus 1 +//Bit 12:0 OSD scaler input height minus 1 +#define OSD2_SCI_WH_M1 ((0x3d09 << 2) + 0xff000000) +//Bit 28:16 OSD scaler output horizontal start +//Bit 12:0 OSD scaler output horizontal end +#define OSD2_SCO_H_START_END ((0x3d0a << 2) + 0xff000000) +//Bit 28:16 OSD scaler output vertical start +//Bit 12:0 OSD scaler output vertical end +#define OSD2_SCO_V_START_END ((0x3d0b << 2) + 0xff000000) +#define OSD2_DB_FLT_CTRL ((0x3d0c << 2) + 0xff000000) +//Bit 31:27 reserved +//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed +//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed +//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB +//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below +//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below +//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y; +//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m]) +//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6 +//Bit 16 reserved +//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6 +//Bit 12 reserved +//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6 +//Bit 8 reserved +//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma +//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma +//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma +//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma +//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +#define OSD2_DB_FLT_CTRL1 ((0x3d0d << 2) + 0xff000000) +//Bit 31:18 reserved +//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2 +//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8 +//Bit 11 reserved +//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6 +//Bit 7 reserved +//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6 +//Bit 3 reserved +//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6 +#define OSD2_DB_FLT_LUMA_THRD ((0x3d0e << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 23:22 reserved +//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4 +//Bit 15:14 reserved +//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else +#define OSD2_DB_FLT_CHRM_THRD ((0x3d0f << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 23:22 reserved +//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4 +//Bit 15:14 reserved +//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif +#define OSD2_DB_FLT_RANDLUT ((0x3d10 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7 +//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6 +//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5 +//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4 +//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3 +//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2 +//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1 +//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0 +#define OSD2_DB_FLT_PXI_THRD ((0x3d11 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise +//Bit 15:10 reserved +//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise +#define OSD2_DB_FLT_SEED_Y ((0x3d12 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default +#define OSD2_DB_FLT_SEED_U ((0x3d13 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default +#define OSD2_DB_FLT_SEED_V ((0x3d14 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD2_DB_FLT_SEED3 ((0x3d15 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD2_DB_FLT_SEED4 ((0x3d16 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD2_DB_FLT_SEED5 ((0x3d17 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD2_SCALE_COEF_IDX ((0x3d18 << 2) + 0xff000000) +//coefficients for vertical filter and horizontal filter +#define OSD2_SCALE_COEF ((0x3d19 << 2) + 0xff000000) +#define OSD34_SCALE_COEF_IDX ((0x3d1e << 2) + 0xff000000) +//coefficients for vertical filter and horizontal filter +#define OSD34_SCALE_COEF ((0x3d1f << 2) + 0xff000000) +//vertical scaler phase step +//Bit 27:0, 4.24 format +#define OSD34_VSC_PHASE_STEP ((0x3d20 << 2) + 0xff000000) +//Bit 31:16, botttom vertical scaler initial phase +//Bit 15:0, top vertical scaler initial phase +#define OSD34_VSC_INI_PHASE ((0x3d21 << 2) + 0xff000000) +//Bit 24 osd vertical Scaler enable +//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace +//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines +//Bit 20 osd_vsc_phase0_always_en +//Bit 19 osd_vsc_nearest_en +//Bit 17:16 osd_vsc_bot_rpt_l0_num +//Bit 14:11 osd_vsc_bot_ini_rcv_num +//Bit 9:8 osd_vsc_top_rpt_l0_num +//Bit 6:3 osd_vsc_top_ini_rcv_num +//Bit 2:0 osd_vsc_bank_length +#define OSD34_VSC_CTRL0 ((0x3d22 << 2) + 0xff000000) +//horizontal scaler phase step +//Bit 27:0, 4.24 format +#define OSD34_HSC_PHASE_STEP ((0x3d23 << 2) + 0xff000000) +//Bit 31:16, horizontal scaler initial phase1 +//Bit 15:0, horizontal scaler initial phase0 +#define OSD34_HSC_INI_PHASE ((0x3d24 << 2) + 0xff000000) +//Bit 22 osd horizontal scaler enable +//Bit 21 osd_hsc_double_pix_mode +//Bit 20 osd_hsc_phase0_always_en +//Bit 19 osd_hsc_nearest_en +//Bit 17:16 osd_hsc_rpt_p0_num1 +//Bit 14:11 osd_hsc_ini_rcv_num1 +//Bit 9:8 osd_hsc_rpt_p0_num0 +//Bit 6:3 osd_hsc_ini_rcv_num0 +//Bit 2:0 osd_hsc_bank_length +#define OSD34_HSC_CTRL0 ((0x3d25 << 2) + 0xff000000) +//for 3D quincunx sub-sampling +//bit 15:8 pattern, each patten 1 bit, from lsb -> msb +//bit 6:4 pattern start +//bit 2:0 pattern end +#define OSD34_HSC_INI_PAT_CTRL ((0x3d26 << 2) + 0xff000000) +//bit 31:24, componet 0 +//bit 23:16, component 1 +//bit 15:8, component 2 +//bit 7:0 component 3, alpha +#define OSD34_SC_DUMMY_DATA ((0x3d27 << 2) + 0xff000000) +//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. +//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha. +//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. +//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha. +//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source +//Bit 3 osd scaler path enable +//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix +#define OSD34_SC_CTRL0 ((0x3d28 << 2) + 0xff000000) +//Bit 28:16 OSD scaler input width minus 1 +//Bit 12:0 OSD scaler input height minus 1 +#define OSD34_SCI_WH_M1 ((0x3d29 << 2) + 0xff000000) +//Bit 28:16 OSD scaler output horizontal start +//Bit 12:0 OSD scaler output horizontal end +#define OSD34_SCO_H_START_END ((0x3d2a << 2) + 0xff000000) +//Bit 28:16 OSD scaler output vertical start +//Bit 12:0 OSD scaler output vertical end +#define OSD34_SCO_V_START_END ((0x3d2b << 2) + 0xff000000) +#define OSD34_DB_FLT_CTRL ((0x3d2c << 2) + 0xff000000) +//Bit 31:27 reserved +//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed +//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed +//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB +//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below +//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below +//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y; +//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m]) +//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6 +//Bit 16 reserved +//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6 +//Bit 12 reserved +//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6 +//Bit 8 reserved +//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma +//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma +//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma +//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma +//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +#define OSD34_DB_FLT_CTRL1 ((0x3d2d << 2) + 0xff000000) +//Bit 31:18 reserved +//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2 +//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8 +//Bit 11 reserved +//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6 +//Bit 7 reserved +//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6 +//Bit 3 reserved +//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6 +#define OSD34_DB_FLT_LUMA_THRD ((0x3d2e << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 23:22 reserved +//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4 +//Bit 15:14 reserved +//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else +#define OSD34_DB_FLT_CHRM_THRD ((0x3d2f << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 23:22 reserved +//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4 +//Bit 15:14 reserved +//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif +#define OSD34_DB_FLT_RANDLUT ((0x3d30 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7 +//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6 +//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5 +//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4 +//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3 +//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2 +//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1 +//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0 +#define OSD34_DB_FLT_PXI_THRD ((0x3d31 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise +//Bit 15:10 reserved +//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise +#define OSD34_DB_FLT_SEED_Y ((0x3d32 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default +#define OSD34_DB_FLT_SEED_U ((0x3d33 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default +#define OSD34_DB_FLT_SEED_V ((0x3d34 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD34_DB_FLT_SEED3 ((0x3d35 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD34_DB_FLT_SEED4 ((0x3d36 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +#define OSD34_DB_FLT_SEED5 ((0x3d37 << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default +// for osd3 & osd4 blend +#define OSD34_OUT_HSCOPE ((0x3d40 << 2) + 0xff000000) +#define OSD34_OUT_VSCOPE ((0x3d41 << 2) + 0xff000000) +#define OSD34_DUMMY_DATA ((0x3d42 << 2) + 0xff000000) +#define OSD34_BLEND_CTRL0 ((0x3d43 << 2) + 0xff000000) +#define OSD34_BLEND_CTRL1 ((0x3d44 << 2) + 0xff000000) +#define OSD34_RO_HV_CNT ((0x3d45 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_COEF00_01 ((0x3d60 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_COEF02_10 ((0x3d61 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_COEF11_12 ((0x3d62 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_COEF20_21 ((0x3d63 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_COEF22 ((0x3d64 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_COEF13_14 ((0x3d65 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_COEF23_24 ((0x3d66 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_COEF15_25 ((0x3d67 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_CLIP ((0x3d68 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 ((0x3d69 << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_OFFSET2 ((0x3d6a << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 ((0x3d6b << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 ((0x3d6c << 2) + 0xff000000) +#define VPP_WRAP_OSD1_MATRIX_EN_CTRL ((0x3d6d << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_COEF00_01 ((0x3d70 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_COEF02_10 ((0x3d71 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_COEF11_12 ((0x3d72 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_COEF20_21 ((0x3d73 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_COEF22 ((0x3d74 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_COEF13_14 ((0x3d75 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_COEF23_24 ((0x3d76 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_COEF15_25 ((0x3d77 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_CLIP ((0x3d78 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 ((0x3d79 << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_OFFSET2 ((0x3d7a << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 ((0x3d7b << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 ((0x3d7c << 2) + 0xff000000) +#define VPP_WRAP_OSD2_MATRIX_EN_CTRL ((0x3d7d << 2) + 0xff000000) +#define VIU_OSD3_CTRL_STAT ((0x3d80 << 2) + 0xff000000) +#define VIU_OSD3_CTRL_STAT2 ((0x3d81 << 2) + 0xff000000) +#define VIU_OSD3_COLOR_ADDR ((0x3d82 << 2) + 0xff000000) +#define VIU_OSD3_COLOR ((0x3d83 << 2) + 0xff000000) +#define VIU_OSD3_TCOLOR_AG0 ((0x3d84 << 2) + 0xff000000) +#define VIU_OSD3_TCOLOR_AG1 ((0x3d85 << 2) + 0xff000000) +#define VIU_OSD3_TCOLOR_AG2 ((0x3d86 << 2) + 0xff000000) +#define VIU_OSD3_TCOLOR_AG3 ((0x3d87 << 2) + 0xff000000) +#define VIU_OSD3_BLK0_CFG_W0 ((0x3d88 << 2) + 0xff000000) +#define VIU_OSD3_BLK1_CFG_W0 ((0x3d89 << 2) + 0xff000000) +#define VIU_OSD3_BLK2_CFG_W0 ((0x3d8a << 2) + 0xff000000) +#define VIU_OSD3_BLK3_CFG_W0 ((0x3d8b << 2) + 0xff000000) +#define VIU_OSD3_BLK0_CFG_W1 ((0x3d8c << 2) + 0xff000000) +#define VIU_OSD3_BLK1_CFG_W1 ((0x3d8d << 2) + 0xff000000) +#define VIU_OSD3_BLK2_CFG_W1 ((0x3d8e << 2) + 0xff000000) +#define VIU_OSD3_BLK3_CFG_W1 ((0x3d8f << 2) + 0xff000000) +#define VIU_OSD3_BLK0_CFG_W2 ((0x3d90 << 2) + 0xff000000) +#define VIU_OSD3_BLK1_CFG_W2 ((0x3d91 << 2) + 0xff000000) +#define VIU_OSD3_BLK2_CFG_W2 ((0x3d92 << 2) + 0xff000000) +#define VIU_OSD3_BLK3_CFG_W2 ((0x3d93 << 2) + 0xff000000) +#define VIU_OSD3_BLK0_CFG_W3 ((0x3d94 << 2) + 0xff000000) +#define VIU_OSD3_BLK1_CFG_W3 ((0x3d95 << 2) + 0xff000000) +#define VIU_OSD3_BLK2_CFG_W3 ((0x3d96 << 2) + 0xff000000) +#define VIU_OSD3_BLK3_CFG_W3 ((0x3d97 << 2) + 0xff000000) +#define VIU_OSD3_BLK0_CFG_W4 ((0x3d98 << 2) + 0xff000000) +#define VIU_OSD3_BLK1_CFG_W4 ((0x3d99 << 2) + 0xff000000) +#define VIU_OSD3_BLK2_CFG_W4 ((0x3d9a << 2) + 0xff000000) +#define VIU_OSD3_BLK3_CFG_W4 ((0x3d9b << 2) + 0xff000000) +#define VIU_OSD3_FIFO_CTRL_STAT ((0x3d9c << 2) + 0xff000000) +#define VIU_OSD3_TEST_RDDATA ((0x3d9d << 2) + 0xff000000) +#define VIU_OSD3_PROT_CTRL ((0x3d9e << 2) + 0xff000000) +#define VIU_OSD3_MALI_UNPACK_CTRL ((0x3d9f << 2) + 0xff000000) +#define VIU_OSD3_DIMM_CTRL ((0x3da0 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_COEF00_01 ((0x3db0 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_COEF02_10 ((0x3db1 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_COEF11_12 ((0x3db2 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_COEF20_21 ((0x3db3 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_COEF22 ((0x3db4 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_COEF13_14 ((0x3db5 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_COEF23_24 ((0x3db6 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_COEF15_25 ((0x3db7 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_CLIP ((0x3db8 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_OFFSET0_1 ((0x3db9 << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_OFFSET2 ((0x3dba << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_PRE_OFFSET0_1 ((0x3dbb << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_PRE_OFFSET2 ((0x3dbc << 2) + 0xff000000) +#define VIU_OSD3_MATRIX_EN_CTRL ((0x3dbd << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_COEF00_01 ((0x3db0 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_COEF02_10 ((0x3db1 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_COEF11_12 ((0x3db2 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_COEF20_21 ((0x3db3 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_COEF22 ((0x3db4 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_COEF13_14 ((0x3db5 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_COEF23_24 ((0x3db6 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_COEF15_25 ((0x3db7 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_CLIP ((0x3db8 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 ((0x3db9 << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_OFFSET2 ((0x3dba << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 ((0x3dbb << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 ((0x3dbc << 2) + 0xff000000) +#define VPP_WRAP_OSD3_MATRIX_EN_CTRL ((0x3dbd << 2) + 0xff000000) +#define VIU_OSD4_CTRL_STAT ((0x3dc0 << 2) + 0xff000000) +#define VIU_OSD4_CTRL_STAT2 ((0x3dc1 << 2) + 0xff000000) +#define VIU_OSD4_COLOR_ADDR ((0x3dc2 << 2) + 0xff000000) +#define VIU_OSD4_COLOR ((0x3dc3 << 2) + 0xff000000) +#define VIU_OSD4_TCOLOR_AG0 ((0x3dc4 << 2) + 0xff000000) +#define VIU_OSD4_TCOLOR_AG1 ((0x3dc5 << 2) + 0xff000000) +#define VIU_OSD4_TCOLOR_AG2 ((0x3dc6 << 2) + 0xff000000) +#define VIU_OSD4_TCOLOR_AG3 ((0x3dc7 << 2) + 0xff000000) +#define VIU_OSD4_BLK0_CFG_W0 ((0x3dc8 << 2) + 0xff000000) +#define VIU_OSD4_BLK1_CFG_W0 ((0x3dc9 << 2) + 0xff000000) +#define VIU_OSD4_BLK2_CFG_W0 ((0x3dca << 2) + 0xff000000) +#define VIU_OSD4_BLK3_CFG_W0 ((0x3dcb << 2) + 0xff000000) +#define VIU_OSD4_BLK0_CFG_W1 ((0x3dcc << 2) + 0xff000000) +#define VIU_OSD4_BLK1_CFG_W1 ((0x3dcd << 2) + 0xff000000) +#define VIU_OSD4_BLK2_CFG_W1 ((0x3dce << 2) + 0xff000000) +#define VIU_OSD4_BLK3_CFG_W1 ((0x3dcf << 2) + 0xff000000) +#define VIU_OSD4_BLK0_CFG_W2 ((0x3dd0 << 2) + 0xff000000) +#define VIU_OSD4_BLK1_CFG_W2 ((0x3dd1 << 2) + 0xff000000) +#define VIU_OSD4_BLK2_CFG_W2 ((0x3dd2 << 2) + 0xff000000) +#define VIU_OSD4_BLK3_CFG_W2 ((0x3dd3 << 2) + 0xff000000) +#define VIU_OSD4_BLK0_CFG_W3 ((0x3dd4 << 2) + 0xff000000) +#define VIU_OSD4_BLK1_CFG_W3 ((0x3dd5 << 2) + 0xff000000) +#define VIU_OSD4_BLK2_CFG_W3 ((0x3dd6 << 2) + 0xff000000) +#define VIU_OSD4_BLK3_CFG_W3 ((0x3dd7 << 2) + 0xff000000) +#define VIU_OSD4_BLK0_CFG_W4 ((0x3dd8 << 2) + 0xff000000) +#define VIU_OSD4_BLK1_CFG_W4 ((0x3dd9 << 2) + 0xff000000) +#define VIU_OSD4_BLK2_CFG_W4 ((0x3dda << 2) + 0xff000000) +#define VIU_OSD4_BLK3_CFG_W4 ((0x3ddb << 2) + 0xff000000) +#define VIU_OSD4_FIFO_CTRL_STAT ((0x3ddc << 2) + 0xff000000) +#define VIU_OSD4_TEST_RDDATA ((0x3ddd << 2) + 0xff000000) +#define VIU_OSD4_PROT_CTRL ((0x3dde << 2) + 0xff000000) +#define VIU_OSD4_MALI_UNPACK_CTRL ((0x3ddf << 2) + 0xff000000) +#define VIU_OSD4_DIMM_CTRL ((0x3de0 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_COEF00_01 ((0x3df0 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_COEF02_10 ((0x3df1 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_COEF11_12 ((0x3df2 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_COEF20_21 ((0x3df3 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_COEF22 ((0x3df4 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_COEF13_14 ((0x3df5 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_COEF23_24 ((0x3df6 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_COEF15_25 ((0x3df7 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_CLIP ((0x3df8 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_OFFSET0_1 ((0x3df9 << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_OFFSET2 ((0x3dfa << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_PRE_OFFSET0_1 ((0x3dfb << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_PRE_OFFSET2 ((0x3dfc << 2) + 0xff000000) +#define VIU_OSD4_MATRIX_EN_CTRL ((0x3dfd << 2) + 0xff000000) + // synopsys translate_off +// synopsys translate_on +// +// Closing file: vpu_osdsc_bld_regs.h +// +// ----------------------------------------------- +// REG_BASE: VPPF_VCBUS_BASE = 0x40 +// ----------------------------------------------- +// +// Reading file: lc_stts_curve.h +// +#define LC_CURVE_CTRL ((0x4000 << 2) + 0xff000000) + //Bit 31 :12 reg_lc_misc U RW default = 'h0 None + //Bit 11 :10 reserved U RW default = 'h0 None + //Bit 9 :8 reg_lc_hist_curve_nodes_hlpf U RW default = 'h1 horizontal lpf of the ram_curve_nodes, 0: no LPF, 1= [1 2 1]; 2: [1 2 2 2 1]/8 + //Bit 7 :6 reserved U RW default = 'h0 None + //Bit 5 :4 reg_lc_hist_curve_nodes_vlpf U RW default = 'h1 vertical lpf of the ram_curve_nodes, 0: no LPF, 1= [1 2 1]; 2: [1 2 2 2 1]/8 + //Bit 3 :2 reserved U RW default = 'h0 None + //Bit 1 reg_lc_blackbar_mute_en U RW default = 'h1 mute the black bar corresponding bin, 0: no mute, 1: mute enable; default=1 + //Bit 0 reg_lc_curve_en U RW default = 'h1 default=0 +#define LC_CURVE_HV_NUM ((0x4001 << 2) + 0xff000000) + //Bit 31 :13 reserved U RW default = 'h0 None + //Bit 12 :8 reg_lc_cur_blk_hnum U RW default = 'hc lc processing region number of V, maximum to (STA_LEN_V-1) (0~8), should be same as reg_lc_blk_hnum + //Bit 7 :5 reserved U RW default = 'h0 None + //Bit 4 :0 reg_lc_cur_blk_vnum U RW default = 'h8 lc processing region number of H, maximum to (STA_LEN_H-1) (0~12), should be same as reg_lc_blk_vnum +#define LC_CURVE_LMT_RAT ((0x4002 << 2) + 0xff000000) + //Bit 31 :16 reserved U RW default = 'h0 None + //Bit 15 :8 reg_lmtrat_minmax U RW default = 'h6 x/1024 of amount + //Bit 7 :0 reg_lmtrat_valid U RW default = 'h14 x/1024 of amount +#define LC_CURVE_CONTRAST_LH ((0x4003 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_contrast_low U RW default = 'h10 contrast gain to the lc for dark side, normalized 256 as "1", set adaptive TODO + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_contrast_hig U RW default = 'h18 contrast gain to the lc for bright side, normalized 256 as "1" +#define LC_CURVE_CONTRAST__LMT_LH ((0x4004 << 2) + 0xff000000) + //Bit 31 :24 reg_lc_cntstlmt_low_0 U RW default = 'ha limit for the contrast low, delta_low = MIN(delta_low, MIN( MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1])) + //Bit 23 :16 reg_lc_cntstlmt_hig_0 U RW default = 'h14 limit for the contrast high,delta_hig = MIN(delta_hig, MIN( MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1])) + //Bit 15 :8 reg_lc_cntstlmt_low_1 U RW default = 'hff limit for the contrast low, delta_low = MIN(delta_low, MIN( MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1])) + //Bit 7 :0 reg_lc_cntstlmt_hig_1 U RW default = 'hff limit for the contrast high,delta_hig = MIN(delta_hig, MIN( MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1])) +#define LC_CURVE_CONTRAST_SCL_LH ((0x4005 << 2) + 0xff000000) + //Bit 31 :16 reserved U RW default = 'h0 None + //Bit 15 :8 reg_lc_cntstscl_low U RW default = 'h40 scale for the contrast low, norm 8 as 1; delta_low = MIN(delta_low, MIN(MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1])) + //Bit 7 :0 reg_lc_cntstscl_hig U RW default = 'h20 scale for the contrast high,norm 8 as 1; delta_hig = MIN(delta_hig, MIN(MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1])) +#define LC_CURVE_CONTRAST_BVN_LH ((0x4006 << 2) + 0xff000000) + //Bit 31 :16 reserved U RW default = 'h0 None + //Bit 15 :8 reg_lc_cntstbvn_low U RW default = 'h20 scale to num_m as limit of min_val to minBV distance, to protect mono-color, default = 32; min_val= MAX(min_val, minBV- MAX(num_m-1,0)*bvn_low) + //Bit 7 :0 reg_lc_cntstbvn_hig U RW default = 'h20 scale to num_m as limit of max_val to maxBV distance, to protect mono-color, default = 32; min_val= MIN(max_val, maxBV+ MAX(num_m-1,0)*bvn_lo +#define LC_CURVE_MISC0 ((0x4007 << 2) + 0xff000000) + //Bit 31 :20 reserved U RW default = 'h0 None + //Bit 19 :16 reg_lc_num_m_coring U RW default = 'h1 coring to num_m, soft coring,default = 2; + //Bit 15 :8 reg_lc_vbin_min U RW default = 'h30 4x is min width of valid histogram bin num, + //Bit 7 :0 reg_lc_slope_max_face U RW default = 'h38 maximum slope for the pkBin-maxBV range curve to do face protection, normalized to 32 as 1, default= 48 +#define LC_CURVE_YPKBV_RAT ((0x4008 << 2) + 0xff000000) + //Bit 31 :24 reg_lc_ypkbv_ratio_0 U RW default = 'h8c x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1 + //Bit 23 :16 reg_lc_ypkbv_ratio_1 U RW default = 'ha0 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1 + //Bit 15 :8 reg_lc_ypkbv_ratio_2 U RW default = 'h78 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1 + //Bit 7 :0 reg_lc_ypkbv_ratio_3 U RW default = 'h60 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1 +#define LC_CURVE_YPKBV_SLP_LMT ((0x4009 << 2) + 0xff000000) + //Bit 31 :16 reserved U RW default = 'h0 None + //Bit 15 :8 reg_lc_ypkbv_slope_lmt_0 U RW default = 'hc min max slop for the curves to avoid artifacts, [0] for min_slope, [1] for max_slop, e.g.max_slope= limit*(pkBv-minBv)+min_val as high bound of the ypkBV; normalized to 32 as 1 + //Bit 7 :0 reg_lc_ypkbv_slope_lmt_1 U RW default = 'h60 None +#define LC_CURVE_YMINVAL_LMT_0_1 ((0x400a << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_yminval_lmt_0 U RW default = 'h30 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_yminval_lmt_1 U RW default = 'h50 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] +#define LC_CURVE_YMINVAL_LMT_2_3 ((0x400b << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_yminval_lmt_2 U RW default = 'h78 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_yminval_lmt_3 U RW default = 'h80 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] +#define LC_CURVE_YMINVAL_LMT_4_5 ((0x400c << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_yminval_lmt_4 U RW default = 'ha0 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_yminval_lmt_5 U RW default = 'hc4 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] +#define LC_CURVE_YMINVAL_LMT_6_7 ((0x400d << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_yminval_lmt_6 U RW default = 'he0 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_yminval_lmt_7 U RW default = 'h100 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] +#define LC_CURVE_YMINVAL_LMT_8_9 ((0x400e << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_yminval_lmt_8 U RW default = 'h120 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_yminval_lmt_9 U RW default = 'h140 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] +#define LC_CURVE_YMINVAL_LMT_10_11 ((0x400f << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_yminval_lmt_10 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_yminval_lmt_11 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] +#define LC_CURVE_YMAXVAL_LMT_0_1 ((0x4010 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ymaxval_lmt_0 U RW default = 'h78 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ymaxval_lmt_1 U RW default = 'h96 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... +#define LC_CURVE_YMAXVAL_LMT_2_3 ((0x4011 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ymaxval_lmt_2 U RW default = 'he6 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ymaxval_lmt_3 U RW default = 'h112 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... +#define LC_CURVE_YMAXVAL_LMT_4_5 ((0x4012 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ymaxval_lmt_4 U RW default = 'h14a lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ymaxval_lmt_5 U RW default = 'h180 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... +#define LC_CURVE_YMAXVAL_LMT_6_7 ((0x4013 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ymaxval_lmt_6 U RW default = 'h1d4 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ymaxval_lmt_7 U RW default = 'h200 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... +#define LC_CURVE_YMAXVAL_LMT_8_9 ((0x4014 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ymaxval_lmt_8 U RW default = 'h240 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ymaxval_lmt_9 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... +#define LC_CURVE_YMAXVAL_LMT_10_11 ((0x4015 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ymaxval_lmt_10 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ymaxval_lmt_11 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... +#define LC_CURVE_HISTVLD_THRD ((0x4016 << 2) + 0xff000000) + //Bit 31 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_histvld_thrd U RW default = 'h1fa threshold to compare to bin to get number of valid bins +#define LC_CURVE_BB_MUTE_THRD ((0x4017 << 2) + 0xff000000) + //Bit 31 :24 reserved U RW default = 'h0 None + //Bit 23 :0 reg_lc_blackbar_mute_thrd U RW default = 'h2a30 1/8 of the region +#define LC_CURVE_INT_STATUS ((0x4018 << 2) + 0xff000000) +#define LC_CURVE_RAM_CTRL ((0x4020 << 2) + 0xff000000) +#define LC_CURVE_RAM_ADDR ((0x4021 << 2) + 0xff000000) +#define LC_CURVE_RAM_DATA ((0x4022 << 2) + 0xff000000) +#define LC_CURVE_YMINVAL_LMT_12_13 ((0x4040 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_yminval_lmt_12 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_yminval_lmt_13 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] +#define LC_CURVE_YMINVAL_LMT_14_15 ((0x4041 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_yminval_lmt_14 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_yminval_lmt_15 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60] +#define LC_CURVE_YMAXVAL_LMT_12_13 ((0x4042 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ymaxval_lmt_12 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ymaxval_lmt_13 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... +#define LC_CURVE_YMAXVAL_LMT_14_15 ((0x4043 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ymaxval_lmt_14 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ymaxval_lmt_15 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ... +//u10, lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]) +#define LC_CURVE_YPKBV_LMT_0_1 ((0x4044 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ypkbv_lmt_0 U RW default = 'h78 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ypkbv_lmt_1 U RW default = 'h96 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... +#define LC_CURVE_YPKBV_LMT_2_3 ((0x4045 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ypkbv_lmt_2 U RW default = 'he6 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ypkbv_lmt_3 U RW default = 'h112 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... +#define LC_CURVE_YPKBV_LMT_4_5 ((0x4046 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ypkbv_lmt_4 U RW default = 'h14a lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ypkbv_lmt_5 U RW default = 'h180 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... +#define LC_CURVE_YPKBV_LMT_6_7 ((0x4047 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ypkbv_lmt_6 U RW default = 'h1d4 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ypkbv_lmt_7 U RW default = 'h200 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... +#define LC_CURVE_YPKBV_LMT_8_9 ((0x4048 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ypkbv_lmt_8 U RW default = 'h240 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ypkbv_lmt_9 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... +#define LC_CURVE_YPKBV_LMT_10_11 ((0x4049 << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ypkbv_lmt_10 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ypkbv_lmt_11 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... +#define LC_CURVE_YPKBV_LMT_12_13 ((0x404a << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ypkbv_lmt_12 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ypkbv_lmt_13 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... +#define LC_CURVE_YPKBV_LMT_14_15 ((0x404b << 2) + 0xff000000) + //Bit 31 :26 reserved U RW default = 'h0 None + //Bit 25 :16 reg_lc_ypkbv_lmt_14 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... + //Bit 15 :10 reserved U RW default = 'h0 None + //Bit 9 :0 reg_lc_ypkbv_lmt_15 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ... +//------------------------------------------------------------- +#define LC_STTS_GCLK_CTRL0 ((0x4028 << 2) + 0xff000000) +#define LC_STTS_CTRL0 ((0x4029 << 2) + 0xff000000) +#define LC_STTS_WIDTHM1_HEIGHTM1 ((0x402a << 2) + 0xff000000) +#define LC_STTS_MATRIX_COEF00_01 ((0x402b << 2) + 0xff000000) +#define LC_STTS_MATRIX_COEF02_10 ((0x402c << 2) + 0xff000000) +#define LC_STTS_MATRIX_COEF11_12 ((0x402d << 2) + 0xff000000) +#define LC_STTS_MATRIX_COEF20_21 ((0x402e << 2) + 0xff000000) +#define LC_STTS_MATRIX_COEF22 ((0x402f << 2) + 0xff000000) +#define LC_STTS_MATRIX_OFFSET0_1 ((0x4030 << 2) + 0xff000000) +#define LC_STTS_MATRIX_OFFSET2 ((0x4031 << 2) + 0xff000000) +#define LC_STTS_MATRIX_PRE_OFFSET0_1 ((0x4032 << 2) + 0xff000000) +#define LC_STTS_MATRIX_PRE_OFFSET2 ((0x4033 << 2) + 0xff000000) +#define LC_STTS_MATRIX_HL_COLOR ((0x4034 << 2) + 0xff000000) +#define LC_STTS_MATRIX_PROBE_POS ((0x4035 << 2) + 0xff000000) +#define LC_STTS_MATRIX_PROBE_COLOR ((0x4036 << 2) + 0xff000000) +#define LC_STTS_HIST_REGION_IDX ((0x4037 << 2) + 0xff000000) +#define LC_STTS_HIST_SET_REGION ((0x4038 << 2) + 0xff000000) +#define LC_STTS_HIST_READ_REGION ((0x4039 << 2) + 0xff000000) +#define LC_STTS_HIST_START_RD_REGION ((0x403a << 2) + 0xff000000) +#define LC_STTS_WHITE_INFO ((0x403b << 2) + 0xff000000) +#define LC_STTS_BLACK_INFO ((0x403c << 2) + 0xff000000) +// +// Closing file: lc_stts_curve.h +// +// ----------------------------------------------- +// REG_BASE: VDIN_AFBCE_VCBUS_BASE = 0x41 +// ----------------------------------------------- +// +// Reading file: vdin_afbce_regs.h +// +// synopsys translate_off +// synopsys translate_on +//=========================================================================== +// VDIN +//=========================================================================== +#define VDIN2_WR_CTRL ((0x4101 << 2) + 0xff000000) +#define VDIN2_WR_CTRL2 ((0x4102 << 2) + 0xff000000) +#define VDIN2_WR_H_START_END ((0x4103 << 2) + 0xff000000) +#define VDIN2_WR_V_START_END ((0x4104 << 2) + 0xff000000) +#define VDIN2_DBG_AXI_CMD_CNT ((0x4105 << 2) + 0xff000000) +#define VDIN2_DBG_AXI_DAT_CNT ((0x4106 << 2) + 0xff000000) +#define VDIN2_WR_URGENT_CTRL ((0x4107 << 2) + 0xff000000) +#define VDIN2_RO_WRMIF_STATUS ((0x4108 << 2) + 0xff000000) +#define VDIN_TOP_SECURE0_ST_RO ((0x4109 << 2) + 0xff000000) +#define VDIN_TOP_SECURE_DUMMY ((0x410a << 2) + 0xff000000) +#define VDIN_TOP_DOUBLE_CTRL ((0x410b << 2) + 0xff000000) +#define VDIN_TOP_SECURE1_ST_RO ((0x410c << 2) + 0xff000000) +#define VDIN_TOP_MISC ((0x410d << 2) + 0xff000000) +#define VDIN_TOP_SECURE_REG0 ((0x410e << 2) + 0xff000000) +#define VDIN_TOP_SECURE_REG1 ((0x410f << 2) + 0xff000000) +// 8'ha0 ~ 8'hc6 +// +// Reading file: vdin_afbc_enc_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define AFBCE_ENABLE ((0x41a0 << 2) + 0xff000000) +//Bit 31:20, gclk_ctrl unsigned , default = 0, +//Bit 19:16, afbce_sync_sel unsigned , default = 0, +//Bit 15:14, reserved +//Bit 13, enc_rst_mode unsigned , default = 0, +//Bit 12, enc_en_mode unsigned , default = 0, +//Bit 11:9, reserved +//Bit 8, enc_enable unsigned , default = 0, +//Bit 7:1, reserved +//Bit 0, reserved enc_frm_start pulse use this bit don't use +#define AFBCE_MODE ((0x41a1 << 2) + 0xff000000) +//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field +//Bit 28, reserved unsigned, default = 0 , enable singal of crop +//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode +//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent +//Bit 23, reserved +//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4 +//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4 +//Bit 13:1, reserved +//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb +#define AFBCE_SIZE_IN ((0x41a2 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel +#define AFBCE_BLK_SIZE_IN ((0x41a3 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel +#define AFBCE_HEAD_BADDR ((0x41a4 << 2) + 0xff000000) +//Bit 31:0, head_baddr unsigned, default = 32'h00; +#define AFBCE_MIF_SIZE ((0x41a5 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:28, ddr_blk_size unsigned, default = 1; +//Bit 27, reserved +//Bit 26:24, cmd_blk_size unsigned, default = 3; +//Bit 23:21, reserved +//Bit 20:16, uncmp_size unsigned, default = 20; +//Bit 15:0, mmu_page_size unsigned, default = 4096; +#define AFBCE_PIXEL_IN_HOR_SCOPE ((0x41a6 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; // +//Bit 15:13, reserved +//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; // +#define AFBCE_PIXEL_IN_VER_SCOPE ((0x41a7 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; // +//Bit 15:13, reserved +//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; // +#define AFBCE_CONV_CTRL ((0x41a8 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048 +//Bit 15:12, reserved +//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n +#define AFBCE_MIF_HOR_SCOPE ((0x41a9 << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25:16, blk_end_h unsigned, default = 0 ; // +//Bit 15:10, reserved +//Bit 9:0, blk_bgn_h unsigned, default = 59 ; // +#define AFBCE_MIF_VER_SCOPE ((0x41aa << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, blk_end_v unsigned, default = 0 ; // +//Bit 15:12, reserved +//Bit 11:0, blk_bgn_v unsigned, default = 269 ; // +#define AFBCE_STAT1 ((0x41ab << 2) + 0xff000000) +//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status +//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ; +#define AFBCE_STAT2 ((0x41ac << 2) + 0xff000000) +//Bit 31, reserved +//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ; +#define AFBCE_FORMAT ((0x41ad << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11:10 reserved +//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB +//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth +//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth +#define AFBCE_MODE_EN ((0x41ae << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:26 reserved +//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation +//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation +//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride +//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride +//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride +//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride +//Bit 19 reserved +//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable +//Bit 11 reserved +//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss +//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block +//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split +//Bit 7: 6 reserved +//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128 +//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128 +//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7 +//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value +#define AFBCE_DWSCALAR ((0x41af << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +#define AFBCE_DEFCOLOR_1 ((0x41b0 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr] +//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr] +#define AFBCE_DEFCOLOR_2 ((0x41b1 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr] +//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr] +#define AFBCE_QUANT_ENABLE ((0x41b2 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion +//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion +//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1; +//Bit 7: 5 reserved +//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy +//Bit 3: 1 reserved +//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy +#define AFBCE_IQUANT_LUT_1 ((0x41b3 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCE_IQUANT_LUT_2 ((0x41b4 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCE_IQUANT_LUT_3 ((0x41b5 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCE_IQUANT_LUT_4 ((0x41b6 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCE_RQUANT_LUT_1 ((0x41b7 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting) +//Bit 27 reserved +//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5 +//Bit 23 reserved +//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4 +//Bit 19 reserved +//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4 +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2 +#define AFBCE_RQUANT_LUT_2 ((0x41b8 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0 +#define AFBCE_RQUANT_LUT_3 ((0x41b9 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting) +//Bit 27 reserved +//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5 +//Bit 23 reserved +//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4 +//Bit 19 reserved +//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4 +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2 +#define AFBCE_RQUANT_LUT_4 ((0x41ba << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1 +//Bit 11 reserved +//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1 +//Bit 7 reserved +//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0 +#define AFBCE_YUV_FORMAT_CONV_MODE ((0x41bb << 2) + 0xff000000) +//Bit 31: 8 reserved +//Bit 7 reserved +//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0 +#define AFBCE_DUMMY_DATA ((0x41bc << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ; +#define AFBCE_CLR_FLAG ((0x41bd << 2) + 0xff000000) +//Bit 31:0 reg_afbce_clr_flag // unsigned, default = 0 ; +#define AFBCE_STA_FLAGT ((0x41be << 2) + 0xff000000) +//Bit 31:0 ro_afbce_sta_flag // unsigned, RO,default = 0 ; +#define AFBCE_MMU_NUM ((0x41bf << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ; +#define AFBCE_MMU_RMIF_CTRL1 ((0x41c0 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst +//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num +//Bit 15 reserved +//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd, + // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64 +//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64 +//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4 +//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable +//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable +//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable +//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable +//Bit 3 reserved +//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit +#define AFBCE_MMU_RMIF_CTRL2 ((0x41c1 << 2) + 0xff000000) +//Bit 31:30 reg_sw_rst // unsigned , default = 0, +//Bit 29:24 reserved +//Bit 23:18 reg_gclk_ctrl +//Bit 17 reserved +//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg : + // 16 reg_ugt_init : urgent initial value + // 15 reg_ugt_en : urgent enable + // 14 reg_ugt_type : 1= wrmif 0=rdmif + // 7:4 reg_ugt_top_th: urgent top threshold + // 3:0 reg_ugt_bot_th: urgent bottom threshold +#define AFBCE_MMU_RMIF_CTRL3 ((0x41c2 << 2) + 0xff000000) +//Bit 31:17 reserved +//Bit 16 reg_acc_mode // unsigned , default = 1, +//Bit 15:13 reserved +//Bit 12:0 reg_stride // unsigned , default = 4096, +#define AFBCE_MMU_RMIF_CTRL4 ((0x41c3 << 2) + 0xff000000) +//Bit 31:0 reg_baddr // unsigned , default = 0, +#define AFBCE_MMU_RMIF_SCOPE_X ((0x41c4 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position +#define AFBCE_MMU_RMIF_SCOPE_Y ((0x41c5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio +#define AFBCE_MMU_RMIF_RO_STAT ((0x41c6 << 2) + 0xff000000) +//Bit 15:0 reg_status // unsigned , +#define AFBCE_PIP_CTRL ((0x41ca << 2) + 0xff000000) +//Bit 31:3 reserved +//Bit 2 reg_enc_align_en //unsigned , RW,default = 1, +//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0, +//Bit 0 reg_pip_mode //unsigned , RW,default = 0, +#define AFBCE_ROT_CTRL ((0x41cb << 2) + 0xff000000) +//Bit 31:5 reserved +//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable +//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode +#define AFBCE_DIMM_CTRL ((0x41cc << 2) + 0xff000000) +//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal +//Bit 30 reserved +//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vdin_afbc_enc_regs.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vdin_afbce_regs.h +// +// ----------------------------------------------- +// REG_BASE: LCD2_VCBUS_BASE = 0x42 +// ----------------------------------------------- +//`include "a.h" +// ----------------------------------------------- +// REG_BASE: DOLBYTV_VCBUS_BASE = 0x43 +// ----------------------------------------------- +// +// Reading file: dolby_tv_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DOLBY_TV_REG_START ((0x4300 << 2) + 0xff000000) +// dolby register address 0~0xDA +#define DOLBY_TV_CLKGATE_CTRL ((0x43f1 << 2) + 0xff000000) +//bit[9:8] R-RW 0~3 0 dma2axi_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock" +//bit[7:6] R-RW 0~3 0 bl_dolby_swaps_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock" +//bit[5:4] R-RW 0~3 0 el_swaps_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock" +//bit[3:2] R-RW 0~3 0 el_buf_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock" +//bit[1:0] R-RW 0~3 0 top_level_reg_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock" +#define DOLBY_TV_SWAP_CTRL0 ((0x43f2 << 2) + 0xff000000) +//bit[2] R-RW 0~1 0 el_41mode : 1 "bl resolution : el resolution = 4:1", 0 "bl_res : el_res = 1:1" +//bit[1] R-RW 0~1 0 el_enable : 1 "enhancement layer is supported", 0 "el is not supported" +//bit[0] R-RW 0~1 0 source_enable : 1 "base layer is supported", 0 "bl is not supported" +#define DOLBY_TV_SWAP_CTRL1 ((0x43f3 << 2) + 0xff000000) +//bit[28:16] R-RW 0~8191 0 htotal : total pixels number in each line +//bit[21:0] R-RW 0~8191 0 vtotal : total line number in each frame (only support progress frame) +#define DOLBY_TV_SWAP_CTRL2 ((0x43f4 << 2) + 0xff000000) +//bit[28:16] R-RW 0~4096 0 hsize : active pixels number in each line +//bit[21:0] R-RW 0~3840 0 vsize : active lines number in each frame +#define DOLBY_TV_SWAP_CTRL3 ((0x43f5 << 2) + 0xff000000) +//bit[28:16] R-RW 0~8191 0 hsync_width : hsync signal width (high effective) +//bit[21:0] R-RW 0~8191 0 vsync_width : vysnc singal width (high effective) +#define DOLBY_TV_SWAP_CTRL4 ((0x43f6 << 2) + 0xff000000) +//bit[28:16] R-RW 0~8191 0 hsync_backporch : pixels number between hsync and h_active_duration +//bit[21:0] R-RW 0~8191 0 vsync_backporch : lines number between vsync and v_active_duration +#define DOLBY_TV_SWAP_CTRL5 ((0x43f7 << 2) + 0xff000000) +//[25:8] R-RW : reg_tunnel_sel for tunnel bit match swap +//bit[4] R-RW 0~1 0 bl_tunnel_mode : 1 "hdmi input, source is 12bit422 tunnel in 8bit444", 0 "opt mode, 10 bit 444" +//bit[3:2] R-RW 0~3 0 bl_uv_mode : 3 "uv=in_u", 2 "uv[0]=u[0],uv[1]=v[0]", 1 "uv[0]=v[0],uv[1]=u[0]", 0 "uv=in_v" +//bit[1:0] R-RW 0~3 0 el_uv_mode : 3 "uv=in_u", 2 "uv[0]=u[0],uv[1]=v[0]", 1 "uv[0]=v[0],uv[1]=u[0]", 0 "uv=in_v" +#define DOLBY_TV_SWAP_CTRL6 ((0x43f8 << 2) + 0xff000000) +//bit[31] R-RW 0~1 dm_uv_input : uv select +//bit[23:16] R-RW 0~1 0 dump_ctrl : 1 "fixed output bitdepth as 12bit", 0 "output bitdepth based on vdr_bit_depth" +//bit[15] R-RW 0~1 datapath_reset_n_enable : manual reset control +//bit[14] R-RW 0~1 handshake_reset_n_enable : manual reset control +//bit[13] R-RW 0~1 axi_reset_n_enable : manual reset control +//bit[5:2] R-RW 0~15 vdr_bit_depth +//bit[1:0] R-RW 0~3 reg_hdmi_mode +#define DOLBY_TV_SWAP_CTRL7 ((0x43f9 << 2) + 0xff000000) +//reserved +#define DOLBY_TV_AXI2DMA_CTRL0 ((0x43fa << 2) + 0xff000000) +//bit[31] R-RW 0~1 0 reg_req_en : enable req after line count +//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path +//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit +//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable +//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr +//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable +//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive +//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request +//bit[18:16] R-RW 0~7 0 reg_arsize : axi arsize +//bit[14:12] R-RW 0~7 0 reg_arprot : axi arprot +//bit[11:8] R-RW 0~15 0 reg_aruser : axi aruser +//bit[5:4] R-RW 0~3 0 reg_arid : axi arid +//bit[3:0] R-RW 0~2 0 reg_lens : default request lens, each burst has "reg_lens+1" data +#define DOLBY_TV_AXI2DMA_CTRL1 ((0x43fb << 2) + 0xff000000) +//bit[31] R-RW 0~1 0 axi_addr_mode : 1 "canvas mode", 0 "normal mode" +//bit[27:16] R-RW 0~4095 0 dma_size0 : total data number in dma0 +//bit[11:0] R-RW 0~4095 0 dma_size1 : total data number in dma1 +#define DOLBY_TV_AXI2DMA_CTRL2 ((0x43fc << 2) + 0xff000000) +//bit[31:0] R-RW 0~4294967295 0 axi_start_addr : axi start address +#define DOLBY_TV_AXI2DMA_CTRL3 ((0x43fd << 2) + 0xff000000) +//bit[11:0] R-RW 0~4095 0 hold_line : after hold_line the axi slave start requesting +#define DOLBY_TV_STATUS0 ((0x43fe << 2) + 0xff000000) +#define DOLBY_TV_STATUS1 ((0x43ff << 2) + 0xff000000) +#define DOLBY_TV_ADAPTIVE_SCALE_REGADDR ((0x43e0 << 2) + 0xff000000) +#define DOLBY_TV_ADAPTIVE_SCALE_REGDATA ((0x43e1 << 2) + 0xff000000) +#define DOLBY_TV_ADAPTIVE_SCALE_LUTADDR ((0x43e2 << 2) + 0xff000000) +#define DOLBY_TV_ADAPTIVE_SCALE_LUTDATA ((0x43e3 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: dolby_tv_regs.h +// +// ----------------------------------------------- +// REG_BASE: DOLBY1B_VCBUS_BASE = 0x44 +// ----------------------------------------------- +// +// Reading file: dolby1b_regs.h +// +// synopsys translate_off +// synopsys translate_on +#define DOLBY_CORE1B_REG_START ((0x4400 << 2) + 0xff000000) +#define DOLBY_CORE1B_CLKGATE_CTRL ((0x44f2 << 2) + 0xff000000) +#define DOLBY_CORE1B_SWAP_CTRL0 ((0x44f3 << 2) + 0xff000000) +#define DOLBY_CORE1B_SWAP_CTRL1 ((0x44f4 << 2) + 0xff000000) +#define DOLBY_CORE1B_SWAP_CTRL2 ((0x44f5 << 2) + 0xff000000) +#define DOLBY_CORE1B_SWAP_CTRL3 ((0x44f6 << 2) + 0xff000000) +#define DOLBY_CORE1B_SWAP_CTRL4 ((0x44f7 << 2) + 0xff000000) +#define DOLBY_CORE1B_SWAP_CTRL5 ((0x44f8 << 2) + 0xff000000) +#define DOLBY_CORE1B_DMA_CTRL ((0x44f9 << 2) + 0xff000000) +#define DOLBY_CORE1B_DMA_STATUS ((0x44fa << 2) + 0xff000000) +#define DOLBY_CORE1B_STATUS0 ((0x44fb << 2) + 0xff000000) +#define DOLBY_CORE1B_STATUS1 ((0x44fc << 2) + 0xff000000) +#define DOLBY_CORE1B_STATUS2 ((0x44fd << 2) + 0xff000000) +#define DOLBY_CORE1B_STATUS3 ((0x44fe << 2) + 0xff000000) +#define DOLBY_CORE1B_DMA_PORT ((0x44ff << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: dolby1b_regs.h +// +// ----------------------------------------------- +// REG_BASE: FGRAIN_VCBUS_BASE = 0x48 +// ----------------------------------------------- +//`include "afbcd_mult_regs.h" +// +// Reading file: afbcd_vd_regs.h +// +// synopsys translate_off +// synopsys translate_on +////===============================//// +// reg addr map +// 0 -3f : rdmif +// 40-6f : afbcd +// 70-7f : fgrain +////===============================//// +#define VD1_IF0_GEN_REG ((0x4800 << 2) + 0xff000000) +#define VD1_IF0_CANVAS0 ((0x4801 << 2) + 0xff000000) +#define VD1_IF0_CANVAS1 ((0x4802 << 2) + 0xff000000) +#define VD1_IF0_LUMA_X0 ((0x4803 << 2) + 0xff000000) +#define VD1_IF0_LUMA_Y0 ((0x4804 << 2) + 0xff000000) +#define VD1_IF0_CHROMA_X0 ((0x4805 << 2) + 0xff000000) +#define VD1_IF0_CHROMA_Y0 ((0x4806 << 2) + 0xff000000) +#define VD1_IF0_LUMA_X1 ((0x4807 << 2) + 0xff000000) +#define VD1_IF0_LUMA_Y1 ((0x4808 << 2) + 0xff000000) +#define VD1_IF0_CHROMA_X1 ((0x4809 << 2) + 0xff000000) +#define VD1_IF0_CHROMA_Y1 ((0x480a << 2) + 0xff000000) +#define VD1_IF0_RPT_LOOP ((0x480b << 2) + 0xff000000) +#define VD1_IF0_LUMA0_RPT_PAT ((0x480c << 2) + 0xff000000) +#define VD1_IF0_CHROMA0_RPT_PAT ((0x480d << 2) + 0xff000000) +#define VD1_IF0_LUMA1_RPT_PAT ((0x480e << 2) + 0xff000000) +#define VD1_IF0_CHROMA1_RPT_PAT ((0x480f << 2) + 0xff000000) +#define VD1_IF0_LUMA_PSEL ((0x4810 << 2) + 0xff000000) +#define VD1_IF0_CHROMA_PSEL ((0x4811 << 2) + 0xff000000) +#define VD1_IF0_DUMMY_PIXEL ((0x4812 << 2) + 0xff000000) +#define VD1_IF0_LUMA_FIFO_SIZE ((0x4813 << 2) + 0xff000000) +#define VD1_IF0_AXI_CMD_CNT ((0x4814 << 2) + 0xff000000) +#define VD1_IF0_AXI_RDAT_CNT ((0x4815 << 2) + 0xff000000) +#define VD1_IF0_RANGE_MAP_Y ((0x4816 << 2) + 0xff000000) +#define VD1_IF0_RANGE_MAP_CB ((0x4817 << 2) + 0xff000000) +#define VD1_IF0_RANGE_MAP_CR ((0x4818 << 2) + 0xff000000) +#define VD1_IF0_GEN_REG2 ((0x4819 << 2) + 0xff000000) +#define VD1_IF0_PROT ((0x481a << 2) + 0xff000000) +#define VD1_IF0_URGENT_CTRL ((0x481b << 2) + 0xff000000) +#define VD1_IF0_GEN_REG3 ((0x481c << 2) + 0xff000000) +#define VIU_VD1_FMT_CTRL ((0x481d << 2) + 0xff000000) +#define VIU_VD1_FMT_W ((0x481e << 2) + 0xff000000) +#define VD2_IF0_GEN_REG ((0x4880 << 2) + 0xff000000) +#define VD2_IF0_CANVAS0 ((0x4881 << 2) + 0xff000000) +#define VD2_IF0_CANVAS1 ((0x4882 << 2) + 0xff000000) +#define VD2_IF0_LUMA_X0 ((0x4883 << 2) + 0xff000000) +#define VD2_IF0_LUMA_Y0 ((0x4884 << 2) + 0xff000000) +#define VD2_IF0_CHROMA_X0 ((0x4885 << 2) + 0xff000000) +#define VD2_IF0_CHROMA_Y0 ((0x4886 << 2) + 0xff000000) +#define VD2_IF0_LUMA_X1 ((0x4887 << 2) + 0xff000000) +#define VD2_IF0_LUMA_Y1 ((0x4888 << 2) + 0xff000000) +#define VD2_IF0_CHROMA_X1 ((0x4889 << 2) + 0xff000000) +#define VD2_IF0_CHROMA_Y1 ((0x488a << 2) + 0xff000000) +#define VD2_IF0_RPT_LOOP ((0x488b << 2) + 0xff000000) +#define VD2_IF0_LUMA0_RPT_PAT ((0x488c << 2) + 0xff000000) +#define VD2_IF0_CHROMA0_RPT_PAT ((0x488d << 2) + 0xff000000) +#define VD2_IF0_LUMA1_RPT_PAT ((0x488e << 2) + 0xff000000) +#define VD2_IF0_CHROMA1_RPT_PAT ((0x488f << 2) + 0xff000000) +#define VD2_IF0_LUMA_PSEL ((0x4890 << 2) + 0xff000000) +#define VD2_IF0_CHROMA_PSEL ((0x4891 << 2) + 0xff000000) +#define VD2_IF0_DUMMY_PIXEL ((0x4892 << 2) + 0xff000000) +#define VD2_IF0_LUMA_FIFO_SIZE ((0x4893 << 2) + 0xff000000) +#define VD2_IF0_AXI_CMD_CNT ((0x4894 << 2) + 0xff000000) +#define VD2_IF0_AXI_RDAT_CNT ((0x4895 << 2) + 0xff000000) +#define VD2_IF0_RANGE_MAP_Y ((0x4896 << 2) + 0xff000000) +#define VD2_IF0_RANGE_MAP_CB ((0x4897 << 2) + 0xff000000) +#define VD2_IF0_RANGE_MAP_CR ((0x4898 << 2) + 0xff000000) +#define VD2_IF0_GEN_REG2 ((0x4899 << 2) + 0xff000000) +#define VD2_IF0_PROT ((0x489a << 2) + 0xff000000) +#define VD2_IF0_URGENT_CTRL ((0x489b << 2) + 0xff000000) +#define VD2_IF0_GEN_REG3 ((0x489c << 2) + 0xff000000) +#define VIU_VD2_FMT_CTRL ((0x489d << 2) + 0xff000000) +#define VIU_VD2_FMT_W ((0x489e << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: afbcd_vd_regs.h +// +//`include "fgrain_regs.h" //nouse +// ----------------------------------------------- +// REG_BASE: VPPC_VCBUS_BASE = 0x50 +// ----------------------------------------------- +// +// Reading file: srsharp_regs.h +// +// synopsys translate_off +// synopsys translate_on +//SRSHARP0 8'h00 - 8'hff +//SRSHARP1 8'h100 - 8'1ff +#define SRSHARP0_OFFSET (0x000<<2) +#define SRSHARP1_OFFSET (0x200<<2) + +// +// Reading file: sharp_regs.h +// +#define SHARP_HVSIZE ((0x5000 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_pknr_hsize . unsigned , default = 1920 +//Bit 15:13, reserved +//Bit 12: 0, reg_pknr_vsize . unsigned , default = 1080 +#define SHARP_HVBLANK_NUM ((0x5001 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_deband_hblank +//Bit 15: 8, reg_pknr_hblank_num . unsigned , default = 20 +//Bit 7: 0, reg_pknr_vblank_num . unsigned , default = 73 +#define NR_GAUSSIAN_MODE ((0x5002 << 2) + 0xff000000) +//Bit 31:14, reserved +//Bit 13:12, reg_nr_gau_ynorm : C adpative coef norm, 0: 128, 1: 256, 2: 512, 3: 1024 . unsigned , default = 0 +//Bit 11:10, reserved +//Bit 9: 8, reg_nr_gau_cnorm : C adpative coef norm, 0: 128, 1: 256, 2: 512, 3: 1024 . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 4, reg_nr_gau_ymode : 0 3x3 filter; 1: 5x5 filter; 2/3:adpative coef . unsigned , default = 1 +//Bit 3: 2, reserved +//Bit 1: 0, reg_nr_gau_cmode : 0 3x3 filter; 1: 5x5 filter; 2/3:adpative coef . unsigned , default = 1 +#define PK_CON_2CIRHPGAIN_TH_RATE ((0x5005 << 2) + 0xff000000) +//Bit 31:24, reg_pk_cirhpcon2gain0 : threshold0 of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 25 +//Bit 23:16, reg_pk_cirhpcon2gain1 : threshold1 of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 60 +//Bit 15: 8, reg_pk_cirhpcon2gain5 : rate0 (for hpcon<th0) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 80 +//Bit 7: 0, reg_pk_cirhpcon2gain6 : rate1 (for hpcon>th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 20 +#define PK_CON_2CIRHPGAIN_LIMIT ((0x5006 << 2) + 0xff000000) +//Bit 31:24, reg_pk_cirhpcon2gain2 : level limit(for hpcon<th0) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 155 +//Bit 23:16, reg_pk_cirhpcon2gain3 : level limit(for th0<hpcon<th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 150 +//Bit 15: 8, reg_pk_cirhpcon2gain4 : level limit(for hpcon>th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 5 +//Bit 7: 0, reserved +#define PK_CON_2CIRBPGAIN_TH_RATE ((0x5007 << 2) + 0xff000000) +//Bit 31:24, reg_pk_cirbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 20 +//Bit 23:16, reg_pk_cirbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same).. unsigned , default = 50 +//Bit 15: 8, reg_pk_cirbpcon2gain5 : rate0 (for bpcon<th0) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 50 +//Bit 7: 0, reg_pk_cirbpcon2gain6 : rate1 (for bpcon>th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 25 +#define PK_CON_2CIRBPGAIN_LIMIT ((0x5008 << 2) + 0xff000000) +//Bit 31:24, reg_pk_cirbpcon2gain2 : level limit(for bpcon<th0) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 155 +//Bit 23:16, reg_pk_cirbpcon2gain3 : level limit(for th0<bpcon<th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 150 +//Bit 15: 8, reg_pk_cirbpcon2gain4 : level limit(for bpcon>th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 5 +//Bit 7: 0, reserved +#define PK_CON_2DRTHPGAIN_TH_RATE ((0x5009 << 2) + 0xff000000) +//Bit 31:24, reg_pk_drthpcon2gain0 : threshold0 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 25 +//Bit 23:16, reg_pk_drthpcon2gain1 : threshold1 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 60 +//Bit 15: 8, reg_pk_drthpcon2gain5 : rate0 (for hpcon<th0) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 80 +//Bit 7: 0, reg_pk_drthpcon2gain6 : rate1 (for hpcon>th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 20 +#define PK_CON_2DRTHPGAIN_LIMIT ((0x500a << 2) + 0xff000000) +//Bit 31:24, reg_pk_drthpcon2gain2 : level limit(for hpcon<th0) of curve to map hpcon to hpgain for directional hp filter (best direction).. unsigned , default = 105 +//Bit 23:16, reg_pk_drthpcon2gain3 : level limit(for th0<hpcon<th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 96 +//Bit 15: 8, reg_pk_drthpcon2gain4 : level limit(for hpcon>th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 5 +//Bit 7: 0, reserved +#define PK_CON_2DRTBPGAIN_TH_RATE ((0x500b << 2) + 0xff000000) +//Bit 31:24, reg_pk_drtbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 20 +//Bit 23:16, reg_pk_drtbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50 +//Bit 15: 8, reg_pk_drtbpcon2gain5 : rate0 (for bpcon<th0) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50 +//Bit 7: 0, reg_pk_drtbpcon2gain6 : rate1 (for bpcon>th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 25 +#define PK_CON_2DRTBPGAIN_LIMIT ((0x500c << 2) + 0xff000000) +//Bit 31:24, reg_pk_drtbpcon2gain2 : level limit(for bpcon<th0) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 55 +//Bit 23:16, reg_pk_drtbpcon2gain3 : level limit(for th0<bpcon<th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 40 +//Bit 15: 8, reg_pk_drtbpcon2gain4 : level limit(for bpcon>th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 5 +//Bit 7: 0, reserved +#define PK_CIRFB_LPF_MODE ((0x500d << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:28, reg_cirhp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1 +//Bit 27:26, reserved +//Bit 25:24, reg_cirhp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1 +//Bit 23:22, reserved +//Bit 21:20, reg_cirhp_diag_mode : filter on HP; 1: [1 2 1]/4; . unsigned , default = 1 +//Bit 19:14, reserved +//Bit 13:12, reg_cirbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1 +//Bit 11:10, reserved +//Bit 9: 8, reg_cirbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1 +//Bit 7: 6, reserved +//Bit 5: 4, reg_cirbp_diag_mode : filter on BP; 1: [1 2 1]/4; . unsigned , default = 1 +//Bit 3: 0, reserved +#define PK_DRTFB_LPF_MODE ((0x500e << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:28, reg_drthp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1 +//Bit 27:26, reserved +//Bit 25:24, reg_drthp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1 +//Bit 23:22, reserved +//Bit 21:20, reg_drthp_diag_mode : filter on HP; 1: [1 2 1]/4; 1 . unsigned , default = 1 +//Bit 19:14, reserved +//Bit 13:12, reg_drtbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1 +//Bit 11:10, reserved +//Bit 9: 8, reg_drtbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1 +//Bit 7: 6, reserved +//Bit 5: 4, reg_drtbp_diag_mode : filter on BP; 1: [1 2 1]/4; 1 . unsigned , default = 1 +//Bit 3: 0, reserved +#define PK_CIRFB_HP_CORING ((0x500f << 2) + 0xff000000) +//Bit 31:22, reserved +//Bit 21:16, reg_cirhp_horz_core : coring of HP for Horz . unsigned , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_cirhp_vert_core : coring of HP for Vert . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_cirhp_diag_core : coring of HP for Diag . unsigned , default = 0 +#define PK_CIRFB_BP_CORING ((0x5010 << 2) + 0xff000000) +//Bit 31:22, reserved +//Bit 21:16, reg_cirbp_horz_core : coring of HP for Horz . unsigned , default = 1 +//Bit 15:14, reserved +//Bit 13: 8, reg_cirbp_vert_core : coring of HP for Vert . unsigned , default = 1 +//Bit 7: 6, reserved +//Bit 5: 0, reg_cirbp_diag_core : coring of HP for Diag . unsigned , default = 1 +#define PK_DRTFB_HP_CORING ((0x5011 << 2) + 0xff000000) +//Bit 31:22, reserved +//Bit 21:16, reg_drthp_horz_core : coring of HP for Horz . unsigned , default = 1 +//Bit 15:14, reserved +//Bit 13: 8, reg_drthp_vert_core : coring of HP for Vert . unsigned , default = 1 +//Bit 7: 6, reserved +//Bit 5: 0, reg_drthp_diag_core : coring of HP for Diag . unsigned , default = 1 +#define PK_DRTFB_BP_CORING ((0x5012 << 2) + 0xff000000) +//Bit 31:22, reserved +//Bit 21:16, reg_drtbp_horz_core : coring of HP for Horz . unsigned , default = 1 +//Bit 15:14, reserved +//Bit 13: 8, reg_drtbp_vert_core : coring of HP for Vert . unsigned , default = 1 +//Bit 7: 6, reserved +//Bit 5: 0, reg_drtbp_diag_core : coring of HP for Diag . unsigned , default = 1 +#define PK_CIRFB_BLEND_GAIN ((0x5013 << 2) + 0xff000000) +//Bit 31:28, reg_hp_cir_hgain : normalized 8 as '1' . unsigned , default = 8 +//Bit 27:24, reg_hp_cir_vgain : normalized 8 as '1' . unsigned , default = 8 +//Bit 23:20, reg_hp_cir_dgain : normalized 8 as '1' . unsigned , default = 8 +//Bit 19:16, reserved +//Bit 15:12, reg_bp_cir_hgain : normalized 8 as '1' . unsigned , default = 8 +//Bit 11: 8, reg_bp_cir_vgain : normalized 8 as '1' . unsigned , default = 8 +//Bit 7: 4, reg_bp_cir_dgain : normalized 8 as '1' . unsigned , default = 8 +//Bit 3: 0, reserved +#define NR_ALPY_SSD_GAIN_OFST ((0x5014 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_nr_alp0_ssd_gain : gain to max ssd normalized 16 as '1' . unsigned , default = 16 +//Bit 7: 6, reserved +//Bit 5: 0, reg_nr_alp0_ssd_ofst : offset to ssd before dividing to min_err . signed , default = -2 +#define NR_ALP0Y_ERR2CURV_TH_RATE ((0x5015 << 2) + 0xff000000) +//Bit 31:24, reg_nr_alp0_minerr_ypar0 : threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255.. unsigned , default = 10 +//Bit 23:16, reg_nr_alp0_minerr_ypar1 : threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25 +//Bit 15: 8, reg_nr_alp0_minerr_ypar5 : rate0 (for mierr<th0) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 80 +//Bit 7: 0, reg_nr_alp0_minerr_ypar6 : rate1 (for mierr>th1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64 +#define NR_ALP0Y_ERR2CURV_LIMIT ((0x5016 << 2) + 0xff000000) +//Bit 31:24, reg_nr_alp0_minerr_ypar2 : level limit(for mierr<th0) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for flat region. 0~255.. unsigned , default = 63 +//Bit 23:16, reg_nr_alp0_minerr_ypar3 : level limit(for th0<mierr<th1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for misc region. 0~255.. unsigned , default = 0 +//Bit 15: 8, reg_nr_alp0_minerr_ypar4 : level limit(for mierr>th1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63 +//Bit 7: 0, reserved +#define NR_ALP0C_ERR2CURV_TH_RATE ((0x5017 << 2) + 0xff000000) +//Bit 31:24, reg_nr_alp0_minerr_cpar0 : threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur.. unsigned , default = 10 +//Bit 23:16, reg_nr_alp0_minerr_cpar1 : threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25 +//Bit 15: 8, reg_nr_alp0_minerr_cpar5 : rate0 (for mierr<th0) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 80 +//Bit 7: 0, reg_nr_alp0_minerr_cpar6 : rate1 (for mierr>th1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64 +#define NR_ALP0C_ERR2CURV_LIMIT ((0x5018 << 2) + 0xff000000) +//Bit 31:24, reg_nr_alp0_minerr_cpar2 : level limit(for mierr<th0) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for flat region. 0~255.. unsigned , default = 63 +//Bit 23:16, reg_nr_alp0_minerr_cpar3 : level limit(for th0<mierr<th1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for misc region. 0~255.. unsigned , default = 0 +//Bit 15: 8, reg_nr_alp0_minerr_cpar4 : level limit(for mierr>th1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63 +//Bit 7: 0, reserved +#define NR_ALP0_MIN_MAX ((0x5019 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_nr_alp0_ymin : normalized to 64 as '1' . unsigned , default = 0 +//Bit 23:22, reserved +//Bit 21:16, reg_nr_alp0_ymax : normalized to 64 as '1' . unsigned , default = 63 +//Bit 15:14, reserved +//Bit 13: 8, reg_nr_alp0_cmin : normalized to 64 as '1' . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_nr_alp0_cmax : normalized to 64 as '1' . unsigned , default = 63 +#define NR_ALP1_MIERR_CORING ((0x501a << 2) + 0xff000000) +//Bit 31:17, reserved +//Bit 16, reg_nr_alp1_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_nr_alp1_core_rate : normalized 64 as "1" . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_nr_alp1_core_ofst : normalized 64 as "1" . signed , default = 3 +#define NR_ALP1_ERR2CURV_TH_RATE ((0x501b << 2) + 0xff000000) +//Bit 31:24, reg_nr_alp1_minerr_par0 : threshold0 of curve to map mierr to alp1 for luma/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255.. unsigned , default = 0 +//Bit 23:16, reg_nr_alp1_minerr_par1 : threshold1 of curve to map mierr to alp1 for luma/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255.. unsigned , default = 24 +//Bit 15: 8, reg_nr_alp1_minerr_par5 : rate0 (for mierr<th0) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope.. unsigned , default = 0 +//Bit 7: 0, reg_nr_alp1_minerr_par6 : rate1 (for mierr>th1) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255. unsigned , default = 20 +#define NR_ALP1_ERR2CURV_LIMIT ((0x501c << 2) + 0xff000000) +//Bit 31:24, reg_nr_alp1_minerr_par2 : level limit(for mierr<th0) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255.. unsigned , default = 0 +//Bit 23:16, reg_nr_alp1_minerr_par3 : level limit(for th0<mierr<th1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255.. unsigned , default = 16 +//Bit 15: 8, reg_nr_alp1_minerr_par4 : level limit(for mierr>th1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before. unsigned , default = 63 +//Bit 7: 0, reserved +#define NR_ALP1_MIN_MAX ((0x501d << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_nr_alp1_ymin : normalized to 64 as '1' . unsigned , default = 0 +//Bit 23:22, reserved +//Bit 21:16, reg_nr_alp1_ymax : normalized to 64 as '1' . unsigned , default = 63 +//Bit 15:14, reserved +//Bit 13: 8, reg_nr_alp1_cmin : normalized to 64 as '1' . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_nr_alp1_cmax : normalized to 64 as '1' . unsigned , default = 63 +#define PK_ALP2_MIERR_CORING ((0x501e << 2) + 0xff000000) +//Bit 31:17, reserved +//Bit 16, reg_pk_alp2_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 1 +//Bit 15:14, reserved +//Bit 13: 8, reg_pk_alp2_core_rate : normalized 64 as "1" . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_pk_alp2_core_ofst : normalized 64 as "1" . signed , default = 1 +#define PK_ALP2_ERR2CURV_TH_RATE ((0x501f << 2) + 0xff000000) +//Bit 31:24, reg_pk_alp2_minerr_par0 : threshold0 of curve to map mierr to alp2 for luma channel, this will be set value of flat region mierr that no need peaking.. unsigned , default = 0 +//Bit 23:16, reg_pk_alp2_minerr_par1 : threshold1 of curve to map mierr to alp2 for luma channel,this will be set value of texture region mierr that can not do peaking. 0~255.. unsigned , default = 24 +//Bit 15: 8, reg_pk_alp2_minerr_par5 : rate0 (for mierr<th0) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 0 +//Bit 7: 0, reg_pk_alp2_minerr_par6 : rate1 (for mierr>th1) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 20 +#define PK_ALP2_ERR2CURV_LIMIT ((0x5020 << 2) + 0xff000000) +//Bit 31:24, reg_pk_alp2_minerr_par2 : level limit(for mierr<th0) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for flat region. 0~255.. unsigned , default = 0 +//Bit 23:16, reg_pk_alp2_minerr_par3 : level limit(for th0<mierr<th1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for misc region. 0~255.. unsigned , default = 16 +//Bit 15: 8, reg_pk_alp2_minerr_par4 : level limit(for mierr>th1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for texture region. 0~255. default = 32;. unsigned , default = 32 +//Bit 7: 0, reserved +#define PK_ALP2_MIN_MAX ((0x5021 << 2) + 0xff000000) +//Bit 31:14, reserved +//Bit 13: 8, reg_pk_alp2_min : normalized to 64 as '1' . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_pk_alp2_max : normalized to 64 as '1' . unsigned , default = 63 +#define PK_FINALGAIN_HP_BP ((0x5022 << 2) + 0xff000000) +//Bit 31:18, reserved +//Bit 17:16, reg_final_gain_rs : s2: right shift bits for the gain normalization, 0 normal to 32 as 1; 1 normalize to 64 as 1; -2 normalized to 8 as 1; -1 normalize 16 as 1. default = 0 +//Bit 15: 8, reg_hp_final_gain : gain to highpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 40 +//Bit 7: 0, reg_bp_final_gain : gain to bandpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 30 +#define PK_OS_HORZ_CORE_GAIN ((0x5023 << 2) + 0xff000000) +//Bit 31:24, reg_pk_os_hsidecore : side coring (not to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8 +//Bit 23:16, reg_pk_os_hsidegain : side gain (not to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20 +//Bit 15: 8, reg_pk_os_hmidcore : midd coring (to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2 +//Bit 7: 0, reg_pk_os_hmidgain : midd gain (to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20 +#define PK_OS_VERT_CORE_GAIN ((0x5024 << 2) + 0xff000000) +//Bit 31:24, reg_pk_os_vsidecore : side coring (not to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8 +//Bit 23:16, reg_pk_os_vsidegain : side gain (not to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20 +//Bit 15: 8, reg_pk_os_vmidcore : midd coring (to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2 +//Bit 7: 0, reg_pk_os_vmidgain : midd gain (to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20 +#define PK_OS_ADPT_MISC ((0x5025 << 2) + 0xff000000) +//Bit 31:24, reg_pk_os_minerr_core : coring to minerr for adaptive overshoot margin. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 40 +//Bit 23:16, reg_pk_os_minerr_gain : gain to minerr based adaptive overshoot margin. normalized to 64 as '1'. 0~255;. unsigned , default = 6 +//Bit 15: 8, reg_pk_os_adpt_max : maximum limit adaptive overshoot margin (4x). 0~255; . unsigned , default = 200 +//Bit 7: 0, reg_pk_os_adpt_min : minimun limit adaptive overshoot margin (1x). 0~255; . unsigned , default = 20 +#define PK_OS_STATIC ((0x5026 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:28, reg_pk_osh_mode : 0~3: (2x+1) window in H direction . unsigned , default = 2 +//Bit 27:26, reserved +//Bit 25:24, reg_pk_osv_mode : 0~3: (2x+1) window in V direction . unsigned , default = 2 +//Bit 23:22, reserved +//Bit 21:12, reg_pk_os_down : static negative overshoot margin. 0~1023; . unsigned , default = 200 +//Bit 11:10, reserved +//Bit 9: 0, reg_pk_os_up : static positive overshoot margin. 0~1023; . unsigned , default = 200 +#define PK_NR_ENABLE ((0x5027 << 2) + 0xff000000) +//Bit 31: 4, reserved +//Bit 3: 2, reg_3d_mode , 0: no 3D; 1: L/R; 2: T/B; 3: horizontal interleaved, dft = 0 //. unsigned , default = 0 +//Bit 1, reg_pk_en . unsigned , default = 1 +//Bit 0, reg_nr_en . unsigned , default = 1 +#define PK_DRT_SAD_MISC ((0x5028 << 2) + 0xff000000) +//Bit 31:24, reg_pk_sad_ver_gain : gain to sad[4], 16 normalized to "1"; . unsigned , default = 32 +//Bit 23:16, reg_pk_sad_hor_gain : gain to sad[0], 16 normalized to "1"; . unsigned , default = 24 +//Bit 15:12, reserved +//Bit 11 reserved +//Bit 10: 9, reg_pk_bias_diag : bias towards diag . unsigned , default = 0 +//Bit 8, reserved +//Bit 7: 5, reserved +//Bit 4: 0, reg_pk_drt_force : force direction of drt peaking filter, h2b: 0:hp drt force, 1: bp drt force; 2: bp+hp drt force, 3: no force;. unsigned , default = 24 +#define NR_TI_DNLP_BLEND ((0x5029 << 2) + 0xff000000) +//Bit 31:11, reserved +//Bit 10: 8, reg_dnlp_input_mode : dnlp input options. 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os). unsigned , default = 4 +//Bit 7: 4, reserved +//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1 +//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2 +//////////////////////////////////////////////////////////////////////////////// +// new ti regsters from here +//////////////////////////////////////////////////////////////////////////////// +#define LTI_DIR_CORE_ALPHA ((0x502a << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_adp_lti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 10 +//Bit 23:20, reserved +//Bit 19:16, reg_adp_lti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_adp_lti_dir_alpmin : min value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=10 . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_adp_lti_dir_alpmax : max value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=63 . unsigned , default = 63 +#define CTI_DIR_ALPHA ((0x502b << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_adp_cti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 5 +//Bit 23:20, reserved +//Bit 19:16, reg_adp_cti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_adp_cti_dir_alpmin : min value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=10 . unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5: 0, reg_adp_cti_dir_alpmax : max value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=63 . unsigned , default = 63 +#define LTI_CTI_DF_GAIN ((0x502c << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_adp_lti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12 +//Bit 23:22, reserved +//Bit 21:16, reg_adp_lti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12 +//Bit 15:14, reserved +//Bit 13: 8, reg_adp_cti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12 +//Bit 7: 6, reserved +//Bit 5: 0, reg_adp_cti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12 +#define LTI_CTI_DIR_AC_DBG ((0x502d << 2) + 0xff000000) +//Bit 31, reserved +//Bit 30, reg_adp_lti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf . unsigned , default = 1 +//Bit 29, reserved +//Bit 28, reg_adp_lti_dir_difmode : 0: y_dif; 1: y_dif + (u_dif+v_dif)/2; . unsigned , default = 1 +//Bit 27, reserved +//Bit 26, reg_adp_cti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf dft=1 . unsigned , default = 1 +//Bit 25:24, reg_adp_cti_dir_difmode : 0: (u_dif+v_dif); 1: y_dif/2 + (u_dif+v_dif)*3/4; 2: y_dif + (u_dif+v_dif)/2; 3: y_dif*2 (not recomended). unsigned , default = 2 +//Bit 23:22, reg_adp_hvlti_dcblend_mode : 0: hlti_dc; 1:vlti_dc; 2: avg 3; blend on alpha . unsigned , default = 3 +//Bit 21:20, reg_adp_hvcti_dcblend_mode : 0: hcti_dc; 1:vcti_dc; 2: avg 3; blend on alpha . unsigned , default = 2 +//Bit 19:18, reg_adp_hvlti_acblend_mode : hlti_ac; 1:vlti_ac; 2: add 3;:adaptive to alpha . unsigned , default = 3 +//Bit 17:16, reg_adp_hvcti_acblend_mode : hcti_ac; 1:vcti_ac; 2: add 3;: adaptive to alpha . unsigned , default = 2 +//Bit 15, reserved +//Bit 14:12, reg_adp_hlti_debug , for hlti debug, default = 0 . unsigned , default = 0 +//Bit 11, reserved +//Bit 10: 8, reg_adp_vlti_debug , for vlti debug, default = 0 . unsigned , default = 0 +//Bit 7, reserved +//Bit 6: 4, reg_adp_hcti_debug , for hcti debug, default = 0 . unsigned , default = 0 +//Bit 3, reserved +//Bit 2: 0, reg_adp_vcti_debug , for vcti debug, default = 0 . unsigned , default = 0 +#define HCTI_FLT_CLP_DC ((0x502e << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28, reg_adp_hcti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1 +//Bit 27:26, reg_adp_hcti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 25:24, reg_adp_hcti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 2. unsigned , default = 2 +//Bit 23:22, reg_adp_hcti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 21:20, reg_adp_hcti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1 +//Bit 19:18, reg_adp_hcti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1 +//Bit 17:16, reg_adp_hcti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1 +//Bit 15:12, reg_adp_hcti_hard_clp_win , window size, 0~8, default = 5 . unsigned , default = 5 +//Bit 11: 8, reg_adp_hcti_hard_win_min , window size, 0~8, default = 3 . unsigned , default = 3 +//Bit 7: 5, reserved +//Bit 4, reg_adp_hcti_clp_mode , 0: hard clip, 1: adaptive clip, default = 1 . unsigned , default = 1 +//Bit 3, reserved +//Bit 2: 0, reg_adp_hcti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 0 . unsigned , default = 0 +#define HCTI_BST_GAIN ((0x502f << 2) + 0xff000000) +//Bit 31:24, reg_adp_hcti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 80 . unsigned , default = 80 +//Bit 23:16, reg_adp_hcti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 96 . unsigned , default = 96 +//Bit 15: 8, reg_adp_hcti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 64 . unsigned , default = 64 +//Bit 7: 0, reg_adp_hcti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 16 . unsigned , default = 16 +#define HCTI_BST_CORE ((0x5030 << 2) + 0xff000000) +//Bit 31:24, reg_adp_hcti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5 +//Bit 23:16, reg_adp_hcti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5 +//Bit 15: 8, reg_adp_hcti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5 +//Bit 7: 0, reg_adp_hcti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 5 +#define HCTI_CON_2_GAIN_0 ((0x5031 << 2) + 0xff000000) +//Bit 31:29, reg_adp_hcti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: .... default = 1. unsigned , default = 1 +//Bit 28:26, reg_adp_hcti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 2 . unsigned , default = 2 +//Bit 25:24, reg_adp_hcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0 +//Bit 23:16, reg_adp_hcti_con_2_gain0 , default = 25 . unsigned , default = 25 +//Bit 15: 8, reg_adp_hcti_con_2_gain1 , default = 60 . unsigned , default = 60 +//Bit 7: 0, reg_adp_hcti_con_2_gain2 0;, default = 5 . unsigned , default = 5 +#define HCTI_CON_2_GAIN_1 ((0x5032 << 2) + 0xff000000) +//Bit 31:24, reg_adp_hcti_con_2_gain3 96;, default = 96 . unsigned , default = 96 +//Bit 23:16, reg_adp_hcti_con_2_gain4 5;, default = 5 . unsigned , default = 5 +//Bit 15: 8, reg_adp_hcti_con_2_gain5 80;, default = 80 . unsigned , default = 80 +//Bit 7: 0, reg_adp_hcti_con_2_gain6 20;, default = 20 . unsigned , default = 20 +#define HCTI_OS_MARGIN ((0x5033 << 2) + 0xff000000) +//Bit 31: 8, reserved +//Bit 7: 0, reg_adp_hcti_os_margin : margin for hcti overshoot, default = 0 . unsigned , default = 0 +#define HLTI_FLT_CLP_DC ((0x5034 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28, reg_adp_hlti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1 +//Bit 27:26, reg_adp_hlti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 25:24, reg_adp_hlti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 1. unsigned , default = 1 +//Bit 23:22, reg_adp_hlti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 1 . unsigned , default = 1 +//Bit 21:20, reg_adp_hlti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1 +//Bit 19:18, reg_adp_hlti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1 +//Bit 17:16, reg_adp_hlti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1 +//Bit 15:12, reg_adp_hlti_hard_clp_win , window size, 0~8, default = 2 . unsigned , default = 2 +//Bit 11: 8, reg_adp_hlti_hard_win_min , window size, 0~8, default = 1 . unsigned , default = 1 +//Bit 7: 5, reserved +//Bit 4, reg_adp_hlti_clp_mode , 0: hard clip, 1: adaptive clip, default = 0 . unsigned , default = 0 +//Bit 3, reserved +//Bit 2: 0, reg_adp_hlti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 4 . unsigned , default = 4 +#define HLTI_BST_GAIN ((0x5035 << 2) + 0xff000000) +//Bit 31:24, reg_adp_hlti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 32 . unsigned , default = 32 +//Bit 23:16, reg_adp_hlti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 32 . unsigned , default = 32 +//Bit 15: 8, reg_adp_hlti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 28 . unsigned , default = 28 +//Bit 7: 0, reg_adp_hlti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 12 . unsigned , default = 12 +#define HLTI_BST_CORE ((0x5036 << 2) + 0xff000000) +//Bit 31:24, reg_adp_hlti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5 +//Bit 23:16, reg_adp_hlti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5 +//Bit 15: 8, reg_adp_hlti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5 +//Bit 7: 0, reg_adp_hlti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 3 +#define HLTI_CON_2_GAIN_0 ((0x5037 << 2) + 0xff000000) +//Bit 31:29, reg_adp_hlti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: ....., default = 1. unsigned , default = 1 +//Bit 28:26, reg_adp_hlti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 1 . unsigned , default = 1 +//Bit 25:24, reg_adp_hlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0 +//Bit 23:16, reg_adp_hlti_con_2_gain0 25;, default = 25 . unsigned , default = 25 +//Bit 15: 8, reg_adp_hlti_con_2_gain1 60;, default = 60 . unsigned , default = 60 +//Bit 7: 0, reg_adp_hlti_con_2_gain2 0;, default = 5 . unsigned , default = 5 +#define HLTI_CON_2_GAIN_1 ((0x5038 << 2) + 0xff000000) +//Bit 31:24, reg_adp_hlti_con_2_gain3 96;, default = 96 . unsigned , default = 96 +//Bit 23:16, reg_adp_hlti_con_2_gain4 5;, default = 95 . unsigned , default = 95 +//Bit 15: 8, reg_adp_hlti_con_2_gain5 80;, default = 80 . unsigned , default = 80 +//Bit 7: 0, reg_adp_hlti_con_2_gain6 20;, default = 20 . unsigned , default = 20 +#define HLTI_OS_MARGIN ((0x5039 << 2) + 0xff000000) +//Bit 31: 8, reserved +//Bit 7: 0, reg_adp_hlti_os_margin : margin for hlti overshoot, default = 0 . unsigned , default = 0 +#define VLTI_FLT_CON_CLP ((0x503a << 2) + 0xff000000) +//Bit 31:15, reserved +//Bit 14, reg_adp_vlti_en : enable bit of vlti, default = 1 . unsigned , default = 1 +//Bit 13:12, reg_adp_vlti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 11:10, reg_adp_vlti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 9: 8, reg_adp_vlti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 7: 6, reg_adp_vlti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 5: 4, reg_adp_vlti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1 +//Bit 3, reserved +//Bit 2, reg_adp_vlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0 +//Bit 1, reserved +//Bit 0, reg_adp_vlti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0 +#define VLTI_BST_GAIN ((0x503b << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_adp_vlti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 32 . unsigned , default = 32 +//Bit 15: 8, reg_adp_vlti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 32 . unsigned , default = 32 +//Bit 7: 0, reg_adp_vlti_bst_gain2 : gain to boost filter usf, default = 32 . unsigned , default = 32 +#define VLTI_BST_CORE ((0x503c << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_adp_vlti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5 +//Bit 15: 8, reg_adp_vlti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5 +//Bit 7: 0, reg_adp_vlti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3 +#define VLTI_CON_2_GAIN_0 ((0x503d << 2) + 0xff000000) +//Bit 31:24, reg_adp_vlti_con_2_gain0 25;, default = 25 . unsigned , default = 25 +//Bit 23:16, reg_adp_vlti_con_2_gain1 60;, default = 60 . unsigned , default = 60 +//Bit 15: 8, reg_adp_vlti_con_2_gain2 0;, default = 5 . unsigned , default = 5 +//Bit 7: 0, reg_adp_vlti_con_2_gain3 96;, default = 96 . unsigned , default = 96 +#define VLTI_CON_2_GAIN_1 ((0x503e << 2) + 0xff000000) +//Bit 31:24, reg_adp_vlti_con_2_gain4 5;, default = 95 . unsigned , default = 95 +//Bit 23:16, reg_adp_vlti_con_2_gain5 80;, default = 80 . unsigned , default = 80 +//Bit 15: 8, reg_adp_vlti_con_2_gain6 20;, default = 20 . unsigned , default = 20 +//Bit 7: 0, reg_adp_vlti_os_margin : margin for vlti overshoot, default = 0 . unsigned , default = 0 +#define VCTI_FLT_CON_CLP ((0x503f << 2) + 0xff000000) +//Bit 31:15, reserved +//Bit 14, reg_adp_vcti_en : enable bit of vlti, default = 1 . unsigned , default = 1 +//Bit 13:12, reg_adp_vcti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 11:10, reg_adp_vcti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 9: 8, reg_adp_vcti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 7: 6, reg_adp_vcti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2 +//Bit 5: 4, reg_adp_vcti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1 +//Bit 3, reserved +//Bit 2, reg_adp_vcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0 +//Bit 1, reserved +//Bit 0, reg_adp_vcti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0 +#define VCTI_BST_GAIN ((0x5040 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_adp_vcti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 16 . unsigned , default = 16 +//Bit 15: 8, reg_adp_vcti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 16 . unsigned , default = 16 +//Bit 7: 0, reg_adp_vcti_bst_gain2 : gain to boost filter usf, default = 16 . unsigned , default = 16 +#define VCTI_BST_CORE ((0x5041 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_adp_vcti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5 +//Bit 15: 8, reg_adp_vcti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5 +//Bit 7: 0, reg_adp_vcti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3 +#define VCTI_CON_2_GAIN_0 ((0x5042 << 2) + 0xff000000) +//Bit 31:24, reg_adp_vcti_con_2_gain0 25;, default = 25 . unsigned , default = 25 +//Bit 23:16, reg_adp_vcti_con_2_gain1 60;, default = 60 . unsigned , default = 60 +//Bit 15: 8, reg_adp_vcti_con_2_gain2 0;, default = 5 . unsigned , default = 5 +//Bit 7: 0, reg_adp_vcti_con_2_gain3 96;, default = 96 . unsigned , default = 96 +#define VCTI_CON_2_GAIN_1 ((0x5043 << 2) + 0xff000000) +//Bit 31:24, reg_adp_vcti_con_2_gain4 5;, default = 95 . unsigned , default = 95 +//Bit 23:16, reg_adp_vcti_con_2_gain5 80;, default = 80 . unsigned , default = 80 +//Bit 15: 8, reg_adp_vcti_con_2_gain6 20;, default = 20 . unsigned , default = 20 +//Bit 7: 0, reg_adp_vcti_os_margin : margin for vcti overshoot, default = 0 . unsigned , default = 0 +#define SHARP_3DLIMIT ((0x5044 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, reg_3d_mid_width ,width of left part of 3d input, dft = half size of input width default = 0 . unsigned , default = 960 +//Bit 15:13, reserved +//Bit 12: 0, reg_3d_mid_height ,height of left part of 3d input, dft = half size of input height default = 0 . unsigned , default = 540 +#define DNLP_EN ((0x5045 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_dnlp_hblank +//Bit 7: 1, reserved +//Bit 0, reg_dnlp_en . unsigned , default = 1 +#define DEMO_CRTL ((0x5056 << 2) + 0xff000000) +//Bit 31:19, reserved +//Bit 18:17, demo_disp_position . unsigned , default = 2 +//Bit 16, demo_hsvsharp_enable . unsigned , default = 0 +//Bit 15:13, reserved +//Bit 12: 0, demo_left_top_screen_width : . unsigned , default = 360 +#define SHARP_SR2_CTRL ((0x5057 << 2) + 0xff000000) +//Bit 31:25, reserved +//Bit 24 reg_sr2_bic_pknr_bypass : +//Bit 23:22 reserved +//Bit 21:16, reg_sr2_pk_la_err_dis_rate : . unsigned , low angle and high angle error should not be no less than nearby_error*rate/64; default = 24 +//Bit 15:8, reg_sr2_pk_sad_diag_gain : . unsigned , gain to sad[2] and sad[6], 16 normalized to "1"; default = 16 +//Bit 7, reg_sr2_vert_outphs : . unsigned , default = 0 +//Bit 6, reg_sr2_horz_outphs : . unsigned , default = 0 +//Bit 5, reg_sr2_vert_ratio : . unsigned , default = 0 +//Bit 4, reg_sr2_hori_ratio : . unsigned , default = 0 +//Bit 3, reg_sr2_bic_norm : . unsigned , default = 1 +//Bit 2, reg_sr2_enable : . unsigned , default = 0 +//Bit 1, reg_sr2_sharp_prc_lr_hbic : . unsigned , default = 0 +//Bit 0, reg_sr2_sharp_prc_lr : lti/cti/nr/peaking processing using LR grid, 0: on HR grid; 1:on LR grid, horizontally no upscale, but using simple bic . unsigned , default = 0 +#define SHARP_SR2_YBIC_HCOEF0 ((0x5058 << 2) + 0xff000000) +//Bit 31:24, reg_sr2_y_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel Filter will be normalized to 128 as �� default=0 +//Bit 23:16, reg_sr2_y_bic_hcoef02 the same as above; default=0 +//Bit 15: 8, reg_sr2_y_bic_hcoef01 the same as above; default=64 +//Bit 7: 0, reg_sr2_y_bic_hcoef00 the same as above; default=0 +#define SHARP_SR2_YBIC_HCOEF1 ((0x5059 << 2) + 0xff000000) +//Bit 31:24, reg_sr2_y_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as �� default=-4 +//Bit 23:16, reg_sr2_y_bic_hcoef12 the same as above; default=36 +//Bit 15: 8, reg_sr2_y_bic_hcoef11 the same as above; default=36 +//Bit 7: 0, reg_sr2_y_bic_hcoef10 the same as above; default=-4 +#define SHARP_SR2_CBIC_HCOEF0 ((0x505a << 2) + 0xff000000) +//Bit 31:24, reg_sr2_c_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel ,Filter will be normalized to 128 as �� default=0 +//Bit 23:16, reg_sr2_c_bic_hcoef02 the same as above; default=21 +//Bit 15: 8, reg_sr2_c_bic_hcoef01 the same as above; default=22 +//Bit 7: 0, reg_sr2_c_bic_hcoef00 the same as above; default=21 +#define SHARP_SR2_CBIC_HCOEF1 ((0x505b << 2) + 0xff000000) +//Bit 31:24, reg_sr2_c_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as �� default=-4 +//Bit 23:16, reg_sr2_c_bic_hcoef12 the same as above; default=36 +//Bit 15: 8, reg_sr2_c_bic_hcoef11 the same as above; default=36 +//Bit 7: 0, reg_sr2_c_bic_hcoef10 the same as above; default=-4 +#define SHARP_SR2_YBIC_VCOEF0 ((0x505c << 2) + 0xff000000) +//Bit 31:24, reg_sr2_y_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as �� default=0 +//Bit 23:16, reg_sr2_y_bic_vcoef02 the same as above; default=0 +//Bit 15: 8, reg_sr2_y_bic_vcoef01 the same as above; default=64 +//Bit 7: 0, reg_sr2_y_bic_vcoef00 the same as above; default=0 +#define SHARP_SR2_YBIC_VCOEF1 ((0x505d << 2) + 0xff000000) +//Bit 31:24, reg_sr2_y_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channe, lFilter will be normalized to 128 as �� default=-4 +//Bit 23:16, reg_sr2_y_bic_vcoef12 the same as above; default=36 +//Bit 15: 8, reg_sr2_y_bic_vcoef11 the same as above; default=36 +//Bit 7: 0, reg_sr2_y_bic_vcoef10 the same as above; default=-4 +#define SHARP_SR2_CBIC_VCOEF0 ((0x505e << 2) + 0xff000000) +//Bit 31:24, reg_sr2_c_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as �� default=0 +//Bit 23:16, reg_sr2_c_bic_vcoef02 the same as above; default=21 +//Bit 15: 8, reg_sr2_c_bic_vcoef01 the same as above; default=22 +//Bit 7: 0, reg_sr2_c_bic_vcoef00 the same as above; default=21 +#define SHARP_SR2_CBIC_VCOEF1 ((0x505f << 2) + 0xff000000) +//Bit 31:24, reg_sr2_c_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as �� default=-4 +//Bit 23:16, reg_sr2_c_bic_vcoef12 the same as above; default=36 +//Bit 15: 8, reg_sr2_c_bic_vcoef11 the same as above; default=36 +//Bit 7: 0, reg_sr2_c_bic_vcoef10 the same as above; default=-4 +#define SHARP_SR2_MISC ((0x5060 << 2) + 0xff000000) +//Bit 31:2, reserved +//Bit 1, reg_sr2_cmpmux_bef : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for RGB->GBR; +//Bit 0, reg_sr2_cmpmux_aft : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for GBR-RGB; +#define SHARP_SR3_SAD_CTRL ((0x5061 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_sr3_pk_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 +//Bit 23:22 reserved +//Bit 21:16 reg_sr3_lti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6 +//Bit 15:14 reserved +//Bit 13:8 reg_sr3_cti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6 +//Bit 7, reg_sr3_lti_hsad_mode // u1: mode for hsad of lti caluclation; 0: block based; 1:othor shape; default= 1 +//Bit 6, reg_sr3_cti_hsad_mode // u1: mode for hsad of cti caluclation; 0: block based; 1:othor shape; default= 1 +//Bit 5, reg_sr3_lti_dsad_mode // u1: mode for dsad of lti caluclation, 0: block based; 1:othor shape; default= 1 +//Bit 4, reg_sr3_cti_dsad_mode // u1: mode for dsad of cti caluclation, 0: block based; 1:othor shape; default= 1 +//Bit 3, reg_sr3_lti_vsad_mode // u1: mode for vsad of lti caluclation, 0: block based; 1:othor shape; default= 1 +//Bit 2, reg_sr3_cti_vsad_mode // u1: mode for vsad of cti caluclation, 0: block based; 1:othor shape; default= 1 +//Bit 1, reg_sr3_lti_hsad_hlpf // u1: hlpf for hsad of lti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1 +//Bit 0, reg_sr3_cti_hsad_hlpf // u1: hlpf for hsad of cti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1 +#define SHARP_SR3_PK_CTRL0 ((0x5062 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11, reg_sr3_pk_sad_mode // u1: mode for sad of peaking and noise reduction, 0: block based; 1:othor shape; default= 1 +//Bit 10, reg_sr3_pk_hsad_hlpf // u1: hlpf for hsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1 +//Bit 9, reg_sr3_pk_vsad_hlpf // u1: hlpf for vsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1 +//Bit 8, reg_sr3_pk_dsad_hlpf // u1: hlpf for dsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1 +//Bit 7:6, reg_sr3_pk_hpdrt_mode // u2: mode for HPdrt filter: default= 3 +//Bit 5:4, reg_sr3_pk_bpdrt_mode // u2: mode for BPdrt filter: default= 3 +//Bit 3:2, reg_sr3_pk_drtbld_range // u2: range of the min2 and min direction distance; default =1 +//Bit 1, reserved +//Bit 0, reg_sr3_pk_ti_blend_mode // u1: blend mode of the TI and PK results: default = 0; +#define SHARP_SR3_PK_CTRL1 ((0x5063 << 2) + 0xff000000) +//Bit 31, reserved +//Bit 30:28, reg_sr3_pk_hp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1 +//Bit 27, reserved +//Bit 26:24, reg_sr3_pk_bp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1 +//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32; +//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32; +//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1 +//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1 +//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12 +#define SHARP_DEJ_CTRL ((0x5064 << 2) + 0xff000000) +//Bit 31:4 reserved +//Bit 15:8, reg_sr3_dejaggy_hblank // u8 +//Bit 7:4 reserved +//Bit 3:2, reg_sr3_dejaggy_sameside_prtct // u2: enable of sr3 dejaggy same side curve protect from filter, [0] for proc, [1] for ctrl path, default=3 +//Bit 1, reg_sr3_dejaggy_sameside_mode // u1: mode of the sameside flag decision: default =1 +//Bit 0, reg_sr3_dejaggy_enable // u1: enable of sr3 dejaggy: default =0 +#define SHARP_DEJ_ALPHA ((0x5065 << 2) + 0xff000000) +//Bit 31:28, reg_sr3_dejaggy_ctrlchrm_alpha_1 //u4: alpha for LR video LPF, default = 0 +//Bit 27:24, reg_sr3_dejaggy_ctrlchrm_alpha_0 //u4: alpha for LR video LPF, default = 15 +//Bit 23:20, reg_sr3_dejaggy_ctrlluma_alpha_1 //u4: alpha for LR video LPF, default = 0 +//Bit 19:16, reg_sr3_dejaggy_ctrlluma_alpha_0 //u4: alpha for LR video LPF, default = 15 +//Bit 15:12, reg_sr3_dejaggy_procchrm_alpha_1 //u4: alpha for LR video LPF, default = 4 +//Bit 11:8, reg_sr3_dejaggy_procchrm_alpha_0 //u4: alpha for LR video LPF, default = 6 +//Bit 7:4, reg_sr3_dejaggy_procluma_alpha_1 //u4: alpha for LR video LPF, default = 4 +//Bit 3:0, reg_sr3_dejaggy_procluma_alpha_0 //u4: alpha for LR video LPF, default = 6 +#define SHARP_SR3_DRTLPF_EN ((0x5066 << 2) + 0xff000000) +//Bit 31:15 reserved +//Bit 14:8, reg_pk_debug_edge . unsigned , default = 0 +//Bit 7, reserved +//Bit 6:4, reg_sr3_drtlpf_theta_en //u1x3 theta (pure vertical and horizontal HF burst protection) enable. 0: not enable, 1:enable protection +//Bit 3, reserved +//Bit 2:0 reg_sr3_drtlpf_enable //u1x3 directional lpf on luma U and V channels, default = 7 +#define SHARP_SR3_DRTLPF_ALPHA_0 ((0x5067 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_sr3_drtlpf_alpha3 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 9 +//Bit 23:22 reserved +//Bit 21:16 reg_sr3_drtlpf_alpha2 //u6: default =10 +//Bit 15:14 reserved +//Bit 13:8 reg_sr3_drtlpf_alpha1 //u6: default = 11 +//Bit 7:6 reserved +//Bit 5:0 reg_sr3_drtlpf_alpha0 //u6: default = 12 +#define SHARP_SR3_DRTLPF_ALPHA_1 ((0x5068 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_sr3_drtlpf_alpha7 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 1 +//Bit 23:22 reserved +//Bit 21:16 reg_sr3_drtlpf_alpha6 //u6: default = 4 +//Bit 15:14 reserved +//Bit 13:8 reg_sr3_drtlpf_alpha5 //u6: default = 7 +//Bit 7:6 reserved +//Bit 5:0 reg_sr3_drtlpf_alpha4 //u6: default = 8 +#define SHARP_SR3_DRTLPF_ALPHA_2 ((0x5069 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_sr3_drtlpf_alpha11 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 0 +//Bit 23:22 reserved +//Bit 21:16 reg_sr3_drtlpf_alpha10 //u6: default = 0 +//Bit 15:14 reserved +//Bit 13:8 reg_sr3_drtlpf_alpha9 //u6: default = 0 +//Bit 7:6 reserved +//Bit 5:0 reg_sr3_drtlpf_alpha8 //u6: default = 0 +#define SHARP_SR3_DRTLPF_ALPHA_OFST ((0x506a << 2) + 0xff000000) +//Bit 31:28 reg_sr3_drtlpf_alpha_ofst7 //s4: directional lpf alpha coef ofset of each directions, default = -8 +//Bit 27:24 reg_sr3_drtlpf_alpha_ofst6 //s4: default = -8 +//Bit 23:20 reg_sr3_drtlpf_alpha_ofst5 //s4: default = -8 +//Bit 19:16 reg_sr3_drtlpf_alpha_ofst4 //s4: default = -8 +//Bit 15:12 reg_sr3_drtlpf_alpha_ofst3 //s4: default = -8 +//Bit 11:8 reg_sr3_drtlpf_alpha_ofst2 //s4: default = -8 +//Bit 7:4 reg_sr3_drtlpf_alpha_ofst1 //s4: default = -8 +//Bit 3:0 reg_sr3_drtlpf_alpha_ofst0 //s4: default = -8 +#define SHARP_SR3_DERING_CTRL ((0x506b << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_sr3_dering_enable // u3: dering enable bits; default = 1 +//Bit 27 reserved +//Bit 26:24 reg_sr3_dering_varlpf_mode // u3: local variant LPF mode: 0 no filter, 1, errosion 3x3; 2: 3x3 lpf; 3 and up: 3x3 errosion + lpf default = 3 +//Bit 23:20 reg_sr3_dering_maxrange // u4: maximum:range of dering in LR resolution, max to 12; default = 9 +//Bit 19:18 reserved +//Bit 17:16 reg_sr3_dering_lcvar_blend_mode // u2: mode for lcvar calculation: 0: HVblend; 1: diagblend; 2: HVblend+V (for hring); 3: HVblend+ DiagBlend default = 2 +//Bit 15:8 reg_sr3_dering_lcvar_gain // u8: gain to local variant and normalized to 32 as "1" default = 64 +//Bit 7:0 reg_sr3_dering_lcvar_nearby_maxsad_th // u8: threshold to use nearer side maxsad if that side sad is larger than this threshold, ortherwise, use the max one default = 28 +#define SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ((0x506c << 2) + 0xff000000) +//Bit 31:24 reg_sr3_dering_luma2pkgain3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkgain based on LPF luma level. default=255 +//Bit 23:16 reg_sr3_dering_luma2pkgain2 // u8: level limit(for bpcon<th0) of curve for dering pkgain based on LPF luma level. default=255 +//Bit 15:8 reg_sr3_dering_luma2pkgain1 // u8: threshold1 of curve for dering pkgain based on LPF luma level default =200 +//Bit 7:0 reg_sr3_dering_luma2pkgain0 // u8: threshold0 of curve for dering pkgain based on LPF luma level. default =30 +#define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ((0x506d << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_sr3_dering_luma2pkgain6 // u8: rate1 (for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =24 +//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. dfault =50 +//Bit 7:0 reg_sr3_dering_luma2pkgain4 // u8: level limit(for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =255 +#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 ((0x506e << 2) + 0xff000000) +//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkOS based on LPF luma level. default=255 +//Bit 23:16 reg_sr3_dering_luma2pkos2 // u8: level limit(for bpcon<th0) of curve for dering pkOS based on LPF luma level. default=255 +//Bit 15:8 reg_sr3_dering_luma2pkos1 // u8: threshold1 of curve for dering pkOS based on LPF luma level default =200 +//Bit 7:0 reg_sr3_dering_luma2pkos0 // u8: threshold0 of curve for dering pkOS based on LPF luma leve. default =30 +#define SHARP_SR3_DERING_LUMA2PKOS_4TO6 ((0x506f << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_sr3_dering_luma2pkos6 // u8: rate1 (for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =24 +//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. dfault =50 +//Bit 7:0 reg_sr3_dering_luma2pkos4 // u8: level limit(for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =255 +#define SHARP_SR3_DERING_GAINVS_MADSAD ((0x5070 << 2) + 0xff000000) +//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0 +//Bit 27:24 reg_sr3_dering_gainvs_maxsad6 //u4: default = 0 +//Bit 23:20 reg_sr3_dering_gainvs_maxsad5 //u4: default = 0 +//Bit 19:16 reg_sr3_dering_gainvs_maxsad4 //u4: default = 0 +//Bit 15:12 reg_sr3_dering_gainvs_maxsad3 //u4: default = 0 +//Bit 11:8 reg_sr3_dering_gainvs_maxsad2 //u4: default = 0 +//Bit 7:4 reg_sr3_dering_gainvs_maxsad1 //u4: default = 4 +//Bit 3:0 reg_sr3_dering_gainvs_maxsad0 //u4: default = 8 +#define SHARP_SR3_DERING_GAINVS_VR2MAX ((0x5071 << 2) + 0xff000000) +//Bit 31:28 reg_sr3_dering_gainvs_vr2max7 //u4: pkgain vs ratio = max(local_var, floor)/maxsad nearby, default = 15 +//Bit 27:24 reg_sr3_dering_gainvs_vr2max6 //u4: default = 15 +//Bit 23:20 reg_sr3_dering_gainvs_vr2max5 //u4: default = 15 +//Bit 19:16 reg_sr3_dering_gainvs_vr2max4 //u4: default = 15 +//Bit 15:12 reg_sr3_dering_gainvs_vr2max3 //u4: default = 14 +//Bit 11:8 reg_sr3_dering_gainvs_vr2max2 //u4: default = 12 +//Bit 7:4 reg_sr3_dering_gainvs_vr2max1 //u4: default = 2 +//Bit 3:0 reg_sr3_dering_gainvs_vr2max0 //u4: default = 0 +#define SHARP_SR3_DERING_PARAM0 ((0x5072 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:16 reg_sr3_dering_lcvar_floor //u8: local varianet no smaller than this value to calculate dgain max(localvar,x)/maxsad. default = 10 +//Bit 15:8 reg_sr3_dering_vr2max_gain //u8: gain to max(local_var, floor)/maxsad before feeding to LUT. default = 32 +//Bit 7:6 reserved +//Bit 5:0 reg_sr3_dering_vr2max_limt //u6: limit of maxsad to max(local_var, floor)*(max(maxsad, lmit))/maxsad. default = 16 +#define SHARP_SR3_DRTLPF_THETA ((0x5073 << 2) + 0xff000000) +//Bit 31:0 reg_sr3_drtlpf_theta //u4x8: directional lpf beta coef for min_sad/min2_sad compared to x=0:7 correspond to[1:8]/16; 0 means no drtLPF, 15: 100% alpha dependant drtLPF +#define SHARP_SATPRT_CTRL ((0x5074 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:16 reg_satprt_sat_core //u8: 4x will be coring to cor(irgb_max-irgb_min) to calculate the oy_delt, the smaller the more protection to color, the larger only the rich color will be protected; +//Bit 15:8 reg_satprt_sat_rate //u8: rate to cor(irgb_max-irgb_min) to calculate the oy_delt, the larger the more protection to rich color; norm 16 as 1 +//Bit 7:4 reserved +//Bit 3:2 reg_satprt_csc_mode //u2: csc mode of current yuv input: 0:601, 1:709, 2:BT2020 NCL, 3:reserved +//Bit 1 reg_satprt_is_lmt //u1: flag telling the YUV is limited range data or full range data, 0 full range, 1: limited range +//Bit 0 reg_satprt_enable //u1: enable of saturation protection for dnlp adjustments +#define SHARP_SATPRT_DIVM ((0x5075 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:0 reg_satprt_div_m //u8x3, 1/m, normalized to 128 as 1, default=1 +#define SHARP_DB_FLT_CTRL ((0x5077 << 2) + 0xff000000) +//Bit 31:27 reserved +//Bit 26 reg_nrdeband_reset1 +//Bit 25 reg_nrdeband_reset0 +//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0:yuv 1:RGB +//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below +//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below +//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y; +//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m]) +//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6 +//Bit 16 reserved +//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6 +//Bit 12 reserved +//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6 +//Bit 8 reserved +//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma +//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma +//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma +//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma +//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7 +#define SHARP_DB_FLT_RANDLUT ((0x5079 << 2) + 0xff000000) +//Bit 31:24 reserved +//Bit 23:21 reg_nrdebandslut7 // unsigned , default = 1 lut0 +//Bit 20:18 reg_nrdebandslut6 // unsigned , default = 1 lut0 +//Bit 17:15 reg_nrdebandslut5 // unsigned , default = 1 lut0 +//Bit 14:12 reg_nrdebandslut4 // unsigned , default = 1 lut0 +//Bit 11: 9 reg_nrdebandslut3 // unsigned , default = 1 lut0 +//Bit 8: 6 reg_nrdebandslut2 // unsigned , default = 1 lut0 +//Bit 5: 3 reg_nrdebandslut1 // unsigned , default = 1 lut0 +//Bit 2: 0 reg_nrdebandslut0 // unsigned , default = 1 lut0 +#define SHARP_DB_FLT_PXI_THRD ((0x507a << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 to luma/|u/v| for using the denoise +//Bit 15:10 reserved +//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 to luma/|u/v| for using the denoise +#define SHARP_DB_FLT_SEED_Y ((0x507b << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 noise adding seed for Y. seed[0]= 0x60a52f20; as default +#define SHARP_DB_FLT_SEED_U ((0x507c << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 noise adding seed for U. seed[0]= 0x60a52f27; as default +#define SHARP_DB_FLT_SEED_V ((0x507d << 2) + 0xff000000) +//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default +#define SHARP_PKGAIN_VSLUMA_LUT_L ((0x507e << 2) + 0xff000000) +//Bit 31:28 reg_pkgain_vsluma_lut7; +//Bit 27:24 reg_pkgain_vsluma_lut6; +//Bit 23:20 reg_pkgain_vsluma_lut5; +//Bit 19:16 reg_pkgain_vsluma_lut4; +//Bit 15:12 reg_pkgain_vsluma_lut3; +//Bit 11: 8 reg_pkgain_vsluma_lut2; +//Bit 7: 4 reg_pkgain_vsluma_lut1; +//Bit 3: 0 reg_pkgain_vsluma_lut0; +#define SHARP_PKGAIN_VSLUMA_LUT_H ((0x507f << 2) + 0xff000000) +//Bit 31: 4 reserved; +//Bit 3: 0 reg_pkgain_vsluma_lut8; +#define SHARP_PKOSHT_VSLUMA_LUT_L ((0x5080 << 2) + 0xff000000) +//Bit 31:28 reg_pkosht_vsluma_lut7; +//Bit 27:24 reg_pkosht_vsluma_lut6; +//Bit 23:20 reg_pkosht_vsluma_lut5; +//Bit 19:16 reg_pkosht_vsluma_lut4; +//Bit 15:12 reg_pkosht_vsluma_lut3; +//Bit 11: 8 reg_pkosht_vsluma_lut2; +//Bit 7: 4 reg_pkosht_vsluma_lut1; +//Bit 3: 0 reg_pkosht_vsluma_lut0; +#define SHARP_PKOSHT_VSLUMA_LUT_H ((0x5081 << 2) + 0xff000000) +//Bit 31: 4 reserved; +//Bit 3: 0 reg_pkosht_vsluma_lut8; +#define SHARP_SATPRT_LMT_RGB1 ((0x5082 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27:16 reg_satprt_lmt_g //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023 +//Bit 15:12 reserved +//Bit 11:0 reg_satprt_lmt_r //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023 +#define SHARP_SATPRT_LMT_RGB2 ((0x5083 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11:0 reg_satprt_lmt_b //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023 +#define SHARP_GATE_CLK_CTRL_0 ((0x5084 << 2) + 0xff000000) +//Bit 31: 0 reg_gate_clk_ctrl_0 +#define SHARP_GATE_CLK_CTRL_1 ((0x5085 << 2) + 0xff000000) +//Bit 31: 0 reg_gate_clk_ctrl_1 +#define SHARP_GATE_CLK_CTRL_2 ((0x5086 << 2) + 0xff000000) +//Bit 31: 0 reg_gate_clk_ctrl_2 +#define SHARP_GATE_CLK_CTRL_3 ((0x5087 << 2) + 0xff000000) +//Bit 31: 0 reg_gate_clk_ctrl_3 +#define SHARP_DPS_CTRL ((0x5088 << 2) + 0xff000000) +//Bit 31: 0 reg_sharp_dps_ctrl +#define DNLP_00 ((0x5090 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid0 : dnlp00 . unsigned , default = 32'h00008060 +#define DNLP_01 ((0x5091 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid1 : dnlp01 . unsigned , default = 32'h100e0c0a +#define DNLP_02 ((0x5092 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid2 : dnlp02 . unsigned , default = 32'h1a171412 +#define DNLP_03 ((0x5093 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid3 : dnlp03 . unsigned , default = 32'h2824201d +#define DNLP_04 ((0x5094 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid4 : dnlp04 . unsigned , default = 32'h3834302c +#define DNLP_05 ((0x5095 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid5 : dnlp05 . unsigned , default = 32'h4b45403c +#define DNLP_06 ((0x5096 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid6 : dnlp06 . unsigned , default = 32'h605b5550 +#define DNLP_07 ((0x5097 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid7 : dnlp07 . unsigned , default = 32'h80787068 +#define DNLP_08 ((0x5098 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid8 : dnlp08 . unsigned , default = 32'ha0989088 +#define DNLP_09 ((0x5099 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid9 : dnlp09 . unsigned , default = 32'hb8b2aca6 +#define DNLP_10 ((0x509a << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid10 : dnlp10 . unsigned , default = 32'hc8c4c0bc +#define DNLP_11 ((0x509b << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid11 : dnlp11 . unsigned , default = 32'hd4d2cecb +#define DNLP_12 ((0x509c << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid12 : dnlp12 . unsigned , default = 32'hdad8d7d6 +#define DNLP_13 ((0x509d << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid13 : dnlp13 . unsigned , default = 32'he2e0dedc +#define DNLP_14 ((0x509e << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid14 : dnlp14 . unsigned , default = 32'hf0ece8e4 +#define DNLP_15 ((0x509f << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid15 : dnlp15 . unsigned , default = 32'hfffcf8f4 +#define DNLP_16 ((0x50a0 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid16 : dnlp16 . unsigned , default = 32'h08060402 +#define DNLP_17 ((0x50a1 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid17 : dnlp17 . unsigned , default = 32'h100e0c0a +#define DNLP_18 ((0x50a2 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid18 : dnlp18 . unsigned , default = 32'h1a171412 +#define DNLP_19 ((0x50a3 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid19 : dnlp19 . unsigned , default = 32'h2824201d +#define DNLP_20 ((0x50a4 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid20 : dnlp20 . unsigned , default = 32'h3834302c +#define DNLP_21 ((0x50a5 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid21 : dnlp21 . unsigned , default = 32'h4b45403c +#define DNLP_22 ((0x50a6 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid22 : dnlp22 . unsigned , default = 32'h605b5550 +#define DNLP_23 ((0x50a7 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid23 : dnlp23 . unsigned , default = 32'h80787068 +#define DNLP_24 ((0x50a8 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid24 : dnlp24 . unsigned , default = 32'ha0989088 +#define DNLP_25 ((0x50a9 << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid25 : dnlp25 . unsigned , default = 32'hb8b2aca6 +#define DNLP_26 ((0x50aa << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid26 : dnlp26 . unsigned , default = 32'hc8c4c0bc +#define DNLP_27 ((0x50ab << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid27 : dnlp27 . unsigned , default = 32'hd4d2cecb +#define DNLP_28 ((0x50ac << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid28 : dnlp28 . unsigned , default = 32'hdad8d7d6 +#define DNLP_29 ((0x50ad << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid29 : dnlp29 . unsigned , default = 32'he2e0dedc +#define DNLP_30 ((0x50ae << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid30 : dnlp30 . unsigned , default = 32'hf0ece8e4 +#define DNLP_31 ((0x50af << 2) + 0xff000000) +//Bit 31: 0, reg_dnlp_ygrid31 : dnlp31 . unsigned , default = 32'hfffcf8f4 +#define SHARP_SYNC_CTRL ((0x50b0 << 2) + 0xff000000) +//Bit 15: 0, reg_sync_ctrl //reg_sync_ctrl: shaddow register control . unsigned , default = 0 +#define LC_INPUT_MUX ((0x50b1 << 2) + 0xff000000) +//Bit 31:7 reserved +//Bit 6:4 reg_lcinput_ysel //u3, local contrast luma input options 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os) . unsigned , default = 5 +//Bit 3 reserved +//Bit 2:0 reg_lcinput_csel //u3, local contrast chroma input options 0: org_c; 1: gau_c; 2: gauadp_c; 3: edgadplpf_c; 4: nr_c;5: cti_c; 6: pk_c . unsigned , default = 5 +#define NR_GAU_YH_COEF02 ((0x50b2 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:20 reg_nr_gau_yhcoef_0 //s10, luma's horizontal adaptive coef0 . signed , default = 32 +//Bit 19:10 reg_nr_gau_yhcoef_1 //s10, luma's horizontal adaptive coef1 . signed , default = 32 +//Bit 9: 0 reg_nr_gau_yhcoef_2 //s10, luma's horizontal adaptive coef2 . signed , default = 16 +#define NR_GAU_YH_COEF34 ((0x50b3 << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19:10 reg_nr_gau_yhcoef_3 //s10, luma's horizontal adaptive coef3 . signed , default = 0 +//Bit 9: 0 reg_nr_gau_yhcoef_4 //s10, luma's horizontal adaptive coef4 . signed , default = 0 +#define NR_GAU_YV_COEF1 ((0x50b4 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:20 reg_nr_gau_yvcoef_0 //s10, luma's vertical adaptive coef0 . signed , default = 32 +//Bit 19:10 reg_nr_gau_yvcoef_1 //s10, luma's vertical adaptive coef1 . signed , default = 32 +//Bit 9: 0 reg_nr_gau_yvcoef_2 //s10, luma's vertical adaptive coef2 . signed , default = 16 +#define NR_GAU_CH_COEF02 ((0x50b5 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:20 reg_nr_gau_chcoef_0 //s10, chroma's horizontal adaptive coef0 . signed , default = 32 +//Bit 19:10 reg_nr_gau_chcoef_1 //s10, chroma's horizontal adaptive coef1 . signed , default = 32 +//Bit 9: 0 reg_nr_gau_chcoef_2 //s10, chroma's horizontal adaptive coef2 . signed , default = 16 +#define NR_GAU_CH_COEF34 ((0x50b6 << 2) + 0xff000000) +//Bit 31:20 reserved +//Bit 19:10 reg_nr_gau_chcoef_3 //s10, chroma's horizontal adaptive coef3 . signed , default = 0 +//Bit 9: 0 reg_nr_gau_chcoef_4 //s10, chroma's horizontal adaptive coef4 . signed , default = 0 +#define NR_GAU_CV_COEF1 ((0x50b7 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:20 reg_nr_gau_cvcoef_0 //s10, chroma's vertical adaptive coef0 . signed , default = 32 +//Bit 19:10 reg_nr_gau_cvcoef_1 //s10, chroma's vertical adaptive coef1 . signed , default = 32 +//Bit 9: 0 reg_nr_gau_cvcoef_2 //s10, chroma's vertical adaptive coef2 . signed , default = 16 +#define SHARP_DB_FLT_CTRL1 ((0x50b8 << 2) + 0xff000000) +//Bit 31:18 reserved +//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2 +//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8 +//Bit 11 reserved +//Bit 10: 8 reserved +//Bit 7 reserved +//Bit 6: 4 reserved +//Bit 3 reserved +//Bit 2: 0 reserved +#define SHARP_DB_FLT_LUMA_THRD ((0x50b9 << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 23:22 reserved +//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4 +//Bit 15:14 reserved +//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else +#define SHARP_DB_FLT_CHRM_THRD ((0x50ba << 2) + 0xff000000) +//Bit 31:30 reserved +//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf +//Bit 23:22 reserved +//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4 +//Bit 15:14 reserved +//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2 +//Bit 7: 6 reserved +//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif +#define LC_TOP_CTRL ((0x50c0 << 2) + 0xff000000) + //Bit 31 :8 reg_lc_misc U RW default = 'h0 + //Bit 7 :5 reserved U RW default = 'h0 None + //Bit 4 reg_lc_enable U RW default = 'h1 enable signal for local contrast enhancement, 1-enable; 0 disable + //Bit 3 :1 reserved U RW default = 'h0 None + //Bit 0 reg_lc_blkblend_mode U RW default = 'h1 use bilinear interpolation between blocks, 0: no interpolation 1: blender enabled +#define LC_HV_NUM ((0x50c1 << 2) + 0xff000000) + //Bit 31 :13 reserved U RW default = 'h0 None + //Bit 12 :8 reg_lc_blk_hnum U RW default = 'hc lc processing region number of V, maximum to (STA_LEN_V-1) (0~8) + //Bit 7 :5 reserved U RW default = 'h0 None + //Bit 4 :0 reg_lc_blk_vnum U RW default = 'h8 lc processing region number of H, maximum to (STA_LEN_H-1) (0~12) +#define LC_SAT_LUT_0_1 ((0x50c2 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_0 U RW default = 'hc saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_1 U RW default = 'h20 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_2_3 ((0x50c3 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_2 U RW default = 'h38 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_3 U RW default = 'h54 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_4_5 ((0x50c4 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_4 U RW default = 'h73 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_5 U RW default = 'h95 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_6_7 ((0x50c5 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_6 U RW default = 'hb9 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_7 U RW default = 'hdf saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_8_9 ((0x50c6 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_8 U RW default = 'h107 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_9 U RW default = 'h131 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_10_11 ((0x50c7 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_10 U RW default = 'h15c saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_11 U RW default = 'h189 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_12_13 ((0x50c8 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_12 U RW default = 'h1b8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_13 U RW default = 'h1e8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_14_15 ((0x50c9 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_14 U RW default = 'h219 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_15 U RW default = 'h24c saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_16_17 ((0x50ca << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_16 U RW default = 'h280 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_17 U RW default = 'h2b6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_18_19 ((0x50cb << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_18 U RW default = 'h2ec saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_19 U RW default = 'h324 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_20_21 ((0x50cc << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_20 U RW default = 'h35d saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_21 U RW default = 'h397 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_22_23 ((0x50cd << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_22 U RW default = 'h3d2 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_23 U RW default = 'h40e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_24_25 ((0x50ce << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_24 U RW default = 'h44b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_25 U RW default = 'h489 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_26_27 ((0x50cf << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_26 U RW default = 'h4c8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_27 U RW default = 'h507 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_28_29 ((0x50d0 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_28 U RW default = 'h548 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_29 U RW default = 'h58a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_30_31 ((0x50d1 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_30 U RW default = 'h5cd saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_31 U RW default = 'h610 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_32_33 ((0x50d2 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_32 U RW default = 'h654 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_33 U RW default = 'h69a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_34_35 ((0x50d3 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_34 U RW default = 'h6e0 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_35 U RW default = 'h726 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_36_37 ((0x50d4 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_36 U RW default = 'h76e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_37 U RW default = 'h7b6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_38_39 ((0x50d5 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_38 U RW default = 'h7ff saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_39 U RW default = 'h849 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_40_41 ((0x50d6 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_40 U RW default = 'h894 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_41 U RW default = 'h8df saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_42_43 ((0x50d7 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_42 U RW default = 'h92b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_43 U RW default = 'h978 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_44_45 ((0x50d8 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_44 U RW default = 'h9c6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_45 U RW default = 'ha14 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_46_47 ((0x50d9 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_46 U RW default = 'ha63 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_47 U RW default = 'hab2 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_48_49 ((0x50da << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_48 U RW default = 'hb02 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_49 U RW default = 'hb53 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_50_51 ((0x50db << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_50 U RW default = 'hba5 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_51 U RW default = 'hbf7 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_52_53 ((0x50dc << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_52 U RW default = 'hc4a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_53 U RW default = 'hc9d saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_54_55 ((0x50dd << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_54 U RW default = 'hcf1 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_55 U RW default = 'hd46 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_56_57 ((0x50de << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_56 U RW default = 'hd9b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_57 U RW default = 'hdf1 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_58_59 ((0x50df << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_58 U RW default = 'he47 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_59 U RW default = 'he9e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_60_61 ((0x50e0 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_satur_lut_60 U RW default = 'hef6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_61 U RW default = 'hf4e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_SAT_LUT_62 ((0x50e1 << 2) + 0xff000000) + //Bit 31 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_satur_lut_62 U RW default = 'hfa7 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2 +#define LC_CURVE_BLK_HIDX_0_1 ((0x50e2 << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_hidx_0 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_hidx_1 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_HIDX_2_3 ((0x50e3 << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_hidx_2 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_hidx_3 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_HIDX_4_5 ((0x50e4 << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_hidx_4 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_hidx_5 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_HIDX_6_7 ((0x50e5 << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_hidx_6 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_hidx_7 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_HIDX_8_9 ((0x50e6 << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_hidx_8 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_hidx_9 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_HIDX_10_11 ((0x50e7 << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_hidx_10 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_hidx_11 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_HIDX_12 ((0x50e8 << 2) + 0xff000000) + //Bit 31 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_hidx_12 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_VIDX_0_1 ((0x50e9 << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_vidx_0 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_vidx_1 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_VIDX_2_3 ((0x50ea << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_vidx_2 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_vidx_3 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_VIDX_4_5 ((0x50eb << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_vidx_4 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_vidx_5 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_VIDX_6_7 ((0x50ec << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :16 reg_lc_blk_vidx_6 U RW default = 'h0 block boundary x-index + //Bit 15 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_vidx_7 U RW default = 'h0 block boundary x-index +#define LC_CURVE_BLK_VIDX_8 ((0x50ed << 2) + 0xff000000) + //Bit 31 :14 reserved U RW default = 'h0 None + //Bit 13 :0 reg_lc_blk_vidx_8 U RW default = 'h0 block boundary x-index +#define LC_YUV2RGB_MAT_0_1 ((0x50ee << 2) + 0xff000000) + //Bit 31 :29 reserved U RW default = 'h0 None + //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_0 S RW default = 1192 yuv2rgb 3x3 matrix + //Bit 15 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_1 S RW default = 'h0 yuv2rgb 3x3 matrix +#define LC_YUV2RGB_MAT_2_3 ((0x50ef << 2) + 0xff000000) + //Bit 31 :29 reserved U RW default = 'h0 None + //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_2 S RW default = 1836 yuv2rgb 3x3 matrix + //Bit 15 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_3 S RW default = 1192 yuv2rgb 3x3 matrix +#define LC_YUV2RGB_MAT_4_5 ((0x50f0 << 2) + 0xff000000) + //Bit 31 :29 reserved U RW default = 'h0 None + //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_4 S RW default = -218 yuv2rgb 3x3 matrix + //Bit 15 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_5 S RW default = -547 yuv2rgb 3x3 matrix +#define LC_YUV2RGB_MAT_6_7 ((0x50f1 << 2) + 0xff000000) + //Bit 31 :29 reserved U RW default = 'h0 None + //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_6 S RW default = 1192 yuv2rgb 3x3 matrix + //Bit 15 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_7 S RW default = '2166 yuv2rgb 3x3 matrix +#define LC_YUV2RGB_MAT_8 ((0x50f2 << 2) + 0xff000000) + //Bit 31 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_8 S RW default = 'h0 yuv2rgb 3x3 matrix +#define LC_RGB2YUV_MAT_0_1 ((0x50f3 << 2) + 0xff000000) + //Bit 31 :29 reserved U RW default = 'h0 None + //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_0 S RW default = 187 rgb2yuv 3x3 matrix + //Bit 15 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_1 S RW default = 629 rgb2yuv 3x3 matrix +#define LC_RGB2YUV_MAT_2_3 ((0x50f4 << 2) + 0xff000000) + //Bit 31 :29 reserved U RW default = 'h0 None + //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_2 S RW default = 63 rgb2yuv 3x3 matrix + //Bit 15 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_3 S RW default = -103 rgb2yuv 3x3 matrix +#define LC_RGB2YUV_MAT_4_5 ((0x50f5 << 2) + 0xff000000) + //Bit 31 :29 reserved U RW default = 'h0 None + //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_4 S RW default = -346 rgb2yuv 3x3 matrix + //Bit 15 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_5 S RW default = 450 rgb2yuv 3x3 matrix +#define LC_RGB2YUV_MAT_6_7 ((0x50f6 << 2) + 0xff000000) + //Bit 31 :29 reserved U RW default = 'h0 None + //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_6 S RW default = 450 rgb2yuv 3x3 matrix + //Bit 15 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_7 S RW default = -409 rgb2yuv 3x3 matrix +#define LC_RGB2YUV_MAT_8 ((0x50f7 << 2) + 0xff000000) + //Bit 31 :13 reserved U RW default = 'h0 None + //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_8 S RW default = 41 rgb2yuv 3x3 matrix +#define LC_YUV2RGB_OFST ((0x50f8 << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_yuv2rgb_ofset_0 U RW default = 'h40 yuv2rgb pre-offset to yuv, + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_yuv2rgb_ofset_1 U RW default = 'h200 yuv2rgb pre-offset to yuv, +#define LC_YUV2RGB_CLIP ((0x50f9 << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :28 reg_lc_yuv2rgb_rs U RW default = 'h0 matrix normalization right shift extra bits, norm= (1<<(8+rs)) + //Bit 27 :16 reg_lc_yuv2rgb_clip_0 U RW default = 'h0 yuv2rgb converted RGB clipping range + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_yuv2rgb_clip_1 U RW default = 'h3ff yuv2rgb converted RGB clipping range +#define LC_RGB2YUV_OFST ((0x50fa << 2) + 0xff000000) + //Bit 31 :28 reserved U RW default = 'h0 None + //Bit 27 :16 reg_lc_rgb2yuv_ofset_0 U RW default = 'h40 rgb2yuv post-offset to yuv, + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_rgb2yuv_ofset_1 U RW default = 'h200 rgb2yuv post-offset to yuv, +#define LC_RGB2YUV_CLIP ((0x50fb << 2) + 0xff000000) + //Bit 31 :30 reserved U RW default = 'h0 None + //Bit 29 :28 reg_lc_rgb2yuv_rs U RW default = 'h0 matrix normalization right shift extra bits, norm= (1<<(10+rs)) + //Bit 27 :16 reg_lc_rgb2yuv_clip_0 U RW default = 'h0 rgb2yuv converted YUV clipping range + //Bit 15 :12 reserved U RW default = 'h0 None + //Bit 11 :0 reg_lc_rgb2yuv_clip_1 U RW default = 'h3ff rgb2yuv converted YUV clipping range +#define LC_MAP_RAM_CTRL ((0x50fc << 2) + 0xff000000) +#define LC_MAP_RAM_ADDR ((0x50fd << 2) + 0xff000000) +#define LC_MAP_RAM_DATA ((0x50fe << 2) + 0xff000000) +#define SHARP_FMETER_CTRL ((0x5089 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0 +//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0 +//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0 +//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0 +//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0 +//Bit 3: 1 reserved +//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0 +#define SHARP_FMETER_WIN_HOR ((0x508a << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_fmeter_xwin_ed //u13, window location: hend .unsigned , default = 1920 +//Bit 15:13 reserved +//Bit 12: 0 reg_fmeter_xwin_st //u13, window location: hstart .unsigned , default = 0 +#define SHARP_FMETER_WIN_VER ((0x508b << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_fmeter_ywin_ed //u14, window location: vend .unsigned , default = 1080 +//Bit 15:13 reserved +//Bit 12: 0 reg_fmeter_ywin_st //u14, window location: vstart .unsigned , default = 0 +#define SHARP_FMETER_CORING ((0x508c << 2) + 0xff000000) +//Bit 31:24 reg_fmeter_low_bound //u8, low bound for threshold .unsigned , default = 4 +//Bit 23:16 reg_fmeter_coring_d //u8, coring of diff before compare with threhold for diagonal frequency .unsigned , default = 4 +//Bit 15:8 reg_fmeter_coring_v //u8, coring of diff before compare with threhold for vertical frequency .unsigned , default = 4 +//Bit 7: 0 reg_fmeter_coring_h //u8, coring of diff before compare with threhold for horizontal frequency .unsigned , default = 4 +#define SHARP_FMETER_RATIO_H ((0x508d << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:16 reg_fmeter_ratio_h2 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16 +//Bit 15:14 reserved +//Bit 13: 8 reg_fmeter_ratio_h1 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16 +//Bit 7 : 6 reserved +//Bit 5 : 0 reg_fmeter_ratio_h0 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16 +#define SHARP_FMETER_RATIO_V ((0x508e << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:16 reg_fmeter_ratio_v2 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16 +//Bit 15:14 reserved +//Bit 13: 8 reg_fmeter_ratio_v1 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16 +//Bit 7 : 6 reserved +//Bit 5 : 0 reg_fmeter_ratio_v0 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16 +#define SHARP_FMETER_RATIO_D ((0x508f << 2) + 0xff000000) +//Bit 31:22 reserved +//Bit 21:16 reg_fmeter_ratio_d2 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16 +//Bit 15:14 reserved +//Bit 13: 8 reg_fmeter_ratio_d1 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16 +//Bit 7 : 6 reserved +//Bit 5 : 0 reg_fmeter_ratio_d0 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16 +#define SHARP_RO_FMETER_HCNT_TYPE0 ((0x5046 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_hcnt_type0 //u32, count for horizontal frequency +#define SHARP_RO_FMETER_HCNT_TYPE1 ((0x5047 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_hcnt_type1 //u32, count for horizontal frequency +#define SHARP_RO_FMETER_HCNT_TYPE2 ((0x5048 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_hcnt_type2 //u32, count for horizontal frequency +#define SHARP_RO_FMETER_HCNT_TYPE3 ((0x5049 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_hcnt_type3 //u32, count for horizontal frequency +#define SHARP_RO_FMETER_VCNT_TYPE0 ((0x504a << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_vcnt_type0 //u32, count for vertical frequency +#define SHARP_RO_FMETER_VCNT_TYPE1 ((0x504b << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_vcnt_type1 //u32, count for vertical frequency +#define SHARP_RO_FMETER_VCNT_TYPE2 ((0x504c << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_vcnt_type2 //u32, count for vertical frequency +#define SHARP_RO_FMETER_VCNT_TYPE3 ((0x504d << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_vcnt_type3 //u32, count for vertical frequency +#define SHARP_RO_FMETER_PDCNT_TYPE0 ((0x504e << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_pdcnt_type0 //u32, count for positive diagonal frequency +#define SHARP_RO_FMETER_PDCNT_TYPE1 ((0x504f << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_pdcnt_type1 //u32, count for positive diagonal frequency +#define SHARP_RO_FMETER_PDCNT_TYPE2 ((0x5050 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_pdcnt_type2 //u32, count for positive diagonal frequency +#define SHARP_RO_FMETER_PDCNT_TYPE3 ((0x5051 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_pdcnt_type3 //u32, count for positive diagonal frequency +#define SHARP_RO_FMETER_NDCNT_TYPE0 ((0x5052 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_ndcnt_type0 //u32, count for negitive diagonal frequency +#define SHARP_RO_FMETER_NDCNT_TYPE1 ((0x5053 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_ndcnt_type1 //u32, count for negitive diagonal frequency +#define SHARP_RO_FMETER_NDCNT_TYPE2 ((0x5054 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_ndcnt_type2 //u32, count for negitive diagonal frequency +#define SHARP_RO_FMETER_NDCNT_TYPE3 ((0x5055 << 2) + 0xff000000) +//Bit 31:0 ro_fmeter_ndcnt_type3 //u32, count for negitive diagonal frequency +// +// Closing file: sharp_regs.h +// + +#define SRSHARP0_SHARP_HVSIZE (SRSHARP0_OFFSET + SHARP_HVSIZE ) //0x00 // +#define SRSHARP0_SHARP_HVBLANK_NUM (SRSHARP0_OFFSET + SHARP_HVBLANK_NUM ) //0x01 // +#define SRSHARP0_NR_GAUSSIAN_MODE (SRSHARP0_OFFSET + NR_GAUSSIAN_MODE ) //0x02 // +//`define SRSHARP0_PK_HVCON_LPF_MODE (`SRSHARP0_OFFSET + `PK_HVCON_LPF_MODE ) //8'h03 // +//`define SRSHARP0_PK_CON_BLEND_GAIN (`SRSHARP0_OFFSET + `PK_CON_BLEND_GAIN ) //8'h04 // +#define SRSHARP0_PK_CON_2CIRHPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2CIRHPGAIN_TH_RATE ) //0x05 // +#define SRSHARP0_PK_CON_2CIRHPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2CIRHPGAIN_LIMIT ) //0x06 // +#define SRSHARP0_PK_CON_2CIRBPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2CIRBPGAIN_TH_RATE ) //0x07 // +#define SRSHARP0_PK_CON_2CIRBPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2CIRBPGAIN_LIMIT ) //0x08 // +#define SRSHARP0_PK_CON_2DRTHPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2DRTHPGAIN_TH_RATE ) //0x09 // +#define SRSHARP0_PK_CON_2DRTHPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2DRTHPGAIN_LIMIT ) //0x0a // +#define SRSHARP0_PK_CON_2DRTBPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2DRTBPGAIN_TH_RATE ) //0x0b // +#define SRSHARP0_PK_CON_2DRTBPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2DRTBPGAIN_LIMIT ) //0x0c // +#define SRSHARP0_PK_CIRFB_LPF_MODE (SRSHARP0_OFFSET + PK_CIRFB_LPF_MODE ) //0x0d // +#define SRSHARP0_PK_DRTFB_LPF_MODE (SRSHARP0_OFFSET + PK_DRTFB_LPF_MODE ) //0x0e // +#define SRSHARP0_PK_CIRFB_HP_CORING (SRSHARP0_OFFSET + PK_CIRFB_HP_CORING ) //0x0f // +#define SRSHARP0_PK_CIRFB_BP_CORING (SRSHARP0_OFFSET + PK_CIRFB_BP_CORING ) //0x10 // +#define SRSHARP0_PK_DRTFB_HP_CORING (SRSHARP0_OFFSET + PK_DRTFB_HP_CORING ) //0x11 // +#define SRSHARP0_PK_DRTFB_BP_CORING (SRSHARP0_OFFSET + PK_DRTFB_BP_CORING ) //0x12 // +#define SRSHARP0_PK_CIRFB_BLEND_GAIN (SRSHARP0_OFFSET + PK_CIRFB_BLEND_GAIN ) //0x13 // +#define SRSHARP0_NR_ALPY_SSD_GAIN_OFST (SRSHARP0_OFFSET + NR_ALPY_SSD_GAIN_OFST ) //0x14 // +#define SRSHARP0_NR_ALP0Y_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP0Y_ERR2CURV_TH_RATE ) //0x15 // +#define SRSHARP0_NR_ALP0Y_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP0Y_ERR2CURV_LIMIT ) //0x16 // +#define SRSHARP0_NR_ALP0C_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP0C_ERR2CURV_TH_RATE ) //0x17 // +#define SRSHARP0_NR_ALP0C_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP0C_ERR2CURV_LIMIT ) //0x18 // +#define SRSHARP0_NR_ALP0_MIN_MAX (SRSHARP0_OFFSET + NR_ALP0_MIN_MAX ) //0x19 // +#define SRSHARP0_NR_ALP1_MIERR_CORING (SRSHARP0_OFFSET + NR_ALP1_MIERR_CORING ) //0x1a // +#define SRSHARP0_NR_ALP1_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP1_ERR2CURV_TH_RATE ) //0x1b // +#define SRSHARP0_NR_ALP1_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP1_ERR2CURV_LIMIT ) //0x1c // +#define SRSHARP0_NR_ALP1_MIN_MAX (SRSHARP0_OFFSET + NR_ALP1_MIN_MAX ) //0x1d // +#define SRSHARP0_PK_ALP2_MIERR_CORING (SRSHARP0_OFFSET + PK_ALP2_MIERR_CORING ) //0x1e // +#define SRSHARP0_PK_ALP2_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + PK_ALP2_ERR2CURV_TH_RATE ) //0x1f // +#define SRSHARP0_PK_ALP2_ERR2CURV_LIMIT (SRSHARP0_OFFSET + PK_ALP2_ERR2CURV_LIMIT ) //0x20 // +#define SRSHARP0_PK_ALP2_MIN_MAX (SRSHARP0_OFFSET + PK_ALP2_MIN_MAX ) //0x21 // +#define SRSHARP0_PK_FINALGAIN_HP_BP (SRSHARP0_OFFSET + PK_FINALGAIN_HP_BP ) //0x22 // +#define SRSHARP0_PK_OS_HORZ_CORE_GAIN (SRSHARP0_OFFSET + PK_OS_HORZ_CORE_GAIN ) //0x23 // +#define SRSHARP0_PK_OS_VERT_CORE_GAIN (SRSHARP0_OFFSET + PK_OS_VERT_CORE_GAIN ) //0x24 // +#define SRSHARP0_PK_OS_ADPT_MISC (SRSHARP0_OFFSET + PK_OS_ADPT_MISC ) //0x25 // +#define SRSHARP0_PK_OS_STATIC (SRSHARP0_OFFSET + PK_OS_STATIC ) //0x26 // +#define SRSHARP0_PK_NR_ENABLE (SRSHARP0_OFFSET + PK_NR_ENABLE ) //0x27 // +#define SRSHARP0_PK_DRT_SAD_MISC (SRSHARP0_OFFSET + PK_DRT_SAD_MISC ) //0x28 // +#define SRSHARP0_NR_TI_DNLP_BLEND (SRSHARP0_OFFSET + NR_TI_DNLP_BLEND ) //0x29 // +#define SRSHARP0_LTI_DIR_CORE_ALPHA (SRSHARP0_OFFSET + LTI_DIR_CORE_ALPHA ) //0x2a // +#define SRSHARP0_CTI_DIR_ALPHA (SRSHARP0_OFFSET + CTI_DIR_ALPHA ) //0x2b // +#define SRSHARP0_LTI_CTI_DF_GAIN (SRSHARP0_OFFSET + LTI_CTI_DF_GAIN ) //0x2c // +#define SRSHARP0_LTI_CTI_DIR_AC_DBG (SRSHARP0_OFFSET + LTI_CTI_DIR_AC_DBG ) //0x2d // +#define SRSHARP0_HCTI_FLT_CLP_DC (SRSHARP0_OFFSET + HCTI_FLT_CLP_DC ) //0x2e // +#define SRSHARP0_HCTI_BST_GAIN (SRSHARP0_OFFSET + HCTI_BST_GAIN ) //0x2f // +#define SRSHARP0_HCTI_BST_CORE (SRSHARP0_OFFSET + HCTI_BST_CORE ) //0x30 // +#define SRSHARP0_HCTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + HCTI_CON_2_GAIN_0 ) //0x31 // +#define SRSHARP0_HCTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + HCTI_CON_2_GAIN_1 ) //0x32 // +#define SRSHARP0_HCTI_OS_MARGIN (SRSHARP0_OFFSET + HCTI_OS_MARGIN ) //0x33 // +#define SRSHARP0_HLTI_FLT_CLP_DC (SRSHARP0_OFFSET + HLTI_FLT_CLP_DC ) //0x34 // +#define SRSHARP0_HLTI_BST_GAIN (SRSHARP0_OFFSET + HLTI_BST_GAIN ) //0x35 // +#define SRSHARP0_HLTI_BST_CORE (SRSHARP0_OFFSET + HLTI_BST_CORE ) //0x36 // +#define SRSHARP0_HLTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + HLTI_CON_2_GAIN_0 ) //0x37 // +#define SRSHARP0_HLTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + HLTI_CON_2_GAIN_1 ) //0x38 // +#define SRSHARP0_HLTI_OS_MARGIN (SRSHARP0_OFFSET + HLTI_OS_MARGIN ) //0x39 // +#define SRSHARP0_VLTI_FLT_CON_CLP (SRSHARP0_OFFSET + VLTI_FLT_CON_CLP ) //0x3a // +#define SRSHARP0_VLTI_BST_GAIN (SRSHARP0_OFFSET + VLTI_BST_GAIN ) //0x3b // +#define SRSHARP0_VLTI_BST_CORE (SRSHARP0_OFFSET + VLTI_BST_CORE ) //0x3c // +#define SRSHARP0_VLTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + VLTI_CON_2_GAIN_0 ) //0x3d // +#define SRSHARP0_VLTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + VLTI_CON_2_GAIN_1 ) //0x3e // +#define SRSHARP0_VCTI_FLT_CON_CLP (SRSHARP0_OFFSET + VCTI_FLT_CON_CLP ) //0x3f // +#define SRSHARP0_VCTI_BST_GAIN (SRSHARP0_OFFSET + VCTI_BST_GAIN ) //0x40 // +#define SRSHARP0_VCTI_BST_CORE (SRSHARP0_OFFSET + VCTI_BST_CORE ) //0x41 // +#define SRSHARP0_VCTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + VCTI_CON_2_GAIN_0 ) //0x42 // +#define SRSHARP0_VCTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + VCTI_CON_2_GAIN_1 ) //0x43 // +#define SRSHARP0_SHARP_3DLIMIT (SRSHARP0_OFFSET + SHARP_3DLIMIT ) //0x44 // +#define SRSHARP0_DNLP_EN (SRSHARP0_OFFSET + DNLP_EN ) //0x45 // +//`define SRSHARP0_DNLP_00 (`SRSHARP0_OFFSET + `DNLP_00 ) //8'h46 // +//`define SRSHARP0_DNLP_01 (`SRSHARP0_OFFSET + `DNLP_01 ) //8'h47 // +//`define SRSHARP0_DNLP_02 (`SRSHARP0_OFFSET + `DNLP_02 ) //8'h48 // +//`define SRSHARP0_DNLP_03 (`SRSHARP0_OFFSET + `DNLP_03 ) //8'h49 // +//`define SRSHARP0_DNLP_04 (`SRSHARP0_OFFSET + `DNLP_04 ) //8'h4a // +//`define SRSHARP0_DNLP_05 (`SRSHARP0_OFFSET + `DNLP_05 ) //8'h4b // +//`define SRSHARP0_DNLP_06 (`SRSHARP0_OFFSET + `DNLP_06 ) //8'h4c // +//`define SRSHARP0_DNLP_07 (`SRSHARP0_OFFSET + `DNLP_07 ) //8'h4d // +//`define SRSHARP0_DNLP_08 (`SRSHARP0_OFFSET + `DNLP_08 ) //8'h4e // +//`define SRSHARP0_DNLP_09 (`SRSHARP0_OFFSET + `DNLP_09 ) //8'h4f // +//`define SRSHARP0_DNLP_10 (`SRSHARP0_OFFSET + `DNLP_10 ) //8'h50 // +//`define SRSHARP0_DNLP_11 (`SRSHARP0_OFFSET + `DNLP_11 ) //8'h51 // +//`define SRSHARP0_DNLP_12 (`SRSHARP0_OFFSET + `DNLP_12 ) //8'h52 // +//`define SRSHARP0_DNLP_13 (`SRSHARP0_OFFSET + `DNLP_13 ) //8'h53 // +//`define SRSHARP0_DNLP_14 (`SRSHARP0_OFFSET + `DNLP_14 ) //8'h54 // +//`define SRSHARP0_DNLP_15 (`SRSHARP0_OFFSET + `DNLP_15 ) //8'h55 // +#define SRSHARP0_DEMO_CRTL (SRSHARP0_OFFSET + DEMO_CRTL ) //0x56 // +#define SRSHARP0_SHARP_SR2_CTRL (SRSHARP0_OFFSET + SHARP_SR2_CTRL ) //0x57 // +#define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_HCOEF0 ) //0x58 +#define SRSHARP0_SHARP_SR2_YBIC_HCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_HCOEF1 ) //0x59 // +#define SRSHARP0_SHARP_SR2_CBIC_HCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_HCOEF0 ) //0x5a // +#define SRSHARP0_SHARP_SR2_CBIC_HCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_HCOEF1 ) //0x5b // +#define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_VCOEF0 ) //0x5c // +#define SRSHARP0_SHARP_SR2_YBIC_VCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_VCOEF1 ) //0x5d // +#define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_VCOEF0 ) //0x5e // +#define SRSHARP0_SHARP_SR2_CBIC_VCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_VCOEF1 ) //0x5f // +#define SRSHARP0_SHARP_SR2_MISC (SRSHARP0_OFFSET + SHARP_SR2_MISC ) //0x60 // +#define SRSHARP0_SR3_SAD_CTRL (SRSHARP0_OFFSET + SHARP_SR3_SAD_CTRL ) // 0x61 // +#define SRSHARP0_SR3_PK_CTRL0 (SRSHARP0_OFFSET + SHARP_SR3_PK_CTRL0 ) // 0x62 +#define SRSHARP0_SR3_PK_CTRL1 (SRSHARP0_OFFSET + SHARP_SR3_PK_CTRL1 ) // 0x63 +#define SRSHARP0_DEJ_CTRL (SRSHARP0_OFFSET + SHARP_DEJ_CTRL ) // 0x64 +#define SRSHARP0_DEJ_ALPHA (SRSHARP0_OFFSET + SHARP_DEJ_ALPHA ) // 0x65 +#define SRSHARP0_SR3_DRTLPF_EN (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_EN ) // 0x66 +#define SRSHARP0_SR3_DRTLPF_ALPHA_0 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_0 ) // 0x67 +#define SRSHARP0_SR3_DRTLPF_ALPHA_1 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_1 ) // 0x68 +#define SRSHARP0_SR3_DRTLPF_ALPHA_2 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_2 ) // 0x69 +#define SRSHARP0_SR3_DRTLPF_ALPHA_OFST (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_OFST ) // 0x6a +#define SRSHARP0_SR3_DERING_CTRL (SRSHARP0_OFFSET + SHARP_SR3_DERING_CTRL ) // 0x6b +#define SRSHARP0_SR3_DERING_LUMA2PKGAIN_0TO3 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ) // 0x6c +#define SRSHARP0_SR3_DERING_LUMA2PKGAIN_4TO6 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ) // 0x6d +#define SRSHARP0_SR3_DERING_LUMA2PKOS_0TO3 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_0TO3 ) // 0x6e +#define SRSHARP0_SR3_DERING_LUMA2PKOS_4TO6 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_4TO6 ) // 0x6f +#define SRSHARP0_SR3_DERING_GAINVS_MADSAD (SRSHARP0_OFFSET + SHARP_SR3_DERING_GAINVS_MADSAD ) // 0x70 +#define SRSHARP0_SR3_DERING_GAINVS_VR2MAX (SRSHARP0_OFFSET + SHARP_SR3_DERING_GAINVS_VR2MAX ) // 0x71 +#define SRSHARP0_SR3_DERING_PARAM0 (SRSHARP0_OFFSET + SHARP_SR3_DERING_PARAM0 ) // 0x72 +#define SRSHARP0_SR3_DRTLPF_THETA (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_THETA ) // 0x73 +#define SRSHARP0_SATPRT_CTRL (SRSHARP0_OFFSET + SHARP_SATPRT_CTRL ) // 0x74 +#define SRSHARP0_SATPRT_DIVM (SRSHARP0_OFFSET + SHARP_SATPRT_DIVM ) // 0x75 +#define SRSHARP0_DB_FLT_CTRL (SRSHARP0_OFFSET + SHARP_DB_FLT_CTRL ) // 0x77 +//`define SRSHARP0_DB_FLT_YC_THRD (`SRSHARP0_OFFSET + `SHARP_DB_FLT_YC_THRD ) // 8'h78 +#define SRSHARP0_DB_FLT_CTRL1 (SRSHARP0_OFFSET + SHARP_DB_FLT_CTRL1 ) // 0xb8 +#define SRSHARP0_DB_FLT_LUMA_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_LUMA_THRD ) // 0xb9 +#define SRSHARP0_DB_FLT_CHRM_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_CHRM_THRD ) // 0xba +#define SRSHARP0_DB_FLT_RANDLUT (SRSHARP0_OFFSET + SHARP_DB_FLT_RANDLUT ) // 0x79 +#define SRSHARP0_DB_FLT_PXI_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_PXI_THRD ) // 0x7a +#define SRSHARP0_DB_FLT_SEED_Y (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_Y ) // 0x7b +#define SRSHARP0_DB_FLT_SEED_U (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_U ) // 0x7c +#define SRSHARP0_DB_FLT_SEED_V (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_V ) // 0x7d +#define SRSHARP0_PKGAIN_VSLUMA_LUT_L (SRSHARP0_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_L ) // 0x7e +#define SRSHARP0_PKGAIN_VSLUMA_LUT_H (SRSHARP0_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_H ) // 0x7f +#define SRSHARP0_PKOSHT_VSLUMA_LUT_L (SRSHARP0_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_L ) // 0x80 +#define SRSHARP0_PKOSHT_VSLUMA_LUT_H (SRSHARP0_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_H ) // 0x81 +#define SRSHARP0_SATPRT_LMT_RGB1 (SRSHARP0_OFFSET + SHARP_SATPRT_LMT_RGB1 ) // 0x82 +#define SRSHARP0_SATPRT_LMT_RGB2 (SRSHARP0_OFFSET + SHARP_SATPRT_LMT_RGB2 ) // 0x83 +#define SRSHARP0_SHARP_GATE_CLK_CTRL_0 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_0 ) // 0x84 +#define SRSHARP0_SHARP_GATE_CLK_CTRL_1 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_1 ) // 0x85 +#define SRSHARP0_SHARP_GATE_CLK_CTRL_2 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_2 ) // 0x86 +#define SRSHARP0_SHARP_GATE_CLK_CTRL_3 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_3 ) // 0x87 +#define SRSHARP0_SHARP_DPS_CTRL (SRSHARP0_OFFSET + SHARP_DPS_CTRL ) // 0x88 +#define SRSHARP0_DNLP_00 (SRSHARP0_OFFSET + DNLP_00 ) // 0x90 // +#define SRSHARP0_DNLP_01 (SRSHARP0_OFFSET + DNLP_01 ) // 0x91 // +#define SRSHARP0_DNLP_02 (SRSHARP0_OFFSET + DNLP_02 ) // 0x92 // +#define SRSHARP0_DNLP_03 (SRSHARP0_OFFSET + DNLP_03 ) // 0x93 // +#define SRSHARP0_DNLP_04 (SRSHARP0_OFFSET + DNLP_04 ) // 0x94 // +#define SRSHARP0_DNLP_05 (SRSHARP0_OFFSET + DNLP_05 ) // 0x95 // +#define SRSHARP0_DNLP_06 (SRSHARP0_OFFSET + DNLP_06 ) // 0x96 // +#define SRSHARP0_DNLP_07 (SRSHARP0_OFFSET + DNLP_07 ) // 0x97 // +#define SRSHARP0_DNLP_08 (SRSHARP0_OFFSET + DNLP_08 ) // 0x98 // +#define SRSHARP0_DNLP_09 (SRSHARP0_OFFSET + DNLP_09 ) // 0x99 // +#define SRSHARP0_DNLP_10 (SRSHARP0_OFFSET + DNLP_10 ) // 0x9a // +#define SRSHARP0_DNLP_11 (SRSHARP0_OFFSET + DNLP_11 ) // 0x9b // +#define SRSHARP0_DNLP_12 (SRSHARP0_OFFSET + DNLP_12 ) // 0x9c // +#define SRSHARP0_DNLP_13 (SRSHARP0_OFFSET + DNLP_13 ) // 0x9d // +#define SRSHARP0_DNLP_14 (SRSHARP0_OFFSET + DNLP_14 ) // 0x9e // +#define SRSHARP0_DNLP_15 (SRSHARP0_OFFSET + DNLP_15 ) // 0x9f // +#define SRSHARP0_DNLP_16 (SRSHARP0_OFFSET + DNLP_16 ) // 0xa0 // +#define SRSHARP0_DNLP_17 (SRSHARP0_OFFSET + DNLP_17 ) // 0xa1 // +#define SRSHARP0_DNLP_18 (SRSHARP0_OFFSET + DNLP_18 ) // 0xa2 // +#define SRSHARP0_DNLP_19 (SRSHARP0_OFFSET + DNLP_19 ) // 0xa3 // +#define SRSHARP0_DNLP_20 (SRSHARP0_OFFSET + DNLP_20 ) // 0xa4 // +#define SRSHARP0_DNLP_21 (SRSHARP0_OFFSET + DNLP_21 ) // 0xa5 // +#define SRSHARP0_DNLP_22 (SRSHARP0_OFFSET + DNLP_22 ) // 0xa6 // +#define SRSHARP0_DNLP_23 (SRSHARP0_OFFSET + DNLP_23 ) // 0xa7 // +#define SRSHARP0_DNLP_24 (SRSHARP0_OFFSET + DNLP_24 ) // 0xa8 // +#define SRSHARP0_DNLP_25 (SRSHARP0_OFFSET + DNLP_25 ) // 0xa9 // +#define SRSHARP0_DNLP_26 (SRSHARP0_OFFSET + DNLP_26 ) // 0xaa // +#define SRSHARP0_DNLP_27 (SRSHARP0_OFFSET + DNLP_27 ) // 0xab // +#define SRSHARP0_DNLP_28 (SRSHARP0_OFFSET + DNLP_28 ) // 0xac // +#define SRSHARP0_DNLP_29 (SRSHARP0_OFFSET + DNLP_29 ) // 0xad // +#define SRSHARP0_DNLP_30 (SRSHARP0_OFFSET + DNLP_30 ) // 0xae // +#define SRSHARP0_DNLP_31 (SRSHARP0_OFFSET + DNLP_31 ) // 0xaf // +#define SRSHARP0_SHARP_SYNC_CTRL (SRSHARP0_OFFSET + SHARP_SYNC_CTRL ) // 0xb0 // +#define SRSHARP0_LC_INPUT_MUX (SRSHARP0_OFFSET + LC_INPUT_MUX ) // 0xb1 // +#define SRSHARP0_NR_GAU_YH_COEF02 (SRSHARP0_OFFSET + NR_GAU_YH_COEF02 ) // 0xb2 // +#define SRSHARP0_NR_GAU_YH_COEF34 (SRSHARP0_OFFSET + NR_GAU_YH_COEF34 ) // 0xb3 // +#define SRSHARP0_NR_GAU_YV_COEF1 (SRSHARP0_OFFSET + NR_GAU_YV_COEF1 ) // 0xb4 // +#define SRSHARP0_NR_GAU_CH_COEF02 (SRSHARP0_OFFSET + NR_GAU_CH_COEF02 ) // 0xb5 // +#define SRSHARP0_NR_GAU_CH_COEF34 (SRSHARP0_OFFSET + NR_GAU_CH_COEF34 ) // 0xb6 // +#define SRSHARP0_NR_GAU_CV_COEF1 (SRSHARP0_OFFSET + NR_GAU_CV_COEF1 ) // 0xb7 // +#define SRSHARP0_LC_TOP_CTRL (SRSHARP0_OFFSET + LC_TOP_CTRL ) // 0xc0 // +#define SRSHARP0_LC_HV_NUM (SRSHARP0_OFFSET + LC_HV_NUM ) // 0xc1 +#define SRSHARP0_LC_SAT_LUT_0_1 (SRSHARP0_OFFSET + LC_SAT_LUT_0_1 ) // 0xc2 +#define SRSHARP0_LC_SAT_LUT_2_3 (SRSHARP0_OFFSET + LC_SAT_LUT_2_3 ) // 0xc3 +#define SRSHARP0_LC_SAT_LUT_4_5 (SRSHARP0_OFFSET + LC_SAT_LUT_4_5 ) // 0xc4 +#define SRSHARP0_LC_SAT_LUT_6_7 (SRSHARP0_OFFSET + LC_SAT_LUT_6_7 ) // 0xc5 +#define SRSHARP0_LC_SAT_LUT_8_9 (SRSHARP0_OFFSET + LC_SAT_LUT_8_9 ) // 0xc6 +#define SRSHARP0_LC_SAT_LUT_10_11 (SRSHARP0_OFFSET + LC_SAT_LUT_10_11 ) // 0xc7 +#define SRSHARP0_LC_SAT_LUT_12_13 (SRSHARP0_OFFSET + LC_SAT_LUT_12_13 ) // 0xc8 +#define SRSHARP0_LC_SAT_LUT_14_15 (SRSHARP0_OFFSET + LC_SAT_LUT_14_15 ) // 0xc9 +#define SRSHARP0_LC_SAT_LUT_16_17 (SRSHARP0_OFFSET + LC_SAT_LUT_16_17 ) // 0xca +#define SRSHARP0_LC_SAT_LUT_18_19 (SRSHARP0_OFFSET + LC_SAT_LUT_18_19 ) // 0xcb +#define SRSHARP0_LC_SAT_LUT_20_21 (SRSHARP0_OFFSET + LC_SAT_LUT_20_21 ) // 0xcc +#define SRSHARP0_LC_SAT_LUT_22_23 (SRSHARP0_OFFSET + LC_SAT_LUT_22_23 ) // 0xcd +#define SRSHARP0_LC_SAT_LUT_24_25 (SRSHARP0_OFFSET + LC_SAT_LUT_24_25 ) // 0xce +#define SRSHARP0_LC_SAT_LUT_26_27 (SRSHARP0_OFFSET + LC_SAT_LUT_26_27 ) // 0xcf +#define SRSHARP0_LC_SAT_LUT_28_29 (SRSHARP0_OFFSET + LC_SAT_LUT_28_29 ) // 0xd0 +#define SRSHARP0_LC_SAT_LUT_30_31 (SRSHARP0_OFFSET + LC_SAT_LUT_30_31 ) // 0xd1 +#define SRSHARP0_LC_SAT_LUT_32_33 (SRSHARP0_OFFSET + LC_SAT_LUT_32_33 ) // 0xd2 +#define SRSHARP0_LC_SAT_LUT_34_35 (SRSHARP0_OFFSET + LC_SAT_LUT_34_35 ) // 0xd3 +#define SRSHARP0_LC_SAT_LUT_36_37 (SRSHARP0_OFFSET + LC_SAT_LUT_36_37 ) // 0xd4 +#define SRSHARP0_LC_SAT_LUT_38_39 (SRSHARP0_OFFSET + LC_SAT_LUT_38_39 ) // 0xd5 +#define SRSHARP0_LC_SAT_LUT_40_41 (SRSHARP0_OFFSET + LC_SAT_LUT_40_41 ) // 0xd6 +#define SRSHARP0_LC_SAT_LUT_42_43 (SRSHARP0_OFFSET + LC_SAT_LUT_42_43 ) // 0xd7 +#define SRSHARP0_LC_SAT_LUT_44_45 (SRSHARP0_OFFSET + LC_SAT_LUT_44_45 ) // 0xd8 +#define SRSHARP0_LC_SAT_LUT_46_47 (SRSHARP0_OFFSET + LC_SAT_LUT_46_47 ) // 0xd9 +#define SRSHARP0_LC_SAT_LUT_48_49 (SRSHARP0_OFFSET + LC_SAT_LUT_48_49 ) // 0xda +#define SRSHARP0_LC_SAT_LUT_50_51 (SRSHARP0_OFFSET + LC_SAT_LUT_50_51 ) // 0xdb +#define SRSHARP0_LC_SAT_LUT_52_53 (SRSHARP0_OFFSET + LC_SAT_LUT_52_53 ) // 0xdc +#define SRSHARP0_LC_SAT_LUT_54_55 (SRSHARP0_OFFSET + LC_SAT_LUT_54_55 ) // 0xdd +#define SRSHARP0_LC_SAT_LUT_56_57 (SRSHARP0_OFFSET + LC_SAT_LUT_56_57 ) // 0xde +#define SRSHARP0_LC_SAT_LUT_58_59 (SRSHARP0_OFFSET + LC_SAT_LUT_58_59 ) // 0xdf +#define SRSHARP0_LC_SAT_LUT_60_61 (SRSHARP0_OFFSET + LC_SAT_LUT_60_61 ) // 0xe0 +#define SRSHARP0_LC_SAT_LUT_62 (SRSHARP0_OFFSET + LC_SAT_LUT_62 ) // 0xe1 +#define SRSHARP0_LC_CURVE_BLK_HIDX_0_1 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_0_1 ) // 0xe2 +#define SRSHARP0_LC_CURVE_BLK_HIDX_2_3 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_2_3 ) // 0xe3 +#define SRSHARP0_LC_CURVE_BLK_HIDX_4_5 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_4_5 ) // 0xe4 +#define SRSHARP0_LC_CURVE_BLK_HIDX_6_7 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_6_7 ) // 0xe5 +#define SRSHARP0_LC_CURVE_BLK_HIDX_8_9 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_8_9 ) // 0xe6 +#define SRSHARP0_LC_CURVE_BLK_HIDX_10_11 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_10_11 ) // 0xe7 +#define SRSHARP0_LC_CURVE_BLK_HIDX_12 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_12 ) // 0xe8 +#define SRSHARP0_LC_CURVE_BLK_VIDX_0_1 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_0_1 ) // 0xe9 +#define SRSHARP0_LC_CURVE_BLK_VIDX_2_3 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_2_3 ) // 0xea +#define SRSHARP0_LC_CURVE_BLK_VIDX_4_5 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_4_5 ) // 0xeb +#define SRSHARP0_LC_CURVE_BLK_VIDX_6_7 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_6_7 ) // 0xec +#define SRSHARP0_LC_CURVE_BLK_VIDX_8 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_8 ) // 0xed +#define SRSHARP0_LC_YUV2RGB_MAT_0_1 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_0_1 ) // 0xee +#define SRSHARP0_LC_YUV2RGB_MAT_2_3 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_2_3 ) // 0xef +#define SRSHARP0_LC_YUV2RGB_MAT_4_5 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_4_5 ) // 0xf0 +#define SRSHARP0_LC_YUV2RGB_MAT_6_7 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_6_7 ) // 0xf1 +#define SRSHARP0_LC_YUV2RGB_MAT_8 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_8 ) // 0xf2 +#define SRSHARP0_LC_RGB2YUV_MAT_0_1 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_0_1 ) // 0xf3 +#define SRSHARP0_LC_RGB2YUV_MAT_2_3 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_2_3 ) // 0xf4 +#define SRSHARP0_LC_RGB2YUV_MAT_4_5 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_4_5 ) // 0xf5 +#define SRSHARP0_LC_RGB2YUV_MAT_6_7 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_6_7 ) // 0xf6 +#define SRSHARP0_LC_RGB2YUV_MAT_8 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_8 ) // 0xf7 +#define SRSHARP0_LC_YUV2RGB_OFST (SRSHARP0_OFFSET + LC_YUV2RGB_OFST ) // 0xf8 +#define SRSHARP0_LC_YUV2RGB_CLIP (SRSHARP0_OFFSET + LC_YUV2RGB_CLIP ) // 0xf9 +#define SRSHARP0_LC_RGB2YUV_OFST (SRSHARP0_OFFSET + LC_RGB2YUV_OFST ) // 0xfa +#define SRSHARP0_LC_RGB2YUV_CLIP (SRSHARP0_OFFSET + LC_RGB2YUV_CLIP ) // 0xfb +#define SRSHARP0_LC_MAP_RAM_CTRL (SRSHARP0_OFFSET + LC_MAP_RAM_CTRL ) // 0xfc +#define SRSHARP0_LC_MAP_RAM_ADDR (SRSHARP0_OFFSET + LC_MAP_RAM_ADDR ) // 0xfd +#define SRSHARP0_LC_MAP_RAM_DATA (SRSHARP0_OFFSET + LC_MAP_RAM_DATA ) // 0xfe + +#define SRSHARP0_FMETER_CTRL (SRSHARP0_OFFSET + SHARP_FMETER_CTRL ) // 0x89 +#define SRSHARP0_FMETER_WIN_HOR (SRSHARP0_OFFSET + SHARP_FMETER_WIN_HOR ) // 0x8a +#define SRSHARP0_FMETER_WIN_VER (SRSHARP0_OFFSET + SHARP_FMETER_WIN_VER ) // 0x8b +#define SRSHARP0_FMETER_CORING (SRSHARP0_OFFSET + SHARP_FMETER_CORING ) // 0x8c +#define SRSHARP0_FMETER_RATIO_H (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_H ) // 0x8d +#define SRSHARP0_FMETER_RATIO_V (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_V ) // 0x8e +#define SRSHARP0_FMETER_RATIO_D (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_D ) // 0x8f +#define SRSHARP0_RO_FMETER_HCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE0 ) // 0x46 +#define SRSHARP0_RO_FMETER_HCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE1 ) // 0x47 +#define SRSHARP0_RO_FMETER_HCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE2 ) // 0x48 +#define SRSHARP0_RO_FMETER_HCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE3 ) // 0x49 +#define SRSHARP0_RO_FMETER_VCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE0 ) // 0x4a +#define SRSHARP0_RO_FMETER_VCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE1 ) // 0x4b +#define SRSHARP0_RO_FMETER_VCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE2 ) // 0x4c +#define SRSHARP0_RO_FMETER_VCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE3 ) // 0x4d +#define SRSHARP0_RO_FMETER_PDCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE0 ) // 0x4e +#define SRSHARP0_RO_FMETER_PDCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE1 ) // 0x4f +#define SRSHARP0_RO_FMETER_PDCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE2 ) // 0x50 +#define SRSHARP0_RO_FMETER_PDCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE3 ) // 0x51 +#define SRSHARP0_RO_FMETER_NDCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE0 ) // 0x52 +#define SRSHARP0_RO_FMETER_NDCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE1 ) // 0x53 +#define SRSHARP0_RO_FMETER_NDCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE2 ) // 0x54 +#define SRSHARP0_RO_FMETER_NDCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE3 ) // 0x55 + + + + + +//// srsharp1 reg define + +#define SRSHARP1_SHARP_HVSIZE (SRSHARP1_OFFSET + SHARP_HVSIZE ) //0x00 // +#define SRSHARP1_SHARP_HVBLANK_NUM (SRSHARP1_OFFSET + SHARP_HVBLANK_NUM ) //0x01 // +#define SRSHARP1_NR_GAUSSIAN_MODE (SRSHARP1_OFFSET + NR_GAUSSIAN_MODE ) //0x02 // +#define SRSHARP1_PK_CON_2CIRHPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2CIRHPGAIN_TH_RATE ) //0x05 // +#define SRSHARP1_PK_CON_2CIRHPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2CIRHPGAIN_LIMIT ) //0x06 // +#define SRSHARP1_PK_CON_2CIRBPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2CIRBPGAIN_TH_RATE ) //0x07 // +#define SRSHARP1_PK_CON_2CIRBPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2CIRBPGAIN_LIMIT ) //0x08 // +#define SRSHARP1_PK_CON_2DRTHPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2DRTHPGAIN_TH_RATE ) //0x09 // +#define SRSHARP1_PK_CON_2DRTHPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2DRTHPGAIN_LIMIT ) //0x0a // +#define SRSHARP1_PK_CON_2DRTBPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2DRTBPGAIN_TH_RATE ) //0x0b // +#define SRSHARP1_PK_CON_2DRTBPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2DRTBPGAIN_LIMIT ) //0x0c // +#define SRSHARP1_PK_CIRFB_LPF_MODE (SRSHARP1_OFFSET + PK_CIRFB_LPF_MODE ) //0x0d // +#define SRSHARP1_PK_DRTFB_LPF_MODE (SRSHARP1_OFFSET + PK_DRTFB_LPF_MODE ) //0x0e // +#define SRSHARP1_PK_CIRFB_HP_CORING (SRSHARP1_OFFSET + PK_CIRFB_HP_CORING ) //0x0f // +#define SRSHARP1_PK_CIRFB_BP_CORING (SRSHARP1_OFFSET + PK_CIRFB_BP_CORING ) //0x10 // +#define SRSHARP1_PK_DRTFB_HP_CORING (SRSHARP1_OFFSET + PK_DRTFB_HP_CORING ) //0x11 // +#define SRSHARP1_PK_DRTFB_BP_CORING (SRSHARP1_OFFSET + PK_DRTFB_BP_CORING ) //0x12 // +#define SRSHARP1_PK_CIRFB_BLEND_GAIN (SRSHARP1_OFFSET + PK_CIRFB_BLEND_GAIN ) //0x13 // +#define SRSHARP1_NR_ALPY_SSD_GAIN_OFST (SRSHARP1_OFFSET + NR_ALPY_SSD_GAIN_OFST ) //0x14 // +#define SRSHARP1_NR_ALP0Y_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP0Y_ERR2CURV_TH_RATE ) //0x15 // +#define SRSHARP1_NR_ALP0Y_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP0Y_ERR2CURV_LIMIT ) //0x16 // +#define SRSHARP1_NR_ALP0C_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP0C_ERR2CURV_TH_RATE ) //0x17 // +#define SRSHARP1_NR_ALP0C_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP0C_ERR2CURV_LIMIT ) //0x18 // +#define SRSHARP1_NR_ALP0_MIN_MAX (SRSHARP1_OFFSET + NR_ALP0_MIN_MAX ) //0x19 // +#define SRSHARP1_NR_ALP1_MIERR_CORING (SRSHARP1_OFFSET + NR_ALP1_MIERR_CORING ) //0x1a // +#define SRSHARP1_NR_ALP1_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP1_ERR2CURV_TH_RATE ) //0x1b // +#define SRSHARP1_NR_ALP1_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP1_ERR2CURV_LIMIT ) //0x1c // +#define SRSHARP1_NR_ALP1_MIN_MAX (SRSHARP1_OFFSET + NR_ALP1_MIN_MAX ) //0x1d // +#define SRSHARP1_PK_ALP2_MIERR_CORING (SRSHARP1_OFFSET + PK_ALP2_MIERR_CORING ) //0x1e // +#define SRSHARP1_PK_ALP2_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + PK_ALP2_ERR2CURV_TH_RATE ) //0x1f // +#define SRSHARP1_PK_ALP2_ERR2CURV_LIMIT (SRSHARP1_OFFSET + PK_ALP2_ERR2CURV_LIMIT ) //0x20 // +#define SRSHARP1_PK_ALP2_MIN_MAX (SRSHARP1_OFFSET + PK_ALP2_MIN_MAX ) //0x21 // +#define SRSHARP1_PK_FINALGAIN_HP_BP (SRSHARP1_OFFSET + PK_FINALGAIN_HP_BP ) //0x22 // +#define SRSHARP1_PK_OS_HORZ_CORE_GAIN (SRSHARP1_OFFSET + PK_OS_HORZ_CORE_GAIN ) //0x23 // +#define SRSHARP1_PK_OS_VERT_CORE_GAIN (SRSHARP1_OFFSET + PK_OS_VERT_CORE_GAIN ) //0x24 // +#define SRSHARP1_PK_OS_ADPT_MISC (SRSHARP1_OFFSET + PK_OS_ADPT_MISC ) //0x25 // +#define SRSHARP1_PK_OS_STATIC (SRSHARP1_OFFSET + PK_OS_STATIC ) //0x26 // +#define SRSHARP1_PK_NR_ENABLE (SRSHARP1_OFFSET + PK_NR_ENABLE ) //0x27 // +#define SRSHARP1_PK_DRT_SAD_MISC (SRSHARP1_OFFSET + PK_DRT_SAD_MISC ) //0x28 // +#define SRSHARP1_NR_TI_DNLP_BLEND (SRSHARP1_OFFSET + NR_TI_DNLP_BLEND ) //0x29 // +#define SRSHARP1_LTI_DIR_CORE_ALPHA (SRSHARP1_OFFSET + LTI_DIR_CORE_ALPHA ) //0x2a // +#define SRSHARP1_CTI_DIR_ALPHA (SRSHARP1_OFFSET + CTI_DIR_ALPHA ) //0x2b // +#define SRSHARP1_LTI_CTI_DF_GAIN (SRSHARP1_OFFSET + LTI_CTI_DF_GAIN ) //0x2c // +#define SRSHARP1_LTI_CTI_DIR_AC_DBG (SRSHARP1_OFFSET + LTI_CTI_DIR_AC_DBG ) //0x2d // +#define SRSHARP1_HCTI_FLT_CLP_DC (SRSHARP1_OFFSET + HCTI_FLT_CLP_DC ) //0x2e // +#define SRSHARP1_HCTI_BST_GAIN (SRSHARP1_OFFSET + HCTI_BST_GAIN ) //0x2f // +#define SRSHARP1_HCTI_BST_CORE (SRSHARP1_OFFSET + HCTI_BST_CORE ) //0x30 // +#define SRSHARP1_HCTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + HCTI_CON_2_GAIN_0 ) //0x31 // +#define SRSHARP1_HCTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + HCTI_CON_2_GAIN_1 ) //0x32 // +#define SRSHARP1_HCTI_OS_MARGIN (SRSHARP1_OFFSET + HCTI_OS_MARGIN ) //0x33 // +#define SRSHARP1_HLTI_FLT_CLP_DC (SRSHARP1_OFFSET + HLTI_FLT_CLP_DC ) //0x34 // +#define SRSHARP1_HLTI_BST_GAIN (SRSHARP1_OFFSET + HLTI_BST_GAIN ) //0x35 // +#define SRSHARP1_HLTI_BST_CORE (SRSHARP1_OFFSET + HLTI_BST_CORE ) //0x36 // +#define SRSHARP1_HLTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + HLTI_CON_2_GAIN_0 ) //0x37 // +#define SRSHARP1_HLTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + HLTI_CON_2_GAIN_1 ) //0x38 // +#define SRSHARP1_HLTI_OS_MARGIN (SRSHARP1_OFFSET + HLTI_OS_MARGIN ) //0x39 // +#define SRSHARP1_VLTI_FLT_CON_CLP (SRSHARP1_OFFSET + VLTI_FLT_CON_CLP ) //0x3a // +#define SRSHARP1_VLTI_BST_GAIN (SRSHARP1_OFFSET + VLTI_BST_GAIN ) //0x3b // +#define SRSHARP1_VLTI_BST_CORE (SRSHARP1_OFFSET + VLTI_BST_CORE ) //0x3c // +#define SRSHARP1_VLTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + VLTI_CON_2_GAIN_0 ) //0x3d // +#define SRSHARP1_VLTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + VLTI_CON_2_GAIN_1 ) //0x3e // +#define SRSHARP1_VCTI_FLT_CON_CLP (SRSHARP1_OFFSET + VCTI_FLT_CON_CLP ) //0x3f // +#define SRSHARP1_VCTI_BST_GAIN (SRSHARP1_OFFSET + VCTI_BST_GAIN ) //0x40 // +#define SRSHARP1_VCTI_BST_CORE (SRSHARP1_OFFSET + VCTI_BST_CORE ) //0x41 // +#define SRSHARP1_VCTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + VCTI_CON_2_GAIN_0 ) //0x42 // +#define SRSHARP1_VCTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + VCTI_CON_2_GAIN_1 ) //0x43 // +#define SRSHARP1_SHARP_3DLIMIT (SRSHARP1_OFFSET + SHARP_3DLIMIT ) //0x44 // +#define SRSHARP1_DNLP_EN (SRSHARP1_OFFSET + DNLP_EN ) //0x45 // +//`define SRSHARP1_DNLP_00 (`SRSHARP1_OFFSET + `DNLP_00 ) //8'h46 // +//`define SRSHARP1_DNLP_01 (`SRSHARP1_OFFSET + `DNLP_01 ) //8'h47 // +//`define SRSHARP1_DNLP_02 (`SRSHARP1_OFFSET + `DNLP_02 ) //8'h48 // +//`define SRSHARP1_DNLP_03 (`SRSHARP1_OFFSET + `DNLP_03 ) //8'h49 // +//`define SRSHARP1_DNLP_04 (`SRSHARP1_OFFSET + `DNLP_04 ) //8'h4a // +//`define SRSHARP1_DNLP_05 (`SRSHARP1_OFFSET + `DNLP_05 ) //8'h4b // +//`define SRSHARP1_DNLP_06 (`SRSHARP1_OFFSET + `DNLP_06 ) //8'h4c // +//`define SRSHARP1_DNLP_07 (`SRSHARP1_OFFSET + `DNLP_07 ) //8'h4d // +//`define SRSHARP1_DNLP_08 (`SRSHARP1_OFFSET + `DNLP_08 ) //8'h4e // +//`define SRSHARP1_DNLP_09 (`SRSHARP1_OFFSET + `DNLP_09 ) //8'h4f // +//`define SRSHARP1_DNLP_10 (`SRSHARP1_OFFSET + `DNLP_10 ) //8'h50 // +//`define SRSHARP1_DNLP_11 (`SRSHARP1_OFFSET + `DNLP_11 ) //8'h51 // +//`define SRSHARP1_DNLP_12 (`SRSHARP1_OFFSET + `DNLP_12 ) //8'h52 // +//`define SRSHARP1_DNLP_13 (`SRSHARP1_OFFSET + `DNLP_13 ) //8'h53 // +//`define SRSHARP1_DNLP_14 (`SRSHARP1_OFFSET + `DNLP_14 ) //8'h54 // +//`define SRSHARP1_DNLP_15 (`SRSHARP1_OFFSET + `DNLP_15 ) //8'h55 // +#define SRSHARP1_DEMO_CRTL (SRSHARP1_OFFSET + DEMO_CRTL ) //0x56 // +#define SRSHARP1_SHARP_SR2_CTRL (SRSHARP1_OFFSET + SHARP_SR2_CTRL ) //0x57 // +#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_HCOEF0 ) //0x58 +#define SRSHARP1_SHARP_SR2_YBIC_HCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_HCOEF1 ) //0x59 // +#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_HCOEF0 ) //0x5a // +#define SRSHARP1_SHARP_SR2_CBIC_HCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_HCOEF1 ) //0x5b // +#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_VCOEF0 ) //0x5c // +#define SRSHARP1_SHARP_SR2_YBIC_VCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_VCOEF1 ) //0x5d // +#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_VCOEF0 ) //0x5e // +#define SRSHARP1_SHARP_SR2_CBIC_VCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_VCOEF1 ) //0x5f // +#define SRSHARP1_SHARP_SR2_MISC (SRSHARP1_OFFSET + SHARP_SR2_MISC ) //0x60 // +#define SRSHARP1_SR3_SAD_CTRL (SRSHARP1_OFFSET + SHARP_SR3_SAD_CTRL ) // 0x61 // +#define SRSHARP1_SR3_PK_CTRL0 (SRSHARP1_OFFSET + SHARP_SR3_PK_CTRL0 ) // 0x62 +#define SRSHARP1_SR3_PK_CTRL1 (SRSHARP1_OFFSET + SHARP_SR3_PK_CTRL1 ) // 0x63 +#define SRSHARP1_DEJ_CTRL (SRSHARP1_OFFSET + SHARP_DEJ_CTRL ) // 0x64 +#define SRSHARP1_DEJ_ALPHA (SRSHARP1_OFFSET + SHARP_DEJ_ALPHA ) // 0x65 +#define SRSHARP1_SR3_DRTLPF_EN (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_EN ) // 0x66 +#define SRSHARP1_SR3_DRTLPF_ALPHA_0 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_0 ) // 0x67 +#define SRSHARP1_SR3_DRTLPF_ALPHA_1 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_1 ) // 0x68 +#define SRSHARP1_SR3_DRTLPF_ALPHA_2 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_2 ) // 0x69 +#define SRSHARP1_SR3_DRTLPF_ALPHA_OFST (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_OFST ) // 0x6a +#define SRSHARP1_SR3_DERING_CTRL (SRSHARP1_OFFSET + SHARP_SR3_DERING_CTRL ) // 0x6b +#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ) // 0x6c +#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ) // 0x6d +#define SRSHARP1_SR3_DERING_LUMA2PKOS_0TO3 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_0TO3 ) // 0x6e +#define SRSHARP1_SR3_DERING_LUMA2PKOS_4TO6 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_4TO6 ) // 0x6f +#define SRSHARP1_SR3_DERING_GAINVS_MADSAD (SRSHARP1_OFFSET + SHARP_SR3_DERING_GAINVS_MADSAD ) // 0x70 +#define SRSHARP1_SR3_DERING_GAINVS_VR2MAX (SRSHARP1_OFFSET + SHARP_SR3_DERING_GAINVS_VR2MAX ) // 0x71 +#define SRSHARP1_SR3_DERING_PARAM0 (SRSHARP1_OFFSET + SHARP_SR3_DERING_PARAM0 ) // 0x72 +#define SRSHARP1_SR3_DRTLPF_THETA (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_THETA ) // 0x73 +#define SRSHARP1_SATPRT_CTRL (SRSHARP1_OFFSET + SHARP_SATPRT_CTRL ) // 0x74 +#define SRSHARP1_SATPRT_DIVM (SRSHARP1_OFFSET + SHARP_SATPRT_DIVM ) // 0x75 +#define SRSHARP1_DB_FLT_CTRL (SRSHARP1_OFFSET + SHARP_DB_FLT_CTRL ) // 0x77 +//`define SRSHARP1_DB_FLT_YC_THRD (`SRSHARP1_OFFSET + `SHARP_DB_FLT_YC_THRD ) // 8'h78 +#define SRSHARP1_DB_FLT_CTRL1 (SRSHARP1_OFFSET + SHARP_DB_FLT_CTRL1 ) // 0xb8 +#define SRSHARP1_DB_FLT_LUMA_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_LUMA_THRD ) // 0xb9 +#define SRSHARP1_DB_FLT_CHRM_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_CHRM_THRD ) // 0xba +#define SRSHARP1_DB_FLT_RANDLUT (SRSHARP1_OFFSET + SHARP_DB_FLT_RANDLUT ) // 0x79 +#define SRSHARP1_DB_FLT_PXI_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_PXI_THRD ) // 0x7a +#define SRSHARP1_DB_FLT_SEED_Y (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_Y ) // 0x7b +#define SRSHARP1_DB_FLT_SEED_U (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_U ) // 0x7c +#define SRSHARP1_DB_FLT_SEED_V (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_V ) // 0x7d +#define SRSHARP1_PKGAIN_VSLUMA_LUT_L (SRSHARP1_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_L ) // 0x7e +#define SRSHARP1_PKGAIN_VSLUMA_LUT_H (SRSHARP1_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_H ) // 0x7f +#define SRSHARP1_PKOSHT_VSLUMA_LUT_L (SRSHARP1_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_L ) // 0x80 +#define SRSHARP1_PKOSHT_VSLUMA_LUT_H (SRSHARP1_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_H ) // 0x81 +#define SRSHARP1_SATPRT_LMT_RGB1 (SRSHARP1_OFFSET + SHARP_SATPRT_LMT_RGB1 ) // 0x82 +#define SRSHARP1_SATPRT_LMT_RGB2 (SRSHARP1_OFFSET + SHARP_SATPRT_LMT_RGB2 ) // 0x83 +#define SRSHARP1_SHARP_GATE_CLK_CTRL_0 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_0 ) // 0x84 +#define SRSHARP1_SHARP_GATE_CLK_CTRL_1 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_1 ) // 0x85 +#define SRSHARP1_SHARP_GATE_CLK_CTRL_2 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_2 ) // 0x86 +#define SRSHARP1_SHARP_GATE_CLK_CTRL_3 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_3 ) // 0x87 +#define SRSHARP1_SHARP_DPS_CTRL (SRSHARP1_OFFSET + SHARP_DPS_CTRL ) // 0x88 +#define SRSHARP1_DNLP_00 (SRSHARP1_OFFSET + DNLP_00 ) // 0x90 // +#define SRSHARP1_DNLP_01 (SRSHARP1_OFFSET + DNLP_01 ) // 0x91 // +#define SRSHARP1_DNLP_02 (SRSHARP1_OFFSET + DNLP_02 ) // 0x92 // +#define SRSHARP1_DNLP_03 (SRSHARP1_OFFSET + DNLP_03 ) // 0x93 // +#define SRSHARP1_DNLP_04 (SRSHARP1_OFFSET + DNLP_04 ) // 0x94 // +#define SRSHARP1_DNLP_05 (SRSHARP1_OFFSET + DNLP_05 ) // 0x95 // +#define SRSHARP1_DNLP_06 (SRSHARP1_OFFSET + DNLP_06 ) // 0x96 // +#define SRSHARP1_DNLP_07 (SRSHARP1_OFFSET + DNLP_07 ) // 0x97 // +#define SRSHARP1_DNLP_08 (SRSHARP1_OFFSET + DNLP_08 ) // 0x98 // +#define SRSHARP1_DNLP_09 (SRSHARP1_OFFSET + DNLP_09 ) // 0x99 // +#define SRSHARP1_DNLP_10 (SRSHARP1_OFFSET + DNLP_10 ) // 0x9a // +#define SRSHARP1_DNLP_11 (SRSHARP1_OFFSET + DNLP_11 ) // 0x9b // +#define SRSHARP1_DNLP_12 (SRSHARP1_OFFSET + DNLP_12 ) // 0x9c // +#define SRSHARP1_DNLP_13 (SRSHARP1_OFFSET + DNLP_13 ) // 0x9d // +#define SRSHARP1_DNLP_14 (SRSHARP1_OFFSET + DNLP_14 ) // 0x9e // +#define SRSHARP1_DNLP_15 (SRSHARP1_OFFSET + DNLP_15 ) // 0x9f // +#define SRSHARP1_DNLP_16 (SRSHARP1_OFFSET + DNLP_16 ) // 0xa0 // +#define SRSHARP1_DNLP_17 (SRSHARP1_OFFSET + DNLP_17 ) // 0xa1 // +#define SRSHARP1_DNLP_18 (SRSHARP1_OFFSET + DNLP_18 ) // 0xa2 // +#define SRSHARP1_DNLP_19 (SRSHARP1_OFFSET + DNLP_19 ) // 0xa3 // +#define SRSHARP1_DNLP_20 (SRSHARP1_OFFSET + DNLP_20 ) // 0xa4 // +#define SRSHARP1_DNLP_21 (SRSHARP1_OFFSET + DNLP_21 ) // 0xa5 // +#define SRSHARP1_DNLP_22 (SRSHARP1_OFFSET + DNLP_22 ) // 0xa6 // +#define SRSHARP1_DNLP_23 (SRSHARP1_OFFSET + DNLP_23 ) // 0xa7 // +#define SRSHARP1_DNLP_24 (SRSHARP1_OFFSET + DNLP_24 ) // 0xa8 // +#define SRSHARP1_DNLP_25 (SRSHARP1_OFFSET + DNLP_25 ) // 0xa9 // +#define SRSHARP1_DNLP_26 (SRSHARP1_OFFSET + DNLP_26 ) // 0xaa // +#define SRSHARP1_DNLP_27 (SRSHARP1_OFFSET + DNLP_27 ) // 0xab // +#define SRSHARP1_DNLP_28 (SRSHARP1_OFFSET + DNLP_28 ) // 0xac // +#define SRSHARP1_DNLP_29 (SRSHARP1_OFFSET + DNLP_29 ) // 0xad // +#define SRSHARP1_DNLP_30 (SRSHARP1_OFFSET + DNLP_30 ) // 0xae // +#define SRSHARP1_DNLP_31 (SRSHARP1_OFFSET + DNLP_31 ) // 0xaf // +#define SRSHARP1_SHARP_SYNC_CTRL (SRSHARP1_OFFSET + SHARP_SYNC_CTRL ) // 0xb0 // +#define SRSHARP1_LC_INPUT_MUX (SRSHARP1_OFFSET + LC_INPUT_MUX ) // 0xb1 // +#define SRSHARP1_NR_GAU_YH_COEF02 (SRSHARP1_OFFSET + NR_GAU_YH_COEF02 ) // 0xb2 // +#define SRSHARP1_NR_GAU_YH_COEF34 (SRSHARP1_OFFSET + NR_GAU_YH_COEF34 ) // 0xb3 // +#define SRSHARP1_NR_GAU_YV_COEF1 (SRSHARP1_OFFSET + NR_GAU_YV_COEF1 ) // 0xb4 // +#define SRSHARP1_NR_GAU_CH_COEF02 (SRSHARP1_OFFSET + NR_GAU_CH_COEF02 ) // 0xb5 // +#define SRSHARP1_NR_GAU_CH_COEF34 (SRSHARP1_OFFSET + NR_GAU_CH_COEF34 ) // 0xb6 // +#define SRSHARP1_NR_GAU_CV_COEF1 (SRSHARP1_OFFSET + NR_GAU_CV_COEF1 ) // 0xb7 // +#define SRSHARP1_LC_TOP_CTRL (SRSHARP1_OFFSET + LC_TOP_CTRL ) // 0xc0 // +#define SRSHARP1_LC_HV_NUM (SRSHARP1_OFFSET + LC_HV_NUM ) // 0xc1 +#define SRSHARP1_LC_SAT_LUT_0_1 (SRSHARP1_OFFSET + LC_SAT_LUT_0_1 ) // 0xc2 +#define SRSHARP1_LC_SAT_LUT_2_3 (SRSHARP1_OFFSET + LC_SAT_LUT_2_3 ) // 0xc3 +#define SRSHARP1_LC_SAT_LUT_4_5 (SRSHARP1_OFFSET + LC_SAT_LUT_4_5 ) // 0xc4 +#define SRSHARP1_LC_SAT_LUT_6_7 (SRSHARP1_OFFSET + LC_SAT_LUT_6_7 ) // 0xc5 +#define SRSHARP1_LC_SAT_LUT_8_9 (SRSHARP1_OFFSET + LC_SAT_LUT_8_9 ) // 0xc6 +#define SRSHARP1_LC_SAT_LUT_10_11 (SRSHARP1_OFFSET + LC_SAT_LUT_10_11 ) // 0xc7 +#define SRSHARP1_LC_SAT_LUT_12_13 (SRSHARP1_OFFSET + LC_SAT_LUT_12_13 ) // 0xc8 +#define SRSHARP1_LC_SAT_LUT_14_15 (SRSHARP1_OFFSET + LC_SAT_LUT_14_15 ) // 0xc9 +#define SRSHARP1_LC_SAT_LUT_16_17 (SRSHARP1_OFFSET + LC_SAT_LUT_16_17 ) // 0xca +#define SRSHARP1_LC_SAT_LUT_18_19 (SRSHARP1_OFFSET + LC_SAT_LUT_18_19 ) // 0xcb +#define SRSHARP1_LC_SAT_LUT_20_21 (SRSHARP1_OFFSET + LC_SAT_LUT_20_21 ) // 0xcc +#define SRSHARP1_LC_SAT_LUT_22_23 (SRSHARP1_OFFSET + LC_SAT_LUT_22_23 ) // 0xcd +#define SRSHARP1_LC_SAT_LUT_24_25 (SRSHARP1_OFFSET + LC_SAT_LUT_24_25 ) // 0xce +#define SRSHARP1_LC_SAT_LUT_26_27 (SRSHARP1_OFFSET + LC_SAT_LUT_26_27 ) // 0xcf +#define SRSHARP1_LC_SAT_LUT_28_29 (SRSHARP1_OFFSET + LC_SAT_LUT_28_29 ) // 0xd0 +#define SRSHARP1_LC_SAT_LUT_30_31 (SRSHARP1_OFFSET + LC_SAT_LUT_30_31 ) // 0xd1 +#define SRSHARP1_LC_SAT_LUT_32_33 (SRSHARP1_OFFSET + LC_SAT_LUT_32_33 ) // 0xd2 +#define SRSHARP1_LC_SAT_LUT_34_35 (SRSHARP1_OFFSET + LC_SAT_LUT_34_35 ) // 0xd3 +#define SRSHARP1_LC_SAT_LUT_36_37 (SRSHARP1_OFFSET + LC_SAT_LUT_36_37 ) // 0xd4 +#define SRSHARP1_LC_SAT_LUT_38_39 (SRSHARP1_OFFSET + LC_SAT_LUT_38_39 ) // 0xd5 +#define SRSHARP1_LC_SAT_LUT_40_41 (SRSHARP1_OFFSET + LC_SAT_LUT_40_41 ) // 0xd6 +#define SRSHARP1_LC_SAT_LUT_42_43 (SRSHARP1_OFFSET + LC_SAT_LUT_42_43 ) // 0xd7 +#define SRSHARP1_LC_SAT_LUT_44_45 (SRSHARP1_OFFSET + LC_SAT_LUT_44_45 ) // 0xd8 +#define SRSHARP1_LC_SAT_LUT_46_47 (SRSHARP1_OFFSET + LC_SAT_LUT_46_47 ) // 0xd9 +#define SRSHARP1_LC_SAT_LUT_48_49 (SRSHARP1_OFFSET + LC_SAT_LUT_48_49 ) // 0xda +#define SRSHARP1_LC_SAT_LUT_50_51 (SRSHARP1_OFFSET + LC_SAT_LUT_50_51 ) // 0xdb +#define SRSHARP1_LC_SAT_LUT_52_53 (SRSHARP1_OFFSET + LC_SAT_LUT_52_53 ) // 0xdc +#define SRSHARP1_LC_SAT_LUT_54_55 (SRSHARP1_OFFSET + LC_SAT_LUT_54_55 ) // 0xdd +#define SRSHARP1_LC_SAT_LUT_56_57 (SRSHARP1_OFFSET + LC_SAT_LUT_56_57 ) // 0xde +#define SRSHARP1_LC_SAT_LUT_58_59 (SRSHARP1_OFFSET + LC_SAT_LUT_58_59 ) // 0xdf +#define SRSHARP1_LC_SAT_LUT_60_61 (SRSHARP1_OFFSET + LC_SAT_LUT_60_61 ) // 0xe0 +#define SRSHARP1_LC_SAT_LUT_62 (SRSHARP1_OFFSET + LC_SAT_LUT_62 ) // 0xe1 +#define SRSHARP1_LC_CURVE_BLK_HIDX_0_1 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_0_1 ) // 0xe2 +#define SRSHARP1_LC_CURVE_BLK_HIDX_2_3 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_2_3 ) // 0xe3 +#define SRSHARP1_LC_CURVE_BLK_HIDX_4_5 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_4_5 ) // 0xe4 +#define SRSHARP1_LC_CURVE_BLK_HIDX_6_7 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_6_7 ) // 0xe5 +#define SRSHARP1_LC_CURVE_BLK_HIDX_8_9 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_8_9 ) // 0xe6 +#define SRSHARP1_LC_CURVE_BLK_HIDX_10_11 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_10_11 ) // 0xe7 +#define SRSHARP1_LC_CURVE_BLK_HIDX_12 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_12 ) // 0xe8 +#define SRSHARP1_LC_CURVE_BLK_VIDX_0_1 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_0_1 ) // 0xe9 +#define SRSHARP1_LC_CURVE_BLK_VIDX_2_3 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_2_3 ) // 0xea +#define SRSHARP1_LC_CURVE_BLK_VIDX_4_5 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_4_5 ) // 0xeb +#define SRSHARP1_LC_CURVE_BLK_VIDX_6_7 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_6_7 ) // 0xec +#define SRSHARP1_LC_CURVE_BLK_VIDX_8 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_8 ) // 0xed +#define SRSHARP1_LC_YUV2RGB_MAT_0_1 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_0_1 ) // 0xee +#define SRSHARP1_LC_YUV2RGB_MAT_2_3 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_2_3 ) // 0xef +#define SRSHARP1_LC_YUV2RGB_MAT_4_5 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_4_5 ) // 0xf0 +#define SRSHARP1_LC_YUV2RGB_MAT_6_7 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_6_7 ) // 0xf1 +#define SRSHARP1_LC_YUV2RGB_MAT_8 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_8 ) // 0xf2 +#define SRSHARP1_LC_RGB2YUV_MAT_0_1 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_0_1 ) // 0xf3 +#define SRSHARP1_LC_RGB2YUV_MAT_2_3 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_2_3 ) // 0xf4 +#define SRSHARP1_LC_RGB2YUV_MAT_4_5 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_4_5 ) // 0xf5 +#define SRSHARP1_LC_RGB2YUV_MAT_6_7 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_6_7 ) // 0xf6 +#define SRSHARP1_LC_RGB2YUV_MAT_8 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_8 ) // 0xf7 +#define SRSHARP1_LC_YUV2RGB_OFST (SRSHARP1_OFFSET + LC_YUV2RGB_OFST ) // 0xf8 +#define SRSHARP1_LC_YUV2RGB_CLIP (SRSHARP1_OFFSET + LC_YUV2RGB_CLIP ) // 0xf9 +#define SRSHARP1_LC_RGB2YUV_OFST (SRSHARP1_OFFSET + LC_RGB2YUV_OFST ) // 0xfa +#define SRSHARP1_LC_RGB2YUV_CLIP (SRSHARP1_OFFSET + LC_RGB2YUV_CLIP ) // 0xfb +#define SRSHARP1_LC_MAP_RAM_CTRL (SRSHARP1_OFFSET + LC_MAP_RAM_CTRL ) // 0xfc +#define SRSHARP1_LC_MAP_RAM_ADDR (SRSHARP1_OFFSET + LC_MAP_RAM_ADDR ) // 0xfd +#define SRSHARP1_LC_MAP_RAM_DATA (SRSHARP1_OFFSET + LC_MAP_RAM_DATA ) // 0xfe + +#define SRSHARP1_FMETER_CTRL (SRSHARP1_OFFSET + SHARP_FMETER_CTRL ) // 0x89 +#define SRSHARP1_FMETER_WIN_HOR (SRSHARP1_OFFSET + SHARP_FMETER_WIN_HOR ) // 0x8a +#define SRSHARP1_FMETER_WIN_VER (SRSHARP1_OFFSET + SHARP_FMETER_WIN_VER ) // 0x8b +#define SRSHARP1_FMETER_CORING (SRSHARP1_OFFSET + SHARP_FMETER_CORING ) // 0x8c +#define SRSHARP1_FMETER_RATIO_H (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_H ) // 0x8d +#define SRSHARP1_FMETER_RATIO_V (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_V ) // 0x8e +#define SRSHARP1_FMETER_RATIO_D (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_D ) // 0x8f +#define SRSHARP1_RO_FMETER_HCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE0 ) // 0x46 +#define SRSHARP1_RO_FMETER_HCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE1 ) // 0x47 +#define SRSHARP1_RO_FMETER_HCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE2 ) // 0x48 +#define SRSHARP1_RO_FMETER_HCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE3 ) // 0x49 +#define SRSHARP1_RO_FMETER_VCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE0 ) // 0x4a +#define SRSHARP1_RO_FMETER_VCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE1 ) // 0x4b +#define SRSHARP1_RO_FMETER_VCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE2 ) // 0x4c +#define SRSHARP1_RO_FMETER_VCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE3 ) // 0x4d +#define SRSHARP1_RO_FMETER_PDCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE0 ) // 0x4e +#define SRSHARP1_RO_FMETER_PDCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE1 ) // 0x4f +#define SRSHARP1_RO_FMETER_PDCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE2 ) // 0x50 +#define SRSHARP1_RO_FMETER_PDCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE3 ) // 0x51 +#define SRSHARP1_RO_FMETER_NDCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE0 ) // 0x52 +#define SRSHARP1_RO_FMETER_NDCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE1 ) // 0x53 +#define SRSHARP1_RO_FMETER_NDCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE2 ) // 0x54 +#define SRSHARP1_RO_FMETER_NDCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE3 ) // 0x55 + + + +// synopsys translate_off +// synopsys translate_on +// +// Closing file: srsharp_regs.h +// +// ----------------------------------------------- +// REG_BASE: VPPE_VCBUS_BASE = 0x51 +// ----------------------------------------------- +// 8'h50/51/52/53 have used for srsharp_regs +// +// Reading file: srsharp_regs2.h +// +// synopsys translate_off +// synopsys translate_on +//SRSHARP0 8'h00 - 8'hff +//SRSHARP1 8'h100 - 8'1ff +#define SRSHARP0_OFFSET (0x000<<2) +#define SRSHARP1_OFFSET (0x200<<2) + +// +// Reading file: sharp_regs2.h +// +// synopsys translate_off +// synopsys translate_on +#define SR7_DRTLPF_EN ((0x5100 << 2) + 0xff000000) +//Bit 31:11, reserved +//Bit 10, reg_sr7_drtlpf_beta_en2 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0 +//Bit 9, reg_sr7_drtlpf_beta_en1 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0 +//Bit 8, reg_sr7_drtlpf_beta_en0 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0 +//Bit 7: 6, reserved +//Bit 5, reg_sr7_drtlpf_edge_en2 : enable of direction lpf based on edge strength. unsigned , default = 0 +//Bit 4, reg_sr7_drtlpf_edge_en1 : enable of direction lpf based on edge strength. unsigned , default = 0 +//Bit 3, reg_sr7_drtlpf_edge_en0 : enable of direction lpf based on edge strength. unsigned , default = 0 +//Bit 2, reg_sr7_drtlpf_sdfd_en2 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1 +//Bit 1, reg_sr7_drtlpf_sdfd_en1 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1 +//Bit 0, reg_sr7_drtlpf_sdfd_en0 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1 +#define SR7_DRTLPF_BETA ((0x5101 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:12, reg_sr7_drtlpf_beta3 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 0 +//Bit 11: 8, reg_sr7_drtlpf_beta2 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 4 +//Bit 7: 4, reg_sr7_drtlpf_beta1 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 8 +//Bit 3: 0, reg_sr7_drtlpf_beta0 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 15 +#define SR7_PKBLD_BETA ((0x5102 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:12, reg_sr7_pkdrtbld_beta3 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 0 +//Bit 11: 8, reg_sr7_pkdrtbld_beta2 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 4 +//Bit 7: 4, reg_sr7_pkdrtbld_beta1 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 8 +//Bit 3: 0, reg_sr7_pkdrtbld_beta0 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 15 +#define SR7_XLTIBLD_BETA ((0x5103 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:12, reg_sr7_xlti_dcbld_beta3 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 0 +//Bit 11: 8, reg_sr7_xlti_dcbld_beta2 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 4 +//Bit 7: 4, reg_sr7_xlti_dcbld_beta1 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 8 +//Bit 3: 0, reg_sr7_xlti_dcbld_beta0 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 15 +#define SR7_DRTLPF_EDGE0 ((0x5104 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_drtlpf_edge7 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 27:24, reg_sr7_drtlpf_edge6 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 23:20, reg_sr7_drtlpf_edge5 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 19:16, reg_sr7_drtlpf_edge4 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 15:12, reg_sr7_drtlpf_edge3 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 11: 8, reg_sr7_drtlpf_edge2 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 7: 4, reg_sr7_drtlpf_edge1 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 3: 0, reg_sr7_drtlpf_edge0 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +#define SR7_DRTLPF_EDGE1 ((0x5105 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_drtlpf_edge15 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 27:24, reg_sr7_drtlpf_edge14 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 23:20, reg_sr7_drtlpf_edge13 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 19:16, reg_sr7_drtlpf_edge12 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 15:12, reg_sr7_drtlpf_edge11 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 11: 8, reg_sr7_drtlpf_edge10 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 7: 4, reg_sr7_drtlpf_edge9 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +//Bit 3: 0, reg_sr7_drtlpf_edge8 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15 +#define SR7_DRTLPF_SDCOR0 ((0x5106 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_drtlpf_sdcor7 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 27:24, reg_sr7_drtlpf_sdcor6 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 23:20, reg_sr7_drtlpf_sdcor5 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 19:16, reg_sr7_drtlpf_sdcor4 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 15:12, reg_sr7_drtlpf_sdcor3 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 11: 8, reg_sr7_drtlpf_sdcor2 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 7: 4, reg_sr7_drtlpf_sdcor1 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 3: 0, reg_sr7_drtlpf_sdcor0 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +#define SR7_DRTLPF_SDCOR1 ((0x5107 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_drtlpf_sdcor15 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 27:24, reg_sr7_drtlpf_sdcor14 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 23:20, reg_sr7_drtlpf_sdcor13 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 19:16, reg_sr7_drtlpf_sdcor12 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 15:12, reg_sr7_drtlpf_sdcor11 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 11: 8, reg_sr7_drtlpf_sdcor10 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 7: 4, reg_sr7_drtlpf_sdcor9 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 3: 0, reg_sr7_drtlpf_sdcor8 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15 +#define SR7_CTIGAIN_SDCOR0 ((0x5108 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_ctigain_sdcor7 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 27:24, reg_sr7_ctigain_sdcor6 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 23:20, reg_sr7_ctigain_sdcor5 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 19:16, reg_sr7_ctigain_sdcor4 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 15:12, reg_sr7_ctigain_sdcor3 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 11: 8, reg_sr7_ctigain_sdcor2 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 7: 4, reg_sr7_ctigain_sdcor1 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 3: 0, reg_sr7_ctigain_sdcor0 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +#define SR7_CTIGAIN_SDCOR1 ((0x5109 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_ctigain_sdcor15 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 27:24, reg_sr7_ctigain_sdcor14 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 23:20, reg_sr7_ctigain_sdcor13 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 19:16, reg_sr7_ctigain_sdcor12 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 15:12, reg_sr7_ctigain_sdcor11 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 11: 8, reg_sr7_ctigain_sdcor10 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 7: 4, reg_sr7_ctigain_sdcor9 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 3: 0, reg_sr7_ctigain_sdcor8 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +#define SR7_LTIGAIN_SDCOR0 ((0x510a << 2) + 0xff000000) +//Bit 31:28, reg_sr7_ltigain_sdcor7 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 27:24, reg_sr7_ltigain_sdcor6 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 23:20, reg_sr7_ltigain_sdcor5 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 19:16, reg_sr7_ltigain_sdcor4 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 15:12, reg_sr7_ltigain_sdcor3 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 11: 8, reg_sr7_ltigain_sdcor2 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 7: 4, reg_sr7_ltigain_sdcor1 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 3: 0, reg_sr7_ltigain_sdcor0 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +#define SR7_LTIGAIN_SDCOR1 ((0x510b << 2) + 0xff000000) +//Bit 31:28, reg_sr7_ltigain_sdcor15 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 27:24, reg_sr7_ltigain_sdcor14 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 23:20, reg_sr7_ltigain_sdcor13 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 19:16, reg_sr7_ltigain_sdcor12 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 15:12, reg_sr7_ltigain_sdcor11 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 11: 8, reg_sr7_ltigain_sdcor10 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 7: 4, reg_sr7_ltigain_sdcor9 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +//Bit 3: 0, reg_sr7_ltigain_sdcor8 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15 +#define SR7_HLTIBPF_TAP0 ((0x510c << 2) + 0xff000000) +//Bit 31:24, reg_sr7_hlti_bpf_tap153 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0 +//Bit 23:16, reg_sr7_hlti_bpf_tap152 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -34 +//Bit 15: 8, reg_sr7_hlti_bpf_tap151 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -1 +//Bit 7: 0, reg_sr7_hlti_bpf_tap150 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 120 +#define SR7_HLTIBPF_TAP1 ((0x510d << 2) + 0xff000000) +//Bit 31:24, reg_sr7_hlti_bpf_tap157 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 2 +//Bit 23:16, reg_sr7_hlti_bpf_tap156 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -7 +//Bit 15: 8, reg_sr7_hlti_bpf_tap155 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 1 +//Bit 7: 0, reg_sr7_hlti_bpf_tap154 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -21 +#define SR7_HCTIBPF_TAP0 ((0x510e << 2) + 0xff000000) +//Bit 31:24, reg_sr7_hcti_bpf_tap153 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0 +//Bit 23:16, reg_sr7_hcti_bpf_tap152 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -34 +//Bit 15: 8, reg_sr7_hcti_bpf_tap151 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -1 +//Bit 7: 0, reg_sr7_hcti_bpf_tap150 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 120 +#define SR7_HCTIBPF_TAP1 ((0x510f << 2) + 0xff000000) +//Bit 31:24, reg_sr7_hcti_bpf_tap157 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 2 +//Bit 23:16, reg_sr7_hcti_bpf_tap156 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -7 +//Bit 15: 8, reg_sr7_hcti_bpf_tap155 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 1 +//Bit 7: 0, reg_sr7_hcti_bpf_tap154 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -21 +#define SR7_PKLONGBPF_HTAP0 ((0x5110 << 2) + 0xff000000) +//Bit 31:24, reg_sr7_pk_long_bpf_hztap153 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -24 +//Bit 23:16, reg_sr7_pk_long_bpf_hztap152 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -19 +//Bit 15: 8, reg_sr7_pk_long_bpf_hztap151 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 31 +//Bit 7: 0, reg_sr7_pk_long_bpf_hztap150 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 66 +#define SR7_PKLONGBPF_HTAP1 ((0x5111 << 2) + 0xff000000) +//Bit 31:24, reg_sr7_pk_long_bpf_hztap157 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -6 +//Bit 23:16, reg_sr7_pk_long_bpf_hztap156 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -10 +//Bit 15: 8, reg_sr7_pk_long_bpf_hztap155 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -1 +//Bit 7: 0, reg_sr7_pk_long_bpf_hztap154 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -4 +#define SR7_PKLONGHPF_HTAP0 ((0x5112 << 2) + 0xff000000) +//Bit 31:24, reg_sr7_pk_long_hpf_hztap153 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 27 +//Bit 23:16, reg_sr7_pk_long_hpf_hztap152 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -15 +//Bit 15: 8, reg_sr7_pk_long_hpf_hztap151 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -32 +//Bit 7: 0, reg_sr7_pk_long_hpf_hztap150 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 58 +#define SR7_PKLONGHPF_HTAP1 ((0x5113 << 2) + 0xff000000) +//Bit 31:24, reg_sr7_pk_long_hpf_hztap157 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 8 +//Bit 23:16, reg_sr7_pk_long_hpf_hztap156 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -6 +//Bit 15: 8, reg_sr7_pk_long_hpf_hztap155 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -1 +//Bit 7: 0, reg_sr7_pk_long_hpf_hztap154 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -10 +#define SR7_VLTIBPF_TAP0 ((0x5114 << 2) + 0xff000000) +//Bit 31:24, reg_sr7_vlti_bpf_tap093 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0 +//Bit 23:16, reg_sr7_vlti_bpf_tap092 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -41 +//Bit 15: 8, reg_sr7_vlti_bpf_tap091 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0 +//Bit 7: 0, reg_sr7_vlti_bpf_tap090 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 126 +#define SR7_VLTIBPF_TAP1 ((0x5115 << 2) + 0xff000000) +//Bit 31: 8, reserved +//Bit 7: 0, reg_sr7_vlti_bpf_tap094 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -22 +#define SR7_VCTIBPF_TAP0 ((0x5116 << 2) + 0xff000000) +//Bit 31:24, reg_sr7_vcti_bpf_tap093 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0 +//Bit 23:16, reg_sr7_vcti_bpf_tap092 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -41 +//Bit 15: 8, reg_sr7_vcti_bpf_tap091 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0 +//Bit 7: 0, reg_sr7_vcti_bpf_tap090 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 126 +#define SR7_VCTIBPF_TAP1 ((0x5117 << 2) + 0xff000000) +//Bit 31: 8, reserved +//Bit 7: 0, reg_sr7_vcti_bpf_tap094 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -22 +#define SR7_PKLONGBPF_VTAP0 ((0x5118 << 2) + 0xff000000) +//Bit 31:24, reg_sr7_pk_long_bpf_vdtap093 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -32 +//Bit 23:16, reg_sr7_pk_long_bpf_vdtap092 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -28 +//Bit 15: 8, reg_sr7_pk_long_bpf_vdtap091 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 30 +//Bit 7: 0, reg_sr7_pk_long_bpf_vdtap090 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 68 +#define SR7_PKLONGBPF_VTAP1 ((0x5119 << 2) + 0xff000000) +//Bit 31: 8, reserved +//Bit 7: 0, reg_sr7_pk_long_bpf_vdtap094 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -4 +#define SR7_PKLONGHPF_VTAP0 ((0x511a << 2) + 0xff000000) +//Bit 31:24, reg_sr7_pk_long_hpf_vdtap093 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 30 +//Bit 23:16, reg_sr7_pk_long_hpf_vdtap092 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -28 +//Bit 15: 8, reg_sr7_pk_long_hpf_vdtap091 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -31 +//Bit 7: 0, reg_sr7_pk_long_hpf_vdtap090 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 68 +#define SR7_PKLONGHPF_VTAP1 ((0x511b << 2) + 0xff000000) +//Bit 31: 8, reserved +//Bit 7: 0, reg_sr7_pk_long_hpf_vdtap094 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -5 +#define SR7_CIRBPLONG_ALP ((0x511c << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:12, reg_sr7_cirbp_long_alpha3 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15 +//Bit 11: 8, reg_sr7_cirbp_long_alpha2 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15 +//Bit 7: 4, reg_sr7_cirbp_long_alpha1 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15 +//Bit 3: 0, reg_sr7_cirbp_long_alpha0 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15 +#define SR7_CIRHPLONG_ALP ((0x511d << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:12, reg_sr7_cirhp_long_alpha3 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15 +//Bit 11: 8, reg_sr7_cirhp_long_alpha2 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15 +//Bit 7: 4, reg_sr7_cirhp_long_alpha1 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15 +//Bit 3: 0, reg_sr7_cirhp_long_alpha0 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15 +#define SR7_DRTBPLONG_ALP ((0x511e << 2) + 0xff000000) +//Bit 31:28, reg_sr7_drtbp_long_alpha7 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 27:24, reg_sr7_drtbp_long_alpha6 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 23:20, reg_sr7_drtbp_long_alpha5 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 19:16, reg_sr7_drtbp_long_alpha4 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 15:12, reg_sr7_drtbp_long_alpha3 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 11: 8, reg_sr7_drtbp_long_alpha2 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 7: 4, reg_sr7_drtbp_long_alpha1 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 3: 0, reg_sr7_drtbp_long_alpha0 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +#define SR7_DRTHPLONG_ALP ((0x511f << 2) + 0xff000000) +//Bit 31:28, reg_sr7_drthp_long_alpha7 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 27:24, reg_sr7_drthp_long_alpha6 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 23:20, reg_sr7_drthp_long_alpha5 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 19:16, reg_sr7_drthp_long_alpha4 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 15:12, reg_sr7_drthp_long_alpha3 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 11: 8, reg_sr7_drthp_long_alpha2 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 7: 4, reg_sr7_drthp_long_alpha1 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +//Bit 3: 0, reg_sr7_drthp_long_alpha0 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15 +#define SR7_PKMINMAXCIR_BLD_LUT2D0 ((0x5120 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d7 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0 +//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d6 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0 +//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d5 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d4 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d3 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d2 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d1 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d0 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +#define SR7_PKMINMAXCIR_BLD_LUT2D1 ((0x5121 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d15 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d14 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0 +//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d13 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d12 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d11 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d10 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d9 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d8 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +#define SR7_PKMINMAXCIR_BLD_LUT2D2 ((0x5122 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d23 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6 +//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d22 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10 +//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d21 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d20 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d19 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d18 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d17 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d16 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12 +#define SR7_PKMINMAXCIR_BLD_LUT2D3 ((0x5123 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d31 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 14 +//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d30 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d29 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d28 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 8 +//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d27 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d26 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d25 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d24 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +#define SR7_PKMINMAXCIR_BLD_LUT2D4 ((0x5124 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d35 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d34 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d33 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d32 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12 +#define SR7_PKMINMAXLPF_BLD_LUT2D0 ((0x5125 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d7 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0 +//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d6 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0 +//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d5 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d4 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d3 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d2 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d1 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d0 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +#define SR7_PKMINMAXLPF_BLD_LUT2D1 ((0x5126 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d15 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d14 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0 +//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d13 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d12 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d11 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d10 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d9 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d8 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +#define SR7_PKMINMAXLPF_BLD_LUT2D2 ((0x5127 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d23 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6 +//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d22 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10 +//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d21 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d20 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d19 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d18 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d17 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d16 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12 +#define SR7_PKMINMAXLPF_BLD_LUT2D3 ((0x5128 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d31 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 14 +//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d30 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d29 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d28 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 8 +//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d27 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d26 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d25 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d24 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4 +#define SR7_PKMINMAXLPF_BLD_LUT2D4 ((0x5129 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d35 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d34 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d33 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15 +//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d32 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12 +#define SR7_PKDRT_BLD_EN ((0x512a << 2) + 0xff000000) +//Bit 31: 1, reserved +//Bit 0, reg_sr7_pkdrtbld_beta_en : enable of direction ambiguity protection for drt and cir blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0 +#define SR7_DRTDIF_TH ((0x512b << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15: 8, reg_sr7_drtdif_min2sad_th1 : for min2_sad threshold for ambiguilty ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;. unsigned , default = 128 +//Bit 7: 0, reg_sr7_drtdif_min2sad_th0 : for min2_sad threshold for ambiguilty ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;. unsigned , default = 128 +#define SR7_TIBLD_PRT ((0x512c << 2) + 0xff000000) +//Bit 31:14, reserved +//Bit 13, reg_sr7_hlti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1 +//Bit 12, reg_sr7_vlti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1 +//Bit 11: 8, reg_sr7_xcti_dcbld_beta1 : beta for denoise and org dc blend base on the x=cal_drt_dif4(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 0 +//Bit 7: 4, reg_sr7_xcti_dcbld_beta0 : beta for denoise and org dc blend base on the x=cal_drt_dif4(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 15 +//Bit 3, reg_sr7_hcti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1 +//Bit 2, reg_sr7_vcti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1 +//Bit 1, reg_sr7_hcti_dcbld_use_ybeta : enable to use beta from hlti, 0, use c-beta, 1, use y-beta. unsigned , default = 0 +//Bit 0, reg_sr7_vcti_dcbld_use_ybeta : enable to use beta from vlti, 0, use c-beta, 1, use y-beta. unsigned , default = 0 +#define SR7_HTI_OPT_FORCE ((0x512d << 2) + 0xff000000) +//Bit 31: 6, reserved +//Bit 5, reg_sr7_diag_force_hti1 : force hti for diagonal edges luma/chroma, 0: diagonal use vti, 1: diagonal use hti, default=1. unsigned , default = 1 +//Bit 4, reg_sr7_diag_force_hti0 : force hti for diagonal edges luma/chroma, 0: diagonal use vti, 1: diagonal use hti, default=1. unsigned , default = 1 +//Bit 3, reg_sr7_horz_force_vti1 : force vti for horizontal edges luma/chroma, 0: bias hti, 1: horizontal edge force 100% vti, default=1. unsigned , default = 1 +//Bit 2, reg_sr7_horz_force_vti0 : force vti for horizontal edges luma/chroma, 0: bias hti, 1: horizontal edge force 100% vti, default=1. unsigned , default = 1 +//Bit 1, reg_sr7_alph_force_hvsad1 : alpha = minsad*64/maxsad, force minsad=sad_h, maxsad=sad_v for alpha calculation, [0]for luma, [1] for chroma. if sad_h>sad_v alpha will be large, default=1. unsigned , default = 1 +//Bit 0, reg_sr7_alph_force_hvsad0 : alpha = minsad*64/maxsad, force minsad=sad_h, maxsad=sad_v for alpha calculation, [0]for luma, [1] for chroma. if sad_h>sad_v alpha will be large, default=1. unsigned , default = 1 +#define SR7_HVTI_FINALGAIN ((0x512e << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, reg_sr7_hvti_finalgain1 : final gain for HVTI boost, for easier level tunning for application, normalized to 256 as 1.0 default = 256. unsigned , default = 256 +//Bit 15:12, reserved +//Bit 11: 0, reg_sr7_hvti_finalgain0 : final gain for HVTI boost, for easier level tunning for application, normalized to 256 as 1.0 default = 256. unsigned , default = 256 +#define SR7_TIOS_SDRATIO ((0x512f << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:24, reg_sr7_hti_osmargin_sdratio1 : ratio for HTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3 +//Bit 23:22, reserved +//Bit 21:16, reg_sr7_hti_osmargin_sdratio0 : ratio for HTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3 +//Bit 15:14, reserved +//Bit 13: 8, reg_sr7_vti_osmargin_sdratio1 : ratio for VTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3 +//Bit 7: 6, reserved +//Bit 5: 0, reg_sr7_vti_osmargin_sdratio0 : ratio for VTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3 +#define SR7_XTI_SDFDEN ((0x5130 << 2) + 0xff000000) +//Bit 31: 2, reserved +//Bit 1, reg_sr7_xtigain_sdfd_en1 : adaptive gamma for cti boost gain enable.[0]for luma, [1] for chroma. 0: not enable, 1:enable, default = 1. unsigned , default = 1 +//Bit 0, reg_sr7_xtigain_sdfd_en0 : adaptive gamma for cti boost gain enable.[0]for luma, [1] for chroma. 0: not enable, 1:enable, default = 1. unsigned , default = 1 +#define SR7_FDSD_PARAM ((0x5131 << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25, reg_fdsd_vlpf_en : use vertical [1 2 1] lpf filter for the fd and sd derivativecalculations. unsigned , default = 1 +//Bit 24, reg_fdsd_hlpf_en : use horizontal [1 2 1] lpf filter for the fd and sd derivativecalculations. unsigned , default = 1 +//Bit 23:20, reg_sd_coring_th1 : coring to SD'= MAX(SD - FD*ratio - coring,0); default = 0. unsigned , default = 0 +//Bit 19:16, reg_sd_coring_th0 : coring to SD'= MAX(SD - FD*ratio - coring,0); default = 0. unsigned , default = 0 +//Bit 15:14, reserved +//Bit 13: 8, reg_sd_coring_ratio2fd1 : ratio to FD for adaptive coring to SD'= MAX(SD - FD*ratio - coring,0); normalized 64 as 1.0 default = 4. unsigned , default = 4 +//Bit 7: 6, reserved +//Bit 5: 0, reg_sd_coring_ratio2fd0 : ratio to FD for adaptive coring to SD'= MAX(SD - FD*ratio - coring,0); normalized 64 as 1.0 default = 4. unsigned , default = 4 +#define SR7_TI_BPF_EN ((0x5132 << 2) + 0xff000000) +//Bit 31: 4, reserved +//Bit 3, reg_sr7_hlti_bpf_en : enable of tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. unsigned , default = 1 +//Bit 2, reg_sr7_hcti_bpf_en : enable of tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. unsigned , default = 1 +//Bit 1, reg_sr7_vlti_bpf_en : enable of tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0, mainly for 2x2 UP case. unsigned , default = 1 +//Bit 0, reg_sr7_vcti_bpf_en : enable of tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0, mainly for 2x2 UP case. unsigned , default = 1 +#define SR7_PKLONG_PF_EN ((0x5133 << 2) + 0xff000000) +//Bit 31: 2, reserved +//Bit 1, reg_sr7_pk_long_bpf_en : enable of long BPF for peaking only store half of the filter normalized to 258 as 1.0. unsigned , default = 1 +//Bit 0, reg_sr7_pk_long_hpf_en : enable of long HPF for peaking only store half of the filter normalized to 258 as 1.0. unsigned , default = 1 +#define SR7_PKLONG_PF_GAIN ((0x5134 << 2) + 0xff000000) +//Bit 31:24, reg_sr7_pk_long_bpf_hzgain : gain to long horizontal BPF for peaking, normalized to 64 as 1.0. unsigned , default = 64 +//Bit 23:16, reg_sr7_pk_long_bpf_vdgain : gain to long vertical and diagonal BPF for peaking, normalized to 64 as 1.0. unsigned , default = 64 +//Bit 15: 8, reg_sr7_pk_long_hpf_hzgain : gain to long horizontal HPF for peaking, normalized to 64 as 1.0. unsigned , default = 64 +//Bit 7: 0, reg_sr7_pk_long_hpf_vdgain : gain to long vertical and diagonal HPF for peaking, normalized to 64 as 1.0. unsigned , default = 64 +#define SR7_PKMINMAX_BLD ((0x5135 << 2) + 0xff000000) +//Bit 31: 4, reserved +//Bit 3, reg_sr7_pk_mimaxerr2_cirbld_on_bp : enable to use adaptive blender of drtBP vs cirBP alpha2, the larger of cell, the more cirPK results, 0: alp2=lut2d(minerr, maxerr),1:alp2=min_err/maxerr,default = 1. unsigned , default = 1 +//Bit 2, reg_sr7_pk_mimaxerr2_cirbld_on_hp : enable to use adaptive blender of drtHP vs cirHP alpha2, the larger of cell, the more cirPK results, 0: alp2=lut2d(minerr, maxerr),1:alp2=min_err/maxerr,default = 1. unsigned , default = 1 +//Bit 1, reg_sr7_pk_mimaxerr2_lpfbld_on_bp : enable to use adaptive blender of BP result lpf along edge based on the mimaxsad relationship, default = 1. unsigned , default = 1 +//Bit 0, reg_sr7_pk_mimaxerr2_lpfbld_on_hp : enable to use adaptive blender of HP result lpf along edge based on the mimaxsad relationship, default = 1. unsigned , default = 1 +#define SR7_TI_CONMAXERR_GAIN ((0x5136 << 2) + 0xff000000) +//Bit 31:16, reserved +//Bit 15:12, reg_sr7_hti_conmaxerr_gain1 : con=max(con, maxerr) for the horizontal transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8 +//Bit 11: 8, reg_sr7_hti_conmaxerr_gain0 : con=max(con, maxerr) for the horizontal transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8 +//Bit 7: 4, reg_sr7_vti_conmaxerr_gain1 : con=max(con, maxerr) for the vertical transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8 +//Bit 3: 0, reg_sr7_vti_conmaxerr_gain0 : con=max(con, maxerr) for the vertical transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8 +#define SR7_CC_PK_ADJ ((0x5137 << 2) + 0xff000000) +//Bit 31:25, reserved +//Bit 24, reg_sr7_cc_enable : color compensation enable, 0: no CC, 1: with CC, default = 1. unsigned , default = 1 +//Bit 23:22, reserved +//Bit 21:20, reg_sr7_cc_yinp_sel : color compensation input luma selection, 0: org_y; 1: gau_y ; 2:gauadp_y; 3:edgeadp_y (same as dnlp input sel), default= 0. unsigned , default = 0 +//Bit 19:18, reg_sr7_cc_ydlt_sel : color compensation output luma selection, 0: peaking+lti output; 1: dnlp output; 2/3: peaking+lti+dnlp, default = 2. unsigned , default = 2 +//Bit 17:16, reg_sr7_cc_sat_norm : normalization of lut cell to saturation. 0: norm to 8 as 1.0, sat[0:23/8]; 1: norm to 16 as 1.0, sat[1/16:31/16]; 2: norm to 32 as 1.0, sat[17/32:47/32]; 3:norm to 64 as 1.0, sat[49/64:79/64]. unsigned , default = 1 +//Bit 15: 8, reg_sr7_cc_ydlt_pscl : prescale to the y-delta (if >0) before feeding to y-lumadlt, normalized 64 as 1.0. default = 64.. unsigned , default = 64 +//Bit 7: 0, reg_sr7_cc_ydlt_nscl : prescale to the y-delta (if <0) before feeding to y-lumadlt, normalized 64 as 1.0. default = 64.. unsigned , default = 64 +#define SR7_CC_LUT0 ((0x5138 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_cc_lut003 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0 +//Bit 27:24, reg_sr7_cc_lut002 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0 +//Bit 23:20, reg_sr7_cc_lut001 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0 +//Bit 19:16, reg_sr7_cc_lut000 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0 +//Bit 15:12, reg_sr7_cc_lut103 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 8 +//Bit 11: 8, reg_sr7_cc_lut102 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 4 +//Bit 7: 4, reg_sr7_cc_lut101 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 2 +//Bit 3: 0, reg_sr7_cc_lut100 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 1 +#define SR7_CC_LUT1 ((0x5139 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:24, reg_sr7_cc_lut202 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 12 +//Bit 23:20, reg_sr7_cc_lut201 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 8 +//Bit 19:16, reg_sr7_cc_lut200 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 4 +//Bit 15:12, reserved +//Bit 11: 8, reg_sr7_cc_lut302 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 15 +//Bit 7: 4, reg_sr7_cc_lut301 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 10 +//Bit 3: 0, reg_sr7_cc_lut300 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 5 +#define SR7_CC_LUT2 ((0x513a << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:20, reg_sr7_cc_lut401 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 15 +//Bit 19:16, reg_sr7_cc_lut400 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 8 +//Bit 15:12, reg_sr7_cc_lut501 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=5/8 dft={6,13}. unsigned , default = 13 +//Bit 11: 8, reg_sr7_cc_lut500 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=5/8 dft={6,13}. unsigned , default = 6 +//Bit 7: 4, reg_sr7_cc_lut600 : valid for y-lumadlt= 1/4, ; of x-lumainput=6/8 dft={5}. unsigned , default = 5 +//Bit 3: 0, reg_sr7_cc_lut700 : valid for y-lumadlt= 1/4, ; of x-lumainput=7/8 dft={4}. unsigned , default = 4 +#define SR7_CC_LUT3 ((0x513b << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:20, reg_sr7_cc_lut710 : valid for y-lumadlt= -1/4, ; of x-lumainput=1/8 dft={4}. unsigned , default = 4 +//Bit 19:16, reg_sr7_cc_lut610 : valid for y-lumadlt= -1/4, ; of x-lumainput=2/8 dft={5}. unsigned , default = 5 +//Bit 15:12, reg_sr7_cc_lut511 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=3/8 dft={6,13}. unsigned , default = 13 +//Bit 11: 8, reg_sr7_cc_lut510 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=3/8 dft={6,13}. unsigned , default = 6 +//Bit 7: 4, reg_sr7_cc_lut411 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 15 +//Bit 3: 0, reg_sr7_cc_lut410 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 8 +#define SR7_CC_LUT4 ((0x513c << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:20, reg_sr7_cc_lut312 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 15 +//Bit 19:16, reg_sr7_cc_lut311 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 10 +//Bit 15:12, reg_sr7_cc_lut310 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 5 +//Bit 11: 8, reg_sr7_cc_lut212 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 12 +//Bit 7: 4, reg_sr7_cc_lut211 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 8 +//Bit 3: 0, reg_sr7_cc_lut210 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 4 +#define SR7_CC_LUT5 ((0x513d << 2) + 0xff000000) +//Bit 31:28, reg_sr7_cc_lut113 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 8 +//Bit 27:24, reg_sr7_cc_lut112 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 4 +//Bit 23:20, reg_sr7_cc_lut111 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 2 +//Bit 19:16, reg_sr7_cc_lut110 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 1 +//Bit 15:12, reg_sr7_cc_lut013 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0 +//Bit 11: 8, reg_sr7_cc_lut012 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0 +//Bit 7: 4, reg_sr7_cc_lut011 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0 +//Bit 3: 0, reg_sr7_cc_lut010 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0 +#define SR7_GRAPHIC_CTRL ((0x513e << 2) + 0xff000000) +//Bit 31:11, reserved +//Bit 10, reg_sr7_grph_en : enable graphic statistic . unsigned , default = 1 +//Bit 9, reg_sr7_grph_hflt : horizontal filter, 0: [0 1 -1], 1: [-1 2 -1]. unsigned , default = 1 +//Bit 8, reg_sr7_grph_vflt : vertical filter, 0: [0 1 -1], 1: [-1 2 -1]. unsigned , default = 1 +//Bit 7: 0, reg_sr7_grph_dif_cor : coring for dif while count for graphic. unsigned , default = 0 +#define SR7_GRAPHIC_THD_GAIN ((0x513f << 2) + 0xff000000) +//Bit 31:24, reg_sr7_grph_flt_thd : flat threshold for dif while count for graphic. unsigned , default = 2 +//Bit 23:16, reg_sr7_grph_dtl_thd : detail threshold for dif while count for graphic. unsigned , default = 40 +//Bit 15: 8, reg_sr7_grph_hgain : horizontal gain for fast squart of hp. unsigned , default = 32 +//Bit 7: 0, reg_sr7_grph_vgain : vertical gain for fast squart of hp. unsigned , default = 32 +#define SR7_RO_GRAPHIC_FLT_CNT ((0x5140 << 2) + 0xff000000) +//Bit 31: 0, ro_sr7_grph_flt_cnt : flat count numbers for graphic. unsigned , default = 0 +#define SR7_RO_GRAPHIC_DTL_CNT ((0x5141 << 2) + 0xff000000) +//Bit 31: 0, ro_sr7_grph_dtl_cnt : detail count numbers for graphic. unsigned , default = 0 +#define SR7_CLR_PRT_PARAM ((0x5142 << 2) + 0xff000000) +//Bit 31:18, reserved +//Bit 17:16, reg_sr7_clr_prct_inpsel : input UV selection for color protection, 0: org; 1: NRout; 2: CTIout; 3: (NR+TIout)/2. unsigned , default = 3 +//Bit 15: 8, reg_sr7_clr_prct_dnlp_gain : gain to de-boost of dnlp_dlt base on color region, norm to 64 as 1.0. set to 0 as disable. unsigned , default = 64 +//Bit 7: 0, reg_sr7_clr_prct_peak_gain : gain to de-boost of peak_dlt base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64 +#define SR7_CLR_PRT_LC_GAIN ((0x5143 << 2) + 0xff000000) +//Bit 31:24, reserved +//Bit 23:16, reg_sr7_clr_prct_lc_gain2 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64 +//Bit 15: 8, reg_sr7_clr_prct_lc_gain1 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64 +//Bit 7: 0, reg_sr7_clr_prct_lc_gain0 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64 +#define SR7_CLR_PRT_LUT0 ((0x5144 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut7 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut6 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut5 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut4 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut3 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut2 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut1 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut0 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT1 ((0x5145 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut15 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut14 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut13 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut12 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut11 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut10 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut9 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut8 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT2 ((0x5146 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut23 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut22 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut21 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut20 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut19 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut18 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut17 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut16 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT3 ((0x5147 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut31 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut30 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut29 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut28 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut27 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut26 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut25 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut24 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT4 ((0x5148 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut39 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut38 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut37 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut36 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut35 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut34 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut33 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut32 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT5 ((0x5149 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut47 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut46 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut45 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut44 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut43 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut42 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut41 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut40 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT6 ((0x514a << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut55 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut54 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut53 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut52 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut51 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut50 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut49 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut48 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT7 ((0x514b << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut63 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut62 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut61 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut60 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut59 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut58 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut57 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut56 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT8 ((0x514c << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut71 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut70 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut69 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut68 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut67 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut66 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut65 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut64 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT9 ((0x514d << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut79 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut78 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut77 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut76 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut75 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut74 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut73 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut72 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT10 ((0x514e << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut87 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut86 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut85 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut84 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut83 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut82 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut81 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut80 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT11 ((0x514f << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut95 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut94 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut93 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut92 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut91 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut90 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut89 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut88 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT12 ((0x5150 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut103 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut102 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut101 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut100 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut99 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut98 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut97 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut96 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT13 ((0x5151 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut111 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut110 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut109 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut108 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut107 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut106 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut105 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut104 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT14 ((0x5152 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut119 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut118 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut117 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut116 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut115 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut114 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut113 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut112 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT15 ((0x5153 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut127 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut126 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut125 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut124 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut123 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut122 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut121 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut120 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT16 ((0x5154 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut135 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut134 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut133 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut132 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut131 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut130 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut129 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut128 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT17 ((0x5155 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut143 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut142 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut141 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut140 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut139 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut138 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut137 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut136 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT18 ((0x5156 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut151 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 27:24, reg_sr7_clr_prct_lut150 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 23:20, reg_sr7_clr_prct_lut149 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 19:16, reg_sr7_clr_prct_lut148 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut147 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut146 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut145 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut144 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT19 ((0x5157 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut159 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut158 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut157 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut156 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut155 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut154 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut153 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 3: 0, reg_sr7_clr_prct_lut152 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +#define SR7_CLR_PRT_LUT20 ((0x5158 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut167 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 27:24, reg_sr7_clr_prct_lut166 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 23:20, reg_sr7_clr_prct_lut165 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 19:16, reg_sr7_clr_prct_lut164 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut163 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut162 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut161 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut160 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT21 ((0x5159 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut175 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut174 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut173 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut172 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut171 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut170 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut169 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 3: 0, reg_sr7_clr_prct_lut168 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +#define SR7_CLR_PRT_LUT22 ((0x515a << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut183 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 27:24, reg_sr7_clr_prct_lut182 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 23:20, reg_sr7_clr_prct_lut181 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 19:16, reg_sr7_clr_prct_lut180 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut179 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut178 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut177 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut176 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT23 ((0x515b << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut191 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut190 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut189 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut188 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut187 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut186 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut185 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 3: 0, reg_sr7_clr_prct_lut184 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +#define SR7_CLR_PRT_LUT24 ((0x515c << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut199 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 27:24, reg_sr7_clr_prct_lut198 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 23:20, reg_sr7_clr_prct_lut197 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 19:16, reg_sr7_clr_prct_lut196 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut195 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut194 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut193 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut192 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT25 ((0x515d << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut207 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut206 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut205 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut204 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut203 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut202 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut201 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 3: 0, reg_sr7_clr_prct_lut200 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +#define SR7_CLR_PRT_LUT26 ((0x515e << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut215 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 27:24, reg_sr7_clr_prct_lut214 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 23:20, reg_sr7_clr_prct_lut213 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 19:16, reg_sr7_clr_prct_lut212 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut211 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut210 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut209 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut208 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT27 ((0x515f << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut223 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut222 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut221 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut220 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut219 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut218 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut217 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 3: 0, reg_sr7_clr_prct_lut216 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +#define SR7_CLR_PRT_LUT28 ((0x5160 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut231 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 27:24, reg_sr7_clr_prct_lut230 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 23:20, reg_sr7_clr_prct_lut229 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 19:16, reg_sr7_clr_prct_lut228 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut227 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut226 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut225 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut224 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT29 ((0x5161 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut239 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut238 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut237 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut236 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut235 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut234 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut233 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +//Bit 3: 0, reg_sr7_clr_prct_lut232 : color protection lut, 16 is normalized to 1. unsigned , default = 15 +#define SR7_CLR_PRT_LUT30 ((0x5162 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut247 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut246 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut245 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut244 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut243 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut242 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut241 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut240 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +#define SR7_CLR_PRT_LUT31 ((0x5163 << 2) + 0xff000000) +//Bit 31:28, reg_sr7_clr_prct_lut255 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 27:24, reg_sr7_clr_prct_lut254 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 23:20, reg_sr7_clr_prct_lut253 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 19:16, reg_sr7_clr_prct_lut252 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 15:12, reg_sr7_clr_prct_lut251 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 11: 8, reg_sr7_clr_prct_lut250 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 7: 4, reg_sr7_clr_prct_lut249 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +//Bit 3: 0, reg_sr7_clr_prct_lut248 : color protection lut, 16 is normalized to 1. unsigned , default = 0 +// synopsys translate_off +// synopsys translate_on +// +// Closing file: sharp_regs2.h +// + +#define SRSHARP0_SR7_DRTLPF_EN (SRSHARP0_OFFSET + SR7_DRTLPF_EN )// +#define SRSHARP0_SR7_DRTLPF_BETA (SRSHARP0_OFFSET + SR7_DRTLPF_BETA )// +#define SRSHARP0_SR7_PKBLD_BETA (SRSHARP0_OFFSET + SR7_PKBLD_BETA )// +#define SRSHARP0_SR7_XLTIBLD_BETA (SRSHARP0_OFFSET + SR7_XLTIBLD_BETA )// +#define SRSHARP0_SR7_DRTLPF_EDGE0 (SRSHARP0_OFFSET + SR7_DRTLPF_EDGE0 )// +#define SRSHARP0_SR7_DRTLPF_EDGE1 (SRSHARP0_OFFSET + SR7_DRTLPF_EDGE1 )// +#define SRSHARP0_SR7_DRTLPF_SDCOR0 (SRSHARP0_OFFSET + SR7_DRTLPF_SDCOR0 )// +#define SRSHARP0_SR7_DRTLPF_SDCOR1 (SRSHARP0_OFFSET + SR7_DRTLPF_SDCOR1 )// +#define SRSHARP0_SR7_CTIGAIN_SDCOR0 (SRSHARP0_OFFSET + SR7_CTIGAIN_SDCOR0 )// +#define SRSHARP0_SR7_CTIGAIN_SDCOR1 (SRSHARP0_OFFSET + SR7_CTIGAIN_SDCOR1 )// +#define SRSHARP0_SR7_LTIGAIN_SDCOR0 (SRSHARP0_OFFSET + SR7_LTIGAIN_SDCOR0 )// +#define SRSHARP0_SR7_LTIGAIN_SDCOR1 (SRSHARP0_OFFSET + SR7_LTIGAIN_SDCOR1 )// +#define SRSHARP0_SR7_HLTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_HLTIBPF_TAP0 )// +#define SRSHARP0_SR7_HLTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_HLTIBPF_TAP1 )// +#define SRSHARP0_SR7_HCTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_HCTIBPF_TAP0 )// +#define SRSHARP0_SR7_HCTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_HCTIBPF_TAP1 )// +#define SRSHARP0_SR7_PKLONGBPF_HTAP0 (SRSHARP0_OFFSET + SR7_PKLONGBPF_HTAP0 ) // +#define SRSHARP0_SR7_PKLONGBPF_HTAP1 (SRSHARP0_OFFSET + SR7_PKLONGBPF_HTAP1 ) // +#define SRSHARP0_SR7_PKLONGHPF_HTAP0 (SRSHARP0_OFFSET + SR7_PKLONGHPF_HTAP0 ) // +#define SRSHARP0_SR7_PKLONGHPF_HTAP1 (SRSHARP0_OFFSET + SR7_PKLONGHPF_HTAP1 ) // +#define SRSHARP0_SR7_VLTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_VLTIBPF_TAP0 ) // +#define SRSHARP0_SR7_VLTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_VLTIBPF_TAP1 ) // +#define SRSHARP0_SR7_VCTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_VCTIBPF_TAP0 ) // +#define SRSHARP0_SR7_VCTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_VCTIBPF_TAP1 ) // +#define SRSHARP0_SR7_PKLONGBPF_VTAP0 (SRSHARP0_OFFSET + SR7_PKLONGBPF_VTAP0 ) // +#define SRSHARP0_SR7_PKLONGBPF_VTAP1 (SRSHARP0_OFFSET + SR7_PKLONGBPF_VTAP1 ) // +#define SRSHARP0_SR7_PKLONGHPF_VTAP0 (SRSHARP0_OFFSET + SR7_PKLONGHPF_VTAP0 ) // +#define SRSHARP0_SR7_PKLONGHPF_VTAP1 (SRSHARP0_OFFSET + SR7_PKLONGHPF_VTAP1 ) // +#define SRSHARP0_SR7_CIRBPLONG_ALP (SRSHARP0_OFFSET + SR7_CIRBPLONG_ALP ) // +#define SRSHARP0_SR7_CIRHPLONG_ALP (SRSHARP0_OFFSET + SR7_CIRHPLONG_ALP ) // +#define SRSHARP0_SR7_DRTBPLONG_ALP (SRSHARP0_OFFSET + SR7_DRTBPLONG_ALP ) // +#define SRSHARP0_SR7_DRTHPLONG_ALP (SRSHARP0_OFFSET + SR7_DRTHPLONG_ALP ) // +#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D0 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D0) // +#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D1 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D1) // +#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D2 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D2) // +#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D3 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D3) // +#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D4 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D4) // +#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D0 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D0) // +#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D1 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D1) // +#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D2 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D2) // +#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D3 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D3) // +#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D4 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D4) // +#define SRSHARP0_SR7_PKDRT_BLD_EN (SRSHARP0_OFFSET + SR7_PKDRT_BLD_EN ) // +#define SRSHARP0_SR7_DRTDIF_TH (SRSHARP0_OFFSET + SR7_DRTDIF_TH ) // +#define SRSHARP0_SR7_TIBLD_PRT (SRSHARP0_OFFSET + SR7_TIBLD_PRT ) // +#define SRSHARP0_SR7_HTI_OPT_FORCE (SRSHARP0_OFFSET + SR7_HTI_OPT_FORCE ) // +#define SRSHARP0_SR7_HVTI_FINALGAIN (SRSHARP0_OFFSET + SR7_HVTI_FINALGAIN ) // +#define SRSHARP0_SR7_TIOS_SDRATIO (SRSHARP0_OFFSET + SR7_TIOS_SDRATIO ) // +#define SRSHARP0_SR7_XTI_SDFDEN (SRSHARP0_OFFSET + SR7_XTI_SDFDEN ) // +#define SRSHARP0_SR7_FDSD_PARAM (SRSHARP0_OFFSET + SR7_FDSD_PARAM ) // +#define SRSHARP0_SR7_TI_BPF_EN (SRSHARP0_OFFSET + SR7_TI_BPF_EN ) // +#define SRSHARP0_SR7_PKLONG_PF_EN (SRSHARP0_OFFSET + SR7_PKLONG_PF_EN ) // +#define SRSHARP0_SR7_PKLONG_PF_GAIN (SRSHARP0_OFFSET + SR7_PKLONG_PF_GAIN ) // +#define SRSHARP0_SR7_PKMINMAX_BLD (SRSHARP0_OFFSET + SR7_PKMINMAX_BLD ) // +#define SRSHARP0_SR7_TI_CONMAXERR_GAIN (SRSHARP0_OFFSET + SR7_TI_CONMAXERR_GAIN ) // +#define SRSHARP0_SR7_CC_PK_ADJ (SRSHARP0_OFFSET + SR7_CC_PK_ADJ ) // +#define SRSHARP0_SR7_CC_LUT0 (SRSHARP0_OFFSET + SR7_CC_LUT0 ) // +#define SRSHARP0_SR7_CC_LUT1 (SRSHARP0_OFFSET + SR7_CC_LUT1 ) // +#define SRSHARP0_SR7_CC_LUT2 (SRSHARP0_OFFSET + SR7_CC_LUT2 ) // +#define SRSHARP0_SR7_CC_LUT3 (SRSHARP0_OFFSET + SR7_CC_LUT3 ) // +#define SRSHARP0_SR7_CC_LUT4 (SRSHARP0_OFFSET + SR7_CC_LUT4 ) // +#define SRSHARP0_SR7_CC_LUT5 (SRSHARP0_OFFSET + SR7_CC_LUT5 ) // +#define SRSHARP0_SR7_GRAPHIC_CTRL (SRSHARP0_OFFSET + SR7_GRAPHIC_CTRL ) // +#define SRSHARP0_SR7_GRAPHIC_THD_GAIN (SRSHARP0_OFFSET + SR7_GRAPHIC_THD_GAIN ) // +#define SRSHARP0_SR7_RO_GRAPHIC_FLT_CNT (SRSHARP0_OFFSET + SR7_RO_GRAPHIC_FLT_CNT ) // +#define SRSHARP0_SR7_RO_GRAPHIC_DTL_CNT (SRSHARP0_OFFSET + SR7_RO_GRAPHIC_DTL_CNT ) // +#define SRSHARP0_SR7_CLR_PRT_PARAM (SRSHARP0_OFFSET + SR7_CLR_PRT_PARAM ) // +#define SRSHARP0_SR7_CLR_PRT_LC_GAIN (SRSHARP0_OFFSET + SR7_CLR_PRT_LC_GAIN ) // +#define SRSHARP0_SR7_CLR_PRT_LUT0 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT0 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT1 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT1 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT2 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT2 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT3 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT3 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT4 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT4 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT5 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT5 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT6 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT6 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT7 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT7 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT8 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT8 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT9 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT9 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT10 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT10 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT11 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT11 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT12 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT12 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT13 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT13 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT14 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT14 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT15 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT15 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT16 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT16 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT17 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT17 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT18 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT18 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT19 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT19 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT20 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT20 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT21 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT21 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT22 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT22 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT23 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT23 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT24 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT24 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT25 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT25 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT26 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT26 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT27 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT27 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT28 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT28 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT29 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT29 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT30 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT30 ) // +#define SRSHARP0_SR7_CLR_PRT_LUT31 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT31 ) // + + +//// srsharp1 reg define +#define SRSHARP1_SR7_DRTLPF_EN (SRSHARP1_OFFSET + SR7_DRTLPF_EN )// +#define SRSHARP1_SR7_DRTLPF_BETA (SRSHARP1_OFFSET + SR7_DRTLPF_BETA )// +#define SRSHARP1_SR7_PKBLD_BETA (SRSHARP1_OFFSET + SR7_PKBLD_BETA )// +#define SRSHARP1_SR7_XLTIBLD_BETA (SRSHARP1_OFFSET + SR7_XLTIBLD_BETA )// +#define SRSHARP1_SR7_DRTLPF_EDGE0 (SRSHARP1_OFFSET + SR7_DRTLPF_EDGE0 )// +#define SRSHARP1_SR7_DRTLPF_EDGE1 (SRSHARP1_OFFSET + SR7_DRTLPF_EDGE1 )// +#define SRSHARP1_SR7_DRTLPF_SDCOR0 (SRSHARP1_OFFSET + SR7_DRTLPF_SDCOR0 )// +#define SRSHARP1_SR7_DRTLPF_SDCOR1 (SRSHARP1_OFFSET + SR7_DRTLPF_SDCOR1 )// +#define SRSHARP1_SR7_CTIGAIN_SDCOR0 (SRSHARP1_OFFSET + SR7_CTIGAIN_SDCOR0 )// +#define SRSHARP1_SR7_CTIGAIN_SDCOR1 (SRSHARP1_OFFSET + SR7_CTIGAIN_SDCOR1 )// +#define SRSHARP1_SR7_LTIGAIN_SDCOR0 (SRSHARP1_OFFSET + SR7_LTIGAIN_SDCOR0 )// +#define SRSHARP1_SR7_LTIGAIN_SDCOR1 (SRSHARP1_OFFSET + SR7_LTIGAIN_SDCOR1 )// +#define SRSHARP1_SR7_HLTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_HLTIBPF_TAP0 )// +#define SRSHARP1_SR7_HLTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_HLTIBPF_TAP1 )// +#define SRSHARP1_SR7_HCTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_HCTIBPF_TAP0 )// +#define SRSHARP1_SR7_HCTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_HCTIBPF_TAP1 )// +#define SRSHARP1_SR7_PKLONGBPF_HTAP0 (SRSHARP1_OFFSET + SR7_PKLONGBPF_HTAP0 ) // +#define SRSHARP1_SR7_PKLONGBPF_HTAP1 (SRSHARP1_OFFSET + SR7_PKLONGBPF_HTAP1 ) // +#define SRSHARP1_SR7_PKLONGHPF_HTAP0 (SRSHARP1_OFFSET + SR7_PKLONGHPF_HTAP0 ) // +#define SRSHARP1_SR7_PKLONGHPF_HTAP1 (SRSHARP1_OFFSET + SR7_PKLONGHPF_HTAP1 ) // +#define SRSHARP1_SR7_VLTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_VLTIBPF_TAP0 ) // +#define SRSHARP1_SR7_VLTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_VLTIBPF_TAP1 ) // +#define SRSHARP1_SR7_VCTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_VCTIBPF_TAP0 ) // +#define SRSHARP1_SR7_VCTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_VCTIBPF_TAP1 ) // +#define SRSHARP1_SR7_PKLONGBPF_VTAP0 (SRSHARP1_OFFSET + SR7_PKLONGBPF_VTAP0 ) // +#define SRSHARP1_SR7_PKLONGBPF_VTAP1 (SRSHARP1_OFFSET + SR7_PKLONGBPF_VTAP1 ) // +#define SRSHARP1_SR7_PKLONGHPF_VTAP0 (SRSHARP1_OFFSET + SR7_PKLONGHPF_VTAP0 ) // +#define SRSHARP1_SR7_PKLONGHPF_VTAP1 (SRSHARP1_OFFSET + SR7_PKLONGHPF_VTAP1 ) // +#define SRSHARP1_SR7_CIRBPLONG_ALP (SRSHARP1_OFFSET + SR7_CIRBPLONG_ALP ) // +#define SRSHARP1_SR7_CIRHPLONG_ALP (SRSHARP1_OFFSET + SR7_CIRHPLONG_ALP ) // +#define SRSHARP1_SR7_DRTBPLONG_ALP (SRSHARP1_OFFSET + SR7_DRTBPLONG_ALP ) // +#define SRSHARP1_SR7_DRTHPLONG_ALP (SRSHARP1_OFFSET + SR7_DRTHPLONG_ALP ) // +#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D0 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D0) // +#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D1 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D1) // +#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D2 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D2) // +#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D3 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D3) // +#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D4 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D4) // +#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D0 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D0) // +#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D1 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D1) // +#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D2 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D2) // +#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D3 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D3) // +#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D4 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D4) // +#define SRSHARP1_SR7_PKDRT_BLD_EN (SRSHARP1_OFFSET + SR7_PKDRT_BLD_EN ) // +#define SRSHARP1_SR7_DRTDIF_TH (SRSHARP1_OFFSET + SR7_DRTDIF_TH ) // +#define SRSHARP1_SR7_TIBLD_PRT (SRSHARP1_OFFSET + SR7_TIBLD_PRT ) // +#define SRSHARP1_SR7_HTI_OPT_FORCE (SRSHARP1_OFFSET + SR7_HTI_OPT_FORCE ) // +#define SRSHARP1_SR7_HVTI_FINALGAIN (SRSHARP1_OFFSET + SR7_HVTI_FINALGAIN ) // +#define SRSHARP1_SR7_TIOS_SDRATIO (SRSHARP1_OFFSET + SR7_TIOS_SDRATIO ) // +#define SRSHARP1_SR7_XTI_SDFDEN (SRSHARP1_OFFSET + SR7_XTI_SDFDEN ) // +#define SRSHARP1_SR7_FDSD_PARAM (SRSHARP1_OFFSET + SR7_FDSD_PARAM ) // +#define SRSHARP1_SR7_TI_BPF_EN (SRSHARP1_OFFSET + SR7_TI_BPF_EN ) // +#define SRSHARP1_SR7_PKLONG_PF_EN (SRSHARP1_OFFSET + SR7_PKLONG_PF_EN ) // +#define SRSHARP1_SR7_PKLONG_PF_GAIN (SRSHARP1_OFFSET + SR7_PKLONG_PF_GAIN ) // +#define SRSHARP1_SR7_PKMINMAX_BLD (SRSHARP1_OFFSET + SR7_PKMINMAX_BLD ) // +#define SRSHARP1_SR7_TI_CONMAXERR_GAIN (SRSHARP1_OFFSET + SR7_TI_CONMAXERR_GAIN ) // +#define SRSHARP1_SR7_CC_PK_ADJ (SRSHARP1_OFFSET + SR7_CC_PK_ADJ ) // +#define SRSHARP1_SR7_CC_LUT0 (SRSHARP1_OFFSET + SR7_CC_LUT0 ) // +#define SRSHARP1_SR7_CC_LUT1 (SRSHARP1_OFFSET + SR7_CC_LUT1 ) // +#define SRSHARP1_SR7_CC_LUT2 (SRSHARP1_OFFSET + SR7_CC_LUT2 ) // +#define SRSHARP1_SR7_CC_LUT3 (SRSHARP1_OFFSET + SR7_CC_LUT3 ) // +#define SRSHARP1_SR7_CC_LUT4 (SRSHARP1_OFFSET + SR7_CC_LUT4 ) // +#define SRSHARP1_SR7_CC_LUT5 (SRSHARP1_OFFSET + SR7_CC_LUT5 ) // +#define SRSHARP1_SR7_GRAPHIC_CTRL (SRSHARP1_OFFSET + SR7_GRAPHIC_CTRL ) // +#define SRSHARP1_SR7_GRAPHIC_THD_GAIN (SRSHARP1_OFFSET + SR7_GRAPHIC_THD_GAIN ) // +#define SRSHARP1_SR7_RO_GRAPHIC_FLT_CNT (SRSHARP1_OFFSET + SR7_RO_GRAPHIC_FLT_CNT ) // +#define SRSHARP1_SR7_RO_GRAPHIC_DTL_CNT (SRSHARP1_OFFSET + SR7_RO_GRAPHIC_DTL_CNT ) // +#define SRSHARP1_SR7_CLR_PRT_PARAM (SRSHARP1_OFFSET + SR7_CLR_PRT_PARAM ) // +#define SRSHARP1_SR7_CLR_PRT_LC_GAIN (SRSHARP1_OFFSET + SR7_CLR_PRT_LC_GAIN ) // +#define SRSHARP1_SR7_CLR_PRT_LUT0 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT0 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT1 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT1 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT2 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT2 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT3 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT3 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT4 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT4 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT5 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT5 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT6 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT6 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT7 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT7 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT8 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT8 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT9 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT9 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT10 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT10 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT11 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT11 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT12 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT12 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT13 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT13 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT14 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT14 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT15 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT15 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT16 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT16 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT17 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT17 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT18 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT18 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT19 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT19 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT20 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT20 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT21 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT21 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT22 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT22 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT23 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT23 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT24 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT24 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT25 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT25 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT26 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT26 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT27 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT27 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT28 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT28 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT29 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT29 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT30 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT30 ) // +#define SRSHARP1_SR7_CLR_PRT_LUT31 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT31 ) // + +// synopsys translate_off +// synopsys translate_on +// +// Closing file: srsharp_regs2.h +// +// ----------------------------------------------- +// REG_BASE: VPPG_VCBUS_BASE = 0x52 +// ----------------------------------------------- +// 8'h50/51/52/53 have used for srsharp_regs +// ----------------------------------------------- +// REG_BASE: VPPH_VCBUS_BASE = 0x53 +// ----------------------------------------------- +// 8'h50/51/52/53 have used for srsharp_regs +//afbcd_multx6 use 3 reg_pages +// ----------------------------------------------- +// REG_BASE: MADE_VCBUS_BASE = 0x54 +// ----------------------------------------------- +// +// Reading file: afbcd_mult_regs.h +// +// synopsys translate_off +// synopsys translate_on +////===============================//// +// reg addr map +// 8'h0 - 8'h3f : rdmif +// 8'h40 - 8'h6f : afbcd +// 8'h70 - 8'h7f : fgrain +////===============================//// +#define RDMIFXN_GEN_REG ((0x5400 << 2) + 0xff000000) +#define RDMIFXN_CANVAS0 ((0x5401 << 2) + 0xff000000) +#define RDMIFXN_CANVAS1 ((0x5402 << 2) + 0xff000000) +#define RDMIFXN_LUMA_X0 ((0x5403 << 2) + 0xff000000) +#define RDMIFXN_LUMA_Y0 ((0x5404 << 2) + 0xff000000) +#define RDMIFXN_CHROMA_X0 ((0x5405 << 2) + 0xff000000) +#define RDMIFXN_CHROMA_Y0 ((0x5406 << 2) + 0xff000000) +#define RDMIFXN_LUMA_X1 ((0x5407 << 2) + 0xff000000) +#define RDMIFXN_LUMA_Y1 ((0x5408 << 2) + 0xff000000) +#define RDMIFXN_CHROMA_X1 ((0x5409 << 2) + 0xff000000) +#define RDMIFXN_CHROMA_Y1 ((0x540a << 2) + 0xff000000) +#define RDMIFXN_RPT_LOOP ((0x540b << 2) + 0xff000000) +#define RDMIFXN_LUMA0_RPT_PAT ((0x540c << 2) + 0xff000000) +#define RDMIFXN_CHROMA0_RPT_PAT ((0x540d << 2) + 0xff000000) +#define RDMIFXN_LUMA1_RPT_PAT ((0x540e << 2) + 0xff000000) +#define RDMIFXN_CHROMA1_RPT_PAT ((0x540f << 2) + 0xff000000) +#define RDMIFXN_LUMA_PSEL ((0x5410 << 2) + 0xff000000) +#define RDMIFXN_CHROMA_PSEL ((0x5411 << 2) + 0xff000000) +#define RDMIFXN_DUMMY_PIXEL ((0x5412 << 2) + 0xff000000) +#define RDMIFXN_LUMA_FIFO_SIZE ((0x5413 << 2) + 0xff000000) +#define RDMIFXN_AXI_CMD_CNT ((0x5414 << 2) + 0xff000000) +#define RDMIFXN_AXI_RDAT_CNT ((0x5415 << 2) + 0xff000000) +#define RDMIFXN_RANGE_MAP_Y ((0x5416 << 2) + 0xff000000) +#define RDMIFXN_RANGE_MAP_CB ((0x5417 << 2) + 0xff000000) +#define RDMIFXN_RANGE_MAP_CR ((0x5418 << 2) + 0xff000000) +#define RDMIFXN_GEN_REG2 ((0x5419 << 2) + 0xff000000) +#define RDMIFXN_PROT ((0x541a << 2) + 0xff000000) +#define RDMIFXN_URGENT_CTRL ((0x541b << 2) + 0xff000000) +#define RDMIFXN_GEN_REG3 ((0x541c << 2) + 0xff000000) +#define RDMIFXN_CFMT_CTRL ((0x541d << 2) + 0xff000000) +#define RDMIFXN_CFMT_W ((0x541e << 2) + 0xff000000) +#define AFBCDM_ENABLE ((0x5440 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0 +//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size +//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable +//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb +//Bit 19, reg_dos_uncomp_mode unsigned , default = 0 +//Bit 18:16, soft_rst unsigned , default = 4 +//Bit 15:14, reserved +//Bit 13:12, ddr_blk_size unsigned , default = 1 +//Bit 11:9, cmd_blk_size unsigend , default = 3 +//Bit 8, dec_enable unsigned , default = 0 +//Bit 7:2, reserved +//Bit 1, head_len_sel unsigned , default = 1 +//Bit 0, dec_frm_start unsigned , default = 0 +#define AFBCDM_MODE ((0x5441 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size; +//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size +//Bit 27:26, rev_mode uns, default = 0 , reverse mode +//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent +//Bit 23, reserved +//Bit 22:16, hold_line_num uns, default = 4 , +//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4 +//Bit 13:8, compbits_yuv uns, default = 0 , +// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit +//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2 +#define AFBCDM_SIZE_IN ((0x5442 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel +#define AFBCDM_DEC_DEF_COLOR ((0x5443 << 2) + 0xff000000) +//Bit 31:30, reserved +//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value +//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value +//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value +#define AFBCDM_CONV_CTRL ((0x5444 << 2) + 0xff000000) +//Bit 31:14, reserved +//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420 +//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n +#define AFBCDM_LBUF_DEPTH ((0x5445 << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel +//Bit 15:12, reserved +//Bit 11:0, mif_lbuf_depth uns, default = 128; +#define AFBCDM_HEAD_BADDR ((0x5446 << 2) + 0xff000000) +//Bit 31:0, mif_info_baddr uns, default = 32'h0; +#define AFBCDM_BODY_BADDR ((0x5447 << 2) + 0xff000000) +//Bit 31:0, mif_data_baddr uns, default = 32'h00010000; +#define AFBCDM_SIZE_OUT ((0x5448 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel +#define AFBCDM_OUT_YSCOPE ((0x5449 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel +//Bit 15:13, reserved +//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel +#define AFBCDM_STAT ((0x544a << 2) + 0xff000000) +//Bit 31:1, ro_dbg_top_info uns, default = 0 +//Bit 0, frm_end_stat uns, default = 0 frame end status +#define AFBCDM_VD_CFMT_CTRL ((0x544b << 2) + 0xff000000) +//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock +//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit +//Bit 29 reserved +//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation +//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase +//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable +//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1 +//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable +//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always +// repeat data, no interpolation +//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line +//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable +//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable +//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning +//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase +//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4) +//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable +#define AFBCDM_VD_CFMT_W ((0x544c << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width +//Bit 15:13 reserved +//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width +#define AFBCDM_MIF_HOR_SCOPE ((0x544d << 2) + 0xff000000) +//Bit 31:26, reserved +//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor +//Bit 15:10, reserved +//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor +#define AFBCDM_MIF_VER_SCOPE ((0x544e << 2) + 0xff000000) +//Bit 31:28, reserved +//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver +//Bit 15:12, reserved +//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver +#define AFBCDM_PIXEL_HOR_SCOPE ((0x544f << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel +//Bit 15:13, reserved +//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel +#define AFBCDM_PIXEL_VER_SCOPE ((0x5450 << 2) + 0xff000000) +//Bit 31:29, reserved +//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel +//Bit 15:13, reserved +//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel +#define AFBCDM_VD_CFMT_H ((0x5451 << 2) + 0xff000000) +//Bit 31:13, reserved +//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height +#define AFBCDM_IQUANT_ENABLE ((0x5452 << 2) + 0xff000000) +//Bit 31:12 reserved +//Bit 11 reg_quant_expand_en_1 //unsigned, RW, default = 0 enable for quantization value expansion +//Bit 10 reg_quant_expand_en_0 //unsigned, RW, default = 0 enable for quantization value expansion +//Bit 9: 8 reg_bcleav_ofst //signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1; +//Bit 7: 5 reserved +//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy +//Bit 3: 1 reserved +//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy +#define AFBCDM_IQUANT_LUT_1 ((0x5453 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCDM_IQUANT_LUT_2 ((0x5454 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCDM_IQUANT_LUT_3 ((0x5455 << 2) + 0xff000000) +//Bit 31 reserved +//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 27 reserved +//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 23 reserved +//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 19 reserved +//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCDM_IQUANT_LUT_4 ((0x5456 << 2) + 0xff000000) +//Bit 31:16 reserved +//Bit 15 reserved +//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 11 reserved +//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 7 reserved +//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +//Bit 3 reserved +//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1) +#define AFBCDM_ROT_CTRL ((0x5460 << 2) + 0xff000000) +//Bit 31:28 reserved +//Bit 27 reg_pip_mode //unsigned, RW, default = 0 , 0:dec_src from vdin/dos 1:dec_src from pip +//Bit 26:24 reg_rot_uv_vshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121) +//Bit 23 reserved +//Bit 22:20 reg_rot_uv_hshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121) +//Bit 19:18 reg_rot_uv_vshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink +//Bit 17:16 reg_rot_uv_hshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink +//Bit 15 reserved +//Bit 14:12 reg_rot_y_vshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121) +//Bit 11 reserved +//Bit 10:8 reg_rot_y_hshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121) +//Bit 7:6 reg_rot_y_vshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink +//Bit 5:4 reg_rot_y_hshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink +//Bit 3:2 reg_rot_uv422_drop_mode //unsigned, RW, default = 0 , 0:average 1:left 2:right +//Bit 1 reg_rot_uv422_omode //unsigned, RW, default = 0 , when rot input fmt422, 0:output_uv422 1:output_uv420 +//Bit 0 reg_rot_enable //unsigned, RW, default = 0 , rotation enable +#define AFBCDM_ROT_SCOPE ((0x5461 << 2) + 0xff000000) +//Bit 31:17 reserved +//Bit 16 reg_rot_ifmt_force444 //unsigned, RW , default = 1, 1: rot input fmt force as 444 +//Bit 15:14 reg_rot_ofmt_mode //unsigned, RW , default = 0, rot output fmt mode +//Bit 13:12 reg_rot_compbits_out_y //unsigned, RW , default = 0, rot output compbit y +//Bit 11:10 reg_rot_compbits_out_uv //unsigned, RW , default = 0, rot output compbit uv +//Bit 9:8 reg_rot_wrbgn_v //unsigned, RW , default = 0, rot pic vert size window begin pixel +//Bit 7:5 reserved +//Bit 4:0 reg_rot_wrbgn_h //unsigned, RW , default = 0, rot pic hori size window begin pixel +#define AFBCDM_RPLC_CTRL ((0x5462 << 2) + 0xff000000) +//Bit 31 reg_rplc_inter_corr_en //unsigned, RW , default = 0 , //pip replace inte-frame edge correct enable +//Bit 30 reg_rplc_dummy_corr_en //unsigned, RW , default = 0 , //pip replace outsize of real-pipframe edge correct enable +//Bit 29 reg_rplc_byps //unsigned, RW , default = 1 , //pip replace module bypass +//Bit 28:16 reg_rplc_vsize_in //unsigned, RW , default = 1080, // +//Bit 15:13 reserved +//Bit 12:0 reg_rplc_hsize_in //unsigned, RW , default = 1920, +#define AFBCDM_RPLC_PICEN ((0x5463 << 2) + 0xff000000) +//Bit 27:16 reg_rplc_def_color_y //unsigned, RW , default =0 , //pip replace def_color_y +//Bit 15:0 reg_rplc_pic_enable //unsigned, RW , default =16'hffff , //pip replace pip_picure enbale +#define AFBCDM_RPLC_DEFCOL ((0x5464 << 2) + 0xff000000) +//Bit 23:12 reg_rplc_def_color_v //unsigned, RW , default =0 , //pip replace def_color_v +//Bit 11:0 reg_rplc_def_color_u //unsigned, RW , default =0 , //pip replace def_color_u +#define AFBCDM_RPLC_SCPXN_ADDR ((0x5465 << 2) + 0xff000000) +//Bit 31:0 reg_rplc_scpxn_addr //unsigned, RW , default =0 , //pip replace scopx16 addr +#define AFBCDM_RPLC_SCPXN_DATA ((0x5466 << 2) + 0xff000000) +//Bit 31:0 reg_rplc_scpxn_data //unsigned, RW , default =0 , //pip replace scopx16 data +#define AFBCDM_FGRAIN_CTRL ((0x5470 << 2) + 0xff000000) +//Bit 31:26 reserved +//Bit 25:24 reg_sync_ctrl // unsigned , RW, default = 0 +//Bit 23 reserved +//Bit 22 reg_dma_st_clr // unsigned , RW, default = 0 clear DMA error status +//Bit 21 reg_hold4dma_scale // unsigned , RW, default = 0 1 to wait DMA scale data ready before accept input data default = 0 +//Bit 20 reg_hold4dma_tbl // unsigned , RW, default = 0 1 to wait DMA grain table data ready before accept input data default = 0 +//Bit 19 reg_cin_uv_swap // unsigned , RW, default = 0 1 to swap U/V input +//Bit 18 reg_cin_rev // unsigned , RW, default = 0 1 to reverse the U/V input order +//Bit 17 reg_yin_rev // unsigned , RW, default = 0 1 to reverse the Y input order +//Bit 16 reg_fgrain_ext_imode // unsigned , RW, default = 1 0 to indicate the input data is *4 in 8bit mode +//Bit 15 reg_use_par_apply_fgrain // unsigned , RW, default = 0 1 to use apply_fgrain from DMA table +//Bit 14 reg_fgrain_last_ln_mode // unsigned , RW, default = 0 1 to keep fgrain noise generator though the input is finished for rdmif. +//Bit 13 reg_fgrain_use_sat4bp // unsigned , RW, default = 0 1 to use fgain_max/min for sat not {DW{1'b1}}/0 +//Bit 12 reg_apply_c_mode // unsigned , RW, default = 1 0 to following C +//Bit 11 reg_fgrain_tbl_sign_mode // unsigned , RW, default = 1 0 to indicate signed bit is not extended in 8bit mode +//Bit 10 reg_fgrain_tbl_ext_mode // unsigned , RW, default = 1 0 to indicate the grain table is *4 in 8bit mode +//Bit 9: 8 reg_fmt_mode // unsigned , RW, default = 2 0:444; 1:422; 2:420; 3:reserved +//Bit 7: 6 reg_comp_bits // unsigned , RW, default = 1 0:8bits; 1:10bits, else 12 bits +//Bit 5: 4 reg_rev_mode // unsigned . RW, default = 0 0:h_rev; 1:v_rev; +//Bit 3 reserved +//Bit 2 reg_block_mode // unsigned , RW, default = 1 +//Bit 1 reg_fgrain_loc_en // unsigned , RW, default = 0 frame-based fgrain enable +//Bit 0 reg_fgrain_glb_en // unsigned , RW, default = 0 global-based fgrain enable +#define AFBCDM_FGRAIN_WIN_H ((0x5471 << 2) + 0xff000000) +//Bit 31:16 reg_win_end_h .unsigned , default = 3812 +//Bit 15: 0, reg_win_bgn_h .unsigned , default = 0 +#define AFBCDM_FGRAIN_WIN_V ((0x5472 << 2) + 0xff000000) +//Bit 31:16 reg_win_end_v .unsigned , default = 2156 +//Bit 15: 0, reg_win_bgn_v .unsigned , default = 0 +#define AFBCDM_FGRAIN_SW_Y_RANNGE ((0x5473 << 2) + 0xff000000) +//Bit 31, reg_fgrain_sw_yrange .unsigned , default = 0 +//Bit 30:26, reserved +//Bit 25:16, reg_fgrain_ymax .unsigned , default = 1023 +//Bit 15:10, reserved +//Bit 9: 0, reg_fgrain_ymin .unsigned , default = 0 +#define AFBCDM_FGRAIN_SW_C_RANNGE ((0x5474 << 2) + 0xff000000) +//Bit 31, reg_fgrain_sw_crange .unsigned , default = 0 +//Bit 30:26, reserved +//Bit 25:16, reg_fgrain_cmax .unsigned , default = 1023 +//Bit 15:10, reserved +//Bit 9: 0, reg_fgrain_cmin .unsigned , default = 0 +#define AFBCDM_FGRAIN_GCLK_CTRL_0 ((0x5475 << 2) + 0xff000000) +//Bit 31:0, reg_fgrain_gclk_ctrl0 .unsigned , default = 0 +#define AFBCDM_FGRAIN_GCLK_CTRL_1 ((0x5476 << 2) + 0xff000000) +//Bit 31:0, reg_fgrain_gclk_ctrl1 .unsigned , default = 0 +#define AFBCDM_FGRAIN_GCLK_CTRL_2 ((0x5477 << 2) + 0xff000000) +//Bit 31:0, reg_fgrain_gclk_ctrl2 .unsigned , default = 0 +#define AFBCDM_FGRAIN_PARAM_ADDR ((0x5478 << 2) + 0xff000000) +#define AFBCDM_FGRAIN_PARAM_DATA ((0x5479 << 2) + 0xff000000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: afbcd_mult_regs.h +// +//afbcd_multx6 use 3 reg_pages +// ----------------------------------------------- +// REG_BASE: MADF_VCBUS_BASE = 0x55 +// ----------------------------------------------- +//`include "afbcd_mult_regs.h" +//afbcd_multx6 use 3 reg_pages +// ----------------------------------------------- +// REG_BASE: MADG_VCBUS_BASE = 0x56 +// ----------------------------------------------- +//`include "afbcd_mult_regs.h" +// ----------------------------------------------- +// REG_BASE: MADH_VCBUS_BASE = 0x57 +// ----------------------------------------------- +// ----------------------------------------------- +// REG_BASE: VPPI_VCBUS_BASE = 0x58 +// ----------------------------------------------- +// +// Reading file: pip_alph_gen_regs.h +// +// +// Reading file: vd1_pip_alph_gen_regs.h +// +// synopsys translate_off +// synopsys translate_on +// +////===================================//// +////reg +////===================================//// +#define VD1_PIP_ALPH_CTRL ((0x5880 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28 reg_alph_gen_dbg unsigned,default = 0 +//Bit 27:12 reg_pic_en unsigned,default = 16'h0 +//Bit 11:3 reg_alph0 unsigned,default = 0 +//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 0:original, 1: 0.5 alpha 2: 0.25/0.5/0.75 alph +//Bit 0 reg_alph_gen_byps unsigned, default = 1 +#define VD1_PIP_ALPH_SCP_H_0 ((0x5881 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_1 ((0x5882 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_2 ((0x5883 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_3 ((0x5884 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_4 ((0x5885 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_5 ((0x5886 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_6 ((0x5887 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_7 ((0x5888 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_8 ((0x5889 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_9 ((0x588a << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_10 ((0x588b << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_11 ((0x588c << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_12 ((0x588d << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_13 ((0x588e << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_14 ((0x588f << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_H_15 ((0x5890 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_0 ((0x5891 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_1 ((0x5892 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_2 ((0x5893 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_3 ((0x5894 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_4 ((0x5895 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_5 ((0x5896 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_6 ((0x5897 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_7 ((0x5898 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_8 ((0x5899 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_9 ((0x589a << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_10 ((0x589b << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_11 ((0x589c << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_12 ((0x589d << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_13 ((0x589e << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_14 ((0x589f << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0 +#define VD1_PIP_ALPH_SCP_V_15 ((0x58a0 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0 +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vd1_pip_alph_gen_regs.h +// +// +// Reading file: vd2_pip_alph_gen_regs.h +// +// synopsys translate_off +// synopsys translate_on +// +////===================================//// +////reg +////===================================//// +#define VD2_PIP_ALPH_CTRL ((0x58b0 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28 reg_alph_gen_dbg unsigned,default = 0 +//Bit 27:12 reg_pic_en unsigned,default = 16'h +//Bit 11:3 reg_alph0 unsigned,default = 0 +//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 0:original, 1: 0.5 alpha 2: 0.25/0.5/0.75 alph +//Bit 0 reg_alph_gen_byps unsigned, default = 1 +#define VD2_PIP_ALPH_SCP_H_0 ((0x58b1 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_1 ((0x58b2 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_2 ((0x58b3 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_3 ((0x58b4 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_4 ((0x58b5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_5 ((0x58b6 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_6 ((0x58b7 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_7 ((0x58b8 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_8 ((0x58b9 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_9 ((0x58ba << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_10 ((0x58bb << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_11 ((0x58bc << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_12 ((0x58bd << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_13 ((0x58be << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_14 ((0x58bf << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_H_15 ((0x58c0 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_0 ((0x58c1 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_1 ((0x58c2 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_2 ((0x58c3 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_3 ((0x58c4 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_4 ((0x58c5 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_5 ((0x58c6 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_6 ((0x58c7 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_7 ((0x58c8 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_8 ((0x58c9 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_9 ((0x58ca << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_10 ((0x58cb << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_11 ((0x58cc << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_12 ((0x58cd << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_13 ((0x58ce << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_14 ((0x58cf << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0 +#define VD2_PIP_ALPH_SCP_V_15 ((0x58d0 << 2) + 0xff000000) +//Bit 31:29 reserved +//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0 +//Bit 15:13 reserved +//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0 +// synopsys translate_off +// synopsys translate_on +// +// Closing file: vd2_pip_alph_gen_regs.h +// +// +// Closing file: pip_alph_gen_regs.h +// +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ./vcbus_regs.h +// +// +// Reading file: ./ge2d_regs.h +// +// synopsys translate_off +// synopsys translate_on +//=========================================================================== +////// GE2D Registers 0x8a0 - 0x8ff +//address is 0xd016_0000 - 0xd0160000 - 0xd01603ff +//=========================================================================== +// ----------------------------------------------- +// REG_BASE: GE2D_GCBUS_BASE = 0x00 +// ----------------------------------------------- +//Bit 31, destination bytemask only if destination bitmask is enable +//Bit 30, destination bitmask enable +//Bit 29, source2 key enable +//Bit 28, source2 key mode, 0: mask data when match, 1: mask data when unmatch +//Bit 27, source1 key enable +//Bit 26, source1 key mode, 0: mask data when match, 1: mask data when unmatch +//Bit 25:24, dst1 8bit mode component selection, +// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha +//Bit 23 dst clip mode, 0: write inside clip window, 1: write outside clip window +//Bit 22:17, reserved +//Bit 16:15, src2 8bit mode component selection, +// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha +//Bit 14 src2 fill mode, 0: repeat data, 1: fill default color +//Bit 13:12 src2 picture struct, 00: frame, 10: even, 11: odd +//Bit 11 src1 x direction yc ration, 0: 1:1, 1: 2:1 +//Bit 10 src1 y direction yc ration, 0: 1:1, 1: 2:1 +//Bit 9:7 reserved +//Bit 6:5, src1 8bit mode component selection, +// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha +//Bit 4 src1 fill mode, 0: repeat data, 1: fill default color +//Bit 3 src1 lookup table enable +//Bit 2:1 src1 picture struct, 00: frame, 10: even, 11: odd +//Bit 0 src1 separate buffer enable +#define GE2D_GEN_CTRL0 ((0x00a0 << 2) + 0xff040000) +//Bit 31, soft rst +//Bit 30, dst write response counter reset +//Bit 29, disable adding dst write response count to busy bit +//Bit 28:26, reserved +//bit 25:24, interrupt control, if bit[0] true, generate interrupt when one command done, +// if bit[1] true, generate interrupt when ge2d change from busy to not busy +//Bit 23:22 src2 burst size control +//Bit 21:16 src1 burst size control, 5:4, yfifo, 3:2, cbfifo, 1:0, crfifo +// each 2bit, 00: 24 64bitword, 01: 32 64bitword, 10: 48 64bitwords, 11: 64 64bitwords +//Bit 15:14, dst1 picture struct, 00: frame, 10:top, 11: bottom +//Bit 13:12, bit 13 if true, force read src1, bit 12 if true, force read src2 +//Bit 11, dst2 request urgent enable +//Bit 10, src1 request urgent enable +//Bit 9, src2 request urgent enable +//Bit 8, dst1 request urgent enable +//Bit 7:0 src1 global alpha +#define GE2D_GEN_CTRL1 ((0x00a1 << 2) + 0xff040000) +//Bit31 alpha conversion mode in alu, 0: alpha_out = (alpha !=0) ? alpha +1 : 0; +// otherwise, alpha_out = (alpha < 128) ? alpha: alpha + 1; +//Bit30 color conversion mode in alu, 0: color_out = (color != 0) ? color +1: 0; +// otherwise, color_out = (color < 128) ? color: color + 1; +//Bit29 src1_gb_alpha_en, As = src1_gb_alpha_en ? Asr * Ag: Asr +//Bit28 dst1_color_round_mode, 0: truncate, 1: + 0.5 rounding +//Bit27 src2_color_expand_mode, 0: add 0, 1: add MSBs +//Bit26 src2_alpha_expand_mode, 0: add 0, 1: add MSBs +//Bit25 src1_color_expand_mode, 0: add 0, 1: add MSBs +//Bit24 src1_alpha_expand_mode, 0: add 0, 1: add MSBs +//Bit 23 if true, dst little endian, otherwise big endian +//Bit 22:19 dst1 color_map +// dst1_format=0 : output 8-bit; +// dst1_format=1, dst1_color_map=1: output 16-bit YCbCr 655; +// dst1_format=1, dst1_color_map=2: output 16-bit YCbCr 844; +// dst1_format=1, dst1_color_map=3: output 16-bit YCbCrA 6442; +// dst1_format=1, dst1_color_map=4: output 16-bit YCbCrA 4444; +// dst1_format=1, dst1_color_map=5: output 16-bit YCbCr 565; +// dst1_format=1, dst1_color_map=6: output 16-bit AYCbCr 4444; +// dst1_format=1, dst1_color_map=7: output 16-bit AYCbCr 1555; +// dst1_format=1, dst1_color_map=8: output 16-bit YCbCrA 4642; +// dst1_format=1, dst1_color_map=9: output 16-bit CbCr 88; +// dst1_format=1, dst1_color_map=10:output 16-bit CrCb 88; +// dst1_format=2, dst1_color_map=0: output 24-bit YCbCr 888; +// dst1_format=2, dst1_color_map=1: output 24-bit YCbCrA 5658; +// dst1_format=2, dst1_color_map=2: output 24-bit AYCbCr 8565; +// dst1_format=2, dst1_color_map=3: output 24-bit YCbCrA 6666; +// dst1_format=2, dst1_color_map=4: output 24-bit AYCbCr 6666; +// dst1_format=2, dst1_color_map=5: output 24-bit CrCbY 888; +// dst1_format=3, dst1_color_map=0: output 32-bit YCbCrA 8888; +// dst1_format=3, dst1_color_map=1: output 32-bit AYCbCr 8888; +// dst1_format=3, dst1_color_map=2: output 32-bit ACrCbY 8888; +// dst1_format=3, dst1_color_map=3: output 32-bit CrCbYA 8888. +//Bit 17:16 dst1_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit +//Bit 15 if true, src2 little endian, otherwise big endian +//Bit 14:11 src2 color_map +// src2_format=0 : output 8-bit; +// src2_format=1, src2_color_map=1: output 16-bit YCbCr 655; +// src2_format=1, src2_color_map=2: output 16-bit YCbCr 844; +// src2_format=1, src2_color_map=3: output 16-bit YCbCrA 6442; +// src2_format=1, src2_color_map=4: output 16-bit YCbCrA 4444; +// src2_format=1, src2_color_map=5: output 16-bit YCbCr 565; +// src2_format=1, src2_color_map=6: output 16-bit AYCbCr 4444; +// src2_format=1, src2_color_map=7: output 16-bit AYCbCr 1555; +// src2_format=1, src2_color_map=8: output 16-bit YCbCrA 4642; +// src2_format=2, src2_color_map=0: output 24-bit YCbCr 888; +// src2_format=2, src2_color_map=1: output 24-bit YCbCrA 5658; +// src2_format=2, src2_color_map=2: output 24-bit AYCbCr 8565; +// src2_format=2, src2_color_map=3: output 24-bit YCbCrA 6666; +// src2_format=2, src2_color_map=4: output 24-bit AYCbCr 6666; +// src2_format=2, src2_color_map=5: output 24-bit CrCbY 888; +// src2_format=3, src2_color_map=0: output 32-bit YCbCrA 8888; +// src2_format=3, src2_color_map=1: output 32-bit AYCbCr 8888; +// src2_format=3, src2_color_map=2: output 32-bit ACrCbY 8888; +// src2_format=3, src2_color_map=3: output 32-bit CrCbYA 8888. +//Bit 9:8 src2 format, 00: 8bit, 01:16bit, 10:24bit 11: 32bit +//Bit 7 if true, src1 little endian, otherwise big endian +//Bit 6:3 src1 color_map +// src1_format=0 : output 8-bit; +// src1_format=1, src1_color_map=0: output 4:2:2 (Y0Cb0Y1Cr0); +// src1_format=1, src1_color_map=1: output 16-bit YCbCr 655; +// src1_format=1, src1_color_map=2: output 16-bit YCbCr 844; +// src1_format=1, src1_color_map=3: output 16-bit YCbCrA 6442; +// src1_format=1, src1_color_map=4: output 16-bit YCbCrA 4444; +// src1_format=1, src1_color_map=5: output 16-bit YCbCr 565; +// src1_format=1, src1_color_map=6: output 16-bit AYCbCr 4444; +// src1_format=1, src1_color_map=7: output 16-bit AYCbCr 1555; +// src1_format=1, src2_color_map=8: output 16-bit YCbCrA 4642; +// src1_format=2, src1_color_map=0: output 24-bit YCbCr 888; +// src1_format=2, src1_color_map=1: output 24-bit YCbCrA 5658; +// src1_format=2, src1_color_map=2: output 24-bit AYCbCr 8565; +// src1_format=2, src1_color_map=3: output 24-bit YCbCrA 6666; +// src1_format=2, src1_color_map=4: output 24-bit AYCbCr 6666; +// src1_format=2, src1_color_map=5: output 24-bit CrCbY 888; +// src1_format=2, src1_color_map=14:output 8-bit Y and 16-bit CbCr; +// src1_format=2, src1_color_map=15:output 8-bit Y and 16-bit CrCb; +// src1_format=3, src1_color_map=0: output 32-bit YCbCrA 8888; +// src1_format=3, src1_color_map=1: output 32-bit AYCbCr 8888; +// src1_format=3, src1_color_map=2: output 32-bit ACrCbY 8888; +// src1_format=3, src1_color_map=3: output 32-bit CrCbYA 8888. +//Bit 1:0 src1 format, 00: 8bit, 01:16bit/4:2:2, 10:24bit 11: 32bit +#define GE2D_GEN_CTRL2 ((0x00a2 << 2) + 0xff040000) +//Bit 9 if true, all src2 data use default color +//Bit 8 if true, all src1 data use default color +//Bit 7 if true, dst x/y swap +//Bit 6 if true, dst x direction reversely read +//Bit 5 if true, dst y direction reversely read +//Bit 4 if true, src2 x direction reversely read +//Bit 3 if true, src2 y direction reversely read +//Bit 2 if true, src1 x direction reversely read +//Bit 1 if true, src1 y direction reversely read +//Bit 0 cmd write +#define GE2D_CMD_CTRL ((0x00a3 << 2) + 0xff040000) +//Read only +//Bit 28:17 dst write response counter, for debug only +//Bit 16:7 ge2d_dp status, for debug only +//Bit 6 read src1 cmd ready +//Bit 5 read src2 cmd ready +//Bit 4 pre dpcmd ready +//Bit 3 ge2d dpcmd ready +//Bit 2 ge2d buffer command valid +//Bit 1 ge2d current command valid +//Bit 0 ge2d busy +#define GE2D_STATUS0 ((0x00a4 << 2) + 0xff040000) +// +//Read only +// Bit 29:16 ge2d_dst1_status, for debug only +// Bit 15 ge2d_rd_src2 core.fifo_empty +// Bit 14 ge2d_rd_src2 core.fifo_overflow +// Bit 13:12 ge2d_rd_src2 core.req_st +// Bit 11 ge2d_rd_src2 cmd_if.cmd_err, true if cmd_format=1 +// Bit 10 ge2d_rd_src2 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state +// Bit 9 ge2d_rd_src1 luma_core(chroma_core).fifo_empty +// Bit 8 ge2d_rd_src1 luma_core(chroma_core).fifo_overflow +// Bit 7: 6 ge2d_rd_src1 chroma_core.req_st_cr +// Bit 5: 4 ge2d_rd_src1 chroma_core.req_st_cb +// Bit 3: 2 ge2d_rd_src1 luma_core.req_st_y +// Bit 1 ge2d_rd_src1 cmd_if.stat_read_window_err, 1=reading/clipping window setting exceed limit +// Bit 0 ge2d_rd_src1 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state +#define GE2D_STATUS1 ((0x00a5 << 2) + 0xff040000) +//SRC1 default clolor +//{Y,Cb,Cr,A}/{R,G,B,A} +#define GE2D_SRC1_DEF_COLOR ((0x00a6 << 2) + 0xff040000) +//Bit 31, SRC1 clip x start extra, if true, one more data is read for chroma +//Bit 28:16, SRC1 clip x start +//Bit 15, SRC1 clip x end extra, if true, one more data is read for chroma +//Bit 12:0, SRC1 clip x end +#define GE2D_SRC1_CLIPX_START_END ((0x00a7 << 2) + 0xff040000) +//Bit 31, SRC1 clip y start extra, if true, one more data is read for chroma +//Bit 28:16, SRC1 clip y start +//Bit 15, SRC1 clip y end extra, if true, one more data is read for chroma +//Bit 12:0, SRC1 clip y end +#define GE2D_SRC1_CLIPY_START_END ((0x00a8 << 2) + 0xff040000) +//Bit 31:24, SRC1 canvas address0 +//Bit 23:16, SRC1 canvas address1 +//Bit 15:8, SRC1 canvas address2 +#define GE2D_SRC1_CANVAS ((0x00a9 << 2) + 0xff040000) +//Bit 31, SRC1 x start extra bit1, if true, one more chroma data is read for x even start chroma data when y/c ratio = 2 +// or x even/odd start chroma extra data when y/c ratio = 1 +//Bit 30, SRC1 x start extra bit0, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2 +//Bit 29:16, SRC1 x start, signed data +//Bit 15, SRC1 x end extra bit1, if true, one more chroma data is read for x odd end chroma data when y/c ratio = 2 +// or x even/odd end chroma extra data when y/c ratio = 1 +//Bit 14, SRC1 x end extra bit0, if true, one more chroma data is read for x even end chroma data when y/c ratio = 2 +//Bit 13:0, SRC1 x end, signed data +#define GE2D_SRC1_X_START_END ((0x00aa << 2) + 0xff040000) +//Bit 31, SRC1 y start extra, if true, one more chroma data is read for y even start chroma data when y/c ratio = 2 +// or y even/odd start chroma extra data when y/c ratio = 1 +//Bit 30, SRC1 y start extra, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2 +//Bit 28:16, SRC1 y start +//Bit 15, SRC1 y end extra bit1, if true, one more chroma data is read for y odd end chroma data when y/c ratio = 2 +// or y even/odd end chroma extra data when y/c ratio = 1 +//Bit 14, SRC1 y end extra bit0, if true, one more chroma data is read for y even end chroma data when y/c ratio = 2 +//Bit 12:0, SRC1 y end +#define GE2D_SRC1_Y_START_END ((0x00ab << 2) + 0xff040000) +// Bit 31: 9 Reserved +// Bit 8 RW, 0 = Write LUT, 1 = Read LUT +// Bit 7: 0 RW, lut_addr +#define GE2D_SRC1_LUT_ADDR ((0x00ac << 2) + 0xff040000) +// Bit 31:24 RW, Y or R +// Bit 23:16 RW, Cb or G +// Bit 15: 8 RW, Cr or B +// Bit 7: 0 RW, Alpha +#define GE2D_SRC1_LUT_DAT ((0x00ad << 2) + 0xff040000) +//Bit 19, if true, horizontal formatter using repeat to get the pixel, otherwise using interpolation +//Bit 18, horizontal formatter en +//Bit 17, if true, vertical formatter using repeat to get the pixel, otherwise using interpolation +//Bit 16, vertical formatter en +//Bit 15:8 X direction chroma phase, +// [7:4] for x direction even start/end chroma phase when y/c ratio = 2 +// or start/end even/odd chroma phase when y/c ratio = 1 +// [3:0] for x direction odd start/end chroma phase only when y/c ration = 2 +//Bit 7:0 Y direction chroma phase, +// [7:4] for y direction even start/end chroma phase when y/c ratio = 2 +// or start/end even/odd chroma phase when y/c ratio = 1 +// [3:0] for y direction odd start/end chroma phase only when y/c ration = 2 +#define GE2D_SRC1_FMT_CTRL ((0x00ae << 2) + 0xff040000) +//SRC2 default clolor +//{Y,Cb,Cr,A}/{R,G,B,A} +#define GE2D_SRC2_DEF_COLOR ((0x00af << 2) + 0xff040000) +//Bit 28:16, SRC2 clip x start +//Bit 12:0, SRC2 clip x end +#define GE2D_SRC2_CLIPX_START_END ((0x00b0 << 2) + 0xff040000) +//Bit 28:16, SRC2 clip y start +//Bit 12:0, SRC2 clip y end +#define GE2D_SRC2_CLIPY_START_END ((0x00b1 << 2) + 0xff040000) +//Bit 28:16, SRC2 x start +//Bit 12:0, SRC2 x end +#define GE2D_SRC2_X_START_END ((0x00b2 << 2) + 0xff040000) +//Bit 28:16, SRC2 y start +//Bit 12:0, SRC2 y end +#define GE2D_SRC2_Y_START_END ((0x00b3 << 2) + 0xff040000) +//Bit 28:16, DST clip x start +//Bit 12:0, DST clip x end +#define GE2D_DST_CLIPX_START_END ((0x00b4 << 2) + 0xff040000) +// +//Bit 28:16, DST clip y start +//Bit 12:0, DST clip y end +#define GE2D_DST_CLIPY_START_END ((0x00b5 << 2) + 0xff040000) +//Bit 28:16, DST x start +//Bit 12:0, DST x end +#define GE2D_DST_X_START_END ((0x00b6 << 2) + 0xff040000) +// +//Bit 28:16, DST x start +//Bit 12:0, DST x end +#define GE2D_DST_Y_START_END ((0x00b7 << 2) + 0xff040000) +//Bit 23:16 DST2 canvas address +//Bit 15:8 SRC2 canvas address +//Bit 7:0 DST1 canvas address +#define GE2D_SRC2_DST_CANVAS ((0x00b8 << 2) + 0xff040000) +//vertical scaler phase step +//Bit 28:0, 5.24 format +#define GE2D_VSC_START_PHASE_STEP ((0x00b9 << 2) + 0xff040000) +//phase slope +//Bit 24:0, bit 24 signed bit +#define GE2D_VSC_PHASE_SLOPE ((0x00ba << 2) + 0xff040000) +//Bit 30:29, vertical repeat line0 number +//Bit 23:0, vertical scaler initial phase +#define GE2D_VSC_INI_CTRL ((0x00bb << 2) + 0xff040000) +//horizontal scaler phase step +//Bit 28:0, 5.24 format +#define GE2D_HSC_START_PHASE_STEP ((0x00bc << 2) + 0xff040000) +//phase slope +//Bit 24:0, bit 24 signed bit +#define GE2D_HSC_PHASE_SLOPE ((0x00bd << 2) + 0xff040000) +//Bit 30:29, horizontal repeat line0 number +//Bit 23:0, horizontal scaler initial phase +#define GE2D_HSC_INI_CTRL ((0x00be << 2) + 0xff040000) +//Bit 31:24, advance number in this round, if horizontal scaler is working on dividing mode +//Bit 23:0, horizontal scaler advance phase in this round, if horizontal scaler is working on dividing mode +#define GE2D_HSC_ADV_CTRL ((0x00bf << 2) + 0xff040000) +//Bit 30, vertical nearest mode enable, must set vt_bank_length = 4 +//Bit 29, horizontal nearest mode enable, must set hz_bank_length = 4 +//Bit 28, horizontal scaler dividing mode enable +//Bit 27:15, horizontal dividing length, if bit 28 is enable +//Bit 14, pre horizontal scaler enable +//Bit 13, pre vertical scale enable +//Bit 12, vertical scale enable +//Bit 11, horizontal scaler enable +//Bit 9, if true, treat horizontal repeat line number(GE2D_HSC_INI_CTRL bit 30:29) as repeating line, +// otherwise using treat horizontal repeat line number as minus line number. +//Bit 8, if true, treat vertical repeat line number(GE2D_VSC_INI_CTRL bit 30:29) as repeating line, +// otherwise using treat vertical repeat line number as minus line number. +//Bit 7, if true, always use phase0 in vertical scaler +//Bit 6:4, vertical scaler bank length +//Bit 3, if true, always use phase0 in horizontal scaler +//Bit 2:0, horizontal scaler bank length +#define GE2D_SC_MISC_CTRL ((0x00c0 << 2) + 0xff040000) +//Read only +//vertical scaler next round integer pixel pointer, signed data +//Bit 13:0 +#define GE2D_VSC_NRND_POINT ((0x00c1 << 2) + 0xff040000) +//Read only +//vertical scaler next round phase +//bit 23:0 +#define GE2D_VSC_NRND_PHASE ((0x00c2 << 2) + 0xff040000) +//Read only +//horizontal scaler next round integer pixel pointer, signed data +//Bit 13:0 +#define GE2D_HSC_NRND_POINT ((0x00c3 << 2) + 0xff040000) +//Read only +//horizontal scaler next round phase +//bit 23:0 +#define GE2D_HSC_NRND_PHASE ((0x00c4 << 2) + 0xff040000) +// +//Bit 28:20, pre_offset0 +//Bit 18:10, pre_offset1 +//Bit 8:0, pre_offset2 +#define GE2D_MATRIX_PRE_OFFSET ((0x00c5 << 2) + 0xff040000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define GE2D_MATRIX_COEF00_01 ((0x00c6 << 2) + 0xff040000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define GE2D_MATRIX_COEF02_10 ((0x00c7 << 2) + 0xff040000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define GE2D_MATRIX_COEF11_12 ((0x00c8 << 2) + 0xff040000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define GE2D_MATRIX_COEF20_21 ((0x00c9 << 2) + 0xff040000) +//Bit 28:16 coef22 +//Bit 7 input y/cb/cr saturation enable +//Bit 0 conversion matrix enable +#define GE2D_MATRIX_COEF22_CTRL ((0x00ca << 2) + 0xff040000) +//Bit 28:20, offset0 +//Bit 18:10, offset1 +//Bit 8:0, offset2 +#define GE2D_MATRIX_OFFSET ((0x00cb << 2) + 0xff040000) +//Bit 26:25, SRC1 color multiplier alpha selection +// if 00, Cs = Csr +// if 01, Cs = Csr * Asr * Ag (if source is not premultiplied) +// if 10, Cs = Csr * Ag (if source is premultipied) +//Bit 24 SRC2 color multiplier alpha selection +// if 0, no multiplier, Cd = Cdr, otherwise, Cd = Cdr * Ad. +//Bit 22:12 ALU color operation +// bit10:8 Blending Mode Parameter +// 3'b000: ADD Cs*Fs + Cd*Fd +// 3'b001: SUBTRACT Cs*Fs - Cd*Fd +// 3'b010: REVERSE SUBTRACT Cd*Fd - Cs*Fs +// 3'b011: MIN min(Cs*Fs, Cd*Fd) +// 3'b100: MAX max(Cs*Fs, Cd*Fd) +// 3'b101: LOGIC OP Cs op Cd +// bit7:4 Source Color Blending Factor CFs +// 4'b0000: ZERO 0 +// 4'b0001: ONE 1 +// 4'b0010: SRC_COLOR Cs(RGBs) +// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs) +// 4'b0100: DST_COLOR Cd(RGBd) +// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd) +// 4'b0110: SRC_ALPHA As +// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As +// 4'b1000: DST_ALPHA Ad +// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad +// 4'b1010: CONST_COLOR Cc(RGBc) +// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc) +// 4'b1100: CONST_ALPHA Ac +// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac +// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad) +// bit3:0 dest Color Blending Factor CFd, when bit10:8 != LOGIC OP +// 4'b0000: ZERO 0 +// 4'b0001: ONE 1 +// 4'b0010: SRC_COLOR Cs(RGBs) +// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs) +// 4'b0100: DST_COLOR Cd(RGBd) +// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd) +// 4'b0110: SRC_ALPHA As +// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As +// 4'b1000: DST_ALPHA Ad +// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad +// 4'b1010: CONST_COLOR Cc(RGBc) +// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc) +// 4'b1100: CONST_ALPHA Ac +// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac +// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad) +// bit3:0 logic operations, when bit10:8 == LOGIC OP +// 4'b0000: CLEAR 0 +// 4'b0001: COPY s +// 4'b0010: NOOP d +// 4'b0011: SET 1 +// 4'b0100: COPY_INVERT ~s +// 4'b0101: INVERT ~d +// 4'b0110: AND_REVERSE s & ~d +// 4'b0111: OR_REVERSE s | ~d +// 4'b1000: AND s & d +// 4'b1001: OR s | d +// 4'b1010: NAND ~(s & d) +// 4'b1011: NOR ~(s | d) +// 4'b1100: XOR s ^ d +// 4'b1101: EQUIV ~(s ^ d) +// 4'b1110: AND_INVERTED ~s & d +// 4'b1111: OR_INVERTED ~s | d +//Bit 10:0 ALU alpha operation +// bit10:8 Blending Equation Math Operation +// 3'b000: ADD As*Fs + Ad*Fd +// 3'b001: SUBTRACT As*Fs - Ad*Fd +// 3'b010: REVERSE SUBTRACT Ad*Fd - As*Fs +// 3'b011: MIN min(As*Fs, Ad*Fd) +// 3'b100: MAX max(As*Fs, Ad*Fd) +// 3'b101: LOGIC OP As op Ad +// bit7:4 Source alpha Blending Factor AFs +// 4'b0000 0 +// 4'b0001 1 +// 4'b0010 As +// 4'b0011 1 - As +// 4'b0100 Ad +// 4'b0101 1 - Ad +// 4'b0110 Ac +// 4'b0111 1 - Ac +// .... reserved +// bit3:0 Destination alpha Blending Factor AFd, when bit10:8 != LOGIC OP +// 4'b0000 0 +// 4'b0001 1 +// 4'b0010 As +// 4'b0011 1 - As +// 4'b0100 Ad +// 4'b0101 1 - Ad +// 4'b0110 Ac +// 4'b0111 1 - Ac +// .... reserved +// bit3:0 logic operations, when bit10:8 == LOGIC OP +// 4'b0000: CLEAR 0 +// 4'b0001: COPY s +// 4'b0010: NOOP d +// 4'b0011: SET 1 +// 4'b0100: COPY_INVERT ~s +// 4'b0101: INVERT ~d +// 4'b0110: AND_REVERSE s & ~d +// 4'b0111: OR_REVERSE s | ~d +// 4'b1000: AND s & d +// 4'b1001: OR s | d +// 4'b1010: NAND ~(s & d) +// 4'b1011: NOR ~(s | d) +// 4'b1100: XOR s ^ d +// 4'b1101: EQUIV ~(s ^ d) +// 4'b1110: AND_INVERTED ~s & d +// 4'b1111: OR_INVERTED ~s | d +#define GE2D_ALU_OP_CTRL ((0x00cc << 2) + 0xff040000) +//bit 31:0 (RGBA,YCBCRA) +#define GE2D_ALU_CONST_COLOR ((0x00cd << 2) + 0xff040000) +//SRC1 Key +//31:0 +#define GE2D_SRC1_KEY ((0x00ce << 2) + 0xff040000) +//SRC1 Key Mask +//31:0 +#define GE2D_SRC1_KEY_MASK ((0x00cf << 2) + 0xff040000) +//SRC2 Key +//31:0 +#define GE2D_SRC2_KEY ((0x00d0 << 2) + 0xff040000) +//SRC2 Key Mask +//31:0 +#define GE2D_SRC2_KEY_MASK ((0x00d1 << 2) + 0xff040000) +//Destination Bit Mask +//31:0 +#define GE2D_DST_BITMASK ((0x00d2 << 2) + 0xff040000) +//Bit 31 DP onoff mode, 0: on_counter means how many pixels will output before ge2d turns off +// 1: on_counter means how many clocks will ge2d turn on before ge2d turns off +//Bit 30:16 DP on counter +//Bit 15 0: vd_format doesnt have onoff mode, 1: vd format has onoff mode +//Bit 14:0 DP off counter +#define GE2D_DP_ONOFF_CTRL ((0x00d3 << 2) + 0xff040000) +//Because there are many coefficients used in the vertical filter and horizontal filters, +//indirect access the coefficients of vertical filter and horizontal filter is used. +//For vertical filter, there are 33x4 coefficients +//For horizontal filter, there are 33x4 coefficients +//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2) +//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not +//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef +//Bit 8 type of index, 0: vertical coef +// 1: horizontal coef +//Bit 6:0 coef index +#define GE2D_SCALE_COEF_IDX ((0x00d4 << 2) + 0xff040000) +//coefficients for vertical filter and horizontal filter +#define GE2D_SCALE_COEF ((0x00d5 << 2) + 0xff040000) +//Bit 24 src2 alpha fill mode: together with GE2D_GEN_CTRL0[4](fill_mode), define what alpha values are used +// for the area outside the clipping window. As below: +// fill_mode=0, alpha_fill_mode=0 : use inner alpha, (or default_alpha if src data have no alpha values); +// fill_mode=0, alpha_fill_mode=1 : use outside_alpha; +// fill_mode=1, alpha_fill_mode=0 : use default_alpha; +// fill_mode=1, alpha_fill_mode=1 : use outside_alpha. +//Bit 23:16 src2 outside alpha +//Bit 8 src1 alpha fill mode, refer to src2 alpha fill mode above. +//Bit 7:0 src1 outside alpha +#define GE2D_SRC_OUTSIDE_ALPHA ((0x00d6 << 2) + 0xff040000) +//Bit 31 antiflick enable +//Bit 24 1: alpha value for the first line use repeated alpha, 0: use bit 23:16 as the first line alpha +//Bit 23:16 register value for the first line alpha when bit 24 is 1 +//Bit 8 1: alpha value for the last line use repeated alpha, 0: use bit 7:0 as the last line alpha +//Bit 7:0 register value for the last line alpha when bit 8 is 1 +#define GE2D_ANTIFLICK_CTRL0 ((0x00d8 << 2) + 0xff040000) +//Bit 25, rgb_sel, 1: antiflick RGBA, 0: antiflick YCbCrA +//Bit 24, cbcr_en, 1: also filter cbcr in case of antiflicking YCbCrA, 0: no filter on cbcr in case of antiflicking YCbCrA +//Bit 23:16, R mult coef for converting RGB to Y +//Bit 15:8, G mult coef for converting RGB to Y +//Bit 7:0, B mult coef for converting RGB to Y +//Y = (R * y_r + G * y_g + B * y_b) / 256 +#define GE2D_ANTIFLICK_CTRL1 ((0x00d9 << 2) + 0xff040000) +//Bit 31:24, Y threhold1, when 0<Y<=th1, use filter0; +//Bit 23:16, color antiflick filter0 n3 +//Bit 15:8, color antiflick filter0 n2 +//Bit 7:0, color antiflick filter0 n1 +//Y = (line_up * n1 + line_center * n2 + line_dn * n3) / 128 +#define GE2D_ANTIFLICK_COLOR_FILT0 ((0x00da << 2) + 0xff040000) +//Bit 31:24, Y threhold2, when th1<Y<=th2, use filter1; +//Bit 23:16, color antiflick filter1 n3 +//Bit 15:8, color antiflick filter1 n2 +//Bit 7:0, color antiflick filter1 n1 +#define GE2D_ANTIFLICK_COLOR_FILT1 ((0x00db << 2) + 0xff040000) +//Bit 31:24, Y threhold3, when th2<Y<=th3, use filter2; Y>th3, use filter3 +//Bit 23:16, color antiflick filter2 n3 +//Bit 15:8, color antiflick filter2 n2 +//Bit 7:0, color antiflick filter2 n1 +#define GE2D_ANTIFLICK_COLOR_FILT2 ((0x00dc << 2) + 0xff040000) +//Bit 23:16, color antiflick filter3 n3 +//Bit 15:8, color antiflick filter3 n2 +//Bit 7:0, color antiflick filter3 n1 +#define GE2D_ANTIFLICK_COLOR_FILT3 ((0x00dd << 2) + 0xff040000) +//Bit 31:24, Alpha threhold1, when 0<Alpha<=th1, use filter0; +//Bit 23:16, Alpha antiflick filter0 n3 +//Bit 15:8, Alpha antiflick filter0 n2 +//Bit 7:0, Alpha antiflick filter0 n1 +//Alpha = (line_up * n1 + line_center * n2 + line_dn * n3) / 128 +#define GE2D_ANTIFLICK_ALPHA_FILT0 ((0x00de << 2) + 0xff040000) +//Bit 31:24, Alpha threhold2, when th1<Alpha<=th2, use filter1; +//Bit 23:16, Alpha antiflick filter1 n3 +//Bit 15:8, Alpha antiflick filter1 n2 +//Bit 7:0, Alpha antiflick filter1 n1 +#define GE2D_ANTIFLICK_ALPHA_FILT1 ((0x00df << 2) + 0xff040000) +//Bit 31:24, Alpha threhold3, when th2<Alpha<=th3, use filter2; Alpha>th3, use filter3 +//Bit 23:16, Alpha antiflick filter2 n3 +//Bit 15:8, Alpha antiflick filter2 n2 +//Bit 7:0, Alpha antiflick filter2 n1 +#define GE2D_ANTIFLICK_ALPHA_FILT2 ((0x00e0 << 2) + 0xff040000) +//Bit 23:16, Alpha antiflick filter3 n3 +//Bit 15:8, Alpha antiflick filter3 n2 +//Bit 7:0, Alpha antiflick filter3 n1 +#define GE2D_ANTIFLICK_ALPHA_FILT3 ((0x00e1 << 2) + 0xff040000) +//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) +//Bit 30:22 din_offset (signed data) +//Bit 21:14 map_coef (unsigned data) +//Bit 13:10 map_sr (unsigned data) +//Bit 9:1 dout_offset (signed data) +//Bit 0 enable +#define GE2D_SRC1_RANGE_MAP_Y_CTRL ((0x00e3 << 2) + 0xff040000) +//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) +//Bit 30:22 din_offset (signed data) +//Bit 21:14 map_coef (unsigned data) +//Bit 13:10 map_sr (unsigned data) +//Bit 9:1 dout_offset (signed data) +//Bit 0 enable +#define GE2D_SRC1_RANGE_MAP_CB_CTRL ((0x00e4 << 2) + 0xff040000) +//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset) +//Bit 30:22 din_offset (signed data) +//Bit 21:14 map_coef (unsigned data) +//Bit 13:10 map_sr (unsigned data) +//Bit 9:1 dout_offset (signed data) +//Bit 0 enable +#define GE2D_SRC1_RANGE_MAP_CR_CTRL ((0x00e5 << 2) + 0xff040000) +//Bit 21:16 src1 prearbitor burst number +//Bit 13:8 src2 prearbitor burst number +//Bit 5:0 dst prearbitor burst number +#define GE2D_ARB_BURST_NUM ((0x00e6 << 2) + 0xff040000) +//each 6bit ID, high 4bit are thread ID, low 2bits are the token +//Bit 21:16 src1 ID +//Bit 13:8 src2 ID +//Bit 5:0 dst ID +#define GE2D_TID_TOKEN ((0x00e7 << 2) + 0xff040000) +//Bit 31:28 dst2_bytemask_val. 1-bit mask for each byte (8-bit). Applicable only if both dst_bitmask_en=1 and dst_bytemask_only=1. +//Bit 27:26, dst2 picture struct, 00: frame, 10:top, 11: bottom +//Bit 25:24, dst2 8bit mode component selection, +// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha +//Bit 22:19 dst2 color_map +// dst2_format=0 : output 8-bit; +// dst2_format=1, dst2_color_map=1: output 16-bit YCbCr 655; +// dst2_format=1, dst2_color_map=2: output 16-bit YCbCr 844; +// dst2_format=1, dst2_color_map=3: output 16-bit YCbCrA 6442; +// dst2_format=1, dst2_color_map=4: output 16-bit YCbCrA 4444; +// dst2_format=1, dst2_color_map=5: output 16-bit YCbCr 565; +// dst2_format=1, dst2_color_map=6: output 16-bit AYCbCr 4444; +// dst2_format=1, dst2_color_map=7: output 16-bit AYCbCr 1555; +// dst2_format=1, dst2_color_map=8: output 16-bit YCbCrA 4642; +// dst2_format=1, dst2_color_map=9: output 16-bit CbCr 88; +// dst2_format=1, dst2_color_map=10:output 16-bit CrCb 88; +// dst2_format=2, dst2_color_map=0: output 24-bit YCbCr 888; +// dst2_format=2, dst2_color_map=1: output 24-bit YCbCrA 5658; +// dst2_format=2, dst2_color_map=2: output 24-bit AYCbCr 8565; +// dst2_format=2, dst2_color_map=3: output 24-bit YCbCrA 6666; +// dst2_format=2, dst2_color_map=4: output 24-bit AYCbCr 6666; +// dst2_format=2, dst2_color_map=5: output 24-bit CrCbY 888; +// dst2_format=3, dst2_color_map=0: output 32-bit YCbCrA 8888; +// dst2_format=3, dst2_color_map=1: output 32-bit AYCbCr 8888; +// dst2_format=3, dst2_color_map=2: output 32-bit ACrCbY 8888; +// dst2_format=3, dst2_color_map=3: output 32-bit CrCbYA 8888. +//Bit 17:16 dst2_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit +//Bit 15 reserved +//Bit 14 dst2_color_round_mode, 0: truncate, 1: + 0.5 rounding +//Bit 13:12, dst2_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation. +//Bit 11:10, dst2_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation. +//Bit 9 reserved +//Bit 8, dst2_enable. 0: disable dst2 (default); 1=enable dst2. +//Bit 7: 6 reserved +//Bit 5: 4, dst1_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation. +//Bit 3: 2, dst1_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation. +//Bit 1 reserved +//Bit 0, dst1_enable. 0: disable dst1; 1=enable dst1 (default). +#define GE2D_GEN_CTRL3 ((0x00e8 << 2) + 0xff040000) +//Read only +// Bit 13:0 ge2d_dst2_status, for debug only +#define GE2D_STATUS2 ((0x00e9 << 2) + 0xff040000) +//Bit 27:26 src1 Y fifo size control, 00: 512, 01: 256, 10: 128 11: 96 +//Bit 25:24 src2 fifo size control, 00: 512, 01: 256, 10: 128 11: 96 +//Bit 23:22 dst1 fifo size control, 00: 512, 01: 256, 10: 128 11: 64 +//Bit 21:20 dst2 fifo size control, 00: 512, 01: 256, 10: 128 11: 64 +//Bit 19:18, dst1 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64 +//Bit 17:16, dst2 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64 +//Bit 15:1, top_wrap_ctrl +//bit 0, if true, disable bug fix about the dp_out_done/scale_out_done(test1823) hang issue when scaling down ratio is high. +#define GE2D_GEN_CTRL4 ((0x00ea << 2) + 0xff040000) +#define GE2D_GCLK_CTRL0 ((0x00ef << 2) + 0xff040000) +#define GE2D_GCLK_CTRL1 ((0x00f0 << 2) + 0xff040000) +#define GE2D_GEN_CTRL5 ((0x00f1 << 2) + 0xff040000) +//Bit 28:20, pre_offset0 +//Bit 18:10, pre_offset1 +//Bit 8:0, pre_offset2 +#define GE2D_MATRIX2_PRE_OFFSET ((0x0090 << 2) + 0xff040000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define GE2D_MATRIX2_COEF00_01 ((0x0091 << 2) + 0xff040000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define GE2D_MATRIX2_COEF02_10 ((0x0092 << 2) + 0xff040000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define GE2D_MATRIX2_COEF11_12 ((0x0093 << 2) + 0xff040000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define GE2D_MATRIX2_COEF20_21 ((0x0094 << 2) + 0xff040000) +//Bit 28:16 coef22 +//Bit 7 input y/cb/cr saturation enable +//Bit 0 conversion matrix enable +#define GE2D_MATRIX2_COEF22_CTRL ((0x0095 << 2) + 0xff040000) +//Bit 28:20, offset0 +//Bit 18:10, offset1 +//Bit 8:0, offset2 +#define GE2D_MATRIX2_OFFSET ((0x0096 << 2) + 0xff040000) +//Bit 19:0, src2 stride size in 64bits +// +// +//Bit 28:20, pre_offset0 +//Bit 18:10, pre_offset1 +//Bit 8:0, pre_offset2 +#define GE2D_MATRIX3_PRE_OFFSET ((0x0097 << 2) + 0xff040000) +//Bit 28:16 coef00 +//Bit 12:0 coef01 +#define GE2D_MATRIX3_COEF00_01 ((0x0098 << 2) + 0xff040000) +//Bit 28:16 coef02 +//Bit 12:0 coef10 +#define GE2D_MATRIX3_COEF02_10 ((0x0099 << 2) + 0xff040000) +//Bit 28:16 coef11 +//Bit 12:0 coef12 +#define GE2D_MATRIX3_COEF11_12 ((0x009a << 2) + 0xff040000) +//Bit 28:16 coef20 +//Bit 12:0 coef21 +#define GE2D_MATRIX3_COEF20_21 ((0x009b << 2) + 0xff040000) +//Bit 28:16 coef22 +//Bit 7 input y/cb/cr saturation enable +//Bit 0 conversion matrix enable +#define GE2D_MATRIX3_COEF22_CTRL ((0x009c << 2) + 0xff040000) +//Bit 28:20, offset0 +//Bit 18:10, offset1 +//Bit 8:0, offset2 +#define GE2D_MATRIX3_OFFSET ((0x009d << 2) + 0xff040000) +// synopsys translate_off +// synopsys translate_on +// +// Closing file: ./ge2d_regs.h +// +// +// Reading file: ./parser_regs.h +// +// +//*************************************************************************** +// Title: parser.h +// +// Author: chong.gu +// +// Created: 17:15:11 06/08/2019 +// +// Description: +// +// Note: +// +// History: +// +//*************************************************************************** +//----------------------------------------------------------- +// PARSER +//----------------------------------------------------------- +// ----------------------------------------------- +// REG_BASE: PARSER_PCBUS_BASE = 0x38 +// ----------------------------------------------- +// bit 31:8 -- es_pack_size +// bit 7:6 -- es_type 00-Video, 01-Audio, 10-Subtitle +// bit 5 -- es_write +// bit 4 -- es_passthrough +// bit 3 -- insert_before_es_write +// bit 2 -- discard_cmd +// bit 1 -- search_cmd +// bit 0 -- Parser Busy +#define PARSER_CONTROL ((0x3860 << 2) + 0xfdf00000) +// Write +// bit 31:0 begin address for parser fetch +// Read +// 32 bit current fetch address +#define PARSER_FETCH_ADDR ((0x3861 << 2) + 0xfdf00000) +// Write +// bit 31 circle buffer indicator +// bit 30 check_buffer_stop_addr +// bit 29:27 fetch endian +// bit 26:0 buffer size ( Bytes ) +// Special command: +// when bit 26:0 == 27'h0 +// then bit 29 -- stream_passthrough_enable +// bit 28:27 -- stream_passthrough_type +// Read +// 6:5 cmd_rd_ptr +// 4:3 cmd_wr_ptr +// 2:0 cmd_number +#define PARSER_FETCH_CMD ((0x3862 << 2) + 0xfdf00000) +// 31:0 stop_fetch_addr +#define PARSER_FETCH_STOP_ADDR ((0x3863 << 2) + 0xfdf00000) +// 31:0 stop_fetch_addr - current_write_addr // read only +#define PARSER_FETCH_LEVEL ((0x3864 << 2) + 0xfdf00000) +// bit 31 - fetch_dma_urgent +// bit 30 - stream_dma_urgent +// bit 29 - force_pfifo_ren +// bit 28 - pfifo_peak_enable +// bit 27 - enable_free_clk_parser_reg +// bit 26 - +// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3) +// bit 23:16 - pfifo_empty_count +// bit 15:12 - max_es_write_cycle (x16x64bits) +// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits ) +// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits ) +// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits +#define PARSER_CONFIG ((0x3865 << 2) + 0xfdf00000) +// bit 24:16 -- pfifo_level +// bit 9:0 -- point to byte address +#define PFIFO_WR_PTR ((0x3866 << 2) + 0xfdf00000) +// bit 9:0 -- point to byte address +#define PFIFO_RD_PTR ((0x3867 << 2) + 0xfdf00000) +// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width +#define PFIFO_DATA ((0x3868 << 2) + 0xfdf00000) +// bit 31:0 -- parser search pattern +#define PARSER_SEARCH_PATTERN ((0x3869 << 2) + 0xfdf00000) +// bit 31:0 -- parser search mask ( 0 - disable bit match test ) +#define PARSER_SEARCH_MASK ((0x386a << 2) + 0xfdf00000) +// bit 31:16 -- parser_int_disable_count +// bit 15:8 -- Parser interrupt enable for host cpu +// bit 7:0 -- Parser interrupt enable for Amrisc +#define PARSER_INT_ENABLE ((0x386b << 2) + 0xfdf00000) +// Bit 7 -- fetch_cmd_finished +// Bit 6:5 -- reserved +// Bit 4 -- parse finished +// Bit 3 -- discard finished +// Bit 2 -- insert zero finished +// Bit 1 -- Action Finished Except Search Start Code +// Bit 0 -- Search match interrupt (StartCode found) +// Read 7:0 int status +// Write will clear (bit based) +#define PARSER_INT_STATUS ((0x386c << 2) + 0xfdf00000) +// 15 - SCR_32_READ_OUT (Read Only) +// 14 - SCR_32_data_valid +// 13 - SCR_32_data +// 12 - SCR_count_en +// 11:0 - SCR90K_DIV +#define PARSER_SCR_CTL ((0x386d << 2) + 0xfdf00000) +// bit 31:0 SCR value +#define PARSER_SCR ((0x386e << 2) + 0xfdf00000) +// bit 31:24 -- insert_loop_number +// bit 23:21 -- +// bit 20:16 -- insert_byte_number +// bit 15:0 -- discard number +#define PARSER_PARAMETER ((0x386f << 2) + 0xfdf00000) +// bit 31:0 -- insert data // write only +// write to PARSER_CONTROL will reset the write position +// continous write to this address can write upto 16 bytes +#define PARSER_INSERT_DATA ((0x3870 << 2) + 0xfdf00000) +// Bit 31:24 -- Reserved Stream_ID +// Bit 23:16 -- Sub Stream_ID +// Bit 15:8 -- Audio Stream_ID +// Bit 7:0 -- Video Stream_ID +#define VAS_STREAM_ID ((0x3871 << 2) + 0xfdf00000) +// Bit 31:0 -- VIDEO_DTS +#define VIDEO_DTS ((0x3872 << 2) + 0xfdf00000) +// Bit 31:0 -- VIDEO_PTS +#define VIDEO_PTS ((0x3873 << 2) + 0xfdf00000) +// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR +#define VIDEO_PTS_DTS_WR_PTR ((0x3874 << 2) + 0xfdf00000) +// Bit 31:0 -- AUDIO_PTS +#define AUDIO_PTS ((0x3875 << 2) + 0xfdf00000) +// Bit 31:0 -- AUDIO_PTS_WR_PTR +#define AUDIO_PTS_WR_PTR ((0x3876 << 2) + 0xfdf00000) +// bit 31:20 -- stream_es_count ( Read Only) +// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only) +// bit 18 -- stream_es_passthrough_enable +// bit 17:16 -- stream_es_passthrough_type +// bit 15:13 -- VIDEO2 Ees_write Endian +// bit 12 -- VIDEO2 using manual read point +// bit 11:9 -- SUB Ees_write Endian +// bit 8 -- SUB using manual read point +// bit 7:5 -- AUDIO Ees_write Endian +// bit 4 -- AUDIO using manual read point +// bit 3:1 -- VIDEO Ees_write Endian +// bit 0 -- VIDEO using manual read point +#define PARSER_ES_CONTROL ((0x3877 << 2) + 0xfdf00000) +// Bit 31:0 PFIFO_MONITOR +#define PFIFO_MONITOR ((0x3878 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_VIDEO DDR Interface +// -------------------------------------------- +// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number +// The Start pointer will automatically be truncated to land on +// an 8-byte boundary. That is, bits [2:0] = 0; +#define PARSER_VIDEO_START_PTR ((0x3880 << 2) + 0xfdf00000) +#define PARSER_VIDEO_END_PTR ((0x3881 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_VIDEO Buffer Level Manager +// -------------------------------------------- +#define PARSER_VIDEO_WP ((0x3882 << 2) + 0xfdf00000) +#define PARSER_VIDEO_RP ((0x3883 << 2) + 0xfdf00000) +#define PARSER_VIDEO_HOLE ((0x3884 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_AUDIO DDR Interface +// -------------------------------------------- +// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number +// The Start pointer will automatically be truncated to land on +// an 8-byte boundary. That is, bits [2:0] = 0; +#define PARSER_AUDIO_START_PTR ((0x3885 << 2) + 0xfdf00000) +#define PARSER_AUDIO_END_PTR ((0x3886 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_AUDIO Buffer Level Manager +// -------------------------------------------- +#define PARSER_AUDIO_WP ((0x3887 << 2) + 0xfdf00000) +#define PARSER_AUDIO_RP ((0x3888 << 2) + 0xfdf00000) +#define PARSER_AUDIO_HOLE ((0x3889 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_SUB DDR Interface +// -------------------------------------------- +// The PARSER_SUB start pointer into DDR memory is a 32-bit number +// The Start pointer will automatically be truncated to land on +// an 8-byte boundary. That is, bits [2:0] = 0; +#define PARSER_SUB_START_PTR ((0x388a << 2) + 0xfdf00000) +#define PARSER_SUB_END_PTR ((0x388b << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_SUB Buffer Level Manager +// -------------------------------------------- +#define PARSER_SUB_WP ((0x388c << 2) + 0xfdf00000) +#define PARSER_SUB_RP ((0x388d << 2) + 0xfdf00000) +#define PARSER_SUB_HOLE ((0x388e << 2) + 0xfdf00000) +// Bit[31] dma_busy +// Bit[30] cur_fetch_or_es_write +// Bit[29:28] reserved +// Bit[27:24] fetch_status +// Bit[23:0] buffer_cycles_left +#define PARSER_FETCH_INFO ((0x388f << 2) + 0xfdf00000) +// Bit[31:28] ctl_status +// Bit[27:24] insert_byte_offset +// Bit[23:0] es_pack_left_cycle +#define PARSER_STATUS ((0x3890 << 2) + 0xfdf00000) +// Bit [31:16] AUDIO_wrap_count +// Bit [15:0] VIDEO_wrap_count +#define PARSER_AV_WRAP_COUNT ((0x3891 << 2) + 0xfdf00000) +// bit[29:24] A_brst_num_parser +// bit[21:16] A_id_parser +// bit[11:0] wrrsp_count_parser +#define WRRSP_PARSER ((0x3892 << 2) + 0xfdf00000) +// `define CSS_cmd 12'h200 // address of css command and indirect register +// `define CSS_cntl 12'h201 // css control register +// `define CSS_data 12'h202 // indirect register +// `define CSS_id1_data 12'h203 // ID data for the first and second bytes +// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes +//CPPM registers +// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control +// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register +// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register +// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register +// `define CPPM_CMD 12'h214 //CPPM command and control register +// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug +// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug +// -------------------------------------------- +// PARSER_VIDEO2 DDR Interface +// -------------------------------------------- +// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number +// The Start pointer will automatically be truncated to land on +// an 8-byte boundary. That is, bits [2:0] = 0; +#define PARSER_VIDEO2_START_PTR ((0x3893 << 2) + 0xfdf00000) +#define PARSER_VIDEO2_END_PTR ((0x3894 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_VIDEO2 Buffer Level Manager +// -------------------------------------------- +#define PARSER_VIDEO2_WP ((0x3895 << 2) + 0xfdf00000) +#define PARSER_VIDEO2_RP ((0x3896 << 2) + 0xfdf00000) +#define PARSER_VIDEO2_HOLE ((0x3897 << 2) + 0xfdf00000) +// Bit [31:16] AUDIO_wrap_count +// Bit [15:0] VIDEO2_wrap_count +#define PARSER_AV2_WRAP_COUNT ((0x3898 << 2) + 0xfdf00000) +//----------------------------------------------------------- +// PARSER_B +//----------------------------------------------------------- +// ----------------------------------------------- +// REG_BASE: PARSER_B_PCBUS_BASE = 0x11 +// ----------------------------------------------- +#define PARSER_B_PARSER_CONTROL ((0x1160 << 2) + 0xfdf00000) +// Write +// bit 31:0 begin address for parser fetch +// Read +// 32 bit current fetch address +#define PARSER_B_PARSER_FETCH_ADDR ((0x1161 << 2) + 0xfdf00000) +// Write +// bit 31 circle buffer indicator +// bit 30 check_buffer_stop_addr +// bit 29:27 fetch endian +// bit 26:0 buffer size ( Bytes ) +// Special command: +// when bit 26:0 == 27'h0 +// then bit 29 -- stream_passthrough_enable +// bit 28:27 -- stream_passthrough_type +// Read +// 6:5 cmd_rd_ptr +// 4:3 cmd_wr_ptr +// 2:0 cmd_number +#define PARSER_B_PARSER_FETCH_CMD ((0x1162 << 2) + 0xfdf00000) +// 31:0 stop_fetch_addr +#define PARSER_B_PARSER_FETCH_STOP_ADDR ((0x1163 << 2) + 0xfdf00000) +// 31:0 stop_fetch_addr - current_write_addr // read only +#define PARSER_B_PARSER_FETCH_LEVEL ((0x1164 << 2) + 0xfdf00000) +// bit 31 - fetch_dma_urgent +// bit 30 - stream_dma_urgent +// bit 29 - force_pfifo_ren +// bit 28 - pfifo_peak_enable +// bit 27 - enable_free_clk_parser_reg +// bit 26 - +// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3) +// bit 23:16 - pfifo_empty_count +// bit 15:12 - max_es_write_cycle (x16x64bits) +// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits ) +// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits ) +// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits +#define PARSER_B_PARSER_CONFIG ((0x1165 << 2) + 0xfdf00000) +// bit 24:16 -- pfifo_level +// bit 9:0 -- point to byte address +#define PARSER_B_PFIFO_WR_PTR ((0x1166 << 2) + 0xfdf00000) +// bit 9:0 -- point to byte address +#define PARSER_B_PFIFO_RD_PTR ((0x1167 << 2) + 0xfdf00000) +// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width +#define PARSER_B_PFIFO_DATA ((0x1168 << 2) + 0xfdf00000) +// bit 31:0 -- parser search pattern +#define PARSER_B_PARSER_SEARCH_PATTERN ((0x1169 << 2) + 0xfdf00000) +// bit 31:0 -- parser search mask ( 0 - disable bit match test ) +#define PARSER_B_PARSER_SEARCH_MASK ((0x116a << 2) + 0xfdf00000) +// bit 31:16 -- parser_int_disable_count +// bit 15:8 -- Parser interrupt enable for host cpu +// bit 7:0 -- Parser interrupt enable for Amrisc +#define PARSER_B_PARSER_INT_ENABLE ((0x116b << 2) + 0xfdf00000) +// Bit 7 -- fetch_cmd_finished +// Bit 6:5 -- reserved +// Bit 4 -- parse finished +// Bit 3 -- discard finished +// Bit 2 -- insert zero finished +// Bit 1 -- Action Finished Except Search Start Code +// Bit 0 -- Search match interrupt (StartCode found) +// Read 7:0 int status +// Write will clear (bit based) +#define PARSER_B_PARSER_INT_STATUS ((0x116c << 2) + 0xfdf00000) +// 15 - SCR_32_READ_OUT (Read Only) +// 14 - SCR_32_data_valid +// 13 - SCR_32_data +// 12 - SCR_count_en +// 11:0 - SCR90K_DIV +#define PARSER_B_PARSER_SCR_CTL ((0x116d << 2) + 0xfdf00000) +// bit 31:0 SCR value +#define PARSER_B_PARSER_SCR ((0x116e << 2) + 0xfdf00000) +// bit 31:24 -- insert_loop_number +// bit 23:21 -- +// bit 20:16 -- insert_byte_number +// bit 15:0 -- discard number +#define PARSER_B_PARSER_PARAMETER ((0x116f << 2) + 0xfdf00000) +// bit 31:0 -- insert data // write only +// write to PARSER_CONTROL will reset the write position +// continous write to this address can write upto 16 bytes +#define PARSER_B_PARSER_INSERT_DATA ((0x1170 << 2) + 0xfdf00000) +// Bit 31:24 -- Reserved Stream_ID +// Bit 23:16 -- Sub Stream_ID +// Bit 15:8 -- Audio Stream_ID +// Bit 7:0 -- Video Stream_ID +#define PARSER_B_VAS_STREAM_ID ((0x1171 << 2) + 0xfdf00000) +// Bit 31:0 -- VIDEO_DTS +#define PARSER_B_VIDEO_DTS ((0x1172 << 2) + 0xfdf00000) +// Bit 31:0 -- VIDEO_PTS +#define PARSER_B_VIDEO_PTS ((0x1173 << 2) + 0xfdf00000) +// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR +#define PARSER_B_VIDEO_PTS_DTS_WR_PTR ((0x1174 << 2) + 0xfdf00000) +// Bit 31:0 -- AUDIO_PTS +#define PARSER_B_AUDIO_PTS ((0x1175 << 2) + 0xfdf00000) +// Bit 31:0 -- AUDIO_PTS_WR_PTR +#define PARSER_B_AUDIO_PTS_WR_PTR ((0x1176 << 2) + 0xfdf00000) +// bit 31:20 -- stream_es_count ( Read Only) +// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only) +// bit 18 -- stream_es_passthrough_enable +// bit 17:16 -- stream_es_passthrough_type +// bit 15:13 -- VIDEO2 Ees_write Endian +// bit 12 -- VIDEO2 using manual read point +// bit 11:9 -- SUB Ees_write Endian +// bit 8 -- SUB using manual read point +// bit 7:5 -- AUDIO Ees_write Endian +// bit 4 -- AUDIO using manual read point +// bit 3:1 -- VIDEO Ees_write Endian +// bit 0 -- VIDEO using manual read point +#define PARSER_B_PARSER_ES_CONTROL ((0x1177 << 2) + 0xfdf00000) +// Bit 31:0 PFIFO_MONITOR +#define PARSER_B_PFIFO_MONITOR ((0x1178 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_VIDEO DDR Interface +// -------------------------------------------- +// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number +// The Start pointer will automatically be truncated to land on +// an 8-byte boundary. That is, bits [2:0] = 0; +#define PARSER_B_PARSER_VIDEO_START_PTR ((0x1180 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_VIDEO_END_PTR ((0x1181 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_VIDEO Buffer Level Manager +// -------------------------------------------- +#define PARSER_B_PARSER_VIDEO_WP ((0x1182 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_VIDEO_RP ((0x1183 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_VIDEO_HOLE ((0x1184 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_AUDIO DDR Interface +// -------------------------------------------- +// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number +// The Start pointer will automatically be truncated to land on +// an 8-byte boundary. That is, bits [2:0] = 0; +#define PARSER_B_PARSER_AUDIO_START_PTR ((0x1185 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_AUDIO_END_PTR ((0x1186 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_AUDIO Buffer Level Manager +// -------------------------------------------- +#define PARSER_B_PARSER_AUDIO_WP ((0x1187 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_AUDIO_RP ((0x1188 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_AUDIO_HOLE ((0x1189 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_SUB DDR Interface +// -------------------------------------------- +// The PARSER_SUB start pointer into DDR memory is a 32-bit number +// The Start pointer will automatically be truncated to land on +// an 8-byte boundary. That is, bits [2:0] = 0; +#define PARSER_B_PARSER_SUB_START_PTR ((0x118a << 2) + 0xfdf00000) +#define PARSER_B_PARSER_SUB_END_PTR ((0x118b << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_SUB Buffer Level Manager +// -------------------------------------------- +#define PARSER_B_PARSER_SUB_WP ((0x118c << 2) + 0xfdf00000) +#define PARSER_B_PARSER_SUB_RP ((0x118d << 2) + 0xfdf00000) +#define PARSER_B_PARSER_SUB_HOLE ((0x118e << 2) + 0xfdf00000) +// Bit[31] dma_busy +// Bit[30] cur_fetch_or_es_write +// Bit[29:28] reserved +// Bit[27:24] fetch_status +// Bit[23:0] buffer_cycles_left +#define PARSER_B_PARSER_FETCH_INFO ((0x118f << 2) + 0xfdf00000) +// Bit[31:28] ctl_status +// Bit[27:24] insert_byte_offset +// Bit[23:0] es_pack_left_cycle +#define PARSER_B_PARSER_STATUS ((0x1190 << 2) + 0xfdf00000) +// Bit [31:16] AUDIO_wrap_count +// Bit [15:0] VIDEO_wrap_count +#define PARSER_B_PARSER_AV_WRAP_COUNT ((0x1191 << 2) + 0xfdf00000) +// bit[29:24] A_brst_num_parser +// bit[21:16] A_id_parser +// bit[11:0] wrrsp_count_parser +#define PARSER_B_WRRSP_PARSER ((0x1192 << 2) + 0xfdf00000) +// `define CSS_cmd 12'h200 // address of css command and indirect register +// `define CSS_cntl 12'h201 // css control register +// `define CSS_data 12'h202 // indirect register +// `define CSS_id1_data 12'h203 // ID data for the first and second bytes +// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes +//CPPM registers +// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control +// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register +// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register +// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register +// `define CPPM_CMD 12'h214 //CPPM command and control register +// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug +// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug +// -------------------------------------------- +// PARSER_VIDEO2 DDR Interface +// -------------------------------------------- +// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number +// The Start pointer will automatically be truncated to land on +// an 8-byte boundary. That is, bits [2:0] = 0; +#define PARSER_B_PARSER_VIDEO2_START_PTR ((0x1193 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_VIDEO2_END_PTR ((0x1194 << 2) + 0xfdf00000) +// -------------------------------------------- +// PARSER_VIDEO2 Buffer Level Manager +// -------------------------------------------- +#define PARSER_B_PARSER_VIDEO2_WP ((0x1195 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_VIDEO2_RP ((0x1196 << 2) + 0xfdf00000) +#define PARSER_B_PARSER_VIDEO2_HOLE ((0x1197 << 2) + 0xfdf00000) +// Bit [31:16] AUDIO_wrap_count +// Bit [15:0] VIDEO2_wrap_count +#define PARSER_B_PARSER_AV2_WRAP_COUNT ((0x1198 << 2) + 0xfdf00000) + + +/*OTP*/ +#define OTP_TEE_REG_BASE (0xFE440000) + +#define OTP_TEE_RDY (0x00 + OTP_TEE_REG_BASE) +#define OTP_TEE_RDY_1 (0x04 + OTP_TEE_REG_BASE) + +#define OTP_TEE_CFG (0x08 + OTP_TEE_REG_BASE) + +#define OTP_TEE_WR_DAT0 (0x10 + OTP_TEE_REG_BASE) +#define OTP_TEE_WR_DAT1 (0x14 + OTP_TEE_REG_BASE) +#define OTP_TEE_WR_DAT2 (0x18 + OTP_TEE_REG_BASE) +#define OTP_TEE_WR_DAT3 (0x1c + OTP_TEE_REG_BASE) + +#define OTP_TEE_RD_DAT0 (0x20 + OTP_TEE_REG_BASE) +#define OTP_TEE_RD_DAT1 (0x24 + OTP_TEE_REG_BASE) +#define OTP_TEE_RD_DAT2 (0x28 + OTP_TEE_REG_BASE) +#define OTP_TEE_RD_DAT3 (0x2c + OTP_TEE_REG_BASE) + + +#define OTP_LIC00 (0x40 + OTP_TEE_REG_BASE) +#define OTP_LIC01 (0x44 + OTP_TEE_REG_BASE) +#define OTP_LIC02 (0x48 + OTP_TEE_REG_BASE) +#define OTP_LIC03 (0x4c + OTP_TEE_REG_BASE) + +#define OTP_LIC10 (0x50 + OTP_TEE_REG_BASE) +#define OTP_LIC11 (0x54 + OTP_TEE_REG_BASE) +#define OTP_LIC12 (0x58 + OTP_TEE_REG_BASE) +#define OTP_LIC13 (0x5c + OTP_TEE_REG_BASE) + +#define OTP_LIC20 (0x60 + OTP_TEE_REG_BASE) +#define OTP_LIC21 (0x64 + OTP_TEE_REG_BASE) +#define OTP_LIC22 (0x68 + OTP_TEE_REG_BASE) +#define OTP_LIC23 (0x6C + OTP_TEE_REG_BASE) + +#define OTP_LIC30 (0x70 + OTP_TEE_REG_BASE) +#define OTP_LIC31 (0x74 + OTP_TEE_REG_BASE) +#define OTP_LIC32 (0x78 + OTP_TEE_REG_BASE) +#define OTP_LIC33 (0x7c + OTP_TEE_REG_BASE) + + +// +// Closing file: ./parser_regs.h +// +#include "fixme.h" +#include "soc_def.h" +#endif // REGISTER_H +
diff --git a/arch/arm/include/asm/arch-sc2/regs.h b/arch/arm/include/asm/arch-sc2/regs.h new file mode 100644 index 0000000..36bbe91 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/regs.h
@@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_REG_H__ +#define __AML_REG_H__ +/* + * all used regs + */ +/* + * ISA_TIMERE use SYSCTRL_TIMERE + * WATCHDOG_CNTL use RESETCTRL_WATCHDOG_CTRL0 + * WATCHDOG_TCNT use RESETCTRL_WATCHDOG_CNT + * WATCHDOG_RST use RESETCTRL_WATCHDOG_CLR + */ +#define ISA_TIMERE ((0x0041 << 2) + 0xfe005800) +#define WATCHDOG_CNTL ((0x0040 << 2) + 0xfe000000) +#define WATCHDOG_TCNT ((0x0042 << 2) + 0xfe000000) +#define WATCHDOG_RST ((0x0043 << 2) + 0xfe000000) + +/* + * SEC_AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4 + * AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4 + * AO_RTI_STATUS_REG3 use SYSCTRL_SEC_STICKY_REG1 + * AO_SEC_SD_CFG15 use SYSCTRL_SEC_STATUS_REG2 + */ +#define SEC_AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800) +#define AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800) +#define AO_RTI_STATUS_REG3 ((0x00e1 << 2) + 0xfe005800) +#define AO_SEC_SD_CFG15 ((0x00c2 << 2) + 0xfe005800) + +/* PREG_STICKY_REG8 use SYSCTRL_STICKY_REG7 + * P_AO_SEC_GP_CFG12 use SYSCTRL_DEBUG_REG6 + * P_AO_SEC_GP_CFG13 use SYSCTRL_DEBUG_REG7 + */ +#define PREG_STICKY_REG8 ((0x00b7 << 2) + 0xfe005800) +#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)((0x0096 << 2) + 0xfe005800) +#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)((0x0097 << 2) + 0xfe005800) + +/* + * P_AO_RTI_PINMUX_REG0 use PADCTRL_PIN_MUX_REG0 + * P_AO_TIMEBASE_CNTL1 use CLKTREE_TIMEBASE_CTRL1 + * AO_UART_WFIFO use UART_B_WFIFO + */ +#define P_AO_RTI_PINMUX_REG0 ((0x0000 << 2) + 0xfe000400) +#define P_AO_TIMEBASE_CNTL1 ((0x0016 << 2) + 0xfe000800) +#define AO_UART_WFIFO ((0x0000 << 2) + 0xfe002000) + +/* + * Not AO watch dog + */ +#define P_WATCHDOG_CNTL (volatile uint32_t *)(WATCHDOG_CNTL) +#define P_WATCHDOG_TCNT (volatile uint32_t *)(WATCHDOG_TCNT) +#define P_WATCHDOG_RST (volatile uint32_t *)(WATCHDOG_RST) +#define P_ISA_TIMERE (volatile uint32_t *)(ISA_TIMERE) + +#endif /* __AML_REG_H__ */
diff --git a/arch/arm/include/asm/arch-sc2/romboot.h b/arch/arm/include/asm/arch-sc2/romboot.h new file mode 100644 index 0000000..2967fbb --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/romboot.h
@@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOOT_ROM_H_ +#define __BOOT_ROM_H_ +#ifndef __ASSEMBLY__ +//#include <stdint.h> +//uint8_t simple_i2c(uint8_t adr); +//void spi_pin_mux(void); +//void spi_init(void); +//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size); +//void udelay(uint32_t usec); +//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size); + +#endif /* ! __ASSEMBLY__ */ +#include "config.h" + +/* Magic number to "boot" up A53 */ +#define AO_SEC_SD_CFG10_CB 0x80000000 + +/*BOOT device and ddr size*/ +/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/ +/*19-8: ddr size, 7-0: board revision*/ +//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h +#define AO_SEC_GP_CFG7_W0_BIT 8 +#define AO_SEC_GP_CFG7_W0 0x100 + +#define BOOT_ID_RESERVED 0 +#define BOOT_ID_EMMC 1 +#define BOOT_ID_NAND 2 +#define BOOT_ID_SPI 3 +#define BOOT_ID_SDCARD 4 +#define BOOT_ID_USB 5 + +#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-sc2/sd_emmc.h b/arch/arm/include/asm/arch-sc2/sd_emmc.h new file mode 100644 index 0000000..82d4fb2 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/sd_emmc.h
@@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __SD_EMMC_H__ +#define __SD_EMMC_H__ + +#include <mmc.h> + +#define SDIO_PORT_A 0 +#define SDIO_PORT_B 1 +#define SDIO_PORT_C 2 + +#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */ +#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */ + +#define MESON_SD_EMMC_CLOCK 0x00 +#define CLK_MAX_DIV GENMASK(5, 0) +#define CLK_MAX_SRC GENMASK(7, 6) +#define Cfg_div 0 +#define Cfg_src 6 +#define Cfg_co_phase 8 +#define Cfg_tx_phase 10 +#define Cfg_rx_phase 12 +#define Cfg_sram_pd 14 +#define Cfg_tx_delay 16 +#define Cfg_rx_delay 22 +#define Cfg_always_on 28 +#define Cfg_irq_sdio_sleep 29 +#define Cfg_irq_sdio_sleep_ds 30 + +#define MESON_SD_EMMC_DELAY1 0x4 +#define DLY_D0_MASK GENMASK(5, 0) +#define DLY_D1_MASK GENMASK(11, 6) +#define DLY_D2_MASK GENMASK(17, 12) +#define DLY_D3_MASK GENMASK(23, 18) +#define DLY_D4_MASK GENMASK(31, 24) +#define Dly_d0 0 +#define Dly_d1 6 +#define Dly_d2 12 +#define Dly_d3 18 +#define Dly_d4 24 + +#define MESON_SD_EMMC_DELAY2 0x8 +#define DLY_D5_MASK GENMASK(5, 0) +#define DLY_D6_MASK GENMASK(11, 6) +#define DLY_D7_MASK GENMASK(17, 12) +#define DLY_D8_MASK GENMASK(23, 18) +#define DLY_D9_MASK GENMASK(31, 24) +#define Dly_d5 0 +#define Dly_d6 6 +#define Dly_d7 12 +#define Dly_d8 18 +#define Dly_d9 24 + +#define MESON_SD_EMMC_ADJUST 0xC +#define CALI_SEL_MASK GENMASK(11, 8) +#define ADJ_DLY_MASK GENMASK(21, 16) +#define Cfg_cali_sel 8 +#define Cfg_cali_en 12 +#define Cfg_adj_en 13 +#define Cfg_cali_rise 14 +#define Cfg_ds_en 15 +#define Cfg_adj_dly 16 +#define Cfg_adj_auto 22 +#define Cfg_adj_init 23 + +#define MESON_SD_EMMC_START 0x40 +#define CFG_DESC_INIT BIT(0) +#define CFG_DESC_BUSY BIT(1) +#define CFG_DESC_ADDR 2 + +#define MESON_SD_EMMC_CFG 0x44 +#define CFG_BUS_WIDTH_MASK GENMASK(1, 0) +#define CFG_BUS_WIDTH_1 0 +#define CFG_BUS_WIDTH_4 1 +#define CFG_BUS_WIDTH_8 2 +#define CFG_DDR BIT(2) +#define CFG_BL_LEN_MASK GENMASK(7, 4) +#define CFG_BL_LEN_SHIFT 4 +#define CFG_BL_LEN_512 (9 << 4) +#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8) +#define CFG_RESP_TIMEOUT_256 (8 << 8) +#define CFG_RC_CC_MASK GENMASK(15, 12) +#define CFG_RC_CC_16 (4 << 12) +#define CFG_SDCLK_ALWAYS_ON BIT(18) +#define CFG_AUTO_CLK BIT(23) + +#define MESON_SD_EMMC_STATUS 0x48 +#define STATUS_MASK GENMASK(15, 0) +#define STATUS_ERR_MASK GENMASK(12, 0) +#define STATUS_RXD_ERR_MASK GENMASK(7, 0) +#define STATUS_TXD_ERR BIT(8) +#define STATUS_DESC_ERR BIT(9) +#define STATUS_RESP_ERR BIT(10) +#define STATUS_RESP_TIMEOUT BIT(11) +#define STATUS_DESC_TIMEOUT BIT(12) +#define STATUS_END_OF_CHAIN BIT(13) + +#define MESON_SD_EMMC_IRQ_EN 0x4c + +#define MESON_SD_EMMC_CMD_CFG 0x50 +#define CMD_CFG_LENGTH_MASK GENMASK(8, 0) +#define CMD_CFG_BLOCK_MODE BIT(9) +#define CMD_CFG_R1B BIT(10) +#define CMD_CFG_END_OF_CHAIN BIT(11) +#define CMD_CFG_TIMEOUT_4S (12 << 12) +#define CMD_CFG_NO_RESP BIT(16) +#define CMD_CFG_NO_CMD BIT(17) +#define CMD_CFG_DATA_IO BIT(18) +#define CMD_CFG_DATA_WR BIT(19) +#define CMD_CFG_RESP_NOCRC BIT(20) +#define CMD_CFG_RESP_128 BIT(21) +#define CMD_CFG_RESP_NUM BIT(22) +#define CMD_CFG_DATA_NUM BIT(23) +#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24) +#define CMD_CFG_CMD_INDEX_SHIFT 24 +#define CMD_CFG_ERR BIT(30) +#define CMD_CFG_OWNER BIT(31) + +#define MESON_SD_EMMC_CMD_ARG 0x54 +#define MESON_SD_EMMC_CMD_DAT 0x58 +#define MESON_SD_EMMC_CMD_RSP 0x5c +#define MESON_SD_EMMC_CMD_RSP1 0x60 +#define MESON_SD_EMMC_CMD_RSP2 0x64 +#define MESON_SD_EMMC_CMD_RSP3 0x68 + +#define SD_EMMC_RXD_ERROR (1 << 0) +#define SD_EMMC_TXD_ERROR (1 << 1) +#define SD_EMMC_DESC_ERROR (1 << 2) +#define SD_EMMC_RESP_CRC_ERROR (1 << 3) +#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4) +#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5) + +//boot from sd or emmc +#define SEC_AO_SEC_GP_CFG0 (SYSCTRL_SEC_STATUS_REG4) +#endif
diff --git a/arch/arm/include/asm/arch-sc2/secure_apb.h b/arch/arm/include/asm/arch-sc2/secure_apb.h new file mode 100644 index 0000000..9ffbe1c --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/secure_apb.h
@@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/regs.h> +#include <asm/arch/register.h> + +#define DMA_BASE (uint32_t)(0xfe440400) + +#define DMA_T0 (uint32_t)(DMA_BASE + 0x00) +#define DMA_T1 (uint32_t)(DMA_BASE + 0x04) +#define DMA_T2 (uint32_t)(DMA_BASE + 0x08) +#define DMA_T3 (uint32_t)(DMA_BASE + 0x0c) +#define DMA_T4 (uint32_t)(DMA_BASE + 0x10) +#define DMA_T5 (uint32_t)(DMA_BASE + 0x14) +#define DMA_STS0 (uint32_t)(DMA_BASE + 0x20) +#define DMA_STS1 (uint32_t)(DMA_BASE + 0x24) +#define DMA_STS2 (uint32_t)(DMA_BASE + 0x28) +#define DMA_STS3 (uint32_t)(DMA_BASE + 0x2c) +#define DMA_STS4 (uint32_t)(DMA_BASE + 0x30) +#define DMA_STS5 (uint32_t)(DMA_BASE + 0x34) +#define DMA_CFG (uint32_t)(DMA_BASE + 0x40) +#define DMA_SEC (uint32_t)(DMA_BASE + 0x44) +#define DMA_END (uint32_t)(DMA_BASE + 0x3ff) + +#define P_DMA_T0 (volatile uint32_t *)(DMA_BASE + 0x00) +#define P_DMA_T1 (volatile uint32_t *)(DMA_BASE + 0x04) +#define P_DMA_T2 (volatile uint32_t *)(DMA_BASE + 0x08) +#define P_DMA_T3 (volatile uint32_t *)(DMA_BASE + 0x0c) +#define P_DMA_T4 (volatile uint32_t *)(DMA_BASE + 0x10) +#define P_DMA_T5 (volatile uint32_t *)(DMA_BASE + 0x14) +#define P_DMA_STS0 (volatile uint32_t *)(DMA_BASE + 0x20) +#define P_DMA_STS1 (volatile uint32_t *)(DMA_BASE + 0x24) +#define P_DMA_STS2 (volatile uint32_t *)(DMA_BASE + 0x28) +#define P_DMA_STS3 (volatile uint32_t *)(DMA_BASE + 0x2c) +#define P_DMA_STS4 (volatile uint32_t *)(DMA_BASE + 0x30) +#define P_DMA_STS5 (volatile uint32_t *)(DMA_BASE + 0x34) +#define P_DMA_CFG (volatile uint32_t *)(DMA_BASE + 0x40) +#define P_DMA_SEC (volatile uint32_t *)(DMA_BASE + 0x44)
diff --git a/arch/arm/include/asm/arch-sc2/soc_def.h b/arch/arm/include/asm/arch-sc2/soc_def.h new file mode 100644 index 0000000..d718d32 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/soc_def.h
@@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __SC2_DEF_H__ +#define __SC2_DEF_H__ + +#include "secure_apb.h" + + +#define SEC_AO_SEC_GP_CFG2 SYSCTRL_SEC_STATUS_REG6 +#define SEC_AO_SEC_SD_CFG15 SYSCTRL_SEC_STATUS_REG31 + +#define SEC_AO_RTI_STATUS_REG3 SYSCTRL_SEC_STICKY_REG1 + + +#define AO_SEC_SD_CFG15 SEC_AO_SEC_SD_CFG15 + +/*for SC2 DSP compatible*/ +#define CLKTREE_DSPA_CLK_CTRL0 CLKCTRL_DSPA_CLK_CTRL0 +#define CLKTREE_DSPB_CLK_CTRL0 CLKCTRL_DSPB_CLK_CTRL0 + +#endif /* __SC2_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-sc2/timer.h b/arch/arm/include/asm/arch-sc2/timer.h new file mode 100644 index 0000000..492cc8d --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/timer.h
@@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TIMER_H +#define __TIMER_H + +#include <asm/arch/romboot.h> +#include <asm/arch/timer.h> +#include <asm/arch/io.h> + +/** + * Get the current timestamp from the system timer. + */ +uint32_t get_time(void); + +/** + * Busy-wait. + * + * @param us Number of microseconds to delay. + */ +void _udelay(unsigned int us); + +#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-sc2/timing.h b/arch/arm/include/asm/arch-sc2/timing.h new file mode 100644 index 0000000..aa0e4db --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/timing.h
@@ -0,0 +1,433 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AML_TIMING_H_ +#define __AML_TIMING_H_ + +#include <asm/arch/ddr_define.h> +#include <asm/arch/types.h> +#include <asm/arch/mnPmuSramMsgBlock_ddr3.h> +#include <asm/arch/mnPmuSramMsgBlock_ddr4.h> +#include <asm/arch/mnPmuSramMsgBlock_ddr4_2d.h> +#include <asm/arch/mnPmuSramMsgBlock_lpddr3.h> +#include <asm/arch/mnPmuSramMsgBlock_lpddr4.h> +#include <asm/arch/mnPmuSramMsgBlock_lpddr4_2d.h> +#include <asm/arch/dev_parameter.h> + +#define BL2_INIT_STAGE_0 0 +#define BL2_INIT_STAGE_1 1 +#define BL2_INIT_STAGE_2 2 +#define BL2_INIT_STAGE_3 3 +#define BL2_INIT_STAGE_4 4 +#define BL2_INIT_STAGE_5 5 +#define BL2_INIT_STAGE_6 6 +#define BL2_INIT_STAGE_7 7 +#define BL2_INIT_STAGE_8 8 +#define BL2_INIT_STAGE_9 9 + +typedef struct bl2_reg { + unsigned int reg; + unsigned int value; + unsigned int mask; + unsigned int flag; + unsigned short udelay; + unsigned short rsv_0; +}__attribute__ ((packed)) bl2_reg_t; + +typedef struct training_delay_set_ps{ + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; +// */ + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + ///* + unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; +// unsigned short rever2; +}__attribute__ ((packed)) training_delay_set_ps_t; + +typedef struct ddr_mrs_reg { + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; +}__attribute__ ((packed)) ddr_mrs_reg_t; + +typedef struct ddr_timing{ + unsigned int identifier; + unsigned int cfg_ddr_mrd; + unsigned int cfg_ddr_rfcab; + unsigned int cfg_ddr_rfcpb; + unsigned int cfg_ddr_rpab; + unsigned int cfg_ddr_rppb; + unsigned int cfg_ddr_rtw; + unsigned int cfg_ddr_rl; + unsigned int cfg_ddr_wl; + unsigned int cfg_ddr_ras; + unsigned int cfg_ddr_rc; + unsigned int cfg_ddr_rcd; + unsigned int cfg_ddr_rrds; + unsigned int cfg_ddr_rrdl; + unsigned int cfg_ddr_faw; + unsigned int cfg_ddr_rtp; + unsigned int cfg_ddr_wr; + unsigned int cfg_ddr_wtrs; + unsigned int cfg_ddr_wtrl; + unsigned int cfg_ddr_ccds; + unsigned int cfg_ddr_ccdl; + unsigned int cfg_ddr_exsr; + unsigned int cfg_ddr_xs; + unsigned int cfg_ddr_xp; + unsigned int cfg_ddr_xpdll; + unsigned int cfg_ddr_zqcs; + unsigned int cfg_ddr_cksre; + unsigned int cfg_ddr_cksrx; + unsigned int cfg_ddr_cke; + unsigned int cfg_ddr_mod; + unsigned int cfg_ddr_dqs; + unsigned int cfg_ddr_rstl; + unsigned int cfg_ddr_zqlat; + unsigned int cfg_ddr_mrr; + unsigned int cfg_ddr_ckesr; + unsigned int cfg_ddr_dpd; + unsigned int cfg_ddr_ckeck; + unsigned int cfg_ddr_refi; + unsigned int cfg_ddr_sr; + unsigned int cfg_ddr_ccdmw; + unsigned int cfg_ddr_escke; + unsigned int cfg_ddr_refi_ddr3; + unsigned int cfg_ddr_dfictrldelay; + unsigned int cfg_ddr_dfiphywrdata; + unsigned int cfg_ddr_dfiphywrlat; + unsigned int cfg_ddr_dfiphyrddataen; + unsigned int cfg_ddr_dfiphyrdlat; + unsigned int cfg_ddr_dfictrlupdmin; + unsigned int cfg_ddr_dfictrlupdmax; + unsigned int cfg_ddr_dfimstrresp; + unsigned int cfg_ddr_dfirefmski; + unsigned int cfg_ddr_dfictrlupdi; + unsigned int cfg_ddr_dfidramclk; + unsigned int cfg_ddr_dfilpresp; + unsigned int cfg_ddr_dfiphymstr; + unsigned int cfg_ddr_rtodt; + unsigned int cfg_ddr_wlmrd; + unsigned int cfg_ddr_wlo; + unsigned int cfg_ddr_al; + unsigned int cfg_ddr_zqcl; + unsigned int cfg_ddr_zqcsi; + unsigned int cfg_ddr_zqreset; + unsigned int cfg_ddr_tdqsck_min; + unsigned int cfg_ddr_tdqsck_max; + //training_delay_set_ps_t cfg_ddr_training_delay_ps; + ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2]; + unsigned int dfi_odt1_config_ps[2]; + //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1; + #if 0 + unsigned int cfg_ddr_mr[8]; + unsigned int cfg_ddr_mr11; + unsigned int cfg_ddr_mr12; + unsigned int cfg_ddr_mr13; + unsigned int cfg_ddr_mr14; + unsigned int cfg_ddr_mr16; + unsigned int cfg_ddr_mr17; + unsigned int cfg_ddr_mr22; + unsigned int cfg_ddr_mr24; + unsigned int cfg_ddr_reserve[5]; + #endif +}__attribute__ ((packed)) ddr_timing_t; + +typedef struct ddr_phy_common_extra_set{ + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; +}__attribute__ ((packed)) ddr_phy_common_extra_set_t; + +typedef struct retraining_set{ + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps; +}__attribute__ ((packed)) retraining_set_t; + +typedef struct ddr_set{ + unsigned int magic; + unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test + //unsigned int rsv_int0; + unsigned int ddr_func; + unsigned char board_id; + //board id reserve,,do not modify + unsigned char version; + // firmware reserve version,,do not modify + unsigned char DramType; + //support DramType should confirm with amlogic + //#define CONFIG_DDR_TYPE_DDR3 0 + //#define CONFIG_DDR_TYPE_DDR4 1 + //#define CONFIG_DDR_TYPE_LPDDR4 2 + //#define CONFIG_DDR_TYPE_LPDDR3 3 + //#define CONFIG_DDR_TYPE_LPDDR2 4 + unsigned char DisabledDbyte; + //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3 + //bit 0 ---use byte 0 ,1 disable byte 0, + //bit 1 ---use byte 1 ,1 disable byte 1, + //bit 2 ---use byte 2 ,1 disable byte 2, + //bit 3 ---use byte 3 ,1 disable byte 3, + unsigned char Is2Ttiming; + //ddr3/ddr3 use 2t timing,now only support 2t timming + unsigned char HdtCtrl; + //training information control,do not modify + unsigned char dram_rank_config; + //support Dram connection type should confirm with amlogic + //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0 + //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1 + //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0 + //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1 + //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode + //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve + //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1 + //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0 + + /* rsv_char0. update for diagnose type define */ + unsigned char diagnose; + + unsigned short soc_data_drv_ohm_ps1; + unsigned short dram_data_drv_ohm_ps1; + unsigned short soc_data_odt_ohm_ps1; + unsigned short dram_data_odt_ohm_ps1; + unsigned short dram_data_wr_odt_ohm_ps1; + #if 0 + /* imem/dmem define */ + unsigned int imem_load_addr; + //system reserve,do not modify + unsigned int dmem_load_addr; + //system reserve,do not modify + unsigned short imem_load_size; + #endif + //system reserve,do not modify + unsigned short dmem_load_size; + //system reserve,do not modify + unsigned int ddr_base_addr; + //system reserve,do not modify + unsigned int ddr_start_offset; + //system reserve,do not modify + + unsigned short dram_cs0_size_MB; + //config cs0 dram size ,like 1G DRAM ,setting 1024 + unsigned short dram_cs1_size_MB; + //config cs1 dram size,like 512M DRAM ,setting 512 + /* align8 */ + + unsigned short training_SequenceCtrl[2]; + //system reserve,do not modify + unsigned char phy_odt_config_rank[2]; + //unsigned char rever1; + //unsigned char rever2; + unsigned short rank1_ca_vref_permil; + //training odt config ,only use for training + // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT + // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT + unsigned int dfi_odt_config; + //normal go status od config,use for normal status + //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. + //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. + //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0. + //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1. + //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0. + //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity. + //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0. + //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. + //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. + //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. + unsigned short DRAMFreq[4]; + //config dram frequency,use DRAMFreq[0],ohter reserve + unsigned char PllBypassEn; + //system reserve,do not modify + unsigned char ddr_rdbi_wr_enable; + //system reserve,do not modify + unsigned char ddr_rfc_type; + //config dram rfc type,according dram type,also can use same dram type max config + //#define DDR_RFC_TYPE_DDR3_512Mbx1 0 + //#define DDR_RFC_TYPE_DDR3_512Mbx2 1 + //#define DDR_RFC_TYPE_DDR3_512Mbx4 2 + //#define DDR_RFC_TYPE_DDR3_512Mbx8 3 + //#define DDR_RFC_TYPE_DDR3_512Mbx16 4 + //#define DDR_RFC_TYPE_DDR4_2Gbx1 5 + //#define DDR_RFC_TYPE_DDR4_2Gbx2 6 + //#define DDR_RFC_TYPE_DDR4_2Gbx4 7 + //#define DDR_RFC_TYPE_DDR4_2Gbx8 8 + //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 + //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 + //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 + unsigned char enable_lpddr4x_mode; + //system reserve,do not modify + /* align8 */ + + unsigned int pll_ssc_mode; + // + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + unsigned short clk_drv_ohm; + //config soc clk pin signal driver stength ,select 20,30,40,60ohm + unsigned short cs_drv_ohm; + //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm + unsigned short ac_drv_ohm; + //config soc normal address command pin driver stength ,select 20,30,40,60ohm + unsigned short soc_data_drv_ohm_p; + //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned short soc_data_drv_ohm_n; + //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned short soc_data_odt_ohm_p; + //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned short soc_data_odt_ohm_n; + //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned short dram_data_drv_ohm; + //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm + unsigned short dram_data_odt_ohm; + //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm + unsigned short dram_ac_odt_ohm; + //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm + unsigned short soc_clk_slew_rate; + //system reserve,do not modify + unsigned short soc_cs_slew_rate; + //system reserve,do not modify + unsigned short soc_ac_slew_rate; + //system reserve,do not modify + unsigned short soc_data_slew_rate; + //system reserve,do not modify + unsigned short vref_output_permil; //phy + //setting same with vref_dram_permil + unsigned short vref_receiver_permil; //soc + //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI + unsigned short vref_dram_permil; + //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI + unsigned short max_core_timmming_frequency; + //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register + /* align8 */ + + unsigned char ac_trace_delay[10]; + unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; + //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ + unsigned char lpddr4_x8_mode; + unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function + //[1],slt test parameter ,use for force delay line offset + //system reserve,do not modify + unsigned short tdqs2dq; + unsigned char dram_data_wr_odt_ohm; + unsigned char bitTimeControl_2d; + //system reserve,do not modify + /* align8 */ + unsigned char char_rev1; + unsigned char training_offset;//char_rev2; + unsigned int ddr_dmc_remap[5]; + unsigned int dram_rtt_nom_wr_park[2]; + //system reserve,do not modify + /* align8 */ + unsigned char ddr_lpddr34_ca_remap[4]; + ////use for lpddr3 /lpddr4 ca training data byte lane remap + unsigned char ddr_lpddr34_dq_remap[32]; + ////use for lpddr3 /lpddr4 ca pinmux remap + unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; + //use for lpddr3 /lpddr4 ca pinmux remap + unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; + unsigned char char_rev3; + unsigned char char_rev4; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; + + //override read bit delay +}__attribute__ ((packed)) ddr_set_t; + +typedef struct board_clk_set{ + unsigned short cpu_clk; + unsigned short dsu_clk; + unsigned short vddee; + unsigned short vcck; + unsigned short pxp; + unsigned char szPad[2]; +}__attribute__ ((packed)) board_clk_set_t; + +typedef struct pll_ctrl{ + /*Enable flag: 0xa1:need set pll in bl2 + 0xa2:need set pll in bl2x + other: no need + */ + unsigned char flag; + /* Delay time for timing sequence in 10us, range [0 .. 255]*/ + unsigned char delay_10u; + /* PLL clock + * syspll [93 .. 6000] + * fixpll [93 .. 6000] + * gp0pll [93 .. 6000] + * gp1pll [93 .. 6000] + * hifipll [375 .. 6000] + */ + unsigned short clkset; + unsigned int pll_para[8]; + unsigned int reserve; +} __attribute__ ((packed)) pll_ctrl_t; + +typedef struct pll_set{ + /*new struct for sc2*/ + pll_ctrl_t sys_pll_ctrl; + pll_ctrl_t fix_pll_ctrl; + pll_ctrl_t gp0_pll_ctrl; + pll_ctrl_t gp1_pll_ctrl; + pll_ctrl_t hifi_pll_ctrl; +}__attribute__ ((packed)) pll_set_t; + +typedef struct bl2_sec_parameter{ + /*new struct for sc2*/ + uint32_t version; + uint32_t bl31_region_start; + uint32_t bl31_region_size; + uint32_t bl32_region_start; + uint32_t bl32_region_size; + + uint32_t RFU[27]; +}__attribute__ ((packed)) sec_parameter_t; + +typedef struct dmem_cfg { + PMU_SMB_DDR3U_1D_t ddr3u; + PMU_SMB_DDR4U_1D_t ddr4u; + PMU_SMB_DDR4U_2D_t ddr4u_2d; + PMU_SMB_LPDDR3_1D_t lpddr3u; + PMU_SMB_LPDDR4_1D_t lpddr4u; + PMU_SMB_LPDDR4_2D_t lpddr4u_2d; +} dmem_cfg_t; + +#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-sc2/tsensor.h b/arch/arm/include/asm/arch-sc2/tsensor.h new file mode 100644 index 0000000..8b365a4 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/tsensor.h
@@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TSENSOR_H__ +#define __TSENSOR_H__ + + +struct tsensor_cali_data { + unsigned int cmd; /* R/W */ + unsigned int offset; + unsigned int size; + unsigned long buffer_phy; + unsigned long retcnt_phy; +}; + + +#define CONFIG_HIGH_TEMP_COOL 90 + +#define T_AVG_NUM 16 /*read temp cnt*/ +#define T_VER_MASK 0x80 +#define T_VALUE_MIN 0x1500 +#define T_VALUE_MAX 0x3500 +#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/ + +#define T_CONTROL_DATA 0x62b +#define T_TSCLK_DATA 0x130 + +#define ts_b 3159 +#define ts_a 9411 +#define ts_m 424 +#define ts_n 324 + +#ifdef CONFIG_AML_TSENSOR +int temp_read_entry(void); +int temp_trim_entry(int tempbase, int tempver); +int temp_cooling_entry(void); +#else +int temp_read_entry(void) +{ + return -1; +} +int temp_trim_entry(int tempbase, int tempver) +{ + return -1; +} +int temp_cooling_entry(void) +{ + return 0; +} +#endif +#endif
diff --git a/arch/arm/include/asm/arch-sc2/types.h b/arch/arm/include/asm/arch-sc2/types.h new file mode 100644 index 0000000..2d362b1 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/types.h
@@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __TYPES_H +#define __TYPES_H + +#ifndef _INT8_T_DECLARED +typedef char int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef short int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef int int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef long int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef unsigned char uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef unsigned short uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef unsigned int uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef unsigned long uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INT8PTR_T_DECLARED +typedef char * int8ptr_t; +#define _INT8PTR_T_DECLARED +#endif + +#ifndef _INT16PTR_T_DECLARED +typedef short * int16ptr_t; +#define _INT16PTR_T_DECLARED +#endif + +#ifndef _INT32PTR_T_DECLARED +typedef int * int32ptr_t; +#define _INT32PTR_T_DECLARED +#endif + +#ifndef _INT64PTR_T_DECLARED +typedef long * int64ptr_t; +#define _INT64PTR_T_DECLARED +#endif + +#ifndef _UINT8PTR_T_DECLARED +typedef unsigned char * uint8ptr_t; +#define _UINT8PTR_T_DECLARED +#endif + +#ifndef _UINT16PTR_T_DECLARED +typedef unsigned short * uint16ptr_t; +#define _UINT16PTR_T_DECLARED +#endif + +#ifndef _UINT32PTR_T_DECLARED +typedef unsigned int * uint32ptr_t; +#define _UINT32PTR_T_DECLARED +#endif + +#ifndef _UINT64PTR_T_DECLARED +typedef unsigned long * uint64ptr_t; +#define _UINT64PTR_T_DECLARED +#endif + +#endif \ No newline at end of file
diff --git a/arch/arm/include/asm/arch-sc2/uart.h b/arch/arm/include/asm/arch-sc2/uart.h new file mode 100644 index 0000000..757dc91 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/uart.h
@@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MESON_FIRM_UART_H_ +#define __MESON_FIRM_UART_H_ +#include <config.h> +#include <common.h> +#include "register.h" +//#include "io.h" +#include <asm/arch/secure_apb.h> + +#ifndef CONFIG_CONS_INDEX +#error Please define CONFIG_CONS_INDEX==[0|1] +#endif + +#if CONFIG_CONS_INDEX==0 +#define UART_PORT_CONS UART_PORT_0 +#elif CONFIG_CONS_INDEX==1 +#define UART_PORT_CONS UART_PORT_1 +#elif CONFIG_CONS_INDEX==2 +#define UART_PORT_CONS UART_PORT_AO +#define USE_AO_UART 1 +#else +#error Please define CONFIG_CONS_INDEX==[0|1] +#endif +/* +#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO) +#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO) +#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO) +#define UART_PORT_AO P_AO_UART_WFIFO + +#define UART_WFIFO (0<<2) +#define UART_RFIFO (1<<2) +#define UART_CONTROL (2<<2) +#define UART_STATUS (3<<2) +#define UART_MISC (4<<2) +*/ + +#include "clock.h" + +#define UART_CLK_SRC CLK81 +#define UART_PORT_0 0xfe001c00 +#define UART_PORT_1 0xfe001c00 +#define UART_PORT_AO 0xfe001c00 +#define UART_WFIFO 0 +#define UART_RFIFO 1 +#define UART_CONTROL 2 +#define UART_STATUS 3 +#define UART_MISC 4 + +#if USE_AO_UART == 1 +#define P_UART(uart_base,reg) (uart_base + (reg<<2)) +#else +#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg) +#endif +#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO) +#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO) + +#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL) + #define UART_CNTL_MASK_BAUD_RATE (0xfff) + #define UART_CNTL_MASK_TX_EN (1<<12) + #define UART_CNTL_MASK_RX_EN (1<<13) + #define UART_CNTL_MASK_2WIRE (1<<15) + #define UART_CNTL_MASK_STP_BITS (3<<16) + #define UART_CNTL_MASK_STP_1BIT (0<<16) + #define UART_CNTL_MASK_STP_2BIT (1<<16) + #define UART_CNTL_MASK_PRTY_EVEN (0<<18) + #define UART_CNTL_MASK_PRTY_ODD (1<<18) + #define UART_CNTL_MASK_PRTY_TYPE (1<<18) + #define UART_CNTL_MASK_PRTY_EN (1<<19) + #define UART_CNTL_MASK_CHAR_LEN (3<<20) + #define UART_CNTL_MASK_CHAR_8BIT (0<<20) + #define UART_CNTL_MASK_CHAR_7BIT (1<<20) + #define UART_CNTL_MASK_CHAR_6BIT (2<<20) + #define UART_CNTL_MASK_CHAR_5BIT (3<<20) + #define UART_CNTL_MASK_RST_TX (1<<22) + #define UART_CNTL_MASK_RST_RX (1<<23) + #define UART_CNTL_MASK_CLR_ERR (1<<24) + #define UART_CNTL_MASK_INV_RX (1<<25) + #define UART_CNTL_MASK_INV_TX (1<<26) + #define UART_CNTL_MASK_RINT_EN (1<<27) + #define UART_CNTL_MASK_TINT_EN (1<<28) + #define UART_CNTL_MASK_INV_CTS (1<<29) + #define UART_CNTL_MASK_MASK_ERR (1<<30) + #define UART_CNTL_MASK_INV_RTS (1<<31) +#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS ) + #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0) + #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8) + #define UART_STAT_MASK_PRTY_ERR (1<<16) + #define UART_STAT_MASK_FRAM_ERR (1<<17) + #define UART_STAT_MASK_WFULL_ERR (1<<18) + #define UART_STAT_MASK_RFIFO_FULL (1<<19) + #define UART_STAT_MASK_RFIFO_EMPTY (1<<20) + #define UART_STAT_MASK_TFIFO_FULL (1<<21) + #define UART_STAT_MASK_TFIFO_EMPTY (1<<22) + #define UART_STAT_MASK_XMIT_BUSY (1<<25) + #define UART_STAT_MASK_RECV_BUSY (1<<26) +#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC ) + + +#ifndef CONFIG_SERIAL_STP_BITS +#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2 +#endif +#if CONFIG_SERIAL_STP_BITS==1 +#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT +#elif CONFIG_SERIAL_STP_BITS==2 +#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT +#else +#error CONFIG_SERIAL_STP_BITS wrong +#endif + + +#ifndef CONFIG_SERIAL_PRTY_TYPE +#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3 +#endif +#if CONFIG_SERIAL_PRTY_TYPE==0 +#define UART_PRTY_BIT 0 +#elif CONFIG_SERIAL_PRTY_TYPE==2 +#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN) +#elif CONFIG_SERIAL_PRTY_TYPE==3 +#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD) +#else +#error CONFIG_SERIAL_PRTY_TYPE wrong +#endif + +#ifndef CONFIG_SERIAL_CHAR_LEN +#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8 +#endif +#if CONFIG_SERIAL_CHAR_LEN==5 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT +#elif CONFIG_SERIAL_CHAR_LEN==6 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT +#elif CONFIG_SERIAL_CHAR_LEN==7 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT +#elif CONFIG_SERIAL_CHAR_LEN==8 +#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT +#else +#error CONFIG_SERIAL_CHAR_LEN wrong +#endif +#define UART_CONTROL_SET(baud,clk81) \ + (((clk81)/(baud*4) -1) \ + | UART_STP_BIT \ + | UART_PRTY_BIT \ + | UART_CHAR_LEN \ + | UART_CNTL_MASK_TX_EN \ + | UART_CNTL_MASK_RX_EN \ + | UART_CNTL_MASK_RST_TX \ + | UART_CNTL_MASK_RST_RX \ + | UART_CNTL_MASK_CLR_ERR ) +#endif
diff --git a/arch/arm/include/asm/arch-sc2/usb.h b/arch/arm/include/asm/arch-sc2/usb.h new file mode 100644 index 0000000..f2669d5 --- /dev/null +++ b/arch/arm/include/asm/arch-sc2/usb.h
@@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__ +#define __ARCH_ARM_MESON_USB_H_U_BOOT__ + +#include <common.h> +#include <asm/types.h> +#include <asm/arch/io.h> +#include <asm/arch/secure_apb.h> +#include <generic-phy.h> +#include <asm-generic/gpio.h> + +#define USB_PHY_PORT_MAX 1 +/* Phy register MACRO definitions */ + +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) + +#define PHYUTMI_OTGDISABLE (1 << 6) +#define PHYUTMI_FORCESUSPEND (1 << 1) +#define PHYUTMI_FORCESLEEP (1 << 0) + +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) +#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) + +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) +#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) + +#define PHYCLKRST_SSC_EN (0x1 << 20) +#define PHYCLKRST_REF_SSP_EN (0x1 << 19) +#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) + +#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) + +#define PHYCLKRST_FSEL_MASK (0x3f << 5) +#define PHYCLKRST_FSEL(_x) ((_x) << 5) +#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) +#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) +#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) +#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) + +#define PHYCLKRST_RETENABLEN (0x1 << 4) + +#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) + +#define PHYCLKRST_PORTRESET (0x1 << 1) +#define PHYCLKRST_COMMONONN (0x1 << 0) + +#define PHYPARAM0_REF_USE_PAD (0x1 << 31) +#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) +#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) + +#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) +#define PHYPARAM1_PCS_TXDEEMPH (0x1c) + +#define PHYTEST_POWERDOWN_SSP (0x1 << 3) +#define PHYTEST_POWERDOWN_HSP (0x1 << 2) + +#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) + +#define FSEL_CLKSEL_24M (0x5) + +#define USB_PHY2_ENABLE 0x10000000 +#define USB_PHY2_RESET 0x20000000 + +/* XHCI PHY register structure */ +#define PHY_REGISTER_SIZE 0x20 + +struct phy_aml_usb2_priv { + unsigned int base_addr; + unsigned int reset_addr; + unsigned int dwc2_a_addr; + unsigned int u2_port_num; + unsigned int usbphy_reset_bit[8]; + unsigned int usb_phy2_pll_base_addr[4]; +}; + +struct phy_aml_usb3_priv { + unsigned int base_addr; + unsigned int usb3_port_num; + struct gpio_desc desc; +}; + +/* Register definitions */ +typedef struct u2p_aml_regs { + volatile uint32_t u2p_r0; + volatile uint32_t u2p_r1; +} u2p_aml_regs_t; + +typedef union u2p_r0 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned host_device:1; + unsigned power_ok:1; + unsigned hast_mode:1; + unsigned POR:1; + unsigned IDPULLUP0:1; + unsigned DRVVBUS0:1; + unsigned reserved:26; + } b; +} u2p_r0_t; + +typedef union u2p_r1 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned phy_rdy:1; + unsigned IDDIG0:1; + unsigned OTGSESSVLD0:1; + unsigned VBUSVALID0:1; + unsigned reserved:28; + } b; +} u2p_r1_t; + + +typedef struct usb_aml_regs { + volatile uint32_t usb_r0; + volatile uint32_t usb_r1; + volatile uint32_t usb_r2; + volatile uint32_t usb_r3; + volatile uint32_t usb_r4; + volatile uint32_t usb_r5; +} usb_aml_regs_t; + +typedef union usb_r0 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved:17; + unsigned p30_lane0_tx2rx_loopback:1; + unsigned p30_lane0_ext_pclk_reg:1; + unsigned p30_pcs_rx_los_mask_val:10; + unsigned u2d_ss_scaledown_mode:2; + unsigned u2d_act:1; + } b; +} usb_r0_t; + +typedef union usb_r1 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned u3h_bigendian_gs:1; + unsigned u3h_pme_en:1; + unsigned u3h_hub_port_overcurrent:3; + unsigned reserved_1:2; + unsigned u3h_hub_port_perm_attach:3; + unsigned reserved_2:2; + unsigned u3h_host_u2_port_disable:2; + unsigned reserved_3:2; + unsigned u3h_host_u3_port_disable:1; + unsigned u3h_host_port_power_control_present:1; + unsigned u3h_host_msi_enable:1; + unsigned u3h_fladj_30mhz_reg:6; + unsigned p30_pcs_tx_swing_full:7; + } b; +} usb_r1_t; + +typedef union usb_r2 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved:20; + unsigned p30_pcs_tx_deemph_3p5db:6; + unsigned p30_pcs_tx_deemph_6db:6; + } b; +} usb_r2_t; + +typedef union usb_r3 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned p30_ssc_en:1; + unsigned p30_ssc_range:3; + unsigned p30_ssc_ref_clk_sel:9; + unsigned p30_ref_ssp_en:1; + unsigned reserved:18; + } b; +} usb_r3_t; + +typedef union usb_r4 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned p21_PORTRESET0:1; + unsigned p21_SLEEPM0:1; + unsigned mem_pd:2; + unsigned p21_only:1; + unsigned reserved:27; + } b; +} usb_r4_t; + +typedef union usb_r5 { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned iddig_sync:1; + unsigned iddig_reg:1; + unsigned iddig_cfg:2; + unsigned iddig_en0:1; + unsigned iddig_en1:1; + unsigned iddig_curr:1; + unsigned usb_iddig_irq:1; + unsigned iddig_th:8; + unsigned iddig_cnt:8; + unsigned reserved:8; + } b; +} usb_r5_t; + +/* usb id mode, only after M2 + mode = 0 : HARDWARE + mode = 1 : SW_HOST + mode = 2 : SW_DEVICE + */ +#define USB_ID_MODE_HARDWARE (1) +#define USB_ID_MODE_SW_HOST (2) +#define USB_ID_MODE_SW_DEVICE (3) +int usb2_phy_tuning(uint32_t phy2_pll_base, int port); +void set_usb_pll(uint32_t phy2_pll_base); +int usb_save_phy_dev (unsigned int number, struct phy *phy); +int usb2_phy_init (struct phy *phy); +unsigned int usb_get_dwc_a_base_addr(void); +unsigned int usb_get_device_mode_phy_base(void); +void usb_phy_tuning_reset(void); +void usb_device_mode_init(void); + +#endif
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 1d4ca29..5944bc8 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c
@@ -333,50 +333,6 @@ debug("## Transferring control to Linux (at address %lx)...\n", (ulong) kernel_entry); bootstage_mark(BOOTSTAGE_ID_RUN_OS); - -#ifdef CONFIG_AML_KASLR_SEED - int node, ret, len; - char *prop, *bootargs; - uint64_t seed; - - node = fdt_path_offset(images->ft_addr, "/chosen"); - if (node < 0) - printf("Can't find /chosen node from DTB\n"); - - bootargs = (char *)fdt_getprop(images->ft_addr, node, "bootargs", &len); - if (!bootargs) - printf("Can't find bootargs property in chosen\n"); - - char *env = env_get("ramdump_enable"); - - if ((bootargs && strstr(bootargs, "ramoops_io_en=1")) || (env && (env[0] == '1'))) { - ret = fdt_appendprop_string(images->ft_addr, node, "bootargs", " nokaslr"); - if (!ret) - printf("Not enable kaslr for debug purpose\n"); - else - printf("Fail to set nokaslr %s\n", fdt_strerror(ret)); - } else { - prop = (char *)fdt_getprop(images->ft_addr, node, "kaslr-seed", NULL); - if (!prop) { - printf("Can't find kaslr-seed property in chosen\n"); - } else { - srand(timer_get_us()); - /* - * random() function use hardware RNG, not software, ignore - * coverity weak cryptor report. - */ - /* coverity[dont_call] */ - seed = (uint64_t)rand(); - - ret = fdt_setprop(images->ft_addr, node, "kaslr-seed", &seed, sizeof(seed)); - if (!ret) - printf("Enable kaslr\n"); - else - printf("Can't set kaslr-seed value in chosen\n"); - } - } -#endif - announce_and_cleanup(fake); /*
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 00c693b..f4a2c16 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig
@@ -59,6 +59,22 @@ help Support Amlogic Meson C1 +config MESON_SC2 + bool "SC2" + select ARM64 + select DM + select DM_SERIAL + help + Support Amlogic Meson SC2 + +config MESON_C2 + bool "C2" + select ARM64 + select DM + select DM_SERIAL + help + Support Amlogic Meson C2 + config MESON_G12A bool "G12A" select ARM64
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index 23462f8..ba2b0a7 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_ARCH_MESON) += $(SOC)/ obj-$(CONFIG_AML_HW_SHA2) += hard_sha2.o +obj-$(CONFIG_AML_ANTIROLLBACK) += anti-rollback.o
diff --git a/arch/arm/mach-meson/a1/Makefile b/arch/arm/mach-meson/a1/Makefile index 3eb4674..a7b0aae 100644 --- a/arch/arm/mach-meson/a1/Makefile +++ b/arch/arm/mach-meson/a1/Makefile
@@ -9,6 +9,6 @@ obj-$(CONFIG_CMD_PLLTEST) += pll.o obj-$(CONFIG_CMD_AML_MTEST) += core.o obj-$(CONFIG_AML_HDMITX) += hdmitx.o -#obj-y += usb.o +obj-y += usb.o obj-$(CONFIG_AML_TSENSOR) += tsensor.o obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/a1/bl31_apis.c b/arch/arm/mach-meson/a1/bl31_apis.c index 8b9eb72..cdbea89 100644 --- a/arch/arm/mach-meson/a1/bl31_apis.c +++ b/arch/arm/mach-meson/a1/bl31_apis.c
@@ -27,6 +27,13 @@ return function_id; } +int32_t set_boot_params(const keymaster_boot_params *boot_params) +{ + /* Fake function for the reason that set_boot_params is not + * supported for this platform */ + return -1; +} + #ifdef CONFIG_EFUSE int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg) {
diff --git a/arch/arm/mach-meson/a1/firmware/acs/acs.ld.S b/arch/arm/mach-meson/a1/firmware/acs/acs.ld.S index 029967a..3e5bf1d 100644 --- a/arch/arm/mach-meson/a1/firmware/acs/acs.ld.S +++ b/arch/arm/mach-meson/a1/firmware/acs/acs.ld.S
@@ -12,6 +12,7 @@ *acs_entry.o(.text*) *(.text*) *(.data*) + *(.ddr_settings*) } //ASSERT(. <= 0xFFFF7000, "timing image has exceeded its limit.")
diff --git a/arch/arm/mach-meson/a1/firmware/acs/acs.mk b/arch/arm/mach-meson/a1/firmware/acs/acs.mk index 2294d53..883a9df 100644 --- a/arch/arm/mach-meson/a1/firmware/acs/acs.mk +++ b/arch/arm/mach-meson/a1/firmware/acs/acs.mk
@@ -1,8 +1,9 @@ -SOURCES += acs.c \ - acs_entry.S +SOURCES += acs_entry.S ifdef CONFIG_MDUMP_COMPRESS SOURCES += ramdump.c endif +SOURCES += acs.c + LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/a1/oscring.c b/arch/arm/mach-meson/a1/oscring.c index b0d029f..837394d 100644 --- a/arch/arm/mach-meson/a1/oscring.c +++ b/arch/arm/mach-meson/a1/oscring.c
@@ -91,7 +91,7 @@ } printf("osc efuse info:\n"); - for (i = 0; i < 4; i++) + for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++) printf("0x%x, ", efuseinfo[i]); printf("\n");
diff --git a/arch/arm/mach-meson/a1/pll.c b/arch/arm/mach-meson/a1/pll.c index b8c258b..501a6ea 100644 --- a/arch/arm/mach-meson/a1/pll.c +++ b/arch/arm/mach-meson/a1/pll.c
@@ -8,7 +8,6 @@ #include <amlogic/cpu_id.h> #include <malloc.h> #include <asm/io.h> -#include <asm/arch/clk_measure.h> #include <asm/arch/secure_apb.h> #include <asm/arch/timer.h> #include <asm/arch/pll.h> @@ -42,6 +41,8 @@ static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg); static int fix_pll_test(void); static int ddr_pll_test(void); +extern unsigned long clk_util_clk_msr(unsigned long clk_mux); + #if 0 static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll_set); static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set);
diff --git a/arch/arm/mach-meson/a1/usb.c b/arch/arm/mach-meson/a1/usb.c new file mode 100644 index 0000000..6ee3ad8 --- /dev/null +++ b/arch/arm/mach-meson/a1/usb.c
@@ -0,0 +1,403 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <bitfield.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <power/regulator.h> +#include <clk.h> +#include <asm/arch/usb.h> +#include <amlogic/cpu_id.h> + +#include <linux/compat.h> +#include <linux/ioport.h> +#include <asm-generic/gpio.h> + +#define U2_CTRL_SLEEP_SHIFT 24 +#define U2_HHI_MEM_PD_MASK 0x3 +#define U2_HHI_MEM_PD_SHIFT 0x0 +#define U2_CTRL_ISO_SHIFT 24 +#define PHY20_RESET_LEVEL_BIT 6 +#define USB_RESET_BIT 4 + +#define USB2_PHY_PLL_OFFSET_40 (0x09400414) +#define USB2_PHY_PLL_OFFSET_44 (0x927E0000) +#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5) + +#define USB2_PHY_PLL_OFFSET_34 (0x78000) + +#define USB2_PHY_PLL_OFFSET_50 (0xfe18) +#define USB2_PHY_PLL_OFFSET_54 (0x2a) + +#define TUNING_DISCONNECT_THRESHOLD 0x34 + +#define P_AO_RTI_GEN_PWR_SLEEP0 0xfe007808 +#define P_AO_RTI_GEN_PWR_ISO0 0xfe007804 +#define P_HHI_MEM_PD_REG0 0xfe007850 + +static struct phy usb_phys[2]; + +int get_usbphy_baseinfo(struct phy *usb_phys) +{ + struct udevice *bus; + struct uclass *uc; + int ret, i; + unsigned int count; + + if (usb_phys[0].dev && usb_phys[1].dev) + return 0; + + ret = uclass_get(UCLASS_USB, &uc); + if (ret) + return ret; + uclass_foreach_dev(bus, uc) { + debug("bus->name=%s, bus->driver->name =%s\n", + bus->name, bus->driver->name); + count = dev_count_phandle_with_args(bus, "phys", "#phy-cells"); + debug("usb phy count=%u\n", count); + if (count <= 0) + return count; + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(bus, i, &usb_phys[i]); + if (ret && ret != -ENOENT) { + pr_err("Failed to get USB PHY%d for %s\n", + i, bus->name); + return ret; + } + ret = generic_phy_getinfo(&usb_phys[i]); + if (ret) + return ret; + } + } + return 0; +} + +static void usb_set_power_domain (void) +{ + writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << U2_CTRL_SLEEP_SHIFT))), + P_AO_RTI_GEN_PWR_SLEEP0); + writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << U2_CTRL_ISO_SHIFT))), + P_AO_RTI_GEN_PWR_ISO0); + writel((readl(P_HHI_MEM_PD_REG0) + & (~(U2_HHI_MEM_PD_MASK << U2_HHI_MEM_PD_SHIFT))), P_HHI_MEM_PD_REG0); + + return; +} + +static void usb_set_clock_freq(unsigned int clock_addr) +{ + unsigned int val = (1 << 8) | (1 << 9) | (0 << 0); + writel(val, (unsigned long)clock_addr); + return; +} + +static void set_pll_Calibration_default(uint32_t phy2_pll_base) +{ + u32 tmp; + + tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8)); + tmp &= 0xfff; + tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) + = tmp; +} + +void usb_reset(unsigned int reset_addr, int bit){ + *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit); +} + +static void usb_enable_phy_pll (void) +{ + *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL |= (1 << PHY20_RESET_LEVEL_BIT); +} + +static void usb_disable_phy_pll (void) +{ + *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL &= ~(1 << PHY20_RESET_LEVEL_BIT); +} + +void set_usb_pll(uint32_t phy2_pll_base) +{ + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40)) + = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) = + USB2_PHY_PLL_OFFSET_44; + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) = + USB2_PHY_PLL_OFFSET_48; + udelay(100); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40)) + = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE)) + & (~(USB_PHY2_RESET))); + + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54)) + = USB2_PHY_PLL_OFFSET_54; + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) = + TUNING_DISCONNECT_THRESHOLD; + + set_pll_Calibration_default(phy2_pll_base); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34)) + = USB2_PHY_PLL_OFFSET_34; + + debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD); +} + +int usb_save_phy_dev (unsigned int number, struct phy *phy) +{ + usb_phys[number].dev = phy->dev; + usb_phys[number].id = phy->id; + return 0; +} + +int usb2_phy_init (struct phy *phy) { + struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev); + struct u2p_aml_regs *u2p_aml_reg; + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + int i,cnt; + + usb_save_phy_dev(0, phy); + usb_enable_phy_pll(); + usb_set_power_domain(); + + priv->clktree_usb_bus_ctrl_addr = dev_read_addr_index(phy->dev, 2 + priv->u2_port_num); + if (priv->clktree_usb_bus_ctrl_addr == FDT_ADDR_T_NONE) { + pr_err("Coun't get clktree_usb_bus_ctrl addr index %d\n", 2 + priv->u2_port_num); + } else { + usb_set_clock_freq(priv->clktree_usb_bus_ctrl_addr); + } + + usb_reset(priv->reset_addr, USB_RESET_BIT); + + udelay(500); + priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT; + + for (i = 0; i < priv->u2_port_num; i++) { + u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE)); + dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0; + dev_u2p_r0.b.host_device= 1; + dev_u2p_r0.b.POR= 0; + u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32; + udelay(10); + /***USB PHY RESET : reset1 and reset1_level both need set ***/ + /***reset1: usb_reset ***/ + /***reset1_level: usb_enable_phy_pll ***/ + usb_reset(priv->reset_addr, priv->usbphy_reset_bit[i]); + udelay(50); + + /* wait for phy ready */ + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + cnt = 0; + while (dev_u2p_r1.b.phy_rdy != 1) { + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + /*we wait phy ready max 1ms, common is 100us*/ + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + } + + for (i = 0; i < priv->u2_port_num; i++) { + debug("------set usb pll\n"); + set_usb_pll(priv->usb_phy2_pll_base_addr[i]); + } + return 0; + +} + +int usb2_phy_tuning(uint32_t phy2_pll_base, int port) +{ + return 0; +} + +/**************************************************************/ +/* device mode config */ +/**************************************************************/ +unsigned int usb_get_dwc_a_base_addr(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->dwc2_a_addr; +} +unsigned int usb_get_device_mode_phy_base(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->usb_phy2_pll_base_addr[0]; +} + +void usb_phy_tuning_reset(void) +{ + return; +} + +void usb_device_mode_init(void){ + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + + usb_r0_t dev_usb_r0; + usb_r4_t dev_usb_r4; + int cnt, ret; + u2p_aml_regs_t * u2p_aml_regs; + usb_aml_regs_t *usb_aml_regs; + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + unsigned int phy_base_addr, reset_addr; + + usb_enable_phy_pll(); + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + if (!usb2_priv || !usb3_priv) { + printf("get usb phy address from dts failed\n"); + return; + } + + u2p_aml_regs = (u2p_aml_regs_t * )(ulong)usb2_priv->base_addr; + usb_aml_regs = (usb_aml_regs_t * )(ulong)usb3_priv->base_addr; + phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[0]; + reset_addr = usb2_priv->reset_addr; + + usb_set_power_domain(); + usb_set_clock_freq(CLKTREE_USB_BUSCLK_CTRL); + + printf("PHY2=0x%08x\n", usb2_priv->base_addr); + if ((*(volatile uint32_t *)((ulong)(phy_base_addr + 0x38))) != 0) { + usb_phy_tuning_reset(); + mdelay(150); + } + + //step 1: usb controller reset + usb_reset(reset_addr, USB_RESET_BIT); + + // step 3: enable usb INT internal USB + dev_usb_r0.d32 = usb_aml_regs->usb_r0; + dev_usb_r0.b.u2d_ss_scaledown_mode = 0; + dev_usb_r0.b.u2d_act = 1; + usb_aml_regs->usb_r0 = dev_usb_r0.d32; + + // step 4: disable usb phy sleep + dev_usb_r4.d32 = usb_aml_regs->usb_r4; + dev_usb_r4.b.p21_SLEEPM0 = 1; + usb_aml_regs->usb_r4 = dev_usb_r4.d32; + + // step 5: config phy21 device mode + dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; + dev_u2p_r0.b.host_device= 0; + dev_u2p_r0.b.POR= 0; + u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; + + udelay(10); + //step 6: phy21 reset + usb_reset(reset_addr, PHY20_RESET_LEVEL_BIT); + udelay(50); + + // step 6: wait for phy ready + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + cnt = 0; + while ((dev_u2p_r1.d32 & 0x00000001) != 1) { + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + + set_usb_pll(phy_base_addr); + //-------------------------------------------------- + + // ------------- usb phy21 initinal end ---------- + + //-------------------------------------------------- + +} + +static void usb_disable_phy(uint32_t phy2_pll_base) +{ + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))= + ((USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET) & (~USB_PHY2_ENABLE)); + udelay(5); +} + +static void usb_print_usb_baseinfo + (struct phy_aml_usb2_priv *usb2_priv, struct phy_aml_usb3_priv *usb3_priv) +{ + if (usb3_priv) { + printf("priv->usb3 port num = %d, config addr=0x%08x\n", + usb3_priv->usb3_port_num, usb3_priv->base_addr); + } + if (usb2_priv) { + printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n", + usb2_priv->base_addr, usb2_priv->reset_addr); + + printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n", + usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0], + usb2_priv->usb_phy2_pll_base_addr[1]); + printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr); + } +} + +int usb_aml_detect_operation(int argc, char * const argv[]) +{ + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + int ret; + + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + + if (argc >= 2) { + if (strncmp(argv[1], "disable", 7) == 0) { + usb_disable_phy_pll(); + usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[0]); + printf("disable USB phy\n"); + return 0; + } + + if (strncmp(argv[1], "info", 4) == 0) { + usb_print_usb_baseinfo(usb2_priv, usb3_priv); + return 0; + } + } + return CMD_RET_USAGE; +}
diff --git a/arch/arm/mach-meson/anti-rollback.c b/arch/arm/mach-meson/anti-rollback.c new file mode 100644 index 0000000..7a84d52 --- /dev/null +++ b/arch/arm/mach-meson/anti-rollback.c
@@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/arch/bl31_apis.h> +#include "anti-rollback.h" + +#define FUNCID_ANTIROLLBACK_VERSION_CHECK 0xb2000010 + +#define FUNCID_AVB_VERSION_SET 0xb2000011 +#define FUNCID_AVB_VERSION_GET 0xb2000012 +#define FUNCID_AVB_LOCK_STATE_GET 0xb2000013 +#define FUNCID_AVB_LOCK 0xb2000014 +#define FUNCID_AVB_UNLOCK 0xb2000015 + +#define IMAGE_VERSION_TYPE_BOOTLOADER 0x001 +#define IMAGE_VERSION_TYPE_RECOVERY 0x002 +#define IMAGE_VERSION_TYPE_BOOT 0x003 + +#define KERNEL_TYPE_UNKNOWN 0x00 +#define KERNEL_TYPE_BOOT 0x01 +#define KERNEL_TYPE_RECOVERY 0x02 + +static uint32_t antirollback_image_version_check(uint32_t type, + uint32_t version) +{ + register uint32_t x0 asm("x0") = FUNCID_ANTIROLLBACK_VERSION_CHECK; + register uint32_t x1 asm("x1") = type; + register uint32_t x2 asm("x2") = version; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2)); + } while (0); + + return x0; +} + +bool check_antirollback(uint32_t kernel_version) +{ + bool ret = true; + uint32_t type = (kernel_version >> 24); + uint32_t version = ((kernel_version << 8) >> 8); + if (KERNEL_TYPE_BOOT == type) { + if (antirollback_image_version_check(IMAGE_VERSION_TYPE_BOOT, + version) != 0) { + printf("checking boot.img version failed\n"); + ret = false; + } + } + else if (KERNEL_TYPE_RECOVERY == type) { + if (antirollback_image_version_check( + IMAGE_VERSION_TYPE_RECOVERY, + version) != 0) { + printf("checking recovery.img version failed\n"); + ret = false; + } + } + else { + printf("the kernel type is unknown\n"); + ret = false; + } + + if (ret) + printf("checking version success\n"); + + return ret; +} + +bool set_avb_antirollback(uint32_t index, uint32_t version) +{ + register uint32_t x0 asm("x0") = FUNCID_AVB_VERSION_SET; + register uint32_t x1 asm("x1") = index; + register uint32_t x2 asm("x2") = version; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2)); + } while (0); + + return 0 == x0; +} + +bool get_avb_antirollback(uint32_t index, uint32_t* version) +{ + register uint32_t x0 asm("x0") = FUNCID_AVB_VERSION_GET; + register uint32_t x1 asm("x1") = index; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x0") + __asmeq("%3", "x1") + "smc #0\n" + : "=r"(x0), "=r"(x1) + : "r"(x0), "r"(x1)); + } while (0); + + if (0 == x0) + *version = x1; + + return 0 == x0; +} + +bool get_avb_lock_state(uint32_t* lock_state) +{ + register uint32_t x0 asm("x0") = FUNCID_AVB_LOCK_STATE_GET; + register uint32_t x1 asm("x1") = 0; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x0") + "smc #0\n" + : "=r"(x0), "=r"(x1) + : "r"(x0)); + } while (0); + + if (0 == x0) + *lock_state = x1; + + return 0 == x0; +} + +bool avb_lock(void) +{ + register uint32_t x0 asm("x0") = FUNCID_AVB_LOCK; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + "smc #0\n" + : "=r"(x0) + : "r"(x0)); + } while (0); + + return 0 == x0; +} + +bool avb_unlock(void) +{ + register uint32_t x0 asm("x0") = FUNCID_AVB_UNLOCK; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + "smc #0\n" + : "=r"(x0) + : "r"(x0)); + } while (0); + + return 0 == x0; +}
diff --git a/arch/arm/mach-meson/c1/Makefile b/arch/arm/mach-meson/c1/Makefile index 3eb4674..a7b0aae 100644 --- a/arch/arm/mach-meson/c1/Makefile +++ b/arch/arm/mach-meson/c1/Makefile
@@ -9,6 +9,6 @@ obj-$(CONFIG_CMD_PLLTEST) += pll.o obj-$(CONFIG_CMD_AML_MTEST) += core.o obj-$(CONFIG_AML_HDMITX) += hdmitx.o -#obj-y += usb.o +obj-y += usb.o obj-$(CONFIG_AML_TSENSOR) += tsensor.o obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/c1/bl31_apis.c b/arch/arm/mach-meson/c1/bl31_apis.c index 03e9f76..e21580d 100644 --- a/arch/arm/mach-meson/c1/bl31_apis.c +++ b/arch/arm/mach-meson/c1/bl31_apis.c
@@ -27,6 +27,13 @@ return function_id; } +int32_t set_boot_params(const keymaster_boot_params *boot_params) +{ + /* Fake function for the reason that set_boot_params is not + * supported for this platform */ + return -1; +} + #ifdef CONFIG_EFUSE int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg) {
diff --git a/arch/arm/mach-meson/c1/firmware/acs/acs.c b/arch/arm/mach-meson/c1/firmware/acs/acs.c index 8c07491..76869b3 100644 --- a/arch/arm/mach-meson/c1/firmware/acs/acs.c +++ b/arch/arm/mach-meson/c1/firmware/acs/acs.c
@@ -47,4 +47,5 @@ .board_id = {0,}, .ddr_struct_size = {0,}, .ddr_struct_org_size = sizeof(ddr_set_t), + .revision = ACS_VERSION, };
diff --git a/arch/arm/mach-meson/c1/firmware/acs/acs.ld.S b/arch/arm/mach-meson/c1/firmware/acs/acs.ld.S index 029967a..3e5bf1d 100644 --- a/arch/arm/mach-meson/c1/firmware/acs/acs.ld.S +++ b/arch/arm/mach-meson/c1/firmware/acs/acs.ld.S
@@ -12,6 +12,7 @@ *acs_entry.o(.text*) *(.text*) *(.data*) + *(.ddr_settings*) } //ASSERT(. <= 0xFFFF7000, "timing image has exceeded its limit.")
diff --git a/arch/arm/mach-meson/c1/firmware/acs/acs.mk b/arch/arm/mach-meson/c1/firmware/acs/acs.mk index 2294d53..0c63194 100644 --- a/arch/arm/mach-meson/c1/firmware/acs/acs.mk +++ b/arch/arm/mach-meson/c1/firmware/acs/acs.mk
@@ -1,8 +1,9 @@ -SOURCES += acs.c \ - acs_entry.S +SOURCES += acs_entry.S ifdef CONFIG_MDUMP_COMPRESS SOURCES += ramdump.c endif +SOURCES += acs.c + LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/c1/oscring.c b/arch/arm/mach-meson/c1/oscring.c index e1b4b4e..fcf6872 100644 --- a/arch/arm/mach-meson/c1/oscring.c +++ b/arch/arm/mach-meson/c1/oscring.c
@@ -97,7 +97,7 @@ } printf("osc efuse info:\n"); - for (i = 0; i < 4; i++) + for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++) printf("0x%x, ", efuseinfo[i]); printf("\n");
diff --git a/arch/arm/mach-meson/c1/pll.c b/arch/arm/mach-meson/c1/pll.c index ee01d0f..b53979f 100644 --- a/arch/arm/mach-meson/c1/pll.c +++ b/arch/arm/mach-meson/c1/pll.c
@@ -48,6 +48,7 @@ static int ddr_pll_test(void); static int gp_pll_test(gp_pll_set_t * gp_pll); static int gp_pll_test_all(void); +extern unsigned long clk_util_clk_msr(unsigned long clk_mux); #if 0 static unsigned int pll_range[PLL_ENUM][2] = { @@ -737,7 +738,6 @@ } static int usbphy_pll_test_all(void) { - unsigned int i=0; unsigned int lock_check = PLL_LOCK_CHECK_MAX; int ret=0; unsigned long usbphy_base_cfg = 0xFE004000;
diff --git a/arch/arm/mach-meson/c1/usb.c b/arch/arm/mach-meson/c1/usb.c new file mode 100644 index 0000000..c1aecdb --- /dev/null +++ b/arch/arm/mach-meson/c1/usb.c
@@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <bitfield.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <power/regulator.h> +#include <clk.h> +#include <asm/arch/usb.h> +#include <amlogic/cpu_id.h> + +#include <linux/compat.h> +#include <linux/ioport.h> +#include <asm-generic/gpio.h> + +#define U2_CTRL_SLEEP_SHIFT 24 +#define U2_HHI_MEM_PD_MASK 0x3 +#define U2_HHI_MEM_PD_SHIFT 0x0 +#define U2_CTRL_ISO_SHIFT 24 +#define PHY20_RESET_LEVEL_BIT 4 +#define USB_RESET_BIT 3 + +#define USB2_PHY_PLL_OFFSET_40 (0x09400414) +#define USB2_PHY_PLL_OFFSET_44 (0x927E0000) +#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5) + +#define USB2_PHY_PLL_OFFSET_34 (0x78000) + + +#define USB2_PHY_PLL_OFFSET_50 (0xfe18) +#define USB2_PHY_PLL_OFFSET_54 (0x2a) + +#define TUNING_DISCONNECT_THRESHOLD 0x34 + +#define P_AO_RTI_GEN_PWR_SLEEP0 0xfe007808 +#define P_AO_RTI_GEN_PWR_ISO0 0xfe007804 +#define P_HHI_MEM_PD_REG0 0xfe007850 + +static struct phy usb_phys[2]; + +int get_usbphy_baseinfo(struct phy *usb_phys) +{ + struct udevice *bus; + struct uclass *uc; + int ret, i; + unsigned int count; + + if (usb_phys[0].dev && usb_phys[1].dev) + return 0; + + ret = uclass_get(UCLASS_USB, &uc); + if (ret) + return ret; + uclass_foreach_dev(bus, uc) { + debug("bus->name=%s, bus->driver->name =%s\n", + bus->name, bus->driver->name); + count = dev_count_phandle_with_args(bus, "phys", "#phy-cells"); + debug("usb phy count=%u\n", count); + if (count <= 0) + return count; + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(bus, i, &usb_phys[i]); + if (ret && ret != -ENOENT) { + pr_err("Failed to get USB PHY%d for %s\n", + i, bus->name); + return ret; + } + ret = generic_phy_getinfo(&usb_phys[i]); + if (ret) + return ret; + } + } + return 0; +} + +static void usb_set_power_domain (void) +{ + writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << U2_CTRL_SLEEP_SHIFT))), + P_AO_RTI_GEN_PWR_SLEEP0); + writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << U2_CTRL_ISO_SHIFT))), + P_AO_RTI_GEN_PWR_ISO0); + writel((readl(P_HHI_MEM_PD_REG0) + & (~(U2_HHI_MEM_PD_MASK << U2_HHI_MEM_PD_SHIFT))), P_HHI_MEM_PD_REG0); + + return; +} + +static void usb_set_clock_freq(unsigned int clock_addr) +{ + unsigned int val = (1 << 8) | (2 << 9) | (9 << 0); + writel(val, (unsigned long)clock_addr); + return; +} + +static void set_pll_Calibration_default(uint32_t phy2_pll_base) +{ + u32 tmp; + + tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8)); + tmp &= 0xfff; + tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) + = tmp; +} + +void usb_reset(unsigned int reset_addr, int bit) +{ + *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit); +} + +static void usb_enable_phy_pll (void) +{ + *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL |= (1 << PHY20_RESET_LEVEL_BIT); +} + +static void usb_disable_phy_pll (void) +{ + *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL &= ~(1 << PHY20_RESET_LEVEL_BIT); +} + +void set_usb_pll(uint32_t phy2_pll_base) +{ + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40)) + = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) = + USB2_PHY_PLL_OFFSET_44; + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) = + USB2_PHY_PLL_OFFSET_48; + udelay(100); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40)) + = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE)) + & (~(USB_PHY2_RESET))); + + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54)) + = USB2_PHY_PLL_OFFSET_54; + set_pll_Calibration_default(phy2_pll_base); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) = + TUNING_DISCONNECT_THRESHOLD; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34)) + = USB2_PHY_PLL_OFFSET_34; + + debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD); +} + +int usb_save_phy_dev (unsigned int number, struct phy *phy) +{ + usb_phys[number].dev = phy->dev; + usb_phys[number].id = phy->id; + return 0; +} + +int usb2_phy_init (struct phy *phy) { + struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev); + struct u2p_aml_regs *u2p_aml_reg; + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + int i,cnt; + + usb_save_phy_dev(0, phy); + usb_enable_phy_pll(); + usb_set_power_domain(); + + priv->clktree_usb_bus_ctrl_addr = dev_read_addr_index(phy->dev, 2 + priv->u2_port_num); + if (priv->clktree_usb_bus_ctrl_addr == FDT_ADDR_T_NONE) { + pr_err("Coun't get clktree_usb_bus_ctrl addr index %d\n", 2 + priv->u2_port_num); + } else { + usb_set_clock_freq(priv->clktree_usb_bus_ctrl_addr); + } + + usb_reset(priv->reset_addr, USB_RESET_BIT); + + udelay(500); + priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT; + + for (i = 0; i < priv->u2_port_num; i++) { + u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE)); + dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0; + dev_u2p_r0.b.host_device= 1; + dev_u2p_r0.b.POR= 0; + u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32; + udelay(10); + /***USB PHY RESET : reset1 and reset1_level both need set ***/ + /***reset1: usb_reset ***/ + /***reset1_level: usb_enable_phy_pll ***/ + usb_reset(priv->reset_addr, priv->usbphy_reset_bit[i]); + udelay(50); + + /* wait for phy ready */ + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + cnt = 0; + while (dev_u2p_r1.b.phy_rdy != 1) { + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + /*we wait phy ready max 1ms, common is 100us*/ + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + } + + for (i = 0; i < priv->u2_port_num; i++) { + debug("------set usb pll\n"); + set_usb_pll(priv->usb_phy2_pll_base_addr[i]); + } + return 0; + +} + +int usb2_phy_tuning(uint32_t phy2_pll_base, int port) +{ + return 0; +} + +/**************************************************************/ +/* device mode config */ +/**************************************************************/ +unsigned int usb_get_dwc_a_base_addr(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->dwc2_a_addr; +} + +unsigned int usb_get_device_mode_phy_base(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->usb_phy2_pll_base_addr[0]; +} + +void usb_phy_tuning_reset(void) +{ + return; +} + +void usb_device_mode_init(void){ + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + + usb_r0_t dev_usb_r0; + usb_r4_t dev_usb_r4; + int cnt, ret; + u2p_aml_regs_t * u2p_aml_regs; + usb_aml_regs_t *usb_aml_regs; + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + unsigned int phy_base_addr, reset_addr; + + usb_enable_phy_pll(); + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + if (!usb2_priv || !usb3_priv) { + printf("get usb phy address from dts failed\n"); + return; + } + + u2p_aml_regs = (u2p_aml_regs_t * )((ulong)usb2_priv->base_addr); + usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr); + phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[0]; + reset_addr = usb2_priv->reset_addr; + + usb_set_power_domain(); + usb_set_clock_freq(CLKTREE_USB_BUSCLK_CTRL); + + printf("PHY2=0x%08x\n", usb2_priv->base_addr); + if ((*(volatile uint32_t *)((ulong)(phy_base_addr + 0x38))) != 0) { + usb_phy_tuning_reset(); + mdelay(150); + } + + //step 1: usb controller reset + usb_reset(reset_addr, USB_RESET_BIT); + + // step 3: enable usb INT internal USB + dev_usb_r0.d32 = usb_aml_regs->usb_r0; + dev_usb_r0.b.u2d_ss_scaledown_mode = 0; + dev_usb_r0.b.u2d_act = 1; + usb_aml_regs->usb_r0 = dev_usb_r0.d32; + + // step 4: disable usb phy sleep + dev_usb_r4.d32 = usb_aml_regs->usb_r4; + dev_usb_r4.b.p21_SLEEPM0 = 1; + usb_aml_regs->usb_r4 = dev_usb_r4.d32; + + // step 5: config phy21 device mode + dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; + dev_u2p_r0.b.host_device= 0; + dev_u2p_r0.b.POR= 0; + u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; + + udelay(10); + //step 6: phy21 reset + usb_reset(reset_addr, PHY20_RESET_LEVEL_BIT); + udelay(50); + + // step 6: wait for phy ready + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + cnt = 0; + while ((dev_u2p_r1.d32 & 0x00000001) != 1) { + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + + set_usb_pll(phy_base_addr); + //-------------------------------------------------- + + // ------------- usb phy21 initinal end ---------- + + //-------------------------------------------------- + +} + +static void usb_disable_phy(uint32_t phy2_pll_base) +{ + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))= + ((USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET) & (~USB_PHY2_ENABLE)); + udelay(5); +} + +static void usb_print_usb_baseinfo + (struct phy_aml_usb2_priv *usb2_priv, struct phy_aml_usb3_priv *usb3_priv) +{ + if (usb3_priv) { + printf("priv->usb3 port num = %d, config addr=0x%08x\n", + usb3_priv->usb3_port_num, usb3_priv->base_addr); + } + if (usb2_priv) { + printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n", + usb2_priv->base_addr, usb2_priv->reset_addr); + + printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n", + usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0], + usb2_priv->usb_phy2_pll_base_addr[1]); + printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr); + } +} + +int usb_aml_detect_operation(int argc, char * const argv[]) +{ + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + int ret; + + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + + if (argc >= 2) { + if (strncmp(argv[1], "disable", 7) == 0) { + usb_disable_phy_pll(); + usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[0]); + printf("disable USB phy\n"); + return 0; + } + + if (strncmp(argv[1], "info", 4) == 0) { + usb_print_usb_baseinfo(usb2_priv, usb3_priv); + return 0; + } + } + return CMD_RET_USAGE; +}
diff --git a/arch/arm/mach-meson/c2/Makefile b/arch/arm/mach-meson/c2/Makefile new file mode 100644 index 0000000..a7b0aae --- /dev/null +++ b/arch/arm/mach-meson/c2/Makefile
@@ -0,0 +1,14 @@ + +obj-y := sdio.o pinctrl_init.o +obj-y += bl31_apis.o +obj-y += cpu_reset.o +obj-y += timer.o +#obj-y += mailbox.o +#obj-y += gate_init.o +#obj-y += power_cal.o +obj-$(CONFIG_CMD_PLLTEST) += pll.o +obj-$(CONFIG_CMD_AML_MTEST) += core.o +obj-$(CONFIG_AML_HDMITX) += hdmitx.o +obj-y += usb.o +obj-$(CONFIG_AML_TSENSOR) += tsensor.o +obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/c2/bl31_apis.c b/arch/arm/mach-meson/c2/bl31_apis.c new file mode 100644 index 0000000..470242c --- /dev/null +++ b/arch/arm/mach-meson/c2/bl31_apis.c
@@ -0,0 +1,519 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* + * Trustzone API + */ + +#include <asm/arch/io.h> +#include <asm/arch/efuse.h> +#include <asm/cache.h> +#include <asm/arch/bl31_apis.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> + +static long sharemem_input_base; +static long sharemem_output_base; + +long get_sharemem_info(unsigned long function_id) +{ + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + : "+r" (function_id)); + + return function_id; +} + +#ifdef CONFIG_EFUSE +int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg) +{ + int ret; + unsigned cmd, offset, size; + unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy); + + if (!sharemem_input_base) + sharemem_input_base = + get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + if (arg->cmd == EFUSE_HAL_API_READ) + cmd = EFUSE_READ; + else if (arg->cmd == EFUSE_HAL_API_WRITE) + cmd = EFUSE_WRITE; + else + cmd = EFUSE_WRITE_PATTERN; + offset = arg->offset; + size = arg->size; + + if (arg->cmd == EFUSE_HAL_API_WRITE) + memcpy((void *)sharemem_input_base, + (const void *)arg->buffer_phy, size); + asm __volatile__("" : : : "memory"); + + register uint64_t x0 asm("x0") = cmd; + register uint64_t x1 asm("x1") = offset; + register uint64_t x2 asm("x2") = size; + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2)); + } while (0); + ret = x0; + *retcnt = x0; + + if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0)) + memcpy((void *)arg->buffer_phy, + (const void *)sharemem_output_base, ret); + + if (!ret) + return -1; + else + return 0; +} + +int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg) +{ + int32_t ret; + unsigned cmd; + + if (arg->cmd == EFUSE_HAL_API_USER_MAX) + cmd = EFUSE_USER_MAX; + + asm __volatile__("" : : : "memory"); + + register uint64_t x0 asm("x0") = cmd; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + "smc #0\n" + : "=r"(x0) + : "r"(x0)); + } while (0); + ret = x0; + + if (!ret) + return -1; + else + return ret; +} + +ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count) +{ + struct efuse_hal_api_arg arg; + unsigned long retcnt; + + if (count != EFUSE_BYTES) + return 0; /* Past EOF */ + + arg.cmd = EFUSE_HAL_API_WRITE_PATTERN; + arg.offset = 0; + arg.size = count; + arg.buffer_phy = (unsigned long)buf; + arg.retcnt_phy = (unsigned long)&retcnt; + int ret; + ret = meson_trustzone_efuse(&arg); + return ret; +} +#endif + +uint64_t meson_trustzone_efuse_check(unsigned char *addr) +{ + uint64_t ret = 0; + struct sram_hal_api_arg arg = {}; + + arg.cmd = SRAM_HAL_API_CHECK_EFUSE; + arg.req_len = 0x1000000; + arg.res_len = 0; + arg.req_phy_addr = (unsigned long)addr; + arg.res_phy_addr = (unsigned long)NULL; + + asm __volatile__("" : : : "memory"); + + register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API; + register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM; + register uint64_t x2 asm("x2") = (unsigned long)(&arg); + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2)); + } while (0); + + ret = x0; + + return ret; +} + +void debug_efuse_cmd(unsigned long cmd) +{ + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + : : "r" (cmd)); +} + +void bl31_debug_efuse_write_pattern(const char *buf) +{ + if (!sharemem_input_base) + sharemem_input_base = + get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); + memcpy((void *)sharemem_input_base, (const void *)buf, 512); + + debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN); +} + +void bl31_debug_efuse_read_pattern(char *buf) +{ + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN); + + memcpy((void *)buf, (const void *)sharemem_output_base, 512); +} + +void aml_set_jtag_state(unsigned state, unsigned select) +{ + uint64_t command; + if (state == JTAG_STATE_ON) + command = JTAG_ON; + else + command = JTAG_OFF; + asm __volatile__("" : : : "memory"); + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : : "r" (command), "r"(select)); +} + +void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value) +{ + register long x0 asm("x0") = 0x82000086; + register long x1 asm("x1") = cmd; + register long x2 asm("x2") = value; + register long x3 asm("x3") = 0; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); +} + +unsigned aml_get_reboot_reason(void) +{ + unsigned reason; + uint64_t ret; + + register uint64_t x0 asm("x0") = GET_REBOOT_REASON; + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + :"+r"(x0)); + ret = x0; + reason = (unsigned)(ret&0xffffffff); + return reason; +} + +void set_viu_probe_enable(void) +{ + register uint64_t x0 asm("x0") = VIU_PREOBE_EN; + + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + :"+r"(x0)); +} + +void power_set_ctl(unsigned int id, unsigned int powerflag) +{ + register long x0 asm("x0") = POWER_CTRL; + register long x1 asm("x1") = id; + register long x2 asm("x2") = powerflag; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2)); +} +void power_set_dsp(unsigned int id, unsigned int powerflag) +{ + register long x0 asm("x0") = DSP_SEC_POWERSET; + register long x1 asm("x1") = id; + register long x2 asm("x2") = powerflag; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2)); +} + +void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0) +{ + register long x0 asm("x0") = START_HIFI4; + register long x1 asm("x1") = id; + register long x2 asm("x2") = addr; + register long x3 asm("x3") = cfg0; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); +} + + +unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2) +{ + register long x0 asm("x0") = function_id; + register long x1 asm("x1") = arg0; + register long x2 asm("x2") = arg1; + register long x3 asm("x3") = arg2; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); + + return function_id; +} + +void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2) +{ + register long x0 asm("x0") = function_id; + register long x1 asm("x1") = arg0; + register long x2 asm("x2") = arg1; + register long x3 asm("x3") = arg2; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); + + return ; +} + +unsigned long aml_sec_boot_check(unsigned long nType, + unsigned long pBuffer, + unsigned long nLength, + unsigned long nOption) +{ + uint64_t ret = 1; + +//#define AML_SECURE_LOG_TE + +#if defined(AML_SECURE_LOG_TE) + #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0); + unsigned nT1,nT2,nT3; +#else + #define AML_GET_TE(...) +#endif + + AML_GET_TE(nT1); + + asm __volatile__("" : : : "memory"); + + register uint64_t x0 asm("x0") = AML_DATA_PROCESS; + register uint64_t x1 asm("x1") = nType; + register uint64_t x2 asm("x2") = pBuffer; + register uint64_t x3 asm("x3") = nLength; + register uint64_t x4 asm("x4") = nOption; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + __asmeq("%4", "x3") + __asmeq("%5", "x4") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4)); + } while (0); + + ret = x0; + + AML_GET_TE(nT2);; + + flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength); + + AML_GET_TE(nT3); + +#if defined(AML_SECURE_LOG_TE) + printf("aml log : dec use %d(us) , flush cache used %d(us)\n", + nT2 - nT1, nT3 - nT2); +#endif + + return ret; +} + +void set_usb_boot_function(unsigned long command) +{ + register long x0 asm("x0") = SET_USB_BOOT_FUNC; + register long x1 asm("x1") = command; + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r" (x0) + : "r" (x1)); +} + +void set_boot_first_timeout(uint64_t arg0) +{ + register long x0 asm("x0") = SET_BOOT_FIRST; + register long x1 asm("x1") = arg0; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r" (x0) + : "r" (x1)); +} +void aml_system_off(void) +{ + /* TODO: Add poweroff capability */ + aml_reboot(0x82000042, 1, 0, 0); + aml_reboot(0x84000008, 0, 0, 0); +} + +int __get_chip_id(unsigned char *buff, unsigned int size) +{ + if (buff == NULL || size < 16) + return -1; + + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + if (sharemem_output_base) { + register long x0 asm("x0") = GET_CHIP_ID; + register long x1 asm("x1") = 2; + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r" (x0) + : "r" (x1)); + + if (x0 == 0) { + int version = *((unsigned int *)sharemem_output_base); + + if (version == 2) { + memcpy(buff, (void *)sharemem_output_base + 4, 16); + } + else { + /** + * Legacy 12-byte chip ID read out, transform data + * to expected order format. + */ + uint32_t chip_info = 0;//readl(P_AO_SEC_SD_CFG8); + uint8_t *ch; + int i; + + ((uint32_t *)buff)[0] = + ((chip_info & 0xff000000) | // Family ID + ((chip_info << 8) & 0xff0000) | // Chip Revision + ((chip_info >> 8) & 0xff00)); // Package ID + + ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]); + + /* Transform into expected order for display */ + ch = (uint8_t *)(sharemem_output_base + 4); + for (i = 0; i < 12; i++) + buff[i + 4] = ch[11 - i]; + } + + return 0; + } + } + + return -1; +} + +int bl31_get_cornerinfo(uint8_t *outbuf, int size) +{ + int buff_len = 0; + + if (outbuf == NULL) { + printf("BL33: corner efuse info storebuf is NULL\n"); + return -1; + } + + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + if (sharemem_output_base) { + register long x0 asm("x0") = OSCRING_EFUSE_GET; + register long x1 asm("x1") = size; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r" (x0) + : "r" (x1)); + } while(0); + buff_len = x0; + if (buff_len <= size) { + memcpy(outbuf, (void *)sharemem_output_base, buff_len); + return 0; + } else { + printf("BL33: corner efuse info buf len %d over storebuf size %d\n", buff_len, size); + return -1; + } + } + return -1; +} + +unsigned aml_get_dvfs_id(void) +{ + unsigned dvfs_id; + uint64_t ret; + + register uint64_t x0 asm("x0") = GET_DVFS_TABLE_INDEX; + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + :"+r"(x0)); + ret = x0; + dvfs_id = (unsigned)(ret&0xffffffff); + return dvfs_id; +}
diff --git a/arch/arm/mach-meson/c2/core.c b/arch/arm/mach-meson/c2/core.c new file mode 100644 index 0000000..8640828 --- /dev/null +++ b/arch/arm/mach-meson/c2/core.c
@@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/types.h> +#include <asm/arch/cpu.h> +#include <common.h> + +const unsigned int core_map[] = { + 0x0, + 0x1, + 0x2, + 0x3, +}; + +int get_core_mpidr(unsigned int cpuid) +{ + unsigned int coremax = (unsigned int)(sizeof(core_map)/sizeof(unsigned int)); + + if (cpuid >= coremax) + return -1; + return core_map[cpuid]; +} + +int get_core_idx(unsigned int mpidr) +{ + unsigned int clusterid, cpuid; + + cpuid = mpidr & 0xff; + clusterid = mpidr & 0xff00; + + cpuid += (clusterid >> 6); + + if (cpuid >= NR_CPUS) + return -1; + + return cpuid; +} + +int get_core_max(void) +{ + return (sizeof(core_map)/sizeof(unsigned int)); +}
diff --git a/arch/arm/mach-meson/c2/cpu_reset.c b/arch/arm/mach-meson/c2/cpu_reset.c new file mode 100644 index 0000000..ca0a42d --- /dev/null +++ b/arch/arm/mach-meson/c2/cpu_reset.c
@@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/types.h> +#include <asm/arch/romboot.h> +#include <asm/arch/cpu_reset.h> +#include <asm/arch/io.h> +#include <asm/arch/timer.h> +#include <dm.h> +#include <wdt.h> + +/* + *GPIOE_0 VDDEE_PWM + *GPIOE_1 VDDCPU_PWM + * */ +void set_pwm_to_input(void) +{ + //hxbao, need fine tune + #if 0 + unsigned int val; + + val = readl(AO_RTI_PINMUX_REG1); + val &= ~(0xff << 16); + writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */ + val = readl(AO_GPIO_O_EN_N); + val &= ~(0x3 << 16); + val |= 0x3 << 16; + writel(val, AO_GPIO_O_EN_N);/* set input mode */ + val = readl(AO_RTI_PULL_UP_EN_REG); + val &= ~(0x3 << 16); + writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */ + #endif +} + +void reset_system(void) +{ + struct udevice *watchdog_devp; + int ret; + + set_pwm_to_input(); + + _udelay(10000); //wait print + + ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp); + if (ret < 0) { + printf("failed to reset system because can't get wdt device\n"); + return; + } + wdt_start(watchdog_devp, 0, 0); + while (1); +} + +/* uboot reset interface */ +void reset_cpu(unsigned long flag){ + reset_system(); +}
diff --git a/arch/arm/mach-meson/c2/firmware/acs/Makefile b/arch/arm/mach-meson/c2/firmware/acs/Makefile new file mode 100644 index 0000000..82df695 --- /dev/null +++ b/arch/arm/mach-meson/c2/firmware/acs/Makefile
@@ -0,0 +1,435 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# Default values for build configurations +# + +#export CROSS_COMPILE=/opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf- +pes_parent_dir:=$(shell pwd)/$(lastword $(MAKEFILE_LIST)) +pes_parent_dir:=$(shell dirname $(pes_parent_dir)) +sdk_dir=${pes_parent_dir}/../../../../../../../ +export CROSS_COMPILE=${sdk_dir}amlogic/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf- + +include $(buildsrc)/config.mk +include $(buildtree)/include/autoconf.mk +include $(buildtree)/.config + +# Build verbosity +V := 0 +# Debug build +BUILD_TYPE := ${BL2_BUILD_TYPE} +# Build architecture +ARCH := aarch64 +# Build platform +#DEFAULT_PLAT := gx +PLAT := ${SOC} +export PLAT +# SPD choice +SPD := none +# Base commit to perform code check on +BASE_COMMIT := origin/master +# NS timer register save and restore +NS_TIMER_SWITCH := 0 +# By default, Bl1 acts as the reset handler, not BL31 +RESET_TO_BL31 := 0 + +# Checkpatch ignores +CHECK_IGNORE = --ignore COMPLEX_MACRO + +CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE} +CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE} + +ifeq (${V},0) + Q=@ + CHECKCODE_ARGS += --no-summary --terse +else + Q= +endif +export Q + +ifeq (${GIT_VERSION},) + GIT_VERSION := $(shell git describe --abbrev=7 --dirty --always --tags) +endif +ifeq (${BUILDER},) + BUILDER := ${USER}@$(shell hostname) +endif + +BL_COMMON_SOURCES := common/bl_common.c \ + common/debug.c \ + lib/aarch64/cache_helpers.S \ + lib/aarch64/misc_helpers.S \ + lib/aarch64/tlb_helpers.S \ + lib/aarch64/xlat_helpers.c \ + lib/stdlib/std.c \ + lib/io_storage.c \ + plat/common/aarch64/platform_helpers.S + +BUILD_BASE := $(buildtree)/firmware +#BUILD_PLAT := ${BUILD_BASE}/${PLAT} +BUILD_PLAT := $(buildtree)/board/${BOARDDIR}/firmware +#BUILD_PLAT := $(buildtree)/${BOARDDIR}/firmware + +# Convenience function for adding build definitions +# $(eval $(call add_define,FOO)) will have: +# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +# Convenience function for verifying option has a boolean value +# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1 +define assert_boolean +$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean)) +endef + +ifeq (${PLAT},) + $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.") +endif + +all: msg_start + +msg_start: + @echo "Building ${BOARDDIR}/acs.bin" + +#include plat/${PLAT}/platform.mk +#ifdef BL2_SOURCES +NEED_BL2 := yes +include acs.mk +#endif + +# Include SPD Makefile if one has been specified +ifneq (${SPD},none) + # We expect to locate an spd.mk under the specified SPD directory + SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m") + + ifeq (${SPD_MAKE},) + $(error Error: No services/spd/${SPD}/${SPD}.mk located) + endif + $(info Including ${SPD_MAKE}) + include ${SPD_MAKE} + + # If there's BL32 companion for the chosen SPD, and the SPD wants to build the + # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32 + # variable to "yes" +endif + +.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip +.SUFFIXES: + +INCLUDES += -Iinclude/bl2 \ + -Iinclude/bl31 \ + -Iinclude/common \ + -Iinclude/drivers \ + -Iinclude/drivers/arm \ + -Iinclude/drivers/serial \ + -Iinclude/lib \ + -Iinclude/lib/aarch64 \ + -Iinclude/plat/common \ + -Iinclude/stdlib \ + -Iinclude/stdlib/sys \ + ${PLAT_INCLUDES} \ + ${SPD_INCLUDES} + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +else +CFLAGS += -g +ASFLAGS += -g -Wa,--gdwarf-2 +endif + +# Process NS_TIMER_SWITCH flag +$(eval $(call assert_boolean,NS_TIMER_SWITCH)) +$(eval $(call add_define,NS_TIMER_SWITCH)) + +# Process RESET_TO_BL31 flag +$(eval $(call assert_boolean,RESET_TO_BL31)) +$(eval $(call add_define,RESET_TO_BL31)) + +VPATH_LIST = $(buildsrc)/board/$(BOARDDIR) +#VPATH_LIST = $(buildsrc)/$(BOARDDIR) +VPATH_LIST:=$(VPATH_LIST:%=%/firmware/) + +vpath %.c $(VPATH_LIST) + +ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \ + -mgeneral-regs-only -D__ASSEMBLY__ \ + ${DEFINES} ${INCLUDES} +CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \ + -Werror -mgeneral-regs-only -std=c99 -c -Os \ + ${DEFINES} ${INCLUDES} $(VPATH_LIST:%=-I%) +CFLAGS += -ffunction-sections -fdata-sections +ASFLAGS += ${FIRMWARE_CPPFLAGS} +CFLAGS += ${FIRMWARE_CPPFLAGS} +CFLAGS += -Wno-unused + +LDFLAGS += --fatal-warnings -O1 +LDFLAGS += --gc-sections + +CC := ${CROSS_COMPILE}gcc +CPP := ${CROSS_COMPILE}cpp +AS := ${CROSS_COMPILE}gcc +AR := ${CROSS_COMPILE}ar +LD := ${CROSS_COMPILE}ld +OC := ${CROSS_COMPILE}objcopy +OD := ${CROSS_COMPILE}objdump +NM := ${CROSS_COMPILE}nm +PP := ${CROSS_COMPILE}gcc -E ${CFLAGS} + +# Variables for use with Firmware Image Package +FIPTOOLPATH ?= tools/fip_create +FIPTOOL ?= ${FIPTOOLPATH}/fip_create +fiptool: ${FIPTOOL} +fip: ${BUILD_PLAT}/fip.bin + +locate-checkpatch: +ifndef CHECKPATCH + $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl") +else +ifeq (,$(wildcard ${CHECKPATCH})) + $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl") +endif +endif + +clean: + @echo " CLEAN" + ${Q}rm -rf ${BUILD_PLAT} + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean + +realclean distclean: + @echo " REALCLEAN" + ${Q}rm -rf ${BUILD_BASE} + ${Q}rm -f ${CURDIR}/cscope.* + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean + +checkcodebase: locate-checkpatch + @echo " CHECKING STYLE" + @if test -d .git ; then \ + git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \ + else \ + find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \ + fi + +checkpatch: locate-checkpatch + @echo " CHECKING STYLE" + @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true + +${FIPTOOL}: + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} + @echo + @echo "Built $@ successfully" + @echo + +define match_goals +$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS)))) +endef + +# List of rules that involve building things +BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip + +# Does the list of goals specified on the command line include a build target? +ifneq ($(call match_goals,${BUILD_TARGETS}),) +IS_ANYTHING_TO_BUILD := 1 +endif + +define MAKE_C + +$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) +$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) + +$(OBJ) : $(2) + @echo " CC $$<" + $$(Q)$$(CC) $$(CFLAGS) -c $$< -o $$@ + + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $(1) + $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_S + +$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) +$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) + +$(OBJ) : $(2) + @echo " AS $$<" + $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@ + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $(1) + $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_LD + +$(eval PREREQUISITES := $(1).d) + +$(1) : $(2) + @echo " PP $$<" + $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$< + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $$(dir $$@) + $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_OBJS + $(eval C_OBJS := $(filter %.c,$(2))) + $(eval REMAIN := $(filter-out %.c,$(2))) + $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj)))) + + $(eval S_OBJS := $(filter %.S,$(REMAIN))) + $(eval REMAIN := $(filter-out %.S,$(REMAIN))) + $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj)))) + + $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN))) +endef + + +# NOTE: The line continuation '\' is required in the next define otherwise we +# end up with a line-feed characer at the end of the last c filename. +# Also bare this issue in mind if extending the list of supported filetypes. +define SOURCES_TO_OBJS + $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \ + $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1)))) +endef + +define MAKE_BL + $(eval BUILD_DIR := ${BUILD_PLAT}) + $(eval SOURCES := $(SOURCES)) + $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES)))) + $(eval LINKERFILE := $(BUILD_DIR)/acs.ld) + $(eval MAPFILE := $(BUILD_DIR)/acs.map) + $(eval ELF := $(BUILD_DIR)/acs.elf) + $(eval DUMP := $(BUILD_DIR)/acs.dump) + $(eval BIN := $(BUILD_DIR)/acs.bin) + + $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES))) + $(eval $(call MAKE_LD,$(LINKERFILE),$(LINKERFILE_T))) + +$(BUILD_DIR) : + $$(Q)mkdir -p "$$@" + +$(ELF) : $(OBJS) $(LINKERFILE) + @echo " LD $$@" + @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__". \\nver:${GIT_VERSION} - ${BUILDER}";' | \ + $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o + $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \ + $(BUILD_DIR)/build_message.o $(OBJS) + +$(DUMP) : $(ELF) + @echo " OD $$@" + $${Q}$${OD} -dxS $$< > $$@ + +$(BIN) : $(ELF) + @echo " BIN $$@" + $$(Q)$$(OC) -O binary $$< $$@ + @echo + @echo "Built $$@ successfully" + @echo + +.PHONY : bl$(1) +bl$(1) : $(BUILD_DIR) $(DUMP) $(BIN) + +all : bl$(1) + +$(eval FIP_DEPS += $(if $2,$(BIN),)) +$(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),)) + +endef + +ifeq (${NEED_BL2},yes) +$(eval $(call MAKE_BL,2,in_fip)) +endif + +${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL} + $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd")) + ${Q}${FIPTOOL} --dump \ + ${FIP_ARGS} \ + --bl33 ${BL33} \ + $@ + @echo + @echo "Built $@ successfully" + @echo + + +cscope: + @echo " CSCOPE" + ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files + ${Q}cscope -b -q -k + +help: + @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>" + @echo "" + @echo "PLAT is used to specify which platform you wish to build." + @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}" + @echo "" + @echo "Supported Targets:" + @echo " all Build the BL1, BL2 and BL31 binaries" + @echo " bl1 Build the BL1 binary" + @echo " bl2 Build the BL2 binary" + @echo " bl31 Build the BL31 binary" + @echo " checkcodebase Check the coding style of the entire source tree" + @echo " checkpatch Check the coding style on changes in the current" + @echo " branch against BASE_COMMIT (default origin/master)" + @echo " clean Clean the build for the selected platform" + @echo " cscope Generate cscope index" + @echo " distclean Remove all build artifacts for all platforms" + @echo " fiptool Build the Firmware Image Package(FIP) creation tool" + @echo "" + @echo "note: most build targets require PLAT to be set to a specific platform." + @echo "" + @echo "example: build all targets for the FVP platform:" + @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
diff --git a/arch/arm/mach-meson/c2/firmware/acs/acs.c b/arch/arm/mach-meson/c2/firmware/acs/acs.c new file mode 100644 index 0000000..76869b3 --- /dev/null +++ b/arch/arm/mach-meson/c2/firmware/acs/acs.c
@@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <version.h> +#include <asm/arch/acs.h> +#include <asm/arch/timing.h> +#include "timing.c" + +//main acs struct +acs_set_t __acs_set={ + .acs_magic = "acs__", + .chip_type = 0x0, + .version = 1, + .acs_set_length = sizeof(__acs_set), + + .ddr_magic = "ddrs_", + .ddr_set_version= 1, + .ddr_set_length = sizeof(__ddr_setting), + .ddr_set_addr = (unsigned long)(&__ddr_setting), + + .ddr_reg_magic = "ddrr_", + .ddr_reg_version= 1, + .ddr_reg_length = sizeof(__ddr_reg), + .ddr_reg_addr = (unsigned long)(&__ddr_reg), + + .pll_magic = "pll__", + .pll_set_version= 1, + .pll_set_length = sizeof(__pll_setting), + .pll_set_addr = (unsigned long)(&__pll_setting), + + .sto_magic = "store", + .sto_set_version= 1, + .sto_set_length = 0, + .sto_set_addr = 0, + + .bl2_regs_magic = "bl2r_", + .bl2_regs_version = 1, + .bl2_regs_length = sizeof(__bl2_reg), + .bl2_regs_addr = (unsigned long)(&__bl2_reg), + + .rsv_magic = "rsv0_", + .rsv_set_version= 1, + .rsv_set_length = 0, + .rsv_set_addr = 0, + .board_id = {0,}, + .ddr_struct_size = {0,}, + .ddr_struct_org_size = sizeof(ddr_set_t), + .revision = ACS_VERSION, +};
diff --git a/arch/arm/mach-meson/c2/firmware/acs/acs.ld.S b/arch/arm/mach-meson/c2/firmware/acs/acs.ld.S new file mode 100644 index 0000000..3e5bf1d --- /dev/null +++ b/arch/arm/mach-meson/c2/firmware/acs/acs.ld.S
@@ -0,0 +1,19 @@ + +OUTPUT_FORMAT("elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(acs_entry) + +SECTIONS +{ + . = 0xFFFF6000; + + . : { + __RO_START__ = .; + *acs_entry.o(.text*) + *(.text*) + *(.data*) + *(.ddr_settings*) + } + + //ASSERT(. <= 0xFFFF7000, "timing image has exceeded its limit.") +}
diff --git a/arch/arm/mach-meson/c2/firmware/acs/acs.mk b/arch/arm/mach-meson/c2/firmware/acs/acs.mk new file mode 100644 index 0000000..0c63194 --- /dev/null +++ b/arch/arm/mach-meson/c2/firmware/acs/acs.mk
@@ -0,0 +1,9 @@ +SOURCES += acs_entry.S + +ifdef CONFIG_MDUMP_COMPRESS +SOURCES += ramdump.c +endif + +SOURCES += acs.c + +LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/c2/firmware/acs/acs_entry.S b/arch/arm/mach-meson/c2/firmware/acs/acs_entry.S new file mode 100644 index 0000000..feca813 --- /dev/null +++ b/arch/arm/mach-meson/c2/firmware/acs/acs_entry.S
@@ -0,0 +1,14 @@ + + .globl acs_entry + +acs_entry: + .word 0 + .word __acs_set +#ifdef CONFIG_MDUMP_COMPRESS + .word __ramdump_data + .word __ddr_setting +#else + .word 0x0 + .word __ddr_setting +#endif +
diff --git a/arch/arm/mach-meson/c2/firmware/bl21/Makefile b/arch/arm/mach-meson/c2/firmware/bl21/Makefile new file mode 100644 index 0000000..3c121d8 --- /dev/null +++ b/arch/arm/mach-meson/c2/firmware/bl21/Makefile
@@ -0,0 +1,3 @@ +all: + @echo "BL21 no action for C2 " +
diff --git a/arch/arm/mach-meson/c2/firmware/scp_task/Makefile b/arch/arm/mach-meson/c2/firmware/scp_task/Makefile new file mode 100644 index 0000000..efa820c --- /dev/null +++ b/arch/arm/mach-meson/c2/firmware/scp_task/Makefile
@@ -0,0 +1,3 @@ +all: + @echo "BL301 no action for C2" +
diff --git a/arch/arm/mach-meson/c2/gate_init.c b/arch/arm/mach-meson/c2/gate_init.c new file mode 100644 index 0000000..31629f6 --- /dev/null +++ b/arch/arm/mach-meson/c2/gate_init.c
@@ -0,0 +1,366 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include "power_gate.h" + +#define SECUREBOOT_FLAG_ADDR 0xc8100228 + +#ifdef CONFIG_AML_CVBS +extern unsigned int cvbs_mode; +#endif +void ee_gate_off(void) +{ + printf("ee_gate_off ...\n"); + return; +/* int secureboot = readl(SECUREBOOT_FLAG_ADDR)&(1<<5);*/ + +#ifdef CONFIG_AML_CVBS + unsigned int cvbs_opened = 0; +#endif + +#ifdef CONFIG_AML_CVBS + if ((cvbs_mode == 0) || (cvbs_mode == 1)) + cvbs_opened = 1; +#endif + + /* + //if close , audio maybe have noise + CLK_GATE_OFF(AUD); + CLK_GATE_OFF(AUD2); + CLK_GATE_OFF(AUD_CLK_2); + CLK_GATE_OFF(AUD_CLK_3); + */ + CLK_GATE_OFF(AUD_IN); + CLK_GATE_OFF(AIU_AUD_MIXER); + CLK_GATE_OFF(SANA); + + /*kernel will reopen */ + CLK_GATE_OFF(CTS_ENCL); + /* CLK_GATE_OFF(CTS_ENCT); */ +#if 0 /* HDMITX 480i60hz/576i50hz need this gate */ +#ifdef CONFIG_AML_CVBS + if (cvbs_opened == 0) + CLK_GATE_OFF(CTS_ENCI); +#else + CLK_GATE_OFF(CTS_ENCI); +#endif +#endif + /* CLK_GATE_OFF(CTS_ENCP); */ + + /*close cvbs clock*/ +#ifdef CONFIG_AML_CVBS + if (cvbs_opened == 0) { + CLK_GATE_OFF(DAC_CLK); + CLK_GATE_OFF(CTS_VDAC); + } +#else + CLK_GATE_OFF(DAC_CLK); + CLK_GATE_OFF(CTS_VDAC); +#endif + + /* usb clock close */ + CLK_GATE_OFF(USB0); + CLK_GATE_OFF(USB1); + //CLK_GATE_OFF(USB_CLK); //g12a no reg + CLK_GATE_OFF(MISC_USB0_TO_DDR); + CLK_GATE_OFF(MISC_USB1_TO_DDR); + + /* uarts close */ + CLK_GATE_OFF(UART0); + CLK_GATE_OFF(UART1); + CLK_GATE_OFF(UART2); + CLK_GATE_OFF(UART3); + + CLK_GATE_OFF(VCLK2_VENCP); + CLK_GATE_OFF(VCLK2_VENCT); + CLK_GATE_OFF(VCLK2_VENCT1); + CLK_GATE_OFF(VCLK2_OTHER); +#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */ +#ifdef CONFIG_AML_CVBS + if (cvbs_opened == 0) { + CLK_GATE_OFF(VCLK2_VENCI); + CLK_GATE_OFF(VCLK2_VENCI1); + } +#else + CLK_GATE_OFF(VCLK2_VENCI); + CLK_GATE_OFF(VCLK2_VENCI1); +#endif +#endif + CLK_GATE_OFF(VCLK2_VENCL); + CLK_GATE_OFF(VCLK2_OTHER1); +#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */ +#ifdef CONFIG_AML_CVBS + if (cvbs_opened == 0) + CLK_GATE_OFF(VCLK2_ENCI); +#else + CLK_GATE_OFF(VCLK2_ENCI); +#endif +#endif + CLK_GATE_OFF(VCLK2_ENCL); + CLK_GATE_OFF(VCLK2_ENCT); + + CLK_GATE_OFF(VDEC_CLK_1); + CLK_GATE_OFF(VDEC_CLK_2); + CLK_GATE_OFF(VDEC2_CLK_1); + CLK_GATE_OFF(VDEC2_CLK_2); + CLK_GATE_OFF(HCODEC_CLK_1); + CLK_GATE_OFF(HCODEC_CLK_2); + /* CLK_GATE_OFF(HEVC_CLK_1 ); */ + /* CLK_GATE_OFF(HEVC_CLK_2 ); */ + + //CLK_GATE_OFF(MMC_A_PCLK); //g12a no reg + //CLK_GATE_OFF(MMC_B_PCLK); //g12a no reg + //CLK_GATE_OFF(MMC_C_PCLK); //g12a no reg + + CLK_GATE_OFF(LCD_AN_PHY2); + CLK_GATE_OFF(LCD_AN_PHY3); + + CLK_GATE_OFF(ETHERNET); + //CLK_GATE_OFF(ETH_CLK); //g12a no reg + + CLK_GATE_OFF(GE2D); + CLK_GATE_OFF(GEN_CLK); + //CLK_GATE_OFF(PCM_MCLK); //g12a no reg + //CLK_GATE_OFF(PCM_SCLK); //g12a no reg + + + CLK_GATE_OFF(HIU_PARSER_TOP); + + + /* can not off nand_clk */ + /* CLK_GATE_OFF(NAND_CLK); */ + /* + //HDMI no output + CLK_GATE_OFF(VCLK2_VENCP1); + CLK_GATE_OFF(VCLK2_ENCP); + */ + + /* + //if OFF, HDMI will report error! + CLK_GATE_OFF(HDMI_PCLK); + CLK_GATE_OFF(HDMI_PLL_CNTL); + CLK_GATE_OFF(HDMITX_CLK); + */ + + /* + //PWM B used for VCCK,PWM D used for VDDEE,ignoring + CLK_GATE_OFF(PWM_A_CLK); + CLK_GATE_OFF(PWM_B_CLK); + CLK_GATE_OFF(PWM_C_CLK); + CLK_GATE_OFF(PWM_D_CLK); + CLK_GATE_OFF(PWM_E_CLK); + CLK_GATE_OFF(PWM_F_CLK); + */ + + + /* can not close + CLK_GATE_OFF(VPU_CLK_1); + CLK_GATE_OFF(VPU_CLK_2); + CLK_GATE_OFF(VPU_CLKB); + CLK_GATE_OFF(MALI_CLK_1); + CLK_GATE_OFF(MALI_CLK_2); + CLK_GATE_OFF(ATV_DEMO_VDAC); + CLK_GATE_OFF(EMMC_A); + CLK_GATE_OFF(EMMC_B); + CLK_GATE_OFF(EMMC_C); + CLK_GATE_OFF(EMMC_A_CLK); + CLK_GATE_OFF(EMMC_B_CLK); + + CLK_GATE_OFF(MSR_CLK); + CLK_GATE_OFF(MSR_HS_CLK); + CLK_GATE_OFF(32K_CLK); + CLK_GATE_OFF(VAPB_CLK_1); + CLK_GATE_OFF(VAPB_CLK_2); + CLK_GATE_OFF(GIC); + CLK_GATE_OFF(I2C_AO); //no close for to use + CLK_GATE_OFF(AO_CPU); + CLK_GATE_OFF(ASSIST_MISC); + CLK_GATE_OFF(HIU_PARSER); + CLK_GATE_OFF(PERIPHS_TOP); + CLK_GATE_OFF(PL310_CBUS); + CLK_GATE_OFF(ISA); + CLK_GATE_OFF(SECURE_AHP_APB3); + CLK_GATE_OFF(VPU_INTR); + CLK_GATE_OFF(MMC_PCLK); //can not close + CLK_GATE_OFF(AIU_PCLK); + //can not connect pc + CLK_GATE_OFF(USB_GENERAL); + CLK_GATE_OFF(AHB_DATA_BUS); + CLK_GATE_OFF(AHB_CONTROL_BUS); + CLK_GATE_OFF(HDMI_INTR_SYNC); //should open + //can't suspend @ 2nd time + //CLK_GATE_OFF(RESET); + + // close rom + //disable this bit will make other cpu can not be booted. + //CLK_GATE_OFF(ROM_CLK); + +*/ + /*************************/ + CLK_GATE_OFF(AHB_ARB0); + CLK_GATE_OFF(ASYNC_FIFO); + CLK_GATE_OFF(STREAM); + CLK_GATE_OFF(RANDOM_NUM_GEN); + CLK_GATE_OFF(RANDOM_NUM_GEN1); + CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN); + CLK_GATE_OFF(I2C); + CLK_GATE_OFF(SPI); + CLK_GATE_OFF(SPICC); + CLK_GATE_OFF(DOS); + CLK_GATE_OFF(SAR_ADC); + CLK_GATE_OFF(MISC_DVIN); + CLK_GATE_OFF(BT656); + CLK_GATE_OFF(BT656_2); + CLK_GATE_OFF(PDM); + + /* close AIU */ + CLK_GATE_OFF(AIU_IEC958); + CLK_GATE_OFF(AIU_ICE958_AMCLK); + + CLK_GATE_OFF(AIU_AMCLK_MEASURE); + CLK_GATE_OFF(AIU_AIFIFO2); + CLK_GATE_OFF(AIU_MIXER_REG); + CLK_GATE_OFF(AIU_ADC); + CLK_GATE_OFF(AIU_TOP_LEVEL); + CLK_GATE_OFF(AIU_AOCLK); + CLK_GATE_OFF(AIU_AI_TOP_GLUE); + CLK_GATE_OFF(AIU_I2S_OUT); + + CLK_GATE_OFF(ENC480P); + + CLK_GATE_OFF(DEMUX); +/* +* EFUSE/BLK_MOV clock gate must be on, + kernel storage ops depend on them. + it can be reference PD#112732 +*/ +/* + if (secureboot) { + printf("secure boot ignore [ BLK_MOV, efuse ] clk gate\n"); + } else { + CLK_GATE_OFF(EFUSE); + CLK_GATE_OFF(BLK_MOV); + } +*/ +} + +void ee_gate_on(void) +{ + + printf("ee_gate_on ...\n"); + + /* + //if close , audio maybe have noise + CLK_GATE_ON(AUD); + CLK_GATE_ON(AUD2); + CLK_GATE_ON(AUD_CLK_2); + CLK_GATE_ON(AUD_CLK_3); + */ + CLK_GATE_ON(AUD_IN); + CLK_GATE_ON(AIU_AUD_MIXER); + CLK_GATE_ON(SANA); + + /*kernel will reopen */ + CLK_GATE_ON(CTS_ENCL); + /* CLK_GATE_ON(CTS_ENCT); */ + CLK_GATE_ON(CTS_ENCI); + /* CLK_GATE_ON(CTS_ENCP); */ + + /*close cvbs clock*/ + CLK_GATE_ON(DAC_CLK); + CLK_GATE_ON(CTS_VDAC); + + /* usb clock close */ + CLK_GATE_ON(USB0); + CLK_GATE_ON(USB1); + //CLK_GATE_ON(USB_CLK); //g12a no reg + CLK_GATE_ON(MISC_USB0_TO_DDR); + CLK_GATE_ON(MISC_USB1_TO_DDR); + + /* uarts close */ + CLK_GATE_ON(UART0); + CLK_GATE_ON(UART1); + CLK_GATE_ON(UART2); + CLK_GATE_ON(UART3); + + CLK_GATE_ON(VCLK2_VENCP); + CLK_GATE_ON(VCLK2_VENCT); + CLK_GATE_ON(VCLK2_VENCT1); + CLK_GATE_ON(VCLK2_OTHER); + CLK_GATE_ON(VCLK2_VENCI); + CLK_GATE_ON(VCLK2_VENCI1); + CLK_GATE_ON(VCLK2_VENCL); + CLK_GATE_ON(VCLK2_OTHER1); + + + CLK_GATE_ON(VCLK2_ENCI); + CLK_GATE_ON(VCLK2_ENCL); + CLK_GATE_ON(VCLK2_ENCT); + + CLK_GATE_ON(VDEC_CLK_1); + CLK_GATE_ON(VDEC_CLK_2); + CLK_GATE_ON(VDEC2_CLK_1); + CLK_GATE_ON(VDEC2_CLK_2); + CLK_GATE_ON(HCODEC_CLK_1); + CLK_GATE_ON(HCODEC_CLK_2); + /* CLK_GATE_ON(HEVC_CLK_1 ); */ + /* CLK_GATE_ON(HEVC_CLK_2 ); */ + + //CLK_GATE_ON(MMC_A_PCLK); //g12a no reg + //CLK_GATE_ON(MMC_B_PCLK); //g12a no reg + //CLK_GATE_ON(MMC_C_PCLK); //g12a no reg + + CLK_GATE_ON(LCD_AN_PHY2); + CLK_GATE_ON(LCD_AN_PHY3); + + CLK_GATE_ON(ETHERNET); + //CLK_GATE_ON(ETH_CLK); //g12a no reg + + CLK_GATE_ON(GE2D); + CLK_GATE_ON(GEN_CLK); + //CLK_GATE_ON(PCM_MCLK); //g12a no reg + //CLK_GATE_ON(PCM_SCLK); //g12a no reg + + + CLK_GATE_ON(HIU_PARSER_TOP); + + /*************************/ + CLK_GATE_ON(AHB_ARB0); + CLK_GATE_ON(ASYNC_FIFO); + CLK_GATE_ON(STREAM); + CLK_GATE_ON(RANDOM_NUM_GEN); + CLK_GATE_ON(RANDOM_NUM_GEN1); + CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN); + CLK_GATE_ON(I2C); + CLK_GATE_ON(SPI); + CLK_GATE_ON(SPICC); + CLK_GATE_ON(DOS); + CLK_GATE_ON(SAR_ADC); + CLK_GATE_ON(MISC_DVIN); + CLK_GATE_ON(BT656); + CLK_GATE_ON(BT656_2); + CLK_GATE_ON(PDM); + + /* close AIU */ + CLK_GATE_ON(AIU_IEC958); + CLK_GATE_ON(AIU_ICE958_AMCLK); + + CLK_GATE_ON(AIU_AMCLK_MEASURE); + CLK_GATE_ON(AIU_AIFIFO2); + CLK_GATE_ON(AIU_MIXER_REG); + CLK_GATE_ON(AIU_ADC); + CLK_GATE_ON(AIU_TOP_LEVEL); + CLK_GATE_ON(AIU_AOCLK); + CLK_GATE_ON(AIU_AI_TOP_GLUE); + CLK_GATE_ON(AIU_I2S_OUT); + + CLK_GATE_ON(ENC480P); + + CLK_GATE_ON(DEMUX); + + CLK_GATE_ON(EFUSE); + CLK_GATE_ON(BLK_MOV); +} +
diff --git a/arch/arm/mach-meson/c2/gpio.c b/arch/arm/mach-meson/c2/gpio.c new file mode 100644 index 0000000..7332773 --- /dev/null +++ b/arch/arm/mach-meson/c2/gpio.c
@@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <dm.h> +#include <linux/compiler.h> +#include <amlogic/aml_gpio.h> +#include <asm/arch/gpio.h> + +struct pin_mux_desc { + unsigned char domain; + unsigned char reg; + unsigned char bit; +}; + +#define MUX_AO_DOMAIN 0 +#define MUX_EE_DOMAIN 1 + +#define PIN_MUX(d, r, b) \ +{ \ + .domain = d, \ + .reg = r, \ + .bit = b, \ +} + +#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ +{ \ + .name = n, \ + .first = f, \ + .last = l, \ + .regs = { \ + [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \ + [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \ + [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \ + [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \ + [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \ + }, \ + } +#define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ +{ \ + .name = n, \ + .first = f, \ + .last = l, \ + .regs = { \ + [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \ + [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \ + [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \ + [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \ + [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \ + }, \ + } + +static struct pin_mux_desc pin_to_gpio[] = { + [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0), + [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4), + [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8), + [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12), + [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16), + [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20), + [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24), + [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28), + [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0), + [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4), + [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8), + [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12), + [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16), + [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20), + [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24), + [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0), + [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4), + [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8), + [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12), + [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16), + [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20), + [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24), + [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28), + [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0), + [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4), + [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8), + [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12), + [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16), + [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20), + [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24), + [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28), + [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0), + [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4), + [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8), + [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12), + [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16), + [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20), + [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24), + [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28), + [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0), + [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0), + [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4), + [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8), + [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12), + [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16), + [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20), + [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24), + [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28), + [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0), + [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4), + [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8), + [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12), + [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16), + [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20), + [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24), + [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28), + [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0), + [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4), + [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8), + [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12), + [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16), + [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20), + [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24), + [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28), + [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0), + [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4), + [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8), + [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12), + [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16), + [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20), + [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24), + [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28), + [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0), + [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4), + [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8), + [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12), + [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16), + [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20), + [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24), + [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28), + [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0), + [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4), + [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8), + [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12), + [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16), + [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20), + [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24), + [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28), + [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0), + [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4), + [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8), + [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12), + [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16), + [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20), + [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24), + [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28), + [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0), + [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4), + [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8), + [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12), +}; +/*sequence of banks keep same as arch-g12a/gpio.h*/ +static struct meson_bank mesontxhd_banks[] = { + /*name first last pullen pull dir out in*/ + AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11), + 3, 0, 2, 0, 0, 0, 4, 0, 1, 0), + AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2), + 3, 16, 2, 16, 0, 16, 4, 16, 1, 16), + BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15), + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8), + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15), + 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7), + 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), + BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15), + 5, 0, 5, 0, 16, 0, 17, 0, 18, 0), + BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19), + 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), +}; + +U_BOOT_DEVICES(txhd_gpios) = { + { "gpio_aml", &mesontxhd_banks[0] }, + { "gpio_aml", &mesontxhd_banks[1] }, + { "gpio_aml", &mesontxhd_banks[2] }, + { "gpio_aml", &mesontxhd_banks[3] }, + { "gpio_aml", &mesontxhd_banks[4] }, + { "gpio_aml", &mesontxhd_banks[5] }, + { "gpio_aml", &mesontxhd_banks[6] }, + { "gpio_aml", &mesontxhd_banks[7] }, +}; + +static unsigned long domain[]={ + [MUX_AO_DOMAIN] = 0xff800014, + [MUX_EE_DOMAIN] = 0xff6346c0, +}; + +int clear_pinmux(unsigned int pin) +{ + struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin]; + + regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2), + 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit)); + + return 0; +} + +#ifdef CONFIG_AML_SPICC +#include <asm/arch/secure_apb.h> +/* generic pins control for spicc1. + * if deleted, you have to add it into all g12a board files as necessary. + * GPIOH_4: MOSI:regB[19:16]=3 + * GPIOH_5: MISO:regB[23:20]=3 + * GPIOH_7: CLK:regB[31:28]=3 + */ +int spicc1_pinctrl_enable(bool enable) +{ + unsigned int val; + + val = readl(P_PERIPHS_PIN_MUX_B); + val &= ~(0xf0ff << 16); + if (enable) + val |= 0x3033 << 16; + writel(val, P_PERIPHS_PIN_MUX_B); + return 0; +} +#endif /* CONFIG_AML_SPICC */
diff --git a/arch/arm/mach-meson/c2/hdmitx.c b/arch/arm/mach-meson/c2/hdmitx.c new file mode 100644 index 0000000..5292c87 --- /dev/null +++ b/arch/arm/mach-meson/c2/hdmitx.c
@@ -0,0 +1,594 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/arch/io.h> +#include <asm/io.h> +#include <amlogic/media/vout/hdmitx.h> +#include <asm/arch/regs.h> +#include <asm/arch/secure_apb.h> + +#define HDMITX_DWC_BASE_OFFSET 0xFF600000 +#define HDMITX_TOP_BASE_OFFSET 0xFF608000 + +static int dbg_en =0; + +unsigned long hd_read_reg(volatile unsigned int* addr) +{ + unsigned long val = 0; + + val = *addr; + if (dbg_en) + printk("R: 0x%8p 0x%08lx\n", addr, val); + return val; +} + +void hd_write_reg(volatile unsigned int* addr, unsigned long val) +{ + *addr = val; + if (dbg_en) + printk("W: 0x%8p 0x%08lx %s 0x%08lx\n", addr, + val, (val == hd_read_reg(addr)) ? "==" : "!=", hd_read_reg(addr)); +} + +void hd_set_reg_bits(volatile unsigned int* addr, unsigned long value, + unsigned long offset, unsigned long len) +{ + unsigned long data = 0; + + data = hd_read_reg(addr); + data &= ~(((1L << len) - 1) << offset); + data |= (value & ((1L << len) - 1)) << offset; + hd_write_reg(addr, data); +} + +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" +unsigned int hdmitx_rd_reg(unsigned int addr) +{ + unsigned int large_offset = addr >> 24; + unsigned int small_offset = addr & ((1 << 24) - 1); + unsigned int data = 0; + register long x0 asm("x0") = 0x82000018; + register long x1 asm("x1") = (unsigned long)addr; + + if (large_offset == 0x10) { + large_offset = HDMITX_DWC_BASE_OFFSET; + data = readb((unsigned long)(large_offset + small_offset)); + } else if (large_offset == 0x0){ + large_offset = HDMITX_TOP_BASE_OFFSET; + if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) { + data = readb((unsigned long)(large_offset + small_offset)); + } else { + small_offset = small_offset << 2; + data = readl((unsigned long)(large_offset + small_offset)); + } + } else { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r"(x0) : "r"(x1) + ); + data = (unsigned)(x0&0xffffffff); + } + if (dbg_en) + printk("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP", + addr, data); + + return data; +} + +void hdmitx_wr_reg(unsigned int addr, unsigned int data) +{ + unsigned int large_offset = addr >> 24; + unsigned int small_offset = addr & ((1 << 24) - 1); + register long x0 asm("x0") = 0x82000019; + register long x1 asm("x1") = (unsigned long)addr; + register long x2 asm("x2") = data; + + if (large_offset == 0x10) { + large_offset = HDMITX_DWC_BASE_OFFSET; + writeb(data & 0xff, (unsigned long)(large_offset + small_offset)); + } else if (large_offset == 0x0){ + large_offset = HDMITX_TOP_BASE_OFFSET; + if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) { + writeb(data & 0xff,(unsigned long)(large_offset + small_offset)); + } else { + small_offset = small_offset << 2; + writel(data,(unsigned long)(large_offset + small_offset)); + } + } else { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + "smc #0\n" + : : "r"(x0), "r"(x1), "r"(x2) + ); + } + if (dbg_en) + printk("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP", + addr, data); +} + +void hdmitx_set_reg_bits(unsigned int addr, unsigned int value, + unsigned int offset, unsigned int len) +{ + unsigned int data32 = 0; + + data32 = hdmitx_rd_reg(addr); + data32 &= ~(((1 << len) - 1) << offset); + data32 |= (value & ((1 << len) - 1)) << offset; + hdmitx_wr_reg(addr, data32); +} + +void hdmitx_poll_reg(unsigned int addr, unsigned int val, + unsigned long timeout) +{ + udelay(2000); + if (!(hdmitx_rd_reg(addr) & val)) + printk("hdmitx poll:0x%x val:0x%x t=%dms timeout\n", + addr, val, 2000); +} + +void hdmitx_rd_check_reg (unsigned long addr, + unsigned long exp_data, unsigned long mask) +{ + unsigned long rd_data; + rd_data = hdmitx_rd_reg(addr); + if ((rd_data | mask) != (exp_data | mask)) { + printk("HDMITX-DWC addr=0x%04x rd_data=0x%02x\n", + (unsigned int)addr, (unsigned int)rd_data); + printk("Error: HDMITX-DWC exp_data=0x%02x mask=0x%02x\n", + (unsigned int)exp_data, (unsigned int)mask); + } +} + +static void set_phy_by_mode(unsigned int mode) +{ + switch (mode) { + case 1: /* 5.94/4.5/3.7Gbps */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b); + break; + case 2: /* 2.97Gbps */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); + break; + case 3: /* 1.485Gbps, and below */ + default: + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003); + break; + } +} +void hdmitx_set_phy(struct hdmitx_dev *hdev) +{ + if (!hdev) + return; + + switch (hdev->vic) { + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p60_256x135: + if ((hdev->para->cs == HDMI_COLOR_FORMAT_420) + && (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) + set_phy_by_mode(2); + else + set_phy_by_mode(1); + break; + case HDMI_3840x2160p50_16x9_Y420: + case HDMI_3840x2160p60_16x9_Y420: + case HDMI_4096x2160p50_256x135_Y420: + case HDMI_4096x2160p60_256x135_Y420: + if (hdev->para->cd == HDMI_COLOR_DEPTH_24B) + set_phy_by_mode(2); + else + set_phy_by_mode(1); + break; + case HDMI_3840x2160p24_16x9: + case HDMI_3840x2160p24_64x27: + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p25_64x27: + case HDMI_3840x2160p30_16x9: + case HDMI_3840x2160p30_64x27: + case HDMI_4096x2160p24_256x135: + case HDMI_4096x2160p25_256x135: + case HDMI_4096x2160p30_256x135: + if ((hdev->para->cs == HDMI_COLOR_FORMAT_422) + || (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) + set_phy_by_mode(2); + else + set_phy_by_mode(1); + break; + case HDMI_1920x1080p60_16x9: + case HDMI_1920x1080p50_16x9: + case HDMI_1920x1080i100_16x9: + case HDMI_1920x1080i120_16x9: + case HDMI_1280x720p100_16x9: + case HDMI_1280x720p120_16x9: + default: + set_phy_by_mode(3); + break; + } +/* P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset */ +#define RESET_HDMI_PHY() \ +do { \ + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0xf, 0, 4); \ + mdelay(2); \ + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0xe, 0, 4); \ + mdelay(2); \ +} while (0) + + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0390, 16, 16); + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4); + RESET_HDMI_PHY(); + RESET_HDMI_PHY(); + RESET_HDMI_PHY(); +#undef RESET_HDMI_PHY + + printk("hdmitx phy setting done\n"); +} + +void hdmitx_turnoff(void) +{ + /* Close HDMITX PHY */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0); + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0); + hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0); + /* Disable HPLL */ + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0); +} + +#define WAIT_FOR_PLL_LOCKED(reg) \ + do { \ + unsigned int st = 0; \ + int cnt = 10; \ + while (cnt--) { \ + udelay(50); \ + st = (((hd_read_reg(reg) >> 30) & 0x3) == 3); \ + if (st) \ + break; \ + else { \ + /* reset hpll */ \ + hd_set_reg_bits(reg, 1, 29, 1); \ + hd_set_reg_bits(reg, 0, 29, 1); \ + } \ + } \ + if (cnt < 9) \ + printk("pll[0x%8p] reset %d times\n", reg, 9 - cnt);\ + } while (0) + +static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val, + struct hdmitx_dev *hdev) +{ + int ret = 0; + + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + if (frac_val == 0x8148) { + if (((hdev->para->vic == HDMI_3840x2160p50_16x9) || + (hdev->para->vic == HDMI_3840x2160p60_16x9) || + (hdev->para->vic == HDMI_3840x2160p50_64x27) || + (hdev->para->vic == HDMI_3840x2160p60_64x27)) && + (hdev->para->cs != HDMI_COLOR_FORMAT_420)) { + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x11551293); + } else { + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x44331290); + } + } else { + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290); + } + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLLv1: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + + ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3); + return ret; +} + +static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val) +{ + int ret = 0; + + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLLv2: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + + ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3); + return ret; +} + +static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val) +{ + int ret = 0; + + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x55540000); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLLv3: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + + ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3); + return ret; +} + +void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev) +{ + unsigned int frac_rate ; + + frac_rate = hdev->frac_rate_policy; + if (clk == -1) + return; + printk("config HPLL = %d frac_rate = %d\n", clk, frac_rate); + + switch (clk) { + case 5940000: + if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000, hdev)) + break; + else if (set_hpll_hclk_v2(0x7b,0x18000)) + break; + else if (set_hpll_hclk_v3(0xf7,0x10000)) + break; + else + break; + break; + case 5405400: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004e1); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00007333); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; + case 4455000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b9); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00014000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; + case 3712500: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00049a); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; + case 3450000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048f); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; + case 3243240: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000487); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0000451f); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; + case 2970000: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00047b); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; + case 4324320: + hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b4); + hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00); + hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290); + hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000); + hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0); + printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0)); + break; + default: + printk("error hpll clk: %d\n", clk); + break; + } + printk("config HPLL done\n"); +} + +void set_hpll_od1(unsigned div) +{ + switch (div) { + case 1: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 16, 2); + break; + case 2: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 16, 2); + break; + case 4: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 16, 2); + break; + default: + printk("Err %s[%d]\n", __func__, __LINE__); + break; + } +} + +void set_hpll_od2(unsigned div) +{ + switch (div) { + case 1: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 18, 2); + break; + case 2: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 18, 2); + break; + case 4: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 18, 2); + break; + default: + printk("Err %s[%d]\n", __func__, __LINE__); + break; + } +} + +void set_hpll_od3(unsigned div) +{ + switch (div) { + case 1: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 20, 2); + break; + case 2: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 20, 2); + break; + case 4: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 20, 2); + break; + default: + printk("Err %s[%d]\n", __func__, __LINE__); + break; + } +} + +/* HERE MUST BE BIT OPERATION!!! */ +void set_hpll_sspll(struct hdmitx_dev *hdev) +{ + enum hdmi_vic vic = hdev->vic; + + switch (vic) { + case HDMI_1920x1080p60_16x9: + case HDMI_1920x1080p50_16x9: + case HDMI_1280x720p60_16x9: + case HDMI_1280x720p50_16x9: + case HDMI_1920x1080i60_16x9: + case HDMI_1920x1080i50_16x9: + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 29, 1); + /* bit[22:20] hdmi_dpll_fref_sel + * bit[8] hdmi_dpll_ssc_en + * bit[7:4] hdmi_dpll_ssc_dep_sel + */ + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 20, 3); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 8, 1); + /* 2: 1000ppm 1: 500ppm */ + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 4, 4); + /* bit[15] hdmi_dpll_sdmnc_en */ + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL3, 0, 15, 1); + hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 29, 1); + break; + default: + break; + } +} + +void ddc_pinmux_init(void) +{ + hd_set_reg_bits(P_PAD_PULL_UP_EN_REG3, 0, 0, 2); /*Disable GPIOH_1/2 pull-up/down*/ + hd_set_reg_bits(P_PAD_PULL_UP_REG3, 0, 0, 2); + hd_set_reg_bits(P_PREG_PAD_GPIO3_EN_N, 3, 0, 2); /*GPIOH_1/2 input*/ + hd_set_reg_bits(P_PERIPHS_PIN_MUX_B, 0x11, 0, 8); /*Mux DDC SDA/SCL*/ +} + +int hdmitx_get_hpd_state(void) +{ + int st = 0; + + st = !!(hd_read_reg(P_PREG_PAD_GPIO3_I) & (1 << 2)); + return st; +} + +void hdmitx_prbs(void) +{ + unsigned int i; + + for (i = 0; i < 4; i ++) { + hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000f); + hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000e); + hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x03904002); + hd_write_reg(P_HHI_HDMI_PHY_CNTL4, 0x0001efff | (i << 20)); + hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0xef904002); + mdelay(10); + if (i > 0) + pr_info("prbs D[%d]:%lx\n", i -1, hd_read_reg(P_HHI_HDMI_PHY_STATUS)); + else + pr_info("prbs clk :%lx\n",hd_read_reg(P_HHI_HDMI_PHY_STATUS)); + } +} + +void hdmitx_enable_apb3(void) +{ + /*g12a doesn't need enable apb3*/ + return; + /*hd_set_reg_bits(P_HDMITX_CTRL_PORT, 1, 15, 1);*/ + /*hd_set_reg_bits((P_HDMITX_CTRL_PORT + 0x10), 1, 15, 1);*/ +}
diff --git a/arch/arm/mach-meson/c2/mailbox.c b/arch/arm/mach-meson/c2/mailbox.c new file mode 100644 index 0000000..7105170 --- /dev/null +++ b/arch/arm/mach-meson/c2/mailbox.c
@@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <common.h> +#include <asm/arch/io.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/mailbox.h> +#include <asm/arch/secure_apb.h> + +/* Bit position for size value in MHU header */ +#define SIZE_SHIFT 20 +/* Mask to extract size value in MHU header*/ +#define SIZE_MASK 0x1ff + +static unsigned int *ap_mb_stat[] = { + (unsigned int *)HIU_MAILBOX_STAT_4, + (unsigned int *)HIU_MAILBOX_STAT_5, +}; +static unsigned int *ap_mb_set[] = { + (unsigned int *)HIU_MAILBOX_SET_4, + (unsigned int *)HIU_MAILBOX_SET_5, +}; +static unsigned int *ap_mb_clear[] = { + (unsigned int *)HIU_MAILBOX_CLR_4, + (unsigned int *)HIU_MAILBOX_CLR_5, +}; +static unsigned int *ap_mb_payload[] = { + (unsigned int *)(P_SHARE_SRAM_BASE + MHU_LOW_AP_TO_SCP_PAYLOAD), + (unsigned int *)(P_SHARE_SRAM_BASE + MHU_HIGH_AP_TO_SCP_PAYLOAD), +}; +static unsigned int *scp_mb_stat[] = { + (unsigned int *)HIU_MAILBOX_STAT_1, + (unsigned int *)HIU_MAILBOX_STAT_2, +}; +/* +static unsigned int *scp_mb_set[] = { + (unsigned int *)HIU_MAILBOX_SET_1, + (unsigned int *)HIU_MAILBOX_SET_2, +}; +*/ +static unsigned int *scp_mb_clear[] = { + (unsigned int *)HIU_MAILBOX_CLR_1, + (unsigned int *)HIU_MAILBOX_CLR_2, +}; +static unsigned int *scp_mb_payload[] = { + (unsigned int *)(P_SHARE_SRAM_BASE + MHU_LOW_SCP_TO_AP_PAYLOAD), + (unsigned int *)(P_SHARE_SRAM_BASE + MHU_HIGH_SCP_TO_AP_PAYLOAD), +}; + +static void mb_message_start(unsigned int priority) +{ + while (readl(ap_mb_stat[priority]) != 0) + ; +} +static void mb_message_send(unsigned int command, unsigned int priority) +{ + writel(command, ap_mb_set[priority]); + while (readl(ap_mb_stat[priority]) != 0) + ; +} +static unsigned int mb_message_wait(unsigned int priority) +{ + unsigned int response; + while (!(response = readl(scp_mb_stat[priority]))) + ; + return response; +} +static void mb_message_end(unsigned int priority) +{ + writel(0xffffffff, scp_mb_clear[priority]); +} +static unsigned int mb_message_receive( + void **message_out, + unsigned int *size_out, + unsigned int priority) +{ + unsigned int response = mb_message_wait(priority); + unsigned int size = (response >> SIZE_SHIFT) & SIZE_MASK; + + response &= ~(SIZE_MASK << SIZE_SHIFT); + + if (size_out) + *size_out = size; + if (message_out) + *message_out = (void *)(scp_mb_payload[priority]); + + return response; +} +static void mb_init(unsigned int priority) +{ + writel(0xffffffff, ap_mb_clear[priority]); +} + +static void scpi_send32(unsigned int command, + unsigned int message, unsigned int priority) +{ + mb_init(priority); + mb_message_start(priority); + writel(message, ap_mb_payload[priority]); + mb_message_send(command, priority); + mb_message_wait(priority); + mb_message_end(priority); +} + +static void scpi_send_block(unsigned int command, + unsigned int *message, unsigned int message_size, unsigned int priority) +{ + mb_init(priority); + mb_message_start(priority); + memcpy(ap_mb_payload[priority], message, message_size); + mb_message_send(command, priority); + mb_message_wait(priority); + mb_message_end(priority); +} + +void open_scp_log(unsigned int channel) +{ + scpi_send32(SCPI_CMD_OPEN_SCP_LOG, channel, LOW_PRIORITY); +} + +int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size) +{ + unsigned long command; + + if (size > 0x1fd) + return -1; + + command = ((unsigned int)SCPI_CMD_SET_USR_DATA & 0xff) | ((clinet_id & 0xff) << 8) | ((size & 0x1ff) << 20); + scpi_send_block(command,val,size,0); + + return 0; +} + +/* +* type: +* 0: data; 1: version +*/ +int thermal_calibration(unsigned int type, unsigned int data) +{ + unsigned int *appayload = ap_mb_payload[LOW_PRIORITY]; + unsigned int *response; + unsigned int size; + + mb_message_start(LOW_PRIORITY); + writel(type, appayload); + writel(data, appayload+1); + mb_message_send( + ((0x8 << SIZE_SHIFT) | SCPI_CMD_THERMAL_CALIB), + LOW_PRIORITY); + mb_message_receive((void *)&response, &size, LOW_PRIORITY); + mb_message_end(LOW_PRIORITY); + + if (*response != SCPI_SUCCESS) + return -1; + else + return 0; +} + +int thermal_get_value(unsigned int sensor_id, unsigned int *value) +{ + unsigned int *response; + unsigned int size; + + mb_message_start(LOW_PRIORITY); + writel(sensor_id, ap_mb_payload[LOW_PRIORITY]); + mb_message_send( + ((0x4 << SIZE_SHIFT) | SCPI_CMD_SENSOR_VALUE), + LOW_PRIORITY); + mb_message_receive((void *)&response, &size, LOW_PRIORITY); + mb_message_end(LOW_PRIORITY); + + *value = *(response+1); + if (*response != SCPI_SUCCESS) + return -1; + else + return 0; +} + + +void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt) +{ + unsigned int *appayload = ap_mb_payload[LOW_PRIORITY]; + mb_message_start(LOW_PRIORITY); + writel(vcck_delt, appayload); + writel(ee_delt, appayload+1); + mb_message_send(SCPI_CMD_REV_PWM_DELT, LOW_PRIORITY); + mb_message_wait(LOW_PRIORITY); + mb_message_end(LOW_PRIORITY); +} +
diff --git a/arch/arm/mach-meson/c2/oscring.c b/arch/arm/mach-meson/c2/oscring.c new file mode 100644 index 0000000..8a588cb --- /dev/null +++ b/arch/arm/mach-meson/c2/oscring.c
@@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <common.h> +#include <asm/arch/io.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/clock.h> +#include <asm/arch/oscring.h> + +void ring_powerinit(void) +{ + writel(0x18000a, RING_PWM_VCCK);/*set vcck 0.8v*/ + writel(0x090009, RING_PWM_EE);/*set ee 0.8v*/ +} + +unsigned long clk_util_ring_msr(unsigned long clk_mux) +{ + unsigned int regval = 0; + + writel(0, MSR_CLK_REG0); + /* Set the measurement gate to 64uS */ + /* 64uS is enough for measure the frequence? */ + setbits_le32(MSR_CLK_REG0, (10000 - 1)); + /* Disable continuous measurement */ + /* Disable interrupts */ + clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18)); + clrbits_le32(MSR_CLK_REG0, 0x7f << 20); + setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16)); + /* Wait for the measurement to be done */ + regval = readl(MSR_CLK_REG0); + do { + regval = readl(MSR_CLK_REG0); + } while (regval & (1 << 31)); + + /* Disable measuring */ + clrbits_le32(MSR_CLK_REG0, 1 << 16); + regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff; + + return (regval / 10); +} + +int ring_msr(int index) +{ + const char* clk_table[] = { + [26] = "osc_ring_clk_top(14_rvt) " , + [25] = "osc_ring_clk_top(16_lvt) " , + [24] = "osc_ring_clk_top(16_rvt) " , + [23] = "osc_ring_clk_isp(14_rvt) " , + [22] = "osc_ring_clk_isp(16_lvt) " , + [21] = "osc_ring_clk_isp(16_rvt) " , + [20] = "osc_ring_clk_ddr(14_slvt) " , + [19] = "osc_ring_clk_ddr(14_rvt) " , + [18] = "osc_ring_clk_ddr(16_lvt) " , + [17] = "osc_ring_clk_sram(14_lvt) " , + [16] = "osc_ring_clk_sram(16_slvt) " , + [15] = "osc_ring_clk_sram(16_lvt) " , + [14] = "osc_ring_clk_dsp(14lvt) " , + [13] = "osc_ring_clk_dsp(14rvt) " , + [12] = "osc_ring_clk_dsp(16_rvt) " , + [11] = "osc_ring_clk_dos(14_lvt) " , + [10] = "osc_ring_clk_dos(14_rvt) " , + [9] = "osc_ring_clk_dos(16_rvt) " , + [8] = "osc_ring_clk_nna(14_lvt) " , + [7] = "osc_ring_clk_nna(16_slvt) " , + [6] = "osc_ring_clk_nna(16_lvt) " , + [5] = "osc_ring_clk_cpu1(9T_14_slvt) " , + [4] = "osc_ring_clk_cpu1(9T_14_lvt) " , + [3] = "osc_ring_clk_cpu1(9T_16_slvt) " , + [2] = "osc_ring_clk_cpu0(9T_14_slvt) " , + [1] = "osc_ring_clk_cpu0(9T_14_lvt) " , + [0] = "osc_ring_clk_cpu0(9T_16_slvt) " , + }; + const int tb[] = {93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, + 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119}; + unsigned long i; + uint8_t efuseinfo[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + + if ((index != 0xff) && (index != 0)) { + if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) { + printf("fail get efuse info\n"); + return 0; + } + if ((index >= 1) && (index <= 3)) + printf("%d\n", efuseinfo[index]); + else + printf("input data not support!\n"); + + return 0; + } + if (0xff != index) { + ring_powerinit(); + printf("set vcck vddee to 800mv\n"); + } + /*RING_OSCILLATOR 0x7f: set slow ring*/ + writel(OSCRING_CTL_DATA0, OSCRING_CTL_REG0); + writel(OSCRING_CTL_DATA1, OSCRING_CTL_REG1); + writel(OSCRING_CTL_DATA2, OSCRING_CTL_REG2); + + for (i = 0; i < 27; i++) { + printf("%s :",clk_table[i]); + printf("%ld KHz",clk_util_ring_msr(tb[i])); + printf("\n"); + } + + if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) { + printf("fail get efuse info\n"); + return 0; + } + + printf("osc efuse info:\n"); + for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++) + printf("0x%x, ", efuseinfo[i]); + printf("\n"); + + /*efuse to test value*/ + printf("A35_core0(2) (14SLVT), idd_ee, idd_cpu\n"); + + printf("%d KHz ", (efuseinfo[1] * 50)); + + for (i = 2; i <=3; i++) { + printf("%d uA ", (efuseinfo[i] * 400)); + } + printf("\n"); + + return 0; +}
diff --git a/arch/arm/mach-meson/c2/pinctrl_init.c b/arch/arm/mach-meson/c2/pinctrl_init.c new file mode 100644 index 0000000..829ce28 --- /dev/null +++ b/arch/arm/mach-meson/c2/pinctrl_init.c
@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <dm/uclass.h> +#include <linux/err.h> +#include <asm/arch/pinctrl_init.h> + +int pinctrl_devices_active(int pinctrl_num) +{ + int ret; + int idx; + struct udevice *pinctrl; + + for (idx = 0; idx < pinctrl_num; idx++) { + ret = uclass_get_device(UCLASS_PINCTRL, idx, &pinctrl); + if (ret) { + debug("%s: failed to active pinctrl device [%d]", + __func__, idx); + return -EINVAL; + } + } + + return 0; +}
diff --git a/arch/arm/mach-meson/c2/pll.c b/arch/arm/mach-meson/c2/pll.c new file mode 100644 index 0000000..2c01070 --- /dev/null +++ b/arch/arm/mach-meson/c2/pll.c
@@ -0,0 +1,890 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <command.h> +#include <amlogic/cpu_id.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/timer.h> +#include <asm/arch/pll.h> + +#define STR_PLL_TEST_ALL "all" +#define STR_PLL_TEST_SYS "sys" +#define STR_PLL_TEST_FIX "fix" +#define STR_PLL_TEST_DDR "ddr" +#define STR_PLL_TEST_HIFI "hifi" +#define STR_PLL_TEST_GP "gp0" +#define STR_PLL_TEST_DDS "dds" +#define STR_PLL_TEST_USBPHY "usbphy" +#define STR_PLL_TEST_ETHPHY "ethphy" + +#define PLL_LOCK_CHECK_MAX 10 + +#define RET_PLL_LOCK_FAIL 0x1000 +#define RET_CLK_NOT_MATCH 0x1 +#define SYS_PLL_DIV16_CNTL (1<<24) +#define SYS_CLK_DIV16_CNTL (1) +#define SYS_PLL_TEST_DIV 4 /* div16 */ +#define HDMI_PLL_DIV_CNTL (1<<18) +#define HDMI_PLL_DIV_GATE (1<<19) + +#define PLL_DIV16_OFFSET 4 /* div2/2/4 */ +#define gp_PLL_TEST_DIV 0 /* div1 */ +#define PLL_DIV8_OFFSET 3 + +#define Wr(addr, data) writel(data, addr) +#define Rd(addr) readl(addr) + +static int sys_pll_init(sys_pll_set_t * sys_pll_set); +static int sys_pll_test(sys_pll_set_t * sys_pll_set); +static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg); +static int fix_pll_test(void); +static int ddr_pll_test(void); +static int gp_pll_test(gp_pll_set_t * gp_pll); +static int gp_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg); +extern unsigned long clk_util_clk_msr(unsigned long clk_mux); + +static void update_bits(size_t reg, size_t mask, unsigned int val) +{ + unsigned int tmp, orig; + orig = readl(reg); + tmp = orig & ~mask; + tmp |= val & mask; + writel(tmp, reg); +} + +uint32_t sys_pll_clk[PLL_TEST_SYS_TOTAL] = {3216, 1584}; +sys_pll_cfg_t sys_pll_cfg = { + .sys_pll[0] = { + .cpu_clk = 3216, + .pll_cntl0 = 0x00300486, + .pll_cntl1 = 0x00021092, + .pll_cntl2 = 0x09023302, + .pll_cntl3 = 0x02008000, + }, + .sys_pll[1] = { + .cpu_clk = 1584, + .pll_cntl0 = 0x00000442, + .pll_cntl1 = 0x00021092, + .pll_cntl2 = 0x09023302, + .pll_cntl3 = 0x02008000, + }, +}; + +uint32_t hifi_pll_clk[] = {1560, 744}; +hifi_pll_cfg_t hifi_pll_cfg = { + .hifi_pll[0] = { + .pll_clk = 1560, + .pll_cntl0 = 0x00030441, + .pll_cntl1 = 0x802000b1, + .pll_cntl2 = 0x15002320, + .pll_cntl3 = 0xf0005555, + .pll_cntl4 = 0x45004000, + }, + + .hifi_pll[1] = { + .pll_clk = 744, + .pll_cntl0 = 0x0003041f, + .pll_cntl1 = 0x802000b1, + .pll_cntl2 = 0x12002320, + .pll_cntl3 = 0xf0005555, + .pll_cntl4 = 0x45004000, + }, +}; + +gp0_pll_cfg_t gp0_pll_cfg = { + .gp0_pll[0] = { + .pll_clk = 1560, /* MHz */ + .pll_cntl0 = 0x00030441, + .pll_cntl1 = 0x802000b1, + .pll_cntl2 = 0x11002320, + .pll_cntl3 = 0xd0010000, + .pll_cntl4 = 0x45004000, + .pll_cntl5 = 0x51a051a, + .pll_cntl6 = 0x01888585 + }, + .gp0_pll[1] = { + .pll_clk = 744, /* MHz */ + .pll_cntl0 = 0x0003041f, + .pll_cntl1 = 0x802000b1, + .pll_cntl2 = 0x11002320, + .pll_cntl3 = 0xd0010000, + .pll_cntl4 = 0x45004000, + .pll_cntl5 = 0x51a051a, + .pll_cntl6 = 0x01888585 + }, +}; + +#define PLL_RATE(_rate, _m, _n, _od) \ +{ \ + .rate = (_rate), \ + .m = (_m), \ + .n = (_n), \ + .od = (_od), \ +} + +#define DDSPLL_RATE(_RATE, _CTS, _N) \ +{ \ + .RATE = (_RATE), \ + .CTS= (_CTS), \ + .N = (_N), \ +} + +static void pll_report(unsigned int flag, char * name) +{ + if (flag) + printf("%s pll test failed!\n", name); + else + printf("%s pll test pass!\n", name); + return; +} + +static int clk_around(unsigned int clk, unsigned int cmp) +{ + if (((cmp - 2) <= clk) && (clk <= (cmp + 2))) + return 1; + else + return 0; +} + +void clocks_set_sys_cpu_clk(uint32_t src) +{ + /* + * src + * 0: use 24M, 1: use SYS PLL + */ + uint32_t control; + uint32_t dyn_pre_mux; + uint32_t dyn_post_mux; + uint32_t dyn_div; + //runtime_info_t info; + + // Make sure not busy from last setting and we currently match the last setting + do { + control = readl(CPUCTRL_CLK_CTRL0); + } while( (control & (1 << 28)) ); + + control = control | (1 << 26);// Enable + + dyn_pre_mux = 0; //use oscin + dyn_post_mux = 0; + dyn_div = 0;/* divide by 1 */ + + // Select Dynamic mux + if (src == 1) { + control = control | (1 << 11); + } + else { + control = control & ~(1 << 11); + if (control & (1 << 10)) {// if using Dyn mux1, set dyn mux 0 + // Toggle bit[10] indicating a dynamic mux change + control = (control & ~((1 << 10) | (0x3f << 4) | (1 << 2) | (0x3 << 0))) + | ((0 << 10) + | (dyn_div << 4) + | (dyn_post_mux << 2) + | (dyn_pre_mux << 0)); + } else { + // Toggle bit[10] indicating a dynamic mux change + control = (control & ~((1 << 10) | (0x3f << 20) | (1 << 18) | (0x3 << 16))) + | ((1 << 10) + | (dyn_div << 20) + | (dyn_post_mux << 18) + | (dyn_pre_mux << 16)); + } + } + + writel(control, CPUCTRL_CLK_CTRL0); + + return; +} + +static int sys_pll_init(sys_pll_set_t * sys_pll_set) +{ + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int lock_timeout = 0; + + do { + _udelay(5); + writel(sys_pll_set->pll_cntl0 | (1 << 29), + ANACTRL_SYSPLL_CTRL0); + writel(sys_pll_set->pll_cntl1, ANACTRL_SYSPLL_CTRL1); + writel(sys_pll_set->pll_cntl2, ANACTRL_SYSPLL_CTRL2); + writel(sys_pll_set->pll_cntl3, ANACTRL_SYSPLL_CTRL3); + writel(sys_pll_set->pll_cntl0 | (1 << 28) | (1 << 29), + ANACTRL_SYSPLL_CTRL0); + _udelay(5); + writel(sys_pll_set->pll_cntl0 | (1 << 28), + ANACTRL_SYSPLL_CTRL0); + _udelay(10); + writel(sys_pll_set->pll_cntl0 | (1 << 28) | (1 << 27), + ANACTRL_SYSPLL_CTRL0); + lock_timeout = 80; + do { + _udelay(5); + } while ((0 == ((Rd(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) && + (--lock_timeout)); + } while((0 == ((Rd(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) && + (--lock_check)); + if (lock_check != 0) + return 0; + else + return RET_PLL_LOCK_FAIL; +} + + +static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg) +{ + unsigned int i = 0; + int ret = 0; + + for (i = 0; i < (sizeof(sys_pll_clk) / sizeof(uint32_t)); i++) { + sys_pll_cfg->sys_pll[0].cpu_clk = sys_pll_clk[i]; + ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i])); + } + return ret; +} + + +static int sys_pll_test(sys_pll_set_t * sys_pll_set) +{ + unsigned int clk_msr_val = 0; + unsigned int sys_clk = 0, od = 0; + int ret = 0; + + /* switch sys clk to oscillator */ + clocks_set_sys_cpu_clk(0); + + /* store current sys pll cntl */ + sys_pll_set_t sys_pll; + sys_pll.pll_cntl0 = readl(ANACTRL_SYSPLL_CTRL0) & (~(0x7 << 27)); + sys_pll.pll_cntl1 = readl(ANACTRL_SYSPLL_CTRL1); + sys_pll.pll_cntl2 = readl(ANACTRL_SYSPLL_CTRL2); + sys_pll.pll_cntl3 = readl(ANACTRL_SYSPLL_CTRL3); + + if (sys_pll_set->cpu_clk == 0) { + sys_clk = (24 * (sys_pll_set->pll_cntl0 & 0xFF)) / + ((sys_pll_set->pll_cntl0 >> 10) & 0x1F); + } + + if (0 == sys_pll_set->pll_cntl0) { + printf("sys pll cntl equal NULL, skip\n"); + return -1; + } + + od = (sys_pll_set->pll_cntl0 >> 20) & 0x3; + /* test sys pll */ + if (sys_pll_set->cpu_clk) + sys_clk = sys_pll_set->cpu_clk; + + ret = sys_pll_init(sys_pll_set); + if (ret) { + printf("SYS pll lock Failed! - %4d MHz\n", sys_clk); + } else { + printf("SYS pll lock OK! - %4d MHz >> %d/Div16 - %4d MHz.", + sys_clk, od, (sys_clk >> od) >> PLL_DIV16_OFFSET); + clocks_set_sys_cpu_clk(1); + /*open div16*/ + writel(readl(CPUCTRL_CLK_CTRL1) | (1 << 24) | (1 << 1), + CPUCTRL_CLK_CTRL1); + clk_msr_val = clk_util_clk_msr(45); + printf("CLKMSR(45) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, (sys_clk >> od) >> + SYS_PLL_TEST_DIV)) { + /* sys clk/pll div16 */ + printf(": Match\n"); + } else { + ret = RET_CLK_NOT_MATCH; + printf(": MisMatch\n"); + } + } + + /* restore sys pll */ + clocks_set_sys_cpu_clk(0); + //printf("cpu = 0x%x\n", readl(CPUCTRL_CLK_CTRL0)); + ret = sys_pll_init(&sys_pll); + if (ret) + printf("restore sys pll lock Failed!\n"); + clocks_set_sys_cpu_clk(1); + + return ret; +} + + +static int fix_pll_test(void) +{ + return 0; +} + +static int ddr_pll_test(void) +{ + return 0; +} + +static int hifi_pll_test(hifi_pll_set_t * hifi_pll) +{ + int ret = 0; + unsigned int pll_clk = 0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0; + + if (hifi_pll->pll_clk == 0) + pll_clk = (24 / ((hifi_pll->pll_cntl0 >> 10) & 0x1F) * + (hifi_pll->pll_cntl0 & 0x1FF)); + else + pll_clk = hifi_pll->pll_clk; + + do { + writel(hifi_pll->pll_cntl0 | (1 << 29), + ANACTRL_HIFIPLL_CTRL0); + writel(hifi_pll->pll_cntl1, ANACTRL_HIFIPLL_CTRL1); + writel(hifi_pll->pll_cntl2, ANACTRL_HIFIPLL_CTRL2); + writel(hifi_pll->pll_cntl3, ANACTRL_HIFIPLL_CTRL3); + writel(hifi_pll->pll_cntl4, ANACTRL_HIFIPLL_CTRL4); + _udelay(5); + writel(hifi_pll->pll_cntl0 | (1 << 28) | (1 << 29), + ANACTRL_HIFIPLL_CTRL0); + _udelay(5); + writel(hifi_pll->pll_cntl0 | (1 << 28), + ANACTRL_HIFIPLL_CTRL0); + _udelay(10); + writel(hifi_pll->pll_cntl4 | (1 << 0), ANACTRL_HIFIPLL_CTRL4); + _udelay(100); + } while((0 == ((Rd(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) && + (--lock_check)); + + if (0 == lock_check) { + printf("HIFI pll lock Failed! - %4d MHz\n", pll_clk); + ret += RET_PLL_LOCK_FAIL; + } else { + printf("HIFI pll lock OK! - %4d MHz. Div8 - %4d MHz. ", + pll_clk, pll_clk >> PLL_DIV8_OFFSET); + + Wr(CLKTREE_SPICC_CLK_CTRL, ((3 << 9) | (1 << 8) | (0 << 0))); + clk_msr_val = clk_util_clk_msr(16); + printf("CLKMSR(16) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk >> PLL_DIV8_OFFSET)) { + printf(": Match\n"); + } else { + printf(": MisMatch\n"); + ret += RET_CLK_NOT_MATCH; + } + } + + return ret; +} + +static int hifi_pll_test_all(hifi_pll_cfg_t * hifi_pll_cfg) +{ + unsigned int i = 0; + int ret = 0; + + for (i = 0; i < (sizeof(hifi_pll_clk) / sizeof(uint32_t)); i++) + ret += hifi_pll_test(&(hifi_pll_cfg->hifi_pll[i])); + return ret; +} + +static int gp_pll_test(gp_pll_set_t * gp_pll) +{ + int ret = 0; + unsigned int pll_clk = 0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0; + + if (gp_pll->pll_clk == 0) + pll_clk = (24 / ((gp_pll->pll_cntl0 >> 10) & 0x1F) * + (gp_pll->pll_cntl0 & 0xFF)); + else + pll_clk = gp_pll->pll_clk; + + lock_check = PLL_LOCK_CHECK_MAX; + do { + writel(gp_pll->pll_cntl0 | (1 << 29), ANACTRL_GPPLL_CTRL0); + writel(gp_pll->pll_cntl1, ANACTRL_GPPLL_CTRL1); + writel(gp_pll->pll_cntl2, ANACTRL_GPPLL_CTRL2); + writel(gp_pll->pll_cntl3, ANACTRL_GPPLL_CTRL3); + writel(gp_pll->pll_cntl4, ANACTRL_GPPLL_CTRL4); + writel(gp_pll->pll_cntl5, ANACTRL_GPPLL_CTRL5); + writel(gp_pll->pll_cntl6, ANACTRL_GPPLL_CTRL6); + _udelay(5); + writel(gp_pll->pll_cntl0 | (1 << 28) | (1 << 29), + ANACTRL_GPPLL_CTRL0); + _udelay(5); + writel(gp_pll->pll_cntl0 | (1 << 28), + ANACTRL_GPPLL_CTRL0); + _udelay(10); + writel(gp_pll->pll_cntl4 | (1 << 0), ANACTRL_GPPLL_CTRL4); + _udelay(100); + } while ((!((readl(ANACTRL_GPPLL_STS) >> 31) & 0x1)) && --lock_check); + + if (0 == lock_check) { + printf("GP pll lock Failed! - %4d MHz\n", pll_clk); + ret = RET_PLL_LOCK_FAIL; + } else { + printf("GP pll lock OK! - %4d MHz. Div8 - %4d MHz. ", + pll_clk, pll_clk >> PLL_DIV8_OFFSET); + Wr(CLKTREE_SPICC_CLK_CTRL, ((4 << 9) | (1 << 8) | (0 << 0))); + /* get gp_pll_clk */ + clk_msr_val = clk_util_clk_msr(16); + printf("CLKMSR(16) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk >> PLL_DIV8_OFFSET)) { + printf(": Match\n"); + } else { + printf(": MisMatch\n"); + ret += RET_CLK_NOT_MATCH; + } + } + return ret; +} + +static int gp_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg) +{ + unsigned int i = 0; + int ret = 0; + for (i = 0; i < (sizeof(gp0_pll_cfg_t) / sizeof(gp_pll_set_t)); i++) + ret += gp_pll_test(&(gp0_pll_cfg->gp0_pll[i])); + return ret; +} + +static int dds_pll_test(dds_pll_set_t * dds_pll) +{ + int ret=0; + #if 0 //2020.02.20 + unsigned int i=0, pll_clk=0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0; + + for (i=0; i<(sizeof(ddspll_tbl)/sizeof(ddspll_tbl[0])); i++) { + if (((dds_pll->pll_cntl3)/(dds_pll->pll_cntl4)) == ((ddspll_tbl[i].CTS)/(ddspll_tbl[i].N))) { + pll_clk = ddspll_tbl[i].RATE; + } + } + do { + writel(dds_pll->misctop_cntl0, ANACTRL_MISCTOP_CTRL0); + writel(dds_pll->pll_cntl0, ANACTRL_AUDDDS_CTRL0); + writel(dds_pll->pll_cntl1, ANACTRL_AUDDDS_CTRL1); + writel(dds_pll->pll_cntl2, ANACTRL_AUDDDS_CTRL2); + writel(dds_pll->pll_cntl3, ANACTRL_AUDDDS_CTRL3); + writel(dds_pll->pll_cntl4, ANACTRL_AUDDDS_CTRL4); + writel((dds_pll->pll_cntl0 | (1<<29) | (1<<10) | (1<<11)) & ~(1<<28), ANACTRL_AUDDDS_CTRL0); + + writel(dds_pll->pll_cntl1 | (1<<31), ANACTRL_AUDDDS_CTRL1); + + //printf("gp lock_check: %4d\n", lock_check); + } while ((!((readl(ANACTRL_AUDDDS_STS)>>31)&0x1)) && --lock_check); + if (0 == lock_check) { + printf("dds pll lock Failed! - %4d MHz\n", pll_clk); + ret = RET_PLL_LOCK_FAIL; + } + else { + printf("dds pll lock OK! - %4d MHz.", pll_clk); + clk_msr_val = clk_util_clk_msr(44); + printf("CLKMSR(44) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk)) { + printf(": Match\n"); + } + else { + printf(": MisMatch\n"); + ret += RET_CLK_NOT_MATCH; + } + } + #endif + return ret; +} + +static int dds_pll_test_all(void) +{ + #if 0 //2020.02.20 + unsigned int i=0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0; + int ret=0; + //unsigned int ctrl0 = 0; + + for (i=0; i<(sizeof(ddspll_tbl)/sizeof(ddspll_tbl[0])); i++) { + //ctrl0 = 0; + //ctrl0 = ctrl0 | ((gpll0_tbl[i].m)<<0) | ((gpll0_tbl[i].n)<<10); + do { + writel(0x4, ANACTRL_MISCTOP_CTRL0); + writel(0x50041340, ANACTRL_AUDDDS_CTRL0); + writel(0x0, ANACTRL_AUDDDS_CTRL1); + writel(0x0, ANACTRL_AUDDDS_CTRL2); + writel(ddspll_tbl[i].CTS, ANACTRL_AUDDDS_CTRL3); + writel(ddspll_tbl[i].N, ANACTRL_AUDDDS_CTRL4); + writel(0x60041f40, ANACTRL_AUDDDS_CTRL0); + writel(0x80000000, ANACTRL_AUDDDS_CTRL1); + } while((0 == ((Rd(ANACTRL_AUDDDS_STS) >> 31) & 0x1)) && (--lock_check)); + + if (0 == lock_check) { + printf("dds pll lock Failed! - %4d MHz\n", ddspll_tbl[i].RATE); + ret += RET_PLL_LOCK_FAIL; + } + else { + printf("dds pll lock OK! - %4d MHz.", ddspll_tbl[i].RATE); + //Wr(CLKTREE_SPICC_CLK_CTRL, ((4<<9) | (1<<8) | (7<<0))); + //printf("CLKTREE_SPICC_CLK_CTRL: 0x%8x\n", readl(CLKTREE_SPICC_CLK_CTRL)); + clk_msr_val = clk_util_clk_msr(44); + printf("CLKMSR(44) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, ddspll_tbl[i].RATE)) { + printf(": Match\n"); + } + else { + printf(": MisMatch\n"); + ret += RET_CLK_NOT_MATCH; + } + } + } + return ret; + #endif + + return 0; +} + +static int usbphy_pll_test(usbphy_pll_set_t * usbphy_pll) +{ + int ret = 0; + unsigned int pll_clk = 0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned long usbphy_base_cfg = 0xFE004000; + + if ((usbphy_pll->pll_cntl0 & 0x1FF) == 0x14) { + pll_clk = 480; + } else { + printf("input frequency point is not support\n"); + return -1; + } + writel(usbphy_pll->pll_cntl0, (usbphy_base_cfg + 0x40)); + writel(usbphy_pll->pll_cntl1, (usbphy_base_cfg + 0x44)); + writel(usbphy_pll->pll_cntl2, (usbphy_base_cfg + 0x48)); + + lock_check = PLL_LOCK_CHECK_MAX; + do { + update_bits((usbphy_base_cfg + 0x40), 1<<29, 1 << 29); + _udelay(10); + update_bits((usbphy_base_cfg + 0x40), 1<<29, 0); + _udelay(100); + //printf("ethphy lock_check: %4d\n", lock_check); + } while ((!((readl(usbphy_base_cfg + 0x40)>>31)&0x1)) && --lock_check); + if (0 == lock_check) { + printf("usbphy pll lock Failed! - %4d MHz\n", pll_clk); + ret = RET_PLL_LOCK_FAIL; + } else { + printf("usbphy pll lock OK! - %4d MHz.\n", pll_clk); + } + + return ret; +} + +static int usbphy_pll_test_all(void) +{ + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + int ret=0; + unsigned long usbphy_base_cfg = 0xFE004000; + + writel(0x09400414, (usbphy_base_cfg + 0x40)); + writel(0x927e0000, (usbphy_base_cfg + 0x44)); + writel(0xac5f69e5, (usbphy_base_cfg + 0x48)); + writel(0x29400414, (usbphy_base_cfg + 0x40)); + writel(0x09400414, (usbphy_base_cfg + 0x40)); + + do { + update_bits((usbphy_base_cfg + 0x40), 1<<29, 1 << 29); + _udelay(10); + update_bits((usbphy_base_cfg + 0x40), 1<<29, 0); + _udelay(100); + //printf("usbphy lock_check: %4d\n", lock_check); + } while ((!((readl(usbphy_base_cfg + 0x40)>>31)&0x1)) && --lock_check); + + if (0 == lock_check) { + printf("usbphy pll lock Failed! - 480MHz\n"); + ret += RET_PLL_LOCK_FAIL; + } else { + printf("usbphy pll lock OK! - 480MHz.\n"); + } + + return ret; +} + +static int ethphy_pll_test(ethphy_pll_set_t * ethphy_pll) +{ + int ret = 0; + unsigned int pll_clk=0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0; + + if ((ethphy_pll->pll_cntl0 & 0x1FF) == 0xA) { + pll_clk = 500; + } else { + printf("input frequency point is not support\n"); + return -1; + } + + do { + writel(ethphy_pll->pll_cntl0 | 0x30000000, ETH_PLL_CTL0); + writel(ethphy_pll->pll_cntl1, ETH_PLL_CTL1); + writel(ethphy_pll->pll_cntl2, ETH_PLL_CTL2); + _udelay(150); + writel(ethphy_pll->pll_cntl0 | 0x10000000, ETH_PLL_CTL0); + _udelay(150); + } while ((!((readl(ETH_PLL_CTL0)>>30)&0x1))&& --lock_check); + + if (0 == lock_check) { + printf("ETHPHY pll lock Failed! - %4d MHz\n", pll_clk); + ret = RET_PLL_LOCK_FAIL; + } else { + printf("ETHPHY pll lock OK! - %4d MHz. ", pll_clk); + /* get ethphy_pll_clk */ + clk_msr_val = clk_util_clk_msr(64)<<2; + printf("CLKMSR(64) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk)) { + printf(": Match\n"); + } else { + printf(": MisMatch\n"); + ret = RET_CLK_NOT_MATCH; + } + } + return ret; +} + +static int ethphy_pll_test_all(void) +{ + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0; + int ret = 0; + + do { + writel(0x9c0040a | 0x30000000, ETH_PLL_CTL0); + writel(0x927e0000, ETH_PLL_CTL1); + writel(0xac5f49e5, ETH_PLL_CTL2); + writel(0x00000000, ETH_PLL_CTL3); + _udelay(150); + writel(0x9c0040a | 0x10000000, ETH_PLL_CTL0); + _udelay(150); + } while ((!((readl(ETH_PLL_CTL0)>>30)&0x1))&& --lock_check); + + if (0 == lock_check) { + printf("ethphy pll lock Failed! - 500MHz\n"); + ret += RET_PLL_LOCK_FAIL; + } else { + printf("ethphy pll lock OK! - 500MHz. "); + /* get ethphy_pll_clk */ + clk_msr_val = clk_util_clk_msr(64)<<2; + printf("CLKMSR(64) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, 500)) { + printf(": Match\n"); + } else { + printf(": MisMatch\n"); + ret += RET_CLK_NOT_MATCH; + } + } + + return ret; +} + +static int pll_test_all(unsigned char * pll_list) +{ + int ret = 0; + unsigned char i = 0; + for (i = 0; i < PLL_ENUM; i++) { + switch (pll_list[i]) { + case PLL_SYS: + ret = sys_pll_test_all(&sys_pll_cfg); + pll_report(ret, STR_PLL_TEST_SYS); + break; + case PLL_FIX: + ret = fix_pll_test(); + pll_report(ret, STR_PLL_TEST_FIX); + break; + case PLL_DDR: + ret = ddr_pll_test(); + pll_report(ret, STR_PLL_TEST_DDR); + break; + case PLL_HIFI: + ret = hifi_pll_test_all(&hifi_pll_cfg); + pll_report(ret, STR_PLL_TEST_HIFI); + break; + case PLL_GP: + ret = gp_pll_test_all(&gp0_pll_cfg); + pll_report(ret, STR_PLL_TEST_GP); + break; + case PLL_DDS: + ret = dds_pll_test_all(); + pll_report(ret, STR_PLL_TEST_DDS); + break; + case PLL_USBPHY: + ret = usbphy_pll_test_all(); + pll_report(ret, STR_PLL_TEST_USBPHY); + break; + case PLL_ETHPHY: + ret = ethphy_pll_test_all(); + pll_report(ret, STR_PLL_TEST_ETHPHY); + break; + default: + break; + } + } + return ret; +} + +int pll_test(int argc, char * const argv[]) +{ + int ret = 0; + sys_pll_set_t sys_pll_set = {0}; + hifi_pll_set_t hifi_pll_set = {0}; + gp_pll_set_t gp_pll_set = {0}; + dds_pll_set_t dds_pll_set = {0}; + usbphy_pll_set_t usbphy_pll_set = {0}; + ethphy_pll_set_t ethphy_pll_set = {0}; + + unsigned char plls[PLL_ENUM] = { + PLL_SYS, + 0xff,// PLL_FIX, //0xff will skip this pll + 0xff,// PLL_DDR, + PLL_HIFI, + PLL_GP, + 0xff,//PLL_DDS + 0xff,//PLL_USBPHY + 0xff,//PLL_ETHPHY + }; + + if (0 == strcmp(STR_PLL_TEST_ALL, argv[1])) { + printf("Test all plls\n"); + pll_test_all(plls); + } else if(0 == strcmp(STR_PLL_TEST_SYS, argv[1])) { + if (argc == 2) { + ret = sys_pll_test_all(&sys_pll_cfg); + pll_report(ret, STR_PLL_TEST_SYS); + } else if (argc != 6) { + printf("%s pll test: args error\n", STR_PLL_TEST_SYS); + return -1; + } else { + sys_pll_set.pll_cntl0 = simple_strtoul(argv[2], + NULL, 16); + sys_pll_set.pll_cntl1 = simple_strtoul(argv[3], + NULL, 16); + sys_pll_set.pll_cntl2 = simple_strtoul(argv[4], + NULL, 16); + sys_pll_set.pll_cntl3 = simple_strtoul(argv[5], + NULL, 16); + ret = sys_pll_test(&sys_pll_set); + pll_report(ret, STR_PLL_TEST_SYS); + } + } else if (0 == strcmp(STR_PLL_TEST_HIFI, argv[1])) { + if (argc == 2) { + ret = hifi_pll_test_all(&hifi_pll_cfg); + pll_report(ret, STR_PLL_TEST_HIFI); + } else if (argc != 7){ + printf("%s pll test: args error\n", STR_PLL_TEST_HIFI); + return -1; + } else { + hifi_pll_set.pll_cntl0 = simple_strtoul(argv[2], + NULL, 16); + hifi_pll_set.pll_cntl1 = simple_strtoul(argv[3], + NULL, 16); + hifi_pll_set.pll_cntl2 = simple_strtoul(argv[4], + NULL, 16); + hifi_pll_set.pll_cntl3 = simple_strtoul(argv[5], + NULL, 16); + hifi_pll_set.pll_cntl4 = simple_strtoul(argv[6], + NULL, 16); + ret = hifi_pll_test(&hifi_pll_set); + pll_report(ret, STR_PLL_TEST_HIFI); + } + } else if (0 == strcmp(STR_PLL_TEST_GP, argv[1])) { + if (argc == 2) { + ret = gp_pll_test_all(&gp0_pll_cfg); + pll_report(ret, STR_PLL_TEST_GP); + } else if (argc != 9) { + printf("%s pll test: args error\n", STR_PLL_TEST_GP); + return -1; + } else { + gp_pll_set.pll_cntl0 = simple_strtoul(argv[2], + NULL, 16); + gp_pll_set.pll_cntl1 = simple_strtoul(argv[3], + NULL, 16); + gp_pll_set.pll_cntl2 = simple_strtoul(argv[4], + NULL, 16); + gp_pll_set.pll_cntl3 = simple_strtoul(argv[5], + NULL, 16); + gp_pll_set.pll_cntl4 = simple_strtoul(argv[6], + NULL, 16); + gp_pll_set.pll_cntl5 = simple_strtoul(argv[7], + NULL, 16); + gp_pll_set.pll_cntl6 = simple_strtoul(argv[8], + NULL, 16); + ret = gp_pll_test(&gp_pll_set); + pll_report(ret, STR_PLL_TEST_GP); + } + } else if (0 == strcmp(STR_PLL_TEST_DDR, argv[1])) { + printf("%s pll not support now\n", STR_PLL_TEST_DDR); + return -1; + } else if (0 == strcmp(STR_PLL_TEST_FIX, argv[1])) { + printf("%s pll not support now\n", STR_PLL_TEST_FIX); + return -1; + } else if (0 == strcmp(STR_PLL_TEST_DDS, argv[1])) { + if (argc == 2) { + ret = dds_pll_test_all(); + pll_report(ret, STR_PLL_TEST_DDS); + } else if (argc != 8) { + printf("%s pll test: args error\n", STR_PLL_TEST_DDS); + return -1; + } else { + dds_pll_set.misctop_cntl0 = simple_strtoul(argv[2], + NULL, 16); + dds_pll_set.pll_cntl0 = simple_strtoul(argv[3], + NULL, 16); + dds_pll_set.pll_cntl1 = simple_strtoul(argv[4], + NULL, 16); + dds_pll_set.pll_cntl2 = simple_strtoul(argv[5], + NULL, 16); + dds_pll_set.pll_cntl3 = simple_strtoul(argv[6], + NULL, 16); + dds_pll_set.pll_cntl4 = simple_strtoul(argv[7], + NULL, 16); + ret = dds_pll_test(&dds_pll_set); + pll_report(ret, STR_PLL_TEST_DDS); + } + } else if (0 == strcmp(STR_PLL_TEST_USBPHY, argv[1])) { + if (argc == 2) { + ret = usbphy_pll_test_all(); + pll_report(ret, STR_PLL_TEST_USBPHY); + } else if (argc != 5) { + printf("%s pll test: args error\n", + STR_PLL_TEST_USBPHY); + return -1; + } else { + usbphy_pll_set.pll_cntl0 = simple_strtoul(argv[2], + NULL, 16); + usbphy_pll_set.pll_cntl1 = simple_strtoul(argv[3], + NULL, 16); + usbphy_pll_set.pll_cntl2 = simple_strtoul(argv[4], + NULL, 16); + ret = usbphy_pll_test(&usbphy_pll_set); + pll_report(ret, STR_PLL_TEST_USBPHY); + } + } else if (0 == strcmp(STR_PLL_TEST_ETHPHY, argv[1])) { + if (argc == 2) { + ret = ethphy_pll_test_all(); + pll_report(ret, STR_PLL_TEST_ETHPHY); + } else if (argc != 5) { + printf("%s pll test: args error\n", + STR_PLL_TEST_ETHPHY); + return -1; + } else { + ethphy_pll_set.pll_cntl0 = simple_strtoul(argv[2], + NULL, 16); + ethphy_pll_set.pll_cntl1 = simple_strtoul(argv[3], + NULL, 16); + ethphy_pll_set.pll_cntl2 = simple_strtoul(argv[4], + NULL, 16); + ret = ethphy_pll_test(ðphy_pll_set); + pll_report(ret, STR_PLL_TEST_ETHPHY); + } + } + + return 0; +}
diff --git a/arch/arm/mach-meson/c2/power_cal.c b/arch/arm/mach-meson/c2/power_cal.c new file mode 100644 index 0000000..e4f9c53 --- /dev/null +++ b/arch/arm/mach-meson/c2/power_cal.c
@@ -0,0 +1,135 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/io.h> +#include <amlogic/saradc.h> +#include <asm/arch/mailbox.h> + +#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2)))) +#define vcck_adc_channel 0x4 +#define ee_adc_channel 0x5 +#define default_ref_val 1800 + +extern const int pwm_cal_voltage_table[][2]; +extern const int pwm_cal_voltage_table_ee[][2]; +extern int pwm_cal_voltage_table_size; +extern int pwm_cal_voltage_table_ee_size; + + +enum pwm_id { + pwm_vcck = 0, + pwm_ee, +}; + +unsigned int _get_time(void) +{ + return P_EE_TIMER_E; +} + +void _udelay_(unsigned int us) +{ + unsigned int t0 = _get_time(); + + while (_get_time() - t0 <= us) + ; +} + +int32_t aml_delt_get(int adc_val, unsigned int voltage) +{ + unsigned int adc_volt; + int32_t delt; + int32_t div = 10; /*10mv is min step*/ + + if (adc_val != -1) { + adc_volt = default_ref_val*adc_val/1024; + printf("aml pwm cal adc_val = %x, adc_voltage = %d, def_voltage = %d\n", + adc_val, adc_volt, voltage); + } else { + adc_volt = voltage; + printf("warning:aml pwm cal adc get voltage error\n"); + return 0; + } + delt = voltage - adc_volt; + delt = delt / div; + return delt; +} + +void aml_set_voltage(unsigned int id, unsigned int voltage, int delt) +{ + int to; + + switch (id) { + case pwm_vcck: + for (to = 0; to < pwm_cal_voltage_table_size; to++) { + if (pwm_cal_voltage_table[to][1] >= voltage) { + break; + } + } + to +=delt; + if (to >= pwm_cal_voltage_table_size) { + to = pwm_cal_voltage_table_size - 1; + } + /*vcck volt set by dvfs and avs*/ + //writel(pwm_voltage_table[to][0], PWM_PWM_A_ADRESS); + _udelay_(200); + break; + + case pwm_ee: + for (to = 0; to < pwm_cal_voltage_table_ee_size; to++) { + if (pwm_cal_voltage_table_ee[to][1] >= voltage) { + break; + } + } + to +=delt; + if (to >= pwm_cal_voltage_table_ee_size) { + to = pwm_cal_voltage_table_ee_size - 1; + } + printf("aml pwm cal before ee_address: %x, ee_voltage: %x\n", + AO_PWM_PWM_B, readl(AO_PWM_PWM_B)); + writel(pwm_cal_voltage_table_ee[to][0],AO_PWM_PWM_B); + _udelay_(1000); + printf("aml pwm cal after ee_address: %x, ee_voltage: %x\n", + AO_PWM_PWM_B, readl(AO_PWM_PWM_B)); + break; + default: + break; + } + _udelay_(200); +} + +int aml_cal_pwm(unsigned int ee_voltage, unsigned int vcck_voltage) +{ + int32_t ee_delt, vcck_delt; + unsigned int ee_val, vcck_val; + int ret; + + /*txlx vcck ch4,vddee ch5*/ + ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION, + vcck_adc_channel, &vcck_val); + if (ret) + return ret; + + ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION, + ee_adc_channel, &ee_val); + if (ret) + return ret; + + vcck_delt = aml_delt_get(vcck_val, vcck_voltage); + ee_delt = aml_delt_get(ee_val, ee_voltage); + send_pwm_delt(vcck_delt, ee_delt); + aml_set_voltage(pwm_ee, AML_VDDEE_INIT_VOLTAGE, ee_delt); + //aml_set_voltage(pwm_vcck, CONFIG_VCCK_INIT_VOLTAGE, vcck_delt); + printf("aml board pwm vcck: %x, ee: %x\n", vcck_delt, ee_delt); + + return 0; +} + +void aml_pwm_cal_init(int mode) +{ + printf("aml pwm cal init\n"); + aml_cal_pwm(AML_VDDEE_INIT_VOLTAGE, AML_VCCK_INIT_VOLTAGE); +}
diff --git a/arch/arm/mach-meson/c2/power_gate.h b/arch/arm/mach-meson/c2/power_gate.h new file mode 100644 index 0000000..9ca1a9d --- /dev/null +++ b/arch/arm/mach-meson/c2/power_gate.h
@@ -0,0 +1,1161 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __POWER_MGR_HEADER_ +#define __POWER_MGR_HEADER_ + +#include <asm/arch/io.h> +#include <common.h> +//#include <asm/arch-gxb/io.h> +/* #include <asm/arch-gxb/register.h> */ +#include <asm/arch/secure_apb.h> +/* clock gate control */ + +#define DEBUG_MASK 0 + +#define SET_CLK_GATE_MASK(reg, mask) __raw_writel((__raw_readl(reg)|mask), reg) +#define CLEAR_CLK_GATE_MASK(reg, mask) \ + __raw_writel((__raw_readl(reg)&(~mask)), reg) +#define CLK_GATE_ON(_MOD) do { \ + if (DEBUG_MASK) \ + printf("on reg %24s before read :0x%x : 0x%x\n",\ + GCLK_NAME_##_MOD, \ + (unsigned int)GCLK_REG_##_MOD, \ + __raw_readl(GCLK_REG_##_MOD)); \ + SET_CLK_GATE_MASK(GCLK_REG_##_MOD, \ + (unsigned int)GCLK_MASK_##_MOD); \ + if (DEBUG_MASK) \ + printf("on reg %24s after read :0x%x : 0x%x\n",\ + GCLK_NAME_##_MOD, \ + (unsigned int)GCLK_REG_##_MOD, \ + __raw_readl(GCLK_REG_##_MOD)); \ + } while (0) + +#define CLK_GATE_OFF(_MOD) do { \ + if (DEBUG_MASK) \ + printf("off reg[ %24s ][0x%08x]before read:0x%08x:0x%08x\n",\ + GCLK_NAME_##_MOD, (int)GCLK_MASK_##_MOD, \ + (unsigned int)GCLK_REG_##_MOD, \ + __raw_readl(GCLK_REG_##_MOD)); \ + CLEAR_CLK_GATE_MASK(GCLK_REG_##_MOD, (unsigned int)GCLK_MASK_##_MOD);\ + if (DEBUG_MASK)\ + printf("off reg[ %24s ][0x%08x] read after:0x%08x:0x%08x\n",\ + GCLK_NAME_##_MOD, \ + (int)GCLK_MASK_##_MOD, \ + (unsigned int)GCLK_REG_##_MOD, \ + __raw_readl(GCLK_REG_##_MOD)); \ + } while (0) + +#define IS_CLK_GATE_ON(_MOD) (__raw_readl(GCLK_REG_##_MOD) & (GCLK_MASK_##_MOD)) +#define GATE_INIT(_MOD) GCLK_ref[GCLK_IDX_##_MOD] = IS_CLK_GATE_ON(_MOD) ? 1 : 0 + +#define GCLK_IDX_DDR 0 +#define GCLK_NAME_DDR "DDR" +#define GCLK_DEV_DDR "CLKGATE_DDR" +#define GCLK_REG_DDR (HHI_GCLK_MPEG0) +#define GCLK_MASK_DDR (1<<0) + +#define GCLK_IDX_DOS 1 +#define GCLK_NAME_DOS "DOS" +#define GCLK_DEV_DOS "CLKGATE_DOS" +#define GCLK_REG_DOS (HHI_GCLK_MPEG0) +#define GCLK_MASK_DOS (1<<1) + +#define GCLK_IDX_RESERVED0_0 2 +#define GCLK_NAME_RESERVED0_0 "RESERVED0_0" +#define GCLK_DEV_RESERVED0_0 "CLKGATE_RESERVED0_0" +#define GCLK_REG_RESERVED0_0 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_0 (1<<2) + +#define GCLK_IDX_RESERVED0_1 3 +#define GCLK_NAME_RESERVED0_1 "RESERVED0_1" +#define GCLK_DEV_RESERVED0_1 "CLKGATE_RESERVED0_1" +#define GCLK_REG_RESERVED0_1 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_1 (1<<3) + +/* #define GCLK_IDX_AHB_BRIDGE 4 */ +/* #define GCLK_NAME_AHB_BRIDGE "AHB_BRIDGE" */ +/* #define GCLK_DEV_AHB_BRIDGE "CLKGATE_AHB_BRIDGE" */ +/* #define GCLK_REG_AHB_BRIDGE (HHI_GCLK_MPEG0) */ +/* #define GCLK_MASK_AHB_BRIDGE (1<<4) */ + +#define GCLK_IDX_ISA 5 +#define GCLK_NAME_ISA "ISA" +#define GCLK_DEV_ISA "CLKGATE_ISA" +#define GCLK_REG_ISA (HHI_GCLK_MPEG0) +#define GCLK_MASK_ISA (1<<5) + +/* NEW ADD */ +#define GCLK_IDX_PL310_CBUS 6 +#define GCLK_NAME_PL310_CBUS "PL310_CBUS" +#define GCLK_DEV_PL310_CBUS "CLKGATE_PL310_CBUS" +#define GCLK_REG_PL310_CBUS (HHI_GCLK_MPEG0) +#define GCLK_MASK_PL310_CBUS (1<<6) + +#define GCLK_IDX_PERIPHS_TOP 7 +#define GCLK_NAME_PERIPHS_TOP "PERIPHS_TOP" +#define GCLK_DEV_PERIPHS_TOP "CLKGATE_PERIPHS_TOP" +#define GCLK_REG_PERIPHS_TOP (HHI_GCLK_MPEG0) +#define GCLK_MASK_PERIPHS_TOP (1<<7) + +#define GCLK_IDX_SPICC 8 +#define GCLK_NAME_SPICC "SPICC" +#define GCLK_DEV_SPICC "CLKGATE_SPICC" +#define GCLK_REG_SPICC (HHI_GCLK_MPEG0) +#define GCLK_MASK_SPICC (1<<8) + +#define GCLK_IDX_I2C 9 +#define GCLK_NAME_I2C "I2C" +#define GCLK_DEV_I2C "CLKGATE_I2C" +#define GCLK_REG_I2C (HHI_GCLK_MPEG0) +#define GCLK_MASK_I2C (1<<9) + +#define GCLK_IDX_SAR_ADC 10 +#define GCLK_NAME_SAR_ADC "SAR_ADC" +#define GCLK_DEV_SAR_ADC "CLKGATE_SAR_ADC" +//#define GCLK_REG_SAR_ADC (HHI_SAR_CLK_CNTL) //no HHI_SAR_CLK_CNTL on TXL +#define GCLK_REG_SAR_ADC (AO_SAR_CLK) +#define GCLK_MASK_SAR_ADC (1<<8) + +#define GCLK_IDX_SMART_CARD_MPEG_DOMAIN 11 +#define GCLK_NAME_SMART_CARD_MPEG_DOMAIN "SMART_CARD_MPEG_DOMAIN" +#define GCLK_DEV_SMART_CARD_MPEG_DOMAIN "CLKGATE_SMART_CARD_MPEG_DOMAIN" +#define GCLK_REG_SMART_CARD_MPEG_DOMAIN (HHI_GCLK_MPEG0) +#define GCLK_MASK_SMART_CARD_MPEG_DOMAIN (1<<11) + +#define GCLK_IDX_RANDOM_NUM_GEN 12 +#define GCLK_NAME_RANDOM_NUM_GEN "RANDOM_NUM_GEN" +#define GCLK_DEV_RANDOM_NUM_GEN "CLKGATE_RANDOM_NUM_GEN" +#define GCLK_REG_RANDOM_NUM_GEN (HHI_GCLK_MPEG0) +#define GCLK_MASK_RANDOM_NUM_GEN (1<<12) + +#define GCLK_IDX_UART0 13 +#define GCLK_NAME_UART0 "UART0" +#define GCLK_DEV_UART0 "CLKGATE_UART0" +#define GCLK_REG_UART0 (HHI_GCLK_MPEG0) +#define GCLK_MASK_UART0 (1<<13) + +/* gxb no this clock gate */ +/* #define GCLK_IDX_SDHC 14 */ +/* #define GCLK_NAME_SDHC "SDHC" */ +/* #define GCLK_DEV_SDHC "CLKGATE_SDHC" */ +/* #define GCLK_REG_SDHC (HHI_GCLK_MPEG0) */ +/* #define GCLK_MASK_SDHC (1<<14) */ + +#define GCLK_IDX_STREAM 15 +#define GCLK_NAME_STREAM "STREAM" +#define GCLK_DEV_STREAM "CLKGATE_STREAM" +#define GCLK_REG_STREAM (HHI_GCLK_MPEG0) +#define GCLK_MASK_STREAM (1<<15) + +#define GCLK_IDX_ASYNC_FIFO 16 +#define GCLK_NAME_ASYNC_FIFO "ASYNC_FIFO" +#define GCLK_DEV_ASYNC_FIFO "CLKGATE_ASYNC_FIFO" +#define GCLK_REG_ASYNC_FIFO (HHI_GCLK_MPEG0) +#define GCLK_MASK_ASYNC_FIFO (1<<16) + +/* gxb no this clock gate */ +/* #define GCLK_IDX_SDIO 17 */ +/* #define GCLK_NAME_SDIO "SDIO" */ +/* #define GCLK_DEV_SDIO "CLKGATE_SDIO" */ +/* #define GCLK_REG_SDIO (HHI_GCLK_MPEG0) */ +/* #define GCLK_MASK_SDIO (1<<17) */ + +/* gxb no this clock gate */ +/* #define GCLK_IDX_AUD_BUF 18 */ +/* #define GCLK_NAME_AUD_BUF "AUD_BUF" */ +/* #define GCLK_DEV_AUD_BUF "CLKGATE_AUD_BUF" */ +/* #define GCLK_REG_AUD_BUF (HHI_GCLK_MPEG0) */ +/* #define GCLK_MASK_AUD_BUF (1<<18) */ + +#define GCLK_IDX_HIU_PARSER 19 +#define GCLK_NAME_HIU_PARSER "HIU_PARSER" +#define GCLK_DEV_HIU_PARSER "CLKGATE_HIU_PARSER" +#define GCLK_REG_HIU_PARSER (HHI_GCLK_MPEG0) +#define GCLK_MASK_HIU_PARSER (1<<19) + +#define GCLK_IDX_RESERVED0_2 20 +#define GCLK_NAME_RESERVED0_2 "RESERVED0_2" +#define GCLK_DEV_RESERVED0_2 "CLKGATE_RESERVED0_2" +#define GCLK_REG_RESERVED0_2 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_2 (1<<20) + +/* NEW ADD */ +#define GCLK_IDX_RESERVED0_3 21 +#define GCLK_NAME_RESERVED0_3 "RESERVED0_3 " +#define GCLK_DEV_RESERVED0_3 "CLKGATE_RESERVED0_3 " +#define GCLK_REG_RESERVED0_3 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_3 (1<<21) + +#define GCLK_IDX_RESERVED0_4 22 +#define GCLK_NAME_RESERVED0_4 "RESERVED0_4" +#define GCLK_DEV_RESERVED0_4 "CLKGATE_RESERVED0_4" +#define GCLK_REG_RESERVED0_4 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_4 (1<<22) + +#define GCLK_IDX_ASSIST_MISC 23 +#define GCLK_NAME_ASSIST_MISC "ASSIST_MISC" +#define GCLK_DEV_ASSIST_MISC "CLKGATE_ASSIST_MISC" +#define GCLK_REG_ASSIST_MISC (HHI_GCLK_MPEG0) +#define GCLK_MASK_ASSIST_MISC (1<<23) + + +#define GCLK_IDX_EMMC_A 24 +#define GCLK_NAME_EMMC_A "EMMC_A" +#define GCLK_DEV_EMMC_A "CLKGATE_EMMC_A" +#define GCLK_REG_EMMC_A (HHI_GCLK_MPEG0) +#define GCLK_MASK_EMMC_A (1<<24) + +#define GCLK_IDX_EMMC_B 25 +#define GCLK_NAME_EMMC_B "EMMC_B" +#define GCLK_DEV_EMMC_B "CLKGATE_EMMC_B" +#define GCLK_REG_EMMC_B (HHI_GCLK_MPEG0) +#define GCLK_MASK_EMMC_B (1<<25) + +#define GCLK_IDX_EMMC_C 26 +#define GCLK_NAME_EMMC_C "EMMC_C" +#define GCLK_DEV_EMMC_C "CLKGATE_EMMC_C" +#define GCLK_REG_EMMC_C (HHI_GCLK_MPEG0) +#define GCLK_MASK_EMMC_C (1<<26) + +#define GCLK_IDX_RESERVED0_8 27 +#define GCLK_NAME_RESERVED0_8 "RESERVED0_8" +#define GCLK_DEV_RESERVED0_8 "CLKGATE_RESERVED0_8" +#define GCLK_REG_RESERVED0_8 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_8 (1<<27) + +#define GCLK_IDX_RESERVED0_9 28 +#define GCLK_NAME_RESERVED0_9 "RESERVED0_9" +#define GCLK_DEV_RESERVED0_9 "CLKGATE_RESERVED0_9" +#define GCLK_REG_RESERVED0_9 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_9 (1<<28) + +#define GCLK_IDX_RESERVED0_A 29 +#define GCLK_NAME_RESERVED0_A "RESERVED0_A" +#define GCLK_DEV_RESERVED0_A "CLKGATE_RESERVED0_A" +#define GCLK_REG_RESERVED0_A (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_A (1<<29) + +#define GCLK_IDX_SPI 30 +#define GCLK_NAME_SPI "SPI" +#define GCLK_DEV_SPI "CLKGATE_SPI" +#define GCLK_REG_SPI (HHI_GCLK_MPEG0) +#define GCLK_MASK_SPI (1<<30) + +#define GCLK_IDX_RESERVED0_B 31 +#define GCLK_NAME_RESERVED0_B "RESERVED0_B" +#define GCLK_DEV_RESERVED0_B "CLKGATE_RESERVED0_B" +#define GCLK_REG_RESERVED0_B (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_B (1<<31) + +/**************************************************************/ + +#define GCLK_IDX_RESERVED1_1 32 +#define GCLK_NAME_RESERVED1_1 "RESERVED1_1" +#define GCLK_DEV_RESERVED1_1 "CLKGATE_RESERVED1_1" +#define GCLK_REG_RESERVED1_1 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_1 (1<<0) + + +#define GCLK_IDX_RESERVED1_2 33 +#define GCLK_NAME_RESERVED1_2 "RESERVED1_2" +#define GCLK_DEV_RESERVED1_2 "CLKGATE_RESERVED1_2" +#define GCLK_REG_RESERVED1_2 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_2 (1<<1) + + +#define GCLK_IDX_AUD_IN 34 +#define GCLK_NAME_AUD_IN "AUD_IN" +#define GCLK_DEV_AUD_IN "CLKGATE_AUD_IN" +#define GCLK_REG_AUD_IN (HHI_GCLK_MPEG1) +#define GCLK_MASK_AUD_IN (1<<2) + +#define GCLK_IDX_ETHERNET 35 +#define GCLK_NAME_ETHERNET "ETHERNET" +#define GCLK_DEV_ETHERNET "CLKGATE_ETHERNET" +#define GCLK_REG_ETHERNET (HHI_GCLK_MPEG1) +#define GCLK_MASK_ETHERNET (1<<3) + +/* g12a no reg */ +#if 0 +#define GCLK_IDX_ETH_CLK 145 +#define GCLK_NAME_ETH_CLK "ETH_CLK" +#define GCLK_REG_ETH_CLK (HHI_MPLL_CNTL10) +#define GCLK_MASK_ETH_CLK (1<<3) +#endif + +#define GCLK_IDX_DEMUX 36 +#define GCLK_NAME_DEMUX "DEMUX" +#define GCLK_DEV_DEMUX "CLKGATE_DEMUX" +#define GCLK_REG_DEMUX (HHI_GCLK_MPEG1) +#define GCLK_MASK_DEMUX (1<<4) + +#define GCLK_IDX_RESERVED1_3 37 +#define GCLK_NAME_RESERVED1_3 "RESERVED1_3" +#define GCLK_DEV_RESERVED1_3 "CLKGATE_RESERVED1_3" +#define GCLK_REG_RESERVED1_3 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_3 (1<<5) + +#define GCLK_IDX_AIU_AI_TOP_GLUE 38 +#define GCLK_NAME_AIU_AI_TOP_GLUE "AIU_AI_TOP_GLUE" +#define GCLK_DEV_AIU_AI_TOP_GLUE "CLKGATE_AIU_AI_TOP_GLUE" +#define GCLK_REG_AIU_AI_TOP_GLUE (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_AI_TOP_GLUE (1<<6) + +#define GCLK_IDX_AIU_IEC958 39 +#define GCLK_NAME_AIU_IEC958 "AIU_IEC958" +#define GCLK_DEV_AIU_IEC958 "CLKGATE_AIU_IEC958" +#define GCLK_REG_AIU_IEC958 (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_IEC958 (1<<7) + +#define GCLK_IDX_AIU_I2S_OUT 40 +#define GCLK_NAME_AIU_I2S_OUT "AIU_I2S_OUT" +#define GCLK_DEV_AIU_I2S_OUT "CLKGATE_AIU_I2S_OUT" +#define GCLK_REG_AIU_I2S_OUT (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_I2S_OUT (1<<8) + +#define GCLK_IDX_AIU_AMCLK_MEASURE 41 +#define GCLK_NAME_AIU_AMCLK_MEASURE "AIU_AMCLK_MEASURE" +#define GCLK_DEV_AIU_AMCLK_MEASURE "CLKGATE_AIU_AMCLK_MEASURE" +#define GCLK_REG_AIU_AMCLK_MEASURE (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_AMCLK_MEASURE (1<<9) + +#define GCLK_IDX_AIU_AIFIFO2 42 +#define GCLK_NAME_AIU_AIFIFO2 "AIU_AIFIFO2" +#define GCLK_DEV_AIU_AIFIFO2 "CLKGATE_AIU_AIFIFO2" +#define GCLK_REG_AIU_AIFIFO2 (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_AIFIFO2 (1<<10) + +#define GCLK_IDX_AIU_AUD_MIXER 43 +#define GCLK_NAME_AIU_AUD_MIXER "AIU_AUD_MIXER" +#define GCLK_DEV_AIU_AUD_MIXER "CLKGATE_AIU_AUD_MIXER" +#define GCLK_REG_AIU_AUD_MIXER (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_AUD_MIXER (1<<11) + +#define GCLK_IDX_AIU_MIXER_REG 44 +#define GCLK_NAME_AIU_MIXER_REG "AIU_MIXER_REG" +#define GCLK_DEV_AIU_MIXER_REG "CLKGATE_AIU_MIXER_REG" +#define GCLK_REG_AIU_MIXER_REG (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_MIXER_REG (1<<12) + +#define GCLK_IDX_AIU_ADC 45 +#define GCLK_NAME_AIU_ADC "AIU_ADC" +#define GCLK_DEV_AIU_ADC "CLKGATE_AIU_ADC" +#define GCLK_REG_AIU_ADC (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_ADC (1<<13) + +#define GCLK_IDX_BLK_MOV 46 +#define GCLK_NAME_BLK_MOV "BLK_MOV" +#define GCLK_DEV_BLK_MOV "CLKGATE_BLK_MOV" +#define GCLK_REG_BLK_MOV (HHI_GCLK_MPEG1) +#define GCLK_MASK_BLK_MOV (1<<14) + +/* NEW ADD */ +#define GCLK_IDX_AIU_TOP_LEVEL 47 +#define GCLK_NAME_AIU_TOP_LEVEL "AIU_TOP_LEVEL" +#define GCLK_DEV_AIU_TOP_LEVEL "CLKGATE_AIU_TOP_LEVEL" +#define GCLK_REG_AIU_TOP_LEVEL (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_TOP_LEVEL (1<<15) + +//g12a no reg +#if 0 +#define GCLK_NAME_PCM_MCLK "PCM_MCLK" +#define GCLK_REG_PCM_MCLK (HHI_PCM_CLK_CNTL) +#define GCLK_MASK_PCM_MCLK (1<<9) + +#define GCLK_NAME_PCM_SCLK "PCM_SCLK" +#define GCLK_REG_PCM_SCLK (HHI_PCM_CLK_CNTL) +#define GCLK_MASK_PCM_SCLK (1<<22) +#endif + +#define GCLK_IDX_UART1 48 +#define GCLK_NAME_UART1 "UART1" +#define GCLK_DEV_UART1 "CLKGATE_UART1" +#define GCLK_REG_UART1 (HHI_GCLK_MPEG1) +#define GCLK_MASK_UART1 (1<<16) + +#define GCLK_IDX_RESERVED1_4 49 +#define GCLK_NAME_RESERVED1_4 "RESERVED1_4" +#define GCLK_DEV_RESERVED1_4 "CLKGATE_RESERVED1_4" +#define GCLK_REG_RESERVED1_4 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_4 (1<<17) + +/* NEW ADD */ +#define GCLK_IDX_RESERVED1_5 50 +#define GCLK_NAME_RESERVED1_5 "RESERVED1_5" +#define GCLK_DEV_RESERVED1_5 "CLKGATE_RESERVED1_5" +#define GCLK_REG_RESERVED1_5 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_5 (1<<18) + +#define GCLK_IDX_RESERVED1_6 51 +#define GCLK_NAME_RESERVED1_6 "RESERVED1_6" +#define GCLK_DEV_RESERVED1_6 "CLKGATE_RESERVED1_6" +#define GCLK_REG_RESERVED1_6 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_6 (1<<19) + +#define GCLK_IDX_GE2D 52 +#define GCLK_NAME_GE2D "GE2D" +#define GCLK_DEV_GE2D "CLKGATE_GE2D" +#define GCLK_REG_GE2D (HHI_GCLK_MPEG1) +#define GCLK_MASK_GE2D (1<<20) + +#define GCLK_IDX_USB0 53 +#define GCLK_NAME_USB0 "USB0" +#define GCLK_DEV_USB0 "CLKGATE_USB0" +#define GCLK_REG_USB0 (HHI_GCLK_MPEG1) +#define GCLK_MASK_USB0 (1<<21) + +#define GCLK_IDX_USB1 54 +#define GCLK_NAME_USB1 "USB1" +#define GCLK_DEV_USB1 "CLKGATE_USB1" +#define GCLK_REG_USB1 (HHI_GCLK_MPEG1) +#define GCLK_MASK_USB1 (1<<22) + +#define GCLK_IDX_RESET 55 +#define GCLK_NAME_RESET "RESET" +#define GCLK_DEV_RESET "CLKGATE_RESET" +#define GCLK_REG_RESET (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESET (1<<23) + +#define GCLK_IDX_NAND_CLK 56 +#define GCLK_NAME_NAND_CLK "NAND CLK" +#define GCLK_DEV_NAND_CLK "HHI_NAND_CLK" +#define GCLK_REG_NAND_CLK (HHI_NAND_CLK_CNTL) +#define GCLK_MASK_NAND_CLK (1<<7) + +#define GCLK_IDX_HIU_PARSER_TOP 57 +#define GCLK_NAME_HIU_PARSER_TOP "HIU_PARSER_TOP" +#define GCLK_DEV_HIU_PARSER_TOP "CLKGATE_HIU_PARSER_TOP" +#define GCLK_REG_HIU_PARSER_TOP (HHI_GCLK_MPEG1) +#define GCLK_MASK_HIU_PARSER_TOP (1<<25) + +/* NEW ADD */ + +/* g12a no reg */ +#if 0 +#define GCLK_NAME_USB_CLK "USB_CLK" +#define GCLK_REG_USB_CLK (HHI_USB_CLK_CNTL) +#define GCLK_MASK_USB_CLK (1<<9) +#endif + +#define GCLK_IDX_USB_GENERAL 58 +#define GCLK_NAME_USB_GENERAL "USB_GENERAL" +#define GCLK_DEV_USB_GENERAL "CLKGATE_USB_GENERAL" +#define GCLK_REG_USB_GENERAL (HHI_GCLK_MPEG1) +#define GCLK_MASK_USB_GENERAL (1<<26) + +#define GCLK_IDX_RESERVED1_7 59 +#define GCLK_NAME_RESERVED1_7 "RESERVED1_7" +#define GCLK_DEV_RESERVED1_7 "CLKGATE_RESERVED1_7" +#define GCLK_REG_RESERVED1_7 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_7 (1<<27) + +/* #define GCLK_IDX_VDIN1 60 */ +/* #define GCLK_NAME_VDIN1 "VDIN1" */ +/* #define GCLK_DEV_VDIN1 "CLKGATE_VDIN1" */ +/* #define GCLK_REG_VDIN1 (HHI_GCLK_MPEG1) */ +/* #define GCLK_MASK_VDIN1 (1<<28) */ + +#define GCLK_IDX_AHB_ARB0 61 +#define GCLK_NAME_AHB_ARB0 "AHB_ARB0" +#define GCLK_DEV_AHB_ARB0 "CLKGATE_AHB_ARB0" +#define GCLK_REG_AHB_ARB0 (HHI_GCLK_MPEG1) +#define GCLK_MASK_AHB_ARB0 (1<<29) + +#define GCLK_IDX_EFUSE 62 +#define GCLK_NAME_EFUSE "EFUSE" +#define GCLK_DEV_EFUSE "CLKGATE_EFUSE" +#define GCLK_REG_EFUSE (HHI_GCLK_MPEG1) +#define GCLK_MASK_EFUSE (1<<30) + +#define GCLK_IDX_ROM_CLK 63 +#define GCLK_NAME_ROM_CLK "ROM_CLK" +#define GCLK_DEV_ROM_CLK "CLKGATE_ROM_CLK" +#define GCLK_REG_ROM_CLK (HHI_GCLK_MPEG1) +#define GCLK_MASK_ROM_CLK (1<<31) + +/**************************************************************/ + +#define GCLK_IDX_RESERVED2_0 64 +#define GCLK_NAME_RESERVED2_0 "RESERVED2_0" +#define GCLK_DEV_RESERVED2_0 "CLKGATE_RESERVED2_0" +#define GCLK_REG_RESERVED2_0 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_0 (1<<0) + +#define GCLK_IDX_AHB_DATA_BUS 65 +#define GCLK_NAME_AHB_DATA_BUS "AHB_DATA_BUS" +#define GCLK_DEV_AHB_DATA_BUS "CLKGATE_AHB_DATA_BUS" +#define GCLK_REG_AHB_DATA_BUS (HHI_GCLK_MPEG2) +#define GCLK_MASK_AHB_DATA_BUS (1<<1) + +#define GCLK_IDX_AHB_CONTROL_BUS 66 +#define GCLK_NAME_AHB_CONTROL_BUS "AHB_CONTROL_BUS" +#define GCLK_DEV_AHB_CONTROL_BUS "CLKGATE_AHB_CONTROL_BUS" +#define GCLK_REG_AHB_CONTROL_BUS (HHI_GCLK_MPEG2) +#define GCLK_MASK_AHB_CONTROL_BUS (1<<2) + +#define GCLK_IDX_HDMI_INTR_SYNC 67 +#define GCLK_NAME_HDMI_INTR_SYNC "HDMI_INTR_SYNC" +#define GCLK_DEV_HDMI_INTR_SYNC "CLKGATE_HDMI_INTR_SYNC" +#define GCLK_REG_HDMI_INTR_SYNC (HHI_GCLK_MPEG2) +#define GCLK_MASK_HDMI_INTR_SYNC (1<<3) + +#define GCLK_IDX_HDMI_PCLK 68 +#define GCLK_NAME_HDMI_PCLK "HDMI_PCLK" +#define GCLK_DEV_HDMI_PCLK "CLKGATE_HDMI_PCLK" +#define GCLK_REG_HDMI_PCLK (HHI_GCLK_MPEG2) +#define GCLK_MASK_HDMI_PCLK (1<<4) + +#define GCLK_IDX_PDM 69 +#define GCLK_NAME_PDM "PDM" +#define GCLK_DEV_PDM "CLKGATE_PDM" +#define GCLK_REG_PDM (HHI_GCLK_MPEG2) +#define GCLK_MASK_PDM (1<<5) + +#define GCLK_IDX_BT656 70 +#define GCLK_NAME_BT656 "BT656" +#define GCLK_DEV_BT656 "CLKGATE_BT656" +#define GCLK_REG_BT656 (HHI_GCLK_MPEG2) +#define GCLK_MASK_BT656 (1<<6) + +#define GCLK_IDX_BT656_2 71 +#define GCLK_NAME_BT656_2 "BT656_2" +#define GCLK_DEV_BT656_2 "CLKGATE_BT656_2" +#define GCLK_REG_BT656_2 (HHI_GCLK_MPEG2) +#define GCLK_MASK_BT656_2 (1<<7) + +#define GCLK_IDX_MISC_USB1_TO_DDR 72 +#define GCLK_NAME_MISC_USB1_TO_DDR "MISC_USB1_TO_DDR" +#define GCLK_DEV_MISC_USB1_TO_DDR "CLKGATE_MISC_USB1_TO_DDR" +#define GCLK_REG_MISC_USB1_TO_DDR (HHI_GCLK_MPEG2) +#define GCLK_MASK_MISC_USB1_TO_DDR (1<<8) + +#define GCLK_IDX_MISC_USB0_TO_DDR 73 +#define GCLK_NAME_MISC_USB0_TO_DDR "MISC_USB0_TO_DDR" +#define GCLK_DEV_MISC_USB0_TO_DDR "CLKGATE_MISC_USB0_TO_DDR" +#define GCLK_REG_MISC_USB0_TO_DDR (HHI_GCLK_MPEG2) +#define GCLK_MASK_MISC_USB0_TO_DDR (1<<9) + +#define GCLK_IDX_RESERVED2_4 74 +#define GCLK_NAME_RESERVED2_4 "RESERVED2_4" +#define GCLK_DEV_RESERVED2_4 "CLKGATE_RESERVED2_4" +#define GCLK_REG_RESERVED2_4 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_4 (1<<10) + +#define GCLK_IDX_MMC_PCLK 75 +#define GCLK_NAME_MMC_PCLK "MMC_PCLK" +#define GCLK_DEV_MMC_PCLK "CLKGATE_MMC_PCLK" +#define GCLK_REG_MMC_PCLK (HHI_GCLK_MPEG2) +#define GCLK_MASK_MMC_PCLK (1<<11) + +//g12a no reg +#if 0 +#define GCLK_NAME_MMC_A_PCLK "MMC_A_PCLK" +#define GCLK_REG_MMC_A_PCLK (HHI_MPLL_CNTL10) +#define GCLK_MASK_MMC_A_PCLK (1<<2) + +#define GCLK_NAME_MMC_B_PCLK "MMC_B_PCLK" +#define GCLK_REG_MMC_B_PCLK (HHI_MPLL_CNTL10) +#define GCLK_MASK_MMC_B_PCLK (1<<1) + +#define GCLK_NAME_MMC_C_PCLK "MMC_C_PCLK" +#define GCLK_REG_MMC_C_PCLK (HHI_MPLL_CNTL10) +#define GCLK_MASK_MMC_C_PCLK (1<<0) +#endif + +#define GCLK_NAME_EMMC_A_CLK "EMMC_A_CLK" +#define GCLK_REG_EMMC_A_CLK (HHI_SD_EMMC_CLK_CNTL) +#define GCLK_MASK_EMMC_A_CLK (1<<7) + +#define GCLK_NAME_EMMC_B_CLK "EMMC_B_CLK" +#define GCLK_REG_EMMC_B_CLK (HHI_SD_EMMC_CLK_CNTL) +#define GCLK_MASK_EMMC_B_CLK (1<<23) + +#define GCLK_IDX_MISC_DVIN 76 +#define GCLK_NAME_MISC_DVIN "MISC_DVIN" +#define GCLK_DEV_MISC_DVIN "CLKGATE_MISC_DVIN" +#define GCLK_REG_MISC_DVIN (HHI_GCLK_MPEG2) +#define GCLK_MASK_MISC_DVIN (1<<12) + +#define GCLK_IDX_RESERVED2_5 77 +#define GCLK_NAME_RESERVED2_5 "RESERVED2_5" +#define GCLK_DEV_RESERVED2_5 "CLKGATE_RESERVED2_5" +#define GCLK_REG_RESERVED2_5 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_5 (1<<13) + +#define GCLK_IDX_RESERVED2_6 78 +#define GCLK_NAME_RESERVED2_6 "RESERVED2_6" +#define GCLK_DEV_RESERVED2_6 "CLKGATE_RESERVED2_6" +#define GCLK_REG_RESERVED2_6 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_6 (1<<14) + +#define GCLK_IDX_UART2 79 +#define GCLK_NAME_UART2 "UART2" +#define GCLK_DEV_UART2 "CLKGATE_UART2" +#define GCLK_REG_UART2 (HHI_GCLK_MPEG2) +#define GCLK_MASK_UART2 (1<<15) + +#define GCLK_IDX_RESERVED2_7 80 +#define GCLK_NAME_RESERVED2_7 "RESERVED2_7" +#define GCLK_DEV_RESERVED2_7 "CLKGATE_RESERVED2_7" +#define GCLK_REG_RESERVED2_7 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_7 (1<<16) + +#define GCLK_IDX_RESERVED2_8 81 +#define GCLK_NAME_RESERVED2_8 "RESERVED2_8" +#define GCLK_DEV_RESERVED2_8 "CLKGATE_RESERVED2_8" +#define GCLK_REG_RESERVED2_8 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_8 (1<<17) + +#define GCLK_IDX_RESERVED2_9 82 +#define GCLK_NAME_RESERVED2_9 "RESERVED2_9" +#define GCLK_DEV_RESERVED2_9 "CLKGATE_RESERVED2_9" +#define GCLK_REG_RESERVED2_9 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_9 (1<<18) + +#define GCLK_IDX_RESERVED2_A 83 +#define GCLK_NAME_RESERVED2_A "RESERVED2_A" +#define GCLK_DEV_RESERVED2_A "CLKGATE_RESERVED2_A" +#define GCLK_REG_RESERVED2_A (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_A (1<<19) + +#define GCLK_IDX_RESERVED2_B 84 +#define GCLK_NAME_RESERVED2_B "RESERVED2_B" +#define GCLK_DEV_RESERVED2_B "CLKGATE_RESERVED2_B" +#define GCLK_REG_RESERVED2_B (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_B (1<<20) + +#define GCLK_IDX_UART3 85 +#define GCLK_NAME_UART3 "UART3" +#define GCLK_DEV_UART3 "CLKGATE_UART3" +#define GCLK_REG_UART3 (HHI_GCLK_MPEG2) +#define GCLK_MASK_UART3 (1<<21) + +#define GCLK_IDX_SANA 86 +#define GCLK_NAME_SANA "SANA" +#define GCLK_DEV_SANA "CLKGATE_SANA" +#define GCLK_REG_SANA (HHI_GCLK_MPEG2) +#define GCLK_MASK_SANA (1<<22) + +#define GCLK_IDX_RESERVED2_D 87 +#define GCLK_NAME_RESERVED2_D "RESERVED2_D" +#define GCLK_DEV_RESERVED2_D "CLKGATE_RESERVED2_D" +#define GCLK_REG_RESERVED2_D (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_D (1<<23) + +#define GCLK_IDX_RESERVED2_E 88 +#define GCLK_NAME_RESERVED2_E "RESERVED2_E" +#define GCLK_DEV_RESERVED2_E "CLKGATE_RESERVED2_E" +#define GCLK_REG_RESERVED2_E (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_E (1<<24) + +#define GCLK_IDX_VPU_INTR 89 +#define GCLK_NAME_VPU_INTR "VPU_INTR" +#define GCLK_DEV_VPU_INTR "CLKGATE_VPU_INTR" +#define GCLK_REG_VPU_INTR (HHI_GCLK_MPEG2) +#define GCLK_MASK_VPU_INTR (1<<25) + +#define GCLK_IDX_SECURE_AHP_APB3 90 +#define GCLK_NAME_SECURE_AHP_APB3 "SECURE_AHP_APB3" +#define GCLK_DEV_SECURE_AHP_APB3 "CLKGATE_SECURE_AHP_APB3" +#define GCLK_REG_SECURE_AHP_APB3 (HHI_GCLK_MPEG2) +#define GCLK_MASK_SECURE_AHP_APB3 (1<<26) + +#define GCLK_IDX_RESERVED2_F 91 +#define GCLK_NAME_RESERVED2_F "RESERVED2_F" +#define GCLK_DEV_RESERVED2_F "CLKGATE_RESERVED2_F" +#define GCLK_REG_RESERVED2_F (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_F (1<<27) + +#define GCLK_IDX_RESERVED2_10 92 +#define GCLK_NAME_RESERVED2_10 "RESERVED2_10" +#define GCLK_DEV_RESERVED2_10 "CLKGATE_RESERVED2_10" +#define GCLK_REG_RESERVED2_10 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_10 (1<<28) + +#define GCLK_IDX_CLK81_TO_A9 93 +#define GCLK_NAME_CLK81_TO_A9 "CLK81_TO_A9" +#define GCLK_DEV_CLK81_TO_A9 "CLKGATE_CLK81_TO_A9" +#define GCLK_REG_CLK81_TO_A9 (HHI_GCLK_MPEG2) +#define GCLK_MASK_CLK81_TO_A9 (1<<29) + +#define GCLK_IDX_GIC 94 +#define GCLK_NAME_GIC "GIC" +#define GCLK_DEV_GIC "CLKGATE_GIC" +#define GCLK_REG_GIC (HHI_GCLK_MPEG2) +#define GCLK_MASK_GIC (1<<30) + +#define GCLK_IDX_RESERVED2_12 95 +#define GCLK_NAME_RESERVED2_12 "RESERVED2_12" +#define GCLK_DEV_RESERVED2_12 "CLKGATE_RESERVED2_12" +#define GCLK_REG_RESERVED2_12 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_12 (1<<31) + +/**************************************************************/ + +#define GCLK_IDX_RESERVED3_0 96 +#define GCLK_NAME_RESERVED3_0 "RESERVED3_0" +#define GCLK_DEV_RESERVED3_0 "CLKGATE_RESERVED3_0" +#define GCLK_REG_RESERVED3_0 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED3_0 (1<<0) + +#define GCLK_IDX_VCLK2_VENCI 97 +#define GCLK_NAME_VCLK2_VENCI "VCLK2_VENCI" +#define GCLK_DEV_VCLK2_VENCI "CLKGATE_VCLK2_VENCI" +#define GCLK_REG_VCLK2_VENCI (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCI (1<<1) + +#define GCLK_IDX_VCLK2_VENCI1 98 +#define GCLK_NAME_VCLK2_VENCI1 "VCLK2_VENCI1" +#define GCLK_DEV_VCLK2_VENCI1 "CLKGATE_VCLK2_VENCI1" +#define GCLK_REG_VCLK2_VENCI1 (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCI1 (1<<2) + +#define GCLK_IDX_VCLK2_VENCP 99 +#define GCLK_NAME_VCLK2_VENCP "VCLK2_VENCP" +#define GCLK_DEV_VCLK2_VENCP "CLKGATE_VCLK2_VENCP" +#define GCLK_REG_VCLK2_VENCP (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCP (1<<3) + +#define GCLK_IDX_VCLK2_VENCP1 100 +#define GCLK_NAME_VCLK2_VENCP1 "VCLK2_VENCP1" +#define GCLK_DEV_VCLK2_VENCP1 "CLKGATE_VCLK2_VENCP1" +#define GCLK_REG_VCLK2_VENCP1 (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCP1 (1<<4) + +#define GCLK_IDX_VCLK2_VENCT 101 +#define GCLK_NAME_VCLK2_VENCT "VCLK2_VENCT" +#define GCLK_DEV_VCLK2_VENCT "CLKGATE_VCLK2_VENCT" +#define GCLK_REG_VCLK2_VENCT (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCT (1<<5) + +#define GCLK_IDX_VCLK2_VENCT1 102 +#define GCLK_NAME_VCLK2_VENCT1 "VCLK2_VENCT1" +#define GCLK_DEV_VCLK2_VENCT1 "CLKGATE_VCLK2_VENCT1" +#define GCLK_REG_VCLK2_VENCT1 (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCT1 (1<<6) + +#define GCLK_IDX_VCLK2_OTHER 103 +#define GCLK_NAME_VCLK2_OTHER "VCLK2_OTHER" +#define GCLK_DEV_VCLK2_OTHER "CLKGATE_VCLK2_OTHER" +#define GCLK_REG_VCLK2_OTHER (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_OTHER (1<<7) + +#define GCLK_IDX_VCLK2_ENCI 104 +#define GCLK_NAME_VCLK2_ENCI "VCLK2_ENCI" +#define GCLK_DEV_VCLK2_ENCI "CLKGATE_VCLK2_ENCI" +#define GCLK_REG_VCLK2_ENCI (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_ENCI (1<<8) + +#define GCLK_IDX_VCLK2_ENCP 105 +#define GCLK_NAME_VCLK2_ENCP "VCLK2_ENCP" +#define GCLK_DEV_VCLK2_ENCP "CLKGATE_VCLK2_ENCP" +#define GCLK_REG_VCLK2_ENCP (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_ENCP (1<<9) + +#define GCLK_IDX_DAC_CLK 106 +#define GCLK_NAME_DAC_CLK "DAC_CLK" +#define GCLK_DEV_DAC_CLK "CLKGATE_DAC_CLK" +#define GCLK_REG_DAC_CLK (HHI_GCLK_OTHER) +#define GCLK_MASK_DAC_CLK (1<<10) + +#define GCLK_IDX_RESERVED3_1 107 +#define GCLK_NAME_RESERVED3_1 "RESERVED3_1" +#define GCLK_DEV_RESERVED3_1 "CLKGATE_RESERVED3_1" +#define GCLK_REG_RESERVED3_1 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED3_1 (1<<11) + +#define GCLK_IDX_RESERVED3_2 108 +#define GCLK_NAME_RESERVED3_2 "RESERVED3_2" +#define GCLK_DEV_RESERVED3_2 "CLKGATE_RESERVED3_2" +#define GCLK_REG_RESERVED3_2 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED3_2 (1<<12) + +#define GCLK_IDX_RESERVED3_3 109 +#define GCLK_NAME_RESERVED3_3 "RESERVED3_3" +#define GCLK_DEV_RESERVED3_3 "CLKGATE_RESERVED3_3" +#define GCLK_REG_RESERVED3_3 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED3_3 (1<<13) + +#define GCLK_IDX_AIU_AOCLK 110 +#define GCLK_NAME_AIU_AOCLK "AIU_AOCLK" +#define GCLK_DEV_AIU_AOCLK "CLKGATE_AIU_AOCLK" +#define GCLK_REG_AIU_AOCLK (HHI_GCLK_OTHER) +#define GCLK_MASK_AIU_AOCLK (1<<14) + +#define GCLK_IDX_RESERVED3_4 111 +#define GCLK_NAME_RESERVED3_4 "RESERVED3_4" +#define GCLK_DEV_RESERVED3_4 "CLKGATE_RESERVED3_4" +#define GCLK_REG_RESERVED3_4 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_4 (1<<15) + +#define GCLK_IDX_AIU_ICE958_AMCLK 112 +#define GCLK_NAME_AIU_ICE958_AMCLK "AIU_ICE958_AMCLK" +#define GCLK_DEV_AIU_ICE958_AMCLK "CLKGATE_AIU_ICE958_AMCLK" +#define GCLK_REG_AIU_ICE958_AMCLK (HHI_GCLK_OTHER) +#define GCLK_MASK_AIU_ICE958_AMCLK (1<<16) + +#define GCLK_IDX_RESERVED3_5 113 +#define GCLK_NAME_RESERVED3_5 "RESERVED3_5" +#define GCLK_DEV_RESERVED3_5 "CLKGATE_RESERVED3_5" +#define GCLK_REG_RESERVED3_5 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_5 (1<<17) + +#define GCLK_IDX_RESERVED3_6 114 +#define GCLK_NAME_RESERVED3_6 "RESERVED3_6" +#define GCLK_DEV_RESERVED3_6 "CLKGATE_RESERVED3_6" +#define GCLK_REG_RESERVED3_6 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_6 (1<<18) + +#define GCLK_IDX_RESERVED3_7 115 +#define GCLK_NAME_RESERVED3_7 "RESERVED3_7" +#define GCLK_DEV_RESERVED3_7 "CLKGATE_RESERVED3_7" +#define GCLK_REG_RESERVED3_7 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_7 (1<<19) + +#define GCLK_IDX_ENC480P 116 +#define GCLK_NAME_ENC480P "ENC480P" +#define GCLK_DEV_ENC480P "CLKGATE_ENC480P" +#define GCLK_REG_ENC480P (HHI_GCLK_OTHER) +#define GCLK_MASK_ENC480P (1<<20) + +#define GCLK_IDX_RANDOM_NUM_GEN1 117 +#define GCLK_NAME_RANDOM_NUM_GEN1 "RANDOM_NUM_GEN1" +#define GCLK_DEV_RANDOM_NUM_GEN1 "CLKGATE_RANDOM_NUM_GEN1" +#define GCLK_REG_RANDOM_NUM_GEN1 (HHI_GCLK_OTHER) +#define GCLK_MASK_RANDOM_NUM_GEN1 (1<<21) + +#define GCLK_IDX_VCLK2_ENCT 118 +#define GCLK_NAME_VCLK2_ENCT "GCLK_VENCL_INT" +#define GCLK_DEV_VCLK2_ENCT "CLKGATE_GCLK_VENCL_INT" +#define GCLK_REG_VCLK2_ENCT (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_ENCT (1<<22) + +#define GCLK_IDX_VCLK2_ENCL 119 +#define GCLK_NAME_VCLK2_ENCL "VLKC2_ENCL" +#define GCLK_DEV_VCLK2_ENCL "CLKGATE_VCLK2_ENCL" +#define GCLK_REG_VCLK2_ENCL (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_ENCL (1<<23) + +#define GCLK_IDX_MMC_CLK 120 +#define GCLK_NAME_MMC_CLK "MMC_CLK" +#define GCLK_DEV_MMC_CLK "CLKGATE_MMC_CLK" +#define GCLK_REG_MMC_CLK (HHI_GCLK_OTHER) +#define GCLK_MASK_MMC_CLK (1<<24) + +#define GCLK_IDX_VCLK2_VENCL 121 +#define GCLK_NAME_VCLK2_VENCL "VCLK2_VENCL" +#define GCLK_DEV_VCLK2_VENCL "CLKGATE_VCLK2_VENCL" +#define GCLK_REG_VCLK2_VENCL (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCL (1<<25) + +#define GCLK_IDX_VCLK2_OTHER1 122 +#define GCLK_NAME_VCLK2_OTHER1 "VCLK2_OTHER1" +#define GCLK_DEV_VCLK2_OTHER1 "CLKGATE_VCLK2_OTHER1" +#define GCLK_REG_VCLK2_OTHER1 (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_OTHER1 (1<<26) + +#define GCLK_IDX_RESERVED3_9 123 +#define GCLK_NAME_RESERVED3_9 "RESERVED3_9" +#define GCLK_DEV_RESERVED3_9 "CLKGATE_RESERVED3_9" +#define GCLK_REG_RESERVED3_9 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_9 (1<<27) + +#define GCLK_IDX_RESERVED3_A 124 +#define GCLK_NAME_RESERVED3_A "RESERVED3_A" +#define GCLK_DEV_RESERVED3_A "CLKGATE_RESERVED3_A" +#define GCLK_REG_RESERVED3_A (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_A (1<<28) + +#define GCLK_IDX_RESERVED3_B 125 +#define GCLK_NAME_RESERVED3_B "RESERVED3_B" +#define GCLK_DEV_RESERVED3_B "CLKGATE_RESERVED3_B" +#define GCLK_REG_RESERVED3_B (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_B (1<<29) + +#define GCLK_IDX_RESERVED3_C 126 +#define GCLK_NAME_RESERVED3_C "RESERVED3_C" +#define GCLK_DEV_RESERVED3_C "CLKGATE_RESERVED3_C" +#define GCLK_REG_RESERVED3_C (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_C (1<<30) + +#define GCLK_IDX_EDP_CLK 127 +#define GCLK_NAME_EDP_CLK "EDP_CLK" +#define GCLK_DEV_EDP_CLK "CLKGATE_EDP_CLK" +#define GCLK_REG_EDP_CLK (HHI_GCLK_OTHER) +#define GCLK_MASK_EDP_CLK (1<<31) + +/**************************************************************/ + +#define GCLK_IDX_MEDIA_CPU 128 +#define GCLK_NAME_MEDIA_CPU "MEDIA_CPU" +#define GCLK_DEV_MEDIA_CPU "CLKGATE_MEDIA_CPU" +#define GCLK_REG_MEDIA_CPU (HHI_GCLK_AO) +#define GCLK_MASK_MEDIA_CPU (1<<0) + +#define GCLK_IDX_AHB_SRAM 129 +#define GCLK_NAME_AHB_SRAM "AHB_SRAM" +#define GCLK_DEV_AHB_SRAM "CLKGATE_AHB_SRAM" +#define GCLK_REG_AHB_SRAM (HHI_GCLK_AO) +#define GCLK_MASK_AHB_SRAM (1<<1) + +#define GCLK_IDX_AHB_BUS 130 +#define GCLK_NAME_AHB_BUS "AHB_BUS" +#define GCLK_DEV_AHB_BUS "CLKGATE_AHB_BUS" +#define GCLK_REG_AHB_BUS (HHI_GCLK_AO) +#define GCLK_MASK_AHB_BUS (1<<2) + +#define GCLK_IDX_AO_REGS 131 +#define GCLK_NAME_AO_REGS "AO_REGS" +#define GCLK_DEV_AO_REGS "CLKGATE_AO_REGS" +#define GCLK_REG_AO_REGS (HHI_GCLK_AO) +#define GCLK_MASK_AO_REGS (1<<3) + +#define GCLK_NAME_I2C_AO "I2C_AO" +#define GCLK_REG_I2C_AO (HHI_GCLK_AO) +#define GCLK_MASK_I2C_AO (1<<4) + + +#define GCLK_IDX_CTS_ENCI 132 +#define GCLK_NAME_CTS_ENCI "CTS_ENCI" +#define GCLK_DEV_CTS_ENCI "CLKGATE_CTS_ENCI" +#define GCLK_REG_CTS_ENCI (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_ENCI (1<<0) + +#define GCLK_IDX_CTS_ENCT 133 +#define GCLK_NAME_CTS_ENCT "CTS_ENCT" +#define GCLK_DEV_CTS_ENCT "CLKGATE_CTS_ENCT" +#define GCLK_REG_CTS_ENCT (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_ENCT (1<<1) + +#define GCLK_IDX_CTS_ENCP 134 +#define GCLK_NAME_CTS_ENCP "CTS_ENCP" +#define GCLK_DEV_CTS_ENCP "CLKGATE_CTS_ENCP" +#define GCLK_REG_CTS_ENCP (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_ENCP (1<<2) + +#define GCLK_IDX_CTS_ENCL 135 +#define GCLK_NAME_CTS_ENCL "CTS_ENCL" +#define GCLK_DEV_CTS_ENCL "CLKGATE_CTS_ENCL" +#define GCLK_REG_CTS_ENCL (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_ENCL (1<<3) + +#define GCLK_IDX_CTS_VDAC 136 +#define GCLK_NAME_CTS_VDAC "CTS_VDAC" +#define GCLK_DEV_CTS_VDAC "CLKGATE_CTS_VDAC" +#define GCLK_REG_CTS_VDAC (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_VDAC (1<<4) + +#define GCLK_IDX_CTS_HDMI_TX_PIXEL 137 +#define GCLK_NAME_CTS_HDMI_TX_PIXEL "CTS_HDMI_TX_PIXEL" +#define GCLK_DEV_CTS_HDMI_TX_PIXEL "CLKGATE_CTS_HDMI_TX_PIXEL" +#define GCLK_REG_CTS_HDMI_TX_PIXEL (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_HDMI_TX_PIXEL (1<<5) + +#define GCLK_IDX_AUD 138 +#define GCLK_NAME_AUD "AUD" +#define GCLK_DEV_AUD "CLKGATE_AUD" +#define GCLK_REG_AUD (HHI_AUD_CLK_CNTL) +#define GCLK_MASK_AUD (1<<23) + + +#define GCLK_IDX_AUD2 138 +#define GCLK_NAME_AUD2 "AUD2" +#define GCLK_DEV_AUD2 "CLKGATE_AUD2" +#define GCLK_REG_AUD2 (HHI_AUD_CLK_CNTL) +#define GCLK_MASK_AUD2 (1<<8) + + +#define GCLK_NAME_AUD_CLK_2 "AUD_CLK_2" +#define GCLK_REG_AUD_CLK_2 (HHI_AUD_CLK_CNTL2) +#define GCLK_MASK_AUD_CLK_2 (1<<8) + +#define GCLK_IDX_AUD_CLK_3 138 +#define GCLK_NAME_AUD_CLK_3 "AUD_CLK" +#define GCLK_DEV_AUD_CLK_3 "CLKGATE_AUD_CLK" +#define GCLK_REG_AUD_CLK_3 (HHI_AUD_CLK_CNTL3) +#define GCLK_MASK_AUD_CLK_3 (1<<16) + +#define GCLK_IDX_LCD_AN_PHY2 139 +#define GCLK_NAME_LCD_AN_PHY2 "LCD_AN_PHY2" +#define GCLK_DEV_LCD_AN_PHY2 "CLKGATE_LCD_AN_PHY2" +#define GCLK_REG_LCD_AN_PHY2 (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_LCD_AN_PHY2 (1<<7) + +#define GCLK_IDX_LCD_AN_PHY3 140 +#define GCLK_NAME_LCD_AN_PHY3 "LCD_AN_PHY3" +#define GCLK_DEV_LCD_AN_PHY3 "CLKGATE_LCD_AN_PHY3" +#define GCLK_REG_LCD_AN_PHY3 (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_LCD_AN_PHY3 (1<<6) + +#define GCLK_NAME_ATV_DEMO_VDAC "ATV_DEMO_VDAC" +#define GCLK_REG_ATV_DEMO_VDAC (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_ATV_DEMO_VDAC (1<<8) + +#define GCLK_IDX_HDMI_PLL_CNTL 142 +#define GCLK_NAME_HDMI_PLL_CNTL "HDMI_PLL_CNTL" +#define GCLK_DEV_HDMI_PLL_CNTL "GATE_HDMI_PLL_CNTL" +#define GCLK_REG_HDMI_PLL_CNTL (HHI_HDMI_PLL_CNTL) +#define GCLK_MASK_HDMI_PLL_CNTL (1<<30) + +#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK" +#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL) +#define GCLK_MASK_HDMITX_CLK (1<<8) + + +#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK" +#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL) +#define GCLK_MASK_HDMITX_CLK (1<<8) + +#define GCLK_IDX_VDEC_CLK_1 144 +#define GCLK_NAME_VDEC_CLK_1 "VDEC_CLK_1" +#define GCLK_DEV_VDEC_CLK_1 "CLKGATE_VDEC_CLK_1" +#define GCLK_REG_VDEC_CLK_1 (HHI_VDEC_CLK_CNTL) +#define GCLK_MASK_VDEC_CLK_1 (1<<8) + +#define GCLK_NAME_VDEC_CLK_2 "VDEC_CLK_2" +#define GCLK_REG_VDEC_CLK_2 (HHI_VDEC3_CLK_CNTL) +#define GCLK_MASK_VDEC_CLK_2 (1<<8) + +#define GCLK_NAME_VDEC2_CLK_1 "VDEC2_CLK_1" +#define GCLK_REG_VDEC2_CLK_1 (HHI_VDEC2_CLK_CNTL) +#define GCLK_MASK_VDEC2_CLK_1 (1<<8) + +#define GCLK_NAME_VDEC2_CLK_2 "VDEC2_CLK_2" +#define GCLK_REG_VDEC2_CLK_2 (HHI_VDEC4_CLK_CNTL) +#define GCLK_MASK_VDEC2_CLK_2 (1<<8) + +#define GCLK_IDX_HCODEC_CLK_1 145 +#define GCLK_NAME_HCODEC_CLK_1 "HCODEC_CLK" +#define GCLK_DEV_HCODEC_CLK_1 "CLKGATE_HCODEC_CLK" +#define GCLK_REG_HCODEC_CLK_1 (HHI_VDEC_CLK_CNTL) +#define GCLK_MASK_HCODEC_CLK_1 (1<<24) + +#define GCLK_NAME_HCODEC_CLK_2 "HCODEC_CLK_2" +#define GCLK_REG_HCODEC_CLK_2 (HHI_VDEC3_CLK_CNTL) +#define GCLK_MASK_HCODEC_CLK_2 (1<<24) + +#define GCLK_NAME_HEVC_CLK_1 "HCODEC_CLK_1" +#define GCLK_REG_HEVC_CLK_1 (HHI_VDEC2_CLK_CNTL) +#define GCLK_MASK_HEVC_CLK_1 (1<<24) + +#define GCLK_NAME_HEVC_CLK_2 "HEVC_CLK_2" +#define GCLK_REG_HEVC_CLK_2 (HHI_VDEC4_CLK_CNTL) +#define GCLK_MASK_HEVC_CLK_2 (1<<24) + +#define GCLK_IDX_GEN_CLK 146 +#define GCLK_NAME_GEN_CLK "GEN_CLK" +#define GCLK_DEV_GEN_CLK "CLKGATE_HCODEC_CLK" +#define GCLK_REG_GEN_CLK (HHI_GEN_CLK_CNTL) +#define GCLK_MASK_GEN_CLK (1<<11) + +#define GCLK_NAME_VPU_CLK_1 "VPU_CLK_1" +#define GCLK_REG_VPU_CLK_1 (HHI_VPU_CLK_CNTL) +#define GCLK_MASK_VPU_CLK_1 (1<<8) + +#define GCLK_NAME_VPU_CLK_2 "VPU_CLK_2" +#define GCLK_REG_VPU_CLK_2 (HHI_VPU_CLK_CNTL) +#define GCLK_MASK_VPU_CLK_2 (1<<24) + + +#define GCLK_NAME_VPU_CLKB "VPU_CLKB" +#define GCLK_REG_VPU_CLKB (HHI_VPU_CLKB_CNTL) +#define GCLK_MASK_VPU_CLKB (1<<8) + +#define GCLK_NAME_VAPB_CLK_1 "VAPB_CLK_1" +#define GCLK_REG_VAPB_CLK_1 (HHI_VAPBCLK_CNTL) +#define GCLK_MASK_VAPB_CLK_1 (1<<8) + +#define GCLK_NAME_VAPB_CLK_2 "VAPB_CLK_2" +#define GCLK_REG_VAPB_CLK_2 (HHI_VAPBCLK_CNTL) +#define GCLK_MASK_VAPB_CLK_2 (1<<24) + +#define GCLK_NAME_MALI_CLK_1 "MALI_CLK_1" +#define GCLK_REG_MALI_CLK_1 (HHI_MALI_CLK_CNTL) +#define GCLK_MASK_MALI_CLK_1 (1<<8) + +#define GCLK_NAME_MALI_CLK_2 "MALI_CLK_2" +#define GCLK_REG_MALI_CLK_2 (HHI_MALI_CLK_CNTL) +#define GCLK_MASK_MALI_CLK_2 (1<<24) + +#define GCLK_NAME_PWM_A_CLK "PWM_A_CLK" +#define GCLK_REG_PWM_A_CLK (CBUS_REG_ADDR(0x2156)) +#define GCLK_MASK_PWM_A_CLK (1<<15) + +#define GCLK_NAME_PWM_B_CLK "PWM_B_CLK" +#define GCLK_REG_PWM_B_CLK (CBUS_REG_ADDR(0x2156)) +#define GCLK_MASK_PWM_B_CLK (1<<23) + +#define GCLK_NAME_PWM_C_CLK "PWM_C_CLK" +#define GCLK_REG_PWM_C_CLK (CBUS_REG_ADDR(0x2196)) +#define GCLK_MASK_PWM_C_CLK (1<<15) + +#define GCLK_NAME_PWM_D_CLK "PWM_D_CLK" +#define GCLK_REG_PWM_D_CLK (CBUS_REG_ADDR(0x2196)) +#define GCLK_MASK_PWM_D_CLK (1<<23) + +#define GCLK_NAME_PWM_E_CLK "PWM_E_CLK" +#define GCLK_REG_PWM_E_CLK (CBUS_REG_ADDR(0x21b2)) +#define GCLK_MASK_PWM_E_CLK (1<<15) + +#define GCLK_NAME_PWM_F_CLK "PWM_D_CLK" +#define GCLK_REG_PWM_F_CLK (CBUS_REG_ADDR(0x21b2)) +#define GCLK_MASK_PWM_F_CLK (1<<23) + +#define GCLK_NAME_VDIN_MEAS_CLK "VDIN_MEAS_CLK" +#define GCLK_REG_VDIN_MEAS_CLK (HHI_VDIN_MEAS_CLK_CNTL) +#define GCLK_MASK_VDIN_MEAS_CLK (1<<8) + +#define GCLK_NAME_MSR_CLK "MSR_CLK" +#define GCLK_REG_MSR_CLK (CBUS_REG_ADDR(0x21d7)) +#define GCLK_MASK_MSR_CLK (1<<19) + +#define GCLK_NAME_MSR_HS_CLK "MSR_HS_CLK" +#define GCLK_REG_MSR_HS_CLK (CBUS_REG_ADDR(0x21d9)) +#define GCLK_MASK_MSR_HS_CLK (1<<28) + +#define GCLK_NAME_32K_CLK "32K_CLK" +#define GCLK_REG_32K_CLK (HHI_32K_CLK_CNTL) +#define GCLK_MASK_32K_CLK (1<<15) + + + +#define GCLK_IDX_MAX 200 + +extern short GCLK_ref[GCLK_IDX_MAX]; + +#define REGISTER_CLK(_MOD) \ +static struct clk CLK_##_MOD = { \ + .name = GCLK_NAME_##_MOD, \ + .clock_index = GCLK_IDX_##_MOD, \ + .clock_gate_reg_adr = GCLK_REG_##_MOD, \ + .clock_gate_reg_mask = GCLK_MASK_##_MOD, \ +} + +#define CLK_LOOKUP_ITEM(_MOD) \ + { \ + .dev_id = GCLK_DEV_##_MOD, \ + .con_id = GCLK_NAME_##_MOD, \ + .clk = &CLK_##_MOD, \ + } + + + +/**********************/ +/* internal audio dac control */ +#define ADAC_RESET (0x5000+0x00*4) +#define ADAC_LATCH (0x5000+0x01*4) +#define ADAC_POWER_CTRL_REG1 (0x5000+0x10*4) +#define ADAC_POWER_CTRL_REG2 (0x5000+0x11*4) + +int audio_internal_dac_disable(void); + +/* video dac control */ +int video_dac_enable(unsigned char enable_mask); + +int video_dac_disable(void); + + +#endif
diff --git a/arch/arm/mach-meson/c2/sdio.c b/arch/arm/mach-meson/c2/sdio.c new file mode 100644 index 0000000..14ec635 --- /dev/null +++ b/arch/arm/mach-meson/c2/sdio.c
@@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <asm/arch/io.h> +#include <asm/arch/cpu_sdio.h> +#include <asm/arch/secure_apb.h> +#include <amlogic/cpu_id.h> +#include <common.h> + +void cpu_sd_emmc_pwr_prepare(unsigned port) +{ +} +int cpu_sd_emmc_init(unsigned port) +{ + return 0; +} + +/* return: + 0: insert + 1: not insert + */ +__weak int sd_emmc_detect(unsigned port) +{ + int ret = 0; + + return ret; +} + +
diff --git a/arch/arm/mach-meson/c2/timer.c b/arch/arm/mach-meson/c2/timer.c new file mode 100644 index 0000000..8c16210 --- /dev/null +++ b/arch/arm/mach-meson/c2/timer.c
@@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timer.h> +#include <asm/types.h> + +uint32_t get_time(void) +{ + return readl(SYSCTRL_TIMERE); +} + +void _udelay(unsigned int us) +{ +#ifndef CONFIG_PXP_EMULATOR + unsigned int t0 = get_time(); + + while (get_time() - t0 <= us) + ; +#endif +}
diff --git a/arch/arm/mach-meson/c2/tsensor.c b/arch/arm/mach-meson/c2/tsensor.c new file mode 100644 index 0000000..18c4e79 --- /dev/null +++ b/arch/arm/mach-meson/c2/tsensor.c
@@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <command.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/mailbox.h> +#include <asm/arch/tsensor.h> +#include <asm/arch/bl31_apis.h> + +int tsensor_tz_calibration(unsigned int type, unsigned int data) +{ + int ret; + + register long x0 asm("x0") = TSENSOR_CALI_SET; + register long x1 asm("x1") = type; + register long x2 asm("x2") = data; + register long x3 asm("x3") = 0; + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); + } while (0); + ret = x0; + + if (!ret) + return -1; + else + return 0; +} + +int r1p1_codetotemp(unsigned long value, unsigned int u_efuse) +{ + int64_t temp; + + temp = (value * ts_m) * (1 << 16) / (100 * (1 << 16) + ts_n * value); + if (u_efuse & 0x8000) { + temp = ((temp - (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10; + } else { + temp = ((temp + (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10; + } + return temp; +} + +int r1p1_temp_read(int type) +{ + unsigned int ret, u_efuse; + unsigned int value_ts, value_all_ts; + int tmp = -1; + int i, cnt; + char buf[2]; + + switch (type) { + case 1: + /*enable thermal1*/ + writel(T_CONTROL_DATA, TS_CFG_REG1); + writel(T_TSCLK_DATA, CLKTREE_TS_CLK_CTRL); + ret = readl(SYSCTRL_SEC_STATUS_REG13);/*thermal1 cali data in reg CFG10*/ + mdelay(5); + buf[0] = (ret) & 0xff; + buf[1] = (ret >> 8) & 0xff; + u_efuse = buf[1]; + u_efuse = (u_efuse << 8) | buf[0]; + value_ts = 0; + value_all_ts = 0; + cnt = 0; + for (i = 0; i <= 10; i ++) { + udelay(50); + value_ts = readl(TS_STAT0) & 0xffff; + } + for (i = 0; i <= T_AVG_NUM; i ++) { + udelay(T_DLY_TIME); + value_ts = readl(TS_STAT0) & 0xffff; + if ((value_ts >= T_VALUE_MIN) && + (value_ts <= T_VALUE_MAX)) { + value_all_ts += value_ts; + cnt ++; + } + } + value_ts = value_all_ts / cnt; + printf("tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse); + if (value_ts == 0) { + printf("tsensor read temp is zero\n"); + return -1; + } + tmp = r1p1_codetotemp(value_ts, u_efuse); + printf("temp1: %d\n", tmp); + break; + default: + printf("r1p1 tsensor trim type not support\n"); + return -1; + } + return tmp; +} + +unsigned int r1p1_temptocode(unsigned long value, int tempbase) +{ + unsigned long tmp1, tmp2, u_efuse, signbit; + + printf("a b m n: %d, %d, %d, %d\n", ts_a, ts_b, ts_m, ts_n); + tmp1 = ((tempbase * 10 + ts_b) * (1 << 16)) / ts_a; /*ideal u*/ + printf("%s : tmp1: 0x%lx\n", __func__, tmp1); + tmp2 = (ts_m * value * (1 << 16)) / ((1 << 16) * 100 + ts_n * value); + printf("%s : tmp2: 0x%lx\n", __func__, tmp2); + signbit = ((tmp1 > tmp2) ? 0 : 1); + u_efuse = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + if (u_efuse > 0x3ff) + return 0; + u_efuse = (1 << 11) | (signbit << 10) | u_efuse; + return u_efuse; +} + +int r1p1_temp_trim(int tempbase, int tempver, int type) +{ + unsigned int u_efuse, index_ts, index_ver; + unsigned int value_ts, value_all_ts; + int i, cnt; + + printf("r1p1 temp trim type: 0x%x\n", type); + switch (type) { + case 0: + index_ver = 5; + tempver = tempver & 0xf; + if (tsensor_tz_calibration(index_ver, tempver) < 0) + printf("version tsensor thermal_calibration send error\n"); + break; + case 1: + value_ts = 0; + value_all_ts = 0; + index_ts = 6; + cnt = 0; + /*enable thermal1*/ + writel(T_CONTROL_DATA, TS_CFG_REG1); + writel(T_TSCLK_DATA, CLKTREE_TS_CLK_CTRL); + for (i = 0; i <= 10; i ++) { + udelay(50); + value_ts = readl(TS_STAT0) & 0xffff; + } + for (i = 0; i <= T_AVG_NUM; i ++) { + udelay(T_DLY_TIME); + value_ts = readl(TS_STAT0) & 0xffff; + printf("tsensor read: 0x%x\n", value_ts); + if ((value_ts >= T_VALUE_MIN) && + (value_ts <= T_VALUE_MAX)) { + value_all_ts += value_ts; + cnt ++; + } + } + value_ts = value_all_ts / cnt; + printf("tsensor avg: 0x%x\n", value_ts); + if (value_ts == 0) { + printf("tsensor read temp is zero\n"); + return -1; + } + u_efuse = r1p1_temptocode(value_ts, tempbase); + if (!u_efuse) { + printf("ts efuse is greater than 0x3ff, not trim!\n"); + return -1; + } + printf("ts efuse:%d\n", u_efuse); + printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts); + if (tsensor_tz_calibration(index_ts, u_efuse) < 0) { + printf("tsensor thermal_calibration send error\n"); + return -1; + } + break; + default: + printf("r1p1 tsensor trim type not support\n"); + return -1; + break; + } + return 0; +} + +int temp_read_entry(void) +{ + unsigned int ret, ver; + + ret = readl(SYSCTRL_SEC_STATUS_REG13); + ver = (ret >> 24) & 0xff; + if (0 == (ver & T_VER_MASK)) { + printf("tsensor no trimmed: calidata:0x%x\n", + readl(SYSCTRL_SEC_STATUS_REG13)); + return -1; + } + ret = (ver & 0xf) >> 2; + switch (ret) { + case 0x2: + printf("temp type no support\n"); + break; + case 0x0: + printf("temp type no support\n"); + break; + case 0x1: + r1p1_temp_read(1); + printf("read the thermal\n"); + break; + case 0x3: + printf("temp type no support\n"); + return -1; + break; + default: + printf("thermal version not support!!!Please check!\n"); + return -1; + } + return 0; +} + +int temp_trim_entry(int tempbase, int tempver) +{ + unsigned int ret, ver; + + ret = readl(SYSCTRL_SEC_STATUS_REG13); + ver = (ret >> 24) & 0xff; + if (ver & T_VER_MASK) { + printf("tsensor trimmed: cali data: 0x%x\n", + readl(SYSCTRL_SEC_STATUS_REG13)); + return -1; + } + + printf("tsensor input trim tempver, tempver:0x%x\n", tempver); + switch (tempver) { + case 0x84: + ret = r1p1_temp_trim(tempbase, tempver, 1); + if (!ret) { + r1p1_temp_trim(tempbase, tempver, 0); + printf("triming the thermal by bbt-sw\n"); + } + break; + case 0x85: + ret = r1p1_temp_trim(tempbase, tempver, 1); + if (!ret) { + r1p1_temp_trim(tempbase, tempver, 0); + printf("triming the thermal by bbt-ops\n"); + } + break; + case 0x87: + ret = r1p1_temp_trim(tempbase, tempver, 1); + if (!ret) { + r1p1_temp_trim(tempbase, tempver, 0); + printf("triming the thermal by slt\n"); + } + break; + default: + printf("thermal version not support!!!Please check!\n"); + return -1; + } + return 0; +} + +int temp_cooling_entry(void) +{ +#ifdef CONFIG_AML_TSENSOR_COOL + int temp; + + while (1) { + temp = r1p1_temp_read(1); + if (temp <= CONFIG_HIGH_TEMP_COOL) { + printf("device cool done\n"); + break; + } + mdelay(2000); + printf("warning: temp %d over %d, cooling\n", temp, + CONFIG_HIGH_TEMP_COOL); + } +#endif + return 0; +}
diff --git a/arch/arm/mach-meson/c2/usb.c b/arch/arm/mach-meson/c2/usb.c new file mode 100644 index 0000000..ac20578 --- /dev/null +++ b/arch/arm/mach-meson/c2/usb.c
@@ -0,0 +1,634 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <bitfield.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <power/regulator.h> +#include <clk.h> +#include <asm/arch/usb.h> +#include <amlogic/cpu_id.h> + +#include <linux/compat.h> +#include <linux/ioport.h> +#include <asm-generic/gpio.h> + +#define U2_CTRL_SLEEP_SHIFT 24 +#define U2_HHI_MEM_PD_MASK 0x3 +#define U2_HHI_MEM_PD_SHIFT 0x0 +#define U2_CTRL_ISO_SHIFT 24 +#define PHY20_RESET_LEVEL_BIT 4 +#define USB_RESET_BIT 3 + +#define USB2_PHY_PLL_OFFSET_40 (0x0816a010) +#define USB2_PHY_PLL_OFFSET_44 (0x000a72f2) + +#define USB2_PHY_PLL_OFFSET_34 (0x70000) + +#define USB2_PHY_PLL_OFFSET_50 (0xfe18) +#define USB2_PHY_PLL_OFFSET_54 (0x2a) + +#define TUNING_DISCONNECT_THRESHOLD 0x34 + +#define P_AO_RTI_GEN_PWR_SLEEP0 0xfe013008 +#define P_AO_RTI_GEN_PWR_ISO0 0xfe013004 +#define P_HHI_MEM_PD_REG0 0xfe013050 + +struct phy usb_phys[2]; + +int get_usbphy_baseinfo(struct phy *usb_phys) +{ + struct udevice *bus; + struct uclass *uc; + int ret, i; + unsigned int count; + + if (usb_phys[0].dev && usb_phys[1].dev) + return 0; + + ret = uclass_get(UCLASS_USB, &uc); + if (ret) + return ret; + uclass_foreach_dev(bus, uc) { + debug("bus->name=%s, bus->driver->name =%s\n", + bus->name, bus->driver->name); + count = dev_count_phandle_with_args(bus, "phys", "#phy-cells"); + debug("usb phy count=%u\n", count); + if (count <= 0) + return count; + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(bus, i, &usb_phys[i]); + if (ret && ret != -ENOENT) { + pr_err("Failed to get USB PHY%d for %s\n", + i, bus->name); + return ret; + } + ret = generic_phy_getinfo(&usb_phys[i]); + if (ret) + return ret; + } + } + return 0; +} + +static void usb_set_power_domain (void) +{ + writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << U2_CTRL_SLEEP_SHIFT))), + P_AO_RTI_GEN_PWR_SLEEP0); + writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << U2_CTRL_ISO_SHIFT))), + P_AO_RTI_GEN_PWR_ISO0); + writel((readl(P_HHI_MEM_PD_REG0) + & (~(U2_HHI_MEM_PD_MASK << U2_HHI_MEM_PD_SHIFT))), P_HHI_MEM_PD_REG0); + + return; +} + +static void usb_set_calibration_trim(uint32_t phy2_pll_base, uint8_t mode) +{ + uint32_t cali, value,i, tmp; + uint8_t cali_en; + + if (mode == DEVICE_MODE) { + value = readl((unsigned long)(phy2_pll_base + 0x10)); + value |= 0xfff; + writel(value, (unsigned long)(phy2_pll_base + 0x10)); + return; + } + + cali = readl((unsigned long)SYSCTRL_SEC_STATUS_REG12); + cali_en = (cali >> 30) & 0x1; + tmp = cali >> 26; + + if (cali_en) { + tmp =tmp & 0xf; + cali = tmp; + if (cali > 12) + cali = 12; + + value = readl((unsigned long)(phy2_pll_base + 0x10)); + value &= (~0xfff); + for (i = 0; i < cali; i++) + value |= (1 << i); + + writel(value, (unsigned long)(phy2_pll_base + 0x10)); + } + +} + +static void usb_set_clock_freq(unsigned int clock_addr) +{ + unsigned int val = (1 << 8) | (2 << 9) | (9 << 0); + writel(val, (unsigned long)clock_addr); + return; +} + +void usb_reset(unsigned int reset_addr, int bit){ + *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit); +} + +static void usb_enable_phy_pll (void) +{ + *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL |= (1 << PHY20_RESET_LEVEL_BIT); +} + +static void usb_disable_phy_pll (void) +{ + *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL &= ~(1 << PHY20_RESET_LEVEL_BIT); +} + +void set_usb_pll(uint32_t phy2_pll_base) +{ + uint32_t tmp, retry = 5; + +__retry: + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))= + (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) = + USB2_PHY_PLL_OFFSET_44; + udelay(5); + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))= + (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE); + udelay(5); + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))= + (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_ENABLE); + udelay(10); + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44))= + (USB2_PHY_PLL_OFFSET_44 | USBPLL_LK_OD_EN); + + udelay(200); + + tmp = *(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40); + + if (tmp >> USBPLL_LOCKFLAG_BIT) { + goto __setphyparameter; + } else { + retry --; + if (!retry) + goto __setphyparameter; + goto __retry; + } + +__setphyparameter: + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54)) + = USB2_PHY_PLL_OFFSET_54; + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) = + TUNING_DISCONNECT_THRESHOLD; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34)) + = USB2_PHY_PLL_OFFSET_34; + + debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD); +} + +int usb_save_phy_dev (unsigned int number, struct phy *phy) +{ + usb_phys[number].dev = phy->dev; + usb_phys[number].id = phy->id; + return 0; +} + +int usb2_phy_init (struct phy *phy) { + struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev); + struct u2p_aml_regs *u2p_aml_reg; + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + int i,cnt; + + usb_save_phy_dev(0, phy); + usb_enable_phy_pll(); + usb_set_power_domain(); + + priv->clktree_usb_bus_ctrl_addr = dev_read_addr_index(phy->dev, 2 + priv->u2_port_num); + if (priv->clktree_usb_bus_ctrl_addr == FDT_ADDR_T_NONE) { + pr_err("Coun't get clktree_usb_bus_ctrl addr index %d\n", 2 + priv->u2_port_num); + } else { + usb_set_clock_freq(priv->clktree_usb_bus_ctrl_addr); + } + + usb_reset(priv->reset_addr, USB_RESET_BIT); + + udelay(500); + priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT; + + for (i = 0; i < priv->u2_port_num; i++) { + u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE)); + dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0; + dev_u2p_r0.b.host_device= 1; + dev_u2p_r0.b.POR= 0; + u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32; + udelay(10); + /***USB PHY RESET : reset1 and reset1_level both need set ***/ + /***reset1: usb_reset ***/ + /***reset1_level: usb_enable_phy_pll ***/ + usb_reset(priv->reset_addr, priv->usbphy_reset_bit[i]); + + usb_set_calibration_trim(priv->usb_phy2_pll_base_addr[i], HOST_MODE); + + udelay(50); + + /* wait for phy ready */ + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + cnt = 0; + while (dev_u2p_r1.b.phy_rdy != 1) { + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + /*we wait phy ready max 1ms, common is 100us*/ + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + } + + for (i = 0; i < priv->u2_port_num; i++) { + debug("------set usb pll\n"); + set_usb_pll(priv->usb_phy2_pll_base_addr[i]); + writel(0xfe18, (unsigned long)(priv->usb_phy2_pll_base_addr[i] + 0x50)); + } + return 0; + +} + +int usb2_phy_tuning(uint32_t phy2_pll_base, int port) +{ + return 0; +} + +/**************************************************************/ +/* device mode config */ +/**************************************************************/ +unsigned int usb_get_dwc_a_base_addr(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->dwc2_a_addr; +} + +unsigned int usb_get_device_mode_phy_base(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->usb_phy2_pll_base_addr[0]; +} + +void usb_phy_tuning_reset(void) +{ + return; +} + +void usb_device_mode_init(void){ + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + + usb_r0_t dev_usb_r0; + usb_r4_t dev_usb_r4; + int cnt, ret; + u2p_aml_regs_t * u2p_aml_regs; + usb_aml_regs_t *usb_aml_regs; + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + unsigned int phy_base_addr, reset_addr; + + usb_enable_phy_pll(); + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + if (!usb2_priv || !usb3_priv) { + printf("get usb phy address from dts failed\n"); + return; + } + + u2p_aml_regs = (u2p_aml_regs_t * )((ulong)usb2_priv->base_addr); + usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr); + phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[0]; + reset_addr = usb2_priv->reset_addr; + + usb_set_power_domain(); + usb_set_clock_freq(CLKTREE_USB_BUSCLK_CTRL); + + printf("PHY2=0x%08x\n", usb2_priv->base_addr); + if ((*(volatile uint32_t *)((ulong)(phy_base_addr + 0x38))) != 0) { + usb_phy_tuning_reset(); + mdelay(150); + } + + //step 1: usb controller reset + usb_reset(reset_addr, USB_RESET_BIT); + + // step 3: enable usb INT internal USB + dev_usb_r0.d32 = usb_aml_regs->usb_r0; + dev_usb_r0.b.u2d_ss_scaledown_mode = 0; + dev_usb_r0.b.u2d_act = 1; + usb_aml_regs->usb_r0 = dev_usb_r0.d32; + + // step 4: disable usb phy sleep + dev_usb_r4.d32 = usb_aml_regs->usb_r4; + dev_usb_r4.b.p21_SLEEPM0 = 1; + usb_aml_regs->usb_r4 = dev_usb_r4.d32; + + // step 5: config phy21 device mode + dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; + dev_u2p_r0.b.host_device= 0; + dev_u2p_r0.b.POR= 0; + u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; + + udelay(10); + //step 6: phy21 reset + usb_reset(reset_addr, PHY20_RESET_LEVEL_BIT); + udelay(50); + usb_set_calibration_trim(phy_base_addr, DEVICE_MODE); + udelay(50); + + // step 6: wait for phy ready + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + cnt = 0; + while ((dev_u2p_r1.d32 & 0x00000001) != 1) { + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + + set_usb_pll(phy_base_addr); + writel(0xbe18, (unsigned long)(phy_base_addr + 0x50)); + //-------------------------------------------------- + + // ------------- usb phy21 initinal end ---------- + + //-------------------------------------------------- + +} + +/**************************************************************/ +/* BC Detect */ +/**************************************************************/ +#define USB_AML_BC_OFFSET 0xA0 + +static void usb_bc_set_device(uint32_t phy2_config_base){ + struct u2p_aml_regs * u2p_aml_regs = (struct u2p_aml_regs * )((ulong)phy2_config_base); + u2p_r0_t u2p_r0; + + u2p_r0.d32 = u2p_aml_regs->u2p_r0; + u2p_r0.b.host_device = 0; + + u2p_aml_regs->u2p_r0 = u2p_r0.d32; + return; +} + +static void usb_bc_en_det(uint32_t bc_reg_base, uint32_t usb3_config_base) +{ + bc_reg_list_t * bc_reg_s = (struct bc_reg_list *)bc_reg_base; + bc_ctrl_t ctrl; + struct usb_aml_regs * usb3_config_reg = (struct usb_aml_regs *)usb3_config_base; + usb_r0_t cfg0_reg; + + cfg0_reg.d32 = usb3_config_reg->usb_r0; + cfg0_reg.b.u2d_act = 1; + usb3_config_reg->usb_r0 = cfg0_reg.d32; + mdelay(20); + + ctrl.d32 = bc_reg_s->bc_ctrl; + ctrl.b.bc_en = 1; + bc_reg_s->bc_ctrl = ctrl.d32; + + mdelay(700); +} + +static void usb_bc_disable_det(uint32_t bc_reg_base) +{ + bc_reg_list_t * bc_reg_s = (struct bc_reg_list *)bc_reg_base; + bc_ctrl_t ctrl; + + ctrl.d32 = bc_reg_s->bc_ctrl; + ctrl.b.bc_en = 0; + bc_reg_s->bc_ctrl = ctrl.d32; +} + +static void usb_bc_clean_det(uint32_t bc_reg_base) +{ + bc_reg_list_t * bc_reg_s = (struct bc_reg_list *)bc_reg_base; + bc_ctrl_t ctrl; + + ctrl.d32 = bc_reg_s->bc_ctrl; + ctrl.b.bc_int_clean = 1; + bc_reg_s->bc_ctrl = ctrl.d32; +} + + +static int usb_bc_read_bc_status(uint32_t bc_reg_base) +{ + bc_reg_list_t *bc_reg_s = (bc_reg_list_t *)bc_reg_base; + bc_status_t b_status; + int ret; + unsigned int i; + + for (i = 0; i < 3; i++) { + pr_crit("check bc detection: %d times\n", i+1); + if ((readl(0xfe0044a4) & 0x1) == 0) { + pr_crit("bc detection ERROR\n"); + pr_crit("0xfe0044a0:0x%x\n", readl(0xfe0044a0)); + pr_crit("0xfe0044a4:0x%x\n", readl(0xfe0044a4)); + pr_crit("0xfe0044a8:0x%x\n", readl(0xfe0044a8)); + pr_crit("0xfe0044ac:0x%x\n", readl(0xfe0044ac)); + pr_crit("0xfe0044b0:0x%x\n", readl(0xfe0044b0)); + pr_crit("0xfe0044b4:0x%x\n", readl(0xfe0044b4)); + pr_crit("0xfe0044b8:0x%x\n", readl(0xfe0044b8)); + pr_crit("0xfe0044c0:0x%x\n", readl(0xfe0044c0)); + pr_crit("0xfe0044c4:0x%x\n", readl(0xfe0044c4)); + pr_crit("0xfe0044c8:0x%x\n", readl(0xfe0044c8)); + pr_crit("0xfe0044cc:0x%x\n", readl(0xfe0044cc)); + pr_crit("0xfe0044d0:0x%x\n", readl(0xfe0044d0)); + pr_crit("0xfe0044d4:0x%x\n", readl(0xfe0044d4)); + pr_crit("0xfe004420:0x%x\n", readl(0xfe004420)); + pr_crit("0xfe004480:0x%x\n", readl(0xfe004480)); + pr_crit("0xfe004050:0x%x\n", readl(0xfe004050)); + pr_crit("0xfe000800:0x%x\n", readl(0xfe000800)); + pr_crit("0xfe013080:0x%x\n", readl(0xfe013080)); + pr_crit("0xfe000004:0x%x\n", readl(0xfe000004)); + pr_crit("0xfe000044:0x%x\n", readl(0xfe000044)); + pr_crit("0xfe000084:0x%x\n", readl(0xfe000084)); + mdelay(700); + } else { + pr_crit("bc detection end\n"); + pr_crit("status reg: 0x%x\n", readl(0xfe0044a4)); + break; + } + } + + b_status.d32 = bc_reg_s->bc_status; + pr_crit("BC STATUS is : "); + switch (b_status.b.port_status) { + case 0: + env_set("charger_type","UNKNOWN"); + pr_crit("port status: default\n"); + break; + case 1: + env_set("charger_type","SDP"); + pr_crit("SDP:Standard downstream port\n"); + break; + case 2: + env_set("charger_type","DCP"); + pr_crit("DCP: Delicated charging port\n"); + break; + case 3: + env_set("charger_type","CDP"); + pr_crit("CDP: charging downstream port\n"); + break; + case 4: + pr_crit("ACA_A: ACA with ID resistance of RID_A\n"); + break; + case 5: + pr_crit("ACA_B: ACA with ID resistance of RID_B\n"); + break; + case 6: + pr_crit("ACA_C: ACA with ID resistance of RID_C\n"); + break; + case 7: + pr_crit("ACA_DOCK: Equivalent to a charging hub\n"); + break; + case 8: + pr_crit("port status: ACA GND error\n"); + break; + case 9: + pr_crit("port status: analog output error\n"); + break; + case 10: + pr_crit("VBUS remove\n"); + break; + case 11: + pr_crit("VBUS invalid\n"); + break; + default: + pr_crit("port status: reserved\n"); + break; + } + if (b_status.b.port_status >= 4) + env_set("charger_type","UNKNOWN"); + + ret = b_status.b.port_status; + usb_bc_clean_det(bc_reg_base); + return ret; +} + +void usb_bc_detect(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + int ret; + uint32_t phy2_cfg_base, phy3_cfg_base, bc_cfg_base; + + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + pr_err("get usb dts failed\n"); + return; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + phy2_cfg_base = usb2_priv->base_addr; + bc_cfg_base = phy2_cfg_base - PHY_REGISTER_SIZE + USB_AML_BC_OFFSET; + phy3_cfg_base = usb3_priv->base_addr; + + writel(0x5018, 0xfe000004); + mdelay(10); + + usb_bc_set_device(phy2_cfg_base); + usb_bc_en_det(bc_cfg_base, phy3_cfg_base); + usb_bc_read_bc_status(bc_cfg_base); + usb_bc_disable_det(bc_cfg_base); +} + +static void usb_disable_phy(uint32_t phy2_pll_base) +{ + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))= + ((USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET) & (~USB_PHY2_ENABLE)); + udelay(5); +} + +static void usb_print_usb_baseinfo + (struct phy_aml_usb2_priv *usb2_priv, struct phy_aml_usb3_priv *usb3_priv) +{ + if (usb3_priv) { + printf("priv->usb3 port num = %d, config addr=0x%08x\n", + usb3_priv->usb3_port_num, usb3_priv->base_addr); + } + if (usb2_priv) { + printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n", + usb2_priv->base_addr, usb2_priv->reset_addr); + + printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n", + usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0], + usb2_priv->usb_phy2_pll_base_addr[1]); + printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr); + } +} + +int usb_aml_detect_operation(int argc, char * const argv[]) +{ + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + int ret; + + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + + if (argc >= 2) { + if (strncmp(argv[1], "bc", 2) == 0) { + usb_bc_detect(); + return 0; + } + + if (strncmp(argv[1], "disable", 7) == 0) { + usb_disable_phy_pll(); + usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[0]); + printf("disable USB phy\n"); + return 0; + } + + if (strncmp(argv[1], "info", 4) == 0) { + usb_print_usb_baseinfo(usb2_priv, usb3_priv); + return 0; + } + } + return CMD_RET_USAGE; +}
diff --git a/arch/arm/mach-meson/g12a/Makefile b/arch/arm/mach-meson/g12a/Makefile index 79ebc0b..0bd1de9 100644 --- a/arch/arm/mach-meson/g12a/Makefile +++ b/arch/arm/mach-meson/g12a/Makefile
@@ -9,6 +9,6 @@ obj-$(CONFIG_CMD_PLLTEST) += pll.o obj-$(CONFIG_CMD_AML_MTEST) += core.o obj-$(CONFIG_AML_HDMITX) += hdmitx.o -#obj-y += usb.o +obj-y += usb.o obj-$(CONFIG_AML_TSENSOR) += tsensor.o obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/g12a/bl31_apis.c b/arch/arm/mach-meson/g12a/bl31_apis.c index e0c2d7d..d01bfe8 100644 --- a/arch/arm/mach-meson/g12a/bl31_apis.c +++ b/arch/arm/mach-meson/g12a/bl31_apis.c
@@ -27,6 +27,36 @@ return function_id; } +int32_t set_boot_params(const keymaster_boot_params *boot_params) +{ + const unsigned cmd = SET_BOOT_PARAMS; + + if (!boot_params) + return -1; + + if (!sharemem_input_base) + sharemem_input_base = + get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); + + memcpy((void *)sharemem_input_base, + (const void *)boot_params, sizeof(keymaster_boot_params)); + + asm __volatile__("" : : : "memory"); + register uint64_t x0 asm("x0") = cmd; + register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params); + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1)); + } while (0); + + return (!x0)? -1: 0; +} + #ifdef CONFIG_EFUSE int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg) { @@ -393,3 +423,37 @@ return -1; } + +int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen) +{ + const unsigned cmd = GET_AVBKEY_FROM_FIP; + uint32_t retlen = 0; + uint32_t ret = 0; + + if (!buf) + return -1; + + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + asm __volatile__("" : : : "memory"); + register uint64_t x0 asm("x0") = cmd; + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + "smc #0\n" + : "=r"(x0) + : "r"(x0)); + } while (0); + + if (!x0) + ret = -1; + retlen = x0; + + if (ret != -1 && buflen >= retlen) + memcpy(buf, (const void *)sharemem_output_base, retlen); + + return ret; +}
diff --git a/arch/arm/mach-meson/g12a/firmware/acs/acs.ld.S b/arch/arm/mach-meson/g12a/firmware/acs/acs.ld.S index 09f7b7d..4a952c7 100644 --- a/arch/arm/mach-meson/g12a/firmware/acs/acs.ld.S +++ b/arch/arm/mach-meson/g12a/firmware/acs/acs.ld.S
@@ -12,6 +12,7 @@ *acs_entry.o(.text*) *(.text*) *(.data*) + *(.ddr_settings*) } //ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.")
diff --git a/arch/arm/mach-meson/g12a/firmware/acs/acs.mk b/arch/arm/mach-meson/g12a/firmware/acs/acs.mk index 2294d53..883a9df 100644 --- a/arch/arm/mach-meson/g12a/firmware/acs/acs.mk +++ b/arch/arm/mach-meson/g12a/firmware/acs/acs.mk
@@ -1,8 +1,9 @@ -SOURCES += acs.c \ - acs_entry.S +SOURCES += acs_entry.S ifdef CONFIG_MDUMP_COMPRESS SOURCES += ramdump.c endif +SOURCES += acs.c + LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/g12a/oscring.c b/arch/arm/mach-meson/g12a/oscring.c index df93ff2..5a18f31 100644 --- a/arch/arm/mach-meson/g12a/oscring.c +++ b/arch/arm/mach-meson/g12a/oscring.c
@@ -100,7 +100,7 @@ } printf("osc efuse info:\n"); - for (i = 0; i <= 11; i++) + for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++) printf("0x%x, ", efuseinfo[i]); printf("\n"); @@ -207,4 +207,4 @@ return ring_msr_sm1(index); return 0; -} \ No newline at end of file +}
diff --git a/arch/arm/mach-meson/g12a/usb.c b/arch/arm/mach-meson/g12a/usb.c new file mode 100644 index 0000000..3993bb3 --- /dev/null +++ b/arch/arm/mach-meson/g12a/usb.c
@@ -0,0 +1,454 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <bitfield.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <power/regulator.h> +#include <clk.h> +#include <asm/arch/usb.h> +#include <amlogic/cpu_id.h> + +#include <linux/compat.h> +#include <linux/ioport.h> +#include <asm-generic/gpio.h> + +#define U2_CTRL_SLEEP_SHIFT 17 +#define U2_HHI_MEM_PD_MASK 0x3 +#define U2_HHI_MEM_PD_SHIFT 30 +#define U2_CTRL_ISO_SHIFT 17 +#define PHY20_RESET_LEVEL_BIT 16 +#define PHY21_RESET_LEVEL_BIT 17 +#define USB_RESET_BIT 2 + +#define USB2_PHY_PLL_OFFSET_40 (0x09400414) +#define USB2_PHY_PLL_OFFSET_44 (0x927E0000) +#define USB2_PHY_PLL_OFFSET_48 (0xac5f49e5) +#define USB2_SM1_PHY_PLL_OFFSET_48 (0xac5f69e5) + +#define USB2_PHY_PLL_OFFSET_10 (0x80000fff) +#define USB2_PHY_PLL_OFFSET_34 (0x78000) + +#define USB2_PHY_PLL_OFFSET_38_CLEAR (0) +#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004) +#define USB2_PHY_PLL_OFFSET_50 (0xfe18) +#define USB2_PHY_PLL_OFFSET_54 (0x2a) + +#define TUNING_DISCONNECT_THRESHOLD 0x34 + +static int Rev_flag = 0; + +static struct phy usb_phys[2]; + +/*Rev_flag == 0XB, g12b and revB, tl1 */ +/*Rev_flag == 1, sm1 */ +static void phy_aml_usb2_check_rev (void) +{ + cpu_id_t cpu_id = get_cpu_id(); + + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) { + if (cpu_id.chip_rev == 0xb) + Rev_flag = 0xb; + else + Rev_flag = 0; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1) { + Rev_flag = MESON_CPU_MAJOR_ID_SM1; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_A1) { + Rev_flag = MESON_CPU_MAJOR_ID_A1; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) { + Rev_flag = MESON_CPU_MAJOR_ID_C1; + } + return; +} + +static int phy_aml_usb2_get_rev_type (void) +{ + int val = 0; + + switch (Rev_flag) { + case MESON_CPU_MAJOR_ID_SM1: + case MESON_CPU_MAJOR_ID_A1: + case MESON_CPU_MAJOR_ID_C1: + case 0xb: + val = 1; + break; + default: + printk("amlogic usb phy need tuning\n"); + val = 0; + break; + } + + return val; +} + +int get_usbphy_baseinfo(struct phy *usb_phys) +{ + struct udevice *bus; + struct uclass *uc; + int ret, i; + unsigned int count; + + if (usb_phys[0].dev && usb_phys[1].dev) + return 0; + + ret = uclass_get(UCLASS_USB, &uc); + if (ret) + return ret; + uclass_foreach_dev(bus, uc) { + debug("bus->name=%s, bus->driver->name =%s\n", + bus->name, bus->driver->name); + count = dev_count_phandle_with_args(bus, "phys", "#phy-cells"); + debug("usb phy count=%u\n", count); + if (count <= 0) + return count; + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(bus, i, &usb_phys[i]); + if (ret && ret != -ENOENT) { + pr_err("Failed to get USB PHY%d for %s\n", + i, bus->name); + return ret; + } + ret = generic_phy_getinfo(&usb_phys[i]); + if (ret) + return ret; + } + } + return 0; +} + +int usb_aml_detect_operation(int argc, char * const argv[]) +{ + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + int ret; + + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + + if (usb3_priv) { + printf("priv->usb3 port num = %d, config addr=0x%08x\n", + usb3_priv->usb3_port_num, usb3_priv->base_addr); + } + if (usb2_priv) { + printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n", + usb2_priv->base_addr, usb2_priv->reset_addr); + + printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n", + usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0], + usb2_priv->usb_phy2_pll_base_addr[1]); + printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr); + } + phy_aml_usb2_check_rev(); + printf("PHY version is 0x%02x\n", Rev_flag); + return 0; +} + +static void usb_set_power_domain (void) +{ + int rev_type; + + rev_type = phy_aml_usb2_get_rev_type(); + if (rev_type ) { + writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << U2_CTRL_SLEEP_SHIFT))), + P_AO_RTI_GEN_PWR_SLEEP0); + writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << U2_CTRL_ISO_SHIFT))), + P_AO_RTI_GEN_PWR_ISO0); + writel((readl(P_HHI_MEM_PD_REG0) + & (~(U2_HHI_MEM_PD_MASK << U2_HHI_MEM_PD_SHIFT))), P_HHI_MEM_PD_REG0); + } + + return; +} + +static void set_pll_Calibration_default(uint32_t phy2_pll_base) +{ + u32 tmp; + + tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8)); + tmp &= 0xfff; + tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) + = tmp; +} + +void usb_reset(unsigned int reset_addr, int bit){ + *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit); +} + +void set_usb_pll(uint32_t phy2_pll_base) +{ + unsigned int pll_offset_48; + int hardware_rev; + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40)) + = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) = + USB2_PHY_PLL_OFFSET_44; + hardware_rev = phy_aml_usb2_get_rev_type(); + if (hardware_rev) + pll_offset_48 = USB2_SM1_PHY_PLL_OFFSET_48; + else + pll_offset_48 = USB2_PHY_PLL_OFFSET_48; + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) = + pll_offset_48; + udelay(100); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40)) + = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE)) + & (~(USB_PHY2_RESET))); + if (hardware_rev) { + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54)) + = USB2_PHY_PLL_OFFSET_54; + set_pll_Calibration_default(phy2_pll_base); + } else { + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) + = USB2_PHY_PLL_OFFSET_10; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38)) + = USB2_PHY_PLL_OFFSET_38_CLEAR; + } + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) = + TUNING_DISCONNECT_THRESHOLD; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34)) + = USB2_PHY_PLL_OFFSET_34; + debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD); +} + +int usb_save_phy_dev (unsigned int number, struct phy *phy) +{ + usb_phys[number].dev = phy->dev; + usb_phys[number].id = phy->id; + return 0; +} + +int usb2_phy_init (struct phy *phy) { + struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev); + struct u2p_aml_regs *u2p_aml_reg; + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + int i,cnt; + + usb_save_phy_dev(0, phy); + phy_aml_usb2_check_rev(); + usb_set_power_domain(); + + usb_reset(priv->reset_addr, USB_RESET_BIT); + + udelay(500); + priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT; + priv->usbphy_reset_bit[1] = PHY21_RESET_LEVEL_BIT; + + for (i = 0; i < priv->u2_port_num; i++) { + u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE)); + dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0; + dev_u2p_r0.b.host_device= 1; + dev_u2p_r0.b.POR= 0; + u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32; + udelay(10); + /***USB PHY RESET : reset1 and reset1_level both need set ***/ + /***reset1: usb_reset ***/ + /***reset1_level: usb_enable_phy_pll ***/ + usb_reset(priv->reset_addr, priv->usbphy_reset_bit[i]); + udelay(50); + + /* wait for phy ready */ + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + cnt = 0; + while (dev_u2p_r1.b.phy_rdy != 1) { + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + /*we wait phy ready max 1ms, common is 100us*/ + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + } + + for (i = 0; i < priv->u2_port_num; i++) { + debug("------set usb pll\n"); + set_usb_pll(priv->usb_phy2_pll_base_addr[i]); + } + return 0; + +} + +int usb2_phy_tuning(uint32_t phy2_pll_base, int port) +{ + unsigned long phy_reg_base; + unsigned int pll_set38, pll_set34, pll_set3, pll_set4; + unsigned int rev_type = 0; + + if (port > 2) + return 0; + + pll_set38 = USB2_PHY_PLL_OFFSET_38_SET; + pll_set34 = USB2_PHY_PLL_OFFSET_34; + + debug("pll38=0x%08x, pll34=0x%08x,\n", + pll_set38, pll_set34); + + + phy_reg_base = phy2_pll_base; + + rev_type = phy_aml_usb2_get_rev_type(); + if (rev_type) { + return 0; + } + + (*(volatile uint32_t *)(phy_reg_base + 0x38)) = pll_set38; + (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set34; + return 0; +} +/**************************************************************/ +/* device mode config */ +/**************************************************************/ +unsigned int usb_get_dwc_a_base_addr(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->dwc2_a_addr; +} + +unsigned int usb_get_device_mode_phy_base(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->usb_phy2_pll_base_addr[1]; +} + +void usb_phy_tuning_reset(void) +{ + unsigned long phy_reg_base = usb_get_device_mode_phy_base(); + int rev_type; + + rev_type = phy_aml_usb2_get_rev_type(); + + if (rev_type) + return; + if (phy_reg_base == 0) + return; + + (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB2_PHY_PLL_OFFSET_38_CLEAR; + (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB2_PHY_PLL_OFFSET_34; +} + +void usb_device_mode_init(void){ + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + + usb_r0_t dev_usb_r0; + usb_r4_t dev_usb_r4; + int cnt, ret; + u2p_aml_regs_t * u2p_aml_regs; + usb_aml_regs_t *usb_aml_regs; + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + unsigned int phy_base_addr, reset_addr; + + phy_aml_usb2_check_rev(); + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + if (!usb2_priv || !usb3_priv) { + printf("get usb phy address from dts failed\n"); + return; + } + + u2p_aml_regs = (u2p_aml_regs_t * )((ulong)(usb2_priv->base_addr + PHY_REGISTER_SIZE)); + usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr); + phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[1]; + reset_addr = usb2_priv->reset_addr; + + usb_set_power_domain(); + + printf("PHY2=0x%08x,PHY3=0x%08x\n", u2p_aml_regs, usb_aml_regs); + if ((*(volatile uint32_t *)((ulong)(phy_base_addr + 0x38))) != 0) { + usb_phy_tuning_reset(); + mdelay(150); + } + + //step 1: usb controller reset + usb_reset(reset_addr, USB_RESET_BIT); + + // step 3: enable usb INT internal USB + dev_usb_r0.d32 = usb_aml_regs->usb_r0; + dev_usb_r0.b.u2d_ss_scaledown_mode = 0; + dev_usb_r0.b.u2d_act = 1; + usb_aml_regs->usb_r0 = dev_usb_r0.d32; + + // step 4: disable usb phy sleep + dev_usb_r4.d32 = usb_aml_regs->usb_r4; + dev_usb_r4.b.p21_SLEEPM0 = 1; + usb_aml_regs->usb_r4 = dev_usb_r4.d32; + + // step 5: config phy21 device mode + dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; + dev_u2p_r0.b.host_device= 0; + dev_u2p_r0.b.POR= 0; + u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; + + udelay(10); + //step 6: phy21 reset + usb_reset(reset_addr, PHY21_RESET_LEVEL_BIT); + udelay(50); + + // step 6: wait for phy ready + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + cnt = 0; + while ((dev_u2p_r1.d32 & 0x00000001) != 1) { + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + + set_usb_pll(phy_base_addr); + //-------------------------------------------------- + + // ------------- usb phy21 initinal end ---------- + + //-------------------------------------------------- + +} +
diff --git a/arch/arm/mach-meson/g12b/Makefile b/arch/arm/mach-meson/g12b/Makefile index 17a815e..dbdb708 100644 --- a/arch/arm/mach-meson/g12b/Makefile +++ b/arch/arm/mach-meson/g12b/Makefile
@@ -6,6 +6,7 @@ obj-y += mailbox.o obj-y += gate_init.o obj-y += power_cal.o +obj-y += usb.o obj-$(CONFIG_CMD_PLLTEST) += pll.o obj-$(CONFIG_CMD_AML_MTEST) += core.o obj-$(CONFIG_AML_HDMITX) += hdmitx.o
diff --git a/arch/arm/mach-meson/g12b/bl31_apis.c b/arch/arm/mach-meson/g12b/bl31_apis.c index e0c2d7d..d01bfe8 100644 --- a/arch/arm/mach-meson/g12b/bl31_apis.c +++ b/arch/arm/mach-meson/g12b/bl31_apis.c
@@ -27,6 +27,36 @@ return function_id; } +int32_t set_boot_params(const keymaster_boot_params *boot_params) +{ + const unsigned cmd = SET_BOOT_PARAMS; + + if (!boot_params) + return -1; + + if (!sharemem_input_base) + sharemem_input_base = + get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); + + memcpy((void *)sharemem_input_base, + (const void *)boot_params, sizeof(keymaster_boot_params)); + + asm __volatile__("" : : : "memory"); + register uint64_t x0 asm("x0") = cmd; + register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params); + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1)); + } while (0); + + return (!x0)? -1: 0; +} + #ifdef CONFIG_EFUSE int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg) { @@ -393,3 +423,37 @@ return -1; } + +int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen) +{ + const unsigned cmd = GET_AVBKEY_FROM_FIP; + uint32_t retlen = 0; + uint32_t ret = 0; + + if (!buf) + return -1; + + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + asm __volatile__("" : : : "memory"); + register uint64_t x0 asm("x0") = cmd; + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + "smc #0\n" + : "=r"(x0) + : "r"(x0)); + } while (0); + + if (!x0) + ret = -1; + retlen = x0; + + if (ret != -1 && buflen >= retlen) + memcpy(buf, (const void *)sharemem_output_base, retlen); + + return ret; +}
diff --git a/arch/arm/mach-meson/g12b/firmware/acs/acs.ld.S b/arch/arm/mach-meson/g12b/firmware/acs/acs.ld.S index 09f7b7d..4a952c7 100644 --- a/arch/arm/mach-meson/g12b/firmware/acs/acs.ld.S +++ b/arch/arm/mach-meson/g12b/firmware/acs/acs.ld.S
@@ -12,6 +12,7 @@ *acs_entry.o(.text*) *(.text*) *(.data*) + *(.ddr_settings*) } //ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.")
diff --git a/arch/arm/mach-meson/g12b/oscring.c b/arch/arm/mach-meson/g12b/oscring.c index 4259434..3b52a23 100644 --- a/arch/arm/mach-meson/g12b/oscring.c +++ b/arch/arm/mach-meson/g12b/oscring.c
@@ -105,7 +105,7 @@ } printf("osc efuse info:\n"); - for (i = 0; i <= 11; i++) + for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++) printf("0x%x, ", efuseinfo[i]); printf("\n");
diff --git a/arch/arm/mach-meson/g12b/usb.c b/arch/arm/mach-meson/g12b/usb.c new file mode 100644 index 0000000..105cf3e --- /dev/null +++ b/arch/arm/mach-meson/g12b/usb.c
@@ -0,0 +1,425 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <bitfield.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <power/regulator.h> +#include <clk.h> +#include <asm/arch/usb.h> +#include <amlogic/cpu_id.h> + +#include <linux/compat.h> +#include <linux/ioport.h> +#include <asm-generic/gpio.h> + +#define PHY20_RESET_LEVEL_BIT 16 +#define PHY21_RESET_LEVEL_BIT 17 +#define USB_RESET_BIT 2 + +#define USB2_PHY_PLL_OFFSET_40 (0x09400414) +#define USB2_PHY_PLL_OFFSET_44 (0x927E0000) +#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5) + +#define USB2_PHY_PLL_OFFSET_10 (0x80000fff) +#define USB2_PHY_PLL_OFFSET_34 (0x78000) +#define USB2_REVB_PHY_PLL_OFFSET_34 (0x70000) + +#define USB2_PHY_PLL_OFFSET_38_CLEAR (0) +#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004) +#define USB2_PHY_PLL_OFFSET_50 (0xfe18) +#define USB2_PHY_PLL_OFFSET_54 (0x2a) + +#define TUNING_DISCONNECT_THRESHOLD 0x3C + +static int Rev_flag = 0; + +static struct phy usb_phys[2]; + +/*Rev_flag == 0XB, g12b and revB, tl1 */ +/*Rev_flag == 1, sm1 */ +static void phy_aml_usb2_check_rev (void) +{ + cpu_id_t cpu_id = get_cpu_id(); + + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) { + if (cpu_id.chip_rev == 0xb) + Rev_flag = 0xb; + else + Rev_flag = 0; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1) { + Rev_flag = MESON_CPU_MAJOR_ID_SM1; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_A1) { + Rev_flag = MESON_CPU_MAJOR_ID_A1; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) { + Rev_flag = MESON_CPU_MAJOR_ID_C1; + } + return; +} + +static int phy_aml_usb2_get_rev_type (void) +{ + int val = 0; + + switch (Rev_flag) { + case MESON_CPU_MAJOR_ID_SM1: + case MESON_CPU_MAJOR_ID_A1: + case MESON_CPU_MAJOR_ID_C1: + case 0xb: + val = 1; + break; + default: + printk("amlogic usb phy need tuning\n"); + val = 0; + break; + } + + return val; +} + +int get_usbphy_baseinfo(struct phy *usb_phys) +{ + struct udevice *bus; + struct uclass *uc; + int ret, i; + unsigned int count; + + if (usb_phys[0].dev && usb_phys[1].dev) + return 0; + + ret = uclass_get(UCLASS_USB, &uc); + if (ret) + return ret; + uclass_foreach_dev(bus, uc) { + debug("bus->name=%s, bus->driver->name =%s\n", + bus->name, bus->driver->name); + count = dev_count_phandle_with_args(bus, "phys", "#phy-cells"); + debug("usb phy count=%u\n", count); + if (count <= 0) + return count; + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(bus, i, &usb_phys[i]); + if (ret && ret != -ENOENT) { + pr_err("Failed to get USB PHY%d for %s\n", + i, bus->name); + return ret; + } + ret = generic_phy_getinfo(&usb_phys[i]); + if (ret) + return ret; + } + } + return 0; +} + +int usb_aml_detect_operation(int argc, char * const argv[]) +{ + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + int ret; + + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + + if (usb3_priv) { + printf("priv->usb3 port num = %d, config addr=0x%08x\n", + usb3_priv->usb3_port_num, usb3_priv->base_addr); + } + if (usb2_priv) { + printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n", + usb2_priv->base_addr, usb2_priv->reset_addr); + + printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n", + usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0], + usb2_priv->usb_phy2_pll_base_addr[1]); + printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr); + } + phy_aml_usb2_check_rev(); + printf("PHY version is 0x%02x\n", Rev_flag); + return 0; +} + +static void set_pll_Calibration_default(uint32_t phy2_pll_base) +{ + u32 tmp; + + tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8)); + tmp &= 0xfff; + tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) + = tmp; +} + +void usb_reset(unsigned int reset_addr, int bit){ + *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit); +} + +void set_usb_pll(uint32_t phy2_pll_base) +{ + int hardware_rev; + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40)) + = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) = + USB2_PHY_PLL_OFFSET_44; + hardware_rev = phy_aml_usb2_get_rev_type(); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) = + USB2_PHY_PLL_OFFSET_48; + udelay(100); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40)) + = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE)) + & (~(USB_PHY2_RESET))); + + if (hardware_rev) { + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54)) + = USB2_PHY_PLL_OFFSET_54; + set_pll_Calibration_default(phy2_pll_base); + } else { + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) + = USB2_PHY_PLL_OFFSET_10; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38)) + = USB2_PHY_PLL_OFFSET_38_CLEAR; + } + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) = + TUNING_DISCONNECT_THRESHOLD; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34)) + = USB2_PHY_PLL_OFFSET_34; + debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD); +} + +int usb_save_phy_dev (unsigned int number, struct phy *phy) +{ + usb_phys[number].dev = phy->dev; + usb_phys[number].id = phy->id; + return 0; +} + +int usb2_phy_init (struct phy *phy) { + struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev); + struct u2p_aml_regs *u2p_aml_reg; + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + int i,cnt; + + usb_save_phy_dev(0, phy); + phy_aml_usb2_check_rev(); + + *(volatile unsigned int *)priv->reset_addr = (1 << USB_RESET_BIT); + + udelay(500); + priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT; + priv->usbphy_reset_bit[1] = PHY21_RESET_LEVEL_BIT; + + for (i = 0; i < priv->u2_port_num; i++) { + u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE)); + dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0; + dev_u2p_r0.b.host_device= 1; + dev_u2p_r0.b.POR= 0; + u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32; + udelay(10); + *(volatile unsigned int *)priv->reset_addr = (1 << priv->usbphy_reset_bit[i]); + udelay(50); + + /* wait for phy ready */ + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + cnt = 0; + while (dev_u2p_r1.b.phy_rdy != 1) { + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + /*we wait phy ready max 1ms, common is 100us*/ + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + } + + for (i = 0; i < priv->u2_port_num; i++) { + debug("------set usb pll\n"); + set_usb_pll(priv->usb_phy2_pll_base_addr[i]); + } + return 0; + +} + +int usb2_phy_tuning(uint32_t phy2_pll_base, int port) +{ + unsigned long phy_reg_base; + unsigned int pll_set38, pll_set34, pll_set3, pll_set4; + unsigned int rev_type = 0; + + if (port > 2) + return 0; + + pll_set38 = USB2_PHY_PLL_OFFSET_38_SET; + pll_set34 = USB2_PHY_PLL_OFFSET_34; + + debug("pll38=0x%08x, pll34=0x%08x,\n", + pll_set38, pll_set34); + + + phy_reg_base = phy2_pll_base; + + rev_type = phy_aml_usb2_get_rev_type(); + if (rev_type) { + return 0; + } + + (*(volatile uint32_t *)(phy_reg_base + 0x38)) = pll_set38; + (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set34; + return 0; +} + +/**************************************************************/ +/* device mode config */ +/**************************************************************/ +unsigned int usb_get_dwc_a_base_addr(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->dwc2_a_addr; +} + +unsigned int usb_get_device_mode_phy_base(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->usb_phy2_pll_base_addr[1]; +} + +void usb_phy_tuning_reset(void) +{ + unsigned long phy_reg_base = usb_get_device_mode_phy_base(); + int rev_type; + + if (phy_reg_base == 0) + return; + rev_type = phy_aml_usb2_get_rev_type(); + + if (rev_type) + return; + + (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB2_PHY_PLL_OFFSET_38_CLEAR; + (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB2_PHY_PLL_OFFSET_34; +} + +void usb_device_mode_init(void){ + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + + usb_r0_t dev_usb_r0; + usb_r4_t dev_usb_r4; + int cnt, ret; + u2p_aml_regs_t * u2p_aml_regs; + usb_aml_regs_t *usb_aml_regs; + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + unsigned int phy_base_addr, reset_addr; + + phy_aml_usb2_check_rev(); + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + if (!usb2_priv || !usb3_priv) { + printf("get usb phy address from dts failed\n"); + return; + } + + u2p_aml_regs = (u2p_aml_regs_t * )((unsigned long)(usb2_priv->base_addr + PHY_REGISTER_SIZE)); + usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr); + phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[1]; + reset_addr = usb2_priv->reset_addr; + + printf("PHY2=0x%08x,PHY3=0x%08x\n", u2p_aml_regs, usb_aml_regs); + if ((*(volatile uint32_t *)(phy_base_addr + 0x38)) != 0) { + usb_phy_tuning_reset(); + mdelay(150); + } + + //step 1: usb controller reset + usb_reset(reset_addr, USB_RESET_BIT); + + // step 3: enable usb INT internal USB + dev_usb_r0.d32 = usb_aml_regs->usb_r0; + dev_usb_r0.b.u2d_ss_scaledown_mode = 0; + dev_usb_r0.b.u2d_act = 1; + usb_aml_regs->usb_r0 = dev_usb_r0.d32; + + // step 4: disable usb phy sleep + dev_usb_r4.d32 = usb_aml_regs->usb_r4; + dev_usb_r4.b.p21_SLEEPM0 = 1; + usb_aml_regs->usb_r4 = dev_usb_r4.d32; + + // step 5: config phy21 device mode + dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; + dev_u2p_r0.b.host_device= 0; + dev_u2p_r0.b.POR= 0; + u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; + + udelay(10); + //step 6: phy21 reset + usb_reset(reset_addr, PHY21_RESET_LEVEL_BIT); + udelay(50); + + // step 6: wait for phy ready + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + cnt = 0; + while ((dev_u2p_r1.d32 & 0x00000001) != 1) { + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + + //set_usb_phy21_pll(); + set_usb_pll(phy_base_addr); + //-------------------------------------------------- + + // ------------- usb phy21 initinal end ---------- + + //-------------------------------------------------- + +} +
diff --git a/arch/arm/mach-meson/hard_sha2.c b/arch/arm/mach-meson/hard_sha2.c index 49a73ba..782cc8b 100644 --- a/arch/arm/mach-meson/hard_sha2.c +++ b/arch/arm/mach-meson/hard_sha2.c
@@ -8,7 +8,7 @@ #include <string.h> #include <dma.h> #include <asm/arch/regs.h> -#include <asm/arch-c1/secure_apb.h> +#include <asm/arch/secure_apb.h> #include <u-boot/sha256.h> #ifndef __AP_DMA_H__ @@ -50,7 +50,7 @@ uint8_t *hash, uint8_t last_update) { dma_dsc_t dsc; - unsigned char szTempSHA2[32]; + unsigned char szTempSHA2[64]; if (!last_update && (ilen % 64)) {
diff --git a/arch/arm/mach-meson/sc2/Makefile b/arch/arm/mach-meson/sc2/Makefile new file mode 100644 index 0000000..091200f --- /dev/null +++ b/arch/arm/mach-meson/sc2/Makefile
@@ -0,0 +1,15 @@ + +obj-y := sdio.o pinctrl_init.o +obj-y += bl31_apis.o +obj-y += cpu_reset.o +obj-y += timer.o +obj-y += mailbox.o +#obj-y += gate_init.o +#obj-y += power_cal.o +obj-$(CONFIG_CMD_PLLTEST) += pll.o +obj-$(CONFIG_CMD_AML_MTEST) += core.o +obj-y += usb.o +obj-$(CONFIG_AML_TSENSOR) += tsensor.o +obj-$(CONFIG_AML_OSCRING) += oscring.o +obj-$(CONFIG_AML_HDMITX20) += hdmitx_hw.o hdmitx_clk.o +obj-y += aml_efuse.o
diff --git a/arch/arm/mach-meson/sc2/aml_efuse.c b/arch/arm/mach-meson/sc2/aml_efuse.c new file mode 100644 index 0000000..16005e0 --- /dev/null +++ b/arch/arm/mach-meson/sc2/aml_efuse.c
@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. +*/ + +#include <common.h> +#include <asm/arch/io.h> +#include <amlogic/aml_efuse.h> +#include <asm/arch/secure_apb.h> + +//function for EFUSE license query +int IS_FEAT_BOOT_VERIFY(void) +{ + uint32_t lic_val; + + lic_val = readl(OTP_LIC00); + + if (((lic_val>>8) & 0x3ff0c) == 0x3ff0c) + return 1; + + return 0; +}
diff --git a/arch/arm/mach-meson/sc2/bl31_apis.c b/arch/arm/mach-meson/sc2/bl31_apis.c new file mode 100644 index 0000000..9ed4d32 --- /dev/null +++ b/arch/arm/mach-meson/sc2/bl31_apis.c
@@ -0,0 +1,578 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/* + * Trustzone API + */ + +#include <asm/arch/io.h> +#include <asm/arch/efuse.h> +#include <asm/cache.h> +#include <asm/arch/bl31_apis.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> + +static long sharemem_input_base; +static long sharemem_output_base; + +long get_sharemem_info(unsigned long function_id) +{ + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + : "+r" (function_id)); + + return function_id; +} + +int32_t set_boot_params(const keymaster_boot_params *boot_params) +{ + const unsigned cmd = SET_BOOT_PARAMS; + + if (!boot_params) + return -1; + + if (!sharemem_input_base) + sharemem_input_base = + get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); + + memcpy((void *)sharemem_input_base, + (const void *)boot_params, sizeof(keymaster_boot_params)); + + asm __volatile__("" : : : "memory"); + register uint64_t x0 asm("x0") = cmd; + register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params); + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1)); + } while (0); + + return (!x0)? -1: 0; +} + +#ifdef CONFIG_EFUSE +int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg) +{ + int ret; + unsigned cmd, offset, size; + unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy); + + if (!sharemem_input_base) + sharemem_input_base = + get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + if (arg->cmd == EFUSE_HAL_API_READ) + cmd = EFUSE_READ; + else if (arg->cmd == EFUSE_HAL_API_WRITE) + cmd = EFUSE_WRITE; + else + cmd = EFUSE_WRITE_PATTERN; + offset = arg->offset; + size = arg->size; + + if (arg->cmd == EFUSE_HAL_API_WRITE) + memcpy((void *)sharemem_input_base, + (const void *)arg->buffer_phy, size); + asm __volatile__("" : : : "memory"); + + register uint64_t x0 asm("x0") = cmd; + register uint64_t x1 asm("x1") = offset; + register uint64_t x2 asm("x2") = size; + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2)); + } while (0); + ret = x0; + *retcnt = x0; + + if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0)) + memcpy((void *)arg->buffer_phy, + (const void *)sharemem_output_base, ret); + + if (!ret) + return -1; + else + return 0; +} + +int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg) +{ + int32_t ret; + unsigned cmd; + + if (arg->cmd == EFUSE_HAL_API_USER_MAX) + cmd = EFUSE_USER_MAX; + + asm __volatile__("" : : : "memory"); + + register uint64_t x0 asm("x0") = cmd; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + "smc #0\n" + : "=r"(x0) + : "r"(x0)); + } while (0); + ret = x0; + + if (!ret) + return -1; + else + return ret; +} + +ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count) +{ + struct efuse_hal_api_arg arg; + unsigned long retcnt; + + if (count != EFUSE_BYTES) + return 0; /* Past EOF */ + + arg.cmd = EFUSE_HAL_API_WRITE_PATTERN; + arg.offset = 0; + arg.size = count; + arg.buffer_phy = (unsigned long)buf; + arg.retcnt_phy = (unsigned long)&retcnt; + int ret; + ret = meson_trustzone_efuse(&arg); + return ret; +} +#endif + +uint64_t meson_trustzone_efuse_check(unsigned char *addr) +{ + uint64_t ret = 0; + struct sram_hal_api_arg arg = {}; + + arg.cmd = SRAM_HAL_API_CHECK_EFUSE; + arg.req_len = 0x1000000; + arg.res_len = 0; + arg.req_phy_addr = (unsigned long)addr; + arg.res_phy_addr = (unsigned long)NULL; + + asm __volatile__("" : : : "memory"); + + register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API; + register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM; + register uint64_t x2 asm("x2") = (unsigned long)(&arg); + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2)); + } while (0); + + ret = x0; + + return ret; +} + +void debug_efuse_cmd(unsigned long cmd) +{ + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + : : "r" (cmd)); +} + +void bl31_debug_efuse_write_pattern(const char *buf) +{ + if (!sharemem_input_base) + sharemem_input_base = + get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); + memcpy((void *)sharemem_input_base, (const void *)buf, 512); + + debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN); +} + +void bl31_debug_efuse_read_pattern(char *buf) +{ + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN); + + memcpy((void *)buf, (const void *)sharemem_output_base, 512); +} + +void aml_set_jtag_state(unsigned state, unsigned select) +{ + uint64_t command; + if (state == JTAG_STATE_ON) + command = JTAG_ON; + else + command = JTAG_OFF; + asm __volatile__("" : : : "memory"); + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : : "r" (command), "r"(select)); +} + +void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value) +{ + register long x0 asm("x0") = 0x82000086; + register long x1 asm("x1") = cmd; + register long x2 asm("x2") = value; + register long x3 asm("x3") = 0; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); +} + +unsigned aml_get_reboot_reason(void) +{ + unsigned reason; + uint64_t ret; + + register uint64_t x0 asm("x0") = GET_REBOOT_REASON; + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + :"+r"(x0)); + ret = x0; + reason = (unsigned)(ret&0xffffffff); + return reason; +} + +void set_viu_probe_enable(void) +{ + register uint64_t x0 asm("x0") = VIU_PREOBE_EN; + + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + :"+r"(x0)); +} + +void power_set_dsp(unsigned int id, unsigned int powerflag) +{ + register long x0 asm("x0") = DSP_SEC_POWERSET; + register long x1 asm("x1") = id; + register long x2 asm("x2") = powerflag; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2)); +} + +void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0) +{ + register long x0 asm("x0") = START_HIFI4; + register long x1 asm("x1") = id; + register long x2 asm("x2") = addr; + register long x3 asm("x3") = cfg0; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); +} + + +unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2) +{ + register long x0 asm("x0") = function_id; + register long x1 asm("x1") = arg0; + register long x2 asm("x2") = arg1; + register long x3 asm("x3") = arg2; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); + + return function_id; +} + +/* clear boot sequence related registers */ +void aml_set_bootsequence(uint32_t val) +{ + register long x0 asm("x0") = SET_STORAGE_BOOTSEQUENCE; + register long x1 asm("x1") = val; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + :"+r"(x0) + : "r" (x1)); + + return; +} + +void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2) +{ + register long x0 asm("x0") = function_id; + register long x1 asm("x1") = arg0; + register long x2 asm("x2") = arg1; + register long x3 asm("x3") = arg2; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); + + return ; +} + +unsigned long aml_sec_boot_check(unsigned long nType, + unsigned long pBuffer, + unsigned long nLength, + unsigned long nOption) +{ + uint64_t ret = 1; + +//#define AML_SECURE_LOG_TE + +#if defined(AML_SECURE_LOG_TE) + #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0); + unsigned nT1,nT2,nT3; +#else + #define AML_GET_TE(...) +#endif + + AML_GET_TE(nT1); + + switch (nType) { + case AML_D_P_W_EFUSE_AMLOGIC: + case AML_D_P_W_EFUSE_SECURE_BOOT: + break; + default: + return 0; + } + + asm __volatile__("" : : : "memory"); + + register uint64_t x0 asm("x0") = AML_DATA_PROCESS; + register uint64_t x1 asm("x1") = nType; + register uint64_t x2 asm("x2") = pBuffer; + register uint64_t x3 asm("x3") = nLength; + register uint64_t x4 asm("x4") = nOption; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + __asmeq("%4", "x3") + __asmeq("%5", "x4") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4)); + } while (0); + + ret = x0; + + AML_GET_TE(nT2);; + + flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength); + + AML_GET_TE(nT3); + +#if defined(AML_SECURE_LOG_TE) + printf("aml log : dec use %d(us) , flush cache used %d(us)\n", + nT2 - nT1, nT3 - nT2); +#endif + + return ret; +} + +void set_usb_boot_function(unsigned long command) +{ + register long x0 asm("x0") = SET_USB_BOOT_FUNC; + register long x1 asm("x1") = command; + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r" (x0) + : "r" (x1)); +} + +void set_boot_first_timeout(uint64_t arg0) +{ + register long x0 asm("x0") = SET_BOOT_FIRST; + register long x1 asm("x1") = arg0; + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r" (x0) + : "r" (x1)); +} +void aml_system_off(void) +{ + /* TODO: Add poweroff capability */ + aml_reboot(0x82000042, 1, 0, 0); + aml_reboot(0x84000008, 0, 0, 0); +} + +int __get_chip_id(unsigned char *buff, unsigned int size) +{ + if (buff == NULL || size < 16) + return -1; + + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + if (sharemem_output_base) { + register long x0 asm("x0") = GET_CHIP_ID; + register long x1 asm("x1") = 2; + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r" (x0) + : "r" (x1)); + + if (x0 == 0) { + int version = *((unsigned int *)sharemem_output_base); + + if (version == 2) { + memcpy(buff, (void *)sharemem_output_base + 4, 16); + } + else { + /** + * Legacy 12-byte chip ID read out, transform data + * to expected order format. + */ + uint32_t chip_info = 0;//readl(P_AO_SEC_SD_CFG8); + uint8_t *ch; + int i; + + ((uint32_t *)buff)[0] = + ((chip_info & 0xff000000) | // Family ID + ((chip_info << 8) & 0xff0000) | // Chip Revision + ((chip_info >> 8) & 0xff00)); // Package ID + + ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]); + + /* Transform into expected order for display */ + ch = (uint8_t *)(sharemem_output_base + 4); + for (i = 0; i < 12; i++) + buff[i + 4] = ch[11 - i]; + } + + return 0; + } + } + + return -1; +} + +int bl31_get_cornerinfo(uint8_t *outbuf, int size) +{ + int buff_len = 0; + + if (outbuf == NULL) { + printf("BL33: corner efuse info storebuf is NULL\n"); + return -1; + } + + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + if (sharemem_output_base) { + register long x0 asm("x0") = OSCRING_EFUSE_GET; + register long x1 asm("x1") = size; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r" (x0) + : "r" (x1)); + } while(0); + buff_len = x0; + if (buff_len <= size) { + memcpy(outbuf, (void *)sharemem_output_base, buff_len); + return 0; + } else { + printf("BL33: corner efuse info buf len %d over storebuf size %d\n", buff_len, size); + return -1; + } + } + return -1; +} + +int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen) +{ + const unsigned cmd = GET_AVBKEY_FROM_FIP; + uint32_t retlen = 0; + uint32_t ret = 0; + + if (!buf) + return -1; + + if (!sharemem_output_base) + sharemem_output_base = + get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE); + + asm __volatile__("" : : : "memory"); + register uint64_t x0 asm("x0") = cmd; + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + "smc #0\n" + : "=r"(x0) + : "r"(x0)); + } while (0); + + if (!x0) + ret = -1; + retlen = x0; + + if (ret != -1 && buflen >= retlen) + memcpy(buf, (const void *)sharemem_output_base, retlen); + + return ret; +}
diff --git a/arch/arm/mach-meson/sc2/core.c b/arch/arm/mach-meson/sc2/core.c new file mode 100644 index 0000000..8640828 --- /dev/null +++ b/arch/arm/mach-meson/sc2/core.c
@@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/types.h> +#include <asm/arch/cpu.h> +#include <common.h> + +const unsigned int core_map[] = { + 0x0, + 0x1, + 0x2, + 0x3, +}; + +int get_core_mpidr(unsigned int cpuid) +{ + unsigned int coremax = (unsigned int)(sizeof(core_map)/sizeof(unsigned int)); + + if (cpuid >= coremax) + return -1; + return core_map[cpuid]; +} + +int get_core_idx(unsigned int mpidr) +{ + unsigned int clusterid, cpuid; + + cpuid = mpidr & 0xff; + clusterid = mpidr & 0xff00; + + cpuid += (clusterid >> 6); + + if (cpuid >= NR_CPUS) + return -1; + + return cpuid; +} + +int get_core_max(void) +{ + return (sizeof(core_map)/sizeof(unsigned int)); +}
diff --git a/arch/arm/mach-meson/sc2/cpu_reset.c b/arch/arm/mach-meson/sc2/cpu_reset.c new file mode 100644 index 0000000..ca0a42d --- /dev/null +++ b/arch/arm/mach-meson/sc2/cpu_reset.c
@@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/types.h> +#include <asm/arch/romboot.h> +#include <asm/arch/cpu_reset.h> +#include <asm/arch/io.h> +#include <asm/arch/timer.h> +#include <dm.h> +#include <wdt.h> + +/* + *GPIOE_0 VDDEE_PWM + *GPIOE_1 VDDCPU_PWM + * */ +void set_pwm_to_input(void) +{ + //hxbao, need fine tune + #if 0 + unsigned int val; + + val = readl(AO_RTI_PINMUX_REG1); + val &= ~(0xff << 16); + writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */ + val = readl(AO_GPIO_O_EN_N); + val &= ~(0x3 << 16); + val |= 0x3 << 16; + writel(val, AO_GPIO_O_EN_N);/* set input mode */ + val = readl(AO_RTI_PULL_UP_EN_REG); + val &= ~(0x3 << 16); + writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */ + #endif +} + +void reset_system(void) +{ + struct udevice *watchdog_devp; + int ret; + + set_pwm_to_input(); + + _udelay(10000); //wait print + + ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp); + if (ret < 0) { + printf("failed to reset system because can't get wdt device\n"); + return; + } + wdt_start(watchdog_devp, 0, 0); + while (1); +} + +/* uboot reset interface */ +void reset_cpu(unsigned long flag){ + reset_system(); +}
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/Makefile b/arch/arm/mach-meson/sc2/firmware/acs/Makefile new file mode 100644 index 0000000..01d869a --- /dev/null +++ b/arch/arm/mach-meson/sc2/firmware/acs/Makefile
@@ -0,0 +1,437 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# Default values for build configurations +# + +export CROSS_COMPILE=/opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf- + +include $(buildsrc)/config.mk +include $(buildtree)/include/autoconf.mk +include $(buildtree)/.config + +# Build verbosity +V := 0 +# Debug build +BUILD_TYPE := ${BL2_BUILD_TYPE} +# Build architecture +ARCH := aarch64 +# Build platform +#DEFAULT_PLAT := gx +PLAT := ${SOC} +export PLAT +# SPD choice +SPD := none +# Base commit to perform code check on +BASE_COMMIT := origin/master +# NS timer register save and restore +NS_TIMER_SWITCH := 0 +# By default, Bl1 acts as the reset handler, not BL31 +RESET_TO_BL31 := 0 + +# Checkpatch ignores +CHECK_IGNORE = --ignore COMPLEX_MACRO + +CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE} +CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE} + +ifeq (${V},0) + Q=@ + CHECKCODE_ARGS += --no-summary --terse +else + Q= +endif +export Q + +ifeq (${GIT_VERSION},) + GIT_VERSION := $(shell git describe --abbrev=7 --dirty --always --tags) +endif +ifeq (${BUILDER},) + BUILDER := ${USER}@$(shell hostname) +endif + +BL_COMMON_SOURCES := common/bl_common.c \ + common/debug.c \ + lib/aarch64/cache_helpers.S \ + lib/aarch64/misc_helpers.S \ + lib/aarch64/tlb_helpers.S \ + lib/aarch64/xlat_helpers.c \ + lib/stdlib/std.c \ + lib/io_storage.c \ + plat/common/aarch64/platform_helpers.S + +BUILD_BASE := $(buildtree)/firmware +#BUILD_PLAT := ${BUILD_BASE}/${PLAT} +BUILD_PLAT := $(buildtree)/board/${BOARDDIR}/firmware +#BUILD_PLAT := $(buildtree)/${BOARDDIR}/firmware + +# Convenience function for adding build definitions +# $(eval $(call add_define,FOO)) will have: +# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +# Convenience function for verifying option has a boolean value +# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1 +define assert_boolean +$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean)) +endef + +ifeq (${PLAT},) + $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.") +endif + +all: msg_start + +msg_start: + @echo "Building ${BOARDDIR}/acs.bin" + +#include plat/${PLAT}/platform.mk +#ifdef BL2_SOURCES +NEED_BL2 := yes +include acs.mk +#endif + +# Include SPD Makefile if one has been specified +ifneq (${SPD},none) + # We expect to locate an spd.mk under the specified SPD directory + SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m") + + ifeq (${SPD_MAKE},) + $(error Error: No services/spd/${SPD}/${SPD}.mk located) + endif + $(info Including ${SPD_MAKE}) + include ${SPD_MAKE} + + # If there's BL32 companion for the chosen SPD, and the SPD wants to build the + # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32 + # variable to "yes" +endif + +.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip +.SUFFIXES: + +INCLUDES += -Iinclude/bl2 \ + -Iinclude/bl31 \ + -Iinclude/common \ + -Iinclude/drivers \ + -Iinclude/drivers/arm \ + -Iinclude/drivers/serial \ + -Iinclude/lib \ + -Iinclude/lib/aarch64 \ + -Iinclude/plat/common \ + -Iinclude/stdlib \ + -Iinclude/stdlib/sys \ + ${PLAT_INCLUDES} \ + ${SPD_INCLUDES} + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +else +CFLAGS += -g +ASFLAGS += -g -Wa,--gdwarf-2 +endif + +# Process NS_TIMER_SWITCH flag +$(eval $(call assert_boolean,NS_TIMER_SWITCH)) +$(eval $(call add_define,NS_TIMER_SWITCH)) + +# Process RESET_TO_BL31 flag +$(eval $(call assert_boolean,RESET_TO_BL31)) +$(eval $(call add_define,RESET_TO_BL31)) + +VPATH_LIST = $(buildsrc)/board/$(BOARDDIR) +#VPATH_LIST = $(buildsrc)/$(BOARDDIR) +VPATH_LIST:=$(VPATH_LIST:%=%/firmware/) + +vpath %.c $(VPATH_LIST) + +ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \ + -mgeneral-regs-only -D__ASSEMBLY__ \ + ${DEFINES} ${INCLUDES} +CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \ + -Werror -mgeneral-regs-only -std=c99 -c -Os \ + ${DEFINES} ${INCLUDES} $(VPATH_LIST:%=-I%) +CFLAGS += -ffunction-sections -fdata-sections +ASFLAGS += ${FIRMWARE_CPPFLAGS} +CFLAGS += ${FIRMWARE_CPPFLAGS} +CFLAGS += -Wno-unused + +LDFLAGS += --fatal-warnings -O1 +LDFLAGS += --gc-sections + +OCFLAGS += -j .dev_header -j .generic_param -j .clk_param \ + -j .misc_param -j .store_param -j .ddr_param \ + --gap-fill 0x0 + +CC := ${CROSS_COMPILE}gcc +CPP := ${CROSS_COMPILE}cpp +AS := ${CROSS_COMPILE}gcc +AR := ${CROSS_COMPILE}ar +LD := ${CROSS_COMPILE}ld +OC := ${CROSS_COMPILE}objcopy +OD := ${CROSS_COMPILE}objdump +NM := ${CROSS_COMPILE}nm +PP := ${CROSS_COMPILE}gcc -E ${CFLAGS} + +# Variables for use with Firmware Image Package +FIPTOOLPATH ?= tools/fip_create +FIPTOOL ?= ${FIPTOOLPATH}/fip_create +fiptool: ${FIPTOOL} +fip: ${BUILD_PLAT}/fip.bin + +locate-checkpatch: +ifndef CHECKPATCH + $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl") +else +ifeq (,$(wildcard ${CHECKPATCH})) + $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl") +endif +endif + +clean: + @echo " CLEAN" + ${Q}rm -rf ${BUILD_PLAT} + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean + +realclean distclean: + @echo " REALCLEAN" + ${Q}rm -rf ${BUILD_BASE} + ${Q}rm -f ${CURDIR}/cscope.* + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean + +checkcodebase: locate-checkpatch + @echo " CHECKING STYLE" + @if test -d .git ; then \ + git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \ + else \ + find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \ + fi + +checkpatch: locate-checkpatch + @echo " CHECKING STYLE" + @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true + +${FIPTOOL}: + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} + @echo + @echo "Built $@ successfully" + @echo + +define match_goals +$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS)))) +endef + +# List of rules that involve building things +BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip + +# Does the list of goals specified on the command line include a build target? +ifneq ($(call match_goals,${BUILD_TARGETS}),) +IS_ANYTHING_TO_BUILD := 1 +endif + +define MAKE_C + +$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) +$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) + +$(OBJ) : $(2) + @echo " CC $$<" + $$(Q)$$(CC) $$(CFLAGS) -c $$< -o $$@ + + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $(1) + $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_S + +$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) +$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) + +$(OBJ) : $(2) + @echo " AS $$<" + $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@ + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $(1) + $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_LD + +$(eval PREREQUISITES := $(1).d) + +$(1) : $(2) + @echo " PP $$<" + $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$< + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $$(dir $$@) + $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_OBJS + $(eval C_OBJS := $(filter %.c,$(2))) + $(eval REMAIN := $(filter-out %.c,$(2))) + $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj)))) + + $(eval S_OBJS := $(filter %.S,$(REMAIN))) + $(eval REMAIN := $(filter-out %.S,$(REMAIN))) + $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj)))) + + $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN))) +endef + + +# NOTE: The line continuation '\' is required in the next define otherwise we +# end up with a line-feed characer at the end of the last c filename. +# Also bare this issue in mind if extending the list of supported filetypes. +define SOURCES_TO_OBJS + $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \ + $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1)))) +endef + +define MAKE_BL + $(eval BUILD_DIR := ${BUILD_PLAT}) + $(eval SOURCES := $(SOURCES)) + $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES)))) + $(eval LINKERFILE := $(BUILD_DIR)/acs.ld) + $(eval MAPFILE := $(BUILD_DIR)/acs.map) + $(eval ELF := $(BUILD_DIR)/acs.elf) + $(eval DUMP := $(BUILD_DIR)/acs.dump) + $(eval BIN := $(BUILD_DIR)/acs.bin) + + $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES))) + $(eval $(call MAKE_LD,$(LINKERFILE),$(LINKERFILE_T))) + +$(BUILD_DIR) : + $$(Q)mkdir -p "$$@" + +$(ELF) : $(OBJS) $(LINKERFILE) + @echo " LD $$@" + @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__". \\nver:${GIT_VERSION} - ${BUILDER}";' | \ + $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o + $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \ + $(BUILD_DIR)/build_message.o $(OBJS) + +$(DUMP) : $(ELF) + @echo " OD $$@" + $${Q}$${OD} -D -x $$< > $$@ + +$(BIN) : $(ELF) + @echo " BIN $$@" + $$(Q)$$(OC) $$(OCFLAGS) -O binary $$< $$@.tmp + @dd if=/dev/zero of=$$@ bs=4096 count=7 + @dd if=$$@.tmp of=$$@ conv=notrunc && rm -f $$@.tmp + @echo + @echo "Built $$@ successfully" + @echo + +.PHONY : bl$(1) +bl$(1) : $(BUILD_DIR) $(DUMP) $(BIN) + +all : bl$(1) + +$(eval FIP_DEPS += $(if $2,$(BIN),)) +$(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),)) + +endef + +ifeq (${NEED_BL2},yes) +$(eval $(call MAKE_BL,2,in_fip)) +endif + +${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL} + $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd")) + ${Q}${FIPTOOL} --dump \ + ${FIP_ARGS} \ + --bl33 ${BL33} \ + $@ + @echo + @echo "Built $@ successfully" + @echo + + +cscope: + @echo " CSCOPE" + ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files + ${Q}cscope -b -q -k + +help: + @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>" + @echo "" + @echo "PLAT is used to specify which platform you wish to build." + @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}" + @echo "" + @echo "Supported Targets:" + @echo " all Build the BL1, BL2 and BL31 binaries" + @echo " bl1 Build the BL1 binary" + @echo " bl2 Build the BL2 binary" + @echo " bl31 Build the BL31 binary" + @echo " checkcodebase Check the coding style of the entire source tree" + @echo " checkpatch Check the coding style on changes in the current" + @echo " branch against BASE_COMMIT (default origin/master)" + @echo " clean Clean the build for the selected platform" + @echo " cscope Generate cscope index" + @echo " distclean Remove all build artifacts for all platforms" + @echo " fiptool Build the Firmware Image Package(FIP) creation tool" + @echo "" + @echo "note: most build targets require PLAT to be set to a specific platform." + @echo "" + @echo "example: build all targets for the FVP platform:" + @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/acs.c b/arch/arm/mach-meson/sc2/firmware/acs/acs.c new file mode 100644 index 0000000..f6f58e1 --- /dev/null +++ b/arch/arm/mach-meson/sc2/firmware/acs/acs.c
@@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <version.h> +#include <asm/arch/acs.h> +#include <asm/arch/timing.h> +#include "timing.c" + +dev_param_hdr_t __param_hdr __attribute__ ((section(".dev_header"))) = { + .magic = DEV_PARAM_MAGIC, + .version = DEV_PARAM_VERSION, + + .bl2_regs_magic = "bl2r_", + .bl2_regs_length = sizeof(__bl2_reg), + + .board_clk_magic = "bclk_", + .board_clk_length = sizeof(__board_clk_setting), + + .opt_reg_magic = "ops__", + .opt_reg_length = sizeof(__bl2_ops_reg), + + .sto_set_magic = "store", + .sto_set_length = sizeof(__store_para), + + .ddr_set_magic = "ddrs_", + .ddr_set_length = sizeof(__ddr_setting), +}; +
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/acs.ld.S b/arch/arm/mach-meson/sc2/firmware/acs/acs.ld.S new file mode 100644 index 0000000..3f84ef3 --- /dev/null +++ b/arch/arm/mach-meson/sc2/firmware/acs/acs.ld.S
@@ -0,0 +1,55 @@ + +OUTPUT_FORMAT("elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(acs_entry) + +SECTIONS +{ + . = 0x00007000; + . = ALIGN(4); + .entry : { + __RO_START__ = .; + *acs_entry.o(.text*) + *(.text*) + *(.data*) + *(.bss*) + } + + . = 0x00000000; + .dev_header : + { + *(.dev_header*) + } + + . = 0x00000200; + .generic_param : + { + *(.generic_param*) + } + + . = 0x00005800; + .clk_param : + { + *(.clk_param*) + } + + . = 0x00005c00; + .misc_param : + { + *(.misc_param*) + } + + . = 0x00005e00; + .store_param : + { + *(.store_param*) + } + + . = 0x00006000; + .ddr_param : + { + *(.ddr_param*) + } + + ASSERT(. <= 0x00007000, "params image has exceeded its limit.") +}
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/acs.mk b/arch/arm/mach-meson/sc2/firmware/acs/acs.mk new file mode 100644 index 0000000..0c63194 --- /dev/null +++ b/arch/arm/mach-meson/sc2/firmware/acs/acs.mk
@@ -0,0 +1,9 @@ +SOURCES += acs_entry.S + +ifdef CONFIG_MDUMP_COMPRESS +SOURCES += ramdump.c +endif + +SOURCES += acs.c + +LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/acs_entry.S b/arch/arm/mach-meson/sc2/firmware/acs/acs_entry.S new file mode 100644 index 0000000..e6ec19b --- /dev/null +++ b/arch/arm/mach-meson/sc2/firmware/acs/acs_entry.S
@@ -0,0 +1,14 @@ + + .globl acs_entry + +acs_entry: + .word __param_hdr + .word __bl2_reg + .word __board_clk_setting + .word __bl2_ops_reg + .word __store_para + .word __ddr_setting + .rept 10 + .word 0x0 + .endr +
diff --git a/arch/arm/mach-meson/sc2/firmware/bl21/Makefile b/arch/arm/mach-meson/sc2/firmware/bl21/Makefile new file mode 100644 index 0000000..b6d7d1a --- /dev/null +++ b/arch/arm/mach-meson/sc2/firmware/bl21/Makefile
@@ -0,0 +1,3 @@ +all: + @echo "BL21 no action for A1 " +
diff --git a/arch/arm/mach-meson/sc2/firmware/scp_task/Makefile b/arch/arm/mach-meson/sc2/firmware/scp_task/Makefile new file mode 100644 index 0000000..925690d --- /dev/null +++ b/arch/arm/mach-meson/sc2/firmware/scp_task/Makefile
@@ -0,0 +1,3 @@ +all: + echo "BL301 no action for A1" +
diff --git a/arch/arm/mach-meson/sc2/gate_init.c b/arch/arm/mach-meson/sc2/gate_init.c new file mode 100644 index 0000000..31629f6 --- /dev/null +++ b/arch/arm/mach-meson/sc2/gate_init.c
@@ -0,0 +1,366 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include "power_gate.h" + +#define SECUREBOOT_FLAG_ADDR 0xc8100228 + +#ifdef CONFIG_AML_CVBS +extern unsigned int cvbs_mode; +#endif +void ee_gate_off(void) +{ + printf("ee_gate_off ...\n"); + return; +/* int secureboot = readl(SECUREBOOT_FLAG_ADDR)&(1<<5);*/ + +#ifdef CONFIG_AML_CVBS + unsigned int cvbs_opened = 0; +#endif + +#ifdef CONFIG_AML_CVBS + if ((cvbs_mode == 0) || (cvbs_mode == 1)) + cvbs_opened = 1; +#endif + + /* + //if close , audio maybe have noise + CLK_GATE_OFF(AUD); + CLK_GATE_OFF(AUD2); + CLK_GATE_OFF(AUD_CLK_2); + CLK_GATE_OFF(AUD_CLK_3); + */ + CLK_GATE_OFF(AUD_IN); + CLK_GATE_OFF(AIU_AUD_MIXER); + CLK_GATE_OFF(SANA); + + /*kernel will reopen */ + CLK_GATE_OFF(CTS_ENCL); + /* CLK_GATE_OFF(CTS_ENCT); */ +#if 0 /* HDMITX 480i60hz/576i50hz need this gate */ +#ifdef CONFIG_AML_CVBS + if (cvbs_opened == 0) + CLK_GATE_OFF(CTS_ENCI); +#else + CLK_GATE_OFF(CTS_ENCI); +#endif +#endif + /* CLK_GATE_OFF(CTS_ENCP); */ + + /*close cvbs clock*/ +#ifdef CONFIG_AML_CVBS + if (cvbs_opened == 0) { + CLK_GATE_OFF(DAC_CLK); + CLK_GATE_OFF(CTS_VDAC); + } +#else + CLK_GATE_OFF(DAC_CLK); + CLK_GATE_OFF(CTS_VDAC); +#endif + + /* usb clock close */ + CLK_GATE_OFF(USB0); + CLK_GATE_OFF(USB1); + //CLK_GATE_OFF(USB_CLK); //g12a no reg + CLK_GATE_OFF(MISC_USB0_TO_DDR); + CLK_GATE_OFF(MISC_USB1_TO_DDR); + + /* uarts close */ + CLK_GATE_OFF(UART0); + CLK_GATE_OFF(UART1); + CLK_GATE_OFF(UART2); + CLK_GATE_OFF(UART3); + + CLK_GATE_OFF(VCLK2_VENCP); + CLK_GATE_OFF(VCLK2_VENCT); + CLK_GATE_OFF(VCLK2_VENCT1); + CLK_GATE_OFF(VCLK2_OTHER); +#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */ +#ifdef CONFIG_AML_CVBS + if (cvbs_opened == 0) { + CLK_GATE_OFF(VCLK2_VENCI); + CLK_GATE_OFF(VCLK2_VENCI1); + } +#else + CLK_GATE_OFF(VCLK2_VENCI); + CLK_GATE_OFF(VCLK2_VENCI1); +#endif +#endif + CLK_GATE_OFF(VCLK2_VENCL); + CLK_GATE_OFF(VCLK2_OTHER1); +#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */ +#ifdef CONFIG_AML_CVBS + if (cvbs_opened == 0) + CLK_GATE_OFF(VCLK2_ENCI); +#else + CLK_GATE_OFF(VCLK2_ENCI); +#endif +#endif + CLK_GATE_OFF(VCLK2_ENCL); + CLK_GATE_OFF(VCLK2_ENCT); + + CLK_GATE_OFF(VDEC_CLK_1); + CLK_GATE_OFF(VDEC_CLK_2); + CLK_GATE_OFF(VDEC2_CLK_1); + CLK_GATE_OFF(VDEC2_CLK_2); + CLK_GATE_OFF(HCODEC_CLK_1); + CLK_GATE_OFF(HCODEC_CLK_2); + /* CLK_GATE_OFF(HEVC_CLK_1 ); */ + /* CLK_GATE_OFF(HEVC_CLK_2 ); */ + + //CLK_GATE_OFF(MMC_A_PCLK); //g12a no reg + //CLK_GATE_OFF(MMC_B_PCLK); //g12a no reg + //CLK_GATE_OFF(MMC_C_PCLK); //g12a no reg + + CLK_GATE_OFF(LCD_AN_PHY2); + CLK_GATE_OFF(LCD_AN_PHY3); + + CLK_GATE_OFF(ETHERNET); + //CLK_GATE_OFF(ETH_CLK); //g12a no reg + + CLK_GATE_OFF(GE2D); + CLK_GATE_OFF(GEN_CLK); + //CLK_GATE_OFF(PCM_MCLK); //g12a no reg + //CLK_GATE_OFF(PCM_SCLK); //g12a no reg + + + CLK_GATE_OFF(HIU_PARSER_TOP); + + + /* can not off nand_clk */ + /* CLK_GATE_OFF(NAND_CLK); */ + /* + //HDMI no output + CLK_GATE_OFF(VCLK2_VENCP1); + CLK_GATE_OFF(VCLK2_ENCP); + */ + + /* + //if OFF, HDMI will report error! + CLK_GATE_OFF(HDMI_PCLK); + CLK_GATE_OFF(HDMI_PLL_CNTL); + CLK_GATE_OFF(HDMITX_CLK); + */ + + /* + //PWM B used for VCCK,PWM D used for VDDEE,ignoring + CLK_GATE_OFF(PWM_A_CLK); + CLK_GATE_OFF(PWM_B_CLK); + CLK_GATE_OFF(PWM_C_CLK); + CLK_GATE_OFF(PWM_D_CLK); + CLK_GATE_OFF(PWM_E_CLK); + CLK_GATE_OFF(PWM_F_CLK); + */ + + + /* can not close + CLK_GATE_OFF(VPU_CLK_1); + CLK_GATE_OFF(VPU_CLK_2); + CLK_GATE_OFF(VPU_CLKB); + CLK_GATE_OFF(MALI_CLK_1); + CLK_GATE_OFF(MALI_CLK_2); + CLK_GATE_OFF(ATV_DEMO_VDAC); + CLK_GATE_OFF(EMMC_A); + CLK_GATE_OFF(EMMC_B); + CLK_GATE_OFF(EMMC_C); + CLK_GATE_OFF(EMMC_A_CLK); + CLK_GATE_OFF(EMMC_B_CLK); + + CLK_GATE_OFF(MSR_CLK); + CLK_GATE_OFF(MSR_HS_CLK); + CLK_GATE_OFF(32K_CLK); + CLK_GATE_OFF(VAPB_CLK_1); + CLK_GATE_OFF(VAPB_CLK_2); + CLK_GATE_OFF(GIC); + CLK_GATE_OFF(I2C_AO); //no close for to use + CLK_GATE_OFF(AO_CPU); + CLK_GATE_OFF(ASSIST_MISC); + CLK_GATE_OFF(HIU_PARSER); + CLK_GATE_OFF(PERIPHS_TOP); + CLK_GATE_OFF(PL310_CBUS); + CLK_GATE_OFF(ISA); + CLK_GATE_OFF(SECURE_AHP_APB3); + CLK_GATE_OFF(VPU_INTR); + CLK_GATE_OFF(MMC_PCLK); //can not close + CLK_GATE_OFF(AIU_PCLK); + //can not connect pc + CLK_GATE_OFF(USB_GENERAL); + CLK_GATE_OFF(AHB_DATA_BUS); + CLK_GATE_OFF(AHB_CONTROL_BUS); + CLK_GATE_OFF(HDMI_INTR_SYNC); //should open + //can't suspend @ 2nd time + //CLK_GATE_OFF(RESET); + + // close rom + //disable this bit will make other cpu can not be booted. + //CLK_GATE_OFF(ROM_CLK); + +*/ + /*************************/ + CLK_GATE_OFF(AHB_ARB0); + CLK_GATE_OFF(ASYNC_FIFO); + CLK_GATE_OFF(STREAM); + CLK_GATE_OFF(RANDOM_NUM_GEN); + CLK_GATE_OFF(RANDOM_NUM_GEN1); + CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN); + CLK_GATE_OFF(I2C); + CLK_GATE_OFF(SPI); + CLK_GATE_OFF(SPICC); + CLK_GATE_OFF(DOS); + CLK_GATE_OFF(SAR_ADC); + CLK_GATE_OFF(MISC_DVIN); + CLK_GATE_OFF(BT656); + CLK_GATE_OFF(BT656_2); + CLK_GATE_OFF(PDM); + + /* close AIU */ + CLK_GATE_OFF(AIU_IEC958); + CLK_GATE_OFF(AIU_ICE958_AMCLK); + + CLK_GATE_OFF(AIU_AMCLK_MEASURE); + CLK_GATE_OFF(AIU_AIFIFO2); + CLK_GATE_OFF(AIU_MIXER_REG); + CLK_GATE_OFF(AIU_ADC); + CLK_GATE_OFF(AIU_TOP_LEVEL); + CLK_GATE_OFF(AIU_AOCLK); + CLK_GATE_OFF(AIU_AI_TOP_GLUE); + CLK_GATE_OFF(AIU_I2S_OUT); + + CLK_GATE_OFF(ENC480P); + + CLK_GATE_OFF(DEMUX); +/* +* EFUSE/BLK_MOV clock gate must be on, + kernel storage ops depend on them. + it can be reference PD#112732 +*/ +/* + if (secureboot) { + printf("secure boot ignore [ BLK_MOV, efuse ] clk gate\n"); + } else { + CLK_GATE_OFF(EFUSE); + CLK_GATE_OFF(BLK_MOV); + } +*/ +} + +void ee_gate_on(void) +{ + + printf("ee_gate_on ...\n"); + + /* + //if close , audio maybe have noise + CLK_GATE_ON(AUD); + CLK_GATE_ON(AUD2); + CLK_GATE_ON(AUD_CLK_2); + CLK_GATE_ON(AUD_CLK_3); + */ + CLK_GATE_ON(AUD_IN); + CLK_GATE_ON(AIU_AUD_MIXER); + CLK_GATE_ON(SANA); + + /*kernel will reopen */ + CLK_GATE_ON(CTS_ENCL); + /* CLK_GATE_ON(CTS_ENCT); */ + CLK_GATE_ON(CTS_ENCI); + /* CLK_GATE_ON(CTS_ENCP); */ + + /*close cvbs clock*/ + CLK_GATE_ON(DAC_CLK); + CLK_GATE_ON(CTS_VDAC); + + /* usb clock close */ + CLK_GATE_ON(USB0); + CLK_GATE_ON(USB1); + //CLK_GATE_ON(USB_CLK); //g12a no reg + CLK_GATE_ON(MISC_USB0_TO_DDR); + CLK_GATE_ON(MISC_USB1_TO_DDR); + + /* uarts close */ + CLK_GATE_ON(UART0); + CLK_GATE_ON(UART1); + CLK_GATE_ON(UART2); + CLK_GATE_ON(UART3); + + CLK_GATE_ON(VCLK2_VENCP); + CLK_GATE_ON(VCLK2_VENCT); + CLK_GATE_ON(VCLK2_VENCT1); + CLK_GATE_ON(VCLK2_OTHER); + CLK_GATE_ON(VCLK2_VENCI); + CLK_GATE_ON(VCLK2_VENCI1); + CLK_GATE_ON(VCLK2_VENCL); + CLK_GATE_ON(VCLK2_OTHER1); + + + CLK_GATE_ON(VCLK2_ENCI); + CLK_GATE_ON(VCLK2_ENCL); + CLK_GATE_ON(VCLK2_ENCT); + + CLK_GATE_ON(VDEC_CLK_1); + CLK_GATE_ON(VDEC_CLK_2); + CLK_GATE_ON(VDEC2_CLK_1); + CLK_GATE_ON(VDEC2_CLK_2); + CLK_GATE_ON(HCODEC_CLK_1); + CLK_GATE_ON(HCODEC_CLK_2); + /* CLK_GATE_ON(HEVC_CLK_1 ); */ + /* CLK_GATE_ON(HEVC_CLK_2 ); */ + + //CLK_GATE_ON(MMC_A_PCLK); //g12a no reg + //CLK_GATE_ON(MMC_B_PCLK); //g12a no reg + //CLK_GATE_ON(MMC_C_PCLK); //g12a no reg + + CLK_GATE_ON(LCD_AN_PHY2); + CLK_GATE_ON(LCD_AN_PHY3); + + CLK_GATE_ON(ETHERNET); + //CLK_GATE_ON(ETH_CLK); //g12a no reg + + CLK_GATE_ON(GE2D); + CLK_GATE_ON(GEN_CLK); + //CLK_GATE_ON(PCM_MCLK); //g12a no reg + //CLK_GATE_ON(PCM_SCLK); //g12a no reg + + + CLK_GATE_ON(HIU_PARSER_TOP); + + /*************************/ + CLK_GATE_ON(AHB_ARB0); + CLK_GATE_ON(ASYNC_FIFO); + CLK_GATE_ON(STREAM); + CLK_GATE_ON(RANDOM_NUM_GEN); + CLK_GATE_ON(RANDOM_NUM_GEN1); + CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN); + CLK_GATE_ON(I2C); + CLK_GATE_ON(SPI); + CLK_GATE_ON(SPICC); + CLK_GATE_ON(DOS); + CLK_GATE_ON(SAR_ADC); + CLK_GATE_ON(MISC_DVIN); + CLK_GATE_ON(BT656); + CLK_GATE_ON(BT656_2); + CLK_GATE_ON(PDM); + + /* close AIU */ + CLK_GATE_ON(AIU_IEC958); + CLK_GATE_ON(AIU_ICE958_AMCLK); + + CLK_GATE_ON(AIU_AMCLK_MEASURE); + CLK_GATE_ON(AIU_AIFIFO2); + CLK_GATE_ON(AIU_MIXER_REG); + CLK_GATE_ON(AIU_ADC); + CLK_GATE_ON(AIU_TOP_LEVEL); + CLK_GATE_ON(AIU_AOCLK); + CLK_GATE_ON(AIU_AI_TOP_GLUE); + CLK_GATE_ON(AIU_I2S_OUT); + + CLK_GATE_ON(ENC480P); + + CLK_GATE_ON(DEMUX); + + CLK_GATE_ON(EFUSE); + CLK_GATE_ON(BLK_MOV); +} +
diff --git a/arch/arm/mach-meson/sc2/gpio.c b/arch/arm/mach-meson/sc2/gpio.c new file mode 100644 index 0000000..7332773 --- /dev/null +++ b/arch/arm/mach-meson/sc2/gpio.c
@@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <dm.h> +#include <linux/compiler.h> +#include <amlogic/aml_gpio.h> +#include <asm/arch/gpio.h> + +struct pin_mux_desc { + unsigned char domain; + unsigned char reg; + unsigned char bit; +}; + +#define MUX_AO_DOMAIN 0 +#define MUX_EE_DOMAIN 1 + +#define PIN_MUX(d, r, b) \ +{ \ + .domain = d, \ + .reg = r, \ + .bit = b, \ +} + +#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ +{ \ + .name = n, \ + .first = f, \ + .last = l, \ + .regs = { \ + [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \ + [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \ + [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \ + [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \ + [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \ + }, \ + } +#define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ +{ \ + .name = n, \ + .first = f, \ + .last = l, \ + .regs = { \ + [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \ + [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \ + [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \ + [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \ + [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \ + }, \ + } + +static struct pin_mux_desc pin_to_gpio[] = { + [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0), + [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4), + [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8), + [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12), + [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16), + [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20), + [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24), + [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28), + [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0), + [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4), + [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8), + [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12), + [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16), + [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20), + [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24), + [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0), + [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4), + [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8), + [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12), + [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16), + [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20), + [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24), + [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28), + [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0), + [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4), + [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8), + [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12), + [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16), + [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20), + [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24), + [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28), + [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0), + [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4), + [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8), + [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12), + [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16), + [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20), + [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24), + [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28), + [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0), + [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0), + [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4), + [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8), + [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12), + [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16), + [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20), + [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24), + [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28), + [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0), + [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4), + [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8), + [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12), + [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16), + [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20), + [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24), + [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28), + [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0), + [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4), + [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8), + [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12), + [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16), + [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20), + [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24), + [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28), + [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0), + [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4), + [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8), + [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12), + [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16), + [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20), + [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24), + [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28), + [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0), + [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4), + [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8), + [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12), + [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16), + [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20), + [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24), + [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28), + [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0), + [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4), + [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8), + [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12), + [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16), + [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20), + [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24), + [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28), + [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0), + [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4), + [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8), + [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12), + [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16), + [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20), + [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24), + [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28), + [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0), + [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4), + [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8), + [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12), +}; +/*sequence of banks keep same as arch-g12a/gpio.h*/ +static struct meson_bank mesontxhd_banks[] = { + /*name first last pullen pull dir out in*/ + AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11), + 3, 0, 2, 0, 0, 0, 4, 0, 1, 0), + AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2), + 3, 16, 2, 16, 0, 16, 4, 16, 1, 16), + BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15), + 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8), + 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15), + 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7), + 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), + BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15), + 5, 0, 5, 0, 16, 0, 17, 0, 18, 0), + BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19), + 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), +}; + +U_BOOT_DEVICES(txhd_gpios) = { + { "gpio_aml", &mesontxhd_banks[0] }, + { "gpio_aml", &mesontxhd_banks[1] }, + { "gpio_aml", &mesontxhd_banks[2] }, + { "gpio_aml", &mesontxhd_banks[3] }, + { "gpio_aml", &mesontxhd_banks[4] }, + { "gpio_aml", &mesontxhd_banks[5] }, + { "gpio_aml", &mesontxhd_banks[6] }, + { "gpio_aml", &mesontxhd_banks[7] }, +}; + +static unsigned long domain[]={ + [MUX_AO_DOMAIN] = 0xff800014, + [MUX_EE_DOMAIN] = 0xff6346c0, +}; + +int clear_pinmux(unsigned int pin) +{ + struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin]; + + regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2), + 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit)); + + return 0; +} + +#ifdef CONFIG_AML_SPICC +#include <asm/arch/secure_apb.h> +/* generic pins control for spicc1. + * if deleted, you have to add it into all g12a board files as necessary. + * GPIOH_4: MOSI:regB[19:16]=3 + * GPIOH_5: MISO:regB[23:20]=3 + * GPIOH_7: CLK:regB[31:28]=3 + */ +int spicc1_pinctrl_enable(bool enable) +{ + unsigned int val; + + val = readl(P_PERIPHS_PIN_MUX_B); + val &= ~(0xf0ff << 16); + if (enable) + val |= 0x3033 << 16; + writel(val, P_PERIPHS_PIN_MUX_B); + return 0; +} +#endif /* CONFIG_AML_SPICC */
diff --git a/arch/arm/mach-meson/sc2/hdmitx_clk.c b/arch/arm/mach-meson/sc2/hdmitx_clk.c new file mode 100755 index 0000000..efa27e5 --- /dev/null +++ b/arch/arm/mach-meson/sc2/hdmitx_clk.c
@@ -0,0 +1,870 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> +#include "hdmitx_clk.h" + +static uint32_t frac_rate; + +#define msleep(i) udelay(i*1000) + +#define check_clk_config(para)\ + if (para == -1)\ + return; + +#define check_div() \ + if (div == -1)\ + return ;\ + switch (div) {\ + case 1:\ + div = 0; break;\ + case 2:\ + div = 1; break;\ + case 4:\ + div = 2; break;\ + case 6:\ + div = 3; break;\ + case 12:\ + div = 4; break;\ + default:\ + break;\ + } + +#define WAIT_FOR_PLL_LOCKED(_reg) \ + do { \ + unsigned int st = 0; \ + int cnt = 10; \ + unsigned int reg = _reg; \ + while (cnt--) { \ + msleep(5); \ + st = (((hd_read_reg(reg) >> 30) & 0x3) == 3); \ + if (st) \ + break; \ + else { \ + /* reset hpll */ \ + hd_set_reg_bits(reg, 1, 29, 1); \ + hd_set_reg_bits(reg, 0, 29, 1); \ + } \ + } \ + if (cnt < 9) \ + printf("pll[0x%x] reset %d times\n", reg, 9 - cnt);\ + } while (0) + +static void set_hdmitx_sys_clk(void) +{ + hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0, 9, 3); + hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0, 0, 7); + hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 1, 8, 1); +} + +/* + * When VCO outputs 6.0 GHz, if VCO unlock with default v1 + * steps, then need reset with v2 or v3 + */ +static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val) +{ + int ret = 0; + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + + if (frac_val == 0x8148) { + if (((hdev->para->vic == HDMI_3840x2160p50_16x9) || + (hdev->para->vic == HDMI_3840x2160p60_16x9) || + (hdev->para->vic == HDMI_3840x2160p50_64x27) || + (hdev->para->vic == HDMI_3840x2160p60_64x27)) && + (hdev->para->cs != HDMI_COLOR_FORMAT_420)) { + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293); + } else { + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x44331290); + } + } else { + if (hdmitx_find_vendor(hdev) && + ((hdev->para->vic == HDMI_3840x2160p50_16x9) || + (hdev->para->vic == HDMI_3840x2160p60_16x9) || + (hdev->para->vic == HDMI_3840x2160p50_64x27) || + (hdev->para->vic == HDMI_3840x2160p60_64x27) || + (hdev->para->vic == HDMI_4096x2160p50_256x135) || + (hdev->para->vic == HDMI_4096x2160p60_256x135)) && + (hdev->para->cs != HDMI_COLOR_FORMAT_420)) { + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293); + } else { + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a68dc00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290); + } + } + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + + ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3); + return ret; /* return hpll locked status */ +} + +static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val) +{ + int ret = 0; + + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0xea68dc00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + + ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3); + return ret; /* return hpll locked status */ +} + +static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val) +{ + int ret = 0; + + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff)); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0xea68dc00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x55540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + + ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3); + return ret; /* return hpll locked status */ +} + +void set_hpll_clk_out(unsigned int clk) +{ + pr_info("config HPLL = %d frac_rate = %d\n", clk, frac_rate); + switch (clk) { + case 5940000: + if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000)) + break; + if (set_hpll_hclk_v2(0x7b, 0x18000)) + break; + if (set_hpll_hclk_v3(0xf7, 0x10000)) + break; + break; + case 5850000: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004f3); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 5600000: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004e9); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000aaab); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);/*test*/ + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 5405400: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004e1); + if (frac_rate) + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000); + else + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00007333); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 4897000: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004cc); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000d560); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 4455000: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004b9); + if (frac_rate) + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000e10e); + else + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00014000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 4324320: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004b4); + if (frac_rate) + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000); + else + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00005c29); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 3712500: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00049a); + if (frac_rate) + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x000110e1); + else + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00016000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 3450000: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00048f); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 3243240: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b000487); + if (frac_rate) + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000); + else + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000451f); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 3197500: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b000485); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00007555); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 2970000: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00047b); + if (frac_rate) + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x000140b4); + else + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + case 4032000: + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004a8); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000); + hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1); + WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0); + pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0)); + break; + default: + printf("error hpll clk: %d\n", clk); + break; + } +} + +static void set_hpll_sspll(struct hdmitx_dev *hdev) +{ + enum hdmi_vic vic = hdev->vic; + + switch (vic) { + case HDMI_1920x1080p60_16x9: + case HDMI_1920x1080p50_16x9: + case HDMI_1280x720p60_16x9: + case HDMI_1280x720p50_16x9: + case HDMI_1920x1080i60_16x9: + case HDMI_1920x1080i50_16x9: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 29, 1); + /* bit[22:20] hdmi_dpll_fref_sel + * bit[8] hdmi_dpll_ssc_en + * bit[7:4] hdmi_dpll_ssc_dep_sel + */ + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 1, 20, 3); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 1, 8, 1); + /* 2: 1000ppm 1: 500ppm */ + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 2, 4, 4); + if (hdev->dongle_mode) + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 4, 4, 4); + /* bit[15] hdmi_dpll_sdmnc_en */ + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL3, 0, 15, 1); + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 29, 1); + break; + default: + break; + } +} + +static void set_hpll_od1(unsigned div) +{ + switch (div) { + case 1: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 16, 2); + break; + case 2: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 16, 2); + break; + case 4: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 16, 2); + break; + default: + break; + } +} + +static void set_hpll_od2(unsigned div) +{ + switch (div) { + case 1: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 18, 2); + break; + case 2: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 18, 2); + break; + case 4: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 18, 2); + break; + default: + break; + } +} + +static void set_hpll_od3(unsigned div) +{ + switch (div) { + case 1: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 20, 2); + break; + case 2: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 20, 2); + break; + case 4: + hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 20, 2); + break; + default: + printf("Err %s[%d]\n", __func__, __LINE__); + break; + } +} + +// -------------------------------------------------- +// clocks_set_vid_clk_div +// -------------------------------------------------- +// wire clk_final_en = control[19]; +// wire clk_div1 = control[18]; +// wire [1:0] clk_sel = control[17:16]; +// wire set_preset = control[15]; +// wire [14:0] shift_preset = control[14:0]; +static void set_hpll_od3_clk_div(int div_sel) +{ + int shift_val = 0; + int shift_sel = 0; + + /* When div 6.25, need to reset vid_pll_div */ + if (div_sel == VID_PLL_DIV_6p25) { + msleep(1); + hd_write_reg(P_RESETCTRL_RESET0, 1 << 19); + } + // Disable the output clock + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 18, 2); + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1); + + switch (div_sel) { + case VID_PLL_DIV_1: shift_val = 0xFFFF; shift_sel = 0; break; + case VID_PLL_DIV_2: shift_val = 0x0aaa; shift_sel = 0; break; + case VID_PLL_DIV_3: shift_val = 0x0db6; shift_sel = 0; break; + case VID_PLL_DIV_3p5: shift_val = 0x36cc; shift_sel = 1; break; + case VID_PLL_DIV_3p75: shift_val = 0x6666; shift_sel = 2; break; + case VID_PLL_DIV_4: shift_val = 0x0ccc; shift_sel = 0; break; + case VID_PLL_DIV_5: shift_val = 0x739c; shift_sel = 2; break; + case VID_PLL_DIV_6: shift_val = 0x0e38; shift_sel = 0; break; + case VID_PLL_DIV_6p25: shift_val = 0x0000; shift_sel = 3; break; + case VID_PLL_DIV_7: shift_val = 0x3c78; shift_sel = 1; break; + case VID_PLL_DIV_7p5: shift_val = 0x78f0; shift_sel = 2; break; + case VID_PLL_DIV_12: shift_val = 0x0fc0; shift_sel = 0; break; + case VID_PLL_DIV_14: shift_val = 0x3f80; shift_sel = 1; break; + case VID_PLL_DIV_15: shift_val = 0x7f80; shift_sel = 2; break; + case VID_PLL_DIV_2p5: shift_val = 0x5294; shift_sel = 2; break; + case VID_PLL_DIV_3p25: shift_val = 0x66cc; shift_sel = 2; break; + default: + debug("Error: clocks_set_vid_clk_div: Invalid parameter\n"); + break; + } + + if (shift_val == 0xffff ) { // if divide by 1 + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 18, 1); + } else { + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 18, 1); + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 16, 2); + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1); + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 0, 15); + + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, shift_sel, 16, 2); + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 15, 1); + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, shift_val, 0, 15); + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1); + } + // Enable the final output clock + hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 19, 1); +} + +static void set_vid_clk_div(unsigned div) +{ + check_clk_config(div); + if (div == 0) + div = 1; + hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 0, 16, 3); // select vid_pll_clk + hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div-1, 0, 8); + hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 7, 0, 3); +} + +static void set_hdmi_tx_pixel_div(unsigned div) +{ + check_div(); + hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, div, 16, 4); + hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 5, 1); //enable gate +} + +static void set_encp_div(unsigned div) +{ + check_div(); + hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div, 24, 4); + hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 2, 1); //enable gate + hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 1, 19, 1); +} + +static void set_enci_div(unsigned div) +{ + check_div(); + hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div, 28, 4); + hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 0, 1); //enable gate + hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 1, 19, 1); +} + +/* mode hpll_clk_out od1 od2(PHY) od3 + * vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div + */ +/* For colordepth 8bits */ +static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = { + {{HDMI_720x480i60_4x3, HDMI_720x480i60_16x9, + HDMI_720x576i50_4x3, HDMI_720x576i50_16x9, GROUP_END}, + 1, VIU_ENCI, 4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, -1, 2}, + {{HDMI_720x576p50_4x3, HDMI_720x576p50_16x9, + HDMI_720x480p60_4x3, HDMI_720x480p60_16x9, GROUP_END}, + 1, VIU_ENCP, 4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, 2, -1}, + {{HDMI_720x576p100_16x9, + HDMI_720x480p120_16x9, + GROUP_END}, + 1, VIU_ENCP, 4324320, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1}, + {{HDMI_1280x720p50_16x9, + HDMI_1280x720p60_16x9, + GROUP_END}, + 1, VIU_ENCP, 5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1}, + {{HDMI_1920x1080i60_16x9, + HDMI_1920x1080i50_16x9, + GROUP_END}, + 1, VIU_ENCP, 5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1}, + {{HDMI_1920x1080i100_16x9, + HDMI_1920x1080i120_16x9, + HDMI_1280x720p100_16x9, + HDMI_1280x720p120_16x9, + GROUP_END}, + 1, VIU_ENCP, 5940000, 4, 1, 1, VID_PLL_DIV_5, 1, 2, 2, -1}, + {{HDMI_1920x1080p60_16x9, + HDMI_1920x1080p50_16x9, + GROUP_END}, + 1, VIU_ENCP, 5940000, 4, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + {{HDMI_1920x1080p30_16x9, + HDMI_1920x1080p24_16x9, + HDMI_1920x1080p25_16x9, + GROUP_END}, + 1, VIU_ENCP, 5940000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + {{HDMI_3840x2160p30_16x9, + HDMI_3840x2160p25_16x9, + HDMI_3840x2160p24_16x9, + HDMI_4096x2160p24_256x135, + HDMI_4096x2160p25_256x135, + HDMI_4096x2160p30_256x135, + HDMI_1920x1080p100_16x9, + HDMI_1920x1080p120_16x9, + GROUP_END}, + 1, VIU_ENCP, 5940000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_2160x1200p90hz, + GROUP_END}, + 1, VIU_ENCP, 5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + {{HDMI_3840x2160p60_16x9, + HDMI_3840x2160p50_16x9, + HDMI_4096x2160p60_256x135, + HDMI_4096x2160p50_256x135, + GROUP_END}, + 1, VIU_ENCP, 5940000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1}, + {{HDMI_4096x2160p60_256x135_Y420, + HDMI_4096x2160p50_256x135_Y420, + HDMI_3840x2160p60_16x9_Y420, + HDMI_3840x2160p50_16x9_Y420, + GROUP_END}, + 1, VIU_ENCP, 5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1}, + /* pll setting for VESA modes */ + {{HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */ + GROUP_END}, + 1, VIU_ENCP, 4028000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_800x480p60hz, + GROUP_END}, + 1, VIU_ENCP, 4761600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_800x600p60hz, + GROUP_END}, + 1, VIU_ENCP, 3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_852x480p60hz, + HDMIV_854x480p60hz, + GROUP_END}, + 1, VIU_ENCP, 4838400, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1024x600p60hz, + GROUP_END}, + 1, VIU_ENCP, 4032000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1}, + {{HDMIV_1024x768p60hz, + GROUP_END}, + 1, VIU_ENCP, 5200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1280x768p60hz, + GROUP_END}, + 1, VIU_ENCP, 3180000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1280x800p60hz, + GROUP_END}, + 1, VIU_ENCP, 5680000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1152x864p75hz, + HDMIV_1280x960p60hz, + HDMIV_1280x1024p60hz, + HDMIV_1600x900p60hz, + GROUP_END}, + 1, VIU_ENCP, 4320000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1600x1200p60hz, + GROUP_END}, + 1, VIU_ENCP, 3240000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1360x768p60hz, + HDMIV_1366x768p60hz, + GROUP_END}, + 1, VIU_ENCP, 3420000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1400x1050p60hz, + GROUP_END}, + 1, VIU_ENCP, 4870000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1440x900p60hz, + GROUP_END}, + 1, VIU_ENCP, 4260000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1440x2560p60hz, + GROUP_END}, + 1, VIU_ENCP, 4897000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1440x2560p70hz, + GROUP_END}, + 1, VIU_ENCP, 5600000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1680x1050p60hz, + GROUP_END}, + 1, VIU_ENCP, 5850000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_1920x1200p60hz, + GROUP_END}, + 1, VIU_ENCP, 3865000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + {{HDMIV_2560x1600p60hz, + GROUP_END}, + 1, VIU_ENCP, 3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1}, + { + { + HDMIV_3440x1440p60hz, GROUP_END + }, + 1, VIU_ENCP, 3197500, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1 + }, + { + { + HDMIV_2400x1200p90hz, GROUP_END + }, + 1, VIU_ENCP, 5600000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1 + }, +}; + +/* For colordepth 10bits */ +static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = { + {{HDMI_720x480i60_4x3, HDMI_720x480i60_16x9, + HDMI_720x576i50_4x3, HDMI_720x576i50_16x9, GROUP_END}, + 1, VIU_ENCI, 5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, -1, 2}, + {{HDMI_720x576p50_4x3, HDMI_720x576p50_16x9, + HDMI_720x480p60_4x3, HDMI_720x480p60_16x9, GROUP_END}, + 1, VIU_ENCP, 5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1}, + {{HDMI_720x576p100_16x9, + HDMI_720x480p120_16x9, + GROUP_END}, + 1, VIU_ENCP, 5405400, 4, 2, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1}, + {{HDMI_1280x720p50_16x9, + HDMI_1280x720p60_16x9, + GROUP_END}, + 1, VIU_ENCP, 3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1}, + {{HDMI_1920x1080i60_16x9, + HDMI_1920x1080i50_16x9, + GROUP_END}, + 1, VIU_ENCP, 3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1}, + {{HDMI_1920x1080i120_16x9, + HDMI_1920x1080i100_16x9, + HDMI_1280x720p100_16x9, + HDMI_1280x720p120_16x9, + GROUP_END}, + 1, VIU_ENCP, 3712500, 2, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1}, + {{HDMI_1920x1080p60_16x9, + HDMI_1920x1080p50_16x9, + GROUP_END}, + 1, VIU_ENCP, 3712500, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1}, + {{HDMI_1920x1080p120_16x9, + HDMI_1920x1080p100_16x9, + GROUP_END}, + 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1}, + {{HDMI_1920x1080p30_16x9, + HDMI_1920x1080p24_16x9, + HDMI_1920x1080p25_16x9, + GROUP_END}, + 1, VIU_ENCP, 3712500, 2, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1}, + {{HDMI_4096x2160p60_256x135_Y420, + HDMI_4096x2160p50_256x135_Y420, + HDMI_3840x2160p60_16x9_Y420, + HDMI_3840x2160p50_16x9_Y420, + GROUP_END}, + 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1}, + {{HDMI_3840x2160p24_16x9, + HDMI_3840x2160p25_16x9, + HDMI_3840x2160p30_16x9, + HDMI_4096x2160p24_256x135, + HDMI_4096x2160p25_256x135, + HDMI_4096x2160p30_256x135, + GROUP_END}, + 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1}, +}; + +/* For colordepth 12bits */ +static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = { + {{HDMI_720x480i60_4x3, HDMI_720x480i60_16x9, + HDMI_720x576i50_4x3, HDMI_720x576i50_16x9, GROUP_END}, + 1, VIU_ENCI, 3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, -1, 2}, + {{HDMI_720x576p50_4x3, HDMI_720x576p50_16x9, + HDMI_720x480p60_4x3, HDMI_720x480p60_16x9, GROUP_END}, + 1, VIU_ENCP, 3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1}, + {{HDMI_720x576p100_16x9, + HDMI_720x480p120_16x9, + GROUP_END}, + 1, VIU_ENCP, 3243240, 2, 2, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1}, + {{HDMI_1280x720p50_16x9, + HDMI_1280x720p60_16x9, + GROUP_END}, + 1, VIU_ENCP, 4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1}, + {{HDMI_1920x1080i60_16x9, + HDMI_1920x1080i50_16x9, + GROUP_END}, + 1, VIU_ENCP, 4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1}, + {{HDMI_1920x1080i120_16x9, + HDMI_1920x1080i100_16x9, + HDMI_1280x720p100_16x9, + HDMI_1280x720p120_16x9, + GROUP_END}, + 1, VIU_ENCP, 4455000, 2, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1}, + {{HDMI_1920x1080p60_16x9, + HDMI_1920x1080p50_16x9, + GROUP_END}, + 1, VIU_ENCP, 4455000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1}, + {{HDMI_1920x1080p120_16x9, + HDMI_1920x1080p100_16x9, + GROUP_END}, + 1, VIU_ENCP, 4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1}, + {{HDMI_1920x1080p30_16x9, + HDMI_1920x1080p24_16x9, + HDMI_1920x1080p25_16x9, + GROUP_END}, + 1, VIU_ENCP, 4455000, 2, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1}, + {{HDMI_4096x2160p60_256x135_Y420, + HDMI_4096x2160p50_256x135_Y420, + HDMI_3840x2160p60_16x9_Y420, + HDMI_3840x2160p50_16x9_Y420, + GROUP_END}, + 1, VIU_ENCP, 4455000, 1, 1, 2, VID_PLL_DIV_3p25, 1, 2, 1, -1}, + {{HDMI_3840x2160p24_16x9, + HDMI_3840x2160p25_16x9, + HDMI_3840x2160p30_16x9, + HDMI_4096x2160p24_256x135, + HDMI_4096x2160p25_256x135, + HDMI_4096x2160p30_256x135, + GROUP_END}, + 1, VIU_ENCP, 4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1}, +}; + +static void set_hdmitx_fe_clk(struct hdmitx_dev *hdev) +{ + unsigned int tmp = 0; + enum hdmi_vic vic = hdev->vic; + hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 9, 1); + + switch (vic) { + case HDMI_720x480i60_16x9: + case HDMI_720x576i50_16x9: + case HDMI_720x480i60_4x3: + case HDMI_720x576i50_4x3: + tmp = (hd_read_reg(P_CLKCTRL_VID_CLK_DIV) >> 28) & 0xf; + break; + default: + tmp = (hd_read_reg(P_CLKCTRL_VID_CLK_DIV) >> 24) & 0xf; + break; + } + + hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, tmp, 20, 4); +} + +static void set_hdmitx_clk_(struct hdmitx_dev *hdev, enum hdmi_color_depth cd) +{ + int i = 0; + int j = 0; + struct hw_enc_clk_val_group *p_enc = NULL; + enum hdmi_vic vic = hdev->vic; + char *sspll_dis = NULL; + + if (cd == HDMI_COLOR_DEPTH_24B) { + p_enc = &setting_enc_clk_val_24[0]; + for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_24); j++) { + for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] != GROUP_END)); i ++) { + if (vic == p_enc[j].group[i]) + goto next; + } + } + if (j == ARRAY_SIZE(setting_enc_clk_val_24)) { + debug("Not find VIC = %d for hpll setting\n", vic); + return; + } + } else if (cd == HDMI_COLOR_DEPTH_30B) { + p_enc = &setting_enc_clk_val_30[0]; + for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_30); j++) { + for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] != GROUP_END)); i ++) { + if (vic == p_enc[j].group[i]) + goto next; + } + } + if (j == ARRAY_SIZE(setting_enc_clk_val_30)) { + debug("Not find VIC = %d for hpll setting\n", vic); + return; + } + } else if (cd == HDMI_COLOR_DEPTH_36B) { + p_enc = &setting_enc_clk_val_36[0]; + for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_36); j++) { + for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] + != GROUP_END)); i++) { + if (vic == p_enc[j].group[i]) + goto next; + } + } + if (j == ARRAY_SIZE(setting_enc_clk_val_36)) { + printf("Not find VIC = %d for hpll setting\n", vic); + return; + } + } else { + printf("not support colordepth 48bits\n"); + return; + } +next: + set_hdmitx_sys_clk(); + set_hpll_clk_out(p_enc[j].hpll_clk_out); + sspll_dis = env_get("sspll_dis"); + if ((!sspll_dis || !strcmp(sspll_dis, "0")) && + (cd == HDMI_COLOR_DEPTH_24B)) + set_hpll_sspll(hdev); + set_hpll_od1(p_enc[j].od1); + set_hpll_od2(p_enc[j].od2); + set_hpll_od3(p_enc[j].od3); + set_hpll_od3_clk_div(p_enc[j].vid_pll_div); + debug("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div); + set_vid_clk_div(p_enc[j].vid_clk_div); + set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div); + set_encp_div(p_enc[j].encp_div); + set_enci_div(p_enc[j].enci_div); + set_hdmitx_fe_clk(hdev); +} + +int hdmitx_likely_frac_rate_mode(char *m) +{ + if (strstr(m, "24hz") || strstr(m, "30hz") || strstr(m, "60hz") + || strstr(m, "120hz") || strstr(m, "240hz")) + return 1; + else + return 0; +} + +void hdmitx_set_clk(struct hdmitx_dev *hdev) +{ + char *frac_rate_str = NULL; + + frac_rate_str = env_get("frac_rate_policy"); + if (frac_rate_str && (frac_rate_str[0] == '0')) + frac_rate = 0; + else if (hdmitx_likely_frac_rate_mode(hdev->para->ext_name)) + frac_rate = 1; + hdev->frac_rate_policy = frac_rate; + + if (hdev->para->cs != HDMI_COLOR_FORMAT_422) + set_hdmitx_clk_(hdev, hdev->para->cd); + else + set_hdmitx_clk_(hdev, HDMI_COLOR_DEPTH_24B); +} +
diff --git a/arch/arm/mach-meson/sc2/hdmitx_clk.h b/arch/arm/mach-meson/sc2/hdmitx_clk.h new file mode 100644 index 0000000..d8fda6f --- /dev/null +++ b/arch/arm/mach-meson/sc2/hdmitx_clk.h
@@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMITX_COMMON_H__ +#define __HDMITX_COMMON_H__ + +#include <common.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> + +#define VID_PLL_DIV_1 0 +#define VID_PLL_DIV_2 1 +#define VID_PLL_DIV_3 2 +#define VID_PLL_DIV_3p5 3 +#define VID_PLL_DIV_3p75 4 +#define VID_PLL_DIV_4 5 +#define VID_PLL_DIV_5 6 +#define VID_PLL_DIV_6 7 +#define VID_PLL_DIV_6p25 8 +#define VID_PLL_DIV_7 9 +#define VID_PLL_DIV_7p5 10 +#define VID_PLL_DIV_12 11 +#define VID_PLL_DIV_14 12 +#define VID_PLL_DIV_15 13 +#define VID_PLL_DIV_2p5 14 +#define VID_PLL_DIV_3p25 15 + +enum viu_type { + VIU_ENCL = 0, + VIU_ENCI, + VIU_ENCP, + VIU_ENCT, +}; + +typedef struct{ + enum hdmi_vic vic; + unsigned viu_path; + enum viu_type viu_type; + unsigned hpll_clk_out; + unsigned od1; + unsigned od2; + unsigned od3; + unsigned vid_pll_div; + unsigned vid_clk_div; + unsigned hdmi_tx_pixel_div; + unsigned encp_div; + unsigned enci_div; +}hw_enc_clk_val_t; + +#define GROUP_MAX 10 +#define GROUP_END -1 +struct hw_enc_clk_val_group { + enum hdmi_vic group[GROUP_MAX]; + unsigned viu_path; + enum viu_type viu_type; + unsigned hpll_clk_out; + unsigned od1; + unsigned od2; + unsigned od3; + unsigned vid_pll_div; + unsigned vid_clk_div; + unsigned hdmi_tx_pixel_div; + unsigned encp_div; + unsigned enci_div; +}; + +#endif
diff --git a/arch/arm/mach-meson/sc2/hdmitx_hw.c b/arch/arm/mach-meson/sc2/hdmitx_hw.c new file mode 100644 index 0000000..51c9fbf --- /dev/null +++ b/arch/arm/mach-meson/sc2/hdmitx_hw.c
@@ -0,0 +1,314 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <amlogic/media/vout/hdmitx/hdmitx_module.h> +#include <amlogic/media/vout/hdmitx/hdmitx_reg.h> +#include <amlogic/media/vout/hdmitx/mach_reg.h> +#include <asm/arch/bl31_apis.h> +#include "hdmitx_misc.h" + +static struct reg_map reg_maps[] = { + [CBUS_REG_IDX] = { /* CBUS */ + .base_addr = 0xfe001000, + }, + [PERIPHS_REG_IDX] = { /* PERIPHS */ + .base_addr = 0xfe004000, + }, + [VCBUS_REG_IDX] = { /* VPU */ + .base_addr = 0xff000000, + }, + [HHI_REG_IDX] = { /* HIU */ + .base_addr = 0xfe000000, + }, + [SYSCTRL_REG_IDX] = { + .base_addr = 0xfe010000, + }, + [RESETCTRL_REG_IDX] = { + .base_addr = 0xfe002000, + }, + [ANACTRL_REG_IDX] = { + .base_addr = 0xfe008000, + }, + [PWRCTRL_REG_IDX] = { + .base_addr = 0xfe00c000, + }, + [HDMITX_SEC_REG_IDX] = { /* HDMITX DWC LEVEL*/ + .base_addr = 0xfe300000, + }, + [HDMITX_REG_IDX] = { /* HDMITX TOP LEVEL*/ + .base_addr = 0xfe308000, + }, + [REG_IDX_END] = { + }, +}; + +#define HDMITX_DWC_BASE_OFFSET (reg_maps[HDMITX_SEC_REG_IDX].base_addr) +#define HDMITX_TOP_BASE_OFFSET (reg_maps[HDMITX_REG_IDX].base_addr) + +int hdmitx_get_hpd_state(void) +{ + int st = 0; + + st = !!(hd_read_reg(P_PADCTRL_GPIOH_I) & (1 << 2)); + return st; +} + +void hdmitx_ddc_init(void) +{ + /*Mux DDC SDA/SCL*/ + hd_set_reg_bits(P_PADCTRL_PIN_MUX_REGB, 1, 0, 4); + hd_set_reg_bits(P_PADCTRL_PIN_MUX_REGB, 1, 4, 4); +} + +static uint32_t get_base_addr(uint32_t idx) +{ + if (idx >= REG_IDX_END) + return 0; + if (!reg_maps[idx].base_addr) + printf("%s[%d] idx = %d\n", __func__, __LINE__, idx); + + return reg_maps[idx].base_addr; +} + +uint32_t hd_get_paddr(uint32_t addr) +{ + uint32_t idx = (addr) >> BASE_REG_OFFSET; + uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr); + uint32_t paddr; + + paddr = get_base_addr(idx) + offset_addr; + return paddr; +} + +uint32_t hd_read_reg(uint32_t addr) +{ + uint32_t val; + uint32_t idx = (addr) >> BASE_REG_OFFSET; + uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr); + void *paddr; + + paddr = (void *)((unsigned long)(get_base_addr(idx) + offset_addr)); + val = readl(paddr); + + return val; +} + +void hd_write_reg(unsigned int addr, unsigned int val) +{ + uint32_t idx = (addr) >> BASE_REG_OFFSET; + uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr); + void *paddr; + + paddr = (void *)((unsigned long)(get_base_addr(idx) + offset_addr)); + writel(val, paddr); +} + +void hd_set_reg_bits(unsigned int addr, unsigned int value, + unsigned int offset, unsigned int len) +{ + unsigned int data32 = 0; + + data32 = hd_read_reg(addr); + data32 &= ~(((1 << len) - 1) << offset); + data32 |= (value & ((1 << len) - 1)) << offset; + hd_write_reg(addr, data32); +} + +static unsigned int hdmitx_rd_reg_normal(unsigned int addr) +{ + unsigned int data; + register long x0 asm("x0") = 0x82000018; + register long x1 asm("x1") = (unsigned long)addr; + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + "smc #0\n" + : "+r"(x0) : "r"(x1) + ); + data = (unsigned int)(x0&0xffffffff); + + return data; +} + +static void hdmitx_wr_reg_normal(unsigned int addr, unsigned int data) +{ + register long x0 asm("x0") = 0x82000019; + register long x1 asm("x1") = (unsigned long)addr; + register long x2 asm("x2") = data; + + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + "smc #0\n" + : : "r"(x0), "r"(x1), "r"(x2) + ); +} + +unsigned int hdmitx_rd_reg(unsigned int addr) +{ + unsigned int large_offset = addr >> 24; + unsigned int small_offset = addr & ((1 << 24) - 1); + unsigned long hdmitx_addr = 0; + unsigned int data; + + switch (large_offset) { + case 0x10: + /*DWC*/ + hdmitx_addr = HDMITX_DWC_BASE_OFFSET + small_offset; + data = readb(hdmitx_addr); + break; + case 0x11: + case 0x01: + data = hdmitx_rd_reg_normal(addr); + break; + case 0x00: + default: + /* TOP */ + if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) { + hdmitx_addr = HDMITX_TOP_BASE_OFFSET + small_offset; + data = readb(hdmitx_addr); + } else { + hdmitx_addr = HDMITX_TOP_BASE_OFFSET + (small_offset << 2); + data = readl(hdmitx_addr); + } + break; + } + + return data; +} + +void hdmitx_wr_reg(unsigned int addr, unsigned int data) +{ + unsigned int large_offset = addr >> 24; + unsigned int small_offset = addr & ((1 << 24) - 1); + unsigned long hdmitx_addr = 0; + + switch (large_offset) { + case 0x10: + /*DWC*/ + hdmitx_addr = HDMITX_DWC_BASE_OFFSET + small_offset; + writeb(data & 0xff, hdmitx_addr); + break; + case 0x11: + case 0x01: + /*SECURITY DWC/TOP*/ + hdmitx_wr_reg_normal(addr, data); + break; + case 00: + default: + /*TOP*/ + if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) { + hdmitx_addr = HDMITX_TOP_BASE_OFFSET + small_offset; + writeb(data & 0xff, hdmitx_addr); + } else { + hdmitx_addr = HDMITX_TOP_BASE_OFFSET + (small_offset << 2); + writel(data, hdmitx_addr); + } + } +} + +void hdmitx_set_reg_bits(unsigned int addr, unsigned int value, + unsigned int offset, unsigned int len) +{ + unsigned int data32 = 0; + + data32 = hdmitx_rd_reg(addr); + data32 &= ~(((1 << len) - 1) << offset); + data32 |= (value & ((1 << len) - 1)) << offset; + hdmitx_wr_reg(addr, data32); +} + +void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout) +{ +} + +unsigned int hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data, + unsigned int mask) +{ + return 0; +} + +void hdmitx_hdcp_init(void) +{ + register long x0 asm("x0") = 0x82000012; + asm volatile( + __asmeq("%0", "x0") + "smc #0\n" + : : "r"(x0) + ); +} + +void hdmitx_set_phypara(enum hdmi_phy_para mode) +{ + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x0); +/* P_ANACTRL_HDMIPHY_CTRL1 bit[1]: enable clock bit[0]: soft reset */ +#define RESET_HDMI_PHY() \ +do { \ + hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0xf, 0, 4); \ + mdelay(2); \ + hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0xe, 0, 4); \ + mdelay(2); \ +} while (0) + + hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0x0390, 16, 16); + hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0x0, 0, 4); + RESET_HDMI_PHY(); + RESET_HDMI_PHY(); +#undef RESET_HDMI_PHY + + switch (mode) { + case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */ + case HDMI_PHYPARA_4p5G: + case HDMI_PHYPARA_3p7G: + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x37eb65c4); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x0000080b); + break; + case HDMI_PHYPARA_3G: /* 2.97Gbps */ + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb42a2); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003); + break; + case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */ + case HDMI_PHYPARA_DEF: + default: + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb4252); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003); + break; + } +} + +void hdmitx_turnoff(void) +{ + /* Close HDMITX PHY */ + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0); + /* Disable HPLL */ + hd_write_reg(ANACTRL_HDMIPLL_CTRL0, 0); +} + +void hdmitx_test_prbs(void) +{ + unsigned int i; + + for (i = 0; i < 4; i ++) { + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x0390000f); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x0390000e); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x03904002); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL4, 0x0001efff | (i << 20)); + hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0xef904002); + mdelay(1); + if (i == 0) + printf("prbs clk: %08x\n",hd_read_reg(P_ANACTRL_HDMIPLL_CTRL6)); + else + printf("prbs D[%d]: %08x\n", i -1, hd_read_reg(P_ANACTRL_HDMIPLL_CTRL6)); + } +}
diff --git a/arch/arm/mach-meson/sc2/hdmitx_misc.h b/arch/arm/mach-meson/sc2/hdmitx_misc.h new file mode 100644 index 0000000..5e32df8 --- /dev/null +++ b/arch/arm/mach-meson/sc2/hdmitx_misc.h
@@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMITX_MISC_H__ +#define __HDMITX_MISC_H__ + +/* miscellaneous definition */ + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 */ +#define CLKCTRL_SYS_CLK_EN0_REG2 0x0013 +#define P_CLKCTRL_SYS_CLK_EN0_REG2 HHI_REG_ADDR(CLKCTRL_SYS_CLK_EN0_REG2) +#define CLKCTRL_VID_CLK_CTRL 0x0030 +#define P_CLKCTRL_VID_CLK_CTRL HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL) +#define CLKCTRL_VID_CLK_CTRL2 0x0031 +#define P_CLKCTRL_VID_CLK_CTRL2 HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL2) +#define CLKCTRL_VID_CLK_DIV 0x0032 +#define P_CLKCTRL_VID_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_CLK_DIV) +#define CLKCTRL_HDMI_CLK_CTRL 0x0038 +#define P_CLKCTRL_HDMI_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDMI_CLK_CTRL) +#define CLKCTRL_VID_PLL_CLK_DIV 0x0039 +#define P_CLKCTRL_VID_PLL_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_PLL_CLK_DIV) +#define CLKCTRL_HDCP22_CLK_CTRL 0x0040 +#define P_CLKCTRL_HDCP22_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDCP22_CLK_CTRL) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe002000 */ +#define RESETCTRL_RESET0 0x0000 +#define P_RESETCTRL_RESET0 RESETCTRL_REG_ADDR(RESETCTRL_RESET0) +#define RESETCTRL_RESET2 0x0002 +#define P_RESETCTRL_RESET2 RESETCTRL_REG_ADDR(RESETCTRL_RESET2) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 */ +#define ANACTRL_HDMIPLL_CTRL0 0x0070 +#define P_ANACTRL_HDMIPLL_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL0) +#define ANACTRL_HDMIPLL_CTRL1 0x0071 +#define P_ANACTRL_HDMIPLL_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL1) +#define ANACTRL_HDMIPLL_CTRL2 0x0072 +#define P_ANACTRL_HDMIPLL_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL2) +#define ANACTRL_HDMIPLL_CTRL3 0x0073 +#define P_ANACTRL_HDMIPLL_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL3) +#define ANACTRL_HDMIPLL_CTRL4 0x0074 +#define P_ANACTRL_HDMIPLL_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL4) +#define ANACTRL_HDMIPLL_CTRL5 0x0075 +#define P_ANACTRL_HDMIPLL_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL5) +#define ANACTRL_HDMIPLL_CTRL6 0x0076 +#define P_ANACTRL_HDMIPLL_CTRL6 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL6) +#define ANACTRL_HDMIPLL_STS 0x0077 +#define P_ANACTRL_HDMIPLL_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_STS) +#define ANACTRL_HDMIPLL_VLOCK 0x0079 +#define P_ANACTRL_HDMIPLL_VLOCK ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_VLOCK) +#define ANACTRL_HDMIPHY_CTRL0 0x0080 +#define P_ANACTRL_HDMIPHY_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL0) +#define ANACTRL_HDMIPHY_CTRL1 0x0081 +#define P_ANACTRL_HDMIPHY_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL1) +#define ANACTRL_HDMIPHY_CTRL2 0x0082 +#define P_ANACTRL_HDMIPHY_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL2) +#define ANACTRL_HDMIPHY_CTRL3 0x0083 +#define P_ANACTRL_HDMIPHY_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL3) +#define ANACTRL_HDMIPHY_CTRL4 0x0084 +#define P_ANACTRL_HDMIPHY_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL4) +#define ANACTRL_HDMIPHY_CTRL5 0x0085 +#define P_ANACTRL_HDMIPHY_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL5) +#define ANACTRL_HDMIPHY_STS 0x0086 +#define P_ANACTRL_HDMIPHY_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_STS) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000 */ +#define PWRCTRL_MEM_PD11 0x001b +#define P_PWRCTRL_MEM_PD11 PWRCTRL_REG_ADDR(PWRCTRL_MEM_PD11) + +#endif
diff --git a/arch/arm/mach-meson/sc2/mailbox.c b/arch/arm/mach-meson/sc2/mailbox.c new file mode 100644 index 0000000..93cef28 --- /dev/null +++ b/arch/arm/mach-meson/sc2/mailbox.c
@@ -0,0 +1,153 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <common.h> +#include <asm/arch/io.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/mailbox.h> +#include <asm/arch/secure_apb.h> + +#define aml_writel32(value, reg) writel(value, reg) +#define aml_readl32(reg) readl(reg) + + +static inline void mbwrite(uint32_t to, void *from, long count) +{ + int i = 0; + int len = count / 4 + (count % 4); + uint32_t *p = from; + + while (len > 0) { + aml_writel32(p[i], to + (4 * i)); + len--; + i++; + } +} + +static inline void mbclean(uint32_t to, long count) +{ + int i = 0; + int len = count / 4 + (count % 4); + + while (len > 0) { + aml_writel32(0, to + (4 * i)); + len--; + i++; + } +} + +int mhu_get_addr(uint32_t chan, uint32_t *mboxset, uint32_t *mboxsts, + uintptr_t *mboxpl, uint32_t *mboxwr, uint32_t *mboxrd, + uint32_t *mboxirqclr, uint32_t *mboxid) +{ + int ret = 0; + + switch (chan) { + case AOCPU_REE_CHANNEL: + *mboxset = REE2AO_SET_ADDR; + *mboxsts = REE2AO_STS_ADDR; + *mboxwr = REE2AO_WR_ADDR; + *mboxrd = REE2AO_RD_ADDR; + *mboxirqclr = REE2AO_IRQCLR_ADDR; + *mboxid = REE2AO_MBOX_ID; + break; + default: + printf("[BL33]: no support chan 0x%x\n", chan); + ret = -1; + break; + }; + return ret; +} + +void mhu_message_start(uint32_t mboxsts) +{ + /* Make sure any previous command has finished */ + while (aml_readl32(mboxsts) != 0); +} + +void mhu_build_payload(uintptr_t mboxpl, uint32_t mboxwr, void *message, uint32_t size) +{ + if (size > (MHU_PAYLOAD_SIZE - MHU_DATA_OFFSET)) { + printf("bl33: scpi send input size error\n"); + return; + } + if (size == 0) + return; + mbwrite(mboxwr + MHU_DATA_OFFSET, message, size); +} + +void mhu_get_payload(uintptr_t mboxpl, uint32_t mboxwr, void *message, uint32_t size) +{ + if (size > (MHU_PAYLOAD_SIZE - MHU_DATA_OFFSET)) { + printf("bl33: scpi send input size error\n"); + return; + } + if (size == 0) + return; + printf("bl33: scpi no support get revmessage\n"); +} + +void mhu_message_send(uint32_t mboxset, uint32_t command, uint32_t size) +{ + uint32_t mbox_cmd; + mbox_cmd = MHU_CMD_BUILD(command, size + MHU_DATA_OFFSET); + aml_writel32(mbox_cmd, mboxset); +} + +uint32_t mhu_message_wait(uint32_t mboxsts) +{ + /* Wait for response from HIFI */ + uint32_t response; + + while ((response = aml_readl32(mboxsts))); + + return response; +} + +void mhu_message_end(uintptr_t mboxpl, uint32_t mboxwr, uint32_t mboxirqclr, uint32_t mboxid) +{ + mbclean(mboxwr, MHU_PAYLOAD_SIZE); + /* Clear any response we got by writing all ones to the CLEAR register */ + aml_writel32(MHU_ACK_MASK(mboxid), mboxirqclr); +} + +void mhu_init(void) +{ + aml_writel32(0xffffffffu, REE2AO_CLR_ADDR); + printf("[BL33] mhu init done -v2\n"); +} +int scpi_send_data(uint32_t chan, uint32_t command, + void *sendmessage, uint32_t sendsize, + void *revmessage, uint32_t revsize) +{ + uint32_t mboxset = 0; + uint32_t mboxsts = 0; + uintptr_t mboxpl = 0; + uint32_t mboxwr = 0; + uint32_t mboxrd = 0; + uint32_t mboxirq = 0; + uint32_t mboxid = 0; + int ret = 0; + + ret = mhu_get_addr(chan, &mboxset, &mboxsts, + &mboxpl, &mboxwr, &mboxrd, + &mboxirq, &mboxid); + if (ret) { + printf("bl33: mhu get addr fail\n"); + return ret; + } + mhu_message_start(mboxsts); + if (sendmessage != NULL && sendsize != 0) + mhu_build_payload(mboxpl, mboxwr, sendmessage, sendsize); + mhu_message_send(mboxset, command, sendsize); + mhu_message_wait(mboxsts); + if (revmessage != NULL && revsize != 0) + mhu_get_payload(mboxpl, mboxrd, revmessage, revsize); + mhu_message_end(mboxpl, mboxwr, mboxirq, mboxid); + return ret; +} +
diff --git a/arch/arm/mach-meson/sc2/oscring.c b/arch/arm/mach-meson/sc2/oscring.c new file mode 100644 index 0000000..de7fa03 --- /dev/null +++ b/arch/arm/mach-meson/sc2/oscring.c
@@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <common.h> +#include <asm/arch/io.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/clock.h> +#include <asm/arch/oscring.h> + +void ring_powerinit(void) +{ + writel(0x18000a, RING_PWM_VCCK);/*set vcck 0.8v*/ + writel(0x90009, RING_PWM_EE);/*set ee 0.8v*/ +} + +unsigned long clk_util_ring_msr(unsigned long clk_mux) +{ + unsigned int regval = 0; + + writel(0, MSR_CLK_REG0); + /* Set the measurement gate to 64uS */ + /* 64uS is enough for measure the frequence? */ + setbits_le32(MSR_CLK_REG0, (10000 - 1)); + /* Disable continuous measurement */ + /* Disable interrupts */ + clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18)); + clrbits_le32(MSR_CLK_REG0, 0x7f << 20); + setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16)); + mdelay(10); + /* Wait for the measurement to be done */ + regval = readl(MSR_CLK_REG0); + do { + regval = readl(MSR_CLK_REG0); + } while (regval & (1 << 31)); + + /* Disable measuring */ + clrbits_le32(MSR_CLK_REG0, 1 << 16); + regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff; + + return (regval / 10); +} + +int ring_msr(int index) +{ + const char* clk_table[] = { + [17] = "dspa_osc_ring(SVT16) " , + [16] = "axi_sram_osc_ring(SVT16) " , + [15] = "sys_cpu_osc_ring3(LVT16) " , + [14] = "sys_cpu_osc_ring2(ULVT16) " , + [13] = "sys_cpu_osc_ring1(ULVT20) " , + [12] = "sys_cpu_osc_ring0(ULVT16) " , + [11] = "ddr_osc_ring(LVT16) " , + [10] = "dos_osc_ring3(ULVT20) " , + [9] = "dos_osc_ring2(LVT16) " , + [8] = "dos_osc_ring1(SVT16) " , + [7] = "dos_osc_ring0(SVT24) " , + [6] = "vpu_osc_ring2(LVT16) " , + [5] = "vpu_osc_ring1(LVT20) " , + [4] = "vpu_osc_ring0(SVT24) " , + [3] = "gpu_osc_ring2(SVT16) " , + [2] = "gpu_osc_ring1(ULVT16) " , + [1] = "gpu_osc_ring0(LVT16) " , + [0] = "dmc_osc_ring(LVT16) " , + }; + const int tb[] = {180, 181, 182, 183, 184, 185, 186, 187, 188, 189, + 190, 191, 192, 193, 194, 195, 196, 197}; + unsigned long i; + uint8_t efuseinfo[4] = {0, 0, 0, 0}; + + if ((index != 0xff) && (index != 0)) { + if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) { + printf("fail get efuse info\n"); + return 0; + } + if ((index >= 1) && (index <= 3)) + printf("%d\n", efuseinfo[index]); + else + printf("input data not support!\n"); + + return 0; + } + if (0xff != index) { + ring_powerinit(); + printf("set vcck vddee to 800mv\n"); + } + /*RING_OSCILLATOR 0x7f: set slow ring*/ + writel(OSCRING_CTL_DATA0, OSCRING_CTL_REG0); + writel(OSCRING_CTL_DATA1, OSCRING_CTL_REG1); + + for (i = 0; i < 18; i++) { + printf("%s :",clk_table[i]); + printf("%ld KHz",clk_util_ring_msr(tb[i])); + printf("\n"); + } + + if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) { + printf("fail get efuse info\n"); + return 0; + } + + printf("osc efuse info:\n"); + for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++) + printf("0x%x, ", efuseinfo[i]); + printf("\n"); + + /*efuse to test value*/ + printf("osc_ring_core0(20lvt), idd_ee, idd_cpu\n"); + + printf("%d KHz ", (efuseinfo[1] * 20)); + + for (i = 2; i <=3; i++) { + printf("%d uA ", (efuseinfo[i] * 400)); + } + printf("\n"); + + return 0; +}
diff --git a/arch/arm/mach-meson/sc2/pinctrl_init.c b/arch/arm/mach-meson/sc2/pinctrl_init.c new file mode 100644 index 0000000..829ce28 --- /dev/null +++ b/arch/arm/mach-meson/sc2/pinctrl_init.c
@@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <dm/uclass.h> +#include <linux/err.h> +#include <asm/arch/pinctrl_init.h> + +int pinctrl_devices_active(int pinctrl_num) +{ + int ret; + int idx; + struct udevice *pinctrl; + + for (idx = 0; idx < pinctrl_num; idx++) { + ret = uclass_get_device(UCLASS_PINCTRL, idx, &pinctrl); + if (ret) { + debug("%s: failed to active pinctrl device [%d]", + __func__, idx); + return -EINVAL; + } + } + + return 0; +}
diff --git a/arch/arm/mach-meson/sc2/pll.c b/arch/arm/mach-meson/sc2/pll.c new file mode 100644 index 0000000..29b1b9e --- /dev/null +++ b/arch/arm/mach-meson/sc2/pll.c
@@ -0,0 +1,962 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/timer.h> +#include <asm/arch/pll.h> +#include <linux/arm-smccc.h> + +#define STR_PLL_TEST_ALL "all" +#define STR_PLL_TEST_SYS "sys" +#define STR_PLL_TEST_FIX "fix" +#define STR_PLL_TEST_DDR "ddr" +#define STR_PLL_TEST_HDMI "hdmi" +#define STR_PLL_TEST_GP0 "gp0" +#define STR_PLL_TEST_GP1 "gp1" +#define STR_PLL_TEST_HIFI "hifi" +#define STR_PLL_TEST_PCIE "pcie" +#define STR_PLL_TEST_ETHPHY "ethphy" +#define STR_PLL_TEST_USBPHY "usbphy" + + +#define PLL_LOCK_CHECK_MAX 3 + +#define RET_PLL_LOCK_FAIL 0x1000 +#define RET_CLK_NOT_MATCH 0x1 +#define SYS_PLL_DIV16_CNTL (1 << 24) +#define SYS_CLK_DIV16_CNTL (1 << 1) +#define SYS_PLL_TEST_DIV 4 /* div16 */ +#define HDMI_PLL_DIV_CNTL (1 << 18) +#define HDMI_PLL_DIV_GATE (1 << 19) + +#define PLL_DIV16_OFFSET 4 /* div2/2/4 */ + +#define RW_CPUCTRL_SYS_CPU_CLK 0 +#define SYS_PLL 1 +#define RW_CPUCTRL_SYS_CPU_CLK5 2 +#define GP1_PLL 3 + +extern unsigned long clk_util_clk_msr(unsigned long clk_mux); + +gp0_pll_cfg_t gp0_pll_cfg = { + .gp0_pll[0] = { + .pll_clk = 6000, /* MHz */ + .pll_cntl0 = 0x080304fa, + .pll_cntl1 = 0x00000000, + .pll_cntl2 = 0x00000000, + .pll_cntl3 = 0x48681c00, + .pll_cntl4 = 0x88770290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x56540000 + }, + .gp0_pll[1] = { + .pll_clk = 3000, /* MHz */ + .pll_cntl0 = 0X0803047d, + .pll_cntl1 = 0x00006aab, + .pll_cntl2 = 0x00000000, + .pll_cntl3 = 0x6a295c00, + .pll_cntl4 = 0x65771290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x54540000 + }, +}; + +gp1_pll_cfg_t gp1_pll_cfg = { + .gp1_pll[0] = { + .pll_clk = 6000, /* MHz */ + .pll_cntl0 = 0x080304fa, + .pll_cntl1 = 0x00000000, + .pll_cntl2 = 0x00000000, + .pll_cntl3 = 0x48681c00, + .pll_cntl4 = 0x88770290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x56540000 + }, + .gp1_pll[1] = { + .pll_clk = 3000, /* MHz */ + .pll_cntl0 = 0X0803047d, + .pll_cntl1 = 0x00006aab, + .pll_cntl2 = 0x00000000, + .pll_cntl3 = 0x6a295c00, + .pll_cntl4 = 0x65771290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x54540000 + }, +}; + +hdmi_pll_cfg_t hdmi_pll_cfg = { + .hdmi_pll[0] = { + .pll_clk = 5940, /* MHz */ + .pll_cntl0 = 0x0b3004f7, + .pll_cntl1 = 0x00010000, + .pll_cntl2 = 0x00000000, + .pll_cntl3 = 0x6a28dc00, + .pll_cntl4 = 0x65771290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x56540000 + }, + .hdmi_pll[1] = { + .pll_clk = 2970, + .pll_cntl0 = 0x0b00047b, + .pll_cntl1 = 0x00018000, + .pll_cntl2 = 0x00000000, + .pll_cntl3 = 0x6a29dc00, + .pll_cntl4 = 0x65771290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x54540000 + }, +}; + +uint32_t sys_pll_clk[] = {6000, 3000}; +sys_pll_cfg_t sys_pll_cfg = { + .sys_pll[0] = { + .cpu_clk = 6000, + .pll_cntl = 0X080004fa, + .pll_cntl1 = 0x0, + .pll_cntl2 = 0x0, + .pll_cntl3 = 0x48681c00, + .pll_cntl4 = 0x88770290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x56540000 + }, + + .sys_pll[1] = { + .cpu_clk = 3000, + .pll_cntl = 0X0800047d, + .pll_cntl1 = 0x0, + .pll_cntl2 = 0x0, + .pll_cntl3 = 0x48681c00, + .pll_cntl4 = 0x88770290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x56540000 + }, +}; + +hifi_pll_cfg_t hifi_pll_cfg = { + .hifi_pll[0] = { + .pll_clk = 6005, + .pll_cntl0 = 0X080304fa, + .pll_cntl1 = 0X00006aab, + .pll_cntl2 = 0x0, + .pll_cntl3 = 0x6a285c00, + .pll_cntl4 = 0x65771290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x56540000 + }, + + .hifi_pll[1] = { + .pll_clk = 3000, + .pll_cntl0 = 0X0803047d, + .pll_cntl1 = 0X00006aab, + .pll_cntl2 = 0x0, + .pll_cntl3 = 0x6a295c00, + .pll_cntl4 = 0x65771290, + .pll_cntl5 = 0x39272000, + .pll_cntl6 = 0x54540000 + }, +}; + +/*PCIE clk_out = 24M*m/2^(n+1)/OD*/ +static const struct pciepll_rate_table pcie_pll_rate_table[] = { + PLL_RATE(4800, 200, 1, 12), +}; + +static void pll_report(unsigned int flag, char * name) +{ + if (flag) + printf("%s pll test failed!\n", name); + else + printf("%s pll test pass!\n", name); + return; +} + +static int clk_around(unsigned int clk, unsigned int cmp) +{ + if (cmp == 1) + cmp += 1; + if (((cmp-2) <= clk) && (clk <= (cmp+2))) + return 1; + else + return 0; +} + +static void clocks_set_sys_cpu_clk(uint32_t freq) +{ + struct arm_smccc_res res; + + arm_smccc_smc(0x8200009C, RW_CPUCTRL_SYS_CPU_CLK, freq, 0, 0, 0, + 0, 0, &res); +} + +static int sys_pll_init(sys_pll_set_t * sys_pll_set) +{ + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int lock_timeout = 0; + struct arm_smccc_res res; + + do { + arm_smccc_smc(0x8200009C, SYS_PLL, sys_pll_set->pll_cntl, 0, + 0, 0, 0, 0, &res); + //Wr(ANACTRL_SYSPLL_CTRL0, sys_pll_set->pll_cntl); + //Wr(ANACTRL_SYSPLL_CTRL0, sys_pll_set->pll_cntl | (3 << 28)); + //Wr(ANACTRL_SYSPLL_CTRL1, sys_pll_set->pll_cntl1); + //Wr(ANACTRL_SYSPLL_CTRL2, sys_pll_set->pll_cntl2); + //Wr(ANACTRL_SYSPLL_CTRL3, sys_pll_set->pll_cntl3); + //Wr(ANACTRL_SYSPLL_CTRL4, sys_pll_set->pll_cntl4); + //Wr(ANACTRL_SYSPLL_CTRL5, sys_pll_set->pll_cntl5); + //Wr(ANACTRL_SYSPLL_CTRL6, sys_pll_set->pll_cntl6); + //Wr(ANACTRL_SYSPLL_CTRL0, ((1<<29) | Rd(HHI_SYS_PLL_CNTL0))); + //Wr(ANACTRL_SYSPLL_CTRL0, Rd(HHI_SYS_PLL_CNTL0)&(~(1<<29))); + lock_timeout = 200; + do { + _udelay(2); + } while ((!((readl(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) && + --lock_timeout); + } while((!((readl(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) && --lock_check); + + if (lock_check != 0) + return 0; + else + return RET_PLL_LOCK_FAIL; +} + +static int sys_pll_test(sys_pll_set_t * sys_pll_set) +{ + unsigned int clk_msr_val = 0; + unsigned int sys_clk = 0; + sys_pll_set_t sys_pll; + int ret = 0; + + /* switch sys clk to oscillator */ + clocks_set_sys_cpu_clk(0); + + /* store current sys pll cntl */ + sys_pll.pll_cntl = readl(ANACTRL_SYSPLL_CTRL0); + sys_pll.pll_cntl1 = readl(ANACTRL_SYSPLL_CTRL1); + sys_pll.pll_cntl2 = readl(ANACTRL_SYSPLL_CTRL2); + sys_pll.pll_cntl3 = readl(ANACTRL_SYSPLL_CTRL3); + sys_pll.pll_cntl4 = readl(ANACTRL_SYSPLL_CTRL4); + sys_pll.pll_cntl5 = readl(ANACTRL_SYSPLL_CTRL5); + sys_pll.pll_cntl6 = readl(ANACTRL_SYSPLL_CTRL6); + + if (sys_pll_set->cpu_clk == 0) { + sys_clk = (24 / ((sys_pll_set->pll_cntl >> 10) & 0x1F) * + (sys_pll_set->pll_cntl & 0x1FF)) >> + ((sys_pll_set->pll_cntl >> 16) & 0x3); + } else { + sys_clk = sys_pll_set->cpu_clk; + } + + if (0 == sys_pll_set->pll_cntl) { + printf("sys pll cntl equal NULL, skip\n"); + return -1; + } + + /* test sys pll */ + ret = sys_pll_init(sys_pll_set); + _udelay(5); + if (ret) { + printf("SYS pll lock Failed! - %4d MHz\n", sys_clk); + } else { + printf("SYS pll lock OK! - %4d MHz. Div16 - %4d MHz. ", + sys_clk, sys_clk >> PLL_DIV16_OFFSET); + clk_msr_val = clk_util_clk_msr(23); + printf("CLKMSR(23) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, sys_clk >> SYS_PLL_TEST_DIV)) { + /* sys clk/pll div16 */ + printf(": Match\n"); + } else { + ret = RET_CLK_NOT_MATCH; + printf(": MisMatch\n"); + } + } + + /* restore sys pll */ + sys_pll_init(&sys_pll); + clocks_set_sys_cpu_clk(1); + + return ret; +} + +static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg) +{ + unsigned int i = 0; + int ret = 0; + + for (i = 0; i < (sizeof(sys_pll_cfg_t) / sizeof(sys_pll_set_t)); i++) + ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i])); + return ret; +} + +static void set_dsu_clk(uint32_t flag) +{ + struct arm_smccc_res res; + + arm_smccc_smc(0x8200009C, RW_CPUCTRL_SYS_CPU_CLK5, flag, 0, 0, 0, + 0, 0, &res); +} + +static int gp1_pll_init(gp1_pll_set_t * gp1_pll_set) +{ + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int lock_timeout = 0; + struct arm_smccc_res res; + + do { + arm_smccc_smc(0x8200009C, GP1_PLL, gp1_pll_set->pll_cntl0, + gp1_pll_set->pll_cntl3, gp1_pll_set->pll_cntl4, + 0, 0, 0, &res); + lock_timeout = 200; + do { + _udelay(2); + } while ((!((readl(ANACTRL_GP1PLL_STS) >> 31) & 0x1)) && + --lock_timeout); + } while((!((readl(ANACTRL_GP1PLL_STS) >> 31) & 0x1)) && --lock_check); + + if (lock_check != 0) + return 0; + else + return RET_PLL_LOCK_FAIL; +} + +static int gp1_pll_test(gp1_pll_set_t * gp1_pll_set) +{ + unsigned int clk_msr_val = 0, od = 0; + unsigned int pll_clk = 0; + gp1_pll_set_t gp1_pll; + int ret = 0; + + od = (gp1_pll_set->pll_cntl0 >> 16) & 0x7; + /* switch dsu clk to oscillator */ + set_dsu_clk(0); + + /* store current gp1 pll cntl */ + gp1_pll.pll_cntl0 = readl(ANACTRL_GP1PLL_CTRL0); + gp1_pll.pll_cntl1 = readl(ANACTRL_GP1PLL_CTRL1); + gp1_pll.pll_cntl2 = readl(ANACTRL_GP1PLL_CTRL2); + gp1_pll.pll_cntl3 = readl(ANACTRL_GP1PLL_CTRL3); + gp1_pll.pll_cntl4 = readl(ANACTRL_GP1PLL_CTRL4); + gp1_pll.pll_cntl5 = readl(ANACTRL_GP1PLL_CTRL5); + gp1_pll.pll_cntl6 = readl(ANACTRL_GP1PLL_CTRL6); + + if (gp1_pll_set->pll_clk == 0) { + pll_clk = (24 / ((gp1_pll_set->pll_cntl0 >> 10) & 0x1F) * + (gp1_pll_set->pll_cntl0 & 0x1FF)); + } else { + pll_clk = gp1_pll_set->pll_clk; + } + + if (0 == gp1_pll_set->pll_cntl0) { + printf("gp1 pll cntl equal NULL, skip\n"); + return -1; + } + + /* test gp1 pll */ + ret = gp1_pll_init(gp1_pll_set); + _udelay(5); + if (ret) { + printf("GP1 pll lock Failed! - %4d MHz\n", pll_clk); + } else { + printf("GP1 pll lock OK! - %4d MHz>>%d - %4d MHz. ", + pll_clk, od, pll_clk >> od); + clk_msr_val = clk_util_clk_msr(21); + printf("CLKMSR(21) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk >> od)) { + printf(": Match\n"); + } else { + ret = RET_CLK_NOT_MATCH; + printf(": MisMatch\n"); + } + } + + /* restore gp1 pll */ + gp1_pll_init(&gp1_pll); + set_dsu_clk(1); + + return ret; +} + +static int gp1_pll_test_all(gp1_pll_cfg_t * gp1_pll_cfg) +{ + unsigned int i = 0; + int ret = 0; + + for (i = 0; i < (sizeof(gp1_pll_cfg_t) / sizeof(gp1_pll_set_t)); i++) + ret += gp1_pll_test(&(gp1_pll_cfg->gp1_pll[i])); + return ret; +} + +static int fix_pll_test(void) +{ + return 0; +} + +static int ddr_pll_test(void) +{ + return 0; +} + +static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll) +{ + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + + do { + writel(hdmi_pll->pll_cntl0, ANACTRL_HDMIPLL_CTRL0); + writel(hdmi_pll->pll_cntl0 | (3 << 28), ANACTRL_HDMIPLL_CTRL0); + writel(hdmi_pll->pll_cntl1, ANACTRL_HDMIPLL_CTRL1); + writel(hdmi_pll->pll_cntl2, ANACTRL_HDMIPLL_CTRL2); + writel(hdmi_pll->pll_cntl3, ANACTRL_HDMIPLL_CTRL3); + writel(hdmi_pll->pll_cntl4, ANACTRL_HDMIPLL_CTRL4); + writel(hdmi_pll->pll_cntl5, ANACTRL_HDMIPLL_CTRL5); + writel(hdmi_pll->pll_cntl6, ANACTRL_HDMIPLL_CTRL6); + + writel(readl(ANACTRL_HDMIPLL_CTRL0) | (1 << 29), + ANACTRL_HDMIPLL_CTRL0); + _udelay(10); + writel(readl(ANACTRL_HDMIPLL_CTRL0) & (~(1 << 29)), + ANACTRL_HDMIPLL_CTRL0); + _udelay(100); + } while ((!(0x3==((readl(ANACTRL_HDMIPLL_STS) >> 30) & 0x3))) && + --lock_check); + if (lock_check != 0) + return 0; + else + return RET_PLL_LOCK_FAIL; +} + +static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set) +{ + unsigned int pll_clk = 0 , od = 0; + unsigned int pll_clk_div = 0; + unsigned int clk_msr_val = 0; + unsigned int clk_msr_reg = 0; + int ret = 0; + + /* store pll div setting */ + clk_msr_reg = readl(CLKCTRL_VID_PLL_CLK_DIV); + /* connect vid_pll_div to HDMIPLL directly */ + clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 19); + clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15); + + /* div14 */ + clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 18); + clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x3 << 16); + clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15); + clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x7fff); + setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 16); + setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15); + setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x3f80); + clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15); + + setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 19); + + /* test pll */ + if (hdmi_pll_set->pll_clk == 0) + pll_clk = ((24 * (hdmi_pll_set->pll_cntl0 & 0xff)) / + ((hdmi_pll_set->pll_cntl0 >> 10) & 0x1f)); + else + pll_clk = hdmi_pll_set->pll_clk; + + _udelay(10); + ret = hdmi_pll_init(hdmi_pll_set); + if (ret) { + printf("HDMI pll lock Failed! - %4d MHz\n", pll_clk); + } else { + od = (hdmi_pll_set->pll_cntl0 >> 20) & 0x3; + pll_clk_div = (pll_clk >>od) / 14; + printf("HDMI pll lock OK! - %4d MHz>>%d and Div14 - %4d MHz. ", + pll_clk, od, pll_clk_div); + /* get [ 55][1485 MHz] vid_pll_div_clk_out */ + clk_msr_val = clk_util_clk_msr(50); + printf("CLKMSR(50) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk_div)) { + printf(": Match\n"); + } else { + ret = RET_CLK_NOT_MATCH; + printf(": MisMatch\n"); + } + } + + /* restore pll */ + /* restore div cntl bit */ + writel(clk_msr_reg, CLKCTRL_VID_PLL_CLK_DIV); + + return ret; +} + +static int hdmi_pll_test_all(hdmi_pll_cfg_t * hdmi_pll_cfg) +{ + unsigned int i = 0; + int ret = 0; + + for (i = 0; i < (sizeof(hdmi_pll_cfg_t) / sizeof(hdmi_pll_set_t)); i++) + ret += hdmi_pll_test(&(hdmi_pll_cfg->hdmi_pll[i])); + return ret; +} + +static int gp0_pll_test(gp0_pll_set_t * gp0_pll) +{ + unsigned int pll_clk = 0; + int ret = 0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0, od = 0; + + od = (gp0_pll->pll_cntl0 >> 16) & 0x7; + + if (gp0_pll->pll_clk == 0) + pll_clk = (24 / ((gp0_pll->pll_cntl0 >> 10) & 0x1F) * + (gp0_pll->pll_cntl0 & 0x1FF)); + else + pll_clk = gp0_pll->pll_clk; + + do { + writel(gp0_pll->pll_cntl0, ANACTRL_GP0PLL_CTRL0); + writel(gp0_pll->pll_cntl0 | (3 << 28), ANACTRL_GP0PLL_CTRL0); + writel(gp0_pll->pll_cntl1, ANACTRL_GP0PLL_CTRL1); + writel(gp0_pll->pll_cntl2, ANACTRL_GP0PLL_CTRL2); + writel(gp0_pll->pll_cntl3, ANACTRL_GP0PLL_CTRL3); + writel(gp0_pll->pll_cntl4, ANACTRL_GP0PLL_CTRL4); + writel(gp0_pll->pll_cntl5, ANACTRL_GP0PLL_CTRL5); + writel(gp0_pll->pll_cntl6, ANACTRL_GP0PLL_CTRL6); + + writel(readl(ANACTRL_GP0PLL_CTRL0) | (1 << 29), + ANACTRL_GP0PLL_CTRL0); + _udelay(10); + writel(readl(ANACTRL_GP0PLL_CTRL0) & (~(1 << 29)), + ANACTRL_GP0PLL_CTRL0); + _udelay(100); + } while ((!((readl(ANACTRL_GP0PLL_STS) >> 31) & 0x1)) && --lock_check); + + if (0 == lock_check) { + printf("GP0 pll lock Failed! - %4d MHz\n", pll_clk); + ret = RET_PLL_LOCK_FAIL; + } else { + printf("GP0 pll lock OK! - %4d MHz >>%d - %4d MHz. ", + pll_clk, od, pll_clk >> od); + /* get gp0_pll_clk */ + clk_msr_val = clk_util_clk_msr(20); + printf("CLKMSR(20) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk >> od)) { + printf(": Match\n"); + } else { + printf(": MisMatch\n"); + ret = RET_CLK_NOT_MATCH; + } + } + return ret; +} + +static int gp0_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg) +{ + unsigned int i = 0; + int ret = 0; + for (i = 0; i < (sizeof(gp0_pll_cfg_t) / sizeof(gp0_pll_set_t)); i++) + ret += gp0_pll_test(&(gp0_pll_cfg->gp0_pll[i])); + return ret; +} + +static int hifi_pll_test(hifi_pll_set_t * hifi_pll) +{ + unsigned int pll_clk = 0; + int ret = 0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0, od = 0; + + od = (hifi_pll->pll_cntl0 >> 16) & 0x3; + + if (hifi_pll->pll_clk == 0) + pll_clk = (24 / ((hifi_pll->pll_cntl0 >> 10) & 0x1F) * + (hifi_pll->pll_cntl0 & 0x1FF)); + else + pll_clk = hifi_pll->pll_clk; + + do { + writel(hifi_pll->pll_cntl0, ANACTRL_HIFIPLL_CTRL0); + writel(hifi_pll->pll_cntl0 | (3 << 28), ANACTRL_HIFIPLL_CTRL0); + writel(hifi_pll->pll_cntl1, ANACTRL_HIFIPLL_CTRL1); + writel(hifi_pll->pll_cntl2, ANACTRL_HIFIPLL_CTRL2); + writel(hifi_pll->pll_cntl3, ANACTRL_HIFIPLL_CTRL3); + writel(hifi_pll->pll_cntl4, ANACTRL_HIFIPLL_CTRL4); + writel(hifi_pll->pll_cntl5, ANACTRL_HIFIPLL_CTRL5); + writel(hifi_pll->pll_cntl6, ANACTRL_HIFIPLL_CTRL6); + writel(readl(ANACTRL_HIFIPLL_CTRL0) | (1 << 29), + ANACTRL_HIFIPLL_CTRL0); + _udelay(10); + writel(readl(ANACTRL_HIFIPLL_CTRL0)&(~(1 << 29)), + ANACTRL_HIFIPLL_CTRL0); + _udelay(100); + } while ((!((readl(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) && + --lock_check); + if (0 == lock_check) { + printf("HIFI pll lock Failed! - %4d MHz\n", pll_clk); + ret = RET_PLL_LOCK_FAIL; + } else { + printf("HIFI pll lock OK! - %4d MHz.Div8 - %4d MHz.", + pll_clk, pll_clk >> od); + /* get hifi_pll_clk */ + clk_msr_val = clk_util_clk_msr(19); + printf("CLKMSR(19) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk >> od)) { + printf(": Match\n"); + } else { + printf(": MisMatch\n"); + ret = RET_CLK_NOT_MATCH; + } + } + return ret; +} + +static int hifi_pll_test_all(hifi_pll_cfg_t * hifi_pll_cfg) +{ + unsigned int i = 0; + int ret = 0; + + for (i = 0; i < (sizeof(hifi_pll_cfg_t) / sizeof(hifi_pll_set_t)); i++) + ret += hifi_pll_test(&(hifi_pll_cfg->hifi_pll[i])); + return ret; +} + +static int pcie_pll_test(pcie_pll_set_t * pcie_pll) +{ + int ret = 0; + unsigned int i = 0, pll_clk = 0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0; + + for (i = 0; i < (sizeof(pcie_pll_rate_table) / + sizeof(pcie_pll_rate_table[0])); i++) { + if ((pcie_pll->pll_cntl0 & 0xFF) == + pcie_pll_rate_table[i].m) + pll_clk = pcie_pll_rate_table[i].rate; + } + + do { + writel(pcie_pll->pll_cntl0, ANACTRL_PCIEPLL_CTRL0); + writel(pcie_pll->pll_cntl0 | 0x30000000, + ANACTRL_PCIEPLL_CTRL0); + writel(pcie_pll->pll_cntl1, ANACTRL_PCIEPLL_CTRL1); + writel(pcie_pll->pll_cntl2, ANACTRL_PCIEPLL_CTRL2); + writel(pcie_pll->pll_cntl3, ANACTRL_PCIEPLL_CTRL3); + writel(pcie_pll->pll_cntl4, ANACTRL_PCIEPLL_CTRL4); + writel(pcie_pll->pll_cntl5, ANACTRL_PCIEPLL_CTRL5); + writel(pcie_pll->pll_cntl5 | 0x68, ANACTRL_PCIEPLL_CTRL5); + _udelay(20); + writel(pcie_pll->pll_cntl4 | 0x00800000, + ANACTRL_PCIEPLL_CTRL4); + _udelay(10); + writel(pcie_pll->pll_cntl0 | 0x34000000, + ANACTRL_PCIEPLL_CTRL0); + writel(((pcie_pll->pll_cntl0 & (~(1 << 29))) | (1 << 26)) | + (1 << 28), ANACTRL_PCIEPLL_CTRL0); + _udelay(10); + writel(pcie_pll->pll_cntl2 & (~(1 << 8)), + ANACTRL_PCIEPLL_CTRL2); + _udelay(10); + } while ((!((readl(ANACTRL_PCIEPLL_STS) >> 31) & 0x1)) && + --lock_check); + if (0 == lock_check) { + printf("PCIE pll lock Failed! - %4d MHz\n", pll_clk); + ret = RET_PLL_LOCK_FAIL; + } else { + printf("PCIE pll lock OK! - %4d MHz.Div48 - %4d MHz. ", + pll_clk, pll_clk / 48); + /* get pcie_pll_clk */ + clk_msr_val = clk_util_clk_msr(16); + printf("CLKMSR(16) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, pll_clk / 48)) { + printf(": Match\n"); + } else { + printf(": MisMatch\n"); + ret = RET_CLK_NOT_MATCH; + } + } + + return ret; +} + +static int pcie_pll_test_all(void) +{ + unsigned int i = 0; + unsigned int lock_check = PLL_LOCK_CHECK_MAX; + unsigned int clk_msr_val = 0; + int ret = 0; + + do { + writel(0x200c04c8, ANACTRL_PCIEPLL_CTRL0); + writel(0x300c04c8, ANACTRL_PCIEPLL_CTRL0); + writel(0x30000000, ANACTRL_PCIEPLL_CTRL1); + writel(0x00001100, ANACTRL_PCIEPLL_CTRL2); + writel(0x10058e00, ANACTRL_PCIEPLL_CTRL3); + writel(0x000100c0, ANACTRL_PCIEPLL_CTRL4); + writel(0x68000048, ANACTRL_PCIEPLL_CTRL5); + writel(0x68000068, ANACTRL_PCIEPLL_CTRL5); + _udelay(20); + writel(0x008100c0, ANACTRL_PCIEPLL_CTRL4); + _udelay(10); + writel(0x340c04c8, ANACTRL_PCIEPLL_CTRL0); + writel(0x140c04c8, ANACTRL_PCIEPLL_CTRL0); + _udelay(10); + writel(0x00001000, ANACTRL_PCIEPLL_CTRL2); + _udelay(10); + } while ((!((readl(ANACTRL_PCIEPLL_STS) >> 31) & 0x1)) && + --lock_check); + + if (0 == lock_check) { + printf("pcie pll lock Failed! - %4d MHz\n", + pcie_pll_rate_table[i].rate); + ret += RET_PLL_LOCK_FAIL; + } else { + printf("pcie pll lock OK! - %4d MHz.Div48 - %4d MHz.", + pcie_pll_rate_table[i].rate, + pcie_pll_rate_table[i].rate / 48); + /* get pcie_pll_clk */ + clk_msr_val = clk_util_clk_msr(16); + printf("CLKMSR(16) - %4d MHz ", clk_msr_val); + if (clk_around(clk_msr_val, + pcie_pll_rate_table[i].rate / 48)) { + printf(": Match\n"); + } else { + printf(": MisMatch\n"); + ret += RET_CLK_NOT_MATCH; + } + } + + return ret; +} + +static int pll_test_all(unsigned char * pll_list) +{ + int ret = 0; + unsigned char i = 0; + + for (i = 0; i < PLL_ENUM; i++) { + switch (pll_list[i]) { + case PLL_SYS: + ret = sys_pll_test_all(&sys_pll_cfg); + pll_report(ret, STR_PLL_TEST_SYS); + break; + case PLL_FIX: + ret = fix_pll_test(); + pll_report(ret, STR_PLL_TEST_FIX); + break; + case PLL_DDR: + ret = ddr_pll_test(); + pll_report(ret, STR_PLL_TEST_DDR); + break; + case PLL_HDMI: + ret = hdmi_pll_test_all(&hdmi_pll_cfg); + pll_report(ret, STR_PLL_TEST_HDMI); + break; + case PLL_GP0: + ret = gp0_pll_test_all(&gp0_pll_cfg); + pll_report(ret, STR_PLL_TEST_GP0); + break; + case PLL_HIFI: + ret = hifi_pll_test_all(&hifi_pll_cfg); + pll_report(ret, STR_PLL_TEST_HIFI); + break; + case PLL_PCIE: + ret = pcie_pll_test_all(); + pll_report(ret, STR_PLL_TEST_PCIE); + break; + case PLL_GP1: + ret = gp1_pll_test_all(&gp1_pll_cfg); + pll_report(ret, STR_PLL_TEST_GP1); + break; + default: + break; + } + } + return ret; +} + +int pll_test(int argc, char * const argv[]) +{ + int ret = 0; + sys_pll_set_t sys_pll_set = {0}; + hdmi_pll_set_t hdmi_pll_set = {0}; + gp0_pll_set_t gp0_pll_set = {0}; + gp1_pll_set_t gp1_pll_set = {0}; + hifi_pll_set_t hifi_pll_set = {0}; + pcie_pll_set_t pcie_pll_set = {0}; + + unsigned char plls[PLL_ENUM] = { + PLL_SYS, + 0xff,// PLL_FIX, //0xff will skip this pll + 0xff,// PLL_DDR, + PLL_HDMI, + PLL_GP0, + PLL_HIFI, + PLL_PCIE, + PLL_GP1, + 0xff,//PLL_USBPHY + }; + + if (0 == strcmp(STR_PLL_TEST_ALL, argv[1])) { + printf("Test all plls\n"); + pll_test_all(plls); + } else if(0 == strcmp(STR_PLL_TEST_SYS, argv[1])) { + if (argc == 2) { + ret = sys_pll_test_all(&sys_pll_cfg); + pll_report(ret, STR_PLL_TEST_SYS); + } else if (argc != 9) { + printf("%s pll test: args error\n", STR_PLL_TEST_SYS); + return -1; + } else { + sys_pll_set.pll_cntl = simple_strtoul(argv[2], NULL, + 16); + sys_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, + 16); + sys_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, + 16); + sys_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, + 16); + sys_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, + 16); + sys_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, + 16); + sys_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, + 16); + ret = sys_pll_test(&sys_pll_set); + pll_report(ret, STR_PLL_TEST_SYS); + } + } else if (0 == strcmp(STR_PLL_TEST_HDMI, argv[1])) { + if (argc == 2) { + ret = hdmi_pll_test_all(&hdmi_pll_cfg); + pll_report(ret, STR_PLL_TEST_HDMI); + } else if (argc != 9) { + printf("%s pll test: args error\n", STR_PLL_TEST_HDMI); + return -1; + } else { + hdmi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, + 16); + hdmi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, + 16); + hdmi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, + 16); + hdmi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, + 16); + hdmi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, + 16); + hdmi_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, + 16); + hdmi_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, + 16); + ret = hdmi_pll_test(&hdmi_pll_set); + pll_report(ret, STR_PLL_TEST_HDMI); + } + } else if (0 == strcmp(STR_PLL_TEST_GP0, argv[1])) { + if (argc == 2) { + ret = gp0_pll_test_all(&gp0_pll_cfg); + pll_report(ret, STR_PLL_TEST_GP0); + } else if (argc != 9) { + printf("%s pll test: args error\n", STR_PLL_TEST_GP0); + return -1; + } else { + gp0_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, + 16); + gp0_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, + 16); + gp0_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, + 16); + gp0_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, + 16); + gp0_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, + 16); + gp0_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, + 16); + gp0_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, + 16); + ret = gp0_pll_test(&gp0_pll_set); + pll_report(ret, STR_PLL_TEST_GP0); + } + } else if (0 == strcmp(STR_PLL_TEST_HIFI, argv[1])) { + if (argc == 2) { + ret = hifi_pll_test_all(&hifi_pll_cfg); + pll_report(ret, STR_PLL_TEST_HIFI); + } else if (argc != 9) { + printf("%s pll test:args error\n", STR_PLL_TEST_HIFI); + return -1; + } else { + hifi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, + 16); + hifi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, + 16); + hifi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, + 16); + hifi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, + 16); + hifi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, + 16); + hifi_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, + 16); + hifi_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, + 16); + ret = hifi_pll_test(&hifi_pll_set); + pll_report(ret, STR_PLL_TEST_HIFI); + } + } else if (0 == strcmp(STR_PLL_TEST_PCIE, argv[1])) { + if (argc == 2) { + ret = pcie_pll_test_all(); + pll_report(ret, STR_PLL_TEST_PCIE); + } else if (argc != 8) { + printf("%s pll test: args error\n", STR_PLL_TEST_PCIE); + return -1; + } else { + pcie_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, + 16); + pcie_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, + 16); + pcie_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, + 16); + pcie_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, + 16); + pcie_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, + 16); + pcie_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, + 16); + ret = pcie_pll_test(&pcie_pll_set); + pll_report(ret, STR_PLL_TEST_PCIE); + } + } else if (0 == strcmp(STR_PLL_TEST_GP1, argv[1])) { + if (argc == 2) { + ret = gp1_pll_test_all(&gp1_pll_cfg); + pll_report(ret, STR_PLL_TEST_GP1); + } else if (argc != 9) { + printf("%s pll test: args error\n", STR_PLL_TEST_GP1); + return -1; + } else { + gp1_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, + 16); + gp1_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, + 16); + gp1_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, + 16); + gp1_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, + 16); + gp1_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, + 16); + gp1_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, + 16); + gp1_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, + 16); + ret = gp1_pll_test(&gp1_pll_set); + pll_report(ret, STR_PLL_TEST_GP1); + } + } else if (0 == strcmp(STR_PLL_TEST_DDR, argv[1])) { + printf("%s pll not support now\n", STR_PLL_TEST_DDR); + return -1; + } else if (0 == strcmp(STR_PLL_TEST_FIX, argv[1])) { + printf("%s pll not support now\n", STR_PLL_TEST_FIX); + return -1; + } + + return 0; +}
diff --git a/arch/arm/mach-meson/sc2/power_cal.c b/arch/arm/mach-meson/sc2/power_cal.c new file mode 100644 index 0000000..e4f9c53 --- /dev/null +++ b/arch/arm/mach-meson/sc2/power_cal.c
@@ -0,0 +1,135 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/io.h> +#include <amlogic/saradc.h> +#include <asm/arch/mailbox.h> + +#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2)))) +#define vcck_adc_channel 0x4 +#define ee_adc_channel 0x5 +#define default_ref_val 1800 + +extern const int pwm_cal_voltage_table[][2]; +extern const int pwm_cal_voltage_table_ee[][2]; +extern int pwm_cal_voltage_table_size; +extern int pwm_cal_voltage_table_ee_size; + + +enum pwm_id { + pwm_vcck = 0, + pwm_ee, +}; + +unsigned int _get_time(void) +{ + return P_EE_TIMER_E; +} + +void _udelay_(unsigned int us) +{ + unsigned int t0 = _get_time(); + + while (_get_time() - t0 <= us) + ; +} + +int32_t aml_delt_get(int adc_val, unsigned int voltage) +{ + unsigned int adc_volt; + int32_t delt; + int32_t div = 10; /*10mv is min step*/ + + if (adc_val != -1) { + adc_volt = default_ref_val*adc_val/1024; + printf("aml pwm cal adc_val = %x, adc_voltage = %d, def_voltage = %d\n", + adc_val, adc_volt, voltage); + } else { + adc_volt = voltage; + printf("warning:aml pwm cal adc get voltage error\n"); + return 0; + } + delt = voltage - adc_volt; + delt = delt / div; + return delt; +} + +void aml_set_voltage(unsigned int id, unsigned int voltage, int delt) +{ + int to; + + switch (id) { + case pwm_vcck: + for (to = 0; to < pwm_cal_voltage_table_size; to++) { + if (pwm_cal_voltage_table[to][1] >= voltage) { + break; + } + } + to +=delt; + if (to >= pwm_cal_voltage_table_size) { + to = pwm_cal_voltage_table_size - 1; + } + /*vcck volt set by dvfs and avs*/ + //writel(pwm_voltage_table[to][0], PWM_PWM_A_ADRESS); + _udelay_(200); + break; + + case pwm_ee: + for (to = 0; to < pwm_cal_voltage_table_ee_size; to++) { + if (pwm_cal_voltage_table_ee[to][1] >= voltage) { + break; + } + } + to +=delt; + if (to >= pwm_cal_voltage_table_ee_size) { + to = pwm_cal_voltage_table_ee_size - 1; + } + printf("aml pwm cal before ee_address: %x, ee_voltage: %x\n", + AO_PWM_PWM_B, readl(AO_PWM_PWM_B)); + writel(pwm_cal_voltage_table_ee[to][0],AO_PWM_PWM_B); + _udelay_(1000); + printf("aml pwm cal after ee_address: %x, ee_voltage: %x\n", + AO_PWM_PWM_B, readl(AO_PWM_PWM_B)); + break; + default: + break; + } + _udelay_(200); +} + +int aml_cal_pwm(unsigned int ee_voltage, unsigned int vcck_voltage) +{ + int32_t ee_delt, vcck_delt; + unsigned int ee_val, vcck_val; + int ret; + + /*txlx vcck ch4,vddee ch5*/ + ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION, + vcck_adc_channel, &vcck_val); + if (ret) + return ret; + + ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION, + ee_adc_channel, &ee_val); + if (ret) + return ret; + + vcck_delt = aml_delt_get(vcck_val, vcck_voltage); + ee_delt = aml_delt_get(ee_val, ee_voltage); + send_pwm_delt(vcck_delt, ee_delt); + aml_set_voltage(pwm_ee, AML_VDDEE_INIT_VOLTAGE, ee_delt); + //aml_set_voltage(pwm_vcck, CONFIG_VCCK_INIT_VOLTAGE, vcck_delt); + printf("aml board pwm vcck: %x, ee: %x\n", vcck_delt, ee_delt); + + return 0; +} + +void aml_pwm_cal_init(int mode) +{ + printf("aml pwm cal init\n"); + aml_cal_pwm(AML_VDDEE_INIT_VOLTAGE, AML_VCCK_INIT_VOLTAGE); +}
diff --git a/arch/arm/mach-meson/sc2/power_gate.h b/arch/arm/mach-meson/sc2/power_gate.h new file mode 100644 index 0000000..9ca1a9d --- /dev/null +++ b/arch/arm/mach-meson/sc2/power_gate.h
@@ -0,0 +1,1161 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __POWER_MGR_HEADER_ +#define __POWER_MGR_HEADER_ + +#include <asm/arch/io.h> +#include <common.h> +//#include <asm/arch-gxb/io.h> +/* #include <asm/arch-gxb/register.h> */ +#include <asm/arch/secure_apb.h> +/* clock gate control */ + +#define DEBUG_MASK 0 + +#define SET_CLK_GATE_MASK(reg, mask) __raw_writel((__raw_readl(reg)|mask), reg) +#define CLEAR_CLK_GATE_MASK(reg, mask) \ + __raw_writel((__raw_readl(reg)&(~mask)), reg) +#define CLK_GATE_ON(_MOD) do { \ + if (DEBUG_MASK) \ + printf("on reg %24s before read :0x%x : 0x%x\n",\ + GCLK_NAME_##_MOD, \ + (unsigned int)GCLK_REG_##_MOD, \ + __raw_readl(GCLK_REG_##_MOD)); \ + SET_CLK_GATE_MASK(GCLK_REG_##_MOD, \ + (unsigned int)GCLK_MASK_##_MOD); \ + if (DEBUG_MASK) \ + printf("on reg %24s after read :0x%x : 0x%x\n",\ + GCLK_NAME_##_MOD, \ + (unsigned int)GCLK_REG_##_MOD, \ + __raw_readl(GCLK_REG_##_MOD)); \ + } while (0) + +#define CLK_GATE_OFF(_MOD) do { \ + if (DEBUG_MASK) \ + printf("off reg[ %24s ][0x%08x]before read:0x%08x:0x%08x\n",\ + GCLK_NAME_##_MOD, (int)GCLK_MASK_##_MOD, \ + (unsigned int)GCLK_REG_##_MOD, \ + __raw_readl(GCLK_REG_##_MOD)); \ + CLEAR_CLK_GATE_MASK(GCLK_REG_##_MOD, (unsigned int)GCLK_MASK_##_MOD);\ + if (DEBUG_MASK)\ + printf("off reg[ %24s ][0x%08x] read after:0x%08x:0x%08x\n",\ + GCLK_NAME_##_MOD, \ + (int)GCLK_MASK_##_MOD, \ + (unsigned int)GCLK_REG_##_MOD, \ + __raw_readl(GCLK_REG_##_MOD)); \ + } while (0) + +#define IS_CLK_GATE_ON(_MOD) (__raw_readl(GCLK_REG_##_MOD) & (GCLK_MASK_##_MOD)) +#define GATE_INIT(_MOD) GCLK_ref[GCLK_IDX_##_MOD] = IS_CLK_GATE_ON(_MOD) ? 1 : 0 + +#define GCLK_IDX_DDR 0 +#define GCLK_NAME_DDR "DDR" +#define GCLK_DEV_DDR "CLKGATE_DDR" +#define GCLK_REG_DDR (HHI_GCLK_MPEG0) +#define GCLK_MASK_DDR (1<<0) + +#define GCLK_IDX_DOS 1 +#define GCLK_NAME_DOS "DOS" +#define GCLK_DEV_DOS "CLKGATE_DOS" +#define GCLK_REG_DOS (HHI_GCLK_MPEG0) +#define GCLK_MASK_DOS (1<<1) + +#define GCLK_IDX_RESERVED0_0 2 +#define GCLK_NAME_RESERVED0_0 "RESERVED0_0" +#define GCLK_DEV_RESERVED0_0 "CLKGATE_RESERVED0_0" +#define GCLK_REG_RESERVED0_0 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_0 (1<<2) + +#define GCLK_IDX_RESERVED0_1 3 +#define GCLK_NAME_RESERVED0_1 "RESERVED0_1" +#define GCLK_DEV_RESERVED0_1 "CLKGATE_RESERVED0_1" +#define GCLK_REG_RESERVED0_1 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_1 (1<<3) + +/* #define GCLK_IDX_AHB_BRIDGE 4 */ +/* #define GCLK_NAME_AHB_BRIDGE "AHB_BRIDGE" */ +/* #define GCLK_DEV_AHB_BRIDGE "CLKGATE_AHB_BRIDGE" */ +/* #define GCLK_REG_AHB_BRIDGE (HHI_GCLK_MPEG0) */ +/* #define GCLK_MASK_AHB_BRIDGE (1<<4) */ + +#define GCLK_IDX_ISA 5 +#define GCLK_NAME_ISA "ISA" +#define GCLK_DEV_ISA "CLKGATE_ISA" +#define GCLK_REG_ISA (HHI_GCLK_MPEG0) +#define GCLK_MASK_ISA (1<<5) + +/* NEW ADD */ +#define GCLK_IDX_PL310_CBUS 6 +#define GCLK_NAME_PL310_CBUS "PL310_CBUS" +#define GCLK_DEV_PL310_CBUS "CLKGATE_PL310_CBUS" +#define GCLK_REG_PL310_CBUS (HHI_GCLK_MPEG0) +#define GCLK_MASK_PL310_CBUS (1<<6) + +#define GCLK_IDX_PERIPHS_TOP 7 +#define GCLK_NAME_PERIPHS_TOP "PERIPHS_TOP" +#define GCLK_DEV_PERIPHS_TOP "CLKGATE_PERIPHS_TOP" +#define GCLK_REG_PERIPHS_TOP (HHI_GCLK_MPEG0) +#define GCLK_MASK_PERIPHS_TOP (1<<7) + +#define GCLK_IDX_SPICC 8 +#define GCLK_NAME_SPICC "SPICC" +#define GCLK_DEV_SPICC "CLKGATE_SPICC" +#define GCLK_REG_SPICC (HHI_GCLK_MPEG0) +#define GCLK_MASK_SPICC (1<<8) + +#define GCLK_IDX_I2C 9 +#define GCLK_NAME_I2C "I2C" +#define GCLK_DEV_I2C "CLKGATE_I2C" +#define GCLK_REG_I2C (HHI_GCLK_MPEG0) +#define GCLK_MASK_I2C (1<<9) + +#define GCLK_IDX_SAR_ADC 10 +#define GCLK_NAME_SAR_ADC "SAR_ADC" +#define GCLK_DEV_SAR_ADC "CLKGATE_SAR_ADC" +//#define GCLK_REG_SAR_ADC (HHI_SAR_CLK_CNTL) //no HHI_SAR_CLK_CNTL on TXL +#define GCLK_REG_SAR_ADC (AO_SAR_CLK) +#define GCLK_MASK_SAR_ADC (1<<8) + +#define GCLK_IDX_SMART_CARD_MPEG_DOMAIN 11 +#define GCLK_NAME_SMART_CARD_MPEG_DOMAIN "SMART_CARD_MPEG_DOMAIN" +#define GCLK_DEV_SMART_CARD_MPEG_DOMAIN "CLKGATE_SMART_CARD_MPEG_DOMAIN" +#define GCLK_REG_SMART_CARD_MPEG_DOMAIN (HHI_GCLK_MPEG0) +#define GCLK_MASK_SMART_CARD_MPEG_DOMAIN (1<<11) + +#define GCLK_IDX_RANDOM_NUM_GEN 12 +#define GCLK_NAME_RANDOM_NUM_GEN "RANDOM_NUM_GEN" +#define GCLK_DEV_RANDOM_NUM_GEN "CLKGATE_RANDOM_NUM_GEN" +#define GCLK_REG_RANDOM_NUM_GEN (HHI_GCLK_MPEG0) +#define GCLK_MASK_RANDOM_NUM_GEN (1<<12) + +#define GCLK_IDX_UART0 13 +#define GCLK_NAME_UART0 "UART0" +#define GCLK_DEV_UART0 "CLKGATE_UART0" +#define GCLK_REG_UART0 (HHI_GCLK_MPEG0) +#define GCLK_MASK_UART0 (1<<13) + +/* gxb no this clock gate */ +/* #define GCLK_IDX_SDHC 14 */ +/* #define GCLK_NAME_SDHC "SDHC" */ +/* #define GCLK_DEV_SDHC "CLKGATE_SDHC" */ +/* #define GCLK_REG_SDHC (HHI_GCLK_MPEG0) */ +/* #define GCLK_MASK_SDHC (1<<14) */ + +#define GCLK_IDX_STREAM 15 +#define GCLK_NAME_STREAM "STREAM" +#define GCLK_DEV_STREAM "CLKGATE_STREAM" +#define GCLK_REG_STREAM (HHI_GCLK_MPEG0) +#define GCLK_MASK_STREAM (1<<15) + +#define GCLK_IDX_ASYNC_FIFO 16 +#define GCLK_NAME_ASYNC_FIFO "ASYNC_FIFO" +#define GCLK_DEV_ASYNC_FIFO "CLKGATE_ASYNC_FIFO" +#define GCLK_REG_ASYNC_FIFO (HHI_GCLK_MPEG0) +#define GCLK_MASK_ASYNC_FIFO (1<<16) + +/* gxb no this clock gate */ +/* #define GCLK_IDX_SDIO 17 */ +/* #define GCLK_NAME_SDIO "SDIO" */ +/* #define GCLK_DEV_SDIO "CLKGATE_SDIO" */ +/* #define GCLK_REG_SDIO (HHI_GCLK_MPEG0) */ +/* #define GCLK_MASK_SDIO (1<<17) */ + +/* gxb no this clock gate */ +/* #define GCLK_IDX_AUD_BUF 18 */ +/* #define GCLK_NAME_AUD_BUF "AUD_BUF" */ +/* #define GCLK_DEV_AUD_BUF "CLKGATE_AUD_BUF" */ +/* #define GCLK_REG_AUD_BUF (HHI_GCLK_MPEG0) */ +/* #define GCLK_MASK_AUD_BUF (1<<18) */ + +#define GCLK_IDX_HIU_PARSER 19 +#define GCLK_NAME_HIU_PARSER "HIU_PARSER" +#define GCLK_DEV_HIU_PARSER "CLKGATE_HIU_PARSER" +#define GCLK_REG_HIU_PARSER (HHI_GCLK_MPEG0) +#define GCLK_MASK_HIU_PARSER (1<<19) + +#define GCLK_IDX_RESERVED0_2 20 +#define GCLK_NAME_RESERVED0_2 "RESERVED0_2" +#define GCLK_DEV_RESERVED0_2 "CLKGATE_RESERVED0_2" +#define GCLK_REG_RESERVED0_2 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_2 (1<<20) + +/* NEW ADD */ +#define GCLK_IDX_RESERVED0_3 21 +#define GCLK_NAME_RESERVED0_3 "RESERVED0_3 " +#define GCLK_DEV_RESERVED0_3 "CLKGATE_RESERVED0_3 " +#define GCLK_REG_RESERVED0_3 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_3 (1<<21) + +#define GCLK_IDX_RESERVED0_4 22 +#define GCLK_NAME_RESERVED0_4 "RESERVED0_4" +#define GCLK_DEV_RESERVED0_4 "CLKGATE_RESERVED0_4" +#define GCLK_REG_RESERVED0_4 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_4 (1<<22) + +#define GCLK_IDX_ASSIST_MISC 23 +#define GCLK_NAME_ASSIST_MISC "ASSIST_MISC" +#define GCLK_DEV_ASSIST_MISC "CLKGATE_ASSIST_MISC" +#define GCLK_REG_ASSIST_MISC (HHI_GCLK_MPEG0) +#define GCLK_MASK_ASSIST_MISC (1<<23) + + +#define GCLK_IDX_EMMC_A 24 +#define GCLK_NAME_EMMC_A "EMMC_A" +#define GCLK_DEV_EMMC_A "CLKGATE_EMMC_A" +#define GCLK_REG_EMMC_A (HHI_GCLK_MPEG0) +#define GCLK_MASK_EMMC_A (1<<24) + +#define GCLK_IDX_EMMC_B 25 +#define GCLK_NAME_EMMC_B "EMMC_B" +#define GCLK_DEV_EMMC_B "CLKGATE_EMMC_B" +#define GCLK_REG_EMMC_B (HHI_GCLK_MPEG0) +#define GCLK_MASK_EMMC_B (1<<25) + +#define GCLK_IDX_EMMC_C 26 +#define GCLK_NAME_EMMC_C "EMMC_C" +#define GCLK_DEV_EMMC_C "CLKGATE_EMMC_C" +#define GCLK_REG_EMMC_C (HHI_GCLK_MPEG0) +#define GCLK_MASK_EMMC_C (1<<26) + +#define GCLK_IDX_RESERVED0_8 27 +#define GCLK_NAME_RESERVED0_8 "RESERVED0_8" +#define GCLK_DEV_RESERVED0_8 "CLKGATE_RESERVED0_8" +#define GCLK_REG_RESERVED0_8 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_8 (1<<27) + +#define GCLK_IDX_RESERVED0_9 28 +#define GCLK_NAME_RESERVED0_9 "RESERVED0_9" +#define GCLK_DEV_RESERVED0_9 "CLKGATE_RESERVED0_9" +#define GCLK_REG_RESERVED0_9 (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_9 (1<<28) + +#define GCLK_IDX_RESERVED0_A 29 +#define GCLK_NAME_RESERVED0_A "RESERVED0_A" +#define GCLK_DEV_RESERVED0_A "CLKGATE_RESERVED0_A" +#define GCLK_REG_RESERVED0_A (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_A (1<<29) + +#define GCLK_IDX_SPI 30 +#define GCLK_NAME_SPI "SPI" +#define GCLK_DEV_SPI "CLKGATE_SPI" +#define GCLK_REG_SPI (HHI_GCLK_MPEG0) +#define GCLK_MASK_SPI (1<<30) + +#define GCLK_IDX_RESERVED0_B 31 +#define GCLK_NAME_RESERVED0_B "RESERVED0_B" +#define GCLK_DEV_RESERVED0_B "CLKGATE_RESERVED0_B" +#define GCLK_REG_RESERVED0_B (HHI_GCLK_MPEG0) +#define GCLK_MASK_RESERVED0_B (1<<31) + +/**************************************************************/ + +#define GCLK_IDX_RESERVED1_1 32 +#define GCLK_NAME_RESERVED1_1 "RESERVED1_1" +#define GCLK_DEV_RESERVED1_1 "CLKGATE_RESERVED1_1" +#define GCLK_REG_RESERVED1_1 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_1 (1<<0) + + +#define GCLK_IDX_RESERVED1_2 33 +#define GCLK_NAME_RESERVED1_2 "RESERVED1_2" +#define GCLK_DEV_RESERVED1_2 "CLKGATE_RESERVED1_2" +#define GCLK_REG_RESERVED1_2 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_2 (1<<1) + + +#define GCLK_IDX_AUD_IN 34 +#define GCLK_NAME_AUD_IN "AUD_IN" +#define GCLK_DEV_AUD_IN "CLKGATE_AUD_IN" +#define GCLK_REG_AUD_IN (HHI_GCLK_MPEG1) +#define GCLK_MASK_AUD_IN (1<<2) + +#define GCLK_IDX_ETHERNET 35 +#define GCLK_NAME_ETHERNET "ETHERNET" +#define GCLK_DEV_ETHERNET "CLKGATE_ETHERNET" +#define GCLK_REG_ETHERNET (HHI_GCLK_MPEG1) +#define GCLK_MASK_ETHERNET (1<<3) + +/* g12a no reg */ +#if 0 +#define GCLK_IDX_ETH_CLK 145 +#define GCLK_NAME_ETH_CLK "ETH_CLK" +#define GCLK_REG_ETH_CLK (HHI_MPLL_CNTL10) +#define GCLK_MASK_ETH_CLK (1<<3) +#endif + +#define GCLK_IDX_DEMUX 36 +#define GCLK_NAME_DEMUX "DEMUX" +#define GCLK_DEV_DEMUX "CLKGATE_DEMUX" +#define GCLK_REG_DEMUX (HHI_GCLK_MPEG1) +#define GCLK_MASK_DEMUX (1<<4) + +#define GCLK_IDX_RESERVED1_3 37 +#define GCLK_NAME_RESERVED1_3 "RESERVED1_3" +#define GCLK_DEV_RESERVED1_3 "CLKGATE_RESERVED1_3" +#define GCLK_REG_RESERVED1_3 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_3 (1<<5) + +#define GCLK_IDX_AIU_AI_TOP_GLUE 38 +#define GCLK_NAME_AIU_AI_TOP_GLUE "AIU_AI_TOP_GLUE" +#define GCLK_DEV_AIU_AI_TOP_GLUE "CLKGATE_AIU_AI_TOP_GLUE" +#define GCLK_REG_AIU_AI_TOP_GLUE (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_AI_TOP_GLUE (1<<6) + +#define GCLK_IDX_AIU_IEC958 39 +#define GCLK_NAME_AIU_IEC958 "AIU_IEC958" +#define GCLK_DEV_AIU_IEC958 "CLKGATE_AIU_IEC958" +#define GCLK_REG_AIU_IEC958 (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_IEC958 (1<<7) + +#define GCLK_IDX_AIU_I2S_OUT 40 +#define GCLK_NAME_AIU_I2S_OUT "AIU_I2S_OUT" +#define GCLK_DEV_AIU_I2S_OUT "CLKGATE_AIU_I2S_OUT" +#define GCLK_REG_AIU_I2S_OUT (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_I2S_OUT (1<<8) + +#define GCLK_IDX_AIU_AMCLK_MEASURE 41 +#define GCLK_NAME_AIU_AMCLK_MEASURE "AIU_AMCLK_MEASURE" +#define GCLK_DEV_AIU_AMCLK_MEASURE "CLKGATE_AIU_AMCLK_MEASURE" +#define GCLK_REG_AIU_AMCLK_MEASURE (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_AMCLK_MEASURE (1<<9) + +#define GCLK_IDX_AIU_AIFIFO2 42 +#define GCLK_NAME_AIU_AIFIFO2 "AIU_AIFIFO2" +#define GCLK_DEV_AIU_AIFIFO2 "CLKGATE_AIU_AIFIFO2" +#define GCLK_REG_AIU_AIFIFO2 (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_AIFIFO2 (1<<10) + +#define GCLK_IDX_AIU_AUD_MIXER 43 +#define GCLK_NAME_AIU_AUD_MIXER "AIU_AUD_MIXER" +#define GCLK_DEV_AIU_AUD_MIXER "CLKGATE_AIU_AUD_MIXER" +#define GCLK_REG_AIU_AUD_MIXER (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_AUD_MIXER (1<<11) + +#define GCLK_IDX_AIU_MIXER_REG 44 +#define GCLK_NAME_AIU_MIXER_REG "AIU_MIXER_REG" +#define GCLK_DEV_AIU_MIXER_REG "CLKGATE_AIU_MIXER_REG" +#define GCLK_REG_AIU_MIXER_REG (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_MIXER_REG (1<<12) + +#define GCLK_IDX_AIU_ADC 45 +#define GCLK_NAME_AIU_ADC "AIU_ADC" +#define GCLK_DEV_AIU_ADC "CLKGATE_AIU_ADC" +#define GCLK_REG_AIU_ADC (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_ADC (1<<13) + +#define GCLK_IDX_BLK_MOV 46 +#define GCLK_NAME_BLK_MOV "BLK_MOV" +#define GCLK_DEV_BLK_MOV "CLKGATE_BLK_MOV" +#define GCLK_REG_BLK_MOV (HHI_GCLK_MPEG1) +#define GCLK_MASK_BLK_MOV (1<<14) + +/* NEW ADD */ +#define GCLK_IDX_AIU_TOP_LEVEL 47 +#define GCLK_NAME_AIU_TOP_LEVEL "AIU_TOP_LEVEL" +#define GCLK_DEV_AIU_TOP_LEVEL "CLKGATE_AIU_TOP_LEVEL" +#define GCLK_REG_AIU_TOP_LEVEL (HHI_GCLK_MPEG1) +#define GCLK_MASK_AIU_TOP_LEVEL (1<<15) + +//g12a no reg +#if 0 +#define GCLK_NAME_PCM_MCLK "PCM_MCLK" +#define GCLK_REG_PCM_MCLK (HHI_PCM_CLK_CNTL) +#define GCLK_MASK_PCM_MCLK (1<<9) + +#define GCLK_NAME_PCM_SCLK "PCM_SCLK" +#define GCLK_REG_PCM_SCLK (HHI_PCM_CLK_CNTL) +#define GCLK_MASK_PCM_SCLK (1<<22) +#endif + +#define GCLK_IDX_UART1 48 +#define GCLK_NAME_UART1 "UART1" +#define GCLK_DEV_UART1 "CLKGATE_UART1" +#define GCLK_REG_UART1 (HHI_GCLK_MPEG1) +#define GCLK_MASK_UART1 (1<<16) + +#define GCLK_IDX_RESERVED1_4 49 +#define GCLK_NAME_RESERVED1_4 "RESERVED1_4" +#define GCLK_DEV_RESERVED1_4 "CLKGATE_RESERVED1_4" +#define GCLK_REG_RESERVED1_4 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_4 (1<<17) + +/* NEW ADD */ +#define GCLK_IDX_RESERVED1_5 50 +#define GCLK_NAME_RESERVED1_5 "RESERVED1_5" +#define GCLK_DEV_RESERVED1_5 "CLKGATE_RESERVED1_5" +#define GCLK_REG_RESERVED1_5 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_5 (1<<18) + +#define GCLK_IDX_RESERVED1_6 51 +#define GCLK_NAME_RESERVED1_6 "RESERVED1_6" +#define GCLK_DEV_RESERVED1_6 "CLKGATE_RESERVED1_6" +#define GCLK_REG_RESERVED1_6 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_6 (1<<19) + +#define GCLK_IDX_GE2D 52 +#define GCLK_NAME_GE2D "GE2D" +#define GCLK_DEV_GE2D "CLKGATE_GE2D" +#define GCLK_REG_GE2D (HHI_GCLK_MPEG1) +#define GCLK_MASK_GE2D (1<<20) + +#define GCLK_IDX_USB0 53 +#define GCLK_NAME_USB0 "USB0" +#define GCLK_DEV_USB0 "CLKGATE_USB0" +#define GCLK_REG_USB0 (HHI_GCLK_MPEG1) +#define GCLK_MASK_USB0 (1<<21) + +#define GCLK_IDX_USB1 54 +#define GCLK_NAME_USB1 "USB1" +#define GCLK_DEV_USB1 "CLKGATE_USB1" +#define GCLK_REG_USB1 (HHI_GCLK_MPEG1) +#define GCLK_MASK_USB1 (1<<22) + +#define GCLK_IDX_RESET 55 +#define GCLK_NAME_RESET "RESET" +#define GCLK_DEV_RESET "CLKGATE_RESET" +#define GCLK_REG_RESET (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESET (1<<23) + +#define GCLK_IDX_NAND_CLK 56 +#define GCLK_NAME_NAND_CLK "NAND CLK" +#define GCLK_DEV_NAND_CLK "HHI_NAND_CLK" +#define GCLK_REG_NAND_CLK (HHI_NAND_CLK_CNTL) +#define GCLK_MASK_NAND_CLK (1<<7) + +#define GCLK_IDX_HIU_PARSER_TOP 57 +#define GCLK_NAME_HIU_PARSER_TOP "HIU_PARSER_TOP" +#define GCLK_DEV_HIU_PARSER_TOP "CLKGATE_HIU_PARSER_TOP" +#define GCLK_REG_HIU_PARSER_TOP (HHI_GCLK_MPEG1) +#define GCLK_MASK_HIU_PARSER_TOP (1<<25) + +/* NEW ADD */ + +/* g12a no reg */ +#if 0 +#define GCLK_NAME_USB_CLK "USB_CLK" +#define GCLK_REG_USB_CLK (HHI_USB_CLK_CNTL) +#define GCLK_MASK_USB_CLK (1<<9) +#endif + +#define GCLK_IDX_USB_GENERAL 58 +#define GCLK_NAME_USB_GENERAL "USB_GENERAL" +#define GCLK_DEV_USB_GENERAL "CLKGATE_USB_GENERAL" +#define GCLK_REG_USB_GENERAL (HHI_GCLK_MPEG1) +#define GCLK_MASK_USB_GENERAL (1<<26) + +#define GCLK_IDX_RESERVED1_7 59 +#define GCLK_NAME_RESERVED1_7 "RESERVED1_7" +#define GCLK_DEV_RESERVED1_7 "CLKGATE_RESERVED1_7" +#define GCLK_REG_RESERVED1_7 (HHI_GCLK_MPEG1) +#define GCLK_MASK_RESERVED1_7 (1<<27) + +/* #define GCLK_IDX_VDIN1 60 */ +/* #define GCLK_NAME_VDIN1 "VDIN1" */ +/* #define GCLK_DEV_VDIN1 "CLKGATE_VDIN1" */ +/* #define GCLK_REG_VDIN1 (HHI_GCLK_MPEG1) */ +/* #define GCLK_MASK_VDIN1 (1<<28) */ + +#define GCLK_IDX_AHB_ARB0 61 +#define GCLK_NAME_AHB_ARB0 "AHB_ARB0" +#define GCLK_DEV_AHB_ARB0 "CLKGATE_AHB_ARB0" +#define GCLK_REG_AHB_ARB0 (HHI_GCLK_MPEG1) +#define GCLK_MASK_AHB_ARB0 (1<<29) + +#define GCLK_IDX_EFUSE 62 +#define GCLK_NAME_EFUSE "EFUSE" +#define GCLK_DEV_EFUSE "CLKGATE_EFUSE" +#define GCLK_REG_EFUSE (HHI_GCLK_MPEG1) +#define GCLK_MASK_EFUSE (1<<30) + +#define GCLK_IDX_ROM_CLK 63 +#define GCLK_NAME_ROM_CLK "ROM_CLK" +#define GCLK_DEV_ROM_CLK "CLKGATE_ROM_CLK" +#define GCLK_REG_ROM_CLK (HHI_GCLK_MPEG1) +#define GCLK_MASK_ROM_CLK (1<<31) + +/**************************************************************/ + +#define GCLK_IDX_RESERVED2_0 64 +#define GCLK_NAME_RESERVED2_0 "RESERVED2_0" +#define GCLK_DEV_RESERVED2_0 "CLKGATE_RESERVED2_0" +#define GCLK_REG_RESERVED2_0 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_0 (1<<0) + +#define GCLK_IDX_AHB_DATA_BUS 65 +#define GCLK_NAME_AHB_DATA_BUS "AHB_DATA_BUS" +#define GCLK_DEV_AHB_DATA_BUS "CLKGATE_AHB_DATA_BUS" +#define GCLK_REG_AHB_DATA_BUS (HHI_GCLK_MPEG2) +#define GCLK_MASK_AHB_DATA_BUS (1<<1) + +#define GCLK_IDX_AHB_CONTROL_BUS 66 +#define GCLK_NAME_AHB_CONTROL_BUS "AHB_CONTROL_BUS" +#define GCLK_DEV_AHB_CONTROL_BUS "CLKGATE_AHB_CONTROL_BUS" +#define GCLK_REG_AHB_CONTROL_BUS (HHI_GCLK_MPEG2) +#define GCLK_MASK_AHB_CONTROL_BUS (1<<2) + +#define GCLK_IDX_HDMI_INTR_SYNC 67 +#define GCLK_NAME_HDMI_INTR_SYNC "HDMI_INTR_SYNC" +#define GCLK_DEV_HDMI_INTR_SYNC "CLKGATE_HDMI_INTR_SYNC" +#define GCLK_REG_HDMI_INTR_SYNC (HHI_GCLK_MPEG2) +#define GCLK_MASK_HDMI_INTR_SYNC (1<<3) + +#define GCLK_IDX_HDMI_PCLK 68 +#define GCLK_NAME_HDMI_PCLK "HDMI_PCLK" +#define GCLK_DEV_HDMI_PCLK "CLKGATE_HDMI_PCLK" +#define GCLK_REG_HDMI_PCLK (HHI_GCLK_MPEG2) +#define GCLK_MASK_HDMI_PCLK (1<<4) + +#define GCLK_IDX_PDM 69 +#define GCLK_NAME_PDM "PDM" +#define GCLK_DEV_PDM "CLKGATE_PDM" +#define GCLK_REG_PDM (HHI_GCLK_MPEG2) +#define GCLK_MASK_PDM (1<<5) + +#define GCLK_IDX_BT656 70 +#define GCLK_NAME_BT656 "BT656" +#define GCLK_DEV_BT656 "CLKGATE_BT656" +#define GCLK_REG_BT656 (HHI_GCLK_MPEG2) +#define GCLK_MASK_BT656 (1<<6) + +#define GCLK_IDX_BT656_2 71 +#define GCLK_NAME_BT656_2 "BT656_2" +#define GCLK_DEV_BT656_2 "CLKGATE_BT656_2" +#define GCLK_REG_BT656_2 (HHI_GCLK_MPEG2) +#define GCLK_MASK_BT656_2 (1<<7) + +#define GCLK_IDX_MISC_USB1_TO_DDR 72 +#define GCLK_NAME_MISC_USB1_TO_DDR "MISC_USB1_TO_DDR" +#define GCLK_DEV_MISC_USB1_TO_DDR "CLKGATE_MISC_USB1_TO_DDR" +#define GCLK_REG_MISC_USB1_TO_DDR (HHI_GCLK_MPEG2) +#define GCLK_MASK_MISC_USB1_TO_DDR (1<<8) + +#define GCLK_IDX_MISC_USB0_TO_DDR 73 +#define GCLK_NAME_MISC_USB0_TO_DDR "MISC_USB0_TO_DDR" +#define GCLK_DEV_MISC_USB0_TO_DDR "CLKGATE_MISC_USB0_TO_DDR" +#define GCLK_REG_MISC_USB0_TO_DDR (HHI_GCLK_MPEG2) +#define GCLK_MASK_MISC_USB0_TO_DDR (1<<9) + +#define GCLK_IDX_RESERVED2_4 74 +#define GCLK_NAME_RESERVED2_4 "RESERVED2_4" +#define GCLK_DEV_RESERVED2_4 "CLKGATE_RESERVED2_4" +#define GCLK_REG_RESERVED2_4 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_4 (1<<10) + +#define GCLK_IDX_MMC_PCLK 75 +#define GCLK_NAME_MMC_PCLK "MMC_PCLK" +#define GCLK_DEV_MMC_PCLK "CLKGATE_MMC_PCLK" +#define GCLK_REG_MMC_PCLK (HHI_GCLK_MPEG2) +#define GCLK_MASK_MMC_PCLK (1<<11) + +//g12a no reg +#if 0 +#define GCLK_NAME_MMC_A_PCLK "MMC_A_PCLK" +#define GCLK_REG_MMC_A_PCLK (HHI_MPLL_CNTL10) +#define GCLK_MASK_MMC_A_PCLK (1<<2) + +#define GCLK_NAME_MMC_B_PCLK "MMC_B_PCLK" +#define GCLK_REG_MMC_B_PCLK (HHI_MPLL_CNTL10) +#define GCLK_MASK_MMC_B_PCLK (1<<1) + +#define GCLK_NAME_MMC_C_PCLK "MMC_C_PCLK" +#define GCLK_REG_MMC_C_PCLK (HHI_MPLL_CNTL10) +#define GCLK_MASK_MMC_C_PCLK (1<<0) +#endif + +#define GCLK_NAME_EMMC_A_CLK "EMMC_A_CLK" +#define GCLK_REG_EMMC_A_CLK (HHI_SD_EMMC_CLK_CNTL) +#define GCLK_MASK_EMMC_A_CLK (1<<7) + +#define GCLK_NAME_EMMC_B_CLK "EMMC_B_CLK" +#define GCLK_REG_EMMC_B_CLK (HHI_SD_EMMC_CLK_CNTL) +#define GCLK_MASK_EMMC_B_CLK (1<<23) + +#define GCLK_IDX_MISC_DVIN 76 +#define GCLK_NAME_MISC_DVIN "MISC_DVIN" +#define GCLK_DEV_MISC_DVIN "CLKGATE_MISC_DVIN" +#define GCLK_REG_MISC_DVIN (HHI_GCLK_MPEG2) +#define GCLK_MASK_MISC_DVIN (1<<12) + +#define GCLK_IDX_RESERVED2_5 77 +#define GCLK_NAME_RESERVED2_5 "RESERVED2_5" +#define GCLK_DEV_RESERVED2_5 "CLKGATE_RESERVED2_5" +#define GCLK_REG_RESERVED2_5 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_5 (1<<13) + +#define GCLK_IDX_RESERVED2_6 78 +#define GCLK_NAME_RESERVED2_6 "RESERVED2_6" +#define GCLK_DEV_RESERVED2_6 "CLKGATE_RESERVED2_6" +#define GCLK_REG_RESERVED2_6 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_6 (1<<14) + +#define GCLK_IDX_UART2 79 +#define GCLK_NAME_UART2 "UART2" +#define GCLK_DEV_UART2 "CLKGATE_UART2" +#define GCLK_REG_UART2 (HHI_GCLK_MPEG2) +#define GCLK_MASK_UART2 (1<<15) + +#define GCLK_IDX_RESERVED2_7 80 +#define GCLK_NAME_RESERVED2_7 "RESERVED2_7" +#define GCLK_DEV_RESERVED2_7 "CLKGATE_RESERVED2_7" +#define GCLK_REG_RESERVED2_7 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_7 (1<<16) + +#define GCLK_IDX_RESERVED2_8 81 +#define GCLK_NAME_RESERVED2_8 "RESERVED2_8" +#define GCLK_DEV_RESERVED2_8 "CLKGATE_RESERVED2_8" +#define GCLK_REG_RESERVED2_8 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_8 (1<<17) + +#define GCLK_IDX_RESERVED2_9 82 +#define GCLK_NAME_RESERVED2_9 "RESERVED2_9" +#define GCLK_DEV_RESERVED2_9 "CLKGATE_RESERVED2_9" +#define GCLK_REG_RESERVED2_9 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_9 (1<<18) + +#define GCLK_IDX_RESERVED2_A 83 +#define GCLK_NAME_RESERVED2_A "RESERVED2_A" +#define GCLK_DEV_RESERVED2_A "CLKGATE_RESERVED2_A" +#define GCLK_REG_RESERVED2_A (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_A (1<<19) + +#define GCLK_IDX_RESERVED2_B 84 +#define GCLK_NAME_RESERVED2_B "RESERVED2_B" +#define GCLK_DEV_RESERVED2_B "CLKGATE_RESERVED2_B" +#define GCLK_REG_RESERVED2_B (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_B (1<<20) + +#define GCLK_IDX_UART3 85 +#define GCLK_NAME_UART3 "UART3" +#define GCLK_DEV_UART3 "CLKGATE_UART3" +#define GCLK_REG_UART3 (HHI_GCLK_MPEG2) +#define GCLK_MASK_UART3 (1<<21) + +#define GCLK_IDX_SANA 86 +#define GCLK_NAME_SANA "SANA" +#define GCLK_DEV_SANA "CLKGATE_SANA" +#define GCLK_REG_SANA (HHI_GCLK_MPEG2) +#define GCLK_MASK_SANA (1<<22) + +#define GCLK_IDX_RESERVED2_D 87 +#define GCLK_NAME_RESERVED2_D "RESERVED2_D" +#define GCLK_DEV_RESERVED2_D "CLKGATE_RESERVED2_D" +#define GCLK_REG_RESERVED2_D (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_D (1<<23) + +#define GCLK_IDX_RESERVED2_E 88 +#define GCLK_NAME_RESERVED2_E "RESERVED2_E" +#define GCLK_DEV_RESERVED2_E "CLKGATE_RESERVED2_E" +#define GCLK_REG_RESERVED2_E (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_E (1<<24) + +#define GCLK_IDX_VPU_INTR 89 +#define GCLK_NAME_VPU_INTR "VPU_INTR" +#define GCLK_DEV_VPU_INTR "CLKGATE_VPU_INTR" +#define GCLK_REG_VPU_INTR (HHI_GCLK_MPEG2) +#define GCLK_MASK_VPU_INTR (1<<25) + +#define GCLK_IDX_SECURE_AHP_APB3 90 +#define GCLK_NAME_SECURE_AHP_APB3 "SECURE_AHP_APB3" +#define GCLK_DEV_SECURE_AHP_APB3 "CLKGATE_SECURE_AHP_APB3" +#define GCLK_REG_SECURE_AHP_APB3 (HHI_GCLK_MPEG2) +#define GCLK_MASK_SECURE_AHP_APB3 (1<<26) + +#define GCLK_IDX_RESERVED2_F 91 +#define GCLK_NAME_RESERVED2_F "RESERVED2_F" +#define GCLK_DEV_RESERVED2_F "CLKGATE_RESERVED2_F" +#define GCLK_REG_RESERVED2_F (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_F (1<<27) + +#define GCLK_IDX_RESERVED2_10 92 +#define GCLK_NAME_RESERVED2_10 "RESERVED2_10" +#define GCLK_DEV_RESERVED2_10 "CLKGATE_RESERVED2_10" +#define GCLK_REG_RESERVED2_10 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_10 (1<<28) + +#define GCLK_IDX_CLK81_TO_A9 93 +#define GCLK_NAME_CLK81_TO_A9 "CLK81_TO_A9" +#define GCLK_DEV_CLK81_TO_A9 "CLKGATE_CLK81_TO_A9" +#define GCLK_REG_CLK81_TO_A9 (HHI_GCLK_MPEG2) +#define GCLK_MASK_CLK81_TO_A9 (1<<29) + +#define GCLK_IDX_GIC 94 +#define GCLK_NAME_GIC "GIC" +#define GCLK_DEV_GIC "CLKGATE_GIC" +#define GCLK_REG_GIC (HHI_GCLK_MPEG2) +#define GCLK_MASK_GIC (1<<30) + +#define GCLK_IDX_RESERVED2_12 95 +#define GCLK_NAME_RESERVED2_12 "RESERVED2_12" +#define GCLK_DEV_RESERVED2_12 "CLKGATE_RESERVED2_12" +#define GCLK_REG_RESERVED2_12 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED2_12 (1<<31) + +/**************************************************************/ + +#define GCLK_IDX_RESERVED3_0 96 +#define GCLK_NAME_RESERVED3_0 "RESERVED3_0" +#define GCLK_DEV_RESERVED3_0 "CLKGATE_RESERVED3_0" +#define GCLK_REG_RESERVED3_0 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED3_0 (1<<0) + +#define GCLK_IDX_VCLK2_VENCI 97 +#define GCLK_NAME_VCLK2_VENCI "VCLK2_VENCI" +#define GCLK_DEV_VCLK2_VENCI "CLKGATE_VCLK2_VENCI" +#define GCLK_REG_VCLK2_VENCI (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCI (1<<1) + +#define GCLK_IDX_VCLK2_VENCI1 98 +#define GCLK_NAME_VCLK2_VENCI1 "VCLK2_VENCI1" +#define GCLK_DEV_VCLK2_VENCI1 "CLKGATE_VCLK2_VENCI1" +#define GCLK_REG_VCLK2_VENCI1 (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCI1 (1<<2) + +#define GCLK_IDX_VCLK2_VENCP 99 +#define GCLK_NAME_VCLK2_VENCP "VCLK2_VENCP" +#define GCLK_DEV_VCLK2_VENCP "CLKGATE_VCLK2_VENCP" +#define GCLK_REG_VCLK2_VENCP (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCP (1<<3) + +#define GCLK_IDX_VCLK2_VENCP1 100 +#define GCLK_NAME_VCLK2_VENCP1 "VCLK2_VENCP1" +#define GCLK_DEV_VCLK2_VENCP1 "CLKGATE_VCLK2_VENCP1" +#define GCLK_REG_VCLK2_VENCP1 (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCP1 (1<<4) + +#define GCLK_IDX_VCLK2_VENCT 101 +#define GCLK_NAME_VCLK2_VENCT "VCLK2_VENCT" +#define GCLK_DEV_VCLK2_VENCT "CLKGATE_VCLK2_VENCT" +#define GCLK_REG_VCLK2_VENCT (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCT (1<<5) + +#define GCLK_IDX_VCLK2_VENCT1 102 +#define GCLK_NAME_VCLK2_VENCT1 "VCLK2_VENCT1" +#define GCLK_DEV_VCLK2_VENCT1 "CLKGATE_VCLK2_VENCT1" +#define GCLK_REG_VCLK2_VENCT1 (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCT1 (1<<6) + +#define GCLK_IDX_VCLK2_OTHER 103 +#define GCLK_NAME_VCLK2_OTHER "VCLK2_OTHER" +#define GCLK_DEV_VCLK2_OTHER "CLKGATE_VCLK2_OTHER" +#define GCLK_REG_VCLK2_OTHER (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_OTHER (1<<7) + +#define GCLK_IDX_VCLK2_ENCI 104 +#define GCLK_NAME_VCLK2_ENCI "VCLK2_ENCI" +#define GCLK_DEV_VCLK2_ENCI "CLKGATE_VCLK2_ENCI" +#define GCLK_REG_VCLK2_ENCI (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_ENCI (1<<8) + +#define GCLK_IDX_VCLK2_ENCP 105 +#define GCLK_NAME_VCLK2_ENCP "VCLK2_ENCP" +#define GCLK_DEV_VCLK2_ENCP "CLKGATE_VCLK2_ENCP" +#define GCLK_REG_VCLK2_ENCP (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_ENCP (1<<9) + +#define GCLK_IDX_DAC_CLK 106 +#define GCLK_NAME_DAC_CLK "DAC_CLK" +#define GCLK_DEV_DAC_CLK "CLKGATE_DAC_CLK" +#define GCLK_REG_DAC_CLK (HHI_GCLK_OTHER) +#define GCLK_MASK_DAC_CLK (1<<10) + +#define GCLK_IDX_RESERVED3_1 107 +#define GCLK_NAME_RESERVED3_1 "RESERVED3_1" +#define GCLK_DEV_RESERVED3_1 "CLKGATE_RESERVED3_1" +#define GCLK_REG_RESERVED3_1 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED3_1 (1<<11) + +#define GCLK_IDX_RESERVED3_2 108 +#define GCLK_NAME_RESERVED3_2 "RESERVED3_2" +#define GCLK_DEV_RESERVED3_2 "CLKGATE_RESERVED3_2" +#define GCLK_REG_RESERVED3_2 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED3_2 (1<<12) + +#define GCLK_IDX_RESERVED3_3 109 +#define GCLK_NAME_RESERVED3_3 "RESERVED3_3" +#define GCLK_DEV_RESERVED3_3 "CLKGATE_RESERVED3_3" +#define GCLK_REG_RESERVED3_3 (HHI_GCLK_MPEG2) +#define GCLK_MASK_RESERVED3_3 (1<<13) + +#define GCLK_IDX_AIU_AOCLK 110 +#define GCLK_NAME_AIU_AOCLK "AIU_AOCLK" +#define GCLK_DEV_AIU_AOCLK "CLKGATE_AIU_AOCLK" +#define GCLK_REG_AIU_AOCLK (HHI_GCLK_OTHER) +#define GCLK_MASK_AIU_AOCLK (1<<14) + +#define GCLK_IDX_RESERVED3_4 111 +#define GCLK_NAME_RESERVED3_4 "RESERVED3_4" +#define GCLK_DEV_RESERVED3_4 "CLKGATE_RESERVED3_4" +#define GCLK_REG_RESERVED3_4 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_4 (1<<15) + +#define GCLK_IDX_AIU_ICE958_AMCLK 112 +#define GCLK_NAME_AIU_ICE958_AMCLK "AIU_ICE958_AMCLK" +#define GCLK_DEV_AIU_ICE958_AMCLK "CLKGATE_AIU_ICE958_AMCLK" +#define GCLK_REG_AIU_ICE958_AMCLK (HHI_GCLK_OTHER) +#define GCLK_MASK_AIU_ICE958_AMCLK (1<<16) + +#define GCLK_IDX_RESERVED3_5 113 +#define GCLK_NAME_RESERVED3_5 "RESERVED3_5" +#define GCLK_DEV_RESERVED3_5 "CLKGATE_RESERVED3_5" +#define GCLK_REG_RESERVED3_5 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_5 (1<<17) + +#define GCLK_IDX_RESERVED3_6 114 +#define GCLK_NAME_RESERVED3_6 "RESERVED3_6" +#define GCLK_DEV_RESERVED3_6 "CLKGATE_RESERVED3_6" +#define GCLK_REG_RESERVED3_6 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_6 (1<<18) + +#define GCLK_IDX_RESERVED3_7 115 +#define GCLK_NAME_RESERVED3_7 "RESERVED3_7" +#define GCLK_DEV_RESERVED3_7 "CLKGATE_RESERVED3_7" +#define GCLK_REG_RESERVED3_7 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_7 (1<<19) + +#define GCLK_IDX_ENC480P 116 +#define GCLK_NAME_ENC480P "ENC480P" +#define GCLK_DEV_ENC480P "CLKGATE_ENC480P" +#define GCLK_REG_ENC480P (HHI_GCLK_OTHER) +#define GCLK_MASK_ENC480P (1<<20) + +#define GCLK_IDX_RANDOM_NUM_GEN1 117 +#define GCLK_NAME_RANDOM_NUM_GEN1 "RANDOM_NUM_GEN1" +#define GCLK_DEV_RANDOM_NUM_GEN1 "CLKGATE_RANDOM_NUM_GEN1" +#define GCLK_REG_RANDOM_NUM_GEN1 (HHI_GCLK_OTHER) +#define GCLK_MASK_RANDOM_NUM_GEN1 (1<<21) + +#define GCLK_IDX_VCLK2_ENCT 118 +#define GCLK_NAME_VCLK2_ENCT "GCLK_VENCL_INT" +#define GCLK_DEV_VCLK2_ENCT "CLKGATE_GCLK_VENCL_INT" +#define GCLK_REG_VCLK2_ENCT (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_ENCT (1<<22) + +#define GCLK_IDX_VCLK2_ENCL 119 +#define GCLK_NAME_VCLK2_ENCL "VLKC2_ENCL" +#define GCLK_DEV_VCLK2_ENCL "CLKGATE_VCLK2_ENCL" +#define GCLK_REG_VCLK2_ENCL (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_ENCL (1<<23) + +#define GCLK_IDX_MMC_CLK 120 +#define GCLK_NAME_MMC_CLK "MMC_CLK" +#define GCLK_DEV_MMC_CLK "CLKGATE_MMC_CLK" +#define GCLK_REG_MMC_CLK (HHI_GCLK_OTHER) +#define GCLK_MASK_MMC_CLK (1<<24) + +#define GCLK_IDX_VCLK2_VENCL 121 +#define GCLK_NAME_VCLK2_VENCL "VCLK2_VENCL" +#define GCLK_DEV_VCLK2_VENCL "CLKGATE_VCLK2_VENCL" +#define GCLK_REG_VCLK2_VENCL (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_VENCL (1<<25) + +#define GCLK_IDX_VCLK2_OTHER1 122 +#define GCLK_NAME_VCLK2_OTHER1 "VCLK2_OTHER1" +#define GCLK_DEV_VCLK2_OTHER1 "CLKGATE_VCLK2_OTHER1" +#define GCLK_REG_VCLK2_OTHER1 (HHI_GCLK_OTHER) +#define GCLK_MASK_VCLK2_OTHER1 (1<<26) + +#define GCLK_IDX_RESERVED3_9 123 +#define GCLK_NAME_RESERVED3_9 "RESERVED3_9" +#define GCLK_DEV_RESERVED3_9 "CLKGATE_RESERVED3_9" +#define GCLK_REG_RESERVED3_9 (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_9 (1<<27) + +#define GCLK_IDX_RESERVED3_A 124 +#define GCLK_NAME_RESERVED3_A "RESERVED3_A" +#define GCLK_DEV_RESERVED3_A "CLKGATE_RESERVED3_A" +#define GCLK_REG_RESERVED3_A (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_A (1<<28) + +#define GCLK_IDX_RESERVED3_B 125 +#define GCLK_NAME_RESERVED3_B "RESERVED3_B" +#define GCLK_DEV_RESERVED3_B "CLKGATE_RESERVED3_B" +#define GCLK_REG_RESERVED3_B (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_B (1<<29) + +#define GCLK_IDX_RESERVED3_C 126 +#define GCLK_NAME_RESERVED3_C "RESERVED3_C" +#define GCLK_DEV_RESERVED3_C "CLKGATE_RESERVED3_C" +#define GCLK_REG_RESERVED3_C (HHI_GCLK_OTHER) +#define GCLK_MASK_RESERVED3_C (1<<30) + +#define GCLK_IDX_EDP_CLK 127 +#define GCLK_NAME_EDP_CLK "EDP_CLK" +#define GCLK_DEV_EDP_CLK "CLKGATE_EDP_CLK" +#define GCLK_REG_EDP_CLK (HHI_GCLK_OTHER) +#define GCLK_MASK_EDP_CLK (1<<31) + +/**************************************************************/ + +#define GCLK_IDX_MEDIA_CPU 128 +#define GCLK_NAME_MEDIA_CPU "MEDIA_CPU" +#define GCLK_DEV_MEDIA_CPU "CLKGATE_MEDIA_CPU" +#define GCLK_REG_MEDIA_CPU (HHI_GCLK_AO) +#define GCLK_MASK_MEDIA_CPU (1<<0) + +#define GCLK_IDX_AHB_SRAM 129 +#define GCLK_NAME_AHB_SRAM "AHB_SRAM" +#define GCLK_DEV_AHB_SRAM "CLKGATE_AHB_SRAM" +#define GCLK_REG_AHB_SRAM (HHI_GCLK_AO) +#define GCLK_MASK_AHB_SRAM (1<<1) + +#define GCLK_IDX_AHB_BUS 130 +#define GCLK_NAME_AHB_BUS "AHB_BUS" +#define GCLK_DEV_AHB_BUS "CLKGATE_AHB_BUS" +#define GCLK_REG_AHB_BUS (HHI_GCLK_AO) +#define GCLK_MASK_AHB_BUS (1<<2) + +#define GCLK_IDX_AO_REGS 131 +#define GCLK_NAME_AO_REGS "AO_REGS" +#define GCLK_DEV_AO_REGS "CLKGATE_AO_REGS" +#define GCLK_REG_AO_REGS (HHI_GCLK_AO) +#define GCLK_MASK_AO_REGS (1<<3) + +#define GCLK_NAME_I2C_AO "I2C_AO" +#define GCLK_REG_I2C_AO (HHI_GCLK_AO) +#define GCLK_MASK_I2C_AO (1<<4) + + +#define GCLK_IDX_CTS_ENCI 132 +#define GCLK_NAME_CTS_ENCI "CTS_ENCI" +#define GCLK_DEV_CTS_ENCI "CLKGATE_CTS_ENCI" +#define GCLK_REG_CTS_ENCI (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_ENCI (1<<0) + +#define GCLK_IDX_CTS_ENCT 133 +#define GCLK_NAME_CTS_ENCT "CTS_ENCT" +#define GCLK_DEV_CTS_ENCT "CLKGATE_CTS_ENCT" +#define GCLK_REG_CTS_ENCT (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_ENCT (1<<1) + +#define GCLK_IDX_CTS_ENCP 134 +#define GCLK_NAME_CTS_ENCP "CTS_ENCP" +#define GCLK_DEV_CTS_ENCP "CLKGATE_CTS_ENCP" +#define GCLK_REG_CTS_ENCP (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_ENCP (1<<2) + +#define GCLK_IDX_CTS_ENCL 135 +#define GCLK_NAME_CTS_ENCL "CTS_ENCL" +#define GCLK_DEV_CTS_ENCL "CLKGATE_CTS_ENCL" +#define GCLK_REG_CTS_ENCL (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_ENCL (1<<3) + +#define GCLK_IDX_CTS_VDAC 136 +#define GCLK_NAME_CTS_VDAC "CTS_VDAC" +#define GCLK_DEV_CTS_VDAC "CLKGATE_CTS_VDAC" +#define GCLK_REG_CTS_VDAC (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_VDAC (1<<4) + +#define GCLK_IDX_CTS_HDMI_TX_PIXEL 137 +#define GCLK_NAME_CTS_HDMI_TX_PIXEL "CTS_HDMI_TX_PIXEL" +#define GCLK_DEV_CTS_HDMI_TX_PIXEL "CLKGATE_CTS_HDMI_TX_PIXEL" +#define GCLK_REG_CTS_HDMI_TX_PIXEL (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_CTS_HDMI_TX_PIXEL (1<<5) + +#define GCLK_IDX_AUD 138 +#define GCLK_NAME_AUD "AUD" +#define GCLK_DEV_AUD "CLKGATE_AUD" +#define GCLK_REG_AUD (HHI_AUD_CLK_CNTL) +#define GCLK_MASK_AUD (1<<23) + + +#define GCLK_IDX_AUD2 138 +#define GCLK_NAME_AUD2 "AUD2" +#define GCLK_DEV_AUD2 "CLKGATE_AUD2" +#define GCLK_REG_AUD2 (HHI_AUD_CLK_CNTL) +#define GCLK_MASK_AUD2 (1<<8) + + +#define GCLK_NAME_AUD_CLK_2 "AUD_CLK_2" +#define GCLK_REG_AUD_CLK_2 (HHI_AUD_CLK_CNTL2) +#define GCLK_MASK_AUD_CLK_2 (1<<8) + +#define GCLK_IDX_AUD_CLK_3 138 +#define GCLK_NAME_AUD_CLK_3 "AUD_CLK" +#define GCLK_DEV_AUD_CLK_3 "CLKGATE_AUD_CLK" +#define GCLK_REG_AUD_CLK_3 (HHI_AUD_CLK_CNTL3) +#define GCLK_MASK_AUD_CLK_3 (1<<16) + +#define GCLK_IDX_LCD_AN_PHY2 139 +#define GCLK_NAME_LCD_AN_PHY2 "LCD_AN_PHY2" +#define GCLK_DEV_LCD_AN_PHY2 "CLKGATE_LCD_AN_PHY2" +#define GCLK_REG_LCD_AN_PHY2 (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_LCD_AN_PHY2 (1<<7) + +#define GCLK_IDX_LCD_AN_PHY3 140 +#define GCLK_NAME_LCD_AN_PHY3 "LCD_AN_PHY3" +#define GCLK_DEV_LCD_AN_PHY3 "CLKGATE_LCD_AN_PHY3" +#define GCLK_REG_LCD_AN_PHY3 (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_LCD_AN_PHY3 (1<<6) + +#define GCLK_NAME_ATV_DEMO_VDAC "ATV_DEMO_VDAC" +#define GCLK_REG_ATV_DEMO_VDAC (HHI_VID_CLK_CNTL2) +#define GCLK_MASK_ATV_DEMO_VDAC (1<<8) + +#define GCLK_IDX_HDMI_PLL_CNTL 142 +#define GCLK_NAME_HDMI_PLL_CNTL "HDMI_PLL_CNTL" +#define GCLK_DEV_HDMI_PLL_CNTL "GATE_HDMI_PLL_CNTL" +#define GCLK_REG_HDMI_PLL_CNTL (HHI_HDMI_PLL_CNTL) +#define GCLK_MASK_HDMI_PLL_CNTL (1<<30) + +#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK" +#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL) +#define GCLK_MASK_HDMITX_CLK (1<<8) + + +#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK" +#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL) +#define GCLK_MASK_HDMITX_CLK (1<<8) + +#define GCLK_IDX_VDEC_CLK_1 144 +#define GCLK_NAME_VDEC_CLK_1 "VDEC_CLK_1" +#define GCLK_DEV_VDEC_CLK_1 "CLKGATE_VDEC_CLK_1" +#define GCLK_REG_VDEC_CLK_1 (HHI_VDEC_CLK_CNTL) +#define GCLK_MASK_VDEC_CLK_1 (1<<8) + +#define GCLK_NAME_VDEC_CLK_2 "VDEC_CLK_2" +#define GCLK_REG_VDEC_CLK_2 (HHI_VDEC3_CLK_CNTL) +#define GCLK_MASK_VDEC_CLK_2 (1<<8) + +#define GCLK_NAME_VDEC2_CLK_1 "VDEC2_CLK_1" +#define GCLK_REG_VDEC2_CLK_1 (HHI_VDEC2_CLK_CNTL) +#define GCLK_MASK_VDEC2_CLK_1 (1<<8) + +#define GCLK_NAME_VDEC2_CLK_2 "VDEC2_CLK_2" +#define GCLK_REG_VDEC2_CLK_2 (HHI_VDEC4_CLK_CNTL) +#define GCLK_MASK_VDEC2_CLK_2 (1<<8) + +#define GCLK_IDX_HCODEC_CLK_1 145 +#define GCLK_NAME_HCODEC_CLK_1 "HCODEC_CLK" +#define GCLK_DEV_HCODEC_CLK_1 "CLKGATE_HCODEC_CLK" +#define GCLK_REG_HCODEC_CLK_1 (HHI_VDEC_CLK_CNTL) +#define GCLK_MASK_HCODEC_CLK_1 (1<<24) + +#define GCLK_NAME_HCODEC_CLK_2 "HCODEC_CLK_2" +#define GCLK_REG_HCODEC_CLK_2 (HHI_VDEC3_CLK_CNTL) +#define GCLK_MASK_HCODEC_CLK_2 (1<<24) + +#define GCLK_NAME_HEVC_CLK_1 "HCODEC_CLK_1" +#define GCLK_REG_HEVC_CLK_1 (HHI_VDEC2_CLK_CNTL) +#define GCLK_MASK_HEVC_CLK_1 (1<<24) + +#define GCLK_NAME_HEVC_CLK_2 "HEVC_CLK_2" +#define GCLK_REG_HEVC_CLK_2 (HHI_VDEC4_CLK_CNTL) +#define GCLK_MASK_HEVC_CLK_2 (1<<24) + +#define GCLK_IDX_GEN_CLK 146 +#define GCLK_NAME_GEN_CLK "GEN_CLK" +#define GCLK_DEV_GEN_CLK "CLKGATE_HCODEC_CLK" +#define GCLK_REG_GEN_CLK (HHI_GEN_CLK_CNTL) +#define GCLK_MASK_GEN_CLK (1<<11) + +#define GCLK_NAME_VPU_CLK_1 "VPU_CLK_1" +#define GCLK_REG_VPU_CLK_1 (HHI_VPU_CLK_CNTL) +#define GCLK_MASK_VPU_CLK_1 (1<<8) + +#define GCLK_NAME_VPU_CLK_2 "VPU_CLK_2" +#define GCLK_REG_VPU_CLK_2 (HHI_VPU_CLK_CNTL) +#define GCLK_MASK_VPU_CLK_2 (1<<24) + + +#define GCLK_NAME_VPU_CLKB "VPU_CLKB" +#define GCLK_REG_VPU_CLKB (HHI_VPU_CLKB_CNTL) +#define GCLK_MASK_VPU_CLKB (1<<8) + +#define GCLK_NAME_VAPB_CLK_1 "VAPB_CLK_1" +#define GCLK_REG_VAPB_CLK_1 (HHI_VAPBCLK_CNTL) +#define GCLK_MASK_VAPB_CLK_1 (1<<8) + +#define GCLK_NAME_VAPB_CLK_2 "VAPB_CLK_2" +#define GCLK_REG_VAPB_CLK_2 (HHI_VAPBCLK_CNTL) +#define GCLK_MASK_VAPB_CLK_2 (1<<24) + +#define GCLK_NAME_MALI_CLK_1 "MALI_CLK_1" +#define GCLK_REG_MALI_CLK_1 (HHI_MALI_CLK_CNTL) +#define GCLK_MASK_MALI_CLK_1 (1<<8) + +#define GCLK_NAME_MALI_CLK_2 "MALI_CLK_2" +#define GCLK_REG_MALI_CLK_2 (HHI_MALI_CLK_CNTL) +#define GCLK_MASK_MALI_CLK_2 (1<<24) + +#define GCLK_NAME_PWM_A_CLK "PWM_A_CLK" +#define GCLK_REG_PWM_A_CLK (CBUS_REG_ADDR(0x2156)) +#define GCLK_MASK_PWM_A_CLK (1<<15) + +#define GCLK_NAME_PWM_B_CLK "PWM_B_CLK" +#define GCLK_REG_PWM_B_CLK (CBUS_REG_ADDR(0x2156)) +#define GCLK_MASK_PWM_B_CLK (1<<23) + +#define GCLK_NAME_PWM_C_CLK "PWM_C_CLK" +#define GCLK_REG_PWM_C_CLK (CBUS_REG_ADDR(0x2196)) +#define GCLK_MASK_PWM_C_CLK (1<<15) + +#define GCLK_NAME_PWM_D_CLK "PWM_D_CLK" +#define GCLK_REG_PWM_D_CLK (CBUS_REG_ADDR(0x2196)) +#define GCLK_MASK_PWM_D_CLK (1<<23) + +#define GCLK_NAME_PWM_E_CLK "PWM_E_CLK" +#define GCLK_REG_PWM_E_CLK (CBUS_REG_ADDR(0x21b2)) +#define GCLK_MASK_PWM_E_CLK (1<<15) + +#define GCLK_NAME_PWM_F_CLK "PWM_D_CLK" +#define GCLK_REG_PWM_F_CLK (CBUS_REG_ADDR(0x21b2)) +#define GCLK_MASK_PWM_F_CLK (1<<23) + +#define GCLK_NAME_VDIN_MEAS_CLK "VDIN_MEAS_CLK" +#define GCLK_REG_VDIN_MEAS_CLK (HHI_VDIN_MEAS_CLK_CNTL) +#define GCLK_MASK_VDIN_MEAS_CLK (1<<8) + +#define GCLK_NAME_MSR_CLK "MSR_CLK" +#define GCLK_REG_MSR_CLK (CBUS_REG_ADDR(0x21d7)) +#define GCLK_MASK_MSR_CLK (1<<19) + +#define GCLK_NAME_MSR_HS_CLK "MSR_HS_CLK" +#define GCLK_REG_MSR_HS_CLK (CBUS_REG_ADDR(0x21d9)) +#define GCLK_MASK_MSR_HS_CLK (1<<28) + +#define GCLK_NAME_32K_CLK "32K_CLK" +#define GCLK_REG_32K_CLK (HHI_32K_CLK_CNTL) +#define GCLK_MASK_32K_CLK (1<<15) + + + +#define GCLK_IDX_MAX 200 + +extern short GCLK_ref[GCLK_IDX_MAX]; + +#define REGISTER_CLK(_MOD) \ +static struct clk CLK_##_MOD = { \ + .name = GCLK_NAME_##_MOD, \ + .clock_index = GCLK_IDX_##_MOD, \ + .clock_gate_reg_adr = GCLK_REG_##_MOD, \ + .clock_gate_reg_mask = GCLK_MASK_##_MOD, \ +} + +#define CLK_LOOKUP_ITEM(_MOD) \ + { \ + .dev_id = GCLK_DEV_##_MOD, \ + .con_id = GCLK_NAME_##_MOD, \ + .clk = &CLK_##_MOD, \ + } + + + +/**********************/ +/* internal audio dac control */ +#define ADAC_RESET (0x5000+0x00*4) +#define ADAC_LATCH (0x5000+0x01*4) +#define ADAC_POWER_CTRL_REG1 (0x5000+0x10*4) +#define ADAC_POWER_CTRL_REG2 (0x5000+0x11*4) + +int audio_internal_dac_disable(void); + +/* video dac control */ +int video_dac_enable(unsigned char enable_mask); + +int video_dac_disable(void); + + +#endif
diff --git a/arch/arm/mach-meson/sc2/sdio.c b/arch/arm/mach-meson/sc2/sdio.c new file mode 100644 index 0000000..14ec635 --- /dev/null +++ b/arch/arm/mach-meson/sc2/sdio.c
@@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <asm/arch/io.h> +#include <asm/arch/cpu_sdio.h> +#include <asm/arch/secure_apb.h> +#include <amlogic/cpu_id.h> +#include <common.h> + +void cpu_sd_emmc_pwr_prepare(unsigned port) +{ +} +int cpu_sd_emmc_init(unsigned port) +{ + return 0; +} + +/* return: + 0: insert + 1: not insert + */ +__weak int sd_emmc_detect(unsigned port) +{ + int ret = 0; + + return ret; +} + +
diff --git a/arch/arm/mach-meson/sc2/timer.c b/arch/arm/mach-meson/sc2/timer.c new file mode 100644 index 0000000..8c16210 --- /dev/null +++ b/arch/arm/mach-meson/sc2/timer.c
@@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timer.h> +#include <asm/types.h> + +uint32_t get_time(void) +{ + return readl(SYSCTRL_TIMERE); +} + +void _udelay(unsigned int us) +{ +#ifndef CONFIG_PXP_EMULATOR + unsigned int t0 = get_time(); + + while (get_time() - t0 <= us) + ; +#endif +}
diff --git a/arch/arm/mach-meson/sc2/tsensor.c b/arch/arm/mach-meson/sc2/tsensor.c new file mode 100644 index 0000000..a6b6741 --- /dev/null +++ b/arch/arm/mach-meson/sc2/tsensor.c
@@ -0,0 +1,340 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <command.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/mailbox.h> +#include <asm/arch/tsensor.h> +#include <asm/arch/bl31_apis.h> + +int tsensor_tz_calibration(unsigned int type, unsigned int data) +{ + int ret; + + register long x0 asm("x0") = TSENSOR_CALI_SET; + register long x1 asm("x1") = type; + register long x2 asm("x2") = data; + register long x3 asm("x3") = 0; + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x3") + "smc #0\n" + : "+r" (x0) + : "r" (x1), "r" (x2), "r" (x3)); + } while (0); + ret = x0; + + if (!ret) + return -1; + else + return 0; +} + +int r1p1_codetotemp(unsigned long value, unsigned int u_efuse) +{ + int64_t temp; + + temp = (value * ts_m) * (1 << 16) / (100 * (1 << 16) + ts_n * value); + if (u_efuse & 0x8000) { + temp = ((temp - (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10; + } else { + temp = ((temp + (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10; + } + return temp; +} + +int r1p1_temp_read(int type) +{ + unsigned int ret, u_efuse; + unsigned int value_ts, value_all_ts; + int tmp = -1; + int i, cnt; + char buf[2]; + + switch (type) { + case 1: + /*enable thermal1*/ + writel(T_CONTROL_DATA, TS_PLL_CFG_REG1); + writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL); + ret = readl(SYSCTRL_SEC_STATUS_REG10);/*thermal1 cali data in reg CFG10*/ + mdelay(5); + buf[0] = (ret) & 0xff; + buf[1] = (ret >> 8) & 0xff; + u_efuse = buf[1]; + u_efuse = (u_efuse << 8) | buf[0]; + value_ts = 0; + value_all_ts = 0; + cnt = 0; + for (i = 0; i <= 10; i ++) { + udelay(50); + value_ts = readl(TS_PLL_STAT0) & 0xffff; + } + for (i = 0; i <= T_AVG_NUM; i ++) { + udelay(T_DLY_TIME); + value_ts = readl(TS_PLL_STAT0) & 0xffff; + if ((value_ts >= T_VALUE_MIN) && + (value_ts <= T_VALUE_MAX)) { + value_all_ts += value_ts; + cnt ++; + } + } + value_ts = value_all_ts / cnt; + printf("pll tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse); + if (value_ts == 0) { + printf("pll tsensor read temp is zero\n"); + return -1; + } + tmp = r1p1_codetotemp(value_ts, u_efuse); + printf("temp1: %d\n", tmp); + break; + case 2: + /*enable thermal2*/ + writel(T_CONTROL_DATA, TS_DDR_CFG_REG1); + writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL); + ret = readl(SYSCTRL_SEC_STATUS_REG28);/*thermal2 cali data in reg CFG28*/ + mdelay(5); + buf[0] = (ret) & 0xff; + buf[1] = (ret >> 8) & 0xff; + u_efuse = buf[1]; + u_efuse = (u_efuse << 8) | buf[0]; + value_ts = 0; + value_all_ts = 0; + cnt = 0; + for (i = 0; i <= 10; i ++) { + udelay(50); + value_ts = readl(TS_DDR_STAT0) & 0xffff; + } + for (i = 0; i <= T_AVG_NUM; i ++) { + udelay(T_DLY_TIME); + value_ts = readl(TS_DDR_STAT0) & 0xffff; + if ((value_ts >= T_VALUE_MIN) && + (value_ts <= T_VALUE_MAX)) { + value_all_ts += value_ts; + cnt ++; + } + } + value_ts = value_all_ts / cnt; + printf("ddr tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse); + if (value_ts == 0) { + printf("ddr tsensor read temp is zero\n"); + return -1; + } + tmp = r1p1_codetotemp(value_ts, u_efuse); + printf("temp1: %d\n", tmp); + break; + default: + printf("r1p1 tsensor trim type not support\n"); + return -1; + } + return tmp; +} + +unsigned int r1p1_temptocode(unsigned long value, int tempbase) +{ + unsigned long tmp1, tmp2, u_efuse, signbit; + + printf("a b m n: %d, %d, %d, %d\n", ts_a, ts_b, ts_m, ts_n); + tmp1 = ((tempbase * 10 + ts_b) * (1 << 16)) / ts_a; /*ideal u*/ + printf("%s : tmp1: 0x%lx\n", __func__, tmp1); + tmp2 = (ts_m * value * (1 << 16)) / ((1 << 16) * 100 + ts_n * value); + printf("%s : tmp2: 0x%lx\n", __func__, tmp2); + signbit = ((tmp1 > tmp2) ? 0 : 1); + u_efuse = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + u_efuse = (signbit << 15) | u_efuse; + return u_efuse; +} + +int r1p1_temp_trim(int tempbase, int tempver, int type) +{ + unsigned int u_efuse, index_ts, index_ver; + unsigned int value_ts, value_all_ts; + int i, cnt; + + printf("r1p1 temp trim type: 0x%x\n", type); + switch (type) { + case 0: + index_ver = 5; + if (tsensor_tz_calibration(index_ver, tempver) < 0) + printf("version tsensor thermal_calibration send error\n"); + break; + case 1: + value_ts = 0; + value_all_ts = 0; + index_ts = 6; + cnt = 0; + /*enable thermal1*/ + writel(T_CONTROL_DATA, TS_PLL_CFG_REG1); + writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL); + for (i = 0; i <= 10; i ++) { + udelay(50); + value_ts = readl(TS_PLL_STAT0) & 0xffff; + } + for (i = 0; i <= T_AVG_NUM; i ++) { + udelay(T_DLY_TIME); + value_ts = readl(TS_PLL_STAT0) & 0xffff; + printf("pll tsensor read: 0x%x\n", value_ts); + if ((value_ts >= T_VALUE_MIN) && + (value_ts <= T_VALUE_MAX)) { + value_all_ts += value_ts; + cnt ++; + } + } + value_ts = value_all_ts / cnt; + printf("pll tsensor avg: 0x%x\n", value_ts); + if (value_ts == 0) { + printf("pll tsensor read temp is zero\n"); + return -1; + } + u_efuse = r1p1_temptocode(value_ts, tempbase); + printf("ts efuse:%d\n", u_efuse); + printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts); + if (tsensor_tz_calibration(index_ts, u_efuse) < 0) { + printf("pll tsensor thermal_calibration send error\n"); + return -1; + } + break; + case 2: + value_ts = 0; + value_all_ts = 0; + index_ts = 7; + cnt = 0; + /*enable thermal1*/ + writel(T_CONTROL_DATA, TS_DDR_CFG_REG1); + writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL); + for (i = 0; i <= 10; i ++) { + udelay(50); + value_ts = readl(TS_DDR_STAT0) & 0xffff; + } + for (i = 0; i <= T_AVG_NUM; i ++) { + udelay(T_DLY_TIME); + value_ts = readl(TS_DDR_STAT0) & 0xffff; + printf("ddr tsensor read: 0x%x\n", value_ts); + if ((value_ts >= T_VALUE_MIN) && + (value_ts <= T_VALUE_MAX)) { + value_all_ts += value_ts; + cnt ++; + } + } + value_ts = value_all_ts / cnt; + printf("ddr tsensor avg: 0x%x\n", value_ts); + if (value_ts == 0) { + printf("ddr tsensor read temp is zero\n"); + return -1; + } + u_efuse = r1p1_temptocode(value_ts, tempbase); + printf("ts efuse:%d\n", u_efuse); + printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts); + if (tsensor_tz_calibration(index_ts, u_efuse) < 0) { + printf("ddr tsensor thermal_calibration send error\n"); + return -1; + } + break; + default: + printf("r1p1 tsensor trim type not support\n"); + return -1; + break; + } + return 0; +} + +int temp_read_entry(void) +{ + unsigned int ret, ver; + + ret = readl(SYSCTRL_SEC_STATUS_REG10); + ver = (ret >> 24) & 0xff; + if (0 == (ver & T_VER_MASK)) { + printf("tsensor no trimmed: calidata:0x%x\n", + readl(SYSCTRL_SEC_STATUS_REG10)); + return -1; + } + ret = (ver & 0xf) >> 2; + switch (ret) { + case 0x0: + printf("temp type no support\n"); + break; + case 0x1: + printf("temp type no support\n"); + break; + case 0x2: + r1p1_temp_read(1); + r1p1_temp_read(2); + printf("read the thermal\n"); + break; + case 0x3: + printf("temp type no support\n"); + return -1; + break; + default: + printf("thermal version not support!!!Please check!\n"); + return -1; + } + return 0; +} + +int temp_trim_entry(int tempbase, int tempver) +{ + unsigned int ret, ver; + + ret = readl(SYSCTRL_SEC_STATUS_REG10); + ver = (ret >> 24) & 0xff; + if (ver & T_VER_MASK) { + printf("tsensor trimmed: cali data: 0x%x\n", + readl(SYSCTRL_SEC_STATUS_REG10)); + return -1; + } + + printf("tsensor input trim tempver, tempver:0x%x\n", tempver); + switch (tempver) { + case 0x88: + r1p1_temp_trim(tempbase, tempver, 1); + r1p1_temp_trim(tempbase, tempver, 2); + r1p1_temp_trim(tempbase, tempver, 0); + printf("triming the thermal by bbt-sw\n"); + break; + case 0x89: + r1p1_temp_trim(tempbase, tempver, 1); + r1p1_temp_trim(tempbase, tempver, 2); + r1p1_temp_trim(tempbase, tempver, 0); + printf("triming the thermal by bbt-ops\n"); + break; + case 0x8b: + r1p1_temp_trim(tempbase, tempver, 1); + r1p1_temp_trim(tempbase, tempver, 2); + r1p1_temp_trim(tempbase, tempver, 0); + printf("triming the thermal by slt\n"); + break; + default: + printf("thermal version not support!!!Please check!\n"); + return -1; + } + return 0; +} + +int temp_cooling_entry(void) +{ +#ifdef CONFIG_AML_TSENSOR_COOL + int temp, temp1; + + while (1) { + temp = r1p1_temp_read(1); + temp1 = r1p1_temp_read(2); + temp = temp > temp1 ? temp : temp1; + if (temp <= CONFIG_HIGH_TEMP_COOL) { + printf("device cool done\n"); + break; + } + mdelay(2000); + printf("warning: temp %d over %d, cooling\n", temp, + CONFIG_HIGH_TEMP_COOL); + } +#endif + return 0; +}
diff --git a/arch/arm/mach-meson/sc2/usb.c b/arch/arm/mach-meson/sc2/usb.c new file mode 100644 index 0000000..4095ef2 --- /dev/null +++ b/arch/arm/mach-meson/sc2/usb.c
@@ -0,0 +1,466 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <bitfield.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <regmap.h> +#include <power/regulator.h> +#include <clk.h> +#include <asm/arch/usb.h> +#include <amlogic/cpu_id.h> + +#include <linux/compat.h> +#include <linux/ioport.h> +#include <asm-generic/gpio.h> + +#define PHY20_RESET_LEVEL_BIT 8 +#define PHY21_RESET_LEVEL_BIT 9 +#define USB_RESET_BIT 4 + +#define USB2_PHY_PLL_OFFSET_40 (0x09400414) +#define USB2_PHY_PLL_OFFSET_44 (0x927E0000) +#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5) + +#define USB2_PHY_PLL_OFFSET_10 (0x80000fff) +#define USB2_PHY_PLL_OFFSET_34 (0x78000) +#define USB2_REVB_PHY_PLL_OFFSET_34 (0x70000) + +#define USB2_PHY_PLL_OFFSET_38_CLEAR (0) +#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004) +#define USB2_PHY_PLL_OFFSET_50 (0xfe18) +#define USB2_PHY_PLL_OFFSET_54 (0x2a) + +#define TUNING_DISCONNECT_THRESHOLD 0x3C + +static int Rev_flag = 0; + +static struct phy usb_phys[2]; + +/*Rev_flag == 0XB, g12b and revB, tl1 */ +/*Rev_flag == 1, sm1 */ +static void phy_aml_usb2_check_rev (void) +{ + cpu_id_t cpu_id = get_cpu_id(); + + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) { + if (cpu_id.chip_rev == 0xb) + Rev_flag = 0xb; + else + Rev_flag = 0; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1) { + Rev_flag = MESON_CPU_MAJOR_ID_SM1; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_A1) { + Rev_flag = MESON_CPU_MAJOR_ID_A1; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) { + Rev_flag = MESON_CPU_MAJOR_ID_C1; + } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) + Rev_flag = MESON_CPU_MAJOR_ID_SC2; + return; +} + +static int phy_aml_usb2_get_rev_type (void) +{ + int val = 0; + + switch (Rev_flag) { + case MESON_CPU_MAJOR_ID_SM1: + case MESON_CPU_MAJOR_ID_A1: + case MESON_CPU_MAJOR_ID_C1: + case MESON_CPU_MAJOR_ID_SC2: + case 0xb: + val = 1; + break; + default: + printk("amlogic usb phy need tuning\n"); + val = 0; + break; + } + + return val; +} + +int get_usbphy_baseinfo(struct phy *usb_phys) +{ + struct udevice *bus; + struct uclass *uc; + int ret, i; + unsigned int count; + + if (usb_phys[0].dev && usb_phys[1].dev) + return 0; + + ret = uclass_get(UCLASS_USB, &uc); + if (ret) + return ret; + uclass_foreach_dev(bus, uc) { + debug("bus->name=%s, bus->driver->name =%s\n", + bus->name, bus->driver->name); + count = dev_count_phandle_with_args(bus, "phys", "#phy-cells"); + debug("usb phy count=%u\n", count); + if (count <= 0) + return count; + for (i = 0; i < count; i++) { + ret = generic_phy_get_by_index(bus, i, &usb_phys[i]); + if (ret && ret != -ENOENT) { + pr_err("Failed to get USB PHY%d for %s\n", + i, bus->name); + return ret; + } + ret = generic_phy_getinfo(&usb_phys[i]); + if (ret) + return ret; + } + } + return 0; +} + +static void set_pll_Calibration_default(uint32_t phy2_pll_base) +{ + u32 tmp; + + tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8)); + tmp &= 0xfff; + tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) + = tmp; +} + +void usb_reset(unsigned int reset_addr, int bit){ + *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit); +} + +static void usb_enable_phy_pll (void) +{ + *(volatile uint32_t *)(unsigned long)RESETCTRL_RESET0_LEVEL |= (3 << PHY20_RESET_LEVEL_BIT); +} + +static void usb_disable_phy_pll (void) +{ + *(volatile uint32_t *)RESETCTRL_RESET0_LEVEL &= ~(3 << PHY20_RESET_LEVEL_BIT); +} + +void set_usb_pll(uint32_t phy2_pll_base) +{ + int hardware_rev; + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40)) + = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) = + USB2_PHY_PLL_OFFSET_44; + hardware_rev = phy_aml_usb2_get_rev_type(); + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) = + USB2_PHY_PLL_OFFSET_48; + udelay(100); + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40)) + = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE)) + & (~(USB_PHY2_RESET))); + + if (hardware_rev) { + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54)) + = USB2_PHY_PLL_OFFSET_54; + set_pll_Calibration_default(phy2_pll_base); + } else { + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50)) + = USB2_PHY_PLL_OFFSET_50; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10)) + = USB2_PHY_PLL_OFFSET_10; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38)) + = USB2_PHY_PLL_OFFSET_38_CLEAR; + } + + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) = + TUNING_DISCONNECT_THRESHOLD; + (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34)) + = USB2_PHY_PLL_OFFSET_34; + debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD); +} + +int usb_save_phy_dev (unsigned int number, struct phy *phy) +{ + usb_phys[number].dev = phy->dev; + usb_phys[number].id = phy->id; + return 0; +} + +int usb2_phy_init (struct phy *phy) { + struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev); + struct u2p_aml_regs *u2p_aml_reg; + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + int i,cnt; + + usb_save_phy_dev(0, phy); + usb_enable_phy_pll(); + //usb_set_power_domain(); + phy_aml_usb2_check_rev(); + + *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << USB_RESET_BIT); + + udelay(500); + priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT; + priv->usbphy_reset_bit[1] = PHY21_RESET_LEVEL_BIT; + + for (i = 0; i < priv->u2_port_num; i++) { + u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE)); + dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0; + dev_u2p_r0.b.host_device= 1; + dev_u2p_r0.b.POR= 0; + u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32; + udelay(10); + *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << priv->usbphy_reset_bit[i]); + udelay(50); + + /* wait for phy ready */ + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + cnt = 0; + while (dev_u2p_r1.b.phy_rdy != 1) { + dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; + /*we wait phy ready max 1ms, common is 100us*/ + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + } + + for (i = 0; i < priv->u2_port_num; i++) { + debug("------set usb pll\n"); + set_usb_pll(priv->usb_phy2_pll_base_addr[i]); + } + return 0; + +} + +int usb2_phy_tuning(uint32_t phy2_pll_base, int port) +{ + unsigned long phy_reg_base; + unsigned int pll_set38, pll_set34; + unsigned int rev_type = 0; + + if (port > 2) + return 0; + + pll_set38 = USB2_PHY_PLL_OFFSET_38_SET; + pll_set34 = USB2_PHY_PLL_OFFSET_34; + + debug("pll38=0x%08x, pll34=0x%08x,\n", + pll_set38, pll_set34); + + + phy_reg_base = phy2_pll_base; + + rev_type = phy_aml_usb2_get_rev_type(); + if (rev_type) { + return 0; + } + + (*(volatile uint32_t *)(phy_reg_base + 0x38)) = pll_set38; + (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set34; + return 0; +} + +/**************************************************************/ +/* device mode config */ +/**************************************************************/ +unsigned int usb_get_dwc_a_base_addr(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->dwc2_a_addr; +} + +unsigned int usb_get_device_mode_phy_base(void) +{ + struct phy_aml_usb2_priv *usb2_priv; + int ret; + + if (!usb_phys[0].dev) { + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + return usb2_priv->usb_phy2_pll_base_addr[1]; +} + +void usb_phy_tuning_reset(void) +{ + unsigned long phy_reg_base = usb_get_device_mode_phy_base(); + int rev_type; + + if (phy_reg_base == 0) + return; + rev_type = phy_aml_usb2_get_rev_type(); + + if (rev_type) + return; + + (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB2_PHY_PLL_OFFSET_38_CLEAR; + (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB2_PHY_PLL_OFFSET_34; +} + +void usb_device_mode_init(void){ + u2p_r0_t dev_u2p_r0; + u2p_r1_t dev_u2p_r1; + + usb_r0_t dev_usb_r0; + usb_r4_t dev_usb_r4; + int cnt, ret; + u2p_aml_regs_t * u2p_aml_regs; + usb_aml_regs_t *usb_aml_regs; + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + unsigned int phy_base_addr, reset_addr; + + phy_aml_usb2_check_rev(); + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + if (!usb2_priv || !usb3_priv) { + printf("get usb phy address from dts failed\n"); + return; + } + + u2p_aml_regs = (u2p_aml_regs_t * )((unsigned long)(usb2_priv->base_addr + PHY_REGISTER_SIZE)); + usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr); + phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[1]; + reset_addr = usb2_priv->reset_addr; + + //printf("PHY2=0x%08x,PHY3=0x%08x\n", u2p_aml_regs, usb_aml_regs); + printf("PHY2=%p,PHY3=%p\n", u2p_aml_regs, usb_aml_regs); + if ((*(volatile uint32_t *)(unsigned long)(phy_base_addr + 0x38)) != 0) { + usb_phy_tuning_reset(); + mdelay(150); + } + + //step 1: usb controller reset + usb_reset(reset_addr, USB_RESET_BIT); + + // step 3: enable usb INT internal USB + dev_usb_r0.d32 = usb_aml_regs->usb_r0; + dev_usb_r0.b.u2d_ss_scaledown_mode = 0; + dev_usb_r0.b.u2d_act = 1; + usb_aml_regs->usb_r0 = dev_usb_r0.d32; + + // step 4: disable usb phy sleep + dev_usb_r4.d32 = usb_aml_regs->usb_r4; + dev_usb_r4.b.p21_SLEEPM0 = 1; + usb_aml_regs->usb_r4 = dev_usb_r4.d32; + + // step 5: config phy21 device mode + dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; + dev_u2p_r0.b.host_device= 0; + dev_u2p_r0.b.POR= 0; + u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; + + udelay(10); + //step 6: phy21 reset + usb_reset(reset_addr, PHY21_RESET_LEVEL_BIT); + udelay(50); + + // step 6: wait for phy ready + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + cnt = 0; + while ((dev_u2p_r1.d32 & 0x00000001) != 1) { + dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; + if (cnt > 200) + break; + else { + cnt++; + udelay(5); + } + } + + //set_usb_phy21_pll(); + set_usb_pll(phy_base_addr); + //-------------------------------------------------- + + // ------------- usb phy21 initinal end ---------- + + //-------------------------------------------------- + +} + +static void usb_disable_phy(uint32_t phy2_pll_base) +{ + (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))= + ((USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET) & (~USB_PHY2_ENABLE)); + udelay(5); +} + +static void usb_print_usb_baseinfo + (struct phy_aml_usb2_priv *usb2_priv, struct phy_aml_usb3_priv *usb3_priv) +{ + if (usb3_priv) { + printf("priv->usb3 port num = %d, config addr=0x%08x\n", + usb3_priv->usb3_port_num, usb3_priv->base_addr); + } + if (usb2_priv) { + printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n", + usb2_priv->base_addr, usb2_priv->reset_addr); + + printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n", + usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0], + usb2_priv->usb_phy2_pll_base_addr[1]); + printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr); + } + phy_aml_usb2_check_rev(); + printf("PHY version is 0x%02x\n", Rev_flag); +} + +int usb_aml_detect_operation(int argc, char * const argv[]) +{ + struct phy_aml_usb2_priv *usb2_priv; + struct phy_aml_usb3_priv *usb3_priv; + int ret; + + ret = get_usbphy_baseinfo(usb_phys); + if (ret) { + printf("get usb dts failed\n"); + return 0; + } + usb2_priv = dev_get_priv(usb_phys[0].dev); + usb3_priv = dev_get_priv(usb_phys[1].dev); + + if (argc >= 2) { + if (strncmp(argv[1], "disable", 7) == 0) { + usb_disable_phy_pll(); + usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[0]); + usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[1]); + printf("disable USB phy\n"); + return 0; + } + + if (strncmp(argv[1], "info", 4) == 0) { + usb_print_usb_baseinfo(usb2_priv, usb3_priv); + return 0; + } + } + return CMD_RET_USAGE; +} +
diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig index bae5cf2..60b7709 100644 --- a/board/amlogic/Kconfig +++ b/board/amlogic/Kconfig
@@ -35,6 +35,12 @@ help "Support U-boot encrypt function" +config UBOOT_RUN_IN_SRAM + bool "Amlogic U-boot run in sram" + default n + help + "Support Amlogic U-boot run in SRAM" + config AML_TSENSOR bool "Amlogic Temp Sensor" help @@ -137,7 +143,8 @@ config A1_AD401_NAND_RTOS bool "A1_AD401_NAND_RTOS" select TARGET_A1_AD401 - select SPI_NAND + #select SPI_NAND + select MTD_SPI_NAND select SYSTEM_RTOS help Select A1 AD401 NOR RTOS board config @@ -145,7 +152,8 @@ config A1_AD401_NAND_LINUX bool "A1_AD401_NAND_LINUX" select TARGET_A1_AD401 - select SPI_NAND + #select SPI_NAND + select MTD_SPI_NAND help Select A1 AD401 NOR RTOS board config @@ -160,7 +168,8 @@ config A1_AD402_NAND_RTOS bool "A1_AD402_NAND_RTOS" select TARGET_A1_AD402 - select SPI_NAND + #select SPI_NAND + select MTD_SPI_NAND select SYSTEM_RTOS help Select A1 AD402 NOR RTOS board config @@ -168,7 +177,8 @@ config A1_AD402_NAND_LINUX bool "A1_AD402_NAND_LINUX" select TARGET_A1_AD402 - select SPI_NAND + #select SPI_NAND + select MTD_SPI_NAND help Select A1 AD402 NOR RTOS board config @@ -183,7 +193,8 @@ config A1_AD409_NAND_RTOS bool "A1_AD409_NAND_RTOS" select TARGET_A1_AD409 - select SPI_NAND + #select SPI_NAND + select MTD_SPI_NAND select SYSTEM_RTOS help Select A1 AD409 NOR RTOS board config @@ -191,7 +202,8 @@ config A1_AD409_NAND_LINUX bool "A1_AD409_NAND_LINUX" select TARGET_A1_AD409 - select SPI_NAND + #select SPI_NAND + select MTD_SPI_NAND help Select A1 AD409 NOR RTOS board config @@ -285,6 +297,12 @@ help Select C1 AE401 config +config C1_AE402 + bool "C1_AE402" + select TARGET_C1_AE402 + help + Select C1 AE402 config + endchoice config TARGET_C1_AE409 @@ -323,6 +341,313 @@ bool "C1 AE401 board" depends on C1_AE401 +config TARGET_C1_AE402 + bool "C1 AE402 board" + depends on C1_AE402 + +endif + +if MESON_SC2 + +config SYS_SOC + default "sc2" + +config DDRFW_TYPE + string "SC2 DDR FW Type" + default "ddr4" + +config BL30_SELECT + string "SC2 BL30 board config" + default "sc2_ah219" + +choice + prompt "SC2 Board" + +config SC2_SKT + bool "SC2_SKT" + select TARGET_SC2_SKT + help + Select SC2 SKT(XXXX) config + +config SC2_AH219 + bool "SC2_AH219" + select TARGET_SC2_AH219 + help + Select SC2 AH219 config + +config SC2_AH212 + bool "SC2_AH212" + select TARGET_SC2_AH212 + help + Select SC2 AH212 config + +config SC2_AH212_DDR3 + bool "SC2_AH212_DDR3" + select TARGET_SC2_AH212_DDR3 + help + Select SC2 AH212 DDR3 config + +config SC2_AH212_LPDDR3 + bool "SC2_AH212_LPDDR3" + select TARGET_SC2_AH212_LPDDR3 + help + Select SC2 AH212 LPDDR3 config + +config SC2_AH212_LPDDR4 + bool "SC2_AH212_LPDDR4" + select TARGET_SC2_AH212_LPDDR4 + help + Select SC2 AH212 LPDDR4 config + +endchoice + +config TARGET_SC2_SKT + bool "SC2 SKT board" + depends on SC2_SKT + +config TARGET_SC2_AH219 + bool "SC2 AH219 board" + depends on SC2_AH219 + +config TARGET_SC2_AH212 + bool "SC2 AH212 board" + depends on SC2_AH212 + +config TARGET_SC2_AH212_DDR3 + bool "SC2 AH212 ddr3 board" + depends on SC2_AH212_DDR3 + +config TARGET_SC2_AH212_LPDDR3 + bool "SC2 AH212 lpddr3 board" + depends on SC2_AH212_LPDDR3 + +config TARGET_SC2_AH212_LPDDR4 + bool "SC2 AH212 lpddr4 board" + depends on SC2_AH212_LPDDR4 + +endif + +if MESON_C2 + +config SYS_SOC + default "c2" + +choice + prompt "C2 Board" + +config C2_SKT + bool "C2_SKT" + select TARGET_C2_SKT + help + Select C2 SKT config mainly for pxp + +config C2_AF409 + bool "C2_AF409" + select TARGET_C2_AF409 + help + Select C2_AF409 (SKT) config + +config C2_AF400 + bool "C2_AF400" + select TARGET_C2_AF400 + help + Select C2_AF400 config + +config C2_AF401 + bool "C2_AF401" + select TARGET_C2_AF401 + help + Select C2_AF401 config + +config C2_AF419 + bool "C2_AF419" + select TARGET_C2_AF419 + help + Select C2_AF419 config + +config C2_A049_P0 + bool "C2_A049_P0" + select TARGET_C2_A049_P0 + help + Select C2 A049 P0 config + +config C2_BSV3_P1 + bool "C2_BSV3_P1" + select TARGET_C2_BSV3_P1 + help + Select C2 BSV3 P1 config + +config C2_SPENCER_P1 + bool "C2_SPENCER_P1" + select TARGET_C2_SPENCER_P1 + help + Select C2 SPENCER P1 config + +config C2_SPENCER_P2 + bool "C2_SPENCER_P2" + select TARGET_C2_SPENCER_P2 + help + Select C2 SPENCER P2 config + +config C2_SPENCER_BX + bool "C2_SPENCER_BX" + select TARGET_C2_SPENCER_BX + help + Select C2 SPENCER BX config + +config C2_VENUS_P1 + bool "C2_VENUS_P1" + select TARGET_C2_VENUS_P1 + help + Select C2 VENUS P1 config + +config C2_VENUS_P2 + bool "C2_VENUS_P2" + select TARGET_C2_VENUS_P2 + help + Select C2 VENUS P2 config + +config C2_VENUS_BX + bool "C2_VENUS_BX" + select TARGET_C2_VENUS_BX + help + Select C2 VENUS BX config + +config C2_BLA4_P0 + bool "C2_BLA4_P0" + select TARGET_C2_BLA4_P0 + help + Select C2 BLA4 P0 config + +config C2_BLA4_P1 + bool "C2_BLA4_P1" + select TARGET_C2_BLA4_P1 + help + Select C2 BLA4 P1 config + +config C2_BLA4_P2 + bool "C2_BLA4_P2" + select TARGET_C2_BLA4_P2 + help + Select C2 BLA4 P2 config + +config C2_BLA4_BX + bool "C2_BLA4_BX" + select TARGET_C2_BLA4_BX + help + Select C2 BLA4 BX config + +config C2_2RS4_P1 + bool "C2_2RS4_P1" + select TARGET_C2_2RS4_P1 + help + Select C2 2RS4 P1 config + +config C2_2RS4_P2 + bool "C2_2RS4_P2" + select TARGET_C2_2RS4_P2 + help + Select C2 2RS4 P2 config + +config C2_XUA4_P1 + bool "C2_XUA4_P1" + select TARGET_C2_XUA4_P1 + help + Select C2 XUA4 P1 config + +config C2_XUA4_BX + bool "C2_XUA4_BX" + select TARGET_C2_XUA4_BX + help + Select C2 XUA4 BX config + +endchoice + +config TARGET_C2_SKT + bool "C2 SKT board" + depends on C2_SKT + +config TARGET_C2_AF409 + bool "C2 AF409 board" + depends on C2_AF409 + + +config TARGET_C2_AF400 + bool "C2 AF400 board" + depends on C2_AF400 + +config TARGET_C2_AF401 + bool "C2 AF401 board" + depends on C2_AF401 + +config TARGET_C2_AF419 + bool "C2 AF419 board" + depends on C2_AF419 + +config TARGET_C2_A049_P0 + bool "C2 A049 P0 board" + depends on C2_A049_P0 + +config TARGET_C2_BSV3_P1 + bool "C2 BSV3 P1 board" + depends on C2_BSV3_P1 + +config TARGET_C2_SPENCER_P1 + bool "C2 SPENCER P1 board" + depends on C2_SPENCER_P1 + +config TARGET_C2_SPENCER_P2 + bool "C2 SPENCER P2 board" + depends on C2_SPENCER_P2 + +config TARGET_C2_SPENCER_BX + bool "C2 SPENCER BX board" + depends on C2_SPENCER_BX + +config TARGET_C2_VENUS_P1 + bool "C2 VENUS P1 board" + depends on C2_VENUS_P1 + +config TARGET_C2_VENUS_P2 + bool "C2 VENUS P2 board" + depends on C2_VENUS_P2 + +config TARGET_C2_VENUS_BX + bool "C2 VENUS BX board" + depends on C2_VENUS_BX + +config TARGET_C2_BLA4_P0 + bool "C2 BLA4 P0 board" + depends on C2_BLA4_P0 + +config TARGET_C2_BLA4_P1 + bool "C2 BLA4 P1 board" + depends on C2_BLA4_P1 + +config TARGET_C2_BLA4_P2 + bool "C2 BLA4 P2 board" + depends on C2_BLA4_P2 + +config TARGET_C2_BLA4_BX + bool "C2 BLA4 BX board" + depends on C2_BLA4_BX + +config TARGET_C2_2RS4_P1 + bool "C2 2RS4 P1 board" + depends on C2_2RS4_P1 + +config TARGET_C2_2RS4_P2 + bool "C2 2RS4 P2 board" + depends on C2_2RS4_P2 + +config TARGET_C2_XUA4_P1 + bool "C2 XUA4 P1 board" + depends on C2_XUA4_P1 + +config TARGET_C2_XUA4_BX + bool "C2 XUA4 BX board" + depends on C2_XUA4_BX + endif if MESON_G12A @@ -363,6 +688,8 @@ source "board/amlogic/c1_ae401/Kconfig" +source "board/amlogic/c1_ae402/Kconfig" + source "board/amlogic/c1_ae409/Kconfig" source "board/amlogic/c1_nq_p2/Kconfig" @@ -373,6 +700,60 @@ source "board/amlogic/c1_gq_bx/Kconfig" +source "board/amlogic/sc2_skt/Kconfig" + +source "board/amlogic/sc2_ah219/Kconfig" + +source "board/amlogic/sc2_ah212/Kconfig" + +source "board/amlogic/sc2_ah212_ddr3/Kconfig" + +source "board/amlogic/sc2_ah212_lpddr3/Kconfig" + +source "board/amlogic/sc2_ah212_lpddr4/Kconfig" + +source "board/amlogic/c2_skt/Kconfig" + +source "board/amlogic/c2_af409/Kconfig" + +source "board/amlogic/c2_af400/Kconfig" + +source "board/amlogic/c2_af401/Kconfig" + +source "board/amlogic/c2_af419/Kconfig" + +source "board/amlogic/c2_a049_p0/Kconfig" + +source "board/amlogic/c2_bsv3_p1/Kconfig" + +source "board/amlogic/c2_spencer_p1/Kconfig" + +source "board/amlogic/c2_spencer_p2/Kconfig" + +source "board/amlogic/c2_spencer_bx/Kconfig" + +source "board/amlogic/c2_venus_p1/Kconfig" + +source "board/amlogic/c2_venus_p2/Kconfig" + +source "board/amlogic/c2_venus_bx/Kconfig" + +source "board/amlogic/c2_bla4_p0/Kconfig" + +source "board/amlogic/c2_bla4_p1/Kconfig" + +source "board/amlogic/c2_bla4_p2/Kconfig" + +source "board/amlogic/c2_bla4_bx/Kconfig" + +source "board/amlogic/c2_2rs4_p1/Kconfig" + +source "board/amlogic/c2_2rs4_p2/Kconfig" + +source "board/amlogic/c2_xua4_p1/Kconfig" + +source "board/amlogic/c2_xua4_bx/Kconfig" + source "board/amlogic/g12a_u200_v1/Kconfig" source "board/amlogic/g12b_w400_v1/Kconfig"
diff --git a/board/amlogic/a1_ad401/a1_ad401.c b/board/amlogic/a1_ad401/a1_ad401.c index a1bee12..feb5708 100644 --- a/board/amlogic/a1_ad401/a1_ad401.c +++ b/board/amlogic/a1_ad401/a1_ad401.c
@@ -135,17 +135,19 @@ phys_size_t get_effective_memsize(void) { -#ifdef UBOOT_RUN_IN_SRAM +#ifdef CONFIG_UBOOT_RUN_IN_SRAM return 0x180000; /* SRAM 1.5MB */ #else return get_dram_size(); -#endif /* UBOOT_RUN_IN_SRAM */ +#endif /* CONFIG_UBOOT_RUN_IN_SRAM */ } +#ifdef CONFIG_UBOOT_RUN_IN_SRAM ulong board_get_usable_ram_top(ulong total_size) { - return PHYS_SDRAM_1_BASE+PHYS_SDRAM_1_SIZE; + return (PHYS_SDRAM_1_BASE+PHYS_SDRAM_1_SIZE); } +#endif int dram_init_banksize(void) { @@ -195,7 +197,7 @@ /* partition table */ /* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) #ifdef CONFIG_SYSTEM_RTOS static const struct mtd_partition spinand_partitions[] = { { @@ -235,12 +237,12 @@ { .name = "recovery", .offset = 0, - .size = 12 * SZ_1M, + .size = 13 * SZ_1M, }, { .name = "boot", .offset = 0, - .size = 11 * SZ_1M, + .size = 10 * SZ_1M, }, { .name = "system", @@ -255,7 +257,7 @@ } }; #endif /*CONFIG_SYSTEM_RTOS*/ -struct mtd_partition *get_partition_table(int *partitions) +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spinand_partitions); return spinand_partitions; @@ -297,11 +299,17 @@ .size = MTDPART_SIZ_FULL, } }; -struct mtd_partition *get_partition_table(int *partitions) + +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spiflash_partitions); return spiflash_partitions; } + +uint64_t spiflash_bootloader_size(void) +{ + return 1 * SZ_1M; +} #endif /* CONFIG_SPI_FLASH */ int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
diff --git a/board/amlogic/a1_ad401/firmware/timing.c b/board/amlogic/a1_ad401/firmware/timing.c index fc37b05..5b289ad 100644 --- a/board/amlogic/a1_ad401/firmware/timing.c +++ b/board/amlogic/a1_ad401/firmware/timing.c
@@ -73,7 +73,7 @@ #endif /* please config __psram_setting[] if board use psram */ -ddr_set_t __ddr_setting[] = { +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { { /* ddr3 */ .board_id = CONFIG_BOARD_ID_MASK,
diff --git a/board/amlogic/a1_ad402/a1_ad402.c b/board/amlogic/a1_ad402/a1_ad402.c index a1bee12..47d773d 100644 --- a/board/amlogic/a1_ad402/a1_ad402.c +++ b/board/amlogic/a1_ad402/a1_ad402.c
@@ -135,17 +135,19 @@ phys_size_t get_effective_memsize(void) { -#ifdef UBOOT_RUN_IN_SRAM +#ifdef CONFIG_UBOOT_RUN_IN_SRAM return 0x180000; /* SRAM 1.5MB */ #else return get_dram_size(); -#endif /* UBOOT_RUN_IN_SRAM */ +#endif /* CONFIG_UBOOT_RUN_IN_SRAM */ } +#ifdef CONFIG_UBOOT_RUN_IN_SRAM ulong board_get_usable_ram_top(ulong total_size) { - return PHYS_SDRAM_1_BASE+PHYS_SDRAM_1_SIZE; + return (PHYS_SDRAM_1_BASE + PHYS_SDRAM_1_SIZE); } +#endif int dram_init_banksize(void) { @@ -195,7 +197,7 @@ /* partition table */ /* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) #ifdef CONFIG_SYSTEM_RTOS static const struct mtd_partition spinand_partitions[] = { { @@ -235,12 +237,12 @@ { .name = "recovery", .offset = 0, - .size = 12 * SZ_1M, + .size = 13 * SZ_1M, }, { .name = "boot", .offset = 0, - .size = 11 * SZ_1M, + .size = 10 * SZ_1M, }, { .name = "system", @@ -255,7 +257,7 @@ } }; #endif /*CONFIG_SYSTEM_RTOS*/ -struct mtd_partition *get_partition_table(int *partitions) +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spinand_partitions); return spinand_partitions; @@ -297,11 +299,17 @@ .size = MTDPART_SIZ_FULL, } }; -struct mtd_partition *get_partition_table(int *partitions) + +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spiflash_partitions); return spiflash_partitions; } + +uint64_t spiflash_bootloader_size(void) +{ + return 1 * SZ_1M; +} #endif /* CONFIG_SPI_FLASH */ int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
diff --git a/board/amlogic/a1_ad402/aml-user-key.sig b/board/amlogic/a1_ad402/aml-user-key.sig old mode 100644 new mode 100755 index 71e4c63..ceac711 --- a/board/amlogic/a1_ad402/aml-user-key.sig +++ b/board/amlogic/a1_ad402/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/a1_ad402/firmware/timing.c b/board/amlogic/a1_ad402/firmware/timing.c index ce37e5a..eac89ca 100644 --- a/board/amlogic/a1_ad402/firmware/timing.c +++ b/board/amlogic/a1_ad402/firmware/timing.c
@@ -73,7 +73,7 @@ #endif /* please config __psram_setting[] if board use psram */ -ddr_set_t __ddr_setting[] = { +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { { /* ddr3 */ .board_id = CONFIG_BOARD_ID_MASK, @@ -287,95 +287,15 @@ {0, 0, 0, 0, 0, 0}, }; -#define VCCK_VAL AML_VCCK_INIT_VOLTAGE -#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE -/* VCCK PWM table */ -#if (VCCK_VAL == 800) - #define VCCK_VAL_REG 0x00150007 -#elif (VCCK_VAL == 810) - #define VCCK_VAL_REG 0x00140008 -#elif (VCCK_VAL == 820) - #define VCCK_VAL_REG 0x00130009 -#elif (VCCK_VAL == 830) - #define VCCK_VAL_REG 0x0012000a -#elif (VCCK_VAL == 840) - #define VCCK_VAL_REG 0x0011000b -#elif (VCCK_VAL == 850) - #define VCCK_VAL_REG 0x0010000c -#elif (VCCK_VAL == 860) - #define VCCK_VAL_REG 0x000f000d -#elif (VCCK_VAL == 870) - #define VCCK_VAL_REG 0x000e000e -#elif (VCCK_VAL == 880) - #define VCCK_VAL_REG 0x000d000f -#elif (VCCK_VAL == 890) - #define VCCK_VAL_REG 0x000c0010 -#elif (VCCK_VAL == 900) - #define VCCK_VAL_REG 0x000b0011 -#elif (VCCK_VAL == 910) - #define VCCK_VAL_REG 0x000a0012 -#elif (VCCK_VAL == 920) - #define VCCK_VAL_REG 0x00090013 -#elif (VCCK_VAL == 930) - #define VCCK_VAL_REG 0x00080014 -#elif (VCCK_VAL == 940) - #define VCCK_VAL_REG 0x00070015 -#elif (VCCK_VAL == 950) - #define VCCK_VAL_REG 0x00060016 -#elif (VCCK_VAL == 960) - #define VCCK_VAL_REG 0x00050017 -#elif (VCCK_VAL == 970) - #define VCCK_VAL_REG 0x00040018 -#elif (VCCK_VAL == 980) - #define VCCK_VAL_REG 0x00030019 -#elif (VCCK_VAL == 990) - #define VCCK_VAL_REG 0x0002001a -#elif (VCCK_VAL == 1000) - #define VCCK_VAL_REG 0x0001001b -#elif (VCCK_VAL == 1010) - #define VCCK_VAL_REG 0x0000001c -#else - #error "VCCK val out of range\n" -#endif - -/* VDDEE PWM table */ -#if (VDDEE_VAL == 800) - #define VDDEE_VAL_REG 0x0010000c -#elif (VDDEE_VAL == 810) - #define VDDEE_VAL_REG 0x000f000d -#elif (VDDEE_VAL == 820) - #define VDDEE_VAL_REG 0x000e000e -#elif (VDDEE_VAL == 830) - #define VDDEE_VAL_REG 0x000d000f -#elif (VDDEE_VAL == 840) - #define VDDEE_VAL_REG 0x000c0010 -#elif (VDDEE_VAL == 850) - #define VDDEE_VAL_REG 0x000b0011 -#elif (VDDEE_VAL == 860) - #define VDDEE_VAL_REG 0x000a0012 -#elif (VDDEE_VAL == 870) - #define VDDEE_VAL_REG 0x00090013 -#elif (VDDEE_VAL == 880) - #define VDDEE_VAL_REG 0x00080014 -#elif (VDDEE_VAL == 890) - #define VDDEE_VAL_REG 0x00070015 -#elif (VDDEE_VAL == 900) - #define VDDEE_VAL_REG 0x00060016 -#elif (VDDEE_VAL == 910) - #define VDDEE_VAL_REG 0x00050017 -#elif (VDDEE_VAL == 920) - #define VDDEE_VAL_REG 0x00040018 -#elif (VDDEE_VAL == 930) - #define VDDEE_VAL_REG 0x00030019 -#elif (VDDEE_VAL == 940) - #define VDDEE_VAL_REG 0x0002001a -#elif (VDDEE_VAL == 950) - #define VDDEE_VAL_REG 0x0001001b -#elif (VDDEE_VAL == 960) - #define VDDEE_VAL_REG 0x0000001c -#else - #error "VDDEE val out of range\n" -#endif +#define VDDCORE_VAL AML_VDDCORE_INIT_VOLTAGE +/* If AML_VDDCORE_INIT_VOLTAGE_SEL is 1, the voltage of vddcore + * will be controlled by efuse. if 0, it is controlled by + * AML_VDDCORE_INIT_VOLTAGE + */ +#define VDD_VAL_SEL AML_VDDCORE_INIT_VOLTAGE_SEL +#define BL2_EE_ADD AML_VDDCORE_INIT_EFUSE_MARGIN /* margin */ +#define FT_VMIN_OFFSET AML_VDDCORE_INIT_EFUSE_OFFSET /*vmin efuse offset*/ +#define FT_BASE_VOLT AML_VDDCORE_INIT_EFUSE_BASE_V0LT /* for PWM use */ /* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ @@ -385,6 +305,14 @@ #define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2))) #define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2))) +#define P_PADCTRL_PIN_MUX_REG7 0xfe00041c +#define P_PADCTRL_GPIOF_DS 0xfe000554 +#define CLK_PWM_CLK_EF_CTRL ((0x0033 << 2) + 0xfe000800) +#define P_PWMEF_MISC_REG_EF 0xfe005408 +#define VDDCORE_TABLE_END 0XFFFFFFFF +#define P_PWMEF_PWM_F 0xfe005404 + + bl2_reg_t __bl2_reg[] = { /* demo, user defined override register */ {0, 0, 0xffffffff, 0, 0, 0}, @@ -405,4 +333,37 @@ {PADCTRL_GPIOF_O, 1 << 11, 0, 0, BL2_INIT_STAGE_POWERKEY_INIT | POWERKEY_CFG0, 0}, /* power key up config*/ + /* vddcore voltage init, controled by pwm f, + * Do not initialize the pwm duty register here, + * initialize in bl2 according to efuse + */ + {P_PWMEF_MISC_REG_EF, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0}, + {CLK_PWM_CLK_EF_CTRL, 1 << 24 , ((0x3 << 25) | (0xff << 16)), 0, BL2_INIT_STAGE_1, 0}, + {P_PADCTRL_GPIOF_DS, 0x3 << 24, 0x3 << 24, 0, BL2_INIT_STAGE_1, 0}, + {P_PADCTRL_PIN_MUX_REG7,(0x2 << 16), (0xf << 16), 0, BL2_INIT_STAGE_1, 0}, + + /* Transfer voltage table temporarily use __bl2_reg to transfer */ + {0x00000022, 1041, 0x00010021, 1031, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x00020020, 1021, 0x0003001f, 1011, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0004001e, 1001, 0x0005001d, 990, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0006001c, 980, 0x0007001b, 970, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0008001a, 960, 0x00090019, 950, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x000a0018, 940, 0x000b0017, 930, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x000c0016, 920, 0x000d0015, 910, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x000e0014, 900, 0x000f0013, 890, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x00100012, 880, 0x00110011, 870, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x00120010, 860, 0x0013000f, 850, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0014000e, 840, 0x0015000d, 830, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0016000c, 820, 0x0017000b, 810, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0018000a, 800, 0x00190009, 790, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x001a0008, 780, 0x001b0007, 770, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x001c0006, 760, 0x001d0005, 750, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x001e0004, 740, 0x001f0003, 730, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x00200002, 720, 0x00210001, 710, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + /* If there are invalid parameters at the end, use VDDCORE_TABLE_END to fill */ + {0x00220000, 700, VDDCORE_TABLE_END, 0, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + + /* Transfer customer voltage, pwm duty register addr, sel flag */ + {P_PWMEF_PWM_F, VDDCORE_VAL, VDD_VAL_SEL, 0, BL2_INIT_STAGE_VDDCORE_CONFIG, 0}, + {BL2_EE_ADD, FT_VMIN_OFFSET, FT_BASE_VOLT, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, };
diff --git a/board/amlogic/a1_ad409/a1_ad409.c b/board/amlogic/a1_ad409/a1_ad409.c index 5b810e0..14000cd 100644 --- a/board/amlogic/a1_ad409/a1_ad409.c +++ b/board/amlogic/a1_ad409/a1_ad409.c
@@ -134,17 +134,19 @@ phys_size_t get_effective_memsize(void) { -#ifdef UBOOT_RUN_IN_SRAM +#ifdef CONFIG_UBOOT_RUN_IN_SRAM return 0x180000; /* SRAM 1.5MB */ #else return get_dram_size(); -#endif /* UBOOT_RUN_IN_SRAM */ +#endif /* CONFIG_UBOOT_RUN_IN_SRAM */ } +#ifdef CONFIG_UBOOT_RUN_IN_SRAM ulong board_get_usable_ram_top(ulong total_size) { - return PHYS_SDRAM_1_BASE+PHYS_SDRAM_1_SIZE; + return (PHYS_SDRAM_1_BASE + PHYS_SDRAM_1_SIZE); } +#endif int dram_init_banksize(void) { @@ -201,7 +203,7 @@ /* partition table */ /* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) #ifdef CONFIG_SYSTEM_RTOS static const struct mtd_partition spinand_partitions[] = { { @@ -261,7 +263,7 @@ } }; #endif /*CONFIG_SYSTEM_RTOS*/ -struct mtd_partition *get_partition_table(int *partitions) +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spinand_partitions); return spinand_partitions; @@ -308,11 +310,17 @@ .size = MTDPART_SIZ_FULL, } }; -struct mtd_partition *get_partition_table(int *partitions) + +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spiflash_partitions); return spiflash_partitions; } + +uint64_t spiflash_bootloader_size(void) +{ + return 1 * SZ_1M; +} #endif /* CONFIG_SPI_FLASH */ int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
diff --git a/board/amlogic/a1_ad409/firmware/timing.c b/board/amlogic/a1_ad409/firmware/timing.c index f42c28b..e4d410b 100644 --- a/board/amlogic/a1_ad409/firmware/timing.c +++ b/board/amlogic/a1_ad409/firmware/timing.c
@@ -85,7 +85,7 @@ #endif /* please config __psram_setting[] if board use psram */ -ddr_set_t __ddr_setting[] = { +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { { /* ddr3 */ .board_id = CONFIG_BOARD_ID_MASK, @@ -308,80 +308,14 @@ }; #define VDDCORE_VAL AML_VDDCORE_INIT_VOLTAGE -/* VDDCORE PWM table */ -#if (VDDCORE_VAL == 1039) - #define VDDCORE_VAL_REG 0x00000022 -#elif (VDDCORE_VAL == 1029) - #define VDDCORE_VAL_REG 0x00010021 -#elif (VDDCORE_VAL == 1019) - #define VDDCORE_VAL_REG 0x00020020 -#elif (VDDCORE_VAL == 1009) - #define VDDCORE_VAL_REG 0x0003001f -#elif (VDDCORE_VAL == 999) - #define VDDCORE_VAL_REG 0x0004001e -#elif (VDDCORE_VAL == 989) - #define VDDCORE_VAL_REG 0x0005001d -#elif (VDDCORE_VAL == 978) - #define VDDCORE_VAL_REG 0x0006001c -#elif (VDDCORE_VAL == 968) - #define VDDCORE_VAL_REG 0x0007001b -#elif (VDDCORE_VAL == 958) - #define VDDCORE_VAL_REG 0x0008001a -#elif (VDDCORE_VAL == 948) - #define VDDCORE_VAL_REG 0x00090019 -#elif (VDDCORE_VAL == 938) - #define VDDCORE_VAL_REG 0x000a0018 -#elif (VDDCORE_VAL == 927) - #define VDDCORE_VAL_REG 0x000b0017 -#elif (VDDCORE_VAL == 917) - #define VDDCORE_VAL_REG 0x000c0016 -#elif (VDDCORE_VAL == 907) - #define VDDCORE_VAL_REG 0x000d0015 -#elif (VDDCORE_VAL == 897) - #define VDDCORE_VAL_REG 0x000e0014 -#elif (VDDCORE_VAL == 887) - #define VDDCORE_VAL_REG 0x000f0013 -#elif (VDDCORE_VAL == 876) - #define VDDCORE_VAL_REG 0x00100012 -#elif (VDDCORE_VAL == 866) - #define VDDCORE_VAL_REG 0x00110011 -#elif (VDDCORE_VAL == 856) - #define VDDCORE_VAL_REG 0x00120010 -#elif (VDDCORE_VAL == 846) - #define VDDCORE_VAL_REG 0x0013000f -#elif (VDDCORE_VAL == 836) - #define VDDCORE_VAL_REG 0x0014000e -#elif (VDDCORE_VAL == 826) - #define VDDCORE_VAL_REG 0x0015000d -#elif (VDDCORE_VAL == 815) - #define VDDCORE_VAL_REG 0x0016000c -#elif (VDDCORE_VAL == 805) - #define VDDCORE_VAL_REG 0x0017000b -#elif (VDDCORE_VAL == 795) - #define VDDCORE_VAL_REG 0x0018000a -#elif (VDDCORE_VAL == 785) - #define VDDCORE_VAL_REG 0x00190009 -#elif (VDDCORE_VAL == 775) - #define VDDCORE_VAL_REG 0x001a0008 -#elif (VDDCORE_VAL == 764) - #define VDDCORE_VAL_REG 0x001b0007 -#elif (VDDCORE_VAL == 754) - #define VDDCORE_VAL_REG 0x001c0006 -#elif (VDDCORE_VAL == 744) - #define VDDCORE_VAL_REG 0x001d0005 -#elif (VDDCORE_VAL == 734) - #define VDDCORE_VAL_REG 0x001e0004 -#elif (VDDCORE_VAL == 724) - #define VDDCORE_VAL_REG 0x001f0003 -#elif (VDDCORE_VAL == 714) - #define VDDCORE_VAL_REG 0x00200002 -#elif (VDDCORE_VAL == 703) - #define VDDCORE_VAL_REG 0x00210001 -#elif (VDDCORE_VAL == 693) - #define VDDCORE_VAL_REG 0x00220000 -#else - #error "VDDCORE val out of range\n" -#endif +/* If AML_VDDCORE_INIT_VOLTAGE_SEL is 1, the voltage of vddcore + * will be controlled by efuse. if 0, it is controlled by + * AML_VDDCORE_INIT_VOLTAGE + */ +#define VDD_VAL_SEL AML_VDDCORE_INIT_VOLTAGE_SEL +#define BL2_EE_ADD AML_VDDCORE_INIT_EFUSE_MARGIN /* margin */ +#define FT_VMIN_OFFSET AML_VDDCORE_INIT_EFUSE_OFFSET /*vmin efuse offset*/ +#define FT_BASE_VOLT AML_VDDCORE_INIT_EFUSE_BASE_V0LT /* for PWM use */ /* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ @@ -393,14 +327,43 @@ #define P_PWMAB_PWM_A 0xfe002400 //#define P_PWMAB_PWM_B 0xfe002404 #define P_PWMAB_MISC_REG_AB 0xfe002408 +#define VDDCORE_TABLE_END 0XFFFFFFFF bl2_reg_t __bl2_reg[] = { /* demo, user defined override register */ {0, 0, 0xffffffff, 0, 0, 0}, - /* vddcore voltage init, controled by pwm A */ - {P_PWMAB_PWM_A, VDDCORE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, - {P_PWMAB_MISC_REG_AB, ((1 << 15) | (1 << 0)), 0x7f, 0, BL2_INIT_STAGE_1, 0}, - {CLK_PWM_CLK_AB_CTRL, 1 << 8 , 0x3ff | 0x1 << 15, 0, BL2_INIT_STAGE_1, 0}, + /* vddcore voltage init, controled by pwm A, + * Do not initialize the pwm duty register here, + * initialize in bl2 according to efuse + */ + /*{P_PWMAB_PWM_A, 0x0017000b, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},*/ + {P_PWMAB_MISC_REG_AB, ((1 << 15) | (1 << 0)), (0x7f << 8), 0, BL2_INIT_STAGE_1, 0}, + {CLK_PWM_CLK_AB_CTRL, 1 << 8 , ((0x3 << 9) | (0xff << 0)), 0, BL2_INIT_STAGE_1, 0}, {P_PADCTRL_GPIOF_DS, 0x3 << 20, 0x3 << 20, 0, BL2_INIT_STAGE_1, 0}, {P_PADCTRL_PIN_MUX_REG7,(0x1 << 8), (0xf << 8), 0, BL2_INIT_STAGE_1, 0}, + + /* Transfer voltage table temporarily use __bl2_reg to transfer */ + {0x00000022, 1039, 0x00010021, 1029, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x00020020, 1019, 0x0003001f, 1009, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0004001e, 999, 0x0005001d, 989, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0006001c, 978, 0x0007001b, 968, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0008001a, 958, 0x00090019, 948, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x000a0018, 938, 0x000b0017, 927, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x000c0016, 917, 0x000d0015, 907, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x000e0014, 897, 0x000f0013, 887, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x00100012, 876, 0x00110011, 866, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x00120010, 856, 0x0013000f, 846, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0014000e, 836, 0x0015000d, 826, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0016000c, 815, 0x0017000b, 805, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x0018000a, 795, 0x00190009, 785, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x001a0008, 775, 0x001b0007, 764, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x001c0006, 754, 0x001d0005, 744, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x001e0004, 734, 0x001f0003, 724, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + {0x00200002, 714, 0x00210001, 703, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + /* If there are invalid parameters at the end, use VDDCORE_TABLE_END to fill */ + {0x00220000, 693, VDDCORE_TABLE_END, 0, BL2_INIT_STAGE_VDDCORE_TABLE, 0}, + + /* Transfer customer voltage, pwm duty register addr, sel flag */ + {P_PWMAB_PWM_A, VDDCORE_VAL, VDD_VAL_SEL, 0, BL2_INIT_STAGE_VDDCORE_CONFIG, 0}, + {BL2_EE_ADD, FT_VMIN_OFFSET, FT_BASE_VOLT, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, };
diff --git a/board/amlogic/c1_ae400/c1_ae400.c b/board/amlogic/c1_ae400/c1_ae400.c index d84d1a7..e2cdc91 100644 --- a/board/amlogic/c1_ae400/c1_ae400.c +++ b/board/amlogic/c1_ae400/c1_ae400.c
@@ -95,6 +95,9 @@ pinctrl_devices_active(PIN_CONTROLLER_NUM); active_clk(); + run_command("gpio c GPIOA_10", 0); + run_command("gpio c GPIOA_12", 0); + return 0; } @@ -173,9 +176,92 @@ return 0; } +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 1 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +/* +* mtd nand partition table, only care the size! +* offset will be calculated by nand driver. +*/ +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif + /* partition table */ /* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) static const struct mtd_partition spinand_partitions[] = { { .name = "logo", @@ -204,7 +290,7 @@ .size = MTDPART_SIZ_FULL, } }; -struct mtd_partition *get_partition_table(int *partitions) +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spinand_partitions); return spinand_partitions;
diff --git a/board/amlogic/c1_ae400/firmware/ramdump.c b/board/amlogic/c1_ae400/firmware/ramdump.c new file mode 100644 index 0000000..d0ae3ff --- /dev/null +++ b/board/amlogic/c1_ae400/firmware/ramdump.c
@@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifdef CONFIG_MDUMP_COMPRESS +#include "ramdump.h" + +struct ram_compress_full __ramdump_data = { + .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR, + .full_memsize = CONFIG_DDR_TOTAL_SIZE, + .section_count = CONFIG_COMPRESS_SECTION, + .sections = { + { + /* memory afer compressed data address */ + .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR, + .section_size = CONFIG_DDR_TOTAL_SIZE - + CONFIG_COMPRESSED_DATA_ADDR, + .section_index = 4, + .compress_type = RAM_COMPRESS_NORMAL, + }, + { + /* memory before bl2 */ + .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR, + .section_size = CONFIG_BL2_IGNORE_ADDR - + CONFIG_COMPRESS_START_ADDR, + .section_index = 1, + .compress_type = RAM_COMPRESS_NORMAL, + }, + { + /* memory in reserved bl2 */ + .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR, + .section_size = CONFIG_BL2_IGNORE_SIZE, + .section_index = 2, + .compress_type = RAM_COMPRESS_SET, + .set_value = 0x0, + }, + { + /* segment 4: normal compress */ + .phy_addr = (void *)CONFIG_SEG4_ADDR, + .section_size = CONFIG_COMPRESSED_DATA_ADDR - + CONFIG_SEG4_ADDR, + .section_index = 3, + .compress_type = RAM_COMPRESS_NORMAL, + } + }, +}; +#endif /* CONFIG_MDUMP_COMPRESS */ +
diff --git a/board/amlogic/c1_ae400/firmware/ramdump.h b/board/amlogic/c1_ae400/firmware/ramdump.h new file mode 100644 index 0000000..de49681 --- /dev/null +++ b/board/amlogic/c1_ae400/firmware/ramdump.h
@@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __RAM_DUMP_H__ +#define __RAM_DUMP_H__ + +#include <config.h> +#ifdef CONFIG_MDUMP_COMPRESS +#define CONFIG_COMPRESS_SECTION 4 + +#if CONFIG_COMPRESS_SECTION > 8 +#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8 +#endif +/* + * Full Memory lay out for RAM compress: + * + * DDR_TOP -> +--------+ + * | | + * | | + * | 4 | + * | | + * | | + * |~~~~~~~~| <- store compressing data + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * |~~~~~~~~| + * COMPRESSED_DATA -> +--------+ + * | | + * | 3 | + * | | + * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE + * |||||||||| + * ||||2||||| + * |||||||||| + * BL2_IGNORE_ADDR -> +--------+ + * | | + * | 1 | + * | | + * COMPRESS_START_ADDR -> +--------+ + */ +#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20) +#define CONFIG_COMPRESSED_DATA_ADDR (0x10000000) +#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000) + +#define CONFIG_COMPRESS_START_ADDR (0x00000000) +#define CONFIG_BL2_IGNORE_ADDR (0x05000000) +//#define CONFIG_BL2_IGNORE_SIZE (0x00300000) +#define CONFIG_BL2_IGNORE_SIZE (0x00400000) +#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \ + CONFIG_BL2_IGNORE_SIZE) + +enum { + RAM_COMPRESS_NORMAL = 1, + RAM_COMPRESS_COPY = 2, + RAM_COMPRESS_SET = 3 /* set ram content to same vale */ +}; + +struct ram_compress_section { + void *phy_addr; + unsigned int section_size; + unsigned int section_index : 8; + unsigned int compress_type : 8; + unsigned int set_value : 16; +}; + +struct ram_compress_full { + void *store_phy_addr; + unsigned int full_memsize; + unsigned int section_count; + struct ram_compress_section sections[CONFIG_COMPRESS_SECTION]; +}; + +#endif +#endif /* __RAM_DUMP_H__ */
diff --git a/board/amlogic/c1_ae400/firmware/timing.c b/board/amlogic/c1_ae400/firmware/timing.c index b139ecd..4161c36 100644 --- a/board/amlogic/c1_ae400/firmware/timing.c +++ b/board/amlogic/c1_ae400/firmware/timing.c
@@ -8,7 +8,6 @@ #include <asm/arch/ddr_define.h> /* board clk defines */ -#define DDR_SIZE 0 #define CPU_CLK 1512 /* ddr config support multiple configs for boards which use same bootloader: @@ -60,9 +59,90 @@ #define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 #define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 -ddr_set_t __ddr_setting[] = { +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { { - /* ddr3 */ + // c1 4layer 2pcs ddr3 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +{ + // c1 4layer 2pcs ddr3 rank0 768MB .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0, @@ -71,7 +151,7 @@ .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .dmem_load_size = 0x1000, //4K + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,21 +219,21 @@ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, */ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm - .ddr_func = DDR_FUNC, + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, }, { - /* ddr4 */ + // c1 4layer 2pcs ddr4 rank0 .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .DramType = CONFIG_DDR_TYPE_DDR4, - /* DRAMFreq = 192, 256, 384, 512, 768-1536 */ - .DRAMFreq = {1176, 0, 0, 0}, .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1176, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .dmem_load_size = 0x1000, //4K + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -209,8 +289,9 @@ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, */ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm - .ddr_func = DDR_FUNC, + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, }, };
diff --git a/board/amlogic/c1_ae401/c1_ae401.c b/board/amlogic/c1_ae401/c1_ae401.c index d84d1a7..1c15260 100644 --- a/board/amlogic/c1_ae401/c1_ae401.c +++ b/board/amlogic/c1_ae401/c1_ae401.c
@@ -95,6 +95,9 @@ pinctrl_devices_active(PIN_CONTROLLER_NUM); active_clk(); + run_command("gpio c GPIOA_10", 0); + run_command("gpio c GPIOA_12", 0); + return 0; } @@ -173,9 +176,87 @@ return 0; } +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 1 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif /* partition table */ /* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) static const struct mtd_partition spinand_partitions[] = { { .name = "logo", @@ -204,7 +285,7 @@ .size = MTDPART_SIZ_FULL, } }; -struct mtd_partition *get_partition_table(int *partitions) +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spinand_partitions); return spinand_partitions;
diff --git a/board/amlogic/c1_ae401/firmware/timing.c b/board/amlogic/c1_ae401/firmware/timing.c index b139ecd..4161c36 100644 --- a/board/amlogic/c1_ae401/firmware/timing.c +++ b/board/amlogic/c1_ae401/firmware/timing.c
@@ -8,7 +8,6 @@ #include <asm/arch/ddr_define.h> /* board clk defines */ -#define DDR_SIZE 0 #define CPU_CLK 1512 /* ddr config support multiple configs for boards which use same bootloader: @@ -60,9 +59,90 @@ #define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 #define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 -ddr_set_t __ddr_setting[] = { +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { { - /* ddr3 */ + // c1 4layer 2pcs ddr3 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +{ + // c1 4layer 2pcs ddr3 rank0 768MB .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0, @@ -71,7 +151,7 @@ .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .dmem_load_size = 0x1000, //4K + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -139,21 +219,21 @@ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, */ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm - .ddr_func = DDR_FUNC, + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, }, { - /* ddr4 */ + // c1 4layer 2pcs ddr4 rank0 .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .DramType = CONFIG_DDR_TYPE_DDR4, - /* DRAMFreq = 192, 256, 384, 512, 768-1536 */ - .DRAMFreq = {1176, 0, 0, 0}, .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1176, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .dmem_load_size = 0x1000, //4K + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -209,8 +289,9 @@ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, */ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm - .ddr_func = DDR_FUNC, + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, }, };
diff --git a/board/amlogic/c1_ae402/Kconfig b/board/amlogic/c1_ae402/Kconfig new file mode 100644 index 0000000..49f620a --- /dev/null +++ b/board/amlogic/c1_ae402/Kconfig
@@ -0,0 +1,25 @@ +if TARGET_C1_AE402 + +config SYS_SOC + default "c1" + +config SYS_BOARD + default "c1_ae402" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c1_ae402" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +endif
diff --git a/board/amlogic/c1_ae402/Makefile b/board/amlogic/c1_ae402/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c1_ae402/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c1_ae402/aml-user-key.sig b/board/amlogic/c1_ae402/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c1_ae402/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c1_ae402/c1_ae402.c b/board/amlogic/c1_ae402/c1_ae402.c new file mode 100644 index 0000000..790cace --- /dev/null +++ b/board/amlogic/c1_ae402/c1_ae402.c
@@ -0,0 +1,269 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + run_command("gpio c GPIOA_10", 0); + run_command("gpio c GPIOA_12", 0); + + return 0; +} + +int board_late_init(void) +{ + printf("board late init\n"); + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c1_ae402/firmware/timing.c b/board/amlogic/c1_ae402/firmware/timing.c new file mode 100644 index 0000000..4161c36 --- /dev/null +++ b/board/amlogic/c1_ae402/firmware/timing.c
@@ -0,0 +1,476 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + + +/* ddr configs */ +#define DDR_RFC_TYPE_DDR3_512Mbx1 0 +#define DDR_RFC_TYPE_DDR3_512Mbx2 1 +#define DDR_RFC_TYPE_DDR3_512Mbx4 2 +#define DDR_RFC_TYPE_DDR3_512Mbx8 3 +#define DDR_RFC_TYPE_DDR3_512Mbx16 4 +#define DDR_RFC_TYPE_DDR4_2Gbx1 5 +#define DDR_RFC_TYPE_DDR4_2Gbx2 6 +#define DDR_RFC_TYPE_DDR4_2Gbx4 7 +#define DDR_RFC_TYPE_DDR4_2Gbx8 8 + +#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 +#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 +#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +{ + // c1 4layer 2pcs ddr3 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +{ + // c1 4layer 2pcs ddr3 rank0 768MB + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + /* DRAMFreq = 192, 256, 384, 512, 768-1536 */ + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 768, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +{ + // c1 4layer 2pcs ddr4 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1176, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, //60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff, + .soc_cs_slew_rate = 0x3ff, + .soc_ac_slew_rate = 0x3ff, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 500, + .vref_receiver_permil = 0,//700, + .vref_dram_permil = 0,//700, + //.vref_reverse = 0, + //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, + .ac_trace_delay = {16,32,32,32,32,32,32,32,32,32}, + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +}; + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1040) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1030) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1020) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1010) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 1000) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 990) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 980) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 970) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 960) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 950) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 940) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 930) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 920) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 910) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 900) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 890) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 880) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 870) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 860) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 850) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 840) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 830) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 820) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 810) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 800) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 790) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 780) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 770) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 760) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 750) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 740) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 730) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 720) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 710) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 700) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#if (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 902) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 912) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 922) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +};
diff --git a/board/amlogic/c1_ae409/aml-key/bl2aesiv b/board/amlogic/c1_ae409/aml-key/bl2aesiv new file mode 100755 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c1_ae409/aml-key/bl2aesiv Binary files differ
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diff --git a/board/amlogic/c1_ae409/aml-key/bl3xaesiv b/board/amlogic/c1_ae409/aml-key/bl3xaesiv new file mode 100755 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c1_ae409/aml-key/bl3xaesiv Binary files differ
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diff --git a/board/amlogic/c1_ae409/aml-key/kernelaesiv b/board/amlogic/c1_ae409/aml-key/kernelaesiv new file mode 100755 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c1_ae409/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/c1_ae409/aml-key/kernelaeskey b/board/amlogic/c1_ae409/aml-key/kernelaeskey new file mode 100755 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c1_ae409/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/c1_ae409/c1_ae409.c b/board/amlogic/c1_ae409/c1_ae409.c index d84d1a7..d3c1d11 100644 --- a/board/amlogic/c1_ae409/c1_ae409.c +++ b/board/amlogic/c1_ae409/c1_ae409.c
@@ -173,9 +173,87 @@ return 0; } +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 1 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif /* partition table */ /* partition table for spinand flash */ -#ifdef CONFIG_SPI_NAND +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) static const struct mtd_partition spinand_partitions[] = { { .name = "logo", @@ -204,7 +282,7 @@ .size = MTDPART_SIZ_FULL, } }; -struct mtd_partition *get_partition_table(int *partitions) +const struct mtd_partition *get_partition_table(int *partitions) { *partitions = ARRAY_SIZE(spinand_partitions); return spinand_partitions;
diff --git a/board/amlogic/c1_ae409/firmware/timing.c b/board/amlogic/c1_ae409/firmware/timing.c index b139ecd..f32ad39 100644 --- a/board/amlogic/c1_ae409/firmware/timing.c +++ b/board/amlogic/c1_ae409/firmware/timing.c
@@ -8,7 +8,6 @@ #include <asm/arch/ddr_define.h> /* board clk defines */ -#define DDR_SIZE 0 #define CPU_CLK 1512 /* ddr config support multiple configs for boards which use same bootloader: @@ -60,7 +59,7 @@ #define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 #define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 -ddr_set_t __ddr_setting[] = { +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { { /* ddr3 */ .board_id = CONFIG_BOARD_ID_MASK, @@ -71,7 +70,7 @@ .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .dmem_load_size = 0x1000, //4K + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -147,13 +146,12 @@ .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, - .DramType = CONFIG_DDR_TYPE_DDR4, - /* DRAMFreq = 192, 256, 384, 512, 768-1536 */ - .DRAMFreq = {1176, 0, 0, 0}, .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1176, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .dmem_load_size = 0x1000, //4K + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1,
diff --git a/board/amlogic/c1_gq_p2/c1_gq_p2.c b/board/amlogic/c1_gq_p2/c1_gq_p2.c index 9081ba5..23911dd 100755 --- a/board/amlogic/c1_gq_p2/c1_gq_p2.c +++ b/board/amlogic/c1_gq_p2/c1_gq_p2.c
@@ -1,7 +1,23 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ + * board/amlogic/c1_gq_p2/c1_gq_p2.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ #include <common.h> #include <asm/io.h> @@ -30,13 +46,10 @@ #ifdef CONFIG_SECURE_POWER_CONTROL #include <asm/arch/pwr_ctrl.h> #endif -#include <asm/arch/reboot.h> -#include <linux/ctype.h> /* isdigit define */ DECLARE_GLOBAL_DATA_PTR; #define LED_ENABLE_PIN_NAME "gpiom_7" -#define RING_LED_ENABLE_PIN_NAME "gpiom_6" int led_power_enable(char *name) { @@ -141,7 +154,8 @@ unsigned long value = simple_strtoul(p, &p_next, 10); if (value > 255) { - pr_err("LED: value %d is too large: %lu\n", i, value); + pr_err("LED: value %d is too large: %lu\n", + settings_[i]); return; } settings_[map[i]] = value; @@ -198,87 +212,11 @@ mdelay(1); dm_i2c_reg_write(led_devp, 0x1, 0x3f); dm_i2c_reg_write(led_devp, 0x8, 0x61); - dm_i2c_reg_write(led_devp, 0x70, 0x0); for (i = 0; i < N_CAL_SETTINGS; ++i) dm_i2c_reg_write(led_devp, i + 2, cal_settings[i]); #endif // CONFIG_SYS_I2C_MESON } -void ring_led_init(void) -{ -#ifdef CONFIG_SYS_I2C_MESON - int ret, i; - struct udevice *led_devp = NULL; - - ret = led_power_enable(RING_LED_ENABLE_PIN_NAME); - if (ret) { - pr_err("LED: LED power enable fail\n"); - return; - } - - if (!i2c_get_chip_for_busnum(MESON_I2C_M3, 0x14, 1, &led_devp)) { - // zero out 9 bytes of colour channel data - uint8_t color[9] = {0}; - ret = dm_i2c_write(led_devp, 0xb, &color, sizeof(color)); - if (ret < 0) { - pr_err("LED: i2c write failed with error %d\n", ret); - } - - uint8_t enable[] = {0x40, 0x1c}; - ret = dm_i2c_write(led_devp, 0x0, &enable, sizeof(enable)); - if (ret < 0) { - pr_err("LED: i2c write failed with error %d\n", ret); - } - } else if (!i2c_get_chip_for_busnum(MESON_I2C_M3, 0x20, 1, &led_devp)) { - uint8_t data[1]; - - /* Global Control Register - * [0]: Chip enabled - * [1-2]: 9 bits + 3 bits dither brightness resolution - * [3]: Reserved - * [4-6]: 16 MHz OSC frequency for 32 kHz PWM frequency - * [7]: Auto power save enabled */ - data[0] = 0x87; - ret = dm_i2c_write(led_devp, 0x20, &data, sizeof(data)); - if (ret < 0) { - pr_err("LED: i2c write failed with error %d\n", ret); - } - - /* Group Configure Register - * [0-2]: Group mode disabled - * [3-5]: Reserved - * [6]: Group SL disabled. Color parameter of each LED is - * configured by their respective register SL - * [7]: Reserved */ - data[0] = 0x40; - ret = dm_i2c_write(led_devp, 0x8b, &data, sizeof(data)); - if (ret < 0) { - pr_err("LED: i2c write failed with error %d\n", ret); - } - - /* Global Current Register - * [0-7]: 8 bit global current */ - data[0] = 0xff; - ret = dm_i2c_write(led_devp, 0x58, &data, sizeof(data)); - if (ret < 0) { - pr_err("LED: i2c write failed with error %d\n", ret); - } - - /* Under Voltage Lock Out Control Register - * [0]: UVLO detect disabled - * [1]: UVLO protect disabled */ - data[0] = 0x03; - ret = dm_i2c_write(led_devp, 0x60, &data, sizeof(data)); - if (ret < 0) { - pr_err("LED: i2c write failed with error %d\n", ret); - } - } else { - pr_err("LED: i2c get bus fail\n"); - return; - } -#endif // CONFIG_SYS_I2C_MESON -} - int serial_set_pin_port(unsigned long port_base) { return 0; @@ -347,10 +285,8 @@ pinctrl_devices_active(PIN_CONTROLLER_NUM); active_clk(); - if (!oobe_complete()) { + if (!oobe_complete()) sys_led_init(); - ring_led_init(); - } /* Disable PM_ETH */ #ifdef CONFIG_SECURE_POWER_CONTROL @@ -424,7 +360,7 @@ return 0; } -int do_get_board_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, +int do_get_gq_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int hw_id = 0, ret = 0; @@ -462,42 +398,38 @@ } U_BOOT_CMD( - get_board_hw_id, 1, 0, do_get_board_hw_id, - "get GQ/NQ HW_ID and env_set 'hw_id'\n", - "get_board_hw_id" + get_gq_hw_id, 1, 0, do_get_gq_hw_id, + "get GQ HW_ID and env_set 'hw_id'\n", + "get_gq_hw_id" ); int do_get_wake_args(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - const volatile struct RtosStatusForUboot * const rtos_uboot_status = - STATUS_FOR_UBOOT_BASE_ADDR; + const volatile struct RtosStatus * const rtos_status = + RTOS_STATUS_BASE_ADDR; char wake_args_str[150] = {0}; - u32 wake_reasons; - if ((rtos_uboot_status->magic == RTOS_STATUS_MAGIC) && - (rtos_uboot_status->crc8 == crc8(0, rtos_uboot_status, sizeof(struct RtosStatusForUboot) - 1)) && - oobe_complete()) { - wake_reasons = rtos_uboot_status->wakeup_reasons; + u16 wake_reasons; + if ((rtos_status->crc8 == + crc8(0, rtos_status, sizeof(struct RtosStatus) - 1)) && + oobe_complete()) { + wake_reasons = rtos_status->wakeup_reasons; } else { wake_reasons = 0; } - /* SCHEDULED (4), MCU_RESET (5), SOC_HANG_DETECTED (16), LIMITED_SYS_RESET_DONE (18) */ - const u8 slow_reason = (wake_reasons & 0x50030) != 0; + /* MCU_RESET (5) */ + const u8 mcu_reset = (wake_reasons & 0x20) != 0; /* PIR (0), WiFi (1), doorbell (2), tamper (7), low battery (9), * charger fault (12) */ const u8 fast_reason = (wake_reasons & 0x1287) != 0; - u32 reboot_mode_val = ((readl(SYSCTRL_SEC_STATUS_REG2 ) >> 12) & 0xf); - u8 error_boot = ((reboot_mode_val == AMLOGIC_KERNEL_PANIC) || - (reboot_mode_val == AMLOGIC_WATCHDOG_REBOOT)); - - const u8 fastpath = !slow_reason && !error_boot && fast_reason; + const u8 fastpath = !mcu_reset && fast_reason; char *mode; - if (wake_reasons == 0 || slow_reason) + if (wake_reasons == 0 || mcu_reset) mode = "cold"; else if (wake_reasons == 0x1) mode = "partial_warm"; @@ -516,7 +448,7 @@ } snprintf(wake_args_str, sizeof(wake_args_str), - "androidboot.wake_reasons=0x%08x androidboot.bootpath=%s " + "androidboot.wake_reasons=0x%04x androidboot.bootpath=%s " "androidboot.eventpath=%s dhd.load_mode=%s", wake_reasons, fastpath ? "fast" : "slow", event_path, mode); env_set("wake_args", wake_args_str); @@ -528,7 +460,7 @@ "Get wake_reasons and bootpath, envset wake_args\n", "Parses CV status from RTOS extract wake_reasons and bootpath.\n"\ "envsets |wake_args| to add to kernel command line, contains:\n"\ - " androidboot.wake_reason=0x08x: wake_reasons from RTOS\n"\ + " androidboot.wake_reason=0x04x: wake_reasons from RTOS\n"\ " androidboot.bootpath=(fast|slow): boot quickly or check RW FS\n" " androidboot.eventpath=:(event string) specify type of fast boot\n" " dhd.load_mode=(cold|partial_warm|warm) specify load mode for wifi driver\n"
diff --git a/board/amlogic/c1_nq_p2/c1_nq_p2.c b/board/amlogic/c1_nq_p2/c1_nq_p2.c index 90f3b1c..d9a7a84 100644 --- a/board/amlogic/c1_nq_p2/c1_nq_p2.c +++ b/board/amlogic/c1_nq_p2/c1_nq_p2.c
@@ -1,7 +1,23 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ + * board/amlogic/c1_nq_p2/c1_nq_p2.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ #include <common.h> #include <asm/io.h> @@ -30,8 +46,6 @@ #ifdef CONFIG_SECURE_POWER_CONTROL #include <asm/arch/pwr_ctrl.h> #endif -#include <asm/arch/reboot.h> -#include <linux/ctype.h> /* isdigit define */ DECLARE_GLOBAL_DATA_PTR; @@ -140,7 +154,8 @@ unsigned long value = simple_strtoul(p, &p_next, 10); if (value > 255) { - pr_err("LED: value %d is too large: %lu\n", i, value); + pr_err("LED: value %d is too large: %lu\n", + settings_[i]); return; } settings_[map[i]] = value; @@ -197,7 +212,6 @@ mdelay(1); dm_i2c_reg_write(led_devp, 0x1, 0x3f); dm_i2c_reg_write(led_devp, 0x8, 0x61); - dm_i2c_reg_write(led_devp, 0x70, 0x0); for (i = 0; i < N_CAL_SETTINGS; ++i) dm_i2c_reg_write(led_devp, i + 2, cal_settings[i]); #endif // CONFIG_SYS_I2C_MESON @@ -346,7 +360,7 @@ return 0; } -int do_get_board_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, +int do_get_nq_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int hw_id = 0, ret = 0; @@ -384,42 +398,38 @@ } U_BOOT_CMD( - get_board_hw_id, 1, 0, do_get_board_hw_id, - "get GQ/NQ HW_ID and env_set 'hw_id'\n", - "get_board_hw_id" + get_nq_hw_id, 1, 0, do_get_nq_hw_id, + "get NQ HW_ID and env_set 'hw_id'\n", + "get_nq_hw_id" ); int do_get_wake_args(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - const volatile struct RtosStatusForUboot * const rtos_uboot_status = - STATUS_FOR_UBOOT_BASE_ADDR; + const volatile struct RtosStatus * const rtos_status = + RTOS_STATUS_BASE_ADDR; char wake_args_str[150] = {0}; - u32 wake_reasons; - if ((rtos_uboot_status->magic == RTOS_STATUS_MAGIC) && - (rtos_uboot_status->crc8 == crc8(0, rtos_uboot_status, sizeof(struct RtosStatusForUboot) - 1)) && - oobe_complete()) { - wake_reasons = rtos_uboot_status->wakeup_reasons; + u16 wake_reasons; + if ((rtos_status->crc8 == + crc8(0, rtos_status, sizeof(struct RtosStatus) - 1)) && + oobe_complete()) { + wake_reasons = rtos_status->wakeup_reasons; } else { wake_reasons = 0; } - /* SCHEDULED (4), MCU_RESET (5), SOC_HANG_DETECTED (16), LIMITED_SYS_RESET_DONE (18) */ - const u8 slow_reason = (wake_reasons & 0x50030) != 0; + /* MCU_RESET (5) */ + const u8 mcu_reset = (wake_reasons & 0x20) != 0; /* PIR (0), WiFi (1), doorbell (2), tamper (7), low battery (9), * charger fault (12) */ const u8 fast_reason = (wake_reasons & 0x1287) != 0; - u32 reboot_mode_val = ((readl(SYSCTRL_SEC_STATUS_REG2 ) >> 12) & 0xf); - u8 error_boot = ((reboot_mode_val == AMLOGIC_KERNEL_PANIC) || - (reboot_mode_val == AMLOGIC_WATCHDOG_REBOOT)); - - const u8 fastpath = !slow_reason && !error_boot && fast_reason; + const u8 fastpath = !mcu_reset && fast_reason; char *mode; - if (wake_reasons == 0 || slow_reason) + if (wake_reasons == 0 || mcu_reset) mode = "cold"; else if (wake_reasons == 0x1) mode = "partial_warm"; @@ -438,7 +448,7 @@ } snprintf(wake_args_str, sizeof(wake_args_str), - "androidboot.wake_reasons=0x%08x androidboot.bootpath=%s " + "androidboot.wake_reasons=0x%04x androidboot.bootpath=%s " "androidboot.eventpath=%s dhd.load_mode=%s", wake_reasons, fastpath ? "fast" : "slow", event_path, mode); env_set("wake_args", wake_args_str); @@ -450,7 +460,7 @@ "Get wake_reasons and bootpath, envset wake_args\n", "Parses CV status from RTOS extract wake_reasons and bootpath.\n"\ "envsets |wake_args| to add to kernel command line, contains:\n"\ - " androidboot.wake_reason=0x08x: wake_reasons from RTOS\n"\ + " androidboot.wake_reason=0x04x: wake_reasons from RTOS\n"\ " androidboot.bootpath=(fast|slow): boot quickly or check RW FS\n" " androidboot.eventpath=:(event string) specify type of fast boot\n" " dhd.load_mode=(cold|partial_warm|warm) specify load mode for wifi driver\n"
diff --git a/board/amlogic/c1_nq_p2/firmware/timing.c b/board/amlogic/c1_nq_p2/firmware/timing.c index f7ccbbd..f7ba2fc 100644 --- a/board/amlogic/c1_nq_p2/firmware/timing.c +++ b/board/amlogic/c1_nq_p2/firmware/timing.c
@@ -1,7 +1,23 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ + * board/amlogic/c1_nq_p2/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ #include <asm/arch/secure_apb.h> #include <asm/arch/timing.h>
diff --git a/board/amlogic/c2_2rs4_p1/Kconfig b/board/amlogic/c2_2rs4_p1/Kconfig new file mode 100644 index 0000000..05e3f8f --- /dev/null +++ b/board/amlogic/c2_2rs4_p1/Kconfig
@@ -0,0 +1,37 @@ +if TARGET_C2_2RS4_P1 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_2rs4_p1" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_2rs4_p1" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +config LED_AW210XX + bool "enable/disable AW210XX LED" + default y + +endif
diff --git a/board/amlogic/c2_2rs4_p1/Makefile b/board/amlogic/c2_2rs4_p1/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_2rs4_p1/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_2rs4_p1/aml-user-key.sig b/board/amlogic/c2_2rs4_p1/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_2rs4_p1/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_2rs4_p1/c2_2rs4_p1.c b/board/amlogic/c2_2rs4_p1/c2_2rs4_p1.c new file mode 100644 index 0000000..e345687 --- /dev/null +++ b/board/amlogic/c2_2rs4_p1/c2_2rs4_p1.c
@@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/leds-aw210xx.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + // set to white by default + sys_led_init(WHITE); + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_2rs4_p1/firmware/timing.c b/board/amlogic/c2_2rs4_p1/firmware/timing.c new file mode 100755 index 0000000..ec2f8ee --- /dev/null +++ b/board/amlogic/c2_2rs4_p1/firmware/timing.c
@@ -0,0 +1,1095 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_LPDDR4 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5(SOC_LEDRING_EN) low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10(BAT_HEALTH_CHECK_EN) low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11(BAT_VSENSE_EN) low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_2rs4_p2/Kconfig b/board/amlogic/c2_2rs4_p2/Kconfig new file mode 100644 index 0000000..48d8107 --- /dev/null +++ b/board/amlogic/c2_2rs4_p2/Kconfig
@@ -0,0 +1,37 @@ +if TARGET_C2_2RS4_P2 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_2rs4_p2" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_2rs4_p2" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +config LED_AW210XX + bool "enable/disable AW210XX LED" + default y + +endif
diff --git a/board/amlogic/c2_2rs4_p2/Makefile b/board/amlogic/c2_2rs4_p2/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_2rs4_p2/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_2rs4_p2/aml-user-key.sig b/board/amlogic/c2_2rs4_p2/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_2rs4_p2/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_2rs4_p2/c2_2rs4_p2.c b/board/amlogic/c2_2rs4_p2/c2_2rs4_p2.c new file mode 100644 index 0000000..e345687 --- /dev/null +++ b/board/amlogic/c2_2rs4_p2/c2_2rs4_p2.c
@@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/leds-aw210xx.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + // set to white by default + sys_led_init(WHITE); + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_2rs4_p2/firmware/timing.c b/board/amlogic/c2_2rs4_p2/firmware/timing.c new file mode 100755 index 0000000..ec2f8ee --- /dev/null +++ b/board/amlogic/c2_2rs4_p2/firmware/timing.c
@@ -0,0 +1,1095 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_LPDDR4 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5(SOC_LEDRING_EN) low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10(BAT_HEALTH_CHECK_EN) low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11(BAT_VSENSE_EN) low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_a049_p0/Kconfig b/board/amlogic/c2_a049_p0/Kconfig new file mode 100644 index 0000000..55d5e04 --- /dev/null +++ b/board/amlogic/c2_a049_p0/Kconfig
@@ -0,0 +1,29 @@ +if TARGET_C2_A049_P0 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_a049_p0" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_a049_p0" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +endif
diff --git a/board/amlogic/c2_a049_p0/Makefile b/board/amlogic/c2_a049_p0/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_a049_p0/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_a049_p0/aml-user-key.sig b/board/amlogic/c2_a049_p0/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_a049_p0/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_a049_p0/c2_a049_p0.c b/board/amlogic/c2_a049_p0/c2_a049_p0.c new file mode 100644 index 0000000..f2a0ab3 --- /dev/null +++ b/board/amlogic/c2_a049_p0/c2_a049_p0.c
@@ -0,0 +1,289 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/led_aw2015.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); +#ifndef CONFIG_ENABLE_CHARGER_DETECTION + sys_led_init(WHITE); +#endif + + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_a049_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_5 : GPIOD_10 + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x3F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9, GPIOD_10 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x3F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x3F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_a049_hw_id, 1, 0, do_get_a049_hw_id, + "get a049 HW_ID and env_set 'hw_id'\n", + "get_a049_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_a049_p0/firmware/timing.c b/board/amlogic/c2_a049_p0/firmware/timing.c new file mode 100755 index 0000000..b29736a --- /dev/null +++ b/board/amlogic/c2_a049_p0/firmware/timing.c
@@ -0,0 +1,651 @@ +/* + * board/amlogic/c2_a049_p0/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +} +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + //{PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + //{PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + //{PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + //{PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_af400/Kconfig b/board/amlogic/c2_af400/Kconfig new file mode 100644 index 0000000..47dd569 --- /dev/null +++ b/board/amlogic/c2_af400/Kconfig
@@ -0,0 +1,25 @@ +if TARGET_C2_AF400 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_af400" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_af400" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +endif
diff --git a/board/amlogic/c2_af400/Makefile b/board/amlogic/c2_af400/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_af400/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af400/aml-key/bl2aesiv b/board/amlogic/c2_af400/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af400/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/bl2aeskey b/board/amlogic/c2_af400/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af400/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/bl3xaesiv b/board/amlogic/c2_af400/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af400/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/bl3xaeskey b/board/amlogic/c2_af400/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af400/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/kernelaesiv b/board/amlogic/c2_af400/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af400/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/kernelaeskey b/board/amlogic/c2_af400/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af400/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/c2_af400/aml-user-key.sig b/board/amlogic/c2_af400/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_af400/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_af400/c2_af400.c b/board/amlogic/c2_af400/c2_af400.c new file mode 100644 index 0000000..59ec2ee --- /dev/null +++ b/board/amlogic/c2_af400/c2_af400.c
@@ -0,0 +1,321 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + run_command("gpio c GPIOA_10", 0); + run_command("gpio c GPIOA_12", 0); + + return 0; +} + +int board_late_init(void) +{ + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* +* mtd nand partition table, only care the size! +* offset will be calculated by nand driver. +*/ +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "misc", + .offset = 0, + .size = 8 * SZ_8K, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af400/firmware/timing.c b/board/amlogic/c2_af400/firmware/timing.c new file mode 100644 index 0000000..0e16d83 --- /dev/null +++ b/board/amlogic/c2_af400/firmware/timing.c
@@ -0,0 +1,3510 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if 1//timing_config,af400 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 + +#if 0//timing_config,af409 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,90,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,90,128,128,128,128,128, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 + +#if 0//timing_config,af419 +{ + //af419 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-40,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-40,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 1 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af419 + +#if 0//timing_config,af401 DDR3 +{ + //af401 DDR3 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_512MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792,667 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000069,// 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000069,// 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000019,// 25 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x0000009c,// 156 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000009e,// 158 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000b5,// 181 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000b8,// 184 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000b6,// 182 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a5,// 165 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000c7,// 199 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b6,// 182 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000c4,// 196 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000c4,// 196 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d2,// 210 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000b7,// 183 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000b7,// 183 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000c1,// 193 + + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037e,// 894 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000036a,// 874 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000370,// 880 + + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000008b,// 139 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000072,// 114 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000093,// 147 + + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000053,// 83 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000077,// 119 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000038,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000004d,// 77 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000094,// 148 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000038,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000039,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000003c,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000049,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000061,// 97 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000053,// 83 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000047,// 71 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44 + + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} , + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //real DDR3 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af401 DDR3 + +#if 0 //timing_config,af400 LPDDR4 rank01 +{ + //af400 LPDDR4 rank01 + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_1024MB, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE + //.cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_READ_DBI_ENABLE,//DDR_WRITE_READ_DBI_DISABLE , + //.cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_READ_DBI_ENABLE|DDR_WRITE_DBI_ENABLE,//DDR_WRITE_READ_DBI_DISABLE , + //enable write dbi need dq pinmux correct,since of write mask pattern is fixed in current design + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT + .cfg_board_common_setting.fast_boot = { 0 }, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 300, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, +#if 0 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0, 0, 0, 0, 0, 0, 0, 0, //0,0,0,0,0,0,0,0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + }, //total 36 +#endif +#if 1 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 +#endif + +#if 0 + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 +#endif +#if 1 //default cs cke 0 ,other AC=128 + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 +#endif +#if 0 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 64 + 128, 30 + 128 + 13, 30 + 128, 30 + 128, 17 + 128, 30 + 128, 30 + 128, 30 + 128 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + }, + + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 1357, 1400, 1400, 1400, 1357, 1400, 1400, 1400 + }, //total 8 //edge mode + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 26, 32, 26, + 32, 26, 32, 26 + }, //total 44 + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, +#endif + +#if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d, // 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000069, // 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x00000073, // 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x00000069, // 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x00000091, // 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x00000250, // 592 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x0000024c, // 588 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x00000256, // 598 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x0000025a, // 602 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x0000025b, // 603 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x00000255, // 597 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x00000241, // 577 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x00000248, // 584 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x0000023e, // 574 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x00000245, // 581 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x0000024d, // 589 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x00000247, // 583 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x00000245, // 581 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x00000246, // 582 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x00000243, // 579 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x00000257, // 599 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x00000254, // 596 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x00000260, // 608 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x00000261, // 609 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x0000025f, // 607 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x0000025a, // 602 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x0000025f, // 607 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x00000259, // 601 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x00000253, // 595 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x00000250, // 592 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x00000263, // 611 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x00000254, // 596 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x00000252, // 594 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x00000252, // 594 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x0000025b, // 603 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d, // 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000069, // 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x00000073, // 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0 + 4] = 0x0000007d, // 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1 + 4] = 0x00000069, // 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2 + 4] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3 + 4] = 0x00000073, // 115 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0 + 36] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1 + 36] = 0x00000250, // 592 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2 + 36] = 0x0000024c, // 588 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3 + 36] = 0x00000256, // 598 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4 + 36] = 0x0000025a, // 602 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5 + 36] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6 + 36] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7 + 36] = 0x0000025b, // 603 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8 + 36] = 0x00000255, // 597 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9 + 36] = 0x00000241, // 577 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10 + 36] = 0x00000248, // 584 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11 + 36] = 0x0000023e, // 574 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12 + 36] = 0x00000245, // 581 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13 + 36] = 0x0000024d, // 589 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14 + 36] = 0x00000247, // 583 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15 + 36] = 0x00000245, // 581 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16 + 36] = 0x00000246, // 582 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17 + 36] = 0x00000243, // 579 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18 + 36] = 0x00000257, // 599 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19 + 36] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20 + 36] = 0x00000254, // 596 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21 + 36] = 0x00000260, // 608 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22 + 36] = 0x00000261, // 609 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23 + 36] = 0x0000025f, // 607 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24 + 36] = 0x0000025a, // 602 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25 + 36] = 0x0000025f, // 607 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26 + 36] = 0x00000259, // 601 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27 + 36] = 0x00000253, // 595 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28 + 36] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29 + 36] = 0x00000250, // 592 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30 + 36] = 0x00000263, // 611 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31 + 36] = 0x00000254, // 596 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32 + 36] = 0x00000252, // 594 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33 + 36] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34 + 36] = 0x00000252, // 594 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35 + 36] = 0x0000025b, // 603 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0 + 4] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1 + 4] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2 + 4] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3 + 4] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007a, // 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x00000072, // 114 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x00000079, // 121 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x00000076, // 118 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0 + 4] = 0x0000007a, // 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1 + 4] = 0x00000072, // 114 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2 + 4] = 0x00000079, // 121 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3 + 4] = 0x00000076, // 118 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x0000003a, // 58 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044, // 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004c, // 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x00000036, // 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049, // 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000056, // 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000036, // 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000032, // 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x00000041, // 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x0000004e, // 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048, // 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047, // 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000005b, // 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x0000004a, // 74 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = 0x0000003f, // 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x00000033, // 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000052, // 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0 + 36] = 0x0000003a, // 58 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1 + 36] = 0x00000044, // 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2 + 36] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3 + 36] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4 + 36] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5 + 36] = 0x0000004c, // 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6 + 36] = 0x00000036, // 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7 + 36] = 0x00000049, // 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8 + 36] = 0x00000056, // 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9 + 36] = 0x00000036, // 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10 + 36] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11 + 36] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12 + 36] = 0x00000032, // 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13 + 36] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14 + 36] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15 + 36] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16 + 36] = 0x00000041, // 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17 + 36] = 0x0000004e, // 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18 + 36] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19 + 36] = 0x00000048, // 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20 + 36] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21 + 36] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22 + 36] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23 + 36] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24 + 36] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25 + 36] = 0x00000047, // 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26 + 36] = 0x0000005b, // 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27 + 36] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28 + 36] = 0x0000004a, // 74 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29 + 36] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30 + 36] = 0x0000003f, // 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31 + 36] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32 + 36] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33 + 36] = 0x00000033, // 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34 + 36] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35 + 36] = 0x00000052, // 82 +#endif +#if 1 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4] = 0x00000019, // 25 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8] = 0x00000018, // 32 //0x20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23] = 0x00000019, // 25 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25] = 0x00000019, // 25 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35] = 0x00000018, // 32 +#endif +#if 1 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37] = 0x00000020 - 8, // 34 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39] = 0x00000020 - 8, // 34 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41] = 0x00000020 - 8, // 34 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43] = 0x00000020 - 8, // 34 +#endif +#if 1 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0] = 0x00000000, // 0X5b,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35] = 0x00000000, // 0 +#endif + + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 0, 5, + 0, 1, 0, 0, 4, 0, 5, 0, + 1, 3, 3, 4, 2, 0, 0, 0, + 0, 0, 0, 2, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, +#if 0 + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 +#endif + +#if 1 + .cfg_board_common_setting.ddr_dq_remap = { + 0, 4, 1, 2, 3, 5, 7, 6, + 12, 13, 9, 11, 8, 15, 14, 10, + 20, 21, 22, 23, 16, 17, 19, 18, + 31, 29, 30, 28, 24, 26, 27, 25, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 +#endif + + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },//ddr_set_t end +}, +#endif //end af400 LPDDR4 rank01 + +#if 0 //timing_config,af400 LPDDR4 rank0 +{ + //af400 LPDDR4 rank0 + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT + .cfg_board_common_setting.fast_boot = { 0 }, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 300, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, +#if 0 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0, 0, 0, 0, 0, 0, 0, 0, //0,0,0,0,0,0,0,0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + }, //total 36 +#endif +#if 1 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 +#endif + +#if 0 + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 +#endif +#if 1 //default cs cke 0 ,other AC=128 + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 +#endif +#if 0 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 64 + 128, 30 + 128 + 13, 30 + 128, 30 + 128, 17 + 128, 30 + 128, 30 + 128, 30 + 128 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, + }, + + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 1357, 1400, 1400, 1400, 1357, 1400, 1400, 1400 + }, //total 8 //edge mode + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 26, 32, 26, + 32, 26, 32, 26 + }, //total 44 + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, +#endif + +#if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d, // 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000069, // 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x00000073, // 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x00000069, // 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x00000091, // 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x00000250, // 592 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x0000024c, // 588 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x00000256, // 598 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x0000025a, // 602 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x0000025b, // 603 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x00000255, // 597 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x00000241, // 577 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x00000248, // 584 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x0000023e, // 574 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x00000245, // 581 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x0000024d, // 589 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x00000247, // 583 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x00000245, // 581 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x00000246, // 582 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x00000243, // 579 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x00000257, // 599 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x00000254, // 596 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x00000260, // 608 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x00000261, // 609 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x0000025f, // 607 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x0000025a, // 602 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x0000025f, // 607 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x00000259, // 601 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x00000253, // 595 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x00000250, // 592 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x00000263, // 611 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x00000254, // 596 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x00000252, // 594 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x00000252, // 594 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x0000025b, // 603 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d, // 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000069, // 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x00000073, // 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0 + 4] = 0x0000007d, // 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1 + 4] = 0x00000069, // 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2 + 4] = 0x00000087, // 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3 + 4] = 0x00000073, // 115 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0 + 36] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1 + 36] = 0x00000250, // 592 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2 + 36] = 0x0000024c, // 588 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3 + 36] = 0x00000256, // 598 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4 + 36] = 0x0000025a, // 602 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5 + 36] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6 + 36] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7 + 36] = 0x0000025b, // 603 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8 + 36] = 0x00000255, // 597 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9 + 36] = 0x00000241, // 577 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10 + 36] = 0x00000248, // 584 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11 + 36] = 0x0000023e, // 574 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12 + 36] = 0x00000245, // 581 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13 + 36] = 0x0000024d, // 589 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14 + 36] = 0x00000247, // 583 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15 + 36] = 0x00000245, // 581 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16 + 36] = 0x00000246, // 582 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17 + 36] = 0x00000243, // 579 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18 + 36] = 0x00000257, // 599 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19 + 36] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20 + 36] = 0x00000254, // 596 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21 + 36] = 0x00000260, // 608 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22 + 36] = 0x00000261, // 609 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23 + 36] = 0x0000025f, // 607 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24 + 36] = 0x0000025a, // 602 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25 + 36] = 0x0000025f, // 607 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26 + 36] = 0x00000259, // 601 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27 + 36] = 0x00000253, // 595 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28 + 36] = 0x0000025d, // 605 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29 + 36] = 0x00000250, // 592 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30 + 36] = 0x00000263, // 611 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31 + 36] = 0x00000254, // 596 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32 + 36] = 0x00000252, // 594 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33 + 36] = 0x00000251, // 593 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34 + 36] = 0x00000252, // 594 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35 + 36] = 0x0000025b, // 603 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0 + 4] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1 + 4] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2 + 4] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3 + 4] = 0x00000744, // 1860 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007a, // 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x00000072, // 114 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x00000079, // 121 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x00000076, // 118 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0 + 4] = 0x0000007a, // 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1 + 4] = 0x00000072, // 114 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2 + 4] = 0x00000079, // 121 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3 + 4] = 0x00000076, // 118 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x0000003a, // 58 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044, // 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004c, // 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x00000036, // 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049, // 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000056, // 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000036, // 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000032, // 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x00000041, // 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x0000004e, // 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048, // 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047, // 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000005b, // 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x0000004a, // 74 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = 0x0000003f, // 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x00000033, // 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000052, // 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0 + 36] = 0x0000003a, // 58 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1 + 36] = 0x00000044, // 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2 + 36] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3 + 36] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4 + 36] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5 + 36] = 0x0000004c, // 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6 + 36] = 0x00000036, // 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7 + 36] = 0x00000049, // 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8 + 36] = 0x00000056, // 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9 + 36] = 0x00000036, // 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10 + 36] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11 + 36] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12 + 36] = 0x00000032, // 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13 + 36] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14 + 36] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15 + 36] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16 + 36] = 0x00000041, // 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17 + 36] = 0x0000004e, // 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18 + 36] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19 + 36] = 0x00000048, // 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20 + 36] = 0x00000035, // 53 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21 + 36] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22 + 36] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23 + 36] = 0x00000046, // 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24 + 36] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25 + 36] = 0x00000047, // 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26 + 36] = 0x0000005b, // 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27 + 36] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28 + 36] = 0x0000004a, // 74 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29 + 36] = 0x0000003c, // 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30 + 36] = 0x0000003f, // 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31 + 36] = 0x0000003b, // 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32 + 36] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33 + 36] = 0x00000033, // 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34 + 36] = 0x0000003e, // 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35 + 36] = 0x00000052, // 82 +#endif +#if 1 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4] = 0x00000019, // 25 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8] = 0x00000018, // 32 //0x20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23] = 0x00000019, // 25 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25] = 0x00000019, // 25 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34] = 0x00000018, // 24 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35] = 0x00000018, // 32 +#endif +#if 1 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37] = 0x00000020 - 8, // 34 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39] = 0x00000020 - 8, // 34 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41] = 0x00000020 - 8, // 34 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42] = 0x00000018, // 32 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43] = 0x00000020 - 8, // 34 +#endif +#if 1 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0] = 0x00000000, // 0X5b,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34] = 0x00000000, // 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35] = 0x00000000, // 0 +#endif + + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 0, 5, + 0, 1, 0, 0, 4, 0, 5, 0, + 1, 3, 3, 4, 2, 0, 0, 0, + 0, 0, 0, 2, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, +#if 0 + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 +#endif + +#if 1 + .cfg_board_common_setting.ddr_dq_remap = { + 0, 4, 1, 2, 3, 5, 7, 6, + 12, 13, 9, 11, 8, 15, 14, 10, + 20, 21, 22, 23, 16, 17, 19, 18, + 31, 29, 30, 28, 24, 26, 27, 25, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 +#endif + + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },//ddr_set_t end +}, +#endif //end af400 LPDDR4 rank0 + +#if 0//timing_config,af409 LPDDR4 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + #if 0 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + },//total 36 + #endif + #if 1 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,40,32,40,32,40,32,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 0, 1, + 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 LPDDR4 + +#if 0 //timing_config,for dd3 pxp +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT , + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + } , + + //ac_group0-ac_group1 + #endif + #if 1 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35, + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 123,124,0,126,127,0,0,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 //real board + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,} , + + + #endif + + #if 1 //for pxp + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8 + + #else + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for dd3 pxp + +#if 0 //timing_config,for ddr4 pxp remap +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT , + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for ddr4 pxp remap +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif +.ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +};
diff --git a/board/amlogic/c2_af401/Kconfig b/board/amlogic/c2_af401/Kconfig new file mode 100644 index 0000000..74ba913 --- /dev/null +++ b/board/amlogic/c2_af401/Kconfig
@@ -0,0 +1,25 @@ +if TARGET_C2_AF401 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_af401" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_af401" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +endif
diff --git a/board/amlogic/c2_af401/Makefile b/board/amlogic/c2_af401/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_af401/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af401/aml-key/bl2aesiv b/board/amlogic/c2_af401/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af401/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/bl2aeskey b/board/amlogic/c2_af401/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af401/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/bl3xaesiv b/board/amlogic/c2_af401/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af401/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/bl3xaeskey b/board/amlogic/c2_af401/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af401/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/kernelaesiv b/board/amlogic/c2_af401/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af401/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/kernelaeskey b/board/amlogic/c2_af401/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af401/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/c2_af401/aml-user-key.sig b/board/amlogic/c2_af401/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_af401/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_af401/c2_af401.c b/board/amlogic/c2_af401/c2_af401.c new file mode 100644 index 0000000..59ec2ee --- /dev/null +++ b/board/amlogic/c2_af401/c2_af401.c
@@ -0,0 +1,321 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + run_command("gpio c GPIOA_10", 0); + run_command("gpio c GPIOA_12", 0); + + return 0; +} + +int board_late_init(void) +{ + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* +* mtd nand partition table, only care the size! +* offset will be calculated by nand driver. +*/ +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "misc", + .offset = 0, + .size = 8 * SZ_8K, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af401/firmware/timing.c b/board/amlogic/c2_af401/firmware/timing.c new file mode 100644 index 0000000..5153e8b --- /dev/null +++ b/board/amlogic/c2_af401/firmware/timing.c
@@ -0,0 +1,3110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if 0//timing_config,af400 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 + +#if 0//timing_config,af409 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,90,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,90,128,128,128,128,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 + +#if 0//timing_config,af419 +{ + //af419 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-40,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-40,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 1 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af419 + +#if 1//timing_config,af401 DDR3 +{ + //af401 DDR3 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_512MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792,667 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000069,// 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000069,// 105 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000019,// 25 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x0000009c,// 156 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000009e,// 158 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000b5,// 181 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000b8,// 184 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000b6,// 182 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a5,// 165 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000c7,// 199 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b6,// 182 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000c4,// 196 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000c4,// 196 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d2,// 210 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000b7,// 183 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000b7,// 183 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000c1,// 193 + + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037e,// 894 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000036a,// 874 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000370,// 880 + + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000008b,// 139 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000072,// 114 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000093,// 147 + + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000053,// 83 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000077,// 119 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000038,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000004d,// 77 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000094,// 148 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000038,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000039,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000003c,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000049,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000061,// 97 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000053,// 83 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000047,// 71 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44 + + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} , + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //real DDR3 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af401 DDR3 + +#if 0//timing_config,google DDR3 board +{ + //google DDR3 board + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792,667 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44 + + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} , + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //real DDR3 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end google DDR3 board + +#if 0//timing_config,af400 LPDDR4 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 300, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1//default cs cke 0 ,other AC=128 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,0,0, //0,0,0,0,0,0,0,0, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128, + },//total 36 + #endif + //write delay line setting + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + } , + #endif + #if 1 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 26, 32, 26, + 32, 26, 32, 26 + }, //total 44 + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 0, 1, + 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, + }, + #endif + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 lpddr4 + +#if 0//timing_config,af409 LPDDR4 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + #if 0 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + },//total 36 + #endif + #if 1 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,40,32,40,32,40,32,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 0, 1, + 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 LPDDR4 + +#if 0 //timing_config,for dd3 pxp +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT , + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + } , + + //ac_group0-ac_group1 + #endif + #if 1 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35, + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 123,124,0,126,127,0,0,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 //real board + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,} , + + + #endif + + #if 1 //for pxp + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8 + + #else + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for dd3 pxp + +#if 0 //timing_config,for ddr4 pxp remap +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT , + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for ddr4 pxp remap +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif +.ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +};
diff --git a/board/amlogic/c2_af409/Kconfig b/board/amlogic/c2_af409/Kconfig new file mode 100644 index 0000000..b4c91c2 --- /dev/null +++ b/board/amlogic/c2_af409/Kconfig
@@ -0,0 +1,25 @@ +if TARGET_C2_AF409 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_af409" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_af409" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +endif
diff --git a/board/amlogic/c2_af409/Makefile b/board/amlogic/c2_af409/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_af409/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af409/aml-key/bl2aesiv b/board/amlogic/c2_af409/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af409/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/bl2aeskey b/board/amlogic/c2_af409/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af409/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/bl3xaesiv b/board/amlogic/c2_af409/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af409/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/bl3xaeskey b/board/amlogic/c2_af409/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af409/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/kernelaesiv b/board/amlogic/c2_af409/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af409/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/kernelaeskey b/board/amlogic/c2_af409/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af409/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/c2_af409/aml-user-key.sig b/board/amlogic/c2_af409/aml-user-key.sig new file mode 100755 index 0000000..088d1cf --- /dev/null +++ b/board/amlogic/c2_af409/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_af409/c2_af409.c b/board/amlogic/c2_af409/c2_af409.c new file mode 100644 index 0000000..d319abe --- /dev/null +++ b/board/amlogic/c2_af409/c2_af409.c
@@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + struct udevice *i2c = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + /*active gpio i2c */ + err = uclass_get_device_by_name(UCLASS_I2C, + "i2c-gpio-0", &i2c); + if (err) { + pr_err("Can't find i2c-gpio-0 (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + return 0; +} + +int board_late_init(void) +{ + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* +* mtd nand partition table, only care the size! +* offset will be calculated by nand driver. +*/ +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "misc", + .offset = 0, + .size = 8 * SZ_8K, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af409/firmware/timing.c b/board/amlogic/c2_af409/firmware/timing.c new file mode 100644 index 0000000..b4397f5 --- /dev/null +++ b/board/amlogic/c2_af409/firmware/timing.c
@@ -0,0 +1,3597 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +//#define T406_LPDDR4 1 +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if 0//timing_config,af400 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 + +#if 1 //timing_config,af409 +{ + + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,90,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128,128,90,128,128,128,128,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 + +#if 0//timing_config,af419 +{ + //af419 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-40,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128,128,128-40,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 1 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af419 + +#if 0//timing_config,real DDR3 +{ + //real DDR3 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44 + + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} , + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //real DDR3 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end real DDR3 + +#if 0//timing_config,af400 LPDDR4 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 300, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1//default cs cke 0 ,other AC=128 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,0,0, //0,0,0,0,0,0,0,0, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128, + },//total 36 + #endif + //write delay line setting + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + } , + #endif + #if 1 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,26,32,26,32,26,32,26} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 0, 1, + 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, + }, + #endif + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 lpddr4 + +#if 0//timing_config,af409 LPDDR4 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + #if 0 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + },//total 36 + #endif + #if 1 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,40,32,40,32,40,32,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 0, 1, + 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 LPDDR4 + +#if 0 //timing_config,for dd3 pxp +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT , + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + } , + + //ac_group0-ac_group1 + #endif + #if 1 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35, + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 123,124,0,126,127,0,0,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 //real board + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,} , + + + #endif + + #if 1 //for pxp + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8 + + #else + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for dd3 pxp + +#if 0 //timing_config,for ddr4 pxp remap +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT , + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for ddr4 pxp remap + + +#ifdef T406_LPDDR4 //timing_config,for T406 LPDDR4 +//ddr_set_t ddr_set_t_default= +{ +//old fast_boot[0]=0x00000000,// 0 +.cfg_board_common_setting.fast_boot[0]=0x000000fd,// 253 +.cfg_board_common_setting.fast_boot[1]=0x00000000,// 0 +.cfg_board_common_setting.fast_boot[2]=0x00000000,// 0 +.cfg_board_common_setting.fast_boot[3]=0x00000000,// 0 +.cfg_board_common_setting.timming_magic=0x00000000,// 0 +.cfg_board_common_setting.timming_max_valid_configs=0x00000001,// 1 +.cfg_board_common_setting.timming_struct_version=0x00000000,// 0 +.cfg_board_common_setting.timming_struct_org_size=0x000004bc,// 1212 +.cfg_board_common_setting.timming_struct_real_size=0x00000000,// 0 +.cfg_board_common_setting.ddr_func=0x00000000,// 0 +.cfg_board_common_setting.board_id=0x000000ff,// 255 +.cfg_board_common_setting.DramType=0x00000002,// 2 +.cfg_board_common_setting.dram_rank_config=0x00000007,// 7 +.cfg_board_common_setting.DisabledDbyte=0x000000f0,// 240 +.cfg_board_common_setting.dram_cs0_base_add=0x00000000,// 0 +.cfg_board_common_setting.dram_cs1_base_add=0x00000000,// 0 +.cfg_board_common_setting.dram_cs0_size_MB=0x00000400,// 1024 +.cfg_board_common_setting.dram_cs1_size_MB=0x00000400,// 1024 +.cfg_board_common_setting.dram_x4x8x16_mode=0x00000000,// 0 +.cfg_board_common_setting.Is2Ttiming=0x00000000,// 0 +.cfg_board_common_setting.log_level=0x00000001,// 1 +.cfg_board_common_setting.ddr_rdbi_wr_enable=0x00000000,// 0 +.cfg_board_common_setting.pll_ssc_mode=0x00000000,// 0 +.cfg_board_common_setting.org_tdqs2dq=0x00000000,// 0 +.cfg_board_common_setting.reserve1_test_function[0]=0x00000000,// 0 +.cfg_board_common_setting.reserve1_test_function[1]=0x00000000,// 0 +.cfg_board_common_setting.ddr_dmc_remap[0]=0x14941cc5,// 345251013 +.cfg_board_common_setting.ddr_dmc_remap[1]=0x1ee6000b,// 518389771 +.cfg_board_common_setting.ddr_dmc_remap[2]=0x2f6ace51,// 795528785 +.cfg_board_common_setting.ddr_dmc_remap[3]=0x3bcdeb38,// 1003350840 +.cfg_board_common_setting.ddr_dmc_remap[4]=0x000a41be,// 672190 +.cfg_board_common_setting.ac_pinmux[0]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[1]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[2]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[3]=0x00000001,// 1 +.cfg_board_common_setting.ac_pinmux[4]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[5]=0x00000001,// 1 +.cfg_board_common_setting.ac_pinmux[6]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[7]=0x00000005,// 5 +.cfg_board_common_setting.ac_pinmux[8]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[9]=0x00000001,// 1 +.cfg_board_common_setting.ac_pinmux[10]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[11]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[12]=0x00000004,// 4 +.cfg_board_common_setting.ac_pinmux[13]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[14]=0x00000005,// 5 +.cfg_board_common_setting.ac_pinmux[15]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[16]=0x00000001,// 1 +.cfg_board_common_setting.ac_pinmux[17]=0x00000003,// 3 +.cfg_board_common_setting.ac_pinmux[18]=0x00000003,// 3 +.cfg_board_common_setting.ac_pinmux[19]=0x00000004,// 4 +.cfg_board_common_setting.ac_pinmux[20]=0x00000002,// 2 +.cfg_board_common_setting.ac_pinmux[21]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[22]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[23]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[24]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[25]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[26]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[27]=0x00000002,// 2 +.cfg_board_common_setting.ac_pinmux[28]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[29]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[30]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[31]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[32]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[33]=0x00000000,// 0 +.cfg_board_common_setting.ac_pinmux[34]=0x00000000,// 0 +.cfg_board_common_setting.ddr_dqs_swap=0x00000000,// 0 +.cfg_board_common_setting.ddr_dq_remap[0]=0x00000000,// 0 +.cfg_board_common_setting.ddr_dq_remap[1]=0x00000004,// 4 +.cfg_board_common_setting.ddr_dq_remap[2]=0x00000001,// 1 +.cfg_board_common_setting.ddr_dq_remap[3]=0x00000002,// 2 +.cfg_board_common_setting.ddr_dq_remap[4]=0x00000003,// 3 +.cfg_board_common_setting.ddr_dq_remap[5]=0x00000005,// 5 +.cfg_board_common_setting.ddr_dq_remap[6]=0x00000007,// 7 +.cfg_board_common_setting.ddr_dq_remap[7]=0x00000006,// 6 +.cfg_board_common_setting.ddr_dq_remap[8]=0x0000000c,// 12 +.cfg_board_common_setting.ddr_dq_remap[9]=0x0000000d,// 13 +.cfg_board_common_setting.ddr_dq_remap[10]=0x00000009,// 9 +.cfg_board_common_setting.ddr_dq_remap[11]=0x0000000b,// 11 +.cfg_board_common_setting.ddr_dq_remap[12]=0x00000008,// 8 +.cfg_board_common_setting.ddr_dq_remap[13]=0x0000000f,// 15 +.cfg_board_common_setting.ddr_dq_remap[14]=0x0000000e,// 14 +.cfg_board_common_setting.ddr_dq_remap[15]=0x0000000a,// 10 +.cfg_board_common_setting.ddr_dq_remap[16]=0x00000014,// 20 +.cfg_board_common_setting.ddr_dq_remap[17]=0x00000015,// 21 +.cfg_board_common_setting.ddr_dq_remap[18]=0x00000016,// 22 +.cfg_board_common_setting.ddr_dq_remap[19]=0x00000017,// 23 +.cfg_board_common_setting.ddr_dq_remap[20]=0x00000010,// 16 +.cfg_board_common_setting.ddr_dq_remap[21]=0x00000011,// 17 +.cfg_board_common_setting.ddr_dq_remap[22]=0x00000013,// 19 +.cfg_board_common_setting.ddr_dq_remap[23]=0x00000012,// 18 +.cfg_board_common_setting.ddr_dq_remap[24]=0x0000001f,// 31 +.cfg_board_common_setting.ddr_dq_remap[25]=0x0000001d,// 29 +.cfg_board_common_setting.ddr_dq_remap[26]=0x0000001e,// 30 +.cfg_board_common_setting.ddr_dq_remap[27]=0x0000001c,// 28 +.cfg_board_common_setting.ddr_dq_remap[28]=0x00000018,// 24 +.cfg_board_common_setting.ddr_dq_remap[29]=0x0000001a,// 26 +.cfg_board_common_setting.ddr_dq_remap[30]=0x0000001b,// 27 +.cfg_board_common_setting.ddr_dq_remap[31]=0x00000019,// 25 +.cfg_board_common_setting.ddr_dq_remap[32]=0x00000020,// 32 +.cfg_board_common_setting.ddr_dq_remap[33]=0x00000021,// 33 +.cfg_board_common_setting.ddr_dq_remap[34]=0x00000022,// 34 +.cfg_board_common_setting.ddr_dq_remap[35]=0x00000023,// 35 +.cfg_board_common_setting.ddr_vddee_setting[0]=0x00000000,// 0 +.cfg_board_common_setting.ddr_vddee_setting[1]=0x00000000,// 0 +.cfg_board_common_setting.ddr_vddee_setting[2]=0x00000000,// 0 +.cfg_board_common_setting.ddr_vddee_setting[3]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].DRAMFreq=0x00000528,// 1320 +.cfg_board_SI_setting_ps[0].PllBypassEn=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].training_SequenceCtrl=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ddr_odt_config=0x00000001,// 1 +.cfg_board_SI_setting_ps[0].clk_drv_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[0].cs_drv_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[0].ac_drv_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p=0x00000028,// 40 +.cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n=0x00000028,// 40 +.cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n=0x00000050,// 80 +.cfg_board_SI_setting_ps[0].dram_data_drv_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[0].dram_data_odt_ohm=0x00000050,// 80 +.cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].dram_ac_odt_ohm=0x00000078,// 120 +.cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting=0x00000001,// 1 +.cfg_board_SI_setting_ps[0].reserve2=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].vref_ac_permil =0x0000012c,// 300 +.cfg_board_SI_setting_ps[0].vref_soc_data_permil =0x000000a0,// 160 +.cfg_board_SI_setting_ps[0].vref_dram_data_permil=0x0000014a,// 330 +.cfg_board_SI_setting_ps[0].max_core_timmming_frequency=0x00000640,// 1600 +.cfg_board_SI_setting_ps[0].training_phase_parameter[0]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].training_phase_parameter[1]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[0]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[1]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[2]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[3]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[4]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[5]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[6]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[7]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[8]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[9]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[10]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[11]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[12]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[13]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[14]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[15]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[16]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[17]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[18]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[19]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[20]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[21]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[22]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[23]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[24]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[25]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[26]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[27]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[28]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[29]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[30]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[31]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[32]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[33]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[34]=0x00000000,// 0 +.cfg_board_SI_setting_ps[0].ac_trace_delay_org[35]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[0]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[1]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[2]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[3]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[4]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[5]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[6]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[7]=0x00000114,// 0 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[8]=0x00000114,// 276 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[9]=0x00000114,// 276 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[10]=0x0000013c,// 316 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[11]=0x00000114,// 276 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[12]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[13]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[14]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[15]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[16]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[17]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[18]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[19]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[20]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[21]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[22]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[23]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[24]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[25]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[26]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[27]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[28]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[29]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[30]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[31]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[32]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[33]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[34]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].ac_trace_delay[35]=0x00000100,// 256 +.cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125 +.cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000069,// 105 +.cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000087,// 135 +.cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000073,// 115 +.cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x0000007d,// 125 +.cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000069,// 105 +.cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000087,// 135 +.cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000073,// 115 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x00000163,// 355 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000161,// 353 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000015c,// 348 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000016a,// 362 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000170,// 368 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000173,// 371 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x00000161,// 353 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000016d,// 365 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000167,// 359 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000152,// 338 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000159,// 345 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000150,// 336 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x00000156,// 342 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000015c,// 348 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000158,// 344 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000159,// 345 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015a,// 346 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000156,// 342 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000016b,// 363 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x00000174,// 372 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000166,// 358 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000175,// 373 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000173,// 371 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000175,// 373 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000016c,// 364 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000016e,// 366 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000165,// 357 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000170,// 368 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x00000160,// 352 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000176,// 374 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000164,// 356 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x00000164,// 356 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x00000163,// 355 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000161,// 353 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x0000016b,// 363 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000163,// 355 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000161,// 353 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x0000015c,// 348 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x0000016a,// 362 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000170,// 368 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000173,// 371 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000161,// 353 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x0000016d,// 365 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000167,// 359 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000152,// 338 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000159,// 345 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000150,// 336 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000156,// 342 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x0000015c,// 348 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000158,// 344 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000159,// 345 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x0000015a,// 346 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000156,// 342 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x0000016b,// 363 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000174,// 372 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000166,// 358 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000175,// 373 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000173,// 371 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000175,// 373 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x0000016c,// 364 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000173,// 371 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x0000016e,// 366 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000165,// 357 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000170,// 368 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000160,// 352 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000176,// 374 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000164,// 356 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000164,// 356 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000163,// 355 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000161,// 353 +.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x0000016b,// 363 +.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000002fd,// 765 +.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000030f,// 783 +.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x000002f1,// 753 +.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x000002fa,// 762 +.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000002fd,// 765 +.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x0000030f,// 783 +.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x000002f1,// 753 +.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x000002fa,// 762 +.cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 +.cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 +.cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006c,// 108 +.cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000070,// 112 +.cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000075,// 117 +.cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x0000006c,// 108 +.cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x0000006c,// 108 +.cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000070,// 112 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000036,// 54 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003f,// 63 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000034,// 52 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000044,// 68 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000045,// 69 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000034,// 52 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000042,// 66 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x0000003c,// 60 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000033,// 51 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000033,// 51 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000031,// 49 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000031,// 49 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000037,// 55 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000033,// 51 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000039,// 57 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000033,// 51 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000034,// 52 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000037,// 55 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000003f,// 63 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000035,// 53 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000042,// 66 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000003a,// 58 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000046,// 70 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000039,// 57 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000003b,// 59 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000036,// 54 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x0000003f,// 63 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000034,// 52 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000044,// 68 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000045,// 69 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000034,// 52 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000042,// 66 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x0000003c,// 60 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000033,// 51 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000033,// 51 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000031,// 49 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000031,// 49 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000037,// 55 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000033,// 51 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000039,// 57 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000033,// 51 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000034,// 52 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000037,// 55 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x0000003f,// 63 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000035,// 53 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000042,// 66 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x0000003a,// 58 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000046,// 70 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000039,// 57 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x0000003b,// 59 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000038,// 56 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000016,// 22 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000016,// 22 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000016,// 22 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000015,// 21 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000015,// 21 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000015,// 21 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000017,// 23 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000018,// 24 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000050,// 80 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].reserve_training_parameter[0]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].reserve_training_parameter[1]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].reserve_training_parameter[2]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].reserve_training_parameter[3]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].reserve_training_parameter[4]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].reserve_training_parameter[5]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].reserve_training_parameter[6]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[0].reserve_training_parameter[7]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].DRAMFreq=0x0000029b,// 667 +.cfg_board_SI_setting_ps[1].PllBypassEn=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].training_SequenceCtrl=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ddr_odt_config=0x00000001,// 1 +.cfg_board_SI_setting_ps[1].clk_drv_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[1].cs_drv_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[1].ac_drv_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p=0x00000028,// 40 +.cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n=0x00000028,// 40 +.cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p=0x0000003c,// 60 +.cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].dram_data_drv_ohm=0x00000022,// 34 +.cfg_board_SI_setting_ps[1].dram_data_odt_ohm=0x0000003c,// 60 +.cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].dram_ac_odt_ohm=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm=0x00000028,// 40 +.cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting=0x00000001,// 1 +.cfg_board_SI_setting_ps[1].reserve2=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].vref_ac_permil =0x00000000,// 0 +.cfg_board_SI_setting_ps[1].vref_soc_data_permil =0x000000a0,// 160 +.cfg_board_SI_setting_ps[1].vref_dram_data_permil=0x0000012c,// 300 +.cfg_board_SI_setting_ps[1].max_core_timmming_frequency=0x00000640,// 1600 +.cfg_board_SI_setting_ps[1].training_phase_parameter[0]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].training_phase_parameter[1]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[0]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[1]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[2]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[3]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[4]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[5]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[6]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[7]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[8]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[9]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[10]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[11]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[12]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[13]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[14]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[15]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[16]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[17]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[18]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[19]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[20]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[21]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[22]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[23]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[24]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[25]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[26]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[27]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[28]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[29]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[30]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[31]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[32]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[33]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[34]=0x00000000,// 0 +.cfg_board_SI_setting_ps[1].ac_trace_delay_org[35]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[0]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[1]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[2]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[3]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[4]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[5]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[6]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[7]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[8]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[9]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[10]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[11]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[12]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[13]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[14]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[15]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[16]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[17]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[18]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[19]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[20]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[21]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[22]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[23]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[24]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[25]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[26]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[27]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[28]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[29]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[30]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[31]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[32]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[33]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[34]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].ac_trace_delay[35]=0x00000080,// 128 +.cfg_ddr_training_delay_ps[1].write_dqs_delay[0]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].write_dqs_delay[1]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].write_dqs_delay[2]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].write_dqs_delay[3]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].write_dqs_delay[4]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].write_dqs_delay[5]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].write_dqs_delay[6]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].write_dqs_delay[7]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[0]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[1]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[2]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[3]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[4]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[5]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[6]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[7]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[8]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[9]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[10]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[11]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[12]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[13]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[14]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[15]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[16]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[17]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[18]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[19]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[20]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[21]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[22]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[23]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[24]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[25]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[26]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[27]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[28]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[29]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[30]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[31]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[32]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[33]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[34]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[35]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[36]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[37]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[38]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[39]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[40]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[41]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[42]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[43]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[44]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[45]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[46]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[47]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[48]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[49]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[50]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[51]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[52]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[53]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[54]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[55]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[56]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[57]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[58]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[59]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[60]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[61]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[62]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[63]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[64]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[65]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[66]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[67]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[68]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[69]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[70]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[71]=0x00000032,// 50 +.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[0]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[1]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[2]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[3]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[4]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[5]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[6]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[7]=0x000000c0,// 192 +.cfg_ddr_training_delay_ps[1].read_dqs_delay[0]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[1].read_dqs_delay[1]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[1].read_dqs_delay[2]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[1].read_dqs_delay[3]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[1].read_dqs_delay[4]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[1].read_dqs_delay[5]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[1].read_dqs_delay[6]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[1].read_dqs_delay[7]=0x00000040,// 64 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[0]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[1]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[2]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[3]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[4]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[5]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[6]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[7]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[8]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[9]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[10]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[11]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[12]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[13]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[14]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[15]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[16]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[17]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[18]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[19]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[20]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[21]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[22]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[23]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[24]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[25]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[26]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[27]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[28]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[29]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[30]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[31]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[32]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[33]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[34]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[35]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[36]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[37]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[38]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[39]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[40]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[41]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[42]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[43]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[44]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[45]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[46]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[47]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[48]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[49]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[50]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[51]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[52]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[53]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[54]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[55]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[56]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[57]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[58]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[59]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[60]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[61]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[62]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[63]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[64]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[65]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[66]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[67]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[68]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[69]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[70]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[71]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[0]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[1]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[2]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[3]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[4]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[5]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[6]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[7]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[8]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[9]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[10]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[11]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[12]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[13]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[14]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[15]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[16]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[17]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[18]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[19]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[20]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[21]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[22]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[23]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[24]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[25]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[26]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[27]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[28]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[29]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[30]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[31]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[32]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[33]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[34]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[35]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[36]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[37]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[38]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[39]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[40]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[41]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[42]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].soc_bit_vref[43]=0x00000010,// 16 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[0]=0x00000050,// 80 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[1]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[2]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[3]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[4]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[5]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[6]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[7]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[8]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[9]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[10]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[11]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[12]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[13]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[14]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[15]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[16]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[17]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[18]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[19]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[20]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[21]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[22]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[23]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[24]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[25]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[26]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[27]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[28]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[29]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[30]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[31]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[32]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[33]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[34]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].dram_bit_vref[35]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].reserve_training_parameter[0]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].reserve_training_parameter[1]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].reserve_training_parameter[2]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].reserve_training_parameter[3]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].reserve_training_parameter[4]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].reserve_training_parameter[5]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].reserve_training_parameter[6]=0x00000000,// 0 +.cfg_ddr_training_delay_ps[1].reserve_training_parameter[7]=0x00000000,// 0 +}, +#endif +}; + +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif +.ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +};
diff --git a/board/amlogic/c2_af419/Kconfig b/board/amlogic/c2_af419/Kconfig new file mode 100644 index 0000000..99396e9 --- /dev/null +++ b/board/amlogic/c2_af419/Kconfig
@@ -0,0 +1,25 @@ +if TARGET_C2_AF419 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_af419" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_af419" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +endif
diff --git a/board/amlogic/c2_af419/Makefile b/board/amlogic/c2_af419/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_af419/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af419/aml-key/bl2aesiv b/board/amlogic/c2_af419/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af419/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/bl2aeskey b/board/amlogic/c2_af419/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af419/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/bl3xaesiv b/board/amlogic/c2_af419/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af419/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/bl3xaeskey b/board/amlogic/c2_af419/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af419/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/kernelaesiv b/board/amlogic/c2_af419/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_af419/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/kernelaeskey b/board/amlogic/c2_af419/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_af419/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/c2_af419/aml-user-key.sig b/board/amlogic/c2_af419/aml-user-key.sig new file mode 100644 index 0000000..088d1cf --- /dev/null +++ b/board/amlogic/c2_af419/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_af419/c2_af419.c b/board/amlogic/c2_af419/c2_af419.c new file mode 100644 index 0000000..0b7867d --- /dev/null +++ b/board/amlogic/c2_af419/c2_af419.c
@@ -0,0 +1,318 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + return 0; +} + +int board_late_init(void) +{ + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* +* mtd nand partition table, only care the size! +* offset will be calculated by nand driver. +*/ +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "misc", + .offset = 0, + .size = 8 * SZ_8K, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af419/firmware/timing.c b/board/amlogic/c2_af419/firmware/timing.c new file mode 100644 index 0000000..9e5f5ca --- /dev/null +++ b/board/amlogic/c2_af419/firmware/timing.c
@@ -0,0 +1,2775 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if 0//timing_config,af400 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 + +#if 0//timing_config,af409 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,90,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,90,128,128,128,128,384, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 + +#if 1//timing_config,af419 +{ + //af419 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-40,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-40,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 1 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af419 + +#if 0//timing_config,real DDR3 +{ + //real DDR3 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44 + + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} , + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //real DDR3 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end real DDR3 + +#if 0//timing_config,af400 LPDDR4 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 300, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1//default cs cke 0 ,other AC=128 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,0,256, //0,0,0,0,0,0,0,0, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128, + },//total 36 + #endif + //write delay line setting + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + } , + #endif + #if 1 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,26,32,26,32,26,32,26} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 0, 1, + 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, + }, + #endif + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 lpddr4 + +#if 0//timing_config,af409 LPDDR4 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + #if 0 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + },//total 36 + #endif + #if 1 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,40,32,40,32,40,32,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 0, 1, + 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 LPDDR4 + +#if 0 //timing_config,for dd3 pxp +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT , + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + } , + + //ac_group0-ac_group1 + #endif + #if 1 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35, + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 123,124,0,126,127,0,0,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 //real board + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,} , + + + #endif + + #if 1 //for pxp + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8 + + #else + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for dd3 pxp + +#if 0 //timing_config,for ddr4 pxp remap +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT , + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for ddr4 pxp remap +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif +.ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +};
diff --git a/board/amlogic/c2_bla4_bx/Kconfig b/board/amlogic/c2_bla4_bx/Kconfig new file mode 100644 index 0000000..f75643f --- /dev/null +++ b/board/amlogic/c2_bla4_bx/Kconfig
@@ -0,0 +1,37 @@ +if TARGET_C2_BLA4_BX + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_bla4_bx" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_bla4_bx" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +config LED_AW2026 + bool "enable/disable AW2026 LED" + default y + +endif
diff --git a/board/amlogic/c2_bla4_bx/Makefile b/board/amlogic/c2_bla4_bx/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_bla4_bx/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bla4_bx/aml-user-key.sig b/board/amlogic/c2_bla4_bx/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_bla4_bx/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_bla4_bx/c2_bla4_bx.c b/board/amlogic/c2_bla4_bx/c2_bla4_bx.c new file mode 100644 index 0000000..bb85c68 --- /dev/null +++ b/board/amlogic/c2_bla4_bx/c2_bla4_bx.c
@@ -0,0 +1,319 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/leds-aw2026.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + // set to white by default + sys_led_init(WHITE); + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_bid = 0, hw_cid = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HW_BID_2 : GPIOD_8 + * HW_BID_1 : GPIOD_5 + * HW_BID_0 : GPIOD_4 + * HW_CID_2 : GPIOX_10 + * HW_CID_1 : GPIOX_9 + * HW_CID_0 : GPIOX_8 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); + ret = readl(PADCTRL_GPIOX_PULL_EN); + writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_4, GPIOD_5 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); + /* GPIOX_8, GPIOX_9, GPIOX_10 */ + ret = readl(PADCTRL_PIN_MUX_REG7); + writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); + ret = readl(PADCTRL_GPIOX_OEN); + writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_bid = (ret >> 4) & 0x3; + hw_bid |= (ret >> 6) & 0x4; + ret = readl(PADCTRL_GPIOX_I); + hw_cid = (ret >> 8) & 0x7; + + if (BLA4_HW_CID != hw_cid) { + pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); + sys_led_init(YELLOW); + while(1); + } + + ret = (hw_cid << 0x3) | hw_bid; + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bla4_bx/firmware/timing.c b/board/amlogic/c2_bla4_bx/firmware/timing.c new file mode 100755 index 0000000..b703ec3 --- /dev/null +++ b/board/amlogic/c2_bla4_bx/firmware/timing.c
@@ -0,0 +1,1457 @@ +/* + * board/amlogic/c2_bla4_bx/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_DDR4 1 +#define ENABLE_LPDDR4 0 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR4 +{ + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + .cfg_board_common_setting. ddr_dqs_swap = 0, + + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end ENABLE_DDR4 +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_bla4_p0/Kconfig b/board/amlogic/c2_bla4_p0/Kconfig new file mode 100644 index 0000000..a8f75cc --- /dev/null +++ b/board/amlogic/c2_bla4_p0/Kconfig
@@ -0,0 +1,37 @@ +if TARGET_C2_BLA4_P0 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_bla4_p0" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_bla4_p0" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +config LED_AW2026 + bool "enable/disable AW2026 LED" + default y + +endif
diff --git a/board/amlogic/c2_bla4_p0/Makefile b/board/amlogic/c2_bla4_p0/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_bla4_p0/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bla4_p0/aml-user-key.sig b/board/amlogic/c2_bla4_p0/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_bla4_p0/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_bla4_p0/c2_bla4_p0.c b/board/amlogic/c2_bla4_p0/c2_bla4_p0.c new file mode 100644 index 0000000..bb85c68 --- /dev/null +++ b/board/amlogic/c2_bla4_p0/c2_bla4_p0.c
@@ -0,0 +1,319 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/leds-aw2026.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + // set to white by default + sys_led_init(WHITE); + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_bid = 0, hw_cid = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HW_BID_2 : GPIOD_8 + * HW_BID_1 : GPIOD_5 + * HW_BID_0 : GPIOD_4 + * HW_CID_2 : GPIOX_10 + * HW_CID_1 : GPIOX_9 + * HW_CID_0 : GPIOX_8 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); + ret = readl(PADCTRL_GPIOX_PULL_EN); + writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_4, GPIOD_5 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); + /* GPIOX_8, GPIOX_9, GPIOX_10 */ + ret = readl(PADCTRL_PIN_MUX_REG7); + writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); + ret = readl(PADCTRL_GPIOX_OEN); + writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_bid = (ret >> 4) & 0x3; + hw_bid |= (ret >> 6) & 0x4; + ret = readl(PADCTRL_GPIOX_I); + hw_cid = (ret >> 8) & 0x7; + + if (BLA4_HW_CID != hw_cid) { + pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); + sys_led_init(YELLOW); + while(1); + } + + ret = (hw_cid << 0x3) | hw_bid; + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bla4_p0/firmware/timing.c b/board/amlogic/c2_bla4_p0/firmware/timing.c new file mode 100755 index 0000000..a4e5e95 --- /dev/null +++ b/board/amlogic/c2_bla4_p0/firmware/timing.c
@@ -0,0 +1,1457 @@ +/* + * board/amlogic/c2_bla4_p0/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_DDR4 1 +#define ENABLE_LPDDR4 0 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR4 +{ + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + .cfg_board_common_setting. ddr_dqs_swap = 0, + + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end ENABLE_DDR4 +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_bla4_p1/Kconfig b/board/amlogic/c2_bla4_p1/Kconfig new file mode 100644 index 0000000..99d02ec --- /dev/null +++ b/board/amlogic/c2_bla4_p1/Kconfig
@@ -0,0 +1,37 @@ +if TARGET_C2_BLA4_P1 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_bla4_p1" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_bla4_p1" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +config LED_AW2026 + bool "enable/disable AW2026 LED" + default y + +endif
diff --git a/board/amlogic/c2_bla4_p1/Makefile b/board/amlogic/c2_bla4_p1/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_bla4_p1/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bla4_p1/aml-user-key.sig b/board/amlogic/c2_bla4_p1/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_bla4_p1/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_bla4_p1/c2_bla4_p1.c b/board/amlogic/c2_bla4_p1/c2_bla4_p1.c new file mode 100644 index 0000000..bb85c68 --- /dev/null +++ b/board/amlogic/c2_bla4_p1/c2_bla4_p1.c
@@ -0,0 +1,319 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/leds-aw2026.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + // set to white by default + sys_led_init(WHITE); + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_bid = 0, hw_cid = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HW_BID_2 : GPIOD_8 + * HW_BID_1 : GPIOD_5 + * HW_BID_0 : GPIOD_4 + * HW_CID_2 : GPIOX_10 + * HW_CID_1 : GPIOX_9 + * HW_CID_0 : GPIOX_8 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); + ret = readl(PADCTRL_GPIOX_PULL_EN); + writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_4, GPIOD_5 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); + /* GPIOX_8, GPIOX_9, GPIOX_10 */ + ret = readl(PADCTRL_PIN_MUX_REG7); + writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); + ret = readl(PADCTRL_GPIOX_OEN); + writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_bid = (ret >> 4) & 0x3; + hw_bid |= (ret >> 6) & 0x4; + ret = readl(PADCTRL_GPIOX_I); + hw_cid = (ret >> 8) & 0x7; + + if (BLA4_HW_CID != hw_cid) { + pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); + sys_led_init(YELLOW); + while(1); + } + + ret = (hw_cid << 0x3) | hw_bid; + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bla4_p1/firmware/timing.c b/board/amlogic/c2_bla4_p1/firmware/timing.c new file mode 100755 index 0000000..e1067e1 --- /dev/null +++ b/board/amlogic/c2_bla4_p1/firmware/timing.c
@@ -0,0 +1,1457 @@ +/* + * board/amlogic/c2_bla4_p1/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_DDR4 1 +#define ENABLE_LPDDR4 0 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR4 +{ + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + .cfg_board_common_setting. ddr_dqs_swap = 0, + + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end ENABLE_DDR4 +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_bla4_p2/Kconfig b/board/amlogic/c2_bla4_p2/Kconfig new file mode 100644 index 0000000..bbdcb05 --- /dev/null +++ b/board/amlogic/c2_bla4_p2/Kconfig
@@ -0,0 +1,37 @@ +if TARGET_C2_BLA4_P2 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_bla4_p2" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_bla4_p2" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +config LED_AW2026 + bool "enable/disable AW2026 LED" + default y + +endif
diff --git a/board/amlogic/c2_bla4_p2/Makefile b/board/amlogic/c2_bla4_p2/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_bla4_p2/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bla4_p2/aml-user-key.sig b/board/amlogic/c2_bla4_p2/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_bla4_p2/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_bla4_p2/c2_bla4_p2.c b/board/amlogic/c2_bla4_p2/c2_bla4_p2.c new file mode 100644 index 0000000..bb85c68 --- /dev/null +++ b/board/amlogic/c2_bla4_p2/c2_bla4_p2.c
@@ -0,0 +1,319 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/leds-aw2026.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + // set to white by default + sys_led_init(WHITE); + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_bid = 0, hw_cid = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HW_BID_2 : GPIOD_8 + * HW_BID_1 : GPIOD_5 + * HW_BID_0 : GPIOD_4 + * HW_CID_2 : GPIOX_10 + * HW_CID_1 : GPIOX_9 + * HW_CID_0 : GPIOX_8 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); + ret = readl(PADCTRL_GPIOX_PULL_EN); + writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_4, GPIOD_5 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); + /* GPIOX_8, GPIOX_9, GPIOX_10 */ + ret = readl(PADCTRL_PIN_MUX_REG7); + writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); + ret = readl(PADCTRL_GPIOX_OEN); + writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_bid = (ret >> 4) & 0x3; + hw_bid |= (ret >> 6) & 0x4; + ret = readl(PADCTRL_GPIOX_I); + hw_cid = (ret >> 8) & 0x7; + + if (BLA4_HW_CID != hw_cid) { + pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); + sys_led_init(YELLOW); + while(1); + } + + ret = (hw_cid << 0x3) | hw_bid; + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bla4_p2/firmware/timing.c b/board/amlogic/c2_bla4_p2/firmware/timing.c new file mode 100755 index 0000000..dfaec2e --- /dev/null +++ b/board/amlogic/c2_bla4_p2/firmware/timing.c
@@ -0,0 +1,1457 @@ +/* + * board/amlogic/c2_bla4_p2/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_DDR4 1 +#define ENABLE_LPDDR4 0 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR4 +{ + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + .cfg_board_common_setting. ddr_dqs_swap = 0, + + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end ENABLE_DDR4 +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_bsv3_p1/Kconfig b/board/amlogic/c2_bsv3_p1/Kconfig new file mode 100644 index 0000000..fa7a0d3 --- /dev/null +++ b/board/amlogic/c2_bsv3_p1/Kconfig
@@ -0,0 +1,33 @@ +if TARGET_C2_BSV3_P1 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_bsv3_p1" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_bsv3_p1" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +endif
diff --git a/board/amlogic/c2_bsv3_p1/Makefile b/board/amlogic/c2_bsv3_p1/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_bsv3_p1/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_bsv3_p1/aml-user-key.sig b/board/amlogic/c2_bsv3_p1/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_bsv3_p1/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_bsv3_p1/c2_bsv3_p1.c b/board/amlogic/c2_bsv3_p1/c2_bsv3_p1.c new file mode 100644 index 0000000..c04cc81 --- /dev/null +++ b/board/amlogic/c2_bsv3_p1/c2_bsv3_p1.c
@@ -0,0 +1,352 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/led_aw2015.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + return 0; +} + +int board_late_init(void) +{ + unsigned int ret; + enum gpio_state pgood; + struct udevice *ssr; + int err; + + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + /* Read GPIOA_8 (pgood) value */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOA_PULL_EN); + writel(ret & (~(0x1 << 8)), PADCTRL_GPIOA_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOA_8 */ + ret = readl(PADCTRL_PIN_MUX_REGC); + writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REGC); + + /* enable input */ + ret = readl(PADCTRL_GPIOA_OEN); + writel(ret | (0x1 << 8), PADCTRL_GPIOA_OEN); + + /* read pgood value */ + ret = readl(PADCTRL_GPIOA_I); + pgood = (ret >> 8) & 0x1; + + pr_info("pgood=%d\n", pgood); + + err = ssr_probe(&ssr); + + if (err) { + return err; + } + + err = check_power(ssr, pgood); + + if (err) { + sys_led_init(BLINK_YELLOW); + } + + while (err) { + pr_crit("Stop booting kernel due to low ac voltage\n"); + mdelay(1000); + pr_crit("Retrying...\n"); + + /* pgood may change within 4 seconds after transition from AC power to battery */ + /* Read new pgood value before check power */ + ret = readl(PADCTRL_GPIOA_I); + pgood = (ret >> 8) & 0x1; + pr_info("pgood=%d\n", pgood); + + err = check_power(ssr, pgood); + } + + pr_info("Init led device after emmc tuning\n"); + sys_led_init(WHITE); + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_bsv3_p1/firmware/timing.c b/board/amlogic/c2_bsv3_p1/firmware/timing.c new file mode 100755 index 0000000..90a0c48 --- /dev/null +++ b/board/amlogic/c2_bsv3_p1/firmware/timing.c
@@ -0,0 +1,1098 @@ +/* + * board/amlogic/c2_bsv3_p1/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_LPDDR4 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_skt/Kconfig b/board/amlogic/c2_skt/Kconfig new file mode 100644 index 0000000..3c4a8af --- /dev/null +++ b/board/amlogic/c2_skt/Kconfig
@@ -0,0 +1,25 @@ +if TARGET_C2_SKT + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_skt" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_skt" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +endif
diff --git a/board/amlogic/c2_skt/Makefile b/board/amlogic/c2_skt/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_skt/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_skt/aml-key/bl2aesiv b/board/amlogic/c2_skt/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_skt/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/bl2aeskey b/board/amlogic/c2_skt/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_skt/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/bl3xaesiv b/board/amlogic/c2_skt/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_skt/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/bl3xaeskey b/board/amlogic/c2_skt/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_skt/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/kernelaesiv b/board/amlogic/c2_skt/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/c2_skt/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/kernelaeskey b/board/amlogic/c2_skt/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/c2_skt/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/c2_skt/aml-user-key.sig b/board/amlogic/c2_skt/aml-user-key.sig new file mode 100755 index 0000000..088d1cf --- /dev/null +++ b/board/amlogic/c2_skt/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_skt/c2_skt.c b/board/amlogic/c2_skt/c2_skt.c new file mode 100644 index 0000000..db0a652 --- /dev/null +++ b/board/amlogic/c2_skt/c2_skt.c
@@ -0,0 +1,316 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_PXP_EMULATOR + printf("board late init\n"); +#else + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + +#endif + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +/* MUST NOT CHANGE this part unless u know what you are doing! +* inherent parition for descrete bootloader to store fip +* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM +* name must be same with TPL_PART_NAME +*/ +{ + .name = "tpl", + .offset = 0, + .size = 0, +}, +{ + .name = "recovery", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 32*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 304*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} +#endif +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "misc", + .offset = 0, + .size = 8 * SZ_8K, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_skt/firmware/timing.c b/board/amlogic/c2_skt/firmware/timing.c new file mode 100644 index 0000000..20dc4b8 --- /dev/null +++ b/board/amlogic/c2_skt/firmware/timing.c
@@ -0,0 +1,2775 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if 0//timing_config,af400 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 + +#if 1//timing_config,af409 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,90,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,90,128,128,128,128,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256,256,256,256,256, + 256,256,256,256, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266, + 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 + +#if 0//timing_config,af419 +{ + //af419 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-40,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-40,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 1 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af419 + +#if 0//timing_config,real DDR3 +{ + //real DDR3 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-20,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,}, + #endif + #if 0 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32, + 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44 + + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} , + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //real DDR3 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end real DDR3 + +#if 0//timing_config,af400 LPDDR4 +{ + //af400 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 300, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1//default cs cke 0 ,other AC=128 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,0,256, //0,0,0,0,0,0,0,0, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128, + 128+128,128+128,128+128,128+128, + },//total 36 + #endif + //write delay line setting + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128, + } , + #endif + #if 1 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + #endif + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,26,32,26,32,26,32,26} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 0, 1, + 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, + }, + #endif + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af400 lpddr4 + +#if 0//timing_config,af409 LPDDR4 +{ + //af409 + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0}, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 667, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + #if 0 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + },//total 36 + #endif + #if 1 + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + //write delay line setting + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256, + 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,}, + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = { + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,}, + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,40,32,40,32,40,32,40} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + //pinmux setting + #if 0 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 1 //lpddr4 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 0, 1, + 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0, + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 8,15,11,13,9,12,14,10, + 3,0,6,4,5,7,2,1, + 17,18,23,22,20,21,19,16, + 28,30,27,25,26,24,29,31, + 33,32,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + #endif + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + #endif + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end af409 LPDDR4 + +#if 0 //timing_config,for dd3 pxp +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT , + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + } , + + //ac_group0-ac_group1 + #endif + #if 1 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35, + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 123,124,0,126,127,0,0,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 //real board + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64,} , + + + #endif + + #if 1 //for pxp + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8 + + #else + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128, + 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} , + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,42,42,42,42,42, + 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for dd3 pxp + +#if 0 //timing_config,for ddr4 pxp remap +//ddr_set_t ddr_set_t_default= +{ + .cfg_board_common_setting. timming_magic = 0 , + .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_version = 0 , + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) , + .cfg_board_common_setting. timming_struct_real_size = 0 , //0 + .cfg_board_common_setting. fast_boot = {0} , + .cfg_board_common_setting. ddr_func = 0 , + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK , + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 , + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 , + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 , + .cfg_board_common_setting. dram_cs0_base_add = 0 , + .cfg_board_common_setting. dram_cs1_base_add = 0 , + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB , + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB , + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 , + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE , + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC , + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE , + .cfg_board_common_setting. org_tdqs2dq = 0 , + .cfg_board_common_setting. reserve1_test_function = {0} , + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT , + #if 1 //af409 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + #endif + #if 0 //af419 + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1, + }, + #endif + #if 0 + .cfg_board_common_setting. ac_pinmux = + { + 0, 0, 0, 1, 2, 3, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0 + } , + #endif + .cfg_board_common_setting. ddr_dqs_swap = 0 , + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 14,13,12,15,8,9,11,10, + 20,21,22,23,16,17,19,18, + 24,25,28,26,31,30,27,29, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,3,1,0,6,7,4,5, + 11,10,9,8,15,14,13,12, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 3,2,0,1,7,6,5,4, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + //1,0,3,2,5,4,7,6, + #endif + #if 0 + .cfg_board_common_setting. ddr_dq_remap = { + 2,7,1,5,3,6,0,4, + 10,11,15,13,14,9,8,12, + 24,29,26,31,25,28,27,30, + 23,18,21,19,22,17,20,16, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + + #if 1 + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + } , //d0-d31 dm0 dm1 dm2 dm3 + #endif + .cfg_board_common_setting. ddr_vddee_setting = {0} , + + + .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model + .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[0]. reserve2 = 0 , + .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128,128,128,128,128,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + #if 1 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192, + 192,192,192,192,192,192,192,192,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50} , //total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} , + //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),}, + + .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 , + .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 , + .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 , + .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 , + .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM , + .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM , + .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ , + .cfg_board_SI_setting_ps[1]. reserve2 = 0 , + .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 , + .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 , + .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} , + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #if 0 + .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = { + 123,124,125,126,127,128,128,128, + 129,128,127,126,125,124,123,122, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + + #if 1 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + } , //total 36 + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0, + } , //total 36 + #endif + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} , + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} , + #if 1 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10, + 10,10,10,10,10,10,10,10,} , + #endif + #if 0 + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64, + 64,64,64,64,64,64,64,64} , + //total 72 + #endif + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0} , //total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40} , //total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32} , //total 36 + .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} , +}, +#endif //end for ddr4 pxp remap +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif +.ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +};
diff --git a/board/amlogic/c2_spencer_bx/Kconfig b/board/amlogic/c2_spencer_bx/Kconfig new file mode 100644 index 0000000..ec4b712 --- /dev/null +++ b/board/amlogic/c2_spencer_bx/Kconfig
@@ -0,0 +1,29 @@ +if TARGET_C2_SPENCER_BX + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_spencer_bx" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_spencer_bx" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +endif
diff --git a/board/amlogic/c2_spencer_bx/Makefile b/board/amlogic/c2_spencer_bx/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_spencer_bx/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_spencer_bx/aml-user-key.sig b/board/amlogic/c2_spencer_bx/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_spencer_bx/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_spencer_bx/c2_spencer_bx.c b/board/amlogic/c2_spencer_bx/c2_spencer_bx.c new file mode 100644 index 0000000..ba197e9 --- /dev/null +++ b/board/amlogic/c2_spencer_bx/c2_spencer_bx.c
@@ -0,0 +1,274 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/led_aw2015.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); +#ifndef CONFIG_ENABLE_CHARGER_DETECTION + sys_led_init(WHITE); +#endif + + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_spencer_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_spencer_hw_id, 1, 0, do_get_spencer_hw_id, + "get spencer HW_ID and env_set 'hw_id'\n", + "get_spencer_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_spencer_bx/firmware/timing.c b/board/amlogic/c2_spencer_bx/firmware/timing.c new file mode 100755 index 0000000..7edde5c --- /dev/null +++ b/board/amlogic/c2_spencer_bx/firmware/timing.c
@@ -0,0 +1,636 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +} +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_spencer_p1/Kconfig b/board/amlogic/c2_spencer_p1/Kconfig new file mode 100644 index 0000000..f5579c6 --- /dev/null +++ b/board/amlogic/c2_spencer_p1/Kconfig
@@ -0,0 +1,29 @@ +if TARGET_C2_SPENCER_P1 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_spencer_p1" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_spencer_p1" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +endif
diff --git a/board/amlogic/c2_spencer_p1/Makefile b/board/amlogic/c2_spencer_p1/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_spencer_p1/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_spencer_p1/aml-user-key.sig b/board/amlogic/c2_spencer_p1/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_spencer_p1/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_spencer_p1/c2_spencer_p1.c b/board/amlogic/c2_spencer_p1/c2_spencer_p1.c new file mode 100644 index 0000000..ba197e9 --- /dev/null +++ b/board/amlogic/c2_spencer_p1/c2_spencer_p1.c
@@ -0,0 +1,274 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/led_aw2015.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); +#ifndef CONFIG_ENABLE_CHARGER_DETECTION + sys_led_init(WHITE); +#endif + + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_spencer_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_spencer_hw_id, 1, 0, do_get_spencer_hw_id, + "get spencer HW_ID and env_set 'hw_id'\n", + "get_spencer_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_spencer_p1/firmware/timing.c b/board/amlogic/c2_spencer_p1/firmware/timing.c new file mode 100755 index 0000000..7edde5c --- /dev/null +++ b/board/amlogic/c2_spencer_p1/firmware/timing.c
@@ -0,0 +1,636 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +} +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_spencer_p2/Kconfig b/board/amlogic/c2_spencer_p2/Kconfig new file mode 100644 index 0000000..f2f1171 --- /dev/null +++ b/board/amlogic/c2_spencer_p2/Kconfig
@@ -0,0 +1,29 @@ +if TARGET_C2_SPENCER_P2 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_spencer_p2" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_spencer_p2" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +endif
diff --git a/board/amlogic/c2_spencer_p2/Makefile b/board/amlogic/c2_spencer_p2/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_spencer_p2/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_spencer_p2/aml-user-key.sig b/board/amlogic/c2_spencer_p2/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_spencer_p2/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_spencer_p2/c2_spencer_p2.c b/board/amlogic/c2_spencer_p2/c2_spencer_p2.c new file mode 100644 index 0000000..ba197e9 --- /dev/null +++ b/board/amlogic/c2_spencer_p2/c2_spencer_p2.c
@@ -0,0 +1,274 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/led_aw2015.h> +#include <linux/mtd/partitions.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + printf("board init\n"); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); +#ifndef CONFIG_ENABLE_CHARGER_DETECTION + sys_led_init(WHITE); +#endif + + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_spencer_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_spencer_hw_id, 1, 0, do_get_spencer_hw_id, + "get spencer HW_ID and env_set 'hw_id'\n", + "get_spencer_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_spencer_p2/firmware/timing.c b/board/amlogic/c2_spencer_p2/firmware/timing.c new file mode 100755 index 0000000..950f68b --- /dev/null +++ b/board/amlogic/c2_spencer_p2/firmware/timing.c
@@ -0,0 +1,639 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +} +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOA_1/2 input */ + {PADCTRL_GPIOA_O, 0, 0xf, 0, BL2_INIT_STAGE_1, 0}, + +#endif +};
diff --git a/board/amlogic/c2_venus_bx/Kconfig b/board/amlogic/c2_venus_bx/Kconfig new file mode 100644 index 0000000..5c57c17 --- /dev/null +++ b/board/amlogic/c2_venus_bx/Kconfig
@@ -0,0 +1,33 @@ +if TARGET_C2_VENUS_BX + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_venus_bx" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_venus_bx" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +endif
diff --git a/board/amlogic/c2_venus_bx/Makefile b/board/amlogic/c2_venus_bx/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_venus_bx/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_venus_bx/aml-user-key.sig b/board/amlogic/c2_venus_bx/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_venus_bx/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_venus_bx/c2_venus_bx.c b/board/amlogic/c2_venus_bx/c2_venus_bx.c new file mode 100644 index 0000000..c04cc81 --- /dev/null +++ b/board/amlogic/c2_venus_bx/c2_venus_bx.c
@@ -0,0 +1,352 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/led_aw2015.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + return 0; +} + +int board_late_init(void) +{ + unsigned int ret; + enum gpio_state pgood; + struct udevice *ssr; + int err; + + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + /* Read GPIOA_8 (pgood) value */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOA_PULL_EN); + writel(ret & (~(0x1 << 8)), PADCTRL_GPIOA_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOA_8 */ + ret = readl(PADCTRL_PIN_MUX_REGC); + writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REGC); + + /* enable input */ + ret = readl(PADCTRL_GPIOA_OEN); + writel(ret | (0x1 << 8), PADCTRL_GPIOA_OEN); + + /* read pgood value */ + ret = readl(PADCTRL_GPIOA_I); + pgood = (ret >> 8) & 0x1; + + pr_info("pgood=%d\n", pgood); + + err = ssr_probe(&ssr); + + if (err) { + return err; + } + + err = check_power(ssr, pgood); + + if (err) { + sys_led_init(BLINK_YELLOW); + } + + while (err) { + pr_crit("Stop booting kernel due to low ac voltage\n"); + mdelay(1000); + pr_crit("Retrying...\n"); + + /* pgood may change within 4 seconds after transition from AC power to battery */ + /* Read new pgood value before check power */ + ret = readl(PADCTRL_GPIOA_I); + pgood = (ret >> 8) & 0x1; + pr_info("pgood=%d\n", pgood); + + err = check_power(ssr, pgood); + } + + pr_info("Init led device after emmc tuning\n"); + sys_led_init(WHITE); + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_venus_bx/firmware/timing.c b/board/amlogic/c2_venus_bx/firmware/timing.c new file mode 100755 index 0000000..8e8bb78 --- /dev/null +++ b/board/amlogic/c2_venus_bx/firmware/timing.c
@@ -0,0 +1,1098 @@ +/* + * board/amlogic/c2_venus_bx/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_LPDDR4 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_venus_p1/Kconfig b/board/amlogic/c2_venus_p1/Kconfig new file mode 100644 index 0000000..1ffb990 --- /dev/null +++ b/board/amlogic/c2_venus_p1/Kconfig
@@ -0,0 +1,33 @@ +if TARGET_C2_VENUS_P1 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_venus_p1" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_venus_p1" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +endif
diff --git a/board/amlogic/c2_venus_p1/Makefile b/board/amlogic/c2_venus_p1/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_venus_p1/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_venus_p1/aml-user-key.sig b/board/amlogic/c2_venus_p1/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_venus_p1/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_venus_p1/c2_venus_p1.c b/board/amlogic/c2_venus_p1/c2_venus_p1.c new file mode 100644 index 0000000..6bff1dd --- /dev/null +++ b/board/amlogic/c2_venus_p1/c2_venus_p1.c
@@ -0,0 +1,310 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/led_aw2015.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + return 0; +} + +int board_late_init(void) +{ + struct udevice *ssr; + int err; + + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + err = ssr_probe(&ssr); + + if (err) { + return err; + } + + err = check_power(ssr, NOT_AVAILABLE); + + if (err) { + sys_led_init(BLINK_YELLOW); + } + + while (err) { + pr_crit("Stop booting kernel due to low ac voltage\n"); + mdelay(1000); + pr_crit("Retrying...\n"); + + err = check_power(ssr, NOT_AVAILABLE); + } + + pr_info("Init led device after emmc tuning\n"); + sys_led_init(WHITE); + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_venus_p1/firmware/timing.c b/board/amlogic/c2_venus_p1/firmware/timing.c new file mode 100755 index 0000000..86f6bce --- /dev/null +++ b/board/amlogic/c2_venus_p1/firmware/timing.c
@@ -0,0 +1,1085 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_LPDDR4 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_common_setting.ddr_vddee_setting[1] = (0x0 << 24) | +(0x8a << 16) | (0x85 << 8) | (0x8a << 0), + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_venus_p2/Kconfig b/board/amlogic/c2_venus_p2/Kconfig new file mode 100644 index 0000000..3194ef6 --- /dev/null +++ b/board/amlogic/c2_venus_p2/Kconfig
@@ -0,0 +1,33 @@ +if TARGET_C2_VENUS_P2 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_venus_p2" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_venus_p2" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +endif
diff --git a/board/amlogic/c2_venus_p2/Makefile b/board/amlogic/c2_venus_p2/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_venus_p2/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_venus_p2/aml-user-key.sig b/board/amlogic/c2_venus_p2/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_venus_p2/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_venus_p2/c2_venus_p2.c b/board/amlogic/c2_venus_p2/c2_venus_p2.c new file mode 100644 index 0000000..dbc42ff --- /dev/null +++ b/board/amlogic/c2_venus_p2/c2_venus_p2.c
@@ -0,0 +1,324 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/led_aw2015.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + return 0; +} + +int board_late_init(void) +{ + struct udevice *ssr; + int err; + + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + err = ssr_probe(&ssr); + + if (err) { + return err; + } + + err = check_power(ssr, NOT_AVAILABLE); + + if (err) { + sys_led_init(BLINK_YELLOW); + } + + while (err) { + pr_crit("Stop booting kernel due to low ac voltage\n"); + mdelay(1000); + pr_crit("Retrying...\n"); + + err = check_power(ssr, NOT_AVAILABLE); + } + + pr_info("Init led device after emmc tuning\n"); + sys_led_init(WHITE); + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_id = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HWID_4 : GPIOD_9 + * HWID_3 : GPIOD_8 + * HWID_2 : GPIOD_7 + * HWID_1 : GPIOD_6 + * HWID_0 : GPIOD_5 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x1F << 5)), PADCTRL_GPIOD_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_5, GPIOD_6, GPIOD_7 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFFF << 20)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8, GPIOD_9 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xFF << 0)), PADCTRL_PIN_MUX_REG1); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x1F << 5), PADCTRL_GPIOD_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_id = (ret >> 5) & 0x1F; + + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_venus_p2/firmware/timing.c b/board/amlogic/c2_venus_p2/firmware/timing.c new file mode 100755 index 0000000..266efd1 --- /dev/null +++ b/board/amlogic/c2_venus_p2/firmware/timing.c
@@ -0,0 +1,1100 @@ +/* + * board/amlogic/c2_venus_p2/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_LPDDR4 1 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_common_setting.ddr_vddee_setting[1] = (0x0 << 24) | +(0x8a << 16) | (0x85 << 8) | (0x8a << 0), + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_xua4_bx/Kconfig b/board/amlogic/c2_xua4_bx/Kconfig new file mode 100644 index 0000000..b0dde4b --- /dev/null +++ b/board/amlogic/c2_xua4_bx/Kconfig
@@ -0,0 +1,37 @@ +if TARGET_C2_XUA4_BX + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_xua4_bx" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_xua4_bx" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +config LED_AW2026 + bool "enable/disable AW2026 LED" + default y + +endif
diff --git a/board/amlogic/c2_xua4_bx/Makefile b/board/amlogic/c2_xua4_bx/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_xua4_bx/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_xua4_bx/aml-user-key.sig b/board/amlogic/c2_xua4_bx/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_xua4_bx/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_xua4_bx/c2_xua4_bx.c b/board/amlogic/c2_xua4_bx/c2_xua4_bx.c new file mode 100644 index 0000000..9e8cf44 --- /dev/null +++ b/board/amlogic/c2_xua4_bx/c2_xua4_bx.c
@@ -0,0 +1,319 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/leds-aw2026.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + // set to white by default + sys_led_init(WHITE); + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_bid = 0, hw_cid = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HW_BID_2 : GPIOD_8 + * HW_BID_1 : GPIOD_5 + * HW_BID_0 : GPIOD_4 + * HW_CID_2 : GPIOX_10 + * HW_CID_1 : GPIOX_9 + * HW_CID_0 : GPIOX_8 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); + ret = readl(PADCTRL_GPIOX_PULL_EN); + writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_4, GPIOD_5 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); + /* GPIOX_8, GPIOX_9, GPIOX_10 */ + ret = readl(PADCTRL_PIN_MUX_REG7); + writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); + ret = readl(PADCTRL_GPIOX_OEN); + writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_bid = (ret >> 4) & 0x3; + hw_bid |= (ret >> 6) & 0x4; + ret = readl(PADCTRL_GPIOX_I); + hw_cid = (ret >> 8) & 0x7; + + if (XUA4_HW_CID != hw_cid) { + pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); + sys_led_init(YELLOW); + while(1); + } + + ret = (hw_cid << 0x3) | hw_bid; + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_xua4_bx/firmware/timing.c b/board/amlogic/c2_xua4_bx/firmware/timing.c new file mode 100755 index 0000000..6e35a04 --- /dev/null +++ b/board/amlogic/c2_xua4_bx/firmware/timing.c
@@ -0,0 +1,1457 @@ +/* + * board/amlogic/c2_xua4_bx/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_DDR4 1 +#define ENABLE_LPDDR4 0 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR4 +{ + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-50,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + .cfg_board_common_setting. ddr_dqs_swap = 0, + + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end ENABLE_DDR4 +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/c2_xua4_p1/Kconfig b/board/amlogic/c2_xua4_p1/Kconfig new file mode 100644 index 0000000..3af9170 --- /dev/null +++ b/board/amlogic/c2_xua4_p1/Kconfig
@@ -0,0 +1,37 @@ +if TARGET_C2_XUA4_P1 + +config SYS_SOC + default "c2" + +config SYS_BOARD + default "c2_xua4_p1" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "c2_xua4_p1" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default y + help + support plltest command + +config I2C_REGULATOR + bool "use i2c regulator to configure vddee" + default n + +config DDR_WINDOWING_BOOT + bool "enable/disable ddr windowing boot" + default n + +config LED_AW2026 + bool "enable/disable AW2026 LED" + default y + +endif
diff --git a/board/amlogic/c2_xua4_p1/Makefile b/board/amlogic/c2_xua4_p1/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/c2_xua4_p1/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_xua4_p1/aml-user-key.sig b/board/amlogic/c2_xua4_p1/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/c2_xua4_p1/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/c2_xua4_p1/c2_xua4_p1.c b/board/amlogic/c2_xua4_p1/c2_xua4_p1.c new file mode 100644 index 0000000..9e8cf44 --- /dev/null +++ b/board/amlogic/c2_xua4_p1/c2_xua4_p1.c
@@ -0,0 +1,319 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <amlogic/leds-aw2026.h> +#include <linux/mtd/partitions.h> +#include <linux/ssr/ps13216.h> + +DECLARE_GLOBAL_DATA_PTR; + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +unsigned int get_dram_size(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +} + + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = get_dram_size(); + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +void board_init_mem(void) { + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } +} + +int board_init(void) +{ + unsigned int value; + + printf("board init\n"); + + /* set GPIOB_3 to low before emmc init */ + value = readl(PADCTRL_PIN_MUX_REG3); + /* set to gpio pin */ + writel(value & ~(0xf << 12), PADCTRL_PIN_MUX_REG3); + value = readl(PADCTRL_GPIOB_OEN); + /* enable gpio output */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_OEN); + value = readl(PADCTRL_GPIOB_O); + /* set output value to low */ + writel(value & ~(0x1 << 3), PADCTRL_GPIOB_O); + udelay(20000); + + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + pinctrl_devices_active(PIN_CONTROLLER_NUM); + active_clk(); + + // set to white by default + sys_led_init(WHITE); + return 0; +} + +int board_late_init(void) +{ + board_init_mem(); + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ +#ifdef UBOOT_RUN_IN_SRAM + return 0x180000; /* SRAM 1.5MB */ +#else + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ +#endif /* UBOOT_RUN_IN_SRAM */ +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +int do_get_hw_id(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned int hw_bid = 0, hw_cid = 0, ret = 0; + char hw_id_str[8] = {0}; // eg: 0x0A + + /* + * HW_BID_2 : GPIOD_8 + * HW_BID_1 : GPIOD_5 + * HW_BID_0 : GPIOD_4 + * HW_CID_2 : GPIOX_10 + * HW_CID_1 : GPIOX_9 + * HW_CID_0 : GPIOX_8 + * + */ + /* disable gpio pull */ + ret = readl(PADCTRL_GPIOD_PULL_EN); + writel(ret & (~(0x13 << 4)), PADCTRL_GPIOD_PULL_EN); + ret = readl(PADCTRL_GPIOX_PULL_EN); + writel(ret & (~(0x7 << 8)), PADCTRL_GPIOX_PULL_EN); + + /* pin mux to gpio pin */ + /* GPIOD_4, GPIOD_5 */ + ret = readl(PADCTRL_PIN_MUX_REG0); + writel(ret & (~(0xFF << 16)), PADCTRL_PIN_MUX_REG0); + /* GPIOD_8 */ + ret = readl(PADCTRL_PIN_MUX_REG1); + writel(ret & (~(0xF << 0)), PADCTRL_PIN_MUX_REG1); + /* GPIOX_8, GPIOX_9, GPIOX_10 */ + ret = readl(PADCTRL_PIN_MUX_REG7); + writel(ret & (~(0xFFF << 0)), PADCTRL_PIN_MUX_REG7); + + /* enable input */ + ret = readl(PADCTRL_GPIOD_OEN); + writel(ret | (0x13 << 4), PADCTRL_GPIOD_OEN); + ret = readl(PADCTRL_GPIOX_OEN); + writel(ret | (0x7 << 8), PADCTRL_GPIOX_OEN); + + /* read hw id */ + ret = readl(PADCTRL_GPIOD_I); + hw_bid = (ret >> 4) & 0x3; + hw_bid |= (ret >> 6) & 0x4; + ret = readl(PADCTRL_GPIOX_I); + hw_cid = (ret >> 8) & 0x7; + + if (XUA4_HW_CID != hw_cid) { + pr_err("The image doesn't match the device(CID=0x%x)\n", hw_cid); + sys_led_init(YELLOW); + while(1); + } + + ret = (hw_cid << 0x3) | hw_bid; + snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", ret); + env_set("hw_id", hw_id_str); + return 0; +} + +U_BOOT_CMD( + get_hw_id, 1, 0, do_get_hw_id, "get HW_ID and env_set 'hw_id'\n", "get_hw_id" +); + +/* partition table */ +/* partition table for spinand flash */ +#ifdef CONFIG_SPI_NAND +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_xua4_p1/firmware/timing.c b/board/amlogic/c2_xua4_p1/firmware/timing.c new file mode 100755 index 0000000..716d683 --- /dev/null +++ b/board/amlogic/c2_xua4_p1/firmware/timing.c
@@ -0,0 +1,1457 @@ +/* + * board/amlogic/c2_xua4_p1/firmware/timing.c + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define TIMMING_MAX_CONFIG 1 +#define ENABLE_DDR3 0 +#define ENABLE_DDR4 1 +#define ENABLE_LPDDR4 0 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { +#if ENABLE_DDR4 +{ + .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4, + .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096 + .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT, + .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)}, + .cfg_board_common_setting. fast_boot[0] = 0x1, + .cfg_board_common_setting. fast_boot[3] = 0x46, + + //DDR frequercy 1 + .cfg_board_SI_setting_ps[0].DRAMFreq = 1272,//1320,1200,1104,1008,912,792 + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128,128,128-20,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0]. ac_trace_delay = { + 128,128,128-50,128,128,128,128,128, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384,384,384,384,384, + 384,384,384,384, + },//total 36 + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0]. soc_bit_vref = { + 0,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,50,40,50,40,50,40,50},//total 44 + .cfg_ddr_training_delay_ps[0]. dram_bit_vref = { + 0,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 6, (0 << 7) | 6, (1 << 7) | 5, (0 << 7) | 0, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, (1 << 7) | 10, + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + }, + + //pinmux setting + .cfg_board_common_setting. ac_pinmux = { + 0, 0, 0, 1, 2, 3, + 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11, + }, + .cfg_board_common_setting. ddr_dqs_swap = 0, + + .cfg_board_common_setting. ddr_dq_remap = { + 0,1,2,3,4,5,6,7, + 8,9,10,11,12,13,14,15, + 16,17,18,19,20,21,22,23, + 24,25,26,27,28,29,30,31, + 32,33,34,35 + },//d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start + .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_version = 0, + .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting. timming_struct_real_size = 0, //0 + .cfg_board_common_setting. ddr_func = 0, + .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting. dram_cs0_base_add = 0, + .cfg_board_common_setting. dram_cs1_base_add = 0, + + .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting. org_tdqs2dq = 0, + .cfg_board_common_setting. reserve1_test_function = {0}, + .cfg_board_common_setting. ddr_vddee_setting = {0}, + + //DDR frequercy 2 + .cfg_board_SI_setting_ps[1].DRAMFreq = 600, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + + .cfg_ddr_training_delay_ps[1]. ac_trace_delay = { + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128,128,128,128,128, + 128,128,128,128, + },//total 36 + .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0}, + //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32}, + .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = { + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50, + 50,50,50,50,50,50,50,50,}, + + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8 + //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8 + .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0},//total 72 + .cfg_ddr_training_delay_ps[1]. soc_bit_vref = { + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40, + 40,40,40,40,40,40,40,40,40,40,40},//total 44 + .cfg_ddr_training_delay_ps[1]. dram_bit_vref = { + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32,32,32,32,32,32,32,32,32, + 32,32,32},//total 36 + + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end +}, +#endif //end ENABLE_DDR4 +#if ENABLE_DDR3 +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = {0}, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = {0}, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, + .cfg_board_common_setting.ac_pinmux = + { + 0, 0, 0, 1, 2, 3, 0, 1, + 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 12, 13, 14, 15, 0, 0, + 0, 0, 20, 21, 22, 0, 0, 25, + 26, 27, 0 + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + .cfg_board_common_setting.ddr_dq_remap = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, + }, //d0-d31 dm0 dm1 dm2 dm3 + .cfg_board_common_setting.ddr_vddee_setting = {0}, + .cfg_board_SI_setting_ps[0].DRAMFreq = 912, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 128, 128, 128 - 20, 128, 128, 128, 128, 128, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, 384, 384, 384, 384, + 384, 384, 384, 384, + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay = { + 128 - 1, 128 - 1, 128 + 48, 128 + 58, 128 + 32, 128 + 32, 128 + 32, 128 + 32 + }, + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = { + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, 128 + 128, + 128 + 128, 128 + 128, 128 + 128, 128 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, 96 + 128, + }, + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = { + 896, 896, 896, 896, 896, 896, 896, 896 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dqs_delay = { + 64, 64, 50, 40, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[0].soc_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32 + 5, 32, 32 + 5, + 32, 32 + 5, 32, 32 + 5 + }, + .cfg_ddr_training_delay_ps[0].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d,// 125 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000091,// 145 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x0000009b,// 155 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x000000a0,// 160 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x000000c2,// 194 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x000000b0,// 176 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x000000b4,// 180 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x000000ba,// 186 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x000000d5,// 213 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x000000c1,// 193 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x000000d0,// 208 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x000000cc,// 204 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x000000c3,// 195 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x000000be,// 190 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x000000c0,// 192 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x000000c8,// 200 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x000000e0,// 224 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x000000e5,// 229 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x000000e2,// 226 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x000000e9,// 233 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x000000e6,// 230 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x000000eb,// 235 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x000000f5,// 245 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x000000e7,// 231 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x000000fd,// 253 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x000000e8,// 232 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x000000e4,// 228 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x000000ee,// 238 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x000000ec,// 236 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x000000f2,// 242 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x0000038c,// 908 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x0000037a,// 890 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x0000039a,// 922 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x0000007d-0x30,// 125 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x0000006d-0x30,// 109 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x0000006f-0x30,// 111 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000038-0x30,// 56 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004b-0x30,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x0000003b-0x30,// 59 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049-0x30,// 73 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000039-0x30,// 57 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x00000045-0x30,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000034-0x30,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x00000086-0x30,// 134 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000037-0x30,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x00000048-0x30,// 72 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000044-0x30,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x00000042-0x30,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047-0x30,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000007f-0x30,// 127 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x00000040-0x30,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x00000052-0x30,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003d-0x30,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = (0x0000004e)-0x30,// 78 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003c-0x30,// 60 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = (0x0000003e)-0x30,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x0000003f-0x30,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000004c-0x30,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000091-0x30,// 145 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70] = 0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71] = 0x00000000,// 0 + + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {0}, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = {0}, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50 + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0}, +}, +#endif + +#if ENABLE_LPDDR4 //LPDDR4 rank0,timing_config +{ + .cfg_board_common_setting.timming_magic = 0, + .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG, + .cfg_board_common_setting.timming_struct_version = 0, + .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t), + .cfg_board_common_setting.timming_struct_real_size = 0, //0 + .cfg_board_common_setting.fast_boot = { 0 }, + .cfg_board_common_setting.ddr_func = 0, + .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK, + .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4, + .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01, + .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63, + .cfg_board_common_setting.dram_cs0_base_add = 0, + .cfg_board_common_setting.dram_cs1_base_add = 0, + .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, + .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB, + .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16, + .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE, + .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC, + .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE , + .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE, + .cfg_board_common_setting.org_tdqs2dq = 0, + .cfg_board_common_setting.reserve1_test_function = { 0 }, + .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, +#ifdef CONFIG_DDR_WINDOWING_BOOT + .cfg_board_common_setting.fast_boot[0] = 0x1, + .cfg_board_common_setting.fast_boot[3] = 0x46, +#endif + //lpddr4 ac pinmux + .cfg_board_common_setting.ac_pinmux = { + 0, 0, 0, 1, 0, 1, 1, 3, + 0, 4, 4, 2, 0, 0, 1, 0, + 2, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 5, 5, 0, 0, 0, 0, + 0, 0, + }, + .cfg_board_common_setting.ddr_dqs_swap = 0, + + .cfg_board_common_setting.ddr_dq_remap = { + 1, 0, 3, 2, 7, 5, 6, 4, + 9, 15, 13, 14, 10, 11, 12, 8, + 21, 19, 20, 18, 17, 16, 22, 23, + 25, 26, 24, 27, 31, 29, 30, 28, + 32, 33, 34, 35 + }, //d0-d31 dm0 dm1 dm2 dm3 + + .cfg_board_common_setting.ddr_vddee_setting = { 0 }, + .cfg_board_SI_setting_ps[0].DRAMFreq = 1320, + .cfg_board_SI_setting_ps[0].PllBypassEn = 0, + .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM, + .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_80_OHM, + .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[0].reserve2 = 0, + .cfg_board_SI_setting_ps[0].vref_ac_permil = 0, //3000/11, + .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0, //170, + .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0, //280, //330 + .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[0].ac_trace_delay_org = { + 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[0].ac_trace_delay = { + 64 + 128, 64 + 128, 64 + 128-64, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0, + 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128-40, 128 + 20 + 128-10, 128 + 0 + 128, 128 + 0 + 128+10, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, + }, //total 36 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 }, + + .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000af,// 175 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000aa,// 170 + .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000cd,// 205 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x000001cd,// 461 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x000001ba,// 442 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x000001e1,// 481 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x000001d0,// 464 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x000001cc,// 460 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x000001d9,// 473 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x000001da,// 474 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x000001e9,// 489 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x000001e2,// 482 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x000001ea,// 490 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x000001d5,// 469 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x000001c6,// 454 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x000001ce,// 462 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x000001b5,// 437 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x000001c7,// 455 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x000001c4,// 452 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x000001d7,// 471 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x000001eb,// 491 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x000001d1,// 465 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x000001f7,// 503 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x000001d8,// 472 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x000001cf,// 463 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x000001d3,// 467 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x000001c9,// 457 + .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x000001de,// 478 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000003ab,// 939 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000383,// 899 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000395,// 917 + .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000378,// 888 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x0000007e,// 126 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000088,// 136 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000070,// 112 + .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x0000007a,// 122 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000044,// 68 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000054,// 84 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000047,// 71 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000051,// 81 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000037,// 55 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003d,// 61 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000052,// 82 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x0000005b,// 91 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x0000005a,// 90 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x0000004b,// 75 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x0000004f,// 79 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000030,// 48 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000046,// 70 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000042,// 66 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x0000004c,// 76 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000058,// 88 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000045,// 69 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000041,// 65 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000056,// 86 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000003f,// 63 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000055,// 85 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x0000003e,// 62 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000034,// 52 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000036,// 54 + .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000040,// 64 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000013,// 19 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000014,// 20 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000016,// 22 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000015,// 21 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0 + .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { + (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, + (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, (1 << 7) | 8, + (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, (1 << 7) | 0, + }, + .cfg_board_SI_setting_ps[1].DRAMFreq = 667, + .cfg_board_SI_setting_ps[1].PllBypassEn = 0, + .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0, + .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0, + .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM, + .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM, + .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM, + .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM, + .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ, + .cfg_board_SI_setting_ps[1].reserve2 = 0, + .cfg_board_SI_setting_ps[1].vref_ac_permil = 0, + .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0, + .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0, + .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0, + .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 }, + .cfg_board_SI_setting_ps[1].ac_trace_delay_org = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + .cfg_ddr_training_delay_ps[1].ac_trace_delay = { + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, 128, 128, 128, 128, + 128, 128, 128, 128, + }, //total 36 + + .cfg_ddr_training_delay_ps[1].write_dqs_delay = { + 0, 0, 0, 0, 0, 0, 0, 0 + }, + .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = { + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, + }, + .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = { + 192, 192, 192, 192, 192, 192, 192, 192 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dqs_delay = { + 64, 64, 64, 64, 64, 64, 64, 64 + }, //total 8 + .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + }, //total 72 + .cfg_ddr_training_delay_ps[1].soc_bit_vref = { + 0, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40, 40, 40, 40, 40, + 40, 40, 40, 40 + }, //total 44 + .cfg_ddr_training_delay_ps[1].dram_bit_vref = { + 0, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32, 32, 32, 32, 32, + 32, 32, 32, 32 + }, //total 36 + .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 }, +}, +#endif +}; +//ddr timing end + +pll_set_t __pll_setting = { + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif + .spi_ctrl = 0, + .lCustomerID = AML_CUSTOMER_ID, + .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */ + .log_ctrl = (1 << 7) | /* (1<<7), print bl2 log into buffer */ +#ifdef CONFIG_SILENT_CONSOLE + (1<<6), /* do not print log buffer */ +#else + (0<<6), /* print log buffer before run bl31 */ +#endif + .ddr_timming_save_mode = 1, +}; + +ddr_reg_t __ddr_reg[] = { + /* demo, user defined override register */ + {0xaabbccdd, 0, 0, 0, 0, 0}, + {0x11223344, 0, 0, 0, 0, 0}, + {0, 0, 0, 0, 0, 0}, +}; + + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/ +#ifdef CONFIG_I2C_REGULATOR +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0xb +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0xc +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0xd +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xe +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xf +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0x10 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0x11 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0x12 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0x13 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x14 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x15 +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x16 +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x17 +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x18 +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x19 +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x1a +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x1b +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x1c +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x1d +#else + #error "VDDEE val out of range\n" +#endif + +#else + +#if (VDDEE_VAL == 711) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 721) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 731) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 741) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 751) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 761) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 771) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 781) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 791) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 801) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 811) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 821) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 831) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 841) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 851) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 861) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 871) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 881) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 891) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif +#endif + +/* for PWM use */ +/* + * GPIOE_0 PWM_A VDDEE_PWM + * + * GPIOE_1 PWM_B VCCK_PWM + */ +/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */ +#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400) +#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400) + +/* pwm clock and pwm controller */ +#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800) +#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400) +#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400) +#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400) + +bl2_reg_t __bl2_reg[] = { +#ifdef CONFIG_I2C_REGULATOR + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x1 << 1, 0x1 << 1, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOA_5 low */ + {PADCTRL_GPIOA_O, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOA_OEN, 0x0 << 5, 0x1 << 5, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOD_10 low */ + {PADCTRL_GPIOD_O, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* Set GPIOX_11 low */ + {PADCTRL_GPIOX_O, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOX_OEN, 0x0 << 11, 0x1 << 11, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL, 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0x3 << 2, 0x3 << 2, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#ifdef CONFIG_PDVFS_ENABLE + /* table_id, ee_voltage, ...... */ + {1, 0x11, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {2, 0x14, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {3, 0x16, 0x0, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {0x0, VDDEE_VAL_REG, 0x0, 0, BL2_INIT_STAGE_I2C_REGULATOR, 0}, +#endif +#else + /* demo, user defined override register */ + {0, 0, 0xffffffff, 0, 0, 0}, +#ifdef CONFIG_PDVFS_ENABLE + {PWMAB_PWM_A, 0x000c0006, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0}, + {PWMAB_PWM_A, 0x00090009, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_2, 0}, + {PWMAB_PWM_A, 0x0007000b, 0xffffffff, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_3, 0}, +#else + {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, +#endif + {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0}, + /* enable vddcpu dc-dc, set GPIOD_10 high */ + {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0}, + /* set pwm A and pwm B clock rate to 24M, enable them */ + {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3*/ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0}, + {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0}, +#endif +};
diff --git a/board/amlogic/configs/a1_ad401.h b/board/amlogic/configs/a1_ad401.h index 893e36b..856f489 100644 --- a/board/amlogic/configs/a1_ad401.h +++ b/board/amlogic/configs/a1_ad401.h
@@ -210,7 +210,7 @@ /* running in sram */ #define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM +#ifdef CONFIG_UBOOT_RUN_IN_SRAM #define CONFIG_SYS_INIT_SP_ADDR (0x00200000) /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (256*1024) @@ -253,8 +253,8 @@ #error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif /* #define CONFIG_AML_SD_EMMC 1 */ @@ -268,15 +268,8 @@ #endif #define CONFIG_PARTITIONS 1 -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_CMD_NAND 1 - #define CONFIG_MTD_DEVICE 1 - /* #define CONFIG_RBTREE */ - #define CONFIG_CMD_NAND_TORTURE 1 - #define CONFIG_CMD_MTDPARTS 1 - #define CONFIG_MTD_PARTITIONS 1 +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 2 - #define CONFIG_SYS_NAND_BASE_LIST {0} #endif /* vpu */ @@ -344,9 +337,7 @@ /*file system*/ #define CONFIG_DOS_PARTITION 1 #define CONFIG_EFI_PARTITION 1 -#if 0 -#define CONFIG_AML_PARTITION 1 -#endif + /* #define CONFIG_MMC 1 */ #define CONFIG_FS_FAT 1 #define CONFIG_FS_EXT4 1
diff --git a/board/amlogic/configs/a1_ad402.h b/board/amlogic/configs/a1_ad402.h index 893e36b..6496f13 100644 --- a/board/amlogic/configs/a1_ad402.h +++ b/board/amlogic/configs/a1_ad402.h
@@ -11,9 +11,15 @@ /* * platform power init config */ -#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage -#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage -#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage +#define AML_VDDCORE_INIT_VOLTAGE 840 // VCCK power up voltage + /* If AML_VDDCORE_INIT_VOLTAGE_SEL is 1, the voltage of vddee + * will be controlled by efuse. if 0, it is controlled by + * AML_VDDCORE_INIT_VOLTAGE + */ +#define AML_VDDCORE_INIT_VOLTAGE_SEL 1 +#define AML_VDDCORE_INIT_EFUSE_MARGIN 30 +#define AML_VDDCORE_INIT_EFUSE_OFFSET 0xc8 +#define AML_VDDCORE_INIT_EFUSE_BASE_V0LT 680 /* configs for CEC */ /* SMP Definitinos */ @@ -210,7 +216,7 @@ /* running in sram */ #define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM +#ifdef CONFIG_UBOOT_RUN_IN_SRAM #define CONFIG_SYS_INIT_SP_ADDR (0x00200000) /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (256*1024) @@ -253,8 +259,8 @@ #error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif /* #define CONFIG_AML_SD_EMMC 1 */ @@ -268,15 +274,8 @@ #endif #define CONFIG_PARTITIONS 1 -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_CMD_NAND 1 - #define CONFIG_MTD_DEVICE 1 - /* #define CONFIG_RBTREE */ - #define CONFIG_CMD_NAND_TORTURE 1 - #define CONFIG_CMD_MTDPARTS 1 - #define CONFIG_MTD_PARTITIONS 1 +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 2 - #define CONFIG_SYS_NAND_BASE_LIST {0} #endif /* vpu */
diff --git a/board/amlogic/configs/a1_ad409.h b/board/amlogic/configs/a1_ad409.h index fa10181..79e2e5b 100644 --- a/board/amlogic/configs/a1_ad409.h +++ b/board/amlogic/configs/a1_ad409.h
@@ -13,6 +13,14 @@ */ #define AML_VDDCORE_INIT_VOLTAGE 805 // VCCK power up voltage +/* If AML_VDDCORE_INIT_VOLTAGE_SEL is 1, the voltage of vddee + * will be controlled by efuse. if 0, it is controlled by + * AML_VDDCORE_INIT_VOLTAGE + */ +#define AML_VDDCORE_INIT_VOLTAGE_SEL 1 +#define AML_VDDCORE_INIT_EFUSE_MARGIN 30 +#define AML_VDDCORE_INIT_EFUSE_OFFSET 0xc8 +#define AML_VDDCORE_INIT_EFUSE_BASE_V0LT 680 /* SMP Definitinos */ #define CPU_RELEASE_ADDR secondary_boot_func @@ -20,10 +28,6 @@ /* Bootloader Control Block function That is used for recovery and the bootloader to talk to each other */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - /* Serial config */ #define CONFIG_CONS_INDEX 2 #define CONFIG_BAUDRATE 115200 @@ -206,7 +210,7 @@ /* running in sram */ #define UBOOT_RUN_IN_SRAM -#ifdef UBOOT_RUN_IN_SRAM +#ifdef CONFIG_UBOOT_RUN_IN_SRAM #define CONFIG_SYS_INIT_SP_ADDR (0x00200000) /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (256*1024) @@ -250,8 +254,8 @@ #error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif /* #define CONFIG_AML_SD_EMMC 1 */ @@ -268,15 +272,8 @@ #define CONFIG_SYS_NO_FLASH 1 #endif -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_CMD_NAND 1 - #define CONFIG_MTD_DEVICE 1 - /* #define CONFIG_RBTREE */ - #define CONFIG_CMD_NAND_TORTURE 1 - #define CONFIG_CMD_MTDPARTS 1 - #define CONFIG_MTD_PARTITIONS 1 +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 2 - #define CONFIG_SYS_NAND_BASE_LIST {0} #endif /* vpu */
diff --git a/board/amlogic/configs/c1_ae400.h b/board/amlogic/configs/c1_ae400.h index 00b6000..e3e6131 100644 --- a/board/amlogic/configs/c1_ae400.h +++ b/board/amlogic/configs/c1_ae400.h
@@ -18,13 +18,6 @@ /* SMP Definitinos */ #define CPU_RELEASE_ADDR secondary_boot_func -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - /* Serial config */ #define CONFIG_CONS_INDEX 2 #define CONFIG_BAUDRATE 115200 @@ -81,6 +74,7 @@ "fb_height=1080\0" \ "frac_rate_policy=1\0" \ "usb_burning=adnl 1000\0" \ + "usb_force_upgrade=0\0" \ "fdt_high=0x20000000\0"\ "sdcburncfg=aml_sdc_burn.ini\0"\ "EnableSelinux=enforcing\0" \ @@ -100,6 +94,7 @@ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ "\0"\ "upgrade_check="\ + "if itest ${usb_force_upgrade} == 1; then adnl; fi;"\ "echo recovery_status=${recovery_status};"\ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ "run storeargs; run recovery_from_flash;"\ @@ -258,8 +253,24 @@ #error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 #endif /* #define CONFIG_AML_SD_EMMC 1 */ @@ -272,19 +283,9 @@ #define CONFIG_EMMC_DDR52_CLK 35000000 #endif #define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_CMD_NAND 1 - #define CONFIG_MTD_DEVICE 1 - /* #define CONFIG_RBTREE */ - #define CONFIG_CMD_NAND_TORTURE 1 - #define CONFIG_CMD_MTDPARTS 1 - #define CONFIG_MTD_PARTITIONS 1 +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 2 - #define CONFIG_SYS_NAND_BASE_LIST {0} #endif /* vpu */ @@ -394,6 +395,7 @@ #endif /* CONFIG_AML_SECURE_UBOOT */ #define CONFIG_FIP_IMG_SUPPORT 1 +#define CONFIG_MDUMP_COMPRESS 1 #endif
diff --git a/board/amlogic/configs/c1_ae401.h b/board/amlogic/configs/c1_ae401.h index 347e254..01651c5 100644 --- a/board/amlogic/configs/c1_ae401.h +++ b/board/amlogic/configs/c1_ae401.h
@@ -18,13 +18,6 @@ /* SMP Definitinos */ #define CPU_RELEASE_ADDR secondary_boot_func -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - /* Serial config */ #define CONFIG_CONS_INDEX 2 #define CONFIG_BAUDRATE 115200 @@ -258,8 +251,24 @@ #error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 #endif /* #define CONFIG_AML_SD_EMMC 1 */ @@ -276,15 +285,8 @@ #define CONFIG_SYS_NO_FLASH 1 #endif -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_CMD_NAND 1 - #define CONFIG_MTD_DEVICE 1 - /* #define CONFIG_RBTREE */ - #define CONFIG_CMD_NAND_TORTURE 1 - #define CONFIG_CMD_MTDPARTS 1 - #define CONFIG_MTD_PARTITIONS 1 +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined(CONFIG_MTD_SPI_NAND) #define CONFIG_SYS_MAX_NAND_DEVICE 2 - #define CONFIG_SYS_NAND_BASE_LIST {0} #endif /* vpu */
diff --git a/board/amlogic/configs/c1_ae402.h b/board/amlogic/configs/c1_ae402.h new file mode 100644 index 0000000..01651c5 --- /dev/null +++ b/board/amlogic/configs/c1_ae402.h
@@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 940 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "boot_part=boot\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} boot 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} boot 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run storeargs;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +//#define CONFIG_MESON_NFC +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined(CONFIG_MTD_SPI_NAND) + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +//#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 + +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c1_ae409.h b/board/amlogic/configs/c1_ae409.h index ea90938..e12bd0b 100644 --- a/board/amlogic/configs/c1_ae409.h +++ b/board/amlogic/configs/c1_ae409.h
@@ -261,8 +261,24 @@ #error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif -#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) -#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 #endif /* #define CONFIG_AML_SD_EMMC 1 */ @@ -279,15 +295,8 @@ #define CONFIG_SYS_NO_FLASH 1 #endif -#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_CMD_NAND 1 - #define CONFIG_MTD_DEVICE 1 - /* #define CONFIG_RBTREE */ - #define CONFIG_CMD_NAND_TORTURE 1 - #define CONFIG_CMD_MTDPARTS 1 - #define CONFIG_MTD_PARTITIONS 1 +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 2 - #define CONFIG_SYS_NAND_BASE_LIST {0} #endif /* vpu */ @@ -387,7 +396,7 @@ /* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ #define CONFIG_AML_CRYPTO_UBOOT 1 - +//#define CONFIG_AML_SIGNED_UBOOT 1 /* unify build for generate encrypted kernel image SRC : "board/amlogic/(board)/boot.img" DST : "fip/boot.img.encrypt" */
diff --git a/board/amlogic/configs/c1_gq_p2.h b/board/amlogic/configs/c1_gq_p2.h index b10038b..4846982 100644 --- a/board/amlogic/configs/c1_gq_p2.h +++ b/board/amlogic/configs/c1_gq_p2.h
@@ -1,7 +1,21 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + /* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ #ifndef __BOARD_CFG_H__ #define __BOARD_CFG_H__ @@ -39,36 +53,6 @@ #define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ #define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" - -#endif //AML_ENABLE_PRODUCTION_MODE - /* args/envs */ #define CONFIG_SYS_MAXARGS 64 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -80,10 +64,8 @@ "loadaddr_kernel=0x07000000\0"\ "loadaddr_dspa=0x06000000\0"\ "ringtone_addr=0x06800000\0"\ - "dspfw_size=0x200000\0"\ - "ringtone_size=0x100000\0"\ "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ + "usb_burning=adnl\0" \ "fdt_high=0x10000000\0"\ "active_slot=_a\0"\ "boot_part=boot_a\0"\ @@ -96,17 +78,15 @@ "\0"\ "run_dspa="\ "unzip 0x6400000 ${loadaddr_dspa};"\ - "if ext4load mmc ${ringtone_part} ${ringtone_addr} quartz_dsp_bootpackage_v4.bin; then ;"\ + "if ext4load mmc ${ringtone_part} ${ringtone_addr} ringtone.wav; then ;"\ "else echo ringtone file not found!;"\ "fi;"\ - "flushmemory ${ringtone_addr} ${ringtone_size};"\ - "dspset 0 1 1;dsprun 0 ${loadaddr_dspa} ${dspfw_size};"\ + "dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ "\0"\ "storeargs="\ "get_rebootmode;"\ "get_wake_args;"\ "get_chiptype;"\ - "get_cpu_rev;"\ "if test ${reboot_mode} = fastboot; then "\ "setenv reboot_mode warm_reboot;"\ "fi;"\ @@ -116,10 +96,8 @@ "hw_id=${hw_id} "\ "androidboot.reboot_mode=${reboot_mode} "\ "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ "androidboot.hardware="__stringify(BOARD_NAME)" "\ "androidboot.slot_suffix=${active_slot} "\ - "androidboot.bl2_boot_part=${bl2_part} "\ "androidboot.firstboot=${firstboot} "\ "${wake_args} "\ "jtag=${jtag};"\ @@ -141,7 +119,6 @@ "fi;fi;fi;fi;"\ "\0" \ "storeboot="\ - JUDGE_MODE \ "setenv loadaddr ${loadaddr_kernel};"\ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ "echo try upgrade as booting failure; run update;"\ @@ -153,7 +130,7 @@ "\0"\ "recovery_from_fat_dev="\ "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ "bootm ${loadaddr};fi;"\ "\0"\ "recovery_from_udisk="\ @@ -164,13 +141,13 @@ "get_valid_slot;"\ "\0"\ "get_hw_id=" \ - "get_board_hw_id;" \ + "get_gq_hw_id;" \ "\0" \ "oqc_check="\ "setenv test_mode false;"\ "setenv fatload_dev usb;"\ "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt; then "\ "setenv test_mode true;"\ "fi;"\ "fi;"\ @@ -357,7 +334,6 @@ #endif /* CONFIG_AML_SECURE_UBOOT */ #define CONFIG_FIP_IMG_SUPPORT 1 -#define CONFIG_AML_KASLR_SEED #endif
diff --git a/board/amlogic/configs/c1_nq_p2.h b/board/amlogic/configs/c1_nq_p2.h index 84fd01f..59a2341 100644 --- a/board/amlogic/configs/c1_nq_p2.h +++ b/board/amlogic/configs/c1_nq_p2.h
@@ -1,7 +1,21 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ #ifndef __BOARD_CFG_H__ #define __BOARD_CFG_H__ @@ -39,35 +53,6 @@ #define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ #define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ -#ifdef AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is production mode;" -#define CONFIG_AML_PRODUCT_MODE 1 -#ifdef CONFIG_MESON_SERIAL -#define CONFIG_DISABLE_AML_SERIAL 1 -#endif //CONFIG_MESON_SERIAL -#define USB_BURNING_OPTION "echo productmode" -#else //AML_ENABLE_PRODUCTION_MODE -#define JUDGE_MODE "echo this is not production mode;" -#define CONFIG_CMD_BOOTD 1 -#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) -#define CONFIG_CMD_BOOTZ 1 -#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -#ifdef CONFIG_ARM64 -#define CONFIG_CMD_BOOTI 1 -#endif //CONFIG_ARM64 -#define CONFIG_CMD_MEMORY 1 -#define CONFIG_CMD_SOURCE 1 -#ifdef CONFIG_MISC -#define CONFIG_CMD_JTAG 1 -#endif //CONFIG_MISC -#ifdef CONFIG_CMD_BOOTI -#define CONFIG_CMD_LZMADEC 1 -#define CONFIG_CMD_UNZIP 1 -#define CONFIG_LZMA 1 -#endif //CONFIG_CMD_BOOTI -#define USB_BURNING_OPTION "adnl" -#endif //AML_ENABLE_PRODUCTION_MODE - /* args/envs */ #define CONFIG_SYS_MAXARGS 64 #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -78,9 +63,8 @@ "loadaddr_rtos=0x00001000\0"\ "loadaddr_kernel=0x07000000\0"\ "loadaddr_dspa=0x06000000\0"\ - "dspfw_size=0x200000\0"\ "otg_device=1\0" \ - "usb_burning=" USB_BURNING_OPTION "\0" \ + "usb_burning=adnl\0" \ "fdt_high=0x10000000\0"\ "active_slot=_a\0"\ "boot_part=boot_a\0"\ @@ -91,13 +75,12 @@ "\0"\ "run_dspa="\ "unzip 0x6400000 ${loadaddr_dspa};"\ - "dspset 0 1 1;dsprun 0 ${loadaddr_dspa} ${dspfw_size}; "\ + "dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ "\0"\ "storeargs="\ "get_rebootmode;"\ "get_wake_args;"\ "get_chiptype;"\ - "get_cpu_rev;"\ "if test ${reboot_mode} = fastboot; then "\ "setenv reboot_mode warm_reboot;"\ "fi;"\ @@ -107,10 +90,8 @@ "hw_id=${hw_id} "\ "androidboot.reboot_mode=${reboot_mode} "\ "chip_type=${chip_type} "\ - "cpu_rev=${cpu_rev} "\ "androidboot.hardware="__stringify(BOARD_NAME)" "\ "androidboot.slot_suffix=${active_slot} "\ - "androidboot.bl2_boot_part=${bl2_part} "\ "androidboot.firstboot=${firstboot} "\ "${wake_args} "\ "jtag=${jtag};"\ @@ -132,7 +113,6 @@ "fi;fi;fi;fi;"\ "\0" \ "storeboot="\ - JUDGE_MODE \ "setenv loadaddr ${loadaddr_kernel};"\ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ "echo try upgrade as booting failure; run update;"\ @@ -144,7 +124,7 @@ "\0"\ "recovery_from_fat_dev="\ "setenv loadaddr ${loadaddr_kernel};"\ - "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ "bootm ${loadaddr};fi;"\ "\0"\ "recovery_from_udisk="\ @@ -155,13 +135,13 @@ "get_valid_slot;"\ "\0"\ "get_hw_id=" \ - "get_board_hw_id;" \ + "get_nq_hw_id;" \ "\0" \ "oqc_check="\ "setenv test_mode false;"\ "setenv fatload_dev usb;"\ "if usb start 0; then "\ - "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt; then "\ "setenv test_mode true;"\ "fi;"\ "fi;"\ @@ -348,7 +328,6 @@ #endif /* CONFIG_AML_SECURE_UBOOT */ #define CONFIG_FIP_IMG_SUPPORT 1 -#define CONFIG_AML_KASLR_SEED #endif
diff --git a/board/amlogic/configs/c2_2rs4_p1.h b/board/amlogic/configs/c2_2rs4_p1.h new file mode 100644 index 0000000..79d08c4 --- /dev/null +++ b/board/amlogic/configs/c2_2rs4_p1.h
@@ -0,0 +1,464 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_2rs4_p2.h b/board/amlogic/configs/c2_2rs4_p2.h new file mode 100644 index 0000000..79d08c4 --- /dev/null +++ b/board/amlogic/configs/c2_2rs4_p2.h
@@ -0,0 +1,464 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_a049_p0.h b/board/amlogic/configs/c2_a049_p0.h new file mode 100644 index 0000000..2a0da4d --- /dev/null +++ b/board/amlogic/configs/c2_a049_p0.h
@@ -0,0 +1,417 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=adnl\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "run usb_bc_check;" \ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "get_hw_id=" \ + "get_a049_hw_id;" \ + "\0" \ + "usb_bc_check=" \ + "musb bc;" \ + "charger_detect_boot;" \ + "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ + "\0" \ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "run get_hw_id;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_af400.h b/board/amlogic/configs/c2_af400.h new file mode 100644 index 0000000..c4090b2 --- /dev/null +++ b/board/amlogic/configs/c2_af400.h
@@ -0,0 +1,416 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 //VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "otg_device=1\0" \ + "charger_type=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=adnl 1000\0" \ + "usb_force_upgrade=0\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "boot_part=boot\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "if test ${usb_force_upgrade} = 1; then adnl; fi;"\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} charger_type=${charger_type} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "ddr_auto_fast_boot_check 6;"\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid} charger_type=${charger_type};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run storeargs;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_af401.h b/board/amlogic/configs/c2_af401.h new file mode 100644 index 0000000..a51ef41 --- /dev/null +++ b/board/amlogic/configs/c2_af401.h
@@ -0,0 +1,409 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 //VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "boot_part=boot\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "ddr_auto_fast_boot_check 6;"\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run storeargs;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_af409.h b/board/amlogic/configs/c2_af409.h new file mode 100644 index 0000000..583b73e --- /dev/null +++ b/board/amlogic/configs/c2_af409.h
@@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 //VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "boot_part=boot\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "ddr_auto_fast_boot_check 6;"\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run storeargs;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_af419.h b/board/amlogic/configs/c2_af419.h new file mode 100644 index 0000000..583b73e --- /dev/null +++ b/board/amlogic/configs/c2_af419.h
@@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 //VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "boot_part=boot\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "ddr_auto_fast_boot_check 6;"\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run storeargs;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_bla4_bx.h b/board/amlogic/configs/c2_bla4_bx.h new file mode 100644 index 0000000..5e5026e --- /dev/null +++ b/board/amlogic/configs/c2_bla4_bx.h
@@ -0,0 +1,466 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +#define BLA4_HW_CID 0x0 + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOD_2; then "\ + "echo RESET KEY not pressed;"\ + "else "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_bla4_p0.h b/board/amlogic/configs/c2_bla4_p0.h new file mode 100644 index 0000000..5e5026e --- /dev/null +++ b/board/amlogic/configs/c2_bla4_p0.h
@@ -0,0 +1,466 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +#define BLA4_HW_CID 0x0 + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOD_2; then "\ + "echo RESET KEY not pressed;"\ + "else "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_bla4_p1.h b/board/amlogic/configs/c2_bla4_p1.h new file mode 100644 index 0000000..5e5026e --- /dev/null +++ b/board/amlogic/configs/c2_bla4_p1.h
@@ -0,0 +1,466 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +#define BLA4_HW_CID 0x0 + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOD_2; then "\ + "echo RESET KEY not pressed;"\ + "else "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_bla4_p2.h b/board/amlogic/configs/c2_bla4_p2.h new file mode 100644 index 0000000..5e5026e --- /dev/null +++ b/board/amlogic/configs/c2_bla4_p2.h
@@ -0,0 +1,466 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +#define BLA4_HW_CID 0x0 + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOD_2; then "\ + "echo RESET KEY not pressed;"\ + "else "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_bsv3_p1.h b/board/amlogic/configs/c2_bsv3_p1.h new file mode 100644 index 0000000..79d08c4 --- /dev/null +++ b/board/amlogic/configs/c2_bsv3_p1.h
@@ -0,0 +1,464 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_skt.h b/board/amlogic/configs/c2_skt.h new file mode 100644 index 0000000..9902b21 --- /dev/null +++ b/board/amlogic/configs/c2_skt.h
@@ -0,0 +1,421 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 //VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "boot_part=boot\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "ddr_auto_fast_boot_check 6;"\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_PXP_EMULATOR +#define CONFIG_PREBOOT "echo preboot for pxp" +#define CONFIG_BOOTCOMMAND \ + "setenv bootargs console=ttyS0 earlycon=meson,0xfe002000 loglevel=9;\ + setenv dtb_mem_addr 0x6000000;fdt addr 0x6000000;booti 0x8000000 0x7000000 0x6000000;" +#define CONFIG_ENV_IS_NOWHERE 1 +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run storeargs;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) + #define CONFIG_CMD_NAND 1 + #define CONFIG_MTD_DEVICE 1 + #define CONFIG_CMD_UBI 1 + #define CONFIG_CMD_UBIFS 1 + #define CONFIG_RBTREE 1 + #define CONFIG_CMD_MTDPARTS 1 + #define CONFIG_MTD_PARTITIONS 1 + #define CONFIG_MTD_UBI_WL_THRESHOLD 4096 + #define CONFIG_MTD_UBI_BEB_LIMIT 20 +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined(CONFIG_MTD_SPI_NAND) + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_spencer_bx.h b/board/amlogic/configs/c2_spencer_bx.h new file mode 100644 index 0000000..dea7ec5 --- /dev/null +++ b/board/amlogic/configs/c2_spencer_bx.h
@@ -0,0 +1,437 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "run usb_bc_check;" \ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "get_hw_id=" \ + "get_spencer_hw_id;" \ + "\0" \ + "usb_bc_check=" \ + "musb bc;" \ + "charger_detect_boot;" \ + "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ + "\0" \ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "run get_hw_id;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_spencer_p1.h b/board/amlogic/configs/c2_spencer_p1.h new file mode 100644 index 0000000..78ba778 --- /dev/null +++ b/board/amlogic/configs/c2_spencer_p1.h
@@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#define CONFIG_CLI_ENABLED 1 + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=adnl\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "run usb_bc_check;" \ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "get_hw_id=" \ + "get_spencer_hw_id;" \ + "\0" \ + "usb_bc_check=" \ + "musb bc;" \ + "charger_detect_boot;" \ + "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ + "\0" \ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "run get_hw_id;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_spencer_p2.h b/board/amlogic/configs/c2_spencer_p2.h new file mode 100644 index 0000000..78ba778 --- /dev/null +++ b/board/amlogic/configs/c2_spencer_p2.h
@@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#define CONFIG_CLI_ENABLED 1 + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=adnl\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "run usb_bc_check;" \ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "get_hw_id=" \ + "get_spencer_hw_id;" \ + "\0" \ + "usb_bc_check=" \ + "musb bc;" \ + "charger_detect_boot;" \ + "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ + "\0" \ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "run get_hw_id;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_venus_bx.h b/board/amlogic/configs/c2_venus_bx.h new file mode 100644 index 0000000..79d08c4 --- /dev/null +++ b/board/amlogic/configs/c2_venus_bx.h
@@ -0,0 +1,464 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_venus_p1.h b/board/amlogic/configs/c2_venus_p1.h new file mode 100644 index 0000000..d6f8539 --- /dev/null +++ b/board/amlogic/configs/c2_venus_p1.h
@@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#define CONFIG_CLI_ENABLED 1 + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=adnl\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_venus_p2.h b/board/amlogic/configs/c2_venus_p2.h new file mode 100644 index 0000000..0414867 --- /dev/null +++ b/board/amlogic/configs/c2_venus_p2.h
@@ -0,0 +1,428 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#define CONFIG_CLI_ENABLED 1 + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=adnl\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOX_12; then "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "else "\ + "echo RESET KEY not pressed;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_xua4_bx.h b/board/amlogic/configs/c2_xua4_bx.h new file mode 100644 index 0000000..28a3c78 --- /dev/null +++ b/board/amlogic/configs/c2_xua4_bx.h
@@ -0,0 +1,474 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +#define XUA4_HW_CID 0x1 + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "musb bc;" \ + "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "run usb_bc_check;"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "usb_bc_check=" \ + "musb bc;" \ + "charger_detect_boot;" \ + "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ + "\0" \ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOD_2; then "\ + "echo RESET KEY not pressed;"\ + "else "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/c2_xua4_p1.h b/board/amlogic/configs/c2_xua4_p1.h new file mode 100644 index 0000000..28a3c78 --- /dev/null +++ b/board/amlogic/configs/c2_xua4_p1.h
@@ -0,0 +1,474 @@ + +/* + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +#define XUA4_HW_CID 0x1 + +/* UBOOT Facotry usb burning config */ +#ifndef AML_DISABLE_UPDATE_MODE +#define CONFIG_AML_V3_FACTORY_BURN 1 +#define CONFIG_AML_V3_USB_TOOl 1 +#define CONFIG_USB_GADGET_DOWNLOAD 1 +#define CONFIG_FASTBOOT_DWC_PCD 1 +#define CONFIG_USB_DEVICE_V2 1 +#endif + +/* enable command line for bringup */ +#ifdef CONFIG_ENABLE_UBOOT_CLI +#define CONFIG_CLI_ENABLED 1 +#endif + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage +/*if CONFIG_PDVFS_ENABLE is defined, AML_VCCK_INIT_VOLTAGE will be invalid*/ +#define CONFIG_PDVFS_ENABLE + + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +#ifdef AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is production mode;" +#define CONFIG_AML_PRODUCT_MODE 1 +#ifdef CONFIG_FASTBOOT +#define CONFIG_NO_FASTBOOT_FLASHING 1 +#endif //CONFIG_FASTBOOT +#ifdef CONFIG_MESON_SERIAL +#define CONFIG_DISABLE_AML_SERIAL 1 +#endif //CONFIG_MESON_SERIAL +#define USB_BURNING_OPTION "echo productmode" +#else //AML_ENABLE_PRODUCTION_MODE +#define JUDGE_MODE "echo this is not production mode;" +#define CONFIG_CMD_BOOTD 1 +#if (defined(CONFIG_ARM) && !defined(CONFIG_ARM64)) +#define CONFIG_CMD_BOOTZ 1 +#endif //defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI 1 +#endif //CONFIG_ARM64 +#define CONFIG_CMD_MEMORY 1 +#define CONFIG_CMD_SOURCE 1 +#ifdef CONFIG_MISC +#define CONFIG_CMD_JTAG 1 +#endif //CONFIG_MISC +#ifdef CONFIG_CMD_BOOTI +#define CONFIG_CMD_LZMADEC 1 +#define CONFIG_CMD_UNZIP 1 +#define CONFIG_LZMA 1 +#endif //CONFIG_CMD_BOOTI +#define USB_BURNING_OPTION "adnl" + +#endif //AML_ENABLE_PRODUCTION_MODE + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "loadaddr_kernel=0x01080000\0"\ + "loadaddr_dspa=0x06000000\0"\ + "otg_device=1\0" \ + "usb_burning=" USB_BURNING_OPTION "\0" \ + "fdt_high=0x20000000\0"\ + "EnableSelinux=enforcing\0" \ + "boot_part=boot_a\0"\ + "active_slot=_a\0"\ + "Irq_check_en=0\0"\ + "fatload_dev=usb\0"\ + "initargs="\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "run_dspa="\ + "unzip 0x6400000 ${loadaddr_dspa};"\ + "dspset 0 1 0;dspset 0 1 1;dsprun 0 ${loadaddr_dspa}; "\ + "\0"\ + "storeargs="\ + "get_rebootmode;"\ + "get_chiptype;"\ + "get_cpu_rev;"\ + "get_ee_vol;"\ + "if test ${reboot_mode} = fastboot; then "\ + "setenv reboot_mode warm_reboot;"\ + "fi;"\ + "setenv bootargs ${initargs} otg_device=${otg_device} "\ + "gpt " \ + "androidboot.reboot_mode=${reboot_mode} "\ + "hw_id=${hw_id} "\ + "boot_ac_voltage=${boot_ac_voltage} "\ + "chip_type=${chip_type} "\ + "cpu_rev=${cpu_rev} "\ + "vddee=${vddee_voltage} "\ + "irq_check_en=${Irq_check_en} "\ + "androidboot.hardware="__stringify(BOARD_NAME)" "\ + "androidboot.bl2_boot_part=${bl2_part} "\ + "androidboot.slot_suffix=${active_slot} "\ + "androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs};"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "echo reboot_mode:${reboot_mode};"\ + "if test ${reboot_mode} = factory_boot; then " \ + "musb bc;" \ + "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ + "setenv bootargs ${bootargs} androidboot.real_reboot_mode=${real_reboot_mode};"\ + "if imgread kernel system_b ${loadaddr_kernel}; then " \ + "bootm ${loadaddr_kernel};"\ + "fi;" \ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = delayed_reboot; then "\ + "delayed_reboot;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + JUDGE_MODE \ + "setenv loadaddr ${loadaddr_kernel};"\ + "run usb_bc_check;"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_udisk;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img 0x10000000 0; then "\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "ddr_windowing_boot="\ + "ddr_auto_fast_boot_check 6;"\ + "\0"\ + "usb_bc_check=" \ + "musb bc;" \ + "charger_detect_boot;" \ + "setenv bootargs ${bootargs} androidboot.charger_type=${charger_type};"\ + "\0" \ + "oqc_check="\ + "setenv test_mode false;"\ + "setenv fatload_dev usb;"\ + "if usb start 0; then "\ + "if fatload ${fatload_dev} 0 ${loadaddr} OQC.txt 0x100000 0; then "\ + "setenv test_mode true;"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.test_mode=${test_mode};"\ + "\0"\ + "upgrade_and_oqc_key_check="\ + "if gpio input GPIOD_2; then "\ + "echo RESET KEY not pressed;"\ + "else "\ + "echo RESET KEY pressed;"\ + "setenv boot_external_image 1;"\ + "run recovery_from_udisk;"\ + "setenv boot_external_image 0;"\ + "run oqc_check;"\ + "fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + +#ifdef CONFIG_DDR_WINDOWING_BOOT +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run ddr_windowing_boot;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run run_dspa; "\ + "get_hw_id;" \ + "get_boot_ac_voltage;" \ + "run storeargs;"\ + "run upgrade_and_oqc_key_check;"\ + "run switch_bootmode;" +#endif + +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 +/* top hide for NBG file */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/g12a_u200_v1.h b/board/amlogic/configs/g12a_u200_v1.h index e0600c0..9d1075d 100644 --- a/board/amlogic/configs/g12a_u200_v1.h +++ b/board/amlogic/configs/g12a_u200_v1.h
@@ -96,7 +96,7 @@ "firstboot=1\0"\ "upgrade_step=0\0"\ "jtag=disable\0"\ - "loadaddr=1080000\0"\ + "loadaddr=3080000\0"\ "panel_type=lcd_1\0" \ "outputmode=1080p60hz\0" \ "hdmimode=1080p60hz\0" \ @@ -133,7 +133,7 @@ "Irq_check_en=0\0"\ "fs_type=""rootfstype=ramfs""\0"\ "initargs="\ - "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\ + "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\ "\0"\ "upgrade_check="\ "echo upgrade_step=${upgrade_step}; "\ @@ -175,7 +175,11 @@ "fi;fi;fi;fi;fi;fi;"\ "\0" \ "storeboot="\ - "boot_cooling;"\ + "if test ${reboot_mode} = normal; then "\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else "\ + "boot_cooling;"\ + "fi;fi;"\ "get_system_as_root_mode;"\ "echo system_mode: ${system_mode};"\ "if test ${system_mode} = 1; then "\ @@ -391,62 +395,14 @@ #error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + #if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) #error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif -#if 0 -#ifdef CONFIG_MESON_NFC - -/* bootlaoder is construct by bl2 and fip - * when DISCRETE_BOOTLOADER is enabled, bl2 & fip - * will not be stored continuously, and nand layout - * would be bl2|rsv|fip|normal, but not - * bl2|fip|rsv|noraml anymore - */ -#if 0 -#define CONFIG_DISCRETE_BOOTLOADER -#endif - -#ifdef CONFIG_DISCRETE_BOOTLOADER -#if 0 -#define CONFIG_TPL_SIZE_PER_COPY 0x200000 -#define CONFIG_TPL_COPY_NUM 4 -#define CONFIG_TPL_PART_NAME "tpl" -/* for bl2, restricted by romboot */ -/* SKT 1024 pages only support 4 block, so 4 copies */ -#define CONFIG_BL2_COPY_NUM 4 -#endif -#endif /* CONFIG_DISCRETE_BOOTLOADER */ - -/* #define CONFIG_CMD_NAND 1 */ -#define CONFIG_MTD_DEVICE 1 -/* mtd parts of ourown.*/ -#define CONFIG_AML_MTDPART 1 -/* mtd parts by env default way.*/ -/* -#define MTDIDS_NAME_STR "aml_nand.0" -#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR -#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ - "3M@8192K(logo)," \ - "10M(recovery)," \ - "8M(kernel)," \ - "40M(rootfs)," \ - "-(data)" -*/ -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_MTD_UBI_WL_THRESHOLD 4096 -#define CONFIG_MTD_UBI_BEB_LIMIT 20 -#define CONFIG_RBTREE -#define CONFIG_CMD_NAND_TORTURE 1 -#define CONFIG_CMD_MTDPARTS 1 -#define CONFIG_MTD_PARTITIONS 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_SYS_NAND_BASE_LIST {0} -#endif -#endif - /* #define CONFIG_AML_SD_EMMC 1 */ #ifdef CONFIG_AML_SD_EMMC #define CONFIG_GENERIC_MMC 1 @@ -462,14 +418,7 @@ #endif #if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND - #define CONFIG_CMD_NAND 1 - #define CONFIG_MTD_DEVICE 1 - /* #define CONFIG_RBTREE */ - #define CONFIG_CMD_NAND_TORTURE 1 - #define CONFIG_CMD_MTDPARTS 1 - #define CONFIG_MTD_PARTITIONS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 2 - #define CONFIG_SYS_NAND_BASE_LIST {0} #endif /* vpu */
diff --git a/board/amlogic/configs/g12b_w400_v1.h b/board/amlogic/configs/g12b_w400_v1.h index 399c8fb..e31f038 100644 --- a/board/amlogic/configs/g12b_w400_v1.h +++ b/board/amlogic/configs/g12b_w400_v1.h
@@ -45,13 +45,6 @@ #define CONFIG_SARADC_CH 2 #endif -/* Bootloader Control Block function - That is used for recovery and the bootloader to talk to each other - */ -#if 0 -#define CONFIG_BOOTLOADER_CONTROL_BLOCK -#endif - /* Serial config */ #define CONFIG_CONS_INDEX 2 #define CONFIG_BAUDRATE 115200 @@ -175,7 +168,11 @@ "fi;fi;fi;fi;fi;fi;"\ "\0" \ "storeboot="\ - "boot_cooling;"\ + "if test ${reboot_mode} = normal; then "\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else "\ + "boot_cooling;"\ + "fi;fi;"\ "get_system_as_root_mode;"\ "echo system_mode: ${system_mode};"\ "if test ${system_mode} = 1; then "\ @@ -396,6 +393,10 @@ #error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + #if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC) #error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; #endif @@ -445,7 +446,6 @@ #define CONFIG_RBTREE #define CONFIG_CMD_NAND_TORTURE 1 #define CONFIG_CMD_MTDPARTS 1 -#define CONFIG_MTD_PARTITIONS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 2 #define CONFIG_SYS_NAND_BASE_LIST {0} #endif @@ -460,19 +460,9 @@ #define CONFIG_EMMC_DDR52_CLK 35000000 #endif #define CONFIG_PARTITIONS 1 -#if 0 -#define CONFIG_SYS_NO_FLASH 1 -#endif #if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND - #define CONFIG_CMD_NAND 1 - #define CONFIG_MTD_DEVICE y - /* #define CONFIG_RBTREE */ - #define CONFIG_CMD_NAND_TORTURE 1 - #define CONFIG_CMD_MTDPARTS 1 - #define CONFIG_MTD_PARTITIONS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 2 - #define CONFIG_SYS_NAND_BASE_LIST {0} #endif /* vpu */
diff --git a/board/amlogic/configs/sc2_ah212.h b/board/amlogic/configs/sc2_ah212.h new file mode 100644 index 0000000..6787595 --- /dev/null +++ b/board/amlogic/configs/sc2_ah212.h
@@ -0,0 +1,494 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/*if disable uboot console, enable it*/ +//#define CONFIG_SILENT_CONSOLE +#ifdef CONFIG_SILENT_CONSOLE +#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC +#endif + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x03080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "colorattribute=444,8bit\0"\ + "cvbsmode=576cvbs\0" \ + "vout_init=disable\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "hdmichecksum=0x00000000\0" \ + "dolby_status=0\0" \ + "dolby_vision_on=0\0" \ + "frac_rate_policy=1\0" \ + "hdr_policy=0\0" \ + "hdmi_read_edid=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "lock=10101000\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "active_slot=normal\0"\ + "boot_part=boot\0"\ + "vendor_boot_part=vendor_boot\0"\ + "board=ohm\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run init_display;run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \ + "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot 0;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "get_system_as_root_mode;"\ + "echo system_mode in storeboot: ${system_mode};"\ + "get_valid_slot;"\ + "get_avb_mode;"\ + "echo active_slot in storeboot: ${active_slot};"\ + "if test ${system_mode} = 1; then "\ + "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "echo come to vendor_boot true;"\ + "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type};"\ + "fi;"\ + "fi;"\ + "if test ${active_slot} != normal; then "\ + "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\ + "fi;"\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "get_valid_slot;"\ + "echo active_slot: ${active_slot};"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if test ${active_slot} = normal; then "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "if test ${partiton_mode} = normal; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\ + "fi;"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_avb_mode;"\ + "get_valid_slot;"\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv loadaddr_kernel 0x2080000;"\ + "setenv dtb_mem_addr 0x1f00000;"\ + "fi;"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;dovi process;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};dovi set;dovi pkg;vpp hdrpkt;"\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "factory_provision init;"\ + "\0"\ + "upgrade_key="\ + "if gpio input GPIOD_3; then "\ + "echo detect upgrade key; run update;"\ + "fi;"\ + "\0"\ + +#if 1 +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run init_display;"\ + "run storeargs;"\ + "run upgrade_key;" \ + "bcb uboot-command;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT "echo preboot" +#endif +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (96*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +#define CONFIG_CMD_NET 1 +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 + +/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000 + +/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */ +//#define CONFIG_UPDATE_MMU_TABLE + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +//#define CONFIG_AML_HW_SHA2 + +#define CONFIG_MULTI_DTB 1 + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/sc2_ah212_ddr3.h b/board/amlogic/configs/sc2_ah212_ddr3.h new file mode 100644 index 0000000..6787595 --- /dev/null +++ b/board/amlogic/configs/sc2_ah212_ddr3.h
@@ -0,0 +1,494 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/*if disable uboot console, enable it*/ +//#define CONFIG_SILENT_CONSOLE +#ifdef CONFIG_SILENT_CONSOLE +#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC +#endif + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x03080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "colorattribute=444,8bit\0"\ + "cvbsmode=576cvbs\0" \ + "vout_init=disable\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "hdmichecksum=0x00000000\0" \ + "dolby_status=0\0" \ + "dolby_vision_on=0\0" \ + "frac_rate_policy=1\0" \ + "hdr_policy=0\0" \ + "hdmi_read_edid=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "lock=10101000\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "active_slot=normal\0"\ + "boot_part=boot\0"\ + "vendor_boot_part=vendor_boot\0"\ + "board=ohm\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run init_display;run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \ + "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot 0;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "get_system_as_root_mode;"\ + "echo system_mode in storeboot: ${system_mode};"\ + "get_valid_slot;"\ + "get_avb_mode;"\ + "echo active_slot in storeboot: ${active_slot};"\ + "if test ${system_mode} = 1; then "\ + "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "echo come to vendor_boot true;"\ + "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type};"\ + "fi;"\ + "fi;"\ + "if test ${active_slot} != normal; then "\ + "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\ + "fi;"\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "get_valid_slot;"\ + "echo active_slot: ${active_slot};"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if test ${active_slot} = normal; then "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "if test ${partiton_mode} = normal; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\ + "fi;"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_avb_mode;"\ + "get_valid_slot;"\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv loadaddr_kernel 0x2080000;"\ + "setenv dtb_mem_addr 0x1f00000;"\ + "fi;"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;dovi process;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};dovi set;dovi pkg;vpp hdrpkt;"\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "factory_provision init;"\ + "\0"\ + "upgrade_key="\ + "if gpio input GPIOD_3; then "\ + "echo detect upgrade key; run update;"\ + "fi;"\ + "\0"\ + +#if 1 +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run init_display;"\ + "run storeargs;"\ + "run upgrade_key;" \ + "bcb uboot-command;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT "echo preboot" +#endif +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (96*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +#define CONFIG_CMD_NET 1 +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 + +/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000 + +/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */ +//#define CONFIG_UPDATE_MMU_TABLE + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +//#define CONFIG_AML_HW_SHA2 + +#define CONFIG_MULTI_DTB 1 + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/sc2_ah212_lpddr3.h b/board/amlogic/configs/sc2_ah212_lpddr3.h new file mode 100644 index 0000000..6787595 --- /dev/null +++ b/board/amlogic/configs/sc2_ah212_lpddr3.h
@@ -0,0 +1,494 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/*if disable uboot console, enable it*/ +//#define CONFIG_SILENT_CONSOLE +#ifdef CONFIG_SILENT_CONSOLE +#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC +#endif + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x03080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "colorattribute=444,8bit\0"\ + "cvbsmode=576cvbs\0" \ + "vout_init=disable\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "hdmichecksum=0x00000000\0" \ + "dolby_status=0\0" \ + "dolby_vision_on=0\0" \ + "frac_rate_policy=1\0" \ + "hdr_policy=0\0" \ + "hdmi_read_edid=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "lock=10101000\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "active_slot=normal\0"\ + "boot_part=boot\0"\ + "vendor_boot_part=vendor_boot\0"\ + "board=ohm\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run init_display;run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \ + "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot 0;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "get_system_as_root_mode;"\ + "echo system_mode in storeboot: ${system_mode};"\ + "get_valid_slot;"\ + "get_avb_mode;"\ + "echo active_slot in storeboot: ${active_slot};"\ + "if test ${system_mode} = 1; then "\ + "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "echo come to vendor_boot true;"\ + "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type};"\ + "fi;"\ + "fi;"\ + "if test ${active_slot} != normal; then "\ + "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\ + "fi;"\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "get_valid_slot;"\ + "echo active_slot: ${active_slot};"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if test ${active_slot} = normal; then "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "if test ${partiton_mode} = normal; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\ + "fi;"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_avb_mode;"\ + "get_valid_slot;"\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv loadaddr_kernel 0x2080000;"\ + "setenv dtb_mem_addr 0x1f00000;"\ + "fi;"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;dovi process;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};dovi set;dovi pkg;vpp hdrpkt;"\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "factory_provision init;"\ + "\0"\ + "upgrade_key="\ + "if gpio input GPIOD_3; then "\ + "echo detect upgrade key; run update;"\ + "fi;"\ + "\0"\ + +#if 1 +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run init_display;"\ + "run storeargs;"\ + "run upgrade_key;" \ + "bcb uboot-command;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT "echo preboot" +#endif +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (96*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +#define CONFIG_CMD_NET 1 +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 + +/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000 + +/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */ +//#define CONFIG_UPDATE_MMU_TABLE + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +//#define CONFIG_AML_HW_SHA2 + +#define CONFIG_MULTI_DTB 1 + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/sc2_ah212_lpddr4.h b/board/amlogic/configs/sc2_ah212_lpddr4.h new file mode 100644 index 0000000..6787595 --- /dev/null +++ b/board/amlogic/configs/sc2_ah212_lpddr4.h
@@ -0,0 +1,494 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/*if disable uboot console, enable it*/ +//#define CONFIG_SILENT_CONSOLE +#ifdef CONFIG_SILENT_CONSOLE +#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC +#endif + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x03080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "colorattribute=444,8bit\0"\ + "cvbsmode=576cvbs\0" \ + "vout_init=disable\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "hdmichecksum=0x00000000\0" \ + "dolby_status=0\0" \ + "dolby_vision_on=0\0" \ + "frac_rate_policy=1\0" \ + "hdr_policy=0\0" \ + "hdmi_read_edid=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "lock=10101000\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "active_slot=normal\0"\ + "boot_part=boot\0"\ + "vendor_boot_part=vendor_boot\0"\ + "board=ohm\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run init_display;run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \ + "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot 0;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "get_system_as_root_mode;"\ + "echo system_mode in storeboot: ${system_mode};"\ + "get_valid_slot;"\ + "get_avb_mode;"\ + "echo active_slot in storeboot: ${active_slot};"\ + "if test ${system_mode} = 1; then "\ + "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "echo come to vendor_boot true;"\ + "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type};"\ + "fi;"\ + "fi;"\ + "if test ${active_slot} != normal; then "\ + "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\ + "fi;"\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "get_valid_slot;"\ + "echo active_slot: ${active_slot};"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if test ${active_slot} = normal; then "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "if test ${partiton_mode} = normal; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\ + "fi;"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_avb_mode;"\ + "get_valid_slot;"\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv loadaddr_kernel 0x2080000;"\ + "setenv dtb_mem_addr 0x1f00000;"\ + "fi;"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;dovi process;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};dovi set;dovi pkg;vpp hdrpkt;"\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "factory_provision init;"\ + "\0"\ + "upgrade_key="\ + "if gpio input GPIOD_3; then "\ + "echo detect upgrade key; run update;"\ + "fi;"\ + "\0"\ + +#if 1 +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run init_display;"\ + "run storeargs;"\ + "run upgrade_key;" \ + "bcb uboot-command;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT "echo preboot" +#endif +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (96*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +#define CONFIG_CMD_NET 1 +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 + +/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000 + +/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */ +//#define CONFIG_UPDATE_MMU_TABLE + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +//#define CONFIG_AML_HW_SHA2 + +#define CONFIG_MULTI_DTB 1 + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/sc2_ah219.h b/board/amlogic/configs/sc2_ah219.h new file mode 100644 index 0000000..badec91 --- /dev/null +++ b/board/amlogic/configs/sc2_ah219.h
@@ -0,0 +1,485 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x03080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "colorattribute=444,8bit\0"\ + "cvbsmode=576cvbs\0" \ + "vout_init=disable\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "hdmichecksum=0x00000000\0" \ + "dolby_status=0\0" \ + "dolby_vision_on=0\0" \ + "frac_rate_policy=1\0" \ + "hdr_policy=0\0" \ + "hdmi_read_edid=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "lock=10101000\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "active_slot=normal\0"\ + "boot_part=boot\0"\ + "vendor_boot_part=vendor_boot\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run init_display;run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \ + "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot 0;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "get_system_as_root_mode;"\ + "echo system_mode in storeboot: ${system_mode};"\ + "get_valid_slot;"\ + "get_avb_mode;"\ + "echo active_slot in storeboot: ${active_slot};"\ + "if test ${system_mode} = 1; then "\ + "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "echo come to vendor_boot true;"\ + "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type};"\ + "fi;"\ + "fi;"\ + "if test ${active_slot} != normal; then "\ + "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\ + "fi;"\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "get_valid_slot;"\ + "echo active_slot: ${active_slot};"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if test ${active_slot} = normal; then "\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "if test ${partiton_mode} = normal; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else "\ + "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\ + "fi;"\ + "fi;"\ + "fi;"\ + "\0"\ + "bcb_cmd="\ + "get_avb_mode;"\ + "get_valid_slot;"\ + "if test ${vendor_boot_mode} = true; then "\ + "setenv loadaddr_kernel 0x2080000;"\ + "setenv dtb_mem_addr 0x1f00000;"\ + "fi;"\ + "\0"\ + "init_display="\ + "get_rebootmode;"\ + "echo reboot_mode:::: ${reboot_mode};"\ + "if test ${reboot_mode} = quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv reboot_mode_android ""quiescent"";"\ + "setenv dolby_status 0;"\ + "setenv dolby_vision_on 0;"\ + "run storeargs;"\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "osd open;osd clear;"\ + "else "\ + "setenv reboot_mode_android ""normal"";"\ + "run storeargs;"\ + "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;dovi process;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};dovi set;dovi pkg;vpp hdrpkt;"\ + "fi;fi;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "factory_provision init;"\ + "\0"\ + "upgrade_key="\ + "if gpio input GPIOD_3; then "\ + "echo detect upgrade key; run update;"\ + "fi;"\ + "\0"\ + +#if 1 +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run init_display;"\ + "run storeargs;"\ + "run upgrade_key;" \ + "bcb uboot-command;"\ + "run switch_bootmode;" +#else +#define CONFIG_PREBOOT "echo preboot" +#endif +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (96*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +#define CONFIG_CMD_NET 1 +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ +#define CONFIG_CMD_PLLTEST 1 + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 + +/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +//#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/configs/sc2_skt.h b/board/amlogic/configs/sc2_skt.h new file mode 100644 index 0000000..61f1193 --- /dev/null +++ b/board/amlogic/configs/sc2_skt.h
@@ -0,0 +1,409 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __BOARD_CFG_H__ +#define __BOARD_CFG_H__ + +#include <asm/arch/cpu.h> + +/* + * platform power init config + */ + +#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage +#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Bootloader Control Block function + That is used for recovery and the bootloader to talk to each other + */ +#if 0 +#define CONFIG_BOOTLOADER_CONTROL_BLOCK +#endif + +/* Serial config */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 + +/* Enable ir remote wake up for bl30 */ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+ +#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch- +#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power +#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04 +#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF +#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF + +/*config the default parameters for adc power key*/ +#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/ +#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/ + +#define CONFIG_BOOTLOADER_CONTROL_BLOCK + +#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition +#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}" +#else +#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}" +#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition + +/* args/envs */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "firstboot=1\0"\ + "silent=1\0"\ + "upgrade_step=0\0"\ + "jtag=disable\0"\ + "loadaddr=0x00020000\0"\ + "os_ident_addr=0x00500000\0"\ + "loadaddr_rtos=0x00001000\0"\ + "loadaddr_kernel=0x03080000\0"\ + "otg_device=1\0" \ + "panel_type=lcd_1\0" \ + "outputmode=1080p60hz\0" \ + "hdmimode=1080p60hz\0" \ + "cvbsmode=576cvbs\0" \ + "display_width=1920\0" \ + "display_height=1080\0" \ + "display_bpp=16\0" \ + "display_color_index=16\0" \ + "display_layer=osd0\0" \ + "display_color_fg=0xffff\0" \ + "display_color_bg=0\0" \ + "dtb_mem_addr=0x01000000\0" \ + "fb_addr=0x00300000\0" \ + "fb_width=1920\0" \ + "fb_height=1080\0" \ + "frac_rate_policy=1\0" \ + "usb_burning=adnl 1000\0" \ + "fdt_high=0x20000000\0"\ + "sdcburncfg=aml_sdc_burn.ini\0"\ + "EnableSelinux=enforcing\0" \ + "recovery_part=recovery\0"\ + "recovery_offset=0\0"\ + "cvbs_drv=0\0"\ + "osd_reverse=0\0"\ + "video_reverse=0\0"\ + "boot_part=boot\0"\ + "Irq_check_en=0\0"\ + "common_dtb_load=" CONFIG_DTB_LOAD "\0"\ + "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\ + "fatload_dev=usb\0"\ + "fs_type=""rootfstype=ramfs""\0"\ + "initargs="\ + "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\ + "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\ + "\0"\ + "upgrade_check="\ + "echo recovery_status=${recovery_status};"\ + "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\ + "run storeargs; run recovery_from_flash;"\ + "else fi;"\ + "echo upgrade_step=${upgrade_step}; "\ + "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\ + "\0"\ + "storeargs="\ + "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\ + "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\ + "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\ + "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\ + "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\ + "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\ + "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\ + "run cmdline_keys;"\ + "\0"\ + "switch_bootmode="\ + "get_rebootmode;"\ + "if test ${reboot_mode} = factory_reset; then "\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = update; then "\ + "run update;"\ + "else if test ${reboot_mode} = quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "else if test ${reboot_mode} = recovery_quiescent; then "\ + "setenv bootargs ${bootargs} androidboot.quiescent=1;"\ + "run recovery_from_flash;"\ + "else if test ${reboot_mode} = cold_boot; then "\ + "else if test ${reboot_mode} = fastboot; then "\ + "fastboot;"\ + "fi;fi;fi;fi;fi;fi;"\ + "\0" \ + "storeboot="\ + "run get_os_type;"\ + "if test ${os_type} = rtos; then "\ + "setenv loadaddr ${loadaddr_rtos};"\ + "store read ${loadaddr} ${boot_part} 0 0x400000;"\ + "bootm ${loadaddr};"\ + "else if test ${os_type} = kernel; then "\ + "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\ + "else echo wrong OS format ${os_type}; fi;fi;"\ + "echo try upgrade as booting failure; run update;"\ + "\0" \ + "update="\ + /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\ + "run usb_burning; "\ + "run recovery_from_sdcard;"\ + "run recovery_from_udisk;"\ + "run recovery_from_flash;"\ + "\0"\ + "recovery_from_fat_dev="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\ + "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\ + "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\ + "bootm ${loadaddr};fi;"\ + "\0"\ + "recovery_from_udisk="\ + "setenv fatload_dev usb;"\ + "if usb start 0; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_sdcard="\ + "setenv fatload_dev mmc;"\ + "if mmcinfo; then run recovery_from_fat_dev; fi;"\ + "\0"\ + "recovery_from_flash="\ + "setenv loadaddr ${loadaddr_kernel};"\ + "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\ + "if imgread dtb recovery ${dtb_mem_addr}; then "\ + "else echo restore dtb; run common_dtb_load;"\ + "fi;"\ + "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\ + "\0"\ + "bcb_cmd="\ + "get_valid_slot;"\ + "\0"\ + "cmdline_keys="\ + "setenv usid 1234567890; setenv region_code US;"\ + "if keyman init 0x1234; then "\ + "if keyman read usid ${loadaddr} str; then fi;"\ + "if keyman read region_code ${loadaddr} str; then fi;"\ + "if keyman read mac ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\ + "fi;"\ + "if keyman read deviceid ${loadaddr} str; then "\ + "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\ + "fi;"\ + "fi;"\ + "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\ + "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\ + "setenv serial ${usid}; setenv serial# ${usid};"\ + "\0"\ + "upgrade_key="\ + "if gpio input GPIOD_3; then "\ + "echo detect upgrade key; run update;"\ + "fi;"\ + "\0"\ + +#if 0 +#define CONFIG_PREBOOT \ + "run bcb_cmd; "\ + "run upgrade_check;"\ + "run storeargs;"\ + "run upgrade_key;" +#else +#define CONFIG_PREBOOT "echo preboot" +#endif +/* #define CONFIG_ENV_IS_NOWHERE 1 */ +#define CONFIG_ENV_SIZE (64*1024) +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_ANDROID_BOOT_IMAGE 1 +#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/ + +/* ATTENTION */ +/* DDR configs move to board/amlogic/[board]/firmware/timing.c */ + +/* running in sram */ +//#define UBOOT_RUN_IN_SRAM +#ifdef UBOOT_RUN_IN_SRAM +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (256*1024) +#else +#define CONFIG_SYS_INIT_SP_ADDR (0x00200000) +#define CONFIG_SYS_MALLOC_LEN (64*1024*1024) +#endif + +//#define CONFIG_NR_DRAM_BANKS 1 +/* ddr functions */ +#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test +#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp +#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down +#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref +#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function +#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function + +/* storage: emmc/nand/sd */ +#define CONFIG_ENV_OVERWRITE +/* #define CONFIG_CMD_SAVEENV */ +/* fixme, need fix*/ + +#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE) +#error env in amlnand/mmc already be compatible; +#endif + +/* +* storage +* |---------|---------| +* | | +* emmc<--Compatible-->nand +* |-------|-------| +* | | +* MTD<-Exclusive->NFTL +* | +* |***************|***************| +* slc-nand SPI-nand SPI-nor +* (raw nand) +*/ +/* axg only support slc nand */ +/* swither for mtd nand which is for slc only. */ + + +#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT) +#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime; +#endif + +#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC) +#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime; +#endif + +/* #define CONFIG_AML_SD_EMMC 1 */ +#ifdef CONFIG_AML_SD_EMMC + #define CONFIG_GENERIC_MMC 1 + #define CONFIG_CMD_MMC 1 + #define CONFIG_CMD_GPT 1 + #define CONFIG_SYS_MMC_ENV_DEV 1 + #define CONFIG_EMMC_DDR52_EN 0 + #define CONFIG_EMMC_DDR52_CLK 35000000 +#endif +#define CONFIG_PARTITIONS 1 +#if 0 +#define CONFIG_SYS_NO_FLASH 1 +#endif + +#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND + #define CONFIG_SYS_MAX_NAND_DEVICE 2 +#endif + +/* vpu */ +#define AML_VPU_CLK_LEVEL_DFT 7 + +/* osd */ +#define OSD_SCALE_ENABLE +#define AML_OSD_HIGH_VERSION + +/* USB + * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard + * Enable CONFIG_MUSB_UDD for Device functionalities. + */ +/* #define CONFIG_MUSB_UDC 1 */ +/* #define CONFIG_CMD_USB 1 */ + +#define USB_PHY2_PLL_PARAMETER_1 0x09400414 +#define USB_PHY2_PLL_PARAMETER_2 0x927e0000 +#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5 + +#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18) +#define USB_G12x_PHY_PLL_SETTING_2 (0xfff) +#define USB_G12x_PHY_PLL_SETTING_3 (0x78000) +#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004) +#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c) + +#define AML_TXLX_USB 1 +#define AML_USB_V2 1 +#define USB_GENERAL_BIT 3 +#define USB_PHY21_BIT 4 + +/* UBOOT fastboot config */ + + +/* UBOOT Facotry usb/sdcard burning config */ + +/* net */ +/* #define CONFIG_CMD_NET 1 */ +#define CONFIG_ETH_DESIGNWARE +#if defined(CONFIG_CMD_NET) + #define CONFIG_DESIGNWARE_ETH 1 + #define CONFIG_PHYLIB 1 + #define CONFIG_NET_MULTI 1 + #define CONFIG_CMD_PING 1 + #define CONFIG_CMD_DHCP 1 + #define CONFIG_CMD_RARP 1 + #define CONFIG_HOSTNAME "arm_gxbb" +#if 0 + #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */ +#endif + #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */ + #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */ + #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */ + #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */ + #define CONFIG_NETMASK 255.255.255.0 +#endif /* (CONFIG_CMD_NET) */ + +#define MAC_ADDR_NEW 1 + +/* other devices */ +#define CONFIG_SHA1 1 +#define CONFIG_MD5 1 + +/* commands */ +#define CONFIG_CMD_PLLTEST 1 + +/*file system*/ +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_EFI_PARTITION 1 +/* #define CONFIG_MMC 1 */ +#define CONFIG_FS_FAT 1 +#define CONFIG_FS_EXT4 1 +#define CONFIG_LZO 1 + +/* Cache Definitions */ +/* #define CONFIG_SYS_DCACHE_OFF */ +/* #define CONFIG_SYS_ICACHE_OFF */ + +/* other functions */ +#define CONFIG_LIBAVB 1 + +/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */ +#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000 + +#define CONFIG_CPU_ARMV8 + +//use sha2 command +#define CONFIG_CMD_SHA2 + +//use hardware sha2 +#define CONFIG_AML_HW_SHA2 + +/* #define CONFIG_MULTI_DTB 1 */ + +/* support secure boot */ +#define CONFIG_AML_SECURE_UBOOT 1 + +#if defined(CONFIG_AML_SECURE_UBOOT) + +/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */ +#define CONFIG_AML_CRYPTO_UBOOT 1 +//#define CONFIG_AML_SIGNED_UBOOT 1 +/* unify build for generate encrypted kernel image + SRC : "board/amlogic/(board)/boot.img" + DST : "fip/boot.img.encrypt" */ +/* #define CONFIG_AML_CRYPTO_IMG 1 */ + +#endif /* CONFIG_AML_SECURE_UBOOT */ + +#define CONFIG_FIP_IMG_SUPPORT 1 + +#endif +
diff --git a/board/amlogic/defconfigs/a1_ad401_nand_linux_defconfig b/board/amlogic/defconfigs/a1_ad401_nand_linux_defconfig index 70aa20a..d6ca433 100644 --- a/board/amlogic/defconfigs/a1_ad401_nand_linux_defconfig +++ b/board/amlogic/defconfigs/a1_ad401_nand_linux_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -25,6 +26,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_SETEXPR is not set @@ -42,6 +44,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -73,6 +76,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_ad401_nand_rtos_defconfig b/board/amlogic/defconfigs/a1_ad401_nand_rtos_defconfig index 89e37ff..7642ac9 100644 --- a/board/amlogic/defconfigs/a1_ad401_nand_rtos_defconfig +++ b/board/amlogic/defconfigs/a1_ad401_nand_rtos_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -25,6 +26,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_SETEXPR is not set @@ -42,6 +44,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -73,6 +76,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_ad401_nor_rtos_defconfig b/board/amlogic/defconfigs/a1_ad401_nor_rtos_defconfig index ea9f32b..b283faa 100644 --- a/board/amlogic/defconfigs/a1_ad401_nor_rtos_defconfig +++ b/board/amlogic/defconfigs/a1_ad401_nor_rtos_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -23,6 +24,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_ITEST is not set @@ -41,6 +43,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -77,6 +80,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_ad402_nand_linux_defconfig b/board/amlogic/defconfigs/a1_ad402_nand_linux_defconfig index 012765b..6ae5670 100644 --- a/board/amlogic/defconfigs/a1_ad402_nand_linux_defconfig +++ b/board/amlogic/defconfigs/a1_ad402_nand_linux_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -25,6 +26,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_SETEXPR is not set @@ -42,6 +44,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -73,6 +76,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_ad402_nand_rtos_defconfig b/board/amlogic/defconfigs/a1_ad402_nand_rtos_defconfig index 946fb2e..1966a60 100644 --- a/board/amlogic/defconfigs/a1_ad402_nand_rtos_defconfig +++ b/board/amlogic/defconfigs/a1_ad402_nand_rtos_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -25,6 +26,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_SETEXPR is not set @@ -42,6 +44,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -73,6 +76,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_ad402_nor_rtos_defconfig b/board/amlogic/defconfigs/a1_ad402_nor_rtos_defconfig index 1077300..f6842a9 100644 --- a/board/amlogic/defconfigs/a1_ad402_nor_rtos_defconfig +++ b/board/amlogic/defconfigs/a1_ad402_nor_rtos_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -23,6 +24,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_ITEST is not set @@ -41,6 +43,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -76,6 +79,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_ad409_nand_linux_defconfig b/board/amlogic/defconfigs/a1_ad409_nand_linux_defconfig index e412693..c9ffa83 100644 --- a/board/amlogic/defconfigs/a1_ad409_nand_linux_defconfig +++ b/board/amlogic/defconfigs/a1_ad409_nand_linux_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -25,6 +26,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_SETEXPR is not set @@ -42,6 +44,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -73,6 +76,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_ad409_nand_rtos_defconfig b/board/amlogic/defconfigs/a1_ad409_nand_rtos_defconfig index d3f3c61..8704c83 100644 --- a/board/amlogic/defconfigs/a1_ad409_nand_rtos_defconfig +++ b/board/amlogic/defconfigs/a1_ad409_nand_rtos_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -25,6 +26,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_SETEXPR is not set @@ -42,6 +44,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -73,6 +76,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_ad409_nor_rtos_defconfig b/board/amlogic/defconfigs/a1_ad409_nor_rtos_defconfig index c215ded..daa737a 100644 --- a/board/amlogic/defconfigs/a1_ad409_nor_rtos_defconfig +++ b/board/amlogic/defconfigs/a1_ad409_nor_rtos_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARCH_MESON=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -24,6 +25,7 @@ # CONFIG_CMD_LOADS is not set CONFIG_CMD_MTD=y CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_SARADC=y # CONFIG_CMD_ITEST is not set @@ -42,6 +44,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y @@ -78,6 +81,7 @@ CONFIG_MESON_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y CONFIG_AML_SPIFCV2=y CONFIG_USB=y CONFIG_DM_USB=y
diff --git a/board/amlogic/defconfigs/a1_pxp_defconfig b/board/amlogic/defconfigs/a1_pxp_defconfig index f0ec35a..aaac89c 100644 --- a/board/amlogic/defconfigs/a1_pxp_defconfig +++ b/board/amlogic/defconfigs/a1_pxp_defconfig
@@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_MESON_A1=y CONFIG_PXP_EMULATOR=y +CONFIG_UBOOT_RUN_IN_SRAM=y CONFIG_AML_TSENSOR=y CONFIG_AML_TSENSOR_COOL=y CONFIG_NEED_BL32=y @@ -42,6 +43,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_A1=y
diff --git a/board/amlogic/defconfigs/c1_ae400_defconfig b/board/amlogic/defconfigs/c1_ae400_defconfig index 8320a61..63d7b46 100644 --- a/board/amlogic/defconfigs/c1_ae400_defconfig +++ b/board/amlogic/defconfigs/c1_ae400_defconfig
@@ -43,10 +43,14 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_C1=y CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_FLASH_NAND=y +CONFIG_FASTBOOT_FLASH=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y @@ -56,6 +60,8 @@ CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_NAND=y +CONFIG_MESON_NFC=y +# CONFIG_MTD_SPI_NAND is not set CONFIG_DM_SPI_FLASH=y CONFIG_DM_ETH=y CONFIG_PHY=y
diff --git a/board/amlogic/defconfigs/c1_ae401_defconfig b/board/amlogic/defconfigs/c1_ae401_defconfig index 628c7ef..03d9acd 100644 --- a/board/amlogic/defconfigs/c1_ae401_defconfig +++ b/board/amlogic/defconfigs/c1_ae401_defconfig
@@ -43,10 +43,14 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_C1=y CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_FLASH_NAND=y +CONFIG_FASTBOOT_FLASH=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y @@ -56,6 +60,8 @@ CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_NAND=y +CONFIG_MESON_NFC=y +# CONFIG_MTD_SPI_NAND is not set CONFIG_DM_SPI_FLASH=y CONFIG_DM_ETH=y CONFIG_PHY=y
diff --git a/board/amlogic/defconfigs/c1_ae402_defconfig b/board/amlogic/defconfigs/c1_ae402_defconfig new file mode 100644 index 0000000..bcb4b4c --- /dev/null +++ b/board/amlogic/defconfigs/c1_ae402_defconfig
@@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C1=y +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C1_AE402=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c1_ae402# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_MTDPARTS=y +# CONFIG_CMD_RSVMEM is not set +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c1-c308x-ae402" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C1=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_MESON_NFC=y +# CONFIG_MTD_SPI_NAND is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C1=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c1_ae409_defconfig b/board/amlogic/defconfigs/c1_ae409_defconfig index 91617a8..c3169cb 100644 --- a/board/amlogic/defconfigs/c1_ae409_defconfig +++ b/board/amlogic/defconfigs/c1_ae409_defconfig
@@ -42,10 +42,14 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_C1=y CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_FLASH_NAND=y +CONFIG_FASTBOOT_FLASH=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MESON=y @@ -56,6 +60,7 @@ CONFIG_MTD=y CONFIG_NAND=y CONFIG_MESON_NFC=y +# CONFIG_MTD_SPI_NAND is not set CONFIG_DM_SPI_FLASH=y CONFIG_PHYLIB=y CONFIG_PHY_AMLOGIC=y
diff --git a/board/amlogic/defconfigs/c1_gq_bx_defconfig b/board/amlogic/defconfigs/c1_gq_bx_defconfig index 1860678..2a9747a 100644 --- a/board/amlogic/defconfigs/c1_gq_bx_defconfig +++ b/board/amlogic/defconfigs/c1_gq_bx_defconfig
@@ -101,7 +101,7 @@ CONFIG_BOOTLOADER_CONTROL_BLOCK=y CONFIG_CMD_BOOTCTOL_AVB=y CONFIG_G_AB_SYSTEM=y -CONFIG_CMD_DDR_TEST=n +CONFIG_CMD_DDR_TEST=y CONFIG_LZ4=y CONFIG_CMD_NET=n CONFIG_CMD_BOOTD=n @@ -127,9 +127,3 @@ CONFIG_CMD_FLASH=n CONFIG_CMD_UUID=n CONFIG_CMD_PINMUX=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set
diff --git a/board/amlogic/defconfigs/c1_gq_p2_defconfig b/board/amlogic/defconfigs/c1_gq_p2_defconfig index fe7a282..adce613 100644 --- a/board/amlogic/defconfigs/c1_gq_p2_defconfig +++ b/board/amlogic/defconfigs/c1_gq_p2_defconfig
@@ -101,7 +101,7 @@ CONFIG_BOOTLOADER_CONTROL_BLOCK=y CONFIG_CMD_BOOTCTOL_AVB=y CONFIG_G_AB_SYSTEM=y -CONFIG_CMD_DDR_TEST=n +CONFIG_CMD_DDR_TEST=y CONFIG_LZ4=y CONFIG_CMD_NET=n CONFIG_CMD_BOOTD=n
diff --git a/board/amlogic/defconfigs/c1_nq_bx_defconfig b/board/amlogic/defconfigs/c1_nq_bx_defconfig index b6773e5..0fdbaf6 100644 --- a/board/amlogic/defconfigs/c1_nq_bx_defconfig +++ b/board/amlogic/defconfigs/c1_nq_bx_defconfig
@@ -101,7 +101,7 @@ CONFIG_BOOTLOADER_CONTROL_BLOCK=y CONFIG_CMD_BOOTCTOL_AVB=y CONFIG_G_AB_SYSTEM=y -CONFIG_CMD_DDR_TEST=n +CONFIG_CMD_DDR_TEST=y CONFIG_LZ4=y CONFIG_CMD_NET=n CONFIG_CMD_BOOTD=n @@ -127,9 +127,3 @@ CONFIG_CMD_FLASH=n CONFIG_CMD_UUID=n CONFIG_CMD_PINMUX=n -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_MEMORY is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_JTAG is not set
diff --git a/board/amlogic/defconfigs/c1_nq_p2_defconfig b/board/amlogic/defconfigs/c1_nq_p2_defconfig index 41315ae..106a8b9 100644 --- a/board/amlogic/defconfigs/c1_nq_p2_defconfig +++ b/board/amlogic/defconfigs/c1_nq_p2_defconfig
@@ -101,7 +101,7 @@ CONFIG_BOOTLOADER_CONTROL_BLOCK=y CONFIG_CMD_BOOTCTOL_AVB=y CONFIG_G_AB_SYSTEM=y -CONFIG_CMD_DDR_TEST=n +CONFIG_CMD_DDR_TEST=y CONFIG_LZ4=y CONFIG_CMD_NET=n CONFIG_CMD_BOOTD=n
diff --git a/board/amlogic/defconfigs/c1_pxp_defconfig b/board/amlogic/defconfigs/c1_pxp_defconfig index 82d6e43..0fe8369 100644 --- a/board/amlogic/defconfigs/c1_pxp_defconfig +++ b/board/amlogic/defconfigs/c1_pxp_defconfig
@@ -42,6 +42,7 @@ # CONFIG_REGMAP is not set CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_C1=y
diff --git a/board/amlogic/defconfigs/c2_2rs4_p1_defconfig b/board/amlogic/defconfigs/c2_2rs4_p1_defconfig new file mode 100644 index 0000000..0ae47f0 --- /dev/null +++ b/board/amlogic/defconfigs/c2_2rs4_p1_defconfig
@@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_2RS4_P1=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_2rs4_p1# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-2rs4" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=n +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=n +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set +CONFIG_LOGLEVEL=7
diff --git a/board/amlogic/defconfigs/c2_2rs4_p2_defconfig b/board/amlogic/defconfigs/c2_2rs4_p2_defconfig new file mode 100644 index 0000000..8d3b994 --- /dev/null +++ b/board/amlogic/defconfigs/c2_2rs4_p2_defconfig
@@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_2RS4_P2=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_2rs4_p2# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-2rs4" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=n +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=n +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set +CONFIG_LOGLEVEL=7
diff --git a/board/amlogic/defconfigs/c2_a049_p0_defconfig b/board/amlogic/defconfigs/c2_a049_p0_defconfig new file mode 100644 index 0000000..3144be6 --- /dev/null +++ b/board/amlogic/defconfigs/c2_a049_p0_defconfig
@@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_A049_P0=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_a049_p0# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-a049" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_ENABLE_CHARGER_DETECTION=y +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y
diff --git a/board/amlogic/defconfigs/c2_af400_defconfig b/board/amlogic/defconfigs/c2_af400_defconfig new file mode 100644 index 0000000..f9b7ed1 --- /dev/null +++ b/board/amlogic/defconfigs/c2_af400_defconfig
@@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_AF400=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_af400# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af400" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_MESON_NFC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SECURE_POWER_CONTROL=y
diff --git a/board/amlogic/defconfigs/c2_af401_defconfig b/board/amlogic/defconfigs/c2_af401_defconfig new file mode 100644 index 0000000..ade03fb --- /dev/null +++ b/board/amlogic/defconfigs/c2_af401_defconfig
@@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_AF401=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_af401# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af401" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_MESON_NFC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SECURE_POWER_CONTROL=y
diff --git a/board/amlogic/defconfigs/c2_af409_defconfig b/board/amlogic/defconfigs/c2_af409_defconfig new file mode 100644 index 0000000..ec28295 --- /dev/null +++ b/board/amlogic/defconfigs/c2_af409_defconfig
@@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_AF409=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_af409# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af409" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_MESON_NFC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_DM_ETH=y
diff --git a/board/amlogic/defconfigs/c2_af419_defconfig b/board/amlogic/defconfigs/c2_af419_defconfig new file mode 100644 index 0000000..e54ea70 --- /dev/null +++ b/board/amlogic/defconfigs/c2_af419_defconfig
@@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_AF419=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_af419# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af419" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_MESON_NFC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_DM_ETH=y
diff --git a/board/amlogic/defconfigs/c2_bla4_bx_defconfig b/board/amlogic/defconfigs/c2_bla4_bx_defconfig new file mode 100644 index 0000000..ec1246a --- /dev/null +++ b/board/amlogic/defconfigs/c2_bla4_bx_defconfig
@@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_BLA4_BX=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_bla4_bx# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bla4" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=n +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=n +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set +CONFIG_LOGLEVEL=7 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_SAVEENV=y +CONFIG_ENV_IS_IN_STORAGE=y
diff --git a/board/amlogic/defconfigs/c2_bla4_p0_defconfig b/board/amlogic/defconfigs/c2_bla4_p0_defconfig new file mode 100644 index 0000000..5027107 --- /dev/null +++ b/board/amlogic/defconfigs/c2_bla4_p0_defconfig
@@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_BLA4_P0=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_bla4_p0# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bla4" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=n +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=n +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set +CONFIG_LOGLEVEL=7
diff --git a/board/amlogic/defconfigs/c2_bla4_p1_defconfig b/board/amlogic/defconfigs/c2_bla4_p1_defconfig new file mode 100644 index 0000000..fcc5978 --- /dev/null +++ b/board/amlogic/defconfigs/c2_bla4_p1_defconfig
@@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_BLA4_P1=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_bla4_p1# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bla4" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=n +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=n +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set +CONFIG_LOGLEVEL=7 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_SAVEENV=y +CONFIG_ENV_IS_IN_STORAGE=y
diff --git a/board/amlogic/defconfigs/c2_bla4_p2_defconfig b/board/amlogic/defconfigs/c2_bla4_p2_defconfig new file mode 100644 index 0000000..925f294 --- /dev/null +++ b/board/amlogic/defconfigs/c2_bla4_p2_defconfig
@@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_BLA4_P2=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_bla4_p2# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bla4" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=n +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=n +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set +CONFIG_LOGLEVEL=7 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_SAVEENV=y +CONFIG_ENV_IS_IN_STORAGE=y
diff --git a/board/amlogic/defconfigs/c2_bsv3_p1_defconfig b/board/amlogic/defconfigs/c2_bsv3_p1_defconfig new file mode 100644 index 0000000..1c8ca17 --- /dev/null +++ b/board/amlogic/defconfigs/c2_bsv3_p1_defconfig
@@ -0,0 +1,112 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_BSV3_P1=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_bsv3_p1# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-bsv3" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=y +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set
diff --git a/board/amlogic/defconfigs/c2_pxp_defconfig b/board/amlogic/defconfigs/c2_pxp_defconfig new file mode 100644 index 0000000..9461d3e --- /dev/null +++ b/board/amlogic/defconfigs/c2_pxp_defconfig
@@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +CONFIG_PXP_EMULATOR=y +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_SKT=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_pxp# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-pxp" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_MESON_NFC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SECURE_POWER_CONTROL=y
diff --git a/board/amlogic/defconfigs/c2_spencer_bx_defconfig b/board/amlogic/defconfigs/c2_spencer_bx_defconfig new file mode 100644 index 0000000..9170b4e --- /dev/null +++ b/board/amlogic/defconfigs/c2_spencer_bx_defconfig
@@ -0,0 +1,111 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_SPENCER_BX=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_spencer_bx# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-spencer" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_ENABLE_CHARGER_DETECTION=y +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set
diff --git a/board/amlogic/defconfigs/c2_spencer_p1_defconfig b/board/amlogic/defconfigs/c2_spencer_p1_defconfig new file mode 100644 index 0000000..7a41ff1 --- /dev/null +++ b/board/amlogic/defconfigs/c2_spencer_p1_defconfig
@@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_SPENCER_P1=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_spencer_p1# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-spencer" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_LOGLEVEL=7 +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_ENABLE_CHARGER_DETECTION=y +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y
diff --git a/board/amlogic/defconfigs/c2_spencer_p2_defconfig b/board/amlogic/defconfigs/c2_spencer_p2_defconfig new file mode 100644 index 0000000..515095c --- /dev/null +++ b/board/amlogic/defconfigs/c2_spencer_p2_defconfig
@@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_SPENCER_P2=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_spencer_p2# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-spencer" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_LOGLEVEL=7 +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_ENABLE_CHARGER_DETECTION=y +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y
diff --git a/board/amlogic/defconfigs/c2_venus_bx_defconfig b/board/amlogic/defconfigs/c2_venus_bx_defconfig new file mode 100644 index 0000000..ee0898f --- /dev/null +++ b/board/amlogic/defconfigs/c2_venus_bx_defconfig
@@ -0,0 +1,112 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_VENUS_BX=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_venus_bx# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-venus" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=y +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set
diff --git a/board/amlogic/defconfigs/c2_venus_p1_defconfig b/board/amlogic/defconfigs/c2_venus_p1_defconfig new file mode 100644 index 0000000..544426a --- /dev/null +++ b/board/amlogic/defconfigs/c2_venus_p1_defconfig
@@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_VENUS_P1=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_venus_p1# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-venus" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_LOGLEVEL=7 +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=y +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=y
diff --git a/board/amlogic/defconfigs/c2_venus_p2_defconfig b/board/amlogic/defconfigs/c2_venus_p2_defconfig new file mode 100644 index 0000000..fea070c --- /dev/null +++ b/board/amlogic/defconfigs/c2_venus_p2_defconfig
@@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_VENUS_P2=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_venus_p2# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-venus" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_LOGLEVEL=7 +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=y +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=y
diff --git a/board/amlogic/defconfigs/c2_xua4_bx_defconfig b/board/amlogic/defconfigs/c2_xua4_bx_defconfig new file mode 100644 index 0000000..ce5385b --- /dev/null +++ b/board/amlogic/defconfigs/c2_xua4_bx_defconfig
@@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_XUA4_BX=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_xua4_bx# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-xua4" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=n +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=n +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set +CONFIG_LOGLEVEL=7 +CONFIG_ENABLE_CHARGER_DETECTION=y
diff --git a/board/amlogic/defconfigs/c2_xua4_p1_defconfig b/board/amlogic/defconfigs/c2_xua4_p1_defconfig new file mode 100644 index 0000000..a1931a4 --- /dev/null +++ b/board/amlogic/defconfigs/c2_xua4_p1_defconfig
@@ -0,0 +1,114 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_C2=y +# CONFIG_PXP_EMULATOR is not set +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_NEED_BL32=y +CONFIG_C2_XUA4_P1=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="c2_xua4_p1# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_RSVMEM=y +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c325x-xua4" +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_C2=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_C2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_AML_MTDPART=y +CONFIG_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_C2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPIFCV2=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_AML_GPT=y +CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y +CONFIG_IMG_SECURE_CHECK_SZ=66060288 +CONFIG_CMD_FACTORY_BOOT=y +CONFIG_CMD_REBOOT=y +CONFIG_AML_RPMB_DISABLE=y +CONFIG_CMD_BOOTCTOL_AVB=y +CONFIG_G_AB_SYSTEM=y +CONFIG_LZ4=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_GET_CHIPTYPE=y +CONFIG_I2C_REGULATOR=n +CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y +CONFIG_SCHUMACHER_SSR=n +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_MEMORY is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_JTAG is not set +CONFIG_LOGLEVEL=7 +CONFIG_ENABLE_CHARGER_DETECTION=y
diff --git a/board/amlogic/defconfigs/g12a_u200_v1_defconfig b/board/amlogic/defconfigs/g12a_u200_v1_defconfig index cd50bce..a9f6496 100644 --- a/board/amlogic/defconfigs/g12a_u200_v1_defconfig +++ b/board/amlogic/defconfigs/g12a_u200_v1_defconfig
@@ -23,6 +23,7 @@ # CONFIG_CMD_IMI is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_SF=y @@ -43,6 +44,7 @@ CONFIG_ENV_IS_IN_STORAGE=y CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_G12=y @@ -55,7 +57,6 @@ CONFIG_NAND=y #CONFIG_SPI_NAND=y CONFIG_DM_SPI_FLASH=y -CONFIG_MTD_UBI=y CONFIG_PHY=y CONFIG_AML_USB3_PHY=y CONFIG_AML_USB2_PHY=y @@ -95,7 +96,6 @@ CONFIG_AML_VPP=y CONFIG_AML_VPU=y CONFIG_AML_CVBS=y -CONFIG_AML_HDMITX=y CONFIG_AML_LCD=y CONFIG_AML_LCD_TV=y CONFIG_AML_LCD_TABLET=y
diff --git a/board/amlogic/defconfigs/g12b_w400_v1_defconfig b/board/amlogic/defconfigs/g12b_w400_v1_defconfig index 3b77e26..98dde20 100644 --- a/board/amlogic/defconfigs/g12b_w400_v1_defconfig +++ b/board/amlogic/defconfigs/g12b_w400_v1_defconfig
@@ -23,6 +23,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y @@ -42,6 +43,7 @@ CONFIG_ENV_IS_IN_STORAGE=y CONFIG_ADC=y CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y CONFIG_CLK=y CONFIG_CLK_MESON=y CONFIG_CLK_MESON_G12=y @@ -55,7 +57,6 @@ CONFIG_MMC_MESON_GX=y CONFIG_NAND=y CONFIG_DM_SPI_FLASH=y -CONFIG_MTD_UBI=y CONFIG_PHY=y CONFIG_AML_USB3_PHY=y CONFIG_AML_USB2_PHY=y @@ -95,7 +96,6 @@ CONFIG_AML_VPP=y CONFIG_AML_VPU=y CONFIG_AML_CVBS=y -CONFIG_AML_HDMITX=y CONFIG_AML_LCD=y CONFIG_AML_LCD_TV=y CONFIG_AML_LCD_TABLET=y
diff --git a/board/amlogic/defconfigs/sc2_ah212_ddr3_defconfig b/board/amlogic/defconfigs/sc2_ah212_ddr3_defconfig new file mode 100644 index 0000000..09499d5 --- /dev/null +++ b/board/amlogic/defconfigs/sc2_ah212_ddr3_defconfig
@@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_SC2=y +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_DDRFW_TYPE="ddr3" +CONFIG_BL30_SELECT="sc2_ah212" +CONFIG_SC2_AH212_DDR3=y +CONFIG_DEBUG_UART_BASE=0xfe07a000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="sc2_ah212_ddr3# " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_BOOTCTOL_AVB=y +# CONFIG_CMD_RSVMEM is not set +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah212-ddr3" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON_G12A=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_SC2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_AML_MTDPART=y +CONFIG_PHYLIB=y +CONFIG_PHY_AMLOGIC=y +CONFIG_DM_ETH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_SC2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_AML_VOUT=y +CONFIG_AML_OSD=y +CONFIG_AML_CANVAS=y +CONFIG_AML_DOLBY=y +CONFIG_AML_VPP=y +CONFIG_AML_VPU=y +CONFIG_AML_CVBS=y +CONFIG_AML_HDMITX=y +CONFIG_AML_HDMITX20=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_FAT_WRITE=y +CONFIG_AML_FACTORY_PROVISION=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah212_defconfig b/board/amlogic/defconfigs/sc2_ah212_defconfig new file mode 100644 index 0000000..7df5ee7 --- /dev/null +++ b/board/amlogic/defconfigs/sc2_ah212_defconfig
@@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_SC2=y +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_DDRFW_TYPE="ddr4" +CONFIG_BL30_SELECT="sc2_ah212" +CONFIG_SC2_AH212=y +CONFIG_DEBUG_UART_BASE=0xfe07a000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="sc2_ah212# " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_BOOTCTOL_AVB=y +# CONFIG_CMD_RSVMEM is not set +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah212" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON_G12A=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_SC2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_AML_MTDPART=y +CONFIG_PHYLIB=y +CONFIG_PHY_AMLOGIC=y +CONFIG_DM_ETH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_SC2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_AML_VOUT=y +CONFIG_AML_OSD=y +CONFIG_AML_CANVAS=y +CONFIG_AML_DOLBY=y +CONFIG_AML_VPP=y +CONFIG_AML_VPU=y +CONFIG_AML_CVBS=y +CONFIG_AML_HDMITX=y +CONFIG_AML_HDMITX20=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_FAT_WRITE=y +CONFIG_AML_FACTORY_PROVISION=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TEE=y +CONFIG_OPTEE=y
diff --git a/board/amlogic/defconfigs/sc2_ah212_lpddr3_defconfig b/board/amlogic/defconfigs/sc2_ah212_lpddr3_defconfig new file mode 100644 index 0000000..4dc8192 --- /dev/null +++ b/board/amlogic/defconfigs/sc2_ah212_lpddr3_defconfig
@@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_SC2=y +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_DDRFW_TYPE="lpddr3" +CONFIG_BL30_SELECT="sc2_ah212" +CONFIG_SC2_AH212_LPDDR3=y +CONFIG_DEBUG_UART_BASE=0xfe07a000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="sc2_ah212_lpddr3# " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_BOOTCTOL_AVB=y +# CONFIG_CMD_RSVMEM is not set +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah212-ddr3" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON_G12A=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_SC2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_AML_MTDPART=y +CONFIG_PHYLIB=y +CONFIG_PHY_AMLOGIC=y +CONFIG_DM_ETH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_SC2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_AML_VOUT=y +CONFIG_AML_OSD=y +CONFIG_AML_CANVAS=y +CONFIG_AML_DOLBY=y +CONFIG_AML_VPP=y +CONFIG_AML_VPU=y +CONFIG_AML_CVBS=y +CONFIG_AML_HDMITX=y +CONFIG_AML_HDMITX20=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_FAT_WRITE=y +CONFIG_AML_FACTORY_PROVISION=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah212_lpddr4_defconfig b/board/amlogic/defconfigs/sc2_ah212_lpddr4_defconfig new file mode 100644 index 0000000..ad6254c --- /dev/null +++ b/board/amlogic/defconfigs/sc2_ah212_lpddr4_defconfig
@@ -0,0 +1,110 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_SC2=y +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_DDRFW_TYPE="lpddr4" +CONFIG_BL30_SELECT="sc2_ah212" +CONFIG_SC2_AH212_LPDDR4=y +CONFIG_DEBUG_UART_BASE=0xfe07a000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="sc2_ah212_lpddr4# " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_BOOTCTOL_AVB=y +# CONFIG_CMD_RSVMEM is not set +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah212-ddr3" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON_G12A=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_SC2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_AML_MTDPART=y +CONFIG_PHYLIB=y +CONFIG_PHY_AMLOGIC=y +CONFIG_DM_ETH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_SC2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_AML_VOUT=y +CONFIG_AML_OSD=y +CONFIG_AML_CANVAS=y +CONFIG_AML_DOLBY=y +CONFIG_AML_VPP=y +CONFIG_AML_VPU=y +CONFIG_AML_CVBS=y +CONFIG_AML_HDMITX=y +CONFIG_AML_HDMITX20=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_FAT_WRITE=y +CONFIG_AML_FACTORY_PROVISION=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah219_defconfig b/board/amlogic/defconfigs/sc2_ah219_defconfig new file mode 100644 index 0000000..9427acb --- /dev/null +++ b/board/amlogic/defconfigs/sc2_ah219_defconfig
@@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_SC2=y +CONFIG_AML_TSENSOR=y +CONFIG_AML_TSENSOR_COOL=y +CONFIG_DDRFW_TYPE="ddr4" +CONFIG_BL30_SELECT="sc2_ah219" +CONFIG_SC2_AH219=y +CONFIG_DEBUG_UART_BASE=0xfe07a000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="sc2_ah219# " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_AML_STORAGE=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_SARADC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_BOOTCTOL_AVB=y +# CONFIG_CMD_RSVMEM is not set +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=y +CONFIG_AML_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah219" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON_G12A=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_SC2=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MESON_GX=y +CONFIG_AML_MTDPART=y +CONFIG_PHYLIB=y +CONFIG_PHY_AMLOGIC=y +CONFIG_DM_ETH=y +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=y +CONFIG_AML_USB2_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_SC2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_AML_SPICC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_AML_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y +CONFIG_AML_V3_FACTORY_BURN=y +CONFIG_AML_V3_USB_TOOl=y +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_AML_VOUT=y +CONFIG_AML_OSD=y +CONFIG_AML_CANVAS=y +CONFIG_AML_DOLBY=y +CONFIG_AML_VPP=y +CONFIG_AML_VPU=y +CONFIG_AML_CVBS=y +CONFIG_AML_HDMITX=y +CONFIG_AML_HDMITX20=y +CONFIG_UNIFY_KEY_MANAGE=y +CONFIG_SECURE_STORAGE=y +CONFIG_SECURE_POWER_CONTROL=y +CONFIG_FAT_WRITE=y +CONFIG_AML_FACTORY_PROVISION=y +CONFIG_EFUSE=y +CONFIG_SHA1=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TEE=y +CONFIG_OPTEE=y
diff --git a/board/amlogic/defconfigs/sc2_pxp_defconfig b/board/amlogic/defconfigs/sc2_pxp_defconfig new file mode 100644 index 0000000..b36f989 --- /dev/null +++ b/board/amlogic/defconfigs/sc2_pxp_defconfig
@@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x00000000 +CONFIG_MESON_SC2=y +CONFIG_PXP_EMULATOR=y +CONFIG_AML_TSENSOR=n +CONFIG_AML_TSENSOR_COOL=n +CONFIG_NEED_BL32=n +CONFIG_SC2_SKT=y +CONFIG_DEBUG_UART_BASE=0xfe07a000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="echo bootcmd" +CONFIG_BOARD_LATE_INIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="sc2_pxp# " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_CLKMSR=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_DSPSET=n +CONFIG_CMD_EFUSE=n +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MTD=y +CONFIG_CMD_SF=n +CONFIG_CMD_USB=n +CONFIG_CMD_SARADC=n +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTDPARTS=n +CONFIG_AML_STORAGE=y +# CONFIG_CMD_RSVMEM is not set +CONFIG_CMD_WATCHDOG=y +CONFIG_CMD_JTAG=n +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-pxp" +CONFIG_ENV_IS_IN_STORAGE=y +# CONFIG_REGMAP is not set +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_SARADC_MESON_G12A=y +CONFIG_CLK=y +CONFIG_CLK_MESON=y +CONFIG_CLK_MESON_SC2=y +CONFIG_USB_FUNCTION_FASTBOOT=n +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_MISC=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=n +CONFIG_AML_MTDPART=y +CONFIG_NAND=n +CONFIG_DM_SPI_FLASH=n +CONFIG_PHY=y +CONFIG_AML_USB3_PHY=n +CONFIG_AML_USB2_PHY=n +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MESON_SC2=y +CONFIG_DM_REGULATOR=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=n +CONFIG_DM_SPI=n +CONFIG_AML_SPIFCV2=n +CONFIG_USB=n +CONFIG_DM_USB=n +CONFIG_AML_USB=n +CONFIG_USB_XHCI_HCD=n +CONFIG_USB_XHCI_DWC3=n +CONFIG_USB_GADGET=n +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_AML_V3_FACTORY_BURN=n +CONFIG_AML_V3_USB_TOOl=n +CONFIG_WDT=y +CONFIG_WDT_MESON=y +CONFIG_AML_DRIVER=y +CONFIG_AML_MEDIA=y +CONFIG_AML_VOUT=y +CONFIG_AML_OSD=y +CONFIG_AML_CANVAS=y +CONFIG_AML_VPP=y +CONFIG_AML_VPU=y +CONFIG_AML_HDMITX20=y +CONFIG_EFUSE=n +CONFIG_SHA1=y +CONFIG_SHA256=y +CONFIG_OF_LIBFDT_OVERLAY=n +CONFIG_SECURE_POWER_CONTROL=y
diff --git a/board/amlogic/g12a_u200_v1/firmware/timing.c b/board/amlogic/g12a_u200_v1/firmware/timing.c index fa059e2..6fba580 100644 --- a/board/amlogic/g12a_u200_v1/firmware/timing.c +++ b/board/amlogic/g12a_u200_v1/firmware/timing.c
@@ -8,8 +8,7 @@ #include <asm/arch/ddr_define.h> /* board clk defines */ -#define DDR_SIZE 0 -#define CPU_CLK 1200 +#define CPU_CLK 1200 /* ddr config support multiple configs for boards which use same bootloader: * config steps: @@ -44,19 +43,92 @@ * */ -ddr_set_t __ddr_setting[] = { +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { { - /* g12a skt (u209) ddr4 */ + // g12a 4layer 4pcs ddr4 rank01 (1320)(T204) + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1320, 0, 0, 0}, + .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0xffff, + .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 80, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 80, //60, + .dram_ac_odt_ohm = 0, + .dram_data_wr_odt_ohm = 120, + .soc_clk_slew_rate = 0x3ff, + .soc_cs_slew_rate = 0x3ff, + .soc_ac_slew_rate = 0x3ff, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 500, + .vref_receiver_permil = 8200/12,//700, + .vref_dram_permil = 9200/12,//700, + //.vref_reverse = 0, + //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, + .ac_trace_delay = {32+10,32,32+10,32+10,32,32,32+10,32+10,32+10,32+8}, + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, + .training_offset = (1<<3) | (4<<0),//read dqs offset after training,bit3=0 right move,bit3=1 left move,bit[2:0] offset step +}, +{ + // g12a 4layer 2pcs ddr4 rank0 (1320)(U200) .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, .DramType = CONFIG_DDR_TYPE_DDR4, - .DRAMFreq = {1200, 0, 0, 0}, + .DRAMFreq = {1320, 0, 0, 0}, .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -64,8 +136,8 @@ .dram_cs0_size_MB = 0xffff, .dram_cs1_size_MB = 0, .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0808, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -87,7 +159,7 @@ .vref_dram_permil = 0,//700, //.vref_reverse = 0, //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, - .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32}, .ddr_dmc_remap = { [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), @@ -114,10 +186,10 @@ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, - .bitTimeControl_2d = 1, + .fast_boot[0] = 1, }, { - /* g12a skt (u209) ddr3 */ + // g12a 4layer 4pcs ddr3 rank01 (912)(U212) .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, @@ -125,8 +197,8 @@ .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -134,8 +206,8 @@ .dram_cs0_size_MB = 0xffff, .dram_cs1_size_MB = 0xffff, .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0c0c, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -172,7 +244,7 @@ .ddr_dmc_remap = { [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), - [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), }, @@ -196,7 +268,89 @@ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, - .bitTimeControl_2d = 1, + .fast_boot[0] = 1, +}, +{ + // g12a 4layer 2pcs ddr3 rank0 (912) + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, }, { /* g12a skt (u209) lpddr4 */ @@ -209,8 +363,8 @@ .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -218,8 +372,8 @@ .dram_cs0_size_MB = 0xffff,//1024, .dram_cs1_size_MB = 0xffff,//1024, .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0808, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -271,7 +425,8 @@ .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, .diagnose = CONFIG_DIAGNOSE_DISABLE, - .bitTimeControl_2d = 1, + .bitTimeControl_2d = 1, + .fast_boot[0] = 1, }, { /* g12a Y2 dongle */ @@ -284,8 +439,8 @@ .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -293,8 +448,8 @@ .dram_cs0_size_MB = 0xffff,//1024, .dram_cs1_size_MB = 0,//1024, .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0808, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -344,6 +499,7 @@ .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, .bitTimeControl_2d = 1, + .fast_boot[0] = 1, }, #if 0 { @@ -357,8 +513,8 @@ .DRAMFreq = {600, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -366,8 +522,8 @@ .dram_cs0_size_MB = 0xffff,//1024, .dram_cs1_size_MB = 0xffff,//1024, .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x00c, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm @@ -405,6 +561,8 @@ .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, .diagnose = CONFIG_DIAGNOSE_DISABLE, + .bitTimeControl_2d = 1, + .fast_boot[0] = 1, }, #endif };
diff --git a/board/amlogic/g12b_w400_v1/firmware/timing.c b/board/amlogic/g12b_w400_v1/firmware/timing.c index a60b33c..3978115 100644 --- a/board/amlogic/g12b_w400_v1/firmware/timing.c +++ b/board/amlogic/g12b_w400_v1/firmware/timing.c
@@ -8,8 +8,7 @@ #include <asm/arch/ddr_define.h> /* board clk defines */ -#define DDR_SIZE 0 -#define CPU_CLK 1200 +#define CPU_CLK 1200 /* ddr config support multiple configs for boards which use same bootloader: * config steps: @@ -44,19 +43,93 @@ * */ -ddr_set_t __ddr_setting[] = { +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = { { - /* ddr4 */ + // g12a 4layer 4pcs ddr4 rank01 (1320)(T204) + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1320, 0, 0, 0}, + .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0xffff, + .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 80, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 80, //60, + .dram_ac_odt_ohm = 0, + .dram_data_wr_odt_ohm = 120, + .soc_clk_slew_rate = 0x3ff, + .soc_cs_slew_rate = 0x3ff, + .soc_ac_slew_rate = 0x3ff, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 500, + .vref_receiver_permil = 8200/12,//700, + .vref_dram_permil = 9200/12,//700, + //.vref_reverse = 0, + //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, + .ac_trace_delay = {32+10,32,32+10,32+10,32,32,32+10,32+10,32+10,32+8}, + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, + .magic = DRAM_CFG_MAGIC, + .bitTimeControl_2d = 1, //training time setting,=1,200ms;=7,2s; + .fast_boot[0] = 1, + .training_offset = (1<<3) | (4<<0),//read dqs offset after training,bit3=0 right move,bit3=1 left move,bit[2:0] offset step +}, +{ + // g12a 4layer 2pcs ddr4 rank0 (1320)(U200) .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, .DramType = CONFIG_DDR_TYPE_DDR4, - .DRAMFreq = {1200, 0, 0, 0}, + .DRAMFreq = {1320, 0, 0, 0}, .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -64,8 +137,8 @@ .dram_cs0_size_MB = 0xffff, .dram_cs1_size_MB = 0, .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0808, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -87,7 +160,7 @@ .vref_dram_permil = 0,//700, //.vref_reverse = 0, //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, - .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32}, .ddr_dmc_remap = { [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), @@ -114,9 +187,11 @@ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, + .bitTimeControl_2d = 1, //training time setting,=1,200ms;=7,2s; + .fast_boot[0] = 1, }, { - /* ddr3 */ + // g12a 4layer 4pcs ddr3 rank01 (912)(U212) .board_id = CONFIG_BOARD_ID_MASK, .version = 1, .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, @@ -124,8 +199,8 @@ .DRAMFreq = {912, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 1, @@ -133,8 +208,8 @@ .dram_cs0_size_MB = 0xffff, .dram_cs1_size_MB = 0xffff, .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0c0c, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -171,7 +246,7 @@ .ddr_dmc_remap = { [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), - [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), }, @@ -195,6 +270,91 @@ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, + .bitTimeControl_2d = 1, //training time setting,=1,200ms;=7,2s; + .fast_boot[0] = 1, +}, +{ + // g12a 4layer 2pcs ddr3 rank0 (912) + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .bitTimeControl_2d = 1, //training time setting,=1,200ms;=7,2s; + .fast_boot[0] = 1, }, { /* lpddr4 */ @@ -207,8 +367,8 @@ .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -216,8 +376,8 @@ .dram_cs0_size_MB = 0xffff,//1024, .dram_cs1_size_MB = 0xffff,//1024, .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0808, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -269,6 +429,8 @@ .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, .diagnose = CONFIG_DIAGNOSE_DISABLE, + .bitTimeControl_2d = 1, + .fast_boot[0] = 1, }, { /* Y2 dongle */ @@ -281,8 +443,8 @@ .DRAMFreq = {1392, 0, 0, 0}, .ddr_base_addr = CFG_DDR_BASE_ADDR, .ddr_start_offset = CFG_DDR_START_OFFSET, - .imem_load_addr = 0xFFFC0000, //sram - .dmem_load_size = 0x1000, //4K + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K .DisabledDbyte = 0xf0, .Is2Ttiming = 0, @@ -290,8 +452,8 @@ .dram_cs0_size_MB = 0xffff,//1024, .dram_cs1_size_MB = 0,//1024, .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f - .phy_odt_config_rank = {0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT - .dfi_odt_config = 0x0808, + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 .PllBypassEn = 0, //bit0-ps0,bit1-ps1 .ddr_rdbi_wr_enable = 0, .clk_drv_ohm = 40, @@ -340,6 +502,8 @@ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm .ddr_func = DDR_FUNC, .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, + .bitTimeControl_2d = 1, }, };
diff --git a/board/amlogic/sc2_ah212/Kconfig b/board/amlogic/sc2_ah212/Kconfig new file mode 100644 index 0000000..ec3b787 --- /dev/null +++ b/board/amlogic/sc2_ah212/Kconfig
@@ -0,0 +1,30 @@ +if TARGET_SC2_AH212 + +config SYS_SOC + default "sc2" + +config SYS_BOARD + default "sc2_ah212" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "sc2_ah212" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default n + help + support plltest command + +config AML_REBOOT + bool "reboot cmd" + default y + help + support uboot reboot cmd +endif
diff --git a/board/amlogic/sc2_ah212/Makefile b/board/amlogic/sc2_ah212/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/sc2_ah212/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah212/aml-key/bl2aesiv b/board/amlogic/sc2_ah212/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/bl2aeskey b/board/amlogic/sc2_ah212/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/bl3xaesiv b/board/amlogic/sc2_ah212/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/bl3xaeskey b/board/amlogic/sc2_ah212/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/kernelaesiv b/board/amlogic/sc2_ah212/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/kernelaeskey b/board/amlogic/sc2_ah212/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-user-key.sig b/board/amlogic/sc2_ah212/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/sc2_ah212/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/sc2_ah212/firmware/timing.c b/board/amlogic/sc2_ah212/firmware/timing.c new file mode 100644 index 0000000..d4cb45c --- /dev/null +++ b/board/amlogic/sc2_ah212/firmware/timing.c
@@ -0,0 +1,385 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define DSU_CLK 1200 + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = { +{ + // g12a 4layer 2pcs ddr3 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +{ + // g12a 4layer 2pcs ddr4 rank0 (1320)(U200) + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1320, 0, 0, 0}, + .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, //60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff, + .soc_cs_slew_rate = 0x3ff, + .soc_ac_slew_rate = 0x3ff, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 500, + .vref_receiver_permil = 0,//700, + .vref_dram_permil = 0,//700, + //.vref_reverse = 0, + //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, + .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32}, + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +}; + +board_clk_set_t __board_clk_setting +__attribute__ ((section(".clk_param"))) = { + /* clock settings for bl2 */ + .cpu_clk = CPU_CLK / 24 * 24, + .dsu_clk = DSU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif +}; + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG */ +#if (VDDEE_VAL == 700) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 710) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 720) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 730) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 740) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 750) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 760) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 770) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 780) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 790) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 800) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 810) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 820) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 830) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 840) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 850) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 860) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 870) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 880) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = { + //hxbao, need fine tune + {0, 0, 0xffffffff, 0, 0, 0}, +}; + +/* gpio/pinmux/pwm init */ +register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES] +__attribute__ ((section(".misc_param"))) = { + /* demo, user defined override register */ + {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + /* enable vddcpu dc-dc, set TEST_N to high */ + {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0}, + {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0}, + /* set pwm h and pwm j clock rate to 24M, enable them */ + {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3 */ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */ + {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0}, + {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0}, +}; + +/* for all the storage parameter */ +storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = { + .common = { + .version = 0x01, + .device_fip_container_size = 0x280000, + .device_fip_container_copies = 4, + }, + .nand = { + .version = 0x01, + .bbt_pages = 0x01, + .bbt_start_block = 20, + .discrete_mode = 1, + .setup_data.nand_setup_data = (2 << 20) | \ + (0 << 19) | \ + (1 << 17) | \ + (4 << 14) | \ + (0 << 13) | \ + (64 << 6) | \ + (4 << 0), + .reserved_area_blk_cnt = 48, + .page_per_block = 128, + .use_param_page_list = 0, + }, +};
diff --git a/board/amlogic/sc2_ah212/fw_arb.cfg b/board/amlogic/sc2_ah212/fw_arb.cfg new file mode 100644 index 0000000..5237e72 --- /dev/null +++ b/board/amlogic/sc2_ah212/fw_arb.cfg
@@ -0,0 +1,16 @@ +# Configure Firmware Anti-rollback Versions +device_scs_vers=0x0 +device_tee_vers=0x0 +device_ree_vers=0x0 + +# Configure Segmentation ID +DEVICE_SCS_SEGID=0x0 +DEVICE_VENDOR_SEGID=0x0 + +############################################################### +DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1))) +DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1))) +DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1))) +echo $DEVICE_SCS_VERS +echo $DEVICE_TEE_VERS +echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah212/sc2_ah212.c b/board/amlogic/sc2_ah212/sc2_ah212.c new file mode 100644 index 0000000..540a410 --- /dev/null +++ b/board/amlogic/sc2_ah212/sc2_ah212.c
@@ -0,0 +1,405 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> +#include <asm/arch/bl31_apis.h> +#ifdef CONFIG_AML_VPU +#include <amlogic/media/vpu/vpu.h> +#endif +#ifdef CONFIG_AML_VPP +#include <amlogic/media/vpp/vpp.h> +#endif +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/media/vout/hdmitx/hdmitx_ext.h> +#endif +#ifdef CONFIG_AML_CVBS +#include <amlogic/media/vout/aml_cvbs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +#ifdef CONFIG_AML_HDMITX20 +static void hdmitx_set_hdmi_5v(void) +{ + /*Power on VCC_5V for HDMI_5V*/ +} +#endif + +void board_init_mem(void) { + #if 1 + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } + #endif +} + +int board_init(void) +{ + printf("board init\n"); + + /* The non-secure watchdog is enabled in BL2 TEE, disable it */ + run_command("watchdog off", 0); + printf("watchdog disable\n"); + + aml_set_bootsequence(0); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + #if 0 + active_clk(); + #endif + pinctrl_devices_active(PIN_CONTROLLER_NUM); + run_command("gpio clr GPIOH_8", 0); +#ifdef CONFIG_AML_HDMITX20 + hdmitx_set_hdmi_5v(); + hdmitx_init(); +#endif + return 0; +} + +int board_late_init(void) +{ + printf("board late init\n"); + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + run_command("run bcb_cmd", 0); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + /* reset vout init state */ + run_command("setenv vout_init disable", 0); +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif +#ifdef CONFIG_AML_VPP + vpp_init(); +#endif + +#ifdef CONFIG_AML_CVBS + cvbs_init(); +#endif + run_command("amlsecurecheck", 0); + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ + +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf1000000UL, + .phys = 0xf1000000UL, + .size = 0x0f000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + /* update mmu table from bl2 ddr auto detect size */ +#ifdef CONFIG_UPDATE_MMU_TABLE + unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4; + switch (nddrSize) + { + case (CONFIG_1G_SIZE): + case (CONFIG_2G_SIZE): + case (CONFIG_3G_SIZE): + case (CONFIG_DDR_MAX_SIZE): + bd_mem_map[0].size = nddrSize; + break; + default : + printf("aml log : ERROR DDR detect size not match MMU !"); + break; + } +#endif + + //printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 1 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} + +uint64_t spiflash_bootloader_size(void) +{ + return 3 * SZ_1M; +} +#endif /* CONFIG_SPI_FLASH */ + +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +#ifdef CONFIG_DISCRETE_BOOTLOADER +{ + .name = BOOT_BL2E, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_BL2X, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DDRFIP, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DEVFIP, + .offset = 0, + .size = 0, +}, +#endif +{ + .name = "logo", + .offset = 0, + .size = 2*SZ_1M, +}, +{ + .name = "recovery", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 64*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} + +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +#ifdef CONFIG_MULTI_DTB +int checkhw(char * name) +{ + strcpy(name, "sc2_s905x4_ah212\0"); + setenv("aml_dt", "sc2_s905x4_ah212\0"); + return 0; +} +#endif + +const char * const _env_args_reserve_[] = +{ + "lock", + "upgrade_step", + "bootloader_version", + + NULL//Keep NULL be last to tell END +}; + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah212_ddr3/Kconfig b/board/amlogic/sc2_ah212_ddr3/Kconfig new file mode 100644 index 0000000..7d4efc9 --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/Kconfig
@@ -0,0 +1,30 @@ +if TARGET_SC2_AH212_DDR3 + +config SYS_SOC + default "sc2" + +config SYS_BOARD + default "sc2_ah212_ddr3" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "sc2_ah212_ddr3" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default n + help + support plltest command + +config AML_REBOOT + bool "reboot cmd" + default y + help + support uboot reboot cmd +endif
diff --git a/board/amlogic/sc2_ah212_ddr3/Makefile b/board/amlogic/sc2_ah212_ddr3/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aesiv b/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aeskey b/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaesiv b/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaeskey b/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaesiv b/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaeskey b/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-user-key.sig b/board/amlogic/sc2_ah212_ddr3/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/firmware/timing.c b/board/amlogic/sc2_ah212_ddr3/firmware/timing.c new file mode 100644 index 0000000..2ddecf2 --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/firmware/timing.c
@@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define DSU_CLK 1200 + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = { +{ + // U212 4layer 4pcs ddr3 rank01 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0xffff, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +{ + // 4layer 2pcs ddr3 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +}; + +board_clk_set_t __board_clk_setting +__attribute__ ((section(".clk_param"))) = { + /* clock settings for bl2 */ + .cpu_clk = CPU_CLK / 24 * 24, + .dsu_clk = DSU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif +}; + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG */ +#if (VDDEE_VAL == 700) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 710) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 720) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 730) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 740) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 750) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 760) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 770) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 780) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 790) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 800) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 810) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 820) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 830) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 840) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 850) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 860) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 870) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 880) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = { + //hxbao, need fine tune + {0, 0, 0xffffffff, 0, 0, 0}, +}; + +/* gpio/pinmux/pwm init */ +register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES] +__attribute__ ((section(".misc_param"))) = { + /* demo, user defined override register */ + {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + /* enable vddcpu dc-dc, set TEST_N to high */ + {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0}, + {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0}, + /* set pwm h and pwm j clock rate to 24M, enable them */ + {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3 */ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */ + {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0}, + {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0}, +}; + +/* for all the storage parameter */ +storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = { + .common = { + .version = 0x01, + .device_fip_container_size = 0x280000, + .device_fip_container_copies = 4, + }, + .nand = { + .version = 0x01, + .bbt_pages = 0x01, + .bbt_start_block = 20, + .discrete_mode = 1, + .setup_data.nand_setup_data = (2 << 20) | \ + (0 << 19) | \ + (1 << 17) | \ + (4 << 14) | \ + (0 << 13) | \ + (64 << 6) | \ + (4 << 0), + .reserved_area_blk_cnt = 48, + .page_per_block = 128, + .use_param_page_list = 0, + }, +};
diff --git a/board/amlogic/sc2_ah212_ddr3/fw_arb.cfg b/board/amlogic/sc2_ah212_ddr3/fw_arb.cfg new file mode 100644 index 0000000..5237e72 --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/fw_arb.cfg
@@ -0,0 +1,16 @@ +# Configure Firmware Anti-rollback Versions +device_scs_vers=0x0 +device_tee_vers=0x0 +device_ree_vers=0x0 + +# Configure Segmentation ID +DEVICE_SCS_SEGID=0x0 +DEVICE_VENDOR_SEGID=0x0 + +############################################################### +DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1))) +DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1))) +DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1))) +echo $DEVICE_SCS_VERS +echo $DEVICE_TEE_VERS +echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah212_ddr3/sc2_ah212_ddr3.c b/board/amlogic/sc2_ah212_ddr3/sc2_ah212_ddr3.c new file mode 100644 index 0000000..0d297f0 --- /dev/null +++ b/board/amlogic/sc2_ah212_ddr3/sc2_ah212_ddr3.c
@@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> +#include <asm/arch/bl31_apis.h> +#ifdef CONFIG_AML_VPU +#include <amlogic/media/vpu/vpu.h> +#endif +#ifdef CONFIG_AML_VPP +#include <amlogic/media/vpp/vpp.h> +#endif +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/media/vout/hdmitx/hdmitx_ext.h> +#endif +#ifdef CONFIG_AML_CVBS +#include <amlogic/media/vout/aml_cvbs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +#ifdef CONFIG_AML_HDMITX20 +static void hdmitx_set_hdmi_5v(void) +{ + /*Power on VCC_5V for HDMI_5V*/ +} +#endif + +void board_init_mem(void) { + #if 1 + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } + #endif +} + +int board_init(void) +{ + printf("board init\n"); + + /* The non-secure watchdog is enabled in BL2 TEE, disable it */ + run_command("watchdog off", 0); + printf("watchdog disable\n"); + + aml_set_bootsequence(0); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + #if 0 + active_clk(); + #endif + pinctrl_devices_active(PIN_CONTROLLER_NUM); + run_command("gpio clr GPIOH_8", 0); +#ifdef CONFIG_AML_HDMITX20 + hdmitx_set_hdmi_5v(); + hdmitx_init(); +#endif + return 0; +} + +int board_late_init(void) +{ + printf("board late init\n"); + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + run_command("run bcb_cmd", 0); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + /* reset vout init state */ + run_command("setenv vout_init disable", 0); +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif +#ifdef CONFIG_AML_VPP + vpp_init(); +#endif + +#ifdef CONFIG_AML_CVBS + cvbs_init(); +#endif + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ + +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf1000000UL, + .phys = 0xf1000000UL, + .size = 0x0f000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + /* update mmu table from bl2 ddr auto detect size */ +#ifdef CONFIG_UPDATE_MMU_TABLE + unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4; + switch (nddrSize) + { + case (CONFIG_1G_SIZE): + case (CONFIG_2G_SIZE): + case (CONFIG_3G_SIZE): + case (CONFIG_DDR_MAX_SIZE): + bd_mem_map[0].size = nddrSize; + break; + default : + printf("aml log : ERROR DDR detect size not match MMU !"); + break; + } +#endif + + //printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 1 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} + +uint64_t spiflash_bootloader_size(void) +{ + return 3 * SZ_1M; +} +#endif /* CONFIG_SPI_FLASH */ + +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +#ifdef CONFIG_DISCRETE_BOOTLOADER +{ + .name = BOOT_BL2E, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_BL2X, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DDRFIP, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DEVFIP, + .offset = 0, + .size = 0, +}, +#endif +{ + .name = "logo", + .offset = 0, + .size = 2*SZ_1M, +}, +{ + .name = "recovery", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 64*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} + +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +#ifdef CONFIG_MULTI_DTB +int checkhw(char * name) +{ + strcpy(name, "sc2_s905x4_ah212\0"); + setenv("aml_dt", "sc2_s905x4_ah212\0"); + return 0; +} +#endif + +const char * const _env_args_reserve_[] = +{ + "lock", + "upgrade_step", + "bootloader_version", + + NULL//Keep NULL be last to tell END +}; + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah212_lpddr3/Kconfig b/board/amlogic/sc2_ah212_lpddr3/Kconfig new file mode 100644 index 0000000..cf65ade --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/Kconfig
@@ -0,0 +1,30 @@ +if TARGET_SC2_AH212_LPDDR3 + +config SYS_SOC + default "sc2" + +config SYS_BOARD + default "sc2_ah212_lpddr3" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "sc2_ah212_lpddr3" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default n + help + support plltest command + +config AML_REBOOT + bool "reboot cmd" + default y + help + support uboot reboot cmd +endif
diff --git a/board/amlogic/sc2_ah212_lpddr3/Makefile b/board/amlogic/sc2_ah212_lpddr3/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aesiv b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aeskey b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaesiv b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaeskey b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaesiv b/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaeskey b/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-user-key.sig b/board/amlogic/sc2_ah212_lpddr3/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/firmware/timing.c b/board/amlogic/sc2_ah212_lpddr3/firmware/timing.c new file mode 100644 index 0000000..3263e05 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/firmware/timing.c
@@ -0,0 +1,380 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define DSU_CLK 1200 + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = { +{ + // 2layer lpddr3 rank01 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR3, + .DRAMFreq = {400, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0xffff,//1024, + .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 60, + .cs_drv_ohm = 60, + .ac_drv_ohm = 60, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 30, // + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x3ff,//0x253, + .soc_ac_slew_rate = 0x3ff,//0x253, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 800,//200, + .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why? + .vref_dram_permil = 600,//875, + //.vref_reverse = 0, + .ac_trace_delay = {10,2,10,10,10,0x0,0x0,0x0,0x0,0x0}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ), + [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8}, + .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24}, + //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .diagnose = CONFIG_DIAGNOSE_DISABLE, + .training_offset = (0<<3) | (4<<0),//read dqs offset after training,bit3=0 right move,bit3=1 left move,bit[2:0] offset step +}, +{ + // 2layer lpddr3 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR3, + .DRAMFreq = {600, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0,//1024, + .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 60, + .cs_drv_ohm = 60, + .ac_drv_ohm = 60, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 30, // + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x3ff,//0x253, + .soc_ac_slew_rate = 0x3ff,//0x253, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 800,//200, + .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why? + .vref_dram_permil = 600,//875, + //.vref_reverse = 0, + .ac_trace_delay = {10,2,10,10,10,0x0,0x0,0x0,0x0,0x0}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ), + [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8}, + .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24}, + //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .diagnose = CONFIG_DIAGNOSE_DISABLE, + .training_offset = (0<<3) | (4<<0),//read dqs offset after training,bit3=0 right move,bit3=1 left move,bit[2:0] offset step +}, +}; + +board_clk_set_t __board_clk_setting +__attribute__ ((section(".clk_param"))) = { + /* clock settings for bl2 */ + .cpu_clk = CPU_CLK / 24 * 24, + .dsu_clk = DSU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif +}; + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG */ +#if (VDDEE_VAL == 700) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 710) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 720) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 730) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 740) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 750) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 760) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 770) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 780) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 790) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 800) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 810) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 820) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 830) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 840) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 850) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 860) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 870) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 880) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = { + //hxbao, need fine tune + {0, 0, 0xffffffff, 0, 0, 0}, +}; + +/* gpio/pinmux/pwm init */ +register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES] +__attribute__ ((section(".misc_param"))) = { + /* demo, user defined override register */ + {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + /* enable vddcpu dc-dc, set TEST_N to high */ + {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0}, + {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0}, + /* set pwm h and pwm j clock rate to 24M, enable them */ + {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3 */ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */ + {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0}, + {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0}, +}; + +/* for all the storage parameter */ +storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = { + .common = { + .version = 0x01, + .device_fip_container_size = 0x280000, + .device_fip_container_copies = 4, + }, + .nand = { + .version = 0x01, + .bbt_pages = 0x01, + .bbt_start_block = 20, + .discrete_mode = 1, + .setup_data.nand_setup_data = (2 << 20) | \ + (0 << 19) | \ + (1 << 17) | \ + (4 << 14) | \ + (0 << 13) | \ + (64 << 6) | \ + (4 << 0), + .reserved_area_blk_cnt = 48, + .page_per_block = 128, + .use_param_page_list = 0, + }, +};
diff --git a/board/amlogic/sc2_ah212_lpddr3/fw_arb.cfg b/board/amlogic/sc2_ah212_lpddr3/fw_arb.cfg new file mode 100644 index 0000000..5237e72 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/fw_arb.cfg
@@ -0,0 +1,16 @@ +# Configure Firmware Anti-rollback Versions +device_scs_vers=0x0 +device_tee_vers=0x0 +device_ree_vers=0x0 + +# Configure Segmentation ID +DEVICE_SCS_SEGID=0x0 +DEVICE_VENDOR_SEGID=0x0 + +############################################################### +DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1))) +DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1))) +DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1))) +echo $DEVICE_SCS_VERS +echo $DEVICE_TEE_VERS +echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah212_lpddr3/sc2_ah212_lpddr3.c b/board/amlogic/sc2_ah212_lpddr3/sc2_ah212_lpddr3.c new file mode 100644 index 0000000..0d297f0 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr3/sc2_ah212_lpddr3.c
@@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> +#include <asm/arch/bl31_apis.h> +#ifdef CONFIG_AML_VPU +#include <amlogic/media/vpu/vpu.h> +#endif +#ifdef CONFIG_AML_VPP +#include <amlogic/media/vpp/vpp.h> +#endif +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/media/vout/hdmitx/hdmitx_ext.h> +#endif +#ifdef CONFIG_AML_CVBS +#include <amlogic/media/vout/aml_cvbs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +#ifdef CONFIG_AML_HDMITX20 +static void hdmitx_set_hdmi_5v(void) +{ + /*Power on VCC_5V for HDMI_5V*/ +} +#endif + +void board_init_mem(void) { + #if 1 + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } + #endif +} + +int board_init(void) +{ + printf("board init\n"); + + /* The non-secure watchdog is enabled in BL2 TEE, disable it */ + run_command("watchdog off", 0); + printf("watchdog disable\n"); + + aml_set_bootsequence(0); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + #if 0 + active_clk(); + #endif + pinctrl_devices_active(PIN_CONTROLLER_NUM); + run_command("gpio clr GPIOH_8", 0); +#ifdef CONFIG_AML_HDMITX20 + hdmitx_set_hdmi_5v(); + hdmitx_init(); +#endif + return 0; +} + +int board_late_init(void) +{ + printf("board late init\n"); + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + run_command("run bcb_cmd", 0); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + /* reset vout init state */ + run_command("setenv vout_init disable", 0); +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif +#ifdef CONFIG_AML_VPP + vpp_init(); +#endif + +#ifdef CONFIG_AML_CVBS + cvbs_init(); +#endif + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ + +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf1000000UL, + .phys = 0xf1000000UL, + .size = 0x0f000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + /* update mmu table from bl2 ddr auto detect size */ +#ifdef CONFIG_UPDATE_MMU_TABLE + unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4; + switch (nddrSize) + { + case (CONFIG_1G_SIZE): + case (CONFIG_2G_SIZE): + case (CONFIG_3G_SIZE): + case (CONFIG_DDR_MAX_SIZE): + bd_mem_map[0].size = nddrSize; + break; + default : + printf("aml log : ERROR DDR detect size not match MMU !"); + break; + } +#endif + + //printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 1 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} + +uint64_t spiflash_bootloader_size(void) +{ + return 3 * SZ_1M; +} +#endif /* CONFIG_SPI_FLASH */ + +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +#ifdef CONFIG_DISCRETE_BOOTLOADER +{ + .name = BOOT_BL2E, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_BL2X, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DDRFIP, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DEVFIP, + .offset = 0, + .size = 0, +}, +#endif +{ + .name = "logo", + .offset = 0, + .size = 2*SZ_1M, +}, +{ + .name = "recovery", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 64*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} + +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +#ifdef CONFIG_MULTI_DTB +int checkhw(char * name) +{ + strcpy(name, "sc2_s905x4_ah212\0"); + setenv("aml_dt", "sc2_s905x4_ah212\0"); + return 0; +} +#endif + +const char * const _env_args_reserve_[] = +{ + "lock", + "upgrade_step", + "bootloader_version", + + NULL//Keep NULL be last to tell END +}; + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah212_lpddr4/Kconfig b/board/amlogic/sc2_ah212_lpddr4/Kconfig new file mode 100644 index 0000000..0d0d386 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/Kconfig
@@ -0,0 +1,30 @@ +if TARGET_SC2_AH212_LPDDR4 + +config SYS_SOC + default "sc2" + +config SYS_BOARD + default "sc2_ah212_lpddr4" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "sc2_ah212_lpddr3" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default n + help + support plltest command + +config AML_REBOOT + bool "reboot cmd" + default y + help + support uboot reboot cmd +endif
diff --git a/board/amlogic/sc2_ah212_lpddr4/Makefile b/board/amlogic/sc2_ah212_lpddr4/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aesiv b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aeskey b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaesiv b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaeskey b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaesiv b/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaeskey b/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-user-key.sig b/board/amlogic/sc2_ah212_lpddr4/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/firmware/timing.c b/board/amlogic/sc2_ah212_lpddr4/firmware/timing.c new file mode 100644 index 0000000..77f4303 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/firmware/timing.c
@@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define DSU_CLK 1200 + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = { +{ + // 2layer lpddr4 rank01 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR4, + .DRAMFreq = {1008, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0xffff,//1024, + .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 0, + .soc_data_odt_ohm_n = 120, + .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6 + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 120, + .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x100,//0x253, + .soc_ac_slew_rate = 0x100,//0x253, + .soc_data_slew_rate = 0x1ff, + .vref_output_permil = 350,//200, + .vref_receiver_permil = 0, + .vref_dram_permil = 0, + //.vref_reverse = 0, + .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .diagnose = CONFIG_DIAGNOSE_DISABLE, +}, +{ + // 2layer lpddr4 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1, + .DramType = CONFIG_DDR_TYPE_LPDDR4, + .DRAMFreq = {1008, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 0, + .HdtCtrl = 0xa, + .dram_cs0_size_MB = 0xffff,//1024, + .dram_cs1_size_MB = 0,//1024, + .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 0, + .soc_data_odt_ohm_n = 120, + .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6 + .dram_data_odt_ohm = 120, + .dram_ac_odt_ohm = 120, + .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq + .soc_clk_slew_rate = 0x3ff,//0x253, + .soc_cs_slew_rate = 0x100,//0x253, + .soc_ac_slew_rate = 0x100,//0x253, + .soc_data_slew_rate = 0x1ff, + .vref_output_permil = 350,//200, + .vref_receiver_permil = 0, + .vref_dram_permil = 0, + //.vref_reverse = 0, + .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00}, + .ac_pinmux = {00,00}, + .ddr_dmc_remap = { + [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ), + [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ), + [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28}, + .dram_rtt_nom_wr_park = {00,00}, + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +}; + +board_clk_set_t __board_clk_setting +__attribute__ ((section(".clk_param"))) = { + /* clock settings for bl2 */ + .cpu_clk = CPU_CLK / 24 * 24, + .dsu_clk = DSU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif +}; + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG */ +#if (VDDEE_VAL == 700) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 710) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 720) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 730) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 740) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 750) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 760) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 770) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 780) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 790) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 800) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 810) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 820) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 830) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 840) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 850) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 860) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 870) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 880) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = { + //hxbao, need fine tune + {0, 0, 0xffffffff, 0, 0, 0}, +}; + +/* gpio/pinmux/pwm init */ +register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES] +__attribute__ ((section(".misc_param"))) = { + /* demo, user defined override register */ + {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + /* enable vddcpu dc-dc, set TEST_N to high */ + {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0}, + {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0}, + /* set pwm h and pwm j clock rate to 24M, enable them */ + {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3 */ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */ + {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0}, + {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0}, +}; + +/* for all the storage parameter */ +storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = { + .common = { + .version = 0x01, + .device_fip_container_size = 0x280000, + .device_fip_container_copies = 4, + }, + .nand = { + .version = 0x01, + .bbt_pages = 0x01, + .bbt_start_block = 20, + .discrete_mode = 1, + .setup_data.nand_setup_data = (2 << 20) | \ + (0 << 19) | \ + (1 << 17) | \ + (4 << 14) | \ + (0 << 13) | \ + (64 << 6) | \ + (4 << 0), + .reserved_area_blk_cnt = 48, + .page_per_block = 128, + .use_param_page_list = 0, + }, +};
diff --git a/board/amlogic/sc2_ah212_lpddr4/fw_arb.cfg b/board/amlogic/sc2_ah212_lpddr4/fw_arb.cfg new file mode 100644 index 0000000..5237e72 --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/fw_arb.cfg
@@ -0,0 +1,16 @@ +# Configure Firmware Anti-rollback Versions +device_scs_vers=0x0 +device_tee_vers=0x0 +device_ree_vers=0x0 + +# Configure Segmentation ID +DEVICE_SCS_SEGID=0x0 +DEVICE_VENDOR_SEGID=0x0 + +############################################################### +DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1))) +DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1))) +DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1))) +echo $DEVICE_SCS_VERS +echo $DEVICE_TEE_VERS +echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah212_lpddr4/sc2_ah212_lpddr4.c b/board/amlogic/sc2_ah212_lpddr4/sc2_ah212_lpddr4.c new file mode 100644 index 0000000..12b5ebe --- /dev/null +++ b/board/amlogic/sc2_ah212_lpddr4/sc2_ah212_lpddr4.c
@@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> +#include <asm/arch/bl31_apis.h> +#ifdef CONFIG_AML_VPU +#include <amlogic/media/vpu/vpu.h> +#endif +#ifdef CONFIG_AML_VPP +#include <amlogic/media/vpp/vpp.h> +#endif +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/media/vout/hdmitx/hdmitx_ext.h> +#endif +#ifdef CONFIG_AML_CVBS +#include <amlogic/media/vout/aml_cvbs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + +#ifdef CONFIG_AML_HDMITX20 +static void hdmitx_set_hdmi_5v(void) +{ + /*Power on VCC_5V for HDMI_5V*/ +} +#endif + +void board_init_mem(void) { + #if 1 + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } + #endif +} + +int board_init(void) +{ + printf("board init\n"); + + /* The non-secure watchdog is enabled in BL2 TEE, disable it */ + run_command("watchdog off", 0); + printf("watchdog disable\n"); + + aml_set_bootsequence(0); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + #if 0 + active_clk(); + #endif + pinctrl_devices_active(PIN_CONTROLLER_NUM); + run_command("gpio clr GPIOH_8", 0); +#ifdef CONFIG_AML_HDMITX20 + hdmitx_set_hdmi_5v(); + hdmitx_init(); +#endif + return 0; +} + +int board_late_init(void) +{ + printf("board late init\n"); + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + run_command("run bcb_cmd", 0); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + /* reset vout init state */ + run_command("setenv vout_init disable", 0); +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif +#ifdef CONFIG_AML_VPP + vpp_init(); +#endif + +#ifdef CONFIG_AML_CVBS + cvbs_init(); +#endif + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ + +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf1000000UL, + .phys = 0xf1000000UL, + .size = 0x0f000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + //update mmu table from bl2 ddr auto detect size +#ifdef CONFIG_UPDATE_MMU_TABLE + unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4; + switch (nddrSize) + { + case (CONFIG_1G_SIZE): + case (CONFIG_2G_SIZE): + case (CONFIG_3G_SIZE): + case (CONFIG_DDR_MAX_SIZE): + bd_mem_map[0].size = nddrSize; + break; + default : + printf("aml log : ERROR DDR detect size not match MMU !"); + break; + } +#endif + + //printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 1 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} + +uint64_t spiflash_bootloader_size(void) +{ + return 3 * SZ_1M; +} +#endif /* CONFIG_SPI_FLASH */ + +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +#ifdef CONFIG_DISCRETE_BOOTLOADER +{ + .name = BOOT_BL2E, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_BL2X, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DDRFIP, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DEVFIP, + .offset = 0, + .size = 0, +}, +#endif +{ + .name = "logo", + .offset = 0, + .size = 2*SZ_1M, +}, +{ + .name = "recovery", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 64*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} + +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +#ifdef CONFIG_MULTI_DTB +int checkhw(char * name) +{ + strcpy(name, "sc2_s905x4_ah212\0"); + setenv("aml_dt", "sc2_s905x4_ah212\0"); + return 0; +} +#endif + +const char * const _env_args_reserve_[] = +{ + "lock", + "upgrade_step", + "bootloader_version", + + NULL//Keep NULL be last to tell END +}; + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah219/Kconfig b/board/amlogic/sc2_ah219/Kconfig new file mode 100644 index 0000000..b8e4142 --- /dev/null +++ b/board/amlogic/sc2_ah219/Kconfig
@@ -0,0 +1,31 @@ +if TARGET_SC2_AH219 + +config SYS_SOC + default "sc2" + +config SYS_BOARD + default "sc2_ah219" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "sc2_ah219" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default n + help + support plltest command + +config AML_REBOOT + bool "reboot cmd" + default y + help + support uboot reboot cmd + +endif
diff --git a/board/amlogic/sc2_ah219/Makefile b/board/amlogic/sc2_ah219/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/sc2_ah219/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah219/aml-key/bl2aesiv b/board/amlogic/sc2_ah219/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah219/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/bl2aeskey b/board/amlogic/sc2_ah219/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah219/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/bl3xaesiv b/board/amlogic/sc2_ah219/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah219/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/bl3xaeskey b/board/amlogic/sc2_ah219/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah219/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/kernelaesiv b/board/amlogic/sc2_ah219/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_ah219/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/kernelaeskey b/board/amlogic/sc2_ah219/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_ah219/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-user-key.sig b/board/amlogic/sc2_ah219/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/sc2_ah219/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/sc2_ah219/firmware/timing.c b/board/amlogic/sc2_ah219/firmware/timing.c new file mode 100644 index 0000000..30f569b --- /dev/null +++ b/board/amlogic/sc2_ah219/firmware/timing.c
@@ -0,0 +1,408 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 +#define DSU_CLK 1200 + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = { +{ + // g12a 4layer 2pcs ddr3 rank0 + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +{ + // g12a 4layer 2pcs ddr4 rank0 (1320)(U200) + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1320, 0, 0, 0}, + .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.imem_load_addr = 0xFFFC0000, //sram + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, //60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff, + .soc_cs_slew_rate = 0x3ff, + .soc_ac_slew_rate = 0x3ff, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 500, + .vref_receiver_permil = 0,//700, + .vref_dram_permil = 0,//700, + //.vref_reverse = 0, + //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, + .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32}, + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, + .fast_boot[0] = 1, +}, +}; + +board_clk_set_t __board_clk_setting +__attribute__ ((section(".clk_param"))) = { + /* clock settings for bl2 */ + .cpu_clk = CPU_CLK / 24 * 24, + .dsu_clk = DSU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif +}; + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG */ +#if (VDDEE_VAL == 700) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 710) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 720) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 730) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 740) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 750) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 760) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 770) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 780) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 790) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 800) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 810) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 820) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 830) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 840) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 850) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 860) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 870) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 880) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = { + //hxbao, need fine tune + {0, 0, 0xffffffff, 0, 0, 0}, +}; + +/* gpio/pinmux/pwm init */ +register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES] +__attribute__ ((section(".misc_param"))) = { + /* demo, user defined override register */ + {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + /* enable vddcpu dc-dc, set TEST_N to high */ + {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0}, + {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0}, + /* set pwm h and pwm j clock rate to 24M, enable them */ + {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3 */ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */ + {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0}, + {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0}, +}; + + +#ifdef CONFIG_MTD_SPI_NAND +/* for spinand storage parameter */ +storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = { + .common = { + .version = 0x01, + .device_fip_container_size = 0x300000, + .device_fip_container_copies = 4, + }, + .nand = { + .version = 0x01, + .bbt_pages = 1, // TODO: BL2E BBT + .bbt_start_block = 20, + .discrete_mode = 1, + .setup_data.spi_nand_page_size = 2048, + .reserved.spi_nand_planes_per_lun = 1, + .reserved_area_blk_cnt = 48, + .page_per_block = 64, + .use_param_page_list = 0, + }, +}; +#else +/* for slcnand storage parameter */ +storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = { + .common = { + .version = 0x01, + .device_fip_container_size = 0x300000, + .device_fip_container_copies = 4, + }, + .nand = { + .version = 0x01, + .bbt_pages = 0x01, + .bbt_start_block = 0x20, + .discrete_mode = 1, + .setup_data.nand_setup_data = (2 << 20) | \ + (0 << 19) | \ + (1 << 17) | \ + (4 << 14) | \ + (0 << 13) | \ + (64 << 6) | \ + (4 << 0), + .reserved_area_blk_cnt = 48, + .page_per_block = 128, + .use_param_page_list = 0, + }, +}; +#endif
diff --git a/board/amlogic/sc2_ah219/fw_arb.cfg b/board/amlogic/sc2_ah219/fw_arb.cfg new file mode 100644 index 0000000..5237e72 --- /dev/null +++ b/board/amlogic/sc2_ah219/fw_arb.cfg
@@ -0,0 +1,16 @@ +# Configure Firmware Anti-rollback Versions +device_scs_vers=0x0 +device_tee_vers=0x0 +device_ree_vers=0x0 + +# Configure Segmentation ID +DEVICE_SCS_SEGID=0x0 +DEVICE_VENDOR_SEGID=0x0 + +############################################################### +DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1))) +DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1))) +DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1))) +echo $DEVICE_SCS_VERS +echo $DEVICE_TEE_VERS +echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah219/sc2_ah219.c b/board/amlogic/sc2_ah219/sc2_ah219.c new file mode 100644 index 0000000..1ecd6b9 --- /dev/null +++ b/board/amlogic/sc2_ah219/sc2_ah219.c
@@ -0,0 +1,380 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> +#include <asm/arch/bl31_apis.h> +#include <amlogic/aml_mtd.h> + +#ifdef CONFIG_AML_VPU +#include <amlogic/media/vpu/vpu.h> +#endif +#ifdef CONFIG_AML_VPP +#include <amlogic/media/vpp/vpp.h> +#endif +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/media/vout/hdmitx/hdmitx_ext.h> +#endif +#ifdef CONFIG_AML_CVBS +#include <amlogic/media/vout/aml_cvbs.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + + +#ifdef CONFIG_AML_HDMITX20 +static void hdmitx_set_hdmi_5v(void) +{ + /*Power on VCC_5V for HDMI_5V*/ +} +#endif +void board_init_mem(void) { + #if 1 + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } + #endif +} + +int board_init(void) +{ + printf("board init\n"); + + /* The non-secure watchdog is enabled in BL2 TEE, disable it */ + run_command("watchdog off", 0); + printf("watchdog disable\n"); + + aml_set_bootsequence(0); + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + #if 0 + active_clk(); + #endif + pinctrl_devices_active(PIN_CONTROLLER_NUM); +#ifdef CONFIG_AML_HDMITX20 + hdmitx_set_hdmi_5v(); + hdmitx_init(); +#endif + return 0; +} + +int board_late_init(void) +{ + printf("board late init\n"); + + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + run_command("run bcb_cmd", 0); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + /* reset vout init state */ + run_command("setenv vout_init disable", 0); +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif +#ifdef CONFIG_AML_VPP + vpp_init(); +#endif +#ifdef CONFIG_AML_CVBS + cvbs_init(); +#endif + run_command("amlsecurecheck", 0); + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ + +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + //printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 1 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} + +uint64_t spiflash_bootloader_size(void) +{ + return 3 * SZ_1M; +} +#endif /* CONFIG_SPI_FLASH */ + +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +#ifdef CONFIG_DISCRETE_BOOTLOADER +{ + .name = BOOT_BL2E, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_BL2X, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DDRFIP, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DEVFIP, + .offset = 0, + .size = 0, +}, +#endif +{ + .name = "logo", + .offset = 0, + .size = 2*SZ_1M, +}, +{ + .name = "recovery", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 64*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +} +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} + +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +const char * const _env_args_reserve_[] = +{ + "lock", + "upgrade_step", + "bootloader_version", + + NULL//Keep NULL be last to tell END +}; + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_skt/Kconfig b/board/amlogic/sc2_skt/Kconfig new file mode 100644 index 0000000..5bdd867 --- /dev/null +++ b/board/amlogic/sc2_skt/Kconfig
@@ -0,0 +1,30 @@ +if TARGET_SC2_SKT + +config SYS_SOC + default "sc2" + +config SYS_BOARD + default "sc2_skt" + +config SYS_VENDOR + default "amlogic" + +config SYS_CONFIG_NAME + default "sc2_skt" + +config DTB_BIND_KERNEL + bool "load dtb from boot part but not flash rsv" + default n + +config CMD_PLLTEST + bool "support plltest command" + default n + help + support plltest command + +config AML_REBOOT + bool "reboot cmd" + default y + help + support uboot reboot cmd +endif
diff --git a/board/amlogic/sc2_skt/Makefile b/board/amlogic/sc2_skt/Makefile new file mode 100644 index 0000000..0403c0c --- /dev/null +++ b/board/amlogic/sc2_skt/Makefile
@@ -0,0 +1 @@ +obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_skt/aml-key/bl2aesiv b/board/amlogic/sc2_skt/aml-key/bl2aesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_skt/aml-key/bl2aesiv Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/bl2aeskey b/board/amlogic/sc2_skt/aml-key/bl2aeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_skt/aml-key/bl2aeskey Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/bl3xaesiv b/board/amlogic/sc2_skt/aml-key/bl3xaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_skt/aml-key/bl3xaesiv Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/bl3xaeskey b/board/amlogic/sc2_skt/aml-key/bl3xaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_skt/aml-key/bl3xaeskey Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/kernelaesiv b/board/amlogic/sc2_skt/aml-key/kernelaesiv new file mode 100644 index 0000000..01d633b --- /dev/null +++ b/board/amlogic/sc2_skt/aml-key/kernelaesiv Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/kernelaeskey b/board/amlogic/sc2_skt/aml-key/kernelaeskey new file mode 100644 index 0000000..91c9e46 --- /dev/null +++ b/board/amlogic/sc2_skt/aml-key/kernelaeskey Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-user-key.sig b/board/amlogic/sc2_skt/aml-user-key.sig new file mode 100644 index 0000000..0f89a75 --- /dev/null +++ b/board/amlogic/sc2_skt/aml-user-key.sig Binary files differ
diff --git a/board/amlogic/sc2_skt/firmware/timing.c b/board/amlogic/sc2_skt/firmware/timing.c new file mode 100644 index 0000000..5b93090 --- /dev/null +++ b/board/amlogic/sc2_skt/firmware/timing.c
@@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/secure_apb.h> +#include <asm/arch/timing.h> +#include <asm/arch/ddr_define.h> + +/* board clk defines */ +#define CPU_CLK 1512 + +/* ddr config support multiple configs for boards which use same bootloader: + * config steps: + * 1. add a new data struct in __ddr_setting[] + * 2. config correct board_id, ddr_type, freq, etc.. + */ + + +/* CAUTION!! */ +/* Confirm ddr configs with hardware designer, + * if you don't know how to config, then don't edit it + */ + +/* Key configs */ +/* + * board_id: check hardware adc config + * dram_rank_config: + * #define CONFIG_DDR_CHL_AUTO 0xF + * #define CONFIG_DDR0_16BIT_CH0 0x1 + * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 + * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 + * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 + * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 + * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 + * DramType: + * #define CONFIG_DDR_TYPE_DDR3 0 + * #define CONFIG_DDR_TYPE_DDR4 1 + * #define CONFIG_DDR_TYPE_LPDDR4 2 + * #define CONFIG_DDR_TYPE_LPDDR3 3 + * DRAMFreq: + * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq + * + */ + + +/* ddr configs */ +#define DDR_RFC_TYPE_DDR3_512Mbx1 0 +#define DDR_RFC_TYPE_DDR3_512Mbx2 1 +#define DDR_RFC_TYPE_DDR3_512Mbx4 2 +#define DDR_RFC_TYPE_DDR3_512Mbx8 3 +#define DDR_RFC_TYPE_DDR3_512Mbx16 4 +#define DDR_RFC_TYPE_DDR4_2Gbx1 5 +#define DDR_RFC_TYPE_DDR4_2Gbx2 6 +#define DDR_RFC_TYPE_DDR4_2Gbx4 7 +#define DDR_RFC_TYPE_DDR4_2Gbx8 8 + +#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 +#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 +#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 + +ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = { +{ + /* ddr3 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0, + .DramType = CONFIG_DDR_TYPE_DDR3, + /* DRAMFreq = 192, 256, 384, 512, 768-1536 */ + .DRAMFreq = {912, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 768, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 34, + .soc_data_drv_ohm_n = 34, + .soc_data_odt_ohm_p = 60, //48, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x300, + .soc_cs_slew_rate = 0x300, + .soc_ac_slew_rate = 0x300, + .soc_data_slew_rate = 0x200, + .vref_output_permil = 500, + .vref_receiver_permil = 500, //700, + .vref_dram_permil = 500, //700, + //.vref_reverse = 0, + .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32}, + //{00,00}, + .ac_pinmux = {00,00}, +#if 1 + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, +#else + //16bit + .ddr_dmc_remap = { + [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ), + [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )), + [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ), + [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ), + }, +#endif + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +{ + /* ddr4 */ + .board_id = CONFIG_BOARD_ID_MASK, + .version = 1, + .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, + .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8, + .DramType = CONFIG_DDR_TYPE_DDR4, + .DRAMFreq = {1176, 0, 0, 0}, + .ddr_base_addr = CFG_DDR_BASE_ADDR, + .ddr_start_offset = CFG_DDR_START_OFFSET, + //.dmem_load_size = 0x1000, //4K + + .DisabledDbyte = 0xf0, + .Is2Ttiming = 1, + .HdtCtrl = 0xC8, + .dram_cs0_size_MB = 0xffff, + .dram_cs1_size_MB = 0, + .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f + .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT + .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808 + .PllBypassEn = 0, //bit0-ps0,bit1-ps1 + .ddr_rdbi_wr_enable = 0, + .clk_drv_ohm = 40, + .cs_drv_ohm = 40, + .ac_drv_ohm = 40, + .soc_data_drv_ohm_p = 40, + .soc_data_drv_ohm_n = 40, + .soc_data_odt_ohm_p = 60, + .soc_data_odt_ohm_n = 0, + .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better + .dram_data_odt_ohm = 60, //60, + .dram_ac_odt_ohm = 0, + .soc_clk_slew_rate = 0x3ff, + .soc_cs_slew_rate = 0x3ff, + .soc_ac_slew_rate = 0x3ff, + .soc_data_slew_rate = 0x2ff, + .vref_output_permil = 500, + .vref_receiver_permil = 0,//700, + .vref_dram_permil = 0,//700, + //.vref_reverse = 0, + //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40}, + .ac_trace_delay = {16,32,32,32,32,32,32,32,32,32}, + .ddr_dmc_remap = { + [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ), + [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ), + [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ), + [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ), + [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ), + }, + .ddr_lpddr34_ca_remap = {00,00}, + .ddr_lpddr34_dq_remap = {00,00}, + .dram_rtt_nom_wr_park = {00,00}, + + /* pll ssc config: + * + * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], + * ppm = strength * 500 + * mode: 0=center, 1=up, 2=down + * + * eg: + * 1. config 1000ppm center ss. then mode=0, strength=2 + * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0, + * 2. config 3000ppm down ss. then mode=2, strength=6 + * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, + */ + .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm + .ddr_func = DDR_FUNC, + .magic = DRAM_CFG_MAGIC, +}, +}; + +board_clk_set_t __board_clk_setting +__attribute__ ((section(".clk_param"))) = { + /* clock settings for bl2 */ + .cpu_clk = CPU_CLK / 24 * 24, +#ifdef CONFIG_PXP_EMULATOR + .pxp = 1, +#else + .pxp = 0, +#endif +}; + + +#define VCCK_VAL AML_VCCK_INIT_VOLTAGE +#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE +/* VCCK PWM table */ +#if (VCCK_VAL == 1039) + #define VCCK_VAL_REG 0x00000022 +#elif (VCCK_VAL == 1029) + #define VCCK_VAL_REG 0x00010021 +#elif (VCCK_VAL == 1019) + #define VCCK_VAL_REG 0x00020020 +#elif (VCCK_VAL == 1009) + #define VCCK_VAL_REG 0x0003001f +#elif (VCCK_VAL == 999) + #define VCCK_VAL_REG 0x0004001e +#elif (VCCK_VAL == 989) + #define VCCK_VAL_REG 0x0005001d +#elif (VCCK_VAL == 979) + #define VCCK_VAL_REG 0x0006001c +#elif (VCCK_VAL == 969) + #define VCCK_VAL_REG 0x0007001b +#elif (VCCK_VAL == 959) + #define VCCK_VAL_REG 0x0008001a +#elif (VCCK_VAL == 949) + #define VCCK_VAL_REG 0x00090019 +#elif (VCCK_VAL == 939) + #define VCCK_VAL_REG 0x000a0018 +#elif (VCCK_VAL == 929) + #define VCCK_VAL_REG 0x000b0017 +#elif (VCCK_VAL == 919) + #define VCCK_VAL_REG 0x000c0016 +#elif (VCCK_VAL == 909) + #define VCCK_VAL_REG 0x000d0015 +#elif (VCCK_VAL == 899) + #define VCCK_VAL_REG 0x000e0014 +#elif (VCCK_VAL == 889) + #define VCCK_VAL_REG 0x000f0013 +#elif (VCCK_VAL == 879) + #define VCCK_VAL_REG 0x00100012 +#elif (VCCK_VAL == 869) + #define VCCK_VAL_REG 0x00110011 +#elif (VCCK_VAL == 859) + #define VCCK_VAL_REG 0x00120010 +#elif (VCCK_VAL == 849) + #define VCCK_VAL_REG 0x0013000f +#elif (VCCK_VAL == 839) + #define VCCK_VAL_REG 0x0014000e +#elif (VCCK_VAL == 829) + #define VCCK_VAL_REG 0x0015000d +#elif (VCCK_VAL == 819) + #define VCCK_VAL_REG 0x0016000c +#elif (VCCK_VAL == 809) + #define VCCK_VAL_REG 0x0017000b +#elif (VCCK_VAL == 799) + #define VCCK_VAL_REG 0x0018000a +#elif (VCCK_VAL == 789) + #define VCCK_VAL_REG 0x00190009 +#elif (VCCK_VAL == 779) + #define VCCK_VAL_REG 0x001a0008 +#elif (VCCK_VAL == 769) + #define VCCK_VAL_REG 0x001b0007 +#elif (VCCK_VAL == 759) + #define VCCK_VAL_REG 0x001c0006 +#elif (VCCK_VAL == 749) + #define VCCK_VAL_REG 0x001d0005 +#elif (VCCK_VAL == 739) + #define VCCK_VAL_REG 0x001e0004 +#elif (VCCK_VAL == 729) + #define VCCK_VAL_REG 0x001f0003 +#elif (VCCK_VAL == 719) + #define VCCK_VAL_REG 0x00200002 +#elif (VCCK_VAL == 709) + #define VCCK_VAL_REG 0x00210001 +#elif (VCCK_VAL == 699) + #define VCCK_VAL_REG 0x00220000 +#else + #error "VCCK val out of range\n" +#endif + +/* VDDEE_VAL_REG */ +#if (VDDEE_VAL == 700) + #define VDDEE_VAL_REG 0x120000 +#elif (VDDEE_VAL == 710) + #define VDDEE_VAL_REG 0x110001 +#elif (VDDEE_VAL == 720) + #define VDDEE_VAL_REG 0x100002 +#elif (VDDEE_VAL == 730) + #define VDDEE_VAL_REG 0xf0003 +#elif (VDDEE_VAL == 740) + #define VDDEE_VAL_REG 0xe0004 +#elif (VDDEE_VAL == 750) + #define VDDEE_VAL_REG 0xd0005 +#elif (VDDEE_VAL == 760) + #define VDDEE_VAL_REG 0xc0006 +#elif (VDDEE_VAL == 770) + #define VDDEE_VAL_REG 0xb0007 +#elif (VDDEE_VAL == 780) + #define VDDEE_VAL_REG 0xa0008 +#elif (VDDEE_VAL == 790) + #define VDDEE_VAL_REG 0x90009 +#elif (VDDEE_VAL == 800) + #define VDDEE_VAL_REG 0x8000a +#elif (VDDEE_VAL == 810) + #define VDDEE_VAL_REG 0x7000b +#elif (VDDEE_VAL == 820) + #define VDDEE_VAL_REG 0x6000c +#elif (VDDEE_VAL == 830) + #define VDDEE_VAL_REG 0x5000d +#elif (VDDEE_VAL == 840) + #define VDDEE_VAL_REG 0x4000e +#elif (VDDEE_VAL == 850) + #define VDDEE_VAL_REG 0x3000f +#elif (VDDEE_VAL == 860) + #define VDDEE_VAL_REG 0x20010 +#elif (VDDEE_VAL == 870) + #define VDDEE_VAL_REG 0x10011 +#elif (VDDEE_VAL == 880) + #define VDDEE_VAL_REG 0x12 +#else + #error "VDDEE val out of range\n" +#endif + +bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = { + //hxbao, need fine tune + {0, 0, 0xffffffff, 0, 0, 0}, +}; + +/* gpio/pinmux/pwm init */ +register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES] +__attribute__ ((section(".misc_param"))) = { + /* demo, user defined override register */ + {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0}, + {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0}, + /* enable vddcpu dc-dc, set TEST_N to high */ + {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0}, + {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0}, + /* set pwm h and pwm j clock rate to 24M, enable them */ + {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 drive strength to 3 */ + {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0}, + /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */ + {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0}, + {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0}, +}; + +/* for all the storage parameter */ +storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = { + .common = { + .version = 0x01, + .device_fip_container_size = 0x280000, + .device_fip_container_copies = 4, + }, + .nand = { + .version = 0x01, + .bbt_pages = 0x1, + .bbt_start_block = 0x20, + .discrete_mode = 1, + .setup_data.nand_setup_data = (2 << 20) | \ + (0 << 19) | \ + (1 << 17) | \ + (4 << 14) | \ + (0 << 13) | \ + (64 << 6) | \ + (4 << 0), + .reserved_area_blk_cnt = 48, + .page_per_block = 128, + .use_param_page_list = 0, + }, +};
diff --git a/board/amlogic/sc2_skt/fw_arb.cfg b/board/amlogic/sc2_skt/fw_arb.cfg new file mode 100644 index 0000000..5237e72 --- /dev/null +++ b/board/amlogic/sc2_skt/fw_arb.cfg
@@ -0,0 +1,16 @@ +# Configure Firmware Anti-rollback Versions +device_scs_vers=0x0 +device_tee_vers=0x0 +device_ree_vers=0x0 + +# Configure Segmentation ID +DEVICE_SCS_SEGID=0x0 +DEVICE_VENDOR_SEGID=0x0 + +############################################################### +DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1))) +DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1))) +DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1))) +echo $DEVICE_SCS_VERS +echo $DEVICE_TEE_VERS +echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_skt/sc2_skt.c b/board/amlogic/sc2_skt/sc2_skt.c new file mode 100644 index 0000000..d0cd0e5 --- /dev/null +++ b/board/amlogic/sc2_skt/sc2_skt.c
@@ -0,0 +1,356 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <errno.h> +#include <environment.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/pinctrl_init.h> +#include <linux/sizes.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <asm/armv8/mmu.h> +#include <amlogic/aml_v3_burning.h> +#include <amlogic/aml_v2_burning.h> +#include <linux/mtd/partitions.h> +#include <asm/arch/bl31_apis.h> +#ifdef CONFIG_AML_VPU +#include <amlogic/media/vpu/vpu.h> +#endif +#ifdef CONFIG_AML_VPP +#include <amlogic/media/vpp/vpp.h> +#endif +#ifdef CONFIG_AML_HDMITX20 +#include <amlogic/media/vout/hdmitx/hdmitx_module.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void sys_led_init(void) +{ +} + +int serial_set_pin_port(unsigned long port_base) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +/* secondary_boot_func + * this function should be write with asm, here, is is only for compiling pass + * */ +void secondary_boot_func(void) +{ +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +int active_clk(void) +{ + struct udevice *clk = NULL; + int err; + + err = uclass_get_device_by_name(UCLASS_CLK, + "xtal-clk", &clk); + if (err) { + pr_err("Can't find xtal-clk clock (%d)\n", err); + return err; + } + err = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@0", &clk); + if (err) { + pr_err("Can't find clock-controller@0 clock (%d)\n", err); + return err; + } + + return 0; +} + + +#ifdef CONFIG_AML_HDMITX20 +static void hdmitx_set_hdmi_5v(void) +{ + /*Power on VCC_5V for HDMI_5V*/ +} +#endif +void board_init_mem(void) { + #if 1 + /* config bootm low size, make sure whole dram/psram space can be used */ + phys_size_t ram_size; + char *env_tmp; + env_tmp = env_get("bootm_size"); + if (!env_tmp) { + ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); + env_set_hex("bootm_low", 0); + env_set_hex("bootm_size", ram_size); + } + #endif +} + +int board_init(void) +{ + printf("board init\n"); + + /* The non-secure watchdog is enabled in BL2 TEE, disable it */ + run_command("watchdog off", 0); + printf("watchdog disable\n"); + aml_set_bootsequence(0); + #if 0 + //Please keep try usb boot first in board_init, as other init before usb may cause burning failure +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2))) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + active_clk(); + #endif + pinctrl_devices_active(PIN_CONTROLLER_NUM); +#ifdef CONFIG_AML_HDMITX20 + hdmitx_set_hdmi_5v(); + hdmitx_init(); +#endif + return 0; +} + +int board_late_init(void) +{ + printf("board late init\n"); + + #if 0 + run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\ + "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0); + board_init_mem(); + +#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + if ( run_command("run common_dtb_load", 0) ) { + printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load")); + } else { + //load dtb here then users can directly use 'fdt' command + run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0); + } +#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb + +#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard + aml_try_factory_sdcard_burning(0, gd->bd); +#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE + //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003' +#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2)) + { aml_v3_factory_usb_burning(0, gd->bd); } +#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl) + + #endif + +#ifdef CONFIG_AML_VPU + vpu_probe(); +#endif +#ifdef CONFIG_AML_VPP + vpp_init(); +#endif + return 0; +} + + +phys_size_t get_effective_memsize(void) +{ + // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4 +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE; +#else + return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4); +#endif /* CONFIG_SYS_MEM_TOP_HIDE */ + +} + +static struct mm_region bd_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bd_mem_map; + +int mach_cpu_init(void) { + //printf("\nmach_cpu_init\n"); + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + /* eg: bl31/32 rsv */ + return 0; +} + +/* partition table for spinor flash */ +#ifdef CONFIG_SPI_FLASH +static const struct mtd_partition spiflash_partitions[] = { + { + .name = "env", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "dtb", + .offset = 0, + .size = 1 * SZ_256K, + }, + { + .name = "boot", + .offset = 0, + .size = 2 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "user", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; + +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spiflash_partitions); + return spiflash_partitions; +} +#endif /* CONFIG_SPI_FLASH */ + +#ifdef CONFIG_MESON_NFC +static struct mtd_partition normal_partition_info[] = { +#ifdef CONFIG_DISCRETE_BOOTLOADER +{ + .name = BOOT_BL2E, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_BL2X, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DDRFIP, + .offset = 0, + .size = 0, +}, +{ + .name = BOOT_DEVFIP, + .offset = 0, + .size = 0, +}, +#endif +{ + .name = "logo", + .offset = 0, + .size = 2*SZ_1M, +}, +{ + .name = "recovery", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "boot", + .offset = 0, + .size = 16*SZ_1M, +}, +{ + .name = "system", + .offset = 0, + .size = 64*SZ_1M, +}, +/* last partition get the rest capacity */ +{ + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, +}, +}; + +struct mtd_partition *get_aml_mtd_partition(void) +{ + return normal_partition_info; +} + +int get_aml_partition_count(void) +{ + return ARRAY_SIZE(normal_partition_info); +} + +#endif + +/* partition table */ +/* partition table for spinand flash */ +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) +static const struct mtd_partition spinand_partitions[] = { + { + .name = "logo", + .offset = 0, + .size = 2 * SZ_1M, + }, + { + .name = "recovery", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "boot", + .offset = 0, + .size = 16 * SZ_1M, + }, + { + .name = "system", + .offset = 0, + .size = 64 * SZ_1M, + }, + /* last partition get the rest capacity */ + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +}; +const struct mtd_partition *get_partition_table(int *partitions) +{ + *partitions = ARRAY_SIZE(spinand_partitions); + return spinand_partitions; +} +#endif /* CONFIG_SPI_NAND */ + +int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;} + +int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;} + +void __attribute__((weak)) set_working_fdt_addr(ulong addr) {} + +int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;} + +void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/build_uboot.sh b/build_uboot.sh index c916320..da14fcb 100755 --- a/build_uboot.sh +++ b/build_uboot.sh
@@ -1,6 +1,9 @@ #!/bin/bash exec_name=$0 +dbg_flag="debug" +zircon_cfg="" +prebuilt_path="" set -o errtrace trap 'echo Fatal error: script ${exec_name} aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR @@ -11,14 +14,30 @@ echo DIR:$DIR function usage(){ - echo "Usage: ${exec_name} <board> [workspace path]" - echo "supported boards: estelle-p1, estelle-p2" - echo " newman-p2, newman-p2_1, newman-b1, newman-b3, newman-b4" - echo " legion-p1" - echo " puddy-p0" - echo " elaine-p0, elaine-p1" - echo " nq-p2, nq-b1, nq-b3, nq-b4" - echo " gq-p2, gq-b1, gq-b3, gq-b4" + echo "Usage: ${exec_name} <board> [workspace path] [-o (prebuilt path)]" + echo "supported boards: spencer-p1/p2/b1/b3/b4, venus-p1/p2, a049-p0, bsv3-p1" +} + +function update_prebuilt_path() { + has_bl2_bl3x=0 + if [ -d $DIR/../bl2 ] && [ -d $DIR/../bl31 ] && [ -d $DIR/../bl32 ]; then + has_bl2_bl3x=1 + fi + + if [ "$has_bl2_bl3x" == "0" ]; then + default_prebuilt_path=${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/blx + if [ -d ${default_prebuilt_path} ]; then + prebuilt_path=${default_prebuilt_path} + echo "use prebuilt from ${prebuilt_path}" + fi + fi + + if [ -z "$prebuilt_path" ]; then + prebuilt_path=fip/${soc_family_name} + echo "unspecified prebuilt path, will use local prebuilt ${prebuilt_path}" + fi + + echo "current prebuilt path: ${prebuilt_path}" } function building_uboot(){ @@ -29,33 +48,27 @@ cfg_suffix=$6 config=${local_name}_${rev}${cfg_suffix} + product=`echo ${board} | cut -d "-" -f1` echo "building u-boot for ${board}" - ./mk ${config} --board_name $board_name --bl2 fip/${soc_family_name}/bl2.bin --bl30 fip/${soc_family_name}/bl30.bin --bl31 fip/${soc_family_name}/bl31.img --bl32 fip/${soc_family_name}/bl32.img $5 + update_prebuilt_path + ./mk ${config} --board_name $board_name --bl2 ${prebuilt_path}/bl2.bin --bl30 ${prebuilt_path}/bl30.bin --bl31 ${prebuilt_path}/bl31.img --bl32 ${prebuilt_path}/bl32.img $5 # make T=1 to use latest git commit time as build timestamp. echo "mk done\n" - product=`echo ${board} | cut -d "-" -f1` if [ ! -z $workspace_path ]; then mkdir -p ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - if [ "$product" == "estelle" ] || \ - [ "$product" == "newman" ] || \ - [ "$product" == "legion" ] || \ - [ "$product" == "puddy" ] || \ - [ "$product" == "elaine" ] || \ - [ "$product" == "nq" ] || \ - [ "$product" == "gq" ]; then + if [ "$product" == "spencer" ] || \ + [ "$product" == "venus" ] || \ + [ "$product" == "a049" ] || \ + [ "$product" == "bsv3" ] || \ + [ "$product" == "bla4" ] || \ + [ "$product" == "2rs4" ] || \ + [ "$product" == "xua4" ]; then # Copy bl2 and bl3x images for bootloader signing under eureka source. cp fip/build/bl2_new.bin \ ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl2_new.bin.${board} - if [[ "$product" == "nq" || "$product" == "gq" ]] ; then - cp fip/c1/bl30_new.fake \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl30_new.bin.${board} - else - cp fip/build/bl30_new.bin \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl30_new.bin.${board} - fi cp fip/build/bl31.img \ ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl31.img.${board} cp fip/build/bl32.img \ @@ -65,22 +78,13 @@ # Copy ddr bin for bootloader signing under eureka source. # TODO(ljchen): Remove hard code of ddr files under vendor/amlogic. - cp fip/${soc_family_name}/ddr4_1d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/ddr4_2d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/ddr3_1d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/piei.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/lpddr4_1d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/lpddr4_2d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/diag_lpddr4.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/aml_ddr.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ + if [ "$board" == "a049-p0" ]; then + cp fip/${soc_family_name}/aml_ddr.fw \ + ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/aml_ddr.fw.$board + else + cp fip/${soc_family_name}/aml_ddr.fw \ + ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ + fi else cp fip/${soc_family_name}/u-boot.bin.usb.bl2 \ @@ -107,71 +111,103 @@ readonly cross_compile_t32=$DIR/../amlogic/linaro/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi- readonly vendor_amlogic=$DIR/../vendor/amlogic -dbg_flag="debug" -zircon_cfg="" - -if [ "$3" = "release" -o "$4" = "release" ]; then - dbg_flag="release" -elif [ "$4" = "zircon" -o "$5" = "zircon" ]; then - zircon_cfg="_zircon" +shift +if [ -n "$workspace_path" ]; then + shift fi - +for arg in "$@" +do + case $arg in + -d) + shift + ;; + release) + dbg_flag="release" + shift + ;; + zircon) + zircon_cfg="_zircon" + shift + ;; + -o) + shift + if [ -n "$1" ]; then + prebuilt_path=$1 + shift + else + echo "Error: -o option requires an argument." + exit 1 + fi + ;; + esac +done export ENABLE_UBOOT_UPDATE=1 +export ENABLE_UBOOT_CLI=1 export ENABLE_PRODUCTION_MODE=0 + case $board in - estelle-p1) - building_uboot g12a g12a_estelle p1 $board + spencer-p1) + building_uboot c2 c2_spencer p1 $board $dbg_flag ;; - estelle-p2) - building_uboot g12a g12a_estelle p2 $board + spencer-p2) + building_uboot c2 c2_spencer p2 $board $dbg_flag ;; - newman-p2) - building_uboot g12b g12b_newman px $board $dbg_flag $zircon_cfg + spencer-b1|spencer-b3) + export ENABLE_UBOOT_CLI=0 + building_uboot c2 c2_spencer bx $board $dbg_flag ;; - newman-p2_1) - building_uboot g12b g12b_newman p2_1 $board $dbg_flag $zircon_cfg - ;; - newman-b1|newman-b3) - building_uboot g12b g12b_newman bx $board $dbg_flag $zircon_cfg - ;; - newman-b4) + spencer-b4) export ENABLE_UBOOT_UPDATE=0 - building_uboot g12b g12b_newman bx $board $dbg_flag $zircon_cfg - ;; - legion-p1) - building_uboot g12a gl2a_legion p1 $board - ;; - puddy-p0) - building_uboot g12b g12b_puddy px $board $dbg_flag $zircon_cfg - ;; - elaine-p0) - building_uboot sm1 sm1_elaine p0 $board $dbg_flag - ;; - elaine-p1) - building_uboot sm1 sm1_elaine p1 $board $dbg_flag - ;; - nq-p2) - building_uboot c1 c1_nq p2 $board $dbg_flag - ;; - nq-b1|nq-b3) - building_uboot c1 c1_nq bx $board $dbg_flag - ;; - nq-b4) - export ENABLE_UBOOT_UPDATE=0 + export ENABLE_UBOOT_CLI=0 export ENABLE_PRODUCTION_MODE=1 - building_uboot c1 c1_nq bx $board $dbg_flag + building_uboot c2 c2_spencer bx $board $dbg_flag ;; - gq-p2) - building_uboot c1 c1_gq p2 $board $dbg_flag + venus-p1) + building_uboot c2 c2_venus p1 $board $dbg_flag ;; - gq-b1|gq-b3) - building_uboot c1 c1_gq bx $board $dbg_flag + venus-p2) + building_uboot c2 c2_venus p2 $board $dbg_flag ;; - gq-b4) + venus-b1|venus-b3) + building_uboot c2 c2_venus bx $board $dbg_flag + ;; + venus-b4) export ENABLE_UBOOT_UPDATE=0 + export ENABLE_UBOOT_CLI=0 export ENABLE_PRODUCTION_MODE=1 - building_uboot c1 c1_gq bx $board $dbg_flag + building_uboot c2 c2_venus bx $board $dbg_flag + ;; + a049-p0) + export ENABLE_UBOOT_CLI=0 + building_uboot c2 c2_a049 p0 $board $dbg_flag + ;; + bsv3-p1) + building_uboot c2 c2_bsv3 p1 $board $dbg_flag + ;; + bla4-p0) + building_uboot c2 c2_bla4 p0 $board $dbg_flag + ;; + bla4-p1) + building_uboot c2 c2_bla4 p1 $board $dbg_flag + ;; + bla4-p2) + building_uboot c2 c2_bla4 p2 $board $dbg_flag + ;; + bla4-b1) + building_uboot c2 c2_bla4 bx $board $dbg_flag + ;; + 2rs4-p1) + building_uboot c2 c2_2rs4 p1 $board $dbg_flag + ;; + 2rs4-p2) + building_uboot c2 c2_2rs4 p2 $board $dbg_flag + ;; + xua4-p1) + building_uboot c2 c2_xua4 p1 $board $dbg_flag + ;; + xua4-b1) + building_uboot c2 c2_xua4 bx $board $dbg_flag ;; *) echo "unknown board: $board"
diff --git a/build_uboot_spencer_mars.sh b/build_uboot_spencer_mars.sh deleted file mode 100755 index 94b728a..0000000 --- a/build_uboot_spencer_mars.sh +++ /dev/null
@@ -1,124 +0,0 @@ -#!/bin/bash - -exec_name=$0 - -set -o errtrace -trap 'echo Fatal error: script ${exec_name} aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR - -cpu_num=$(grep -c processor /proc/cpuinfo) - -DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" -echo DIR:$DIR - -function usage(){ - echo "Usage: ${exec_name} <board> [workspace path]" - echo "supported boards: spencer-p0, mars-p0" -} - -function building_uboot(){ - soc_family_name=$1 - local_name=$2 - rev=$3 - board_name=$4 - cfg_suffix=$6 - - config=${local_name}_${rev}${cfg_suffix} - echo "building u-boot for ${board}" - - ./mk ${config} --board_name $board_name --bl2 fip/${soc_family_name}/bl2.bin --bl30 fip/${soc_family_name}/bl30.bin --bl31 fip/${soc_family_name}/bl31.img --bl32 fip/${soc_family_name}/bl32.img $5 - - # make T=1 to use latest git commit time as build timestamp. - - echo "mk done\n" - product=`echo ${board} | cut -d "-" -f1` - if [ ! -z $workspace_path ]; then - mkdir -p ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - if [ "$product" == "spencer" ] || \ - [ "$product" == "mars" ]; then - # Copy bl2 and bl3x images for bootloader signing under eureka source. - cp fip/build/bl2_new.bin \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl2_new.bin.${board} - if [[ "$product" == "spencer" || "$product" == "mars" ]] ; then - cp fip/c1/bl30_new.fake \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl30_new.bin.${board} - else - cp fip/build/bl30_new.bin \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl30_new.bin.${board} - fi - cp fip/build/bl31.img \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl31.img.${board} - cp fip/build/bl32.img \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl32.img.${board} - cp fip/build/bl33.bin \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/bl33.bin.${board} - - # Copy ddr bin for bootloader signing under eureka source. - # TODO(ljchen): Remove hard code of ddr files under vendor/amlogic. - cp fip/${soc_family_name}/ddr4_1d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/ddr4_2d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/ddr3_1d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/piei.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/lpddr4_1d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/lpddr4_2d.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/diag_lpddr4.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/ - cp fip/${soc_family_name}/aml_ddr.fw \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/aml_ddr.fw.${board} - - else - cp fip/${soc_family_name}/u-boot.bin.usb.bl2 \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/u-boot.bin.usb.bl2 - cp fip/${soc_family_name}/u-boot.bin.usb.tpl \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/u-boot.bin.usb.tpl - cp fip/${soc_family_name}/u-boot.bin \ - ${workspace_path}/vendor/amlogic/${product}/prebuilt/bootloader/u-boot.bin - fi - fi -} - -if (( $# < 1 )) -then - usage - exit 2 -fi - -pushd $DIR - -readonly board=$1 -readonly workspace_path=$2 -readonly cross_compile=$DIR/../amlogic/linaro/gcc-linaro-7.3.1-2018.05-i686_aarch64-elf/bin/aarch64-elf- -readonly cross_compile_t32=$DIR/../amlogic/linaro/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi- -readonly vendor_amlogic=$DIR/../vendor/amlogic - -dbg_flag="debug" -zircon_cfg="" - -if [ "$3" = "release" -o "$4" = "release" ]; then - dbg_flag="release" -elif [ "$4" = "zircon" -o "$5" = "zircon" ]; then - zircon_cfg="_zircon" -fi - - -export ENABLE_UBOOT_UPDATE=1 - -case $board in - spencer-p0) - # Spencer mock board based on nq-p2 - building_uboot c1 c1_nq p2 $board $dbg_flag - ;; - mars-p0) - # Mars mock board based on gq-p2 - building_uboot c1 c1_gq p2 $board $dbg_flag - ;; - *) - echo "unknown board: $board" - exit 1 -esac -popd
diff --git a/cmd/Kconfig b/cmd/Kconfig index 6786480..51f3e27 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig
@@ -896,6 +896,7 @@ default y if NAND_SUNXI default y if MESON_NFC default y if SPI_NAND + default y if MTD_SPI_NAND help NAND support.
diff --git a/cmd/aml_mmc.c b/cmd/aml_mmc.c index 5cee627..3ffc78b 100644 --- a/cmd/aml_mmc.c +++ b/cmd/aml_mmc.c
@@ -325,7 +325,7 @@ /* erase bootloader in user/boot0/boot1 */ for (i = mmc_part_nonius; i < count; i++) { if (map & (0x1 << i)) { - if (!blk_select_hwpart(mmc->dev,i)) { + if (!blk_select_hwpart_devnum(IF_TYPE_MMC, 1, i)) { /* some customer may use boot1 higher 2M as private data. */ #ifdef CONFIG_EMMC_BOOT1_TOUCH_REGION if (2 == i && CONFIG_EMMC_BOOT1_TOUCH_REGION <= size) { @@ -1464,7 +1464,6 @@ } #endif -#ifdef CONFIG_WRITE_PROTECT static int set_write_prot(struct mmc *mmc, u64 start) { struct mmc_cmd cmd; @@ -1646,9 +1645,9 @@ int blk_shift; struct partitions *part_info; u64 cnt; - u64 start = 0; - u64 align_start = 0; - u64 wp_grp_size = 0; + u64 start = *start_addr; + u64 align_start = *start_addr; + u64 wp_grp_size = *wp_grp_size_addr; u64 group_num ; u64 partition_end; @@ -2514,7 +2513,6 @@ return ret; } -#endif static int set_driver_strength(struct mmc *mmc, int strength) { @@ -2669,12 +2667,10 @@ U_BOOT_CMD_MKENT(controller, 3, 0, do_amlmmc_controller, "", ""), U_BOOT_CMD_MKENT(size, 4, 0, do_amlmmc_size, "", ""), U_BOOT_CMD_MKENT(env, 2, 0, do_amlmmc_env, "", ""), -#ifdef CONFIG_WRITE_PROTECT U_BOOT_CMD_MKENT(write_protect, 5, 0, do_amlmmc_write_protect, "", ""), U_BOOT_CMD_MKENT(send_wp_status, 4, 0, do_amlmmc_send_wp_status, "", ""), U_BOOT_CMD_MKENT(send_wp_type, 4, 0, do_amlmmc_send_wp_type, "", ""), U_BOOT_CMD_MKENT(clear_wp, 4, 0, do_amlmmc_clear_wp, "", ""), -#endif U_BOOT_CMD_MKENT(ds, 4, 0, do_amlmmc_driver_strength, "", ""), #ifdef CONFIG_SECURITYKEY U_BOOT_CMD_MKENT(key, 2, 0, do_amlmmc_key, "", ""), @@ -2713,7 +2709,6 @@ "amlmmc ext_csd <device_num> <byte> <value> - write sd/emmc device EXT_CSD [byte] value\n" "amlmmc response <device_num> - read sd/emmc last command response\n" "amlmmc controller <device_num> - read sd/emmc controller register\n" -#ifdef CONFIG_WRITE_PROTECT "amlmmc write_protect <partition_name> <write_protect_type>\n" " - set write protect on partition through power_on or temporary\n" "amlmmc write_protect <addr_base16> <cnt_base10> <write_protect_type>\n" @@ -2724,7 +2719,6 @@ "amlmmc send_wp_type <addr_base16> <cnt_base10> send protect type on specified address\n" "amlmmc clear_wp <partition_name> clear write protect of partition\n" "amlmmc clear_wp <addr_base16> <cnt_base10> clear write protect on specified addresst\n" -#endif "amlmmc ds <dev_num> <val> set driver strength\n" #ifdef CONFIG_SECURITYKEY "amlmmc key - disprotect key partition\n" @@ -3205,6 +3199,34 @@ return ret; } +int emmc_erase_rsv(struct mmc *mmc, char *rsv_part) +{ + u64 cnt = 0, n = 0, blk = 0; + struct partitions *part = NULL; + struct virtual_partition *vpart = NULL; + + if (rsv_part == NULL) + return -1; + + vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME); + part = aml_get_partition_by_name(MMC_RESERVED_NAME); + if (strcmp(rsv_part, "dtb") == 0) { + blk = (part->offset + vpart->offset) / mmc->read_bl_len; + cnt = (vpart->size * 2) / mmc->read_bl_len; + if (cnt != 0) + n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt); + printf("%s is erased %s\n", + rsv_part, (n == 0) ? "OK" : "ERROR"); + return (n == 0) ? 0 : 1; + } else if (strcmp(rsv_part, "key") == 0) { + n = mmc_key_erase(); + printf("%s is erased %s\n", + rsv_part, (n == 0) ? "OK" : "ERROR"); + return (n == 0) ? 0 : 1; + } + return 1; +} + int do_emmc_erase(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int dev;
diff --git a/cmd/amlogic/Kconfig b/cmd/amlogic/Kconfig index b06606d..2a45610 100644 --- a/cmd/amlogic/Kconfig +++ b/cmd/amlogic/Kconfig
@@ -1,8 +1,9 @@ menu "Amlogic commands" -config AML_RPMB_DISABLE +config AML_RPMB + depends on OPTEE bool "support RPMB set in bootargs" - default n + default y help Support RPMB set in bootargs. @@ -112,7 +113,27 @@ config CMD_GET_CHIPTYPE bool "get chip type in u-boot" - default y + default n help get chip type and save to command line + +config CMD_AML_MISC + bool "classify amlogic misc command" + default y + help + classify amlogic misc command to the fixed file + +config ENABLE_CHARGER_DETECTION + bool "enable and disable charger detection" + default n + help + only allow booting when charger is detected as DCP + +config AML_ROBUST + bool "envs for robust upgrade" + depends on AML_STORAGE + default y + help + "envs for robust upgrade like defendkey" + endmenu
diff --git a/cmd/amlogic/Makefile b/cmd/amlogic/Makefile index 47c327e..2d2255b 100644 --- a/cmd/amlogic/Makefile +++ b/cmd/amlogic/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_AML_STORE_WRAPPER) += store_wrapper.o obj-$(CONFIG_AML_IMG_READ) += imgread.o obj-$(CONFIG_AML_DEFENV) += defenv_without.o +obj-$(CONFIG_AML_ROBUST) += bootloader_status.o # amlogic commands obj-$(CONFIG_CMD_REBOOT) += cmd_reboot.o flash_ts.o nand_ts.o mmc_ts.o @@ -23,18 +24,19 @@ ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK #obj-y += cmd_bcb.o #obj-y += get_bcb_boot_part.o +obj-y += cmd_dynamic.o ifdef CONFIG_CMD_BOOTCTOL_AVB obj-y += cmd_bootctl_avb.o else obj-y += cmd_bootctl.o endif endif -ifndef CONFIG_AML_RPMB_DISABLE -#obj-y += cmd_rpmb.o -endif +obj-$(CONFIG_AML_RPMB) += cmd_rpmb.o obj-$(CONFIG_CMD_BOOTCTOL_AVB) += cmd_avb.o obj-$(CONFIG_CMD_DDR_D2PLL) += cmd_d2pll.o obj-$(CONFIG_CMD_DDR_TEST) += cmd_ddr_test_g12.o obj-$(CONFIG_CMD_OS_IDENT) += os_ident.o obj-$(CONFIG_CMD_GET_CHIPTYPE) += cmd_get_chiptype.o +obj-$(CONFIG_AML_FACTORY_PROVISION) += cmd_factory_provision.o +obj-$(CONFIG_CMD_AML_MISC) += cmd_misc.o
diff --git a/cmd/amlogic/bootloader_status.c b/cmd/amlogic/bootloader_status.c new file mode 100644 index 0000000..ffb0612 --- /dev/null +++ b/cmd/amlogic/bootloader_status.c
@@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <config.h> +#include <common.h> +#include <linux/kernel.h> +#include <amlogic/aml_efuse.h> +#include <amlogic/cpu_id.h> +#include <amlogic/storage.h> + +#ifndef IS_FEAT_BOOT_VERIFY +#define IS_FEAT_BOOT_VERIFY() 0 +#endif// #ifndef IS_FEAT_BOOT_VERIFY +int __attribute__((weak)) store_logic_read(const char *name, loff_t off, size_t size, void *buf) +{ return store_read(name, off, size, buf);} + +typedef struct andr_img_hdr boot_img_hdr; + +#define debugP(fmt...) //printf("[DbgBootSta]L%d:", __LINE__),printf(fmt) +#define errorP(fmt...) printf("ErrBootSta(L%d):", __LINE__),printf(fmt) +#define wrnP(fmt...) printf("wrn:"fmt) +#define MsgP(fmt...) printf("[BootSta]"fmt) + +//check SWPL-31296 for details +static int do_get_bootloader_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bool printStat = false; + bool saveenv = false; + debugP("Initial value for argc=%d\n", argc); + while (argc > 1 && **(argv + 1) == '-') { + char *arg = *++argv; + + --argc; + while (*++arg) { + switch (*arg) { + case 'p': /* print */ + printStat = true; + break; + case 's': /* saveenv */ + saveenv = true; + break; + default: + return CMD_RET_USAGE; + } + } + } + debugP("Final value for argc=%d\n", argc); + //1,forUpgrade_socType, cpu familyId + const cpu_id_t cpuid = get_cpu_id(); + const int familyId = cpuid.family_id; + env_set_hex("forUpgrade_socType", familyId); + + //2,forUpgrade_secureBoot + const bool secureboot = IS_FEAT_BOOT_VERIFY(); + env_set("forUpgrade_secureBoot", secureboot ? "true" : "false"); + + //3,forUpgrade_robustOta + bool supportRobustOta = false; + switch (familyId) { + case 0x32: + supportRobustOta = true; + break; + default:break; + } + env_set("forUpgrade_robustOta", supportRobustOta ? "true" : "false"); + + //4,forUpgrade_flashType + const char* BootDevices[] = { + "BOOT_EMMC", "BOOT_SD", + "BOOT_NAND_NFTL", "BOOT_NAND_MTD", + "BOOT_SNAND", "BOOT_SNOR", + }; + const char* bootDevice = "BOOT_NONE"; + enum boot_type_e bootType = store_get_type(); + int i = 0; + for (; i < ARRAY_SIZE(BootDevices); ++i) { + if ((1<<i) != bootType) continue; + bootDevice = BootDevices[i]; + break; + } + env_set("forUpgrade_flashType", bootDevice); + + //5,forUpgrade_bootloaderCopies, how many copies supported + int bootCopies = 1; + switch (bootType) { + case BOOT_EMMC: bootCopies = 3; break; + default:break; + } + env_set_ulong("forUpgrade_bootloaderCopies", bootCopies); + + //6,forUpgrade_bootloaderIndex + //for emmc, 0/1/2 is user/boot0/boot1 + const int bootCpyIndex = store_bootup_bootidx("bootloader"); + env_set_ulong("forUpgrade_bootloaderIndex", bootCpyIndex); + + //7,get first boot index, for defendkey + const int firstBootCpyIndex = store_boot_copy_start(); + env_set_ulong("forUpgrade_1stBootIndex", firstBootCpyIndex); + + if (printStat) run_command("printenv forUpgrade_socType forUpgrade_secureBoot " + " forUpgrade_robustOta forUpgrade_flashType forUpgrade_bootloaderCopies " + " forUpgrade_bootloaderIndex forUpgrade_1stBootIndex", 0); + + if (saveenv) run_command("saveenv", 0); + + return CMD_RET_SUCCESS; +} + +static void run_recovery_from_flash(void) { + env_set("dolby_status","0"); + run_command("run init_display", 0); + run_command("run storeargs", 0); + run_command("run recovery_from_flash", 0); +} + +static void run_recovery_from_cache(void) { + + char *loadaddr_kernel = env_get("loadaddr_kernel"); + if (loadaddr_kernel != NULL) { + env_set("loadaddr",loadaddr_kernel); + } else { + env_set("loadaddr","0x01080000"); + } + env_set("dolby_status","0"); + run_command("run init_display", 0); + run_command("run storeargs", 0); + run_command("if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;", 0); + run_command("if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; fi;", 0); + + env_set("check_result","recovery_succ"); + run_command("bootm ${loadaddr}", 0); + env_set("check_result","recovery_fail"); + env_set("reboot_status","reboot_recovery"); + run_command("saveenv", 0); + run_command("reboot", 0);//need reboot old bootloader +} + +static void aml_recovery() { + int ret = 0; + char *mode = NULL; + char recovery[768] = {0}; + char command[32]; + char miscbuf[4096] = {0}; + + run_command("get_rebootmode", 0); + + //get reboot_mode + mode = env_get("reboot_mode"); + if (mode == NULL) { + wrnP("can not get reboot mode, so skip recovery check\n"); + } else { + if ((!strcmp(mode, "factory_reset")) || (!strcmp(mode, "update"))) { + env_set("dolby_status","0"); + } + } + + ret = boot_info_open_partition(miscbuf); + if (ret != 0) { + wrnP("open misc partition failed, so skip recovery check"); + return; + } + + char *default_env = env_get("default_env"); + //if factoryreset, need default uboot env + if (default_env != NULL) { + if (strstr(default_env, "1")) { + printf("factory reset, need default all uboot env.\n"); + run_command("env default -a;saveenv;", 0); + return; + } + } + + //if run recovery, need disable dolby + memcpy(command, miscbuf, 32); + if (!memcmp(command, "boot-recovery", strlen("boot-recovery"))) { + env_set("dolby_status","0"); + return; + } +} + +static int do_secureboot_check(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + int code_boot = 0; + int match_flag = 0; + char *rebootstatus = NULL; + char *checkresult = NULL; + char *bootloaderindex = NULL; + char *expect_index = NULL; + char *robustota = NULL; + char *mode = NULL; + + //if recovery mode, need disable dv, if factoryreset, need default uboot env + aml_recovery(); + + //check_result init + checkresult = env_get("check_result"); + if (checkresult == NULL) { + env_set("check_result","succ"); + } + + //reboot_status init + rebootstatus = env_get("reboot_status"); + if (rebootstatus == NULL) { + env_set("reboot_status","reboot_init"); + } + + //no secure check need + if (!strcmp(rebootstatus, "reboot_init")) { + return -1; + } + + //check reboot_end + if (!strcmp(rebootstatus, "reboot_end")) { + env_set("reboot_status","reboot_init"); + run_command("saveenv", 0); + } + + //get reboot_mode + mode = env_get("reboot_mode"); + if (mode == NULL) { + wrnP("can not get reboot mode, so skip secure check\n"); + return -1; + } + + wrnP("secure check reboot_mode:%s\n", mode); + code_boot = strcmp(mode, "cold_boot"); + if (code_boot == 0) { + wrnP("not support code_boot for check\n"); + //env_set("reboot_status","reboot_init"); + //run_command("saveenv", 0); + //return -1; + } + + //get boot status + run_command("amlbootsta -p -s", 0); + + //get forUpgrade_robustOta and check if support robustota + robustota = env_get("forUpgrade_robustOta"); + if ((robustota == NULL) || !strcmp(robustota, "false")) { + return -1; + } + + //get bootloader index + bootloaderindex = env_get("forUpgrade_bootloaderIndex"); + if (bootloaderindex == NULL) { + wrnP("can not get bootloader index, so skip secure check\n"); + return -1; + } + + //get expect index + expect_index = env_get("expect_index"); + if (expect_index == NULL) { + wrnP("can not get expect index, so skip secure check\n"); + return -1; + } + + match_flag = strcmp(bootloaderindex, expect_index); + + //first reboot, command from recovery, need reboot next + if (!strcmp(rebootstatus,"reboot_next")) { + wrnP("--secure check reboot_next---\n"); + //bootloader index, expect == current, no need reboot next + if (match_flag == 0) { + wrnP("current index is expect, no need reboot next, run ceche recovery\n"); + run_recovery_from_cache(); + return 0; + } else { + wrnP("now ready start reboot next\n"); + env_set("reboot_status","reboot_finish"); + run_command("saveenv", 0); + run_command("reboot next", 0); + return 0; + } + } else if (!strcmp(rebootstatus,"reboot_finish")) {//second reboot, reboot next from uboot + wrnP("--secure check reboot_finish---\n"); + env_set("reboot_status","reboot_end"); + run_command("saveenv", 0); + + if (match_flag == 0) { + wrnP("reboot next succ, bootloader secure check pass......\n"); + run_recovery_from_cache(); + return 0; + } else { + //bootloader check failed, run recovery show error + wrnP("reboot next fail, bootloader secure check fail(curr:%s, expect:%s)......\n",bootloaderindex, expect_index); + env_set("check_result","bootloader_fail"); + run_command("saveenv", 0); + run_recovery_from_flash(); + return 0; + } + } else if (!strcmp(rebootstatus,"reboot_recovery")) { + //recovery check failed, run recovery show error + wrnP("--secure check reboot_recovery---\n"); + env_set("reboot_status","reboot_end"); + run_command("saveenv", 0); + run_recovery_from_flash(); + return 0; + } else { + env_set("check_result","succ"); + } + + return 0; +} + + +U_BOOT_CMD_COMPLETE( + amlbootsta, 3, 0, do_get_bootloader_status, + "get bootloader status in env", + "[-p] print bootloader status\n" + "[-s] saveenv after generate bootloader status\n", + var_complete +); + +U_BOOT_CMD_COMPLETE( + amlsecurecheck, 1, 0, do_secureboot_check, + "try bootloader/dtb/recovery secure check", + "" + "", + var_complete +); + +
diff --git a/cmd/amlogic/cmd_avb.c b/cmd/amlogic/cmd_avb.c index df92f4c..adcc1ed 100644 --- a/cmd/amlogic/cmd_avb.c +++ b/cmd/amlogic/cmd_avb.c
@@ -20,11 +20,26 @@ #endif #define AVB_USE_TESTKEY -#define MAX_DTB_SIZE (256 * 1024) +#define MAX_DTB_SIZE (AML_DTB_IMG_MAX_SZ + 512) +#define DTB_PARTITION_SIZE 258048 +#define AVB_NUM_SLOT (4) +#define MAX_AVBKEY_LEN (8 + 1024) -#ifdef AVB_USE_TESTKEY -extern const char testkey2048[520]; -extern const int testkey2048_length; +#define CONFIG_AVB2_KPUB_EMBEDDED +#define CONFIG_AVB2_KPUB_DEFAULT + +#ifdef CONFIG_AVB2_KPUB_VENDOR +/** + * Use of vendor public key automatically disable default public key + */ +#undef CONFIG_AVB2_KPUB_DEFAULT +extern const char avb2_kpub_vendor[]; +extern const int avb2_kpub_vendor_len; +#endif /* CONFIG_AVB_KPUB_VENDOR */ + +#if defined(CONFIG_AVB2_KPUB_DEFAULT) || defined(CONFIG_AVB2_KPUB_DEFAULT_VENDOR) +extern const char avb2_kpub_default[]; +extern const int avb2_kpub_default_len; #endif AvbOps avb_ops_; @@ -41,7 +56,7 @@ return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION; *out_num_read = 0; - if (!memcmp(partition, "dtb", strlen("dtb"))) { + if (!memcmp(partition, "dt", strlen("dt"))) { char *dtb_buf = malloc(MAX_DTB_SIZE); if (!dtb_buf) @@ -83,7 +98,7 @@ if (part_bytes < offset) return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION; - if (!memcmp(partition, "dtb", strlen("dtb"))) { + if (!memcmp(partition, "dt", strlen("dt"))) { if (offset) return AVB_IO_RESULT_ERROR_IO; /* rc = store_dtb_rw((void *)buffer, num_bytes, 1); */ @@ -139,8 +154,8 @@ { int rc = 0; - if (!memcmp(partition, "dtb", strlen("dtb"))) { - *out_size_num_bytes = MAX_DTB_SIZE; + if (!memcmp(partition, "dt", strlen("dt"))) { + *out_size_num_bytes = DTB_PARTITION_SIZE; } else { /* rc = store_get_partititon_size((unsigned char *)partition, out_size_num_bytes); */ rc = store_part_size((unsigned char *)partition); @@ -149,7 +164,6 @@ return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; } *out_size_num_bytes = rc; - *out_size_num_bytes *= 512; } return AVB_IO_RESULT_OK; @@ -159,23 +173,108 @@ size_t public_key_length, const uint8_t* public_key_metadata, size_t public_key_metadata_length, bool* out_is_trusted) { -#ifdef AVB_USE_TESTKEY - printf("Verified using testkey\n"); - if (testkey2048_length != public_key_length) { - *out_is_trusted = false; - return AVB_IO_RESULT_OK; - } - if (!avb_safe_memcmp(public_key_data, testkey2048, testkey2048_length)) - *out_is_trusted = true; - else - *out_is_trusted = false; -#else - unsigned long bl31_addr = get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); - memcpy((void *)bl31_addr, public_key_data, public_key_length); - flush_cache(bl31_addr, public_key_length); - *out_is_trusted = aml_sec_boot_check(AML_D_P_AVB_PUBKEY_VERIFY, - bl31_addr, public_key_length, 0); +#ifdef CONFIG_AVB2_KPUB_FROM_FIP + uint8_t public_key[MAX_AVBKEY_LEN]; + uint32_t ret = 0; #endif + + *out_is_trusted = false; + +#ifdef CONFIG_AVB2_KPUB_FROM_FIP + printf("AVB2 try finding fip kpub\n"); + memset(public_key, 0, MAX_AVBKEY_LEN); + ret = get_avbkey_from_fip(public_key, MAX_AVBKEY_LEN); + if (!ret) { + printf("AVB2 verifying with fip kpub\n"); + if (!avb_safe_memcmp(public_key_data, public_key, public_key_length)) { + *out_is_trusted = true; + return AVB_IO_RESULT_OK; + } else { + *out_is_trusted = false; + return AVB_IO_RESULT_OK; + } + } else { + printf("cannot find fip kpub\n"); + } +#endif + /* fall through here. + * Since AVB2_KPUB_FROM_FIP only works with secureboot enabled + * In order not to break compatiblity, it will fallback to embedded mode + */ +#ifdef CONFIG_AVB2_KPUB_EMBEDDED +/** + * CONFIG_AVB2_KPUB_DEFAULT and CONFIG_AVB2_KPUB_VENDOR should be + * exclusive ideally, however the world is not ideal. + * + * Instead of forbidding it, just print out a warning to let the user + * know this is not something they should be doing unless they really + * know what they are doing. + */ +#if defined(CONFIG_AVB2_KPUB_VENDOR) && defined(CONFIG_AVB2_KPUB_DEFAULT_VENDOR) + #pragma message("Both vendor and default AVB2 public keys are enabled") +#endif /* CONFIG_AVB2_KPUB_VENDOR && CONFIG_AVB2_KPUB_DEFAULT_VENDOR */ + +#if defined(CONFIG_AVB2_KPUB_VENDOR) + printf("AVB2 verify with vendor kpub\n"); + if (avb2_kpub_vendor_len != public_key_length) + *out_is_trusted = false; + else { + if (!avb_safe_memcmp(public_key_data, avb2_kpub_vendor, avb2_kpub_vendor_len)) { + *out_is_trusted = true; + return AVB_IO_RESULT_OK; + } + else + *out_is_trusted = false; + } + +#if 0 + /* for trunk, we need to check default pub key here, because we do not have vendor key in trunk + * but for project, shoule provide vendor pub key, you can replace in board/amlogic/sm1_ac214_v1/avb2_kpub.c + */ + unsigned int isSecure = IS_FEAT_BOOT_VERIFY(); + printf("isSecure: %d\n", isSecure); + if (isSecure == 0) { +#endif +/** + * Allow re-verify with default AVB2 public key if really want to do. + * + * Use of this is *NOT* typical and you should really know what you are + * doing if want to enable this. + */ +#ifdef CONFIG_AVB2_KPUB_DEFAULT_VENDOR + printf("AVB2 re-verify with default kpub\n"); + if (avb2_kpub_default_len != public_key_length) + *out_is_trusted = false; + else { + if (!avb_safe_memcmp(public_key_data, avb2_kpub_default, avb2_kpub_default_len)) { + *out_is_trusted = true; + return AVB_IO_RESULT_OK; + } + else + *out_is_trusted = false; + } +#endif /* CONFIG_AVB2_KPUB_DEFAULT_VENDOR */ +#if 0 + } +#endif +#elif defined(CONFIG_AVB2_KPUB_DEFAULT) + printf("AVB2 verify with default kpub\n"); + if (avb2_kpub_default_len != public_key_length) + *out_is_trusted = false; + else { + if (!avb_safe_memcmp(public_key_data, avb2_kpub_default, avb2_kpub_default_len)) { + *out_is_trusted = true; + return AVB_IO_RESULT_OK; + } + else + *out_is_trusted = false; + } +#else + #error "No AVB2 public key defined" +#endif /* CONFIG_AVB2_KPUB_VENDOR */ + +#endif /* CONFIG_AVB2_KPUB_EMBEDDED */ + return AVB_IO_RESULT_OK; } @@ -289,10 +388,12 @@ int avb_verify(AvbSlotVerifyData** out_data) { - const char * const requested_partitions[5] = {"boot", "recovery", "dtb", NULL}; + const char * requested_partitions_ab[AVB_NUM_SLOT + 1] = {"boot", NULL, NULL, NULL, NULL}; + const char * requested_partitions[AVB_NUM_SLOT + 1] = {"boot", "dt", NULL, NULL, NULL}; AvbSlotVerifyResult result = AVB_SLOT_VERIFY_RESULT_OK; char *s1; char *ab_suffix; + uint32_t i = 0; run_command("get_valid_slot;", 0); s1 = env_get("active_slot"); printf("active_slot is %s\n", s1); @@ -313,7 +414,25 @@ if (is_device_unlocked() || !strcmp(upgradestep, "3")) flags |= AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR; - result = avb_slot_verify(&avb_ops_, requested_partitions, ab_suffix, + if (!strcmp(ab_suffix, "")) { + for (i = 0; i < AVB_NUM_SLOT; i++) { + if (requested_partitions[i] == NULL) { + requested_partitions[i] = "recovery"; + break; + } + } + if (i == AVB_NUM_SLOT) { + printf("ERROR: failed to find an empty slot for recovery"); + return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT; + } + } + + if (!strcmp(ab_suffix, "")) + result = avb_slot_verify(&avb_ops_, requested_partitions, ab_suffix, + flags, + AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, out_data); + else + result = avb_slot_verify(&avb_ops_, requested_partitions_ab, ab_suffix, flags, AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, out_data);
diff --git a/cmd/amlogic/cmd_bcb.c b/cmd/amlogic/cmd_bcb.c index d39660d..a4712e5 100644 --- a/cmd/amlogic/cmd_bcb.c +++ b/cmd/amlogic/cmd_bcb.c
@@ -25,6 +25,9 @@ #define CMD_WIPE_DATA "wipe_data" #define CMD_SYSTEM_CRASH "system_crash" #define CMD_RUN_RECOVERY "boot-recovery" +#define CMD_RESIZE_DATA "resize2fs_data" +#define CMD_FOR_RECOVERY "recovery_" +#define CMD_FASTBOOTD "fastbootd" struct bootloader_message { char command[32]; @@ -68,6 +71,8 @@ char recovery[RECOVERYBUF_SIZE] = {0}; char miscbuf[MISCBUF_SIZE] = {0}; char clearbuf[COMMANDBUF_SIZE+STATUSBUF_SIZE+RECOVERYBUF_SIZE] = {0}; + char* RebootMode; + char* ActiveSlot; if (argc != 2) { return cmd_usage(cmdtp); @@ -98,6 +103,23 @@ memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY)); memcpy(miscbuf+sizeof(command)+sizeof(status), "recovery\n--system_crash", sizeof("recovery\n--system_crash")); store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf); + } else if (!memcmp(command_mark, CMD_RESIZE_DATA, strlen(command_mark))) { + printf("Start to write --resize2fs_data to %s\n", partition); + memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY)); + memcpy(miscbuf+sizeof(command)+sizeof(status), "recovery\n--resize2fs_data", sizeof("recovery\n--resize2fs_data")); + store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf); + } else if (!memcmp(command_mark, CMD_FOR_RECOVERY, strlen(CMD_FOR_RECOVERY))) { + memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY)); + sprintf(recovery, "%s%s", "recovery\n--", command_mark); + memcpy(miscbuf+sizeof(command)+sizeof(status), recovery, strlen(recovery)); + store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf); + return 0; + } else if (!memcmp(command_mark, CMD_FASTBOOTD, strlen(command_mark))) { + printf("write cmd to enter fastbootd \n"); + memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY)); + memcpy(miscbuf+sizeof(command)+sizeof(status), "recovery\n--fastboot", sizeof("recovery\n--fastboot")); + store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf); + return 0; } printf("Start read %s partition datas!\n", partition); @@ -124,6 +146,23 @@ printf("[commannd:%s]\n[status:%s]\n[recovery:%s]\n", command, status, recovery); + run_command("get_rebootmode", 0); + RebootMode = env_get("reboot_mode"); + if (strstr(RebootMode, "quiescent") != NULL) { + printf("quiescent mode.\n"); + run_command("run storeargs", 0); + run_command("setenv bootargs ${bootargs} androidboot.quiescent=1;", 0); + } + + run_command("get_valid_slot", 0); + if (env_get("active_slot")) { + ActiveSlot = env_get("active_slot"); + if (strstr(ActiveSlot, "normal") == NULL) { + printf("ab update mode\n"); + run_command("setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};", 0); + } + } + if (!memcmp(command, CMD_RUN_RECOVERY, strlen(CMD_RUN_RECOVERY))) { if (run_command("run recovery_from_flash", 0) < 0) { printf("run_command for cmd:run recovery_from_flash failed.\n");
diff --git a/cmd/amlogic/cmd_bootctl.c b/cmd/amlogic/cmd_bootctl.c index 1281a8e..74ff178 100644 --- a/cmd/amlogic/cmd_bootctl.c +++ b/cmd/amlogic/cmd_bootctl.c
@@ -296,25 +296,36 @@ if (has_boot_slot == 1) { env_set("active_slot","_a"); env_set("boot_part","boot_a"); + env_set("recovery_part","recovery_a"); env_set("slot-suffixes","0"); } else { env_set("active_slot","normal"); env_set("boot_part","boot"); + env_set("recovery_part","recovery"); + env_set("slot-suffixes","-1"); } } else { if (has_boot_slot == 1) { env_set("active_slot","_b"); env_set("boot_part","boot_b"); + env_set("recovery_part","recovery_b"); env_set("slot-suffixes","1"); } else { env_set("active_slot","normal"); env_set("boot_part","boot"); + env_set("recovery_part","recovery"); + env_set("slot-suffixes","-1"); } } + if (dynamic_partition) + env_set("partiton_mode","dynamic"); + else + env_set("partiton_mode","normal"); + return 0; } @@ -352,12 +363,14 @@ if (strcmp(argv[1], "a") == 0) { env_set("active_slot","_a"); env_set("boot_part","boot_a"); + env_set("recovery_part","recovery_a"); env_set("slot-suffixes","0"); printf("set active slot a \n"); boot_info_set_active_slot(&info, 0); } else if (strcmp(argv[1], "b") == 0) { env_set("active_slot","_b"); env_set("boot_part","boot_b"); + env_set("recovery_part","recovery_b"); env_set("slot-suffixes","1"); printf("set active slot b \n"); boot_info_set_active_slot(&info, 1);
diff --git a/cmd/amlogic/cmd_bootctl_avb.c b/cmd/amlogic/cmd_bootctl_avb.c index b3e8e8c..911b57e 100644 --- a/cmd/amlogic/cmd_bootctl_avb.c +++ b/cmd/amlogic/cmd_bootctl_avb.c
@@ -389,15 +389,32 @@ bootable_a = slot_is_bootable(&(info.slots[0])); bootable_b = slot_is_bootable(&(info.slots[1])); + if (dynamic_partition) + env_set("partiton_mode","dynamic"); + else + env_set("partiton_mode","normal"); + + if (vendor_boot_partition) { + env_set("vendor_boot_mode","true"); + printf("set vendor_boot_mode true\n"); + } + else { + env_set("vendor_boot_mode","false"); + printf("set vendor_boot_mode false\n"); + } + if ((slot == 0) && (bootable_a)) { if (has_boot_slot == 1) { env_set("active_slot","_a"); env_set("boot_part","boot_a"); + env_set("recovery_part","recovery_a"); env_set("slot-suffixes","0"); } else { env_set("active_slot","normal"); env_set("boot_part","boot"); + env_set("recovery_part","recovery"); + env_set("slot-suffixes","-1"); } return 0; } @@ -406,11 +423,14 @@ if (has_boot_slot == 1) { env_set("active_slot","_b"); env_set("boot_part","boot_b"); + env_set("recovery_part","recovery_b"); env_set("slot-suffixes","1"); } else { env_set("active_slot","normal"); env_set("boot_part","boot"); + env_set("recovery_part","recovery"); + env_set("slot-suffixes","-1"); } return 0; } @@ -465,6 +485,7 @@ if (strcmp(argv[1], "a") == 0) { env_set("active_slot","_a"); env_set("boot_part","boot_a"); + env_set("recovery_part","recovery_a"); printf("set active slot a \n"); #ifdef CONFIG_G_AB_SYSTEM env_set("slot-suffixes","a"); @@ -476,6 +497,7 @@ } else if (strcmp(argv[1], "b") == 0) { env_set("active_slot","_b"); env_set("boot_part","boot_b"); + env_set("recovery_part","recovery_b"); printf("set active slot b \n"); #ifdef CONFIG_G_AB_SYSTEM env_set("slot-suffixes","b");
diff --git a/cmd/amlogic/cmd_bootctl_vab.c b/cmd/amlogic/cmd_bootctl_vab.c new file mode 100644 index 0000000..33f2c46 --- /dev/null +++ b/cmd/amlogic/cmd_bootctl_vab.c
@@ -0,0 +1,518 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <malloc.h> +#include <asm/byteorder.h> +#include <config.h> +#include <asm/arch/io.h> +#include <partition_table.h> +#include <libavb.h> +#include <version.h> +#include <amlogic/storage.h> + +#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK + +// Spaces used by misc partition are as below: +// 0 - 2K For bootloader_message +// 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used +// as bootloader_message_ab struct) +// 16K - 32K Used by uncrypt and recovery to store wipe_package for A/B devices +// 32K - 64K System space, used for miscellanious AOSP features. See below. +// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they +// are not configurable without changing all of them. +#define BOOTLOADER_MESSAGE_OFFSET_IN_MISC 0 +#define VENDOR_SPACE_OFFSET_IN_MISC 2 * 1024 +#define WIPE_PACKAGE_OFFSET_IN_MISC 16 * 1024 +#define SYSTEM_SPACE_OFFSET_IN_MISC 32 * 1024 +#define SYSTEM_SPACE_SIZE_IN_MISC 32 * 1024 + + +#define AB_METADATA_MISC_PARTITION_OFFSET 2048 + +#define MISCBUF_SIZE 2080 + +/* Bootloader Message (2-KiB) + * + * This structure describes the content of a block in flash + * that is used for recovery and the bootloader to talk to + * each other. + * + * The command field is updated by linux when it wants to + * reboot into recovery or to update radio or bootloader firmware. + * It is also updated by the bootloader when firmware update + * is complete (to boot into recovery for any final cleanup) + * + * The status field was used by the bootloader after the completion + * of an "update-radio" or "update-hboot" command, which has been + * deprecated since Froyo. + * + * The recovery field is only written by linux and used + * for the system to send a message to recovery or the + * other way around. + * + * The stage field is written by packages which restart themselves + * multiple times, so that the UI can reflect which invocation of the + * package it is. If the value is of the format "#/#" (eg, "1/3"), + * the UI will add a simple indicator of that status. + * + * We used to have slot_suffix field for A/B boot control metadata in + * this struct, which gets unintentionally cleared by recovery or + * uncrypt. Move it into struct bootloader_message_ab to avoid the + * issue. + */ +struct bootloader_message { + char command[32]; + char status[32]; + char recovery[768]; + + // The 'recovery' field used to be 1024 bytes. It has only ever + // been used to store the recovery command line, so 768 bytes + // should be plenty. We carve off the last 256 bytes to store the + // stage string (for multistage packages) and possible future + // expansion. + char stage[32]; + + // The 'reserved' field used to be 224 bytes when it was initially + // carved off from the 1024-byte recovery field. Bump it up to + // 1184-byte so that the entire bootloader_message struct rounds up + // to 2048-byte. + char reserved[1184]; +}; + +/** + * The A/B-specific bootloader message structure (4-KiB). + * + * We separate A/B boot control metadata from the regular bootloader + * message struct and keep it here. Everything that's A/B-specific + * stays after struct bootloader_message, which should be managed by + * the A/B-bootloader or boot control HAL. + * + * The slot_suffix field is used for A/B implementations where the + * bootloader does not set the androidboot.ro.boot.slot_suffix kernel + * commandline parameter. This is used by fs_mgr to mount /system and + * other partitions with the slotselect flag set in fstab. A/B + * implementations are free to use all 32 bytes and may store private + * data past the first NUL-byte in this field. It is encouraged, but + * not mandatory, to use 'struct bootloader_control' described below. + * + * The update_channel field is used to store the Omaha update channel + * if update_engine is compiled with Omaha support. + */ +struct bootloader_message_ab { + struct bootloader_message message; + char slot_suffix[32]; + char update_channel[128]; + + // Round up the entire struct to 4096-byte. + char reserved[1888]; +}; + +#define BOOT_CTRL_MAGIC 0x42414342 /* Bootloader Control AB */ +#define BOOT_CTRL_VERSION 1 + +typedef struct slot_metadata { + // Slot priority with 15 meaning highest priority, 1 lowest + // priority and 0 the slot is unbootable. + uint8_t priority : 4; + // Number of times left attempting to boot this slot. + uint8_t tries_remaining : 3; + // 1 if this slot has booted successfully, 0 otherwise. + uint8_t successful_boot : 1; + // 1 if this slot is corrupted from a dm-verity corruption, 0 + // otherwise. + uint8_t verity_corrupted : 1; + // Reserved for further use. + uint8_t reserved : 7; +}slot_metadata; + +/* Bootloader Control AB + * + * This struct can be used to manage A/B metadata. It is designed to + * be put in the 'slot_suffix' field of the 'bootloader_message' + * structure described above. It is encouraged to use the + * 'bootloader_control' structure to store the A/B metadata, but not + * mandatory. + */ +typedef struct bootloader_control { + // NUL terminated active slot suffix. + char slot_suffix[4]; + // Bootloader Control AB magic number (see BOOT_CTRL_MAGIC). + uint32_t magic; + // Version of struct being used (see BOOT_CTRL_VERSION). + uint8_t version; + // Number of slots being managed. + uint8_t nb_slot : 3; + // Number of times left attempting to boot recovery. + uint8_t recovery_tries_remaining : 3; + // Status of any pending snapshot merge of dynamic partitions. + uint8_t merge_status : 3; + // Ensure 4-bytes alignment for slot_info field. + uint8_t reserved0[1]; + // Per-slot information. Up to 4 slots. + struct slot_metadata slot_info[4]; + // Reserved for further use. + uint8_t reserved1[8]; + // CRC32 of all 28 bytes preceding this field (little endian + // format). + uint32_t crc32_le; +}bootloader_control; + +// Holds Virtual A/B merge status information. Current version is 1. New fields +// must be added to the end. +struct misc_virtual_ab_message { + uint8_t version; + uint32_t magic; + uint8_t merge_status; // IBootControl 1.1, MergeStatus enum. + uint8_t source_slot; // Slot number when merge_status was written. + uint8_t reserved[57]; +}; + +#define MISC_VIRTUAL_AB_MESSAGE_VERSION 2 +#define MISC_VIRTUAL_AB_MAGIC_HEADER 0x56740AB0 + +unsigned int kDefaultBootAttempts = 7; + +bool boot_info_validate(bootloader_control* info) +{ + if (info->magic != BOOT_CTRL_MAGIC) { + printf("Magic 0x%x is incorrect.\n", info->magic); + return false; + } + return true; +} + +void boot_info_reset(bootloader_control* boot_ctrl) +{ + int slot; + memset(boot_ctrl, '\0', sizeof(bootloader_control)); + memcpy(boot_ctrl->slot_suffix, "_a", 2); + boot_ctrl->magic = BOOT_CTRL_MAGIC; + boot_ctrl->version = BOOT_CTRL_VERSION; + boot_ctrl->nb_slot = 1; + + for (slot = 0; slot < 4; ++slot) { + slot_metadata entry = {}; + + if (slot < boot_ctrl->nb_slot) { + entry.priority = 7; + entry.tries_remaining = kDefaultBootAttempts; + entry.successful_boot = 1; + } else { + entry.priority = 0; // Unbootable + entry.tries_remaining = 0; + entry.successful_boot = 0; + } + + boot_ctrl->slot_info[slot] = entry; + } + boot_ctrl->recovery_tries_remaining = 0; +} + +void dump_boot_info(bootloader_control* boot_ctrl) +{ +#if 0 + int slot; + printf("boot_ctrl->slot_suffix = %s\n", boot_ctrl->slot_suffix); + printf("boot_ctrl->magic = 0x%x\n", boot_ctrl->magic); + printf("boot_ctrl->version = %d\n", boot_ctrl->version); + printf("boot_ctrl->nb_slot = %d\n", boot_ctrl->nb_slot); + for (slot = 0; slot < 4; ++slot) { + printf("boot_ctrl->slot_info[%d].priority = %d\n", slot, boot_ctrl->slot_info[slot].priority); + printf("boot_ctrl->slot_info[%d].tries_remaining = %d\n", slot, boot_ctrl->slot_info[slot].tries_remaining); + printf("boot_ctrl->slot_info[%d].successful_boot = %d\n", slot, boot_ctrl->slot_info[slot].successful_boot); + } + printf("boot_ctrl->recovery_tries_remaining = %d\n", boot_ctrl->recovery_tries_remaining); +#endif +} + +static bool slot_is_bootable(slot_metadata* slot) { + return slot->tries_remaining != 0; +} + +int get_active_slot(bootloader_control* info) { + if (info->slot_info[0].priority > info->slot_info[1].priority) { + return 0; + } else if (info->slot_info[0].priority == info->slot_info[1].priority) { + if (info->slot_info[0].successful_boot == 1) + return 0; + else + return 1; + } else { + return 1; + } +} + + +int boot_info_set_active_slot(bootloader_control* bootctrl, int slot) +{ + int i; + // Set every other slot with a lower priority than the new "active" slot. + const unsigned int kActivePriority = 15; + const unsigned int kActiveTries = 6; + for (i = 0; i < bootctrl->nb_slot; ++i) { + if (i != slot) { + if (bootctrl->slot_info[i].priority >= kActivePriority) + bootctrl->slot_info[i].priority = kActivePriority - 1; + } + printf("bootctrl->slot_info[%d].priority = %d\n", i, bootctrl->slot_info[i].priority); + } + + // Note that setting a slot as active doesn't change the successful bit. + // The successful bit will only be changed by setSlotAsUnbootable(). + bootctrl->slot_info[slot].priority = kActivePriority; + bootctrl->slot_info[slot].tries_remaining = kActiveTries; + + printf("bootctrl->slot_info[%d].priority = %d\n", slot, bootctrl->slot_info[slot].priority); + printf("bootctrl->slot_info[%d].tries_remaining = %d\n", slot, bootctrl->slot_info[slot].tries_remaining); + + // Setting the current slot as active is a way to revert the operation that + // set *another* slot as active at the end of an updater. This is commonly + // used to cancel the pending update. We should only reset the verity_corrpted + // bit when attempting a new slot, otherwise the verity bit on the current + // slot would be flip. + if (slot != get_active_slot(bootctrl)) bootctrl->slot_info[slot].verity_corrupted = 0; + + dump_boot_info(bootctrl); + + return 0; +} + +int boot_info_open_partition(char *miscbuf) +{ + char *partition = "misc"; + printf("Start read %s partition datas!\n", partition); + if (store_read((unsigned char *)partition, + 0, MISCBUF_SIZE, (unsigned char *)miscbuf) < 0) { + printf("failed to store read %s.\n", partition); + return -1; + } + return 0; +} + +bool boot_info_load(bootloader_control *out_info, char *miscbuf) +{ + memcpy(out_info, miscbuf+AB_METADATA_MISC_PARTITION_OFFSET, sizeof(bootloader_control)); + dump_boot_info(out_info); + return true; +} + +bool boot_info_save(bootloader_control *info, char *miscbuf) +{ + char *partition = "misc"; + printf("save boot-info \n"); + info->crc32_le = avb_htobe32( + avb_crc32((const uint8_t*)info, sizeof(bootloader_control) - sizeof(uint32_t))); + + memcpy(miscbuf+AB_METADATA_MISC_PARTITION_OFFSET, info, sizeof(bootloader_control)); + dump_boot_info(info); + store_write((unsigned char *)partition, 0, MISCBUF_SIZE, (unsigned char *)miscbuf); + return true; +} + +static int do_GetValidSlot( + cmd_tbl_t * cmdtp, + int flag, + int argc, + char * const argv[]) +{ + char miscbuf[MISCBUF_SIZE] = {0}; + bootloader_control boot_ctrl; + int slot; + bool bootable_a, bootable_b; + + if (argc != 1) { + return cmd_usage(cmdtp); + } + + boot_info_open_partition(miscbuf); + boot_info_load(&boot_ctrl, miscbuf); + + if (!boot_info_validate(&boot_ctrl)) { + printf("boot-info is invalid. Resetting.\n"); + boot_info_reset(&boot_ctrl); + boot_info_save(&boot_ctrl, miscbuf); + } + + slot = get_active_slot(&boot_ctrl); + printf("active slot = %d\n", slot); + + bootable_a = slot_is_bootable(&(boot_ctrl.slot_info[0])); + bootable_b = slot_is_bootable(&(boot_ctrl.slot_info[1])); + + if (dynamic_partition) + env_set("partiton_mode","dynamic"); + else + env_set("partiton_mode","normal"); + + if (vendor_boot_partition) { + env_set("vendor_boot_mode","true"); + printf("set vendor_boot_mode true\n"); + } + else { + env_set("vendor_boot_mode","false"); + printf("set vendor_boot_mode false\n"); + } + + if ((slot == 0) && (bootable_a)) { + if (has_boot_slot == 1) { + env_set("active_slot","_a"); + env_set("boot_part","boot_a"); + env_set("recovery_part","recovery_a"); + env_set("slot-suffixes","0"); + } + else { + env_set("active_slot","normal"); + env_set("boot_part","boot"); + env_set("recovery_part","recovery"); + env_set("slot-suffixes","-1"); + } + return 0; + } + + if ((slot == 1) && (bootable_b)) { + if (has_boot_slot == 1) { + env_set("active_slot","_b"); + env_set("boot_part","boot_b"); + env_set("recovery_part","recovery_b"); + env_set("slot-suffixes","1"); + } + else { + env_set("active_slot","normal"); + env_set("boot_part","boot"); + env_set("recovery_part","recovery"); + env_set("slot-suffixes","-1"); + } + return 0; + } + + return 0; +} + +static int do_SetActiveSlot( + cmd_tbl_t * cmdtp, + int flag, + int argc, + char * const argv[]) +{ + char miscbuf[MISCBUF_SIZE] = {0}; + bootloader_control info; + + if (argc != 2) { + return cmd_usage(cmdtp); + } + + if (has_boot_slot == 0) { + printf("device is not ab mode\n"); + return -1; + } + + boot_info_open_partition(miscbuf); + boot_info_load(&info, miscbuf); + + if (!boot_info_validate(&info)) { + printf("boot-info is invalid. Resetting.\n"); + boot_info_reset(&info); + boot_info_save(&info, miscbuf); + } + + if (strcmp(argv[1], "a") == 0) { + env_set("active_slot","_a"); + env_set("slot-suffixes","0"); + env_set("boot_part","boot_a"); + env_set("recovery_part","recovery_a"); + printf("set active slot a \n"); + boot_info_set_active_slot(&info, 0); + } else if (strcmp(argv[1], "b") == 0) { + env_set("active_slot","_b"); + env_set("slot-suffixes","1"); + env_set("boot_part","boot_b"); + env_set("recovery_part","recovery_b"); + printf("set active slot b \n"); + boot_info_set_active_slot(&info, 1); + } else { + printf("error input slot\n"); + return -1; + } + + boot_info_save(&info, miscbuf); + + return 0; +} + +int do_GetSystemMode (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char* system; +#ifdef CONFIG_SYSTEM_AS_ROOT + system = CONFIG_SYSTEM_AS_ROOT; + strcpy(system, CONFIG_SYSTEM_AS_ROOT); + printf("CONFIG_SYSTEM_AS_ROOT: %s \n", CONFIG_SYSTEM_AS_ROOT); + if (strcmp(system, "systemroot") == 0) { + env_set("system_mode","1"); + } + else { + env_set("system_mode","0"); + } +#else + env_set("system_mode","0"); +#endif + + return 0; +} + +int do_GetAvbMode (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ +#ifdef CONFIG_AVB2 + char* avbmode; + avbmode = CONFIG_AVB2; + strcpy(avbmode, CONFIG_AVB2); + printf("CONFIG_AVB2: %s \n", CONFIG_AVB2); + if (strcmp(avbmode, "avb2") == 0) { + env_set("avb2","1"); + } + else { + env_set("avb2","0"); + } +#else + env_set("avb2","0"); +#endif + + return 0; +} + + +#endif /* CONFIG_BOOTLOADER_CONTROL_BLOCK */ + +U_BOOT_CMD( + get_valid_slot, 2, 0, do_GetValidSlot, + "get_valid_slot", + "\nThis command will choose valid slot to boot up which saved in misc\n" + "partition by mark to decide whether execute command!\n" + "So you can execute command: get_valid_slot" +); + +U_BOOT_CMD( + set_active_slot, 2, 1, do_SetActiveSlot, + "set_active_slot", + "\nThis command will set active slot\n" + "So you can execute command: set_active_slot a" +); + +U_BOOT_CMD( + get_system_as_root_mode, 1, 0, do_GetSystemMode, + "get_system_as_root_mode", + "\nThis command will get system_as_root_mode\n" + "So you can execute command: get_system_as_root_mode" +); + +U_BOOT_CMD( + get_avb_mode, 1, 0, do_GetAvbMode, + "get_avb_mode", + "\nThis command will get avb mode\n" + "So you can execute command: get_avb_mode" +); +
diff --git a/cmd/amlogic/cmd_cvbs.c b/cmd/amlogic/cmd_cvbs.c index ff74dda..b207cd2 100644 --- a/cmd/amlogic/cmd_cvbs.c +++ b/cmd/amlogic/cmd_cvbs.c
@@ -21,12 +21,9 @@ { if ((argc != 2) && (argc != 3) && (argc != 4) && (argc != 5)) { printf("cvbs debug command format as:\n" - " r h/v address\n" - " w value h/v address\n" - " dump h/v addr_start addr_end\n" " enci\n" " clock\n" - " set_clkpath 0/1/2/3\n"); + " clkpath 0/1/2/3\n"); return CMD_RET_FAILURE; } @@ -100,12 +97,9 @@ "cvbs init\n" " init of cvbs\n" "cvbs debug\n" - " r h/v address\n" - " w value h/v address\n" - " dump h/v addr_start addr_end\n" " enci\n" " clock\n" - " set_clkpath 0/1/2/3\n" + " clkpath 0/1/2/3\n" "cvbs output [FORMAT | bist MODE]\n" " FORMAT : [576cvbs|480cvbs|ntsc_m|pal_m|pal_n]\n" " bist mode : [off|1 or colorbar|2 or thinline|3 or dotgrid|0 or fixval]\n"
diff --git a/cmd/amlogic/cmd_ddr_test_g12.c b/cmd/amlogic/cmd_ddr_test_g12.c index 339473d..a747089 100644 --- a/cmd/amlogic/cmd_ddr_test_g12.c +++ b/cmd/amlogic/cmd_ddr_test_g12.c
@@ -1,14 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - #include <common.h> -//#include <u-boot/sha256.h> -//#include <asm/arch/register.h> - -//#include <asm/cpu_id.h> - #define USE_FOR_UBOOT_2018 //#define USE_FOR_UBOOT_2015 @@ -20,227 +10,332 @@ #include <amlogic/cpu_id.h> #endif #ifdef USE_FOR_UBOOT_2015 -//#define DISABLE_ENV -//#define USE_FOR_UBOOT_2018 #include <asm/cpu_id.h> #endif -struct ddr_base_address_table{ - char soc_family_name[16]; - unsigned int chip_id; - unsigned int preg_sticky_reg0; - unsigned int ddr_phy_base_address; - unsigned int ddr_pctl_timing_base_address; - unsigned int ddr_pctl_timing_end_address; - unsigned int ddr_dmc_sticky0; - unsigned int sys_watchdog_base_address; - unsigned int sys_watchdog_enable_value; - unsigned int ddr_pll_base_address; - unsigned int ee_timer_base_address; - unsigned int ee_pwm_base_address; - unsigned int ddr_dmc_apd_address; - unsigned int ddr_dmc_asr_address; +uint32_t do_read_c2_ddr_bdlr_steps(void); +struct ddr_base_address_table { + char soc_family_name[16]; + unsigned int chip_id; + unsigned int preg_sticky_reg0; + unsigned int ddr_phy_base_address; + unsigned int ddr_pctl_timing_base_address; + unsigned int ddr_pctl_timing_end_address; + unsigned int ddr_dmc_sticky0; + unsigned int sys_watchdog_base_address; + unsigned int sys_watchdog_enable_value; + unsigned int ddr_pll_base_address; + unsigned int ee_timer_base_address; + unsigned int ee_pwm_base_address; + unsigned int ddr_dmc_apd_address; + unsigned int ddr_dmc_asr_address; + unsigned int ddr_boot_reason_address; + unsigned int ddr_dmc_lpdd4_retraining_address; + unsigned int ddr_dmc_refresh_ctrl_address; }; typedef struct ddr_base_address_table ddr_base_address_table_t; -#define MESON_CPU_MAJOR_ID_GXBB 0x1F -#define MESON_CPU_MAJOR_ID_GXTVBB 0x20 -#define MESON_CPU_MAJOR_ID_GXLBB 0x21 -#define MESON_CPU_MAJOR_ID_GXM 0x22 -#define MESON_CPU_MAJOR_ID_TXL 0x23 -#define MESON_CPU_MAJOR_ID_TXLX 0x24 -#define MESON_CPU_MAJOR_ID_AXG 0x25 -#define MESON_CPU_MAJOR_ID_GXLX 0x26 -#define MESON_CPU_MAJOR_ID_TXHD 0x27 -#define MESON_CPU_MAJOR_ID_G12A 0x28 -#define MESON_CPU_MAJOR_ID_G12B 0x29 +#define MESON_CPU_MAJOR_ID_GXBB 0x1F +#define MESON_CPU_MAJOR_ID_GXTVBB 0x20 +#define MESON_CPU_MAJOR_ID_GXLBB 0x21 +#define MESON_CPU_MAJOR_ID_GXM 0x22 +#define MESON_CPU_MAJOR_ID_TXL 0x23 +#define MESON_CPU_MAJOR_ID_TXLX 0x24 +#define MESON_CPU_MAJOR_ID_AXG 0x25 +#define MESON_CPU_MAJOR_ID_GXLX 0x26 +#define MESON_CPU_MAJOR_ID_TXHD 0x27 +#define MESON_CPU_MAJOR_ID_G12A 0x28 +#define MESON_CPU_MAJOR_ID_G12B 0x29 -#define MESON_CPU_MAJOR_ID_SM1 0x2B +#define MESON_CPU_MAJOR_ID_SM1 0x2B -#define MESON_CPU_MAJOR_ID_A1 0x2C +#define MESON_CPU_MAJOR_ID_A1 0x2C -#define MESON_CPU_MAJOR_ID_TL1 0x2E -#define MESON_CPU_MAJOR_ID_TM2 0x2F -#define MESON_CPU_MAJOR_ID_C1 0x30 +#define MESON_CPU_MAJOR_ID_TL1 0x2E +#define MESON_CPU_MAJOR_ID_TM2 0x2F +#define MESON_CPU_MAJOR_ID_C1 0x30 +#define MESON_CPU_MAJOR_ID_SC2 0x32 +#define MESON_CPU_MAJOR_ID_C2 0x33 +#define MESON_CPU_MAJOR_ID_T5 0x34 +#define MESON_CPU_MAJOR_ID_T5D 0x35 +#define MESON_CPU_MAJOR_ID_T7 0x36 -#define MESON_CPU_VERSION_LVL_MAJOR 0 -#define MESON_CPU_VERSION_LVL_MINOR 1 -#define MESON_CPU_VERSION_LVL_PACK 2 -#define MESON_CPU_VERSION_LVL_MISC 3 -#define MESON_CPU_VERSION_LVL_MAX MESON_CPU_VERSION_LVL_MISC +#define MESON_CPU_VERSION_LVL_MAJOR 0 +#define MESON_CPU_VERSION_LVL_MINOR 1 +#define MESON_CPU_VERSION_LVL_PACK 2 +#define MESON_CPU_VERSION_LVL_MISC 3 +#define MESON_CPU_VERSION_LVL_MAX MESON_CPU_VERSION_LVL_MISC #define CHIP_ID_MASK 0xff -//#define CHIP_ID_G12A 1 -//#define CHIP_ID_A1 2 -char global_chip_id[12]={0}; +char global_chip_id[12] = { 0 }; #define MESON_CPU_CHIP_ID_SIZE 12 //4 //12byte int ddr_get_chip_id(void) { - int soc_family_id=0; - soc_family_id =get_cpu_id().family_id ; - printf("\nsoc_family_id==0x%08x",soc_family_id); + int soc_family_id = 0; + + soc_family_id = get_cpu_id().family_id; + printf("\nsoc_family_id==0x%08x", soc_family_id); unsigned char chipid[16]; - //unsigned char chipid_inv[12]; - #ifdef GET_CHIP_ID +#ifdef GET_CHIP_ID get_chip_id(chipid, 16); - #endif - int count=0; - for (count=0;count<16;count++ ) - { - if (count>3) - { - global_chip_id[16-1-count]=chipid[count]; - } - //printf("\nchipid[%d]==%08x",count,chipid[count]); +#endif + int count = 0; + + for (count = 0; count < 16; count++) { + if (count > 3) + global_chip_id[16 - 1 - count] = chipid[count]; } - //for(int count=0;count<12;count++ ) - //{ - //printf("\nchipid_inv[%d]==%08x",count,chipid_inv[count]); - //} + return soc_family_id; - //return CHIP_ID_A1; - //return CHIP_ID_G12A; - //return CHIP_ID_MASK; } char CMD_VER[] = "Ver_14"; -ddr_base_address_table_t __ddr_base_address_table[] = { +ddr_base_address_table_t __ddr_base_address_table[] = +{ //g12a { - .soc_family_name="G12A", - .chip_id=MESON_CPU_MAJOR_ID_G12A, - .preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0 - .ddr_phy_base_address=0xfe000000, - .ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400), - .ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400), - .ddr_dmc_sticky0=0xff638800, - .sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000), - .ddr_pll_base_address=((0x0000 << 2) + 0xff638c00), - .ee_timer_base_address=((0x3c62 << 2) + 0xffd00000), - .ee_pwm_base_address=(0xff807000 + (0x001 << 2)), - .ddr_dmc_apd_address=((0x008c << 2) + 0xff638400), - .ddr_dmc_asr_address=((0x008d << 2) + 0xff638400), + .soc_family_name = "G12A", + .chip_id = MESON_CPU_MAJOR_ID_G12A, + .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0 + .ddr_phy_base_address = 0xfe000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400), + .ddr_dmc_sticky0 = 0xff638800, + .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), + .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), + .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000), + .ee_pwm_base_address = (0xff807000 + (0x001 << 2)), + .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400), + .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15 + .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400), }, //g12b { - .soc_family_name="G12B", - .chip_id=MESON_CPU_MAJOR_ID_G12B, - .preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0 - .ddr_phy_base_address=0xfe000000, - .ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400), - .ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400), - .ddr_dmc_sticky0=0xff638800, - .sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000), - .ddr_pll_base_address=((0x0000 << 2) + 0xff638c00), - .ee_timer_base_address=((0x3c62 << 2) + 0xffd00000), - .ee_pwm_base_address=(0xff807000 + (0x001 << 2)), - .ddr_dmc_apd_address=((0x008c << 2) + 0xff638400), - .ddr_dmc_asr_address=((0x008d << 2) + 0xff638400), + .soc_family_name = "G12B", + .chip_id = MESON_CPU_MAJOR_ID_G12B, + .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0 + .ddr_phy_base_address = 0xfe000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400), + .ddr_dmc_sticky0 = 0xff638800, + .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), + .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), + .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000), + .ee_pwm_base_address = (0xff807000 + (0x001 << 2)), + .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400), + .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15 + .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400), }, //tl1 { - .soc_family_name="TL1", - .chip_id=MESON_CPU_MAJOR_ID_TL1, - .preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0 - .ddr_phy_base_address=0xfe000000, - .ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400), - .ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400), - .ddr_dmc_sticky0=0xff638800, - .sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000), - .ddr_pll_base_address=((0x0000 << 2) + 0xff638c00), - .ee_timer_base_address=((0x3c62 << 2) + 0xffd00000), - .ee_pwm_base_address=(0xff807000 + (0x001 << 2)), - .ddr_dmc_apd_address=((0x008c << 2) + 0xff638400), - .ddr_dmc_asr_address=((0x008d << 2) + 0xff638400), + .soc_family_name = "TL1", + .chip_id = MESON_CPU_MAJOR_ID_TL1, + .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0 + .ddr_phy_base_address = 0xfe000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400), + .ddr_dmc_sticky0 = 0xff638800, + .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), + .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), + .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000), + .ee_pwm_base_address = (0xff807000 + (0x001 << 2)), + .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400), + .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15 + .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400), }, //sm1 { - .soc_family_name="SM1", - .chip_id=MESON_CPU_MAJOR_ID_SM1, - .preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0 - .ddr_phy_base_address=0xfe000000, - .ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400), - .ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400), - .ddr_dmc_sticky0=0xff638800, - .sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000), - .ddr_pll_base_address=((0x0000 << 2) + 0xff638c00), - .ee_timer_base_address=((0x3c62 << 2) + 0xffd00000), - .ee_pwm_base_address=(0xff807000 + (0x001 << 2)), - .ddr_dmc_apd_address=((0x008c << 2) + 0xff638400), - .ddr_dmc_asr_address=((0x008d << 2) + 0xff638400), + .soc_family_name = "SM1", + .chip_id = MESON_CPU_MAJOR_ID_SM1, + .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0 + .ddr_phy_base_address = 0xfe000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400), + .ddr_dmc_sticky0 = 0xff638800, + .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), + .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), + .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000), + .ee_pwm_base_address = (0xff807000 + (0x001 << 2)), + .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400), + .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15 + .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400), }, //tm2 { - .soc_family_name="TM2", - .chip_id=MESON_CPU_MAJOR_ID_TM2, - .preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0 - .ddr_phy_base_address=0xfe000000, - .ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400), - .ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400), - .ddr_dmc_sticky0=0xff638800, - .sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000), - .ddr_pll_base_address=((0x0000 << 2) + 0xff638c00), - .ee_timer_base_address=((0x3c62 << 2) + 0xffd00000), - .ee_pwm_base_address=(0xff807000 + (0x001 << 2)), - .ddr_dmc_apd_address=((0x008c << 2) + 0xff638400), - .ddr_dmc_asr_address=((0x008d << 2) + 0xff638400), + .soc_family_name = "TM2", + .chip_id = MESON_CPU_MAJOR_ID_TM2, + .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0 + .ddr_phy_base_address = 0xfe000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400), + .ddr_dmc_sticky0 = 0xff638800, + .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), + .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), + .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000), + .ee_pwm_base_address = (0xff807000 + (0x001 << 2)), + .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400), + .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15 + .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400), }, //a1 { - .soc_family_name="A1", - .chip_id=MESON_CPU_MAJOR_ID_A1, - .preg_sticky_reg0=0xfffff400,//use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0 - .ddr_phy_base_address=0xfc000000, - .ddr_pctl_timing_base_address=((0x0000 << 2) + 0xfd020400), - .ddr_pctl_timing_end_address=((0x00bb << 2) + 0xfd020400), - .ddr_dmc_sticky0=0xfd020800, - .ddr_dmc_apd_address=((0x008c << 2) + 0xfd020400), - .ddr_dmc_asr_address=((0x008d << 2) + 0xfd020400), - .sys_watchdog_base_address=0,//((0x0040 << 2) + 0xfe000000), - .sys_watchdog_enable_value=0x03c401ff, + .soc_family_name = "A1", + .chip_id = MESON_CPU_MAJOR_ID_A1, + .preg_sticky_reg0 = 0xfffff400, //use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0 + .ddr_phy_base_address = 0xfc000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfd020400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfd020400), + .ddr_dmc_sticky0 = 0xfd020800, + .ddr_dmc_apd_address = ((0x008c << 2) + 0xfd020400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xfd020400), + .sys_watchdog_base_address = 0, //((0x0040 << 2) + 0xfe000000), + .sys_watchdog_enable_value = 0x03c401ff, + .ddr_boot_reason_address = ((0x00e1 << 2) + 0xfe005800), //SYSCTRL_SEC_STICKY_REG1 + .ee_timer_base_address = ((0x0041 << 2) + 0xfe005800), }, //c1 { - .soc_family_name="C1", - .chip_id=MESON_CPU_MAJOR_ID_C1, - .preg_sticky_reg0=0xfffff400,//use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0 - .ddr_phy_base_address=0xfd000000, - .ddr_pctl_timing_base_address=((0x0000 << 2) + 0xfe024400), - .ddr_pctl_timing_end_address=((0x00bb << 2) + 0xfe024400), - .ddr_dmc_sticky0=((0x0000 << 2) + 0xfe024800), - .ddr_pll_base_address=((0x0000 << 2) + 0xfe024c00), - .ddr_dmc_apd_address=((0x008c << 2) + 0xfe024400), - .ddr_dmc_asr_address=((0x008d << 2) + 0xfe024400), - .sys_watchdog_base_address=0,//((0x0040 << 2) + 0xfe000000), - .sys_watchdog_enable_value=0x03c401ff, + .soc_family_name = "C1", + .chip_id = MESON_CPU_MAJOR_ID_C1, + .preg_sticky_reg0 = 0xfffff400, //use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0 + .ddr_phy_base_address = 0xfd000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe024400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe024400), + .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xfe024800), + .ddr_pll_base_address = ((0x0000 << 2) + 0xfe024c00), + .ddr_dmc_apd_address = ((0x008c << 2) + 0xfe024400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xfe024400), + .sys_watchdog_base_address = 0, //((0x0040 << 2) + 0xfe000000), + .sys_watchdog_enable_value = 0x03c401ff, + .ddr_boot_reason_address = ((0x00e1 << 2) + 0xfe005800), //SYSCTRL_SEC_STICKY_REG1 + .ee_timer_base_address = ((0x0041 << 2) + 0xfe005800), + }, + //c2 + { + .soc_family_name = "C2", + .chip_id = MESON_CPU_MAJOR_ID_C2, + .preg_sticky_reg0 = ((0x0000 << 2) + 0xfe024800), //use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0 + .ddr_phy_base_address = 0xfd000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe024400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe024400), + .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xfe024800), + .ddr_pll_base_address = ((0x0000 << 2) + 0xfe024c00), + .ddr_dmc_apd_address = ((0x008c << 2) + 0xfe024400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xfe024400), + .sys_watchdog_base_address = 0, //((0x0040 << 2) + 0xfe000000), + .sys_watchdog_enable_value = 0x03c401ff, + .ddr_boot_reason_address = ((0x00e1 << 2) + 0xfe005800), //SYSCTRL_SEC_STICKY_REG1 + .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xfe024400), + .ddr_dmc_refresh_ctrl_address = ((0x0092 << 2) + 0xfe024400), //DMC_DRAM_REFR_CTRL + .ee_timer_base_address = ((0x0041 << 2) + 0xfe005800), + }, + //sc2 + { + .soc_family_name = "SC2", + .chip_id = MESON_CPU_MAJOR_ID_SC2, + .preg_sticky_reg0 = ((0x0000 << 2) + 0xfe036800), // + .ddr_phy_base_address = 0xfc000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe036400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe036400), + .ddr_dmc_sticky0 = 0xfe036800, + .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), //sc2 can not find + .ddr_pll_base_address = ((0x0000 << 2) + 0xfe036c00), + .ee_timer_base_address = ((0x003b << 2) + 0xfe010000), //sc2 can not find + .ee_pwm_base_address = ((0x0001 << 2) + 0xfe05e000), //PWMGH_PWM_B + .ddr_dmc_apd_address = ((0x008c << 2) + 0xfe036400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xfe036400), + .ddr_boot_reason_address = 0xfe036800, //sc2 can not find,SYSCTRL_STICKY_REG0 + }, + //T5 + { + .soc_family_name = "T5", + .chip_id = MESON_CPU_MAJOR_ID_T5, + .preg_sticky_reg0 = ((0x0000 << 2) + 0xff638800), + .ddr_phy_base_address = 0xfe000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400), + .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xff638800), + .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), //AM_DDR_PLL_CNTL0 + .ddr_boot_reason_address = (0xff800000 + (0x003 << 2)), //#define SEC_AO_RTI_STATUS_REG3 + //.ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xfe024400), + + .sys_watchdog_base_address = 0, + .sys_watchdog_enable_value = 0x03c401ff, + .ee_timer_base_address = 0xffd0f188, //#define P_EE_TIMER_E (volatile uint32_t *)0xffd0f188 + .ee_pwm_base_address = ((0x001 << 2) + 0xff807000), //AO_PWM_PWM_B + .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400), + .ddr_dmc_refresh_ctrl_address = ((0x0092 << 2) + 0xff638400), // DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xff638400) + }, + //T5D + { + .soc_family_name = "T5D", + .chip_id = MESON_CPU_MAJOR_ID_T5D, + .preg_sticky_reg0 = ((0x0000 << 2) + 0xff638800), + .ddr_phy_base_address = 0xfe000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400), + .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xff638800), + .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), //AM_DDR_PLL_CNTL0 + .ddr_boot_reason_address = (0xff800000 + (0x003 << 2)), //#define SEC_AO_RTI_STATUS_REG3 + //.ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xfe024400), + + .sys_watchdog_base_address = 0, + .sys_watchdog_enable_value = 0x03c401ff, + .ee_timer_base_address = 0xffd0f188, //#define P_EE_TIMER_E (volatile uint32_t *)0xffd0f188 + .ee_pwm_base_address = ((0x001 << 2) + 0xff807000), //AO_PWM_PWM_B + .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400), + .ddr_dmc_refresh_ctrl_address = ((0x0092 << 2) + 0xff638400), // DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xff638400) + }, + //T7 + { + .soc_family_name = "T7", + .chip_id = MESON_CPU_MAJOR_ID_T7, + .preg_sticky_reg0 = ((0x0000 << 2) + 0xfe036800), // + .ddr_phy_base_address = 0xfc000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe036400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe036400), + .ddr_dmc_sticky0 = ((0x200 << 2) + 0xfe036000), + .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), //sc2 can not find + .ddr_pll_base_address = ((0x0000 << 2) + 0xfe036c00), + .ee_timer_base_address = ((0x003b << 2) + 0xfe010000), //sc2 can not find + .ee_pwm_base_address = ((0x0001 << 2) + 0xfe05e000), //PWMGH_PWM_B + .ddr_dmc_apd_address = ((0x018c << 2) + 0xfe036000), + .ddr_dmc_asr_address = ((0x018d << 2) + 0xfe036000), + .ddr_boot_reason_address = 0xfe036800, //sc2 can not find,SYSCTRL_STICKY_REG0 }, // force id use id mask { - .soc_family_name="UKNOWN", - .chip_id=CHIP_ID_MASK,//MESON_CPU_MAJOR_ID_G12A, - .preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0 - .ddr_phy_base_address=0xfe000000, - .ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400), - .ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400), - .ddr_dmc_sticky0=0xff638800, - .sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000), - .ddr_pll_base_address=((0x0000 << 2) + 0xff638c00), - .ee_timer_base_address=((0x3c62 << 2) + 0xffd00000), - .ee_pwm_base_address=(0xff807000 + (0x001 << 2)), - .ddr_dmc_apd_address=((0x008c << 2) + 0xff638400), - .ddr_dmc_asr_address=((0x008d << 2) + 0xff638400), + .soc_family_name = "UKNOWN", + .chip_id = CHIP_ID_MASK, //MESON_CPU_MAJOR_ID_G12A, + .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0 + .ddr_phy_base_address = 0xfe000000, + .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400), + .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400), + .ddr_dmc_sticky0 = 0xff638800, + .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), + .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), + .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000), + .ee_pwm_base_address = (0xff807000 + (0x001 << 2)), + .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400), + .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400), + .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15 + .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400), }, }; -ddr_base_address_table_t * p_ddr_base={0}; - - +ddr_base_address_table_t *p_ddr_base = { 0 }; #ifdef DISABLE_ENV - int setenv(const char *varname, const char *varvalue) { return 1; @@ -252,175 +347,262 @@ } #endif -#define DWC_AC_PINMUX_TOTAL 28 -#define DWC_DFI_PINMUX_TOTAL 26 -//#define DDR_USE_DEFINE_TEMPLATE_CONFIG 1 -#define DDR_STICKY_MAGIC_NUMBER 0x20180000 -#define DDR_CHIP_ID 0x30 -#define DDR_STICKY_SOURCE_DMC_STICKY 0x1 -#define DDR_STICKY_SOURCE_SRAM 0x2 +#define DWC_AC_PINMUX_TOTAL 28 +#define DWC_DFI_PINMUX_TOTAL 26 -#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config -#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test +#define DDR_STICKY_MAGIC_NUMBER 0x20180000 +#define DDR_CHIP_ID 0x30 +#define DDR_STICKY_SOURCE_DMC_STICKY 0x1 +#define DDR_STICKY_SOURCE_SRAM 0x2 -#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000 -#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000 -#define CONFIG_DDR_TYPE_DDR3 0 -#define CONFIG_DDR_TYPE_DDR4 1 -#define CONFIG_DDR_TYPE_LPDDR4 2 -#define CONFIG_DDR_TYPE_LPDDR3 3 -#define CONFIG_DDR_TYPE_LPDDR2 4 -//#define CONFIG_DDR_TYPE_LPDDR4X 5 -#define CONFIG_DDR_TYPE_AUTO 0xf -#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4 +#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config +#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test -#define CONFIG_DDR0_16BIT_CH0 0x1 -#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 -#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 -#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 -#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 -#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 -#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 -#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 +#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000 +#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000 +#define CONFIG_DDR_TYPE_DDR3 0 +#define CONFIG_DDR_TYPE_DDR4 1 +#define CONFIG_DDR_TYPE_LPDDR4 2 +#define CONFIG_DDR_TYPE_LPDDR3 3 +#define CONFIG_DDR_TYPE_LPDDR2 4 +#define CONFIG_DDR_TYPE_AUTO 0xf +#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4 +#define CONFIG_DDR0_16BIT_CH0 0x1 +#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 +#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 +#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 +#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 +#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 +#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 +#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 +#define DDR_PRINT_DISABLE 0 +#define DDR_PRINT_ENABLE 1 -static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index) +typedef struct board_common_setting { + unsigned int timming_magic; + unsigned short timming_max_valid_configs; + unsigned short timming_struct_version; + unsigned short timming_struct_org_size; + unsigned short timming_struct_real_size; + unsigned char fast_boot[4]; // 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test enable + unsigned int ddr_func; + unsigned char board_id; + unsigned char DramType; + unsigned char dram_rank_config; + unsigned char DisabledDbyte; + unsigned int dram_cs0_base_add; + unsigned int dram_cs1_base_add; + unsigned short dram_cs0_size_MB; + unsigned short dram_cs1_size_MB; + unsigned char dram_x4x8x16_mode; + unsigned char Is2Ttiming; + unsigned char log_level; + unsigned char ddr_rdbi_wr_enable; + unsigned int pll_ssc_mode; + unsigned short org_tdqs2dq; + unsigned char reserve1_test_function[2]; + unsigned int ddr_dmc_remap[5]; + unsigned char ac_pinmux[35]; + unsigned char ddr_dqs_swap; + unsigned char ddr_dq_remap[36]; + unsigned int ddr_vddee_setting[4]; //add,default-value,default-voltage,step +}__attribute__ ((packed)) board_common_setting_t; + +typedef struct board_SI_setting_ps { + unsigned short DRAMFreq; + unsigned char PllBypassEn; + unsigned char training_SequenceCtrl; + unsigned short ddr_odt_config; + unsigned char clk_drv_ohm; + unsigned char cs_drv_ohm; + unsigned char ac_drv_ohm; + unsigned char soc_data_drv_ohm_p; + unsigned char soc_data_drv_ohm_n; + unsigned char soc_data_odt_ohm_p; + unsigned char soc_data_odt_ohm_n; + unsigned char dram_data_drv_ohm; + unsigned char dram_data_odt_ohm; + unsigned char dram_data_wr_odt_ohm; + unsigned char dram_ac_odt_ohm; + unsigned char dram_data_drv_pull_up_calibration_ohm; + unsigned char lpddr4_dram_vout_voltage_range_setting; + unsigned char reserve2; + unsigned short vref_ac_permil; //phy + unsigned short vref_soc_data_permil; //soc + unsigned short vref_dram_data_permil; + unsigned short max_core_timmming_frequency; + unsigned short training_phase_parameter[2]; + unsigned short ac_trace_delay_org[36]; +}__attribute__ ((packed)) board_SI_setting_ps_t; + +typedef struct board_phase_setting_ps { + unsigned short ac_trace_delay[36]; + unsigned short write_dqs_delay[8]; + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[8]; + unsigned char read_dqs_delay[8]; + unsigned char read_dq_bit_delay[72]; + unsigned char soc_bit_vref[44]; + unsigned char dram_bit_vref[36]; + unsigned char reserve_training_parameter[16];//0-7 write dqs offset,8-15 read dqs offset,MSB bit 7 use 0 mean right offset +}__attribute__ ((packed)) board_phase_setting_ps_t; + +typedef struct ddr_set_c2 { + board_common_setting_t cfg_board_common_setting; + board_SI_setting_ps_t cfg_board_SI_setting_ps[2]; + board_phase_setting_ps_t cfg_ddr_training_delay_ps[2]; +}__attribute__ ((packed)) ddr_set_t_c2; + +static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr, uint32_t size, uint32_t offset_index) { - uint32_t read_value=0; - uint32_t addr_t=0; - uint32_t offset=0; - if (size == 8) { - offset=((offset_index%4)<<3); - addr_t=(base_addr+((offset_index>>2) << 2)); - read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t))); - read_value=(read_value>>offset)&0xff; + uint32_t read_value = 0; + uint32_t addr_t = 0; + uint32_t offset = 0; + if (size == 8) { + offset = ((offset_index % 4) << 3); + addr_t = (base_addr + ((offset_index >> 2) << 2)); + read_value = (*(volatile uint32_t *)((unsigned long)(addr_t))); + read_value = (read_value >> offset) & 0xff; } if (size == 16) { - offset=((offset_index%2)<<4); - addr_t=(base_addr+((offset_index>>1) << 2)); - read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t))); - read_value=(read_value>>offset)&0xffff; + offset = ((offset_index % 2) << 4); + addr_t = (base_addr + ((offset_index >> 1) << 2)); + read_value = (*(volatile uint32_t *)((unsigned long)(addr_t))); + read_value = (read_value >> offset) & 0xffff; } return read_value; - } -static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value) + +static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr, uint32_t size, uint32_t offset_index, uint32_t value) { - uint32_t read_value=0; - uint32_t write_value=0; - uint32_t addr_t=0; - uint32_t offset=0; + uint32_t read_value = 0; + uint32_t write_value = 0; + uint32_t addr_t = 0; + uint32_t offset = 0; + if (size == 8) { - offset=((offset_index%4)<<3); - addr_t=(base_addr+((offset_index>>2) << 2)); - read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t))); - write_value=(value<<offset)|(read_value&(~(0xff<<offset))); + offset = ((offset_index % 4) << 3); + addr_t = (base_addr + ((offset_index >> 2) << 2)); + read_value = (*(volatile uint32_t *)((unsigned long)(addr_t))); + write_value = (value << offset) | (read_value & (~(0xff << offset))); } if (size == 16) { - offset=((offset_index%2)<<4); - addr_t=(base_addr+((offset_index>>1) << 2)); - read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t))); - write_value=(value<<offset)|(read_value&(~(0xffff<<offset))); + offset = ((offset_index % 2) << 4); + addr_t = (base_addr + ((offset_index >> 1) << 2)); + read_value = (*(volatile uint32_t *)((unsigned long)(addr_t))); + write_value = (value << offset) | (read_value & (~(0xffff << offset))); } - *(volatile uint32_t *)(( unsigned long )(addr_t))=write_value; + *(volatile uint32_t *)((unsigned long)(addr_t)) = write_value; return write_value; } -typedef struct training_delay_set_ps{ - unsigned char ac_trace_delay[10]; - unsigned char ac_trace_delay_rev[2]; - unsigned char read_dqs_delay[16]; - unsigned char read_dq_bit_delay[72]; - unsigned short write_dqs_delay[16]; -// */ - unsigned short write_dq_bit_delay[72]; - unsigned short read_dqs_gate_delay[16]; - unsigned char soc_bit_vref[36]; - unsigned char dram_bit_vref[32]; - ///* - unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq - unsigned char dfi_mrl; - unsigned char dfi_hwtmrl; - unsigned char ARdPtrInitVal; - unsigned short csr_vrefinglobal; - unsigned short csr_dqsrcvcntrl[4]; - unsigned short csr_pptdqscntinvtrntg0[4]; - unsigned short csr_pptdqscntinvtrntg1[4]; - unsigned short csr_seq0bgpr[9]; - unsigned short csr_dllgainctl; - unsigned short csr_dlllockpara; -// unsigned short rever2; + +uint32_t ddr_min(uint32_t a, uint32_t b) +{ + uint32_t min = a; + + if (a < b) + min = a; + else + min = b; + return min; +} + +uint32_t ddr_max(uint32_t a, uint32_t b) +{ + uint32_t max = a; + + if (a < b) + max = b; + else + max = a; + return max; +} + +typedef struct training_delay_set_ps { + unsigned char ac_trace_delay[10]; + unsigned char ac_trace_delay_rev[2]; + unsigned char read_dqs_delay[16]; + unsigned char read_dq_bit_delay[72]; + unsigned short write_dqs_delay[16]; + unsigned short write_dq_bit_delay[72]; + unsigned short read_dqs_gate_delay[16]; + unsigned char soc_bit_vref[36]; + unsigned char dram_bit_vref[32]; + unsigned char rever1; //read_dqs read_dq,write_dqs, write_dq + unsigned char dfi_mrl; + unsigned char dfi_hwtmrl; + unsigned char ARdPtrInitVal; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; }__attribute__ ((packed)) training_delay_set_ps_t; -typedef struct ddr_phy_common_extra_set{ - unsigned short csr_pllctrl3; - unsigned short csr_pptctlstatic[4]; - unsigned short csr_trainingincdecdtsmen[4]; - unsigned short csr_tsmbyte0[4]; - unsigned short csr_hwtcamode; - unsigned short csr_hwtlpcsena; - unsigned short csr_hwtlpcsenb; - unsigned short csr_acsmctrl13; - unsigned short csr_acsmctrl23; - unsigned char csr_soc_vref_dac1_dfe[36]; + +typedef struct ddr_phy_common_extra_set { + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; }__attribute__ ((packed)) ddr_phy_common_extra_set_t; -typedef struct retraining_set{ - unsigned short csr_pllctrl3; - unsigned short csr_pptctlstatic[4]; - unsigned short csr_trainingincdecdtsmen[4]; - unsigned short csr_tsmbyte0[4]; - unsigned short csr_vrefinglobal; - //unsigned short csr_dfimrl[4]; - unsigned short csr_dqsrcvcntrl[4]; - unsigned short csr_pptdqscntinvtrntg0[4]; - unsigned short csr_pptdqscntinvtrntg1[4]; - unsigned short csr_seq0bgpr[9]; - //unsigned short csr_seq0bgpr2; - //unsigned short csr_seq0bgpr3; - //unsigned short csr_seq0bgpr4; - //unsigned short csr_seq0bgpr5; - //unsigned short csr_seq0bgpr6; - //unsigned short csr_seq0bgpr7; - //unsigned short csr_seq0bgpr8; - unsigned short csr_dllgainctl; - unsigned short csr_dlllockpara; - //unsigned short csr_hwtmrl; - unsigned short csr_hwtcamode; - unsigned short csr_hwtlpcsena; - unsigned short csr_hwtlpcsenb; - unsigned short csr_acsmctrl13; - unsigned short csr_acsmctrl23; - unsigned char csr_soc_vref_dac1_dfe[36]; - //unsigned short rev_41; -} retraining_set_t; -typedef struct ddr_set{ - unsigned int magic; - unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test -// unsigned int rsv_int0; - unsigned int ddr_func; - unsigned char board_id; +typedef struct retraining_set { + unsigned short csr_pllctrl3; + unsigned short csr_pptctlstatic[4]; + unsigned short csr_trainingincdecdtsmen[4]; + unsigned short csr_tsmbyte0[4]; + unsigned short csr_vrefinglobal; + unsigned short csr_dqsrcvcntrl[4]; + unsigned short csr_pptdqscntinvtrntg0[4]; + unsigned short csr_pptdqscntinvtrntg1[4]; + unsigned short csr_seq0bgpr[9]; + unsigned short csr_dllgainctl; + unsigned short csr_dlllockpara; + unsigned short csr_hwtcamode; + unsigned short csr_hwtlpcsena; + unsigned short csr_hwtlpcsenb; + unsigned short csr_acsmctrl13; + unsigned short csr_acsmctrl23; + unsigned char csr_soc_vref_dac1_dfe[36]; +}retraining_set_t; + +typedef struct ddr_set { + unsigned int magic; + unsigned char fast_boot[4]; // 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test + unsigned int ddr_func; + unsigned char board_id; //board id reserve,,do not modify - unsigned char version; + unsigned char version; // firmware reserve version,,do not modify - unsigned char DramType; + unsigned char DramType; //support DramType should confirm with amlogic //#define CONFIG_DDR_TYPE_DDR3 0 //#define CONFIG_DDR_TYPE_DDR4 1 //#define CONFIG_DDR_TYPE_LPDDR4 2 //#define CONFIG_DDR_TYPE_LPDDR3 3 //#define CONFIG_DDR_TYPE_LPDDR2 4 - unsigned char DisabledDbyte; + unsigned char DisabledDbyte; //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3 //bit 0 ---use byte 0 ,1 disable byte 0, //bit 1 ---use byte 1 ,1 disable byte 1, //bit 2 ---use byte 2 ,1 disable byte 2, //bit 3 ---use byte 3 ,1 disable byte 3, - unsigned char Is2Ttiming; + unsigned char Is2Ttiming; //ddr3/ddr3 use 2t timing,now only support 2t timming - unsigned char HdtCtrl; + unsigned char HdtCtrl; //training information control,do not modify - unsigned char dram_rank_config; + unsigned char dram_rank_config; //support Dram connection type should confirm with amlogic //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0 //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1 @@ -432,45 +614,37 @@ //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0 /* rsv_char0. update for diagnose type define */ - unsigned char diagnose; + unsigned char diagnose; - unsigned short soc_data_drv_ohm_ps1; - unsigned short dram_data_drv_ohm_ps1; - unsigned short soc_data_odt_ohm_ps1; - unsigned short dram_data_odt_ohm_ps1; - unsigned short dram_data_wr_odt_ohm_ps1; - #if 0 - /* imem/dmem define */ - unsigned int imem_load_addr; + unsigned short soc_data_drv_ohm_ps1; + unsigned short dram_data_drv_ohm_ps1; + unsigned short soc_data_odt_ohm_ps1; + unsigned short dram_data_odt_ohm_ps1; + unsigned short dram_data_wr_odt_ohm_ps1; //system reserve,do not modify - unsigned int dmem_load_addr; + unsigned short dmem_load_size; //system reserve,do not modify - unsigned short imem_load_size; - #endif + unsigned int ddr_base_addr; //system reserve,do not modify - unsigned short dmem_load_size; - //system reserve,do not modify - unsigned int ddr_base_addr; - //system reserve,do not modify - unsigned int ddr_start_offset; + unsigned int ddr_start_offset; //system reserve,do not modify - unsigned short dram_cs0_size_MB; + unsigned short dram_cs0_size_MB; //config cs0 dram size ,like 1G DRAM ,setting 1024 - unsigned short dram_cs1_size_MB; + unsigned short dram_cs1_size_MB; //config cs1 dram size,like 512M DRAM ,setting 512 /* align8 */ - unsigned short training_SequenceCtrl[2]; + unsigned short training_SequenceCtrl[2]; //system reserve,do not modify - unsigned char phy_odt_config_rank[2]; + unsigned char phy_odt_config_rank[2]; //unsigned char rever1; //unsigned char rever2; - unsigned short rank1_ca_vref_permil; + unsigned short rank1_ca_vref_permil; //training odt config ,only use for training // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT - unsigned int dfi_odt_config; + unsigned int dfi_odt_config; //normal go status od config,use for normal status //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity. //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1. @@ -482,13 +656,13 @@ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1. //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0. //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1. - unsigned short DRAMFreq[4]; + unsigned short DRAMFreq[4]; //config dram frequency,use DRAMFreq[0],ohter reserve - unsigned char PllBypassEn; + unsigned char PllBypassEn; //system reserve,do not modify - unsigned char ddr_rdbi_wr_enable; + unsigned char ddr_rdbi_wr_enable; //system reserve,do not modify - unsigned char ddr_rfc_type; + unsigned char ddr_rfc_type; //config dram rfc type,according dram type,also can use same dram type max config //#define DDR_RFC_TYPE_DDR3_512Mbx1 0 //#define DDR_RFC_TYPE_DDR3_512Mbx2 1 @@ -502,12 +676,11 @@ //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9 //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10 //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11 - unsigned char enable_lpddr4x_mode; + unsigned char enable_lpddr4x_mode; //system reserve,do not modify /* align8 */ - unsigned int pll_ssc_mode; - // + unsigned int pll_ssc_mode; /* pll ssc config: * * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode], @@ -520,121 +693,119 @@ * 2. config 3000ppm down ss. then mode=2, strength=6 * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2, */ - unsigned short clk_drv_ohm; + unsigned short clk_drv_ohm; //config soc clk pin signal driver stength ,select 20,30,40,60ohm - unsigned short cs_drv_ohm; + unsigned short cs_drv_ohm; //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm - unsigned short ac_drv_ohm; + unsigned short ac_drv_ohm; //config soc normal address command pin driver stength ,select 20,30,40,60ohm - unsigned short soc_data_drv_ohm_p; + unsigned short soc_data_drv_ohm_p; //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm - unsigned short soc_data_drv_ohm_n; + unsigned short soc_data_drv_ohm_n; //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm - unsigned short soc_data_odt_ohm_p; + unsigned short soc_data_odt_ohm_p; //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm - unsigned short soc_data_odt_ohm_n; + unsigned short soc_data_odt_ohm_n; //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm - unsigned short dram_data_drv_ohm; + unsigned short dram_data_drv_ohm; //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm - unsigned short dram_data_odt_ohm; + unsigned short dram_data_odt_ohm; //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm - unsigned short dram_ac_odt_ohm; + unsigned short dram_ac_odt_ohm; //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm - unsigned short soc_clk_slew_rate; + unsigned short soc_clk_slew_rate; //system reserve,do not modify - unsigned short soc_cs_slew_rate; + unsigned short soc_cs_slew_rate; //system reserve,do not modify - unsigned short soc_ac_slew_rate; + unsigned short soc_ac_slew_rate; //system reserve,do not modify - unsigned short soc_data_slew_rate; + unsigned short soc_data_slew_rate; //system reserve,do not modify - unsigned short vref_output_permil; //phy + unsigned short vref_output_permil; //phy //setting same with vref_dram_permil - unsigned short vref_receiver_permil; //soc + unsigned short vref_receiver_permil; //soc //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI - unsigned short vref_dram_permil; + unsigned short vref_dram_permil; //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI - unsigned short max_core_timmming_frequency; + unsigned short max_core_timmming_frequency; //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register /* align8 */ - unsigned char ac_trace_delay[10]; - unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; - unsigned char lpddr4_x8_mode; - unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function + unsigned char ac_trace_delay[10]; + unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting; + unsigned char lpddr4_x8_mode; + unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function //[1],slt test parameter ,use for force delay line offset //system reserve,do not modify - unsigned short tdqs2dq; - unsigned char dram_data_wr_odt_ohm; - unsigned char bitTimeControl_2d; + unsigned short tdqs2dq; + unsigned char dram_data_wr_odt_ohm; + unsigned char bitTimeControl_2d; //system reserve,do not modify /* align8 */ - unsigned char char_rev1; - unsigned char char_rev2; - unsigned int ddr_dmc_remap[5]; - unsigned int dram_rtt_nom_wr_park[2]; + unsigned char char_rev1; + unsigned char char_rev2; + unsigned int ddr_dmc_remap[5]; + unsigned int dram_rtt_nom_wr_park[2]; //system reserve,do not modify /* align8 */ - unsigned char ddr_lpddr34_ca_remap[4]; + unsigned char ddr_lpddr34_ca_remap[4]; ////use for lpddr3 /lpddr4 ca training data byte lane remap - unsigned char ddr_lpddr34_dq_remap[32]; + unsigned char ddr_lpddr34_dq_remap[32]; ////use for lpddr3 /lpddr4 ca pinmux remap - unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; + unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL]; //use for lpddr3 /lpddr4 ca pinmux remap - unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; - unsigned char char_rev3; - unsigned char char_rev4; - ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; - training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; - - //override read bit delay + unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL]; + unsigned char char_rev3; + unsigned char char_rev4; + ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t; + training_delay_set_ps_t cfg_ddr_training_delay_ps[2]; }ddr_set_t; ddr_set_t p_ddr_set_t; -#ifndef _SHA256_H -#define _SHA256_H +#ifndef _SHA256_H_DDR +#define _SHA256_H_DDR -#define SHA256_SUM_LEN 32 -#define SHA256_DER_LEN 19 +#define SHA256_SUM_LEN 32 +#define SHA256_DER_LEN 19 -//extern const uint8_t sha256_der_prefix[]; /* Reset watchdog each time we process this many bytes */ -#define CHUNKSZ_SHA256 (64 * 1024) +#define CHUNKSZ_SHA256 (64 * 1024) typedef struct { - uint32_t total[2]; - uint32_t state[8]; - uint8_t buffer[64]; -} sha256_context; + uint32_t total[2]; + uint32_t state[8]; + uint8_t buffer[64]; +} sha256_context_ddr; -const uint8_t sha256_der_prefix_ddr[SHA256_DER_LEN] = { +const uint8_t sha256_der_prefix_ddr[SHA256_DER_LEN] = +{ 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 }; /* -* 32-bit integer manipulation macros (big endian) -*/ + * 32-bit integer manipulation macros (big endian) + */ #ifndef GET_UINT32_BE -#define GET_UINT32_BE(n,b,i) { \ - (n) = ( (unsigned long) (b)[(i) ] << 24 ) \ - | ( (unsigned long) (b)[(i) + 1] << 16 ) \ - | ( (unsigned long) (b)[(i) + 2] << 8 ) \ - | ( (unsigned long) (b)[(i) + 3] ); \ +#define GET_UINT32_BE(n, b, i) { \ + (n) = ((unsigned long)(b)[(i)] << 24) \ + | ((unsigned long)(b)[(i) + 1] << 16) \ + | ((unsigned long)(b)[(i) + 2] << 8) \ + | ((unsigned long)(b)[(i) + 3]); \ } #endif #ifndef PUT_UINT32_BE -#define PUT_UINT32_BE(n,b,i) { \ - (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ - (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ - (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ - (b)[(i) + 3] = (unsigned char) ( (n) ); \ +#define PUT_UINT32_BE(n, b, i) { \ + (b)[(i)] = (unsigned char)((n) >> 24); \ + (b)[(i) + 1] = (unsigned char)((n) >> 16); \ + (b)[(i) + 2] = (unsigned char)((n) >> 8); \ + (b)[(i) + 3] = (unsigned char)((n)); \ } #endif -void sha256_starts_internal(sha256_context * ctx) +void sha256_starts_internal(sha256_context_ddr *ctx) { ctx->total[0] = 0; ctx->total[1] = 0; @@ -649,7 +820,7 @@ ctx->state[7] = 0x5BE0CD19; } -static void sha256_process_internal(sha256_context *ctx, const uint8_t data[64]) +static void sha256_process_internal(sha256_context_ddr *ctx, const uint8_t data[64]) { uint32_t temp1, temp2; uint32_t W[64]; @@ -672,28 +843,28 @@ GET_UINT32_BE(W[14], data, 56); GET_UINT32_BE(W[15], data, 60); -#define SHR(x,n) ((x & 0xFFFFFFFF) >> n) -#define ROTR(x,n) (SHR(x,n) | (x << (32 - n))) +#define SHR(x, n) ((x & 0xFFFFFFFF) >> n) +#define ROTR(x, n) (SHR(x, n) | (x << (32 - n))) -#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3)) -#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10)) +#define S0(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3)) +#define S1(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHR(x, 10)) -#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22)) -#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25)) +#define S2(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) +#define S3(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)) -#define F0(x,y,z) ((x & y) | (z & (x | y))) -#define F1(x,y,z) (z ^ (x & (y ^ z))) +#define F0(x, y, z) ((x & y) | (z & (x | y))) +#define F1(x, y, z) (z ^ (x & (y ^ z))) #define R(t) \ -( \ - W[t] = S1(W[t - 2]) + W[t - 7] + \ - S0(W[t - 15]) + W[t - 16] \ -) + ( \ + W[t] = S1(W[t - 2]) + W[t - 7] + \ + S0(W[t - 15]) + W[t - 16] \ + ) -#define P(a,b,c,d,e,f,g,h,x,K) { \ - temp1 = h + S3(e) + F1(e,f,g) + K + x; \ - temp2 = S2(a) + F0(a,b,c); \ - d += temp1; h = temp1 + temp2; \ +#define P(a, b, c, d, e, f, g, h, x, K) { \ + temp1 = h + S3(e) + F1(e, f, g) + K + x; \ + temp2 = S2(a) + F0(a, b, c); \ + d += temp1; h = temp1 + temp2; \ } A = ctx->state[0]; @@ -780,7 +951,7 @@ ctx->state[7] += H; } -void sha256_update_internal(sha256_context *ctx, const uint8_t *input, uint32_t length) +void sha256_update_internal(sha256_context_ddr *ctx, const uint8_t *input, uint32_t length) { uint32_t left, fill; @@ -797,7 +968,7 @@ ctx->total[1]++; if (left && length >= fill) { - memcpy((void *) (ctx->buffer + left), (void *) input, fill); + memcpy((void *)(ctx->buffer + left), (void *)input, fill); sha256_process_internal(ctx, ctx->buffer); length -= fill; input += fill; @@ -811,17 +982,18 @@ } if (length) - memcpy((void *) (ctx->buffer + left), (void *) input, length); + memcpy((void *)(ctx->buffer + left), (void *)input, length); } -static uint8_t sha256_padding[64] = { +static uint8_t sha256_padding[64] = +{ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -void sha256_finish_internal(sha256_context * ctx, uint8_t digest[32]) +void sha256_finish_internal(sha256_context_ddr *ctx, uint8_t digest[32]) { uint32_t last, padn; uint32_t high, low; @@ -851,198 +1023,159 @@ } /* -* Output = SHA-256( input buffer ). Trigger the watchdog every 'chunk_sz' -* bytes of input processed. -*/ + * Output = SHA-256( input buffer ). Trigger the watchdog every 'chunk_sz' + * bytes of input processed. + */ void sha256_csum_wd_internal(const unsigned char *input, unsigned int ilen, - unsigned char *output, unsigned int chunk_sz) + unsigned char *output, unsigned int chunk_sz) { -#if 0 - int count=0; - for ( count=0;count<ilen;count++) - { - printf("\ninput %08x,p+%08x,%08x",(unsigned int)(unsigned long)(input+count),count,*(input+count)); - } -#endif - sha256_context ctx; + sha256_context_ddr ctx; + sha256_starts_internal(&ctx); sha256_update_internal(&ctx, input, ilen); sha256_finish_internal(&ctx, output); -#if 0 - for ( count=0;count<32;count++) - { - printf("\noutput %08x,p+%08x,%08x",(unsigned int)(unsigned long)(output+count),count,*(output+count)); - } -#endif } - #endif typedef struct ddr_sha_s { - unsigned char sha2[SHA256_SUM_LEN]; - ddr_set_t ddrs; - unsigned char sha_chip_id[MESON_CPU_CHIP_ID_SIZE]; -} ddr_sha_t; + unsigned char sha2[SHA256_SUM_LEN]; + ddr_set_t ddrs; + unsigned char sha_chip_id[MESON_CPU_CHIP_ID_SIZE]; +}ddr_sha_t; -ddr_sha_t ddr_sha = {{0}}; +ddr_sha_t ddr_sha = { { 0 } }; ddr_set_t *ddr_set_t_p_arrary = &ddr_sha.ddrs; +typedef struct ddr_sha_s_c2 { + unsigned char sha2[SHA256_SUM_LEN]; + ddr_set_t_c2 ddrs; + unsigned char sha_chip_id[MESON_CPU_CHIP_ID_SIZE]; +}ddr_sha_t_c2; + +ddr_sha_t_c2 ddr_sha_c2 = { { 0 } }; +ddr_set_t_c2 *ddr_set_t_p_arrary_c2 = &ddr_sha_c2.ddrs; +ddr_set_t_c2 *ddr_set_t_p = NULL; + int check_base_address(void) { - unsigned int table_max=(sizeof(__ddr_base_address_table))/(sizeof(ddr_base_address_table_t)); - unsigned int table_index=0; - char chip_id=0; - chip_id=ddr_get_chip_id(); - p_ddr_base=(ddr_base_address_table_t *)(&__ddr_base_address_table); + ddr_set_t_p = (ddr_set_t_c2 *)(ddr_set_t_p_arrary_c2); + unsigned int table_max = (sizeof(__ddr_base_address_table)) / (sizeof(ddr_base_address_table_t)); + unsigned int table_index = 0; + char chip_id = 0; + chip_id = ddr_get_chip_id(); + p_ddr_base = (ddr_base_address_table_t *)(&__ddr_base_address_table); - printf("\ntable_max=%08x,p_ddr_base_add=%08x,chip_id=%08x",table_max,(unsigned int)( unsigned long )p_ddr_base,chip_id); + printf("\ntable_max=%08x,p_ddr_base_add=%08x,chip_id=%08x", table_max, (unsigned int)(unsigned long)p_ddr_base, chip_id); if (chip_id == 0) - { - chip_id=CHIP_ID_MASK; - } - if (chip_id) - { - for (table_index=0;table_index<table_max;table_index++) - {//p_ddr_base=(p_ddr_base+1); + chip_id = CHIP_ID_MASK; + if (chip_id) { + for (table_index = 0; table_index < table_max; table_index++) { //p_ddr_base=(p_ddr_base+1); printf("\ntable_index=%08x,p_ddr_base_add=%08x,(p_ddr_base->chip_id==%08x", - table_index,(unsigned int)( unsigned long )p_ddr_base,(p_ddr_base->chip_id)); - if ((p_ddr_base->chip_id == chip_id) && (chip_id<CHIP_ID_MASK)) - { - printf("\nfind match chip id=0x%08x ,%s",chip_id,p_ddr_base->soc_family_name); + table_index, (unsigned int)(unsigned long)p_ddr_base, (p_ddr_base->chip_id)); + if ((p_ddr_base->chip_id == chip_id) && (chip_id < CHIP_ID_MASK)) { + printf("\nfind match chip id=0x%08x ,%s", chip_id, p_ddr_base->soc_family_name); break; + } else { + printf("\nno find match chip id=0x%08x, ,%s will use default value", chip_id, p_ddr_base->soc_family_name); } - else - { - printf("\nno find match chip id=0x%08x, ,%s will use default value",chip_id,p_ddr_base->soc_family_name); - } - p_ddr_base=(p_ddr_base+1); + p_ddr_base = (p_ddr_base + 1); } } - int count=0; - for (count = 0; count <12; count++) { - ddr_sha.sha_chip_id[count]=global_chip_id[count]; - } + int count = 0; + for (count = 0; count < 12; count++) + ddr_sha.sha_chip_id[count] = global_chip_id[count]; - return (unsigned int)( unsigned long )(p_ddr_base); + return (unsigned int)(unsigned long)(p_ddr_base); } -char* itoa_ddr_test(int num,char*str,int radix) -{/*Ë÷Òý±í*/ +char *itoa_ddr_test(int num, char *str, int radix) +{ printf("\nitoa_ddr_test 1\n"); - char index[]="0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; - unsigned unum;/*Öмä±äÁ¿*/ + char index[] = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + unsigned unum; char temp; - int i=0,j,k; - /*È·¶¨unumµÄÖµ*/ - if (radix == 10 && num<0) /*Ê®½øÖƸºÊý*/ - { + int i = 0, j, k; + + if (radix == 10 && num < 0) { unum = (unsigned)-num; str[i++] = '-'; + } else { + unum = (unsigned)num; } - else - unum = (unsigned)num;/*ÆäËûÇé¿ö*/ - /*ת»»*/ + printf("\nitoa_ddr_test 2\n"); - printf("\nunum=0x%08x\n",unum); - printf("\nunum2=0x%08x\n",(unum%(unsigned)radix)); - printf("\nradix=0x%08x\n",radix); + printf("\nunum=0x%08x\n", unum); + printf("\nunum2=0x%08x\n", (unum % (unsigned)radix)); + printf("\nradix=0x%08x\n", radix); str[0] = index[0]; printf("\nitoa_ddr_test 22\n"); unum /= radix; printf("\nitoa_ddr_test 23\n"); do { - str[i++] = index[unum%(unsigned)radix]; + str[i++] = index[unum % (unsigned)radix]; unum /= radix; - }while(unum); + } while (unum); printf("\nitoa_ddr_test 3\n"); str[i] = '\0'; - /*ÄæÐò*/ + if (str[0] == '-') - k = 1;/*Ê®½øÖƸºÊý*/ + k = 1; else k = 0; printf("\nitoa_ddr_test 4\n"); - for (j = k;j <= (i-1)/2;j++) - { + for (j = k; j <= (i - 1) / 2; j++) { temp = str[j]; - str[j] = str[i-1+k-j]; - str[i-1+k-j] = temp; + str[j] = str[i - 1 + k - j]; + str[i - 1 + k - j] = temp; } return str; } -//#endif -/* -char *strsep(char **stringp, const char *delim) -{ -char *s; -const char *spanp; -int c, sc; -char *tok; -if ((s = *stringp)== NULL) -return (NULL); -for (tok = s;;) { -c = *s++; -spanp = delim; -do { -if ((sc =*spanp++) == c) { -if (c == 0) -s = NULL; -else -s[-1] = 0; -*stringp = s; -return (tok); -} -} while (sc != 0); -} - -} -*/ int TOLOWER(int ch) { - if ((unsigned int)(ch - 'A') < 26u ) + if ((unsigned int)(ch - 'A') < 26u) ch += 'a' - 'A'; return ch; -}//´óд×Öĸת»»ÎªÐ¡Ð´×Öĸ¡£ +} int isxdigit(int ch) { - return (unsigned int)( ch - '0') < 10u || - (unsigned int)((ch | 0x20) - 'a') < 6u; -}//ÅжÏ×Ö·ûcÊÇ·ñΪʮÁù½øÖÆÊý×Ö¡£ -//µ±cΪA-F,a-f»ò0-9Ö®¼äµÄÊ®Áù½øÖÆÊý×Öʱ£¬·µ»Ø·ÇÁãÖµ£¬·ñÔò·µ»ØÁã¡£ + return (unsigned int)(ch - '0') < 10u + || (unsigned int)((ch | 0x20) - 'a') < 6u; +} + int isdigit(int ch) { return (unsigned int)(ch - '0') < 10u; -}//ÅжÏ×Ö·ûcÊÇ·ñΪÊý×Ö +} + unsigned int simple_guess_base(const char *cp) { if (cp[0] == '0') { if (TOLOWER(cp[1]) == 'x' && isxdigit(cp[2])) return 16; else - // return 8; return 10; } else { return 10; } } + unsigned int simple_strtoull_ddr(const char *cp, char **endp, unsigned int base) { - unsigned int result = 0; - //printf("test sizeof(str_buf)==%d\n",1); + unsigned int result = 0; + if (cp == NULL) //jiaxing add 20170616 return 0; if (!base) base = simple_guess_base(cp); if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x') cp += 2; - if (base == 10) { - while ((*cp)== '0') + if (base == 10) + while ((*cp) == '0') cp++; - } - while (isxdigit(*cp)) {//¼ì²éµ±Ç°cpÊÇ·ñÊǸöÊ®Áù½øÖÆÊýÖµ£¬²»ÊÇÖ±½Ó·µ»Ø0 + while (isxdigit(*cp)) { unsigned int value; value = isdigit(*cp) ? *cp - '0' : TOLOWER(*cp) - 'a' + 10; if (value >= base) @@ -1054,348 +1187,347 @@ *endp = (char *)cp; return result; } + unsigned int env_to_a_num(const char *env_name) { char *str_buf = NULL; char buf[48]; + str_buf = (char *)(&buf); memset(str_buf, 0, sizeof(buf)); - printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf))); + printf("sizeof(str_buf)==%d\n", (unsigned int)(sizeof(buf))); str_buf = getenv(env_name); unsigned int a_num = 0; char *endp; - printf("str==%s\n",str_buf); + printf("str==%s\n", str_buf); - a_num=simple_strtoull_ddr(str_buf, &endp, 0); - printf("%s==0x%08x\n",str_buf,a_num); + a_num = simple_strtoull_ddr(str_buf, &endp, 0); + printf("%s==0x%08x\n", str_buf, a_num); return a_num; } -unsigned int a_num_to_env(const char *env_name ,unsigned int *a_num) + +unsigned int a_num_to_env(const char *env_name, unsigned int *a_num) { - char *str_buf=NULL; + char *str_buf = NULL; char buf[1024]; - //unsigned int str_to_numarry[48]; - //str_buf = (char *)malloc(sizeof(char)*1024); + str_buf = (char *)(&buf); memset(str_buf, 0, sizeof(buf)); - printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf))); + printf("sizeof(str_buf)==%d\n", (unsigned int)(sizeof(buf))); str_buf = getenv(env_name); - printf("str==%s\n",str_buf); + printf("str==%s\n", str_buf); sprintf(buf, "0x%08x", *a_num); - printf( "%s==0x%08x", buf,*a_num); + printf("%s==0x%08x", buf, *a_num); setenv(env_name, buf); - run_command("save",0); + run_command("save", 0); return 1; } -unsigned int env_to_num(const char *env_name,unsigned int *num_arry) + +unsigned int env_to_num(const char *env_name, unsigned int *num_arry) { char *str_buf = NULL; char buf[1024]; unsigned int str_to_numarry[48]; - //str_buf = (char *)malloc(sizeof(char)*1024); + str_buf = (char *)(&buf); memset(str_buf, 0, sizeof(buf)); - printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf))); + printf("sizeof(str_buf)==%d\n", (unsigned int)(sizeof(buf))); str_buf = getenv(env_name); - char * str[48]; + char *str[48]; char *endp; int i; for (i = 0; i < 48; i++) str_to_numarry[i] = 0; - printf("str==%s\n",str_buf); + printf("str==%s\n", str_buf); for (i = 0; i < 48; i++) { str[i] = strsep(&str_buf, ";"); - //str[i] = strsep(&str_buf, " "); if (str[i] == NULL) break; str_to_numarry[i] = simple_strtoull_ddr(str[i], &endp, 0); - //printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]); - //num_arry[i]=str_to_numarry[i]; } for (i = 0; i < 48; i++) { - printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]); + printf("str_to_numarry[%d]==%d\n", i, str_to_numarry[i]); num_arry[i] = str_to_numarry[i]; } - //num_arry=(unsigned int *)(&str_to_numarry); return 1; } -unsigned int num_to_env(const char *env_name,unsigned int *num_arry) +unsigned int num_to_env(const char *env_name, unsigned int *num_arry) { - char *str_buf=NULL; + char *str_buf = NULL; char buf[1024]; int i; - //unsigned int str_to_numarry[48]; - //str_buf = (char *)malloc(sizeof(char)*1024); + str_buf = (char *)(&buf); memset(str_buf, 0, sizeof(buf)); - printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf))); + printf("sizeof(str_buf)==%d\n", (unsigned int)(sizeof(buf))); str_buf = getenv(env_name); - //char * str[48]; - printf("str==%s\n",str_buf); + printf("str==%s\n", str_buf); sprintf(buf, "0x%08x", num_arry[0]); for (i = 1; i < 48; i++) { - //num_arry[i]=0; - sprintf(buf, "%s;0x%08x", buf,num_arry[i]); - printf("%d %d\n", i,num_arry[i]); + sprintf(buf, "%s;0x%08x", buf, num_arry[i]); + printf("%d %d\n", i, num_arry[i]); } - //sprintf(str, "%lx", value); - printf( "%s", buf); + printf("%s", buf); setenv(env_name, buf); - run_command("save",0); - //num_arry=(unsigned int *)(&str_to_numarry); + run_command("save", 0); return 1; } - - - #define TDATA32F 0xffffffff #define TDATA32A 0xaaaaaaaa #define TDATA325 0x55555555 -//#define PREG_STICKY_G12A_REG0 (0xff634400 + (0x070 << 2)) -//#define PREG_STICKY_A1_REG0 ((0x00b0 << 2) + 0xfe005800) -//#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe005800) - - -//#define (p_ddr_base->ddr_phy_base_address) (0xfc000000) -//#define DDR_TEST_AUTO_TEST_CMD_MAGIC 0x01234567 -//#define DMC_STICKY_0 ((0x0000 << 2) + 0xff639800) -//#define DMC_STICKY_0 ((0x0000 << 2) + 0xfd020800) -//#define (p_ddr_base->ddr_dmc_sticky0) (DMC_STICKY_0) #define DMC_STICKY_MAGIC_0 0x12345678 #define DMC_STICKY_MAGIC_1 0xabcdbead #define DMC_STICKY_UBOOT_WINDOW_MAGIC_1 0x22 #define DMC_STICKY_AUTO_TEST_CMD_INDEX_MAGIC_1 0x33 - -//#define (p_ddr_base->preg_sticky_reg0) SYSCTRL_STICKY_REG0//(DMC_STICKY_0) -//#define (p_ddr_base->preg_sticky_reg0+4) ((p_ddr_base->preg_sticky_reg0)+4) - -//#define (p_ddr_base->ddr_ddr_pctl_timing_end_address) ((0x001d << 2) + 0xff638400) -//#define (p_ddr_base->ddr_pctl_timing_base_address) ((0x0000 << 2) + 0xff638400) -//#define (p_ddr_base->ddr_ddr_pctl_timing_end_address) ((0x001d << 2) + 0xfd020400) -//#define (p_ddr_base->ddr_pctl_timing_base_address) ((0x0000 << 2) + 0xfd020400) -//#define (p_ddr_base->ddr_dmc_sticky0) (DMC_STICKY_0) unsigned int dmc_sticky[64]; -unsigned int sticky_reg_base_add=0; +unsigned int sticky_reg_base_add = 0; -//#define DDR_TEST_ACLCDLR -unsigned int global_boot_times= 0; -unsigned int watchdog_time_s= 20; -unsigned int global_ddr_clk=1; -unsigned int bdlr_100step=0; -unsigned int ui_1_32_100step=0; -unsigned int error_count =0; -unsigned int error_outof_count_flag=0; -unsigned int copy_test_flag = 0; -unsigned int training_pattern_flag = 0; -unsigned int test_start_addr=0x1080000; +unsigned int global_boot_times = 0; +unsigned int watchdog_time_s = 20; +unsigned int global_ddr_clk = 1; +unsigned int bdlr_100step = 0; +unsigned int ui_1_32_100step = 0; +unsigned int error_count = 0; +unsigned int error_outof_count_flag = 0; +unsigned int copy_test_flag = 0; +unsigned int training_pattern_flag = 0; +unsigned int test_start_addr = 0x1080000; -unsigned int dq_lcd_bdl_value_aclcdlr_org_a; -unsigned int dq_lcd_bdl_value_bdlr0_org_a; -unsigned int dq_lcd_bdl_value_aclcdlr_min_a; -unsigned int dq_lcd_bdl_value_bdlr0_min_a; -unsigned int dq_lcd_bdl_value_aclcdlr_max_a; -unsigned int dq_lcd_bdl_value_bdlr0_max_a; -unsigned int dq_lcd_bdl_value_aclcdlr_status_a; -unsigned int dq_lcd_bdl_value_bdlr0_status_a; +unsigned int dq_lcd_bdl_value_aclcdlr_org_a; +unsigned int dq_lcd_bdl_value_bdlr0_org_a; +unsigned int dq_lcd_bdl_value_aclcdlr_min_a; +unsigned int dq_lcd_bdl_value_bdlr0_min_a; +unsigned int dq_lcd_bdl_value_aclcdlr_max_a; +unsigned int dq_lcd_bdl_value_bdlr0_max_a; +unsigned int dq_lcd_bdl_value_aclcdlr_status_a; +unsigned int dq_lcd_bdl_value_bdlr0_status_a; -unsigned int dq_lcd_bdl_value_aclcdlr_org_b; -unsigned int dq_lcd_bdl_value_bdlr0_org_b; -unsigned int dq_lcd_bdl_value_aclcdlr_min_b; -unsigned int dq_lcd_bdl_value_bdlr0_min_b; -unsigned int dq_lcd_bdl_value_aclcdlr_max_b; -unsigned int dq_lcd_bdl_value_bdlr0_max_b; +unsigned int dq_lcd_bdl_value_aclcdlr_org_b; +unsigned int dq_lcd_bdl_value_bdlr0_org_b; +unsigned int dq_lcd_bdl_value_aclcdlr_min_b; +unsigned int dq_lcd_bdl_value_bdlr0_min_b; +unsigned int dq_lcd_bdl_value_aclcdlr_max_b; +unsigned int dq_lcd_bdl_value_bdlr0_max_b; -unsigned int dq_lcd_bdl_value_wdq_org_a[4]; -unsigned int dq_lcd_bdl_value_rdqs_org_a[4]; -unsigned int dq_lcd_bdl_value_wdq_min_a[4]; -unsigned int dq_lcd_bdl_value_wdq_max_a[4]; -unsigned int dq_lcd_bdl_value_rdqs_min_a[4]; -unsigned int dq_lcd_bdl_value_rdqs_max_a[4]; -unsigned int dq_lcd_bdl_value_wdq_status_a[4]; -unsigned int dq_lcd_bdl_value_rdqs_status_a[4]; +unsigned int dq_lcd_bdl_value_wdq_org_a[4]; +unsigned int dq_lcd_bdl_value_rdqs_org_a[4]; +unsigned int dq_lcd_bdl_value_wdq_min_a[4]; +unsigned int dq_lcd_bdl_value_wdq_max_a[4]; +unsigned int dq_lcd_bdl_value_rdqs_min_a[4]; +unsigned int dq_lcd_bdl_value_rdqs_max_a[4]; +unsigned int dq_lcd_bdl_value_wdq_status_a[4]; +unsigned int dq_lcd_bdl_value_rdqs_status_a[4]; -unsigned int dq_lcd_bdl_value_wdq_org_b[4]; -unsigned int dq_lcd_bdl_value_rdqs_org_b[4]; -unsigned int dq_lcd_bdl_value_wdq_min_b[4]; -unsigned int dq_lcd_bdl_value_wdq_max_b[4]; -unsigned int dq_lcd_bdl_value_rdqs_min_b[4]; -unsigned int dq_lcd_bdl_value_rdqs_max_b[4]; -unsigned int dq_lcd_bdl_value_wdq_status_b[4]; -unsigned int dq_lcd_bdl_value_rdqs_status_b[4]; -unsigned int acbdlr0_9_reg_org[10]; -unsigned int acbdlr0_9_reg_setup_max[40]; -unsigned int acbdlr0_9_reg_hold_max[40]; -unsigned int acbdlr0_9_reg_setup_time[40]; -unsigned int acbdlr0_9_reg_hold_time[40]; -//unsigned int data_bdlr0_5_reg_org[6]; -unsigned int data_bdlr0_5_reg_org[28];//4//4lane -unsigned int bdlr0_9_reg_setup_max[24*4];//4//4 lane 96 bdlr -unsigned int bdlr0_9_reg_hold_max[24*4]; -unsigned int bdlr0_9_reg_setup_time[24*4]; -unsigned int bdlr0_9_reg_hold_time[24*4]; +unsigned int dq_lcd_bdl_value_wdq_org_b[4]; +unsigned int dq_lcd_bdl_value_rdqs_org_b[4]; +unsigned int dq_lcd_bdl_value_wdq_min_b[4]; +unsigned int dq_lcd_bdl_value_wdq_max_b[4]; +unsigned int dq_lcd_bdl_value_rdqs_min_b[4]; +unsigned int dq_lcd_bdl_value_rdqs_max_b[4]; +unsigned int dq_lcd_bdl_value_wdq_status_b[4]; +unsigned int dq_lcd_bdl_value_rdqs_status_b[4]; +unsigned int acbdlr0_9_reg_org[10]; +unsigned int acbdlr0_9_reg_setup_max[40]; +unsigned int acbdlr0_9_reg_hold_max[40]; +unsigned int acbdlr0_9_reg_setup_time[40]; +unsigned int acbdlr0_9_reg_hold_time[40]; +unsigned int data_bdlr0_5_reg_org[28]; //4//4lane +unsigned int bdlr0_9_reg_setup_max[24 * 4]; //4//4 lane 96 bdlr +unsigned int bdlr0_9_reg_hold_max[24 * 4]; +unsigned int bdlr0_9_reg_setup_time[24 * 4]; +unsigned int bdlr0_9_reg_hold_time[24 * 4]; +unsigned int pre_fetch_enable = 0; -unsigned int pre_fetch_enable=0; +#define readl(addr) (unsigned int)(*((volatile unsigned int *)((unsigned long)(unsigned int)addr))) //rd_reg(addr) +#define writel(data, addr) (*((volatile unsigned int *)((unsigned long)(unsigned int)addr))) = (data) //wr_reg(addr, data) -#define readl(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr) -#define writel(data ,addr) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data) - -#define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data) -#define rd_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr) - -//#define CONFIG_DDR_CMD_BDL_TUNE -//#define CONFIG_CMD_DDR_TEST +#define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int)addr))) = (data) //wr_reg(addr, data) +#define rd_reg(addr) (unsigned int)(*((volatile unsigned int *)((unsigned long)(unsigned int)addr))) //rd_reg(addr) #ifndef CONFIG_CHIP -//#define CONFIG_CHIP CHIP_OLD //CHIP_OLD// //#define CHIP_OLD 0 //#define CHIP_TXLX 1 #define CHIP_OLD 0 #define CHIP_TXLX 1 #define CHIP_A113 2 #define CHIP_G12 3 -#define CONFIG_CHIP CHIP_G12// CHIP_OLD// +#define CONFIG_CHIP CHIP_G12 // CHIP_OLD// #endif #define P_DDR_PHY_DEFAULT 0 #define P_DDR_PHY_GX_BABY 1 -#define P_DDR_PHY_GX_TV_BABY 2 -#define P_DDR_PHY_905X 3 +#define P_DDR_PHY_GX_TV_BABY 2 +#define P_DDR_PHY_905X 3 -//#define P_DDR_PHY_OLD_TAG 0 -#define P_DDR_PHY_G12 4 +#define P_DDR_PHY_G12 4 #define CONFIG_DDR_PHY P_DDR_PHY_G12 -//#define G12_AM_DDR_PLL_CNTL0 0xff638c00 - -//#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT) -//#include <asm/arch/secure_apb.h> -//#endif - #define PATTERN_USE_DDR_DES -#define USE_64BIT_POINTER -//#define USE_32BIT_POINTER +#define USE_64BIT_POINTER #ifdef USE_64BIT_POINTER -#define p_convter_int(a) ( unsigned int )( unsigned long )(a) -#define int_convter_p(a) ( unsigned long )(a) +#define p_convter_int(a) (unsigned int)(unsigned long)(a) +#define int_convter_p(a) (unsigned long)(a) #else -#define p_convter_int(a) ( unsigned int )(a) -#define int_convter_p(a) ( unsigned int )(a) +#define p_convter_int(a) (unsigned int)(a) +#define int_convter_p(a) (unsigned int)(a) #endif #ifdef PATTERN_USE_DDR_DES -#define des_pattern(a,b,c,d) (des[a]^pattern_##b[c][d]) -#define des_inv_pattern(a,b,c,d) ( des[a]^(~(pattern_##b[c][d]))) -#define des_xor_pattern(a,b) ( a^b) -//des[temp_i]^pattern_2[temp_k][temp_i] +#define des_pattern(a, b, c, d) (des[a] ^ pattern_ ## b[c][d]) +#define des_inv_pattern(a, b, c, d) (des[a] ^ (~(pattern_ ## b[c][d]))) +#define des_xor_pattern(a, b) (a ^ b) #else -#define des_pattern(a,b,c,d) (des[a]&0)+pattern_##b[c][d] -#define des_inv_pattern(a,b,c,d) (des[a]&0)+~(pattern_##b[c][d]) -#define des_xor_pattern(a,b) (a&0+b) +#define des_pattern(a, b, c, d) (des[a] & 0) + pattern_ ## b[c][d] +#define des_inv_pattern(a, b, c, d) (des[a] & 0) + ~(pattern_ ## b[c][d]) +#define des_xor_pattern(a, b) (a & 0 + b) #endif - -#define DDR_LCDLR_CK_USE_FAST_PATTERN +#define DDR_LCDLR_CK_USE_FAST_PATTERN #if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT) - #define DDR_PREFETCH_CACHE +#define DDR_PREFETCH_CACHE #endif #ifdef DDR_PREFETCH_CACHE - #define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P)) +#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]" ::"r" (P)) #else - #define ddr_pld_cache(P) +#define ddr_pld_cache(P) #endif - -#define DDR_TEST_START_ADDR 0x1080000// 0x10000000 //CONFIG_SYS_MEMTEST_START +#define DDR_TEST_START_ADDR 0x1080000 // 0x10000000 //CONFIG_SYS_MEMTEST_START #define DDR_TEST_SIZE 0x2000000 -//#define DDR_TEST_SIZE 0x2000 -#if (CONFIG_CHIP>=CHIP_TXLX) - -//#define P_EE_TIMER_E (volatile unsigned int *)((0x3c62 << 2) + 0xffd00000) -//#define P_PIN_MUX_REG1 P_PERIPHS_PIN_MUX_1// (((volatile unsigned *)(0xda834400 + (0x2d << 2)))) -//#define P_PIN_MUX_REG2 P_PERIPHS_PIN_MUX_2// (((volatile unsigned *)(0xda834400 + (0x2e << 2)))) -//#define P_PIN_MUX_REG3 P_PERIPHS_PIN_MUX_3//(((volatile unsigned *)(0xda834400 + (0x2f << 2)))) -//#define P_PIN_MUX_REG7 P_PERIPHS_PIN_MUX_7//(((volatile unsigned *)(0xda834400 + (0x33 << 2)))) +#if (CONFIG_CHIP >= CHIP_TXLX) #endif -#define get_us_time() (rd_reg(p_ddr_base->ee_timer_base_address))// (readl(P_ISA_TIMERE)) +#define get_us_time() (rd_reg(p_ddr_base->ee_timer_base_address)) // (readl(P_ISA_TIMERE)) -//#define DDR_PHY_BASE (0xfc000000) - -//#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address)))=((uint16_t)dat) -//#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address))) #define ACX_MAX 0x80 -unsigned int dwc_ddrphy_apb_wr(unsigned int addr,unsigned int dat) +//OVERRIDE_OPTION +#define DMC_TEST_WINDOW_INDEX_ATXDLY 1 +#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2 +#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3 +#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4 +#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5 +#define DMC_TEST_WINDOW_INDEX_RXENDLY 6 +#define DMC_TEST_WINDOW_INDEX_RXPBDLY_2 7 +#define DMC_TEST_WINDOW_INDEX_DFIMRL 8 +#define DMC_TEST_WINDOW_INDEX_VREF 9 +#define DMC_TEST_WINDOW_INDEX_RETRAINING 10 +#define DMC_TEST_WINDOW_INDEX_EXTERA_COMMON 11 +#define DMC_TEST_WINDOW_INDEX_EXTERA_PS 12 + +#define DMC_TEST_WINDOW_INDEX_RXCLKDLY_DAC1 12 +#define DMC_TEST_WINDOW_INDEX_RXPBDLY_DAC1 13 +#define DMC_TEST_WINDOW_INDEX_RXPBDLY_2_DAC1 14 + +#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11 +#define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12 +#define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x13 + +#define DMC_TEST_WINDOW_INDEX_DDR3_WRITE_VREF_RANG0 0x21 +#define DMC_TEST_WINDOW_INDEX_DDR3_WRITE_VREF_RANG1 0x22 +#define DMC_TEST_WINDOW_INDEX_DDR3_READ_VREF_RANG0 0x23 +#define DMC_TEST_WINDOW_INDEX_DDR3_READ_VREF_RANG1 0x24 + +#define DMC_TEST_WINDOW_INDEX_DDR4_WRITE_VREF_RANG0 0x31 +#define DMC_TEST_WINDOW_INDEX_DDR4_WRITE_VREF_RANG1 0x32 +#define DMC_TEST_WINDOW_INDEX_DDR4_READ_VREF_RANG0 0x33 +#define DMC_TEST_WINDOW_INDEX_DDR4_READ_VREF_RANG1 0x34 + +#define DMC_TEST_WINDOW_INDEX_LPDDR4_WRITE_VREF_RANG0 0x41 +#define DMC_TEST_WINDOW_INDEX_LPDDR4_WRITE_VREF_RANG1 0x42 +#define DMC_TEST_WINDOW_INDEX_LPDDR4_READ_VREF_RANG0 0x43 +#define DMC_TEST_WINDOW_INDEX_LPDDR4_READ_VREF_RANG1 0x44 + +#define DMC_TEST_WINDOW_INDEX_LPDDR3_WRITE_VREF_RANG0 0x51 +#define DMC_TEST_WINDOW_INDEX_LPDDR3_WRITE_VREF_RANG1 0x52 +#define DMC_TEST_WINDOW_INDEX_LPDDR3_READ_VREF_RANG0 0x53 +#define DMC_TEST_WINDOW_INDEX_LPDDR3_READ_VREF_RANG1 0x54 + +unsigned int dwc_ddrphy_apb_wr(unsigned int addr, unsigned int dat) { - *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address)))=((uint16_t)dat); + *(volatile uint16_t *)(int_convter_p(((addr) << 1) + (p_ddr_base->ddr_phy_base_address))) = ((uint16_t)dat); return 1; } -unsigned int dwc_ddrphy_apb_rd(unsigned int addr) +unsigned int dwc_ddrphy_apb_rd(unsigned int addr) { - return *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address))); + return *(volatile uint16_t *)(int_convter_p(((addr) << 1) + (p_ddr_base->ddr_phy_base_address))); } void ddr_udelay(unsigned int us) { unsigned int t0 = (rd_reg((p_ddr_base->ee_timer_base_address))); - while ((rd_reg(((p_ddr_base->ee_timer_base_address)))) - t0 <= us) ; + + while ((rd_reg(((p_ddr_base->ee_timer_base_address)))) - t0 <= us) { + } } -#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1 -#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2 -#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3 +void ddr_udelay_dummy(volatile unsigned int us) +{ + if ((p_ddr_base->ee_timer_base_address)) { + ddr_udelay(us); + } else { + if (us == 0) + us = 10000; + + while (us--) { + } + } +} +#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1 +#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2 +#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3 #define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4 -#define DDR_PARAMETER_READ 1 -#define DDR_PARAMETER_WRITE 2 -#define DDR_PARAMETER_LEFT 1 -#define DDR_PARAMETER_RIGHT 2 +#define DDR_PARAMETER_READ 1 +#define DDR_PARAMETER_WRITE 2 +#define DDR_PARAMETER_LEFT 1 +#define DDR_PARAMETER_RIGHT 2 + +#define REGISTER_READ 1 +#define REGISTER_WRITE 0 typedef struct ddr_test_struct { - unsigned int ddr_data_source ; - unsigned int ddr_data_test_size ; - unsigned int ddr_address_test_size ; - unsigned int ddr_test_watchdog_times_s ; - unsigned int ddr_test_lane_disable ; + unsigned int ddr_data_source; + unsigned int ddr_data_test_size; + unsigned int ddr_address_test_size; + unsigned int ddr_test_watchdog_times_s; + unsigned int ddr_test_lane_disable; - unsigned int ddr_test_window_flag[8] ; - unsigned int ddr_test_window_data[100] ; -} ddr_test_struct_t; + unsigned int ddr_test_window_flag[8]; + unsigned int ddr_test_window_data[100]; +}ddr_test_struct_t; ddr_test_struct_t *g_ddr_test_struct; -unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag ) +unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index, unsigned int parameter_value, unsigned int read_write_flag) { - - if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY) - { - sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0))&0xffff); + if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY) { + sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0)) & 0xffff); if (read_write_flag == DDR_PARAMETER_WRITE) - wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value); + wr_reg((sticky_reg_base_add + (parameter_index << 2)), parameter_value); if (read_write_flag == DDR_PARAMETER_READ) - parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2))); + parameter_value = rd_reg((sticky_reg_base_add + (parameter_index << 2))); } - if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV) - { + if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV) { char *pre_env_name = "ddr_test_data_num"; char *env_name = "ddr_test_data_num_0000"; char *str_buf = NULL; @@ -1404,16 +1536,14 @@ char buf[1024]; str_buf = (char *)(&buf); memset(str_buf, 0, sizeof(buf)); - sprintf(env_name,"%s_%04d",pre_env_name,parameter_index); + sprintf(env_name, "%s_%04d", pre_env_name, parameter_index); sprintf(buf, "0x%08x", parameter_value); - if (read_write_flag == DDR_PARAMETER_WRITE) - { + if (read_write_flag == DDR_PARAMETER_WRITE) { setenv(env_name, buf); - run_command("save",0); + run_command("save", 0); } - if (read_write_flag == DDR_PARAMETER_READ) - { + if (read_write_flag == DDR_PARAMETER_READ) { temp_s = getenv(env_name); if (temp_s) parameter_value = simple_strtoull_ddr(temp_s, &endp, 0); @@ -1422,44 +1552,38 @@ } } - if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY) - { - sticky_reg_base_add=((p_ddr_base->preg_sticky_reg0)); + if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY) { + sticky_reg_base_add = ((p_ddr_base->preg_sticky_reg0)); if (read_write_flag == DDR_PARAMETER_WRITE) - wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value); + wr_reg((sticky_reg_base_add + (parameter_index << 2)), parameter_value); if (read_write_flag == DDR_PARAMETER_READ) - parameter_value=rd_reg((sticky_reg_base_add+(parameter_index<<2))); + parameter_value = rd_reg((sticky_reg_base_add + (parameter_index << 2))); } return parameter_value; } - -unsigned int read_write_window_test_flag(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag ) +unsigned int read_write_window_test_flag(unsigned int source_index, unsigned int parameter_index, unsigned int parameter_value, unsigned int read_write_flag) { - - if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY) - { + if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY) { sticky_reg_base_add = p_ddr_base->preg_sticky_reg0; if (read_write_flag == DDR_PARAMETER_WRITE) - wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value); + wr_reg((sticky_reg_base_add + (parameter_index << 2)), parameter_value); if (read_write_flag == DDR_PARAMETER_READ) - parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2))); + parameter_value = rd_reg((sticky_reg_base_add + (parameter_index << 2))); } - if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY) - { - sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0))&0xffff); + if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY) { + sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0)) & 0xffff); if (read_write_flag == DDR_PARAMETER_WRITE) - wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value); + wr_reg((sticky_reg_base_add + (parameter_index << 2)), parameter_value); if (read_write_flag == DDR_PARAMETER_READ) - parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2))); + parameter_value = rd_reg((sticky_reg_base_add + (parameter_index << 2))); } - if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV) - { + if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV) { char *pre_env_name = "ddr_test_data_num"; char *env_name = "ddr_test_data_num_0000"; char *str_buf = NULL; @@ -1468,16 +1592,14 @@ char buf[1024]; str_buf = (char *)(&buf); memset(str_buf, 0, sizeof(buf)); - sprintf(env_name,"%s_%04d",pre_env_name,parameter_index); + sprintf(env_name, "%s_%04d", pre_env_name, parameter_index); sprintf(buf, "0x%08x", parameter_value); - if (read_write_flag == DDR_PARAMETER_WRITE) - { + if (read_write_flag == DDR_PARAMETER_WRITE) { setenv(env_name, buf); - run_command("save",0); + run_command("save", 0); } - if (read_write_flag == DDR_PARAMETER_READ) - { + if (read_write_flag == DDR_PARAMETER_READ) { temp_s = getenv(env_name); if (temp_s) parameter_value = simple_strtoull_ddr(temp_s, &endp, 0); @@ -1489,422 +1611,146 @@ return parameter_value; } -//#define (p_ddr_base->sys_watchdog_base_address) ((0x0040 << 2) + 0xfe000000) -//#define (p_ddr_base->sys_watchdog_base_address+4) ((0x0041 << 2) + 0xfe000000) -//#define (p_ddr_base->sys_watchdog_base_address+8) ((0x0042 << 2) + 0xfe000000) -//#define (p_ddr_base->sys_watchdog_base_address+12) ((0x0043 << 2) + 0xfe000000) - void ddr_test_watchdog_init(uint32_t msec) { // src: 24MHz // div: 24000 for 1ms // reset ao-22 and ee-21 - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address) = (1<<24)|(1<<25)|(1<<22)|(1<<21)|(24000-1); + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) = (1 << 24) | (1 << 25) | (1 << 22) | (1 << 21) | (24000 - 1); // set timeout - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+8) = msec; - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+12) = 0; + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 8) = msec; + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 12) = 0; // enable - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address) |= (1<<18); + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) |= (1 << 18); } void ddr_test_watchdog_clear(void) { - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+12) = 0; + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 12) = 0; } void ddr_test_watchdog_disable(void) { // turn off internal counter and disable - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address) &= ~((1<<18)|(1<<25)); + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) &= ~((1 << 18) | (1 << 25)); } + void ddr_test_watchdog_enable(uint32_t sec) { - // src: 24MHz // div: 24000 for 1ms // reset ao-22 and ee-21 - // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL); #if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT) - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address)=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms - // set timeout - //*P_WATCHDOG_TCNT = msec; - // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15 - if (sec*100>0xffff) - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+8)=0xffff; + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) = (1 << 24) | (1 << 25) | (1 << 23) | (1 << 21) | (240000 - 1); //10ms + if (sec * 100 > 0xffff) + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 8) = 0xffff; else - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+8)=sec*100; //max 655s - //writel(0,(unsigned int )P_WATCHDOG_RESET); - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+12)=0; - //*P_WATCHDOG_RESET = 0; + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 8) = sec * 100; //max 655s + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 12) = 0; // enable - *(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address)=(*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address))|(1<<18); - //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL); - //*P_WATCHDOG_CNTL |= (1<<18); - + *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) = (*(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address)) | (1 << 18); #endif printf("\nP_WATCHDOG_ENABLE\n"); } + void ddr_test_watchdog_reset_system(void) { int i; - //_udelay(10000); //wait print - if (p_ddr_base->sys_watchdog_enable_value == 0) - p_ddr_base->sys_watchdog_enable_value=0x3 | (1 << 21) // sys reset en - | (1 << 23) // interrupt en - | (1 << 24) // clk en - | (1 << 25) // clk div en - | (1 << 26) ;// sys reset now - writel(0, (p_ddr_base->sys_watchdog_base_address+12)); + + if (p_ddr_base->sys_watchdog_enable_value == 0) { + p_ddr_base->sys_watchdog_enable_value = 0x3 | (1 << 21) // sys reset en + | (1 << 23) // interrupt en + | (1 << 24) // clk en + | (1 << 25) // clk div en + | (1 << 26); // sys reset now + } + writel(0, (p_ddr_base->sys_watchdog_base_address + 12)); while (1) { writel(p_ddr_base->sys_watchdog_enable_value - , (p_ddr_base->sys_watchdog_base_address)); - //writel(0, (p_ddr_base->sys_watchdog_base_address+12)); - writel(0, (p_ddr_base->sys_watchdog_base_address+12)); - writel((p_ddr_base->sys_watchdog_enable_value) | (1<<18), - (p_ddr_base->sys_watchdog_base_address));// watchdog en - for (i=0; i<100; i++) - readl((p_ddr_base->sys_watchdog_base_address));/*Deceive gcc for waiting some cycles */ + , (p_ddr_base->sys_watchdog_base_address)); + writel(0, (p_ddr_base->sys_watchdog_base_address + 12)); + writel((p_ddr_base->sys_watchdog_enable_value) | (1 << 18), + (p_ddr_base->sys_watchdog_base_address)); // watchdog en + for (i = 0; i < 100; i++) + readl((p_ddr_base->sys_watchdog_base_address)); /*Deceive gcc for waiting some cycles */ } } - -#if 0 -void ddr_test_watchdog_init(uint32_t msec) +static void ddr_write(void *buff, unsigned int m_length) { + unsigned int *p; + unsigned int i, j, n; + unsigned int m_len = m_length; - // src: 24MHz - // div: 24000 for 1ms - // reset ao-22 and ee-21 - // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL); -#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT) - *P_WATCHDOG_CNTL = (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1); + p = (unsigned int *)buff; - // set timeout - //*P_WATCHDOG_TCNT = msec; - // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15 - *P_WATCHDOG_TCNT = msec; - //writel(0,(unsigned int )P_WATCHDOG_RESET); - *P_WATCHDOG_RESET = 0; - //*P_WATCHDOG_RESET = 0; - - // enable - *P_WATCHDOG_CNTL = (*P_WATCHDOG_CNTL)|(1<<18); - //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL); - //*P_WATCHDOG_CNTL |= (1<<18); -#else - *P_WATCHDOG_CNTL = (0<<24)|(msec*8-1); - //*P_WATCHDOG_TCNT=msec; -#endif -} - -void ddr_test_watchdog_enable(uint32_t sec) -{ - - // src: 24MHz - // div: 24000 for 1ms - // reset ao-22 and ee-21 - // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL); -#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT) - *P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms - // set timeout - //*P_WATCHDOG_TCNT = msec; - // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15 - if (sec*100>0xffff) - *P_WATCHDOG_TCNT=0xffff; - else - *P_WATCHDOG_TCNT=sec*100; //max 655s - //writel(0,(unsigned int )P_WATCHDOG_RESET); - *P_WATCHDOG_RESET=0; - //*P_WATCHDOG_RESET = 0; - - // enable - *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18); - //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL); - //*P_WATCHDOG_CNTL |= (1<<18); -#else - //*P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(sec*8000-1); - *P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(0xffff); - printf("\nm8baby_watchdog max only 5s,please take care test size not too long for m8baby\n"); -#endif - printf("\nP_WATCHDOG_ENABLE\n"); -} - -void ddr_test_watchdog_disable(void ) -{ - - // src: 24MHz - // div: 24000 for 1ms - // reset ao-22 and ee-21 - // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL); -#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT) - *P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms - // set timeout - //*P_WATCHDOG_TCNT = msec; - // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15 - //*P_WATCHDOG_TCNT=sec*100; - //writel(0,(unsigned int )P_WATCHDOG_RESET); - *P_WATCHDOG_RESET=0; - //*P_WATCHDOG_RESET = 0; - - // enable - *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18)); - //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL); - //*P_WATCHDOG_CNTL |= (1<<18); -#else - *P_WATCHDOG_CNTL=(0<<24)|(0<<19)|(24000-1); -#endif - printf("\nP_WATCHDOG_DISABLE\n"); -} - - -void ddr_test_watchdog_clear(void ) -{ - *P_WATCHDOG_RESET=0; -} - -void ddr_test_watchdog_reset_system(void) -{ - //#define P_WATCHDOG_CNTL 0xc11098d0 - //#define P_WATCHDOG_CNTL1 0xc11098d4 - //#define P_WATCHDOG_TCNT 0xc11098d8 - //#define P_WATCHDOG_RESET 0xc11098dc -#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT) - int i; - - while (1) { - /* - writel( 0x3 | (1 << 21) // sys reset en ao ee 3 - | (1 << 23) // interrupt en - | (1 << 24) // clk en - | (1 << 25) // clk div en - | (1 << 26) // sys reset now ao ee 3 - , (unsigned int )P_WATCHDOG_CNTL); - */ - *P_WATCHDOG_CNTL= - 0x3 | (1 << 21) // sys reset en ao ee 3 - | (1 << 23) // interrupt en - | (1 << 24) // clk en - | (1 << 25) // clk div en - | (1 << 26); // sys reset now ao ee 3; - //printf("\nP_WATCHDOG_CNTL reg_add_%x08==%x08",(unsigned int )P_WATCHDOG_CNTL,readl((unsigned int )P_WATCHDOG_CNTL)); - //printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL)); - //printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL)); - printf("\nP_WATCHDOG_CNTLREG_ADD %x08==%x08",(unsigned int)(unsigned long)P_WATCHDOG_CNTL, - *P_WATCHDOG_CNTL); - //writel(0, (unsigned int )P_WATCHDOG_RESET); - *P_WATCHDOG_RESET=0; - - // writel(readl((unsigned int )P_WATCHDOG_CNTL) | (1<<18), // watchdog en - //(unsigned int )P_WATCHDOG_CNTL); - *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18); - for (i=0; i<100; i++) - *P_WATCHDOG_CNTL; - //readl((unsigned int )P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */ - } - -#else - //WRITE_CBUS_REG(WATCHDOG_TC, 0xf080000 | 2000); - *P_WATCHDOG_CNTL=(0xf080000 | 2000); -#endif - while (1) ; -} -#endif -static void ddr_write(void *buff, unsigned int m_length) -{ - unsigned int *p; - unsigned int i, j, n; - unsigned int m_len = m_length; - - p = ( unsigned int *)buff; - - while (m_len) - { - for (j=0;j<32;j++) - { - + while (m_len) { + for (j = 0; j < 32; j++) { if (m_len >= 128) n = 32; else - n = m_len>>2; + n = m_len >> 2; - for (i = 0; i < n; i++) - { + for (i = 0; i < n; i++) { #ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; + ddr_pld_cache(p); #endif - switch (i) - { - case 0: - case 9: - case 14: - case 25: - case 30: - *(p+i) = TDATA32F; - break; - case 1: - case 6: - case 8: - case 17: - case 22: - *(p+i) = 0; - break; - case 16: - case 23: - case 31: - *(p+i) = TDATA32A; - break; - case 7: - case 15: - case 24: - *(p+i) = TDATA325; - break; - case 2: - case 4: - case 10: - case 12: - case 19: - case 21: - case 27: - case 29: - *(p+i) = 1<<j; - break; - case 3: - case 5: - case 11: - case 13: - case 18: - case 20: - case 26: - case 28: - *(p+i) = ~(1<<j); - break; - } - } - - if (m_len > 128) - { - m_len -= 128; - p += 32; - } - else - { - p += (m_len>>2); - m_len = 0; - break; - } - } - } -} - -static void ddr_read(void *buff, unsigned int m_length) -{ - unsigned int *p; - unsigned int i, j, n; - unsigned int m_len = m_length; - - p = ( unsigned int *)buff; - - while (m_len) - { - for (j=0;j<32;j++) - { - - if (m_len >= 128) - n = 32; - else - n = m_len>>2; - - for (i = 0; i < n; i++) - { -#ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; -#endif - if ((error_outof_count_flag) && (error_count)) - { - printf("Error data out of count"); - m_len=0; + switch (i) { + case 0: + case 9: + case 14: + case 25: + case 30: + *(p + i) = TDATA32F; + break; + case 1: + case 6: + case 8: + case 17: + case 22: + *(p + i) = 0; + break; + case 16: + case 23: + case 31: + *(p + i) = TDATA32A; + break; + case 7: + case 15: + case 24: + *(p + i) = TDATA325; + break; + case 2: + case 4: + case 10: + case 12: + case 19: + case 21: + case 27: + case 29: + *(p + i) = 1 << j; + break; + case 3: + case 5: + case 11: + case 13: + case 18: + case 20: + case 26: + case 28: + *(p + i) = ~(1 << j); break; } - switch (i) - { - - case 0: - case 9: - case 14: - case 25: - case 30: - if (*(p+i) != TDATA32F) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); - } - break; - case 1: - case 6: - case 8: - case 17: - case 22: - if (*(p+i) != 0) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0); - }break; - case 16: - case 23: - case 31: - if (*(p+i) != TDATA32A) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A); - } break; - case 7: - case 15: - case 24: - if (*(p+i) != TDATA325) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325); - } break; - case 2: - case 4: - case 10: - case 12: - case 19: - case 21: - case 27: - case 29: - if (*(p+i) != 1<<j) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 1<<j); - } break; - case 3: - case 5: - case 11: - case 13: - case 18: - case 20: - case 26: - case 28: - if (*(p+i) != ~(1<<j)) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~(1<<j)); - } break; - } } - if (m_len > 128) - { + if (m_len > 128) { m_len -= 128; p += 32; - } - else - { - p += (m_len>>2); + } else { + p += (m_len >> 2); m_len = 0; break; } @@ -1912,212 +1758,101 @@ } } - -static void ddr_write4(void *buff, unsigned int m_length) +static void ddr_read(void *buff, unsigned int m_length) { - unsigned int *p; - unsigned int i, j, n; - unsigned int m_len = m_length; + unsigned int *p; + unsigned int i, j, n; + unsigned int m_len = m_length; - p = ( unsigned int *)buff; + p = (unsigned int *)buff; - while (m_len) - { - for (j=0;j<32;j++) - { - + while (m_len) { + for (j = 0; j < 32; j++) { if (m_len >= 128) n = 32; else - n = m_len>>2; + n = m_len >> 2; - for (i = 0; i < n; i++) - { + for (i = 0; i < n; i++) { #ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; + ddr_pld_cache(p); #endif - switch (i) - { - case 0: - case 1: - case 2: - case 3: - *(p+i) = 0xff00ff00; - break; - case 4: - case 5: - case 6: - case 7: - *(p+i) = ~0xff00ff00; - break; - case 8: - case 9: - case 10: - case 11: - *(p+i) = 0xaa55aa55; - break; - case 12: - case 13: - case 14: - case 15: - *(p+i) = ~0xaa55aa55; - break; - case 16: - case 17: - case 18: - case 19: - - case 24: - case 25: - case 26: - case 27: - *(p+i) = 1<<j; - break; - case 20: - case 21: - case 22: - case 23: - case 28: - case 29: - case 30: - case 31: - *(p+i) = ~(1<<j); - break; - } - } - - if (m_len > 128) - { - m_len -= 128; - p += 32; - } - else - { - p += (m_len>>2); - m_len = 0; - break; - } - } - } -} - -static void ddr_read4(void *buff, unsigned int m_length) -{ - unsigned int *p; - unsigned int i, j, n; - unsigned int m_len = m_length; - - p = ( unsigned int *)buff; - - while (m_len) - { - for (j=0;j<32;j++) - { - - if (m_len >= 128) - n = 32; - else - n = m_len>>2; - - for (i = 0; i < n; i++) - { -#ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; -#endif - if ((error_outof_count_flag) && (error_count)) - { + if ((error_outof_count_flag) && (error_count)) { printf("Error data out of count"); - m_len=0; + m_len = 0; break; } - switch (i) - { - case 0: - case 1: - case 2: - case 3: - // *(p+i) = 0xff00ff00; - if (*(p+i) != 0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); - } - break; - case 4: - case 5: - case 6: - case 7: - // *(p+i) = ~0xff00ff00; - if (*(p+i) != ~0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); - } - break; - case 8: - case 9: - case 10: - case 11: - // *(p+i) = 0xaa55aa55; - if (*(p+i) != 0xaa55aa55) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); - } - break; - case 12: - case 13: - case 14: - case 15: - // *(p+i) = ~0xaa55aa55; - if (*(p+i) != ~0xaa55aa55) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); - } - break; - case 16: - case 17: - case 18: - case 19: - - case 24: - case 25: - case 26: - case 27: - // *(p+i) = 1<<j; - if (*(p+i) != (1<<j)) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); - } - break; - case 20: - case 21: - case 22: - case 23: - case 28: - case 29: - case 30: - case 31: - // *(p+i) = ~(1<<j); - if (*(p+i) !=~( 1<<j)) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); - } - break; + switch (i) { + case 0: + case 9: + case 14: + case 25: + case 30: + if (*(p + i) != TDATA32F) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F); + } + break; + case 1: + case 6: + case 8: + case 17: + case 22: + if (*(p + i) != 0) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0); + } + break; + case 16: + case 23: + case 31: + if (*(p + i) != TDATA32A) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32A); + } + break; + case 7: + case 15: + case 24: + if (*(p + i) != TDATA325) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA325); + } + break; + case 2: + case 4: + case 10: + case 12: + case 19: + case 21: + case 27: + case 29: + if (*(p + i) != 1 << j) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 1 << j); + } + break; + case 3: + case 5: + case 11: + case 13: + case 18: + case 20: + case 26: + case 28: + if (*(p + i) != ~(1 << j)) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~(1 << j)); + } + break; } } - if (m_len > 128) - { + if (m_len > 128) { m_len -= 128; p += 32; - } - else - { - p += (m_len>>2); + } else { + p += (m_len >> 2); m_len = 0; break; } @@ -2125,96 +1860,279 @@ } } -static void ddr_read_full(void *buff, unsigned int m_length,unsigned int start_pattern, - unsigned int pattern_offset) +static void ddr_write4(void *buff, unsigned int m_length) { - unsigned int *p; - unsigned int i=0; - unsigned int m_len = m_length&0xfffffffc; + unsigned int *p; + unsigned int i, j, n; + unsigned int m_len = m_length; - p = ( unsigned int *)buff; - //*(p)=start_pattern; - while (m_len) - { - m_len=m_len-4; + p = (unsigned int *)buff; - // *(p+i) = (*(p))+pattern_offset; + while (m_len) { + for (j = 0; j < 32; j++) { + if (m_len >= 128) + n = 32; + else + n = m_len >> 2; + + for (i = 0; i < n; i++) { +#ifdef DDR_PREFETCH_CACHE + ddr_pld_cache(p); +#endif + switch (i) { + case 0: + case 1: + case 2: + case 3: + *(p + i) = 0xff00ff00; + break; + case 4: + case 5: + case 6: + case 7: + *(p + i) = ~0xff00ff00; + break; + case 8: + case 9: + case 10: + case 11: + *(p + i) = 0xaa55aa55; + break; + case 12: + case 13: + case 14: + case 15: + *(p + i) = ~0xaa55aa55; + break; + case 16: + case 17: + case 18: + case 19: + + case 24: + case 25: + case 26: + case 27: + *(p + i) = 1 << j; + break; + case 20: + case 21: + case 22: + case 23: + case 28: + case 29: + case 30: + case 31: + *(p + i) = ~(1 << j); + break; + } + } + + if (m_len > 128) { + m_len -= 128; + p += 32; + } else { + p += (m_len >> 2); + m_len = 0; + break; + } + } + } +} + +static void ddr_read4(void *buff, unsigned int m_length) +{ + unsigned int *p; + unsigned int i, j, n; + unsigned int m_len = m_length; + + p = (unsigned int *)buff; + + while (m_len) { + for (j = 0; j < 32; j++) { + if (m_len >= 128) + n = 32; + else + n = m_len >> 2; + + for (i = 0; i < n; i++) { +#ifdef DDR_PREFETCH_CACHE + ddr_pld_cache(p); +#endif + if ((error_outof_count_flag) && (error_count)) { + printf("Error data out of count"); + m_len = 0; + break; + } + switch (i) { + case 0: + case 1: + case 2: + case 3: + if (*(p + i) != 0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F); + } + break; + case 4: + case 5: + case 6: + case 7: + if (*(p + i) != ~0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F); + } + break; + case 8: + case 9: + case 10: + case 11: + if (*(p + i) != 0xaa55aa55) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F); + } + break; + case 12: + case 13: + case 14: + case 15: + if (*(p + i) != ~0xaa55aa55) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F); + } + break; + case 16: + case 17: + case 18: + case 19: + + case 24: + case 25: + case 26: + case 27: + if (*(p + i) != (1 << j)) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F); + } + break; + case 20: + case 21: + case 22: + case 23: + case 28: + case 29: + case 30: + case 31: + if (*(p + i) != ~(1 << j)) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F); + } + break; + } + } + + if (m_len > 128) { + m_len -= 128; + p += 32; + } else { + p += (m_len >> 2); + m_len = 0; + break; + } + } + } +} + +static void ddr_read_full(void *buff, unsigned int m_length, unsigned int start_pattern, + unsigned int pattern_offset) +{ + unsigned int *p; + unsigned int i = 0; + unsigned int m_len = m_length & 0xfffffffc; + + p = (unsigned int *)buff; + while (m_len) { + m_len = m_len - 4; #ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p+i) ; + ddr_pld_cache(p + i); #endif - if ((error_outof_count_flag) && (error_count)) - { + if ((error_outof_count_flag) && (error_count)) { printf("Error data out of count"); - m_len=0; + m_len = 0; break; } - if ((*(p+i)) !=(start_pattern+pattern_offset*i)) - { + if ((*(p + i)) != (start_pattern + pattern_offset * i)) { error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), - (start_pattern+pattern_offset*i)); + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), + (start_pattern + pattern_offset * i)); } - break; - + //break; i++; } } -static void ddr_write_full(void *buff, unsigned int m_length,unsigned int start_pattern, - unsigned int pattern_offset) +static void ddr_write_full(void *buff, unsigned int m_length, unsigned int start_pattern, + unsigned int pattern_offset) { - unsigned int *p; - unsigned int i=0; - unsigned int m_len = m_length&0xfffffffc; + unsigned int *p; + unsigned int i = 0; + unsigned int m_len = m_length & 0xfffffffc; - p = ( unsigned int *)buff; - //*(p)=start_pattern; - while (m_len) - { - m_len=m_len-4; - *(p+i) = start_pattern+pattern_offset*i; + p = (unsigned int *)buff; + while (m_len) { + m_len = m_len - 4; + *(p + i) = start_pattern + pattern_offset * i; i++; } } -///* -static void ddr_test_copy(void *addr_dest,void *addr_src,unsigned int memcpy_size) +static void ddr_test_copy(void *addr_dest, void *addr_src, unsigned int memcpy_size) { - unsigned int *p_dest; - unsigned int *p_src; + unsigned int *p_dest; + unsigned int *p_src; - unsigned int m_len = memcpy_size; + unsigned int m_len = memcpy_size; - p_dest = ( unsigned int *)addr_dest; - p_src = ( unsigned int *)addr_src; - m_len = m_len/4; //assume it's multiple of 4 + p_dest = (unsigned int *)addr_dest; + p_src = (unsigned int *)addr_src; + m_len = m_len / 4; //assume it's multiple of 4 while (m_len--) { - ddr_pld_cache(p_src) ;//#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P)) + ddr_pld_cache(p_src); //#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P)) *p_dest++ = *p_src++; *p_dest++ = *p_src++; *p_dest++ = *p_src++; *p_dest++ = *p_src++; } } -//*/ -int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) + +int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { check_base_address(); - char *endp; - unsigned long loop = 1; - unsigned int print_flag =1; - unsigned int src_addr = DDR_TEST_START_ADDR; - unsigned int dec_addr = DDR_TEST_START_ADDR+0x8000000; - unsigned int test_size = DDR_TEST_SIZE; + char *endp = NULL; + unsigned long loop = 1; + unsigned int print_flag = 1; + unsigned int src_addr = DDR_TEST_START_ADDR; + unsigned int dec_addr = DDR_TEST_START_ADDR + 0x8000000; + unsigned int test_size = DDR_TEST_SIZE; - print_flag=1; + print_flag = 1; printf("\nargc== 0x%08x\n", argc); - int i ; - for (i = 0;i<argc;i++) - printf("\nargv[%d]=%s\n",i,argv[i]); + int i; + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); + + if (argc == 1) { + src_addr = DDR_TEST_START_ADDR; + loop = 1; + } + + if (argc > 2) { + if (*argv[2] == 0 || *endp != 0) + src_addr = DDR_TEST_START_ADDR; + } if (argc > 3) { src_addr = simple_strtoull_ddr(argv[1], &endp, 16); @@ -2223,9 +2141,8 @@ loop = 1; if (*argv[3] == 0 || *endp != 0) test_size = DDR_TEST_SIZE; - } - if (test_size<0x1000) + if (test_size < 0x1000) test_size = DDR_TEST_SIZE; if (argc > 4) { loop = simple_strtoull_ddr(argv[4], &endp, 16); @@ -2237,81 +2154,66 @@ if (*argv[5] == 0 || *endp != 0) print_flag = 1; } - //COPY_TEST_START: - ///* - unsigned long time_start, time_end,test_loops; - test_loops=loop; - unsigned long size_count=0; - size_count=loop*test_size; - time_start = get_us_time();//us + unsigned long time_start, time_end, test_loops; + test_loops = loop; + unsigned long size_count = 0; + size_count = loop * test_size; + time_start = get_us_time(); //us do { - // loop = 1; - ddr_test_copy((void *)(int_convter_p(dec_addr)),(void *)(int_convter_p(src_addr)),test_size); - //bcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size); - //mcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size); - if (print_flag) - { - printf("\nloop==0x%08x", ( unsigned int )loop); + ddr_test_copy((void *)(int_convter_p(dec_addr)), (void *)(int_convter_p(src_addr)), test_size); + if (print_flag) { + printf("\nloop==0x%08x", (unsigned int)loop); printf("\n \n"); } - }while(--loop); - //*/ - time_end = get_us_time();//us - printf("\ncopy %d times use %dus\n \n",( unsigned int )test_loops,( unsigned int )(time_end-time_start)); + } while (--loop); + time_end = get_us_time(); //us + printf("\ncopy %d times use %dus\n \n", (unsigned int)test_loops, (unsigned int)(time_end - time_start)); - printf("\nddr copy bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start))); + printf("\nddr copy bandwidth==%d MBYTE/S \n \n", (unsigned int)(size_count / (time_end - time_start))); printf("\rEnd ddr test. \n"); - unsigned int m_len=0,counter=0; - unsigned int *p_dest; - p_dest= (void *)(int_convter_p(dec_addr)); - m_len = test_size/4; //assume it's multiple of 4 - counter=(unsigned int)test_loops; - size_count=counter*test_size; - time_start = get_us_time();//us + unsigned int m_len = 0, counter = 0; + unsigned int *p_dest; + p_dest = (void *)(int_convter_p(dec_addr)); + m_len = test_size / 4; //assume it's multiple of 4 + counter = (unsigned int)test_loops; + size_count = counter * test_size; + time_start = get_us_time(); //us do { loop = 1; - m_len = test_size/4; + m_len = test_size / 4; while (m_len--) { - ddr_pld_cache(p_dest) ; + ddr_pld_cache(p_dest); *p_dest++ = 0x12345678; *p_dest++ = 0x12345678; *p_dest++ = 0x12345678; *p_dest++ = 0x12345678; } - }while(--counter); - time_end = get_us_time();//us - printf("\nwrite %d bytes use %dus\n \n",( unsigned int )test_size,( unsigned int )(time_end-time_start)); + } while (--counter); + time_end = get_us_time(); //us + printf("\nwrite %d bytes use %dus\n \n", (unsigned int)test_size, (unsigned int)(time_end - time_start)); - printf("\nddr write bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start))); + printf("\nddr write bandwidth==%d MBYTE/S \n \n", (unsigned int)(size_count / (time_end - time_start))); - unsigned int *p_src; - p_src= (void *)(int_convter_p(src_addr)); - m_len = test_size/4; //assume it's multiple of 4 - unsigned int temp0=0; - //unsigned int temp1=0; - //unsigned int temp2=0; - //unsigned int temp3=0; - counter=(unsigned int)test_loops; - size_count=counter*test_size; + unsigned int *p_src; + p_src = (void *)(int_convter_p(src_addr)); + m_len = test_size / 4; //assume it's multiple of 4 + unsigned int temp0 = 0; + counter = (unsigned int)test_loops; + size_count = counter * test_size; - // #define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00)) - //writel((1000000<<0), DMC_MON_CTRL1); - //writel((0<<31)|(1<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2); - //writel((1<<31)|(0<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2); - time_start = get_us_time();//us + time_start = get_us_time(); //us do { loop = 1; - m_len = test_size/4; + m_len = test_size / 4; while (m_len--) { - // ddr_pld_cache(p_src++) ; #ifdef DDR_PREFETCH_CACHE - __asm__ __volatile__ ("prfm PLDL1KEEP, [%0, #376]"::"r" (p_src)); + __asm__ __volatile__ ("prfm PLDL1KEEP, [%0, #376]" ::"r" (p_src)); #endif p_src++; - temp0 =( *p_src); + temp0 = (*p_src); m_len--; m_len--; m_len--; @@ -2320,244 +2222,226 @@ m_len--; m_len--; } - }while(--counter); + } while (--counter); *p_dest++ = temp0; *p_dest++ = *p_src; *p_dest++ = *p_src; *p_dest++ = *p_src; - time_end = get_us_time();//us + time_end = get_us_time(); //us - printf("\nread %d Kbytes use %dus\n \n",(unsigned int)(size_count/1000),( unsigned int )(time_end-time_start)); - printf("\nddr read bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start))); + printf("\nread %d Kbytes use %dus\n \n", (unsigned int)(size_count / 1000), (unsigned int)(time_end - time_start)); + printf("\nddr read bandwidth==%d MBYTE/S \n \n", (unsigned int)(size_count / (time_end - time_start))); return 0; } U_BOOT_CMD( - ddr_test_copy, 7, 1, do_ddr_test_copy, + ddr_test_copy, 7, 1, do_ddr_test_copy, "ddr_test_copy function", "ddr_test_copy 0x08000000 0x10000000 0x02000000 1 0 ? \n" -); + ); #define DDR_PATTERN_LOOP_1 32 #define DDR_PATTERN_LOOP_2 64 #define DDR_PATTERN_LOOP_3 96 - - - -static void ddr_write_pattern4_cross_talk_p(void *buff, unsigned int m_length) +static void ddr_write_pattern4_cross_talk_p(void *buff, unsigned int m_length) { - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; - //#define ddr_pattern_loop 32 - p = ( unsigned int *)buff; + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; - while (m_len) - { - // for(j=0;j<32;j++) + p = (unsigned int *)buff; + + while (m_len) { { - if (m_len >= 128*4) - n = 32*4; + if (m_len >= 128 * 4) + n = 32 * 4; else - n = m_len>>2; + n = m_len >> 2; - for (i = 0; i < n; i++) - { + for (i = 0; i < n; i++) { #ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; + ddr_pld_cache(p); #endif - switch (i) - { - case 0: - case 1: - case 2: - case 3: - case 8: - case 9: - case 10: - case 11: - case 16: - case 17: - case 18: - case 19: - case 24: - case 25: - case 26: - case 27: - // case 30: - *(p+i) = TDATA32F; - break; - case 4: - case 5: - case 6: - case 7: - case 12: - case 13: - case 14: - case 15: - case 20: - case 21: - case 22: - case 23: - case 28: - case 29: - case 30: - case 31: - // case 22: - *(p+i) = 0; - break; - case DDR_PATTERN_LOOP_1+0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_1+2: - case DDR_PATTERN_LOOP_1+3: - case DDR_PATTERN_LOOP_1+8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_1+10: - case DDR_PATTERN_LOOP_1+11: - case DDR_PATTERN_LOOP_1+16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_1+18: - case DDR_PATTERN_LOOP_1+19: - case DDR_PATTERN_LOOP_1+24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_1+26: - case DDR_PATTERN_LOOP_1+27: - // case 30: - *(p+i) = TDATA32A; - break; - case DDR_PATTERN_LOOP_1+4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_1+6: - case DDR_PATTERN_LOOP_1+7: - case DDR_PATTERN_LOOP_1+12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_1+14: - case DDR_PATTERN_LOOP_1+15: - case DDR_PATTERN_LOOP_1+20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_1+22: - case DDR_PATTERN_LOOP_1+23: - case DDR_PATTERN_LOOP_1+28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_1+30: - case DDR_PATTERN_LOOP_1+31: - *(p+i) = TDATA325; - - - break; - case DDR_PATTERN_LOOP_2+0: - case DDR_PATTERN_LOOP_2+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_2+3: - *(p+i) =0xfe01fe01; - break; - case DDR_PATTERN_LOOP_2+4: - case DDR_PATTERN_LOOP_2+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_2+7: - *(p+i) =0xfd02fd02; - break; - case DDR_PATTERN_LOOP_2+8: - case DDR_PATTERN_LOOP_2+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_2+11: - *(p+i) =0xfb04fb04; - break; - case DDR_PATTERN_LOOP_2+12: - case DDR_PATTERN_LOOP_2+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_2+15: - *(p+i) =0xf708f708; - break; - case DDR_PATTERN_LOOP_2+16: - case DDR_PATTERN_LOOP_2+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_2+19: - *(p+i) =0xef10ef10; - break; - case DDR_PATTERN_LOOP_2+20: - case DDR_PATTERN_LOOP_2+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_2+23: - *(p+i) =0xdf20df20; - break; - case DDR_PATTERN_LOOP_2+24: - case DDR_PATTERN_LOOP_2+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_2+27: - *(p+i) =0xbf40bf40; - break; - case DDR_PATTERN_LOOP_2+28: - case DDR_PATTERN_LOOP_2+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_2+31: - *(p+i) =0x7f807f80; - break; - case DDR_PATTERN_LOOP_3+0: - case DDR_PATTERN_LOOP_3+1: - case DDR_PATTERN_LOOP_3+2: - case DDR_PATTERN_LOOP_3+3: - *(p+i) =0x00000100; - break; - case DDR_PATTERN_LOOP_3+4: - case DDR_PATTERN_LOOP_3+5: - case DDR_PATTERN_LOOP_3+6: - case DDR_PATTERN_LOOP_3+7: - *(p+i) =0x00000200; - break; - case DDR_PATTERN_LOOP_3+8: - case DDR_PATTERN_LOOP_3+9: - case DDR_PATTERN_LOOP_3+10: - case DDR_PATTERN_LOOP_3+11: - *(p+i) =0x00000400; - break; - case DDR_PATTERN_LOOP_3+12: - case DDR_PATTERN_LOOP_3+13: - case DDR_PATTERN_LOOP_3+14: - case DDR_PATTERN_LOOP_3+15: - *(p+i) =0x00000800; - break; - case DDR_PATTERN_LOOP_3+16: - case DDR_PATTERN_LOOP_3+17: - case DDR_PATTERN_LOOP_3+18: - case DDR_PATTERN_LOOP_3+19: - *(p+i) =0x00001000; - break; - case DDR_PATTERN_LOOP_3+20: - case DDR_PATTERN_LOOP_3+21: - case DDR_PATTERN_LOOP_3+22: - case DDR_PATTERN_LOOP_3+23: - *(p+i) =0x00002000; - break; - case DDR_PATTERN_LOOP_3+24: - case DDR_PATTERN_LOOP_3+25: - case DDR_PATTERN_LOOP_3+26: - case DDR_PATTERN_LOOP_3+27: - *(p+i) =0x00004000; - break; - case DDR_PATTERN_LOOP_3+28: - case DDR_PATTERN_LOOP_3+29: - case DDR_PATTERN_LOOP_3+30: - case DDR_PATTERN_LOOP_3+31: - *(p+i) =0x00008000; - break; - - + switch (i) { + case 0: + case 1: + case 2: + case 3: + case 8: + case 9: + case 10: + case 11: + case 16: + case 17: + case 18: + case 19: + case 24: + case 25: + case 26: + case 27: + *(p + i) = TDATA32F; + break; + case 4: + case 5: + case 6: + case 7: + case 12: + case 13: + case 14: + case 15: + case 20: + case 21: + case 22: + case 23: + case 28: + case 29: + case 30: + case 31: + *(p + i) = 0; + break; + case DDR_PATTERN_LOOP_1 + 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_1 + 2: + case DDR_PATTERN_LOOP_1 + 3: + case DDR_PATTERN_LOOP_1 + 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_1 + 10: + case DDR_PATTERN_LOOP_1 + 11: + case DDR_PATTERN_LOOP_1 + 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_1 + 18: + case DDR_PATTERN_LOOP_1 + 19: + case DDR_PATTERN_LOOP_1 + 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_1 + 26: + case DDR_PATTERN_LOOP_1 + 27: + *(p + i) = TDATA32A; + break; + case DDR_PATTERN_LOOP_1 + 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_1 + 6: + case DDR_PATTERN_LOOP_1 + 7: + case DDR_PATTERN_LOOP_1 + 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_1 + 14: + case DDR_PATTERN_LOOP_1 + 15: + case DDR_PATTERN_LOOP_1 + 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_1 + 22: + case DDR_PATTERN_LOOP_1 + 23: + case DDR_PATTERN_LOOP_1 + 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_1 + 30: + case DDR_PATTERN_LOOP_1 + 31: + *(p + i) = TDATA325; + break; + case DDR_PATTERN_LOOP_2 + 0: + case DDR_PATTERN_LOOP_2 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_2 + 3: + *(p + i) = 0xfe01fe01; + break; + case DDR_PATTERN_LOOP_2 + 4: + case DDR_PATTERN_LOOP_2 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_2 + 7: + *(p + i) = 0xfd02fd02; + break; + case DDR_PATTERN_LOOP_2 + 8: + case DDR_PATTERN_LOOP_2 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_2 + 11: + *(p + i) = 0xfb04fb04; + break; + case DDR_PATTERN_LOOP_2 + 12: + case DDR_PATTERN_LOOP_2 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_2 + 15: + *(p + i) = 0xf708f708; + break; + case DDR_PATTERN_LOOP_2 + 16: + case DDR_PATTERN_LOOP_2 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_2 + 19: + *(p + i) = 0xef10ef10; + break; + case DDR_PATTERN_LOOP_2 + 20: + case DDR_PATTERN_LOOP_2 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_2 + 23: + *(p + i) = 0xdf20df20; + break; + case DDR_PATTERN_LOOP_2 + 24: + case DDR_PATTERN_LOOP_2 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_2 + 27: + *(p + i) = 0xbf40bf40; + break; + case DDR_PATTERN_LOOP_2 + 28: + case DDR_PATTERN_LOOP_2 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_2 + 31: + *(p + i) = 0x7f807f80; + break; + case DDR_PATTERN_LOOP_3 + 0: + case DDR_PATTERN_LOOP_3 + 1: + case DDR_PATTERN_LOOP_3 + 2: + case DDR_PATTERN_LOOP_3 + 3: + *(p + i) = 0x00000100; + break; + case DDR_PATTERN_LOOP_3 + 4: + case DDR_PATTERN_LOOP_3 + 5: + case DDR_PATTERN_LOOP_3 + 6: + case DDR_PATTERN_LOOP_3 + 7: + *(p + i) = 0x00000200; + break; + case DDR_PATTERN_LOOP_3 + 8: + case DDR_PATTERN_LOOP_3 + 9: + case DDR_PATTERN_LOOP_3 + 10: + case DDR_PATTERN_LOOP_3 + 11: + *(p + i) = 0x00000400; + break; + case DDR_PATTERN_LOOP_3 + 12: + case DDR_PATTERN_LOOP_3 + 13: + case DDR_PATTERN_LOOP_3 + 14: + case DDR_PATTERN_LOOP_3 + 15: + *(p + i) = 0x00000800; + break; + case DDR_PATTERN_LOOP_3 + 16: + case DDR_PATTERN_LOOP_3 + 17: + case DDR_PATTERN_LOOP_3 + 18: + case DDR_PATTERN_LOOP_3 + 19: + *(p + i) = 0x00001000; + break; + case DDR_PATTERN_LOOP_3 + 20: + case DDR_PATTERN_LOOP_3 + 21: + case DDR_PATTERN_LOOP_3 + 22: + case DDR_PATTERN_LOOP_3 + 23: + *(p + i) = 0x00002000; + break; + case DDR_PATTERN_LOOP_3 + 24: + case DDR_PATTERN_LOOP_3 + 25: + case DDR_PATTERN_LOOP_3 + 26: + case DDR_PATTERN_LOOP_3 + 27: + *(p + i) = 0x00004000; + break; + case DDR_PATTERN_LOOP_3 + 28: + case DDR_PATTERN_LOOP_3 + 29: + case DDR_PATTERN_LOOP_3 + 30: + case DDR_PATTERN_LOOP_3 + 31: + *(p + i) = 0x00008000; + break; } } - if (m_len >( 128*4)) - { - m_len -=( 128*4); - p += 32*4; - } - else - { - p += (m_len>>2); + if (m_len > (128 * 4)) { + m_len -= (128 * 4); + p += 32 * 4; + } else { + p += (m_len >> 2); m_len = 0; break; } @@ -2565,1270 +2449,522 @@ } } -static void ddr_write_pattern4_cross_talk_p2(void *buff, unsigned int m_length) +static void ddr_write_pattern4_cross_talk_p2(void *buff, unsigned int m_length) { - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; - //#define ddr_pattern_loop 32 - p = ( unsigned int *)buff; + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; - while (m_len) - { - // for(j=0;j<32;j++) + p = (unsigned int *)buff; + + while (m_len) { { - if (m_len >= 128*4) - n = 32*4; + if (m_len >= 128 * 4) + n = 32 * 4; else - n = m_len>>2; + n = m_len >> 2; - for (i = 0; i < n; i++) - { + for (i = 0; i < n; i++) { #ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; + ddr_pld_cache(p); #endif - switch (i) - { + switch (i) { + case 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_3 + 3: + *(p + i) = 0xfe01fe01; + break; + case 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_3 + 7: + *(p + i) = 0xfd02fd02; + break; - case 0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_3+3: - *(p+i) = 0xfe01fe01; - break; - case 4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_3+7: - *(p+i) = 0xfd02fd02; - break; + case 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_3 + 11: + *(p + i) = 0xfb04fb04; + break; - case 8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_3+11: - *(p+i) = 0xfb04fb04; - break; + case 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_3 + 15: + *(p + i) = 0xf708f708; + break; - case 12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_3+15: - *(p+i) = 0xf708f708; - break; + case 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_3 + 19: + *(p + i) = 0xef10ef10; + break; - case 16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_3+19: - *(p+i) = 0xef10ef10; - break; + case 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_3 + 23: + *(p + i) = 0xdf20df20; + break; - case 20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_3+23: - *(p+i) = 0xdf20df20; - break; + case 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_3 + 27: + *(p + i) = 0xbf40bf40; + break; - case 24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_3+27: - *(p+i) = 0xbf40bf40; - break; - - case 28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_3+31: - *(p+i) = 0x7f807f80; - break; + case 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_3 + 31: + *(p + i) = 0x7f807f80; + break; - default: + default: - *(p+i) = 0xff00ff00; - break; + *(p + i) = 0xff00ff00; + break; - break; - - + break; } } - if (m_len >( 128*4)) - { - m_len -=( 128*4); - p += 32*4; - } - else - { - p += (m_len>>2); + if (m_len > (128 * 4)) { + m_len -= (128 * 4); + p += 32 * 4; + } else { + p += (m_len >> 2); m_len = 0; break; } } } } -static void ddr_read_pattern4_cross_talk_p(void *buff, unsigned int m_length) + +static void ddr_read_pattern4_cross_talk_p(void *buff, unsigned int m_length) { - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; - p = ( unsigned int *)buff; + p = (unsigned int *)buff; - while (m_len) - { - // for(j=0;j<32;j++) + while (m_len) { { - if (m_len >= 128*4) - n = 32*4; + if (m_len >= 128 * 4) + n = 32 * 4; else - n = m_len>>2; + n = m_len >> 2; - for (i = 0; i < n; i++) - { + for (i = 0; i < n; i++) { #ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; + ddr_pld_cache(p); #endif - if ((error_outof_count_flag) && (error_count)) - { + if ((error_outof_count_flag) && (error_count)) { printf("Error data out of count"); - m_len=0; + m_len = 0; break; } - switch (i) - { - - case 0: - case 1: - case 2: - case 3: - case 8: - case 9: - case 10: - case 11: - case 16: - case 17: - case 18: - case 19: - case 24: - case 25: - case 26: - case 27: - // case 30: - // *(p+i) = TDATA32F; - if (*(p+i) != TDATA32F) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); - break; - } + switch (i) { + case 0: + case 1: + case 2: + case 3: + case 8: + case 9: + case 10: + case 11: + case 16: + case 17: + case 18: + case 19: + case 24: + case 25: + case 26: + case 27: + if (*(p + i) != TDATA32F) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F); break; - case 4: - case 5: - case 6: - case 7: - case 12: - case 13: - case 14: - case 15: - case 20: - case 21: - case 22: - case 23: - case 28: - case 29: - case 30: - case 31: - // case 22: - // *(p+i) = 0; - if (*(p+i) != 0) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0); - break;} + } + break; + case 4: + case 5: + case 6: + case 7: + case 12: + case 13: + case 14: + case 15: + case 20: + case 21: + case 22: + case 23: + case 28: + case 29: + case 30: + case 31: + if (*(p + i) != 0) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0); break; - case DDR_PATTERN_LOOP_1+0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_1+2: - case DDR_PATTERN_LOOP_1+3: - case DDR_PATTERN_LOOP_1+8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_1+10: - case DDR_PATTERN_LOOP_1+11: - case DDR_PATTERN_LOOP_1+16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_1+18: - case DDR_PATTERN_LOOP_1+19: - case DDR_PATTERN_LOOP_1+24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_1+26: - case DDR_PATTERN_LOOP_1+27: - // case 30: - // *(p+i) = TDATA32A; - if (*(p+i) != TDATA32A) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A); - break; - } + } + break; + case DDR_PATTERN_LOOP_1 + 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_1 + 2: + case DDR_PATTERN_LOOP_1 + 3: + case DDR_PATTERN_LOOP_1 + 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_1 + 10: + case DDR_PATTERN_LOOP_1 + 11: + case DDR_PATTERN_LOOP_1 + 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_1 + 18: + case DDR_PATTERN_LOOP_1 + 19: + case DDR_PATTERN_LOOP_1 + 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_1 + 26: + case DDR_PATTERN_LOOP_1 + 27: + if (*(p + i) != TDATA32A) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32A); break; - case DDR_PATTERN_LOOP_1+4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_1+6: - case DDR_PATTERN_LOOP_1+7: - case DDR_PATTERN_LOOP_1+12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_1+14: - case DDR_PATTERN_LOOP_1+15: - case DDR_PATTERN_LOOP_1+20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_1+22: - case DDR_PATTERN_LOOP_1+23: - case DDR_PATTERN_LOOP_1+28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_1+30: - case DDR_PATTERN_LOOP_1+31: - // *(p+i) = TDATA325; - if (*(p+i) != TDATA325) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325); - break; - } + } + break; + case DDR_PATTERN_LOOP_1 + 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_1 + 6: + case DDR_PATTERN_LOOP_1 + 7: + case DDR_PATTERN_LOOP_1 + 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_1 + 14: + case DDR_PATTERN_LOOP_1 + 15: + case DDR_PATTERN_LOOP_1 + 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_1 + 22: + case DDR_PATTERN_LOOP_1 + 23: + case DDR_PATTERN_LOOP_1 + 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_1 + 30: + case DDR_PATTERN_LOOP_1 + 31: + if (*(p + i) != TDATA325) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA325); break; - case DDR_PATTERN_LOOP_2+0: - case DDR_PATTERN_LOOP_2+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_2+3: - // *(p+i) =0xfe01fe01; - if (*(p+i) !=0xfe01fe01) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01); - break; - } + } + break; + case DDR_PATTERN_LOOP_2 + 0: + case DDR_PATTERN_LOOP_2 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_2 + 3: + if (*(p + i) != 0xfe01fe01) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfe01fe01); break; - case DDR_PATTERN_LOOP_2+4: - case DDR_PATTERN_LOOP_2+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_2+7: - // *(p+i) =0xfd02fd02; - if (*(p+i) != 0xfd02fd02) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02); - break; - } + } + break; + case DDR_PATTERN_LOOP_2 + 4: + case DDR_PATTERN_LOOP_2 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_2 + 7: + if (*(p + i) != 0xfd02fd02) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfd02fd02); break; - case DDR_PATTERN_LOOP_2+8: - case DDR_PATTERN_LOOP_2+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_2+11: - // *(p+i) =0xfb04fb04; - if (*(p+i) != 0xfb04fb04) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04); - break; - } + } + break; + case DDR_PATTERN_LOOP_2 + 8: + case DDR_PATTERN_LOOP_2 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_2 + 11: + if (*(p + i) != 0xfb04fb04) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfb04fb04); break; - case DDR_PATTERN_LOOP_2+12: - case DDR_PATTERN_LOOP_2+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_2+15: - // *(p+i) =0xf7b08f708; - if (*(p+i) != 0xf708f708) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708); - break; - } + } + break; + case DDR_PATTERN_LOOP_2 + 12: + case DDR_PATTERN_LOOP_2 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_2 + 15: + if (*(p + i) != 0xf708f708) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xf708f708); break; - case DDR_PATTERN_LOOP_2+16: - case DDR_PATTERN_LOOP_2+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_2+19: - // *(p+i) =0xef10ef10; - if (*(p+i) != 0xef10ef10) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xef10ef10); - break; - } + } + break; + case DDR_PATTERN_LOOP_2 + 16: + case DDR_PATTERN_LOOP_2 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_2 + 19: + if (*(p + i) != 0xef10ef10) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xef10ef10); break; - case DDR_PATTERN_LOOP_2+20: - case DDR_PATTERN_LOOP_2+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_2+23: - // *(p+i) =0xdf20df20; - if (*(p+i) != 0xdf20df20) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xdf20df20); - break; - } + } + break; + case DDR_PATTERN_LOOP_2 + 20: + case DDR_PATTERN_LOOP_2 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_2 + 23: + if (*(p + i) != 0xdf20df20) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xdf20df20); break; - case DDR_PATTERN_LOOP_2+24: - case DDR_PATTERN_LOOP_2+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_2+27: - // *(p+i) =0xbf40bf40; - if (*(p+i) != 0xbf40bf40) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xbf40bf40); - break; - } + } + break; + case DDR_PATTERN_LOOP_2 + 24: + case DDR_PATTERN_LOOP_2 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_2 + 27: + if (*(p + i) != 0xbf40bf40) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xbf40bf40); break; - case DDR_PATTERN_LOOP_2+28: - case DDR_PATTERN_LOOP_2+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_2+31: - // *(p+i) =0x7f807f80; - if (*(p+i) != 0x7f807f80) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x7f807f80); - break; - - } + } + break; + case DDR_PATTERN_LOOP_2 + 28: + case DDR_PATTERN_LOOP_2 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_2 + 31: + if (*(p + i) != 0x7f807f80) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x7f807f80); break; - case DDR_PATTERN_LOOP_3+0: - case DDR_PATTERN_LOOP_3+1: - case DDR_PATTERN_LOOP_3+2: - case DDR_PATTERN_LOOP_3+3: - // *(p+i) =0x00000100; - if (*(p+i) != 0x00000100) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000100); - break; - } + } + break; + case DDR_PATTERN_LOOP_3 + 0: + case DDR_PATTERN_LOOP_3 + 1: + case DDR_PATTERN_LOOP_3 + 2: + case DDR_PATTERN_LOOP_3 + 3: + if (*(p + i) != 0x00000100) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00000100); break; - case DDR_PATTERN_LOOP_3+4: - case DDR_PATTERN_LOOP_3+5: - case DDR_PATTERN_LOOP_3+6: - case DDR_PATTERN_LOOP_3+7: - // *(p+i) =0x00000100; - if (*(p+i) != 0x00000200) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000200); - break; - } + } + break; + case DDR_PATTERN_LOOP_3 + 4: + case DDR_PATTERN_LOOP_3 + 5: + case DDR_PATTERN_LOOP_3 + 6: + case DDR_PATTERN_LOOP_3 + 7: + if (*(p + i) != 0x00000200) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00000200); break; - case DDR_PATTERN_LOOP_3+8: - case DDR_PATTERN_LOOP_3+9: - case DDR_PATTERN_LOOP_3+10: - case DDR_PATTERN_LOOP_3+11: - // *(p+i) =0x00000100; - if (*(p+i) != 0x00000400) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000400); - break; - } + } + break; + case DDR_PATTERN_LOOP_3 + 8: + case DDR_PATTERN_LOOP_3 + 9: + case DDR_PATTERN_LOOP_3 + 10: + case DDR_PATTERN_LOOP_3 + 11: + if (*(p + i) != 0x00000400) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00000400); break; - case DDR_PATTERN_LOOP_3+12: - case DDR_PATTERN_LOOP_3+13: - case DDR_PATTERN_LOOP_3+14: - case DDR_PATTERN_LOOP_3+15: - // *(p+i) =0x00000100; - if (*(p+i) != 0x00000800) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000800); - break; - } + } + break; + case DDR_PATTERN_LOOP_3 + 12: + case DDR_PATTERN_LOOP_3 + 13: + case DDR_PATTERN_LOOP_3 + 14: + case DDR_PATTERN_LOOP_3 + 15: + if (*(p + i) != 0x00000800) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00000800); break; - case DDR_PATTERN_LOOP_3+16: - case DDR_PATTERN_LOOP_3+17: - case DDR_PATTERN_LOOP_3+18: - case DDR_PATTERN_LOOP_3+19: - // *(p+i) =0xfffffeff; - if (*(p+i) != 0x00001000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00001000); - break; - } + } + break; + case DDR_PATTERN_LOOP_3 + 16: + case DDR_PATTERN_LOOP_3 + 17: + case DDR_PATTERN_LOOP_3 + 18: + case DDR_PATTERN_LOOP_3 + 19: + if (*(p + i) != 0x00001000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00001000); break; - case DDR_PATTERN_LOOP_3+20: - case DDR_PATTERN_LOOP_3+21: - case DDR_PATTERN_LOOP_3+22: - case DDR_PATTERN_LOOP_3+23: - // *(p+i) =0xfffffeff; - if (*(p+i) != 0x00002000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00002000); - - } break; - case DDR_PATTERN_LOOP_3+24: - case DDR_PATTERN_LOOP_3+25: - case DDR_PATTERN_LOOP_3+26: - case DDR_PATTERN_LOOP_3+27: - // *(p+i) =0xfffffeff; - if (*(p+i) != 0x00004000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00004000); - break; - } + } + break; + case DDR_PATTERN_LOOP_3 + 20: + case DDR_PATTERN_LOOP_3 + 21: + case DDR_PATTERN_LOOP_3 + 22: + case DDR_PATTERN_LOOP_3 + 23: + if (*(p + i) != 0x00002000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00002000); + } + break; + case DDR_PATTERN_LOOP_3 + 24: + case DDR_PATTERN_LOOP_3 + 25: + case DDR_PATTERN_LOOP_3 + 26: + case DDR_PATTERN_LOOP_3 + 27: + if (*(p + i) != 0x00004000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00004000); break; - case DDR_PATTERN_LOOP_3+28: - case DDR_PATTERN_LOOP_3+29: - case DDR_PATTERN_LOOP_3+30: - case DDR_PATTERN_LOOP_3+31: - // *(p+i) =0xfffffeff; - if (*(p+i) != 0x00008000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00008000); - break; - } + } + break; + case DDR_PATTERN_LOOP_3 + 28: + case DDR_PATTERN_LOOP_3 + 29: + case DDR_PATTERN_LOOP_3 + 30: + case DDR_PATTERN_LOOP_3 + 31: + if (*(p + i) != 0x00008000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00008000); break; - - - + } + break; } } - if (m_len > 128*4) - { - m_len -= 128*4; - p += 32*4; - } - else - { - p += (m_len>>2); + if (m_len > 128 * 4) { + m_len -= 128 * 4; + p += 32 * 4; + } else { + p += (m_len >> 2); m_len = 0; break; } } } } -//*/ -static void ddr_read_pattern4_cross_talk_p2(void *buff, unsigned int m_length) + +static void ddr_read_pattern4_cross_talk_p2(void *buff, unsigned int m_length) { - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; - p = ( unsigned int *)buff; + p = (unsigned int *)buff; - while (m_len) - { - // for(j=0;j<32;j++) + while (m_len) { { - if (m_len >= 128*4) - n = 32*4; + if (m_len >= 128 * 4) + n = 32 * 4; else - n = m_len>>2; + n = m_len >> 2; - for (i = 0; i < n; i++) - { + for (i = 0; i < n; i++) { #ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; + ddr_pld_cache(p); #endif - if ((error_outof_count_flag) && (error_count)) - { + if ((error_outof_count_flag) && (error_count)) { printf("Error data out of count"); - m_len=0; + m_len = 0; break; } - switch (i) - { - case 0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_3+3: - // *(p+i) = 0xfe01fe01; - if (*(p+i) != 0xfe01fe01) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01); - break; - } + switch (i) { + case 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_3 + 3: + if (*(p + i) != 0xfe01fe01) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfe01fe01); break; - case 4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_3+7: - // *(p+i) = 0xfd02fd02; - if (*(p+i) != 0xfd02fd02) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02); - break; - } + } + break; + case 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_3 + 7: + if (*(p + i) != 0xfd02fd02) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfd02fd02); break; + } + break; - case 8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_3+11: - // *(p+i) = 0xfb04fb04; - if (*(p+i) != 0xfb04fb04) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04); - break; - } + case 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_3 + 11: + if (*(p + i) != 0xfb04fb04) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfb04fb04); break; + } + break; - case 12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_3+15: - // *(p+i) = 0xf708f708; - if (*(p+i) != 0xf708f708) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708); - break; - } + case 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_3 + 15: + if (*(p + i) != 0xf708f708) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xf708f708); break; + } + break; - case 16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_3+19: - // *(p+i) = 0xef10ef10; - if (*(p+i) != 0xef10ef10) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xef10ef10); - break; - } + case 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_3 + 19: + if (*(p + i) != 0xef10ef10) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xef10ef10); break; + } + break; - case 20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_3+23: - // *(p+i) = 0xdf20df20; - if (*(p+i) != 0xdf20df20) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xdf20df20); - break; - } + case 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_3 + 23: + if (*(p + i) != 0xdf20df20) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xdf20df20); break; + } + break; - case 24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_3+27: - // *(p+i) = 0xbf40bf40; - if (*(p+i) != 0xbf40bf40) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xbf40bf40); - break; - } + case 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_3 + 27: + if (*(p + i) != 0xbf40bf40) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xbf40bf40); break; - case 28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_3+31: - // *(p+i) = 0x7f807f80; - if (*(p+i) != 0x7f807f80) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x7f807f80); - break; - } + } + break; + case 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_3 + 31: + if (*(p + i) != 0x7f807f80) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x7f807f80); break; + } + break; - default: - - // *(p+i) = 0xff00ff00; - if (*(p+i) != 0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00); - break; - } + default: + if (*(p + i) != 0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ff00); break; + } + break; - break; - - - } - } - - if (m_len > 128*4) - { - m_len -= 128*4; - p += 32*4; - } - else - { - p += (m_len>>2); - m_len = 0; - break; - } - } - } -} - -static void ddr_write_pattern4_cross_talk_n(void *buff, unsigned int m_length) -{ - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; - //#define ddr_pattern_loop 32 - p = ( unsigned int *)buff; - - while (m_len) - { - // for(j=0;j<32;j++) - { - if (m_len >= 128*4) - n = 32*4; - else - n = m_len>>2; - - for (i = 0; i < n; i++) - { -#ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; -#endif - switch (i) - { - case 0: - case 1: - case 2: - case 3: - case 8: - case 9: - case 10: - case 11: - case 16: - case 17: - case 18: - case 19: - case 24: - case 25: - case 26: - case 27: - // case 30: - *(p+i) = ~TDATA32F; - break; - case 4: - case 5: - case 6: - case 7: - case 12: - case 13: - case 14: - case 15: - case 20: - case 21: - case 22: - case 23: - case 28: - case 29: - case 30: - case 31: - // case 22: - *(p+i) = ~0; - break; - case DDR_PATTERN_LOOP_1+0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_1+2: - case DDR_PATTERN_LOOP_1+3: - case DDR_PATTERN_LOOP_1+8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_1+10: - case DDR_PATTERN_LOOP_1+11: - case DDR_PATTERN_LOOP_1+16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_1+18: - case DDR_PATTERN_LOOP_1+19: - case DDR_PATTERN_LOOP_1+24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_1+26: - case DDR_PATTERN_LOOP_1+27: - // case 30: - *(p+i) = ~TDATA32A; - break; - case DDR_PATTERN_LOOP_1+4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_1+6: - case DDR_PATTERN_LOOP_1+7: - case DDR_PATTERN_LOOP_1+12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_1+14: - case DDR_PATTERN_LOOP_1+15: - case DDR_PATTERN_LOOP_1+20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_1+22: - case DDR_PATTERN_LOOP_1+23: - case DDR_PATTERN_LOOP_1+28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_1+30: - case DDR_PATTERN_LOOP_1+31: - *(p+i) =~TDATA325; - - - break; - case DDR_PATTERN_LOOP_2+0: - case DDR_PATTERN_LOOP_2+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_2+3: - *(p+i) =~0xfe01fe01; - break; - case DDR_PATTERN_LOOP_2+4: - case DDR_PATTERN_LOOP_2+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_2+7: - *(p+i) =~0xfd02fd02; - break; - case DDR_PATTERN_LOOP_2+8: - case DDR_PATTERN_LOOP_2+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_2+11: - *(p+i) =~0xfb04fb04; - break; - case DDR_PATTERN_LOOP_2+12: - case DDR_PATTERN_LOOP_2+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_2+15: - *(p+i) =~0xf708f708; - break; - case DDR_PATTERN_LOOP_2+16: - case DDR_PATTERN_LOOP_2+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_2+19: - *(p+i) =~0xef10ef10; - break; - case DDR_PATTERN_LOOP_2+20: - case DDR_PATTERN_LOOP_2+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_2+23: - *(p+i) =~0xdf20df20; - break; - case DDR_PATTERN_LOOP_2+24: - case DDR_PATTERN_LOOP_2+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_2+27: - *(p+i) =~0xbf40bf40; - break; - case DDR_PATTERN_LOOP_2+28: - case DDR_PATTERN_LOOP_2+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_2+31: - *(p+i) =~0x7f807f80; - break; - case DDR_PATTERN_LOOP_3+0: - case DDR_PATTERN_LOOP_3+1: - case DDR_PATTERN_LOOP_3+2: - case DDR_PATTERN_LOOP_3+3: - *(p+i) =~0x00000100; - break; - case DDR_PATTERN_LOOP_3+4: - case DDR_PATTERN_LOOP_3+5: - case DDR_PATTERN_LOOP_3+6: - case DDR_PATTERN_LOOP_3+7: - *(p+i) =~0x00000200; - break; - case DDR_PATTERN_LOOP_3+8: - case DDR_PATTERN_LOOP_3+9: - case DDR_PATTERN_LOOP_3+10: - case DDR_PATTERN_LOOP_3+11: - *(p+i) =~0x00000400; - break; - case DDR_PATTERN_LOOP_3+12: - case DDR_PATTERN_LOOP_3+13: - case DDR_PATTERN_LOOP_3+14: - case DDR_PATTERN_LOOP_3+15: - *(p+i) =~0x00000800; - break; - case DDR_PATTERN_LOOP_3+16: - case DDR_PATTERN_LOOP_3+17: - case DDR_PATTERN_LOOP_3+18: - case DDR_PATTERN_LOOP_3+19: - *(p+i) =~0x00001000; - break; - case DDR_PATTERN_LOOP_3+20: - case DDR_PATTERN_LOOP_3+21: - case DDR_PATTERN_LOOP_3+22: - case DDR_PATTERN_LOOP_3+23: - *(p+i) =~0x00002000; - break; - case DDR_PATTERN_LOOP_3+24: - case DDR_PATTERN_LOOP_3+25: - case DDR_PATTERN_LOOP_3+26: - case DDR_PATTERN_LOOP_3+27: - *(p+i) =~0x00004000; - break; - case DDR_PATTERN_LOOP_3+28: - case DDR_PATTERN_LOOP_3+29: - case DDR_PATTERN_LOOP_3+30: - case DDR_PATTERN_LOOP_3+31: - *(p+i) =~0x00008000; - break; - - - } - } - - if (m_len >( 128*4)) - { - m_len -=( 128*4); - p += 32*4; - } - else - { - p += (m_len>>2); - m_len = 0; - break; - } - } - } -} - - -static void ddr_write_pattern4_cross_talk_n2(void *buff, unsigned int m_length) -{ - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; - //#define ddr_pattern_loop 32 - p = ( unsigned int *)buff; - - while (m_len) - { - // for(j=0;j<32;j++) - { - if (m_len >= 128*4) - n = 32*4; - else - n = m_len>>2; - - for (i = 0; i < n; i++) - { -#ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; -#endif - - switch (i) - { - case 0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_3+3: - *(p+i) = ~0xfe01fe01; - break; - case 4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_3+7: - *(p+i) = ~0xfd02fd02; - break; - - case 8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_3+11: - *(p+i) = ~0xfb04fb04; - break; - - case 12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_3+15: - *(p+i) = ~0xf708f708; - break; - - case 16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_3+19: - *(p+i) = ~0xef10ef10; - break; - - case 20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_3+23: - *(p+i) = ~0xdf20df20; - break; - - case 24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_3+27: - *(p+i) =~0xbf40bf40; - break; - case 28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_3+31: - *(p+i) = ~0x7f807f80; - break; - - - default: - - *(p+i) = ~0xff00ff00; - break; - - break; - - - } - } - - if (m_len >( 128*4)) - { - m_len -=( 128*4); - p += 32*4; - } - else - { - p += (m_len>>2); - m_len = 0; - break; - } - } - } -} - -static void ddr_read_pattern4_cross_talk_n(void *buff, unsigned int m_length) -{ - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; - - p = ( unsigned int *)buff; - - while (m_len) - { - // for(j=0;j<32;j++) - { - if (m_len >= 128*4) - n = 32*4; - else - n = m_len>>2; - - for (i = 0; i < n; i++) - { -#ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; -#endif - if ((error_outof_count_flag) && (error_count)) - { - printf("Error data out of count"); - m_len=0; break; } - switch (i) - { - case 0: - case 1: - case 2: - case 3: - case 8: - case 9: - case 10: - case 11: - case 16: - case 17: - case 18: - case 19: - case 24: - case 25: - case 26: - case 27: - // case 30: - // *(p+i) = TDATA32F; - if (*(p+i) !=~TDATA32F) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~TDATA32F); - break; - } - break; - case 4: - case 5: - case 6: - case 7: - case 12: - case 13: - case 14: - case 15: - case 20: - case 21: - case 22: - case 23: - case 28: - case 29: - case 30: - case 31: - // case 22: - // *(p+i) = 0; - if (*(p+i) !=~0) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0); - } - break; - case DDR_PATTERN_LOOP_1+0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_1+2: - case DDR_PATTERN_LOOP_1+3: - case DDR_PATTERN_LOOP_1+8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_1+10: - case DDR_PATTERN_LOOP_1+11: - case DDR_PATTERN_LOOP_1+16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_1+18: - case DDR_PATTERN_LOOP_1+19: - case DDR_PATTERN_LOOP_1+24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_1+26: - case DDR_PATTERN_LOOP_1+27: - // case 30: - // *(p+i) = TDATA32A; - if (*(p+i) != ~TDATA32A) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),~TDATA32A); - } - break; - case DDR_PATTERN_LOOP_1+4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_1+6: - case DDR_PATTERN_LOOP_1+7: - case DDR_PATTERN_LOOP_1+12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_1+14: - case DDR_PATTERN_LOOP_1+15: - case DDR_PATTERN_LOOP_1+20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_1+22: - case DDR_PATTERN_LOOP_1+23: - case DDR_PATTERN_LOOP_1+28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_1+30: - case DDR_PATTERN_LOOP_1+31: - // *(p+i) = TDATA325; - if (*(p+i) != ~TDATA325) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~TDATA325); - } - break; - case DDR_PATTERN_LOOP_2+0: - case DDR_PATTERN_LOOP_2+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_2+3: - // *(p+i) =0xfe01fe01; - if (*(p+i) !=~0xfe01fe01) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfe01fe01); - } - break; - case DDR_PATTERN_LOOP_2+4: - case DDR_PATTERN_LOOP_2+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_2+7: - // *(p+i) =0xfd02fd02; - if (*(p+i) != ~0xfd02fd02) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfd02fd02); - } - break; - - case DDR_PATTERN_LOOP_2+8: - case DDR_PATTERN_LOOP_2+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_2+11: - // *(p+i) =0xfb04fb04; - if (*(p+i) != ~0xfb04fb04) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfb04fb04); - } - break; - case DDR_PATTERN_LOOP_2+12: - case DDR_PATTERN_LOOP_2+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_2+15: - // *(p+i) =0xf7b08f708; - if (*(p+i) != ~0xf708f708) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xf708f708); - } - break; - case DDR_PATTERN_LOOP_2+16: - case DDR_PATTERN_LOOP_2+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_2+19: - // *(p+i) =0xef10ef10; - if (*(p+i) != ~0xef10ef10) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xef10ef10); - } - break; - case DDR_PATTERN_LOOP_2+20: - case DDR_PATTERN_LOOP_2+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_2+23: - // *(p+i) =0xdf20df20; - if (*(p+i) != ~0xdf20df20) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xdf20df20); - } - break; - case DDR_PATTERN_LOOP_2+24: - case DDR_PATTERN_LOOP_2+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_2+27: - // *(p+i) =0xbf40bf40; - if (*(p+i) != ~0xbf40bf40) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xbf40bf40); - } - break; - case DDR_PATTERN_LOOP_2+28: - case DDR_PATTERN_LOOP_2+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_2+31: - // *(p+i) =0x7f807f80; - if (*(p+i) != ~0x7f807f80) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x7f807f80); - } - break; - break; - case DDR_PATTERN_LOOP_3+0: - case DDR_PATTERN_LOOP_3+1: - case DDR_PATTERN_LOOP_3+2: - case DDR_PATTERN_LOOP_3+3: - // *(p+i) =0x00000100; - if (*(p+i) != ~0x00000100) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000100); - } - break; - case DDR_PATTERN_LOOP_3+4: - case DDR_PATTERN_LOOP_3+5: - case DDR_PATTERN_LOOP_3+6: - case DDR_PATTERN_LOOP_3+7: - // *(p+i) =0x00000100; - if (*(p+i) != ~0x00000200) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000200); - } - break; - case DDR_PATTERN_LOOP_3+8: - case DDR_PATTERN_LOOP_3+9: - case DDR_PATTERN_LOOP_3+10: - case DDR_PATTERN_LOOP_3+11: - // *(p+i) =0x00000100; - if (*(p+i) != ~0x00000400) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000400); - } - break; - case DDR_PATTERN_LOOP_3+12: - case DDR_PATTERN_LOOP_3+13: - case DDR_PATTERN_LOOP_3+14: - case DDR_PATTERN_LOOP_3+15: - // *(p+i) =0x00000100; - if (*(p+i) != ~0x00000800) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000800); - } - break; - case DDR_PATTERN_LOOP_3+16: - case DDR_PATTERN_LOOP_3+17: - case DDR_PATTERN_LOOP_3+18: - case DDR_PATTERN_LOOP_3+19: - // *(p+i) =0xfffffeff; - if (*(p+i) != ~0x00001000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00001000); - } - break; - case DDR_PATTERN_LOOP_3+20: - case DDR_PATTERN_LOOP_3+21: - case DDR_PATTERN_LOOP_3+22: - case DDR_PATTERN_LOOP_3+23: - // *(p+i) =0xfffffeff; - if (*(p+i) != ~0x00002000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00002000); - } - break; - case DDR_PATTERN_LOOP_3+24: - case DDR_PATTERN_LOOP_3+25: - case DDR_PATTERN_LOOP_3+26: - case DDR_PATTERN_LOOP_3+27: - // *(p+i) =0xfffffeff; - if (*(p+i) != ~0x00004000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00004000); - } - break; - case DDR_PATTERN_LOOP_3+28: - case DDR_PATTERN_LOOP_3+29: - case DDR_PATTERN_LOOP_3+30: - case DDR_PATTERN_LOOP_3+31: - // *(p+i) =0xfffffeff; - if (*(p+i) != ~0x00008000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00008000); - } - break; - - - - } } - if (m_len > 128*4) - { - m_len -= 128*4; - p += 32*4; - } - else - { - p += (m_len>>2); + if (m_len > 128 * 4) { + m_len -= 128 * 4; + p += 32 * 4; + } else { + p += (m_len >> 2); m_len = 0; break; } @@ -3836,815 +2972,707 @@ } } - -//*/ -static void ddr_read_pattern4_cross_talk_n2(void *buff, unsigned int m_length) +static void ddr_write_pattern4_cross_talk_n(void *buff, unsigned int m_length) { - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; - p = ( unsigned int *)buff; + p = (unsigned int *)buff; - while (m_len) - { - // for(j=0;j<32;j++) + while (m_len) { { - if (m_len >= 128*4) - n = 32*4; + if (m_len >= 128 * 4) + n = 32 * 4; else - n = m_len>>2; + n = m_len >> 2; - for (i = 0; i < n; i++) - { + for (i = 0; i < n; i++) { #ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; + ddr_pld_cache(p); #endif - if ((error_outof_count_flag) && (error_count)) - { + switch (i) { + case 0: + case 1: + case 2: + case 3: + case 8: + case 9: + case 10: + case 11: + case 16: + case 17: + case 18: + case 19: + case 24: + case 25: + case 26: + case 27: + *(p + i) = ~TDATA32F; + break; + case 4: + case 5: + case 6: + case 7: + case 12: + case 13: + case 14: + case 15: + case 20: + case 21: + case 22: + case 23: + case 28: + case 29: + case 30: + case 31: + *(p + i) = ~0; + break; + case DDR_PATTERN_LOOP_1 + 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_1 + 2: + case DDR_PATTERN_LOOP_1 + 3: + case DDR_PATTERN_LOOP_1 + 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_1 + 10: + case DDR_PATTERN_LOOP_1 + 11: + case DDR_PATTERN_LOOP_1 + 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_1 + 18: + case DDR_PATTERN_LOOP_1 + 19: + case DDR_PATTERN_LOOP_1 + 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_1 + 26: + case DDR_PATTERN_LOOP_1 + 27: + *(p + i) = ~TDATA32A; + break; + case DDR_PATTERN_LOOP_1 + 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_1 + 6: + case DDR_PATTERN_LOOP_1 + 7: + case DDR_PATTERN_LOOP_1 + 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_1 + 14: + case DDR_PATTERN_LOOP_1 + 15: + case DDR_PATTERN_LOOP_1 + 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_1 + 22: + case DDR_PATTERN_LOOP_1 + 23: + case DDR_PATTERN_LOOP_1 + 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_1 + 30: + case DDR_PATTERN_LOOP_1 + 31: + *(p + i) = ~TDATA325; + break; + case DDR_PATTERN_LOOP_2 + 0: + case DDR_PATTERN_LOOP_2 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_2 + 3: + *(p + i) = ~0xfe01fe01; + break; + case DDR_PATTERN_LOOP_2 + 4: + case DDR_PATTERN_LOOP_2 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_2 + 7: + *(p + i) = ~0xfd02fd02; + break; + case DDR_PATTERN_LOOP_2 + 8: + case DDR_PATTERN_LOOP_2 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_2 + 11: + *(p + i) = ~0xfb04fb04; + break; + case DDR_PATTERN_LOOP_2 + 12: + case DDR_PATTERN_LOOP_2 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_2 + 15: + *(p + i) = ~0xf708f708; + break; + case DDR_PATTERN_LOOP_2 + 16: + case DDR_PATTERN_LOOP_2 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_2 + 19: + *(p + i) = ~0xef10ef10; + break; + case DDR_PATTERN_LOOP_2 + 20: + case DDR_PATTERN_LOOP_2 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_2 + 23: + *(p + i) = ~0xdf20df20; + break; + case DDR_PATTERN_LOOP_2 + 24: + case DDR_PATTERN_LOOP_2 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_2 + 27: + *(p + i) = ~0xbf40bf40; + break; + case DDR_PATTERN_LOOP_2 + 28: + case DDR_PATTERN_LOOP_2 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_2 + 31: + *(p + i) = ~0x7f807f80; + break; + case DDR_PATTERN_LOOP_3 + 0: + case DDR_PATTERN_LOOP_3 + 1: + case DDR_PATTERN_LOOP_3 + 2: + case DDR_PATTERN_LOOP_3 + 3: + *(p + i) = ~0x00000100; + break; + case DDR_PATTERN_LOOP_3 + 4: + case DDR_PATTERN_LOOP_3 + 5: + case DDR_PATTERN_LOOP_3 + 6: + case DDR_PATTERN_LOOP_3 + 7: + *(p + i) = ~0x00000200; + break; + case DDR_PATTERN_LOOP_3 + 8: + case DDR_PATTERN_LOOP_3 + 9: + case DDR_PATTERN_LOOP_3 + 10: + case DDR_PATTERN_LOOP_3 + 11: + *(p + i) = ~0x00000400; + break; + case DDR_PATTERN_LOOP_3 + 12: + case DDR_PATTERN_LOOP_3 + 13: + case DDR_PATTERN_LOOP_3 + 14: + case DDR_PATTERN_LOOP_3 + 15: + *(p + i) = ~0x00000800; + break; + case DDR_PATTERN_LOOP_3 + 16: + case DDR_PATTERN_LOOP_3 + 17: + case DDR_PATTERN_LOOP_3 + 18: + case DDR_PATTERN_LOOP_3 + 19: + *(p + i) = ~0x00001000; + break; + case DDR_PATTERN_LOOP_3 + 20: + case DDR_PATTERN_LOOP_3 + 21: + case DDR_PATTERN_LOOP_3 + 22: + case DDR_PATTERN_LOOP_3 + 23: + *(p + i) = ~0x00002000; + break; + case DDR_PATTERN_LOOP_3 + 24: + case DDR_PATTERN_LOOP_3 + 25: + case DDR_PATTERN_LOOP_3 + 26: + case DDR_PATTERN_LOOP_3 + 27: + *(p + i) = ~0x00004000; + break; + case DDR_PATTERN_LOOP_3 + 28: + case DDR_PATTERN_LOOP_3 + 29: + case DDR_PATTERN_LOOP_3 + 30: + case DDR_PATTERN_LOOP_3 + 31: + *(p + i) = ~0x00008000; + break; + } + } + + if (m_len > (128 * 4)) { + m_len -= (128 * 4); + p += 32 * 4; + } else { + p += (m_len >> 2); + m_len = 0; + break; + } + } + } +} + +static void ddr_write_pattern4_cross_talk_n2(void *buff, unsigned int m_length) +{ + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; + + p = (unsigned int *)buff; + + while (m_len) { + { + if (m_len >= 128 * 4) + n = 32 * 4; + else + n = m_len >> 2; + + for (i = 0; i < n; i++) { +#ifdef DDR_PREFETCH_CACHE + ddr_pld_cache(p); +#endif + + switch (i) { + case 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_3 + 3: + *(p + i) = ~0xfe01fe01; + break; + case 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_3 + 7: + *(p + i) = ~0xfd02fd02; + break; + + case 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_3 + 11: + *(p + i) = ~0xfb04fb04; + break; + + case 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_3 + 15: + *(p + i) = ~0xf708f708; + break; + + case 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_3 + 19: + *(p + i) = ~0xef10ef10; + break; + + case 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_3 + 23: + *(p + i) = ~0xdf20df20; + break; + + case 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_3 + 27: + *(p + i) = ~0xbf40bf40; + break; + case 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_3 + 31: + *(p + i) = ~0x7f807f80; + break; + + + default: + + *(p + i) = ~0xff00ff00; + break; + + break; + } + } + + if (m_len > (128 * 4)) { + m_len -= (128 * 4); + p += 32 * 4; + } else { + p += (m_len >> 2); + m_len = 0; + break; + } + } + } +} + +static void ddr_read_pattern4_cross_talk_n(void *buff, unsigned int m_length) +{ + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; + + p = (unsigned int *)buff; + + while (m_len) { + { + if (m_len >= 128 * 4) + n = 32 * 4; + else + n = m_len >> 2; + + for (i = 0; i < n; i++) { +#ifdef DDR_PREFETCH_CACHE + ddr_pld_cache(p); +#endif + if ((error_outof_count_flag) && (error_count)) { printf("Error data out of count"); - m_len=0; + m_len = 0; + break; + } + switch (i) { + case 0: + case 1: + case 2: + case 3: + case 8: + case 9: + case 10: + case 11: + case 16: + case 17: + case 18: + case 19: + case 24: + case 25: + case 26: + case 27: + if (*(p + i) != ~TDATA32F) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~TDATA32F); + break; + } + break; + case 4: + case 5: + case 6: + case 7: + case 12: + case 13: + case 14: + case 15: + case 20: + case 21: + case 22: + case 23: + case 28: + case 29: + case 30: + case 31: + if (*(p + i) != ~0) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0); + } + break; + case DDR_PATTERN_LOOP_1 + 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_1 + 2: + case DDR_PATTERN_LOOP_1 + 3: + case DDR_PATTERN_LOOP_1 + 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_1 + 10: + case DDR_PATTERN_LOOP_1 + 11: + case DDR_PATTERN_LOOP_1 + 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_1 + 18: + case DDR_PATTERN_LOOP_1 + 19: + case DDR_PATTERN_LOOP_1 + 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_1 + 26: + case DDR_PATTERN_LOOP_1 + 27: + if (*(p + i) != ~TDATA32A) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~TDATA32A); + } + break; + case DDR_PATTERN_LOOP_1 + 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_1 + 6: + case DDR_PATTERN_LOOP_1 + 7: + case DDR_PATTERN_LOOP_1 + 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_1 + 14: + case DDR_PATTERN_LOOP_1 + 15: + case DDR_PATTERN_LOOP_1 + 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_1 + 22: + case DDR_PATTERN_LOOP_1 + 23: + case DDR_PATTERN_LOOP_1 + 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_1 + 30: + case DDR_PATTERN_LOOP_1 + 31: + if (*(p + i) != ~TDATA325) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~TDATA325); + } + break; + case DDR_PATTERN_LOOP_2 + 0: + case DDR_PATTERN_LOOP_2 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_2 + 3: + if (*(p + i) != ~0xfe01fe01) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfe01fe01); + } + break; + case DDR_PATTERN_LOOP_2 + 4: + case DDR_PATTERN_LOOP_2 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_2 + 7: + if (*(p + i) != ~0xfd02fd02) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfd02fd02); + } + break; + + case DDR_PATTERN_LOOP_2 + 8: + case DDR_PATTERN_LOOP_2 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_2 + 11: + if (*(p + i) != ~0xfb04fb04) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfb04fb04); + } + break; + case DDR_PATTERN_LOOP_2 + 12: + case DDR_PATTERN_LOOP_2 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_2 + 15: + if (*(p + i) != ~0xf708f708) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xf708f708); + } + break; + case DDR_PATTERN_LOOP_2 + 16: + case DDR_PATTERN_LOOP_2 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_2 + 19: + if (*(p + i) != ~0xef10ef10) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xef10ef10); + } + break; + case DDR_PATTERN_LOOP_2 + 20: + case DDR_PATTERN_LOOP_2 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_2 + 23: + if (*(p + i) != ~0xdf20df20) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xdf20df20); + } + break; + case DDR_PATTERN_LOOP_2 + 24: + case DDR_PATTERN_LOOP_2 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_2 + 27: + if (*(p + i) != ~0xbf40bf40) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xbf40bf40); + } + break; + case DDR_PATTERN_LOOP_2 + 28: + case DDR_PATTERN_LOOP_2 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_2 + 31: + if (*(p + i) != ~0x7f807f80) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x7f807f80); + } + break; + break; + case DDR_PATTERN_LOOP_3 + 0: + case DDR_PATTERN_LOOP_3 + 1: + case DDR_PATTERN_LOOP_3 + 2: + case DDR_PATTERN_LOOP_3 + 3: + if (*(p + i) != ~0x00000100) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00000100); + } + break; + case DDR_PATTERN_LOOP_3 + 4: + case DDR_PATTERN_LOOP_3 + 5: + case DDR_PATTERN_LOOP_3 + 6: + case DDR_PATTERN_LOOP_3 + 7: + if (*(p + i) != ~0x00000200) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00000200); + } + break; + case DDR_PATTERN_LOOP_3 + 8: + case DDR_PATTERN_LOOP_3 + 9: + case DDR_PATTERN_LOOP_3 + 10: + case DDR_PATTERN_LOOP_3 + 11: + if (*(p + i) != ~0x00000400) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00000400); + } + break; + case DDR_PATTERN_LOOP_3 + 12: + case DDR_PATTERN_LOOP_3 + 13: + case DDR_PATTERN_LOOP_3 + 14: + case DDR_PATTERN_LOOP_3 + 15: + if (*(p + i) != ~0x00000800) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00000800); + } + break; + case DDR_PATTERN_LOOP_3 + 16: + case DDR_PATTERN_LOOP_3 + 17: + case DDR_PATTERN_LOOP_3 + 18: + case DDR_PATTERN_LOOP_3 + 19: + if (*(p + i) != ~0x00001000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00001000); + } + break; + case DDR_PATTERN_LOOP_3 + 20: + case DDR_PATTERN_LOOP_3 + 21: + case DDR_PATTERN_LOOP_3 + 22: + case DDR_PATTERN_LOOP_3 + 23: + if (*(p + i) != ~0x00002000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00002000); + } + break; + case DDR_PATTERN_LOOP_3 + 24: + case DDR_PATTERN_LOOP_3 + 25: + case DDR_PATTERN_LOOP_3 + 26: + case DDR_PATTERN_LOOP_3 + 27: + if (*(p + i) != ~0x00004000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00004000); + } + break; + case DDR_PATTERN_LOOP_3 + 28: + case DDR_PATTERN_LOOP_3 + 29: + case DDR_PATTERN_LOOP_3 + 30: + case DDR_PATTERN_LOOP_3 + 31: + if (*(p + i) != ~0x00008000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00008000); + } + break; + } + } + + if (m_len > 128 * 4) { + m_len -= 128 * 4; + p += 32 * 4; + } else { + p += (m_len >> 2); + m_len = 0; + break; + } + } + } +} + +static void ddr_read_pattern4_cross_talk_n2(void *buff, unsigned int m_length) +{ + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; + + p = (unsigned int *)buff; + + while (m_len) { + { + if (m_len >= 128 * 4) + n = 32 * 4; + else + n = m_len >> 2; + + for (i = 0; i < n; i++) { +#ifdef DDR_PREFETCH_CACHE + ddr_pld_cache(p); +#endif + if ((error_outof_count_flag) && (error_count)) { + printf("Error data out of count"); + m_len = 0; break; } - switch (i) - { - case 0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_3+3: - // *(p+i) = 0xfe01fe01; - if (*(p+i) != ~0xfe01fe01) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfe01fe01); - break; - } + switch (i) { + case 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_3 + 3: + if (*(p + i) != ~0xfe01fe01) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfe01fe01); break; - case 4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_3+7: - // *(p+i) = 0xfd02fd02; - if (*(p+i) != ~0xfd02fd02) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfd02fd02); - break; - } + } + break; + case 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_3 + 7: + if (*(p + i) != ~0xfd02fd02) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfd02fd02); break; + } + break; - case 8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_3+11: - // *(p+i) = 0xfb04fb04; - if (*(p+i) != ~0xfb04fb04) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfb04fb04); - break; - } + case 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_3 + 11: + if (*(p + i) != ~0xfb04fb04) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfb04fb04); break; + } + break; - case 12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_3+15: - // *(p+i) = 0xf708f708; - if (*(p+i) != ~0xf708f708) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xf708f708); - break; - } + case 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_3 + 15: + if (*(p + i) != ~0xf708f708) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xf708f708); break; + } + break; - case 16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_3+19: - // *(p+i) = 0xef10ef10; - if (*(p+i) != ~0xef10ef10) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xef10ef10); - break; - } + case 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_3 + 19: + if (*(p + i) != ~0xef10ef10) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xef10ef10); break; + } + break; - case 20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_3+23: - // *(p+i) = 0xdf20df20; - if (*(p+i) != ~0xdf20df20) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xdf20df20); - break; - } + case 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_3 + 23: + if (*(p + i) != ~0xdf20df20) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xdf20df20); break; + } + break; - case 24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_3+27: - // *(p+i) = 0xbf40bf40; - if (*(p+i) != ~0xbf40bf40) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xbf40bf40); - break; - } + case 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_3 + 27: + if (*(p + i) != ~0xbf40bf40) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xbf40bf40); break; - case 28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_3+31: - // *(p+i) = 0x7f807f80; - if (*(p+i) != ~0x7f807f80) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x7f807f80); - break; - } + } + break; + case 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_3 + 31: + if (*(p + i) != ~0x7f807f80) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x7f807f80); break; + } + break; - default: + default: + if (*(p + i) != ~0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ff00); + break; + } + break; - // *(p+i) = 0xff00ff00; - if (*(p+i) != ~0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00); - break; - } - break; - - break; - - - } - } - - if (m_len > 128*4) - { - m_len -= 128*4; - p += 32*4; - } - else - { - p += (m_len>>2); - m_len = 0; - break; - } - } - } -} - -static void ddr_write_pattern4_no_cross_talk(void *buff, unsigned int m_length) -{ - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; - //#define ddr_pattern_loop 32 - p = ( unsigned int *)buff; - - while (m_len) - { - // for(j=0;j<32;j++) - { - if (m_len >= 128*4) - n = 32*4; - else - n = m_len>>2; - - for (i = 0; i < n; i++) - { -#ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; -#endif - switch (i) - { - case 0: - case 1: - case 2: - case 3: - *(p+i) = 0xff00ff00; - break; - case 4: - case 5: - case 6: - case 7: - *(p+i) = 0xffff0000; - break; - - case 8: - case 9: - case 10: - case 11: - *(p+i) = 0xff000000; - break; - case 12: - case 13: - case 14: - case 15: - *(p+i) = 0xff00ffff; - break; - - case 16: - case 17: - case 18: - case 19: - *(p+i) = 0xff00ffff; - break; - case 20: - case 21: - case 22: - case 23: - *(p+i) = 0xff0000ff; - break; - case 24: - case 25: - case 26: - case 27: - *(p+i) = 0xffff0000; - break; - - case 28: - case 29: - case 30: - case 31: - *(p+i) = 0x00ff00ff; - break; - case DDR_PATTERN_LOOP_1+0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_1+2: - case DDR_PATTERN_LOOP_1+3: - *(p+i) =~0xff00ff00; - break; - case DDR_PATTERN_LOOP_1+4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_1+6: - case DDR_PATTERN_LOOP_1+7: - *(p+i) =~0xffff0000; - break; - case DDR_PATTERN_LOOP_1+8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_1+10: - case DDR_PATTERN_LOOP_1+11: - *(p+i) =~0xff000000; - break; - case DDR_PATTERN_LOOP_1+12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_1+14: - case DDR_PATTERN_LOOP_1+15: - *(p+i) =~0xff00ffff; - break; - case DDR_PATTERN_LOOP_1+16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_1+18: - case DDR_PATTERN_LOOP_1+19: - *(p+i) =~0xff00ffff; - break; - case DDR_PATTERN_LOOP_1+20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_1+22: - case DDR_PATTERN_LOOP_1+23: - *(p+i) =~0xff00ffff; - break; - case DDR_PATTERN_LOOP_1+24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_1+26: - case DDR_PATTERN_LOOP_1+27: - *(p+i) =~0xffff0000; - break; - case DDR_PATTERN_LOOP_1+28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_1+30: - case DDR_PATTERN_LOOP_1+31: - *(p+i) =~0x00ff00ff; - break; - - case DDR_PATTERN_LOOP_2+0: - case DDR_PATTERN_LOOP_2+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_2+3: - *(p+i) =0x00ff0000; - break; - case DDR_PATTERN_LOOP_2+4: - case DDR_PATTERN_LOOP_2+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_2+7: - *(p+i) =0xff000000; - break; - case DDR_PATTERN_LOOP_2+8: - case DDR_PATTERN_LOOP_2+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_2+11: - *(p+i) =0x0000ffff; - break; - case DDR_PATTERN_LOOP_2+12: - case DDR_PATTERN_LOOP_2+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_2+15: - *(p+i) =0x000000ff; - break; - case DDR_PATTERN_LOOP_2+16: - case DDR_PATTERN_LOOP_2+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_2+19: - *(p+i) =0x00ff00ff; - break; - case DDR_PATTERN_LOOP_2+20: - case DDR_PATTERN_LOOP_2+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_2+23: - *(p+i) =0xff00ff00; - break; - case DDR_PATTERN_LOOP_2+24: - case DDR_PATTERN_LOOP_2+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_2+27: - *(p+i) =0xff00ffff; - break; - case DDR_PATTERN_LOOP_2+28: - case DDR_PATTERN_LOOP_2+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_2+31: - *(p+i) =0xff00ff00; - break; - case DDR_PATTERN_LOOP_3+0: - case DDR_PATTERN_LOOP_3+1: - case DDR_PATTERN_LOOP_3+2: - case DDR_PATTERN_LOOP_3+3: - *(p+i) =~0x00ff0000; - break; - case DDR_PATTERN_LOOP_3+4: - case DDR_PATTERN_LOOP_3+5: - case DDR_PATTERN_LOOP_3+6: - case DDR_PATTERN_LOOP_3+7: - *(p+i) =~0xff000000; - break; - case DDR_PATTERN_LOOP_3+8: - case DDR_PATTERN_LOOP_3+9: - case DDR_PATTERN_LOOP_3+10: - case DDR_PATTERN_LOOP_3+11: - *(p+i) =~0x0000ffff; - break; - case DDR_PATTERN_LOOP_3+12: - case DDR_PATTERN_LOOP_3+13: - case DDR_PATTERN_LOOP_3+14: - case DDR_PATTERN_LOOP_3+15: - *(p+i) =~0x000000ff; - break; - case DDR_PATTERN_LOOP_3+16: - case DDR_PATTERN_LOOP_3+17: - case DDR_PATTERN_LOOP_3+18: - case DDR_PATTERN_LOOP_3+19: - *(p+i) =~0x00ff00ff; - break; - case DDR_PATTERN_LOOP_3+20: - case DDR_PATTERN_LOOP_3+21: - case DDR_PATTERN_LOOP_3+22: - case DDR_PATTERN_LOOP_3+23: - *(p+i) =~0xff00ff00; - break; - case DDR_PATTERN_LOOP_3+24: - case DDR_PATTERN_LOOP_3+25: - case DDR_PATTERN_LOOP_3+26: - case DDR_PATTERN_LOOP_3+27: - *(p+i) =~0xff00ffff; - break; - case DDR_PATTERN_LOOP_3+28: - case DDR_PATTERN_LOOP_3+29: - case DDR_PATTERN_LOOP_3+30: - case DDR_PATTERN_LOOP_3+31: - *(p+i) =~0xff00ff00; - break; - - - } - } - - if (m_len >( 128*4)) - { - m_len -=( 128*4); - p += 32*4; - } - else - { - p += (m_len>>2); - m_len = 0; - break; - } - } - } -} - -static void ddr_read_pattern4_no_cross_talk(void *buff, unsigned int m_length) -{ - unsigned int *p; - // unsigned int i, j, n; - unsigned int i, n; - unsigned int m_len = m_length; - - p = ( unsigned int *)buff; - while (m_len) - { - // for(j=0;j<32;j++) - { - if (m_len >= 128*4) - n = 32*4; - else - n = m_len>>2; - - for (i = 0; i < n; i++) - { -#ifdef DDR_PREFETCH_CACHE - ddr_pld_cache(p) ; -#endif - if ((error_outof_count_flag) && (error_count)) - { - printf("Error data out of count"); - m_len=0; break; } - switch (i) - { - case 0: - case 1: - case 2: - case 3: - // if(*(p+i) !=~TDATA32F) - - if ( *(p+i) != 0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00); - } - break; - case 4: - case 5: - case 6: - case 7: - if ( *(p+i) != 0xffff0000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xffff0000); - } - break; - - case 8: - case 9: - case 10: - case 11: - // *(p+i) = 0xff000000; - if ( *(p+i) != 0xff000000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff000000); - } - break; - case 12: - case 13: - case 14: - case 15: - // *(p+i) = 0xff00ffff; - if ( *(p+i) != 0xff00ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff); - } - break; - - case 16: - case 17: - case 18: - case 19: - // *(p+i) = 0xff00ffff; - if ( *(p+i) != 0xff00ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff); - } - break; - case 20: - case 21: - case 22: - case 23: - // *(p+i) = 0xff0000ff; - if ( *(p+i) != 0xff0000ff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff0000ff); - } - break; - case 24: - case 25: - case 26: - case 27: - // *(p+i) = 0xffff0000; - if ( *(p+i) != 0xffff0000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xffff0000); - } - break; - - case 28: - case 29: - case 30: - case 31: - // *(p+i) = 0x00ff00ff; - if ( *(p+i) != 0x00ff00ff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff00ff); - } - break; - case DDR_PATTERN_LOOP_1+0: - case DDR_PATTERN_LOOP_1+1: - case DDR_PATTERN_LOOP_1+2: - case DDR_PATTERN_LOOP_1+3: - // *(p+i) =~0xff00ff00; - if ( *(p+i) != ~0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00); - } - break; - case DDR_PATTERN_LOOP_1+4: - case DDR_PATTERN_LOOP_1+5: - case DDR_PATTERN_LOOP_1+6: - case DDR_PATTERN_LOOP_1+7: - // *(p+i) =~0xffff0000; - if ( *(p+i) != ~0xffff0000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xffff0000); - } - break; - case DDR_PATTERN_LOOP_1+8: - case DDR_PATTERN_LOOP_1+9: - case DDR_PATTERN_LOOP_1+10: - case DDR_PATTERN_LOOP_1+11: - // *(p+i) =~0xff000000; - if ( *(p+i) != ~0xff000000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff000000); - } - break; - case DDR_PATTERN_LOOP_1+12: - case DDR_PATTERN_LOOP_1+13: - case DDR_PATTERN_LOOP_1+14: - case DDR_PATTERN_LOOP_1+15: - // *(p+i) =~0xff00ffff; - if ( *(p+i) != ~0xff00ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff); - } - break; - case DDR_PATTERN_LOOP_1+16: - case DDR_PATTERN_LOOP_1+17: - case DDR_PATTERN_LOOP_1+18: - case DDR_PATTERN_LOOP_1+19: - // *(p+i) =~0xff00ffff; - if ( *(p+i) != ~0xff00ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff); - } - break; - case DDR_PATTERN_LOOP_1+20: - case DDR_PATTERN_LOOP_1+21: - case DDR_PATTERN_LOOP_1+22: - case DDR_PATTERN_LOOP_1+23: - // *(p+i) =~0xff00ffff; - if ( *(p+i) != ~0xff00ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff); - } - break; - case DDR_PATTERN_LOOP_1+24: - case DDR_PATTERN_LOOP_1+25: - case DDR_PATTERN_LOOP_1+26: - case DDR_PATTERN_LOOP_1+27: - // *(p+i) =~0xffff0000; - if ( *(p+i) != ~0xffff0000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xffff0000); - } - break; - case DDR_PATTERN_LOOP_1+28: - case DDR_PATTERN_LOOP_1+29: - case DDR_PATTERN_LOOP_1+30: - case DDR_PATTERN_LOOP_1+31: - // *(p+i) =~0x00ff00ff; - if ( *(p+i) != ~0x00ff00ff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff00ff); - } - break; - - case DDR_PATTERN_LOOP_2+0: - case DDR_PATTERN_LOOP_2+1: - case DDR_PATTERN_LOOP_2+2: - case DDR_PATTERN_LOOP_2+3: - // *(p+i) =0x00ff0000; - if ( *(p+i) != 0x00ff0000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff0000); - } - break; - case DDR_PATTERN_LOOP_2+4: - case DDR_PATTERN_LOOP_2+5: - case DDR_PATTERN_LOOP_2+6: - case DDR_PATTERN_LOOP_2+7: - // *(p+i) =0xff000000; - if ( *(p+i) != 0xff000000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff000000); - } - break; - case DDR_PATTERN_LOOP_2+8: - case DDR_PATTERN_LOOP_2+9: - case DDR_PATTERN_LOOP_2+10: - case DDR_PATTERN_LOOP_2+11: - // *(p+i) =0x0000ffff; - if ( *(p+i) != 0x0000ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x0000ffff); - } - break; - case DDR_PATTERN_LOOP_2+12: - case DDR_PATTERN_LOOP_2+13: - case DDR_PATTERN_LOOP_2+14: - case DDR_PATTERN_LOOP_2+15: - // *(p+i) =0x000000ff; - if ( *(p+i) != 0x000000ff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x000000ff); - } - break; - case DDR_PATTERN_LOOP_2+16: - case DDR_PATTERN_LOOP_2+17: - case DDR_PATTERN_LOOP_2+18: - case DDR_PATTERN_LOOP_2+19: - // *(p+i) =0x00ff00ff; - if ( *(p+i) != 0x00ff00ff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff00ff); - } - break; - case DDR_PATTERN_LOOP_2+20: - case DDR_PATTERN_LOOP_2+21: - case DDR_PATTERN_LOOP_2+22: - case DDR_PATTERN_LOOP_2+23: - // *(p+i) =0xff00ff00; - if ( *(p+i) != 0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00); - } - break; - case DDR_PATTERN_LOOP_2+24: - case DDR_PATTERN_LOOP_2+25: - case DDR_PATTERN_LOOP_2+26: - case DDR_PATTERN_LOOP_2+27: - // *(p+i) =0xff00ffff; - if ( *(p+i) != 0xff00ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff); - } - break; - case DDR_PATTERN_LOOP_2+28: - case DDR_PATTERN_LOOP_2+29: - case DDR_PATTERN_LOOP_2+30: - case DDR_PATTERN_LOOP_2+31: - // *(p+i) =0xff00ff00; - if ( *(p+i) != 0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00); - } - break; - case DDR_PATTERN_LOOP_3+0: - case DDR_PATTERN_LOOP_3+1: - case DDR_PATTERN_LOOP_3+2: - case DDR_PATTERN_LOOP_3+3: - // *(p+i) =~0x00ff0000; - if ( *(p+i) != ~0x00ff0000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff0000); - } - break; - case DDR_PATTERN_LOOP_3+4: - case DDR_PATTERN_LOOP_3+5: - case DDR_PATTERN_LOOP_3+6: - case DDR_PATTERN_LOOP_3+7: - // *(p+i) =~0xff000000; - if ( *(p+i) != ~0xff000000) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff000000); - } - break; - case DDR_PATTERN_LOOP_3+8: - case DDR_PATTERN_LOOP_3+9: - case DDR_PATTERN_LOOP_3+10: - case DDR_PATTERN_LOOP_3+11: - // *(p+i) =~0x0000ffff; - if ( *(p+i) != ~0x0000ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x0000ffff); - } - break; - case DDR_PATTERN_LOOP_3+12: - case DDR_PATTERN_LOOP_3+13: - case DDR_PATTERN_LOOP_3+14: - case DDR_PATTERN_LOOP_3+15: - // *(p+i) =~0x000000ff; - if ( *(p+i) != ~0x000000ff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x000000ff); - } - break; - case DDR_PATTERN_LOOP_3+16: - case DDR_PATTERN_LOOP_3+17: - case DDR_PATTERN_LOOP_3+18: - case DDR_PATTERN_LOOP_3+19: - // *(p+i) =~0x00ff00ff; - if ( *(p+i) != ~0x00ff00ff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff00ff); - } - break; - case DDR_PATTERN_LOOP_3+20: - case DDR_PATTERN_LOOP_3+21: - case DDR_PATTERN_LOOP_3+22: - case DDR_PATTERN_LOOP_3+23: - // *(p+i) =~0xff00ff00; - if ( *(p+i) != ~0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00); - } - break; - case DDR_PATTERN_LOOP_3+24: - case DDR_PATTERN_LOOP_3+25: - case DDR_PATTERN_LOOP_3+26: - case DDR_PATTERN_LOOP_3+27: - // *(p+i) =~0xff00ffff; - if ( *(p+i) != ~0xff00ffff) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff); - } - break; - case DDR_PATTERN_LOOP_3+28: - case DDR_PATTERN_LOOP_3+29: - case DDR_PATTERN_LOOP_3+30: - case DDR_PATTERN_LOOP_3+31: - // *(p+i) =~0xff00ff00; - if ( *(p+i) != ~0xff00ff00) - { - error_count++; - printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00); - } - break; - - - } } - if (m_len >( 128*4)) - { - m_len -=( 128*4); - p += 32*4; - } - else - { - p += (m_len>>2); + if (m_len > 128 * 4) { + m_len -= 128 * 4; + p += 32 * 4; + } else { + p += (m_len >> 2); m_len = 0; break; } @@ -4652,165 +3680,679 @@ } } +static void ddr_write_pattern4_no_cross_talk(void *buff, unsigned int m_length) +{ + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; + p = (unsigned int *)buff; -int do_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) + while (m_len) { + { + if (m_len >= 128 * 4) + n = 32 * 4; + else + n = m_len >> 2; + + for (i = 0; i < n; i++) { +#ifdef DDR_PREFETCH_CACHE + ddr_pld_cache(p); +#endif + switch (i) { + case 0: + case 1: + case 2: + case 3: + *(p + i) = 0xff00ff00; + break; + case 4: + case 5: + case 6: + case 7: + *(p + i) = 0xffff0000; + break; + + case 8: + case 9: + case 10: + case 11: + *(p + i) = 0xff000000; + break; + case 12: + case 13: + case 14: + case 15: + *(p + i) = 0xff00ffff; + break; + + case 16: + case 17: + case 18: + case 19: + *(p + i) = 0xff00ffff; + break; + case 20: + case 21: + case 22: + case 23: + *(p + i) = 0xff0000ff; + break; + case 24: + case 25: + case 26: + case 27: + *(p + i) = 0xffff0000; + break; + + case 28: + case 29: + case 30: + case 31: + *(p + i) = 0x00ff00ff; + break; + case DDR_PATTERN_LOOP_1 + 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_1 + 2: + case DDR_PATTERN_LOOP_1 + 3: + *(p + i) = ~0xff00ff00; + break; + case DDR_PATTERN_LOOP_1 + 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_1 + 6: + case DDR_PATTERN_LOOP_1 + 7: + *(p + i) = ~0xffff0000; + break; + case DDR_PATTERN_LOOP_1 + 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_1 + 10: + case DDR_PATTERN_LOOP_1 + 11: + *(p + i) = ~0xff000000; + break; + case DDR_PATTERN_LOOP_1 + 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_1 + 14: + case DDR_PATTERN_LOOP_1 + 15: + *(p + i) = ~0xff00ffff; + break; + case DDR_PATTERN_LOOP_1 + 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_1 + 18: + case DDR_PATTERN_LOOP_1 + 19: + *(p + i) = ~0xff00ffff; + break; + case DDR_PATTERN_LOOP_1 + 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_1 + 22: + case DDR_PATTERN_LOOP_1 + 23: + *(p + i) = ~0xff00ffff; + break; + case DDR_PATTERN_LOOP_1 + 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_1 + 26: + case DDR_PATTERN_LOOP_1 + 27: + *(p + i) = ~0xffff0000; + break; + case DDR_PATTERN_LOOP_1 + 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_1 + 30: + case DDR_PATTERN_LOOP_1 + 31: + *(p + i) = ~0x00ff00ff; + break; + + case DDR_PATTERN_LOOP_2 + 0: + case DDR_PATTERN_LOOP_2 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_2 + 3: + *(p + i) = 0x00ff0000; + break; + case DDR_PATTERN_LOOP_2 + 4: + case DDR_PATTERN_LOOP_2 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_2 + 7: + *(p + i) = 0xff000000; + break; + case DDR_PATTERN_LOOP_2 + 8: + case DDR_PATTERN_LOOP_2 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_2 + 11: + *(p + i) = 0x0000ffff; + break; + case DDR_PATTERN_LOOP_2 + 12: + case DDR_PATTERN_LOOP_2 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_2 + 15: + *(p + i) = 0x000000ff; + break; + case DDR_PATTERN_LOOP_2 + 16: + case DDR_PATTERN_LOOP_2 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_2 + 19: + *(p + i) = 0x00ff00ff; + break; + case DDR_PATTERN_LOOP_2 + 20: + case DDR_PATTERN_LOOP_2 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_2 + 23: + *(p + i) = 0xff00ff00; + break; + case DDR_PATTERN_LOOP_2 + 24: + case DDR_PATTERN_LOOP_2 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_2 + 27: + *(p + i) = 0xff00ffff; + break; + case DDR_PATTERN_LOOP_2 + 28: + case DDR_PATTERN_LOOP_2 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_2 + 31: + *(p + i) = 0xff00ff00; + break; + case DDR_PATTERN_LOOP_3 + 0: + case DDR_PATTERN_LOOP_3 + 1: + case DDR_PATTERN_LOOP_3 + 2: + case DDR_PATTERN_LOOP_3 + 3: + *(p + i) = ~0x00ff0000; + break; + case DDR_PATTERN_LOOP_3 + 4: + case DDR_PATTERN_LOOP_3 + 5: + case DDR_PATTERN_LOOP_3 + 6: + case DDR_PATTERN_LOOP_3 + 7: + *(p + i) = ~0xff000000; + break; + case DDR_PATTERN_LOOP_3 + 8: + case DDR_PATTERN_LOOP_3 + 9: + case DDR_PATTERN_LOOP_3 + 10: + case DDR_PATTERN_LOOP_3 + 11: + *(p + i) = ~0x0000ffff; + break; + case DDR_PATTERN_LOOP_3 + 12: + case DDR_PATTERN_LOOP_3 + 13: + case DDR_PATTERN_LOOP_3 + 14: + case DDR_PATTERN_LOOP_3 + 15: + *(p + i) = ~0x000000ff; + break; + case DDR_PATTERN_LOOP_3 + 16: + case DDR_PATTERN_LOOP_3 + 17: + case DDR_PATTERN_LOOP_3 + 18: + case DDR_PATTERN_LOOP_3 + 19: + *(p + i) = ~0x00ff00ff; + break; + case DDR_PATTERN_LOOP_3 + 20: + case DDR_PATTERN_LOOP_3 + 21: + case DDR_PATTERN_LOOP_3 + 22: + case DDR_PATTERN_LOOP_3 + 23: + *(p + i) = ~0xff00ff00; + break; + case DDR_PATTERN_LOOP_3 + 24: + case DDR_PATTERN_LOOP_3 + 25: + case DDR_PATTERN_LOOP_3 + 26: + case DDR_PATTERN_LOOP_3 + 27: + *(p + i) = ~0xff00ffff; + break; + case DDR_PATTERN_LOOP_3 + 28: + case DDR_PATTERN_LOOP_3 + 29: + case DDR_PATTERN_LOOP_3 + 30: + case DDR_PATTERN_LOOP_3 + 31: + *(p + i) = ~0xff00ff00; + break; + } + } + + if (m_len > (128 * 4)) { + m_len -= (128 * 4); + p += 32 * 4; + } else { + p += (m_len >> 2); + m_len = 0; + break; + } + } + } +} + +static void ddr_read_pattern4_no_cross_talk(void *buff, unsigned int m_length) +{ + unsigned int *p; + unsigned int i, n; + unsigned int m_len = m_length; + + p = (unsigned int *)buff; + while (m_len) { + { + if (m_len >= 128 * 4) + n = 32 * 4; + else + n = m_len >> 2; + + for (i = 0; i < n; i++) { +#ifdef DDR_PREFETCH_CACHE + ddr_pld_cache(p); +#endif + if ((error_outof_count_flag) && (error_count)) { + printf("Error data out of count"); + m_len = 0; + break; + } + switch (i) { + case 0: + case 1: + case 2: + case 3: + if (*(p + i) != 0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ff00); + } + break; + case 4: + case 5: + case 6: + case 7: + if (*(p + i) != 0xffff0000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xffff0000); + } + break; + + case 8: + case 9: + case 10: + case 11: + if (*(p + i) != 0xff000000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff000000); + } + break; + case 12: + case 13: + case 14: + case 15: + if (*(p + i) != 0xff00ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ffff); + } + break; + + case 16: + case 17: + case 18: + case 19: + if (*(p + i) != 0xff00ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ffff); + } + break; + case 20: + case 21: + case 22: + case 23: + if (*(p + i) != 0xff0000ff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff0000ff); + } + break; + case 24: + case 25: + case 26: + case 27: + if (*(p + i) != 0xffff0000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xffff0000); + } + break; + + case 28: + case 29: + case 30: + case 31: + if (*(p + i) != 0x00ff00ff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00ff00ff); + } + break; + case DDR_PATTERN_LOOP_1 + 0: + case DDR_PATTERN_LOOP_1 + 1: + case DDR_PATTERN_LOOP_1 + 2: + case DDR_PATTERN_LOOP_1 + 3: + if (*(p + i) != ~0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ff00); + } + break; + case DDR_PATTERN_LOOP_1 + 4: + case DDR_PATTERN_LOOP_1 + 5: + case DDR_PATTERN_LOOP_1 + 6: + case DDR_PATTERN_LOOP_1 + 7: + if (*(p + i) != ~0xffff0000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xffff0000); + } + break; + case DDR_PATTERN_LOOP_1 + 8: + case DDR_PATTERN_LOOP_1 + 9: + case DDR_PATTERN_LOOP_1 + 10: + case DDR_PATTERN_LOOP_1 + 11: + if (*(p + i) != ~0xff000000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff000000); + } + break; + case DDR_PATTERN_LOOP_1 + 12: + case DDR_PATTERN_LOOP_1 + 13: + case DDR_PATTERN_LOOP_1 + 14: + case DDR_PATTERN_LOOP_1 + 15: + if (*(p + i) != ~0xff00ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ffff); + } + break; + case DDR_PATTERN_LOOP_1 + 16: + case DDR_PATTERN_LOOP_1 + 17: + case DDR_PATTERN_LOOP_1 + 18: + case DDR_PATTERN_LOOP_1 + 19: + if (*(p + i) != ~0xff00ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ffff); + } + break; + case DDR_PATTERN_LOOP_1 + 20: + case DDR_PATTERN_LOOP_1 + 21: + case DDR_PATTERN_LOOP_1 + 22: + case DDR_PATTERN_LOOP_1 + 23: + if (*(p + i) != ~0xff00ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ffff); + } + break; + case DDR_PATTERN_LOOP_1 + 24: + case DDR_PATTERN_LOOP_1 + 25: + case DDR_PATTERN_LOOP_1 + 26: + case DDR_PATTERN_LOOP_1 + 27: + if (*(p + i) != ~0xffff0000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xffff0000); + } + break; + case DDR_PATTERN_LOOP_1 + 28: + case DDR_PATTERN_LOOP_1 + 29: + case DDR_PATTERN_LOOP_1 + 30: + case DDR_PATTERN_LOOP_1 + 31: + if (*(p + i) != ~0x00ff00ff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00ff00ff); + } + break; + case DDR_PATTERN_LOOP_2 + 0: + case DDR_PATTERN_LOOP_2 + 1: + case DDR_PATTERN_LOOP_2 + 2: + case DDR_PATTERN_LOOP_2 + 3: + if (*(p + i) != 0x00ff0000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00ff0000); + } + break; + case DDR_PATTERN_LOOP_2 + 4: + case DDR_PATTERN_LOOP_2 + 5: + case DDR_PATTERN_LOOP_2 + 6: + case DDR_PATTERN_LOOP_2 + 7: + if (*(p + i) != 0xff000000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff000000); + } + break; + case DDR_PATTERN_LOOP_2 + 8: + case DDR_PATTERN_LOOP_2 + 9: + case DDR_PATTERN_LOOP_2 + 10: + case DDR_PATTERN_LOOP_2 + 11: + if (*(p + i) != 0x0000ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x0000ffff); + } + break; + case DDR_PATTERN_LOOP_2 + 12: + case DDR_PATTERN_LOOP_2 + 13: + case DDR_PATTERN_LOOP_2 + 14: + case DDR_PATTERN_LOOP_2 + 15: + if (*(p + i) != 0x000000ff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x000000ff); + } + break; + case DDR_PATTERN_LOOP_2 + 16: + case DDR_PATTERN_LOOP_2 + 17: + case DDR_PATTERN_LOOP_2 + 18: + case DDR_PATTERN_LOOP_2 + 19: + if (*(p + i) != 0x00ff00ff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00ff00ff); + } + break; + case DDR_PATTERN_LOOP_2 + 20: + case DDR_PATTERN_LOOP_2 + 21: + case DDR_PATTERN_LOOP_2 + 22: + case DDR_PATTERN_LOOP_2 + 23: + if (*(p + i) != 0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ff00); + } + break; + case DDR_PATTERN_LOOP_2 + 24: + case DDR_PATTERN_LOOP_2 + 25: + case DDR_PATTERN_LOOP_2 + 26: + case DDR_PATTERN_LOOP_2 + 27: + if (*(p + i) != 0xff00ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ffff); + } + break; + case DDR_PATTERN_LOOP_2 + 28: + case DDR_PATTERN_LOOP_2 + 29: + case DDR_PATTERN_LOOP_2 + 30: + case DDR_PATTERN_LOOP_2 + 31: + if (*(p + i) != 0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ff00); + } + break; + case DDR_PATTERN_LOOP_3 + 0: + case DDR_PATTERN_LOOP_3 + 1: + case DDR_PATTERN_LOOP_3 + 2: + case DDR_PATTERN_LOOP_3 + 3: + if (*(p + i) != ~0x00ff0000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00ff0000); + } + break; + case DDR_PATTERN_LOOP_3 + 4: + case DDR_PATTERN_LOOP_3 + 5: + case DDR_PATTERN_LOOP_3 + 6: + case DDR_PATTERN_LOOP_3 + 7: + if (*(p + i) != ~0xff000000) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff000000); + } + break; + case DDR_PATTERN_LOOP_3 + 8: + case DDR_PATTERN_LOOP_3 + 9: + case DDR_PATTERN_LOOP_3 + 10: + case DDR_PATTERN_LOOP_3 + 11: + if (*(p + i) != ~0x0000ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x0000ffff); + } + break; + case DDR_PATTERN_LOOP_3 + 12: + case DDR_PATTERN_LOOP_3 + 13: + case DDR_PATTERN_LOOP_3 + 14: + case DDR_PATTERN_LOOP_3 + 15: + if (*(p + i) != ~0x000000ff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x000000ff); + } + break; + case DDR_PATTERN_LOOP_3 + 16: + case DDR_PATTERN_LOOP_3 + 17: + case DDR_PATTERN_LOOP_3 + 18: + case DDR_PATTERN_LOOP_3 + 19: + if (*(p + i) != ~0x00ff00ff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00ff00ff); + } + break; + case DDR_PATTERN_LOOP_3 + 20: + case DDR_PATTERN_LOOP_3 + 21: + case DDR_PATTERN_LOOP_3 + 22: + case DDR_PATTERN_LOOP_3 + 23: + if (*(p + i) != ~0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ff00); + } + break; + case DDR_PATTERN_LOOP_3 + 24: + case DDR_PATTERN_LOOP_3 + 25: + case DDR_PATTERN_LOOP_3 + 26: + case DDR_PATTERN_LOOP_3 + 27: + if (*(p + i) != ~0xff00ffff) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ffff); + } + break; + case DDR_PATTERN_LOOP_3 + 28: + case DDR_PATTERN_LOOP_3 + 29: + case DDR_PATTERN_LOOP_3 + 30: + case DDR_PATTERN_LOOP_3 + 31: + if (*(p + i) != ~0xff00ff00) { + error_count++; + printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ff00); + } + break; + } + } + + if (m_len > (128 * 4)) { + m_len -= (128 * 4); + p += 32 * 4; + } else { + p += (m_len >> 2); + m_len = 0; + break; + } + } + } +} + +int do_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { char *endp; - unsigned int loop = 1; - unsigned int lflag = 0; - unsigned int start_addr = DDR_TEST_START_ADDR; - unsigned int test_size = DDR_TEST_SIZE; - unsigned int simple_pattern_flag = 1; - unsigned int cross_talk_pattern_flag = 1; - unsigned int old_pattern_flag = 1; + unsigned int loop = 1; + unsigned int lflag = 0; + unsigned int start_addr = DDR_TEST_START_ADDR; + unsigned int test_size = DDR_TEST_SIZE; + unsigned int simple_pattern_flag = 1; + unsigned int cross_talk_pattern_flag = 1; + unsigned int old_pattern_flag = 1; + unsigned int print_flag = 1; - unsigned int print_flag = 1; - // copy_test_flag = 0; print_flag = 1; - error_outof_count_flag =0; - error_count =0; + error_outof_count_flag = 0; + error_count = 0; printf("\nargc== 0x%08x\n", argc); - int i ; - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } + int i; + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); if (!argc) goto DDR_TEST_START; if (argc > 1) { if (strcmp(argv[1], "l") == 0) { lflag = 1; - } - else if (strcmp(argv[1], "h") == 0){ + } else if (strcmp(argv[1], "h") == 0) { goto usage; - } - else{ + } else { loop = simple_strtoull_ddr(argv[1], &endp, 10); if (*argv[1] == 0 || *endp != 0) loop = 1; } } - // printf("\nLINE== 0x%08x\n", __LINE__); - if (argc ==1) { - // start_addr = simple_strtoull_ddr(argv[2], &endp, 16); - // if (*argv[2] == 0 || *endp != 0) + if (argc == 1) { start_addr = DDR_TEST_START_ADDR; loop = 1; - } if (argc > 2) { start_addr = simple_strtoull_ddr(argv[2], &endp, 16); if (*argv[2] == 0 || *endp != 0) start_addr = DDR_TEST_START_ADDR; - } if (argc > 3) { test_size = simple_strtoull_ddr(argv[3], &endp, 16); if (*argv[3] == 0 || *endp != 0) test_size = DDR_TEST_SIZE; - } - if (test_size<0x1000) + if (test_size < 0x1000) test_size = DDR_TEST_SIZE; old_pattern_flag = 1; simple_pattern_flag = 1; cross_talk_pattern_flag = 1; - //printf("\nLINE== 0x%08x\n", __LINE__); - if (argc ==2) { - if ( (strcmp(argv[1], "s") == 0)) - { + if (argc == 2) { + if ((strcmp(argv[1], "s") == 0)) { simple_pattern_flag = 1; - old_pattern_flag=0; + old_pattern_flag = 0; cross_talk_pattern_flag = 0; - } - else if ((strcmp(argv[1], "c") == 0)) - { + } else if ((strcmp(argv[1], "c") == 0)) { simple_pattern_flag = 0; - old_pattern_flag=0; + old_pattern_flag = 0; cross_talk_pattern_flag = 1; - } - else if ( (strcmp(argv[1], "e") == 0)) - { - error_outof_count_flag=1; + } else if ((strcmp(argv[1], "e") == 0)) { + error_outof_count_flag = 1; } } - if (argc >2) { - if ( (strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0)) - { + if (argc > 2) { + if ((strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0)) print_flag = 0; - } - if ( (strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0)) - { + if ((strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0)) copy_test_flag = 1; - } - if ( (strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0)) - { + if ((strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0)) { simple_pattern_flag = 1; - old_pattern_flag=0; + old_pattern_flag = 0; cross_talk_pattern_flag = 0; - } - else if ((strcmp(argv[1], "c") == 0)||(strcmp(argv[2], "c") == 0)) - { + } else if ((strcmp(argv[1], "c") == 0) || (strcmp(argv[2], "c") == 0)) { simple_pattern_flag = 0; - old_pattern_flag=0; + old_pattern_flag = 0; cross_talk_pattern_flag = 1; - } - else if ( (strcmp(argv[1], "e") == 0)||(strcmp(argv[2], "e") == 0)) - { - error_outof_count_flag=1; + } else if ((strcmp(argv[1], "e") == 0) || (strcmp(argv[2], "e") == 0)) { + error_outof_count_flag = 1; } } - //printf("\nLINE1== 0x%08x\n", __LINE__); if (argc > 3) { - if ( (strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0) || (strcmp(argv[3], "p") == 0)) - { + if ((strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0) || (strcmp(argv[3], "p") == 0)) copy_test_flag = 1; - } - if ( (strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0) || (strcmp(argv[3], "n") == 0)) - { + if ((strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0) || (strcmp(argv[3], "n") == 0)) print_flag = 0; - } - if ( (strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0) || (strcmp(argv[3], "s") == 0)) - { + if ((strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0) || (strcmp(argv[3], "s") == 0)) { simple_pattern_flag = 1; - old_pattern_flag=0; + old_pattern_flag = 0; cross_talk_pattern_flag = 0; } - if ((strcmp(argv[1], "c") == 0) || (strcmp(argv[2], "c") == 0) || (strcmp(argv[3], "c") == 0)) - { + if ((strcmp(argv[1], "c") == 0) || (strcmp(argv[2], "c") == 0) || (strcmp(argv[3], "c") == 0)) { simple_pattern_flag = 0; - old_pattern_flag=0; + old_pattern_flag = 0; cross_talk_pattern_flag = 1; } - if ( (strcmp(argv[1], "e") == 0) || (strcmp(argv[2], "e") == 0) || (strcmp(argv[3], "e") == 0)) - { - error_outof_count_flag=1; - } + if ((strcmp(argv[1], "e") == 0) || (strcmp(argv[2], "e") == 0) || (strcmp(argv[3], "e") == 0)) + error_outof_count_flag = 1; } - // printf("\nLINE2== 0x%08x\n", __LINE__); - // printf("\nLINE3== 0x%08x\n", __LINE__); - // printf("\nLINE== 0x%08x\n", __LINE__); - DDR_TEST_START: - ///* do { if (lflag) loop = 888; - if (old_pattern_flag == 1) - { + if (old_pattern_flag == 1) { { - // printf("\nLINE== 0x%08x\n", __LINE__); - //printf("\nLINE== 0x%08x\n", __LINE__); - //printf("\nLINE== 0x%08x\n", __LINE__); if (print_flag) printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size); ddr_write((void *)(int_convter_p(start_addr)), test_size); - // flush_dcache_range(start_addr,start_addr + test_size); if (print_flag) { printf("\nEnd write. "); printf("\nStart 1st reading... "); @@ -4818,28 +4360,26 @@ ddr_read((void *)(int_convter_p(start_addr)), test_size); if (print_flag) { printf("\nEnd 1st read. "); - printf("\nStart 2nd reading... ");} + printf("\nStart 2nd reading... "); + } ddr_read((void *)(int_convter_p(start_addr)), test_size); if (print_flag) { printf("\nEnd 2nd read. "); - printf("\nStart 3rd reading... ");} + printf("\nStart 3rd reading... "); + } ddr_read((void *)(int_convter_p(start_addr)), test_size); if (print_flag) printf("\nEnd 3rd read. \n"); - if (copy_test_flag) - {if(print_flag) - printf("\n copy_test_flag = 1,start copy test. \n"); - ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 ); - ddr_read((void *)(int_convter_p(start_addr+test_size/2)), test_size/2); - ddr_read((void *)(int_convter_p(start_addr+test_size/2)), test_size/2); + if (copy_test_flag) { + if (print_flag) + printf("\n copy_test_flag = 1,start copy test. \n"); + ddr_test_copy((void *)(int_convter_p(start_addr + test_size / 2)), (void *)(int_convter_p(start_addr)), test_size / 2); + ddr_read((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2); + ddr_read((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2); } - } { - // printf("\nLINE== 0x%08x\n", __LINE__); - //printf("\nLINE== 0x%08x\n", __LINE__); - //printf("\nLINE== 0x%08x\n", __LINE__); if (print_flag) { printf("\nStart *4 normal pattern. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size); @@ -4847,32 +4387,30 @@ ddr_write4((void *)(int_convter_p(start_addr)), test_size); if (print_flag) { printf("\nEnd write. "); - printf("\nStart 1st reading... ");} + printf("\nStart 1st reading... "); + } ddr_read4((void *)(int_convter_p(start_addr)), test_size); if (print_flag) { printf("\nEnd 1st read. "); - printf("\nStart 2nd reading... ");} + printf("\nStart 2nd reading... "); + } ddr_read4((void *)(int_convter_p(start_addr)), test_size); if (print_flag) { printf("\nEnd 2nd read. "); - printf("\nStart 3rd reading... ");} + printf("\nStart 3rd reading... "); + } ddr_read4((void *)(int_convter_p(start_addr)), test_size); if (print_flag) printf("\rEnd 3rd read. \n"); - if (copy_test_flag) - { - - ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 ); - ddr_read4((void *)(int_convter_p(start_addr+test_size/2)), test_size/2); - ddr_read4((void *)(int_convter_p(start_addr+test_size/2)), test_size/2); + if (copy_test_flag) { + ddr_test_copy((void *)(int_convter_p(start_addr + test_size / 2)), (void *)(int_convter_p(start_addr)), test_size / 2); + ddr_read4((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2); + ddr_read4((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2); } - - } } - if (simple_pattern_flag == 1) - { + if (simple_pattern_flag == 1) { if (print_flag) { printf("\nStart *4 no cross talk pattern. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size); @@ -4880,119 +4418,130 @@ ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size); if (print_flag) { printf("\rEnd write. "); - printf("\rStart 1st reading... ");} + printf("\rStart 1st reading... "); + } ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size); if (print_flag) { printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... ");} + printf("\rStart 2nd reading... "); + } ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size); if (print_flag) { printf("\rEnd 2nd read. "); - printf("\rStart 3rd reading... ");} + printf("\rStart 3rd reading... "); + } ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size); if (print_flag) printf("\rEnd 3rd read. \n"); - if (copy_test_flag) - { - ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 ); - ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr+test_size/2)), test_size/2); - ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr+test_size/2)), test_size/2); + if (copy_test_flag) { + ddr_test_copy((void *)(int_convter_p(start_addr + test_size / 2)), (void *)(int_convter_p(start_addr)), test_size / 2); + ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2); + ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2); } - } - if (cross_talk_pattern_flag == 1) - {if(print_flag){ - printf("\nStart *4 cross talk pattern p. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size); - } - ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd write. "); - printf("\rStart 1st reading... ");} - ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... ");} - ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 2nd read. "); - printf("\rStart 3rd reading... ");} - ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 3rd read. \n"); + if (cross_talk_pattern_flag == 1) { + if (print_flag) { + printf("\nStart *4 cross talk pattern p. "); + printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size); + } + ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd write. "); + printf("\rStart 1st reading... "); + } + ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 1st read. "); + printf("\rStart 2nd reading... "); + } + ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 2nd read. "); + printf("\rStart 3rd reading... "); + } + ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 3rd read. \n"); - printf("\nStart *4 cross talk pattern n. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);} - ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd write. "); - printf("\rStart 1st reading... ");} - ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... ");} - ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 2nd read. "); - printf("\rStart 3rd reading... ");} - ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 3rd read. \n"); + printf("\nStart *4 cross talk pattern n. "); + printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size); + } + ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd write. "); + printf("\rStart 1st reading... "); + } + ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 1st read. "); + printf("\rStart 2nd reading... "); + } + ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 2nd read. "); + printf("\rStart 3rd reading... "); + } + ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 3rd read. \n"); - ///* - printf("\nStart *4 cross talk pattern p2. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);} - ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd write. "); - printf("\rStart 1st reading... ");} - ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... ");} - ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 2nd read. "); - printf("\rStart 3rd reading... ");} - ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 3rd read. \n"); + ///* + printf("\nStart *4 cross talk pattern p2. "); + printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size); + } + ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd write. "); + printf("\rStart 1st reading... "); + } + ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 1st read. "); + printf("\rStart 2nd reading... "); + } + ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 2nd read. "); + printf("\rStart 3rd reading... "); + } + ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 3rd read. \n"); - printf("\nStart *4 cross talk pattern n2. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);} - ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd write. "); - printf("\rStart 1st reading... ");} - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... ");} - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) { - printf("\rEnd 2nd read. "); - printf("\rStart 3rd reading... ");} - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size); - if (print_flag) - printf("\rEnd 3rd read. \n"); + printf("\nStart *4 cross talk pattern n2. "); + printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size); + } + ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd write. "); + printf("\rStart 1st reading... "); + } + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 1st read. "); + printf("\rStart 2nd reading... "); + } + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) { + printf("\rEnd 2nd read. "); + printf("\rStart 3rd reading... "); + } + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size); + if (print_flag) + printf("\rEnd 3rd read. \n"); - if (copy_test_flag) - { - ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 ); - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+test_size/2)), test_size/2); - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+test_size/2)), test_size/2); - } - // */ - + if (copy_test_flag) { + ddr_test_copy((void *)(int_convter_p(start_addr + test_size / 2)), (void *)(int_convter_p(start_addr)), test_size / 2); + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2); + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2); + } } if (print_flag) printf("\nError count==0x%08x", error_count); - - }while(--loop); - //*/ + } while (--loop); printf("\rEnd ddr test. \n"); @@ -5004,145 +4553,119 @@ } U_BOOT_CMD( - ddrtest, 5, 1, do_ddr_test, + ddrtest, 5, 1, do_ddr_test, "DDR test function", "ddrtest [LOOP] [ADDR].Default address is 0x8d000000\n" -); + ); -int do_ddr_special_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_special_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { char *endp; - unsigned int loop = 1; - unsigned int lflag = 0; - unsigned int start_addr = DDR_TEST_START_ADDR; + unsigned int loop = 1; + unsigned int lflag = 0; + unsigned int start_addr = DDR_TEST_START_ADDR; unsigned int test_addr = DDR_TEST_START_ADDR; - unsigned int test_size = DDR_TEST_SIZE; - unsigned int write_times = 1; - unsigned int read_times = 3; - // unsigned int old_pattern_flag = 1; + unsigned int test_size = DDR_TEST_SIZE; + unsigned int write_times = 1; + unsigned int read_times = 3; - unsigned int print_flag = 1; - // copy_test_flag = 0; + unsigned int print_flag = 1; + print_flag = 1; - error_outof_count_flag =0; - error_count =0; + error_outof_count_flag = 0; + error_count = 0; printf("\nargc== 0x%08x\n", argc); - int i ; - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } + int i; + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); if (strcmp(argv[1], "l") == 0) { lflag = 1; - } - else if (strcmp(argv[1], "h") == 0){ + } else if (strcmp(argv[1], "h") == 0) { goto usage; - } - else{ + } else { loop = simple_strtoull_ddr(argv[1], &endp, 10); if (*argv[1] == 0 || *endp != 0) loop = 1; } - // printf("\nLINE== 0x%08x\n", __LINE__); - if (argc ==1) { - // start_addr = simple_strtoull_ddr(argv[2], &endp, 16); - // if (*argv[2] == 0 || *endp != 0) + if (argc == 1) { start_addr = DDR_TEST_START_ADDR; loop = 1; - } if (argc > 2) { start_addr = simple_strtoull_ddr(argv[2], &endp, 16); if (*argv[2] == 0 || *endp != 0) start_addr = DDR_TEST_START_ADDR; - } if (argc > 3) { test_size = simple_strtoull_ddr(argv[3], &endp, 16); if (*argv[3] == 0 || *endp != 0) test_size = DDR_TEST_SIZE; - } - if (test_size<0x1000) + if (test_size < 0x1000) test_size = DDR_TEST_SIZE; if (argc > 4) { write_times = simple_strtoull_ddr(argv[4], &endp, 16); if (*argv[4] == 0 || *endp != 0) write_times = 0; - } if (argc > 5) { read_times = simple_strtoull_ddr(argv[5], &endp, 16); if (*argv[5] == 0 || *endp != 0) read_times = 0; - } - unsigned int base_pattern = 1; - unsigned int inc_flag = 1; + unsigned int base_pattern = 1; + unsigned int inc_flag = 1; if (argc > 6) { base_pattern = simple_strtoull_ddr(argv[6], &endp, 16); if (*argv[6] == 0 || *endp != 0) base_pattern = 0; - } if (argc > 7) { inc_flag = simple_strtoull_ddr(argv[7], &endp, 16); if (*argv[7] == 0 || *endp != 0) inc_flag = 0; - } - unsigned int count = 1; - unsigned int test_val = 1; + unsigned int count = 1; + unsigned int test_val = 1; - ///* do { if (lflag) loop = 888; - if (1) - { - - for (i=0;i<write_times;) - {i++; - printf("\nwrite_times==0x%08x \n",((unsigned int)i)); - test_addr=start_addr; - test_val=base_pattern; - count=(test_size>>2); - do - { - writel(test_val,(unsigned long)test_addr); - test_addr=test_addr+4; + if (1) { + for (i = 0; i < write_times; ) { + i++; + printf("\nwrite_times==0x%08x \n", ((unsigned int)i)); + test_addr = start_addr; + test_val = base_pattern; + count = (test_size >> 2); + do { + writel(test_val, (unsigned long)test_addr); + test_addr = test_addr + 4; if (inc_flag) - test_val=test_val+1; - - } - while (count--) ; + test_val = test_val + 1; + } while (count--); } - for (i=0;i<read_times;) - {i++; - printf("\nread_times==0x%08x \n",((unsigned int)i)); - test_addr=start_addr; - test_val=base_pattern; - count=(test_size>>2); + for (i = 0; i < read_times; ) { + i++; + printf("\nread_times==0x%08x \n", ((unsigned int)i)); + test_addr = start_addr; + test_val = base_pattern; + count = (test_size >> 2); - do - { + do { + if (test_val != (readl((unsigned long)test_addr))) - //writel(val,(unsigned long)reg); - if (test_val != (readl((unsigned long)test_addr))) { - - printf("\nadd==0x%08x,pattern==0x%08x,read==0x%08x \n",((unsigned int)test_addr),((unsigned int)test_val),(readl((unsigned int)test_addr))); - } - test_addr=test_addr+4; + printf("\nadd==0x%08x,pattern==0x%08x,read==0x%08x \n", ((unsigned int)test_addr), ((unsigned int)test_val), (readl((unsigned int)test_addr))); + test_addr = test_addr + 4; if (inc_flag) - test_val=test_val+1; - } - while (count--) ; + test_val = test_val + 1; + } while (count--); } } @@ -5150,9 +4673,7 @@ if (print_flag) printf("\nError count==0x%08x", error_count); - - }while(--loop); - //*/ + } while (--loop); printf("\rEnd ddr test. \n"); @@ -5163,41 +4684,35 @@ return 1; } U_BOOT_CMD( - ddr_spec_test, 8, 1, do_ddr_special_test, + ddr_spec_test, 8, 1, do_ddr_special_test, "DDR test function", "ddrtest [LOOP] [ADDR] [size] [write_times] [read times] [pattern] [inc].ddr_spec_test 1 0x1080000 0x200000 1 3 1 1 \n" -); + ); int ddr_test_s_cross_talk_pattern(int ddr_test_size) { -#define TEST_OFFSET 0//0X40000000 - // unsigned int start_addr = DDR_TEST_START_ADDR+TEST_OFFSET; - unsigned int start_addr=test_start_addr; +#define TEST_OFFSET 0 //0X40000000 + unsigned int start_addr = test_start_addr; - error_outof_count_flag=1; + error_outof_count_flag = 1; - error_count=0; + error_count = 0; -#if (CONFIG_DDR_PHY == P_DDR_PHY_905X) - training_pattern_flag=0; +#if (CONFIG_DDR_PHY == P_DDR_PHY_905X) + training_pattern_flag = 0; #endif - ///* - if (training_pattern_flag) - { -#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) + if (training_pattern_flag) { +#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) ddr_test_gx_training_pattern(ddr_test_size); #endif if (error_count) return 1; else return 0; - } - else - { -#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) + } else { +#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) ddr_test_gx_training_pattern(ddr_test_size); #endif - } { @@ -5210,7 +4725,7 @@ printf("\nStart 2nd reading... "); ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size); if (error_count) - return error_count; + return error_count; printf("\nStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\nEnd write. "); @@ -5221,7 +4736,7 @@ ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size); if (error_count) - return error_count; + return error_count; printf("\nStart *4 no cross talk pattern. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size); @@ -5235,7 +4750,6 @@ if (error_count) return error_count; - //if(cross_talk_pattern_flag==1) { printf("\nStart *4 cross talk pattern p. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); @@ -5249,7 +4763,7 @@ printf("\rEnd 2nd read. "); if (error_count) - return error_count; + return error_count; printf("\nStart *4 cross talk pattern n. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); @@ -5260,9 +4774,6 @@ printf("\rStart 2nd reading... "); ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\rEnd 2nd read. "); - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size); - // printf("\rEnd 3rd read. \n"); } if (error_count) return error_count; @@ -5278,11 +4789,8 @@ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\rEnd 2nd read. "); - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size); - // printf("\rEnd 3rd read. \n"); if (error_count) - return error_count; + return error_count; printf("\nStart *4 cross talk pattern n. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size); @@ -5294,14 +4802,13 @@ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\rEnd 2nd read. "); - if (copy_test_flag) - { + if (copy_test_flag) { if (error_count) - return error_count; + return error_count; printf("\n start copy test ... "); - ddr_test_copy((void *)(int_convter_p(start_addr+ddr_test_size/2)),(void *)(int_convter_p(start_addr)), ddr_test_size/2 ); - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2); - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2); + ddr_test_copy((void *)(int_convter_p(start_addr + ddr_test_size / 2)), (void *)(int_convter_p(start_addr)), ddr_test_size / 2); + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + ddr_test_size / 2)), ddr_test_size / 2); + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + ddr_test_size / 2)), ddr_test_size / 2); } } @@ -5309,49 +4816,34 @@ return 1; else return 0; - } - - +} int ddr_test_s_cross_talk_pattern_quick_retrun(int ddr_test_size) { - error_outof_count_flag =1; - #define TEST_OFFSET 0//0X40000000 - // unsigned int start_addr = DDR_TEST_START_ADDR+TEST_OFFSET; - unsigned int start_addr=test_start_addr; + error_outof_count_flag = 1; +#define TEST_OFFSET 0 //0X40000000 + unsigned int start_addr = test_start_addr; - error_outof_count_flag=1; + error_outof_count_flag = 1; - error_count=0; + error_count = 0; - #if (CONFIG_DDR_PHY == P_DDR_PHY_905X) - training_pattern_flag=0; - #endif - ///* - if (training_pattern_flag) - { - #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) +#if (CONFIG_DDR_PHY == P_DDR_PHY_905X) + training_pattern_flag = 0; +#endif + if (training_pattern_flag) { +#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) ddr_test_gx_training_pattern(ddr_test_size); - #endif - if (error_count) - return 1; - else - return 0; - } - else - { - #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) +#endif + if (error_count) + return 1; + else + return 0; + } else { +#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) ddr_test_gx_training_pattern(ddr_test_size); - #endif +#endif } - // */ - /* - ddr_test_gx_cross_talk_pattern( ddr_test_size); - if (error_count) - return 1; - else - return 0; - */ { printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); @@ -5382,7 +4874,6 @@ printf("\nStart 2nd reading... "); ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size); } - //if(cross_talk_pattern_flag==1) { printf("\nStart *4 cross talk pattern p. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); @@ -5395,10 +4886,6 @@ ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\rEnd 2nd read. "); - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size); - // printf("\rEnd 3rd read. \n"); - printf("\nStart *4 cross talk pattern n. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); @@ -5409,11 +4896,6 @@ printf("\rStart 2nd reading... "); ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\rEnd 2nd read. "); - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size); - // printf("\rEnd 3rd read. \n"); - - } { @@ -5428,10 +4910,6 @@ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\rEnd 2nd read. "); - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size); - // printf("\rEnd 3rd read. \n"); - printf("\nStart *4 cross talk pattern n. "); printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size); @@ -5442,17 +4920,12 @@ printf("\rStart 2nd reading... "); ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\rEnd 2nd read. "); - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size); - // printf("\rEnd 3rd read. \n"); - if (copy_test_flag) - { + if (copy_test_flag) { printf("\n start copy test ... "); - ddr_test_copy((void *)(int_convter_p(start_addr+ddr_test_size/2)),(void *)(int_convter_p(start_addr)), ddr_test_size/2 ); - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2); - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2); + ddr_test_copy((void *)(int_convter_p(start_addr + ddr_test_size / 2)), (void *)(int_convter_p(start_addr)), ddr_test_size / 2); + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + ddr_test_size / 2)), ddr_test_size / 2); + ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + ddr_test_size / 2)), ddr_test_size / 2); } - } if (error_count) @@ -5461,158 +4934,113 @@ return 0; } - -int do_ddr2pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr2pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - -#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12) - extern int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - do_ddr2pll_g12_cmd(cmdtp,flag,argc, argv); +#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12) + extern int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); + do_ddr2pll_g12_cmd(cmdtp, flag, argc, argv); return 1; #endif } -int do_ddr_uboot_new_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_uboot_new_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { //ddr_test_cmd 0x36 0x20180030 0x1 cmd_offset cmd_value value_size reset_enable -#if 1 +#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config +#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test -#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config -#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test - - uint32_t magic_chipid= 0;//rd_reg(P_PREG_STICKY_REG0); - uint32_t sticky_cmd = 0;//rd_reg(P_PREG_STICKY_REG1); + uint32_t magic_chipid = 0; //rd_reg(P_PREG_STICKY_REG0); + uint32_t sticky_cmd = 0; //rd_reg(P_PREG_STICKY_REG1); uint32_t cmd_offset = 0; uint32_t cmd_value = 0; uint32_t reset_enable = 0; uint32_t value_size = 4; char *endp; //bit 0 trigger effect reset. - if ((magic_chipid) != ((DDR_STICKY_MAGIC_NUMBER+DDR_CHIP_ID)&0xffff0000)) { + if ((magic_chipid) != ((DDR_STICKY_MAGIC_NUMBER + DDR_CHIP_ID) & 0xffff0000)) //magic number not match - // magic_chipid=DDR_STICKY_MAGIC_NUMBER+DDR_CHIP_ID; - // sticky_cmd=DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD; printf("sticky0 magic not match\n"); - } - - - // wr_reg(P_PREG_STICKY_REG0, 0); - // wr_reg(P_PREG_STICKY_REG1, 0); - - - printf("\nargc== 0x%08x\n", argc); - int i ; - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } - - + int i; + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); if (argc < 2) goto usage; - magic_chipid = simple_strtoull_ddr(argv[1], &endp,0); + magic_chipid = simple_strtoull_ddr(argv[1], &endp, 0); if (*argv[1] == 0 || *endp != 0) { - printf ("Error: Wrong format parament!\n"); + printf("Error: Wrong format parament!\n"); return 1; } - if (argc >2) - { + if (argc > 2) { sticky_cmd = simple_strtoull_ddr(argv[2], &endp, 0); - if (*argv[2] == 0 || *endp != 0) { + if (*argv[2] == 0 || *endp != 0) sticky_cmd = 0; - } } - if (argc >3) - { + if (argc > 3) { cmd_offset = simple_strtoull_ddr(argv[3], &endp, 0); - if (*argv[3] == 0 || *endp != 0) { + if (*argv[3] == 0 || *endp != 0) cmd_offset = 0; - } } - if (argc >4) - { - cmd_value= simple_strtoull_ddr(argv[4], &endp, 0); - if (*argv[4] == 0 || *endp != 0) { + if (argc > 4) { + cmd_value = simple_strtoull_ddr(argv[4], &endp, 0); + if (*argv[4] == 0 || *endp != 0) cmd_value = 0; - } } - if (argc >5) - { - value_size= simple_strtoull_ddr(argv[5], &endp, 0); - if (*argv[5] == 0 || *endp != 0) { + if (argc > 5) { + value_size = simple_strtoull_ddr(argv[5], &endp, 0); + if (*argv[5] == 0 || *endp != 0) value_size = 4; - } } - if (argc >6) - { - reset_enable= simple_strtoull_ddr(argv[6], &endp, 0); - if (*argv[6] == 0 || *endp != 0) { + if (argc > 6) { + reset_enable = simple_strtoull_ddr(argv[6], &endp, 0); + if (*argv[6] == 0 || *endp != 0) reset_enable = 0; - } } - printf("cmd_offset[0x%08x}==cmd_value [0x%08x]\n", cmd_offset,cmd_value); - writel((magic_chipid&0xffff0000)|(rd_reg((p_ddr_base->preg_sticky_reg0))), (p_ddr_base->preg_sticky_reg0)); - writel(sticky_cmd, (p_ddr_base->preg_sticky_reg0+4)); + printf("cmd_offset[0x%08x}==cmd_value [0x%08x]\n", cmd_offset, cmd_value); + writel((magic_chipid & 0xffff0000) | (rd_reg((p_ddr_base->preg_sticky_reg0))), (p_ddr_base->preg_sticky_reg0)); + writel(sticky_cmd, (p_ddr_base->preg_sticky_reg0 + 4)); uint32_t read_value = 0; - if (value_size) - { - read_value=rd_reg((p_ddr_base->ddr_dmc_sticky0)+((cmd_offset/4)<<2)); - if (value_size == 1) { - wr_reg(((p_ddr_base->ddr_dmc_sticky0)+((cmd_offset/4)<<2)), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xff<<((cmd_offset%4)*8)))))); - } - if (value_size == 2) { - wr_reg(((p_ddr_base->ddr_dmc_sticky0)+((cmd_offset/4)<<2)), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xffff<<((cmd_offset%4)*8)))))); - } - if (value_size == 4) { - // wr_reg(((p_ddr_base->ddr_dmc_sticky0)+cmd_offset/4), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xffff<<((cmd_offset%4)*8)))))); - wr_reg(((p_ddr_base->ddr_dmc_sticky0)+((cmd_offset/4)<<2)), cmd_value); - } + if (value_size) { + read_value = rd_reg((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2)); + if (value_size == 1) + wr_reg(((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2)), ((cmd_value << ((cmd_offset % 4) * 8)) | (read_value & (~(0xff << ((cmd_offset % 4) * 8)))))); + if (value_size == 2) + wr_reg(((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2)), ((cmd_value << ((cmd_offset % 4) * 8)) | (read_value & (~(0xffff << ((cmd_offset % 4) * 8)))))); + if (value_size == 4) + wr_reg(((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2)), cmd_value); - - - - printf("DMC_STICKY_0_ offset[0x%08x}== [0x%08x]\n", cmd_offset,readl(((p_ddr_base->ddr_dmc_sticky0)+((cmd_offset/4)<<2)))); + printf("DMC_STICKY_0_ offset[0x%08x}== [0x%08x]\n", cmd_offset, readl(((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2)))); } - printf("(p_ddr_base->preg_sticky_reg0)== [0x%08x]\n", readl((p_ddr_base->preg_sticky_reg0))); - if (reset_enable) - { + if (reset_enable) { ddr_test_watchdog_reset_system(); - while (1) ; + while (1) { + } } return 0; usage: - - - - - cmd_usage(cmdtp); -#endif return 1; } - -unsigned int -do_test_address_bus(volatile unsigned int * baseAddress, unsigned int nBytes) +unsigned int do_test_address_bus(volatile unsigned int *baseAddress, unsigned int nBytes) { - unsigned int addressMask = (nBytes/sizeof(unsigned int) - 1); + unsigned int addressMask = (nBytes / sizeof(unsigned int) - 1); unsigned int offset; unsigned int testOffset; - unsigned int pattern = (unsigned int) 0xAAAAAAAA; - unsigned int antipattern = (unsigned int) 0x55555555; + unsigned int pattern = (unsigned int)0xAAAAAAAA; + unsigned int antipattern = (unsigned int)0x55555555; unsigned int data1, data2; @@ -5622,9 +5050,7 @@ * Write the default pattern at each of the power-of-two offsets. */ for (offset = 1; (offset & addressMask) != 0; offset <<= 1) - { baseAddress[offset] = pattern; - } /* * Check for address bits stuck high. @@ -5632,21 +5058,17 @@ testOffset = 0; baseAddress[testOffset] = antipattern; - for (offset = 1; (offset & addressMask) != 0; offset <<= 1) - { + for (offset = 1; (offset & addressMask) != 0; offset <<= 1) { data1 = baseAddress[offset]; data2 = baseAddress[offset]; - if (data1 != data2) - { + if (data1 != data2) { printf(" memTestAddressBus - read twice different[offset]: 0x%8x-0x%8x\n", data1, data2); ret = 1; } - if (data1 != pattern) - { + if (data1 != pattern) { printf(" memTestAddressBus - write[0x%8x]: 0x%8x, read[0x%8x]: 0x%8x\n", \ - offset, pattern, offset, data1); + offset, pattern, offset, data1); ret = 1; - //return ((unsigned int) &baseAddress[offset]); } } @@ -5655,60 +5077,47 @@ /* * Check for address bits stuck low or shorted. */ - for (testOffset = 1; (testOffset & addressMask) != 0; testOffset <<= 1) - { + for (testOffset = 1; (testOffset & addressMask) != 0; testOffset <<= 1) { baseAddress[testOffset] = antipattern; - if (baseAddress[0] != pattern) - { + if (baseAddress[0] != pattern) { printf(" memTestAddressBus2 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0]: 0x%8x\n", \ - testOffset, antipattern, baseAddress[0]); + testOffset, antipattern, baseAddress[0]); ret = 1; - //return ((unsigned int) &baseAddress[testOffset]); } - for (offset = 1; (offset & addressMask) != 0; offset <<= 1) - { + for (offset = 1; (offset & addressMask) != 0; offset <<= 1) { data1 = baseAddress[offset]; - if ((data1 != pattern) && (offset != testOffset)) - { + if ((data1 != pattern) && (offset != testOffset)) { printf(" memTestAddressBus3 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \ - testOffset, antipattern, testOffset, data1); + testOffset, antipattern, testOffset, data1); ret = 1; - //return ((unsigned int) &baseAddress[testOffset]); } } baseAddress[testOffset] = pattern; } - - for (offset = 0x1; (offset <=addressMask) ; offset++) - { - if (((~offset) <= addressMask) ) - { + for (offset = 0x1; (offset <= addressMask); offset++) { + if (((~offset) <= addressMask)) { baseAddress[offset] = pattern; baseAddress[(~offset)] = antipattern; } } - for (offset = 0x1; (offset <=addressMask); offset++) - { - if (((~offset) <= addressMask) ) - { - if (baseAddress[offset] != pattern) - { + for (offset = 0x1; (offset <= addressMask); offset++) { + if (((~offset) <= addressMask)) { + if (baseAddress[offset] != pattern) { printf(" memTestAddressBus4 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \ - offset, pattern, offset, baseAddress[offset]); + offset, pattern, offset, baseAddress[offset]); ret = 1; break; } - if (baseAddress[(~offset)] != antipattern) - { + if (baseAddress[(~offset)] != antipattern) { printf(" memTestAddressBus5 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \ - ((~offset)), antipattern, ((~offset)), baseAddress[((~offset))]); + ((~offset)), antipattern, ((~offset)), baseAddress[((~offset))]); ret = 1; break; } @@ -5716,76 +5125,59 @@ } if (ret) - {return (ret); - } - //unsigned int suq_value; - for (offset = 0x1; (offset <=addressMask) ; offset++) - { + return ret; + for (offset = 0x1; (offset <= addressMask); offset++) { { - pattern=((offset<<2)-offset); + pattern = ((offset << 2) - offset); baseAddress[offset] = pattern; - //baseAddress[(~offset)] = antipattern; } } - for (offset = 0x1; (offset <=addressMask); offset++) - { - + for (offset = 0x1; (offset <= addressMask); offset++) { { - pattern=((offset<<2)-offset); - if (baseAddress[offset] != pattern) - { + pattern = ((offset << 2) - offset); + if (baseAddress[offset] != pattern) { printf(" memTestAddressBus6 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \ - offset,pattern, offset, baseAddress[offset]); + offset, pattern, offset, baseAddress[offset]); ret = 1; break; } - - } } + if (ret) - {return (ret); - } - for (offset = 0x1; (offset <=addressMask) ; offset++) - { + return ret; + for (offset = 0x1; (offset <= addressMask); offset++) { { - pattern=~((offset<<2)-offset); + pattern = ~((offset << 2) - offset); baseAddress[offset] = pattern; - //baseAddress[(~offset)] = antipattern; } } - for (offset = 0x1; (offset <=addressMask); offset++) - { - + for (offset = 0x1; (offset <= addressMask); offset++) { { - pattern=~((offset<<2)-offset); - if (baseAddress[offset] != pattern) - { + pattern = ~((offset << 2) - offset); + if (baseAddress[offset] != pattern) { printf(" memTestAddressBus7 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \ - offset,pattern, offset, baseAddress[offset]); + offset, pattern, offset, baseAddress[offset]); ret = 1; break; } - - } } - return (ret); + return ret; } /* memTestAddressBus() */ int ddr_test_s_add_cross_talk_pattern(int ddr_test_size) { - // unsigned int start_addr = DDR_TEST_START_ADDR; - unsigned int start_addr=test_start_addr; - error_outof_count_flag=1; - error_count=0; - ///* + unsigned int start_addr = test_start_addr; + + error_outof_count_flag = 1; + error_count = 0; printf("\rStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size); printf("\rEnd write. "); @@ -5794,245 +5186,133 @@ printf("\rEnd 1st read. "); printf("\rStart 2nd reading... "); ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size); - //*/ - /* - printf("\rStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); - ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd write. "); - printf("\rStart 1st reading... "); - ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... "); - ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size); - */ - ddr_write_full((void *)(int_convter_p(start_addr)), ddr_test_size,0x0,0x3); + ddr_write_full((void *)(int_convter_p(start_addr)), ddr_test_size, 0x0, 0x3); printf("\rEnd write. "); printf("\rStart 1st reading... "); - ddr_read_full((void *)(int_convter_p(start_addr)), ddr_test_size,0,3); + ddr_read_full((void *)(int_convter_p(start_addr)), ddr_test_size, 0, 3); printf("\rEnd 1st read. "); printf("\rStart 2nd reading... "); - ddr_read_full((void *)(int_convter_p(start_addr)), ddr_test_size,0,3); - + ddr_read_full((void *)(int_convter_p(start_addr)), ddr_test_size, 0, 3); printf("\rStart writing add pattern "); if (do_test_address_bus((void *)(int_convter_p(start_addr)), ddr_test_size)) error_count++; - - /* - printf("\nStart *4 no cross talk pattern. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); - ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\nEnd write. "); - printf("\nStart 1st reading... "); - ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\nEnd 1st read. "); - printf("\nStart 2nd reading... "); - ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size); - - //if(cross_talk_pattern_flag==1) - { - printf("\nStart *4 cross talk pattern p. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); - ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd write. "); - printf("\rStart 1st reading... "); - ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... "); - ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 2nd read. "); - - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size); - // printf("\rEnd 3rd read. \n"); - - printf("\nStart *4 cross talk pattern n. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); - ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd write. "); - printf("\rStart 1st reading... "); - ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... "); - ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 2nd read. "); - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); - // printf("\rEnd 3rd read. \n"); - - - } - - { - printf("\nStart *4 cross talk pattern p2. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); - ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd write. "); - printf("\rStart 1st reading... "); - ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... "); - ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 2nd read. "); - - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size); - // printf("\rEnd 3rd read. \n"); - - printf("\nStart *4 cross talk pattern n. "); - printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size); - ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd write. "); - printf("\rStart 1st reading... "); - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 1st read. "); - printf("\rStart 2nd reading... "); - ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size); - printf("\rEnd 2nd read. "); - // printf("\rStart 3rd reading... "); - // ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size); - // printf("\rEnd 3rd read. \n"); - - -} - */ -if (error_count) - return 1; + if (error_count) + return 1; else - return 0; - } + return 0; +} int pll_convert_to_ddr_clk_g12a(unsigned int ddr_pll) { - unsigned int ddr_clk=0; - unsigned int od_div=0xfff; - ddr_pll=ddr_pll&0xfffff; -#if 1// (CONFIG_DDR_PHY == P_DDR_PHY_905X) - //unsigned int ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))/(((ddr_pll>>2)&0x3)+1)); //od1 od - if (((ddr_pll>>16)&7) == 0) - od_div=2; - if (((ddr_pll>>16)&7) == 1) - od_div=3; + unsigned int ddr_clk = 0; + unsigned int od_div = 0xfff; - if (((ddr_pll>>16)&7) == 2) - od_div=4; + ddr_pll = ddr_pll & 0xfffff; + if (((ddr_pll >> 16) & 7) == 0) + od_div = 2; + if (((ddr_pll >> 16) & 7) == 1) + od_div = 3; - if (((ddr_pll>>16)&7) == 3) - od_div=6; + if (((ddr_pll >> 16) & 7) == 2) + od_div = 4; - if (((ddr_pll>>16)&7) == 4) - od_div=8; + if (((ddr_pll >> 16) & 7) == 3) + od_div = 6; - if (((ddr_pll>>10)&0x1f)) - ddr_clk = 2*((((24 * ((ddr_pll>>0)&0x1ff))/((ddr_pll>>10)&0x1f))>>((((ddr_pll>>19)&0x1)==1)?(2):(1))))/od_div; + if (((ddr_pll >> 16) & 7) == 4) + od_div = 8; -#else - ddr_clk = 2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3)); - -#endif - + if (((ddr_pll >> 10) & 0x1f)) + ddr_clk = 2 * ((((24 * ((ddr_pll >> 0) & 0x1ff)) / ((ddr_pll >> 10) & 0x1f)) >> ((((ddr_pll >> 19) & 0x1) == 1) ? (2) : (1)))) / od_div; return ddr_clk; } - int ddr_clk_convert_to_pll_g12a(unsigned int ddr_clk, unsigned char pll_bypass_en) { - uint32_t ddr_pll_vco_ctrl=0; - uint32_t ddr_pll_vco_m=0; - uint32_t ddr_pll_vco_n=0; - uint32_t ddr_pll_vco_ctrl_od=0; - uint32_t ddr_pll_vco_ctrl_od1=0; - ddr_pll_vco_n=1; + uint32_t ddr_pll_vco_ctrl = 0; + uint32_t ddr_pll_vco_m = 0; + uint32_t ddr_pll_vco_n = 0; + uint32_t ddr_pll_vco_ctrl_od = 0; + uint32_t ddr_pll_vco_ctrl_od1 = 0; + + ddr_pll_vco_n = 1; if (pll_bypass_en == 0) { - if ((ddr_clk >=4800/4)) { - //datarate==vco should 3-4.8g - ddr_pll_vco_ctrl_od=1; - ddr_pll_vco_ctrl_od1=0x2; //0 - ddr_pll_vco_m=(ddr_clk*3)/24; //6 - } - else if ((ddr_clk >4800/6)) { - ddr_pll_vco_ctrl_od=2; - ddr_pll_vco_ctrl_od1=0x2; //0 - ddr_pll_vco_m=(ddr_clk*4)/24; //8 - } - else if ((ddr_clk > 4800/8)) { - ddr_pll_vco_ctrl_od=3; - ddr_pll_vco_ctrl_od1=0x2; //0 - ddr_pll_vco_m=(ddr_clk*6)/24; //12 - } - else if ((ddr_clk > 4800/12)) { - ddr_pll_vco_ctrl_od=4; - ddr_pll_vco_ctrl_od1=0x2; //0 - ddr_pll_vco_m=(ddr_clk*8)/24; //16 - } - else if ((ddr_clk > 360)) { - ddr_pll_vco_ctrl_od=3; - ddr_pll_vco_ctrl_od1=0x3; //0 - ddr_pll_vco_m=(ddr_clk*12)/24; - } - else { - //32 should >200M - ddr_pll_vco_ctrl_od=4; - ddr_pll_vco_ctrl_od1=0x3;//0 - ddr_pll_vco_m=(ddr_clk*16)/24; + if ((ddr_clk >= 4800 / 4)) { + ddr_pll_vco_ctrl_od = 1; + ddr_pll_vco_ctrl_od1 = 0x2; //0 + ddr_pll_vco_m = (ddr_clk * 3) / 24; //6 + } else if ((ddr_clk > 4800 / 6)) { + ddr_pll_vco_ctrl_od = 2; + ddr_pll_vco_ctrl_od1 = 0x2; //0 + ddr_pll_vco_m = (ddr_clk * 4) / 24; //8 + } else if ((ddr_clk > 4800 / 8)) { + ddr_pll_vco_ctrl_od = 3; + ddr_pll_vco_ctrl_od1 = 0x2; //0 + ddr_pll_vco_m = (ddr_clk * 6) / 24; //12 + } else if ((ddr_clk > 4800 / 12)) { + ddr_pll_vco_ctrl_od = 4; + ddr_pll_vco_ctrl_od1 = 0x2; //0 + ddr_pll_vco_m = (ddr_clk * 8) / 24; //16 + } else if ((ddr_clk > 360)) { + ddr_pll_vco_ctrl_od = 3; + ddr_pll_vco_ctrl_od1 = 0x3; //0 + ddr_pll_vco_m = (ddr_clk * 12) / 24; + } else { + ddr_pll_vco_ctrl_od = 4; + ddr_pll_vco_ctrl_od1 = 0x3; //0 + ddr_pll_vco_m = (ddr_clk * 16) / 24; } } if (pll_bypass_en == 1) { - ddr_pll_vco_ctrl_od1=0x3;//0 - if ((ddr_clk >=800)) { - //datarate==vco should 2.4-4.8g - ddr_pll_vco_ctrl_od=0; - ddr_pll_vco_m=(ddr_clk*4)/24; - } - else if ((ddr_clk < 4800/6)) { - ddr_pll_vco_ctrl_od=1; - ddr_pll_vco_m=(ddr_clk*2*3)/24; - } - else if ((ddr_clk < 4800/8)) { - ddr_pll_vco_ctrl_od=2; - ddr_pll_vco_m=(ddr_clk*2*4)/24; - } - else if ((ddr_clk < 4800/12)) { - ddr_pll_vco_ctrl_od=3; - ddr_pll_vco_m=(ddr_clk*2*6)/24; - } - else if ((ddr_clk < 4800/16)) { - ddr_pll_vco_ctrl_od=4; - ddr_pll_vco_m=(ddr_clk*2*8)/24; + ddr_pll_vco_ctrl_od1 = 0x3; //0 + if ((ddr_clk >= 800)) { + ddr_pll_vco_ctrl_od = 0; + ddr_pll_vco_m = (ddr_clk * 4) / 24; + } else if ((ddr_clk < 4800 / 6)) { + ddr_pll_vco_ctrl_od = 1; + ddr_pll_vco_m = (ddr_clk * 2 * 3) / 24; + } else if ((ddr_clk < 4800 / 8)) { + ddr_pll_vco_ctrl_od = 2; + ddr_pll_vco_m = (ddr_clk * 2 * 4) / 24; + } else if ((ddr_clk < 4800 / 12)) { + ddr_pll_vco_ctrl_od = 3; + ddr_pll_vco_m = (ddr_clk * 2 * 6) / 24; + } else if ((ddr_clk < 4800 / 16)) { + ddr_pll_vco_ctrl_od = 4; + ddr_pll_vco_m = (ddr_clk * 2 * 8) / 24; } } - ddr_pll_vco_ctrl=ddr_pll_vco_m|(ddr_pll_vco_n<<10)|(ddr_pll_vco_ctrl_od<<16)|(ddr_pll_vco_ctrl_od1<<19); + ddr_pll_vco_ctrl = ddr_pll_vco_m | (ddr_pll_vco_n << 10) | (ddr_pll_vco_ctrl_od << 16) | (ddr_pll_vco_ctrl_od1 << 19); return ddr_pll_vco_ctrl; - - //return ddr_pll_vco_ctrl; } + int pll_convert_to_ddr_clk(unsigned int ddr_pll) { - unsigned int ddr_clk=0; - ddr_pll=ddr_pll&0xfffff; + unsigned int ddr_clk = 0; -#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12) - // printf("\ng12 ddr_pll== %08x \n", ddr_pll); - ddr_clk=pll_convert_to_ddr_clk_g12a( ddr_pll); + ddr_pll = ddr_pll & 0xfffff; + +#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12) + ddr_clk = pll_convert_to_ddr_clk_g12a(ddr_pll); return ddr_clk; #endif -#if (CONFIG_DDR_PHY == P_DDR_PHY_905X) - //unsigned int ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))/(((ddr_pll>>2)&0x3)+1)); - if (((ddr_pll>>16)&0x1f)) +#if (CONFIG_DDR_PHY == P_DDR_PHY_905X) + if (((ddr_pll >> 16) & 0x1f)) - ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))>>((((ddr_pll>>2)&0x3)==3)?(2):(((ddr_pll>>2)&0x3)))); + ddr_clk = 2 * ((((24 * ((ddr_pll >> 4) & 0x1ff)) / ((ddr_pll >> 16) & 0x1f)) >> ((((ddr_pll >> 0) & 0x3) == 3) ? (2) : (((ddr_pll >> 0) & 0x3)))) >> ((((ddr_pll >> 2) & 0x3) == 3) ? (2) : (((ddr_pll >> 2) & 0x3)))); #else - if ((ddr_pll>>9)&0x1f) - ddr_clk = 2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3)); + if ((ddr_pll >> 9) & 0x1f) + ddr_clk = 2 * (((24 * (ddr_pll & 0x1ff)) / ((ddr_pll >> 9) & 0x1f)) >> ((ddr_pll >> 16) & 0x3)); #endif #if (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT) - if ((ddr_pll>>9)&0x1f) - ddr_clk = 2*((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3); + if ((ddr_pll >> 9) & 0x1f) + ddr_clk = 2 * ((24 * (ddr_pll & 0x1ff)) / ((ddr_pll >> 9) & 0x1f)) >> ((ddr_pll >> 16) & 0x3); #endif return ddr_clk; @@ -6040,67 +5320,55 @@ int ddr_clk_convert_to_pll(unsigned int ddr_clk) { - unsigned int ddr_pll=0x10221; + unsigned int ddr_pll = 0x10221; -#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12) - ddr_pll=ddr_clk_convert_to_pll_g12a( ddr_clk,0); +#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12) + ddr_pll = ddr_clk_convert_to_pll_g12a(ddr_clk, 0); return ddr_pll; #endif /* set ddr pll reg */ - if ((ddr_clk >= 40) && (ddr_clk < 750)) { - // OD N M - ddr_pll= (2 << 16) | (1 << 9) | ((((ddr_clk/6)*6)/12) << 0); - } - else if((ddr_clk >= 750) && (ddr_clk < 2000)) { - // OD N M - ddr_pll= (1 << 16) | (1 << 9) | ((((ddr_clk/12)*12)/24) << 0); - } + if ((ddr_clk >= 40) && (ddr_clk < 750)) + ddr_pll = (2 << 16) | (1 << 9) | ((((ddr_clk / 6) * 6) / 12) << 0); + else if ((ddr_clk >= 750) && (ddr_clk < 2000)) + ddr_pll = (1 << 16) | (1 << 9) | ((((ddr_clk / 12) * 12) / 24) << 0); -#if (CONFIG_DDR_PHY == P_DDR_PHY_905X) - ddr_pll=0x00104c5; +#if (CONFIG_DDR_PHY == P_DDR_PHY_905X) + ddr_pll = 0x00104c5; /* set ddr pll reg */ /* - if ((ddr_clk >= 40) && (ddr_clk < 750)) { - // OD N M - ddr_pll= (2 << 2) | (1 << 16) | ((((ddr_clk/6)*6)/12) << 4); - } - else if((ddr_clk >= 750) && (ddr_clk < 2000)) { - // OD N M - ddr_pll= (1 << 2) | (1 << 16) | ((((ddr_clk/12)*12)/24) << 4); - } - */ - if ((ddr_clk < 200)) { + * if ((ddr_clk >= 40) && (ddr_clk < 750)) { + * // OD N M + * ddr_pll= (2 << 2) | (1 << 16) | ((((ddr_clk/6)*6)/12) << 4); + * } + * else if((ddr_clk >= 750) && (ddr_clk < 2000)) { + * // OD N M + * ddr_pll= (1 << 2) | (1 << 16) | ((((ddr_clk/12)*12)/24) << 4); + * } + */ + if ((ddr_clk < 200)) // OD1 OD N M - ddr_pll= (2 << 0) | (3 << 2) | (1 << 16) | ((((ddr_clk*6)/6)/3) << 4); - } - else if ((ddr_clk>= 200) && (ddr_clk< 400)) { + ddr_pll = (2 << 0) | (3 << 2) | (1 << 16) | ((((ddr_clk * 6) / 6) / 3) << 4); + else if ((ddr_clk >= 200) && (ddr_clk < 400)) // OD1 OD N M - ddr_pll= (2 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk*6)/6)/6) << 4); - } - else if ((ddr_clk>= 400) && (ddr_clk < 800)) { + ddr_pll = (2 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk * 6) / 6) / 6) << 4); + else if ((ddr_clk >= 400) && (ddr_clk < 800)) // OD1 OD N M - ddr_pll= (1 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk*12)/12)/12) << 4); - } - else if ((ddr_clk >= 800) && (ddr_clk < 2000)) { + ddr_pll = (1 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk * 12) / 12) / 12) << 4); + else if ((ddr_clk >= 800) && (ddr_clk < 2000)) // OD1 OD N M - ddr_pll= (0 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk*12)/12)/24) << 4); - } + ddr_pll = (0 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk * 12) / 12) / 24) << 4); + #endif #if (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT) { - - - if ((ddr_clk < 750)) { + if ((ddr_clk < 750)) // OD N M - ddr_pll= (2 << 16) | (1 << 9) | (((ddr_clk/24)*2)<< 0) ; - } - else if ((ddr_clk >= 750)) { + ddr_pll = (2 << 16) | (1 << 9) | (((ddr_clk / 24) * 2) << 0); + else if ((ddr_clk >= 750)) // OD N M - ddr_pll= (1 << 16) | (1 << 9) | ((ddr_clk/24)<< 0) ; - } - + ddr_pll = (1 << 16) | (1 << 9) | ((ddr_clk / 24) << 0); } #endif @@ -6109,389 +5377,274 @@ int get_ddr_clk(void) { - unsigned int ddr_clk=1000; - unsigned int ddr_pll=0; - if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_G12A) || - (p_ddr_base->chip_id==MESON_CPU_MAJOR_ID_G12B)|| - (p_ddr_base->chip_id==MESON_CPU_MAJOR_ID_TL1)|| - (p_ddr_base->chip_id==MESON_CPU_MAJOR_ID_SM1)|| - (p_ddr_base->chip_id==MESON_CPU_MAJOR_ID_TM2)|| - (p_ddr_base->chip_id==MESON_CPU_MAJOR_ID_C1)) - { - ddr_pll=rd_reg(p_ddr_base->ddr_pll_base_address); - ddr_pll=ddr_pll&0xfffff; - ddr_clk=pll_convert_to_ddr_clk_g12a( ddr_pll); - } - if (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_A1) - { - ddr_clk=768; + unsigned int ddr_clk = 10; + unsigned int ddr_pll = 0; + + if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_G12A) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_G12B) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_TL1) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_SM1) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_TM2) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C1) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_SC2) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7)) { + ddr_pll = rd_reg(p_ddr_base->ddr_pll_base_address); + ddr_pll = ddr_pll & 0xfffff; + ddr_clk = pll_convert_to_ddr_clk_g12a(ddr_pll); + } else if (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_A1) { + ddr_clk = 768; + } else if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D)) { + uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128); + ddr_clk = rd_reg(stick_store_sticky_f0_reg_base_t); + } else { + ddr_clk = 10; } return ddr_clk; -//#endif - //return ddr_clk; } + void ddr_memcpy(void *dst, const void *src, uint32_t len) { - //enable_mmu_el1_s(); - //printf("\nlen==%d,",len); - //printf(len); - //serial_puts("\n"); - //uint32_t ddr_test_start_time_us=get_us_time(); // check cost time - //const char *s = src; - //char *d = dst; - len=(len>>3); + len = (len >> 3); const long long *s = src; long long *d = dst; - #ifdef TEST_L1_CACHE - void *bound=(void *)src+16*1024; //debug for test L1 cache ,if only read write small aread - #endif - if (pre_fetch_enable) - { - while (len) - { - //if(pre_fetch_enable) - //for best test efficiency not inclued much more code in the while loop - ddr_pld_cache(s) ; - ///1 times len==33554432 copy time==18192 us 1.2g bandwidth 3688M/S - // 4times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S - // 8times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - len=len-4; - #ifdef TEST_L1_CACHE - if ((void *)s >=bound) - { - s=src; - d=dst; - } - #endif - } +#ifdef TEST_L1_CACHE + void *bound = (void *)src + 16 * 1024; //debug for test L1 cache ,if only read write small aread +#endif + if (pre_fetch_enable) { + while (len) { + //for best test efficiency not inclued much more code in the while loop + ddr_pld_cache(s); + ///1 times len==33554432 copy time==18192 us 1.2g bandwidth 3688M/S + // 4times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S + // 8times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + len = len - 4; +#ifdef TEST_L1_CACHE + if ((void *)s >= bound) { + s = src; + d = dst; } - else - { - while (len) - { //for best test efficiency not inclued much more code in the while loop - //if(pre_fetch_enable) - - // ddr_pld_cache(s) ; - ///1 times len==33554432 copy time==18192 us 1.2g bandwidth 3688M/S - // 4times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S - // 8times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - *d++ = *s++; - len=len-4; - #ifdef TEST_L1_CACHE - if ((void *)s >=bound) - { - s=src; - d=dst; - } - #endif - } +#endif + } + } else { + while (len) { //for best test efficiency not inclued much more code in the while loop + ///1 times len==33554432 copy time==18192 us 1.2g bandwidth 3688M/S + // 4times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S + // 8times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + *d++ = *s++; + len = len - 4; +#ifdef TEST_L1_CACHE + if ((void *)s >= bound) { + s = src; + d = dst; } - // uint32_t ddr_test_end_time_us=get_us_time(); // check cost time - // serial_puts("\ncopy time=="); - // serial_put_dec(ddr_test_end_time_us-ddr_test_start_time_us); - // serial_puts("\n"); - //printf("\ncopy time==%d us,",(ddr_test_end_time_us-ddr_test_start_time_us)); -} - -#define PATTERN_MATRIX_X (3+32+16+17) //68*32==2176 ///2.2k -0x880-1 loop -#define PATTERN_MATRIX_Y (32) -#define PATTERN_MATRIX_LOOP_SIZE ((PATTERN_MATRIX_X)*(PATTERN_MATRIX_Y)*4) - -unsigned int cpu_ddr_test_init_pattern_generater(unsigned int add_offset ) -{ - - unsigned int pattern_select=0; - unsigned int pattern_value=0; - //test_size=(test_size>0x10000)?test_size:0x10000; - // uint32_t write_addr = start_add; - uint32_t martix_x_select= 0; - uint32_t martix_y_select= 0; - unsigned int pattern_value_temp_16=0; - { - // uint32_t test_end_add = start_add+test_size; - // for((write_addr=start_add);(write_addr<test_end_add);) - { - pattern_select=((add_offset)%((PATTERN_MATRIX_Y)*(PATTERN_MATRIX_X))); - martix_x_select=pattern_select/(PATTERN_MATRIX_Y); - martix_y_select=pattern_select%(PATTERN_MATRIX_Y); - //write_addr_nibble_start=((((add_offset/PATTERN_MATRIX_Y)/PATTERN_MATRIX_X))* - // (((PATTERN_MATRIX_Y)*PATTERN_MATRIX_X))); - //write_addr_nibble_start=(((add_offset)%PATTERN_MATRIX_Y)%PATTERN_MATRIX_X) - { - if (martix_x_select == 0) - pattern_value=0xaaaa5555; //for 16 bit bus pattern - - if (martix_x_select == 1) - pattern_value=0x0000ffff; //for 16 bit bus pattern - - if (martix_x_select == 2) - pattern_value=0; - - if ((martix_x_select>2) && (martix_x_select<(3+32))) - { - pattern_value=1<<(martix_x_select-3); - } - if ((martix_x_select>(2+32)) && (martix_x_select<(3+32+16))) //for 16 bit bus pattern - { - pattern_value_temp_16=(1<<(martix_x_select-3-32)); - pattern_value=pattern_value_temp_16|((~pattern_value_temp_16)<<16); - } - if ((martix_x_select>(2+32+16)) && (martix_x_select<(3+32+16+17))) //for dbi bus pattern 17 group - { - pattern_value_temp_16=(0x0f0f+0xf0f*(martix_x_select-3-32-16)); - pattern_value=pattern_value_temp_16|((~pattern_value_temp_16)<<16); - } - } - if (martix_y_select%2) - pattern_value=~pattern_value; +#endif } } - // serial_puts("\ncpu_test_ddr_debug4"); +} + +#define PATTERN_MATRIX_X (3 + 32 + 16 + 17) //68*32==2176 ///2.2k -0x880-1 loop +#define PATTERN_MATRIX_Y (32) +#define PATTERN_MATRIX_LOOP_SIZE ((PATTERN_MATRIX_X)*(PATTERN_MATRIX_Y) * 4) + +unsigned int cpu_ddr_test_init_pattern_generater(unsigned int add_offset) +{ + unsigned int pattern_select = 0; + unsigned int pattern_value = 0; + uint32_t martix_x_select = 0; + uint32_t martix_y_select = 0; + unsigned int pattern_value_temp_16 = 0; + + { + { + pattern_select = ((add_offset) % ((PATTERN_MATRIX_Y)*(PATTERN_MATRIX_X))); + martix_x_select = pattern_select / (PATTERN_MATRIX_Y); + martix_y_select = pattern_select % (PATTERN_MATRIX_Y); + { + if (martix_x_select == 0) + pattern_value = 0xaaaa5555; //for 16 bit bus pattern + + if (martix_x_select == 1) + pattern_value = 0x0000ffff; //for 16 bit bus pattern + + if (martix_x_select == 2) + pattern_value = 0; + + if ((martix_x_select > 2) && (martix_x_select < (3 + 32))) + pattern_value = 1 << (martix_x_select - 3); + if ((martix_x_select > (2 + 32)) && (martix_x_select < (3 + 32 + 16))) { //for 16 bit bus pattern + pattern_value_temp_16 = (1 << (martix_x_select - 3 - 32)); + pattern_value = pattern_value_temp_16 | ((~pattern_value_temp_16) << 16); + } + if ((martix_x_select > (2 + 32 + 16)) && (martix_x_select < (3 + 32 + 16 + 17))) { //for dbi bus pattern 17 group + pattern_value_temp_16 = (0x0f0f + 0xf0f * (martix_x_select - 3 - 32 - 16)); + pattern_value = pattern_value_temp_16 | ((~pattern_value_temp_16) << 16); + } + } + if (martix_y_select % 2) + pattern_value = ~pattern_value; + } + } return pattern_value; } -void cpu_ddr_test_init_pattern_area(unsigned int test_init_start,unsigned int test_size,unsigned int parttern_frequency_setting ) +void cpu_ddr_test_init_pattern_area(unsigned int test_init_start, unsigned int test_size, unsigned int parttern_frequency_setting) { - // printf("\n 111"); if (parttern_frequency_setting == 0) - parttern_frequency_setting=1; //for different frequency pattern - test_size=(test_size>((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)))?test_size:((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)); - //unsigned int test_start=0x1080000; - unsigned int write_add=test_init_start; - unsigned int size_loop=0; - unsigned int size_loop_max=0; - //unsigned int count=0; - for (;(size_loop<((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)));) - { - //serial_puts("\ncpu_test_ddr_debug5"); - - // for( count=0;count<(parttern_frequency_setting);) + parttern_frequency_setting = 1; //for different frequency pattern + test_size = (test_size > ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))) ? test_size : ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)); + unsigned int write_add = test_init_start; + unsigned int size_loop = 0; + unsigned int size_loop_max = 0; + for (; (size_loop < ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))); ) { { write_add = (uint32_t)(size_loop + test_init_start); - wr_reg((unsigned long)write_add, cpu_ddr_test_init_pattern_generater((size_loop>>2)/parttern_frequency_setting)); - size_loop=size_loop+4; + wr_reg((unsigned long)write_add, cpu_ddr_test_init_pattern_generater((size_loop >> 2) / parttern_frequency_setting)); + size_loop = size_loop + 4; } - // serial_puts("\ncpu_test_ddr_debug6"); - - // serial_puts(" "); - #if 0 - serial_put_hex(size_loop,32); - serial_puts(" "); - serial_put_hex(cpu_ddr_test_init_pattern_generater(size_loop>>2),32); - #endif } - size_loop=1; - size_loop_max=((test_size/(((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))))+1); - for (;(size_loop<size_loop_max);) - { - // serial_puts("\ncpu_test_ddr_debug41"); - ddr_memcpy((void *)(uint64_t)(test_init_start+((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))*(size_loop)), (void *)(uint64_t)test_init_start, ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))); - //serial_puts("\ncpu_test_ddr_debug42"); + size_loop = 1; + size_loop_max = ((test_size / (((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)))) + 1); + for (; (size_loop < size_loop_max); ) { + ddr_memcpy((void *)(uint64_t)(test_init_start + ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)) * (size_loop)), (void *)(uint64_t)test_init_start, ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))); size_loop++; } } -unsigned int cpu_ddr_test(unsigned test_init_start,unsigned int start_add, unsigned int test_size, unsigned int test_data_bit_enable,unsigned int parttern_frequency_setting) +unsigned int cpu_ddr_test(unsigned test_init_start, unsigned int start_add, unsigned int test_size, unsigned int test_data_bit_enable, unsigned int parttern_frequency_setting) { - //printf("\n 1112"); + unsigned int src_add = test_init_start; + unsigned int pattern_value = 0; + unsigned int size_loop = 0; + unsigned int ddr_test_error = 0; + unsigned int read_add = 0; + unsigned int read_value = 0; - unsigned int src_add=test_init_start; - unsigned int pattern_value=0; - unsigned int size_loop=0; - unsigned int ddr_test_error=0; - unsigned int read_add=0; - unsigned int read_value=0; - test_size=(test_size>0x2000)?(test_size):(0x2000); - //cpu_ddr_test_init_pattern_area(test_size); - uint32_t ddr_test_start_time_us=get_us_time(); // check cost time + test_size = (test_size > 0x2000) ? (test_size) : (0x2000); + uint32_t ddr_test_start_time_us = get_us_time(); // check cost time ddr_memcpy((void *)(uint64_t)start_add, (void *)(uint64_t)src_add, test_size); - uint32_t ddr_test_end_time_us=get_us_time(); // check cost time - printf("\ncpu_ddr_test_test_copy_bandwidth==%d Mbyte/s\n",(1*test_size*2)/(ddr_test_end_time_us-ddr_test_start_time_us)); + uint32_t ddr_test_end_time_us = get_us_time(); // check cost time + printf("\ncpu_ddr_test_test_copy_bandwidth==%d Mbyte/s\n", (1 * test_size * 2) / (ddr_test_end_time_us - ddr_test_start_time_us)); - for (;size_loop<(test_size);) - { + for (; size_loop < (test_size); ) { read_add = (uint32_t)(size_loop + start_add); - read_value=(rd_reg((unsigned long)read_add)); - pattern_value=( cpu_ddr_test_init_pattern_generater((size_loop>>2)/parttern_frequency_setting)); - if (((test_data_bit_enable)&read_value) != ((test_data_bit_enable)&pattern_value)) - { - #if 1 - printf("error data enable %08x read_value %08x pattern_value %08x",test_data_bit_enable,read_value,pattern_value); - #if 0 - serial_puts("\nerror data "); - serial_put_hex(test_data_bit_enable,32); - serial_puts(" "); - serial_put_hex(read_value,32); - serial_puts(" "); - serial_put_hex(pattern_value,32); - serial_puts("\n"); - #endif - #endif + read_value = (rd_reg((unsigned long)read_add)); + pattern_value = (cpu_ddr_test_init_pattern_generater((size_loop >> 2) / parttern_frequency_setting)); + if (((test_data_bit_enable) & read_value) != ((test_data_bit_enable) & pattern_value)) { + printf("error data enable %08x read_value %08x pattern_value %08x", test_data_bit_enable, read_value, pattern_value); ddr_test_error++; return ddr_test_error; } - size_loop=size_loop+(1<<2);// use big step will fast test ,but lose accuracy. + size_loop = size_loop + (1 << 2); // use big step will fast test ,but lose accuracy. } - //printf("\n 1114"); return ddr_test_error; } -int do_cpu_ddr_test (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_cpu_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { check_base_address(); - //ddr_cpu_test 0x1080000 0x10000000 0x2000000 0xffffffff 10 //size do not overlap - int i=0; + int i = 0; printf("\nargc== 0x%08x\n", argc); - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } - unsigned int init_start_add=0; - unsigned int test_add=0; - unsigned int test_size=0; - unsigned int test_data_bit_enable=0; - unsigned int test_loops=0; - unsigned int test_loop=0; - unsigned int test_errors=0; - unsigned int parttern_frequency_setting =1; + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); + unsigned int init_start_add = 0; + unsigned int test_add = 0; + unsigned int test_size = 0; + unsigned int test_data_bit_enable = 0; + unsigned int test_loops = 0; + unsigned int test_loop = 0; + unsigned int test_errors = 0; + unsigned int parttern_frequency_setting = 1; char *endp; - if (argc == 1) + if (argc == 1) { printf("\nplease read help\n"); - else - { + } else { if (argc >= 2) - { - // zq0pr0 = argv[1]; - init_start_add= simple_strtoull_ddr(argv[1], &endp, 0); - } + init_start_add = simple_strtoull_ddr(argv[1], &endp, 0); if (argc >= 3) - { - // zq1pr0 = argv[2]; - test_add= simple_strtoull_ddr(argv[2], &endp, 0); - } + test_add = simple_strtoull_ddr(argv[2], &endp, 0); if (argc >= 4) - { - // zq1pr0 = argv[2]; - test_size= simple_strtoull_ddr(argv[3], &endp, 0); - } + test_size = simple_strtoull_ddr(argv[3], &endp, 0); if (argc >= 5) - { - // zq1pr0 = argv[2]; - test_data_bit_enable= simple_strtoull_ddr(argv[4], &endp, 0); - } - if (argc >= 6) - { - // zq1pr0 = argv[2]; - test_loops= simple_strtoull_ddr(argv[5], &endp, 0); + test_data_bit_enable = simple_strtoull_ddr(argv[4], &endp, 0); + if (argc >= 6) { + test_loops = simple_strtoull_ddr(argv[5], &endp, 0); if (test_loops == 0) - test_loops=1; + test_loops = 1; } - if (argc >= 7) - { - // zq1pr0 = argv[2]; - parttern_frequency_setting= simple_strtoull_ddr(argv[6], &endp, 0); + if (argc >= 7) { + parttern_frequency_setting = simple_strtoull_ddr(argv[6], &endp, 0); if (parttern_frequency_setting == 0) - parttern_frequency_setting=1; + parttern_frequency_setting = 1; } if (argc >= 8) - { - pre_fetch_enable= simple_strtoull_ddr(argv[7], &endp, 0); - - } + pre_fetch_enable = simple_strtoull_ddr(argv[7], &endp, 0); } - uint32_t ddr_test_start_time_us=get_us_time(); // check cost time - cpu_ddr_test_init_pattern_area(init_start_add,test_size,parttern_frequency_setting); - for (test_loop=0;test_loop<test_loops;) - { - test_errors=test_errors+cpu_ddr_test(init_start_add,test_add,test_size,test_data_bit_enable,parttern_frequency_setting); + uint32_t ddr_test_start_time_us = get_us_time(); // check cost time + cpu_ddr_test_init_pattern_area(init_start_add, test_size, parttern_frequency_setting); + for (test_loop = 0; test_loop < test_loops; ) { + test_errors = test_errors + cpu_ddr_test(init_start_add, test_add, test_size, test_data_bit_enable, parttern_frequency_setting); test_loop++; - printf("\ncpu_ddr_test_test_times==%d test_errors==%d",test_loop,test_errors); + printf("\ncpu_ddr_test_test_times==%d test_errors==%d", test_loop, test_errors); } - uint32_t ddr_test_end_time_us=get_us_time(); // check cost time - printf("\ncpu_ddr_test_test_and compare_bandwidth==%d Mbyte/s\n",(test_loops*test_size*2)/(ddr_test_end_time_us-ddr_test_start_time_us)); + uint32_t ddr_test_end_time_us = get_us_time(); // check cost time + printf("\ncpu_ddr_test_test_and compare_bandwidth==%d Mbyte/s\n", (test_loops * test_size * 2) / (ddr_test_end_time_us - ddr_test_start_time_us)); return test_errors; } + U_BOOT_CMD( - ddr_cpu_test, 30, 1, do_cpu_ddr_test, + ddr_cpu_test, 30, 1, do_cpu_ddr_test, "ddr_test_cmd cmd arg1 arg2 arg3...", "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n" ); -int do_ddr_test_write_read (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_test_write_read(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - ///* { printf("\nEnter do_ddr_test_ddr_write_read_current\n"); - // if(!argc) - // goto DDR_TUNE_DQS_START; - int i=0; + int i = 0; printf("\nargc== 0x%08x\n", argc); - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); char *endp; - unsigned int pattern_id=1; - unsigned int pattern[4] ={0}; - unsigned int write_read=0; - unsigned int read_pattern[4]={0} ; - unsigned int loop=1; - unsigned int start_addr = DDR_TEST_START_ADDR; - unsigned int test_size = DDR_TEST_SIZE; - unsigned int copy_offset= DDR_TEST_SIZE; - unsigned int no_show_info= 0; - unsigned int us_delay_counter= 0; + unsigned int pattern_id = 1; + unsigned int pattern[4] = { 0 }; + unsigned int write_read = 0; + unsigned int read_pattern[4] = { 0 }; + unsigned int loop = 1; + unsigned int start_addr = DDR_TEST_START_ADDR; + unsigned int test_size = DDR_TEST_SIZE; + unsigned int copy_offset = DDR_TEST_SIZE; + unsigned int no_show_info = 0; + unsigned int us_delay_counter = 0; - if (argc == 1) + if (argc == 1) { printf("\nplease read help\n"); - else { + } else { if (argc >= 2) - { - // zq0pr0 = argv[1]; - write_read= simple_strtoull_ddr(argv[1], &endp, 0); - } - + write_read = simple_strtoull_ddr(argv[1], &endp, 0); if (argc >= 3) - { - // zq1pr0 = argv[2]; - pattern_id= simple_strtoull_ddr(argv[2], &endp, 0); - } + pattern_id = simple_strtoull_ddr(argv[2], &endp, 0); if (argc >= 4) - { - // zq1pr0 = argv[2]; - loop= simple_strtoull_ddr(argv[3], &endp, 0); - } - if (argc >=5) - { - // zq1pr0 = argv[2]; - start_addr= simple_strtoull_ddr(argv[4], &endp, 0); - } - if (argc >=6) - { - // zq1pr0 = argv[2]; - test_size= simple_strtoull_ddr(argv[5], &endp, 0); - } - if (argc >=7) - { - // zq1pr0 = argv[2]; - no_show_info= simple_strtoull_ddr(argv[6], &endp, 0); - } - if (argc >=8) - { - // zq1pr0 = argv[2]; - us_delay_counter= simple_strtoull_ddr(argv[7], &endp, 0); - } + loop = simple_strtoull_ddr(argv[3], &endp, 0); + if (argc >= 5) + start_addr = simple_strtoull_ddr(argv[4], &endp, 0); + if (argc >= 6) + test_size = simple_strtoull_ddr(argv[5], &endp, 0); + if (argc >= 7) + no_show_info = simple_strtoull_ddr(argv[6], &endp, 0); + if (argc >= 8) + us_delay_counter = simple_strtoull_ddr(argv[7], &endp, 0); } printf("\nwrite_read== 0x%08d\n", write_read); printf("\npattern_id== 0x%08d\n", pattern_id); @@ -6499,2442 +5652,1693 @@ printf("\nstart_addr== 0x%08x\n", start_addr); printf("\ntest_size== 0x%08x\n", test_size); printf("\nus_delay_counter== %d\n", us_delay_counter); - copy_offset=test_size; + copy_offset = test_size; - unsigned int *p; - unsigned int j; + unsigned int *p; + unsigned int j; + p = (unsigned int *)(int_convter_p(start_addr)); - p = (unsigned int * )(int_convter_p(start_addr)); - - if (pattern_id == 0) - { - pattern[0]=0; - pattern[1]=0; - pattern[2]=0; - pattern[3]=0; + if (pattern_id == 0) { + pattern[0] = 0; + pattern[1] = 0; + pattern[2] = 0; + pattern[3] = 0; } - if (pattern_id == 1) - { - pattern[0]=0xffffffff; - pattern[1]=0xffffffff; - pattern[2]=0xffffffff; - pattern[3]=0xffffffff; + if (pattern_id == 1) { + pattern[0] = 0xffffffff; + pattern[1] = 0xffffffff; + pattern[2] = 0xffffffff; + pattern[3] = 0xffffffff; } - - do - { - if (write_read == 0) - { + do { + if (write_read == 0) { if (!no_show_info) - printf("\nloop:0x%08x:Start writing at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size); - for (j=0;j<test_size/4;) - { - *(p+j)=(pattern[0]); - *(p+j+1)=(pattern[1]); - *(p+j+2)=(pattern[2]); - *(p+j+3)=(pattern[3]); - j=j+4; + printf("\nloop:0x%08x:Start writing at 0x%08x - 0x%08x...", loop, start_addr, start_addr + test_size); + for (j = 0; j < test_size / 4; ) { + *(p + j) = (pattern[0]); + *(p + j + 1) = (pattern[1]); + *(p + j + 2) = (pattern[2]); + *(p + j + 3) = (pattern[3]); + j = j + 4; } } - if (write_read == 1) - { + if (write_read == 1) { if (!no_show_info) - printf("\nloop:0x%08x:Start reading at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size); - for (j=0;j<test_size/4;) - { - read_pattern[0]= *(p+j); - read_pattern[1]= *(p+j+1); - read_pattern[2]=*(p+j+2); - read_pattern[3]= *(p+j+3); - j=j+4; + printf("\nloop:0x%08x:Start reading at 0x%08x - 0x%08x...", loop, start_addr, start_addr + test_size); + for (j = 0; j < test_size / 4; ) { + read_pattern[0] = *(p + j); + read_pattern[1] = *(p + j + 1); + read_pattern[2] = *(p + j + 2); + read_pattern[3] = *(p + j + 3); + j = j + 4; } + if (loop == 1) { - if (!no_show_info) + if (!no_show_info) { printf(" \nloop:0x%08x:Start reading read_pattern[0] 0x%08x, pattern[1] 0x%08x,pattern[2] 0x%08x,pattern[3] 0x%08x", - loop,read_pattern[0], read_pattern[1],read_pattern[2],read_pattern[3] - ); } + loop, read_pattern[0], read_pattern[1], read_pattern[2], read_pattern[3] + ); + } + } } - if (write_read == 2) - { + if (write_read == 2) { if (!no_show_info) - printf("\nloop:0x%08x:Start copying at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size); - for (j=0;j<test_size/4;) - { - *(p+j+copy_offset/4)= *(p+j); - *(p+j+1+copy_offset/4)= *(p+j+1); - *(p+j+2+copy_offset/4)= *(p+j+2); - *(p+j+3+copy_offset/4)= *(p+j+3); - j=j+4; + printf("\nloop:0x%08x:Start copying at 0x%08x - 0x%08x...", loop, start_addr, start_addr + test_size); + for (j = 0; j < test_size / 4; ) { + *(p + j + copy_offset / 4) = *(p + j); + *(p + j + 1 + copy_offset / 4) = *(p + j + 1); + *(p + j + 2 + copy_offset / 4) = *(p + j + 2); + *(p + j + 3 + copy_offset / 4) = *(p + j + 3); + j = j + 4; } } if (us_delay_counter) - { ddr_udelay(us_delay_counter); - } - }while(loop--); + } while (loop--); printf("\ntest end\n"); return 1; } - //*/ } -#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12) +#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12) #define TEST_MIN_DDR_EE_VOLTAGE 681 #define TEST_MAX_DDR_EE_VOLTAGE 962 -//#define (p_ddr_base->ee_pwm_base_address) (0xff807000 + (0x001 << 2)) static int pwm_voltage_table_ee[][2] = { - { 0x1c0000, 681}, - { 0x1b0001, 691}, - { 0x1a0002, 701}, - { 0x190003, 711}, - { 0x180004, 721}, - { 0x170005, 731}, - { 0x160006, 741}, - { 0x150007, 751}, - { 0x140008, 761}, - { 0x130009, 772}, - { 0x12000a, 782}, - { 0x11000b, 792}, - { 0x10000c, 802}, - { 0x0f000d, 812}, - { 0x0e000e, 822}, - { 0x0d000f, 832}, - { 0x0c0010, 842}, - { 0x0b0011, 852}, - { 0x0a0012, 862}, - { 0x090013, 872}, - { 0x080014, 882}, - { 0x070015, 892}, - { 0x060016, 902}, - { 0x050017, 912}, - { 0x040018, 922}, - { 0x030019, 932}, - { 0x02001a, 942}, - { 0x01001b, 952}, - { 0x00001c, 962} + { 0x1c0000, 681 }, + { 0x1b0001, 691 }, + { 0x1a0002, 701 }, + { 0x190003, 711 }, + { 0x180004, 721 }, + { 0x170005, 731 }, + { 0x160006, 741 }, + { 0x150007, 751 }, + { 0x140008, 761 }, + { 0x130009, 772 }, + { 0x12000a, 782 }, + { 0x11000b, 792 }, + { 0x10000c, 802 }, + { 0x0f000d, 812 }, + { 0x0e000e, 822 }, + { 0x0d000f, 832 }, + { 0x0c0010, 842 }, + { 0x0b0011, 852 }, + { 0x0a0012, 862 }, + { 0x090013, 872 }, + { 0x080014, 882 }, + { 0x070015, 892 }, + { 0x060016, 902 }, + { 0x050017, 912 }, + { 0x040018, 922 }, + { 0x030019, 932 }, + { 0x02001a, 942 }, + { 0x01001b, 952 }, + { 0x00001c, 962 } }; uint32_t find_vddee_voltage_index(unsigned int target_voltage) { unsigned int to; + for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) { - if (pwm_voltage_table_ee[to][1] >= target_voltage) { + if (pwm_voltage_table_ee[to][1] >= target_voltage) break; - } } - if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) { + + if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) to = ARRAY_SIZE(pwm_voltage_table_ee) - 1; - } return to; } void set_ee_voltage(uint32_t ee_over_ride_voltage) { unsigned int to; - for (to = (ARRAY_SIZE(pwm_voltage_table_ee));( to >0); to--) { - if ((pwm_voltage_table_ee[to-1][1]<ee_over_ride_voltage) && (pwm_voltage_table_ee[to][1] >= ee_over_ride_voltage)) { + + for (to = (ARRAY_SIZE(pwm_voltage_table_ee)); (to > 0); to--) { + if ((pwm_voltage_table_ee[to - 1][1] < ee_over_ride_voltage) && (pwm_voltage_table_ee[to][1] >= ee_over_ride_voltage)) break; - } } + if (ee_over_ride_voltage) { - writel(pwm_voltage_table_ee[to][0],(p_ddr_base->ee_pwm_base_address)); - printf ("\nDDR_overide_EE_voltage ==%d mv /n",pwm_voltage_table_ee[to-1][1]); + writel(pwm_voltage_table_ee[to][0], (p_ddr_base->ee_pwm_base_address)); + if(to) + printf("\nDDR_overide_EE_voltage ==%d mv /n", pwm_voltage_table_ee[to - 1][1]); + else + printf("\nDDR_overide_EE_voltage ==%d mv /n", pwm_voltage_table_ee[to][1]); } } unsigned int read_ee_voltage(void) { unsigned int to; - unsigned int reg_value=0; - reg_value=readl((p_ddr_base->ee_pwm_base_address)); - to=reg_value&0xff; + unsigned int reg_value = 0; + + reg_value = readl((p_ddr_base->ee_pwm_base_address)); + to = reg_value & 0xff; return pwm_voltage_table_ee[to][1]; } + uint32_t get_bdlr_100step(uint32_t ddr_frequency) { - uint32_t bdlr_100step=0; - //uint32_t ps=0; - //ps=(rd_reg(DMC_DRAM_FREQ_CTRL))&1; - dwc_ddrphy_apb_wr(((((0<<20)|(2<<16)|(0<<12)|(0xe3)))),0xc00); - bdlr_100step=(100000000/(2*ddr_frequency))/((dwc_ddrphy_apb_rd((((0<<20)|(2<<16)|(0<<12)|(0xe4)))))&0x3ff); + uint32_t bdlr_100step = 0; + + if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D)) { + bdlr_100step = do_read_c2_ddr_bdlr_steps(); + } else { + dwc_ddrphy_apb_wr(((((0 << 20) | (2 << 16) | (0 << 12) | (0xe3)))), 0xc00); + bdlr_100step = (100000000 / (2 * ddr_frequency)) / ((dwc_ddrphy_apb_rd((((0 << 20) | (2 << 16) | (0 << 12) | (0xe4))))) & 0x3ff); + } return bdlr_100step; } -int do_ddr_test_pwm_bdlr (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_test_pwm_bdlr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { char *endp; + printf("\nEnter g12 do_ddr_test_pwm_bdl function\n"); - // if(!argc) - // goto DDR_TUNE_DQS_START; - int i=0; + int i = 0; printf("\nargc== 0x%08x\n", argc); - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); - //if (argc < 2) - // goto usage; - - - unsigned int argc_count=1; - unsigned int para_meter[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,}; - while (argc_count<argc) - {para_meter[argc_count-1]= simple_strtoul(argv[argc_count], &endp, 0); - if (*argv[argc_count] == 0 || *endp != 0) { - para_meter[argc_count-1] = 0; - } + unsigned int argc_count = 1; + unsigned int para_meter[30] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + while (argc_count < argc) { + para_meter[argc_count - 1] = simple_strtoul(argv[argc_count], &endp, 0); + if (*argv[argc_count] == 0 || *endp != 0) + para_meter[argc_count - 1] = 0; argc_count++; } - //uint32_t id=para_meter[0]; - //uint32_t voltage=para_meter[1]; - uint32_t loop=para_meter[0]; - uint32_t voltage_min=para_meter[1]; - uint32_t voltage_max=para_meter[2]; - uint32_t show_count_message=para_meter[3]; + uint32_t loop = para_meter[0]; + uint32_t voltage_min = para_meter[1]; + uint32_t voltage_max = para_meter[2]; + uint32_t show_count_message = para_meter[3]; - //#define PWM_ID_DEFAULT 0<<0 - //#define PWM_VOLTAGE_DEFAULT 800<<0 - #define PWM_LOOP_DEFAULT 10<<0 - #define PWM_VOLTAGE_MIN_DEFAULT TEST_MIN_DDR_EE_VOLTAGE - #define PWM_VOLTAGE_MAX_DEFAULT TEST_MAX_DDR_EE_VOLTAGE +#define PWM_LOOP_DEFAULT 10 << 0 +#define PWM_VOLTAGE_MIN_DEFAULT TEST_MIN_DDR_EE_VOLTAGE +#define PWM_VOLTAGE_MAX_DEFAULT TEST_MAX_DDR_EE_VOLTAGE + loop = loop ? loop : PWM_LOOP_DEFAULT; + voltage_min = (voltage_min < PWM_VOLTAGE_MIN_DEFAULT) ? PWM_VOLTAGE_MIN_DEFAULT : voltage_min; + voltage_max = (voltage_max > PWM_VOLTAGE_MAX_DEFAULT) ? PWM_VOLTAGE_MAX_DEFAULT : voltage_max; + voltage_max = (voltage_max < PWM_VOLTAGE_MIN_DEFAULT) ? PWM_VOLTAGE_MAX_DEFAULT : voltage_max; - //id=id?id:PWM_ID_DEFAULT; - //voltage=voltage?voltage:PWM_VOLTAGE_DEFAULT; - loop=loop?loop:PWM_LOOP_DEFAULT; - voltage_min=(voltage_min<PWM_VOLTAGE_MIN_DEFAULT)?PWM_VOLTAGE_MIN_DEFAULT:voltage_min; - voltage_max=(voltage_max>PWM_VOLTAGE_MAX_DEFAULT)?PWM_VOLTAGE_MAX_DEFAULT:voltage_max; - voltage_max=(voltage_max<PWM_VOLTAGE_MIN_DEFAULT)?PWM_VOLTAGE_MAX_DEFAULT:voltage_max; + uint16_t bdlr_100_min = 0; + uint16_t bdlr_100_average = 0; + uint16_t bdlr_100_max = 0; + uint16_t bdlr_100_cur = 0; + uint32_t count = 1; - // printf("\nvoltage_min=%d\n",voltage_min); - // printf("\nvoltage_max=%d\n",voltage_max); - uint16_t bdlr_100_min=0; - uint16_t bdlr_100_average=0; - uint16_t bdlr_100_max=0; - uint16_t bdlr_100_cur=0; - //uint16_t cur_ddr_frequency=0; - uint32_t count=1; + bdlr_100_cur = get_bdlr_100step(global_ddr_clk); + bdlr_100_min = bdlr_100_cur; + bdlr_100_max = bdlr_100_cur; + bdlr_100_average = bdlr_100_cur; - bdlr_100_cur=get_bdlr_100step(global_ddr_clk); - bdlr_100_min=bdlr_100_cur; - bdlr_100_max=bdlr_100_cur; - bdlr_100_average=bdlr_100_cur; - - unsigned int to=0; - unsigned int to_min=0; - unsigned int to_max=(ARRAY_SIZE(pwm_voltage_table_ee))-1; - //unsigned int temp_count=0; - printf("\nread org_EE_voltage %d mv \n",read_ee_voltage()); - to_min=find_vddee_voltage_index(voltage_min); - to_max=find_vddee_voltage_index(voltage_max); - for (to =(to_max+1) ;( to >to_min); to--) { - // printf("\nTO=%d\n",to); - writel(pwm_voltage_table_ee[to-1][0],(p_ddr_base->ee_pwm_base_address)); + unsigned int to = 0; + unsigned int to_min = 0; + unsigned int to_max = (ARRAY_SIZE(pwm_voltage_table_ee)) - 1; + printf("\nread org_EE_voltage %d mv \n", read_ee_voltage()); + to_min = find_vddee_voltage_index(voltage_min); + to_max = find_vddee_voltage_index(voltage_max); + for (to = (to_max + 1); (to > to_min); to--) { + writel(pwm_voltage_table_ee[to - 1][0], (p_ddr_base->ee_pwm_base_address)); udelay(1000); - bdlr_100_cur=get_bdlr_100step(global_ddr_clk); - bdlr_100_min=bdlr_100_cur; - bdlr_100_max=bdlr_100_cur; - bdlr_100_average=bdlr_100_cur; - count=1; - - // printf("\nDDR_set EE_voltage %d bdlr_100_average %d bdlr_100_min %d bdlr_100_max %d count %d,bdlr_100_cur %d \n",pwm_voltage_table_ee[to-1][1], - //bdlr_100_average,bdlr_100_min,bdlr_100_max,count,bdlr_100_cur); + bdlr_100_cur = get_bdlr_100step(global_ddr_clk); + bdlr_100_min = bdlr_100_cur; + bdlr_100_max = bdlr_100_cur; + bdlr_100_average = bdlr_100_cur; + count = 1; do { - bdlr_100_cur=(100000000/(2*global_ddr_clk))/((dwc_ddrphy_apb_rd((((0<<20)|(2<<16)|(0<<12)|(0xe4)))))&0x3ff); - bdlr_100_min=(bdlr_100_cur<bdlr_100_min)?bdlr_100_cur:bdlr_100_min; - bdlr_100_max=(bdlr_100_cur>bdlr_100_max)?bdlr_100_cur:bdlr_100_max; - bdlr_100_average=(bdlr_100_cur+bdlr_100_average*count)/(count+1); + bdlr_100_cur = (100000000 / (2 * global_ddr_clk)) / ((dwc_ddrphy_apb_rd((((0 << 20) | (2 << 16) | (0 << 12) | (0xe4))))) & 0x3ff); + bdlr_100_min = (bdlr_100_cur < bdlr_100_min) ? bdlr_100_cur : bdlr_100_min; + bdlr_100_max = (bdlr_100_cur > bdlr_100_max) ? bdlr_100_cur : bdlr_100_max; + bdlr_100_average = (bdlr_100_cur + bdlr_100_average * count) / (count + 1); count++; if (show_count_message) - printf("%d\n",bdlr_100_cur); - - }while(count<loop); - printf("\nDDR_set EE_voltage %d bdlr_100_average %d bdlr_100_min %d bdlr_100_max %d count %d",pwm_voltage_table_ee[to-1][1], - bdlr_100_average,bdlr_100_min,bdlr_100_max,count); + printf("%d\n", bdlr_100_cur); + } while (count < loop); + printf("\nDDR_set EE_voltage %d bdlr_100_average %d bdlr_100_min %d bdlr_100_max %d count %d", pwm_voltage_table_ee[to - 1][1], + bdlr_100_average, bdlr_100_min, bdlr_100_max, count); } return 1; } -int printf_log(char log_level,const char * fmt,...) +int printf_log(char log_level, const char *fmt, ...) { - if (log_level<1) - { + if (log_level < 1) { va_list args; - va_start(args,fmt); - vprintf(fmt,args); // + va_start(args, fmt); + vprintf(fmt, args); // va_end(args); return 0; - } - else + } else { return 1; + } } -int do_read_ddr_training_data(char log_level,ddr_set_t *ddr_set_t_p) + +int do_read_ddr_training_data(char log_level, ddr_set_t *ddr_set_t_p) { - -// ddr_set_t *ddr_set_t_p=NULL; -// ddr_set_t_p=(ddr_set_t *)(ddr_set_t_p_arrary); - printf_log(log_level,"\nddr_set_t_p==0x%08x\n",(uint32_t)(uint64_t)(ddr_set_t_p)); - uint32_t loop=0; - uint32_t loop_max = (4+(0x3f<<2));//((DMC_STICKY_63-DMC_STICKY_0)); - // loop_max=sizeof(ddr_set_t); - for (loop = 0; loop <loop_max; loop+=4) { + printf_log(log_level, "\nddr_set_t_p==0x%08x\n", (uint32_t)(uint64_t)(ddr_set_t_p)); + uint32_t loop = 0; + uint32_t loop_max = (4 + (0x3f << 2)); //((DMC_STICKY_63-DMC_STICKY_0)); + for (loop = 0; loop < loop_max; loop += 4) wr_reg(((uint64_t)(ddr_set_t_p) + loop), rd_reg((p_ddr_base->ddr_dmc_sticky0) + loop)); - } - for (loop = 0; loop <MESON_CPU_CHIP_ID_SIZE; loop++) //update chip id + for (loop = 0; loop < MESON_CPU_CHIP_ID_SIZE; loop++) //update chip id + ddr_sha.sha_chip_id[loop] = global_chip_id[loop]; { - ddr_sha.sha_chip_id[loop]=global_chip_id[loop]; - } - { - uint16_t dq_bit_delay[72]; - unsigned char t_count=0; - uint16_t delay_org=0; - uint16_t delay_temp=0; - uint32_t add_offset=0; - dwc_ddrphy_apb_wr(0xd0000,0x0); - bdlr_100step=get_bdlr_100step(global_ddr_clk); - ui_1_32_100step=(1000000*100/(global_ddr_clk*2*32)); - uint32_t ps=0; - for (ps=0;ps<2;ps++) - { + uint16_t dq_bit_delay[72]; + unsigned char t_count = 0; + uint16_t delay_org = 0; + uint16_t delay_temp = 0; + uint32_t add_offset = 0; + dwc_ddrphy_apb_wr(0xd0000, 0x0); + bdlr_100step = get_bdlr_100step(global_ddr_clk); + ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32)); + uint32_t ps = 0; + for (ps = 0; ps < 2; ps++) { { - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal=0; - printf_log(log_level,"\n ARdPtrInitVal ps=%d",ps); - add_offset=((ps<<20)|(2<<16)|(0<<12)|(0x2e)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal=delay_org; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal = 0; + printf_log(log_level, "\n ARdPtrInitVal ps=%d", ps); + add_offset = ((ps << 20) | (2 << 16) | (0 << 12) | (0x2e)); + delay_org = dwc_ddrphy_apb_rd(add_offset); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal = delay_org; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 0, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org); - printf_log(log_level,"\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL ps=%d",ps); - add_offset=((ps<<20)|(1<<16)|(0<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl=delay_org; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - add_offset=((ps<<20)|(1<<16)|(1<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",1,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - add_offset=((ps<<20)|(1<<16)|(2<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",2,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - add_offset=((ps<<20)|(1<<16)|(3<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",3,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); - add_offset=((ps<<20)|(2<<16)|(0<<12)|(0x20)); - delay_org=dwc_ddrphy_apb_rd(add_offset); + printf_log(log_level, "\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL ps=%d", ps); + add_offset = ((ps << 20) | (1 << 16) | (0 << 12) | (0x20)); + delay_org = dwc_ddrphy_apb_rd(add_offset); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl = delay_org; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 0, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org); + add_offset = ((ps << 20) | (1 << 16) | (1 << 12) | (0x20)); + delay_org = dwc_ddrphy_apb_rd(add_offset); + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 1, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org); + add_offset = ((ps << 20) | (1 << 16) | (2 << 12) | (0x20)); + delay_org = dwc_ddrphy_apb_rd(add_offset); + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 2, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org); + add_offset = ((ps << 20) | (1 << 16) | (3 << 12) | (0x20)); + delay_org = dwc_ddrphy_apb_rd(add_offset); + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 3, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org); + add_offset = ((ps << 20) | (2 << 16) | (0 << 12) | (0x20)); + delay_org = dwc_ddrphy_apb_rd(add_offset); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl=delay_org; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_org); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl = delay_org; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 0, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org); } { - printf_log(log_level,"\n count_index delay_value register_add register_value ps=%d\n ",ps); - printf_log(log_level,"\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI ps=%d",ui_1_32_100step,ps); - for (t_count=0;t_count<10;t_count++) - { - add_offset=((ps<<20)|(0<<16)|(t_count<<12)|(0x80)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + printf_log(log_level, "\n count_index delay_value register_add register_value ps=%d\n ", ps); + printf_log(log_level, "\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI ps=%d", ui_1_32_100step, ps); + for (t_count = 0; t_count < 10; t_count++) { + add_offset = ((ps << 20) | (0 << 16) | (t_count << 12) | (0x80)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_org = dq_bit_delay[t_count]; + delay_temp = (32 * (((delay_org >> 6) & 0xf) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f)); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } } { - printf_log(log_level,"\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI ps=%d",ui_1_32_100step,ps); - for (t_count=0;t_count<16;t_count++) - { - add_offset=((ps<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0xd0+(t_count/8)+((t_count%2)<<8))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); + printf_log(log_level, "\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI ps=%d", ui_1_32_100step, ps); + for (t_count = 0; t_count < 16; t_count++) { + add_offset = ((ps << 20) | (1 << 16) | (((t_count % 8) >> 1) << 12) | (0xd0 + (t_count / 8) + ((t_count % 2) << 8))); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_org = dq_bit_delay[t_count]; + delay_temp = (32 * (((delay_org >> 6) & 0xf) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f)); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[t_count]=delay_temp; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[t_count] = delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } } { - printf_log(log_level,"\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse ps=%d",ui_1_32_100step,ps); - for (t_count=0;t_count<16;t_count++) - { - add_offset=((ps<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x8c+(t_count/8)+((t_count%2)<<8))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + printf_log(log_level, "\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse ps=%d", ui_1_32_100step, ps); + for (t_count = 0; t_count < 16; t_count++) { + add_offset = ((ps << 20) | (1 << 16) | (((t_count % 8) >> 1) << 12) | (0x8c + (t_count / 8) + ((t_count % 2) << 8))); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_org = dq_bit_delay[t_count]; + delay_temp = (32 * (((delay_org >> 6) & 0xf) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f)); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } } { - printf_log(log_level,"\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U ps=%d",ui_1_32_100step,ps); - for (t_count=0;t_count<72;t_count++) - { - add_offset=((ps<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); + printf_log(log_level, "\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U ps=%d", ui_1_32_100step, ps); + for (t_count = 0; t_count < 72; t_count++) { + add_offset = ((ps << 20) | (1 << 16) | (((t_count % 36) / 9) << 12) | (0xc0 + ((t_count % 9) << 8) + (t_count / 36))); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_org = dq_bit_delay[t_count]; + delay_temp = (32 * (((delay_org >> 6) & 0xf) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f)); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } } { - printf_log(log_level,"\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse ps=%d",bdlr_100step,ps); - for (t_count=0;t_count<72;t_count++) - { - add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0x68+((t_count%9)<<8)+(t_count/36))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=((delay_org&0x3f)); + printf_log(log_level, "\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse ps=%d", bdlr_100step, ps); + for (t_count = 0; t_count < 72; t_count++) { + add_offset = ((0 << 20) | (1 << 16) | (((t_count % 36) / 9) << 12) | (0x68 + ((t_count % 9) << 8) + (t_count / 36))); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_org = dq_bit_delay[t_count]; + delay_temp = ((delay_org & 0x3f)); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } } { - printf_log(log_level,"\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse ps=%d",ui_1_32_100step,ps); - for (t_count=0;t_count<16;t_count++) - { - add_offset=((ps<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x80+(t_count/8)+((t_count%2)<<8))); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f)); + printf_log(log_level, "\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse ps=%d", ui_1_32_100step, ps); + for (t_count = 0; t_count < 16; t_count++) { + add_offset = ((ps << 20) | (1 << 16) | (((t_count % 8) >> 1) << 12) | (0x80 + (t_count / 8) + ((t_count % 2) << 8))); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_org = dq_bit_delay[t_count]; + delay_temp = (32 * (((delay_org >> 6) & 0x1f) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f)); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - printf_log(log_level,"\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345 ps=%d",ps); - //((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value) - uint32_t vref_t_count=0; - for (t_count=0;t_count<72;t_count++) - {//add normal vref0---vrefDac0 for just 1->x transitions - add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x40)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=((delay_org)); - if (t_count<35) - { - vref_t_count=((((t_count%36)/9)*8)+(t_count%9)); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[vref_t_count]=delay_temp; + printf_log(log_level, "\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345 ps=%d", ps); + uint32_t vref_t_count = 0; + for (t_count = 0; t_count < 72; t_count++) { //add normal vref0---vrefDac0 for just 1->x transitions + add_offset = ((0 << 20) | (1 << 16) | (((t_count % 36) / 9) << 12) | (((t_count % 36) % 9) << 8) | (0x40)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_org = dq_bit_delay[t_count]; + delay_temp = ((delay_org)); + if (t_count < 35) { + vref_t_count = ((((t_count % 36) / 9) * 8) + (t_count % 9)); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[vref_t_count] = delay_temp; } - if ((t_count%9) == 8) - { - vref_t_count=32+((((t_count%36)/9))); - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[vref_t_count]=delay_temp; + if ((t_count % 9) == 8) { + vref_t_count = 32 + ((((t_count % 36) / 9))); + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[vref_t_count] = delay_temp; } - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - printf_log(log_level,"\n soc vref-dfe dac1 0--->x : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345 ps=%d",ps); - for (t_count=0;t_count<72;t_count++) - { //add dfe vref1---vrefDac1 for just 0->x transitions - add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x30)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_org=dq_bit_delay[t_count]; - delay_temp=((delay_org)); - if (t_count<35) - { - vref_t_count=((((t_count%36)/9)*8)+(t_count%9)); - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count]=delay_temp; + printf_log(log_level, "\n soc vref-dfe dac1 0--->x : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345 ps=%d", ps); + for (t_count = 0; t_count < 72; t_count++) { //add dfe vref1---vrefDac1 for just 0->x transitions + add_offset = ((0 << 20) | (1 << 16) | (((t_count % 36) / 9) << 12) | (((t_count % 36) % 9) << 8) | (0x30)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_org = dq_bit_delay[t_count]; + delay_temp = ((delay_org)); + if (t_count < 35) { + vref_t_count = ((((t_count % 36) / 9) * 8) + (t_count % 9)); + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count] = delay_temp; } - if ((t_count%9) == 8) - { - vref_t_count=32+((((t_count%36)/9))); - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count]=delay_temp; + if ((t_count % 9) == 8) { + vref_t_count = 32 + ((((t_count % 36) / 9))); + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count] = delay_temp; } - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - printf_log(log_level,"\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0. DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0. ps=%d",ps); - add_offset=((0<<20)|(1<<16)|(0<<12)|(0x082)); - delay_temp=dwc_ddrphy_apb_rd(add_offset); - for (t_count=0;t_count<32;t_count++) - { - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[t_count]=delay_temp; + printf_log(log_level, "\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0. DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0. ps=%d", ps); + add_offset = ((0 << 20) | (1 << 16) | (0 << 12) | (0x082)); + delay_temp = dwc_ddrphy_apb_rd(add_offset); + for (t_count = 0; t_count < 32; t_count++) + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[t_count] = delay_temp; - // printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",0,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),delay_temp); + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 0, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_temp); } - #if 0 - // if(over_ride_index ==DMC_TEST_WINDOW_INDEX_RETRAINING) - { // if (read_write==REGISTER_READ) - for (t_count=0;t_count<4;t_count++) - { ddr_set_t_p->retraining[4*t_count+0]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))&0xff; //PptCtlStatic - ddr_set_t_p->retraining[4*t_count+1]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))>>8; //PptCtlStatic - ddr_set_t_p->retraining[4*t_count+2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0 lane 0-3 - ddr_set_t_p->retraining[4*t_count+3]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1 lane 0-3 - } - } - #endif - #if 1 //add for skip training - printf_log(log_level,"\n extra retraining setting. ps=%d",ps); - t_count=0; - add_offset=(0<<20)|(2<<16)|(0<<12)|(0xcb); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + //add for skip training + printf_log(log_level, "\n extra retraining setting. ps=%d", ps); + t_count = 0; + add_offset = (0 << 20) | (2 << 16) | (0 << 12) | (0xcb); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3 = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); - for (t_count=0;t_count<4;t_count++) - { - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0xaa)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + for (t_count = 0; t_count < 4; t_count++) { + add_offset = ((0 << 20) | (1 << 16) | (t_count << 12) | (0xaa)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - for (t_count=0;t_count<4;t_count++) - { - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0x62)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + for (t_count = 0; t_count < 4; t_count++) { + add_offset = ((0 << 20) | (1 << 16) | (t_count << 12) | (0x62)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - for (t_count=0;t_count<4;t_count++) - { - add_offset=((0<<20)|(1<<16)|(t_count<<12)|(0x01)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + for (t_count = 0; t_count < 4; t_count++) { + add_offset = ((0 << 20) | (1 << 16) | (t_count << 12) | (0x01)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - for (t_count=0;t_count<4;t_count++) - { - add_offset=((ps<<20)|(1<<16)|(t_count<<12)|(0x43)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + for (t_count = 0; t_count < 4; t_count++) { + add_offset = ((ps << 20) | (1 << 16) | (t_count << 12) | (0x43)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - for (t_count=0;t_count<4;t_count++) - { - //t_count=0; - add_offset=((ps<<20)|(1<<16)|(t_count<<12)|(0xae)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + for (t_count = 0; t_count < 4; t_count++) { + add_offset = ((ps << 20) | (1 << 16) | (t_count << 12) | (0xae)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - for (t_count=0;t_count<4;t_count++) - { - //t_count=0; - add_offset=((ps<<20)|(1<<16)|(t_count<<12)|(0xaf)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - //for(t_count=0;t_count<4;t_count++) - { - t_count=0; - add_offset=((ps<<20)|(2<<16)|(t_count<<12)|(0xb2)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); - } - for (t_count=1;t_count<9;t_count++) - { - //t_count=0; - add_offset=((ps<<20)|(9<<16)|(0<<12)|(0x200)|t_count); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[t_count]=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + for (t_count = 0; t_count < 4; t_count++) { + add_offset = ((ps << 20) | (1 << 16) | (t_count << 12) | (0xaf)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } { - t_count=0; - add_offset=((ps<<20)|(2<<16)|(t_count<<12)|(0x7c)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + t_count = 0; + add_offset = ((ps << 20) | (2 << 16) | (t_count << 12) | (0xb2)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); + } + for (t_count = 1; t_count < 9; t_count++) { + add_offset = ((ps << 20) | (9 << 16) | (0 << 12) | (0x200) | t_count); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[t_count] = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } { - t_count=0; - add_offset=((ps<<20)|(2<<16)|(t_count<<12)|(0x7d)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + t_count = 0; + add_offset = ((ps << 20) | (2 << 16) | (t_count << 12) | (0x7c)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x77)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + t_count = 0; + add_offset = ((ps << 20) | (2 << 16) | (t_count << 12) | (0x7d)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x72)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + t_count = 0; + add_offset = ((0 << 20) | (2 << 16) | (t_count << 12) | (0x77)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } { - t_count=0; - add_offset=((0<<20)|(2<<16)|(t_count<<12)|(0x73)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + t_count = 0; + add_offset = ((0 << 20) | (2 << 16) | (t_count << 12) | (0x72)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } { - t_count=0; - add_offset=((0<<20)|(4<<16)|(t_count<<12)|(0xfd)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + t_count = 0; + add_offset = ((0 << 20) | (2 << 16) | (t_count << 12) | (0x73)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } { - t_count=0; - add_offset=((0<<20)|(4<<16)|(t_count<<12)|(0xc0)); - dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset); - delay_temp=dq_bit_delay[t_count]; - ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23=delay_temp; - printf_log(log_level,"\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+(p_ddr_base->ddr_phy_base_address))),dq_bit_delay[t_count]); + t_count = 0; + add_offset = ((0 << 20) | (4 << 16) | (t_count << 12) | (0xfd)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13 = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); } - //dwc_ddrphy_apb_wr((ps<<20)|(9<<16)|(0<<12)|(0x28), 0); // csr_PhyInLP3_ADDR - #endif + { + t_count = 0; + add_offset = ((0 << 20) | (4 << 16) | (t_count << 12) | (0xc0)); + dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset); + delay_temp = dq_bit_delay[t_count]; + ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23 = delay_temp; + printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]); + } } } return 1; } -int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - // if(!argc) - // goto DDR_TUNE_DQS_START; - int i=0; - unsigned int ps=0; +int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int i = 0; + unsigned int ps = 0; + printf("\nargc== 0x%08x\n", argc); - for (i = 0;i<argc;i++) - printf("\nargv[%d]=%s\n",i,argv[i]); - ddr_set_t *ddr_set_t_p=NULL; - ddr_set_t_p=(ddr_set_t *)(ddr_set_t_p_arrary); - do_read_ddr_training_data(0,ddr_set_t_p); + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); + ddr_set_t *ddr_set_t_p = NULL; + ddr_set_t_p = (ddr_set_t *)(ddr_set_t_p_arrary); + do_read_ddr_training_data(0, ddr_set_t_p); { - uint32_t count=0; - uint32_t reg_add_offset=0; - uint16_t reg_value=0; - //ddr_log_serial_puts("\npctl timming:\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); - + uint32_t count = 0; + uint32_t reg_add_offset = 0; + uint16_t reg_value = 0; printf("\n PCTL timming: 0x"); - for (count=0;count<((p_ddr_base->ddr_pctl_timing_end_address)-(p_ddr_base->ddr_pctl_timing_base_address));) { - reg_add_offset=((p_ddr_base->ddr_pctl_timing_base_address)+(count)); - //ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); - //ddr_log_serial_put_hex(reg_add_offset,32,p_dev->ddr_gloabl_message.stick_ddr_log_level); - //ddr_log_serial_puts(": ",p_dev->ddr_gloabl_message.stick_ddr_log_level); - //ddr_log_serial_put_hex(readl(reg_add_offset),32,p_dev->ddr_gloabl_message.stick_ddr_log_level); - printf("\n reg_add_offset: %08x %08x %08x ",reg_add_offset,readl(reg_add_offset),reg_add_offset); - count=count+4; + for (count = 0; count < ((p_ddr_base->ddr_pctl_timing_end_address) - (p_ddr_base->ddr_pctl_timing_base_address)); ) { + reg_add_offset = ((p_ddr_base->ddr_pctl_timing_base_address) + (count)); + printf("\n reg_add_offset: %08x %08x %08x ", reg_add_offset, readl(reg_add_offset), reg_add_offset); + count = count + 4; } - //ddr_log_serial_puts("\nmrs register: base (0x54000<<1)+DDR_PHY_BASE,byte offset\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); printf("\n mrs register: "); - printf("\n mrs register: base (0x54000<<1)+DDR_PHY_BASE,%08x byte offset\n",(0x54000<<1)+(p_ddr_base->ddr_phy_base_address)); - for (count=0;count<0x80;) { - reg_add_offset=0x54000+count;//dwc_ddrphy_apb_wr(0x54008,0x1001); - //ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); - //ddr_log_serial_put_hex(count,32,p_dev->ddr_gloabl_message.stick_ddr_log_level); - //ddr_log_serial_puts(": ",p_dev->ddr_gloabl_message.stick_ddr_log_level); - reg_value= ((*(volatile uint16_t *)((uint64_t)(((0x54000+(count>>1))) << 1)+(p_ddr_base->ddr_phy_base_address)))>>(((count)%2)?8:0));//dwc_ddrphy_apb_rd(0x54000+add_offset+1); - reg_value=reg_value&0xff; - //ddr_log_serial_put_hex(reg_value,32,p_dev->ddr_gloabl_message.stick_ddr_log_level); - printf("\n reg_add_offset: %08x %08x %08x",reg_add_offset,reg_value,((((0x54000+(count>>1))) << 1)+(p_ddr_base->ddr_phy_base_address))); - count=count+1; + printf("\n mrs register: base (0x54000<<1)+DDR_PHY_BASE,%08x byte offset\n", (0x54000 << 1) + (p_ddr_base->ddr_phy_base_address)); + for (count = 0; count < 0x80; ) { + reg_add_offset = 0x54000 + count; //dwc_ddrphy_apb_wr(0x54008,0x1001); + reg_value = ((*(volatile uint16_t *)((uint64_t)(((0x54000 + (count >> 1))) << 1) + (p_ddr_base->ddr_phy_base_address))) >> (((count) % 2) ? 8 : 0)); //dwc_ddrphy_apb_rd(0x54000+add_offset+1); + reg_value = reg_value & 0xff; + printf("\n reg_add_offset: %08x %08x %08x", reg_add_offset, reg_value, ((((0x54000 + (count >> 1))) << 1) + (p_ddr_base->ddr_phy_base_address))); + count = count + 1; } - //ddr_log_serial_puts("\ntimming.c:\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); - printf("\n sticky register: "); { uint32_t loop_max = 0; - loop_max=64<<2;//sizeof(ddr_set_t); - //uint32_t loop = 0; - for (count = 0; count < loop_max; count+=4) { - // ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); - // ddr_log_serial_put_hex(count,32,p_dev->ddr_gloabl_message.stick_ddr_log_level); - // ddr_log_serial_puts(": ",p_dev->ddr_gloabl_message.stick_ddr_log_level); - // ddr_log_serial_put_hex(rd_reg((uint64_t)(p_dev->p_ddrs) + count),32,p_dev->ddr_gloabl_message.stick_ddr_log_level); - // count=count+4; - printf("\n reg_add_offset: %08x %08x %08x",count,rd_reg((uint64_t)((p_ddr_base->ddr_dmc_sticky0)) + count),(((p_ddr_base->ddr_dmc_sticky0)) + count)); - } + loop_max = 64 << 2; //sizeof(ddr_set_t); + for (count = 0; count < loop_max; count += 4) + printf("\n reg_add_offset: %08x %08x %08x", count, rd_reg((uint64_t)((p_ddr_base->ddr_dmc_sticky0)) + count), (((p_ddr_base->ddr_dmc_sticky0)) + count)); } { uint32_t loop_max = 0; - loop_max=sizeof(ddr_set_t); + loop_max = sizeof(ddr_set_t); uint32_t count = 0; for (count = 0; count < loop_max; ) { - // ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); - // ddr_log_serial_put_hex(count,32,p_dev->ddr_gloabl_message.stick_ddr_log_level); - // ddr_log_serial_puts(": ",p_dev->ddr_gloabl_message.stick_ddr_log_level); - // ddr_log_serial_put_hex(rd_reg((uint64_t)(p_dev->p_ddrs) + count),32,p_dev->ddr_gloabl_message.stick_ddr_log_level); - printf("\n%08x %08x",count,rd_reg((uint64_t)(ddr_set_t_p) + count)); - count=count+4; - //printf("\n reg_add_offset: %08x %08x %08x",count,rd_reg((uint64_t)((p_ddr_base->ddr_dmc_sticky0)) + count),(((p_ddr_base->ddr_dmc_sticky0)) + count)); + printf("\n%08x %08x", count, rd_reg((uint64_t)(ddr_set_t_p) + count)); + count = count + 4; } } - // ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level); } printf("\n {"); - - uint32_t temp_count=0; + uint32_t temp_count = 0; { - printf("\n.magic=0x%08x,// %d",ddr_set_t_p->magic,ddr_set_t_p->magic); - printf("\n//old fast_boot[%d]=0x%08x,// %d",0,ddr_set_t_p->fast_boot[0],ddr_set_t_p->fast_boot[0]); - ddr_set_t_p->fast_boot[0]=0xfd; //add for auto copy to code test - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.fast_boot[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->fast_boot[temp_count],ddr_set_t_p->fast_boot[temp_count]); - //printf("\n.rsv_int0=0x%08x,// %d",ddr_set_t_p->rsv_int0,ddr_set_t_p->rsv_int0); - printf("\n.board_id=0x%08x,// %d",ddr_set_t_p->board_id,ddr_set_t_p->board_id); - printf("\n.version=0x%08x,// %d",ddr_set_t_p->version,ddr_set_t_p->version); - printf("\n.DramType=0x%08x,// %d",ddr_set_t_p->DramType,ddr_set_t_p->DramType); - printf("\n.DisabledDbyte=0x%08x,// %d",ddr_set_t_p->DisabledDbyte,ddr_set_t_p->DisabledDbyte); - printf("\n.Is2Ttiming=0x%08x,// %d",ddr_set_t_p->Is2Ttiming,ddr_set_t_p->Is2Ttiming); - printf("\n.HdtCtrl=0x%08x,// %d",ddr_set_t_p->HdtCtrl,ddr_set_t_p->HdtCtrl); - printf("\n.dram_rank_config=0x%08x,// %d",ddr_set_t_p->dram_rank_config,ddr_set_t_p->dram_rank_config); - printf("\n.diagnose=0x%08x,// %d",ddr_set_t_p->diagnose,ddr_set_t_p->diagnose); - //printf("\n.imem_load_addr=0x%08x,// %d",ddr_set_t_p->imem_load_addr,ddr_set_t_p->imem_load_addr); - //printf("\n.dmem_load_addr=0x%08x,// %d",ddr_set_t_p->dmem_load_addr,ddr_set_t_p->dmem_load_addr); - //printf("\n.imem_load_size=0x%08x,// %d",ddr_set_t_p->imem_load_size,ddr_set_t_p->imem_load_size); - printf("\n.soc_data_drv_ohm_ps1=0x%08x,// %d",ddr_set_t_p->soc_data_drv_ohm_ps1,ddr_set_t_p->soc_data_drv_ohm_ps1); - printf("\n.dram_data_drv_ohm_ps1=0x%08x,// %d",ddr_set_t_p->dram_data_drv_ohm_ps1,ddr_set_t_p->dram_data_drv_ohm_ps1); - printf("\n.soc_data_odt_ohm_ps1=0x%08x,// %d",ddr_set_t_p->soc_data_odt_ohm_ps1,ddr_set_t_p->soc_data_odt_ohm_ps1); - printf("\n.dram_data_odt_ohm_ps1=0x%08x,// %d",ddr_set_t_p->dram_data_odt_ohm_ps1,ddr_set_t_p->dram_data_odt_ohm_ps1); - printf("\n.dram_data_wr_odt_ohm_ps1=0x%08x,// %d",ddr_set_t_p->dram_data_wr_odt_ohm_ps1,ddr_set_t_p->dram_data_wr_odt_ohm_ps1); + printf("\n.magic=0x%08x,// %d", ddr_set_t_p->magic, ddr_set_t_p->magic); + printf("\n//old fast_boot[%d]=0x%08x,// %d", 0, ddr_set_t_p->fast_boot[0], ddr_set_t_p->fast_boot[0]); + ddr_set_t_p->fast_boot[0] = 0xfd; //add for auto copy to code test + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.fast_boot[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->fast_boot[temp_count], ddr_set_t_p->fast_boot[temp_count]); + printf("\n.board_id=0x%08x,// %d", ddr_set_t_p->board_id, ddr_set_t_p->board_id); + printf("\n.version=0x%08x,// %d", ddr_set_t_p->version, ddr_set_t_p->version); + printf("\n.DramType=0x%08x,// %d", ddr_set_t_p->DramType, ddr_set_t_p->DramType); + printf("\n.DisabledDbyte=0x%08x,// %d", ddr_set_t_p->DisabledDbyte, ddr_set_t_p->DisabledDbyte); + printf("\n.Is2Ttiming=0x%08x,// %d", ddr_set_t_p->Is2Ttiming, ddr_set_t_p->Is2Ttiming); + printf("\n.HdtCtrl=0x%08x,// %d", ddr_set_t_p->HdtCtrl, ddr_set_t_p->HdtCtrl); + printf("\n.dram_rank_config=0x%08x,// %d", ddr_set_t_p->dram_rank_config, ddr_set_t_p->dram_rank_config); + printf("\n.diagnose=0x%08x,// %d", ddr_set_t_p->diagnose, ddr_set_t_p->diagnose); + printf("\n.soc_data_drv_ohm_ps1=0x%08x,// %d", ddr_set_t_p->soc_data_drv_ohm_ps1, ddr_set_t_p->soc_data_drv_ohm_ps1); + printf("\n.dram_data_drv_ohm_ps1=0x%08x,// %d", ddr_set_t_p->dram_data_drv_ohm_ps1, ddr_set_t_p->dram_data_drv_ohm_ps1); + printf("\n.soc_data_odt_ohm_ps1=0x%08x,// %d", ddr_set_t_p->soc_data_odt_ohm_ps1, ddr_set_t_p->soc_data_odt_ohm_ps1); + printf("\n.dram_data_odt_ohm_ps1=0x%08x,// %d", ddr_set_t_p->dram_data_odt_ohm_ps1, ddr_set_t_p->dram_data_odt_ohm_ps1); + printf("\n.dram_data_wr_odt_ohm_ps1=0x%08x,// %d", ddr_set_t_p->dram_data_wr_odt_ohm_ps1, ddr_set_t_p->dram_data_wr_odt_ohm_ps1); - printf("\n.dmem_load_size=0x%08x,// %d",ddr_set_t_p->dmem_load_size,ddr_set_t_p->dmem_load_size); - printf("\n.ddr_base_addr=0x%08x,// %d",ddr_set_t_p->ddr_base_addr,ddr_set_t_p->ddr_base_addr); - printf("\n.ddr_start_offset=0x%08x,// %d",ddr_set_t_p->ddr_start_offset,ddr_set_t_p->ddr_start_offset); - printf("\n.dram_cs0_size_MB=0x%08x,// %d",ddr_set_t_p->dram_cs0_size_MB,ddr_set_t_p->dram_cs0_size_MB); - printf("\n.dram_cs1_size_MB=0x%08x,// %d",ddr_set_t_p->dram_cs1_size_MB,ddr_set_t_p->dram_cs1_size_MB); - printf("\n.training_SequenceCtrl[0]=0x%08x,// %d",ddr_set_t_p->training_SequenceCtrl[0],ddr_set_t_p->training_SequenceCtrl[0]); - printf("\n.training_SequenceCtrl[1]=0x%08x,// %d",ddr_set_t_p->training_SequenceCtrl[1],ddr_set_t_p->training_SequenceCtrl[1]); - printf("\n.phy_odt_config_rank[0]=0x%08x,// %d",ddr_set_t_p->phy_odt_config_rank[0],ddr_set_t_p->phy_odt_config_rank[0]); - printf("\n.phy_odt_config_rank[1]=0x%08x,// %d",ddr_set_t_p->phy_odt_config_rank[1],ddr_set_t_p->phy_odt_config_rank[1]); - //printf("\n.rever1=0x%08x,// %d",ddr_set_t_p->rever1,ddr_set_t_p->rever1); - //printf("\n.rever2=0x%08x,// %d",ddr_set_t_p->rever2,ddr_set_t_p->rever2); - printf("\n.rank1_ca_vref_permil=0x%08x,// %d",ddr_set_t_p->rank1_ca_vref_permil,ddr_set_t_p->rank1_ca_vref_permil); + printf("\n.dmem_load_size=0x%08x,// %d", ddr_set_t_p->dmem_load_size, ddr_set_t_p->dmem_load_size); + printf("\n.ddr_base_addr=0x%08x,// %d", ddr_set_t_p->ddr_base_addr, ddr_set_t_p->ddr_base_addr); + printf("\n.ddr_start_offset=0x%08x,// %d", ddr_set_t_p->ddr_start_offset, ddr_set_t_p->ddr_start_offset); + printf("\n.dram_cs0_size_MB=0x%08x,// %d", ddr_set_t_p->dram_cs0_size_MB, ddr_set_t_p->dram_cs0_size_MB); + printf("\n.dram_cs1_size_MB=0x%08x,// %d", ddr_set_t_p->dram_cs1_size_MB, ddr_set_t_p->dram_cs1_size_MB); + printf("\n.training_SequenceCtrl[0]=0x%08x,// %d", ddr_set_t_p->training_SequenceCtrl[0], ddr_set_t_p->training_SequenceCtrl[0]); + printf("\n.training_SequenceCtrl[1]=0x%08x,// %d", ddr_set_t_p->training_SequenceCtrl[1], ddr_set_t_p->training_SequenceCtrl[1]); + printf("\n.phy_odt_config_rank[0]=0x%08x,// %d", ddr_set_t_p->phy_odt_config_rank[0], ddr_set_t_p->phy_odt_config_rank[0]); + printf("\n.phy_odt_config_rank[1]=0x%08x,// %d", ddr_set_t_p->phy_odt_config_rank[1], ddr_set_t_p->phy_odt_config_rank[1]); + printf("\n.rank1_ca_vref_permil=0x%08x,// %d", ddr_set_t_p->rank1_ca_vref_permil, ddr_set_t_p->rank1_ca_vref_permil); - // unsigned char phy_odt_config_rank[2]; - // unsigned char ddr_fast_boot_function; - // unsigned char dqs_offset_value; - printf("\n.dfi_odt_config=0x%08x,// %d",ddr_set_t_p->dfi_odt_config,ddr_set_t_p->dfi_odt_config); - printf("\n.DRAMFreq[0]=0x%08x,// %d",ddr_set_t_p->DRAMFreq[0],ddr_set_t_p->DRAMFreq[0]); - printf("\n.DRAMFreq[1]=0x%08x,// %d",ddr_set_t_p->DRAMFreq[1],ddr_set_t_p->DRAMFreq[1]); - printf("\n.DRAMFreq[2]=0x%08x,// %d",ddr_set_t_p->DRAMFreq[2],ddr_set_t_p->DRAMFreq[2]); - printf("\n.DRAMFreq[3]=0x%08x,// %d",ddr_set_t_p->DRAMFreq[3],ddr_set_t_p->DRAMFreq[3]); - printf("\n.PllBypassEn=0x%08x,// %d",ddr_set_t_p->PllBypassEn,ddr_set_t_p->PllBypassEn); - printf("\n.ddr_rdbi_wr_enable=0x%08x,// %d",ddr_set_t_p->ddr_rdbi_wr_enable,ddr_set_t_p->ddr_rdbi_wr_enable); - printf("\n.ddr_rfc_type=0x%08x,// %d",ddr_set_t_p->ddr_rfc_type,ddr_set_t_p->ddr_rfc_type); - printf("\n.enable_lpddr4x_mode=0x%08x,// %d",ddr_set_t_p->enable_lpddr4x_mode,ddr_set_t_p->enable_lpddr4x_mode); - printf("\n.pll_ssc_mode=0x%08x,// %d",ddr_set_t_p->pll_ssc_mode,ddr_set_t_p->pll_ssc_mode); - printf("\n.clk_drv_ohm=0x%08x,// %d",ddr_set_t_p->clk_drv_ohm,ddr_set_t_p->clk_drv_ohm); - printf("\n.cs_drv_ohm=0x%08x,// %d",ddr_set_t_p->cs_drv_ohm,ddr_set_t_p->cs_drv_ohm); - printf("\n.ac_drv_ohm=0x%08x,// %d",ddr_set_t_p->ac_drv_ohm,ddr_set_t_p->ac_drv_ohm); - printf("\n.soc_data_drv_ohm_p=0x%08x,// %d",ddr_set_t_p->soc_data_drv_ohm_p,ddr_set_t_p->soc_data_drv_ohm_p); - printf("\n.soc_data_drv_ohm_n=0x%08x,// %d",ddr_set_t_p->soc_data_drv_ohm_n,ddr_set_t_p->soc_data_drv_ohm_n); - printf("\n.soc_data_odt_ohm_p=0x%08x,// %d",ddr_set_t_p->soc_data_odt_ohm_p,ddr_set_t_p->soc_data_odt_ohm_p); - printf("\n.soc_data_odt_ohm_n=0x%08x,// %d",ddr_set_t_p->soc_data_odt_ohm_n,ddr_set_t_p->soc_data_odt_ohm_n); - printf("\n.dram_data_drv_ohm=0x%08x,// %d",ddr_set_t_p->dram_data_drv_ohm,ddr_set_t_p->dram_data_drv_ohm); - printf("\n.dram_data_odt_ohm=0x%08x,// %d",ddr_set_t_p->dram_data_odt_ohm,ddr_set_t_p->dram_data_odt_ohm); - printf("\n.dram_ac_odt_ohm=0x%08x,// %d",ddr_set_t_p->dram_ac_odt_ohm,ddr_set_t_p->dram_ac_odt_ohm); - printf("\n.soc_clk_slew_rate=0x%08x,// %d",ddr_set_t_p->soc_clk_slew_rate,ddr_set_t_p->soc_clk_slew_rate); - printf("\n.soc_cs_slew_rate=0x%08x,// %d",ddr_set_t_p->soc_cs_slew_rate,ddr_set_t_p->soc_cs_slew_rate); - printf("\n.soc_ac_slew_rate=0x%08x,// %d",ddr_set_t_p->soc_ac_slew_rate,ddr_set_t_p->soc_ac_slew_rate); - printf("\n.soc_data_slew_rate=0x%08x,// %d",ddr_set_t_p->soc_data_slew_rate,ddr_set_t_p->soc_data_slew_rate); - printf("\n.vref_output_permil =0x%08x,// %d",ddr_set_t_p->vref_output_permil ,ddr_set_t_p->vref_output_permil ); - printf("\n.vref_receiver_permil =0x%08x,// %d",ddr_set_t_p->vref_receiver_permil ,ddr_set_t_p->vref_receiver_permil ); - printf("\n.vref_dram_permil=0x%08x,// %d",ddr_set_t_p->vref_dram_permil,ddr_set_t_p->vref_dram_permil); - printf("\n.max_core_timmming_frequency=0x%08x,// %d",ddr_set_t_p->max_core_timmming_frequency,ddr_set_t_p->max_core_timmming_frequency); - printf("\n.ac_trace_delay[0]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[0],ddr_set_t_p->ac_trace_delay[0]); - printf("\n.ac_trace_delay[1]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[1],ddr_set_t_p->ac_trace_delay[1]); - printf("\n.ac_trace_delay[2]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[2],ddr_set_t_p->ac_trace_delay[2]); - printf("\n.ac_trace_delay[3]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[3],ddr_set_t_p->ac_trace_delay[3]); - printf("\n.ac_trace_delay[4]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[4],ddr_set_t_p->ac_trace_delay[4]); - printf("\n.ac_trace_delay[5]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[5],ddr_set_t_p->ac_trace_delay[5]); - printf("\n.ac_trace_delay[6]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[6],ddr_set_t_p->ac_trace_delay[6]); - printf("\n.ac_trace_delay[7]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[7],ddr_set_t_p->ac_trace_delay[7]); - printf("\n.ac_trace_delay[8]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[8],ddr_set_t_p->ac_trace_delay[8]); - printf("\n.ac_trace_delay[9]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[9],ddr_set_t_p->ac_trace_delay[9]); - printf("\n.lpddr4_dram_vout_voltage_1_3_2_5_setting=0x%08x,// %d",ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting,ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting); - printf("\n.lpddr4_x8_mode=0x%08x,// %d",ddr_set_t_p->lpddr4_x8_mode,ddr_set_t_p->lpddr4_x8_mode); - printf("\n.ac_pinmux[0]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[0],ddr_set_t_p->ac_pinmux[0]); - printf("\n.ac_pinmux[1]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[1],ddr_set_t_p->ac_pinmux[1]); - printf("\n.ac_pinmux[2]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[2],ddr_set_t_p->ac_pinmux[2]); - printf("\n.ac_pinmux[3]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[3],ddr_set_t_p->ac_pinmux[3]); - printf("\n.ac_pinmux[4]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[4],ddr_set_t_p->ac_pinmux[4]); - printf("\n.ac_pinmux[5]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[5],ddr_set_t_p->ac_pinmux[5]); - printf("\n.ac_pinmux[6]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[6],ddr_set_t_p->ac_pinmux[6]); - printf("\n.ac_pinmux[7]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[7],ddr_set_t_p->ac_pinmux[7]); - printf("\n.ac_pinmux[8]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[8],ddr_set_t_p->ac_pinmux[8]); - printf("\n.ac_pinmux[9]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[9],ddr_set_t_p->ac_pinmux[9]); - printf("\n.ac_pinmux[10]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[10],ddr_set_t_p->ac_pinmux[10]); - printf("\n.ac_pinmux[11]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[11],ddr_set_t_p->ac_pinmux[11]); - printf("\n.ac_pinmux[12]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[12],ddr_set_t_p->ac_pinmux[12]); - printf("\n.ac_pinmux[13]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[13],ddr_set_t_p->ac_pinmux[13]); - printf("\n.ac_pinmux[14]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[14],ddr_set_t_p->ac_pinmux[14]); - printf("\n.ac_pinmux[15]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[15],ddr_set_t_p->ac_pinmux[15]); - printf("\n.ac_pinmux[16]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[16],ddr_set_t_p->ac_pinmux[16]); - printf("\n.ac_pinmux[17]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[17],ddr_set_t_p->ac_pinmux[17]); - printf("\n.ac_pinmux[18]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[18],ddr_set_t_p->ac_pinmux[18]); - printf("\n.ac_pinmux[19]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[19],ddr_set_t_p->ac_pinmux[19]); - printf("\n.ac_pinmux[20]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[20],ddr_set_t_p->ac_pinmux[20]); - printf("\n.ac_pinmux[21]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[21],ddr_set_t_p->ac_pinmux[21]); - printf("\n.ac_pinmux[22]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[22],ddr_set_t_p->ac_pinmux[22]); - printf("\n.ac_pinmux[23]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[23],ddr_set_t_p->ac_pinmux[23]); - printf("\n.ac_pinmux[24]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[24],ddr_set_t_p->ac_pinmux[24]); - printf("\n.ac_pinmux[25]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[25],ddr_set_t_p->ac_pinmux[25]); - printf("\n.ac_pinmux[26]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[26],ddr_set_t_p->ac_pinmux[26]); - printf("\n.ac_pinmux[27]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[27],ddr_set_t_p->ac_pinmux[27]); - printf("\n.dfi_pinmux[0]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[0],ddr_set_t_p->dfi_pinmux[0]); - printf("\n.dfi_pinmux[1]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[1],ddr_set_t_p->dfi_pinmux[1]); - printf("\n.dfi_pinmux[2]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[2],ddr_set_t_p->dfi_pinmux[2]); - printf("\n.dfi_pinmux[3]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[3],ddr_set_t_p->dfi_pinmux[3]); - printf("\n.dfi_pinmux[4]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[4],ddr_set_t_p->dfi_pinmux[4]); - printf("\n.dfi_pinmux[5]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[5],ddr_set_t_p->dfi_pinmux[5]); - printf("\n.dfi_pinmux[6]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[6],ddr_set_t_p->dfi_pinmux[6]); - printf("\n.dfi_pinmux[7]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[7],ddr_set_t_p->dfi_pinmux[7]); - printf("\n.dfi_pinmux[8]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[8],ddr_set_t_p->dfi_pinmux[8]); - printf("\n.dfi_pinmux[9]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[9],ddr_set_t_p->dfi_pinmux[9]); - printf("\n.dfi_pinmux[10]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[10],ddr_set_t_p->dfi_pinmux[10]); - printf("\n.dfi_pinmux[11]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[11],ddr_set_t_p->dfi_pinmux[11]); - printf("\n.dfi_pinmux[12]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[12],ddr_set_t_p->dfi_pinmux[12]); - printf("\n.dfi_pinmux[13]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[13],ddr_set_t_p->dfi_pinmux[13]); - printf("\n.dfi_pinmux[14]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[14],ddr_set_t_p->dfi_pinmux[14]); - printf("\n.dfi_pinmux[15]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[15],ddr_set_t_p->dfi_pinmux[15]); - printf("\n.dfi_pinmux[16]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[16],ddr_set_t_p->dfi_pinmux[16]); - printf("\n.dfi_pinmux[17]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[17],ddr_set_t_p->dfi_pinmux[17]); - printf("\n.dfi_pinmux[18]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[18],ddr_set_t_p->dfi_pinmux[18]); - printf("\n.dfi_pinmux[19]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[19],ddr_set_t_p->dfi_pinmux[19]); - printf("\n.dfi_pinmux[20]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[20],ddr_set_t_p->dfi_pinmux[20]); - printf("\n.dfi_pinmux[21]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[21],ddr_set_t_p->dfi_pinmux[21]); - printf("\n.dfi_pinmux[22]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[22],ddr_set_t_p->dfi_pinmux[22]); - printf("\n.dfi_pinmux[23]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[23],ddr_set_t_p->dfi_pinmux[23]); - printf("\n.dfi_pinmux[24]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[24],ddr_set_t_p->dfi_pinmux[24]); - printf("\n.dfi_pinmux[25]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[25],ddr_set_t_p->dfi_pinmux[25]); - printf("\n.slt_test_function[0] =0x%08x,// %d",ddr_set_t_p->slt_test_function[0] ,ddr_set_t_p->slt_test_function[0] ); - printf("\n.slt_test_function[1] =0x%08x,// %d",ddr_set_t_p->slt_test_function[1] ,ddr_set_t_p->slt_test_function[1] ); - printf("\n.tdqs2dq=0x%08x,// %d",ddr_set_t_p->tdqs2dq,ddr_set_t_p->tdqs2dq); - printf("\n.dram_data_wr_odt_ohm=0x%08x,// %d",ddr_set_t_p->dram_data_wr_odt_ohm,ddr_set_t_p->dram_data_wr_odt_ohm); - printf("\n.bitTimeControl_2d=0x%08x,// %d",ddr_set_t_p->bitTimeControl_2d,ddr_set_t_p->bitTimeControl_2d); - printf("\n.ddr_dmc_remap[0]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[0],ddr_set_t_p->ddr_dmc_remap[0]); - printf("\n.ddr_dmc_remap[1]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[1],ddr_set_t_p->ddr_dmc_remap[1]); - printf("\n.ddr_dmc_remap[2]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[2],ddr_set_t_p->ddr_dmc_remap[2]); - printf("\n.ddr_dmc_remap[3]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[3],ddr_set_t_p->ddr_dmc_remap[3]); - printf("\n.ddr_dmc_remap[4]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[4],ddr_set_t_p->ddr_dmc_remap[4]); - printf("\n.ddr_lpddr34_ca_remap[0]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_ca_remap[0],ddr_set_t_p->ddr_lpddr34_ca_remap[0]); - printf("\n.ddr_lpddr34_ca_remap[1]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_ca_remap[1],ddr_set_t_p->ddr_lpddr34_ca_remap[1]); - printf("\n.ddr_lpddr34_ca_remap[2]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_ca_remap[2],ddr_set_t_p->ddr_lpddr34_ca_remap[2]); - printf("\n.ddr_lpddr34_ca_remap[3]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_ca_remap[3],ddr_set_t_p->ddr_lpddr34_ca_remap[3]); - printf("\n.ddr_lpddr34_dq_remap[0]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[0],ddr_set_t_p->ddr_lpddr34_dq_remap[0]); - printf("\n.ddr_lpddr34_dq_remap[1]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[1],ddr_set_t_p->ddr_lpddr34_dq_remap[1]); - printf("\n.ddr_lpddr34_dq_remap[2]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[2],ddr_set_t_p->ddr_lpddr34_dq_remap[2]); - printf("\n.ddr_lpddr34_dq_remap[3]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[3],ddr_set_t_p->ddr_lpddr34_dq_remap[3]); - printf("\n.ddr_lpddr34_dq_remap[4]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[4],ddr_set_t_p->ddr_lpddr34_dq_remap[4]); - printf("\n.ddr_lpddr34_dq_remap[5]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[5],ddr_set_t_p->ddr_lpddr34_dq_remap[5]); - printf("\n.ddr_lpddr34_dq_remap[6]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[6],ddr_set_t_p->ddr_lpddr34_dq_remap[6]); - printf("\n.ddr_lpddr34_dq_remap[7]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[7],ddr_set_t_p->ddr_lpddr34_dq_remap[7]); - printf("\n.ddr_lpddr34_dq_remap[8]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[8],ddr_set_t_p->ddr_lpddr34_dq_remap[8]); - printf("\n.ddr_lpddr34_dq_remap[9]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[9],ddr_set_t_p->ddr_lpddr34_dq_remap[9]); - printf("\n.ddr_lpddr34_dq_remap[10]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[10],ddr_set_t_p->ddr_lpddr34_dq_remap[10]); - printf("\n.ddr_lpddr34_dq_remap[11]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[11],ddr_set_t_p->ddr_lpddr34_dq_remap[11]); - printf("\n.ddr_lpddr34_dq_remap[12]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[12],ddr_set_t_p->ddr_lpddr34_dq_remap[12]); - printf("\n.ddr_lpddr34_dq_remap[13]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[13],ddr_set_t_p->ddr_lpddr34_dq_remap[13]); - printf("\n.ddr_lpddr34_dq_remap[14]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[14],ddr_set_t_p->ddr_lpddr34_dq_remap[14]); - printf("\n.ddr_lpddr34_dq_remap[15]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[15],ddr_set_t_p->ddr_lpddr34_dq_remap[15]); - printf("\n.ddr_lpddr34_dq_remap[16]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[16],ddr_set_t_p->ddr_lpddr34_dq_remap[16]); - printf("\n.ddr_lpddr34_dq_remap[17]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[17],ddr_set_t_p->ddr_lpddr34_dq_remap[17]); - printf("\n.ddr_lpddr34_dq_remap[18]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[18],ddr_set_t_p->ddr_lpddr34_dq_remap[18]); - printf("\n.ddr_lpddr34_dq_remap[19]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[19],ddr_set_t_p->ddr_lpddr34_dq_remap[19]); - printf("\n.ddr_lpddr34_dq_remap[20]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[20],ddr_set_t_p->ddr_lpddr34_dq_remap[20]); - printf("\n.ddr_lpddr34_dq_remap[21]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[21],ddr_set_t_p->ddr_lpddr34_dq_remap[21]); - printf("\n.ddr_lpddr34_dq_remap[22]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[22],ddr_set_t_p->ddr_lpddr34_dq_remap[22]); - printf("\n.ddr_lpddr34_dq_remap[23]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[23],ddr_set_t_p->ddr_lpddr34_dq_remap[23]); - printf("\n.ddr_lpddr34_dq_remap[24]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[24],ddr_set_t_p->ddr_lpddr34_dq_remap[24]); - printf("\n.ddr_lpddr34_dq_remap[25]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[25],ddr_set_t_p->ddr_lpddr34_dq_remap[25]); - printf("\n.ddr_lpddr34_dq_remap[26]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[26],ddr_set_t_p->ddr_lpddr34_dq_remap[26]); - printf("\n.ddr_lpddr34_dq_remap[27]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[27],ddr_set_t_p->ddr_lpddr34_dq_remap[27]); - printf("\n.ddr_lpddr34_dq_remap[28]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[28],ddr_set_t_p->ddr_lpddr34_dq_remap[28]); - printf("\n.ddr_lpddr34_dq_remap[29]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[29],ddr_set_t_p->ddr_lpddr34_dq_remap[29]); - printf("\n.ddr_lpddr34_dq_remap[30]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[30],ddr_set_t_p->ddr_lpddr34_dq_remap[30]); - printf("\n.ddr_lpddr34_dq_remap[31]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[31],ddr_set_t_p->ddr_lpddr34_dq_remap[31]); - printf("\n.dram_rtt_nom_wr_park[0]=0x%08x,// %d",ddr_set_t_p->dram_rtt_nom_wr_park[0],ddr_set_t_p->dram_rtt_nom_wr_park[0]); - printf("\n.dram_rtt_nom_wr_park[1]=0x%08x,// %d",ddr_set_t_p->dram_rtt_nom_wr_park[1],ddr_set_t_p->dram_rtt_nom_wr_park[1]); - printf("\n.ddr_func=0x%08x,// %d",ddr_set_t_p->ddr_func,ddr_set_t_p->ddr_func); - for ( ps=0;ps<2;ps++) - { - for ( temp_count=0;temp_count<10;temp_count++) - printf("\n.cfg_ddr_training_delay_ps[%d].ac_trace_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count]); + printf("\n.dfi_odt_config=0x%08x,// %d", ddr_set_t_p->dfi_odt_config, ddr_set_t_p->dfi_odt_config); + printf("\n.DRAMFreq[0]=0x%08x,// %d", ddr_set_t_p->DRAMFreq[0], ddr_set_t_p->DRAMFreq[0]); + printf("\n.DRAMFreq[1]=0x%08x,// %d", ddr_set_t_p->DRAMFreq[1], ddr_set_t_p->DRAMFreq[1]); + printf("\n.DRAMFreq[2]=0x%08x,// %d", ddr_set_t_p->DRAMFreq[2], ddr_set_t_p->DRAMFreq[2]); + printf("\n.DRAMFreq[3]=0x%08x,// %d", ddr_set_t_p->DRAMFreq[3], ddr_set_t_p->DRAMFreq[3]); + printf("\n.PllBypassEn=0x%08x,// %d", ddr_set_t_p->PllBypassEn, ddr_set_t_p->PllBypassEn); + printf("\n.ddr_rdbi_wr_enable=0x%08x,// %d", ddr_set_t_p->ddr_rdbi_wr_enable, ddr_set_t_p->ddr_rdbi_wr_enable); + printf("\n.ddr_rfc_type=0x%08x,// %d", ddr_set_t_p->ddr_rfc_type, ddr_set_t_p->ddr_rfc_type); + printf("\n.enable_lpddr4x_mode=0x%08x,// %d", ddr_set_t_p->enable_lpddr4x_mode, ddr_set_t_p->enable_lpddr4x_mode); + printf("\n.pll_ssc_mode=0x%08x,// %d", ddr_set_t_p->pll_ssc_mode, ddr_set_t_p->pll_ssc_mode); + printf("\n.clk_drv_ohm=0x%08x,// %d", ddr_set_t_p->clk_drv_ohm, ddr_set_t_p->clk_drv_ohm); + printf("\n.cs_drv_ohm=0x%08x,// %d", ddr_set_t_p->cs_drv_ohm, ddr_set_t_p->cs_drv_ohm); + printf("\n.ac_drv_ohm=0x%08x,// %d", ddr_set_t_p->ac_drv_ohm, ddr_set_t_p->ac_drv_ohm); + printf("\n.soc_data_drv_ohm_p=0x%08x,// %d", ddr_set_t_p->soc_data_drv_ohm_p, ddr_set_t_p->soc_data_drv_ohm_p); + printf("\n.soc_data_drv_ohm_n=0x%08x,// %d", ddr_set_t_p->soc_data_drv_ohm_n, ddr_set_t_p->soc_data_drv_ohm_n); + printf("\n.soc_data_odt_ohm_p=0x%08x,// %d", ddr_set_t_p->soc_data_odt_ohm_p, ddr_set_t_p->soc_data_odt_ohm_p); + printf("\n.soc_data_odt_ohm_n=0x%08x,// %d", ddr_set_t_p->soc_data_odt_ohm_n, ddr_set_t_p->soc_data_odt_ohm_n); + printf("\n.dram_data_drv_ohm=0x%08x,// %d", ddr_set_t_p->dram_data_drv_ohm, ddr_set_t_p->dram_data_drv_ohm); + printf("\n.dram_data_odt_ohm=0x%08x,// %d", ddr_set_t_p->dram_data_odt_ohm, ddr_set_t_p->dram_data_odt_ohm); + printf("\n.dram_ac_odt_ohm=0x%08x,// %d", ddr_set_t_p->dram_ac_odt_ohm, ddr_set_t_p->dram_ac_odt_ohm); + printf("\n.soc_clk_slew_rate=0x%08x,// %d", ddr_set_t_p->soc_clk_slew_rate, ddr_set_t_p->soc_clk_slew_rate); + printf("\n.soc_cs_slew_rate=0x%08x,// %d", ddr_set_t_p->soc_cs_slew_rate, ddr_set_t_p->soc_cs_slew_rate); + printf("\n.soc_ac_slew_rate=0x%08x,// %d", ddr_set_t_p->soc_ac_slew_rate, ddr_set_t_p->soc_ac_slew_rate); + printf("\n.soc_data_slew_rate=0x%08x,// %d", ddr_set_t_p->soc_data_slew_rate, ddr_set_t_p->soc_data_slew_rate); + printf("\n.vref_output_permil =0x%08x,// %d", ddr_set_t_p->vref_output_permil, ddr_set_t_p->vref_output_permil); + printf("\n.vref_receiver_permil =0x%08x,// %d", ddr_set_t_p->vref_receiver_permil, ddr_set_t_p->vref_receiver_permil); + printf("\n.vref_dram_permil=0x%08x,// %d", ddr_set_t_p->vref_dram_permil, ddr_set_t_p->vref_dram_permil); + printf("\n.max_core_timmming_frequency=0x%08x,// %d", ddr_set_t_p->max_core_timmming_frequency, ddr_set_t_p->max_core_timmming_frequency); + printf("\n.ac_trace_delay[0]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[0], ddr_set_t_p->ac_trace_delay[0]); + printf("\n.ac_trace_delay[1]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[1], ddr_set_t_p->ac_trace_delay[1]); + printf("\n.ac_trace_delay[2]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[2], ddr_set_t_p->ac_trace_delay[2]); + printf("\n.ac_trace_delay[3]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[3], ddr_set_t_p->ac_trace_delay[3]); + printf("\n.ac_trace_delay[4]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[4], ddr_set_t_p->ac_trace_delay[4]); + printf("\n.ac_trace_delay[5]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[5], ddr_set_t_p->ac_trace_delay[5]); + printf("\n.ac_trace_delay[6]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[6], ddr_set_t_p->ac_trace_delay[6]); + printf("\n.ac_trace_delay[7]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[7], ddr_set_t_p->ac_trace_delay[7]); + printf("\n.ac_trace_delay[8]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[8], ddr_set_t_p->ac_trace_delay[8]); + printf("\n.ac_trace_delay[9]=0x%08x,// %d", ddr_set_t_p->ac_trace_delay[9], ddr_set_t_p->ac_trace_delay[9]); + printf("\n.lpddr4_dram_vout_voltage_1_3_2_5_setting=0x%08x,// %d", ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting, ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting); + printf("\n.lpddr4_x8_mode=0x%08x,// %d", ddr_set_t_p->lpddr4_x8_mode, ddr_set_t_p->lpddr4_x8_mode); + printf("\n.ac_pinmux[0]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[0], ddr_set_t_p->ac_pinmux[0]); + printf("\n.ac_pinmux[1]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[1], ddr_set_t_p->ac_pinmux[1]); + printf("\n.ac_pinmux[2]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[2], ddr_set_t_p->ac_pinmux[2]); + printf("\n.ac_pinmux[3]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[3], ddr_set_t_p->ac_pinmux[3]); + printf("\n.ac_pinmux[4]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[4], ddr_set_t_p->ac_pinmux[4]); + printf("\n.ac_pinmux[5]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[5], ddr_set_t_p->ac_pinmux[5]); + printf("\n.ac_pinmux[6]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[6], ddr_set_t_p->ac_pinmux[6]); + printf("\n.ac_pinmux[7]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[7], ddr_set_t_p->ac_pinmux[7]); + printf("\n.ac_pinmux[8]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[8], ddr_set_t_p->ac_pinmux[8]); + printf("\n.ac_pinmux[9]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[9], ddr_set_t_p->ac_pinmux[9]); + printf("\n.ac_pinmux[10]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[10], ddr_set_t_p->ac_pinmux[10]); + printf("\n.ac_pinmux[11]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[11], ddr_set_t_p->ac_pinmux[11]); + printf("\n.ac_pinmux[12]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[12], ddr_set_t_p->ac_pinmux[12]); + printf("\n.ac_pinmux[13]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[13], ddr_set_t_p->ac_pinmux[13]); + printf("\n.ac_pinmux[14]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[14], ddr_set_t_p->ac_pinmux[14]); + printf("\n.ac_pinmux[15]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[15], ddr_set_t_p->ac_pinmux[15]); + printf("\n.ac_pinmux[16]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[16], ddr_set_t_p->ac_pinmux[16]); + printf("\n.ac_pinmux[17]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[17], ddr_set_t_p->ac_pinmux[17]); + printf("\n.ac_pinmux[18]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[18], ddr_set_t_p->ac_pinmux[18]); + printf("\n.ac_pinmux[19]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[19], ddr_set_t_p->ac_pinmux[19]); + printf("\n.ac_pinmux[20]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[20], ddr_set_t_p->ac_pinmux[20]); + printf("\n.ac_pinmux[21]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[21], ddr_set_t_p->ac_pinmux[21]); + printf("\n.ac_pinmux[22]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[22], ddr_set_t_p->ac_pinmux[22]); + printf("\n.ac_pinmux[23]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[23], ddr_set_t_p->ac_pinmux[23]); + printf("\n.ac_pinmux[24]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[24], ddr_set_t_p->ac_pinmux[24]); + printf("\n.ac_pinmux[25]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[25], ddr_set_t_p->ac_pinmux[25]); + printf("\n.ac_pinmux[26]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[26], ddr_set_t_p->ac_pinmux[26]); + printf("\n.ac_pinmux[27]=0x%08x,// %d", ddr_set_t_p->ac_pinmux[27], ddr_set_t_p->ac_pinmux[27]); + printf("\n.dfi_pinmux[0]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[0], ddr_set_t_p->dfi_pinmux[0]); + printf("\n.dfi_pinmux[1]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[1], ddr_set_t_p->dfi_pinmux[1]); + printf("\n.dfi_pinmux[2]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[2], ddr_set_t_p->dfi_pinmux[2]); + printf("\n.dfi_pinmux[3]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[3], ddr_set_t_p->dfi_pinmux[3]); + printf("\n.dfi_pinmux[4]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[4], ddr_set_t_p->dfi_pinmux[4]); + printf("\n.dfi_pinmux[5]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[5], ddr_set_t_p->dfi_pinmux[5]); + printf("\n.dfi_pinmux[6]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[6], ddr_set_t_p->dfi_pinmux[6]); + printf("\n.dfi_pinmux[7]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[7], ddr_set_t_p->dfi_pinmux[7]); + printf("\n.dfi_pinmux[8]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[8], ddr_set_t_p->dfi_pinmux[8]); + printf("\n.dfi_pinmux[9]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[9], ddr_set_t_p->dfi_pinmux[9]); + printf("\n.dfi_pinmux[10]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[10], ddr_set_t_p->dfi_pinmux[10]); + printf("\n.dfi_pinmux[11]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[11], ddr_set_t_p->dfi_pinmux[11]); + printf("\n.dfi_pinmux[12]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[12], ddr_set_t_p->dfi_pinmux[12]); + printf("\n.dfi_pinmux[13]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[13], ddr_set_t_p->dfi_pinmux[13]); + printf("\n.dfi_pinmux[14]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[14], ddr_set_t_p->dfi_pinmux[14]); + printf("\n.dfi_pinmux[15]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[15], ddr_set_t_p->dfi_pinmux[15]); + printf("\n.dfi_pinmux[16]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[16], ddr_set_t_p->dfi_pinmux[16]); + printf("\n.dfi_pinmux[17]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[17], ddr_set_t_p->dfi_pinmux[17]); + printf("\n.dfi_pinmux[18]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[18], ddr_set_t_p->dfi_pinmux[18]); + printf("\n.dfi_pinmux[19]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[19], ddr_set_t_p->dfi_pinmux[19]); + printf("\n.dfi_pinmux[20]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[20], ddr_set_t_p->dfi_pinmux[20]); + printf("\n.dfi_pinmux[21]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[21], ddr_set_t_p->dfi_pinmux[21]); + printf("\n.dfi_pinmux[22]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[22], ddr_set_t_p->dfi_pinmux[22]); + printf("\n.dfi_pinmux[23]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[23], ddr_set_t_p->dfi_pinmux[23]); + printf("\n.dfi_pinmux[24]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[24], ddr_set_t_p->dfi_pinmux[24]); + printf("\n.dfi_pinmux[25]=0x%08x,// %d", ddr_set_t_p->dfi_pinmux[25], ddr_set_t_p->dfi_pinmux[25]); + printf("\n.slt_test_function[0] =0x%08x,// %d", ddr_set_t_p->slt_test_function[0], ddr_set_t_p->slt_test_function[0]); + printf("\n.slt_test_function[1] =0x%08x,// %d", ddr_set_t_p->slt_test_function[1], ddr_set_t_p->slt_test_function[1]); + printf("\n.tdqs2dq=0x%08x,// %d", ddr_set_t_p->tdqs2dq, ddr_set_t_p->tdqs2dq); + printf("\n.dram_data_wr_odt_ohm=0x%08x,// %d", ddr_set_t_p->dram_data_wr_odt_ohm, ddr_set_t_p->dram_data_wr_odt_ohm); + printf("\n.bitTimeControl_2d=0x%08x,// %d", ddr_set_t_p->bitTimeControl_2d, ddr_set_t_p->bitTimeControl_2d); + printf("\n.ddr_dmc_remap[0]=0x%08x,// %d", ddr_set_t_p->ddr_dmc_remap[0], ddr_set_t_p->ddr_dmc_remap[0]); + printf("\n.ddr_dmc_remap[1]=0x%08x,// %d", ddr_set_t_p->ddr_dmc_remap[1], ddr_set_t_p->ddr_dmc_remap[1]); + printf("\n.ddr_dmc_remap[2]=0x%08x,// %d", ddr_set_t_p->ddr_dmc_remap[2], ddr_set_t_p->ddr_dmc_remap[2]); + printf("\n.ddr_dmc_remap[3]=0x%08x,// %d", ddr_set_t_p->ddr_dmc_remap[3], ddr_set_t_p->ddr_dmc_remap[3]); + printf("\n.ddr_dmc_remap[4]=0x%08x,// %d", ddr_set_t_p->ddr_dmc_remap[4], ddr_set_t_p->ddr_dmc_remap[4]); + printf("\n.ddr_lpddr34_ca_remap[0]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_ca_remap[0], ddr_set_t_p->ddr_lpddr34_ca_remap[0]); + printf("\n.ddr_lpddr34_ca_remap[1]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_ca_remap[1], ddr_set_t_p->ddr_lpddr34_ca_remap[1]); + printf("\n.ddr_lpddr34_ca_remap[2]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_ca_remap[2], ddr_set_t_p->ddr_lpddr34_ca_remap[2]); + printf("\n.ddr_lpddr34_ca_remap[3]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_ca_remap[3], ddr_set_t_p->ddr_lpddr34_ca_remap[3]); + printf("\n.ddr_lpddr34_dq_remap[0]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[0], ddr_set_t_p->ddr_lpddr34_dq_remap[0]); + printf("\n.ddr_lpddr34_dq_remap[1]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[1], ddr_set_t_p->ddr_lpddr34_dq_remap[1]); + printf("\n.ddr_lpddr34_dq_remap[2]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[2], ddr_set_t_p->ddr_lpddr34_dq_remap[2]); + printf("\n.ddr_lpddr34_dq_remap[3]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[3], ddr_set_t_p->ddr_lpddr34_dq_remap[3]); + printf("\n.ddr_lpddr34_dq_remap[4]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[4], ddr_set_t_p->ddr_lpddr34_dq_remap[4]); + printf("\n.ddr_lpddr34_dq_remap[5]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[5], ddr_set_t_p->ddr_lpddr34_dq_remap[5]); + printf("\n.ddr_lpddr34_dq_remap[6]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[6], ddr_set_t_p->ddr_lpddr34_dq_remap[6]); + printf("\n.ddr_lpddr34_dq_remap[7]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[7], ddr_set_t_p->ddr_lpddr34_dq_remap[7]); + printf("\n.ddr_lpddr34_dq_remap[8]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[8], ddr_set_t_p->ddr_lpddr34_dq_remap[8]); + printf("\n.ddr_lpddr34_dq_remap[9]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[9], ddr_set_t_p->ddr_lpddr34_dq_remap[9]); + printf("\n.ddr_lpddr34_dq_remap[10]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[10], ddr_set_t_p->ddr_lpddr34_dq_remap[10]); + printf("\n.ddr_lpddr34_dq_remap[11]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[11], ddr_set_t_p->ddr_lpddr34_dq_remap[11]); + printf("\n.ddr_lpddr34_dq_remap[12]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[12], ddr_set_t_p->ddr_lpddr34_dq_remap[12]); + printf("\n.ddr_lpddr34_dq_remap[13]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[13], ddr_set_t_p->ddr_lpddr34_dq_remap[13]); + printf("\n.ddr_lpddr34_dq_remap[14]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[14], ddr_set_t_p->ddr_lpddr34_dq_remap[14]); + printf("\n.ddr_lpddr34_dq_remap[15]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[15], ddr_set_t_p->ddr_lpddr34_dq_remap[15]); + printf("\n.ddr_lpddr34_dq_remap[16]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[16], ddr_set_t_p->ddr_lpddr34_dq_remap[16]); + printf("\n.ddr_lpddr34_dq_remap[17]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[17], ddr_set_t_p->ddr_lpddr34_dq_remap[17]); + printf("\n.ddr_lpddr34_dq_remap[18]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[18], ddr_set_t_p->ddr_lpddr34_dq_remap[18]); + printf("\n.ddr_lpddr34_dq_remap[19]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[19], ddr_set_t_p->ddr_lpddr34_dq_remap[19]); + printf("\n.ddr_lpddr34_dq_remap[20]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[20], ddr_set_t_p->ddr_lpddr34_dq_remap[20]); + printf("\n.ddr_lpddr34_dq_remap[21]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[21], ddr_set_t_p->ddr_lpddr34_dq_remap[21]); + printf("\n.ddr_lpddr34_dq_remap[22]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[22], ddr_set_t_p->ddr_lpddr34_dq_remap[22]); + printf("\n.ddr_lpddr34_dq_remap[23]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[23], ddr_set_t_p->ddr_lpddr34_dq_remap[23]); + printf("\n.ddr_lpddr34_dq_remap[24]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[24], ddr_set_t_p->ddr_lpddr34_dq_remap[24]); + printf("\n.ddr_lpddr34_dq_remap[25]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[25], ddr_set_t_p->ddr_lpddr34_dq_remap[25]); + printf("\n.ddr_lpddr34_dq_remap[26]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[26], ddr_set_t_p->ddr_lpddr34_dq_remap[26]); + printf("\n.ddr_lpddr34_dq_remap[27]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[27], ddr_set_t_p->ddr_lpddr34_dq_remap[27]); + printf("\n.ddr_lpddr34_dq_remap[28]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[28], ddr_set_t_p->ddr_lpddr34_dq_remap[28]); + printf("\n.ddr_lpddr34_dq_remap[29]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[29], ddr_set_t_p->ddr_lpddr34_dq_remap[29]); + printf("\n.ddr_lpddr34_dq_remap[30]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[30], ddr_set_t_p->ddr_lpddr34_dq_remap[30]); + printf("\n.ddr_lpddr34_dq_remap[31]=0x%08x,// %d", ddr_set_t_p->ddr_lpddr34_dq_remap[31], ddr_set_t_p->ddr_lpddr34_dq_remap[31]); + printf("\n.dram_rtt_nom_wr_park[0]=0x%08x,// %d", ddr_set_t_p->dram_rtt_nom_wr_park[0], ddr_set_t_p->dram_rtt_nom_wr_park[0]); + printf("\n.dram_rtt_nom_wr_park[1]=0x%08x,// %d", ddr_set_t_p->dram_rtt_nom_wr_park[1], ddr_set_t_p->dram_rtt_nom_wr_park[1]); + printf("\n.ddr_func=0x%08x,// %d", ddr_set_t_p->ddr_func, ddr_set_t_p->ddr_func); + for (ps = 0; ps < 2; ps++) { + for (temp_count = 0; temp_count < 10; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].ac_trace_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count]); - for ( temp_count=0;temp_count<16;temp_count++) - printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count]); - for ( temp_count=0;temp_count<72;temp_count++) - printf("\n.cfg_ddr_training_delay_ps[%d].read_dq_bit_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count]); - for ( temp_count=0;temp_count<16;temp_count++) - //printf("\n.write_dqs_delay[%d]=%d,",temp_count,ddr_set_t_p->write_dqs_delay[temp_count]); - printf("\n.cfg_ddr_training_delay_ps[%d].write_dqs_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count]); - for ( temp_count=0;temp_count<72;temp_count++) - //printf("\n.write_dq_bit_delay[%d]=%d,",temp_count,ddr_set_t_p->write_dq_bit_delay[temp_count]); - printf("\n.cfg_ddr_training_delay_ps[%d].write_dq_bit_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count]); - for ( temp_count=0;temp_count<16;temp_count++) - //printf("\n.read_dqs_gate_delay[%d]=%d,",temp_count,ddr_set_t_p->read_dqs_gate_delay[temp_count]); - printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_gate_delay[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count]); - for ( temp_count=0;temp_count<36;temp_count++) - //printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]); - printf("\n.cfg_ddr_training_delay_ps[%d].soc_bit_vref[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count]); - for ( temp_count=0;temp_count<36;temp_count++) - //printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]); - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count],ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count]); - //printf("\n.soc_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->soc_bit_vref[temp_count],ddr_set_t_p->soc_bit_vref[temp_count]); - for ( temp_count=0;temp_count<32;temp_count++) - //printf("\n.dram_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->dram_bit_vref[temp_count]); - printf("\n.cfg_ddr_training_delay_ps[%d].dram_bit_vref[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count]); + for (temp_count = 0; temp_count < 16; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count]); + for (temp_count = 0; temp_count < 72; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].read_dq_bit_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count]); + for (temp_count = 0; temp_count < 16; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].write_dqs_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count]); + for (temp_count = 0; temp_count < 72; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].write_dq_bit_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count]); + for (temp_count = 0; temp_count < 16; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_gate_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count]); + for (temp_count = 0; temp_count < 36; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].soc_bit_vref[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count]); + for (temp_count = 0; temp_count < 36; temp_count++) + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count], ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count]); + for (temp_count = 0; temp_count < 32; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].dram_bit_vref[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count]); - //ddr_set_t_p->dq_dqs_delay_flag=0xff; - //printf("\n.rever3=0x%08x,// %d",ddr_set_t_p->rever3,ddr_set_t_p->rever3); - printf("\n.cfg_ddr_training_delay_ps[%d].dfi_mrl=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl); - printf("\n.cfg_ddr_training_delay_ps[%d].dfi_hwtmrl=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl); - printf("\n.cfg_ddr_training_delay_ps[%d].ARdPtrInitVal=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal); + printf("\n.cfg_ddr_training_delay_ps[%d].dfi_mrl=0x%08x,// %d", ps, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl); + printf("\n.cfg_ddr_training_delay_ps[%d].dfi_hwtmrl=0x%08x,// %d", ps, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl); + printf("\n.cfg_ddr_training_delay_ps[%d].ARdPtrInitVal=0x%08x,// %d", ps, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal); - printf("\n.cfg_ddr_training_delay_ps[%d].csr_vrefinglobal=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.cfg_ddr_training_delay_ps[%d].csr_dqsrcvcntrl[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count]); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.cfg_ddr_training_delay_ps[%d].csr_pptdqscntinvtrntg0[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count]); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.cfg_ddr_training_delay_ps[%d].csr_pptdqscntinvtrntg1[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count]); - for ( temp_count=0;temp_count<9;temp_count++) - printf("\n.cfg_ddr_training_delay_ps[%d].csr_seq0bgpr[%d]=0x%08x,// %d",ps,temp_count,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count],ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count]); - printf("\n.cfg_ddr_training_delay_ps[%d].csr_dllgainctl=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl); - printf("\n.cfg_ddr_training_delay_ps[%d].csr_dlllockpara=0x%08x,// %d",ps,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara,ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara); + printf("\n.cfg_ddr_training_delay_ps[%d].csr_vrefinglobal=0x%08x,// %d", ps, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal); + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].csr_dqsrcvcntrl[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count]); + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].csr_pptdqscntinvtrntg0[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count]); + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].csr_pptdqscntinvtrntg1[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count]); + for (temp_count = 0; temp_count < 9; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].csr_seq0bgpr[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count]); + printf("\n.cfg_ddr_training_delay_ps[%d].csr_dllgainctl=0x%08x,// %d", ps, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl); + printf("\n.cfg_ddr_training_delay_ps[%d].csr_dlllockpara=0x%08x,// %d", ps, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara); } - #if 0 - for ( temp_count=0;temp_count<16;temp_count++) - //printf("\n.dram_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->dram_bit_vref[temp_count]); - printf("\n.retraining[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining[temp_count],ddr_set_t_p->retraining[temp_count]); - #endif - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_pllctrl3=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count],ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count]); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count],ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count]); - for ( temp_count=0;temp_count<4;temp_count++) - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count],ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count]); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_pllctrl3=0x%08x,// %d", ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3); + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count], ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count]); + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count], ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count]); + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count], ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count]); - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtcamode=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode); - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena); - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb); - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13); - printf("\n.cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23=0x%08x,// %d",ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23,ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtcamode=0x%08x,// %d", ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena=0x%08x,// %d", ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb=0x%08x,// %d", ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13=0x%08x,// %d", ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13); + printf("\n.cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23=0x%08x,// %d", ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23, ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23); printf("\n},\n"); + } + return 1; +} +uint32_t ddr_mask_convert_offset(uint32_t mask) +{ + uint32_t offset = 0; + + while ((mask & 1)) { + offset++; + mask = (mask >> 1); + } + return offset; +} + +uint32_t ddr_cacl_phy_delay_all_step_c2(char test_index, uint32_t value) +{ + //value bit0-15 fine value ,bit 16-32 coarse value + uint32_t result = 0; + uint32_t coarse_value = 0; + uint32_t fine_value = 0; + + if (value) + coarse_value = (value >> 16); + else + coarse_value = 0; + fine_value = (value & 0xffff); + result = (coarse_value * 128 + fine_value); + return result; +} + +uint32_t ddr_cacl_phy_over_ride_back_reg_c2(char test_index, uint32_t value) +{ + uint32_t result = 0; //bit0-15 fine value ,bit 16-32 coarse value + + if ((test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)) { + if (value > (3 * 128 + 127)) + value = (3 * 128 + 127); + result = (value % 128) + ((value / 128) << 16); + } else if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) || (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)) { + if (value > (7 * 128 + 127)) + value = (7 * 128 + 127); + result = (value % 128) + ((value / 128) << 16); + } else if ((test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) || (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)) { + if (value > (1 * 128 + 127)) + value = (1 * 128 + 127); + result = value; + } else if ((test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) { + if (value > (31 * 128 + 127)) + value = (31 * 128 + 127); + result = (value % 128) + ((value / 128) << 16); + } else if ((test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF)) { + if (value > (63)) + value = (63); + result = value; + } + return result; +} + +uint32_t ddr_disable_update_delay_line_c2(void) +{ + //config phy update use register change and ctrl update req and condition,power on default is or condition + //disable ctrl update req + return 1; +} + +uint32_t ddr_enable_update_delay_line_c2(void) +{ + //config phy update use register change and ctrl update req and condition,power on default is or condition + //enable ctrl update req + return 1; +} + +uint32_t ddr_phy_training_reg_read_write(ddr_set_t_c2 *p_ddrs, char index, + uint32_t sub_index, uint32_t read_write_value, char read_write_enable, char ps) +{ + //read_write_value bit0-15 fine value ,bit 16-32 coarse value + uint32_t delay_old_value = 0; + uint32_t delay_new_value = 0; + uint32_t delay_reg_coarse_value = 0; + uint32_t delay_reg_fine_value = 0; + uint64_t reg_add_coarse = 0; + uint32_t reg_add_coarse_bit_mask = 0; + uint64_t reg_add_fine = 0; + uint32_t reg_add_fine_bit_mask = 0; + uint64_t add_base = (p_ddr_base->ddr_phy_base_address); + uint32_t reg_offset = 0; + uint32_t temp_save = 0; + +#define DDR_X32_F0_A800 (0x800) +#define DDR_X32_F0_A804 (0x804) +#define DDR_X32_F0_A808 (0x808) +#define DDR_X32_F0_A810 (0x810) +#define DDR_X32_F0_A828 (0x828) +#define DDR_X32_F0_A82C (0x82c) +#define DDR_X32_F0_A840 (0x840) +#define DDR_X32_F0_A844 (0x844) +#define DDR_X32_F0_A850 (0x850) +#define DDR_X32_F0_A858 (0x858) +#define DDR_X32_F0_A890 (0x890) +#define DDR_X32_F0_A8D0 (0x8d0) +#define DDR_X32_F0_A8F0 (0x8F0) +#define DDR_X32_F0_A8F8 (0x8F8) +#define DDR_X32_F0_A8D4 (0x8d4) +#define DDR_X32_F0_A930 (0x930) +#define DDR_X32_F0_AC08 (0xc08) +#define DDR_X32_F0_AC2C (0xc2c) +#define DDR_X32_F0_AC40 (0xc40) +#define DDR_X32_F0_AC44 (0xc44) +#define DDR_X32_F0_AC50 (0xc50) +#define DDR_X32_F0_AC58 (0xc58) +#define DDR_X32_F0_ACD0 (0xcd0) +#define DDR_X32_F0_ACD4 (0xcd4) +#define DDR_X32_F0_ACF0 (0xcf0) +#define DDR_X32_F0_ACF8 (0xcf8) +#define DDR_X32_F0_AD30 (0xD30) + reg_offset = ps * (0x1000); + if (!index) + return read_write_value; + //ac group0 then ac group1 + if (index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + if (sub_index < 8) { //ac group 0 + switch (sub_index) { + case 0: //cke0 + reg_add_coarse = (add_base + DDR_X32_F0_A808 + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A82C + reg_offset); + reg_add_coarse_bit_mask = (~(3 << 4)); + reg_add_fine_bit_mask = (~(0x7f << 16)); + break; + case 1: //cke1 + reg_add_coarse = (add_base + DDR_X32_F0_AC08 + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_AC2C + reg_offset); + reg_add_coarse_bit_mask = (~(3 << 4)); + reg_add_fine_bit_mask = (~(0x7f << 16)); + break; + case 2: //cs0 + reg_add_coarse = (add_base + DDR_X32_F0_A808 + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A82C + reg_offset); + reg_add_coarse_bit_mask = (~(3 << 2)); + reg_add_fine_bit_mask = (~(0x7f << 8)); + break; + case 3: //cs1 + reg_add_coarse = (add_base + DDR_X32_F0_AC08 + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_AC2C + reg_offset); + reg_add_coarse_bit_mask = (~(3 << 2)); + reg_add_fine_bit_mask = (~(0x7f << 8)); + break; + case 4: //odt0 + reg_add_coarse = (add_base + DDR_X32_F0_A808 + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A82C + reg_offset); + reg_add_coarse_bit_mask = (~(3 << 0)); + reg_add_fine_bit_mask = (~(0x7f << 0)); + break; + case 5: //odt1 + reg_add_coarse = (add_base + DDR_X32_F0_AC08 + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_AC2C + reg_offset); + reg_add_coarse_bit_mask = (~(3 << 0)); + reg_add_fine_bit_mask = (~(0x7f << 0)); + break; + case 6: //clk + reg_add_coarse = (add_base + DDR_X32_F0_A804 + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A828 + reg_offset); + reg_add_coarse_bit_mask = (~(1 << 18)); + reg_add_fine_bit_mask = (~(0x7f << 8)); + break; + case 7: //this pin use for act pin + //reg_add_coarse = 0; + //reg_add_fine = 0; + reg_add_coarse = (add_base + DDR_X32_F0_A800 + (((36 - 8 - 4 - 2 + 2) / 16) << 2) + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A810 + (((36 - 8 - 4 - 2 + 2) / 4) << 2) + reg_offset); + reg_add_coarse_bit_mask = (~(3 << (((36 - 8 - 4 - 2 + 2) % 16) << 1))); + reg_add_fine_bit_mask = (~(0x7f << (((36 - 8 - 4 - 2 + 2) % 4) * 8))); + + break; + } + } else if (sub_index < (8 + 16)) { ////ac group 1 + reg_add_coarse = (add_base + DDR_X32_F0_A800 + (((sub_index - 8) / 16) << 2) + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A810 + (((sub_index - 8) / 4) << 2) + reg_offset); + reg_add_coarse_bit_mask = (~(3 << (((sub_index - 8) % 16) << 1))); + reg_add_fine_bit_mask = (~(0x7f << (((sub_index - 8) % 4) * 8))); + } else if (sub_index < (8 + 16 + 4)) { + reg_add_coarse = 0; + reg_add_fine = 0; + } else if (sub_index < (8 + 16 + 4 + 3+2)) { + reg_add_coarse = (add_base + DDR_X32_F0_A800 + (((sub_index - 8 - 4) / 16) << 2) + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A810 + (((sub_index - 8 - 4) / 4) << 2) + reg_offset); + reg_add_coarse_bit_mask = (~(3 << (((sub_index - 8 - 4) % 16) << 1))); + reg_add_fine_bit_mask = (~(0x7f << (((sub_index - 8 - 4) % 4) * 8))); + } + #if 0 + else if (sub_index < (8 + 16 + 4 + 3 + 2)) { + reg_add_coarse = 0; + reg_add_fine = 0; + } + #endif + else if (sub_index < (8 + 28)) { + reg_add_coarse = (add_base + DDR_X32_F0_A800 + (((sub_index - 8 - 4 - 2 + 2) / 16) << 2) + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A810 + (((sub_index - 8 - 4 - 2 + 2) / 4) << 2) + reg_offset); + reg_add_coarse_bit_mask = (~(3 << (((sub_index - 8 - 4 - 2 + 2) % 16) << 1))); + reg_add_fine_bit_mask = (~(0x7f << (((sub_index - 8 - 4 - 2 + 2) % 4) * 8))); + } else { + reg_add_coarse = 0; + reg_add_fine = 0; + } + } else if (index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + reg_add_coarse = (add_base + DDR_X32_F0_A8D4 + (sub_index / 4) * ( + DDR_X32_F0_ACD4 - DDR_X32_F0_A8D4) + (((sub_index % 4) << 1) << 2) + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A8F8 + (sub_index / 4) * ( + DDR_X32_F0_ACF8 - DDR_X32_F0_A8F8) + ((sub_index % 4) << 4) + reg_offset); + reg_add_coarse_bit_mask = (~(3 << ((4)))); + reg_add_fine_bit_mask = (~(0x7f << 8)); + } else if (index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + reg_add_coarse = 0; + reg_add_fine = (add_base + DDR_X32_F0_A858 + (sub_index / 4) * ( + DDR_X32_F0_AC58 - DDR_X32_F0_A858) + ((sub_index % 4) << 4) + reg_offset); + reg_add_coarse_bit_mask = 0; + reg_add_fine_bit_mask = (~(0xff << (8))); + } + //d0-d7 dm0 d8-d15 dm1... + else if (index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + reg_add_coarse = (add_base + DDR_X32_F0_A8D0 + (sub_index / 36) * (DDR_X32_F0_ACD0 + - DDR_X32_F0_A8D0) + ((((sub_index % 36) / 9) << 1) << 2) + (((((sub_index) % 9) / 8)) << 2) + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A8F0 + (sub_index / 36) * (DDR_X32_F0_ACF0 + - DDR_X32_F0_A8F0) + ((((sub_index % 36) / 9)) << 4) + (((((sub_index) % 9)) >> 2) << 2) + reg_offset); + reg_add_coarse_bit_mask = (~(7 << (((((sub_index) % 9) % 8) << 2)))); + reg_add_fine_bit_mask = (~(0x7f << (((((sub_index) % 9) % 4) << 3)))); + } + //d0-d7 dm0 d8-d15 dm1... + else if (index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + reg_add_coarse = 0; + reg_add_fine = (add_base + DDR_X32_F0_A850 + (sub_index / 36) * (DDR_X32_F0_AC50 + - DDR_X32_F0_A850) + ((((sub_index % 36) / 9)) << 4) + (((sub_index % 9) >> 2) << 2) + reg_offset); + reg_add_coarse_bit_mask = 0; + reg_add_fine_bit_mask = (~(0xff << (((((sub_index) % 9) % 4) << 3)))); + } else if (index == DMC_TEST_WINDOW_INDEX_RXENDLY) { + reg_add_coarse = (add_base + DDR_X32_F0_A840 + (sub_index / 4) * (DDR_X32_F0_AC40 + - DDR_X32_F0_A840) + reg_offset); + reg_add_fine = (add_base + DDR_X32_F0_A844 + (sub_index / 4) * (DDR_X32_F0_AC44 + - DDR_X32_F0_A844) + reg_offset); + reg_add_coarse_bit_mask = (~(0x1f << ((sub_index << 3)))); + reg_add_fine_bit_mask = (~(0x7f << ((sub_index << 3)))); + } else if (index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { + if (sub_index < (36)) { //vref dq and dbi + reg_add_coarse = 0; + reg_add_fine = (add_base + DDR_X32_F0_A890 + (((sub_index / 9) * 4) << 2) + + (((sub_index % 9) >> 2) << 2) + reg_offset); + reg_add_coarse_bit_mask = 0; + reg_add_fine_bit_mask = (~(0x3f << (((((sub_index) % 9) % 4) << 3)))); + } else if (sub_index < (44)) { //vref dqs and dqsn + reg_add_coarse = 0; + reg_add_fine = (add_base + DDR_X32_F0_A890 + 8 + ((((sub_index - 36) / 2) * 4) << 2) + reg_offset); + reg_add_coarse_bit_mask = 0; + reg_add_fine_bit_mask = (~(0x3f << (((((sub_index - 36) % 2)) << 3) + 8))); + } + } else if (index == DMC_TEST_WINDOW_INDEX_DRAM_VREF) { + if (sub_index < (36)) { //DDR_X32_F0_AD30 DDR_X32_F0_A930 + reg_add_coarse = 0; + reg_add_fine = (add_base + DDR_X32_F0_A930 + + ((DDR_X32_F0_AD30 - DDR_X32_F0_A930) * sub_index % 2) + reg_offset); + reg_add_coarse_bit_mask = 0; + reg_add_fine_bit_mask = (~(0xff << 0)); + } + } else if (index == DMC_TEST_WINDOW_INDEX_EXTERA_PS) { + if (sub_index == 1) { //DDR_X32_F0_AD30 DDR_X32_F0_A930 + } + + return read_write_value; + } + + { + if (reg_add_coarse) + delay_reg_coarse_value = (((rd_reg(reg_add_coarse)) & (~reg_add_coarse_bit_mask)) + >> (ddr_mask_convert_offset(reg_add_coarse_bit_mask))); + if (reg_add_fine) + delay_reg_fine_value = (((rd_reg(reg_add_fine)) & (~reg_add_fine_bit_mask)) + >> (ddr_mask_convert_offset(reg_add_fine_bit_mask))); + + delay_old_value = ((delay_reg_coarse_value << 16) | delay_reg_fine_value); + delay_old_value = ddr_cacl_phy_delay_all_step_c2(index, delay_old_value); + } + + if (read_write_enable == REGISTER_READ) { + read_write_value = delay_old_value; + } else if (read_write_enable == REGISTER_WRITE) { + delay_new_value = read_write_value; + delay_new_value = ddr_cacl_phy_over_ride_back_reg_c2(index, delay_new_value); + temp_save = rd_reg(p_ddr_base->ddr_dmc_refresh_ctrl_address); + wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), 0x21); //take care T5 no set bit //bit 22 dmc to control DFI_CTRLUPD_REQ with zq generation together. + ddr_udelay_dummy(1); + wr_reg(p_ddr_base->ddr_phy_base_address + 0x2440, 1); //detect should update delay when controller update arrive + ddr_udelay_dummy(1); + if (reg_add_coarse) + wr_reg(reg_add_coarse, ((rd_reg(reg_add_coarse)) & (reg_add_coarse_bit_mask)) + | ((delay_new_value >> 16) << (ddr_mask_convert_offset(reg_add_coarse_bit_mask)))); + if (reg_add_fine) + wr_reg(reg_add_fine, ((rd_reg(reg_add_fine)) & (reg_add_fine_bit_mask)) + | ((delay_new_value & 0xffff) << (ddr_mask_convert_offset(reg_add_fine_bit_mask)))); + ddr_udelay_dummy(1); + wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), (temp_save & (~((1 << 22) | (1 << 4))))); + ddr_udelay_dummy(1); + wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), (temp_save & (~((1 << 22)))) | (1 << 4)); + ddr_udelay_dummy(40); //since we are use 3 refresh time ,so shuld over 4*7.8us make sure a update command send out ,then maybe fail + wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), (temp_save & (~((1 << 22)))) | (1 << 4)); + ddr_udelay_dummy(1); + wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), (temp_save)); + } + printf("delay_old_value,%08x,read_write_value,%08x,index,%08x,sub_index,%08x\n", delay_old_value, read_write_value, index, sub_index); + + return read_write_value; +} + +void ddr_read_write_training_value(ddr_set_t_c2 *p_ddrs, char over_ride_index, + char read_write, uint32_t ps, void *input, char print) +{ + uint16_t t_count = 0; + char count_max = 72; + uint16_t t_count_value = 0; + uint16_t delay_temp = 0; + char *input_uint8_p = input; + uint16_t *input_uint16_p = input; + char p_size = 1; + char read_skip = 0; + + for (t_count = 0; t_count < count_max; t_count++) { + if ((over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) + || (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) + || (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) + || (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) + || (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) + || (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) + || (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) + ) { + if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + p_size = 2; + count_max = 36; + } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + p_size = 2; + count_max = 8; + } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + p_size = 1; + count_max = 72; + } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) { + p_size = 2; + count_max = 8; + } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + p_size = 1; + count_max = 8; + } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + p_size = 2; + count_max = 72; + } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { + p_size = 1; + count_max = 44; + } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_EXTERA_PS) { + p_size = 2; + count_max = 8; + } + if (read_write == REGISTER_READ) { + read_skip = 0; + if ((ps == 3) && (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF)) { + if (t_count > 35) + read_skip = 1; + else //ro training no vref value + if ((t_count % 9) == 8) + read_skip = 1; + } + t_count_value = ddr_phy_training_reg_read_write(p_ddrs, + over_ride_index, t_count, t_count_value, read_write, ps); + delay_temp = t_count_value; + if (read_skip) { + } else { + if (p_size == 1) + (*input_uint8_p) = delay_temp; + if (p_size == 2) + (*input_uint16_p) = delay_temp; + } + } else { + if (p_size == 1) + delay_temp = (*input_uint8_p); + if (p_size == 2) + delay_temp = (*input_uint16_p); + t_count_value = delay_temp; + ddr_phy_training_reg_read_write(p_ddrs, over_ride_index, t_count, t_count_value, read_write, ps); + } + if (p_size == 1) + input_uint8_p++; + if (p_size == 2) + input_uint16_p++; + + if (print == DDR_PRINT_ENABLE) { + printf("training_index %d sub_index %d phase %d\n", over_ride_index, t_count, t_count_value); + } else { //maybe funciton will be optimize not use the variable + } + //printf("training_index %d sub_index %d phase %d\n", over_ride_index, t_count, t_count_value); + } + } +} /* ddr_read_write_training_value */ + +void ddr_read_write_training_all_delay_value(ddr_set_t_c2 *p_ddrs, char read_write, char print) +{ + uint32_t ps = 0; + + for (ps = 0; ps < 2; ) { + ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_ATXDLY, + read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].ac_trace_delay), print); + ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_TXDQSDLY, + read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].write_dqs_delay), print); + ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_RXCLKDLY, + read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].read_dqs_delay), print); + ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_TXDQDLY, + read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay), print); + ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_RXPBDLY, + read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay), print); + ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_RXENDLY, + read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay), print); + ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_SOC_VREF, + read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].soc_bit_vref), print); + ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_EXTERA_PS, + read_write, ps, 0, print); + p_ddrs->cfg_ddr_training_delay_ps[ps].dram_bit_vref[0] = ((rd_reg(p_ddr_base->ddr_phy_base_address + 0x3930)) & 0x3f); + + ps = ps + 1; + } +} + +uint32_t ddr_get_c2_bdlr_100step_min(void) +{ + uint32_t bdlr_100step = 0; + uint32_t DRAMFreq = 0; + uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128); + + DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t); + uint32_t dll_counter = 0; + uint32_t dll_counter_max = 0; + + dll_counter = (((rd_reg(p_ddr_base->ddr_phy_base_address + 0x3130)))); + dll_counter_max = ddr_max((dll_counter & 0xff), ((dll_counter >> 8) & 0xff)); + dll_counter_max = ddr_max(dll_counter_max, ((dll_counter >> 16) & 0xff)); + dll_counter_max = ddr_max(dll_counter_max, ((dll_counter >> 24) & 0xff)); + dll_counter_max = dll_counter_max ? dll_counter_max : 1; + bdlr_100step = (100000000 / (2 * (DRAMFreq))) / (dll_counter_max); + return bdlr_100step; +} + +uint32_t ddr_get_c2_bdlr_100step_max(void) +{ + uint32_t bdlr_100step = 0; + uint32_t DRAMFreq = 0; + uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128); + + DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t); + uint32_t dll_counter = 0; + uint32_t dll_counter_min = 0; + + dll_counter = (((rd_reg(p_ddr_base->ddr_phy_base_address + 0x312c)))); + dll_counter_min = ddr_min((dll_counter & 0xff), ((dll_counter >> 8) & 0xff)); + dll_counter_min = ddr_min(dll_counter_min, ((dll_counter >> 16) & 0xff)); + dll_counter_min = ddr_min(dll_counter_min, ((dll_counter >> 24) & 0xff)); + dll_counter_min = dll_counter_min ? dll_counter_min : 1; + bdlr_100step = (100000000 / (2 * (DRAMFreq))) / (dll_counter_min); + return bdlr_100step; +} + +uint32_t ddr_get_c2_bdlr_100step(void) +{ + uint32_t bdlr_100step = 0; + uint32_t DRAMFreq = 0; + uint32_t dll_counter = 0; + uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128); + + DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t); + dll_counter = rd_reg(p_ddr_base->ddr_phy_base_address + 0x3128); + dll_counter = (((dll_counter & 0xff) + ((dll_counter >> 8) & 0xff) + ((dll_counter >> 16) & 0xff) + ((dll_counter >> 24) & 0xff)) >> 2); + bdlr_100step = (100000000 / (2 * DRAMFreq)) / (dll_counter + 1); + return bdlr_100step; +} + +uint32_t ddr_get_c2_bdlr_100step_cur(void) +{ + uint32_t bdlr_100step = 0; + uint32_t DRAMFreq = 0; + uint32_t dll_counter = 0; + uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128); + + DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t); + dll_counter = rd_reg(p_ddr_base->ddr_phy_base_address + 0x3100); + dll_counter = (((dll_counter >> 1) & 0xff)); + bdlr_100step = (100000000 / (2 * DRAMFreq)) / (dll_counter + 1); + // printf("\nrdll_counter=%08x ", rd_reg(p_ddr_base->ddr_phy_base_address + 0x3100)); + return bdlr_100step; +} + +uint32_t ddr_get_ui_1_128_100step(void) +{ + uint32_t DRAMFreq = 0; + uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128); + + DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t); + return (1000000 * 100 / (2 * 128)) / ((DRAMFreq)); +} + +uint32_t do_read_c2_ddr_bdlr_steps(void) +{ + uint32_t DRAMFreq = 0; + + DRAMFreq = get_ddr_clk(); + printf("\nc2_chip_DRAMFreq=%d MHz,100min_bdlr=%d ps,100max_bdlr=%d ps,ave_100_bdlr=%d ps,bdlr_var=%d thousand,cur_100_bdlr=%d ps\n", + DRAMFreq, ddr_get_c2_bdlr_100step_min(), ddr_get_c2_bdlr_100step_max(), ddr_get_c2_bdlr_100step(), + 2000 * (ddr_get_c2_bdlr_100step_max() - ddr_get_c2_bdlr_100step_min()) / (ddr_get_c2_bdlr_100step_max() + ddr_get_c2_bdlr_100step_min()), ddr_get_c2_bdlr_100step_cur()); + + return ddr_get_c2_bdlr_100step(); +} + +int do_read_c2_ddr_training_data(char log_level, ddr_set_t_c2 *ddr_set_t_p) +{ + uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128); + uint32_t stick_store_sticky_f1_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x1128); + + printf_log(log_level, "\nddr_set_t_p==0x%08x\n", (uint32_t)(uint64_t)(ddr_set_t_p)); + uint32_t loop = 0; + uint32_t loop_max = (4 + (0x3f << 2)); //((DMC_STICKY_63-DMC_STICKY_0)); + for (loop = 0; loop < loop_max; loop += 4) + wr_reg(((uint64_t)(ddr_set_t_p) + loop), rd_reg((p_ddr_base->ddr_dmc_sticky0) + loop)); + loop_max = sizeof(board_SI_setting_ps_t); + for (loop = 0; loop < loop_max; loop += 4) + wr_reg(((uint64_t)(&(ddr_set_t_p->cfg_board_SI_setting_ps[0])) + loop), rd_reg((stick_store_sticky_f0_reg_base_t + loop))); + for (loop = 0; loop < loop_max; loop += 4) + wr_reg(((uint64_t)(&(ddr_set_t_p->cfg_board_SI_setting_ps[1])) + loop), rd_reg((stick_store_sticky_f1_reg_base_t + loop))); + for (loop = 0; loop < MESON_CPU_CHIP_ID_SIZE; loop++) //update chip id + + ddr_sha_c2.sha_chip_id[loop] = global_chip_id[loop]; + { + bdlr_100step = get_bdlr_100step(global_ddr_clk); + ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32)); + ddr_read_write_training_all_delay_value(ddr_set_t_p, REGISTER_READ, ~log_level); + } + return 1; +} + +int do_ddr_display_c2_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int i = 0; + unsigned int ps = 0; + + printf("\nargc== 0x%08x\n", argc); + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); + + do_read_c2_ddr_training_data(0, ddr_set_t_p); + + { + uint32_t count = 0; + uint32_t reg_add_offset = 0; + + printf("\n PCTL timming: 0x"); + + for (count = 0; count < ((p_ddr_base->ddr_pctl_timing_end_address) - (p_ddr_base->ddr_pctl_timing_base_address)); ) { + reg_add_offset = ((p_ddr_base->ddr_pctl_timing_base_address) + (count)); + printf("\n reg_add_offset: %08x %08x %08x ", reg_add_offset, readl(reg_add_offset), reg_add_offset); + count = count + 4; + } + printf("\n mrs register: "); + printf("\n mrs register: base (0x54000<<1)+DDR_PHY_BASE,%08x byte offset\n", (0x54000 << 1) + (p_ddr_base->ddr_phy_base_address)); + + printf("\n sticky register: "); + { + uint32_t loop_max = 0; + loop_max = 64 << 2; //sizeof(ddr_set_t); + for (count = 0; count < loop_max; count += 4) + printf("\n reg_add_offset: %08x %08x %08x", count, rd_reg((uint64_t)((p_ddr_base->ddr_dmc_sticky0)) + count), (((p_ddr_base->ddr_dmc_sticky0)) + count)); + } + + { + uint32_t loop_max = 0; + loop_max = sizeof(ddr_set_t_c2); + uint32_t count = 0; + for (count = 0; count < loop_max; ) { + printf("\n%08x %08x", count, rd_reg((uint64_t)(ddr_set_t_p) + count)); + count = count + 4; + } + } + } + + printf("\n {"); + + uint32_t temp_count = 0; + { + printf("\n//old fast_boot[%d]=0x%08x,// %d", 0, ddr_set_t_p->cfg_board_common_setting.fast_boot[0], ddr_set_t_p->cfg_board_common_setting.fast_boot[0]); + ddr_set_t_p->cfg_board_common_setting.fast_boot[0] = 0xfd; //add for auto copy to code test + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.cfg_board_common_setting.fast_boot[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.fast_boot[temp_count], ddr_set_t_p->cfg_board_common_setting.fast_boot[temp_count]); + + printf("\n.cfg_board_common_setting.timming_magic=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_magic, ddr_set_t_p->cfg_board_common_setting.timming_magic); + printf("\n.cfg_board_common_setting.timming_max_valid_configs=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_max_valid_configs, ddr_set_t_p->cfg_board_common_setting.timming_max_valid_configs); + printf("\n.cfg_board_common_setting.timming_struct_version=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_struct_version, ddr_set_t_p->cfg_board_common_setting.timming_struct_version); + printf("\n.cfg_board_common_setting.timming_struct_org_size=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_struct_org_size, ddr_set_t_p->cfg_board_common_setting.timming_struct_org_size); + printf("\n.cfg_board_common_setting.timming_struct_real_size=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_struct_real_size, ddr_set_t_p->cfg_board_common_setting.timming_struct_real_size); + printf("\n.cfg_board_common_setting.ddr_func=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.ddr_func, ddr_set_t_p->cfg_board_common_setting.ddr_func); + printf("\n.cfg_board_common_setting.board_id=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.board_id, ddr_set_t_p->cfg_board_common_setting.board_id); + printf("\n.cfg_board_common_setting.DramType=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.DramType, ddr_set_t_p->cfg_board_common_setting.DramType); + printf("\n.cfg_board_common_setting.dram_rank_config=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_rank_config, ddr_set_t_p->cfg_board_common_setting.dram_rank_config); + printf("\n.cfg_board_common_setting.DisabledDbyte=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.DisabledDbyte, ddr_set_t_p->cfg_board_common_setting.DisabledDbyte); + printf("\n.cfg_board_common_setting.dram_cs0_base_add=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_cs0_base_add, ddr_set_t_p->cfg_board_common_setting.dram_cs0_base_add); + printf("\n.cfg_board_common_setting.dram_cs1_base_add=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_cs1_base_add, ddr_set_t_p->cfg_board_common_setting.dram_cs1_base_add); + printf("\n.cfg_board_common_setting.dram_cs0_size_MB=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_cs0_size_MB, ddr_set_t_p->cfg_board_common_setting.dram_cs0_size_MB); + printf("\n.cfg_board_common_setting.dram_cs1_size_MB=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_cs1_size_MB, ddr_set_t_p->cfg_board_common_setting.dram_cs1_size_MB); + printf("\n.cfg_board_common_setting.dram_x4x8x16_mode=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_x4x8x16_mode, ddr_set_t_p->cfg_board_common_setting.dram_x4x8x16_mode); + printf("\n.cfg_board_common_setting.Is2Ttiming=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.Is2Ttiming, ddr_set_t_p->cfg_board_common_setting.Is2Ttiming); + printf("\n.cfg_board_common_setting.log_level=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.log_level, ddr_set_t_p->cfg_board_common_setting.log_level); + printf("\n.cfg_board_common_setting.ddr_rdbi_wr_enable=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.ddr_rdbi_wr_enable, ddr_set_t_p->cfg_board_common_setting.ddr_rdbi_wr_enable); + printf("\n.cfg_board_common_setting.pll_ssc_mode=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.pll_ssc_mode, ddr_set_t_p->cfg_board_common_setting.pll_ssc_mode); + printf("\n.cfg_board_common_setting.org_tdqs2dq=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.org_tdqs2dq, ddr_set_t_p->cfg_board_common_setting.org_tdqs2dq); + for (temp_count = 0; temp_count < 2; temp_count++) + printf("\n.cfg_board_common_setting.reserve1_test_function[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.reserve1_test_function[temp_count], ddr_set_t_p->cfg_board_common_setting.reserve1_test_function[temp_count]); + for (temp_count = 0; temp_count < 5; temp_count++) + printf("\n.cfg_board_common_setting.ddr_dmc_remap[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.ddr_dmc_remap[temp_count], ddr_set_t_p->cfg_board_common_setting.ddr_dmc_remap[temp_count]); + for (temp_count = 0; temp_count < 35; temp_count++) + printf("\n.cfg_board_common_setting.ac_pinmux[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.ac_pinmux[temp_count], (uint32_t)ddr_set_t_p->cfg_board_common_setting.ac_pinmux[temp_count]); + printf("\n.cfg_board_common_setting.ddr_dqs_swap=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.ddr_dqs_swap, ddr_set_t_p->cfg_board_common_setting.ddr_dqs_swap); + for (temp_count = 0; temp_count < 36; temp_count++) + printf("\n.cfg_board_common_setting.ddr_dq_remap[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.ddr_dq_remap[temp_count], (uint32_t)ddr_set_t_p->cfg_board_common_setting.ddr_dq_remap[temp_count]); + for (temp_count = 0; temp_count < 4; temp_count++) + printf("\n.cfg_board_common_setting.ddr_vddee_setting[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.ddr_vddee_setting[temp_count], (uint32_t)ddr_set_t_p->cfg_board_common_setting.ddr_vddee_setting[temp_count]); + + + + + for (ps = 0; ps < 2; ps++) { + printf("\n.cfg_board_SI_setting_ps[%d].DRAMFreq=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].DRAMFreq, ddr_set_t_p->cfg_board_SI_setting_ps[ps].DRAMFreq); + printf("\n.cfg_board_SI_setting_ps[%d].PllBypassEn=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].PllBypassEn, ddr_set_t_p->cfg_board_SI_setting_ps[ps].PllBypassEn); + printf("\n.cfg_board_SI_setting_ps[%d].training_SequenceCtrl=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].training_SequenceCtrl, ddr_set_t_p->cfg_board_SI_setting_ps[ps].training_SequenceCtrl); + printf("\n.cfg_board_SI_setting_ps[%d].ddr_odt_config=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ddr_odt_config, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ddr_odt_config); + printf("\n.cfg_board_SI_setting_ps[%d].clk_drv_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].clk_drv_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].clk_drv_ohm); + printf("\n.cfg_board_SI_setting_ps[%d].cs_drv_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].cs_drv_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].cs_drv_ohm); + printf("\n.cfg_board_SI_setting_ps[%d].ac_drv_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ac_drv_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ac_drv_ohm); + printf("\n.cfg_board_SI_setting_ps[%d].soc_data_drv_ohm_p=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_drv_ohm_p, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_drv_ohm_p); + printf("\n.cfg_board_SI_setting_ps[%d].soc_data_drv_ohm_n=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_drv_ohm_n, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_drv_ohm_n); + printf("\n.cfg_board_SI_setting_ps[%d].soc_data_odt_ohm_p=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_odt_ohm_p, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_odt_ohm_p); + printf("\n.cfg_board_SI_setting_ps[%d].soc_data_odt_ohm_n=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_odt_ohm_n, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_odt_ohm_n); + printf("\n.cfg_board_SI_setting_ps[%d].dram_data_drv_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_drv_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_drv_ohm); + printf("\n.cfg_board_SI_setting_ps[%d].dram_data_odt_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_odt_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_odt_ohm); + printf("\n.cfg_board_SI_setting_ps[%d].dram_data_wr_odt_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_wr_odt_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_wr_odt_ohm); + printf("\n.cfg_board_SI_setting_ps[%d].dram_ac_odt_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_ac_odt_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_ac_odt_ohm); + printf("\n.cfg_board_SI_setting_ps[%d].dram_data_drv_pull_up_calibration_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_drv_pull_up_calibration_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_drv_pull_up_calibration_ohm); + printf("\n.cfg_board_SI_setting_ps[%d].lpddr4_dram_vout_voltage_range_setting=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].lpddr4_dram_vout_voltage_range_setting, ddr_set_t_p->cfg_board_SI_setting_ps[ps].lpddr4_dram_vout_voltage_range_setting); + printf("\n.cfg_board_SI_setting_ps[%d].reserve2=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].reserve2, ddr_set_t_p->cfg_board_SI_setting_ps[ps].reserve2); + printf("\n.cfg_board_SI_setting_ps[%d].vref_ac_permil =0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_ac_permil, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_ac_permil); + printf("\n.cfg_board_SI_setting_ps[%d].vref_soc_data_permil =0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_soc_data_permil, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_soc_data_permil); + printf("\n.cfg_board_SI_setting_ps[%d].vref_dram_data_permil=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_dram_data_permil, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_dram_data_permil); + printf("\n.cfg_board_SI_setting_ps[%d].max_core_timmming_frequency=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].max_core_timmming_frequency, ddr_set_t_p->cfg_board_SI_setting_ps[ps].max_core_timmming_frequency); + for (temp_count = 0; temp_count < 2; temp_count++) + printf("\n.cfg_board_SI_setting_ps[%d].training_phase_parameter[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_board_SI_setting_ps[ps].training_phase_parameter[temp_count], (uint32_t)ddr_set_t_p->cfg_board_SI_setting_ps[ps].training_phase_parameter[temp_count]); + for (temp_count = 0; temp_count < 36; temp_count++) + printf("\n.cfg_board_SI_setting_ps[%d].ac_trace_delay_org[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ac_trace_delay_org[temp_count], (uint32_t)ddr_set_t_p->cfg_board_SI_setting_ps[ps].ac_trace_delay_org[temp_count]); + + for (temp_count = 0; temp_count < 36; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].ac_trace_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count]); + for (temp_count = 0; temp_count < 8; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].write_dqs_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count]); + for (temp_count = 0; temp_count < 72; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].write_dq_bit_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count]); + for (temp_count = 0; temp_count < 8; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_gate_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count]); + for (temp_count = 0; temp_count < 8; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count]); + for (temp_count = 0; temp_count < 72; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].read_dq_bit_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count]); + for (temp_count = 0; temp_count < 44; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].soc_bit_vref[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count]); + for (temp_count = 0; temp_count < 36; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].dram_bit_vref[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count]); + for (temp_count = 0; temp_count < 16; temp_count++) + printf("\n.cfg_ddr_training_delay_ps[%d].reserve_training_parameter[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].reserve_training_parameter[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].reserve_training_parameter[temp_count]); + } + + + printf("\n},\n"); } return 1; } #ifdef USE_FOR_UBOOT_2018 #include <amlogic/storage.h> -extern struct storage_t *current; +extern struct storage_t *current; + static int ddr_do_store_ddr_parameter_ops(uint8_t *buffer, uint32_t length) { - //if (!current) { - // INIT_LIST_HEAD(&store_dev->list); - // current = store_dev; - // return 0; - //} - char str[1024]=""; - if (!current) - { - sprintf(str,"store init"); - run_command(str,0); + char str[1024] = ""; + + if (!current) { + sprintf(str, "store init"); + run_command(str, 0); } char *name = NULL; { - name ="ddr-parameter"; - printf("\nstore rsv write ddr-parameter 0x%08x 0x%08x\n",(uint32_t)(uint64_t)buffer,length); - //struct storage_t *store = current;//store_get_current(); - //return store->write_rsv(name, length, (u_char *)buffer); - sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x\n",(uint32_t)(uint64_t)buffer,length); - run_command(str,0); + name = "ddr-parameter"; + printf("\nstore rsv write ddr-parameter 0x%08x 0x%08x\n", (uint32_t)(uint64_t)buffer, length); + sprintf(str, "store rsv write ddr-parameter 0x%08x 0x%08x\n", (uint32_t)(uint64_t)buffer, length); + run_command(str, 0); } } - #else - static int ddr_do_store_ddr_parameter_ops(uint8_t *buffer, uint32_t length) { -#if 0 - unsigned long addr; - int ret = 0; - //char* ops = argv[2]; - const unsigned maxDdrPSz = 2 * 1024; - unsigned int actualDtbSz = 0; - actualDtbSz = maxDdrPSz; - if (argc > 4) { - const unsigned bufSz = simple_strtoull_ddr(argv[4], NULL, 0); - if (bufSz > maxDdrPSz) { - printf("fail bufSz (%s) > max 0x%x\n", argv[4], maxDdrPSz); - //return CMD_RET_FAILURE; - } - } - addr = (unsigned long)simple_strtoull_ddr(argv[3], NULL, 16); -#endif extern int store_ddr_parameter_write(uint8_t *buffer, uint32_t length); - //char str[1024]=""; - printf("\nstore ddr_parameter write 0x%08x 0x%08x\n",(uint32_t)(uint64_t)buffer,length); - //run_command(str,0); + printf("\nstore ddr_parameter write 0x%08x 0x%08x\n", (uint32_t)(uint64_t)buffer, length); store_ddr_parameter_write((uint8_t *)buffer, length); return 1; } #endif -#if 0 -int do_ddr_store_write_ddr_parameter_ops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - //do_store_ddr_parameter_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) - //unsigned int ddr_test_cmd=0; - unsigned int arg[30]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}; - //char *endp; - unsigned int i=0; - //ddr_test_cmd = simple_strtoull_ddr(argv[1], &endp, 0); - //for (i = 2;i<argc;i++) - // arg[i-2]=simple_strtoull_ddr(argv[i], &endp, 0); - //printf("\nddr_test_cmd== 0x%08x\n", ddr_test_cmd); - for (i = 0;i<(argc-0);i++) - printf("\narg[%08x]=%08x\n",i,arg[i]); - for (i = 0;i<(argc-0);i++) - printf("\nargv[%08x]=%s\n",i,argv[i]); - //int argc2_length; - //argc2_length=(argc-2); - //cmd_tbl_t *cmdtp2; - //int flag2; - int argc2; - char* argv2[30]; - argc2=5;//argc-1; - //for (i = 1;i<(argc);i++) - // argv2[i-1]=argv[i]; - - #ifdef USE_FOR_UBOOT_2018 - //sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,write_size); - argc2=6; - argv2[1]="rsv"; - argv2[2]="write"; - argv2[3]="ddr-parameter"; - argv2[4]=argv[1];//simple_strtoull_ddr(argv[1], &endp, 0); - argv2[5]=argv[2];//simple_strtoull_ddr(argv[1], &endp, 0); - do_store_rsv_ops(cmdtp,flag,argc2,argv2[]); - #else - //sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,write_size); - argc2=5; - argv2[1]="ddr_parameter"; - argv2[2]="write"; - argv2[3]=argv[1];// simple_strtoull_ddr(argv[1], &endp, 0); - argv2[4]=argv[2];//simple_strtoull_ddr(argv[1], &endp, 0); - //extern int do_store_ddr_parameter_ops(cmd_tbl_t * cmdtp, - // int flag, int argc, char * const argv[]); - ddr_do_store_ddr_parameter_ops(cmdtp,flag,argc2,argv2); - #endif - return 1; -} -U_BOOT_CMD( - ddr_store_write, 30, 1, do_ddr_store_write_ddr_parameter_ops, - "ddr_test_cmd cmd arg1 arg2 arg3...", - "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n" - ); -#endif -int do_ddr_fastboot_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_fastboot_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { check_base_address(); - int i=0; - int count=0; + int i = 0; + int count = 0; char *endp; - unsigned int enable_ddr_fast_boot=0; // 0 pause 1,resume + unsigned int enable_ddr_fast_boot = 0; // 0 pause 1,resume + char *out_sha2; printf("\nargc== 0x%08x\n", argc); - for (i = 0;i<argc;i++) - printf("\nargv[%d]=%s\n",i,argv[i]); - if (argc == 1) + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); + if (argc == 1) { printf("\nplease read help\n"); - else if (argc > 1) - { - count=0; - enable_ddr_fast_boot= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + } else if (argc > 1) { + count = 0; + enable_ddr_fast_boot = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) enable_ddr_fast_boot = 0; - } - // count++; } if (!enable_ddr_fast_boot) return 1; +#define DMC_PHY_RETRAINING_CTRL (p_ddr_base->ddr_dmc_lpdd4_retraining_address) + uint32_t dmc_retraining_ctrl = 0; + dmc_retraining_ctrl = rd_reg(DMC_PHY_RETRAINING_CTRL); - ddr_set_t *ddr_set_t_p=NULL; - ddr_set_t_p=(ddr_set_t *)(ddr_set_t_p_arrary); - uint32_t ddr_set_add=0; - uint32_t ddr_set_size=0; - ddr_set_add=(uint32_t)(uint64_t)(ddr_set_t_p); - ddr_set_size=sizeof(ddr_set_t); - uint32_t write_size=0; - write_size=((ddr_set_size+SHA256_SUM_LEN+MESON_CPU_CHIP_ID_SIZE+511)/512)*512; - do_read_ddr_training_data(1,ddr_set_t_p); - { - dwc_ddrphy_apb_wr(0xd0000,0x0); + if (DMC_PHY_RETRAINING_CTRL) + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl & (~(1 << 31))); + ddr_set_t *ddr_set_t_p = NULL; + ddr_set_t_p = (ddr_set_t *)(ddr_set_t_p_arrary); + uint32_t ddr_set_add = 0; + uint32_t ddr_set_size = 0; - char dmc_test_worst_window_rx=0; - char dmc_test_worst_window_tx=0; - { - dwc_ddrphy_apb_wr((0<<20)|(0xd<<16)|(0<<12)|(0x0),0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel + ddr_set_t_c2 *ddr_set_t_p_c2 = NULL; + ddr_set_t_p_c2 = (ddr_set_t_c2 *)(ddr_set_t_p_arrary_c2); - dmc_test_worst_window_tx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c2)); - dmc_test_worst_window_rx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c3)); - if (dmc_test_worst_window_tx>30) - dmc_test_worst_window_tx=30; - if (dmc_test_worst_window_rx>30) - dmc_test_worst_window_rx=30; -// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c2),t4_write_worst_margin_rank1); -// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c3),t4_read_worst_margin_rank1); - ddr_set_t_p->fast_boot[1]=(((dmc_test_worst_window_tx/2)<<4))|(((dmc_test_worst_window_rx/2))); - } + uint32_t write_size = 0; + + if ((p_ddr_base->chip_id >= MESON_CPU_MAJOR_ID_C2) && (p_ddr_base->chip_id <= MESON_CPU_MAJOR_ID_T5D)) { + ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p_c2); + ddr_set_size = sizeof(ddr_set_t_c2); + out_sha2 = (char *)ddr_sha_c2.sha2; + do_read_c2_ddr_training_data(1, ddr_set_t_p_c2); + + if (enable_ddr_fast_boot == 1) + ddr_set_t_p_c2->cfg_board_common_setting.fast_boot[0] = 0xff; + + if (enable_ddr_fast_boot == 2) + ddr_set_t_p_c2->cfg_board_common_setting.fast_boot[0] = 0; } + //do_read_ddr_training_data(1, ddr_set_t_p); + if ((p_ddr_base->chip_id >= MESON_CPU_MAJOR_ID_G12A) && (p_ddr_base->chip_id <= MESON_CPU_MAJOR_ID_SC2)) { + ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p); + ddr_set_size = sizeof(ddr_set_t); + out_sha2 = (char *)ddr_sha.sha2; + dwc_ddrphy_apb_wr(0xd0000, 0x0); + do_read_ddr_training_data(1, ddr_set_t_p); + char dmc_test_worst_window_rx = 0; + char dmc_test_worst_window_tx = 0; - //store ddr_parameter write 0x77f81cf0 0x300 - //printf("\n "); + { + dwc_ddrphy_apb_wr((0 << 20) | (0xd << 16) | (0 << 12) | (0x0), 0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel - if (enable_ddr_fast_boot == 1) - ddr_set_t_p->fast_boot[0]=0xff; + dmc_test_worst_window_tx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c2)); + dmc_test_worst_window_rx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c3)); + if (dmc_test_worst_window_tx > 30) + dmc_test_worst_window_tx = 30; + if (dmc_test_worst_window_rx > 30) + dmc_test_worst_window_rx = 30; + ddr_set_t_p->fast_boot[1] = (((dmc_test_worst_window_tx / 2) << 4)) | (((dmc_test_worst_window_rx / 2))); + } + if (enable_ddr_fast_boot == 1) + ddr_set_t_p->fast_boot[0] = 0xff; - if (enable_ddr_fast_boot == 2) - ddr_set_t_p->fast_boot[0]=0; + if (enable_ddr_fast_boot == 2) + ddr_set_t_p->fast_boot[0] = 0; + } + if (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7) { + ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p); + ddr_set_size = sizeof(ddr_set_t); + out_sha2 = (char *)ddr_sha.sha2; + dwc_ddrphy_apb_wr(0xd0000, 0x0); + do_read_ddr_training_data(1, ddr_set_t_p); + char dmc_test_worst_window_rx = 0; + char dmc_test_worst_window_tx = 0; + + { + dwc_ddrphy_apb_wr((0 << 20) | (0xd << 16) | (0 << 12) | (0x0), 0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel + + dmc_test_worst_window_tx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c2)); + dmc_test_worst_window_rx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c3)); + if (dmc_test_worst_window_tx > 30) + dmc_test_worst_window_tx = 30; + if (dmc_test_worst_window_rx > 30) + dmc_test_worst_window_rx = 30; + ddr_set_t_p->fast_boot[1] = (((dmc_test_worst_window_tx / 2) << 4)) | (((dmc_test_worst_window_rx / 2))); + } + if (enable_ddr_fast_boot == 1) + ddr_set_t_p->fast_boot[0] = 0xff; + + if (enable_ddr_fast_boot == 2) + ddr_set_t_p->fast_boot[0] = 0; + } + + write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512; { - #if 1 - printf("&ddr_sha.ddrs : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.ddrs); - printf("&ddr_sha.sha2 : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.sha2); - printf("ddr_set_add : 0x%x sizeof(ddr_set_t):0x%x\n ", (uint32_t)(uint64_t)ddr_set_add, (uint32_t)(uint64_t)sizeof(ddr_set_t)); - printf("ddr_set_add_chip_id : 0x%x\n", (uint32_t)(uint64_t)(ddr_set_add+ddr_set_size)); - sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0); - //sha2((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0); + //printf("&ddr_sha.ddrs : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.ddrs); + if(out_sha2) + printf("&ddr_sha.sha2 : 0x%x\n", (uint32_t)(uint64_t)out_sha2); + else + printf("out_sha2 is NULL"); + printf("ddr_set_add : 0x%x sizeof(ddr_set_t):0x%x\n ", (uint32_t)(uint64_t)ddr_set_add, (uint32_t)(uint64_t)ddr_set_size); + printf("ddr_set_add_chip_id : 0x%x\n", (uint32_t)(uint64_t)(ddr_set_add + ddr_set_size)); + sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, ddr_set_size,(unsigned char *) out_sha2, 0); printf("print sha\n"); - //sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(ddr_set_add-32)); - //run_command(str,0); - #endif - #if 0 - char str[1024]=""; - #ifdef USE_FOR_UBOOT_2018 - sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,write_size); - #else - sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,write_size); - #endif - // sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add,ddr_set_size); - // sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add,ddr_set_size); - printf("\nstr=%s\n",str); - run_command(str,0); - #endif - #if 0 - int argc2; - char* argv2[30]; - argc2=3; - - //for (i = 2;i<argc;i++) - // arg[i-2]=simple_strtoull_ddr(argv[i], &endp, 0); - //printf("\nddr_test_cmd== 0x%08x\n", ddr_test_cmd); - // sprintf(argv2[0],"ddr_store_write"); - sprintf(argv2[1],"0x%08x",ddr_set_add-SHA256_SUM_LEN); - sprintf(argv2[2],"0x%08x",write_size); - //sprintf(argv2[3],"0x%08x",0); - for (i = 0;i<(argc2-0);i++) - printf("\nargc2[%08x]=%s\n",i,argv2[i]); - for (i = 0;i<(argc2-0);i++) - printf("\ndebug\n"); - - do_ddr_store_write_ddr_parameter_ops(cmdtp,flag,argc2,argv2); - #endif - ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add-SHA256_SUM_LEN),write_size); + ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size); } - #if 0 - serial_puts("\n"); - for ( count=0;count<(sizeof(ddr_set_t));) { - //printf("\n%08x %08x",count,(rd_reg((uint64_t)(ddr_set_t_p)+(uint64_t)count))); - serial_puts("\n"); - serial_put_hex(count,32); - serial_puts(" "); - serial_put_hex(rd_reg((uint64_t)(p_dev->p_ddrs)+(uint64_t)count),32); - count=count+4; - } - serial_puts("\n"); - #endif return 1; } - #endif -int do_ddr_set_watchdog_value(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) + +int do_ddr_set_watchdog_value(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { char *endp; - int i=0; + int i = 0; + printf("\nargc== 0x%08x\n", argc); - for (i = 0;i<argc;i++) - printf("\nargv[%d]=%s\n",i,argv[i]); + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); - if (argc == 1) + if (argc == 1) { printf("\nplease read help\n"); - - else if (argc > 1) - { + } else if (argc > 1) { { watchdog_time_s = simple_strtoull_ddr(argv[1], &endp, 0); if (*argv[1] == 0 || *endp != 0) - watchdog_time_s= 20; + watchdog_time_s = 20; } - printf("watchdog_time_s==%d\n",watchdog_time_s); + printf("watchdog_time_s==%d\n", watchdog_time_s); } return 1; } - -//#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12) - #define G12_DATA_READ_OFFSET_MAX (0X3F) - #define G12_DATA_WRITE_OFFSET_MAX (0X3F+7*32) - - #define DMC_TEST_WINDOW_INDEX_ATXDLY 1 - #define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2 - #define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3 - #define DMC_TEST_WINDOW_INDEX_TXDQDLY 4 - #define DMC_TEST_WINDOW_INDEX_RXPBDLY 5 - #define DMC_TEST_WINDOW_INDEX_RXENDLY 6 - - #define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11 - #define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12 - #define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x13 - - typedef struct training_delay_information{ - uint16_t ac_delay[10]; - uint16_t txdqs_delay[16]; - uint16_t rxdqs_delay[16]; - uint16_t txdq_delay[72]; - uint16_t rxdq_delay[72]; - uint16_t gate_rxdq_delay[72]; - - } training_delay_t; - training_delay_t training_delay_t_p; - - uint16_t lcd_bdl_value[72][4]; //org min max status - // #define LCD_BDLR_ORG 0 - #define LCD_BDLR_MIN 0 - #define LCD_BDLR_MAX 1 - #define LCD_BDLR_STATUS 2 - - //BYTE0-3 - #define TEST_ARG_0_DMC_STICKY_MAGIC 0 - #define TEST_ARG_1_CMD0 1 - #define TEST_ARG_2_STEP 2 // 0 init 1 test ac 2 test tdqs_write - #define TEST_ARG_3_ALL_TOGHTER 3 - - //BYTE4-7 - #define TEST_ARG_FREQ_NIBBLE_L 4 - #define TEST_ARG_FREQ_NIBBLE_H 5 - - //BYTE8-11 - #define TEST_ARG_BOOT_TIMES_L 6 - #define TEST_ARG_BOOT_TIMES_H 7 - - //BYTE12-15 - #define TEST_ARG_ERROR_FLAG 8 //take 4 byte for kernel test flag - //#define TEST_ARG_ERROR_FLAG 63*4 //take 4 byte for kernel test flag - - //BYTE16-19 - //#define TEST_ARG_16_LCDLR_TEMP_COUNT 16 - #define TEST_ARG_CS0_TEST_START_INDEX 12 - #define TEST_ARG_CS0_TEST_SIZE_INDEX 16 - #define TEST_ARG_CS1_TEST_START_INDEX 20 - #define TEST_ARG_CS1_TEST_SIZE_INDEX 24 - - #define TEST_ARG_WATCHDOG_TIME_SIZE_INDEX 28 - #define TEST_ARG_TEST_INDEX_ENALBE_INDEX 30 - //#define TEST_ARG_NIBBLE_MASK0_ENALBE_INDEX 32 - - #define TEST_ARG_ERROR_FLAG_NULL 0 - #define TEST_ARG_ERROR_FLAG_FAIL 1 - #define TEST_ARG_ERROR_FLAG_PASS 2 - - #define TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE 32 // 32BYTE - #define TEST_ARG_NIBBLE_WIDTH_BYTE 3 //3///BYTE - -int do_ddr_test_dqs_window_sticky(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("\nEnterddr_test_dqs_window function ddr_test_cmd 0x27 0x1080000 0x800000 0x40000000 0x800000 15 0x6 0 0 0 0 0 0 1/config\n"); - printf("\nddr_test_cmd 0x27 cs0_test_start cs0_test_size cs1_test_start cs1_test_size ns test_index_enable nibble_mask0 nibble_mask1 nibble_mask2 dram_type channel_mode config_register all_togther--- watchdog should >15s\n"); - printf("\n ac write_dqs read_dqs can test togther test_index_enable can enable kernel test \n"); - // unsigned int channel_b_en = 0; - // unsigned int reg_add=0; - // unsigned int reg_base_adj=0; - #define DDR_CORSS_TALK_TEST_SIZE 0x20000 - unsigned int temp_test_error=0; - unsigned int nibble_save_offset= 0; - unsigned int nibble_step= 0; - unsigned int nibble_max= 16; - unsigned int test_index_enable= 0; - unsigned int test_index= 0; - unsigned int test_index_max= 6; - unsigned int reg_value= 0; - unsigned int dram_type= 0; - unsigned int channel_mode= 0; - unsigned int kernel_watchdog_s= 20;//240; - // unsigned int finish_clear_flag= 0; - unsigned int config_register= 0; - unsigned int all_toghter_enable=0; - unsigned int error_flag_reg_add=0; - char *string_print_flag= " uboot-window-loop \n"; - //int argc2; - //char * argv2[30]; - char *endp; - char *buf; - buf=""; - - unsigned int cs0_test_start= 0x1080000; - unsigned int cs0_test_size= DDR_CORSS_TALK_TEST_SIZE; - unsigned int cs1_test_start= 0; - unsigned int cs1_test_size= 0; - unsigned int enable_kernel_test=0; - if (argc >1) { - cs0_test_start = simple_strtoull_ddr(argv[1], &endp, 16); - if (*argv[1] == 0 || *endp != 0) - { - cs0_test_start = 0x1080000; - } - } - - if (argc >2) { - cs0_test_size = simple_strtoull_ddr(argv[2], &endp, 16); - if (*argv[2] == 0 || *endp != 0) - { - cs0_test_size = DDR_CORSS_TALK_TEST_SIZE; - } - } - - if (argc >3) { - cs1_test_start = simple_strtoull_ddr(argv[3], &endp, 16); - if (*argv[3] == 0 || *endp != 0) - { - cs1_test_start = 0; - } - } - if (argc >4) { - cs1_test_size = simple_strtoull_ddr(argv[4], &endp, 16); - if (*argv[4] == 0 || *endp != 0) - { - cs1_test_size = 0; - } - } - - unsigned int ddr_test_size= DDR_CORSS_TALK_TEST_SIZE; - ddr_test_size = cs0_test_size; - if (argc >5) { - watchdog_time_s = simple_strtoull_ddr(argv[5], &endp, 0); - if (*argv[5] == 0 || *endp != 0) - { - watchdog_time_s= 20; - } - } - printf("watchdog_time_s==%d\n",watchdog_time_s); - - if (argc >6) { - test_index_enable = simple_strtoull_ddr(argv[6], &endp, 0); - if (*argv[5] == 0 || *endp != 0) - { - test_index_enable= 0; - } - } - printf("test_index_enable==0x%08x\n",test_index_enable); - enable_kernel_test=(test_index_enable>>7)&1; - if (enable_kernel_test) { - printf("enable kernel window test\n"); - } - - unsigned int nibble_mask[3]= {0,0,0}; - if (argc >7) { - nibble_mask[0] = simple_strtoull_ddr(argv[7], &endp, 0); - if (*argv[7] == 0 || *endp != 0) - { - nibble_mask[0]= 0; - } - } - printf("nibble_mask[0]==0x%08x\n",nibble_mask[0]); - if (argc >8) { - nibble_mask[1] = simple_strtoull_ddr(argv[8], &endp, 0); - if (*argv[8] == 0 || *endp != 0) - { - nibble_mask[1]= 0; - } - } - printf("nibble_mask[1]==0x%08x\n",nibble_mask[1]); - if (argc >9) { - nibble_mask[2] = simple_strtoull_ddr(argv[9], &endp, 0); - if (*argv[9] == 0 || *endp != 0) - { - nibble_mask[2]= 0; - } - } - printf("nibble_mask[2]==0x%08x\n",nibble_mask[2]); - - if (argc >10) { - dram_type = simple_strtoull_ddr(argv[10], &endp, 0); - if (*argv[10] == 0 || *endp != 0) - { - dram_type= 0; - } - } - if (argc >11) { - channel_mode = simple_strtoull_ddr(argv[11], &endp, 0); - if (*argv[11] == 0 || *endp != 0) - { - channel_mode= 0; - } - } - ///* - if (argc >12) { - config_register = simple_strtoull_ddr(argv[12], &endp, 0); - if (*argv[12] == 0 || *endp != 0) - { - config_register= 0; - } - }//*/ - ///* - if (argc >13) { - all_toghter_enable = simple_strtoull_ddr(argv[13], &endp, 0); - if (*argv[13] == 0 || *endp != 0) - { - all_toghter_enable= 0; - } - }//*/ - printf("all_toghter_enable==0x%08x\n",all_toghter_enable); - - if (argc >14) { - error_flag_reg_add = simple_strtoull_ddr(argv[14], &endp, 0); - if (*argv[14] == 0 || *endp != 0) - { - error_flag_reg_add= 0; - } - } - printf("error_flag_reg_add==0x%08x\n",error_flag_reg_add); - printf("\ntest use uboot sticky register\n"); - - //DMC_STICKY_0 - char str[1024]=""; - //char str_temp1[1024]=""; - //char str_temp2[1024]=""; - volatile uint16_t *num_arry=NULL; - //volatile uint16_t *p_num_arry; - int i; - //unsigned int stick_base_add=0; - //uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value) - - sticky_reg_base_add=(((p_ddr_base->ddr_dmc_sticky0))&0xffff); - //num_arry = (uint16_t *)(uint64_t )(sticky_reg_base_add); - //num_arry=p_num_arry; - for (i = 0; i < 64*4; i++) { - num_arry[i]=ddr_rd_8_16bit_on_32reg(sticky_reg_base_add,8,i); - if ((i == 0) || (i == 32) || (i == (32+10*3)) || (i == (32+10*3+16*3)) || (i == (32+10*3+16*3+16*3))) - { - printf("\n numarry[%d]" ,i); - } - printf(" %d ",num_arry[i]); - } - - /* - #define TEST_ARG_1_CMD0 1 - //#define TEST_ARG_1_CMD1 1 - #define TEST_ARG_2_STEP 2 - #define TEST_ARG_3_FREQ 3 - #define TEST_ARG_4_STEP_STATUS 4 - #define TEST_ARG_5_BOOT_TIMES 5 - #define TEST_ARG_6_LCDLR_TEMP_COUNT 6 - #define TEST_ARG_7_DMC_STICKY_MAGIC 7 - */ - - uint16_t test_left_max_init_value =32; - uint16_t test_right_max_init_value =32; - uint16_t test_boot_times =0; - uint16_t test_ddr_frequency =0; - //uint16_t temp_sub_value_a =0; - /* - uint16_t test_arg_1_cmd0 =1; //master cmd - uint16_t test_arg_1_cmd1 =0; //min cmd - uint16_t test_arg_2_step =0; //step 0 init -1 lane0 w min -2 lane0 w max -3 lane0 r min 4 lane0 r max -----5 lane1 w min ... - uint16_t test_arg_3_freq =0; - uint16_t test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass - test_arg_0_cmd0=num_arry[0]; - test_arg_1_cmd1=num_arry[1]; - test_arg_2_step=num_arry[2]; - test_arg_3_freq=num_arry[3]; - test_arg_4_step_status=num_arry[4]; - //boot_times=num_arry[5]; - //lcdlr_temp_count=num_arry[6]; - */ - printf("\nTEST_ARG_0_DMC_STICKY_MAGIC==0x%08x\n",num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]); - printf("\nTEST_ARG_1_CMD0==0x%08x\n",num_arry[TEST_ARG_1_CMD0]); - printf("TEST_ARG_2_STEP==0x%08x\n",num_arry[TEST_ARG_2_STEP]); - printf("TEST_ARG_3_ALL_TOGHTER==0x%08x\n",num_arry[TEST_ARG_3_ALL_TOGHTER]); - printf("TEST_ARG_FREQ_NIBBLE_L==0x%08x\n",num_arry[TEST_ARG_FREQ_NIBBLE_L]); - printf("TEST_ARG_FREQ_NIBBLE_H==0x%08x\n",num_arry[TEST_ARG_FREQ_NIBBLE_H]); - printf("TEST_ARG_BOOT_TIMES_L==0x%08x\n",num_arry[TEST_ARG_BOOT_TIMES_L]); - printf("TEST_ARG_BOOT_TIMES_H==0x%08x\n",num_arry[TEST_ARG_BOOT_TIMES_H]); - printf("TEST_ARG_ERROR_FLAG==0x%08x\n",num_arry[TEST_ARG_ERROR_FLAG]); - - printf("TEST_ARG_FREQ==%dM\n",(num_arry[TEST_ARG_FREQ_NIBBLE_H]<<8)|(num_arry[TEST_ARG_FREQ_NIBBLE_L]<<0)); - printf("TEST_ARG_BOOT_TIMES==%d\n",(num_arry[TEST_ARG_BOOT_TIMES_H]<<8)|(num_arry[TEST_ARG_BOOT_TIMES_L]<<0)); - test_boot_times=(num_arry[TEST_ARG_BOOT_TIMES_H]<<8)|(num_arry[TEST_ARG_BOOT_TIMES_L]<<0); - test_ddr_frequency=(num_arry[TEST_ARG_FREQ_NIBBLE_H]<<8)|(num_arry[TEST_ARG_FREQ_NIBBLE_L]<<0); - if ((num_arry[TEST_ARG_0_DMC_STICKY_MAGIC] == (DMC_STICKY_UBOOT_WINDOW_MAGIC_1&0xff)) && - (num_arry[TEST_ARG_1_CMD0]==(DMC_STICKY_UBOOT_WINDOW_MAGIC_1&0xff)) ) //for check magic number make sume enter test command - { - //num_arry[TEST_ARG_5_BOOT_TIMES]++; - test_boot_times++; - num_arry[TEST_ARG_BOOT_TIMES_L]=test_boot_times&0xff; - num_arry[TEST_ARG_BOOT_TIMES_H]=(test_boot_times>>8)&0xff; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_L,num_arry[TEST_ARG_BOOT_TIMES_L]); - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_H,num_arry[TEST_ARG_BOOT_TIMES_H]); - - if ( test_ddr_frequency != global_ddr_clk) // - { - printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_ddr_frequency); - sprintf(str,"d2pll %d",test_ddr_frequency); - printf("\nstr=%s\n",str); - run_command(str,0); - while (1) ; - } - } - else - { - test_boot_times=0; - num_arry[TEST_ARG_BOOT_TIMES_L]=test_boot_times&0xff; - num_arry[TEST_ARG_BOOT_TIMES_H]=(test_boot_times>>8)&0xff; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_L,num_arry[TEST_ARG_BOOT_TIMES_L]); - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_H,num_arry[TEST_ARG_BOOT_TIMES_H]); - num_arry[TEST_ARG_2_STEP]=0; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP,num_arry[TEST_ARG_2_STEP]); - } - printf("test_sticky is not magic nummber,boot times==%d\n",test_boot_times); - - //if(config_register==1) - { - wr_reg((sticky_reg_base_add+TEST_ARG_CS0_TEST_START_INDEX), cs0_test_start); - wr_reg((sticky_reg_base_add+TEST_ARG_CS0_TEST_SIZE_INDEX), cs0_test_size); - wr_reg((sticky_reg_base_add+TEST_ARG_CS1_TEST_START_INDEX), cs1_test_start); - wr_reg((sticky_reg_base_add+TEST_ARG_CS1_TEST_SIZE_INDEX), cs1_test_size); - { - num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX]=watchdog_time_s&0xff; - num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX+1]=(watchdog_time_s>>8)&0xff; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_WATCHDOG_TIME_SIZE_INDEX,num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX]); - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,(TEST_ARG_WATCHDOG_TIME_SIZE_INDEX+1),num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX+1]); - } - num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]=test_index_enable; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_TEST_INDEX_ENALBE_INDEX,num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]); - if (config_register == 1) - { - num_arry[TEST_ARG_2_STEP]=0; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP,num_arry[TEST_ARG_2_STEP]); - } - num_arry[TEST_ARG_3_ALL_TOGHTER]=all_toghter_enable; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_3_ALL_TOGHTER,num_arry[TEST_ARG_3_ALL_TOGHTER]); - } - - if (( num_arry[TEST_ARG_2_STEP]) == 0) - { - { - num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]=DMC_STICKY_UBOOT_WINDOW_MAGIC_1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_0_DMC_STICKY_MAGIC,num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]); - num_arry[TEST_ARG_1_CMD0]=DMC_STICKY_UBOOT_WINDOW_MAGIC_1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_1_CMD0,num_arry[TEST_ARG_1_CMD0]); - num_arry[TEST_ARG_2_STEP]=1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP,num_arry[TEST_ARG_2_STEP]); - { - test_boot_times=0; - num_arry[TEST_ARG_BOOT_TIMES_L]=test_boot_times&0xff; - num_arry[TEST_ARG_BOOT_TIMES_H]=(test_boot_times>>8)&0xff; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_L,num_arry[TEST_ARG_BOOT_TIMES_L]); - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_H,num_arry[TEST_ARG_BOOT_TIMES_H]); - } - { - test_ddr_frequency=global_ddr_clk; - num_arry[TEST_ARG_FREQ_NIBBLE_L]=test_ddr_frequency&0xff; - num_arry[TEST_ARG_FREQ_NIBBLE_H]=(test_ddr_frequency>>8)&0xff; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_FREQ_NIBBLE_L,num_arry[TEST_ARG_FREQ_NIBBLE_L]); - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_FREQ_NIBBLE_H,num_arry[TEST_ARG_FREQ_NIBBLE_H]); - } - - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_NULL; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_ERROR_FLAG,num_arry[TEST_ARG_ERROR_FLAG]); - } - - - for (nibble_step = 0; nibble_step < 72; nibble_step++) - { - //if(lane_step%2) - { - //num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_ORG]=0xffff; - test_left_max_init_value=16; - test_right_max_init_value=16; - if (nibble_step<10) - { - test_left_max_init_value=32; - test_right_max_init_value=32; - } - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN]=test_left_max_init_value; - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX]=test_right_max_init_value; - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS]=0;//0 - //ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,i,num_arry[i]); - } - - { - if (nibble_step<32) - { - if (((nibble_mask[0])>>nibble_step)&1) - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4; - } - else if (nibble_step<64) - { - if (((nibble_mask[1])>>(nibble_step-32))&1) - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4; - } - else if (nibble_step<96) - { - if (((nibble_mask[2])>>(nibble_step-64))&1) - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4; - } - if (all_toghter_enable) - { - if ((nibble_step == 0) || (nibble_step == 10) || (nibble_step == (10+16))) - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=0; - else - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4; - } - } - //num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS]=0xffff;//0 - } - - { - //printf("..num_arry[TEST_ARG_1_CMD0]=%d\n",num_arry[TEST_ARG_1_CMD0]); - for (i = TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE; i < 72*TEST_ARG_NIBBLE_WIDTH_BYTE; i++) { - // num_arry[i]=0; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,i,num_arry[i]); - // ddr_wr_16bit_on_32reg((sticky_reg_base_add+(i<<1)),num_arry[i]); - // printf("num_arry[0x%08x] ==0x%08x\n",i,num_arry[i]); - } - - num_arry[TEST_ARG_2_STEP]=1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); - } - - } - - if (all_toghter_enable) - { - for (nibble_step = 0; nibble_step < 72; nibble_step++) - { - if ((nibble_step == 0) || (nibble_step == 10) || (nibble_step == (10+16))) - { - // num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=0; - } - else - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4; - } - } - - if (config_register == 1) - { - num_arry[TEST_ARG_2_STEP]=0; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); - } - -if (( num_arry[TEST_ARG_2_STEP])) -{ -for (test_index=num_arry[TEST_ARG_2_STEP];test_index<test_index_max ;test_index++ ) -{ - printf("\ntest_index=%d\n",test_index); - if ((((test_index_enable)>>(test_index-1))&1) == 0) - { - num_arry[TEST_ARG_2_STEP]=((num_arry[TEST_ARG_2_STEP])+1);//why can not use ++ - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); - continue; - } - { - if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) - { - nibble_save_offset=0; - nibble_max=10; - nibble_mask[0]= 0x30; - if ((dram_type == CONFIG_DDR_TYPE_LPDDR3)) - { - nibble_mask[0]= 0x3e3; - } - if ((dram_type == CONFIG_DDR_TYPE_LPDDR4)) - { - nibble_mask[0]= 0x273; - if ((channel_mode == CONFIG_DDR0_32BIT_RANK01_CH0)) - nibble_mask[0]= 0x3f3; - } - test_left_max_init_value=64; - test_right_max_init_value=64; - } - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) - { - nibble_save_offset=10; - nibble_max=16; - if ((cs1_test_size == 0)) - { - nibble_mask[0]= 0xff00; - } - test_left_max_init_value=16; - test_right_max_init_value=16; - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) - { - nibble_save_offset=(10)+(16); - if ((cs1_test_size == 0)) - { - nibble_mask[0]= 0xff00; - } - nibble_max=16; - test_left_max_init_value=16; - test_right_max_init_value=16; - } - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) - { - nibble_save_offset=0; - nibble_max=72; - if ((cs1_test_size == 0)) - { - nibble_mask[1]= 0xfffffff0; - nibble_mask[2]= 0xffffffff; - } - test_left_max_init_value=16; - test_right_max_init_value=16; - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) - { - nibble_save_offset=0; - nibble_max=72; - if ((cs1_test_size == 0)) - { - nibble_mask[1]= 0xfffffff0; - nibble_mask[2]= 0xffffffff; - } - - test_left_max_init_value=64; - test_right_max_init_value=64;} - //nibble_max=8;// - // if(nibble_max>30) can not over sticky register size - // nibble_max=30; - for ((nibble_step=0);(nibble_step<nibble_max);(nibble_step++)) - { - if (nibble_step<32) - { - if (((nibble_mask[0])>>nibble_step)&1) - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4; - } - else if (nibble_step<64) - { - if (((nibble_mask[1])>>(nibble_step-32))&1) - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4; - } - else if (nibble_step<96) - { - if (((nibble_mask[2])>>(nibble_step-64))&1) - num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4; - } - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - } - } - -{ - for ((nibble_step=0);(nibble_step<nibble_max);(nibble_step++)) - { - if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 4) - continue; - printf("nibble_step ==%d\n",nibble_step); - - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) - { - if (nibble_step%2) - { - //nibble_save_offset - //num_arry[TEST_ARG_2_STEP]=1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]); - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]); - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - //nibble_step++; - continue; - } - } - test_start_addr=cs0_test_start; - ddr_test_size=cs0_test_size; - if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) - { - test_start_addr=cs0_test_start; - ddr_test_size=cs0_test_size; - } - - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) - { - if (nibble_step>7) - { - test_start_addr=cs1_test_start; - ddr_test_size=cs1_test_size; - } - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) - { - if (nibble_step>7) - { - test_start_addr=cs1_test_start; - ddr_test_size=cs1_test_size; - } - } - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) - { - if (nibble_step>35) - { - test_start_addr=cs1_test_start; - ddr_test_size=cs1_test_size; - } - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) - { - if (nibble_step>35) - { - test_start_addr=cs1_test_start; - ddr_test_size=cs1_test_size; - } - } - { - if (nibble_step<32) - { - nibble_mask[0]=((0xffffffff)&(~(1<<nibble_step))); - nibble_mask[1]=((0xffffffff)); - nibble_mask[2]=((0xffffffff)); - } - else if (nibble_step<64) - { - nibble_mask[0]=((0xffffffff)); - nibble_mask[1]=((0xffffffff)&(~(1<<(nibble_step-32)))); - nibble_mask[2]=((0xffffffff)); - } - else if (nibble_step<96) - { - nibble_mask[0]=((0xffffffff)); - nibble_mask[1]=((0xffffffff)); - nibble_mask[2]=((0xffffffff)&(~(1<<(nibble_step-64)))); - } - } - if (all_toghter_enable) - { - if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) - { - nibble_save_offset=0; - nibble_max=10; - nibble_mask[0]= 0x30; - nibble_mask[1]= 0; - nibble_mask[2]= 0; - if ((dram_type == CONFIG_DDR_TYPE_LPDDR3)) - { - nibble_mask[0]= 0x3e3; - } - if ((dram_type == CONFIG_DDR_TYPE_LPDDR4)) - { - nibble_mask[0]= 0x273; - if ((channel_mode == CONFIG_DDR0_32BIT_RANK01_CH0)) - nibble_mask[0]= 0x3f3; - } - } - else - { - nibble_mask[0]= 0; - nibble_mask[1]= 0; - nibble_mask[2]= 0; - } - } - - ddr_test_watchdog_enable(watchdog_time_s); //s - printf("\nenable %ds watchdog \n",watchdog_time_s); - if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 0xffff) - ||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==0) - ||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==1) ) - { - printf("\nnibble_step ==%d ", nibble_step); - if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 0xffff) - ||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==0)) - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - - if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)] == 0) - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - run_command("reset",0); - } - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]= - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]-1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]); - } - - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - } - - //if(all_toghter_enable) - // sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,0,0,0,DDR_PARAMETER_LEFT, - // num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]); - //else - sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_LEFT, - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]); - printf("\nstr=%s\n",str); - ddr_test_watchdog_clear(); - run_command(str,0); - - temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size); - if (all_toghter_enable && cs1_test_size) - { - test_start_addr=cs1_test_start; - ddr_test_size=cs1_test_size; - temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - test_start_addr=cs0_test_start; - ddr_test_size=cs0_test_size; - //temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - } - if (temp_test_error) - { - run_command("reset",0); - } - else - { - // - if (!enable_kernel_test) - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - run_command("reset",0); - } - else - { - ddr_test_watchdog_enable(kernel_watchdog_s); //s - printf("\nenable %ds watchdog \n",kernel_watchdog_s); - run_command("run storeboot",0); - } - /* - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - run_command("reset",0); - */ - } - } - else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==1) - {//go on find left edge - - if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)] == 0) - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - run_command("reset",0); - } - - if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS) - { - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - } - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_NULL; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - } - run_command("reset",0); - } - if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL) - { - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]= - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]-1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]); - } - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - } - sprintf(buf, "0x%08x", ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)])); - printf( "%s", buf); - // if(all_toghter_enable) - // sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,0,0,0,DDR_PARAMETER_LEFT, - // ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)])); - // else - sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_LEFT, - ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)])); - printf("\nstr=%s\n",str); - ddr_test_watchdog_clear(); - run_command(str,0); - temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size); - if (all_toghter_enable && cs1_test_size) - { - test_start_addr=cs1_test_start; - ddr_test_size=cs1_test_size; - temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - test_start_addr=cs0_test_start; - ddr_test_size=cs0_test_size; - //temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - } - if (temp_test_error) - { - run_command("reset",0); - } - else - { - // - if (!enable_kernel_test) - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - run_command("reset",0); - } - else - { - ddr_test_watchdog_enable(kernel_watchdog_s); //s - printf("\nenable %ds watchdog \n",kernel_watchdog_s); - run_command("run storeboot",0); - } - /* - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - run_command("reset",0); - */ - } - } - } - // run_command("reset",0); - } - - if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 2) || - (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==3)) - { - printf("\nnibble_step ==%d ", nibble_step); - if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 2) - ||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==2)) - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=3; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - - if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)] == 0) - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - run_command("reset",0); - } - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]= - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]-1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]); - } - - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - } - // if(all_toghter_enable) - // sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,0,0,0,DDR_PARAMETER_RIGHT, - // num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]); - // else - sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_RIGHT, - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]); - printf("\nstr=%s\n",str); - ddr_test_watchdog_clear(); - run_command(str,0); - temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size); - if (all_toghter_enable && cs1_test_size) - { - test_start_addr=cs1_test_start; - ddr_test_size=cs1_test_size; - temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - test_start_addr=cs0_test_start; - ddr_test_size=cs0_test_size; - //temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - } - // temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - // temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - if (temp_test_error) - { - run_command("reset",0); - } - else - { - // - if (!enable_kernel_test) - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - run_command("reset",0); - } - else - { - ddr_test_watchdog_enable(kernel_watchdog_s); //s - printf("\nenable %ds watchdog \n",kernel_watchdog_s); - run_command("run storeboot",0); - } - /* - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - run_command("reset",0); - */ - } - } - else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==3) - {//go on find left edge - if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)] == 0) - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - run_command("reset",0); - } - - if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS) - { - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - } - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_NULL; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - } - run_command("reset",0); - } - if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL) - { - { - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]= - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]-1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]); - } - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - } - sprintf(buf, "0x%08x", ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)])); - printf( "%s", buf); - // if(all_toghter_enable) - // sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,0,0,0,DDR_PARAMETER_RIGHT, - // ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)])); - // else - sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_RIGHT, - ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)])); - printf("\nstr=%s\n",str); - ddr_test_watchdog_clear(); - run_command(str,0); - temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size); - if (all_toghter_enable && cs1_test_size) - { - test_start_addr=cs1_test_start; - ddr_test_size=cs1_test_size; - temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - test_start_addr=cs0_test_start; - ddr_test_size=cs0_test_size; - //temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - } - //temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - //temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size); - if (temp_test_error) - { - run_command("reset",0); - } - else - { - if (!enable_kernel_test) - { - num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - TEST_ARG_ERROR_FLAG, - num_arry[TEST_ARG_ERROR_FLAG]); - run_command("reset",0); - } - else - { - ddr_test_watchdog_enable(kernel_watchdog_s); //s - printf("\nenable %ds watchdog \n",kernel_watchdog_s); - run_command("run storeboot",0); - } - - /* - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8, - (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS), - num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]); - run_command("reset",0); - */ - } - } - } - // run_command("reset",0); - } - - ddr_test_watchdog_disable(); //s - { - printf("close watchdog\n"); - } - } - - printf("11num_arry[TEST_ARG_2_STEP]==%d\n",num_arry[TEST_ARG_2_STEP]); - num_arry[TEST_ARG_2_STEP]=(num_arry[TEST_ARG_2_STEP])+1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); - printf("22num_arry[TEST_ARG_2_STEP]==%d\n",num_arry[TEST_ARG_2_STEP]); - //} - - ddr_test_watchdog_disable(); //s - printf("close watchdog\n"); - //} - //for(test_index=1;test_index<test_index_max ;test_index++ ) - { - unsigned int ui_1_32_100step= 0; - unsigned int bdlr_100step= 0; - ui_1_32_100step=(1000000*100/(global_ddr_clk*2*32)); - bdlr_100step=get_bdlr_100step(global_ddr_clk); - //if((((test_index_enable)>>(test_index-1))&1)==0) - - printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,bdlr_100step=%d ps,ui_1_32_100step=%d ps,\n",0,0,global_ddr_clk, - bdlr_100step,ui_1_32_100step); - - printf("\n test result index=="); - printf("%08d",test_index); - - if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { - printf(" ac window:"); - printf(" step_size ps=="); - printf("%08d",ui_1_32_100step); - printf("/100 ps "); - } - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { - printf(" txdqs window:"); - printf(" step_size ps=="); - printf("%08d",ui_1_32_100step); - printf("/100 ps "); - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { - printf(" rx_clk_window:"); - printf(" step_size ps=="); - printf("%08d",ui_1_32_100step); - printf("/100 ps "); - } - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { - printf(" tx_bit_dq_window:"); - printf(" step_size ps=="); - printf("%08d",ui_1_32_100step); - printf("/100 ps "); - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { - printf(" rx_bit_dq_window"); - printf(" step_size ps=="); - printf("%08d",bdlr_100step);//480ps - printf("/100 ps "); - } - printf("ddr clk frequency : "); - printf("%08d",(global_ddr_clk)); - printf("Mhz "); - printf(string_print_flag); - printf("index org min max left right dec vref_range vref_count"); - printf(string_print_flag); - - char delay_left_margin=0; - char delay_right_margin=0; - if (all_toghter_enable == 1) - { - nibble_max=1; - } - for ( nibble_step=0;nibble_step<nibble_max;nibble_step++) - { - //serial_put_dec_out_align(delay_martix[count].add_index,8); - printf("%08d",nibble_step); - printf(" "); - printf("%08d",0); - //serial_puts(" "); - //if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) ) - { - printf(" "); - printf("%08d",0//num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN] - ); - } - { - printf(" "); - printf("%08d",0//num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX] - ); - } - - // delay_left_margin=((num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG]>num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN])? - // (num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG]-num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN]):0); - // delay_right_margin=((num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX]>num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG])? - // (num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX]-num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG]):0); - delay_left_margin=num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]; - delay_right_margin=num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]; - printf(" "); - printf("%08d",delay_left_margin); - - //serial_put_dec_out_align((delay_martix[count].delay_org>delay_martix[count].delay_min)?(delay_martix[count].delay_org-delay_martix[count].delay_min):0,8); - printf(" "); - printf("%08d",delay_right_margin); - //serial_put_dec_out_align((delay_martix[count].delay_max>delay_martix[count].delay_org)?(delay_martix[count].delay_max-delay_martix[count].delay_org):0,8); - printf(" "); - printf("%08d",0); - printf(" "); - printf("%08d",0); - printf(" 2d-eye"); //p_dev->cur_type - printf(" dramtype "); - printf("%08d",0); - printf(" "); - printf("%08d",(global_ddr_clk)); - printf(" M bdl "); - printf("%08d",bdlr_100step);//480ps - printf(" /100 ps "); - printf("1/32step== "); - printf("%08d",ui_1_32_100step); - printf(" /100 ps "); - //serial_puts("bit_init_value "); - //serial_put_dec_out_align((p_dev->ddr_gloabl_message.stick_dmc_ddr_window_test_read_per_bit_init_value),4); - //if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY){ - //serial_puts("txdqsdly_second_tune_min_value "); - //serial_put_dec_out_align(txdqsdly_second_tune_value[count],4); - //} - printf(string_print_flag); - //serial_puts("\n"); - } - } -} -} -} - - if (config_register == 1) - { - if (num_arry[TEST_ARG_2_STEP] == 0) - { - num_arry[TEST_ARG_2_STEP]=1; - ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); - } - } - - if ((enable_kernel_test) && (num_arry[TEST_ARG_2_STEP]>1)) - run_command("run storeboot",0); - return reg_value; -} -//ouyang - -//#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address)))=((uint16_t)dat) -//#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address))) - -//#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address)))=((uint16_t)dat) -//#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address))) -#define ACX_MAX 0x80 - -//dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0),0); -//dwc_ddrphy_apb_wr(0xd0000,0); -//dwc_ddrphy_apb_wr(0xd0000,1); - -//*(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i); -//dwc_ddrphy_apb_wr((ps<<20)|(0<<16)|(instance_num<<12)|(0x80),); - -//ddr_test_acx_g12a a length step test_mode ACx -//ddr_test_acx_g12a a 0x8000000 1 0 0x1 -//argv[0] argv[1] argv[2] argv[3] argv[4] argv[5] -//argv[1],a -//argv[2],test length -//argv[3],test step -//argv[4],test_mode,direction,0,up; 1,down; 2,down first,up follow; -//argv[5],ACx;0-AC0,1-AC1,2-AC2...,9-AC9 - -#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12) #define G12_DATA_READ_OFFSET_MAX (0X3F) -#define G12_DATA_WRITE_OFFSET_MAX (0X3F+7*32) +#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32) #define DMC_TEST_WINDOW_INDEX_ATXDLY 1 #define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2 @@ -8947,1020 +7351,1394 @@ #define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12 #define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x13 -uint32_t ddr_cacl_phy_delay_all_step(char test_index,uint32_t value) +typedef struct training_delay_information { + uint16_t ac_delay[10]; + uint16_t txdqs_delay[16]; + uint16_t rxdqs_delay[16]; + uint16_t txdq_delay[72]; + uint16_t rxdq_delay[72]; + uint16_t gate_rxdq_delay[72]; +} training_delay_t; +training_delay_t training_delay_t_p; + +uint16_t lcd_bdl_value[72][4]; //org min max status +#define LCD_BDLR_MIN 0 +#define LCD_BDLR_MAX 1 +#define LCD_BDLR_STATUS 2 + +//BYTE0-3 +#define TEST_ARG_0_DMC_STICKY_MAGIC 0 +#define TEST_ARG_1_CMD0 1 +#define TEST_ARG_2_STEP 2 // 0 init 1 test ac 2 test tdqs_write +#define TEST_ARG_3_ALL_TOGHTER 3 + +//BYTE4-7 +#define TEST_ARG_FREQ_NIBBLE_L 4 +#define TEST_ARG_FREQ_NIBBLE_H 5 + +//BYTE8-11 +#define TEST_ARG_BOOT_TIMES_L 6 +#define TEST_ARG_BOOT_TIMES_H 7 + +//BYTE12-15 +#define TEST_ARG_ERROR_FLAG 8 //take 4 byte for kernel test flag + +//BYTE16-19 +#define TEST_ARG_CS0_TEST_START_INDEX 12 +#define TEST_ARG_CS0_TEST_SIZE_INDEX 16 +#define TEST_ARG_CS1_TEST_START_INDEX 20 +#define TEST_ARG_CS1_TEST_SIZE_INDEX 24 + +#define TEST_ARG_WATCHDOG_TIME_SIZE_INDEX 28 +#define TEST_ARG_TEST_INDEX_ENALBE_INDEX 30 + +#define TEST_ARG_ERROR_FLAG_NULL 0 +#define TEST_ARG_ERROR_FLAG_FAIL 1 +#define TEST_ARG_ERROR_FLAG_PASS 2 + +#define TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE 32 // 32BYTE +#define TEST_ARG_NIBBLE_WIDTH_BYTE 3 //3///BYTE + +int do_ddr_test_dqs_window_sticky(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - //#define DMC_TEST_WINDOW_INDEX_ATXDLY 1 - //#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2 - //#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3 - //#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4 - //#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5 - uint32_t result=0; - /* - if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { - result=32*(((value>>6)&1)+((value>>5)&1))+value&0x1f; - } - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { - result=32*(((value>>6)&0xf)+((value>>5)&1))+value&0x1f; - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { - result=32*(((value>>6)&0xf)+((value>>5)&1))+value&0x1f; - } - */ -#if 0 - if ((test_index <= DMC_TEST_WINDOW_INDEX_TXDQDLY) ) { - result=(32*(((value>>6)&0xf)+((value>>5)&1))+(value&0x1f)); - } - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { - result=(32*(((value>>6)&0xf)+(((value>>5)&1)*1))+(value&0x1f)); //bit 5 change to 1 UI 20180711 - //result=(32*((((value>>5)&1)*1))+(value&0x1f)); //bit 5 change to 1 UI 20180711 + printf("\nEnterddr_test_dqs_window function ddr_test_cmd 0x27 0x1080000 0x800000 0x40000000 0x800000 15 0x6 0 0 0 0 0 0 1/config\n"); + printf("\nddr_test_cmd 0x27 cs0_test_start cs0_test_size cs1_test_start cs1_test_size ns test_index_enable nibble_mask0 nibble_mask1 nibble_mask2 dram_type channel_mode config_register all_togther--- watchdog should >15s\n"); + printf("\n ac write_dqs read_dqs can test togther test_index_enable can enable kernel test \n"); +#define DDR_CORSS_TALK_TEST_SIZE 0x20000 + unsigned int temp_test_error = 0; + unsigned int nibble_save_offset = 0; + unsigned int nibble_step = 0; + unsigned int nibble_max = 16; + unsigned int test_index_enable = 0; + unsigned int test_index = 0; + unsigned int test_index_max = 6; + unsigned int reg_value = 0; + unsigned int dram_type = 0; + unsigned int channel_mode = 0; + unsigned int kernel_watchdog_s = 20; //240; + unsigned int config_register = 0; + unsigned int all_toghter_enable = 0; + unsigned int error_flag_reg_add = 0; + char *string_print_flag = " uboot-window-loop \n"; + char *endp; + char *buf; + buf = ""; + + unsigned int cs0_test_start = 0x1080000; + unsigned int cs0_test_size = DDR_CORSS_TALK_TEST_SIZE; + unsigned int cs1_test_start = 0; + unsigned int cs1_test_size = 0; + unsigned int enable_kernel_test = 0; + if (argc > 1) { + cs0_test_start = simple_strtoull_ddr(argv[1], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + cs0_test_start = 0x1080000; } - if ((test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) { - result=(32*(((value>>6)&0x1f)+(((value>>5)&1)*1))+(value&0x1f)); - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { - result=value&0x3f; + if (argc > 2) { + cs0_test_size = simple_strtoull_ddr(argv[2], &endp, 16); + if (*argv[2] == 0 || *endp != 0) + cs0_test_size = DDR_CORSS_TALK_TEST_SIZE; } -#else - if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { - result=(32*(((value>>6)&1)+((value>>5)&1)))+(value&0x1f); + if (argc > 3) { + cs1_test_start = simple_strtoull_ddr(argv[3], &endp, 16); + if (*argv[3] == 0 || *endp != 0) + cs1_test_start = 0; } + if (argc > 4) { + cs1_test_size = simple_strtoull_ddr(argv[4], &endp, 16); + if (*argv[4] == 0 || *endp != 0) + cs1_test_size = 0; + } + + unsigned int ddr_test_size = DDR_CORSS_TALK_TEST_SIZE; + ddr_test_size = cs0_test_size; + if (argc > 5) { + watchdog_time_s = simple_strtoull_ddr(argv[5], &endp, 0); + if (*argv[5] == 0 || *endp != 0) + watchdog_time_s = 20; + } + printf("watchdog_time_s==%d\n", watchdog_time_s); + + if (argc > 6) { + test_index_enable = simple_strtoull_ddr(argv[6], &endp, 0); + if (*argv[5] == 0 || *endp != 0) + test_index_enable = 0; + } + printf("test_index_enable==0x%08x\n", test_index_enable); + enable_kernel_test = (test_index_enable >> 7) & 1; + if (enable_kernel_test) + printf("enable kernel window test\n"); + + unsigned int nibble_mask[3] = { 0, 0, 0 }; + if (argc > 7) { + nibble_mask[0] = simple_strtoull_ddr(argv[7], &endp, 0); + if (*argv[7] == 0 || *endp != 0) + nibble_mask[0] = 0; + } + printf("nibble_mask[0]==0x%08x\n", nibble_mask[0]); + if (argc > 8) { + nibble_mask[1] = simple_strtoull_ddr(argv[8], &endp, 0); + if (*argv[8] == 0 || *endp != 0) + nibble_mask[1] = 0; + } + printf("nibble_mask[1]==0x%08x\n", nibble_mask[1]); + if (argc > 9) { + nibble_mask[2] = simple_strtoull_ddr(argv[9], &endp, 0); + if (*argv[9] == 0 || *endp != 0) + nibble_mask[2] = 0; + } + printf("nibble_mask[2]==0x%08x\n", nibble_mask[2]); + + if (argc > 10) { + dram_type = simple_strtoull_ddr(argv[10], &endp, 0); + if (*argv[10] == 0 || *endp != 0) + dram_type = 0; + } + if (argc > 11) { + channel_mode = simple_strtoull_ddr(argv[11], &endp, 0); + if (*argv[11] == 0 || *endp != 0) + channel_mode = 0; + } + if (argc > 12) { + config_register = simple_strtoull_ddr(argv[12], &endp, 0); + if (*argv[12] == 0 || *endp != 0) + config_register = 0; + } + if (argc > 13) { + all_toghter_enable = simple_strtoull_ddr(argv[13], &endp, 0); + if (*argv[13] == 0 || *endp != 0) + all_toghter_enable = 0; + } + printf("all_toghter_enable==0x%08x\n", all_toghter_enable); + + if (argc > 14) { + error_flag_reg_add = simple_strtoull_ddr(argv[14], &endp, 0); + if (*argv[14] == 0 || *endp != 0) + error_flag_reg_add = 0; + } + printf("error_flag_reg_add==0x%08x\n", error_flag_reg_add); + printf("\ntest use uboot sticky register\n"); + + char str[1024] = ""; + volatile uint16_t *num_arry = NULL; + int i; + + sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0)) & 0xffff); + for (i = 0; i < 64 * 4; i++) { + num_arry[i] = ddr_rd_8_16bit_on_32reg(sticky_reg_base_add, 8, i); + if ((i == 0) || (i == 32) || (i == (32 + 10 * 3)) || (i == (32 + 10 * 3 + 16 * 3)) || (i == (32 + 10 * 3 + 16 * 3 + 16 * 3))) + printf("\n numarry[%d]", i); + printf(" %d ", num_arry[i]); + } + + uint16_t test_left_max_init_value = 32; + uint16_t test_right_max_init_value = 32; + uint16_t test_boot_times = 0; + uint16_t test_ddr_frequency = 0; + + printf("\nTEST_ARG_0_DMC_STICKY_MAGIC==0x%08x\n", num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]); + printf("\nTEST_ARG_1_CMD0==0x%08x\n", num_arry[TEST_ARG_1_CMD0]); + printf("TEST_ARG_2_STEP==0x%08x\n", num_arry[TEST_ARG_2_STEP]); + printf("TEST_ARG_3_ALL_TOGHTER==0x%08x\n", num_arry[TEST_ARG_3_ALL_TOGHTER]); + printf("TEST_ARG_FREQ_NIBBLE_L==0x%08x\n", num_arry[TEST_ARG_FREQ_NIBBLE_L]); + printf("TEST_ARG_FREQ_NIBBLE_H==0x%08x\n", num_arry[TEST_ARG_FREQ_NIBBLE_H]); + printf("TEST_ARG_BOOT_TIMES_L==0x%08x\n", num_arry[TEST_ARG_BOOT_TIMES_L]); + printf("TEST_ARG_BOOT_TIMES_H==0x%08x\n", num_arry[TEST_ARG_BOOT_TIMES_H]); + printf("TEST_ARG_ERROR_FLAG==0x%08x\n", num_arry[TEST_ARG_ERROR_FLAG]); + + printf("TEST_ARG_FREQ==%dM\n", (num_arry[TEST_ARG_FREQ_NIBBLE_H] << 8) | (num_arry[TEST_ARG_FREQ_NIBBLE_L] << 0)); + printf("TEST_ARG_BOOT_TIMES==%d\n", (num_arry[TEST_ARG_BOOT_TIMES_H] << 8) | (num_arry[TEST_ARG_BOOT_TIMES_L] << 0)); + test_boot_times = (num_arry[TEST_ARG_BOOT_TIMES_H] << 8) | (num_arry[TEST_ARG_BOOT_TIMES_L] << 0); + test_ddr_frequency = (num_arry[TEST_ARG_FREQ_NIBBLE_H] << 8) | (num_arry[TEST_ARG_FREQ_NIBBLE_L] << 0); + + if ((num_arry[TEST_ARG_0_DMC_STICKY_MAGIC] == (DMC_STICKY_UBOOT_WINDOW_MAGIC_1 & 0xff)) + && (num_arry[TEST_ARG_1_CMD0] == (DMC_STICKY_UBOOT_WINDOW_MAGIC_1 & 0xff))) { //for check magic number make sume enter test command + test_boot_times++; + num_arry[TEST_ARG_BOOT_TIMES_L] = test_boot_times & 0xff; + num_arry[TEST_ARG_BOOT_TIMES_H] = (test_boot_times >> 8) & 0xff; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_L, num_arry[TEST_ARG_BOOT_TIMES_L]); + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_H, num_arry[TEST_ARG_BOOT_TIMES_H]); + + if (test_ddr_frequency != global_ddr_clk) { // + printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n", global_ddr_clk, test_ddr_frequency); + sprintf(str, "d2pll %d", test_ddr_frequency); + printf("\nstr=%s\n", str); + run_command(str, 0); + + while (1) { + } + } + } else { + test_boot_times = 0; + num_arry[TEST_ARG_BOOT_TIMES_L] = test_boot_times & 0xff; + num_arry[TEST_ARG_BOOT_TIMES_H] = (test_boot_times >> 8) & 0xff; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_L, num_arry[TEST_ARG_BOOT_TIMES_L]); + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_H, num_arry[TEST_ARG_BOOT_TIMES_H]); + num_arry[TEST_ARG_2_STEP] = 0; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); + } + printf("test_sticky is not magic nummber,boot times==%d\n", test_boot_times); + + { + wr_reg((sticky_reg_base_add + TEST_ARG_CS0_TEST_START_INDEX), cs0_test_start); + wr_reg((sticky_reg_base_add + TEST_ARG_CS0_TEST_SIZE_INDEX), cs0_test_size); + wr_reg((sticky_reg_base_add + TEST_ARG_CS1_TEST_START_INDEX), cs1_test_start); + wr_reg((sticky_reg_base_add + TEST_ARG_CS1_TEST_SIZE_INDEX), cs1_test_size); + { + num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX] = watchdog_time_s & 0xff; + num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX + 1] = (watchdog_time_s >> 8) & 0xff; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_WATCHDOG_TIME_SIZE_INDEX, num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX]); + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, (TEST_ARG_WATCHDOG_TIME_SIZE_INDEX + 1), num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX + 1]); + } + num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX] = test_index_enable; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_TEST_INDEX_ENALBE_INDEX, num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]); + if (config_register == 1) { + num_arry[TEST_ARG_2_STEP] = 0; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); + } + num_arry[TEST_ARG_3_ALL_TOGHTER] = all_toghter_enable; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_3_ALL_TOGHTER, num_arry[TEST_ARG_3_ALL_TOGHTER]); + } + + if ((num_arry[TEST_ARG_2_STEP]) == 0) { + { + num_arry[TEST_ARG_0_DMC_STICKY_MAGIC] = DMC_STICKY_UBOOT_WINDOW_MAGIC_1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_0_DMC_STICKY_MAGIC, num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]); + num_arry[TEST_ARG_1_CMD0] = DMC_STICKY_UBOOT_WINDOW_MAGIC_1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_1_CMD0, num_arry[TEST_ARG_1_CMD0]); + num_arry[TEST_ARG_2_STEP] = 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); + { + test_boot_times = 0; + num_arry[TEST_ARG_BOOT_TIMES_L] = test_boot_times & 0xff; + num_arry[TEST_ARG_BOOT_TIMES_H] = (test_boot_times >> 8) & 0xff; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_L, num_arry[TEST_ARG_BOOT_TIMES_L]); + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_H, num_arry[TEST_ARG_BOOT_TIMES_H]); + } + { + test_ddr_frequency = global_ddr_clk; + num_arry[TEST_ARG_FREQ_NIBBLE_L] = test_ddr_frequency & 0xff; + num_arry[TEST_ARG_FREQ_NIBBLE_H] = (test_ddr_frequency >> 8) & 0xff; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_FREQ_NIBBLE_L, num_arry[TEST_ARG_FREQ_NIBBLE_L]); + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_FREQ_NIBBLE_H, num_arry[TEST_ARG_FREQ_NIBBLE_H]); + } + + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_NULL; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_ERROR_FLAG, num_arry[TEST_ARG_ERROR_FLAG]); + } + + + for (nibble_step = 0; nibble_step < 72; nibble_step++) { + { + test_left_max_init_value = 16; + test_right_max_init_value = 16; + if (nibble_step < 10) { + test_left_max_init_value = 32; + test_right_max_init_value = 32; + } + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN] = test_left_max_init_value; + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX] = test_right_max_init_value; + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS] = 0; //0 + } + + { + if (nibble_step < 32) { + if (((nibble_mask[0]) >> nibble_step) & 1) + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4; + } else if (nibble_step < 64) { + if (((nibble_mask[1]) >> (nibble_step - 32)) & 1) + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4; + } else if (nibble_step < 96) { + if (((nibble_mask[2]) >> (nibble_step - 64)) & 1) + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4; + } + if (all_toghter_enable) { + if ((nibble_step == 0) || (nibble_step == 10) || (nibble_step == (10 + 16))) + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 0; + else + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4; + } + } + } + + { + for (i = TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE; i < 72 * TEST_ARG_NIBBLE_WIDTH_BYTE; i++) + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, i, num_arry[i]); + + num_arry[TEST_ARG_2_STEP] = 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); + } + } + + if (all_toghter_enable) { + for (nibble_step = 0; nibble_step < 72; nibble_step++) { + if ((nibble_step == 0) || (nibble_step == 10) || (nibble_step == (10 + 16))) { + } else { + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4; + } + } + } + + if (config_register == 1) { + num_arry[TEST_ARG_2_STEP] = 0; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); + } + + if ((num_arry[TEST_ARG_2_STEP])) { + for (test_index = num_arry[TEST_ARG_2_STEP]; test_index < test_index_max; test_index++) { + printf("\ntest_index=%d\n", test_index); + if ((((test_index_enable) >> (test_index - 1)) & 1) == 0) { + num_arry[TEST_ARG_2_STEP] = ((num_arry[TEST_ARG_2_STEP]) + 1); //why can not use ++ + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); + continue; + } + { + if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + nibble_save_offset = 0; + nibble_max = 10; + nibble_mask[0] = 0x30; + if ((dram_type == CONFIG_DDR_TYPE_LPDDR3)) + nibble_mask[0] = 0x3e3; + if ((dram_type == CONFIG_DDR_TYPE_LPDDR4)) { + nibble_mask[0] = 0x273; + if ((channel_mode == CONFIG_DDR0_32BIT_RANK01_CH0)) + nibble_mask[0] = 0x3f3; + } + test_left_max_init_value = 64; + test_right_max_init_value = 64; + } + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + nibble_save_offset = 10; + nibble_max = 16; + if ((cs1_test_size == 0)) + nibble_mask[0] = 0xff00; + test_left_max_init_value = 16; + test_right_max_init_value = 16; + } + if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + nibble_save_offset = (10) + (16); + if ((cs1_test_size == 0)) + nibble_mask[0] = 0xff00; + nibble_max = 16; + test_left_max_init_value = 16; + test_right_max_init_value = 16; + } + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + nibble_save_offset = 0; + nibble_max = 72; + if ((cs1_test_size == 0)) { + nibble_mask[1] = 0xfffffff0; + nibble_mask[2] = 0xffffffff; + } + test_left_max_init_value = 16; + test_right_max_init_value = 16; + } + if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + nibble_save_offset = 0; + nibble_max = 72; + if ((cs1_test_size == 0)) { + nibble_mask[1] = 0xfffffff0; + nibble_mask[2] = 0xffffffff; + } + + test_left_max_init_value = 64; + test_right_max_init_value = 64; + } + for ((nibble_step = 0); (nibble_step < nibble_max); (nibble_step++)) { + if (nibble_step < 32) { + if (((nibble_mask[0]) >> nibble_step) & 1) + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4; + } else if (nibble_step < 64) { + if (((nibble_mask[1]) >> (nibble_step - 32)) & 1) + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4; + } else if (nibble_step < 96) { + if (((nibble_mask[2]) >> (nibble_step - 64)) & 1) + num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4; + } + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + } + } + + { + for ((nibble_step = 0); (nibble_step < nibble_max); (nibble_step++)) { + if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 4) + continue; + printf("nibble_step ==%d\n", nibble_step); + + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + if (nibble_step % 2) { + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step - 1 + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]); + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step - 1 + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]); + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step - 1 + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + continue; + } + } + test_start_addr = cs0_test_start; + ddr_test_size = cs0_test_size; + if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + test_start_addr = cs0_test_start; + ddr_test_size = cs0_test_size; + } + + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + if (nibble_step > 7) { + test_start_addr = cs1_test_start; + ddr_test_size = cs1_test_size; + } + } + if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + if (nibble_step > 7) { + test_start_addr = cs1_test_start; + ddr_test_size = cs1_test_size; + } + } + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + if (nibble_step > 35) { + test_start_addr = cs1_test_start; + ddr_test_size = cs1_test_size; + } + } + if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + if (nibble_step > 35) { + test_start_addr = cs1_test_start; + ddr_test_size = cs1_test_size; + } + } + { + if (nibble_step < 32) { + nibble_mask[0] = ((0xffffffff) & (~(1 << nibble_step))); + nibble_mask[1] = ((0xffffffff)); + nibble_mask[2] = ((0xffffffff)); + } else if (nibble_step < 64) { + nibble_mask[0] = ((0xffffffff)); + nibble_mask[1] = ((0xffffffff) & (~(1 << (nibble_step - 32)))); + nibble_mask[2] = ((0xffffffff)); + } else if (nibble_step < 96) { + nibble_mask[0] = ((0xffffffff)); + nibble_mask[1] = ((0xffffffff)); + nibble_mask[2] = ((0xffffffff) & (~(1 << (nibble_step - 64)))); + } + } + if (all_toghter_enable) { + if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + nibble_save_offset = 0; + nibble_max = 10; + nibble_mask[0] = 0x30; + nibble_mask[1] = 0; + nibble_mask[2] = 0; + if ((dram_type == CONFIG_DDR_TYPE_LPDDR3)) + nibble_mask[0] = 0x3e3; + if ((dram_type == CONFIG_DDR_TYPE_LPDDR4)) { + nibble_mask[0] = 0x273; + if ((channel_mode == CONFIG_DDR0_32BIT_RANK01_CH0)) + nibble_mask[0] = 0x3f3; + } + } else { + nibble_mask[0] = 0; + nibble_mask[1] = 0; + nibble_mask[2] = 0; + } + } + + ddr_test_watchdog_enable(watchdog_time_s); //s + printf("\nenable %ds watchdog \n", watchdog_time_s); + if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 0xffff) + || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 0) + || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 1)) { + printf("\nnibble_step ==%d ", nibble_step); + if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 0xffff) + || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 0)) { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + + if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] == 0) { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 2; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + run_command("reset", 0); + } + { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] = + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] - 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]); + } + + { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_FAIL; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + } + + sprintf(str, "ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d", test_index, nibble_mask[0], nibble_mask[1], nibble_mask[2], DDR_PARAMETER_LEFT, + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]); + printf("\nstr=%s\n", str); + ddr_test_watchdog_clear(); + run_command(str, 0); + + temp_test_error = ddr_test_s_cross_talk_pattern(ddr_test_size); + if (all_toghter_enable && cs1_test_size) { + test_start_addr = cs1_test_start; + ddr_test_size = cs1_test_size; + temp_test_error = temp_test_error + ddr_test_s_cross_talk_pattern(ddr_test_size); + test_start_addr = cs0_test_start; + ddr_test_size = cs0_test_size; + } + if (temp_test_error) { + run_command("reset", 0); + } else { + if (!enable_kernel_test) { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_PASS; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + run_command("reset", 0); + } else { + ddr_test_watchdog_enable(kernel_watchdog_s); //s + printf("\nenable %ds watchdog \n", kernel_watchdog_s); + run_command("run storeboot", 0); + } + } + } else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 1) { //go on find left edge + if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] == 0) { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 2; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + run_command("reset", 0); + } + + if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS) { + { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 2; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + } + { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_NULL; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + } + run_command("reset", 0); + } + if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL) { + { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] = + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] - 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]); + } + { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_FAIL; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + } + sprintf(buf, "0x%08x", (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)])); + printf("%s", buf); + sprintf(str, "ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d", test_index, nibble_mask[0], nibble_mask[1], nibble_mask[2], DDR_PARAMETER_LEFT, + (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)])); + printf("\nstr=%s\n", str); + ddr_test_watchdog_clear(); + run_command(str, 0); + temp_test_error = ddr_test_s_cross_talk_pattern(ddr_test_size); + if (all_toghter_enable && cs1_test_size) { + test_start_addr = cs1_test_start; + ddr_test_size = cs1_test_size; + temp_test_error = temp_test_error + ddr_test_s_cross_talk_pattern(ddr_test_size); + test_start_addr = cs0_test_start; + ddr_test_size = cs0_test_size; + } + if (temp_test_error) { + run_command("reset", 0); + } else { + if (!enable_kernel_test) { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_PASS; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + run_command("reset", 0); + } else { + ddr_test_watchdog_enable(kernel_watchdog_s); //s + printf("\nenable %ds watchdog \n", kernel_watchdog_s); + run_command("run storeboot", 0); + } + } + } + } + } + + if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 2) + || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 3)) { + printf("\nnibble_step ==%d ", nibble_step); + + if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 2) + || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 2)) { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 3; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + + if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] == 0) { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 4; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + run_command("reset", 0); + } + { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] = + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] - 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]); + } + + { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_FAIL; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + } + sprintf(str, "ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d", test_index, nibble_mask[0], nibble_mask[1], nibble_mask[2], DDR_PARAMETER_RIGHT, + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]); + printf("\nstr=%s\n", str); + ddr_test_watchdog_clear(); + run_command(str, 0); + temp_test_error = ddr_test_s_cross_talk_pattern(ddr_test_size); + if (all_toghter_enable && cs1_test_size) { + test_start_addr = cs1_test_start; + ddr_test_size = cs1_test_size; + temp_test_error = temp_test_error + ddr_test_s_cross_talk_pattern(ddr_test_size); + test_start_addr = cs0_test_start; + ddr_test_size = cs0_test_size; + } + if (temp_test_error) { + run_command("reset", 0); + } else { + if (!enable_kernel_test) { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_PASS; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + run_command("reset", 0); + } else { + ddr_test_watchdog_enable(kernel_watchdog_s); //s + printf("\nenable %ds watchdog \n", kernel_watchdog_s); + run_command("run storeboot", 0); + } + } + } else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 3) { //go on find left edge + if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] == 0) { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 4; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + run_command("reset", 0); + } + + if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS) { + { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 4; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]); + } + { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_NULL; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + } + run_command("reset", 0); + } + if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL) { + { + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] = + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] - 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX), + num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]); + } + { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_FAIL; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + } + sprintf(buf, "0x%08x", (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)])); + printf("%s", buf); + sprintf(str, "ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d", test_index, nibble_mask[0], nibble_mask[1], nibble_mask[2], DDR_PARAMETER_RIGHT, + (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)])); + printf("\nstr=%s\n", str); + ddr_test_watchdog_clear(); + run_command(str, 0); + temp_test_error = ddr_test_s_cross_talk_pattern(ddr_test_size); + if (all_toghter_enable && cs1_test_size) { + test_start_addr = cs1_test_start; + ddr_test_size = cs1_test_size; + temp_test_error = temp_test_error + ddr_test_s_cross_talk_pattern(ddr_test_size); + test_start_addr = cs0_test_start; + ddr_test_size = cs0_test_size; + } + if (temp_test_error) { + run_command("reset", 0); + } else { + if (!enable_kernel_test) { + num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_PASS; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, + TEST_ARG_ERROR_FLAG, + num_arry[TEST_ARG_ERROR_FLAG]); + run_command("reset", 0); + } else { + ddr_test_watchdog_enable(kernel_watchdog_s); //s + printf("\nenable %ds watchdog \n", kernel_watchdog_s); + run_command("run storeboot", 0); + } + } + } + } + } + + ddr_test_watchdog_disable(); //s + { + printf("close watchdog\n"); + } + } + + printf("11num_arry[TEST_ARG_2_STEP]==%d\n", num_arry[TEST_ARG_2_STEP]); + num_arry[TEST_ARG_2_STEP] = (num_arry[TEST_ARG_2_STEP]) + 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); + printf("22num_arry[TEST_ARG_2_STEP]==%d\n", num_arry[TEST_ARG_2_STEP]); + + ddr_test_watchdog_disable(); //s + printf("close watchdog\n"); + { + unsigned int ui_1_32_100step = 0; + unsigned int bdlr_100step = 0; + ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32)); + bdlr_100step = get_bdlr_100step(global_ddr_clk); + + printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,bdlr_100step=%d ps,ui_1_32_100step=%d ps,\n", 0, 0, global_ddr_clk, + bdlr_100step, ui_1_32_100step); + + printf("\n test result index=="); + printf("%08d", test_index); + + if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + printf(" ac window:"); + printf(" step_size ps=="); + printf("%08d", ui_1_32_100step); + printf("/100 ps "); + } + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + printf(" txdqs window:"); + printf(" step_size ps=="); + printf("%08d", ui_1_32_100step); + printf("/100 ps "); + } + if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + printf(" rx_clk_window:"); + printf(" step_size ps=="); + printf("%08d", ui_1_32_100step); + printf("/100 ps "); + } + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + printf(" tx_bit_dq_window:"); + printf(" step_size ps=="); + printf("%08d", ui_1_32_100step); + printf("/100 ps "); + } + if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + printf(" rx_bit_dq_window"); + printf(" step_size ps=="); + printf("%08d", bdlr_100step); //480ps + printf("/100 ps "); + } + printf("ddr clk frequency : "); + printf("%08d", (global_ddr_clk)); + printf("Mhz "); + printf(string_print_flag); + printf("index org min max left right dec vref_range vref_count"); + printf(string_print_flag); + + char delay_left_margin = 0; + char delay_right_margin = 0; + if (all_toghter_enable == 1) + nibble_max = 1; + for (nibble_step = 0; nibble_step < nibble_max; nibble_step++) { + printf("%08d", nibble_step); + printf(" "); + printf("%08d", 0); + { + printf(" "); + printf("%08d", 0 //num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN] + ); + } + { + printf(" "); + printf("%08d", 0 //num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX] + ); + } + + delay_left_margin = num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]; + delay_right_margin = num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]; + printf(" "); + printf("%08d", delay_left_margin); + + printf(" "); + printf("%08d", delay_right_margin); + printf(" "); + printf("%08d", 0); + printf(" "); + printf("%08d", 0); + printf(" 2d-eye"); //p_dev->cur_type + printf(" dramtype "); + printf("%08d", 0); + printf(" "); + printf("%08d", (global_ddr_clk)); + printf(" M bdl "); + printf("%08d", bdlr_100step); //480ps + printf(" /100 ps "); + printf("1/32step== "); + printf("%08d", ui_1_32_100step); + printf(" /100 ps "); + printf(string_print_flag); + } + } + } + } + } + + if (config_register == 1) { + if (num_arry[TEST_ARG_2_STEP] == 0) { + num_arry[TEST_ARG_2_STEP] = 1; + ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]); + } + } + + if ((enable_kernel_test) && (num_arry[TEST_ARG_2_STEP] > 1)) + run_command("run storeboot", 0); + return reg_value; +} + +#define ACX_MAX 0x80 + +#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12) +#define G12_DATA_READ_OFFSET_MAX (0X3F) +#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32) + +#define DMC_TEST_WINDOW_INDEX_ATXDLY 1 +#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2 +#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3 +#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4 +#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5 +#define DMC_TEST_WINDOW_INDEX_RXENDLY 6 + +#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11 +#define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12 +#define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x13 + +uint32_t ddr_cacl_phy_delay_all_step(char test_index, uint32_t value) +{ + uint32_t result = 0; + + if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) + result = (32 * (((value >> 6) & 1) + ((value >> 5) & 1))) + (value & 0x1f); //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814 - else if( (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)||(test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)) { - result=(32*(((value>>6)&7)))+(value&0x3f); - } - else //other register bit5 is effect ,but can not modify coarse delay why ? jiaxing 20180814 - result=value&0x3f; -#endif - if (test_index >= DMC_TEST_WINDOW_INDEX_EE_VOLTAGE) { - result=value; - } + else if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) || (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)) + result = (32 * (((value >> 6) & 7))) + (value & 0x3f); + else //other register bit5 is effect ,but can not modify coarse delay why ? jiaxing 20180814 + result = value & 0x3f; + if (test_index >= DMC_TEST_WINDOW_INDEX_EE_VOLTAGE) + result = value; return result; } -uint32_t ddr_cacl_phy_over_ride_back_reg(char test_index,uint32_t value ) +uint32_t ddr_cacl_phy_over_ride_back_reg(char test_index, uint32_t value) { - //#define DMC_TEST_WINDOW_INDEX_ATXDLY - //#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2 - //#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3 - //#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4 - //#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5 - uint32_t result=0; - if ((test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) ) { - if (value<64) { - result=((value/32)<<6)+value%32; - } - else { - result=(3<<5)+(value%32); - } - } - /* - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { - result=((value/32)<<6)+value%32; - } - if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { - result=((value/32)<<6)+value%32; - } - */ - else if((test_index==DMC_TEST_WINDOW_INDEX_TXDQDLY) - ||(test_index==DMC_TEST_WINDOW_INDEX_RXCLKDLY) - ||(test_index==DMC_TEST_WINDOW_INDEX_RXENDLY)) { - //result=((value/32)<<6)+value%64; - result=value%64; - if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) || (test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) { //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814 - result=((value/32)<<6)+value%32; - } - } - else if(test_index==DMC_TEST_WINDOW_INDEX_RXPBDLY) { - result=value&0x3f; - } - else if(test_index==DMC_TEST_WINDOW_INDEX_TXDQSDLY) { -#if 1 - result=((value/32)<<6)+value%32; - /* - if (enable_bit5) - { - if ((result>>6)&1) - {result=(result&0xffbf)|(1<<5); - } - } - */ -#else - result=value%64; -#endif - } - else if(test_index>DMC_TEST_WINDOW_INDEX_RXPBDLY) { - result=value; - } + uint32_t result = 0; - return result; + if ((test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)) { + if (value < 64) + result = ((value / 32) << 6) + value % 32; + else + result = (3 << 5) + (value % 32); + } else if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) + || (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) + || (test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) { + result = value % 64; + if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) || (test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814 + result = ((value / 32) << 6) + value % 32; + } else if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + result = value & 0x3f; + } else if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + result = ((value / 32) << 6) + value % 32; + } else if (test_index > DMC_TEST_WINDOW_INDEX_RXPBDLY) { + result = value; + } + + return result; } -unsigned int do_ddr_g12_read_write_ddr_add_window_lcdlr(unsigned int rank_index,unsigned int add_index,unsigned int lcdlr_value,unsigned int read_write_flag ) +unsigned int do_ddr_g12_read_write_ddr_add_window_lcdlr(unsigned int rank_index, unsigned int add_index, unsigned int lcdlr_value, unsigned int read_write_flag) { - dwc_ddrphy_apb_wr(0xd0000,0);//mw fe1a0000 0 - // reg_base_adj=(p_ddr_base->ddr_phy_base_address); - // reg_add=(((0<<20)|(0<<16)|(test_ACx<<12)|(0x80))<<1) + reg_base_adj; + dwc_ddrphy_apb_wr(0xd0000, 0); //mw fe1a0000 0 if (read_write_flag == DDR_PARAMETER_READ) - { - lcdlr_value=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(add_index<<12)|(0x80)); - } + lcdlr_value = dwc_ddrphy_apb_rd((0 << 20) | (0 << 16) | (add_index << 12) | (0x80)); if (read_write_flag == DDR_PARAMETER_WRITE) - { - dwc_ddrphy_apb_wr(((0<<20)|(0<<16)|(add_index<<12)|(0x80)), lcdlr_value); - } + dwc_ddrphy_apb_wr(((0 << 20) | (0 << 16) | (add_index << 12) | (0x80)), lcdlr_value); - printf("rank_index %d add_index %d lcdlr== %d \n", rank_index,add_index,lcdlr_value); + printf("rank_index %d add_index %d lcdlr== %d \n", rank_index, add_index, lcdlr_value); return lcdlr_value; } -void dwc_window_reg_after_training_update_increas_dq(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_increase_decrease, - uint32_t step_value) +void dwc_window_reg_after_training_update_increas_dq(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease, + uint32_t step_value) { - uint32_t delay_old_value=0; - uint32_t delay_reg_value=0; + uint32_t delay_old_value = 0; + uint32_t delay_reg_value = 0; - uint64_t reg_add=0; + uint64_t reg_add = 0; + if (!over_ride_index) return; if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+step_value; - if (delay_reg_value>255) - delay_reg_value=255; + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0xc0 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); + if (over_ride_increase_decrease == 0) { + delay_reg_value = delay_reg_value + step_value; + if (delay_reg_value > 255) + delay_reg_value = 255; } - if (over_ride_increase_decrease != 0) - { - if (delay_reg_value>step_value) - delay_reg_value=delay_reg_value-step_value; + if (over_ride_increase_decrease != 0) { + if (delay_reg_value > step_value) + delay_reg_value = delay_reg_value - step_value; else - delay_reg_value=0; + delay_reg_value = 0; } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - // dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value); + delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); } - printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n",((unsigned int)(((reg_add) << 1)+(p_ddr_base->ddr_phy_base_address))), - delay_old_value,dwc_ddrphy_apb_rd(reg_add),ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value), - (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add))); + printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n", ((unsigned int)(((reg_add) << 1) + (p_ddr_base->ddr_phy_base_address))), + delay_old_value, dwc_ddrphy_apb_rd(reg_add), ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value), + (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add))); } -void dwc_window_reg_after_training_update(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_value) +void dwc_window_reg_after_training_update(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_value) { - uint32_t delay_old_value=0; - uint32_t delay_reg_value=0; - uint64_t reg_add=0; - // if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) - //p_dev->ddr_gloabl_message.stick_ddr_log_level=0; - //serial_puts("\nstick_test_ddr_window_delay_override_before_after_training_setting=="); - //serial_put_dec(p_dev->ddr_gloabl_message.stick_test_ddr_window_delay_override_before_after_training_setting); - //serial_puts("\n"); + uint32_t delay_old_value = 0; + uint32_t delay_reg_value = 0; + uint64_t reg_add = 0; - if (!over_ride_index) { - return; - } - //ddr_dmc_update_delay_register_before(); - //char enable_bit5=0; - // if ((p_dev->p_ddrs->DramType == CONFIG_DDR_TYPE_LPDDR4) && (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)) - // {enable_bit5=1;} - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value); - if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { - reg_add=((0<<20)|(0<<16)|(over_ride_sub_index<<12)|(0x80)); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - } - - if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0xd0+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0xd0+(over_ride_sub_index/4)),delay_reg_value); - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value); - - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value|(delay_old_value&0xffc0)); - - // {enable_bit5=(delay_old_value>>5)&1;} - //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value,enable_bit5); - - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8))); - delay_old_value=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8))); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value); - //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x18c+(over_ride_sub_index/4)),(delay_reg_value|(delay_old_value&0xffc0))-p_dev->ddr_gloabl_message.stick_phy_read_dqs_nibble_offset); - //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x90+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)),(delay_reg_value|(delay_old_value&0xffc0))); - //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x190+(over_ride_sub_index/4)),(delay_reg_value|(delay_old_value&0xffc0))-p_dev->ddr_gloabl_message.stick_phy_read_dqs_nibble_offset); - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - //dwc_ddrphy_apb_wr(((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))),delay_reg_value|(delay_old_value&0xffc0)); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - } - - if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) { - reg_add=((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x80+(over_ride_sub_index/8))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x180+(over_ride_sub_index/4)),delay_reg_value|(delay_old_value&0xffc0)); - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { - // delay_old_value= init_soc_vref(p_dev->cur_type ,(over_ride_value>>8)&0xff, over_ride_value, over_ride_sub_index ,p_dev->ddr_gloabl_message.stick_ddr_log_level); - // set_soc_vref( p_dev->cur_type , (over_ride_value>>8)&0xff, over_ride_value, over_ride_sub_index ); - dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value); - } - - printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n",((unsigned int)(((reg_add) << 1)+(p_ddr_base->ddr_phy_base_address))), - delay_old_value,dwc_ddrphy_apb_rd(reg_add),ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value), - (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, delay_reg_value)); -} - -void dwc_window_reg_after_training_update_increas_sub(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_increase_decrease, - uint32_t step_value) -{ - uint32_t delay_old_value=0; - uint32_t delay_reg_value=0; - - uint64_t reg_add=0; if (!over_ride_index) return; + delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value); if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { - - reg_add=((0<<20)|(0<<16)|(over_ride_sub_index<<12)|(0x80)); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value); - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+step_value; - if (delay_reg_value>95) - delay_reg_value=95; - } - if (over_ride_increase_decrease != 0) - { - if (delay_reg_value >= step_value) - delay_reg_value=delay_reg_value-step_value; - else - delay_reg_value=0; - } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr((reg_add),delay_reg_value); + reg_add = ((0 << 20) | (0 << 16) | (over_ride_sub_index << 12) | (0x80)); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0xd0+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0xd0+(over_ride_sub_index/4)),delay_reg_value); - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value); + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0xd0 + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); - - //some case will happen tdqs from 0x1f to 0x0 or 0x0 to 0x1f ,then fast boot write back will happen error ,because - // fast boot write back will re-calculate coarse UI,then result dq phase fail. - /* - if (over_ride_increase_decrease == 0) - // if(over_ride_value>ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value)) - {dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)+step_value)|(delay_old_value&0xffc0)); - if (((delay_old_value&0x3f)+step_value)>0x3f) - dwc_ddrphy_apb_wr(reg_add,0x3f|(delay_old_value&0xffc0)); - } - else - {//dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0)); - if (((delay_old_value&0x3f)<step_value)) - dwc_ddrphy_apb_wr(reg_add,(delay_old_value&0xffc0)); - else - dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0)); - } - - */ - if ((over_ride_sub_index%2) == 0) - { - char temp_test_index=DMC_TEST_WINDOW_INDEX_TXDQDLY; - char temp_count=0; - // if(over_ride_increase_decrease==0) - { - for ( temp_count=0;temp_count<9;temp_count++) - { - dwc_window_reg_after_training_update_increas_dq(temp_test_index - ,(((over_ride_sub_index)>>1)*9+temp_count), (!over_ride_increase_decrease),step_value) ; - } - } - } - - - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value|(delay_old_value&0xffc0)); - - // {enable_bit5=(delay_old_value>>5)&1;} - //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value,enable_bit5); - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+step_value; - if (delay_reg_value>255) - delay_reg_value=255; - } - if (over_ride_increase_decrease != 0) - { - if (delay_reg_value>step_value) - delay_reg_value=delay_reg_value-step_value; - else - delay_reg_value=0; - } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - // dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value); - + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); } if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+step_value; - if (delay_reg_value>95) - delay_reg_value=95; - } - if (over_ride_increase_decrease != 0) - { - if (delay_reg_value>step_value) - delay_reg_value=delay_reg_value-step_value; - else - delay_reg_value=0; - } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value); - + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0x8c + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8))); + delay_old_value = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0x8c + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8))); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); + dwc_ddrphy_apb_wr(reg_add + 4, delay_reg_value); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0xc0 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); } if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+step_value; - if (delay_reg_value>63) - delay_reg_value=63; - } - if (over_ride_increase_decrease != 0) - { - if (delay_reg_value>step_value) - delay_reg_value=delay_reg_value-step_value; - else - delay_reg_value=0; - } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0x68 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) { - ///* - reg_add=((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x80+(over_ride_sub_index/8))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) -// if(over_ride_value>ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value)) - { - dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)+step_value)|(delay_old_value&0xffc0)); - if (((delay_old_value&0x3f)+step_value)>0x3f) - dwc_ddrphy_apb_wr(reg_add,0x3f|(delay_old_value&0xffc0)); - } - else - { - dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0)); - if (((delay_old_value&0x3f)<step_value)) - dwc_ddrphy_apb_wr(reg_add,(delay_old_value&0xffc0)); - } - // delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - // dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0)); - //*/ + reg_add = ((0 << 20) | (1 << 16) | ((over_ride_sub_index % 8) << 12) | (0x80 + (over_ride_sub_index / 8))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); } - - if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { - //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value); - //reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40)); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - delay_reg_value=delay_old_value; - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+step_value; - if (delay_reg_value>127) - delay_reg_value=127; - } - if (over_ride_increase_decrease != 0) - { - if (delay_reg_value >= step_value) - delay_reg_value=delay_reg_value-step_value; - else - delay_reg_value=0; - } - //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - } - printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n",((unsigned int)(((reg_add) << 1)+(p_ddr_base->ddr_phy_base_address))), - delay_old_value,dwc_ddrphy_apb_rd(reg_add),ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value), - (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add))); - -} - - -void dwc_window_reg_after_training_update_increas(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_increase_decrease, - uint32_t offset_value) -{ - uint32_t delay_old_value=0; - //uint32_t delay_reg_value=0; - uint32_t temp_count_3=0; - // uint32_t delay_old_value_cacl=0; - // uint32_t delay_reg_value_cacl=0; - //uint32_t over_ride_value=0; - // if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) - //p_dev->ddr_gloabl_message.stick_ddr_log_level=0; - //serial_puts("\nstick_test_ddr_window_delay_override_before_after_training_setting=="); - //serial_put_dec(p_dev->ddr_gloabl_message.stick_test_ddr_window_delay_override_before_after_training_setting); - //serial_puts("\n"); - uint64_t reg_add=0; - if (!over_ride_index) { - return; - } - - //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value); - if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { - reg_add=((0<<20)|(0<<16)|(over_ride_sub_index<<12)|(0x80)); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++) - { - dwc_window_reg_after_training_update_increas_sub(over_ride_index - ,((over_ride_sub_index)), over_ride_increase_decrease,1) ; - } - } - - if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) - { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0xd0+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - /* - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0xd0+(over_ride_sub_index/4)),delay_reg_value); - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value); - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+offset_value; - if (delay_reg_value>96) - delay_reg_value=96; - } - if (over_ride_increase_decrease == 1) - { - if (delay_reg_value >= offset_value) - delay_reg_value=delay_reg_value-offset_value; - else - delay_reg_value=0; - } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0)); - //dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value|(delay_old_value&0xffc0)); - - // {enable_bit5=(delay_old_value>>5)&1;} - //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value,enable_bit5); - */ - for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++) - { - dwc_window_reg_after_training_update_increas_sub(over_ride_index - ,((over_ride_sub_index)), over_ride_increase_decrease,1) ; - } - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) - { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - /* - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+offset_value; - if (delay_reg_value>96) - delay_reg_value=96; - } - if (over_ride_increase_decrease == 1) - { - if (delay_old_value >= offset_value) - delay_reg_value=delay_reg_value-offset_value; - else - delay_reg_value=0; - } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0)); - dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value|(delay_old_value&0xffc0)); - */ - for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++) - { - dwc_window_reg_after_training_update_increas_sub(over_ride_index - ,((over_ride_sub_index)), over_ride_increase_decrease,1) ; - } - - /* - delay_old_value=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x18c+(over_ride_sub_index/8))); - if (over_ride_increase_decrease == 0) - delay_reg_value=delay_old_value+1; - if (over_ride_increase_decrease == 1) - delay_reg_value=delay_old_value-1; - dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x18c+(over_ride_sub_index/8)),delay_reg_value|(delay_old_value&0xffc0)); - dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x190+(over_ride_sub_index/8)),delay_reg_value|(delay_old_value&0xffc0)); - */ - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) - { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - /* - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+offset_value; - if (delay_reg_value>96) - delay_reg_value=96; - } - if (over_ride_increase_decrease == 1) - { - if (delay_reg_value >= offset_value) - delay_reg_value=delay_reg_value-offset_value; - else - delay_reg_value=0; - } - //delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value)+1; - //if(over_ride_increase_decrease==1) - //delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value)-1; - //dwc_ddrphy_apb_wr(((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))),delay_reg_value|(delay_old_value&0xffc0)); - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - */ - for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++) - { - dwc_window_reg_after_training_update_increas_sub(over_ride_index - ,((over_ride_sub_index)), over_ride_increase_decrease,1) ; - } - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) - { - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - /* - delay_reg_value=delay_old_value; - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+offset_value; - if (delay_reg_value>96) - delay_reg_value=96; - } - if (over_ride_increase_decrease == 1) - { - if (delay_reg_value >= offset_value) - delay_reg_value=delay_reg_value-offset_value; - else - delay_reg_value=0; - } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - */ - for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++) - { - dwc_window_reg_after_training_update_increas_sub(over_ride_index - ,((over_ride_sub_index)), over_ride_increase_decrease,1) ; - } - } - - if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) - { - reg_add=((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x80+(over_ride_sub_index/8))); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - /* - delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+offset_value; - if (delay_reg_value>96) - delay_reg_value=96; - } - if (over_ride_increase_decrease == 1) - { - if (delay_reg_value >= offset_value) - delay_reg_value=delay_reg_value-offset_value; - else - delay_reg_value=0; - } - delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0)); - */ - for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++) - { - dwc_window_reg_after_training_update_increas_sub(over_ride_index - ,((over_ride_sub_index)), over_ride_increase_decrease,1) ; - } - } - if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) - { - //dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value); - //reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36))); - reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40)); - delay_old_value=dwc_ddrphy_apb_rd(reg_add); - /* - delay_reg_value=delay_old_value; - if (over_ride_increase_decrease == 0) - { - delay_reg_value=delay_reg_value+offset_value; - if (delay_reg_value>127) - delay_reg_value=127; - } - if (over_ride_increase_decrease == 1) - { - if (delay_reg_value >= offset_value) - delay_reg_value=delay_reg_value-offset_value; - else - delay_reg_value=0; - } - //delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); - dwc_ddrphy_apb_wr(reg_add,delay_reg_value); - */ - for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++) - { - dwc_window_reg_after_training_update_increas_sub(over_ride_index - ,((over_ride_sub_index)), over_ride_increase_decrease,1) ; - } - } + dwc_ddrphy_apb_wr((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x40), over_ride_value); - printf("over_ride_increase_decrease==%d\n",over_ride_increase_decrease); - - if (over_ride_increase_decrease == 1) - { - unsigned int org_cacl_value=(delay_old_value)&0x3f; - printf("org_cacl_value==%d\n",org_cacl_value); - printf("offset_value==%d\n",offset_value); - if ((org_cacl_value&0x3f)<offset_value) - { - char temp_test_index_2=0; - char temp_count_4=0; - char temp_count_2=0; - #if 0 - if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) - { - temp_test_index_2=DMC_TEST_WINDOW_INDEX_TXDQDLY; - if (over_ride_sub_index%2 == 0) - { - for (temp_count_2=0;temp_count_2<9;temp_count_2++) - { - for (temp_count_4=0;temp_count_4<(offset_value-org_cacl_value);temp_count_4++) - { - dwc_window_reg_after_training_update_increas_sub(temp_test_index_2 - ,((over_ride_sub_index>>1)*9+temp_count_2), 0,1) ; - } - } - } - /* - temp_test_index_2=DMC_TEST_WINDOW_INDEX_TXDQSDLY; - dwc_window_reg_after_training_update_increas_sub(temp_test_index_2 - ,((over_ride_index%2)? - (over_ride_index-1): - (over_ride_index+1)), 0) ; - } - */ - } - #endif - if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) - { - temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXPBDLY; - - for ( temp_count_2=0;temp_count_2<4;temp_count_2++) - for (temp_count_4=0;temp_count_4<(((offset_value-org_cacl_value)*ui_1_32_100step)/bdlr_100step);temp_count_4++) - { - dwc_window_reg_after_training_update_increas_sub(temp_test_index_2 - ,((over_ride_sub_index/2)*9+ - temp_count_2+(over_ride_sub_index%2)*4), 0,1) ; - } - } - - if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) - { - temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXPBDLY; - - for ( temp_count_2=0;temp_count_2<4;temp_count_2++) - { - if (temp_count_2 == ((over_ride_sub_index%9)%4)) - temp_count_2++; - for (temp_count_4=0;temp_count_4<(offset_value-org_cacl_value);temp_count_4++) - dwc_window_reg_after_training_update_increas_sub(temp_test_index_2 - ,((over_ride_sub_index/9)*9+ - temp_count_2+(((over_ride_sub_index%9)>3)?4:0)), 0,1) ; - } - //bdlr_100step (org_cacl_value<offset_value) - if ((((offset_value-org_cacl_value)*bdlr_100step)/ui_1_32_100step)) - { - temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXCLKDLY; - for (temp_count_4=0;temp_count_4<(((offset_value-org_cacl_value)*bdlr_100step)/ui_1_32_100step);temp_count_4++) - dwc_window_reg_after_training_update_increas_sub(temp_test_index_2 - ,(((over_ride_sub_index/9)<<1)+ - (((over_ride_sub_index%9)>3)?1:0) - ), 0,1) ; - } - } - } - } - printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n",((unsigned int)(((reg_add) << 1)+(p_ddr_base->ddr_phy_base_address))), - delay_old_value,dwc_ddrphy_apb_rd(reg_add),ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value), - ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add))); - //ddr_log_serial_puts(" ",0); - //ddr_log_serial_put_hex(delay_reg_value,16,0); - //ddr_log_serial_puts(" ",0); - // ddr_dmc_update_delay_register_after(); + printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n", ((unsigned int)(((reg_add) << 1) + (p_ddr_base->ddr_phy_base_address))), + delay_old_value, dwc_ddrphy_apb_rd(reg_add), ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value), + (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, delay_reg_value)); } -int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +void dwc_window_reg_after_training_update_increas_sub(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease, + uint32_t step_value) +{ + uint32_t delay_old_value = 0; + uint32_t delay_reg_value = 0; + + uint64_t reg_add = 0; + + if (!over_ride_index) + return; + if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + reg_add = ((0 << 20) | (0 << 16) | (over_ride_sub_index << 12) | (0x80)); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); + if (over_ride_increase_decrease == 0) { + delay_reg_value = delay_reg_value + step_value; + if (delay_reg_value > 95) + delay_reg_value = 95; + } + if (over_ride_increase_decrease != 0) { + if (delay_reg_value >= step_value) + delay_reg_value = delay_reg_value - step_value; + else + delay_reg_value = 0; + } + delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); + dwc_ddrphy_apb_wr((reg_add), delay_reg_value); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0xd0 + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + + //some case will happen tdqs from 0x1f to 0x0 or 0x0 to 0x1f ,then fast boot write back will happen error ,because + // fast boot write back will re-calculate coarse UI,then result dq phase fail. + if ((over_ride_sub_index % 2) == 0) { + char temp_test_index = DMC_TEST_WINDOW_INDEX_TXDQDLY; + char temp_count = 0; + { + for (temp_count = 0; temp_count < 9; temp_count++) + dwc_window_reg_after_training_update_increas_dq(temp_test_index + , (((over_ride_sub_index) >> 1) * 9 + temp_count), (!over_ride_increase_decrease), step_value); + } + } + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0xc0 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); + if (over_ride_increase_decrease == 0) { + delay_reg_value = delay_reg_value + step_value; + if (delay_reg_value > 255) + delay_reg_value = 255; + } + if (over_ride_increase_decrease != 0) { + if (delay_reg_value > step_value) + delay_reg_value = delay_reg_value - step_value; + else + delay_reg_value = 0; + } + delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0x8c + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); + if (over_ride_increase_decrease == 0) { + delay_reg_value = delay_reg_value + step_value; + if (delay_reg_value > 95) + delay_reg_value = 95; + } + if (over_ride_increase_decrease != 0) { + if (delay_reg_value > step_value) + delay_reg_value = delay_reg_value - step_value; + else + delay_reg_value = 0; + } + delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); + dwc_ddrphy_apb_wr(reg_add + 4, delay_reg_value); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0x68 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); + if (over_ride_increase_decrease == 0) { + delay_reg_value = delay_reg_value + step_value; + if (delay_reg_value > 63) + delay_reg_value = 63; + } + if (over_ride_increase_decrease != 0) { + if (delay_reg_value > step_value) + delay_reg_value = delay_reg_value - step_value; + else + delay_reg_value = 0; + } + delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value); + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) { + reg_add = ((0 << 20) | (1 << 16) | ((over_ride_sub_index % 8) << 12) | (0x80 + (over_ride_sub_index / 8))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value); + if (over_ride_increase_decrease == 0) { + dwc_ddrphy_apb_wr(reg_add, ((delay_old_value & 0x3f) + step_value) | (delay_old_value & 0xffc0)); + if (((delay_old_value & 0x3f) + step_value) > 0x3f) + dwc_ddrphy_apb_wr(reg_add, 0x3f | (delay_old_value & 0xffc0)); + } else { + dwc_ddrphy_apb_wr(reg_add, ((delay_old_value & 0x3f) - step_value) | (delay_old_value & 0xffc0)); + if (((delay_old_value & 0x3f) < step_value)) + dwc_ddrphy_apb_wr(reg_add, (delay_old_value & 0xffc0)); + } + } + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x40)); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + delay_reg_value = delay_old_value; + if (over_ride_increase_decrease == 0) { + delay_reg_value = delay_reg_value + step_value; + if (delay_reg_value > 127) + delay_reg_value = 127; + } + if (over_ride_increase_decrease != 0) { + if (delay_reg_value >= step_value) + delay_reg_value = delay_reg_value - step_value; + else + delay_reg_value = 0; + } + dwc_ddrphy_apb_wr(reg_add, delay_reg_value); + } + printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n", ((unsigned int)(((reg_add) << 1) + (p_ddr_base->ddr_phy_base_address))), + delay_old_value, dwc_ddrphy_apb_rd(reg_add), ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value), + (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add))); +} + +void dwc_window_reg_after_training_update_increas(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease, + uint32_t offset_value) +{ + uint32_t delay_old_value = 0; + uint32_t temp_count_3 = 0; + uint64_t reg_add = 0; + + if (!over_ride_index) + return; + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + reg_add = ((0 << 20) | (0 << 16) | (over_ride_sub_index << 12) | (0x80)); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + dwc_window_reg_after_training_update_increas_sub(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0xd0 + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + dwc_window_reg_after_training_update_increas_sub(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0x8c + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + dwc_window_reg_after_training_update_increas_sub(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0xc0 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + dwc_window_reg_after_training_update_increas_sub(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0x68 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + dwc_window_reg_after_training_update_increas_sub(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) { + reg_add = ((0 << 20) | (1 << 16) | ((over_ride_sub_index % 8) << 12) | (0x80 + (over_ride_sub_index / 8))); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + dwc_window_reg_after_training_update_increas_sub(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { + reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x40)); + delay_old_value = dwc_ddrphy_apb_rd(reg_add); + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + dwc_window_reg_after_training_update_increas_sub(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + + printf("over_ride_increase_decrease==%d\n", over_ride_increase_decrease); + + if (over_ride_increase_decrease == 1) { + unsigned int org_cacl_value = (delay_old_value) & 0x3f; + printf("org_cacl_value==%d\n", org_cacl_value); + printf("offset_value==%d\n", offset_value); + if ((org_cacl_value & 0x3f) < offset_value) { + char temp_test_index_2 = 0; + char temp_count_4 = 0; + char temp_count_2 = 0; + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + temp_test_index_2 = DMC_TEST_WINDOW_INDEX_RXPBDLY; + + for (temp_count_2 = 0; temp_count_2 < 4; temp_count_2++) { + for (temp_count_4 = 0; temp_count_4 < (((offset_value - org_cacl_value) * ui_1_32_100step) / bdlr_100step); temp_count_4++) { + dwc_window_reg_after_training_update_increas_sub(temp_test_index_2 + , ((over_ride_sub_index / 2) * 9 + + temp_count_2 + (over_ride_sub_index % 2) * 4), 0, 1); + } + } + } + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + temp_test_index_2 = DMC_TEST_WINDOW_INDEX_RXPBDLY; + + for (temp_count_2 = 0; temp_count_2 < 4; temp_count_2++) { + if (temp_count_2 == ((over_ride_sub_index % 9) % 4)) + temp_count_2++; + + for (temp_count_4 = 0; temp_count_4 < (offset_value - org_cacl_value); temp_count_4++) { + dwc_window_reg_after_training_update_increas_sub(temp_test_index_2 + , ((over_ride_sub_index / 9) * 9 + + temp_count_2 + (((over_ride_sub_index % 9) > 3) ? 4 : 0)), 0, 1); + } + } + + if ((((offset_value - org_cacl_value) * bdlr_100step) / ui_1_32_100step)) { + temp_test_index_2 = DMC_TEST_WINDOW_INDEX_RXCLKDLY; + + for (temp_count_4 = 0; temp_count_4 < (((offset_value - org_cacl_value) * bdlr_100step) / ui_1_32_100step); temp_count_4++) { + dwc_window_reg_after_training_update_increas_sub(temp_test_index_2 + , (((over_ride_sub_index / 9) << 1) + + (((over_ride_sub_index % 9) > 3) ? 1 : 0) + ), 0, 1); + } + } + } + } + } + printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n", ((unsigned int)(((reg_add) << 1) + (p_ddr_base->ddr_phy_base_address))), + delay_old_value, dwc_ddrphy_apb_rd(reg_add), ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value), + ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add))); +} + +int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { check_base_address(); - #define DMC_WINDOW_CMD 20180010 //g12_d2pll 1584 0 0 0 0 0x8 - //g12_d2pll 1600 5 0 0x10 1 - //g12_d2pll 1600 0 0 0 0 0x10 0 1 - //g12_d2pll 1400 0 0 0 0 0 0 0 0 1 1200 1900 test ddr frequency - //g12_d2pll 1400 0 0 0 0 0 0 0 0 3 1200 1900 test ddr frequency with EE voltage - //g12_d2pll 1600 0 0 0 0 0 0 0 1 //full test - //g12_d2pll 1600 0 0 0 0 0 0 0 1 0 0 0 872 //full test with 872mv EE - //g12_d2pll 1600 0 0 0 0 0x10 0 3 //only test spec sub_index delay window - //g12_d2pll 1600 cmd_index cmd_para1 cmd_para2.... - //g12_d2pll 1600 0x1 override_option_ac_data_delay_vref override_index over_ride_value - //g12_d2pll 1600 0x2 override plus fulltest - //g12_d2pll 1600 0x3 override plus...other function - //g12_d2pll 1600 0x11 window_test - //g12_d2pll 1600 0x21 frequency table test - //g12_d2pll 1600 0x31 sweep_ee_voltage_frequency table test +#define DMC_WINDOW_CMD 20180010 //g12_d2pll 1584 0 0 0 0 0x8 +#define G12_D2PLL_CMD_DMC_FULL_TEST 0x01 +#define G12_D2PLL_CMD_OVER_RIDE 0x02 +#define G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST 0x03 +#define G12_D2PLL_CMD_OVER_RIDE_TRAINING_HDTL 0x04 +#define G12_D2PLL_CMD_OFFSET 0x06 +#define G12_D2PLL_CMD_WINDOW_TEST 0x11 +#define G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE 0x12 +#define G12_D2PLL_CMD_SUSPEND_TEST 0x21 +#define G12_D2PLL_CMD_SWEEP_EE_VOLTAGE_FREQUENCY_TABLE_TEST 0x32 +#define G12_D2PLL_CMD_DDR_EYE_TEST 0x41 +#define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE 0x42 +#define G12_D2PLL_CMD_DDR_EYE_TEST_DAC1 0x43 +#define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE_DAC1 0x44 +#define G12_D2PLL_CMD_DDR_DVFS_TEST 0x51 - //g12_d2pll 1800 1 //dmc fulltest - //g12_d2pll 1800 2 1 1 1 03 2 2 142 0x11 0 950 override after_training_flag override_index sub_index value override_index2 sub_index2 value2 override_index3 sub_index3 value3 - //override 1 2 3 4 5 0x11 - //g12_d2pll 1800 2 1 0x12 0x1 0x0f6 override_soc_vref pin_index (vref_range<<8)|(vref_value) +#define DMC_TEST_WINDOW_INDEX_ATXDLY 1 +#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2 +#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3 +#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4 +#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5 - //g12_d2pll 1800 4 4/5/a //override_training_hdtl_ctl value - - //g12_d2pll 1800 0x21 //dmc suspend test - //g12_d2pll 1800 0x11 0x1f 0 0 0 10 0x20 //dmc window test mask1 mask2 mask3 sub_index read_bit_init_value(use for very high speed) - //g12_d2pll 1800 0x32 1300 1500 790 820 //dmc sweep freq and ee voltage test frequency_min frequency_max ee_voltage_min ee_voltage_max - //g12_d2pll 1800 0x41 2 0 0xfe 0 0 1 0x01 0 0 1 2 0x100000 //dmc eye_test_enable init_range_0 range0 _value vref_start vref_end - //init_range_2 range2_value vref_start2 vref_end2 pin_index_min pin_index_max test_size - - - #define G12_D2PLL_CMD_DMC_FULL_TEST 0x01 - #define G12_D2PLL_CMD_OVER_RIDE 0x02 - #define G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST 0x03 - #define G12_D2PLL_CMD_OVER_RIDE_TRAINING_HDTL 0x04 - #define G12_D2PLL_CMD_WINDOW_TEST 0x11 - #define G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE 0x12 - #define G12_D2PLL_CMD_SUSPEND_TEST 0x21 - //#define G12_D2PLL_CMD_FREQUENCY_TABLE_TEST 0x31 - #define G12_D2PLL_CMD_SWEEP_EE_VOLTAGE_FREQUENCY_TABLE_TEST 0x32 - #define G12_D2PLL_CMD_DDR_EYE_TEST 0x41 - #define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE 0x42 - #define G12_D2PLL_CMD_DDR_EYE_TEST_DAC1 0x43 - #define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE_DAC1 0x44 - - #define G12_D2PLL_CMD_DDR_DVFS_TEST 0x51 - - //OVERRIDE_OPTION - #define DMC_TEST_WINDOW_INDEX_ATXDLY 1 - #define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2 - #define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3 - #define DMC_TEST_WINDOW_INDEX_TXDQDLY 4 - #define DMC_TEST_WINDOW_INDEX_RXPBDLY 5 - - #define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11 +#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11 char *endp; unsigned int pll; - unsigned int window_test_stick_cmd_value=0; -#if 0 - unsigned int stick_test_cmd_index=0; // 1 override_cmd 2 - unsigned int stick_test_ddr_window_delay_override_enable=0; // bit 0 ac 1 data dqs write 2 data dqs read 3 data bit write 4 data bit read 5//data write vref 6 //data read vref - unsigned int stick_test_ddr_window_delay_override_index=0; - unsigned int stick_test_ddr_window_delay_override_value=0; - unsigned int stick_test_ddr_window_delay_override_before_after_training_setting=0; //0 before ,1 after training - unsigned int stick_dmc_ddr_window_test_enable=0; - unsigned int stick_dmc_ddr_window_test_enable_mask=0; - unsigned int stick_dmc_ddr_window_test_enable_spec_sub_index=0; - unsigned int stick_dmc_ddr_window_test_dmc_full_test_enable=0; - unsigned int stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable=0; - - unsigned int stick_dmc_ddr_bl2_sweep_frequency_min=0; - unsigned int stick_dmc_ddr_bl2_sweep_frequency_max=0; - unsigned int stick_dmc_ddr_bl2_ee_voltage=0; -#endif - //if(window_test_stick_value) - { - //stick_test_ddr_window_delay_override_enable=((window_test_stick_value>>24)&0xf);//bit 0 ac bit1 write dq bit 2 read dq - //stick_test_ddr_window_delay_override_index=((window_test_stick_value>>16)&0xff); - //stick_test_ddr_window_delay_override_value=(window_test_stick_value&0xff); - } + unsigned int window_test_stick_cmd_value = 0; /* need at least two arguments */ + if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D)) + do_read_c2_ddr_bdlr_steps(); if (argc < 2) goto usage; - pll = simple_strtoul(argv[1], &endp,0); + pll = simple_strtoul(argv[1], &endp, 0); if (*argv[1] == 0 || *endp != 0) { - printf ("Error: Wrong format parament!pll=0x%08x\n",pll); + printf("Error: Wrong format parament!pll=0x%08x\n", pll); return 1; } - unsigned int argc_count=1; - unsigned int para_meter[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,}; - while (argc_count<argc) - {para_meter[argc_count-1]= simple_strtoul(argv[argc_count], &endp, 0); - if (*argv[argc_count] == 0 || *endp != 0) { - para_meter[argc_count-1] = 0; - } + unsigned int argc_count = 1; + unsigned int para_meter[30] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; + while (argc_count < argc) { + para_meter[argc_count - 1] = simple_strtoul(argv[argc_count], &endp, 0); + if (*argv[argc_count] == 0 || *endp != 0) + para_meter[argc_count - 1] = 0; argc_count++; } - //if(stick_test_cmd_index==) -#if 0 - if (argc >4) - { - stick_test_ddr_window_delay_override_enable=0; - stick_test_ddr_window_delay_override_enable = simple_strtoul(argv[2], &endp, 0); - if (*argv[2] == 0 || *endp != 0) { - stick_test_ddr_window_delay_override_enable = 0; - } - stick_test_ddr_window_delay_override_index = simple_strtoul(argv[3], &endp, 0); - if (*argv[3] == 0 || *endp != 0) { - stick_test_ddr_window_delay_override_index = 0; - } - stick_test_ddr_window_delay_override_value = simple_strtoul(argv[4], &endp, 0); - if (*argv[4] == 0 || *endp != 0) { - stick_test_ddr_window_delay_override_value = 0; - } - } - else - { stick_test_ddr_window_delay_override_enable=0; - stick_test_ddr_window_delay_override_index = 0; - stick_test_ddr_window_delay_override_value = 0; - } - - if (argc >5) - { - stick_test_ddr_window_delay_override_before_after_training_setting = simple_strtoul(argv[5], &endp, 0); - if (*argv[5] == 0 || *endp != 0) { - stick_test_ddr_window_delay_override_before_after_training_setting = 0; - } - } - if (argc >6) - { - stick_dmc_ddr_window_test_enable = simple_strtoul(argv[6], &endp, 0); - if (*argv[6] == 0 || *endp != 0) { - stick_dmc_ddr_window_test_enable = 0; - } - } - if (argc >7) - { - stick_dmc_ddr_window_test_enable_mask = simple_strtoul(argv[7], &endp, 0); - if (*argv[7] == 0 || *endp != 0) { - stick_dmc_ddr_window_test_enable_mask = 0; - } - } - if (argc >8) - { - stick_dmc_ddr_window_test_enable_spec_sub_index = simple_strtoul(argv[8], &endp, 0); - if (*argv[8] == 0 || *endp != 0) { - stick_dmc_ddr_window_test_enable_spec_sub_index = 0; - } - } - if (argc >9) - { - stick_dmc_ddr_window_test_dmc_full_test_enable = simple_strtoul(argv[9], &endp, 0); - if (*argv[9] == 0 || *endp != 0) { - stick_dmc_ddr_window_test_dmc_full_test_enable = 0; - } - } - if (argc >10) - { - stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable = simple_strtoul(argv[10], &endp, 0); - if (*argv[10] == 0 || *endp != 0) { - stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable = 0; - } - } - if (argc >11) - { - stick_dmc_ddr_bl2_sweep_frequency_min = simple_strtoul(argv[11], &endp, 0); - if (*argv[11] == 0 || *endp != 0) { - stick_dmc_ddr_bl2_sweep_frequency_min = 0; - } - } - if (argc >12) - { - stick_dmc_ddr_bl2_sweep_frequency_max = simple_strtoul(argv[12], &endp, 0); - if (*argv[12] == 0 || *endp != 0) { - stick_dmc_ddr_bl2_sweep_frequency_max = 0; - } - } - if (argc >13) - { - stick_dmc_ddr_bl2_ee_voltage = simple_strtoul(argv[13], &endp, 0); - if (*argv[13] == 0 || *endp != 0) { - stick_dmc_ddr_bl2_ee_voltage = 0; - } - } - - -#if defined(CONFIG_M6TV) || defined(CONFIG_M6TVD) - wr_reg( (p_ddr_base->preg_sticky_reg0),0 | (0x3c << 24)); -#else - wr_reg((p_ddr_base->preg_sticky_reg0),0 | (0xf13 << 20)); -#endif - - if (stick_dmc_ddr_window_test_enable) - { - wr_reg((p_ddr_base->preg_sticky_reg0),((stick_dmc_ddr_window_test_enable_spec_sub_index&0xff)<<8)|(stick_dmc_ddr_window_test_enable&0xff) | (0xf12<< 20)); - } - //wr_reg(PREG_STICKY_REG1,pll | (rd_reg(PREG_STICKY_REG1))); - wr_reg(PREG_STICKY_REG1,pll ); - wr_reg(PREG_STICKY_REG2,(stick_test_ddr_window_delay_override_value&0xffff) |((stick_test_ddr_window_delay_override_index&0xff)<<16) - |((stick_test_ddr_window_delay_override_enable&0x7)<<29) - |((stick_test_ddr_window_delay_override_before_after_training_setting&0x1)<<28)); - if (stick_dmc_ddr_window_test_enable_mask) - { - wr_reg(PREG_STICKY_REG3,(stick_dmc_ddr_window_test_enable_mask)); - } - // if(stick_dmc_ddr_window_test_dmc_full_test_enable) - { - wr_reg(PREG_STICKY_REG4,(stick_dmc_ddr_window_test_dmc_full_test_enable<<31)|(stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable<<29)); - } - if (stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable) - { - wr_reg(PREG_STICKY_REG5,(stick_dmc_ddr_bl2_sweep_frequency_min<<0)|(stick_dmc_ddr_bl2_sweep_frequency_max<<16)); - } - if (stick_dmc_ddr_bl2_ee_voltage) - { - wr_reg(PREG_STICKY_REG6,(stick_dmc_ddr_bl2_ee_voltage<<0)); - } -#endif - argc_count=2; - window_test_stick_cmd_value=para_meter[argc_count-1]; - if ((window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE) || (window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST)) - { - para_meter[3]=(para_meter[3]<<24)|(para_meter[4]<<16)|(para_meter[5]<<0); - para_meter[4]=(para_meter[6]<<24)|(para_meter[7]<<16)|(para_meter[8]<<0); - para_meter[5]=(para_meter[9]<<24)|(para_meter[10]<<16)|(para_meter[11]<<0); + argc_count = 2; + window_test_stick_cmd_value = para_meter[argc_count - 1]; + if ((window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE) || (window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST)) { + para_meter[3] = (para_meter[3] << 24) | (para_meter[4] << 16) | (para_meter[5] << 0); + para_meter[4] = (para_meter[6] << 24) | (para_meter[7] << 16) | (para_meter[8] << 0); + para_meter[5] = (para_meter[9] << 24) | (para_meter[10] << 16) | (para_meter[11] << 0); } if ((window_test_stick_cmd_value == G12_D2PLL_CMD_WINDOW_TEST) || (window_test_stick_cmd_value == G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE)) - { - //para_meter[8] size 9 stick_dmc_ddr_window_test_no_use_dqs_dq_correction 10 disable_scramble_use_define_pattern 11 stick_dmc_window_test_loop_flag window loop test - //12 if reinit when test dq 13 pass_to_fail_flag 14 test_dmc_or_cpu - para_meter[5]=(para_meter[9]<<28)|(para_meter[10]<<24)|(para_meter[11]<<20)|(para_meter[12]<<21)|(para_meter[13]<<22)|(para_meter[14]<<25)|(para_meter[5]<<0); + para_meter[5] = (para_meter[9] << 28) | (para_meter[10] << 24) | (para_meter[11] << 20) | (para_meter[12] << 21) | (para_meter[13] << 22) | (para_meter[14] << 25) | (para_meter[5] << 0); + if ((window_test_stick_cmd_value >= G12_D2PLL_CMD_DDR_EYE_TEST) && (window_test_stick_cmd_value <= G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE_DAC1)) { + para_meter[3] = (para_meter[3] << 0) | (para_meter[4] << 8) | (para_meter[5] << 16) | (para_meter[6] << 24); + para_meter[4] = (para_meter[7] << 0) | (para_meter[8] << 8) | (para_meter[9] << 16) | (para_meter[10] << 24); + para_meter[5] = para_meter[11]; //(para_meter[11]<<0)|(para_meter[12]<<8)|(para_meter[13]<<16)|(para_meter[14]<<24); + para_meter[6] = para_meter[12]; //para_meter[15]; + para_meter[7] = para_meter[13]; //para_meter[16]; + para_meter[8] = para_meter[14]; //para_meter[17]; } - if ((window_test_stick_cmd_value >= G12_D2PLL_CMD_DDR_EYE_TEST)&& (window_test_stick_cmd_value <= G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE_DAC1)) - { - para_meter[3]=(para_meter[3]<<0)|(para_meter[4]<<8)|(para_meter[5]<<16)|(para_meter[6]<<24); - para_meter[4]=(para_meter[7]<<0)|(para_meter[8]<<8)|(para_meter[9]<<16)|(para_meter[10]<<24); - para_meter[5]=para_meter[11];//(para_meter[11]<<0)|(para_meter[12]<<8)|(para_meter[13]<<16)|(para_meter[14]<<24); - para_meter[6]=para_meter[12];//para_meter[15]; - para_meter[7]=para_meter[13];//para_meter[16]; - para_meter[8]=para_meter[14];//para_meter[17]; - } - wr_reg((p_ddr_base->preg_sticky_reg0),(rd_reg((p_ddr_base->preg_sticky_reg0))&0xffff) | (0xf13 << 20)); - argc_count=0; - printf("\nP_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count,((p_ddr_base->preg_sticky_reg0)+(argc_count<<2)),rd_reg((p_ddr_base->preg_sticky_reg0)+(argc_count<<2))); - argc_count=1; - //while(argc_count<argc) - while (argc_count<10) - { - wr_reg((p_ddr_base->preg_sticky_reg0)+(argc_count<<2),para_meter[argc_count-1]); - printf("P_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count,((p_ddr_base->preg_sticky_reg0)+(argc_count<<2)),rd_reg((p_ddr_base->preg_sticky_reg0)+(argc_count<<2))); + wr_reg((p_ddr_base->preg_sticky_reg0), (rd_reg((p_ddr_base->preg_sticky_reg0)) & 0xffff) | (0xf13 << 20)); + argc_count = 0; + printf("\nP_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count, ((p_ddr_base->preg_sticky_reg0) + (argc_count << 2)), rd_reg((p_ddr_base->preg_sticky_reg0) + (argc_count << 2))); + argc_count = 1; + while (argc_count < 10) { + wr_reg((p_ddr_base->preg_sticky_reg0) + (argc_count << 2), para_meter[argc_count - 1]); + printf("P_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count, ((p_ddr_base->preg_sticky_reg0) + (argc_count << 2)), rd_reg((p_ddr_base->preg_sticky_reg0) + (argc_count << 2))); argc_count++; } - /* - printf("P_(p_ddr_base->preg_sticky_reg0) [0x%08x]\n", rd_reg((p_ddr_base->preg_sticky_reg0))); - printf("P_(p_ddr_base->preg_sticky_reg0+4) [0x%08x]\n", rd_reg((p_ddr_base->preg_sticky_reg0+4))); - printf("P_PREG_STICKY_REG2 [0x%08x]\n", rd_reg(PREG_STICKY_REG2)); - printf("P_PREG_STICKY_REG3 [0x%08x]\n", rd_reg(PREG_STICKY_REG3)); - printf("P_PREG_STICKY_REG4 [0x%08x]\n", rd_reg(PREG_STICKY_REG4)); - printf("P_PREG_STICKY_REG5 [0x%08x]\n", rd_reg(PREG_STICKY_REG5)); - printf("P_PREG_STICKY_REG6 [0x%08x]\n", rd_reg(PREG_STICKY_REG6)); - */ - printf("reset...\n"); dcache_disable(); - //if ((p_ddr_base->sys_watchdog_base_address) == 0) - run_command("reset",0); - ddr_test_watchdog_reset_system(); + if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_A1) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C1) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_SC2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7) + //|| (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D) + ) { + printf("reset...\n"); + run_command("reset", 0); + } else { //G12A/G12B/SM1/TL1/TM2 + printf("reboot...\n"); //reset will enter bl2 panic path,so change to "reboot" + run_command("reboot", 0); + //ddr_test_watchdog_reset_system(); + } return 0; @@ -9969,340 +8747,491 @@ return 1; } - U_BOOT_CMD( - g12_d2pll, 18, 1, do_ddr2pll_g12_cmd, + g12_d2pll, 18, 1, do_ddr2pll_g12_cmd, "g12_d2pll 1300 1 0x10 0", "g12_d2pll clk delay_index delay_value before_after_training_setting\n" -); + ); #endif -#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12) +#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12) -int do_ddr_g12_override_data(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_g12_override_data(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { -check_base_address(); - //ddr_test_cmd 0x25 1 1 10 10 10 10 10 10 10 10 10 10 - + check_base_address(); +#define DMC_PHY_RETRAINING_CTRL (p_ddr_base->ddr_dmc_lpdd4_retraining_address) + uint32_t dmc_retraining_ctrl = 0; + dmc_retraining_ctrl = rd_reg(DMC_PHY_RETRAINING_CTRL); + unsigned int ddr_dmc_apd_temp_save, ddr_dmc_asr_temp_save; + ddr_dmc_apd_temp_save = readl((p_ddr_base->ddr_dmc_apd_address)); + ddr_dmc_asr_temp_save = readl((p_ddr_base->ddr_dmc_asr_address)); printf("\12nm phy read write register should closd apd and asr funciton\n"); - writel((0), p_ddr_base->ddr_dmc_apd_address); - writel((0), p_ddr_base->ddr_dmc_asr_address); + #define G12_DATA_READ_OFFSET_MAX (0X3F) -#define G12_DATA_WRITE_OFFSET_MAX (0X3F+7*32) +#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32) #if 1 - // if(!argc) - // goto DDR_TUNE_DQS_START; - int i=0; + int i = 0; printf("\nargc== 0x%08x\n", argc); - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); char *endp; //rank_index dq_index write_read left/right offset_value - unsigned int test_index=0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq - unsigned int dq_index=0; //0-8 rank0 lane0 ,rank0 9-17 lane1,rank0 18-26 lane2, rank0 27-35 lane3, 36+0-8 rank1 lane0 ,rank1 36+9-17 lane1,rank1 36+18-26 lane2, rank1 36+27-35 lane3 - // unsigned int test_dq_mask_1=0; //each bit mask corresspond with dq_index - // unsigned int test_dq_mask_2=0; //each bit mask corresspond with dq_index - // unsigned int test_dq_mask_3=0; //each bit mask corresspond with dq_index - //unsigned int write_read_flag=0;// 2 write ,1 read #define DDR_PARAMETER_READ 1 #define DDR_PARAMETER_WRITE 2 - // unsigned int left_right_flag=0;// 1 left ,2 right #define DDR_PARAMETER_LEFT 1 #define DDR_PARAMETER_RIGHT 2 - unsigned int ovrride_value=0;// + unsigned int test_index = 0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq + unsigned int dq_index = 0; //0-8 rank0 lane0 ,rank0 9-17 lane1,rank0 18-26 lane2, rank0 27-35 lane3, 36+0-8 rank1 lane0 ,rank1 36+9-17 lane1,rank1 36+18-26 lane2, rank1 36+27-35 lane3 + unsigned int ovrride_value = 0; // - // unsigned int offset_enable=0;// + unsigned int count = 0; + unsigned int lcdlr_max = 0; - // unsigned int temp_value=0;// - unsigned int count=0; - // unsigned int count1=0; - // unsigned int count_max=0; - unsigned int lcdlr_max=0; - // unsigned int reg_add=0; - // unsigned int reg_value=0; - - if (argc == 1) - { + if (argc == 1) { printf("\nplease read help\n"); - } - else if (argc >4) - {//offset_enable=1; - + } else if (argc > 4) { //offset_enable=1; { - count=0; - test_index= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + count = 0; + test_index = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) test_index = 0; - } - } { count++; - dq_index= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + dq_index = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) dq_index = 0; - } - } - - { count++; - ovrride_value= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + ovrride_value = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) ovrride_value = 0; - } - } - - - } - else { + } else { return 1; } - printf("lcdlr_max %d,\n",lcdlr_max); + printf("lcdlr_max %d,\n", lcdlr_max); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl & (~(1 << 31))); + writel((0), p_ddr_base->ddr_dmc_apd_address); + writel((0), p_ddr_base->ddr_dmc_asr_address); { - - - { - - { - dwc_window_reg_after_training_update(test_index, - dq_index, - ovrride_value); - } - - } + dwc_window_reg_after_training_update(test_index, dq_index, ovrride_value); } - #endif + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address); + writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address); return 1; } U_BOOT_CMD( - ddr_g12_override_data, 20, 1, do_ddr_g12_override_data, + ddr_g12_override_data, 20, 1, do_ddr_g12_override_data, "ddr_g12_override_data 1 0 0 0 1 3", "ddr_g12_override_data test_index dq_index ovrride_value \n" -); -int do_ddr_g12_offset_data(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) + ); + +void ddr_window_reg_after_training_update_increas_sub_c2(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease, uint32_t step) { -check_base_address(); - //ddr_g12_offset_data 1 0 0 0 1 3 + uint32_t delay_old_value = 0; + uint32_t delay_reg_value = 0; + uint32_t ps = 0; + if (!over_ride_index) + return; + if (over_ride_index <=DMC_TEST_WINDOW_INDEX_DRAM_VREF) { + delay_old_value = ddr_phy_training_reg_read_write(ddr_set_t_p, over_ride_index, over_ride_sub_index, delay_old_value, REGISTER_READ, ps); + if (over_ride_increase_decrease == 0) + delay_reg_value = delay_old_value + step; + if (over_ride_increase_decrease != 0) { + if (delay_old_value > step) + delay_reg_value = delay_old_value - step; + else + delay_reg_value = 0; + } -#define G12_DATA_READ_OFFSET_MAX (0X3F) -#define G12_DATA_WRITE_OFFSET_MAX (0X3F+7*32) - printf("\12nm phy read write register should closd apd and asr funciton\n"); - writel((0), p_ddr_base->ddr_dmc_apd_address); - writel((0), p_ddr_base->ddr_dmc_asr_address); -#if 1 - // if(!argc) - // goto DDR_TUNE_DQS_START; - int i=0; - printf("\nargc== 0x%08x\n", argc); - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); + ddr_phy_training_reg_read_write(ddr_set_t_p, over_ride_index, over_ride_sub_index, delay_reg_value, REGISTER_WRITE, + ps); } +} + +void dwc_window_reg_after_training_update_increas_c2(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease, + uint32_t offset_value) +{ + uint32_t temp_count_3 = 0; + + if (!over_ride_index) + return; + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) { + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } + + if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { + for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++) + ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index + , ((over_ride_sub_index)), over_ride_increase_decrease, 1); + } +} + +int do_ddr_c2_offset_data(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + check_base_address(); + + #define DMC_PHY_RETRAINING_CTRL (p_ddr_base->ddr_dmc_lpdd4_retraining_address) + uint32_t dmc_retraining_ctrl = 0; + dmc_retraining_ctrl = rd_reg(DMC_PHY_RETRAINING_CTRL); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl & (~(1 << 31))); + unsigned int ddr_dmc_apd_temp_save, ddr_dmc_asr_temp_save; + ddr_dmc_apd_temp_save = readl(p_ddr_base->ddr_dmc_apd_address); + ddr_dmc_asr_temp_save = readl(p_ddr_base->ddr_dmc_asr_address); +#define G12_DATA_READ_OFFSET_MAX (0X3F) +#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32) + printf("\12nm phy read write register should closd apd and asr funciton\n"); + int i = 0; + + printf("\nargc== 0x%08x\n", argc); + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); char *endp; //rank_index dq_index write_read left/right offset_value - unsigned int test_index=0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq - //unsigned int dq_index=0; //0-8 rank0 lane0 ,rank0 9-17 lane1,rank0 18-26 lane2, rank0 27-35 lane3, 36+0-8 rank1 lane0 ,rank1 36+9-17 lane1,rank1 36+18-26 lane2, rank1 36+27-35 lane3 - unsigned int test_dq_mask_1=0; //each bit mask corresspond with dq_index - unsigned int test_dq_mask_2=0; //each bit mask corresspond with dq_index - unsigned int test_dq_mask_3=0; //each bit mask corresspond with dq_index - //unsigned int write_read_flag=0;// 2 write ,1 read #define DDR_PARAMETER_READ 1 #define DDR_PARAMETER_WRITE 2 - unsigned int left_right_flag=0;// 1 left ,2 right #define DDR_PARAMETER_LEFT 1 #define DDR_PARAMETER_RIGHT 2 - unsigned int offset_value=0;// + unsigned int test_index = 0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq + unsigned int test_dq_mask_1 = 0; //each bit mask corresspond with dq_index + unsigned int test_dq_mask_2 = 0; //each bit mask corresspond with dq_index + unsigned int test_dq_mask_3 = 0; //each bit mask corresspond with dq_index + unsigned int left_right_flag = 0; // 1 left ,2 right #define DDR_PARAMETER_LEFT 1 #define DDR_PARAMETER_RIGHT 2 + unsigned int offset_value = 0; // + unsigned int count = 0; + unsigned int count_max = 0; + unsigned int lcdlr_max = 0; - //unsigned int offset_enable=0;// + global_ddr_clk = get_ddr_clk(); + bdlr_100step = get_bdlr_100step(global_ddr_clk); + ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32)); - //unsigned int temp_value=0;// - unsigned int count=0; - //unsigned int count1=0; - unsigned int count_max=0; - unsigned int lcdlr_max=0; - //unsigned int reg_add=0; - //unsigned int reg_value=0; - - global_ddr_clk=get_ddr_clk(); - bdlr_100step=get_bdlr_100step(global_ddr_clk); - //global_ddr_clk=768; - ui_1_32_100step=(1000000*100/(global_ddr_clk*2*32)); - - if (argc == 1) - { - printf("\nplease read help\n"); - } - else if (argc >6) - {//offset_enable=1; - + if (argc == 1) { + printf("\nplease read aml phy cmd help\n"); + } else if (argc > 6) { //offset_enable=1; { - count=0; - test_index= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + count = 0; + test_index = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) test_index = 0; - } - } { count++; - test_dq_mask_1= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + test_dq_mask_1 = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) test_dq_mask_1 = 0; - } - } { count++; - test_dq_mask_2= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + test_dq_mask_2 = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) test_dq_mask_2 = 0; - } - } { count++; - test_dq_mask_3= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + test_dq_mask_3 = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) test_dq_mask_3 = 0; - } - } { count++; - left_right_flag= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + left_right_flag = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) left_right_flag = 0; - } - } { count++; - offset_value= simple_strtoull_ddr(argv[count+1], &endp, 0); - if (*argv[count+1] == 0 || *endp != 0) - { + offset_value = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) offset_value = 0; - } - } - - - } - else { + } else { + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); return 1; } - printf("lcdlr_max %d,\n",lcdlr_max); + printf("lcdlr_max %d,\n", lcdlr_max); if (left_right_flag == DDR_PARAMETER_RIGHT) - printf("offset right ++ left_right_flag %d,\n",left_right_flag); + printf("offset right ++ left_right_flag %d,\n", left_right_flag); if (left_right_flag == DDR_PARAMETER_LEFT) - printf("offset left --left_right_flag %d,\n",left_right_flag); + printf("offset left --left_right_flag %d,\n", left_right_flag); if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { - count_max=10; - - lcdlr_max=3*32;//0x3ff; + count_max = 36; + lcdlr_max = 4 * 128 - 1; //0x3ff; } - if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { - count_max=16; - - lcdlr_max=16*32;//0x3ff; + count_max = 8; + lcdlr_max = 4 * 128 - 1; //0x3ff; } if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { - count_max=16; - lcdlr_max=96;//0x3f; + count_max = 8; + lcdlr_max = 255; //0x3f; } + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { - count_max=36*2; - lcdlr_max=8*32;//0x1ff; + count_max = 36 * 2; + lcdlr_max = 8 * 128 - 1; //0x1ff; } + if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { - count_max=36*2; - lcdlr_max=0x3f; + count_max = 36 * 2; + lcdlr_max = 255; } if (test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { - count_max=36*1; - lcdlr_max=0x3f; + count_max = 36 * 1; + lcdlr_max = 0x3f; printf(" soc vref rank0 and rank1 share vref dac\n"); } + count = 0; + writel((0), p_ddr_base->ddr_dmc_apd_address); + writel((0), p_ddr_base->ddr_dmc_asr_address); - - count=0; - for (;count<count_max;count++) { - if ((count<32)) { - if (test_dq_mask_1&(1<<(count%32))) { + for (; count < count_max; count++) { + if ((count < 32)) { + if (test_dq_mask_1 & (1 << (count % 32))) continue; - } - } - if ((count>31) && (count<63)) { - if (test_dq_mask_2&(1<<(count%32))) { - continue; - } - } - if ((count>63)) { - if (test_dq_mask_3&(1<<(count%32))) { - continue; - } } - // for (count1=0;count1<offset_value;count1++) + if ((count > 31) && (count < 63)) { + if (test_dq_mask_2 & (1 << (count % 32))) + continue; + } + + if ((count > 63)) { + if (test_dq_mask_3 & (1 << (count % 32))) + continue; + } { - if (left_right_flag == DDR_PARAMETER_RIGHT) - { - dwc_window_reg_after_training_update_increas(test_index, - count, - 0,offset_value); + if (left_right_flag == DDR_PARAMETER_RIGHT) { + dwc_window_reg_after_training_update_increas_c2(test_index, + count, + 0, offset_value); } - if (left_right_flag == DDR_PARAMETER_LEFT) - { + if (left_right_flag == DDR_PARAMETER_LEFT) { + dwc_window_reg_after_training_update_increas_c2(test_index, + count, + 1, offset_value); + } + } + } + writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address); + writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; +} + +int do_ddr_g12_offset_data(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + //ddr_g12_offset_data 1 0 0 0 1 3 + check_base_address(); + + if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) + || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D)) { + do_ddr_c2_offset_data(cmdtp, flag, argc, argv); + return 1; + } +#define DMC_PHY_RETRAINING_CTRL (p_ddr_base->ddr_dmc_lpdd4_retraining_address) + uint32_t dmc_retraining_ctrl = 0; + dmc_retraining_ctrl = rd_reg(DMC_PHY_RETRAINING_CTRL); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl & (~(1 << 31))); + unsigned int ddr_dmc_apd_temp_save, ddr_dmc_asr_temp_save; + ddr_dmc_apd_temp_save = readl(p_ddr_base->ddr_dmc_apd_address); + ddr_dmc_asr_temp_save = readl(p_ddr_base->ddr_dmc_asr_address); +#define G12_DATA_READ_OFFSET_MAX (0X3F) +#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32) + printf("\12nm phy read write register should closd apd and asr funciton\n"); + + int i = 0; + printf("\nargc== 0x%08x\n", argc); + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); + char *endp; + //rank_index dq_index write_read left/right offset_value + unsigned int test_index = 0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq + unsigned int test_dq_mask_1 = 0; //each bit mask corresspond with dq_index + unsigned int test_dq_mask_2 = 0; //each bit mask corresspond with dq_index + unsigned int test_dq_mask_3 = 0; //each bit mask corresspond with dq_index + unsigned int left_right_flag = 0; // 1 left ,2 right #define DDR_PARAMETER_LEFT 1 #define DDR_PARAMETER_RIGHT 2 + unsigned int offset_value = 0; // + unsigned int count = 0; + unsigned int count_max = 0; + unsigned int lcdlr_max = 0; + + global_ddr_clk = get_ddr_clk(); + bdlr_100step = get_bdlr_100step(global_ddr_clk); + ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32)); + + if (argc == 1) { + printf("\nplease read help\n"); + } else if (argc > 6) { //offset_enable=1; + { + count = 0; + test_index = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) + test_index = 0; + } + { + count++; + test_dq_mask_1 = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) + test_dq_mask_1 = 0; + } + { + count++; + test_dq_mask_2 = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) + test_dq_mask_2 = 0; + } + { + count++; + test_dq_mask_3 = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) + test_dq_mask_3 = 0; + } + { + count++; + left_right_flag = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) + left_right_flag = 0; + } + { + count++; + offset_value = simple_strtoull_ddr(argv[count + 1], &endp, 0); + if (*argv[count + 1] == 0 || *endp != 0) + offset_value = 0; + } + } else { + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } + printf("lcdlr_max %d,\n", lcdlr_max); + if (left_right_flag == DDR_PARAMETER_RIGHT) + printf("offset right ++ left_right_flag %d,\n", left_right_flag); + if (left_right_flag == DDR_PARAMETER_LEFT) + printf("offset left --left_right_flag %d,\n", left_right_flag); + if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) { + count_max = 10; + lcdlr_max = 3 * 32; //0x3ff; + } + + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) { + count_max = 16; + lcdlr_max = 16 * 32; //0x3ff; + } + if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) { + count_max = 16; + lcdlr_max = 96; //0x3f; + } + if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) { + count_max = 36 * 2; + lcdlr_max = 8 * 32; //0x1ff; + } + if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) { + count_max = 36 * 2; + lcdlr_max = 0x3f; + } + if (test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) { + count_max = 36 * 1; + lcdlr_max = 0x3f; + printf(" soc vref rank0 and rank1 share vref dac\n"); + } + + count = 0; + writel((0), p_ddr_base->ddr_dmc_apd_address); + writel((0), p_ddr_base->ddr_dmc_asr_address); + + for (; count < count_max; count++) { + if ((count < 32)) { + if (test_dq_mask_1 & (1 << (count % 32))) + continue; + } + + if ((count > 31) && (count < 63)) { + if (test_dq_mask_2 & (1 << (count % 32))) + continue; + } + + if ((count > 63)) { + if (test_dq_mask_3 & (1 << (count % 32))) + continue; + } + { + if (left_right_flag == DDR_PARAMETER_RIGHT) { dwc_window_reg_after_training_update_increas(test_index, - count, - 1,offset_value); + count, + 0, offset_value); + } + if (left_right_flag == DDR_PARAMETER_LEFT) { + dwc_window_reg_after_training_update_increas(test_index, + count, + 1, offset_value); } } } - -#endif + writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address); + writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); return 1; } - U_BOOT_CMD( - ddr_g12_offset_data, 20, 1, do_ddr_g12_offset_data, + ddr_g12_offset_data, 20, 1, do_ddr_g12_offset_data, "ddr_g12_offset_data 1 0 0 0 1 3", "ddr_g12_offset_data test_index mask1 mask2 mask3 left/right offset_value \n" -); + ); #endif - -//char CMD_VER[] = "Ver_11"; -int do_ddr_test_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_test_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { check_base_address(); - //ddr_test_watchdog_init(4000); - //printf("\nopen watchdog %dms\n",4000); + #define DMC_PHY_RETRAINING_CTRL (p_ddr_base->ddr_dmc_lpdd4_retraining_address) + uint32_t dmc_retraining_ctrl = 0; + dmc_retraining_ctrl = rd_reg(DMC_PHY_RETRAINING_CTRL); + unsigned int ddr_dmc_apd_temp_save, ddr_dmc_asr_temp_save; + ddr_dmc_apd_temp_save = readl(p_ddr_base->ddr_dmc_apd_address); + ddr_dmc_asr_temp_save = readl(p_ddr_base->ddr_dmc_asr_address); + printf("\n ddr test cmd version== %s\n", CMD_VER); - //printf("DDR test code build time:=="); - //printf(__DATE__); - //printf(__TIME__); printf("\nargc== 0x%08x\n", argc); - int i ; - for (i = 0;i<argc;i++) - printf("\nargv[%d]=%s\n",i,argv[i]); + int i; + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); /* need at least two arguments */ if (argc < 2) @@ -10310,18 +9239,11 @@ if ((strcmp(argv[1], "h") == 0)) goto usage; -#if 1// ( CONFIG_DDR_PHY >= P_DDR_PHY_G12) printf("\12nm phy read write register should closd apd and asr funciton\n"); - writel((0), p_ddr_base->ddr_dmc_apd_address); - writel((0), p_ddr_base->ddr_dmc_asr_address); - - - global_ddr_clk=get_ddr_clk(); + global_ddr_clk = get_ddr_clk(); printf("\nddr_clk== %dMHz\n", global_ddr_clk); -#endif - #define DDR_TEST_CMD__NONE 0 #define DDR_TEST_CMD__DDR_TEST 1 #define DDR_TEST_CMD__DDR_TUNE_ACLCDLR 2 @@ -10371,872 +9293,1004 @@ #define DDR_TEST_CMD__DDR_G12_DMC_TEST 0x38 #define DDR_TEST_CMD__DDR_G12_EE_BDLR_TEST 0x39 - unsigned int ddr_test_cmd=0; - unsigned int arg[30]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}; + unsigned int ddr_test_cmd = 0; + unsigned int arg[30] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; char *endp; ddr_test_cmd = simple_strtoull_ddr(argv[1], &endp, 0); - for (i = 2;i<argc;i++) - arg[i-2]=simple_strtoull_ddr(argv[i], &endp, 0); + for (i = 2; i < argc; i++) + arg[i - 2] = simple_strtoull_ddr(argv[i], &endp, 0); printf("\nddr_test_cmd== 0x%08x\n", ddr_test_cmd); - for (i = 0;i<(argc-2);i++) - printf("\narg[%08x]=%08x\n",i,arg[i]); - //int argc2_length; - //argc2_length=(argc-2); - //cmd_tbl_t *cmdtp2; - //int flag2; - int argc2; - char* argv2[30]; + for (i = 0; i < (argc - 2); i++) + printf("\narg[%08x]=%08x\n", i, arg[i]); - argc2=argc-1; - for (i = 1;i<(argc);i++) - argv2[i-1]=argv[i]; - //argv2=(char *)argv++; + int argc2; + char *argv2[30]; + + argc2 = argc - 1; + for (i = 1; i < (argc); i++) + argv2[i - 1] = argv[i]; { - run_command("dcache off",0); - run_command("dcache on",0); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl & (~(1 << 31))); + writel((0), p_ddr_base->ddr_dmc_apd_address); + writel((0), p_ddr_base->ddr_dmc_asr_address); + run_command("dcache off", 0); + run_command("dcache on", 0); printf("\n cache off on"); - switch (ddr_test_cmd) - {case(DDR_TEST_CMD__NONE): - { - printf("\n 0x0 help\n"); - printf("\n 0x1 ddrtest ddr_test_cmd 0x1 start_add test_size loops "); - printf("\n 0x2 test aclcdlr ddr_test_cmd 0x2 start_add test_size loops ddr_test_cmd 0x2 a 0 0x8000000 1"); - printf("\n 0x3 test max_pllclk ddr_test_cmd 0x3 test_size loops add_freq sub_freq "); - printf("\n 0x4 test zq ddr_test_cmd 0x4 test_size loops add_freq sub_freq drv_odt_flag "); - printf("\n 0x5 test vref ddr_test_cmd 0x5 "); - printf("\n 0x6 test gxtvbb_crosstalk ddr_test_cmd 0x6 loops pattern_flag "); - printf("\n 0x7 test bandwidth ddr_test_cmd 0x7 size loops port sub_id timer_ms "); - printf("\n 0x8 test lcdlr_use_env_uart ddr_test_cmd 0x8 input_src wr_adj_per[] rd_adj_per[][] "); - printf("\n 0x9 test_reg_use_mask ddr_test_cmd 0x9 reg_add value mask "); - printf("\n 0xa test ac_clk ddr_test_cmd 0xa start_add test_size loops ddr_test_cmd 0xa a 0 0x8000000 1 "); - printf("\n 0xb ... "); - printf("\n 0xc ... "); - printf("\n 0xd ... "); - printf("\n 0xe ... "); - printf("\n 0xf ... "); - printf("\n 0x10 test set zq ddr_test_cmd 0x10 zq0pr0 zq1pr0 zq2pr0 "); - printf("\n 0x11 test tune dqs ddr_test_cmd 0x11 a 0 test_size ddr_test_cmd 0x11 a 0 0x80000"); - printf("\n 0x12 test set start_add ddr_test_cmd 0x12 start_add "); - printf("\n 0x13 test ac_bit_setup_hold time ddr_test_cmd 0x13 a 0 size method pin_id ddr_test_cmd 0x13 a 0 0x8000000 0 0xc"); - printf("\n 0x14 test data_bit_setup_hold time ddr_test_cmd 0x14 a 0 size setup/hold pin_id ddr_test_cmd 0x14 a 0 0x80000 0 3 "); - printf("\n 0x15 test ac_lane_setup_hold ddr_test_cmd 0x15 a 0 size "); - printf("\n 0x16 test ee mdlr ddr_test_cmd 0x16 voltage pwm_id loops "); - printf("\n 0x17 d2pll ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n \ + switch (ddr_test_cmd) { + case (DDR_TEST_CMD__NONE): + { + printf("\n 0x0 help\n"); + printf("\n 0x1 ddrtest ddr_test_cmd 0x1 start_add test_size loops "); + printf("\n 0x2 test aclcdlr ddr_test_cmd 0x2 start_add test_size loops ddr_test_cmd 0x2 a 0 0x8000000 1"); + printf("\n 0x3 test max_pllclk ddr_test_cmd 0x3 test_size loops add_freq sub_freq "); + printf("\n 0x4 test zq ddr_test_cmd 0x4 test_size loops add_freq sub_freq drv_odt_flag "); + printf("\n 0x5 test vref ddr_test_cmd 0x5 "); + printf("\n 0x6 test gxtvbb_crosstalk ddr_test_cmd 0x6 loops pattern_flag "); + printf("\n 0x7 test bandwidth ddr_test_cmd 0x7 size loops port sub_id timer_ms "); + printf("\n 0x8 test lcdlr_use_env_uart ddr_test_cmd 0x8 input_src wr_adj_per[] rd_adj_per[][] "); + printf("\n 0x9 test_reg_use_mask ddr_test_cmd 0x9 reg_add value mask "); + printf("\n 0xa test ac_clk ddr_test_cmd 0xa start_add test_size loops ddr_test_cmd 0xa a 0 0x8000000 1 "); + printf("\n 0xb ... "); + printf("\n 0xc ... "); + printf("\n 0xd ... "); + printf("\n 0xe ... "); + printf("\n 0xf ... "); + printf("\n 0x10 test set zq ddr_test_cmd 0x10 zq0pr0 zq1pr0 zq2pr0 "); + printf("\n 0x11 test tune dqs ddr_test_cmd 0x11 a 0 test_size ddr_test_cmd 0x11 a 0 0x80000"); + printf("\n 0x12 test set start_add ddr_test_cmd 0x12 start_add "); + printf("\n 0x13 test ac_bit_setup_hold time ddr_test_cmd 0x13 a 0 size method pin_id ddr_test_cmd 0x13 a 0 0x8000000 0 0xc"); + printf("\n 0x14 test data_bit_setup_hold time ddr_test_cmd 0x14 a 0 size setup/hold pin_id ddr_test_cmd 0x14 a 0 0x80000 0 3 "); + printf("\n 0x15 test ac_lane_setup_hold ddr_test_cmd 0x15 a 0 size "); + printf("\n 0x16 test ee mdlr ddr_test_cmd 0x16 voltage pwm_id loops "); + printf("\n 0x17 d2pll ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n \ example ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 50 81 1 50 \n \ or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n"); - printf("or ddr_test_cmd 0x17 1200 6034 60346034 0 0 0 0 1 \n"); - printf("\n 0x18 test data_lane_setup_hold ddr_test_cmd 0x18 a 0 size range start_pin_id end_pin_id ddr_test_cmd 0x18 a 0 0x80000 1 0 96 "); - printf("\n 0x19 test phy vref ddr_test_cmd 0x19 a 0 0x80000 1 seed step vref_all vref_lcdlr_offset test_down_up_step seed_hex_dec \ + printf("or ddr_test_cmd 0x17 1200 6034 60346034 0 0 0 0 1 \n"); + printf("\n 0x18 test data_lane_setup_hold ddr_test_cmd 0x18 a 0 size range start_pin_id end_pin_id ddr_test_cmd 0x18 a 0 0x80000 1 0 96 "); + printf("\n 0x19 test phy vref ddr_test_cmd 0x19 a 0 0x80000 1 seed step vref_all vref_lcdlr_offset test_down_up_step seed_hex_dec \ ddr_test_cmd 0x19 a 0 0x1000000 1 63 1 1 0x8 0 1 "); - printf("\n 0x1a test dram vref ddr_test_cmd 0x1A a 0 0x80000 clear seed step vref_all vref_lcdlr_offset test_down_up_step vref_range seed_hex_dec \ + printf("\n 0x1a test dram vref ddr_test_cmd 0x1A a 0 0x80000 clear seed step vref_all vref_lcdlr_offset test_down_up_step vref_range seed_hex_dec \ \n setenv ddr_test_ddr4ram_vref ddr_test_cmd 0x1A a 0 0x0800000 0 0x14 1 0 0x8 0 0 0 ; setenv storeboot run ddr_test_ddr4ram_vref ;save;reset "); - printf("\n 0x1b test ac vref ddr_test_cmd 0x1B a 0 0x80000 clear seed step vref_all vref_lcdlr_offset seed_hex_dec"); - printf("\n 0x1c sweep dram clk use d2pll_env ddr_test_cmd 0x1c test_size start_freq end_freq test_loops ddr_test_cmd 0x1c 0x8000000 800 1500 1"); - printf("\n 0x1d test shift clk ddr_test_cmd 0x1d type delay_ms times"); - printf("\n 0x1e test write_read ddr_test_cmd 0x1e write_read pattern_id loop start_add test_size"); - printf("\n 0x1f test pwm_cmd ddr_test_cmd 0x1f pwmid pwm_low pwm_high"); - printf("\n 0x22 test ddr_window use env ddr_test_cmd 0x22 a 0 test_size watchdog_time \ + printf("\n 0x1b test ac vref ddr_test_cmd 0x1B a 0 0x80000 clear seed step vref_all vref_lcdlr_offset seed_hex_dec"); + printf("\n 0x1c sweep dram clk use d2pll_env ddr_test_cmd 0x1c test_size start_freq end_freq test_loops ddr_test_cmd 0x1c 0x8000000 800 1500 1"); + printf("\n 0x1d test shift clk ddr_test_cmd 0x1d type delay_ms times"); + printf("\n 0x1e test write_read ddr_test_cmd 0x1e write_read pattern_id loop start_add test_size"); + printf("\n 0x1f test pwm_cmd ddr_test_cmd 0x1f pwmid pwm_low pwm_high"); + printf("\n 0x22 test ddr_window use env ddr_test_cmd 0x22 a 0 test_size watchdog_time \ lane_disable_masrk add_test_size setenv bootcmd ddr_test_cmd 0x22 a 0 0x800000 15 0 0x8000000"); - printf("\n defenv;save;setenv bootcmd ddr_test_cmd 0x22 a 0 0x800000 18 0x0 0x8000000"); - printf("\n setenv env_ddrtest_data_lane 0x22;save;reset"); - printf("\n 0x23 test shift ddr frequency ddr_test_cmd 0x23"); - printf("\n 0x24 display ddr_information ddr_test_cmd 0x24"); - printf("\n 0x25 offset ddr_lcdlr ddr_test_cmd 0x25"); - printf("\n 0x26 set watchdog_value ddr_test_cmd 0x26 30"); - printf("\n 0x27 test ddr_window use sticky register ddr_test_cmd 0x27 a 0 test_size watchdog_time \ + printf("\n defenv;save;setenv bootcmd ddr_test_cmd 0x22 a 0 0x800000 18 0x0 0x8000000"); + printf("\n setenv env_ddrtest_data_lane 0x22;save;reset"); + printf("\n 0x23 test shift ddr frequency ddr_test_cmd 0x23"); + printf("\n 0x24 display ddr_information ddr_test_cmd 0x24"); + printf("\n 0x25 offset ddr_lcdlr ddr_test_cmd 0x25"); + printf("\n 0x26 set watchdog_value ddr_test_cmd 0x26 30"); + printf("\n 0x27 test ddr_window use sticky register ddr_test_cmd 0x27 a 0 test_size watchdog_time \ lane_disable_masrk add_test_size setenv bootcmd ddr_test_cmd 0x27 a 0 0x800000 15 0 0x8000000"); - printf("\n 0x28 sweep dram clk use d2pll_sticky ddr_test_cmd 0x28 test_size start_freq end_freq test_loops ddr_test_cmd 0x28 0x8000000 800 1500 1"); - - /* - ddr_tune_dqs_step a 0 0x800000 1 2 lane0-7 min - ddr_tune_dqs_step a 0 0x800000 1 1 lane0-7 max - - ddr_tune_aclcdlr_step a 0 0x8000000 1 2 lane0-1 min - ddr_tune_aclcdlr_step a 0 0x8000000 1 1 lane0-1 max - - setenv bootcmd "ddr_test_cmd 0x22 a 0 0x800000 18 0 0x8000000" watchdog_time £¬lane_disable_mask,add_test_size - setenv env_ddrtest_data_lane 0x22 ÉèÖÃÃüÁʼ±êÖ¾ - save watchdog_time £¬lane_disable_mask,add_test_size - d2pll 1200 - - setenv ddr_soc_iovref_test_ddr_clk "0x0000000"; - setenv ddr_soc_iovref_lef "0x0000000"; - setenv ddr_soc_iovref_org "0x0"; - setenv ddr_soc_iovref_rig "0x000000 "; - save - d2pll 1104 - ddr_test_cmd 0x19 a 0 0x80000 1 70 1 1 0x8 0 1 - - - - ÖزâÒªµôµç£¬Êý¾Ý´æÔÚstick ¼Ä´æÆ÷ÁË - setenv ddr_dram_iovref_test_ddr_clk "0x0000000"; - setenv ddr_dram_iovref_lef "0x0000000"; - setenv ddr_dram_iovref_org "0x0"; - setenv ddr_dram_iovref_rig "0x000000 "; - setenv ddr_test_ddr4ram_vref "ddr_test_cmd 0x1A a 0 0x080000 0 70 0 0 0x08 0 0 1" - setenv bootcmd "run ddr_test_ddr4ram_vref" - save - µôµçÉϵç - d2pll 1104 - */ - - - } - return 1; - - - case(DDR_TEST_CMD__DDR_TEST): - { - // run_command("ddrtest 0x10000000 0x8000000 3",0); - //ddr_test_cmd 0x1 star_add test_size loops - // do_ddr_test(cmdtp, flag, argc2,argv); - do_ddr_test((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2,(argv2)); - break; - } - case(DDR_TEST_CMD__DDR_TUNE_ACLCDLR): - break; - case(DDR_TEST_CMD__DDR_DDR_TUNE_AC_CLK): - break; - case(DDR_TEST_CMD__DDR_TUNE_ZQ): - break; - case(DDR_TEST_CMD__DDR_GXTVBB_CROSSTALK): - break; - case(DDR_TEST_CMD__DDR_BANDWIDTH_TEST): - break; - case(DDR_TEST_CMD__DDR_LCDLR_ENV_TUNE): - break; - case(DDR_TEST_CMD__DDR_MODIFY_REG_USE_MASK): - break; - case(DDR_TEST_CMD__DDR_SETZQ): - break; - - case(DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_STICKY): - break; - case(DDR_TEST_CMD__DDR4_TEST_DATA_WRTIE_READ): - { - // run_command("ddr_test_cmd 0x1e write_read pattern_id loop start_addr test_size delay_us",0); - //ddr_test_cmd 0x1e 1 2 10 0x40000000 0x10000000 - //times =0xffffffff will auto loop - printf("\ntest ddr write read \n"); - - do_ddr_test_write_read((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2)); - } - break; - //DDR_TEST_CMD__DDR_SET_UBOOT_G12_RECONFIG_CMD - case(DDR_TEST_CMD__DDR_SET_UBOOT_G12_RECONFIG_CMD): - { - // run_command("ddr_test_cmd 0x36 - printf("\nset do_ddr_uboot_reconfig cmd\n"); - - do_ddr_uboot_new_cmd((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2)); - } + printf("\n 0x28 sweep dram clk use d2pll_sticky ddr_test_cmd 0x28 test_size start_freq end_freq test_loops ddr_test_cmd 0x28 0x8000000 800 1500 1"); + } + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + //return 1; break; - case(DDR_TEST_CMD__DISPLAY_G12_DDR_INFORMATION): - { - // run_command("ddr_test_cmd 0x37 - printf("\nshow g12 ddr information\n"); - do_ddr_display_g12_ddr_information((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2)); - } - break; - - case(DDR_TEST_CMD__DDR_G12_DMC_TEST): - break; - case(DDR_TEST_CMD__DDR_G12_EE_BDLR_TEST): - { - // run_command("ddr_test_cmd 0x39 - printf("\nUboot BDLR test \n"); - - do_ddr_test_pwm_bdlr((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2)); - } + case (DDR_TEST_CMD__DDR_TEST): + { + do_ddr_test((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2)); break; } - return 1;//test_start_addr + case (DDR_TEST_CMD__DDR_TUNE_ACLCDLR): + break; + case (DDR_TEST_CMD__DDR_DDR_TUNE_AC_CLK): + break; + case (DDR_TEST_CMD__DDR_TUNE_ZQ): + break; + case (DDR_TEST_CMD__DDR_GXTVBB_CROSSTALK): + break; + case (DDR_TEST_CMD__DDR_BANDWIDTH_TEST): + break; + case (DDR_TEST_CMD__DDR_LCDLR_ENV_TUNE): + break; + case (DDR_TEST_CMD__DDR_MODIFY_REG_USE_MASK): + break; + case (DDR_TEST_CMD__DDR_SETZQ): + break; + + case (DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_STICKY): + break; + case (DDR_TEST_CMD__DDR4_TEST_DATA_WRTIE_READ): + { + printf("\ntest ddr write read \n"); + + do_ddr_test_write_read((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2)); + } + break; + case (DDR_TEST_CMD__DDR_SET_UBOOT_G12_RECONFIG_CMD): + { + printf("\nset do_ddr_uboot_reconfig cmd\n"); + + do_ddr_uboot_new_cmd((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2)); + } + break; + + case (DDR_TEST_CMD__DISPLAY_G12_DDR_INFORMATION): + { + printf("\nshow g12 ddr information\n"); + if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5)|| (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D)) + do_ddr_display_c2_ddr_information((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2)); + else + do_ddr_display_g12_ddr_information((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2)); + } + break; + + case (DDR_TEST_CMD__DDR_G12_DMC_TEST): + break; + case (DDR_TEST_CMD__DDR_G12_EE_BDLR_TEST): + { + printf("\nUboot BDLR test \n"); + + do_ddr_test_pwm_bdlr((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2)); + } + break; + } + writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address); + writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; //test_start_addr } usage: cmd_usage(cmdtp); + //wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); return 1; - } + U_BOOT_CMD( - ddr_test_cmd, 30, 1, do_ddr_test_cmd, + ddr_test_cmd, 30, 1, do_ddr_test_cmd, "ddr_test_cmd cmd arg1 arg2 arg3...", "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n" ); -int do_ddr_auto_test_window(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_auto_test_window(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { -check_base_address(); - global_boot_times=rd_reg(p_ddr_base->preg_sticky_reg0); + check_base_address(); + global_boot_times = rd_reg(p_ddr_base->preg_sticky_reg0); printf("\nglobal_boot_times== %d\n", global_boot_times); printf("\nargc== 0x%08x\n", argc); printf("\nargc== 0x%08x\n", argc); - int i ; - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } + int i; + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); - char str[1024]=""; - unsigned int ddr_test_cmd=0; - unsigned int temp_reg_add=0; - unsigned int num_arry[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + char str[1024] = ""; + unsigned int ddr_test_cmd = 0; + unsigned int temp_reg_add = 0; + unsigned int num_arry[32] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; - //int argc2; - //char * argv2[30]; - - temp_reg_add=(((p_ddr_base->ddr_dmc_sticky0))); - //num_arry = (uint16_t *)(uint64_t )(sticky_reg_base_add); + temp_reg_add = (((p_ddr_base->ddr_dmc_sticky0))); for (i = 0; i < 32; i++) { - num_arry[i]=ddr_rd_8_16bit_on_32reg(temp_reg_add,8,i); - if ((i == 0) || (i == 16)) { - printf("\n numarry[%d]" ,i); - } - printf(" %d ",num_arry[i]); + num_arry[i] = ddr_rd_8_16bit_on_32reg(temp_reg_add, 8, i); + if ((i == 0) || (i == 16)) + printf("\n numarry[%d]", i); + printf(" %d ", num_arry[i]); } - ddr_test_cmd=num_arry[0]; + ddr_test_cmd = num_arry[0]; - unsigned int cs0_test_start= 0x1080000; - unsigned int cs0_test_size= DDR_CORSS_TALK_TEST_SIZE; - unsigned int cs1_test_start= 0; - unsigned int cs1_test_size= 0; - unsigned int watchdog_time_s=0; - unsigned int test_index_enable=0; - unsigned int all_toghter_enable=0; - //unsigned int nibble_mask[3]={0,0,0}; - cs0_test_start=((num_arry[TEST_ARG_CS0_TEST_START_INDEX])|((num_arry[TEST_ARG_CS0_TEST_START_INDEX+1])<<8)| - ((num_arry[TEST_ARG_CS0_TEST_START_INDEX+2])<<16)|((num_arry[TEST_ARG_CS0_TEST_START_INDEX+3])<<24)); - cs0_test_size=((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX])|((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX+1])<<8)| - ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX+2])<<16)|((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX+3])<<24)); - cs1_test_start=((num_arry[TEST_ARG_CS1_TEST_START_INDEX])|((num_arry[TEST_ARG_CS1_TEST_START_INDEX+1])<<8)| - ((num_arry[TEST_ARG_CS1_TEST_START_INDEX+2])<<16)|((num_arry[TEST_ARG_CS1_TEST_START_INDEX+3])<<24)); - cs1_test_size=((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX])|((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX+1])<<8)| - ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX+2])<<16)|((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX+3])<<24)); - watchdog_time_s=((num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX])|((num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX+1])<<8)); - test_index_enable=((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX])|((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX+1])<<8)); - all_toghter_enable=(num_arry[TEST_ARG_3_ALL_TOGHTER]); - switch (ddr_test_cmd) - { - case(DMC_STICKY_UBOOT_WINDOW_MAGIC_1): - if (num_arry[1] == DMC_STICKY_UBOOT_WINDOW_MAGIC_1) - { - //argc2=10; - sprintf(str,"ddr_test_cmd 0x27 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \ - 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x",cs0_test_start,cs0_test_size,cs1_test_start,cs1_test_size, - watchdog_time_s,test_index_enable,0,0,0,0,0,0,all_toghter_enable ); - // for (i = 1;i<(argc2);i++) - // { - // argv2[i]=(arg[i]); - // sprintf(str," 0x%08x ",(arg[i])); - // } + unsigned int cs0_test_start = 0x1080000; + unsigned int cs0_test_size = DDR_CORSS_TALK_TEST_SIZE; + unsigned int cs1_test_start = 0; + unsigned int cs1_test_size = 0; + unsigned int watchdog_time_s = 0; + unsigned int test_index_enable = 0; + unsigned int all_toghter_enable = 0; + cs0_test_start = ((num_arry[TEST_ARG_CS0_TEST_START_INDEX]) | ((num_arry[TEST_ARG_CS0_TEST_START_INDEX + 1]) << 8) | + ((num_arry[TEST_ARG_CS0_TEST_START_INDEX + 2]) << 16) | ((num_arry[TEST_ARG_CS0_TEST_START_INDEX + 3]) << 24)); + cs0_test_size = ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX]) | ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX + 1]) << 8) | + ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX + 2]) << 16) | ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX + 3]) << 24)); + cs1_test_start = ((num_arry[TEST_ARG_CS1_TEST_START_INDEX]) | ((num_arry[TEST_ARG_CS1_TEST_START_INDEX + 1]) << 8) | + ((num_arry[TEST_ARG_CS1_TEST_START_INDEX + 2]) << 16) | ((num_arry[TEST_ARG_CS1_TEST_START_INDEX + 3]) << 24)); + cs1_test_size = ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX]) | ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX + 1]) << 8) | + ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX + 2]) << 16) | ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX + 3]) << 24)); + watchdog_time_s = ((num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX]) | ((num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX + 1]) << 8)); + test_index_enable = ((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]) | ((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX + 1]) << 8)); + all_toghter_enable = (num_arry[TEST_ARG_3_ALL_TOGHTER]); + switch (ddr_test_cmd) { + case (DMC_STICKY_UBOOT_WINDOW_MAGIC_1): + if (num_arry[1] == DMC_STICKY_UBOOT_WINDOW_MAGIC_1) { + sprintf(str, "ddr_test_cmd 0x27 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \ + 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", cs0_test_start, cs0_test_size, cs1_test_start, cs1_test_size, + watchdog_time_s, test_index_enable, 0, 0, 0, 0, 0, 0, all_toghter_enable); - printf("\nstr=%s\n",str); + printf("\nstr=%s\n", str); - run_command(str,0); - // ddr_test_cmd((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2,(argv2)); + run_command(str, 0); break; } } return 1; } + U_BOOT_CMD( - ddr_auto_test_window, 30, 1, do_ddr_auto_test_window, + ddr_auto_test_window, 30, 1, do_ddr_auto_test_window, "ddr_test_cmd cmd arg1 arg2 arg3...", "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n" ); -int do_ddr_auto_scan_drv(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_ddr_auto_scan_drv(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { check_base_address(); - // ddr_type 2 lpddr4 rank_config - #define AUTO_SCAN_DDR3 0 - #define AUTO_SCAN_DDR4 1 - #define AUTO_SCAN_LPDDR3 2 - #define AUTO_SCAN_LPDDR4 3 +#define AUTO_SCAN_DDR3 0 +#define AUTO_SCAN_DDR4 1 +#define AUTO_SCAN_LPDDR3 2 +#define AUTO_SCAN_LPDDR4 3 - #define AUTO_SCAN_CONFIG_RANK0 0 - #define AUTO_SCAN_CONFIG_RANK01 1 +#define AUTO_SCAN_CONFIG_RANK0 0 +#define AUTO_SCAN_CONFIG_RANK01 1 - char *string_print_flag= " window-loop \n"; - global_boot_times=rd_reg((p_ddr_base->preg_sticky_reg0)); + char *string_print_flag = " window-loop \n"; + global_boot_times = rd_reg((p_ddr_base->preg_sticky_reg0)); printf("\nargc== 0x%08x\n", argc); printf("\nargc== 0x%08x\n", argc); - int i ; - for (i = 0;i<argc;i++) - { - printf("\nargv[%d]=%s\n",i,argv[i]); - } + int i; + for (i = 0; i < argc; i++) + printf("\nargv[%d]=%s\n", i, argv[i]); - unsigned int ddr_type=0; - unsigned int ddr_channel_rank_config=0; - unsigned int loop=0; + unsigned int ddr_type = 0; + unsigned int ddr_channel_rank_config = 0; + unsigned int loop = 0; char *endp; - if (argc>1) - { + if (argc > 1) { ddr_type = simple_strtoull_ddr(argv[1], &endp, 0); if (*argv[1] == 0 || *endp != 0) - ddr_type=0; + ddr_type = 0; } - if (argc>2) - { + if (argc > 2) { ddr_channel_rank_config = simple_strtoull_ddr(argv[2], &endp, 0); if (*argv[2] == 0 || *endp != 0) - ddr_channel_rank_config=0; + ddr_channel_rank_config = 0; } -if (argc>3) - { + if (argc > 3) { loop = simple_strtoull_ddr(argv[3], &endp, 0); if (*argv[3] == 0 || *endp != 0) - loop=0; + loop = 0; } - unsigned int temp_reg_add=0; + unsigned int temp_reg_add = 0; { - temp_reg_add=(((p_ddr_base->ddr_dmc_sticky0))); + temp_reg_add = (((p_ddr_base->ddr_dmc_sticky0))); } - char str[1024]=""; - // unsigned int ddr_test_cmd=0; - // unsigned int temp_reg_add=0; - // unsigned int num_arry[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + char str[1024] = ""; - unsigned int counter_loop=0; - unsigned int ddr_frequency=0; - unsigned int soc_data_drv_ohm_p=0;//74 //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm - unsigned int soc_data_drv_ohm_n=0;//76 - unsigned int soc_data_odt_ohm_p=0;//78 //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm - unsigned int soc_data_odt_ohm_n=0;//80 - unsigned int dram_data_drv_ohm=0;//82 //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm - unsigned int dram_data_odt_ohm=0;//84 //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm - unsigned int dram_data_wr_odt_ohm=0; //174 char 1 - i=74/2; - soc_data_drv_ohm_p=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i); - i=76/2; - soc_data_drv_ohm_n=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i); - i=78/2; - soc_data_odt_ohm_p=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i); - i=80/2; - soc_data_odt_ohm_n=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i); - i=82/2; - dram_data_drv_ohm=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i); - i=84/2; - dram_data_odt_ohm=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i); - i=174/1; - dram_data_wr_odt_ohm=ddr_rd_8_16bit_on_32reg(temp_reg_add,8,i); - i=52/2; - ddr_frequency=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i); - //ddr_frequency=global_ddr_clk; - if (global_boot_times == 1) - { - printf("\norg_global_boot_times== %d %s", global_boot_times,string_print_flag); - //printf("\nmax_counter=%d %d %s",max_counter_total,max_counter_total*2,string_print_flag); - printf("\nsoc_data_drv_ohm_p=%d %s",soc_data_drv_ohm_p,string_print_flag); - printf("\nsoc_data_drv_ohm_n=%d %s",soc_data_drv_ohm_n,string_print_flag); - printf("\nsoc_data_odt_ohm_p=%d %s",soc_data_odt_ohm_p,string_print_flag); - printf("\nsoc_data_odt_ohm_n=%d %s",soc_data_odt_ohm_n,string_print_flag); - printf("\ndram_data_drv_ohm=%d %s",dram_data_drv_ohm,string_print_flag); - printf("\ndram_data_odt_ohm=%d %s",dram_data_odt_ohm,string_print_flag); - printf("\ndram_data_wr_odt_ohm=%d %s",dram_data_wr_odt_ohm,string_print_flag); + unsigned int counter_loop = 0; + unsigned int ddr_frequency = 0; + unsigned int soc_data_drv_ohm_p = 0; //74 //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned int soc_data_drv_ohm_n = 0; //76 + unsigned int soc_data_odt_ohm_p = 0; //78 //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm + unsigned int soc_data_odt_ohm_n = 0; //80 + unsigned int dram_data_drv_ohm = 0; //82 //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm + unsigned int dram_data_odt_ohm = 0; //84 //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm + unsigned int dram_data_wr_odt_ohm = 0; //174 char 1 + i = 74 / 2; + soc_data_drv_ohm_p = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i); + i = 76 / 2; + soc_data_drv_ohm_n = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i); + i = 78 / 2; + soc_data_odt_ohm_p = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i); + i = 80 / 2; + soc_data_odt_ohm_n = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i); + i = 82 / 2; + dram_data_drv_ohm = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i); + i = 84 / 2; + dram_data_odt_ohm = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i); + i = 174 / 1; + dram_data_wr_odt_ohm = ddr_rd_8_16bit_on_32reg(temp_reg_add, 8, i); + i = 52 / 2; + ddr_frequency = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i); + if (global_boot_times == 1) { + printf("\norg_global_boot_times== %d %s", global_boot_times, string_print_flag); + printf("\nsoc_data_drv_ohm_p=%d %s", soc_data_drv_ohm_p, string_print_flag); + printf("\nsoc_data_drv_ohm_n=%d %s", soc_data_drv_ohm_n, string_print_flag); + printf("\nsoc_data_odt_ohm_p=%d %s", soc_data_odt_ohm_p, string_print_flag); + printf("\nsoc_data_odt_ohm_n=%d %s", soc_data_odt_ohm_n, string_print_flag); + printf("\ndram_data_drv_ohm=%d %s", dram_data_drv_ohm, string_print_flag); + printf("\ndram_data_odt_ohm=%d %s", dram_data_odt_ohm, string_print_flag); + printf("\ndram_data_wr_odt_ohm=%d %s", dram_data_wr_odt_ohm, string_print_flag); } - unsigned int soc_data_drv_ohm_p_t[]={34,40,48,60}; - // unsigned int soc_data_drv_ohm_n_t[]={34,40,48,60}; + unsigned int soc_data_drv_ohm_p_t[] = { 34, 40, 48, 60 }; - unsigned int dram_data_odt_ohm_t_ddr3[]={40,60,120}; //ddr3 - unsigned int dram_data_odt_ohm_t_ddr4[]={40,48,60,120}; //ddr4 - unsigned int dram_data_odt_ohm_t_lpddr4[]={40,48,60,120}; //lpddr4 + unsigned int dram_data_odt_ohm_t_ddr3[] = { 40, 60, 120 }; //ddr3 + unsigned int dram_data_odt_ohm_t_ddr4[] = { 40, 48, 60, 120 }; //ddr4 + unsigned int dram_data_odt_ohm_t_lpddr4[] = { 40, 48, 60, 120 }; //lpddr4 - unsigned int dram_data_drv_ohm_t_ddr3[]={34,40}; //ddr3 - unsigned int dram_data_drv_ohm_t_ddr4[]={34,48}; //ddr4 - unsigned int dram_data_drv_ohm_t_lpddr4[]={40,48,60}; //lpddr4 + unsigned int dram_data_drv_ohm_t_ddr3[] = { 34, 40 }; //ddr3 + unsigned int dram_data_drv_ohm_t_ddr4[] = { 34, 48 }; //ddr4 + unsigned int dram_data_drv_ohm_t_lpddr4[] = { 40, 48, 60 }; //lpddr4 - unsigned int soc_data_odt_ohm_p_t[]={40,48,60,80,120}; - unsigned int soc_data_odt_ohm_n_t[]={40,48,60,80,120}; + unsigned int soc_data_odt_ohm_p_t[] = { 40, 48, 60, 80, 120 }; + unsigned int soc_data_odt_ohm_n_t[] = { 40, 48, 60, 80, 120 }; - unsigned int dram_data_wr_odt_ohm_t_ddr3[]={60,120,0}; //ddr3 - unsigned int dram_data_wr_odt_ohm_t_ddr4[]={80,120,0}; //ddr4 + unsigned int dram_data_wr_odt_ohm_t_ddr3[] = { 60, 120, 0 }; //ddr3 + unsigned int dram_data_wr_odt_ohm_t_ddr4[] = { 80, 120, 0 }; //ddr4 - unsigned int *p_soc_data_drv_ohm_p=NULL; - // unsigned int *p_soc_data_drv_ohm_n=NULL; - unsigned int *p_soc_data_odt_ohm_p=NULL; - unsigned int *p_soc_data_odt_ohm_n=NULL; + unsigned int *p_soc_data_drv_ohm_p = NULL; + unsigned int *p_soc_data_odt_ohm_p = NULL; + unsigned int *p_soc_data_odt_ohm_n = NULL; - unsigned int *p_dram_data_drv_ohm=NULL; - unsigned int *p_dram_data_odt_ohm=NULL; - unsigned int *p_dram_data_wr_odt_ohm=NULL; + unsigned int *p_dram_data_drv_ohm = NULL; + unsigned int *p_dram_data_odt_ohm = NULL; + unsigned int *p_dram_data_wr_odt_ohm = NULL; - p_soc_data_drv_ohm_p=soc_data_drv_ohm_p_t; - // p_soc_data_drv_ohm_n=soc_data_drv_ohm_n_t; - p_soc_data_odt_ohm_p=soc_data_odt_ohm_p_t; - p_soc_data_odt_ohm_n=soc_data_odt_ohm_n_t; + p_soc_data_drv_ohm_p = soc_data_drv_ohm_p_t; + p_soc_data_odt_ohm_p = soc_data_odt_ohm_p_t; + p_soc_data_odt_ohm_n = soc_data_odt_ohm_n_t; - p_dram_data_drv_ohm=dram_data_drv_ohm_t_ddr3; - p_dram_data_odt_ohm=dram_data_odt_ohm_t_ddr3; - p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_ddr3; + p_dram_data_drv_ohm = dram_data_drv_ohm_t_ddr3; + p_dram_data_odt_ohm = dram_data_odt_ohm_t_ddr3; + p_dram_data_wr_odt_ohm = dram_data_wr_odt_ohm_t_ddr3; - unsigned int max_counter_loop_w1=(sizeof(soc_data_drv_ohm_p_t))/(sizeof(soc_data_drv_ohm_p_t[0])); - unsigned int max_counter_loop_w2=(sizeof(dram_data_odt_ohm_t_ddr3))/(sizeof(dram_data_odt_ohm_t_ddr3[0])); - unsigned int max_counter_loop_r1=(sizeof(dram_data_drv_ohm_t_ddr3))/(sizeof(dram_data_drv_ohm_t_ddr3[0])); - unsigned int max_counter_loop_r2=(sizeof(soc_data_odt_ohm_p_t))/(sizeof(soc_data_odt_ohm_p_t[0])); - unsigned int max_counter_loop_wr1=1; + unsigned int max_counter_loop_w1 = (sizeof(soc_data_drv_ohm_p_t)) / (sizeof(soc_data_drv_ohm_p_t[0])); + unsigned int max_counter_loop_w2 = (sizeof(dram_data_odt_ohm_t_ddr3)) / (sizeof(dram_data_odt_ohm_t_ddr3[0])); + unsigned int max_counter_loop_r1 = (sizeof(dram_data_drv_ohm_t_ddr3)) / (sizeof(dram_data_drv_ohm_t_ddr3[0])); + unsigned int max_counter_loop_r2 = (sizeof(soc_data_odt_ohm_p_t)) / (sizeof(soc_data_odt_ohm_p_t[0])); + unsigned int max_counter_loop_wr1 = 1; if (ddr_channel_rank_config) - { - max_counter_loop_wr1=(sizeof(dram_data_wr_odt_ohm_t_ddr3))/(sizeof(dram_data_wr_odt_ohm_t_ddr3[0])); - } - //ddr_channel_rank_configCONFIG_DDR0_32BIT_RANK01_CH0 - if (ddr_type == AUTO_SCAN_DDR4) - { - p_dram_data_drv_ohm=dram_data_drv_ohm_t_ddr4; - p_dram_data_odt_ohm=dram_data_odt_ohm_t_ddr4; - p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_ddr4; - max_counter_loop_w2=(sizeof(dram_data_odt_ohm_t_ddr4))/(sizeof(dram_data_odt_ohm_t_ddr4[0])); - max_counter_loop_r1=(sizeof(dram_data_drv_ohm_t_ddr4))/(sizeof(dram_data_drv_ohm_t_ddr4[0])); + max_counter_loop_wr1 = (sizeof(dram_data_wr_odt_ohm_t_ddr3)) / (sizeof(dram_data_wr_odt_ohm_t_ddr3[0])); + if (ddr_type == AUTO_SCAN_DDR4) { + p_dram_data_drv_ohm = dram_data_drv_ohm_t_ddr4; + p_dram_data_odt_ohm = dram_data_odt_ohm_t_ddr4; + p_dram_data_wr_odt_ohm = dram_data_wr_odt_ohm_t_ddr4; + max_counter_loop_w2 = (sizeof(dram_data_odt_ohm_t_ddr4)) / (sizeof(dram_data_odt_ohm_t_ddr4[0])); + max_counter_loop_r1 = (sizeof(dram_data_drv_ohm_t_ddr4)) / (sizeof(dram_data_drv_ohm_t_ddr4[0])); if (ddr_channel_rank_config) - { - max_counter_loop_wr1=(sizeof(dram_data_wr_odt_ohm_t_ddr4))/(sizeof(dram_data_wr_odt_ohm_t_ddr4[0])); - } + max_counter_loop_wr1 = (sizeof(dram_data_wr_odt_ohm_t_ddr4)) / (sizeof(dram_data_wr_odt_ohm_t_ddr4[0])); } - if (ddr_type == AUTO_SCAN_LPDDR4) - { - p_dram_data_drv_ohm=dram_data_drv_ohm_t_lpddr4; - p_dram_data_odt_ohm=dram_data_odt_ohm_t_lpddr4; - // p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_lpddr4; - max_counter_loop_w2=(sizeof(dram_data_odt_ohm_t_lpddr4))/(sizeof(dram_data_odt_ohm_t_lpddr4[0])); - max_counter_loop_r1=(sizeof(dram_data_drv_ohm_t_lpddr4))/(sizeof(dram_data_drv_ohm_t_lpddr4[0])); - max_counter_loop_r2=(sizeof(soc_data_odt_ohm_n_t))/(sizeof(soc_data_odt_ohm_n_t[0])); + if (ddr_type == AUTO_SCAN_LPDDR4) { + p_dram_data_drv_ohm = dram_data_drv_ohm_t_lpddr4; + p_dram_data_odt_ohm = dram_data_odt_ohm_t_lpddr4; + max_counter_loop_w2 = (sizeof(dram_data_odt_ohm_t_lpddr4)) / (sizeof(dram_data_odt_ohm_t_lpddr4[0])); + max_counter_loop_r1 = (sizeof(dram_data_drv_ohm_t_lpddr4)) / (sizeof(dram_data_drv_ohm_t_lpddr4[0])); + max_counter_loop_r2 = (sizeof(soc_data_odt_ohm_n_t)) / (sizeof(soc_data_odt_ohm_n_t[0])); - // unsigned int *p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_lpddr4; if (ddr_channel_rank_config) - { - max_counter_loop_wr1=1; - } + max_counter_loop_wr1 = 1; } -unsigned int max_counter_total=(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)*max_counter_loop_wr1; + unsigned int max_counter_total = (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2) * max_counter_loop_wr1; //add 2 times recover - /* - switch (global_boot_times) - { - case(1): - { - break; - } - } - */ //each arrary test 2 times ,for maybe 1times will fail,then next time will recovery //jiaxing 20181114 - counter_loop=(((global_boot_times-1)/2)%max_counter_total); - dram_data_wr_odt_ohm=0; - if (max_counter_loop_wr1>1) - { - dram_data_wr_odt_ohm=p_dram_data_wr_odt_ohm[(counter_loop/(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))]; - } - if ((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))<(max_counter_loop_w1*max_counter_loop_w2)) - { - soc_data_drv_ohm_p=p_soc_data_drv_ohm_p[(((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))%max_counter_loop_w1)]; - soc_data_drv_ohm_n=soc_data_drv_ohm_p; - dram_data_odt_ohm=p_dram_data_odt_ohm[ (((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))/max_counter_loop_w1)]; - } - else if((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))==((max_counter_loop_w1*max_counter_loop_w2)+0)) - { + counter_loop = (((global_boot_times - 1) / 2) % max_counter_total); + dram_data_wr_odt_ohm = 0; + if (max_counter_loop_wr1 > 1) + dram_data_wr_odt_ohm = p_dram_data_wr_odt_ohm[(counter_loop / (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))]; + if ((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2)) < (max_counter_loop_w1 * max_counter_loop_w2)) { + soc_data_drv_ohm_p = p_soc_data_drv_ohm_p[(((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) % max_counter_loop_w1)]; + soc_data_drv_ohm_n = soc_data_drv_ohm_p; + dram_data_odt_ohm = p_dram_data_odt_ohm[(((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) / max_counter_loop_w1)]; + } else if ((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2)) == ((max_counter_loop_w1 * max_counter_loop_w2) + 0)) { ddr_test_watchdog_reset_system(); - // sprintf(str,"g12_d2pll 1200 0x11 0x6 0 0x0 0 0 0 0x800000 0 1 " - // printf("\nstr=%s\n",str); - // run_command(str,0); - } - else if((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))<(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2-1)) - { - dram_data_drv_ohm=p_dram_data_drv_ohm[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))%max_counter_loop_r1)]; - soc_data_odt_ohm_p=p_soc_data_odt_ohm_p[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))/max_counter_loop_r1)]; - soc_data_odt_ohm_n=0; - if (ddr_type == CONFIG_DDR_TYPE_LPDDR4) - { - soc_data_odt_ohm_p=0; - soc_data_odt_ohm_n=p_soc_data_odt_ohm_n[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))/max_counter_loop_r1)]; + } else if ((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2)) < (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2 - 1)) { + dram_data_drv_ohm = p_dram_data_drv_ohm[((((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) - (max_counter_loop_w1 * max_counter_loop_w2 + 1)) % max_counter_loop_r1)]; + soc_data_odt_ohm_p = p_soc_data_odt_ohm_p[((((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) - (max_counter_loop_w1 * max_counter_loop_w2 + 1)) / max_counter_loop_r1)]; + soc_data_odt_ohm_n = 0; + if (ddr_type == CONFIG_DDR_TYPE_LPDDR4) { + soc_data_odt_ohm_p = 0; + soc_data_odt_ohm_n = p_soc_data_odt_ohm_n[((((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) - (max_counter_loop_w1 * max_counter_loop_w2 + 1)) / max_counter_loop_r1)]; } - } - else if((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))==(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2-1)) - { + } else if ((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2)) == (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2 - 1)) { ddr_test_watchdog_reset_system(); } - printf("\nglobal_boot_times== %d %s", global_boot_times,string_print_flag); - if (loop) - { - if (((global_boot_times-1)/2)>max_counter_total) + printf("\nglobal_boot_times== %d %s", global_boot_times, string_print_flag); + + if (loop) { + if (((global_boot_times - 1) / 2) > max_counter_total) return 1; } - printf("\nmax_counter=%d %d %s",max_counter_total,max_counter_total*2,string_print_flag); - printf("\nsoc_data_drv_ohm_p=%d %s",soc_data_drv_ohm_p,string_print_flag); - printf("\nsoc_data_drv_ohm_n=%d %s",soc_data_drv_ohm_n,string_print_flag); - printf("\nsoc_data_odt_ohm_p=%d %s",soc_data_odt_ohm_p,string_print_flag); - printf("\nsoc_data_odt_ohm_n=%d %s",soc_data_odt_ohm_n,string_print_flag); - printf("\ndram_data_drv_ohm=%d %s",dram_data_drv_ohm,string_print_flag); - printf("\ndram_data_odt_ohm=%d %s",dram_data_odt_ohm,string_print_flag); - printf("\ndram_data_wr_odt_ohm=%d %s",dram_data_wr_odt_ohm,string_print_flag); -{ - if (soc_data_drv_ohm_p) + printf("\nmax_counter=%d %d %s", max_counter_total, max_counter_total * 2, string_print_flag); + printf("\nsoc_data_drv_ohm_p=%d %s", soc_data_drv_ohm_p, string_print_flag); + printf("\nsoc_data_drv_ohm_n=%d %s", soc_data_drv_ohm_n, string_print_flag); + printf("\nsoc_data_odt_ohm_p=%d %s", soc_data_odt_ohm_p, string_print_flag); + printf("\nsoc_data_odt_ohm_n=%d %s", soc_data_odt_ohm_n, string_print_flag); + printf("\ndram_data_drv_ohm=%d %s", dram_data_drv_ohm, string_print_flag); + printf("\ndram_data_odt_ohm=%d %s", dram_data_odt_ohm, string_print_flag); + printf("\ndram_data_wr_odt_ohm=%d %s", dram_data_wr_odt_ohm, string_print_flag); { - sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 74 %d 2 0 ", - soc_data_drv_ohm_p); - printf("\nstr=%s\n",str); - run_command(str,0); - } - if (soc_data_drv_ohm_n) - { - sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 76 %d 2 0 ", - soc_data_drv_ohm_n); - printf("\nstr=%s\n",str); - run_command(str,0); - } - if (soc_data_odt_ohm_p) - { - sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 78 %d 2 0 ", - soc_data_odt_ohm_p); - printf("\nstr=%s\n",str); - run_command(str,0); - } - if (soc_data_odt_ohm_n) - { - sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 80 %d 2 0 ", - soc_data_odt_ohm_n); - printf("\nstr=%s\n",str); - run_command(str,0); - } - if (dram_data_drv_ohm) - { - sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 82 %d 2 0 ", - dram_data_drv_ohm); - printf("\nstr=%s\n",str); - run_command(str,0); - } - if (dram_data_odt_ohm) - { - sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 84 %d 2 0 ", - dram_data_odt_ohm); - printf("\nstr=%s\n",str); - run_command(str,0); - } - //if(dram_data_wr_odt_ohm) - { - sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 174 %d 1 0 ", - dram_data_wr_odt_ohm); - printf("\nstr=%s\n",str); - run_command(str,0); + if (soc_data_drv_ohm_p) { + sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 74 %d 2 0 ", + soc_data_drv_ohm_p); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + if (soc_data_drv_ohm_n) { + sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 76 %d 2 0 ", + soc_data_drv_ohm_n); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + if (soc_data_odt_ohm_p) { + sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 78 %d 2 0 ", + soc_data_odt_ohm_p); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + if (soc_data_odt_ohm_n) { + sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 80 %d 2 0 ", + soc_data_odt_ohm_n); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + if (dram_data_drv_ohm) { + sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 82 %d 2 0 ", + dram_data_drv_ohm); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + if (dram_data_odt_ohm) { + sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 84 %d 2 0 ", + dram_data_odt_ohm); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + { + sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 174 %d 1 0 ", + dram_data_wr_odt_ohm); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + + sprintf(str, "g12_d2pll %d 0x12 0x6 0 0x0 0 0 0 0x800000 0 1 ", ddr_frequency); + printf("\nstr=%s\n", str); + run_command(str, 0); } - sprintf(str,"g12_d2pll %d 0x12 0x6 0 0x0 0 0 0 0x800000 0 1 ",ddr_frequency); - printf("\nstr=%s\n",str); - run_command(str,0); -} - -return 1; + return 1; } unsigned char temp_sha2[SHA256_SUM_LEN]; int do_verify_flash_ddr_parameter(char log_level) { + unsigned count = 0; + unsigned error = 0; - unsigned count=0; - unsigned error=0; - //dcache_disable(); - char temp_buf[((sizeof(ddr_sha_t)+511)/512)*512]={0}; - #ifdef USE_FOR_UBOOT_2018 - extern int store_rsv_read(const char *name, size_t size, void *buf); - //store_rsv_read("ddr-parameter",((sizeof(ddr_sha_t)+511)/512)*512,(uint8_t *)(&ddr_sha)); - store_rsv_read("ddr-parameter",((sizeof(ddr_sha_t)+511)/512)*512,(uint8_t *)(temp_buf)); - //sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,ddr_set_size+SHA256_SUM_LEN+MESON_CPU_CHIP_ID_SIZE); + if ((p_ddr_base->chip_id >= MESON_CPU_MAJOR_ID_C2) && (p_ddr_base->chip_id <= MESON_CPU_MAJOR_ID_T5D)) { + char temp_buf[((sizeof(ddr_sha_t_c2) + 511) / 512) * 512] = { 0 }; - #else - extern int store_ddr_parameter_read(uint8_t *buffer, uint32_t length); - //store_ddr_parameter_read((uint8_t *)(&ddr_sha),((sizeof(ddr_sha_t)+511)/512)*512); - store_ddr_parameter_read((uint8_t *)(temp_buf),((sizeof(ddr_sha_t)+511)/512)*512); - #endif +#ifdef USE_FOR_UBOOT_2018 + extern int store_rsv_read(const char *name, size_t size, void *buf); + + store_rsv_read("ddr-parameter", ((sizeof(ddr_sha_t_c2) + 511) / 512) * 512, (uint8_t *)(temp_buf)); + +#else + extern int store_ddr_parameter_read(uint8_t *buffer, uint32_t length); + + store_ddr_parameter_read((uint8_t *)(temp_buf), ((sizeof(ddr_sha_t_c2) + 511) / 512) * 512); +#endif + char *s = temp_buf; + char *d = (char *)(&ddr_sha_c2); + + for (count = 0; count < sizeof(ddr_sha_t_c2); count++) { + *d = *s; + s++; + d++; + } + + for (count = 0; count < SHA256_SUM_LEN; count++) + ((temp_sha2[count]) = (ddr_sha_c2.sha2[count])); + + sha256_csum_wd_internal((uint8_t *)(&(ddr_sha_c2.ddrs)), sizeof(ddr_set_t_c2), ddr_sha_c2.sha2, 0); + + for (count = 0; count < SHA256_SUM_LEN; count++) { + if ((temp_sha2[count]) != (ddr_sha_c2.sha2[count])) + error++; + + if (log_level == 0) + printf("\nread sha[%08x] %08x,calu %08x", count, (ddr_sha_c2.sha2[count]), (temp_sha2[count])); + } + +#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1 << 30) + // if ((ddr_sha_c2.ddrs.cfg_board_common_setting.ddr_func) & DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID) + { + for (count = 0; count < MESON_CPU_CHIP_ID_SIZE; count++) { + if ((ddr_sha_c2.sha_chip_id[count]) != (global_chip_id[count])) + error++; + + if (log_level == 0) + printf("\nglobal_chip_id[%08x] %08x,read %08x", count, (global_chip_id[count]), (ddr_sha_c2.sha_chip_id[count])); + } + } + + return error; + } + char temp_buf[((sizeof(ddr_sha_t) + 511) / 512) * 512] = { 0 }; + +#ifdef USE_FOR_UBOOT_2018 + extern int store_rsv_read(const char *name, size_t size, void *buf); + + store_rsv_read("ddr-parameter", ((sizeof(ddr_sha_t) + 511) / 512) * 512, (uint8_t *)(temp_buf)); + +#else + extern int store_ddr_parameter_read(uint8_t *buffer, uint32_t length); + + store_ddr_parameter_read((uint8_t *)(temp_buf), ((sizeof(ddr_sha_t) + 511) / 512) * 512); +#endif char *s = temp_buf; - char *d =(char *) (&ddr_sha); - for (count=0;count<sizeof(ddr_sha_t);count++) - { - *d=*s; + char *d = (char *)(&ddr_sha); + + for (count = 0; count < sizeof(ddr_sha_t); count++) { + *d = *s; s++; d++; } - for (count=0;count<SHA256_SUM_LEN;count++) - { - ((temp_sha2[count])=(ddr_sha.sha2[count])); - } - sha256_csum_wd_internal((uint8_t *)(&(ddr_sha.ddrs)), sizeof(ddr_set_t),ddr_sha.sha2, 0); - //sha256_csum_wd_internal((uint8_t *)(&(ddr_sha.ddrs)), sizeof(ddr_set_t),ddr_sha.sha2, 0); - #if 0 - printf("verify read\n"); - char str[1024]=""; - sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(&ddr_sha)); - run_command(str,0); - printf("verify (ddr_sha->ddrs)\n"); - sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(&(ddr_sha.ddrs))); - run_command(str,0); - printf("cal sha\n"); - sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(&temp_sha2)); - run_command(str,0); - #endif - for (count=0;count<SHA256_SUM_LEN;count++) - { + for (count = 0; count < SHA256_SUM_LEN; count++) + ((temp_sha2[count]) = (ddr_sha.sha2[count])); + + sha256_csum_wd_internal((uint8_t *)(&(ddr_sha.ddrs)), sizeof(ddr_set_t), ddr_sha.sha2, 0); + + for (count = 0; count < SHA256_SUM_LEN; count++) { if ((temp_sha2[count]) != (ddr_sha.sha2[count])) error++; + if (log_level == 0) - printf("\nread sha[%08x] %08x,calu %08x",count,(ddr_sha.sha2[count]),(temp_sha2[count])); + printf("\nread sha[%08x] %08x,calu %08x", count, (ddr_sha.sha2[count]), (temp_sha2[count])); } - #define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30) - if ((ddr_sha.ddrs.ddr_func)&DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID) - { - for (count=0;count<MESON_CPU_CHIP_ID_SIZE;count++) - { + +#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1 << 30) + + if ((ddr_sha.ddrs.ddr_func) & DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID) { + for (count = 0; count < MESON_CPU_CHIP_ID_SIZE; count++) { if ((ddr_sha.sha_chip_id[count]) != (global_chip_id[count])) error++; + if (log_level == 0) - printf("\nglobal_chip_id[%08x] %08x,read %08x",count,(global_chip_id[count]),(ddr_sha.sha_chip_id[count])); + printf("\nglobal_chip_id[%08x] %08x,read %08x", count, (global_chip_id[count]), (ddr_sha.sha_chip_id[count])); } } return error; -} -int do_ddr_auto_fastboot_check(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +} /* do_verify_flash_ddr_parameter */ + +uint32_t enable_ddr_check_boot_reason = 0; +uint32_t boot_reason = 0; +#define HOT_BOOT_MAGIC 0x99887766 +#define HOT_BOOT_STICKY_ADD (p_ddr_base->preg_sticky_reg0 + (6 << 2)) +#define AMLOGIC_COLD_BOOT 0 +int do_ddr_auto_fastboot_check_c2(char auto_window_test_enable_item, uint32_t auto_window_test_dq_size, char pattern_dis_scramble, uint32_t stick_dmc_ddr_window_test_read_vref_offset_value, uint32_t skip_window_test_enable) { - check_base_address(); - #define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT (1<<5) - #define AUTO_WINDOW_TEST_ENABLE_ITEM ((1<<1)|(1<<2)) - // int i=0; - // int count=0; - char *endp; - //unsigned int enable_ddr_fast_boot=0; // 0 pause 1,resume - char auto_window_test_enable_item=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT; - uint32_t auto_window_test_dq_size=0; - char pattern_dis_scramble=0; - uint32_t stick_dmc_ddr_window_test_read_vref_offset_value=0; - uint32_t ddr_set_size=0; - if (argc>1) - { - auto_window_test_enable_item = simple_strtoull_ddr(argv[1], &endp, 0); - if (*argv[1] == 0 || *endp != 0) - auto_window_test_enable_item=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT; - } - if (argc>2) - { - auto_window_test_dq_size = simple_strtoull_ddr(argv[2], &endp, 0); - if (*argv[2] == 0 || *endp != 0) - auto_window_test_dq_size=0; - } - if (argc>3) - { - pattern_dis_scramble = simple_strtoull_ddr(argv[3], &endp, 0); - if (*argv[3] == 0 || *endp != 0) - pattern_dis_scramble=0; - } - if (argc>4) - { - stick_dmc_ddr_window_test_read_vref_offset_value = simple_strtoull_ddr(argv[4], &endp, 0); - if (*argv[4] == 0 || *endp != 0) - stick_dmc_ddr_window_test_read_vref_offset_value=0; - } - char str[1024]=""; - int verify_error=0; - verify_error=do_verify_flash_ddr_parameter(1); - if ((verify_error) == 0) - { - if ((ddr_sha.ddrs.fast_boot[0]) == 0xff) - { + uint32_t ddr_set_size = 0; + uint32_t need_ddr_window_test = 0; + char str[1024] = ""; + int verify_error = 0; + + verify_error = do_verify_flash_ddr_parameter(1); + + if ((verify_error) == 0) { + if ((ddr_sha_c2.ddrs.cfg_board_common_setting.fast_boot[0]) == 0xff) { printf("\nuboot auto fast boot check flash data is ok return \n"); - return 1 ; - } - } - ddr_set_t *ddr_set_t_p=NULL; - ddr_set_t_p=(ddr_set_t *)(ddr_set_t_p_arrary); - //ddr_set_t_p= (ddr_set_t *)(p_ddr_base->ddr_dmc_sticky0); - //if (sizeof(ddr_set_t)<loop_max) - uint32_t ddr_set_add=0; - - ddr_set_add=(uint32_t)(uint64_t)(ddr_set_t_p); - ddr_set_size=sizeof(ddr_set_t); - printf("\nddr_set_t_p==0x%08x\n",ddr_set_add); - - uint32_t write_size=0; - write_size=((ddr_set_size+SHA256_SUM_LEN+MESON_CPU_CHIP_ID_SIZE+511)/512)*512; - #if 1 - do_read_ddr_training_data(1,ddr_set_t_p); - #endif - if ((ddr_set_t_p->fast_boot[0])) - { - printf("\nuboot enable auto fast boot funciton \n"); - if ((verify_error)) - { - printf("\nuboot auto fast boot check verify data happen wrong \n"); - (ddr_set_t_p->fast_boot[0])=1; - } - } - else - return 1 ; - - if ((ddr_set_t_p->fast_boot[0]) == 0xff) - { - printf("\nuboot auto fast boot auto window test is done \n"); - return 1 ; - } - - printf("\n(ddr_set_t_p->fast_boot[0])==0x%08x\n",(ddr_set_t_p->fast_boot[0])); - - if ((ddr_set_t_p->fast_boot[0])<0xfe) - { - printf("\nuboot auto fast boot auto window test begin \n"); - { - ddr_set_t_p->fast_boot[0]=0xfe; - //#if 1 - //printf("print sha\n"); - //sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(ddr_set_add-32)); - //run_command(str,0); - sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0); - //printf("print sha\n"); - //sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(ddr_set_add-32)); - //run_command(str,0); - //#endif - write_size=((ddr_set_size+SHA256_SUM_LEN+MESON_CPU_CHIP_ID_SIZE+511)/512)*512; - { - #if 0 - #ifdef USE_FOR_UBOOT_2018 - sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,write_size); - #else - sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,write_size); - #endif - //sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add,ddr_set_size); - //sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add,ddr_set_size); - printf("\nstr=%s\n",str); - run_command(str,0); - #endif - - #if 0 - int argc2; - char* argv2[30]; - argc2=3; - sprintf(argv2[1],"0x%08x",ddr_set_add-SHA256_SUM_LEN); - sprintf(argv2[2],"0x%08x",write_size); - - do_ddr_store_write_ddr_parameter_ops(cmdtp,flag,argc2,argv2); - #endif - ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add-SHA256_SUM_LEN),write_size); - } - //verify_error=do_verify_flash_ddr_parameter(&ddr_sha,0); - //return 1; - sprintf(str,"g12_d2pll %d 0x11 %d 0 0 0 0 %d 0x%08x 0 %d",ddr_set_t_p->DRAMFreq[0],auto_window_test_enable_item,stick_dmc_ddr_window_test_read_vref_offset_value,auto_window_test_dq_size,pattern_dis_scramble); - printf("\nstr=%s\n",str); - - run_command(str,0); - } - return 1 ; - } - - if ((ddr_set_t_p->fast_boot[0]) == 0xfe) - { - char dmc_test_worst_window_rx=0; - char dmc_test_worst_window_tx=0; - - { - dwc_ddrphy_apb_wr((0<<20)|(0xd<<16)|(0<<12)|(0x0),0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel - - dmc_test_worst_window_tx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c2)); - dmc_test_worst_window_rx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c3)); - printf("\ndmc_test_worst_window_tx =%d \n",dmc_test_worst_window_tx); - printf("\ndmc_test_worst_window_rx=%d \n",dmc_test_worst_window_rx); - if (dmc_test_worst_window_tx>30) - dmc_test_worst_window_tx=30; - if (dmc_test_worst_window_rx>30) - dmc_test_worst_window_rx=30; - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c2),t4_write_worst_margin_rank1); - // dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c3),t4_read_worst_margin_rank1); - ddr_set_t_p->fast_boot[1]=(((dmc_test_worst_window_tx/2)<<4))|(((dmc_test_worst_window_rx/2))); - } - - ddr_set_t_p->fast_boot[0]=0xff; - { - printf("\nuboot auto fast boot auto window test finish \n"); - - if (ddr_set_t_p->fast_boot[2]) - { - if ((ddr_set_t_p->fast_boot[2])&0x7) - { - if (((ddr_set_t_p->fast_boot[2])&0x8)) - sprintf(str,"ddr_g12_offset_data 3 0x0 0 0 1 %d ",(ddr_set_t_p->fast_boot[2])&0x7); - else - sprintf(str,"ddr_g12_offset_data 3 0x0 0 0 2 %d ",(ddr_set_t_p->fast_boot[2])&0x7); - - printf("\nstr=%s\n",str); - - run_command(str,0); - } - if ((ddr_set_t_p->fast_boot[2])&0x70) - { - if (((ddr_set_t_p->fast_boot[2])&0x80)) - sprintf(str,"ddr_g12_offset_data 2 0x0 0 0 1 %d ",((ddr_set_t_p->fast_boot[2])>>4)&0x7); - else - sprintf(str,"ddr_g12_offset_data 2 0x0 0 0 2 %d ",((ddr_set_t_p->fast_boot[2])>>4)&0x7); - - printf("\nstr=%s\n",str); - - run_command(str,0); - } - - sprintf(str,"ddr_fast_boot 1 "); - printf("\nstr=%s\n",str); - run_command(str,0); - } - else - { - // #if 1 - // printf("&ddr_sha.ddrs : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.ddrs); - // printf("&ddr_sha.sha2 : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.sha2); - // printf("ddr_set_add : 0x%x\n", (uint32_t)(uint64_t)ddr_set_add); - - sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0); - // printf("print sha\n"); - // sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(ddr_set_add-32)); - // run_command(str,0); - // #endif - #if 0 - { - #ifdef USE_FOR_UBOOT_2018 - sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,write_size); - #else - sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,write_size); - #endif - printf("\nstr=%s\n",str); - run_command(str,0); - } - #endif - ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add-SHA256_SUM_LEN),write_size); - } return 1; } } + enable_ddr_check_boot_reason = 0; + enable_ddr_check_boot_reason = env_to_a_num("enable_ddr_check_boot_reason"); + printf("\nenable_ddr_check_boot_reason==%d \n", enable_ddr_check_boot_reason); + printf("\nddr_fast_boot_enable_flag==%d \n", env_to_a_num("ddr_fast_boot_enable_flag")); + ddr_set_t_c2 *ddr_set_t_p = NULL; + ddr_set_t_p = (ddr_set_t_c2 *)(ddr_set_t_p_arrary_c2); + uint32_t ddr_set_add = 0; + ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p); + ddr_set_size = sizeof(ddr_set_t_c2); + printf("\nddr_set_t_p==0x%08x\n", ddr_set_add); +#define DMC_PHY_RETRAINING_CTRL (p_ddr_base->ddr_dmc_lpdd4_retraining_address) + uint32_t dmc_retraining_ctrl = 0; + dmc_retraining_ctrl = rd_reg(DMC_PHY_RETRAINING_CTRL); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl & (~(1 << 31))); + uint32_t write_size = 0; + write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512; + do_read_c2_ddr_training_data(1, ddr_set_t_p); + + if (((ddr_set_t_p->cfg_board_common_setting.fast_boot[3]) & 0xc0) && ((ddr_set_t_p->cfg_board_common_setting.fast_boot[3]) & 0x3f)) { + enable_ddr_check_boot_reason = 0; + + if (((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) > 0) && ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) < 0xff)) { + (ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) = 0xfe; + (verify_error) = 0; + } + } + + if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0])) { + printf("\nuboot enable auto fast boot funciton \n"); + + if ((verify_error)) { + printf("\nuboot auto fast boot check verify data happen wrong \n"); + (ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) = 1; + } + } else { + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } + + if (enable_ddr_check_boot_reason) { + boot_reason = 0; //ddr_set_t_p->boot_reason + { + if ((((readl(p_ddr_base->ddr_boot_reason_address) >> 0) & 0xf) == AMLOGIC_COLD_BOOT) && ((rd_reg(HOT_BOOT_STICKY_ADD)) == HOT_BOOT_MAGIC)) + boot_reason = 1; + + if (ddr_set_t_p->cfg_board_common_setting.fast_boot[0] == 0xfe) + boot_reason = 2; + } + printf("\nboot_reason=%08x \n", (boot_reason)); + printf("\nHOT_BOOT_STICKY_ADD=%08x \n", (rd_reg(HOT_BOOT_STICKY_ADD))); + wr_reg(HOT_BOOT_STICKY_ADD, HOT_BOOT_MAGIC); + printf("\nHOT_BOOT_STICKY_ADD=%08x \n", (rd_reg(HOT_BOOT_STICKY_ADD))); + + if (boot_reason == 0) { + if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) < 0xfe) { + need_ddr_window_test = 1; + sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + } else { + sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } else { + sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + } + + if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) == 0xff) { + printf("\nuboot auto fast boot auto window test is done \n"); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } + + if (skip_window_test_enable) { + printf("enable skip window test fast boot mode! \n"); + ddr_set_t_p->cfg_board_common_setting.fast_boot[0] = 0xfe; + } + printf("\n(ddr_set_t_p->cfg_board_common_setting.fast_boot[0])==0x%08x\n", (ddr_set_t_p->cfg_board_common_setting.fast_boot[0])); + + if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) < 0xfe) { + printf("\nuboot auto fast boot auto window test begin \n"); + { + ddr_set_t_p->cfg_board_common_setting.fast_boot[0] = 0xfd; //0xfd for check unexcept power off status + sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t_c2), ddr_sha_c2.sha2, 0); + write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512; + { + ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size); + } + sprintf(str, "g12_d2pll %d 0x11 %d 0 0 0 0 %d 0x%08x 0 %d", ddr_set_t_p->cfg_board_SI_setting_ps[0].DRAMFreq, auto_window_test_enable_item, stick_dmc_ddr_window_test_read_vref_offset_value, auto_window_test_dq_size, pattern_dis_scramble); + printf("\nstr=%s\n", str); + + run_command(str, 0); + } + return 1; + } + + if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) == 0xfe) { +#if 0 + char dmc_test_worst_window_rx = 0; + char dmc_test_worst_window_tx = 0; + + { + dwc_ddrphy_apb_wr((0 << 20) | (0xd << 16) | (0 << 12) | (0x0), 0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel + + dmc_test_worst_window_tx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c2)); + dmc_test_worst_window_rx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c3)); + printf("\ndmc_test_worst_window_tx =%d \n", dmc_test_worst_window_tx); + printf("\ndmc_test_worst_window_rx=%d \n", dmc_test_worst_window_rx); + + if (dmc_test_worst_window_tx > 30) + dmc_test_worst_window_tx = 30; + + if (dmc_test_worst_window_rx > 30) + dmc_test_worst_window_rx = 30; + ddr_set_t_p->fast_boot[1] = (((dmc_test_worst_window_tx / 2) << 4)) | (((dmc_test_worst_window_rx / 2))); + } +#endif + ddr_set_t_p->cfg_board_common_setting.fast_boot[0] = 0xff; + { + printf("\nuboot auto fast boot auto window test finish \n"); + + if (ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) { + if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x7) { + if (((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x8)) + sprintf(str, "ddr_g12_offset_data 3 0x0 0 0 1 %d ", (ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x7); + else + sprintf(str, "ddr_g12_offset_data 3 0x0 0 0 2 %d ", (ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x7); + printf("\nstr=%s\n", str); + + run_command(str, 0); + } + + if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x70) { + if (((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x80)) + sprintf(str, "ddr_g12_offset_data 2 0x0 0 0 1 %d ", ((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) >> 4) & 0x7); + else + sprintf(str, "ddr_g12_offset_data 2 0x0 0 0 2 %d ", ((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) >> 4) & 0x7); + printf("\nstr=%s\n", str); + + run_command(str, 0); + } + sprintf(str, "ddr_fast_boot 1 "); + printf("\nstr=%s\n", str); + run_command(str, 0); + } else { + sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t_c2), ddr_sha_c2.sha2, 0); + ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size); + } + + if ((enable_ddr_check_boot_reason)) { + if (boot_reason) { + sprintf(str, "systemoff"); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + } + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } + } + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; +} /* do_ddr_auto_fastboot_check_c2 */ + +int do_ddr_auto_fastboot_check(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + check_base_address(); +#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT (1 << 5) +#define AUTO_WINDOW_TEST_ENABLE_ITEM ((1 << 1) | (1 << 2)) + char *endp; + char auto_window_test_enable_item = DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT; + uint32_t auto_window_test_dq_size = 0; + char pattern_dis_scramble = 0; + uint32_t stick_dmc_ddr_window_test_read_vref_offset_value = 0; + uint32_t ddr_set_size = 0; + uint32_t need_ddr_window_test = 0; + uint32_t skip_window_test_enable = 0; + if (argc > 1) { + auto_window_test_enable_item = simple_strtoull_ddr(argv[1], &endp, 0); + if (*argv[1] == 0 || *endp != 0) + auto_window_test_enable_item = DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT; + } + if (argc > 2) { + auto_window_test_dq_size = simple_strtoull_ddr(argv[2], &endp, 0); + if (*argv[2] == 0 || *endp != 0) + auto_window_test_dq_size = 0; + } + if (argc > 3) { + pattern_dis_scramble = simple_strtoull_ddr(argv[3], &endp, 0); + if (*argv[3] == 0 || *endp != 0) + pattern_dis_scramble = 0; + } + if (argc > 4) { + stick_dmc_ddr_window_test_read_vref_offset_value = simple_strtoull_ddr(argv[4], &endp, 0); + if (*argv[4] == 0 || *endp != 0) + stick_dmc_ddr_window_test_read_vref_offset_value = 0; + } + if (argc > 5) { + skip_window_test_enable = simple_strtoull_ddr(argv[5], &endp, 0); + if (*argv[5] == 0 || *endp != 0) + skip_window_test_enable = 0; + } + if ((p_ddr_base->chip_id >= MESON_CPU_MAJOR_ID_C2) && (p_ddr_base->chip_id <= MESON_CPU_MAJOR_ID_T5D)) { + do_ddr_auto_fastboot_check_c2(auto_window_test_enable_item,auto_window_test_dq_size,pattern_dis_scramble,stick_dmc_ddr_window_test_read_vref_offset_value,skip_window_test_enable); + return 1; + } + char str[1024] = ""; + int verify_error = 0; + verify_error = do_verify_flash_ddr_parameter(1); + if ((verify_error) == 0) { + if ((ddr_sha.ddrs.fast_boot[0]) == 0xff) { + printf("\nuboot auto fast boot check flash data is ok return \n"); + return 1; + } + } + enable_ddr_check_boot_reason = 0; + enable_ddr_check_boot_reason = env_to_a_num("enable_ddr_check_boot_reason"); + printf("\nenable_ddr_check_boot_reason==%d \n", enable_ddr_check_boot_reason); + printf("\nddr_fast_boot_enable_flag==%d \n", env_to_a_num("ddr_fast_boot_enable_flag")); + ddr_set_t *ddr_set_t_p = NULL; + ddr_set_t_p = (ddr_set_t *)(ddr_set_t_p_arrary); + uint32_t ddr_set_add = 0; + + ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p); + ddr_set_size = sizeof(ddr_set_t); + printf("\nddr_set_t_p==0x%08x\n", ddr_set_add); + #define DMC_PHY_RETRAINING_CTRL (p_ddr_base->ddr_dmc_lpdd4_retraining_address) + uint32_t dmc_retraining_ctrl = 0; + dmc_retraining_ctrl = rd_reg(DMC_PHY_RETRAINING_CTRL); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl & (~(1 << 31))); + uint32_t write_size = 0; + write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512; + do_read_ddr_training_data(1, ddr_set_t_p); + if (((ddr_set_t_p->fast_boot[3]) & 0xc0) && ((ddr_set_t_p->fast_boot[3]) & 0x3f)) { + enable_ddr_check_boot_reason = 0; + if (((ddr_set_t_p->fast_boot[0]) > 0) && ((ddr_set_t_p->fast_boot[0]) < 0xff)) { + (ddr_set_t_p->fast_boot[0]) = 0xfe; + (verify_error) = 0; + } + } + if ((ddr_set_t_p->fast_boot[0])) { + printf("\nuboot enable auto fast boot funciton \n"); + if ((verify_error)) { + printf("\nuboot auto fast boot check verify data happen wrong \n"); + (ddr_set_t_p->fast_boot[0]) = 1; + } + } else { + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } + + if (enable_ddr_check_boot_reason) { + boot_reason = 0; //ddr_set_t_p->boot_reason + { + if ((((readl(p_ddr_base->ddr_boot_reason_address) >> 12) & 0xf) == AMLOGIC_COLD_BOOT) && ((rd_reg(HOT_BOOT_STICKY_ADD)) == HOT_BOOT_MAGIC)) + boot_reason = 1; + if (ddr_set_t_p->fast_boot[0] == 0xfe) + boot_reason = 2; + } + printf("\nboot_reason=%08x \n", (boot_reason)); + printf("\nHOT_BOOT_STICKY_ADD=%08x \n", (rd_reg(HOT_BOOT_STICKY_ADD))); + wr_reg(HOT_BOOT_STICKY_ADD, HOT_BOOT_MAGIC); + printf("\nHOT_BOOT_STICKY_ADD=%08x \n", (rd_reg(HOT_BOOT_STICKY_ADD))); + + if (boot_reason == 0) { + if ((ddr_set_t_p->fast_boot[0]) < 0xfe) { + need_ddr_window_test = 1; + sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + } else { + sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } else { + sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + } + if ((ddr_set_t_p->fast_boot[0]) == 0xff) { + printf("\nuboot auto fast boot auto window test is done \n"); + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } + if (skip_window_test_enable) { + printf("enable skip window test fast boot mode! \n"); + ddr_set_t_p->fast_boot[0] = 0xfe; + } + printf("\n(ddr_set_t_p->fast_boot[0])==0x%08x\n", (ddr_set_t_p->fast_boot[0])); + + if ((ddr_set_t_p->fast_boot[0]) < 0xfe) { + printf("\nuboot auto fast boot auto window test begin \n"); + { + ddr_set_t_p->fast_boot[0] = 0xfd; //0xfd for check unexcept power off status + sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0); + write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512; + { + ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size); + } + sprintf(str, "g12_d2pll %d 0x11 %d 0 0 0 0 %d 0x%08x 0 %d", ddr_set_t_p->DRAMFreq[0], auto_window_test_enable_item, stick_dmc_ddr_window_test_read_vref_offset_value, auto_window_test_dq_size, pattern_dis_scramble); + printf("\nstr=%s\n", str); + + run_command(str, 0); + } + return 1; + } + + if ((ddr_set_t_p->fast_boot[0]) == 0xfe) { + char dmc_test_worst_window_rx = 0; + char dmc_test_worst_window_tx = 0; + + { + dwc_ddrphy_apb_wr((0 << 20) | (0xd << 16) | (0 << 12) | (0x0), 0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel + + dmc_test_worst_window_tx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c2)); + dmc_test_worst_window_rx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c3)); + printf("\ndmc_test_worst_window_tx =%d \n", dmc_test_worst_window_tx); + printf("\ndmc_test_worst_window_rx=%d \n", dmc_test_worst_window_rx); + if (dmc_test_worst_window_tx > 30) + dmc_test_worst_window_tx = 30; + if (dmc_test_worst_window_rx > 30) + dmc_test_worst_window_rx = 30; + ddr_set_t_p->fast_boot[1] = (((dmc_test_worst_window_tx / 2) << 4)) | (((dmc_test_worst_window_rx / 2))); + } + + ddr_set_t_p->fast_boot[0] = 0xff; + { + printf("\nuboot auto fast boot auto window test finish \n"); + + if (ddr_set_t_p->fast_boot[2]) { + if ((ddr_set_t_p->fast_boot[2]) & 0x7) { + if (((ddr_set_t_p->fast_boot[2]) & 0x8)) + sprintf(str, "ddr_g12_offset_data 3 0x0 0 0 1 %d ", (ddr_set_t_p->fast_boot[2]) & 0x7); + else + sprintf(str, "ddr_g12_offset_data 3 0x0 0 0 2 %d ", (ddr_set_t_p->fast_boot[2]) & 0x7); + + printf("\nstr=%s\n", str); + + run_command(str, 0); + } + if ((ddr_set_t_p->fast_boot[2]) & 0x70) { + if (((ddr_set_t_p->fast_boot[2]) & 0x80)) + sprintf(str, "ddr_g12_offset_data 2 0x0 0 0 1 %d ", ((ddr_set_t_p->fast_boot[2]) >> 4) & 0x7); + else + sprintf(str, "ddr_g12_offset_data 2 0x0 0 0 2 %d ", ((ddr_set_t_p->fast_boot[2]) >> 4) & 0x7); + + printf("\nstr=%s\n", str); + + run_command(str, 0); + } + + sprintf(str, "ddr_fast_boot 1 "); + printf("\nstr=%s\n", str); + run_command(str, 0); + } else { + sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0); + ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size); + } + if ((enable_ddr_check_boot_reason)) { + if (boot_reason) { + sprintf(str, "systemoff"); + printf("\nstr=%s\n", str); + run_command(str, 0); + } + } + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); + return 1; + } + } + wr_reg(DMC_PHY_RETRAINING_CTRL, dmc_retraining_ctrl); return 1; } + U_BOOT_CMD( - ddr_auto_scan_drv, 30, 1, do_ddr_auto_scan_drv, + ddr_auto_scan_drv, 30, 1, do_ddr_auto_scan_drv, "ddr_test_cmd cmd arg1 arg2 arg3...", "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n" ); + U_BOOT_CMD( - ddr_fast_boot, 30, 1, do_ddr_fastboot_config, - "ddr_fastboot_config cmd arg1 arg2 arg3...", - "ddr_fastboot_config cmd arg1 arg2 arg3... \n dcache off ? \n" - ); -U_BOOT_CMD( - ddr_auto_fast_boot_check, 30, 1, do_ddr_auto_fastboot_check, + ddr_fast_boot, 30, 1, do_ddr_fastboot_config, "ddr_fastboot_config cmd arg1 arg2 arg3...", "ddr_fastboot_config cmd arg1 arg2 arg3... \n dcache off ? \n" ); +U_BOOT_CMD( + ddr_auto_fast_boot_check, 30, 1, do_ddr_auto_fastboot_check, + "ddr_fastboot_config cmd arg1 arg2 arg3...", + "ddr_fastboot_config cmd arg1 arg2 arg3... \n dcache off ? \n" + );
diff --git a/cmd/amlogic/cmd_dolbyvision.c b/cmd/amlogic/cmd_dolbyvision.c new file mode 100644 index 0000000..95ddee5 --- /dev/null +++ b/cmd/amlogic/cmd_dolbyvision.c
@@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <malloc.h> +#include <asm/byteorder.h> +#include <amlogic/media/dv/dolby_vision.h> + +static int do_dolbyvision_process(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + dolby_vision_process(); + return 1; +} + +static int do_dolbyvision_set(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + apply_stb_core_settings(); + return 1; +} + +static int do_hdmi_package(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + send_hdmi_pkt(); + return 1; +} + +static int do_read_reg(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned long tmp_addr = 0; + + tmp_addr = simple_strtoul(argv[1], NULL, 16); + dv_read_reg((unsigned int)tmp_addr); + printf("addr:%lx, value: %x\n", tmp_addr, + dv_read_reg((unsigned int)tmp_addr)); + return 1; +} + +static int do_write_reg(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned long tmp_addr = 0; + unsigned long tmp_value = 0; + + tmp_addr = simple_strtoul(argv[1], NULL, 16); + tmp_value = simple_strtoul(argv[2], NULL, 16); + dv_write_reg((unsigned int)tmp_addr,(unsigned int)tmp_value); + printf("addr:%lx, value: %x\n", tmp_addr, + dv_read_reg((unsigned int)tmp_addr)); + return 1; +} + +static int do_dolbyvision_debug(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret = 0; + int enable = 0; + unsigned long value = 0; + + if (argc == 2) { + value = simple_strtoul(argv[1], NULL, 16); + switch (value) { + case 0: + dolbyvision_debug(0); + break; + case 1: + dolbyvision_debug(1); + break; + case 2: + dolbyvision_dump_setting(); + break; + default: + cmd_usage(cmdtp); + break; + } + } else { + return cmd_usage(cmdtp); + } + + return ret; +} + +static cmd_tbl_t cmd_dovi_sub[] = { + U_BOOT_CMD_MKENT(process, 1, 1, do_dolbyvision_process, "", ""), + U_BOOT_CMD_MKENT(pkg, 1, 1, do_hdmi_package, "", ""), + U_BOOT_CMD_MKENT(set, 1, 1, do_dolbyvision_set, "", ""), + U_BOOT_CMD_MKENT(rv, 2, 1, do_read_reg, "", ""), + U_BOOT_CMD_MKENT(wv, 3, 1, do_write_reg, "", ""), + U_BOOT_CMD_MKENT(debug, 2, 0, do_dolbyvision_debug, "", ""), +}; + +static int do_dolby_vision(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return cmd_usage(cmdtp); + + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_dovi_sub[0], ARRAY_SIZE(cmd_dovi_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return cmd_usage(cmdtp); +} + +U_BOOT_CMD(dovi, CONFIG_SYS_MAXARGS, 0, do_dolby_vision, + "Dolby_vision sub-system", + "set------------ apply core settings \n" + "dovi pkg--------------send hdmi pkt\n" + "dovi rv---------------Dolby_vision read registers\n" + "dovi wv---------------Dolby_vision write registers\n" + "dovi debug------------0: disable debug; 1:enable debug; 2: dump setting\n" +);
diff --git a/cmd/amlogic/cmd_dynamic.c b/cmd/amlogic/cmd_dynamic.c new file mode 100644 index 0000000..f1f9dec --- /dev/null +++ b/cmd/amlogic/cmd_dynamic.c
@@ -0,0 +1,673 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <malloc.h> +#include <asm/byteorder.h> +#include <config.h> +#include <asm/arch/io.h> +#include <emmc_partitions.h> +#include <partition_table.h> +#include <version.h> +#include <amlogic/storage.h> + +#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK + +/* Magic signature for LpMetadataGeometry. */ +#define LP_METADATA_GEOMETRY_MAGIC 0x616c4467 + +/* Space reserved for geometry information. */ +#define LP_METADATA_GEOMETRY_SIZE 4096 + +#define LP_METADATA_HEADER_SIZE 124 + +#define SUPERBUF_SIZE 16384 + +/* Magic signature for LpMetadataHeader. */ +#define LP_METADATA_HEADER_MAGIC 0x414C5030 + +/* Current metadata version. */ +#define LP_METADATA_MAJOR_VERSION 10 +#define LP_METADATA_MINOR_VERSION_MIN 0 +#define LP_METADATA_MINOR_VERSION_MAX 2 + +/* Attributes for the LpMetadataPartition::attributes field. + * + * READONLY - The partition should not be considered writable. When used with + * device mapper, the block device will be created as read-only. + */ +#define LP_PARTITION_ATTR_NONE 0x0 +#define LP_PARTITION_ATTR_READONLY (1 << 0) + +/* This flag is only intended to be used with super_empty.img and super.img on + * retrofit devices. On these devices there are A and B super partitions, and + * we don't know ahead of time which slot the image will be applied to. + * + * If set, the partition name needs a slot suffix applied. The slot suffix is + * determined by the metadata slot number (0 = _a, 1 = _b). + */ +#define LP_PARTITION_ATTR_SLOT_SUFFIXED (1 << 1) + +/* Mask that defines all valid attributes. */ +#define LP_PARTITION_ATTRIBUTE_MASK (LP_PARTITION_ATTR_READONLY | LP_PARTITION_ATTR_SLOT_SUFFIXED) + +/* Default name of the physical partition that holds logical partition entries. + * The layout of this partition will look like: + * + * +--------------------+ + * | Disk Geometry | + * +--------------------+ + * | Geometry Backup | + * +--------------------+ + * | Metadata | + * +--------------------+ + * | Backup Metadata | + * +--------------------+ + * | Logical Partitions | + * +--------------------+ + */ +#define LP_METADATA_DEFAULT_PARTITION_NAME "super" + +/* Size of a sector is always 512 bytes for compatibility with the Linux kernel. */ +#define LP_SECTOR_SIZE 512 + +/* Amount of space reserved at the start of every super partition to avoid + * creating an accidental boot sector. + */ +#define LP_PARTITION_RESERVED_BYTES 4096 + +/* This structure is stored at block 0 in the first 4096 bytes of the + * partition, and again in the following block. It is never modified and + * describes how logical partition information can be located. + */ +typedef struct LpMetadataGeometry { + /* 0: Magic signature (LP_METADATA_GEOMETRY_MAGIC). */ + uint32_t magic; + + /* 4: Size of the LpMetadataGeometry struct. */ + uint32_t struct_size; + + /* 8: SHA256 checksum of this struct, with this field set to 0. */ + uint8_t checksum[32]; + + /* 40: Maximum amount of space a single copy of the metadata can use. This + * must be a multiple of LP_SECTOR_SIZE. + */ + uint32_t metadata_max_size; + + /* 44: Number of copies of the metadata to keep. For A/B devices, this + * will be 2. For an A/B/C device, it would be 3, et cetera. For Non-A/B + * it will be 1. A backup copy of each slot is kept, so if this is "2", + * there will be four copies total. + */ + uint32_t metadata_slot_count; + + /* 48: Logical block size. This is the minimal alignment for partition and + * extent sizes, and it must be a multiple of LP_SECTOR_SIZE. Note that + * this must be equal across all LUNs that comprise the super partition, + * and thus this field is stored in the geometry, not per-device. + */ + uint32_t logical_block_size; +} __attribute__((packed)) LpMetadataGeometry; + +/* The logical partition metadata has a number of tables; they are described + * in the header via the following structure. + * + * The size of the table can be computed by multiplying entry_size by + * num_entries, and the result must not overflow a 32-bit signed integer. + */ +typedef struct LpMetadataTableDescriptor { + /* 0: Location of the table, relative to end of the metadata header. */ + uint32_t offset; + /* 4: Number of entries in the table. */ + uint32_t num_entries; + /* 8: Size of each entry in the table, in bytes. */ + uint32_t entry_size; +} __attribute__((packed)) LpMetadataTableDescriptor; + +/* Binary format for the header of the logical partition metadata format. + * + * The format has three sections. The header must occur first, and the + * proceeding tables may be placed in any order after. + * + * +-----------------------------------------+ + * | Header data - fixed size | + * +-----------------------------------------+ + * | Partition table - variable size | + * +-----------------------------------------+ + * | Partition table extents - variable size | + * +-----------------------------------------+ + * + * The "Header" portion is described by LpMetadataHeader. It will always + * precede the other three blocks. + * + * All fields are stored in little-endian byte order when serialized. + * + * This struct is versioned; see the |major_version| and |minor_version| + * fields. + */ +typedef struct LpMetadataHeader { + /* 0: Four bytes equal to LP_METADATA_HEADER_MAGIC. */ + uint32_t magic; + + /* 4: Version number required to read this metadata. If the version is not + * equal to the library version, the metadata should be considered + * incompatible. + */ + uint16_t major_version; + + /* 6: Minor version. A library supporting newer features should be able to + * read metadata with an older minor version. However, an older library + * should not support reading metadata if its minor version is higher. + */ + uint16_t minor_version; + + /* 8: The size of this header struct. */ + uint32_t header_size; + + /* 12: SHA256 checksum of the header, up to |header_size| bytes, computed as + * if this field were set to 0. + */ + uint8_t header_checksum[32]; + + /* 44: The total size of all tables. This size is contiguous; tables may not + * have gaps in between, and they immediately follow the header. + */ + uint32_t tables_size; + + /* 48: SHA256 checksum of all table contents. */ + uint8_t tables_checksum[32]; + + /* 80: Partition table descriptor. */ + LpMetadataTableDescriptor partitions; + /* 92: Extent table descriptor. */ + LpMetadataTableDescriptor extents; + /* 104: Updateable group descriptor. */ + LpMetadataTableDescriptor groups; + /* 116: Block device table. */ + LpMetadataTableDescriptor block_devices; +} __attribute__((packed)) LpMetadataHeader; + +/* This struct defines a logical partition entry, similar to what would be + * present in a GUID Partition Table. + */ +typedef struct LpMetadataPartition { + /* 0: Name of this partition in ASCII characters. Any unused characters in + * the buffer must be set to 0. Characters may only be alphanumeric or _. + * The name must include at least one ASCII character, and it must be unique + * across all partition names. The length (36) is the same as the maximum + * length of a GPT partition name. + */ + char name[36]; + + /* 36: Attributes for the partition (see LP_PARTITION_ATTR_* flags above). */ + uint32_t attributes; + + /* 40: Index of the first extent owned by this partition. The extent will + * start at logical sector 0. Gaps between extents are not allowed. + */ + uint32_t first_extent_index; + + /* 44: Number of extents in the partition. Every partition must have at + * least one extent. + */ + uint32_t num_extents; + + /* 48: Group this partition belongs to. */ + uint32_t group_index; +} __attribute__((packed)) LpMetadataPartition; + +/* This extent is a dm-linear target, and the index is an index into the + * LinearExtent table. + */ +#define LP_TARGET_TYPE_LINEAR 0 + +/* This extent is a dm-zero target. The index is ignored and must be 0. */ +#define LP_TARGET_TYPE_ZERO 1 + +/* This struct defines an extent entry in the extent table block. */ +typedef struct LpMetadataExtent { + /* 0: Length of this extent, in 512-byte sectors. */ + uint64_t num_sectors; + + /* 8: Target type for device-mapper (see LP_TARGET_TYPE_* values). */ + uint32_t target_type; + + /* 12: Contents depends on target_type. + * + * LINEAR: The sector on the physical partition that this extent maps onto. + * ZERO: This field must be 0. + */ + uint64_t target_data; + + /* 20: Contents depends on target_type. + * + * LINEAR: Must be an index into the block devices table. + * ZERO: This field must be 0. + */ + uint32_t target_source; +} __attribute__((packed)) LpMetadataExtent; + +/* This struct defines an entry in the groups table. Each group has a maximum + * size, and partitions in a group must not exceed that size. There is always + * a "default" group of unlimited size, which is used when not using update + * groups or when using overlayfs or fastbootd. + */ +typedef struct LpMetadataPartitionGroup { + /* 0: Name of this group. Any unused characters must be 0. */ + char name[36]; + + /* 36: Flags (see LP_GROUP_*). */ + uint32_t flags; + + /* 40: Maximum size in bytes. If 0, the group has no maximum size. */ + uint64_t maximum_size; +} __attribute__((packed)) LpMetadataPartitionGroup; + +/* This flag is only intended to be used with super_empty.img and super.img on + * retrofit devices. If set, the group needs a slot suffix to be interpreted + * correctly. The suffix is automatically applied by ReadMetadata(). + */ +#define LP_GROUP_SLOT_SUFFIXED (1 << 0) + +/* This struct defines an entry in the block_devices table. There must be at + * least one device, and the first device must represent the partition holding + * the super metadata. + */ +typedef struct LpMetadataBlockDevice { + /* 0: First usable sector for allocating logical partitions. this will be + * the first sector after the initial geometry blocks, followed by the + * space consumed by metadata_max_size*metadata_slot_count*2. + */ + uint64_t first_logical_sector; + + /* 8: Alignment for defining partitions or partition extents. For example, + * an alignment of 1MiB will require that all partitions have a size evenly + * divisible by 1MiB, and that the smallest unit the partition can grow by + * is 1MiB. + * + * Alignment is normally determined at runtime when growing or adding + * partitions. If for some reason the alignment cannot be determined, then + * this predefined alignment in the geometry is used instead. By default + * it is set to 1MiB. + */ + uint32_t alignment; + + /* 12: Alignment offset for "stacked" devices. For example, if the "super" + * partition itself is not aligned within the parent block device's + * partition table, then we adjust for this in deciding where to place + * |first_logical_sector|. + * + * Similar to |alignment|, this will be derived from the operating system. + * If it cannot be determined, it is assumed to be 0. + */ + uint32_t alignment_offset; + + /* 16: Block device size, as specified when the metadata was created. This + * can be used to verify the geometry against a target device. + */ + uint64_t size; + + /* 24: Partition name in the GPT. Any unused characters must be 0. */ + char partition_name[36]; + + /* 60: Flags (see LP_BLOCK_DEVICE_* flags below). */ + uint32_t flags; +} __attribute__((packed)) LpMetadataBlockDevice; + +/* This flag is only intended to be used with super_empty.img and super.img on + * retrofit devices. On these devices there are A and B super partitions, and + * we don't know ahead of time which slot the image will be applied to. + * + * If set, the block device needs a slot suffix applied before being used with + * IPartitionOpener. The slot suffix is determined by the metadata slot number + * (0 = _a, 1 = _b). + */ +#define LP_BLOCK_DEVICE_SLOT_SUFFIXED (1 << 0) + + +typedef struct PartitionList +{ + char name[128]; + struct PartitionList* next; +}__attribute__((packed)) PartitionList; + +PartitionList* part_list = NULL; + +void printlist(void) +{ + PartitionList* node = part_list; + while (NULL != node) + { + printf("name: %s\n",node->name); + node = node->next; + } +} + +int GetPrimaryGeometryOffset(void) { + int offset = LP_PARTITION_RESERVED_BYTES; + return offset; +} + +int GetBackupGeometryOffset(void) { + int offset = GetPrimaryGeometryOffset() + LP_METADATA_GEOMETRY_SIZE; + return offset; +} + +int GetPrimaryMetadataOffset(LpMetadataGeometry* geometry, int slot_number) { + int offset = LP_PARTITION_RESERVED_BYTES + (LP_METADATA_GEOMETRY_SIZE * 2) + + geometry->metadata_max_size * slot_number; + printf("GetPrimaryMetadataOffset : %d\n", offset); + return offset; +} + +int GetBackupMetadataOffset(LpMetadataGeometry* geometry, int slot_number) { + int start = LP_PARTITION_RESERVED_BYTES + (LP_METADATA_GEOMETRY_SIZE * 2) + + geometry->metadata_max_size * geometry->metadata_slot_count; + printf("GetBackupMetadataOffset : %d\n", start + geometry->metadata_max_size * slot_number); + return start + geometry->metadata_max_size * slot_number; +} + +int GetTotalMetadataSize(int metadata_max_size, int max_slots) { + return LP_PARTITION_RESERVED_BYTES + + (LP_METADATA_GEOMETRY_SIZE + metadata_max_size * max_slots) * 2; +} + +int ParseGeometry(const void* buffer, LpMetadataGeometry* geometry) { + memcpy(geometry, buffer, sizeof(LpMetadataGeometry)); + + // Check the magic signature. + if (geometry->magic != LP_METADATA_GEOMETRY_MAGIC) { + printf("Logical partition metadata has invalid geometry magic signature\n"); + return -1; + } + // Reject if the struct size is larger than what we compiled. This is so we + // can compute a checksum with the |struct_size| field rather than using + // sizeof. + if (geometry->struct_size > sizeof(LpMetadataGeometry)) { + printf("Logical partition metadata has unrecognized fields.\n"); + return -1; + } + + // Check that the struct size is equal (this will have to change if we ever + // change the struct size in a release). + if (geometry->struct_size != sizeof(LpMetadataGeometry)) { + printf("Logical partition metadata has invalid struct size.\n"); + return -1; + } + if (geometry->metadata_slot_count == 0) { + printf("Logical partition metadata has invalid slot count.\n"); + return -1; + } + if (geometry->metadata_max_size % LP_SECTOR_SIZE != 0) { + printf("Metadata max size is not sector-aligned.\n"); + return -1; + } + return 0; +} + +int ReadPrimaryGeometry(char *superbuf, LpMetadataGeometry* geometry) { + char buffer[LP_METADATA_GEOMETRY_SIZE]; + memcpy(buffer, superbuf+LP_PARTITION_RESERVED_BYTES, LP_METADATA_GEOMETRY_SIZE); + return ParseGeometry(buffer, geometry); +} + +int ReadBackupGeometry(char *superbuf, LpMetadataGeometry* geometry) { + char buffer[LP_METADATA_GEOMETRY_SIZE]; + memcpy(buffer, superbuf+LP_PARTITION_RESERVED_BYTES+LP_METADATA_GEOMETRY_SIZE, LP_METADATA_GEOMETRY_SIZE); + return ParseGeometry(buffer, geometry); +} + +// Read and validate geometry information from a block device that holds +// logical partitions. If the information is corrupted, this will attempt +// to read it from a secondary backup location. +int ReadLogicalPartitionGeometry(char *superbuf, LpMetadataGeometry* geometry) { + if (ReadPrimaryGeometry(superbuf, geometry) == 0) { + return 0; + } + return ReadBackupGeometry(superbuf, geometry); +} + +static int ValidateMetadataHeader(LpMetadataHeader* header) { + // Do basic validation of key metadata bits. + if (header->magic != LP_METADATA_HEADER_MAGIC) { + printf("Logical partition metadata has invalid magic value.\n"); + return -1; + } + // Check that the version is compatible. + if (header->major_version != LP_METADATA_MAJOR_VERSION || + header->minor_version > LP_METADATA_MINOR_VERSION_MAX) { + printf("Logical partition metadata has incompatible version.\n"); + return -1; + } + /*if (!ValidateTableBounds(header, &header->partitions) || + !ValidateTableBounds(header, &header->extents) || + !ValidateTableBounds(header, &header->groups) || + !ValidateTableBounds(header, &header->block_devices)) { + printf("Logical partition metadata has invalid table bounds.\n"); + return -1; + }*/ + // Check that table entry sizes can accomodate their respective structs. If + // table sizes change, these checks will have to be adjusted. + if (header->partitions.entry_size != sizeof(LpMetadataPartition)) { + printf("Logical partition metadata has invalid partition table entry size.\n"); + return -1; + } + if (header->extents.entry_size != sizeof(LpMetadataExtent)) { + printf("Logical partition metadata has invalid extent table entry size.\n"); + return -1; + } + if (header->groups.entry_size != sizeof(LpMetadataPartitionGroup)) { + printf("Logical partition metadata has invalid group table entry size.\n"); + return -1; + } + return 0; +} + + +int ReadMetadataHeader(char *superbuf, LpMetadataHeader* header, + LpMetadataGeometry* geometry, int slot_number) { + char* buffer = NULL; + int cursor = 0; + PartitionList* tail = NULL ; + PartitionList* node = NULL ; + int ishead = 0; + int i; + int index = 0; + char* flag; + + printf("metaoffset: %d\n", GetPrimaryMetadataOffset(geometry, slot_number)); + + memcpy(header, superbuf + GetPrimaryMetadataOffset(geometry, slot_number), sizeof(LpMetadataHeader)); + if (ValidateMetadataHeader(header) != 0) { + return -1; + } + + printf("header table size = %d\n", header->tables_size); + buffer = (char*)malloc(header->tables_size); + if (buffer == NULL) { + printf("Out of memory reading logical partition tables.\n"); + return -1; + } + + index = GetPrimaryMetadataOffset(geometry, slot_number) + sizeof(LpMetadataHeader); +#ifdef CONFIG_CMD_BOOTCTOL_VAB + flag = CONFIG_CMD_BOOTCTOL_VAB; + strcpy(flag, CONFIG_CMD_BOOTCTOL_VAB); + printf("CONFIG_CMD_BOOTCTOL_VAB: %s \n", CONFIG_CMD_BOOTCTOL_VAB); + if ((strcmp(flag, "1") == 0) && (has_boot_slot == 1)) { + index = index + 128; + } +#endif + + memcpy(buffer, superbuf + index, header->tables_size); + cursor = index + header->partitions.offset; + + printf("index: %d\n", index); + printf("cursor: %d\n", cursor); + + // ValidateTableSize ensured that |cursor| is valid for the number of + // entries in the table. + for (i = 0; i < header->partitions.num_entries; i++) { + LpMetadataPartition partition; + memcpy(&partition, superbuf + cursor, sizeof(partition)); + cursor += header->partitions.entry_size; + + printf("partition name : %s\n", partition.name); + + if (partition.attributes & ~LP_PARTITION_ATTRIBUTE_MASK) { + printf("Logical partition has invalid attribute set.\n"); + if (buffer) + free (buffer); + return -1; + } + if (partition.first_extent_index + partition.num_extents < partition.first_extent_index) { + printf("Logical partition first_extent_index + num_extents overflowed.\n"); + if (buffer) + free (buffer); + return -1; + } + if (partition.first_extent_index + partition.num_extents > header->extents.num_entries) { + printf("Logical partition has invalid extent list.\n"); + if (buffer) + free (buffer); + return -1; + } + if (partition.group_index >= header->groups.num_entries) { + printf("Logical partition has invalid group index.\n"); + if (buffer) + free (buffer); + return -1; + } + + node = malloc(sizeof(PartitionList)); + strcpy(node->name, partition.name); + if (ishead == 0) + { + part_list = node ; + part_list->next = NULL ; + tail = node; + ishead = -1; + } + else + { + tail->next = node; + tail = node; + } + //metadata->partitions.push_back(partition); + } + + if (NULL != tail) + tail->next = NULL; + + if (buffer) + free (buffer); + + return 0; +} + +/*void dump_mem(char * buffer, int count) +{ + int i; + printf("***********************************************\n"); + for (i=0; i<count ; i++) + { + if (i % 16 == 0) + printf("\n"); + printf("%02x ", buffer[i]); + } + printf("\n"); + printf("***********************************************\n"); +}*/ + + +int do_ReadMetadata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *partition = "super"; + char* superbuf; + LpMetadataGeometry geometry; + LpMetadataHeader metadata_header; + char *slot; + int slot_number = 0; + superbuf = (char*)malloc(SUPERBUF_SIZE); + if (superbuf == NULL) { + printf("Out of memory reading logical partition tables.\n"); + goto ERR; + } + + if (dynamic_partition) { + if (store_read((unsigned char *)partition, + 0, SUPERBUF_SIZE, (unsigned char *)superbuf) < 0) { + printf("failed to store read %s.\n", partition); + goto ERR; + } + + //dump_mem(superbuf, SUPERBUF_SIZE); + + if (ReadLogicalPartitionGeometry(superbuf, &geometry) != 0) { + goto ERR; + } + + if (has_boot_slot == 1) { + slot = env_get("slot-suffixes"); + printf("slot-suffixes: %s\n", slot); + if (strcmp(slot, "0") == 0) { + slot_number = 0; + } else if (strcmp(slot, "1") == 0) { + slot_number = 1; + } + } + + ReadMetadataHeader(superbuf, &metadata_header, &geometry, slot_number); + + //printlist(); + } + + if (superbuf) + free (superbuf); + + return 0; + +ERR: + if (superbuf) + free (superbuf); + return -1; + +} + +int is_partition_logical(char* parition_name) { + run_command("readMetadata", 0); + PartitionList* node = part_list; + while (NULL != node) + { + printf("name: %s\n",node->name); + if (strcmp(node->name, parition_name) == 0) + return 0; + node = node->next; + } + + return -1; +} + +#else +static int do_ReadMetadata( + cmd_tbl_t * cmdtp, + int flag, + int argc, + char * const argv[]) { + // Do-Nothing! + return 0; +} +#endif /* CONFIG_BOOTLOADER_CONTROL_BLOCK */ + +U_BOOT_CMD( + readMetadata, 1, 0, do_ReadMetadata, + "readMetadata", + "\nThis command will read metadata in super \n" + "So you can execute command: readMetadata" +); +
diff --git a/cmd/amlogic/cmd_factory_provision.c b/cmd/amlogic/cmd_factory_provision.c new file mode 100644 index 0000000..895581c --- /dev/null +++ b/cmd/amlogic/cmd_factory_provision.c
@@ -0,0 +1,961 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <fs.h> +#include <fat.h> +#include <u-boot/sha256.h> +#include <emmc_partitions.h> +#include <stdlib.h> +#include <mapmem.h> +#include <amlogic/storage.h> + +#define CMD_DEBUG (0) +#define CMD_LOG_TAG "[FACTORY-PROVISION] " + +#if CMD_DEBUG +#define LOGD(fmt, ...) printf("%s"fmt, CMD_LOG_TAG, ##__VA_ARGS__) +#else +#define LOGD(fmt, ...) +#endif + +#define LOGE(fmt, ...) printf("%sERROR: "fmt, CMD_LOG_TAG, ##__VA_ARGS__) +#define LOGI(fmt, ...) printf("%s"fmt, CMD_LOG_TAG, ##__VA_ARGS__) + +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +#define FUNCID_PROVISION_SET_IV 0xB200E030 +#define FUNCID_PROVISION_ENCRYPT 0xB200E031 +#define FUNCID_PROVISION_GET_TRANSFER_ADDR 0xB2000007 + +#define SIZE_1K (1024) +#define SIZE_1M (SIZE_1K * SIZE_1K) +#define SIZE_TAG (16) +#define SIZE_IV (16) +#define SIZE_AES_KEY (16) +#define SIZE_HMAC_KEY (32) +#define SIZE_HMAC_DIGEST (32) +#define SIZE_BLOCK (512) + +#define MAX_SIZE_CMD (256) +#define MAX_SIZE_KEYBOX_NAME (256) +#define MAX_SIZE_PART_NAME (32) +#define MAX_SIZE_KEYBOX (SIZE_1K * 16) + +#define MAX_CNT_FS_VALUE (256) + +#define KEYBOX_HDR_MAGIC (0x6B626F78) //"kbox" +#define KEYBOX_HDR_MIN_VERSION (5) + +#define PROVISION_TYPE_FACTORY (0) + +#define ACTION_UNKNOWN (0x00) +#define ACTION_INIT (0x01) +#define ACTION_WRITE (0x02) +#define ACTION_QUERY (0x03) +#define ACTION_REMOVE (0x04) +#define ACTION_CLEAR (0x05) +#define ACTION_LIST (0x06) + +#define DEV_NAME "mmc" +#define DEV_NO (1) +#define PART_TYPE "user" +#define PART_NAME_RSV "rsv" +#define PART_NAME_FTY "factory" + +#define CMD_RET_SUCCESS 0x00000000 +#define CMD_RET_KEYBOX_NOT_EXIST 0x00000001 +#define CMD_RET_KEYBOX_TOO_LARGE 0x00000002 +#define CMD_RET_KEYBOX_NAME_TOO_LONG 0x00000003 +#define CMD_RET_KEYBOX_BAD_FORMAT 0x00000004 +#define CMD_RET_DEVICE_NO_SPACE 0x00000011 +#define CMD_RET_DEVICE_NOT_AVAILABLE 0x00000012 +#define CMD_RET_BAD_PARAMETER 0x00000021 +#define CMD_RET_SMC_CALL_FAILED 0x00000031 +#define CMD_RET_UNKNOWN_ERROR 0x0000FFFF + +struct keybox_header { + uint32_t magic; + uint32_t version; + uint32_t key_type; + uint32_t key_size; + uint32_t provision_type; + uint32_t ta_uuid[4]; + uint32_t reserved[4]; +}; + +struct encryption_context { + char iv[SIZE_IV]; + char tag[SIZE_TAG]; + char epek[SIZE_AES_KEY]; + char rsv[64]; +}; + +struct input_param { + uint32_t action; + const char *keybox_name; + uint32_t keybox_phy_addr; + uint32_t keybox_size; + uint32_t ret_data_addr; +}; + +struct fs_value { + int idx; + uint32_t value; +}; + +static char g_keybox[MAX_SIZE_KEYBOX] = { 0 }; +static char g_fs_data[SIZE_1K] = { 0 }; +static char g_part_name[MAX_SIZE_PART_NAME] = { 0 }; + +static struct fs_value g_fs_vals_rsv[MAX_CNT_FS_VALUE] = { + { 0, 0xEB }, { 1, 0x3C }, { 2, 0x90 }, { 3, 0x6D }, + { 4, 0x6B }, { 5, 0x66 }, { 6, 0x73 }, { 7, 0x2E }, + { 8, 0x66 }, { 9, 0x61 }, { 10, 0x74 }, { 12, 0x02 }, + { 13, 0x10 }, { 14, 0x01 }, { 16, 0x02 }, { 18, 0x02 }, + { 20, 0x80 }, { 21, 0xF8 }, { 22, 0x10 }, { 24, 0x20 }, + { 26, 0x40 }, { 36, 0x80 }, { 38, 0x29 }, { 39, 0x13 }, + { 40, 0x4C }, { 41, 0x98 }, { 42, 0x6A }, { 43, 0x4B }, + { 44, 0x45 }, { 45, 0x59 }, { 46, 0x42 }, { 47, 0x4F }, + { 48, 0x58 }, { 49, 0x20 }, { 50, 0x50 }, { 51, 0x41 }, + { 52, 0x52 }, { 53, 0x54 }, { 54, 0x46 }, { 55, 0x41 }, + { 56, 0x54 }, { 57, 0x31 }, { 58, 0x32 }, { 59, 0x20 }, + { 60, 0x20 }, { 61, 0x20 }, { 62, 0x0E }, { 63, 0x1F }, + { 64, 0xBE }, { 65, 0x5B }, { 66, 0x7C }, { 67, 0xAC }, + { 68, 0x22 }, { 69, 0xC0 }, { 70, 0x74 }, { 71, 0x0B }, + { 72, 0x56 }, { 73, 0xB4 }, { 74, 0x0E }, { 75, 0xBB }, + { 76, 0x07 }, { 78, 0xCD }, { 79, 0x10 }, { 80, 0x5E }, + { 81, 0xEB }, { 82, 0xF0 }, { 83, 0x32 }, { 84, 0xE4 }, + { 85, 0xCD }, { 86, 0x16 }, { 87, 0xCD }, { 88, 0x19 }, + { 89, 0xEB }, { 90, 0xFE }, { 91, 0x54 }, { 92, 0x68 }, + { 93, 0x69 }, { 94, 0x73 }, { 95, 0x20 }, { 96, 0x69 }, + { 97, 0x73 }, { 98, 0x20 }, { 99, 0x6E }, { 100, 0x6F }, + { 101, 0x74 }, { 102, 0x20 }, { 103, 0x61 }, { 104, 0x20 }, + { 105, 0x62 }, { 106, 0x6F }, { 107, 0x6F }, { 108, 0x74 }, + { 109, 0x61 }, { 110, 0x62 }, { 111, 0x6C }, { 112, 0x65 }, + { 113, 0x20 }, { 114, 0x64 }, { 115, 0x69 }, { 116, 0x73 }, + { 117, 0x6B }, { 118, 0x2E }, { 119, 0x20 }, { 120, 0x20 }, + { 121, 0x50 }, { 122, 0x6C }, { 123, 0x65 }, { 124, 0x61 }, + { 125, 0x73 }, { 126, 0x65 }, { 127, 0x20 }, { 128, 0x69 }, + { 129, 0x6E }, { 130, 0x73 }, { 131, 0x65 }, { 132, 0x72 }, + { 133, 0x74 }, { 134, 0x20 }, { 135, 0x61 }, { 136, 0x20 }, + { 137, 0x62 }, { 138, 0x6F }, { 139, 0x6F }, { 140, 0x74 }, + { 141, 0x61 }, { 142, 0x62 }, { 143, 0x6C }, { 144, 0x65 }, + { 145, 0x20 }, { 146, 0x66 }, { 147, 0x6C }, { 148, 0x6F }, + { 149, 0x70 }, { 150, 0x70 }, { 151, 0x79 }, { 152, 0x20 }, + { 153, 0x61 }, { 154, 0x6E }, { 155, 0x64 }, { 156, 0x0D }, + { 157, 0x0A }, { 158, 0x70 }, { 159, 0x72 }, { 160, 0x65 }, + { 161, 0x73 }, { 162, 0x73 }, { 163, 0x20 }, { 164, 0x61 }, + { 165, 0x6E }, { 166, 0x79 }, { 167, 0x20 }, { 168, 0x6B }, + { 169, 0x65 }, { 170, 0x79 }, { 171, 0x20 }, { 172, 0x74 }, + { 173, 0x6F }, { 174, 0x20 }, { 175, 0x74 }, { 176, 0x72 }, + { 177, 0x79 }, { 178, 0x20 }, { 179, 0x61 }, { 180, 0x67 }, + { 181, 0x61 }, { 182, 0x69 }, { 183, 0x6E }, { 184, 0x20 }, + { 185, 0x2E }, { 186, 0x2E }, { 187, 0x2E }, { 188, 0x20 }, + { 189, 0x0D }, { 190, 0x0A }, { 510, 0x55 }, { 511, 0xAA }, + { 512, 0xF8 }, { 513, 0xFF }, { 514, 0xFF }, { 8704, 0xF8 }, + { 8705, 0xFF }, { 8706, 0xFF }, { 16896, 0x4B }, { 16897, 0x45 }, + { 16898, 0x59 }, { 16899, 0x42 }, { 16900, 0x4F }, { 16901, 0x58 }, + { 16902, 0x20 }, { 16903, 0x50 }, { 16904, 0x41 }, { 16905, 0x52 }, + { 16906, 0x54 }, { 16907, 0x08 }, { 16910, 0x1C }, { 16911, 0x78 }, + { 16912, 0x44 }, { 16913, 0x50 }, { 16914, 0x44 }, { 16915, 0x50 }, + { 16918, 0x1C }, { 16919, 0x78 }, { 16920, 0x44 }, { 16921, 0x50 }, + { 0, 0 }, +}; + +static struct fs_value g_fs_vals_fty[MAX_CNT_FS_VALUE] = { + { 0, 0xEB }, { 1, 0x3C }, { 2, 0x90 }, { 3, 0x6D }, + { 4, 0x6B }, { 5, 0x66 }, { 6, 0x73 }, { 7, 0x2E }, + { 8, 0x66 }, { 9, 0x61 }, { 10, 0x74 }, { 12, 0x02 }, + { 13, 0x08 }, { 14, 0x01 }, { 16, 0x02 }, { 18, 0x02 }, + { 20, 0x40 }, { 21, 0xF8 }, { 22, 0x08 }, { 24, 0x20 }, + { 26, 0x40 }, { 36, 0x80 }, { 38, 0x29 }, { 39, 0xDE }, + { 40, 0x62 }, { 41, 0xA6 }, { 42, 0xD0 }, { 43, 0x4B }, + { 44, 0x45 }, { 45, 0x59 }, { 46, 0x42 }, { 47, 0x4F }, + { 48, 0x58 }, { 49, 0x20 }, { 50, 0x50 }, { 51, 0x41 }, + { 52, 0x52 }, { 53, 0x54 }, { 54, 0x46 }, { 55, 0x41 }, + { 56, 0x54 }, { 57, 0x31 }, { 58, 0x32 }, { 59, 0x20 }, + { 60, 0x20 }, { 61, 0x20 }, { 62, 0x0E }, { 63, 0x1F }, + { 64, 0xBE }, { 65, 0x5B }, { 66, 0x7C }, { 67, 0xAC }, + { 68, 0x22 }, { 69, 0xC0 }, { 70, 0x74 }, { 71, 0x0B }, + { 72, 0x56 }, { 73, 0xB4 }, { 74, 0x0E }, { 75, 0xBB }, + { 76, 0x07 }, { 78, 0xCD }, { 79, 0x10 }, { 80, 0x5E }, + { 81, 0xEB }, { 82, 0xF0 }, { 83, 0x32 }, { 84, 0xE4 }, + { 85, 0xCD }, { 86, 0x16 }, { 87, 0xCD }, { 88, 0x19 }, + { 89, 0xEB }, { 90, 0xFE }, { 91, 0x54 }, { 92, 0x68 }, + { 93, 0x69 }, { 94, 0x73 }, { 95, 0x20 }, { 96, 0x69 }, + { 97, 0x73 }, { 98, 0x20 }, { 99, 0x6E }, { 100, 0x6F }, + { 101, 0x74 }, { 102, 0x20 }, { 103, 0x61 }, { 104, 0x20 }, + { 105, 0x62 }, { 106, 0x6F }, { 107, 0x6F }, { 108, 0x74 }, + { 109, 0x61 }, { 110, 0x62 }, { 111, 0x6C }, { 112, 0x65 }, + { 113, 0x20 }, { 114, 0x64 }, { 115, 0x69 }, { 116, 0x73 }, + { 117, 0x6B }, { 118, 0x2E }, { 119, 0x20 }, { 120, 0x20 }, + { 121, 0x50 }, { 122, 0x6C }, { 123, 0x65 }, { 124, 0x61 }, + { 125, 0x73 }, { 126, 0x65 }, { 127, 0x20 }, { 128, 0x69 }, + { 129, 0x6E }, { 130, 0x73 }, { 131, 0x65 }, { 132, 0x72 }, + { 133, 0x74 }, { 134, 0x20 }, { 135, 0x61 }, { 136, 0x20 }, + { 137, 0x62 }, { 138, 0x6F }, { 139, 0x6F }, { 140, 0x74 }, + { 141, 0x61 }, { 142, 0x62 }, { 143, 0x6C }, { 144, 0x65 }, + { 145, 0x20 }, { 146, 0x66 }, { 147, 0x6C }, { 148, 0x6F }, + { 149, 0x70 }, { 150, 0x70 }, { 151, 0x79 }, { 152, 0x20 }, + { 153, 0x61 }, { 154, 0x6E }, { 155, 0x64 }, { 156, 0x0D }, + { 157, 0x0A }, { 158, 0x70 }, { 159, 0x72 }, { 160, 0x65 }, + { 161, 0x73 }, { 162, 0x73 }, { 163, 0x20 }, { 164, 0x61 }, + { 165, 0x6E }, { 166, 0x79 }, { 167, 0x20 }, { 168, 0x6B }, + { 169, 0x65 }, { 170, 0x79 }, { 171, 0x20 }, { 172, 0x74 }, + { 173, 0x6F }, { 174, 0x20 }, { 175, 0x74 }, { 176, 0x72 }, + { 177, 0x79 }, { 178, 0x20 }, { 179, 0x61 }, { 180, 0x67 }, + { 181, 0x61 }, { 182, 0x69 }, { 183, 0x6E }, { 184, 0x20 }, + { 185, 0x2E }, { 186, 0x2E }, { 187, 0x2E }, { 188, 0x20 }, + { 189, 0x0D }, { 190, 0x0A }, { 510, 0x55 }, { 511, 0xAA }, + { 512, 0xF8 }, { 513, 0xFF }, { 514, 0xFF }, { 4608, 0xF8 }, + { 4609, 0xFF }, { 4610, 0xFF }, { 8704, 0x4B }, { 8705, 0x45 }, + { 8706, 0x59 }, { 8707, 0x42 }, { 8708, 0x4F }, { 8709, 0x58 }, + { 8710, 0x20 }, { 8711, 0x50 }, { 8712, 0x41 }, { 8713, 0x52 }, + { 8714, 0x54 }, { 8715, 0x08 }, { 8718, 0x49 }, { 8719, 0xA2 }, + { 8720, 0x4C }, { 8721, 0x50 }, { 8722, 0x4C }, { 8723, 0x50 }, + { 8726, 0x49 }, { 8727, 0xA2 }, { 8728, 0x4C }, { 8729, 0x50 }, + { 0, 0 }, +}; + +static uint32_t get_transfer_phy_addr(uint32_t *transfer_phy_addr) +{ + register uint32_t x0 asm("x0") = FUNCID_PROVISION_GET_TRANSFER_ADDR; + register uint32_t x1 asm("x1") = 0; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x0") + "smc #0\n" + : "=r"(x0), "=r"(x1) + : "r"(x0)); + } while (0); + + if (x0 == 0) + *transfer_phy_addr = x1; + + return x0; +} + +static uint32_t set_iv(uint32_t transfer_addr, uint32_t iv_size) +{ + register uint32_t x0 asm("x0") = FUNCID_PROVISION_SET_IV; + register uint32_t x1 asm("x1") = iv_size; + register uint32_t x2 asm("x2") = transfer_addr; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x0") + __asmeq("%2", "x1") + __asmeq("%3", "x2") + "smc #0\n" + : "=r"(x0) + : "r"(x0), "r"(x1), "r"(x2)); + } while (0); + + return x0; +} + +static uint32_t encrypt(uint32_t transfer_addr, uint32_t *data_size) +{ + register uint32_t x0 asm("x0") = FUNCID_PROVISION_ENCRYPT; + register uint32_t x1 asm("x1") = *data_size; + register uint32_t x2 asm("x2") = transfer_addr; + + do { + asm volatile( + __asmeq("%0", "x0") + __asmeq("%1", "x1") + __asmeq("%2", "x2") + __asmeq("%3", "x0") + __asmeq("%4", "x1") + __asmeq("%5", "x2") + "smc #0\n" + : "=r"(x0), "=r"(x1), "=r"(x2) + : "r"(x0), "r"(x1), "r"(x2)); + } while (0); + + if (x0 == 0) + *data_size = x1; + + return x0; +} + +static void usage(void) +{ + printf("factory_provision -- provision keybox\n\n" + "Usage:\n" + "factory_provision write <keybox_name> <keybox_addr> <keybox_size>\n" + " - write keybox to key partition\n\n" + "factory_provision query <keybox_name> [ret_data_addr]\n" + " - query whether the keybox exists by keybox name\n" + " - when keybox exists, return data: keybox_size(4bytes)\n\n" + "factory_provision remove <keybox_name>\n" + " - remove the keybox by keybox name\n\n"); +} + +static void parse_params(int argc, char * const argv[], + struct input_param *params) +{ + memset(params, 0, sizeof(struct input_param)); + switch (argc) { + case 5: + if (!memcmp(argv[1], "write", strlen("write"))) { + params->action = ACTION_WRITE; + params->keybox_name = argv[2]; + params->keybox_phy_addr = + (uint32_t)simple_strtoul(argv[3], NULL, 0); + params->keybox_size = + (uint32_t)simple_strtoul(argv[4], NULL, 0); + } + break; + case 4: + if (!memcmp(argv[1], "query", strlen("query"))) { + params->action = ACTION_QUERY; + params->keybox_name = argv[2]; + params->ret_data_addr = + (uint32_t)simple_strtoul(argv[3], NULL, 0); + } + break; + case 3: + if (!memcmp(argv[1], "query", strlen("query"))) { + params->action = ACTION_QUERY; + params->keybox_name = argv[2]; + if (getenv("loadaddr") != NULL) + params->ret_data_addr = + (uint32_t)simple_strtoul( + getenv("loadaddr"), NULL, 0); + else + params->ret_data_addr = CONFIG_SYS_LOAD_ADDR; + } else if (!memcmp(argv[1], "remove", strlen("remove"))) { + params->action = ACTION_REMOVE; + params->keybox_name = argv[2]; + } + break; + case 2: + if (!memcmp(argv[1], "init", strlen("init"))) + params->action = ACTION_INIT; + else if (!memcmp(argv[1], "clear", strlen("clear"))) + params->action = ACTION_CLEAR; + else if (!memcmp(argv[1], "list", strlen("list"))) + params->action = ACTION_LIST; + break; + default: + break; + } +} + +static int check_params(const struct input_param *params) +{ + int ret = CMD_RET_SUCCESS; + + switch (params->action) { + case ACTION_INIT: + case ACTION_CLEAR: + case ACTION_LIST: + break; + case ACTION_WRITE: + if (strlen(params->keybox_name) > MAX_SIZE_KEYBOX_NAME) { + LOGE("keybox name is too long, and max length is " + "%d\n", MAX_SIZE_KEYBOX_NAME); + ret = CMD_RET_KEYBOX_NAME_TOO_LONG; + goto exit; + } + if (params->keybox_size > MAX_SIZE_KEYBOX) { + LOGE("keybox size is too large, and max size is %d\n", + MAX_SIZE_KEYBOX); + ret = CMD_RET_KEYBOX_TOO_LARGE; + goto exit; + } + if (!params->keybox_phy_addr) { + LOGE("keybox addr error\n"); + ret = CMD_RET_BAD_PARAMETER; + goto exit; + } + break; + case ACTION_QUERY: + case ACTION_REMOVE: + if (strlen(params->keybox_name) > MAX_SIZE_KEYBOX_NAME) { + LOGE("keybox name is too long, and max length is " + "%d\n", MAX_SIZE_KEYBOX_NAME); + ret = CMD_RET_KEYBOX_NAME_TOO_LONG; + goto exit; + } + break; + default: + ret = CMD_RET_BAD_PARAMETER; + break; + } + +exit: + return ret; +} + +static int preprocess_keybox(char *keybox, uint32_t size) +{ + uint32_t res = 0; + struct encryption_context *enc_cxt = (struct encryption_context *) + (keybox + sizeof(struct keybox_header)); + uint32_t epek_size = sizeof(enc_cxt->epek); + uint32_t transfer_phy_addr = 0; + char *transfer_buf = NULL; + + res = get_transfer_phy_addr(&transfer_phy_addr); + if (res) { + LOGE("get transfer address failed, " + "smc fast call ret = 0x%08X\n", res); + return CMD_RET_SMC_CALL_FAILED; + } + + transfer_buf = map_sysmem(transfer_phy_addr, 0); + + memcpy(transfer_buf, enc_cxt->iv, sizeof(enc_cxt->iv)); + res = set_iv(transfer_phy_addr, sizeof(enc_cxt->iv)); + if (res) { + LOGE("set iv failed, smc fast call ret = 0x%08X\n", res); + return CMD_RET_SMC_CALL_FAILED; + } + + memcpy(transfer_buf, enc_cxt->epek, sizeof(enc_cxt->epek)); + res = encrypt(transfer_phy_addr, &epek_size); + if (res) { + LOGE("encrypt epek failed, smc fast call ret = 0x%08X\n", res); + return CMD_RET_SMC_CALL_FAILED; + } + memcpy(enc_cxt->epek, transfer_buf, epek_size); + + unmap_sysmem(transfer_buf); + + return CMD_RET_SUCCESS; +} + +static const char* get_valid_part_name(void) +{ + int part_num = get_partition_num_by_name(PART_NAME_FTY); + + memset(g_part_name, 0, sizeof(g_part_name)); + if (part_num >= 0) + strcpy(g_part_name, PART_NAME_FTY); + else + strcpy(g_part_name, PART_NAME_RSV); + + return g_part_name; +} + +static const struct fs_value* get_fs_values(void) +{ + int part_num = get_partition_num_by_name(PART_NAME_FTY); + + if (part_num >= 0) + return g_fs_vals_fty; + else + return g_fs_vals_rsv; +} + +static int make_fat_fs(void) +{ + char cmd[MAX_SIZE_CMD] = { 0 }; + int i = 0; + const char *part_name = get_valid_part_name(); + const struct fs_value *fs_vals = get_fs_values(); + uint32_t data_phy_addr = (uint32_t)virt_to_phys(g_fs_data); + uint32_t offset = 0; + + /* erase partition */ + sprintf(cmd, "mmc dev %d;amlmmc switch %d %s;amlmmc erase %s;", + DEV_NO, DEV_NO, PART_TYPE, part_name); + if (run_command(cmd, 0)) { + LOGE("command[%s] failed\n", cmd); + return CMD_RET_UNKNOWN_ERROR; + } + + /* write fat file system */ + memset(g_fs_data, 0, SIZE_1K); + for (i = 0; i < MAX_CNT_FS_VALUE && fs_vals[i].value; i++) { + if ((i > 0) && (fs_vals[i].idx / SIZE_1K != + fs_vals[i - 1].idx / SIZE_1K)) { + memset(cmd, 0, sizeof(cmd)); + offset = fs_vals[i - 1].idx / SIZE_1K * SIZE_1K; + sprintf(cmd, "amlmmc write %s 0x%08X 0x%X 0x%X;", + part_name, data_phy_addr, offset, SIZE_1K); + if (run_command(cmd, 0)) { + LOGE("command[%s] failed\n", cmd); + return CMD_RET_UNKNOWN_ERROR; + } + } + g_fs_data[fs_vals[i].idx % SIZE_1K] = fs_vals[i].value; + } + memset(cmd, 0, sizeof(cmd)); + offset = fs_vals[i - 1].idx / SIZE_1K * SIZE_1K; + sprintf(cmd, "amlmmc write %s 0x%08X 0x%X 0x%X;", + part_name, data_phy_addr, offset, SIZE_1K); + if (run_command(cmd, 0)) { + LOGE("command[%s] failed\n", cmd); + return CMD_RET_UNKNOWN_ERROR; + } + + return CMD_RET_SUCCESS; +} + +static int dev_writable(void) +{ + char cmd[MAX_SIZE_CMD] = { 0 }; + + sprintf(cmd, "fatinfo %s 0x%X:0x%X", DEV_NAME, DEV_NO, + get_partition_num_by_name((char *)get_valid_part_name())); + if (run_command(cmd, 0)) { + LOGD("command[%s] failed\n", cmd); + return CMD_RET_DEVICE_NOT_AVAILABLE; + } + + return CMD_RET_SUCCESS; +} + +static int dev_write(const char *name, const char *data, uint32_t size) +{ + char cmd[MAX_SIZE_CMD] = { 0 }; + + sprintf(cmd, "fatwrite %s 0x%X:0x%X 0x%08X %s 0x%X", DEV_NAME, DEV_NO, + get_partition_num_by_name((char *)get_valid_part_name()), + (uint32_t)virt_to_phys((void *)data), name, size); + if (run_command(cmd, 0)) { + LOGD("command[%s] failed\n", cmd); + return CMD_RET_DEVICE_NOT_AVAILABLE; + } + + return CMD_RET_SUCCESS; +} + +static int init_partition(void) +{ + int ret = CMD_RET_SUCCESS; + char dev_part_str[16] = { 0 }; + + ret = dev_writable(); + if (ret) { + ret = make_fat_fs(); + if (ret) { + LOGE("make fat file system failed\n"); + return ret; + } + ret = dev_writable(); + if (ret) { + LOGE("device not available\n"); + return ret; + } + } + + sprintf(dev_part_str, "0x%X:0x%X", DEV_NO, + get_partition_num_by_name((char *)get_valid_part_name())); + if (fs_set_blk_dev(DEV_NAME, dev_part_str, FS_TYPE_FAT)) { + LOGE("set block device failed\n"); + ret = CMD_RET_UNKNOWN_ERROR; + } + + return ret; +} + +void convert_to_uuid_str(const char uuid[16], char uuid_str[40]) +{ + int i = 0; + const char *uuid_ptr = uuid; + char *str_ptr = uuid_str; + + for (i = 0; i < 4; i++) { + sprintf(str_ptr, "%02x", *uuid_ptr); + str_ptr += 2; + uuid_ptr++; + } + *str_ptr++ = '-'; + for (i = 0; i < 2; i++) { + sprintf(str_ptr, "%02x", *uuid_ptr); + str_ptr += 2; + uuid_ptr++; + } + *str_ptr++ = '-'; + for (i = 0; i < 2; i++) { + sprintf(str_ptr, "%02x", *uuid_ptr); + str_ptr += 2; + uuid_ptr++; + } + *str_ptr++ = '-'; + for (i = 0; i < 8; i++) { + sprintf(str_ptr, "%02x", *uuid_ptr); + str_ptr += 2; + uuid_ptr++; + } +} + +static int check_keybox(const char *keybox, uint32_t size) +{ + const struct keybox_header *hdr = (const struct keybox_header *)keybox; + uint32_t hdr_cxt_size = sizeof(struct keybox_header) + + sizeof(struct encryption_context); + + if (hdr->magic != KEYBOX_HDR_MAGIC) { + LOGE("keybox header magic error" + "(expected magic: 0x%08X; wrong magic: 0x%08X)\n", + KEYBOX_HDR_MAGIC, hdr->magic); + return CMD_RET_KEYBOX_BAD_FORMAT; + } + if (hdr->version < KEYBOX_HDR_MIN_VERSION) { + LOGE("keybox header version error" + "(min version: %d; wrong version: %d)\n", + KEYBOX_HDR_MIN_VERSION, hdr->version); + return CMD_RET_KEYBOX_BAD_FORMAT; + } + if (size > MAX_SIZE_KEYBOX || size <= hdr_cxt_size + || hdr->key_size != size - hdr_cxt_size) { + LOGE("keybox length error\n"); + return CMD_RET_KEYBOX_BAD_FORMAT; + } + if (hdr->provision_type != PROVISION_TYPE_FACTORY) { + LOGE("keybox provision type error" + "(expected type: %d; wrong type: %d)\n", + PROVISION_TYPE_FACTORY, hdr->provision_type); + return CMD_RET_KEYBOX_BAD_FORMAT; + } + + return CMD_RET_SUCCESS; +} + +static void calc_sha256(const char *data, uint32_t data_size, char *sha256) +{ + sha256_context sha256_cxt; + + sha256_starts(&sha256_cxt); + sha256_update(&sha256_cxt, (const uint8_t *)data, (uint32_t)data_size); + sha256_finish(&sha256_cxt, (uint8_t *)sha256); +} + +static int verify_written_keybox(const char *keybox_name, const char *keybox, + uint32_t keybox_size) +{ + char sha256[SHA256_SUM_LEN] = { 0 }; + char written_sha256[SHA256_SUM_LEN] = { 0 }; + loff_t act_read = 0; + + calc_sha256(keybox, keybox_size, sha256); + + memset(g_keybox, 0, sizeof(g_keybox)); + if (fat_read_file(keybox_name, g_keybox, 0, MAX_SIZE_KEYBOX, &act_read)) + return CMD_RET_UNKNOWN_ERROR; + if (keybox_size != act_read) + return CMD_RET_UNKNOWN_ERROR; + + calc_sha256(g_keybox, act_read, written_sha256); + + if (memcmp(sha256, written_sha256, SHA256_SUM_LEN)) + return CMD_RET_UNKNOWN_ERROR; + + return CMD_RET_SUCCESS; +} + +static int append_keybox(const char *keybox_name, const char *keybox, + uint32_t keybox_size) +{ + int ret = CMD_RET_SUCCESS; + + ret = init_partition(); + if (ret) + return ret; + + ret = dev_write(keybox_name, keybox, keybox_size); + if (ret) + return ret; + + ret = verify_written_keybox(keybox_name, keybox, keybox_size); + if (ret) { + LOGE("verify written keybox '%s' failed\n", keybox_name); + return ret; + } + + LOGI("write keybox '%s' success\n", keybox_name); + + return ret; +} + +static int get_keybox_size(const char *keybox_name, uint32_t *size) +{ + loff_t keybox_size = 0; + + if (fat_size(keybox_name, &keybox_size)) { + LOGE("get keybox '%s' size failed\n", keybox_name); + return CMD_RET_UNKNOWN_ERROR; + } else { + *size = (uint32_t)keybox_size; + LOGI("keybox '%s' size is %d\n", keybox_name, *size); + return CMD_RET_SUCCESS; + } +} + +static int query_keybox(const char *keybox_name, char *ret_data) +{ + int ret = CMD_RET_SUCCESS; + + ret = init_partition(); + if (ret) + return ret; + + if (!fat_exists(keybox_name)) { + LOGI("keybox '%s' not exists\n", keybox_name); + return CMD_RET_KEYBOX_NOT_EXIST; + } + else { + return get_keybox_size(keybox_name, (uint32_t *)ret_data); + } +} + +static int remove_keybox(const char *keybox_name) +{ + int ret = init_partition(); + + if (ret) + return ret; + + if (fs_unlink(keybox_name)) { + LOGE("remove '%s' failed\n", keybox_name); + return CMD_RET_UNKNOWN_ERROR; + } + + LOGI("remove '%s' success\n", keybox_name); + return CMD_RET_SUCCESS; +} + +static int remove_all_keyboxes(void) +{ + int ret = CMD_RET_SUCCESS; + struct fs_dir_stream *dirs = NULL; + struct fs_dirent *dent = NULL; + char cmd[MAX_SIZE_CMD] = { 0 }; + + ret = init_partition(); + if (ret) + return ret; + + if (fat_opendir("/", &dirs)) { + LOGE("open '/' failed\n"); + return CMD_RET_UNKNOWN_ERROR; + } + + while (!fat_readdir(dirs, &dent)) { + if (dent->type != FS_DT_REG) // not regular file + continue; + + sprintf(cmd, "fatrm %s 0x%X:0x%X %s", DEV_NAME, DEV_NO, + get_partition_num_by_name( + (char *)get_valid_part_name()), + dent->name); + if (run_command(cmd, 0)) { + ret = CMD_RET_UNKNOWN_ERROR; + LOGE("remove '%s' failed\n", dent->name); + } else { + LOGI("remove '%s' success\n", dent->name); + } + } + + fat_closedir(dirs); + return ret; +} + +static int list_all_keyboxes(void) +{ + int ret = CMD_RET_SUCCESS; + char cmd[MAX_SIZE_CMD] = { 0 }; + + ret = init_partition(); + if (ret) + return ret; + + sprintf(cmd, "fatls %s 0x%X:0x%X", DEV_NAME, DEV_NO, + get_partition_num_by_name((char *)get_valid_part_name())); + if (run_command(cmd, 0)) { + LOGE("command[%s] failed\n", cmd); + ret = CMD_RET_UNKNOWN_ERROR; + } + + return ret; +} + +static int remove_same_type_keybox(uint32_t key_type, const char *uuid) +{ + int ret = CMD_RET_SUCCESS; + struct fs_dir_stream *dirs = NULL; + struct fs_dirent *dent = NULL; + struct keybox_header hdr; + loff_t act_read = 0; + char uuid_str[40] = { 0 }; + + ret = init_partition(); + if (ret) + return ret; + + if (fat_opendir("/", &dirs)) { + LOGE("open '/' failed\n"); + return CMD_RET_UNKNOWN_ERROR; + } + + convert_to_uuid_str(uuid, uuid_str); + while (!fat_readdir(dirs, &dent)) { + if (dent->type != FS_DT_REG) // not regular file + continue; + + memset(&hdr, 0, sizeof(hdr)); + if (fat_read_file(dent->name, &hdr, 0, sizeof(hdr), &act_read) + || act_read != sizeof(hdr)) { + LOGE("read keybox '%s' failed\n", dent->name); + ret = CMD_RET_UNKNOWN_ERROR; + goto exit; + } + + if (!memcmp(uuid, hdr.ta_uuid, sizeof(hdr.ta_uuid)) && + key_type == hdr.key_type) { + ret = remove_keybox(dent->name); + if (ret != CMD_RET_SUCCESS) { + LOGE("remove the same type" + "(uuid = %s, key_type = 0x%02X) " + "keybox '%s' failed\n", + uuid_str, key_type, dent->name); + goto exit; + } + } + } + +exit: + fat_closedir(dirs); + return ret; +} + +int is_storage_medium_supported(void) +{ + int ret = CMD_RET_SUCCESS; + int medium_type = store_get_type(); + char type_str[64] = { 0 }; + + if (medium_type != BOOT_EMMC) { + switch (medium_type) { + case BOOT_SD: + strcpy(type_str, "SD"); + break; + case BOOT_NAND_NFTL: + strcpy(type_str, "NAND_NFTL"); + break; + case BOOT_NAND_MTD: + strcpy(type_str, "NAND_MTD"); + break; + case BOOT_SNAND: + strcpy(type_str, "SNAND"); + break; + case BOOT_SNOR: + strcpy(type_str, "SNOR"); + break; + default: + strcpy(type_str, "Unknown Storage Medium"); + break; + } + + LOGE("Provision function is not supported on '%s' storage medium", type_str); + ret = CMD_RET_DEVICE_NOT_AVAILABLE; + } + + return ret; +} + +int cmd_func(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret = CMD_RET_SUCCESS; + struct input_param params; + char *in_kb = NULL; + char *ret_data = NULL; + const struct keybox_header *hdr = NULL; + + ret = is_storage_medium_supported(); + if (ret != CMD_RET_SUCCESS) + goto exit; + + parse_params(argc, argv, ¶ms); + + ret = check_params(¶ms); + if (ret != CMD_RET_SUCCESS) + goto exit; + + switch (params.action) { + case ACTION_INIT: + ret = init_partition(); + break; + case ACTION_WRITE: + in_kb = map_sysmem(params.keybox_phy_addr, 0); + + ret = check_keybox(in_kb, params.keybox_size); + if (ret != CMD_RET_SUCCESS) + goto exit; + + hdr = (const struct keybox_header *)in_kb; + ret = remove_same_type_keybox(hdr->key_type, + (const char *)hdr->ta_uuid); + if (ret != CMD_RET_SUCCESS) + goto exit; + + memcpy(g_keybox, in_kb, params.keybox_size); + + ret = preprocess_keybox(g_keybox, params.keybox_size); + if (ret != CMD_RET_SUCCESS) + goto exit; + + ret = append_keybox(params.keybox_name, g_keybox, + params.keybox_size); + if (ret != CMD_RET_SUCCESS) + goto exit; + break; + case ACTION_QUERY: + ret_data = map_sysmem(params.ret_data_addr, 0); + ret = query_keybox(params.keybox_name, ret_data); + if (ret != CMD_RET_SUCCESS) + goto exit; + break; + case ACTION_REMOVE: + ret = remove_keybox(params.keybox_name); + if (ret != CMD_RET_SUCCESS) + goto exit; + break; + case ACTION_CLEAR: + ret = remove_all_keyboxes(); + if (ret != CMD_RET_SUCCESS) + goto exit; + break; + case ACTION_LIST: + ret = list_all_keyboxes(); + if (ret != CMD_RET_SUCCESS) + goto exit; + break; + default: + break; + } + +exit: + if (in_kb) + unmap_sysmem(in_kb); + if (ret_data) + unmap_sysmem(ret_data); + if (ret == CMD_RET_BAD_PARAMETER) + usage(); + return ret; +} + +/* -------------------------------------------------------------------- */ +U_BOOT_CMD( + factory_provision, CONFIG_SYS_MAXARGS, 0, cmd_func, + "provision keybox\n", + "write <keybox_name> <keybox_addr> <keybox_size>\n" + " - write keybox to key partition\n\n" + "query <keybox_name> [ret_data_addr]\n" + " - query whether the keybox exists by keybox name\n" + " - when keybox exists, return data: keybox_size(4bytes)\n\n" + "remove <keybox_name>\n" + " - remove the keybox by keybox name\n" +);
diff --git a/cmd/amlogic/cmd_get_chiptype.c b/cmd/amlogic/cmd_get_chiptype.c index dce9117..b2d067c 100644 --- a/cmd/amlogic/cmd_get_chiptype.c +++ b/cmd/amlogic/cmd_get_chiptype.c
@@ -23,11 +23,11 @@ #include <command.h> #include <asm/arch/bl31_apis.h> #include <amlogic/cpu_id.h> -#include <asm/arch/register.h> int do_get_chiptype(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char *type[] = {"SS", "SF", "TT", "FF"}; + /* 0(unknow) - no vmin info */ + char *type[] = {"dvfs_table0", "dvfs_table1", "dvfs_table2", "dvfs_table3"}; unsigned int dvfs_id = aml_get_dvfs_id(); pr_info("get dvfs_id:%d\n", dvfs_id); if (dvfs_id > 3) { @@ -40,32 +40,21 @@ U_BOOT_CMD( get_chiptype, 1, 0, do_get_chiptype, - "get c328x chip type and env_set 'chip_type'\n", + "get c325x chip type and env_set 'chip_type'\n", "get_chiptype" ); int do_get_cpu_rev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cpu_id_t cpu_id = get_cpu_id(); - char rev[4] = { 0 }; - unsigned int reg_val = 0; + char rev[3] = { 0 }; - if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) { + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C2) { snprintf(rev, sizeof(rev), "%x", cpu_id.chip_rev); } else { snprintf(rev, sizeof(rev), "%d", -1); } - reg_val = readl(SYSCTRL_STICKY_REG5); - strcat(rev, "-"); - if (reg_val == 1) { - /* ACRK key */ - strcat(rev, "r"); - } else { - /* DVUK key */ - strcat(rev, "u"); - } - env_set("cpu_rev", rev); return 0;
diff --git a/cmd/amlogic/cmd_hdmitx.c b/cmd/amlogic/cmd_hdmitx.c index bb9e4fc..fc6e846 100644 --- a/cmd/amlogic/cmd_hdmitx.c +++ b/cmd/amlogic/cmd_hdmitx.c
@@ -8,40 +8,122 @@ #include <environment.h> #include <malloc.h> #include <asm/byteorder.h> -#include <amlogic/media/vout/hdmitx.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> +#include <amlogic/media/dv/dolby_vision.h> #ifdef CONFIG_AML_LCD #include <amlogic/media/vout/lcd/aml_lcd.h> #endif +#ifdef CONFIG_AML_LCD +static unsigned int hdmitx_parse_vout_name(char *name) +{ + char *p, *frac_str; + unsigned int frac = 0; + + p = strchr(name, ','); + if (!p) { + frac = 0; + } else { + frac_str = p + 1; + *p = '\0'; + if (strcmp(frac_str, "frac") == 0) + frac = 1; + } + + return frac; +} +#endif + static int do_hpd_detect(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { + struct hdmitx_dev *hdev = hdmitx_get_hdev(); #ifdef CONFIG_AML_LCD struct aml_lcd_drv_s *lcd_drv = NULL; char *mode; + unsigned int frac; #endif - int st; + char* st; + char* hdmimode; + char* cvbsmode; + char* colorattribute; + int hpd_st = 0; + + st = env_get("hdmitx_hpd_bypass"); + if (st && (strcmp(st[0], "1") == 0)) { + printf("hdmitx_hpd_bypass detect\n"); + return 0; + } #ifdef CONFIG_AML_LCD lcd_drv = aml_lcd_get_driver(); if (lcd_drv) { if (lcd_drv->lcd_outputmode_check) { - mode = env_get("outputmode"); - if (lcd_drv->lcd_outputmode_check(mode) == 0) - return 0; + mode = (char *)malloc(64 * sizeof(char)); + if (!mode) { + printf("cmd_hpd: mode malloc falied\n"); + if (lcd_drv->lcd_outputmode_check(mode, 0) == 0) + return 0; + } else { + memset(mode, 0, sizeof(mode)); + sprintf(mode, "%s", getenv("outputmode")); + frac = hdmitx_parse_vout_name(mode); + if (lcd_drv->lcd_outputmode_check(mode, frac) == 0) { + free(mode); + return 0; + } + free(mode); + } } } #endif - st = hdmitx_device.HWOp.get_hpd_state(); - printf("hpd_state=%c\n", st ? '1' : '0'); + hpd_st = hdev->hwop.get_hpd_state(); + if (!hpd_st) { + /* For some TV, they cost extra time to pullup HPD after 5V */ + int loop = 10; - if (st) { - env_set("outputmode", env_get("hdmimode")); - } else { - env_set("outputmode", env_get("cvbsmode")); + while (loop--) { + mdelay(100); + hpd_st = hdev->hwop.get_hpd_state(); + if (hpd_st) { + printf("hpd delay %d ms\n", (10 - loop) * 100); + break; + } + } } - return st; + printf("hpd_state=%d\n", hpd_st); + + /*get hdmi mode and colorattribute from env */ + hdmimode = env_get("hdmimode"); + if (hdmimode) + printf("do_hpd_detect: hdmimode=%s\n", hdmimode); + + + colorattribute = env_get("colorattribute"); + if (colorattribute) + printf("do_hpd_detect: colorattribute=%s\n", colorattribute); + + if (hdmimode) { + if (strstr(hdmimode, "null")) { + env_set("hdmimode", "1080p60hz"); + //run_command("saveenv", 0); + } + } else { + env_set("hdmimode", "1080p60hz"); + //run_command("saveenv", 0); + } + hdmimode = env_get("hdmimode"); + if (hpd_st) { + env_set("outputmode", hdmimode); + } else { + cvbsmode = env_get("cvbsmode"); + if (cvbsmode) + env_set("outputmode", cvbsmode); + env_set("hdmichecksum", "0x00000000"); + //run_command("saveenv", 0); + } + return hpd_st; } static unsigned char edid_raw_buf[256] = {0}; @@ -73,6 +155,7 @@ unsigned int tmp_addr = 0; unsigned char edid_addr = 0; unsigned char st = 0; + struct hdmitx_dev *hdev = hdmitx_get_hdev(); memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf)); if (argc < 2) @@ -84,7 +167,7 @@ edid_addr = tmp_addr; /* read edid raw data */ /* current only support read 1 byte edid data */ - st = hdmitx_device.HWOp.read_edid( + st = hdev->hwop.read_edid( &edid_raw_buf[edid_addr & 0xf8], edid_addr & 0xf8, 8); printf("edid[0x%02x]: 0x%02x\n", edid_addr, edid_raw_buf[edid_addr]); @@ -100,12 +183,13 @@ { unsigned char edid_addr = 0xf8; // Fixed Address unsigned char st = 0; + struct hdmitx_dev *hdev = hdmitx_get_hdev(); memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf)); // read edid raw data // current only support read 1 byte edid data - st = hdmitx_device.HWOp.read_edid(&edid_raw_buf[edid_addr & 0xf8], edid_addr & 0xf8, 8); + st = hdev->hwop.read_edid(&edid_raw_buf[edid_addr & 0xf8], edid_addr & 0xf8, 8); if (1) // Debug only dump_edid_raw_8bytes(&edid_raw_buf[edid_addr & 0xf8]); if (st) { @@ -183,11 +267,12 @@ static int do_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { + struct hdmitx_dev *hdev = hdmitx_get_hdev(); if (argc < 1) return cmd_usage(cmdtp); if (strcmp(argv[1], "list") == 0) - hdmitx_device.HWOp.list_support_modes(); + hdev->hwop.list_support_modes(); else if (strcmp(argv[1], "bist") == 0) { unsigned int mode = 0; if (strcmp(argv[2], "off") == 0) @@ -198,31 +283,48 @@ mode = 3; else mode = simple_strtoul(argv[2], NULL, 10); - hdmitx_device.HWOp.test_bist(mode); + hdev->hwop.test_bist(mode); } else if (strcmp(argv[1], "prbs") == 0) { - hdmitx_device.para->cs = HDMI_COLOR_FORMAT_RGB; - hdmitx_device.para->cd = HDMI_COLOR_DEPTH_24B; - hdmitx_device.vic = HDMI_1920x1080p60_16x9; - hdmi_tx_set(&hdmitx_device); - hdmitx_device.HWOp.test_bist(10); - } else if (strcmp(argv[1], "div40") == 0) { - hdmitx_device.HWOp.test_bist(11); + hdev->para->cs = HDMI_COLOR_FORMAT_RGB; + hdev->para->cd = HDMI_COLOR_DEPTH_24B; + hdev->vic = HDMI_1920x1080p60_16x9; + hdmi_tx_set(hdev); + hdev->hwop.test_prbs(); + } else if (strncmp(argv[1], "div40", 5) == 0) { + bool div40 = 0; + + if (argv[1][5] == '1') + div40 = 1; + hdev->hwop.set_div40(div40); } else { /* "output" */ - hdmitx_device.vic = hdmi_get_fmt_vic(argv[1]); - hdmitx_device.para = hdmi_get_fmt_paras(hdmitx_device.vic); - if (hdmitx_device.vic == HDMI_unkown) { + if (!edid_parsing_ok(hdev)) { + /* SWPL-34712: if EDID parsing error case, not save env, + * only forcely output default mode(480p,RGB,8bit). + */ + printf("edid parsing ng, forcely output 480p, rgb,8bit\n"); + hdev->vic = HDMI_720x480p60_16x9; + hdev->para = + hdmi_get_fmt_paras(hdev->vic); + hdev->para->cs = HDMI_COLOR_FORMAT_RGB; + hdev->para->cd = HDMI_COLOR_DEPTH_24B; + hdmi_tx_set(hdev); + return CMD_RET_SUCCESS; + } + hdev->vic = hdmi_get_fmt_vic(argv[1]); + hdev->para = hdmi_get_fmt_paras(hdev->vic); + if (hdev->vic == HDMI_unkown) { /* Not find VIC */ printf("Not find '%s' mapped VIC\n", argv[1]); return CMD_RET_FAILURE; } else - printf("set hdmitx VIC = %d\n", hdmitx_device.vic); - if (strstr(argv[1], "hz420") != NULL) - hdmitx_device.para->cs = HDMI_COLOR_FORMAT_420; + printf("set hdmitx VIC = %d\n", hdev->vic); if (env_get("colorattribute")) - hdmi_parse_attr(hdmitx_device.para, env_get("colorattribute")); + hdmi_parse_attr(hdev->para, env_get("colorattribute")); + if (strstr(argv[1], "hz420") != NULL) + hdev->para->cs = HDMI_COLOR_FORMAT_420; /* For RGB444 or YCbCr444 under 6Gbps mode, no deepcolor */ /* Only 4k50/60 has 420 modes */ - switch (hdmitx_device.vic) { + switch (hdev->vic) { case HDMI_3840x2160p50_16x9: case HDMI_3840x2160p60_16x9: case HDMI_4096x2160p50_256x135: @@ -235,61 +337,71 @@ case HDMI_4096x2160p60_256x135_Y420: case HDMI_3840x2160p50_64x27_Y420: case HDMI_3840x2160p60_64x27_Y420: - if ((hdmitx_device.para->cs == HDMI_COLOR_FORMAT_RGB) || - (hdmitx_device.para->cs == HDMI_COLOR_FORMAT_444)) { - if (hdmitx_device.para->cd != HDMI_COLOR_DEPTH_24B) { + if ((hdev->para->cs == HDMI_COLOR_FORMAT_RGB) || + (hdev->para->cs == HDMI_COLOR_FORMAT_444)) { + if (hdev->para->cd != HDMI_COLOR_DEPTH_24B) { printf("vic %d cs %d has no cd %d\n", - hdmitx_device.vic, - hdmitx_device.para->cs, - hdmitx_device.para->cd); - hdmitx_device.para->cd = HDMI_COLOR_DEPTH_24B; + hdev->vic, + hdev->para->cs, + hdev->para->cd); + hdev->para->cd = HDMI_COLOR_DEPTH_24B; printf("set cd as %d\n", HDMI_COLOR_DEPTH_24B); } } - if (hdmitx_device.para->cs == HDMI_COLOR_FORMAT_420) - hdmitx_device.vic |= HDMITX_VIC420_OFFSET; + if (hdev->para->cs == HDMI_COLOR_FORMAT_420) + hdev->vic |= HDMITX_VIC420_OFFSET; break; default: - if (hdmitx_device.para->cs == HDMI_COLOR_FORMAT_420) { - printf("vic %d has no cs %d\n", hdmitx_device.vic, - hdmitx_device.para->cs); - hdmitx_device.para->cs = HDMI_COLOR_FORMAT_444; + if (hdev->para->cs == HDMI_COLOR_FORMAT_420) { + printf("vic %d has no cs %d\n", hdev->vic, + hdev->para->cs); + hdev->para->cs = HDMI_COLOR_FORMAT_444; printf("set cs as %d\n", HDMI_COLOR_FORMAT_444); } + /* For VESA modes, should be RGB format */ + if (hdev->vic >= HDMITX_VESA_OFFSET) { + hdev->para->cs = HDMI_COLOR_FORMAT_RGB; + hdev->para->cd = HDMI_COLOR_DEPTH_24B; + } break; - /* For VESA modes, should be RGB format */ - if (hdmitx_device.vic >= HDMITX_VESA_OFFSET) - hdmitx_device.para->cs = HDMI_COLOR_FORMAT_RGB; } - hdmi_tx_set(&hdmitx_device); + printf("set hdmitx VIC = %d CS = %d CD = %d\n", + hdev->vic, hdev->para->cs, hdev->para->cd); + hdmi_tx_set(hdev); } return CMD_RET_SUCCESS; } static int do_blank(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + if (argc < 1) return cmd_usage(cmdtp); if (strcmp(argv[1], "1") == 0) - hdmitx_device.HWOp.output_blank(1); + hdev->hwop.output_blank(1); if (strcmp(argv[1], "0") == 0) - hdmitx_device.HWOp.output_blank(0); + hdev->hwop.output_blank(0); return CMD_RET_SUCCESS; } static int do_off(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - hdmitx_device.vic = HDMI_unkown; - hdmitx_device.HWOp.turn_off(); + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + + hdev->vic = HDMI_unkown; + hdev->hwop.turn_off(); printf("turn off hdmitx\n"); return 1; } static int do_dump(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - hdmitx_device.HWOp.dump_regs(); + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + + hdev->hwop.dump_regs(); return 1; } @@ -319,7 +431,7 @@ static int do_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - struct hdmitx_dev *hdev = &hdmitx_device; + struct hdmitx_dev *hdev = hdmitx_get_hdev(); struct hdmi_format_para *para = hdev->para; printf("%s %d\n", para->ext_name, hdev->vic); @@ -328,24 +440,33 @@ return 1; } -static int do_get_preferred_mode(cmd_tbl_t * cmdtp, int flag, int argc, - char * const argv[]) +static int xtochar(int num, char* checksum) { - struct hdmitx_dev *hdev = &hdmitx_device; - unsigned int byte_num = 0; + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + + if (((hdev->rawedid[num] >> 4 ) & 0xf) <= 9) + checksum[0] = ((hdev->rawedid[num] >> 4 ) & 0xf) + '0'; + else + checksum[0] = ((hdev->rawedid[num] >> 4 ) & 0xf) -10 + 'a'; + + if ((hdev->rawedid[num] & 0xf) <= 9) + checksum[1] = (hdev->rawedid[num] & 0xf) + '0'; + else + checksum[1] = (hdev->rawedid[num] & 0xf) -10 + 'a'; + + return 0; +} + +static void get_parse_edid_data(struct hdmitx_dev *hdev) +{ unsigned char *edid = hdev->rawedid; + unsigned int byte_num = 0; unsigned char blk_no = 1; - struct hdmi_format_para *para; - char pref_mode[64]; - char color_attr[64]; + char *hdr_priority = env_get("hdr_priority"); - memset(edid, 0, EDID_BLK_SIZE * EDID_BLK_NO); - memset(pref_mode, 0, sizeof(pref_mode)); - memset(color_attr, 0, sizeof(color_attr)); - - /* Read complete EDID data sequentially */ + /* get edid data */ while (byte_num < 128 * blk_no) { - hdmitx_device.HWOp.read_edid(&edid[byte_num], byte_num & 0x7f, byte_num / 128); + hdev->hwop.read_edid(&edid[byte_num], byte_num & 0x7f, byte_num / 128); if (byte_num == 120) { blk_no = edid[126] + 1; if (blk_no > 4) @@ -354,30 +475,222 @@ byte_num += 8; } - if (hdmi_edid_parsing(hdev->rawedid, &hdev->RXCap) == 0) { + if (0) dump_full_edid(hdev->rawedid); + + /* parse edid data */ + hdmi_edid_parsing(hdev->rawedid, &hdev->RXCap); + + /* if hdr_priority is 1, then mark dv_info */ + if (hdr_priority && (strcmp(hdr_priority, "1") == 0)) { + memset(&hdev->RXCap.dv_info, 0, sizeof(struct dv_info)); + pr_info("hdr_priority: %s and clear dv_info\n", hdr_priority); } +} + +/* policy process: to find the output mode/attr/dv_type */ +void scene_process(struct hdmitx_dev *hdev, + scene_output_info_t *scene_output_info) +{ + hdmi_data_t hdmidata; + + if (!hdev || !scene_output_info) + return; + /* 1.read dolby vision mode from prop(maybe need to env) */ + memset(&hdmidata, 0, sizeof(hdmi_data_t)); + get_hdmi_data(hdev, &hdmidata); + + /* 2. dolby vision scene process */ + /* only for tv support dv and box enable dv */ + if (is_dolby_enabled() && is_tv_support_dv(hdev)) { + dolbyvision_scene_process(&hdmidata, scene_output_info); + } else if (is_dolby_enabled()) { + /* for enable dolby vision core when + * first boot connecting non dv tv + * NOTE: let systemcontrol to enable DV core + */ + /* scene_output_info->final_dv_type = DOLBY_VISION_ENABLE; */ + } else { + /* for UI disable dolby vision core and boot keep the status + * NOTE: TBD if need to disable DV here + */ + /* scene_output_info->final_dv_type = DOLBY_VISION_DISABLE; */ + } + /* 3.sdr scene process */ + /* decide final display mode and deepcolor */ + if (is_dolby_enabled() && is_tv_support_dv(hdev)) { + /* do nothing */ + } else { + sdr_scene_process(&hdmidata, scene_output_info); + } +} + +static int do_get_parse_edid(cmd_tbl_t * cmdtp, int flag, int argc, + char * const argv[]) +{ + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + unsigned char *edid = hdev->rawedid; + unsigned char *store_checkvalue; + memset(edid, 0, EDID_BLK_SIZE * EDID_BLK_NO); + unsigned int i; + unsigned int checkvalue[4]; + unsigned int checkvalue1; + unsigned int checkvalue2; + char checksum[11]; + char* hdmimode; + char* colorattribute; + char dv_type[2] = {0}; + scene_output_info_t scene_output_info; + + if (!hdev->hwop.get_hpd_state()) { + printf("HDMI HPD low, no need parse EDID\n"); + return 1; + } + memset(&scene_output_info, 0, sizeof(scene_output_info_t)); + + get_parse_edid_data(hdev); + + /* check if the tv has changed or anything wrong */ + store_checkvalue = (unsigned char*)env_get("hdmichecksum"); + colorattribute = env_get("colorattribute"); + hdmimode = env_get("hdmimode"); + + printf("read hdmichecksum: %s, hdmimode: %s, colorattribute: %s\n", + store_checkvalue, hdmimode, colorattribute); + + for (i = 0; i < 4; i++) { + if (('0' <= store_checkvalue[i * 2 + 2]) && (store_checkvalue[i * 2 + 2] <= '9')) + checkvalue1 = store_checkvalue[i * 2 + 2] -'0'; + else + checkvalue1 = store_checkvalue[i * 2 + 2] -'W'; + if (('0' <= store_checkvalue[i * 2 + 3]) && (store_checkvalue[i * 2 + 3] <= '9')) + checkvalue2 = store_checkvalue[i * 2 + 3] -'0'; + else + checkvalue2 = store_checkvalue[i * 2 + 3] -'W'; + checkvalue[i] = checkvalue1 * 16 + checkvalue2; + } + + if ((checkvalue[0] != hdev->rawedid[0x7f]) || + (checkvalue[1] != hdev->rawedid[0xff]) || + (checkvalue[2] != hdev->rawedid[0x17f]) || + (checkvalue[3] != hdev->rawedid[0x1ff])) { + hdev->RXCap.edid_changed = 1; + + checksum[0] = '0'; + checksum[1] = 'x'; + for (i = 0; i < 4; i++) + xtochar(0x80 * i + 0x7f, &checksum[2* i + 2]); + checksum[10] = '\0'; + memcpy(hdev->RXCap.checksum, checksum, 10); + printf("TV has changed, initial mode: %s attr: %s now crc: %s\n", + env_get("outputmode"), env_get("colorattribute"), checksum); + } else { + memcpy(hdev->RXCap.checksum, store_checkvalue, 10); + printf("TV is same, initial mode is: %s attr: %s, checksum: %s\n", + env_get("outputmode"), env_get("colorattribute"), + hdev->RXCap.checksum); + } + + if (hdev->RXCap.edid_changed) { + /* find proper mode if EDID changed */ + scene_process(hdev, &scene_output_info); + env_set("hdmichecksum", hdev->RXCap.checksum); + if (edid_parsing_ok(hdev)) { + /* SWPL-34712: if EDID parsing error case, not save env, + * only output default mode(480p,RGB,8bit). after + * EDID read OK, systemcontrol will recover the hdmi + * mode from env, to avoid keep the default hdmi output + */ + env_set("hdmimode", scene_output_info.final_displaymode); + env_set("outputmode", + scene_output_info.final_displaymode); + env_set("colorattribute", + scene_output_info.final_deepcolor); + /* if change from DV TV to HDR/SDR TV, don't change + * DV status to disabled, as DV core need to be enabled. + */ + if ((scene_output_info.final_dv_type != + get_ubootenv_dv_type()) && + (scene_output_info.final_dv_type != + DOLBY_VISION_DISABLE)) { + sprintf(dv_type, "%d", scene_output_info.final_dv_type); + env_set("dolby_status", dv_type); + /* according to the policy of systemcontrol, + * if current DV mode is not supported by TV + * EDID, DV type maybe changed to one witch + * TV support, and need VPP/DV module to + * update new DV output mode. + */ + printf("update dv_type: %d\n", + scene_output_info.final_dv_type); + } + } + printf("update outputmode: %s\n", env_get("outputmode")); + printf("update colorattribute: %s\n", env_get("colorattribute")); + printf("update hdmichecksum: %s\n", env_get("hdmichecksum")); + } + return 0; +} +static int do_get_preferred_mode(cmd_tbl_t * cmdtp, int flag, int argc, + char * const argv[]) +{ + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + + unsigned char *edid = hdev->rawedid; + + struct hdmi_format_para *para; + char pref_mode[64]; + char color_attr[64]; + char *hdmi_read_edid; + + hdmi_read_edid = env_get("hdmi_read_edid"); + if (hdmi_read_edid && (hdmi_read_edid[0] == '0')) + return 0; + + memset(edid, 0, EDID_BLK_SIZE * EDID_BLK_NO); + memset(pref_mode, 0, sizeof(pref_mode)); + memset(color_attr, 0, sizeof(color_attr)); + + /* If sink is not detected there is a still a good chance it supports proper modes */ + /* 720p is chosen as a safe compromise: supported by most sinks and looks good enough */ + if (!hdev->hwop.get_hpd_state()) { + para = hdmi_get_fmt_paras(HDMI_1280x720p60_16x9); + snprintf(pref_mode, sizeof(pref_mode), "%s", para->sname); + snprintf(color_attr, sizeof(color_attr), "%s", "rgb,8bit"); + printk("no sink, fallback to %s[%d]\n", para->sname, HDMI_1280x720p60_16x9); + goto bypass_edid_read; + } + + get_parse_edid_data(hdev); + para = hdmi_get_fmt_paras(hdev->RXCap.preferred_mode); + if (para) { - sprintf(pref_mode, "setenv hdmimode %s", para->sname); + sprintf(pref_mode, "preferred_mode %s", para->sname); if (hdev->RXCap.pref_colorspace & (1 << 5)) sprintf(color_attr, "setenv colorattribute %s", "444,8bit"); else if (hdev->RXCap.pref_colorspace & (1 << 4)) sprintf(color_attr, "setenv colorattribute %s", "422,8bit"); else sprintf(color_attr, "setenv colorattribute %s", "rgb,8bit"); - } else { /* set default mode */ + } else { hdev->RXCap.preferred_mode = HDMI_720x480p60_16x9; para = hdmi_get_fmt_paras(HDMI_720x480p60_16x9); sprintf(pref_mode, "setenv hdmimode %s", para->sname); sprintf(color_attr, "setenv colorattribute %s", "444,8bit"); } - printk("edid preferred_mode is %s[%d]\n", para->sname, hdev->RXCap.preferred_mode); + printk("sink preferred_mode is %s[%d]\n", para->sname, hdev->RXCap.preferred_mode); +bypass_edid_read: /* save to ENV */ + /* run_command(pref_mode, 0); run_command(color_attr, 0); run_command("saveenv", 0); + */ + printk("hdr mode is %d\n", hdev->RXCap.hdr_info.hdr_sup_eotf_smpte_st_2084); + printk("dv mode is ver:%d len: %x\n", hdev->RXCap.dv_info.ver, hdev->RXCap.dv_info.length); + printk("hdr10+ mode is %d\n", hdev->RXCap.hdr10plus_info.application_version); return 0; } @@ -393,6 +706,7 @@ U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""), U_BOOT_CMD_MKENT(get_preferred_mode, 1, 1, do_get_preferred_mode, "", ""), U_BOOT_CMD_MKENT(reg, 3, 1, do_reg, "", ""), + U_BOOT_CMD_MKENT(get_parse_edid, 1, 1, do_get_parse_edid, "", ""), }; static int do_hdmitx(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) @@ -415,7 +729,7 @@ U_BOOT_CMD(hdmitx, CONFIG_SYS_MAXARGS, 0, do_hdmitx, "HDMITX sub-system", - "hdmitx version:20181013\n" + "hdmitx version:20200618\n" "hdmitx hpd\n" " Detect hdmi rx plug-in\n" "hdmitx get_preferred_mode\n" @@ -439,3 +753,10 @@ "hdmitx rx_det\n" " Auto detect if RX is FBC and set outputmode\n" ); + +struct hdr_info *hdmitx_get_rx_hdr_info(void) +{ + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + + return &hdev->RXCap.hdr_info; +}
diff --git a/cmd/amlogic/cmd_lcd.c b/cmd/amlogic/cmd_lcd.c index 6809604..8a3a1a3 100644 --- a/cmd/amlogic/cmd_lcd.c +++ b/cmd/amlogic/cmd_lcd.c
@@ -5,8 +5,27 @@ #include <common.h> #include <command.h> +#include <malloc.h> #include <amlogic/media/vout/lcd/aml_lcd.h> +static unsigned int lcd_parse_vout_name(char *name) +{ + char *p, *frac_str; + unsigned int frac = 0; + + p = strchr(name, ','); + if (!p) { + frac = 0; + } else { + frac_str = p + 1; + *p = '\0'; + if (strcmp(frac_str, "frac") == 0) + frac = 1; + } + + return frac; +} + static int do_lcd_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();; @@ -26,18 +45,35 @@ static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - char *mode; + char *mode, *str; + unsigned int frac; if (lcd_drv == NULL) { printf("no lcd driver\n"); return 0; } - mode = env_get("outputmode"); + str = getenv("outputmode"); + if (!str) { + printf("no outputmode\n"); + return -1; + } + + mode = (char *)malloc(64); + if (!mode) { + printf("%s: create mode failed\n", __func__); + return -1; + } + memset(mode, 0, sizeof(mode)); + sprintf(mode, "%s", str); + frac = lcd_parse_vout_name(mode); + if (lcd_drv->lcd_enable) - lcd_drv->lcd_enable(mode); + lcd_drv->lcd_enable(mode, frac); else printf("no lcd enable\n"); + + free(mode); return 0; }
diff --git a/cmd/amlogic/cmd_misc.c b/cmd/amlogic/cmd_misc.c new file mode 100644 index 0000000..8094093 --- /dev/null +++ b/cmd/amlogic/cmd_misc.c
@@ -0,0 +1,208 @@ + +/* + * cmd/amlogic/cmd_misc.c + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +*/ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <amlogic/flash_ts.h> +#include <amlogic/led_aw2015.h> +#include <dm.h> + +struct vol_table { + unsigned int val; + char voltage[5]; +}; + +struct vol_table vddee_table[] = { + {0xb, "0.71V"}, + {0xc, "0.72V"}, + {0xd, "0.73V"}, + {0xe, "0.74V"}, + {0xf, "0.75V"}, + {0x10, "0.76V"}, + {0x11, "0.77V"}, + {0x12, "0.78V"}, + {0x13, "0.79V"}, + {0x14, "0.80V"}, + {0x15, "0.81V"}, + {0x16, "0.82V"}, + {0x17, "0.83V"}, + {0x18, "0.84V"}, + {0x19, "0.85V"}, + {0x1a, "0.86V"}, + {0x1b, "0.87V"}, + {0x1c, "0.88V"}, + {0x1d, "0.89V"}, +}; + +int do_charger_detect_boot(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ +#if defined(CONFIG_ENABLE_CHARGER_DETECTION) + char *s; + const char *key_name = "boot.enforce_charger_detection"; + char key_value[256] = { 0 }; + int i = 10; + + s = env_get("reboot_mode"); + if (strncmp(s, "cold_boot", 9)) { + pr_crit("Skip charger enforcement since it's not cold boot\n"); + return 0; + } + + if(is_flash_inited()) { + flash_ts_init(); + + flash_ts_get(key_name, key_value, sizeof(key_value)); + pr_info("FTS read: boot.enforce_charger_detection -> %s\n", key_value); + } + + s = env_get("charger_type"); + if (!strncmp(s, "DCP", 3)) { + pr_info("charger-DCP: Booting...\n"); + sys_led_init(WHITE); + return 0; + } + + if (strncmp(key_value, "true", 4)) { + sys_led_init(YELLOW); + return 0; + } + + sys_led_init(BLINK_YELLOW); + do { + s = env_get("charger_type"); + if (!strncmp(s, "DCP", 3)) { + pr_info("charger-DCP: Booting...\n"); + sys_led_init(WHITE); + break; + } else { + pr_crit("Stop booting kernel due to charger type is incompatible\n"); + pr_crit("Expected: DCP, Actual: %s\n", s); + pr_crit("Register dump:\n"); + pr_crit("[0xfe0044a4] = 0x%x\n", readl(0xfe0044a4)); + mdelay(1000); + i--; + if (i > 0) { + pr_crit("Retrying...\n"); + run_command("musb bc", 0); + } + } + } while(1); + +#endif + return 0; +} + +U_BOOT_CMD( + charger_detect_boot, 1, 0, do_charger_detect_boot, + "only allow booting when charger is detected as DCP\n", + "charger_detect_boot" +); + +int charger_detection_config (char * const value) +{ + int ret = 1; + + if(is_flash_inited()) { + flash_ts_init(); + + char key[] = "boot.enforce_charger_detection"; + ret = flash_ts_set(key, value); + + printf("FTS set:\n%s -> %s\nReturn: %d\n", key, value, ret); + } + return ret; +} + +int do_enable_charger_detection (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char value[] = "true"; + return charger_detection_config(value); +} + +int do_disable_charger_detection (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char value[] = "false"; + return charger_detection_config(value); +} + +int do_clear_charger_detection_flag (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char value[] = ""; + return charger_detection_config(value); +} + +U_BOOT_CMD( + enforce_charger_detection, 1, 0, do_enable_charger_detection, + "Set FTS flag to force chareger detection.", + "enforce_charger_detection\n" +); + +U_BOOT_CMD( + disable_charger_detection, 1, 0, do_disable_charger_detection, + "set FTS flag to disable chareger detection.", + "disable_charger_detection\n" +); + +U_BOOT_CMD( + clear_charger_detection_flag, 1, 0, do_clear_charger_detection_flag, + "clear chareger detection key.", + "clear_charger_detection_flag\n" +); + +int do_get_vddee_voltage(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret = 0; + unsigned int bus_num = 4; + unsigned int dev_addr = 0x6a; + unsigned int reg_addr = 0x0; + unsigned int reg_val; + char voltage_str[5]; + struct udevice *ic_devp = NULL; + int i; + + ret = i2c_get_chip_for_busnum(bus_num, dev_addr, 1, &ic_devp); + if (ret) { + pr_err("LED: i2c get bus fail\n"); + return; + } + + reg_val = dm_i2c_reg_read(ic_devp, reg_addr); + for (i = 0; i < (sizeof(vddee_table)/sizeof(struct vol_table)); i++) { + if((reg_val & 0x3f) == vddee_table[i].val) + break; + } + + if (i == sizeof(vddee_table)/sizeof(struct vol_table)) { + env_set("vddee_voltage", "unknown"); + } else { + env_set("vddee_voltage", vddee_table[i].voltage); + } + + return ret; +} + +U_BOOT_CMD( + get_ee_vol, 1, 0, do_get_vddee_voltage, + "get the vddee voltage and export to cmdline", + "get_ee_vol\n" +);
diff --git a/cmd/amlogic/cmd_osd.c b/cmd/amlogic/cmd_osd.c index ef8feb4..4001c74 100644 --- a/cmd/amlogic/cmd_osd.c +++ b/cmd/amlogic/cmd_osd.c
@@ -11,6 +11,7 @@ #include <splash.h> #include <video_fb.h> #include <video.h> +#include <amlogic/fb.h> int osd_enabled = 0; /* Graphic Device */ @@ -22,6 +23,7 @@ extern void osd_enable_hw(u32 index, u32 enable); extern void osd_set_free_scale_enable_hw(u32 index, u32 enable); extern int osd_rma_test(u32 osd_index); +extern int get_osd_layer(void); static int do_osd_open(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { @@ -37,10 +39,11 @@ static int do_osd_enable(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - ulong index = 0; + int index = 0; - index = simple_strtoul(env_get("display_layer"), NULL, 0); - osd_enable_hw(index, 1); + index = get_osd_layer(); + if (index >= 0) + osd_enable_hw(index, 1); return 0; } @@ -48,38 +51,59 @@ static int do_osd_close(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { + + uint index = 0; + + index = get_osd_layer(); + if (gdev == NULL) return 1; gdev = NULL; - osd_enable_hw(0, 0); - osd_enable_hw(1, 0); - osd_set_free_scale_enable_hw(0, 0); - osd_set_free_scale_enable_hw(1, 0); + if (index >= VIU2_OSD1) { + osd_enable_hw(VIU2_OSD1, 0); + } else { + osd_enable_hw(OSD1, 0); + osd_enable_hw(OSD2, 0); + osd_set_free_scale_enable_hw(OSD1, 0); + osd_set_free_scale_enable_hw(OSD2, 0); + } + osd_enabled = 0; + return 0; } static int do_osd_clear(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { +#ifdef OSD_SCALE_ENABLE + uint index = 0; + ulong fb_addr; + ulong fb_len; +#endif if (gdev == NULL) { printf("Please enable osd device first!\n"); return 1; } #ifdef OSD_SCALE_ENABLE - memset((void *)(long long)(gdev->frameAdrs), 0, - (gdev->fb_width * gdev->fb_height)*gdev->gdfBytesPP); - - flush_cache(gdev->frameAdrs, - ((gdev->fb_width * gdev->fb_height)*gdev->gdfBytesPP)); + index = get_osd_layer(); + if (index < VIU2_OSD1) { + fb_addr = (ulong)gdev->frameAdrs; + fb_len = CANVAS_ALIGNED(gdev->fb_width * gdev->gdfBytesPP) * gdev->fb_height; + } else { + fb_addr = (ulong)(gdev->frameAdrs + + CANVAS_ALIGNED(gdev->fb_width * gdev->gdfBytesPP) * gdev->fb_height); + fb_len = CANVAS_ALIGNED(gdev->winSizeX * gdev->gdfBytesPP) * gdev->winSizeY; + } + memset((void *)fb_addr, 0, fb_len); + flush_cache(fb_addr, fb_len); #else - memset((void *)(long long)(gdev->frameAdrs), 0, - (gdev->winSizeX * gdev->winSizeY)*gdev->gdfBytesPP); + fb_len = CANVAS_ALIGNED(gdev->winSizeX * gdev->gdfBytesPP) * gdev->winSizeY; + memset((void *)(long long)(gdev->frameAdrs), 0, fb_len); - flush_cache(gdev->frameAdrs, - ((gdev->winSizeX * gdev->winSizeY)*gdev->gdfBytesPP)); + flush_cache(gdev->frameAdrs, fb_len); #endif return 0; }
diff --git a/cmd/amlogic/cmd_reboot.c b/cmd/amlogic/cmd_reboot.c index 36b6097..867ab01 100644 --- a/cmd/amlogic/cmd_reboot.c +++ b/cmd/amlogic/cmd_reboot.c
@@ -10,7 +10,9 @@ #include <asm/arch/secure_apb.h> #include <asm/io.h> #include <asm/arch/bl31_apis.h> - +#include <partition_table.h> +#include <amlogic/storage.h> +#include <amlogic/led_aw2015.h> /* run get_rebootmode //set reboot_mode env with current mode */ @@ -18,7 +20,8 @@ int do_get_rebootmode (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { uint32_t reboot_mode_val; -#ifdef CONFIG_MESON_C1 + char reboot_mode[16]; +#if defined(CONFIG_MESON_C1) || defined(CONFIG_MESON_C2) reboot_mode_val = ((readl(SYSCTRL_SEC_STATUS_REG2 ) >> 12) & 0xf); debug("reboot_mode(0x%x)=0x%x\n", SYSCTRL_SEC_STATUS_REG2, reboot_mode_val); #else @@ -26,12 +29,14 @@ debug("reboot_mode(0x%x)=0x%x\n", AO_SEC_SD_CFG15, reboot_mode_val); #endif + strcpy(reboot_mode, "reboot_mode"); if(is_flash_inited()) { flash_ts_init(); const char *fts_key = "bootloader.command"; char fts_value[256] = { 0 }; + printf("default reboot_mode_val is %d\n", reboot_mode_val); flash_ts_get(fts_key, fts_value, sizeof(fts_value)); pr_info("FTS read: bootloader.command -> %s\n", fts_value); @@ -42,8 +47,14 @@ pr_info("overwriting reboot_mode_val to: %d\n", reboot_mode_val); #endif } else if (strncmp(fts_value, "boot-factory", sizeof(fts_value)) == 0) { - reboot_mode_val = AMLOGIC_QUIESCENT_REBOOT; - pr_info("overwriting reboot_mode_val to: %d\n", reboot_mode_val); + /* forece to u-boot console in factory mode */ + if (reboot_mode_val == AMLOGIC_BOOTLOADER_REBOOT) { + env_set("bootdelay","-1"); + } else { + pr_info("overwriting reboot_mode_val to: %d\n", reboot_mode_val); + env_set(reboot_mode, "factory_boot"); + strncpy(reboot_mode, "real_reboot_mode", 16); + } } } @@ -51,77 +62,82 @@ { case AMLOGIC_COLD_BOOT: { - env_set("reboot_mode","cold_boot"); + env_set(reboot_mode,"cold_boot"); break; } case AMLOGIC_NORMAL_BOOT: { - env_set("reboot_mode","normal"); + env_set(reboot_mode,"normal"); break; } case AMLOGIC_QUIESCENT_REBOOT: { - env_set("reboot_mode","factory_boot"); + env_set(reboot_mode,"factory_boot"); break; } case AMLOGIC_FACTORY_RESET_REBOOT: { - env_set("reboot_mode","factory_reset"); + env_set(reboot_mode,"factory_reset"); break; } case AMLOGIC_UPDATE_REBOOT: { - env_set("reboot_mode","update"); + env_set(reboot_mode,"update"); break; } case AMLOGIC_FASTBOOT_REBOOT: { - env_set("reboot_mode","fastboot"); + env_set(reboot_mode,"fastboot"); break; } case AMLOGIC_BOOTLOADER_REBOOT: { - env_set("reboot_mode","bootloader"); + env_set(reboot_mode,"bootloader"); break; } case AMLOGIC_SUSPEND_REBOOT: { - env_set("reboot_mode","suspend_off"); + env_set(reboot_mode,"suspend_off"); break; } case AMLOGIC_HIBERNATE_REBOOT: { - env_set("reboot_mode","hibernate"); + env_set(reboot_mode,"hibernate"); break; } case AMLOGIC_SHUTDOWN_REBOOT: { - env_set("reboot_mode","shutdown_reboot"); + env_set(reboot_mode,"shutdown_reboot"); break; } case AMLOGIC_CRASH_REBOOT: { - env_set("reboot_mode","crash_dump"); + env_set(reboot_mode,"crash_dump"); break; } case AMLOGIC_KERNEL_PANIC: { - env_set("reboot_mode","kernel_panic"); + env_set(reboot_mode,"kernel_panic"); break; } case AMLOGIC_WATCHDOG_REBOOT: { - env_set("reboot_mode","watchdog_reboot"); + env_set(reboot_mode,"watchdog_reboot"); break; } case AMLOGIC_RPMBP_REBOOT: { - env_set("reboot_mode","rpmbp"); + env_set(reboot_mode,"rpmbp"); + break; + } + case AMLOGIC_DELAYED_REBOOT: + { + env_set(reboot_mode,"delayed_reboot"); break; } default: { - env_set("reboot_mode","charging"); + env_set(reboot_mode,"charging"); break; } } @@ -133,13 +149,14 @@ break; } case AMLOGIC_BOOTLOADER_REBOOT: { - env_set("bootdelay","-1"); + if (dynamic_partition) + env_set("reboot_mode","fastboot"); break; } } #endif -#if !defined(CONFIG_AML_RPMB_DISABLE) +#if defined(CONFIG_AML_RPMB) run_command("rpmb_state",0); #endif @@ -155,7 +172,10 @@ pr_info("reboot mode: %s\n", argv[1]); char * mode = argv[1]; - if (strcmp(mode, "cold_boot") == 0) + if (strcmp(mode, "next") == 0) { + store_restore_bootidx(); + reboot_mode_val = AMLOGIC_COLD_BOOT; + } else if (strcmp(mode, "cold_boot") == 0) reboot_mode_val = AMLOGIC_COLD_BOOT; else if (strcmp(mode, "normal") == 0) reboot_mode_val = AMLOGIC_NORMAL_BOOT; @@ -165,9 +185,14 @@ reboot_mode_val = AMLOGIC_QUIESCENT_REBOOT; else if (strcmp(mode, "update") == 0) reboot_mode_val = AMLOGIC_UPDATE_REBOOT; - else if (strcmp(mode, "fastboot") == 0) - reboot_mode_val = AMLOGIC_FASTBOOT_REBOOT; - else if (strcmp(mode, "bootloader") == 0) + else if (strcmp(mode, "fastboot") == 0) { + if (dynamic_partition) { + printf("dynamic partition, enter fastbootd"); + reboot_mode_val = AMLOGIC_FACTORY_RESET_REBOOT; + run_command("bcb fastbootd",0); + } else + reboot_mode_val = AMLOGIC_FASTBOOT_REBOOT; + } else if (strcmp(mode, "bootloader") == 0) reboot_mode_val = AMLOGIC_BOOTLOADER_REBOOT; else if (strcmp(mode, "suspend_off") == 0) reboot_mode_val = AMLOGIC_SUSPEND_REBOOT; @@ -241,6 +266,7 @@ " bootloader\n" " suspend_off\n" " hibernate\n" + " next <ONLY work for SC2>\n" " crash_dump\n" ); @@ -266,3 +292,23 @@ "system off ", "systemoff " ); + +int do_delayed_reboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + uint32_t delay_time; + + delay_time = readl(SYSCTRL_STICKY_REG5); + if (delay_time == 0) + delay_time = 30; + + pr_info("delay %ds before booting...\n", delay_time); + sys_led_init(YELLOW); + udelay(delay_time * 1000 * 1000); + return 0; +} + +U_BOOT_CMD( + delayed_reboot, 1, 1, do_delayed_reboot, + "delayed_reboot ", + "delayed_reboot " +);
diff --git a/cmd/amlogic/cmd_rpmb.c b/cmd/amlogic/cmd_rpmb.c index 51433e8..5bf75a9 100644 --- a/cmd/amlogic/cmd_rpmb.c +++ b/cmd/amlogic/cmd_rpmb.c
@@ -8,48 +8,146 @@ #include <asm/arch/io.h> #include <command.h> #include <malloc.h> -#include <asm/arch/secure_apb.h> +#include <tee.h> + +#define TEE_ERROR_RPMB_AUTH_KEY_PROGRAMMED 0x7FFFFFFD + +#define CMD_RPMB_AUTH_KEY_INIT 0 +#define CMD_RPMB_AUTH_KEY_STATE 1 + +#define TA_RPMB_UUID { 0x0ab5a718, 0xee63, 0x4115, \ + { 0xa0, 0xad, 0xef, 0x6e, 0xe9, 0x8f, 0xcb, 0xc7 } } + +static int do_rpmb_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret = 0; + struct udevice *dev; + struct tee_open_session_arg open_arg; + struct tee_invoke_arg invoke_arg; + const struct tee_optee_ta_uuid uuid = TA_RPMB_UUID; + + dev = tee_find_device(NULL, NULL, NULL, NULL); + if (!dev) { + printf("tee_find_device() failed"); + return -ENODEV; + } + + memset(&open_arg, 0, sizeof(open_arg)); + tee_optee_ta_uuid_to_octets(open_arg.uuid, &uuid); + ret = tee_open_session(dev, &open_arg, 0, NULL); + if (ret) { + printf("tee_open_session() failed, ret = 0x%x\n", ret); + return ret; + } + if (open_arg.ret) { + printf("tee_open_session() failed, ret = 0x%x\n", + open_arg.ret, open_arg.ret_origin); + return open_arg.ret; + } + + memset(&invoke_arg, 0, sizeof(invoke_arg)); + invoke_arg.session = open_arg.session; + invoke_arg.func = CMD_RPMB_AUTH_KEY_INIT; + + ret = tee_invoke_func(dev, &invoke_arg, 0, NULL); + if (ret) { + printf("tee_invoke_func() failed, ret = 0x%x\n", ret); + goto exit; + } + if (invoke_arg.ret == TEE_SUCCESS) { + printf("program RPMB auth key success\n"); + } else if (invoke_arg.ret == TEE_ERROR_RPMB_AUTH_KEY_PROGRAMMED) { + printf("RPMB auth key is programmed already\n"); + } else { + printf("tee_invoke_func() failed, ret = 0x%x, origin = %d\n", + invoke_arg.ret, invoke_arg.ret_origin); + ret = invoke_arg.ret; + goto exit; + } + +exit: + tee_close_session(dev, open_arg.session); + + return ret; +} + +U_BOOT_CMD(rpmb_init, CONFIG_SYS_MAXARGS, 0, do_rpmb_init, + "RPMB sub-system", + "RPMB auth key init\n"); static int do_rpmb_state(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { - int nReturn = __LINE__; + int ret = 0; + struct udevice *dev; + struct tee_open_session_arg open_arg; + struct tee_invoke_arg invoke_arg; + const struct tee_optee_ta_uuid uuid = TA_RPMB_UUID; + struct tee_param param = { .attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT }; -#define AML_RPMB_STATE (((readl(AO_SEC_GP_CFG7))>>22) & 0x01) - - char *pARG = env_get("bootargs"); - - if (pARG) - { - //printf("1 bootargs=%s\n",pARG); - - char *szBuffer=malloc(strlen(pARG)+64); - nReturn = __LINE__; - - if (szBuffer) - { - memset(szBuffer+strlen(pARG),0,64); - strcpy(szBuffer,pARG); - char *pFind = strstr(szBuffer,"androidboot.rpmb_state"); - if (!pFind) - sprintf(szBuffer,"%s androidboot.rpmb_state=%d",pARG,AML_RPMB_STATE); - else - pFind[23] = AML_RPMB_STATE ? '1':'0'; - - //printf("2 bootargs=%s\n",szBuffer); - - env_set("rpmb_state",AML_RPMB_STATE?"1":"0"); //need this? - env_set("bootargs",szBuffer); - free(szBuffer); - szBuffer = 0; - - nReturn = 0; - } - else - printf("aml log : internal sys error!\n"); - + dev = tee_find_device(NULL, NULL, NULL, NULL); + if (!dev) { + printf("tee_find_device() failed"); + return -ENODEV; } - return nReturn; + memset(&open_arg, 0, sizeof(open_arg)); + tee_optee_ta_uuid_to_octets(open_arg.uuid, &uuid); + ret = tee_open_session(dev, &open_arg, 0, NULL); + if (ret) { + printf("tee_open_session() failed, ret = 0x%x\n", ret); + return ret; + } + if (open_arg.ret) { + printf("tee_open_session() failed, ret = 0x%x\n", + open_arg.ret, open_arg.ret_origin); + return open_arg.ret; + } + + memset(&invoke_arg, 0, sizeof(invoke_arg)); + invoke_arg.session = open_arg.session; + invoke_arg.func = CMD_RPMB_AUTH_KEY_STATE; + + ret = tee_invoke_func(dev, &invoke_arg, 1, ¶m); + if (ret) { + printf("tee_invoke_func() failed, ret = 0x%x\n", ret); + goto exit; + } + if (invoke_arg.ret) { + printf("tee_invoke_func() failed, ret = 0x%x, origin = %d\n", + invoke_arg.ret, invoke_arg.ret_origin); + ret = invoke_arg.ret; + goto exit; + } + + char *parg = env_get("bootargs"); + if (parg) + { + char *buff =malloc(strlen(parg) + 64); + if (!buff) { + ret = -ENOMEM; + goto exit; + } + + memset(buff + strlen(parg), 0, 64); + strcpy(buff, parg); + char *find = strstr(buff, "androidboot.rpmb_state"); + if (!find) + sprintf(buff,"%s androidboot.rpmb_state=%d", parg, param.u.value.a); + else + find[23] = param.u.value.a ? '1':'0'; + + //printf("2 bootargs=%s\n",buff); + + env_set("rpmb_state", param.u.value.a?"1":"0"); //need this? + env_set("bootargs", buff); + free(buff); + buff = NULL; + } + +exit: + tee_close_session(dev, open_arg.session); + + return ret; } U_BOOT_CMD(rpmb_state, CONFIG_SYS_MAXARGS, 0, do_rpmb_state,
diff --git a/cmd/amlogic/cmd_rsvmem.c b/cmd/amlogic/cmd_rsvmem.c index ad6561f..1d90194 100644 --- a/cmd/amlogic/cmd_rsvmem.c +++ b/cmd/amlogic/cmd_rsvmem.c
@@ -10,6 +10,16 @@ #ifdef CONFIG_CMD_RSVMEM +#if defined(P_AO_SEC_GP_CFG3) +#define REG_RSVMEM_SIZE P_AO_SEC_GP_CFG3 +#define REG_RSVMEM_BL32_START P_AO_SEC_GP_CFG4 +#define REG_RSVMEM_BL31_START P_AO_SEC_GP_CFG5 +#elif defined(SYSCTRL_SEC_STATUS_REG15) +#define REG_RSVMEM_SIZE SYSCTRL_SEC_STATUS_REG15 +#define REG_RSVMEM_BL32_START SYSCTRL_SEC_STATUS_REG16 +#define REG_RSVMEM_BL31_START SYSCTRL_SEC_STATUS_REG17 +#endif + //#define RSVMEM_DEBUG_ENABLE #ifdef RSVMEM_DEBUG_ENABLE #define rsvmem_dbg(fmt...) printf("[rsvmem] "fmt) @@ -42,11 +52,11 @@ unsigned int aarch32 = 0; rsvmem_dbg("reserved memory check!\n"); - data = readl(P_AO_SEC_GP_CFG3); + data = readl(REG_RSVMEM_SIZE); bl31_rsvmem_size = ((data & 0xffff0000) >> 16) << 10; bl32_rsvmem_size = (data & 0x0000ffff) << 10; - bl31_rsvmem_start = readl(P_AO_SEC_GP_CFG5); - bl32_rsvmem_start = readl(P_AO_SEC_GP_CFG4); + bl31_rsvmem_start = readl(REG_RSVMEM_BL31_START); + bl32_rsvmem_start = readl(REG_RSVMEM_BL32_START); fdtaddr = env_get("fdtaddr"); if (fdtaddr == NULL) { @@ -248,11 +258,11 @@ unsigned int bl32_rsvmem_start = 0; rsvmem_info("reserved memory:\n"); - data = readl(P_AO_SEC_GP_CFG3); + data = readl(REG_RSVMEM_SIZE); bl31_rsvmem_size = ((data & 0xffff0000) >> 16) << 10; bl32_rsvmem_size = (data & 0x0000ffff) << 10; - bl31_rsvmem_start = readl(P_AO_SEC_GP_CFG5); - bl32_rsvmem_start = readl(P_AO_SEC_GP_CFG4); + bl31_rsvmem_start = readl(REG_RSVMEM_BL31_START); + bl32_rsvmem_start = readl(REG_RSVMEM_BL32_START); rsvmem_info("bl31 reserved memory start: 0x%08x\n", bl31_rsvmem_start); rsvmem_info("bl31 reserved memory size: 0x%08x\n", bl31_rsvmem_size);
diff --git a/cmd/amlogic/cmd_vout.c b/cmd/amlogic/cmd_vout.c index cf41115..6f59753 100644 --- a/cmd/amlogic/cmd_vout.c +++ b/cmd/amlogic/cmd_vout.c
@@ -13,7 +13,7 @@ #endif #include <amlogic/media/vout/aml_vout.h> #ifdef CONFIG_AML_HDMITX -#include <amlogic/media/vout/hdmitx.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> #endif #ifdef CONFIG_AML_CVBS @@ -23,15 +23,40 @@ #include <amlogic/media/vout/lcd/aml_lcd.h> #endif +static unsigned int vout_parse_vout_name(char *name) +{ + char *p, *frac_str; + unsigned int frac = 0; + + p = strchr(name, ','); + if (!p) { + frac = 0; + } else { + frac_str = p + 1; + *p = '\0'; + if (strcmp(frac_str, "frac") == 0) + frac = 1; + } + + return frac; +} + static int do_vout_list(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { +#ifdef CONFIG_AML_HDMITX + struct hdmitx_dev *hdmitx_device = hdmitx_get_hdev(); +#endif #ifdef CONFIG_AML_LCD struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); #endif #ifdef CONFIG_AML_HDMITX - printf("\nvalid hdmi mode:\n"); - hdmitx_device.HWOp.list_support_modes(); + if (!hdmitx_device) { + printf("\nerror: hdmitx device is null\n"); + } else { + printf("\nvalid hdmi mode:\n"); + hdmitx_device->hwop.list_support_modes(); + } #endif #ifdef CONFIG_AML_CVBS @@ -56,8 +81,11 @@ static int do_vout_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { + char *mode; + unsigned int frac; #ifdef CONFIG_AML_HDMITX - char mode[64]; + char str[64]; + int venc_sel; #endif #ifdef CONFIG_AML_LCD struct aml_lcd_drv_s *lcd_drv = NULL; @@ -66,25 +94,50 @@ if (argc != 2) return CMD_RET_FAILURE; + mode = (char *)malloc(64 * sizeof(char)); + if (!mode) { + printf("cmd_vout: mode malloc falied, exit\n"); + return CMD_RET_FAILURE; + } + memset(mode, 0, sizeof(mode)); + sprintf(mode, "%s", argv[1]); + frac = vout_parse_vout_name(mode); + #ifdef CONFIG_AML_CVBS - if (cvbs_outputmode_check(argv[1]) == 0) { + if (cvbs_outputmode_check(mode, frac) == 0) { + vout_viu_mux(VOUT_VIU1_SEL, VIU_MUX_ENCI); #ifdef CONFIG_AML_VPP vpp_matrix_update(VPP_CM_YUV); #endif - if (cvbs_set_vmode(argv[1]) == 0) + if (cvbs_set_vmode(mode) == 0) { + free(mode); + run_command("setenv vout_init enable", 0); return CMD_RET_SUCCESS; + } } #endif #ifdef CONFIG_AML_HDMITX - if (hdmi_outputmode_check(argv[1]) == 0) { + if (frac == 0) { /* remove frac support in outputmode */ + venc_sel = hdmi_outputmode_check(mode, frac); + if (venc_sel < VIU_MUX_MAX) { + vout_viu_mux(VOUT_VIU1_SEL, venc_sel); #ifdef CONFIG_AML_VPP - vpp_matrix_update(VPP_CM_YUV); + vpp_matrix_update(VPP_CM_YUV); #endif - memset(mode, 0, sizeof(mode)); - sprintf(mode, "hdmitx output %s", argv[1]); - run_command(mode, 0); - return CMD_RET_SUCCESS; + /* //remove frac support in outputmode + *if (frac) + * setenv("frac_rate_policy", "1"); + *else + * setenv("frac_rate_policy", "0"); + */ + memset(str, 0, sizeof(str)); + sprintf(str, "hdmitx output %s", mode); + run_command(str, 0); + free(mode); + run_command("setenv vout_init enable", 0); + return CMD_RET_SUCCESS; + } } #endif @@ -92,12 +145,15 @@ lcd_drv = aml_lcd_get_driver(); if (lcd_drv) { if (lcd_drv->lcd_outputmode_check) { - if (lcd_drv->lcd_outputmode_check(argv[1]) == 0) { + if (lcd_drv->lcd_outputmode_check(mode, frac) == 0) { + vout_viu_mux(VOUT_VIU1_SEL, VIU_MUX_ENCL); #ifdef CONFIG_AML_VPP vpp_matrix_update(VPP_CM_RGB); #endif if (lcd_drv->lcd_enable) { - lcd_drv->lcd_enable(argv[1]); + lcd_drv->lcd_enable(mode, frac); + free(mode); + run_command("setenv vout_init enable", 0); return CMD_RET_SUCCESS; } else printf("no lcd enable\n"); @@ -108,6 +164,153 @@ } #endif + free(mode); + return CMD_RET_FAILURE; +} + +static int do_vout2_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + char *mode; + unsigned int frac; +#ifdef CONFIG_AML_HDMITX20 + char str[64]; + int venc_sel; +#endif +#ifdef CONFIG_AML_LCD + struct aml_lcd_drv_s *lcd_drv = NULL; +#endif + + if (argc != 2) + return CMD_RET_FAILURE; + + mode = (char *)malloc(64 * sizeof(char)); + if (!mode) { + printf("cmd_vout: mode malloc falied, exit\n"); + return CMD_RET_FAILURE; + } + memset(mode, 0, sizeof(mode)); + sprintf(mode, "%s", argv[1]); + frac = vout_parse_vout_name(mode); + +#ifdef CONFIG_AML_CVBS + if (cvbs_outputmode_check(mode, frac) == 0) { + if (cvbs_set_vmode(mode) == 0) { + free(mode); + return CMD_RET_SUCCESS; + } + } +#endif + +#ifdef CONFIG_AML_HDMITX20 + if (frac == 0) { /* remove frac support in outputmode */ + venc_sel = hdmi_outputmode_check(mode, frac); + if (venc_sel < VIU_MUX_MAX) { + /* //remove frac support in outputmode + *if (frac) + * setenv("frac_rate_policy", "1"); + *else + * setenv("frac_rate_policy", "0"); + */ + memset(str, 0, sizeof(str)); + sprintf(str, "hdmitx output %s", mode); + run_command(str, 0); + free(mode); + return CMD_RET_SUCCESS; + } + } +#endif + +#ifdef CONFIG_AML_LCD + lcd_drv = aml_lcd_get_driver(); + if (lcd_drv) { + if (lcd_drv->lcd_outputmode_check) { + if (lcd_drv->lcd_outputmode_check(mode, frac) == 0) { + if (lcd_drv->lcd_enable) { + lcd_drv->lcd_enable(mode, frac); + free(mode); + return CMD_RET_SUCCESS; + } else + printf("no lcd enable\n"); + } + } + } else { + printf("no lcd driver\n"); + } +#endif + + free(mode); + return CMD_RET_FAILURE; +} + +static int do_vout2_prepare(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + char *mode; + unsigned int frac; +#ifdef CONFIG_AML_HDMITX20 + int venc_sel; +#endif +#ifdef CONFIG_AML_LCD + struct aml_lcd_drv_s *lcd_drv = NULL; +#endif + + if (argc != 2) + return CMD_RET_FAILURE; + + mode = (char *)malloc(64 * sizeof(char)); + if (!mode) { + printf("cmd_vout: mode malloc falied, exit\n"); + return CMD_RET_FAILURE; + } + memset(mode, 0, sizeof(mode)); + sprintf(mode, "%s", argv[1]); + frac = vout_parse_vout_name(mode); + +#ifdef CONFIG_AML_CVBS + if (cvbs_outputmode_check(mode, frac) == 0) { + vout_viu_mux(VOUT_VIU2_SEL, VIU_MUX_ENCI); +#ifdef CONFIG_AML_VPP + vpp_viu2_matrix_update(VPP_CM_YUV); +#endif + free(mode); + return CMD_RET_SUCCESS; + } +#endif + +#ifdef CONFIG_AML_HDMITX20 + venc_sel = hdmi_outputmode_check(mode, frac); + if (venc_sel < VIU_MUX_MAX) { + vout_viu_mux(VOUT_VIU2_SEL, venc_sel); +#ifdef CONFIG_AML_VPP + vpp_viu2_matrix_update(VPP_CM_YUV); +#endif + free(mode); + return CMD_RET_SUCCESS; + } +#endif + +#ifdef CONFIG_AML_LCD + lcd_drv = aml_lcd_get_driver(); + if (lcd_drv) { + if (lcd_drv->lcd_outputmode_check) { + if (lcd_drv->lcd_outputmode_check(mode, frac) == 0) { + vout_viu_mux(VOUT_VIU2_SEL, VIU_MUX_ENCL); +#ifdef CONFIG_AML_VPP + vpp_viu2_matrix_update(VPP_CM_YUV); +#endif + if (lcd_drv->lcd_prepare) { + lcd_drv->lcd_prepare(mode, frac); + free(mode); + return CMD_RET_SUCCESS; + } else + printf("no lcd prepare\n"); + } + } + } else { + printf("no lcd driver\n"); + } +#endif + + free(mode); return CMD_RET_FAILURE; } @@ -149,3 +352,36 @@ " format : perfered output video mode\n" " info : dump vinfo\n" ); + +static cmd_tbl_t cmd_vout2_sub[] = { + U_BOOT_CMD_MKENT(list, 1, 1, do_vout_list, "", ""), + U_BOOT_CMD_MKENT(prepare, 3, 1, do_vout2_prepare, "", ""), + U_BOOT_CMD_MKENT(output, 3, 1, do_vout2_output, "", ""), + U_BOOT_CMD_MKENT(info, 1, 1, do_vout_info, "", ""), +}; + +static int do_vout2(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + cmd_tbl_t *c; + + if (argc < 2) + return cmd_usage(cmdtp); + + argc--; + argv++; + + c = find_cmd_tbl(argv[0], &cmd_vout2_sub[0], ARRAY_SIZE(cmd_vout2_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return cmd_usage(cmdtp); +} + +U_BOOT_CMD(vout2, CONFIG_SYS_MAXARGS, 1, do_vout2, + "VOUT2 sub-system", + "vout2 [list | prepare format | output format | info]\n" + " list : list for valid video mode names.\n" + " format : perfered output video mode\n" + " info : dump vinfo\n" +);
diff --git a/cmd/amlogic/cmd_vpp.c b/cmd/amlogic/cmd_vpp.c index f781f61..f61202f 100644 --- a/cmd/amlogic/cmd_vpp.c +++ b/cmd/amlogic/cmd_vpp.c
@@ -38,8 +38,24 @@ return CMD_RET_SUCCESS; } +static int do_hdr_packet(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + + if (argc < 1) { + printf("[vpp] hdr packet error !!!\n"); + return cmd_usage(cmdtp); + } + if (!check_dolby_vision_on()) { + printf("hdr_packet\n"); + hdr_tx_pkt_cb(); + } + + return CMD_RET_SUCCESS; +} + static cmd_tbl_t cmd_vpp_sub[] = { U_BOOT_CMD_MKENT(pq, 5, 1, do_vpp_pq, "", ""), + U_BOOT_CMD_MKENT(hdrpkt, 1, 1, do_hdr_packet, "", ""), }; static int do_vpp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/cmd/amlogic/imgread.c b/cmd/amlogic/imgread.c index b6858ea..e90915f 100755 --- a/cmd/amlogic/imgread.c +++ b/cmd/amlogic/imgread.c
@@ -12,10 +12,13 @@ #include <asm/arch/secure_apb.h> #include <amlogic/store_wrapper.h> #include <amlogic/aml_efuse.h> -#ifdef CONFIG_MESON_C1 +#if defined(CONFIG_MESON_C1) || defined(CONFIG_MESON_C2) #include <asm/arch/register.h> #endif #include <time_logging.h> +#ifdef CONFIG_G_AB_SYSTEM +#include <asm/arch/secure_apb.h> +#endif #ifndef IS_FEAT_BOOT_VERIFY #define IS_FEAT_BOOT_VERIFY() 0 @@ -101,7 +104,7 @@ static int is_secure_boot_enabled(void) { -#ifdef CONFIG_MESON_C1 +#if defined(CONFIG_MESON_C1) || defined(CONFIG_MESON_C2) const unsigned long cfg10 = readl(SYSCTRL_SEC_STATUS_REG1); return ( cfg10 & (0x1 << 0) ); #else @@ -392,6 +395,9 @@ uint64_t flashReadOff = 0; unsigned secureKernelImgSz = 0; uint32_t offset = 0; +#ifdef CONFIG_G_AB_SYSTEM + uint32_t sticky_reg0_val; +#endif if (2 < argc) { loadaddr = (unsigned char*)simple_strtoul(argv[2], NULL, 16); @@ -423,7 +429,14 @@ rc = store_logic_read(partName, flashReadOff, IMG_PRELOAD_SZ, loadaddr); if (rc) { errorP("Fail to read 0x%xB from part[%s] at offset 0\n", IMG_PRELOAD_SZ, partName); +#ifdef CONFIG_G_AB_SYSTEM + /* In A/B system, force to reboot after loading failure */ + sticky_reg0_val = readl(P_AO_RTI_STICKY_REG0); + sticky_reg0_val |= 0x1 << 26; + writel(sticky_reg0_val, P_AO_RTI_STICKY_REG0); +#else return __LINE__; +#endif } flashReadOff += IMG_PRELOAD_SZ; @@ -433,7 +446,12 @@ genFmt = genimg_get_format(hdr_addr); if (IMAGE_FORMAT_ANDROID != genFmt) { errorP("Fmt unsupported!genFmt 0x%x != 0x%x\n", genFmt, IMAGE_FORMAT_ANDROID); -#ifndef CONFIG_G_AB_SYSTEM +#ifdef CONFIG_G_AB_SYSTEM + /* In A/B system, force to reboot after loading failure */ + sticky_reg0_val = readl(P_AO_RTI_STICKY_REG0); + sticky_reg0_val |= 0x1 << 26; + writel(sticky_reg0_val, P_AO_RTI_STICKY_REG0); +#else return __LINE__; #endif } else { @@ -737,6 +755,11 @@ static int do_image_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + +#ifdef CONFIG_PXP_EMULATOR + printf("\naml log : PXP image all use preload\n"); + return 0; +#else cmd_tbl_t *c; /* Strip off leading 'bmp' command argument */ @@ -751,6 +774,7 @@ cmd_usage(cmdtp); return 1; } +#endif //CONFIG_PXP_EMULATOR } U_BOOT_CMD(
diff --git a/cmd/amlogic/mmc_ts.c b/cmd/amlogic/mmc_ts.c index 5be3715..9eccc84 100644 --- a/cmd/amlogic/mmc_ts.c +++ b/cmd/amlogic/mmc_ts.c
@@ -334,6 +334,9 @@ */ size_t cur_len = strlen(p) + 1; size_t new_len = vlen ? klen + 1 + vlen + 1 : 0; + size_t move_len = 0; + + move_len = ts->cache.len - (p - ts->cache.data + cur_len) - 1; if (cur_len != new_len) { /* we need to move stuff around */ @@ -342,10 +345,14 @@ sizeof(ts->cache.data)) goto no_space; - memmove(p + new_len, p + cur_len, - ts->cache.len - (p - ts->cache.data + cur_len)); - + memmove(p + new_len, p + cur_len, move_len); + if (cur_len > new_len) { + /*Clean up the excess bytes*/ + memset(p + new_len + move_len, 0, cur_len - new_len); + } ts->cache.len = (ts->cache.len - cur_len) + new_len; + /*The last character needs to be set to 0*/ + *(ts->cache.data + ts->cache.len - 1) = '\0'; } else if (!strcmp(p + klen + 1, value)) { /* skip update if new value is the same as the old one */ res = 0;
diff --git a/cmd/bootm.c b/cmd/bootm.c old mode 100644 new mode 100755 index 8abc82a..a3bef37 --- a/cmd/bootm.c +++ b/cmd/bootm.c
@@ -25,7 +25,7 @@ #include <anti-rollback.h> #endif #include <asm/arch/secure_apb.h> -#ifdef CONFIG_MESON_C1 +#if defined(CONFIG_MESON_C1) || defined(CONFIG_MESON_C2) #include <asm/arch/register.h> #endif #include <time_logging.h> @@ -96,7 +96,7 @@ static int is_secure_boot_enabled(void) { -#ifdef CONFIG_MESON_C1 +#if defined(CONFIG_MESON_C1) || defined(CONFIG_MESON_C2) const unsigned long cfg10 = readl(SYSCTRL_SEC_STATUS_REG1); return ( cfg10 & (0x1 << 0) ); #else @@ -180,6 +180,21 @@ pr_info("GXB_IMG_SIZE: 0x%x\n", GXB_IMG_SIZE); pr_info("GXB_IMG_DEC_ALL: 0x%x\n", GXB_IMG_DEC_ALL); } + +#ifdef CONFIG_G_AB_SYSTEM + /* for unsigned boot.img, the aml_sec_boot_check don't verify it's integrity and reliability, + * check the loading status, which we stored to stick register on the loading stage(imgread.c). + * */ + if (!nRet) { + unsigned int load_fail; + load_fail = (readl(P_AO_RTI_STICKY_REG0) >> 26) & 0x1; + if (load_fail) { + writel(readl(P_AO_RTI_STICKY_REG0) & ~(1 << 26), P_AO_RTI_STICKY_REG0); + nRet = -1; + } + } +#endif + if (nRet) { pr_info("\naml log : Sig Check %d\n",nRet); @@ -233,6 +248,7 @@ argv = (char**)&argv_new; } +#ifndef CONFIG_G_AB_SYSTEM #ifdef CONFIG_CMD_BOOTCTOL_AVB char *avb_s = env_get("avb2"); if (avb_s == NULL) { @@ -280,20 +296,43 @@ if (!bootargs) { bootargs = "\0"; } - if (is_device_unlocked()) - bootstate = bootstate_o; - else - bootstate = bootstate_g; - newbootargs = malloc(strlen(bootargs) + strlen(out_data->cmdline) + strlen(bootstate) + 1 + 1 + 1); - if (!newbootargs) { - printf("failed to allocate buffer for bootarg\n"); - return -1; + + if (out_data) { + keymaster_boot_params boot_params; + const int is_dev_unlocked = is_device_unlocked(); + + boot_params.device_locked = is_dev_unlocked? 0: 1; + if (is_dev_unlocked) { + bootstate = bootstate_o; + boot_params.verified_boot_state = 2; + } + else { + bootstate = bootstate_g; + boot_params.verified_boot_state = 0; + } + memcpy(boot_params.verified_boot_key, out_data->boot_key_hash, + sizeof(boot_params.verified_boot_key)); + memcpy(boot_params.verified_boot_hash, out_data->vbmeta_digest, + sizeof(boot_params.verified_boot_hash)); + + if (set_boot_params(&boot_params) < 0) { + printf("failed to set boot params.\n"); + } + + newbootargs = malloc(strlen(bootargs) + strlen(out_data->cmdline) + strlen(bootstate) + 1 + 1 + 1); + if (!newbootargs) { + printf("failed to allocate buffer for bootarg\n"); + return -1; + } + sprintf(newbootargs, "%s %s %s", bootargs, out_data->cmdline, bootstate); + env_set("bootargs", newbootargs); + free(newbootargs); + newbootargs = NULL; + avb_slot_verify_data_free(out_data); } - sprintf(newbootargs, "%s %s %s", bootargs, out_data->cmdline, bootstate); - env_set("bootargs", newbootargs); - avb_slot_verify_data_free(out_data); } #endif//CONFIG_CMD_BOOTCTOL_AVB +#endif return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS |
diff --git a/cmd/clkmsr.c b/cmd/clkmsr.c index 493c662..f2574a2 100644 --- a/cmd/clkmsr.c +++ b/cmd/clkmsr.c
@@ -6,7 +6,8 @@ #include <common.h> #include <command.h> #include <asm/arch/clock.h> -#include <asm/arch/clk_measure.h> + +extern int clk_msr(int index); static int do_clkmsr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
diff --git a/cmd/cmd_dsprun.c b/cmd/cmd_dsprun.c index 872cccf..e82d576 100644 --- a/cmd/cmd_dsprun.c +++ b/cmd/cmd_dsprun.c
@@ -12,6 +12,8 @@ #include <asm/arch/p_register.h> #include <serial.h> +#define DSP_FW_LEN 0x800000 + void dsp_reset(uint32_t id,uint32_t reset_addr) { uint32_t StatVectorSel; @@ -29,14 +31,13 @@ pr_info("\n *P_DSP_CFG0 : ADDR_0X%p, value_0x%8x \n",P_DSP_CFG0,*P_DSP_CFG0); *P_DSP_CFG0 = (*P_DSP_CFG0 & ~(0xffff <<0)) | (0x2018 << 0) | (1<<29) | (0<<0) ; //irq_clken udelay(10); + + *P_DSP_CFG0 = *P_DSP_CFG0 | (1<<31); //Dreset deassert + *P_DSP_CFG0 = *P_DSP_CFG0 | (1<<30); //Breset deassert + udelay(20); + *P_DSP_CFG0 = *P_DSP_CFG0 & ~(1<<31); //Dreset assert - udelay(10); - // *P_DSP_CFG0 = *P_DSP_CFG0 | (1<<31); //Dreset deassert - // _udelay(10); *P_DSP_CFG0 = *P_DSP_CFG0 & ~(1<<30); //Breset - udelay(10); - // *P_DSP_CFG0 = *P_DSP_CFG0 | (1<<30); //Breset deassert - // _udelay(10); pr_info("\n *P_DSP_CFG0 : ADDR_0X%p, value_0x%8x \n",P_DSP_CFG0,*P_DSP_CFG0); } else { init_dsp(id,reset_addr, (0x1 | StatVectorSel<<1 | strobe<<2)); @@ -44,9 +45,9 @@ pr_info("\n *P_DSPB_CFG0 : ADDR_0X%p, value_0x%8x \n",P_DSPB_CFG0,*P_DSPB_CFG0); *P_DSPB_CFG0 = (*P_DSPB_CFG0 & ~(0xffff <<0)) | (0x2019 << 0) | (1<<29) | (0<<0) ; //irq_clken udelay(10); - *P_DSPB_CFG0 = *P_DSPB_CFG0 & ~(1<<31); //Dreset + writel(readl(DSPB_CFG0) & ~(1<<31), DSPB_CFG0); //Dreset udelay(10); - *P_DSPB_CFG0 = *P_DSPB_CFG0 & ~(1<<30); //Breset + writel(readl(DSPB_CFG0) & ~(1<<30), DSPB_CFG0); //Breset udelay(10); pr_info("\n *P_DSPB_CFG0 : ADDR_0X%p, value_0x%8x \n",P_DSPB_CFG0,*P_DSPB_CFG0); } @@ -56,20 +57,18 @@ { unsigned long addr; unsigned int dspid; - unsigned long dspfw_size; - + uint32_t freq_sel; int ret=0; - if (argc < 4) { - pr_err("please input dsp boot args: id, address, fw size!\n"); + if (argc <= 1) { + pr_err("plese input dsp boot args:id, addrss, clk!\n"); return CMD_RET_USAGE; } - dspid = simple_strtoul(argv[1], NULL, 16); addr = simple_strtoul(argv[2], NULL, 16); - dspfw_size = simple_strtoul(argv[3], NULL, 16); - pr_info("dsp%d boot address:0x%lx size:0x%lx", dspid, addr, dspfw_size); + pr_info("dsp%d boot \n",dspid); + pr_info("dspboot start address:0x%lx\n",addr); - flush_cache(addr, dspfw_size); + flush_cache(addr, DSP_FW_LEN); dsp_reset(dspid, addr); pr_info("dsp init over! \n"); @@ -78,41 +77,9 @@ U_BOOT_CMD( - dsprun, 4, 1, do_dsprun, + dsprun, 3, 1, do_dsprun, "load dspboot.bin from ddr address", "arg[0]: cmd\n" "arg[1]: dspid \n" "arg[2]: dspboot.bin load address!" - "arg[3]: dsp firmware size\n" ); - - -static int do_flushmemory(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - unsigned long addr; - unsigned long size; - - int ret=0; - if (argc < 3) { - pr_err("please input bootpackage args: address, fw size!\n"); - return CMD_RET_USAGE; - } - - addr = simple_strtoul(argv[1], NULL, 16); - size = simple_strtoul(argv[2], NULL, 16); - pr_info("%s address:0x%lx size:0x%lx\n", argv[0], addr, size); - flush_cache(addr, size); - return ret; -} - - -U_BOOT_CMD( - flushmemory, 3, 1, do_flushmemory, - "flush cache", - "arg[0]: cmd\n" - "arg[1]: address \n" - "arg[2]: size \n" -); - - -
diff --git a/cmd/cmd_dspset.c b/cmd/cmd_dspset.c index 15ca8e4..13d9bd7 100644 --- a/cmd/cmd_dspset.c +++ b/cmd/cmd_dspset.c
@@ -9,7 +9,7 @@ #include <asm/arch/secure_apb.h> #include <asm/arch/timer.h> #include <asm/arch/bl31_apis.h> -#include <asm/arch/p_register.h> +#include <asm/arch/register.h> #include <serial.h> @@ -74,11 +74,17 @@ } void dsp_clk_init(unsigned int dspid, uint32_t freq_sel) { - clk_util_set_dsp_clk(dspid,freq_sel); + clk_util_set_dsp_clk(dspid, freq_sel); } void dsp_power_set(unsigned int dspid, uint32_t powerflag) { - power_set_dsp(dspid,powerflag); + pr_info("power DSP, Audio \n"); + power_set_dsp(dspid, powerflag); + if (powerflag) { + power_set_ctl(PDID_ACODEC, powerflag);//audio + power_set_ctl(PDID_AUDIO, powerflag);//audio + power_set_ctl(PDID_PDM, powerflag);//pdm + } } @@ -107,8 +113,8 @@ // printf("CLKTREE_SYS_CLK_EN0 value 0x%x \n",readl(CLKTREE_SYS_CLK_EN0)); dsp_clk_init(dspid, freq_sel); - udelay(10); - dsp_power_set(dspid, powerflag) ; + udelay(20); + dsp_power_set(dspid, powerflag); pr_info("dsp init CLK, power over! \n"); return ret;
diff --git a/cmd/i2c.c b/cmd/i2c.c index 09c4ba9..ed14175 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c
@@ -1843,6 +1843,69 @@ } #endif /* defined(CONFIG_SYS_I2C) */ +#if defined(CONFIG_DM_I2C) +static int do_i2c_boot(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + uint8_t buf[5]; + const uint8_t buf_sdc[] = {0x53, 0x44, 0x43}; + const uint8_t buf_usb[] = {0x55, 0x53, 0x42}; + struct udevice *dev; + int ret, i, bus_no; + + /* + * The gpio i2c bum is 5 as default. + * It depends on the Meson i2c controller number. + * It is 5 for the current SoCs, May it be 4 in the future. + * If gpio bus number is not 5, run: i2c dev x first. + */ + if (!i2c_get_cur_bus(&dev)) + bus_no = dev->seq; + else { + bus_no = 5; + printf("Using the default BUS: 5. "); + } + + ret = i2c_get_chip_for_busnum(bus_no, 0x52, 1, &dev); + if (ret) { + printf("Cannot find i2c chip 0: %d\n", ret); + return 0; + } + + if (argc == 1) { + /* read fd/fe/ff */ + ret = dm_i2c_read(dev, 0xfd, &buf[0], 1); + ret = dm_i2c_read(dev, 0xfe, &buf[1], 1); + ret = dm_i2c_read(dev, 0xff, &buf[2], 1); + if (ret) { + printf("HDMI NO POWER or gpio wrong config"); + return ret; + } + buf[3] = '\0'; + printf("Current BOOT is %s\n", buf); + } else { + if (!strcmp(argv[1], "usb")) + strcpy((char *)buf, (const char *)buf_usb); + else if (!strcmp(argv[1], "sdc")) + strcpy((char *)buf, (const char *)buf_sdc); + else { + printf("Not support boot\n"); + return 0; + } + + printf("Setting BOOT to %s\n", argv[1]); + for (i = 0; i < 3; i++) { + ret = dm_i2c_write(dev, 0xfd + i, &buf[i], 1); + if (ret) + return ret; + udelay(1000);/* Waiting for write in*/ + } + } + + return ret; +} +#endif + /** * do_i2c_bus_speed() - Handle the "i2c speed" command-line command * @cmdtp: Command data struct pointer @@ -1965,6 +2028,7 @@ U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""), U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""), #ifdef CONFIG_DM_I2C + U_BOOT_CMD_MKENT(boot, 1, 1, do_i2c_boot, "", ""), U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""), U_BOOT_CMD_MKENT(olen, 2, 1, do_i2c_olen, "", ""), #endif @@ -2043,6 +2107,7 @@ "i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n" " to I2C; the -s option selects bulk write in a single transaction\n" #ifdef CONFIG_DM_I2C + "i2c boot [usb/sdc] - show or set current BOOT\n" "i2c flags chip [flags] - set or get chip flags\n" "i2c olen chip [offset_length] - set or get chip offset length\n" #endif
diff --git a/cmd/jtag.c b/cmd/jtag.c index 6db6c9e..582315a 100644 --- a/cmd/jtag.c +++ b/cmd/jtag.c
@@ -44,6 +44,15 @@ {JTAG_SELECT_ID(DSPB, JTAG_A, 0), "dspb", "jtag_a"}, {JTAG_SELECT_ID(DSPB, JTAG_B, 0), "dspb", "jtag_b"}, {JTAG_SELECT_ID(DSPB, SWD_A, 0), "dspb", "swd_a"}, + + {JTAG_SELECT_ID(DIF, JTAG_A, 0), "dif", "jtag_a"}, + {JTAG_SELECT_ID(DIF, JTAG_B, 0), "dif", "jtag_b"}, + + {JTAG_SELECT_ID(AOCPU, JTAG_A, 0), "aocpu", "jtag_a"}, + {JTAG_SELECT_ID(AOCPU, JTAG_B, 0), "aocpu", "jtag_b"}, + + {JTAG_SELECT_ID(AUCPU, JTAG_A, 0), "aucpu", "jtag_a"}, + {JTAG_SELECT_ID(AUCPU, JTAG_B, 0), "aucpu", "jtag_b"}, }; static int jtag_id_find(const char *core_type, const char *jtag_type) @@ -157,7 +166,7 @@ jtagon, 4, 1, do_jtagon, "enable jtag", "jtagon <core_type> <jtag_type> [cluster_type]\n" - "core_type: [ap | scp | sp | dspa | dspb]\n" + "core_type: [ap | scp | sp | dspa | dspb | dif | aocpu | aucpu]\n" "jtag_type: [jtag_a | jtag_b | swd_a | swd_b]\n" "cluster_type: [0 | 1]" );
diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index 5e35cb7..5fbf1f9 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c
@@ -139,16 +139,11 @@ #define MTDIDS_MAXLEN 128 #define MTDPARTS_MAXLEN 512 #define PARTITION_MAXLEN 16 -static char last_ids[MTDIDS_MAXLEN + 1]; -static char last_parts[MTDPARTS_MAXLEN + 1]; static char last_partition[PARTITION_MAXLEN + 1]; /* low level jffs2 cache cleaning routine */ extern void jffs2_free_cache(struct part_info *part); -/* mtdids mapping list, filled by parse_ids() */ -static struct list_head mtdids; - /* device/partition list, parse_cmdline() parses into here */ static struct list_head devices; @@ -159,10 +154,9 @@ u8 use_defaults; static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part_num); - -/* command line only routines */ -static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len); -static int device_del(struct mtd_device *dev); +#ifndef CONFIG_AML_MTDPART +/* mtdids mapping list, filled by parse_ids() */ +static struct list_head mtdids; /** * Parses a string into a number. The number stored at ptr is @@ -200,7 +194,7 @@ return ret; } -#ifndef CONFIG_AML_MTDPART + /** * Format string describing supplied size. This routine does the opposite job * to memsize_parse(). Size in bytes is converted to string and if possible @@ -299,7 +293,7 @@ index_partitions(); } - +#ifndef CONFIG_AML_MTDPART /** * Produce a mtd_info given a type and num. * @@ -323,6 +317,7 @@ return 0; } + /** * Performs sanity check for supplied flash partition. * Table of existing MTD flash devices is searched and partition device @@ -419,6 +414,7 @@ * @param part partition to validate * @return 0 if partition is valid, 1 otherwise */ + static int part_validate(struct mtdids *id, struct part_info *part) { if (part->size == SIZE_REMAINING) @@ -447,7 +443,7 @@ */ return part_validate_eraseblock(id, part); } -#ifndef CONFIG_AML_MTDPART + /** * Delete selected partition from the partition list of the specified device. * @@ -455,6 +451,7 @@ * @param part partition to delete * @return 0 on success, 1 otherwise */ +static int device_del(struct mtd_device *dev); static int part_del(struct mtd_device *dev, struct part_info *part) { u8 current_save_needed = 0; @@ -493,7 +490,7 @@ return 0; } -#endif + /** * Delete all partitions from parts head list, free memory. * @@ -575,7 +572,7 @@ index_partitions(); return 0; } -#ifndef CONFIG_AML_MTDPART + /** * Add provided partition to the partition list of a given device. * @@ -595,7 +592,6 @@ return 0; } -#endif /** * Parse one partition definition, allocate memory and return pointer to this * location in retpart. @@ -714,6 +710,7 @@ *retpart = part; return 0; } +#endif /** * Check device number to be within valid range for given device type. @@ -723,6 +720,7 @@ * @param size a pointer to the size of the mtd device (output) * @return 0 if device is valid, 1 otherwise */ +#ifndef CONFIG_AML_MTDPART static int mtd_device_validate(u8 type, u8 num, u64 *size) { struct mtd_info *mtd = NULL; @@ -757,6 +755,7 @@ return 0; } +#endif /** * If provided device exists it's partitions are deleted, device is removed @@ -765,6 +764,7 @@ * @param dev device to be deleted * @return 0 on success, 1 otherwise */ +#ifndef CONFIG_AML_MTDPART static int device_del(struct mtd_device *dev) { part_delall(&dev->parts); @@ -788,7 +788,7 @@ index_partitions(); return 0; } - +#endif /** * Search global device list and return pointer to the device of type and num * specified. @@ -835,7 +835,7 @@ else index_partitions(); } -#endif + /** * Parse device type, name and mtd-id. If syntax is ok allocate memory and * return pointer to the device structure. @@ -845,6 +845,7 @@ * @param retdev pointer to the allocated device (output) * @return 0 on success, 1 otherwise */ +static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len); static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_device **retdev) { struct mtd_device *dev; @@ -976,6 +977,7 @@ * * @return 0 on success, 1 otherwise */ +static char last_parts[MTDPARTS_MAXLEN + 1]; static int mtd_devices_init(void) { last_parts[0] = '\0'; @@ -984,7 +986,7 @@ return device_delall(&devices); } -#ifndef CONFIG_AML_MTDPART + /* * Search global mtdids list and find id of requested type and number. * @@ -1004,7 +1006,6 @@ return NULL; } -#endif /** * Search global mtdids list and find id of a requested mtd_id. * @@ -1036,6 +1037,7 @@ return NULL; } +#endif /** * Parse device id string <dev-id> := 'nand'|'nor'|'onenand'|'spi-nand'<dev-num>, @@ -1575,6 +1577,7 @@ * @param buf temporary buffer pointer MTDPARTS_MAXLEN long * @return mtdparts variable string, NULL if not found */ +#ifndef CONFIG_AML_MTDPART static const char *env_get_mtdparts(char *buf) { if (gd->flags & GD_FLG_ENV_READY) @@ -1591,7 +1594,6 @@ * @param mtdparts string specifing mtd partitions * @return 0 on success, 1 otherwise */ -#ifndef CONFIG_AML_MTDPART static int parse_mtdparts(const char *const mtdparts) { const char *p; @@ -1652,6 +1654,7 @@ * @return 0 on success, 1 otherwise */ #ifndef CONFIG_AML_MTDPART +static char last_ids[MTDIDS_MAXLEN + 1]; static int parse_mtdids(const char *const ids) { const char *p = ids;
diff --git a/cmd/saradc.c b/cmd/saradc.c index fb45699..04fc0c7 100644 --- a/cmd/saradc.c +++ b/cmd/saradc.c
@@ -10,6 +10,19 @@ #define ENV_SARADC_VALUE "saradc_val" +struct meson_saradc_mode { + unsigned int sample_mode; + const char *mode_name; +}; + +static const struct meson_saradc_mode mode_table[] = { + {ADC_MODE_AVERAGE, "average"}, //default mode + {ADC_MODE_AVERAGE, "average"}, + {ADC_MODE_HIGH_PRECISION, "high precision"}, + {ADC_MODE_HIGH_RESOLUTION, "high resolution"}, + {ADC_MODE_DECIM_FILTER, "decim filter"} +}; + static const char * const ch7_voltage[] = { "gnd", "vdd/4", @@ -19,13 +32,24 @@ }; static int current_channel = -1; +static unsigned int current_mode; static int do_saradc_open(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + struct udevice *dev; int channel; + int mode; + int ret; + char *endp; + + ret = uclass_get_device_by_name(UCLASS_ADC, "adc", &dev); + if (ret) + return ret; channel = simple_strtoul(argv[1], NULL, 10); + mode = simple_strtoul(argv[2], &endp, 10); + if ((channel < 0) || (channel >= MESON_SARADC_CH_MAX)) { pr_err("No such channel(%d) in SARADC! open failed!\n", @@ -33,8 +57,24 @@ return -1; } + if ((mode < 0) || (mode >= sizeof(mode_table)/sizeof(mode_table[0])) || + (endp && !mode)) { + pr_err("No such mode(%d) in SARADC! open failed!\n", mode); + return -1; + } + + ret = adc_set_mode(dev, channel, mode_table[mode].sample_mode); + if (ret) { + pr_err("current platform does not support [%s] mode\n", + mode_table[mode].mode_name); + return ret; + } + + current_mode = mode_table[mode].sample_mode; current_channel = channel; + printf("SARADC mode is %s\n", mode_table[mode].mode_name); + return 0; } @@ -60,7 +100,8 @@ return -EINVAL; }; - ret = adc_channel_single_shot("adc", current_channel, &val); + ret = adc_channel_single_shot_mode("adc", current_mode, + current_channel, &val); if (ret) return ret; @@ -120,7 +161,8 @@ unsigned int val; int ret; - ret = adc_channel_single_shot("adc", current_channel, &val); + ret = adc_channel_single_shot_mode("adc", current_mode, + current_channel, &val); if (ret) return ret; @@ -145,7 +187,7 @@ } static cmd_tbl_t cmd_saradc_sub[] = { - U_BOOT_CMD_MKENT(open, 2, 0, do_saradc_open, "", ""), + U_BOOT_CMD_MKENT(open, 3, 0, do_saradc_open, "", ""), U_BOOT_CMD_MKENT(close, 1, 0, do_saradc_close, "", ""), U_BOOT_CMD_MKENT(getval, 1, 0, do_saradc_getval, "", ""), U_BOOT_CMD_MKENT(test, 1, 0, do_saradc_test, "", ""), @@ -172,7 +214,8 @@ U_BOOT_CMD( saradc, CONFIG_SYS_MAXARGS, 0, do_saradc, "saradc sub-system", - "saradc open <channel> - open a SARADC channel\n" + "saradc open <channel> <mode> - open a SARADC channel\n\ + mode: 1:average 2:high precision 3:high resolution 4:decim filter\n" "saradc close - close the SARADC\n" "saradc getval - get the value in current channel\n" "saradc test - test the SARADC by channel-7\n"
diff --git a/cmd/sf.c b/cmd/sf.c index f53b2dc..aea0022 100644 --- a/cmd/sf.c +++ b/cmd/sf.c
@@ -321,7 +321,6 @@ static int do_spi_xip(int argc, char * const argv[]) { unsigned long addr; - void *buf; char *endp; int ret = 0; int (*xip_entrance)(int, char **); @@ -330,7 +329,7 @@ addr = simple_strtoul(argv[1], &endp, 16); if (*argv[1] == 0 || *endp != 0) return -1; - printf("addr 0x%x\n", addr); + printf("addr 0x%lu\n", addr); } ret = spifc_xip_prepare();
diff --git a/cmd/storage.c b/cmd/storage.c index 7007256..aaba73c 100644 --- a/cmd/storage.c +++ b/cmd/storage.c
@@ -6,6 +6,11 @@ #include <amlogic/storage.h> #include <div64.h> #include <linux/math64.h> +#include <amlogic/cpu_id.h> +#include <asm/arch/register.h> +#include <asm/arch/bl31_apis.h> + +#include <asm/arch/secure_apb.h> #undef pr_info #define pr_info printf @@ -20,6 +25,11 @@ extern int spi_nand_probe(u32 init_flag); #endif +#ifdef CONFIG_MTD_SPI_NAND +extern int spi_nand_pre(void); +extern int spi_nand_probe(u32 init_flag); +#endif + #ifdef CONFIG_AML_NAND extern int amlnf_pre(void); extern int amlnf_probe(u32 init_flag); @@ -44,6 +54,22 @@ static struct storage_t *current; static struct device_node_t device_list[] = { +#ifdef CONFIG_MESON_NFC + {BOOT_NAND_MTD, "mtd", nand_pre, nand_probe}, +#endif +#ifdef CONFIG_AML_NAND + {BOOT_NAND_NFTL, "nftl", amlnf_pre, amlnf_probe}, +#endif +#ifdef CONFIG_SPI_NAND + /* old drivers will be removed later */ + {BOOT_SNAND, "spi-nand", spi_nand_pre, spi_nand_probe}, +#endif +#ifdef CONFIG_MTD_SPI_NAND + {BOOT_SNAND, "spi-nand", spi_nand_pre, spi_nand_probe}, +#endif +#if CONFIG_SPI_FLASH + {BOOT_SNOR, "spi-nor", spi_nor_pre, spi_nor_probe}, +#endif #if 0 {BOOT_SD, "sd", sdcard_pre, sdcard_probe}, #endif @@ -52,19 +78,6 @@ {BOOT_EMMC, "emmc", emmc_pre, emmc_probe}, #endif -#ifdef CONFIG_MESON_NFC - {BOOT_NAND_MTD, "mtd", nand_pre, nand_probe}, -#endif - -#ifdef CONFIG_AML_NAND - {BOOT_NAND_NFTL, "nftl", amlnf_pre, amlnf_probe}, -#endif -#ifdef CONFIG_SPI_NAND - {BOOT_SNAND, "spi-nand", spi_nand_pre, spi_nand_probe}, -#endif -#if CONFIG_SPI_FLASH - {BOOT_SNOR, "spi-nor", spi_nor_pre, spi_nor_probe} -#endif }; int store_register(struct storage_t *store_dev) @@ -115,34 +128,230 @@ } } -u8 store_device_valid(enum boot_type_e type) -{ - struct list_head *entry; - struct storage_t *dev; +boot_area_entry_t general_boot_part_entry[MAX_BOOT_AREA_ENTRIES] = { + {BAE_BB1ST, BOOT_AREA_BB1ST, 0, BOOT_FIRST_BLOB_SIZE}, + {BAE_BL2E, BOOT_AREA_BL2E, 0, 0x40000}, + {BAE_BL2X, BOOT_AREA_BL2X, 0, 0x40000}, + {BAE_DDRFIP, BOOT_AREA_DDRFIP, 0, 0x40000}, + {BAE_DEVFIP, BOOT_AREA_DEVFIP, 0, 0x300000}, +}; - if (!current) - return 0; - if (current->type == type) - return 1; - list_for_each(entry, ¤t->list) { - dev = list_entry(entry, struct storage_t, list); - if (dev->type == type) - return 1; +struct boot_layout general_boot_layout = {.boot_entry = general_boot_part_entry}; +struct storage_startup_parameter g_ssp; +struct storage_bl *g_storage = NULL; + +static void storage_boot_layout_debug_info( + struct boot_layout *boot_layout) +{ + boot_area_entry_t *boot_entry = boot_layout->boot_entry; + int i; + + printf("boot area list: \n"); + for (i = 0; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i].size; i++) { + printf("%10s ", boot_entry[i].name); + printf("%10llx ", boot_entry[i].offset); + printf("%10llx\n", boot_entry[i].size); } +} + +/* use STORAGE_ROUND_UP, y must be power of 2 */ +#define STORAGE_ROUND_UP_IF_UNALIGN(x, y) ((x) = (((x) + (y) - 1) & (~(y - 1)))) +#define NAND_RSV_OFFSET 1024 +#define ALIGN_SIZE (4096) +int storage_boot_layout_general_setting( + struct boot_layout *boot_layout) +{ + struct storage_startup_parameter *ssp = &g_ssp; + boot_area_entry_t *boot_entry = NULL; + uint64_t align_size, reserved_size = 0; + uint8_t i, cal_copy = ssp->boot_bakups; + + boot_entry = boot_layout->boot_entry; + + align_size = ALIGN_SIZE; + if ((ssp->boot_device == BOOT_NAND_NFTL) || + (ssp->boot_device == BOOT_NAND_MTD)) { + reserved_size = ssp->sip.nsp.layout_reserve_size; + align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.nsp.page_size); + } else if (ssp->boot_device == BOOT_SNAND) { + reserved_size = ssp->sip.snasp.layout_reserve_size; + align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.snasp.pagesize); + } else if (ssp->boot_device == BOOT_EMMC) { + ssp->boot_entry[0].offset = boot_entry[0].offset += + BL2_CORE_BASE_OFFSET_EMMC; + cal_copy = 1; + } + STORAGE_ROUND_UP_IF_UNALIGN(boot_entry[0].size, align_size); + ssp->boot_entry[0].size = boot_entry[0].size; + if ((ssp->boot_device == BOOT_NAND_NFTL) || + (ssp->boot_device == BOOT_NAND_MTD)) + align_size = ssp->sip.nsp.block_size; + else if (ssp->boot_device == BOOT_SNAND) + align_size = ssp->sip.snasp.pagesize * + ssp->sip.snasp.pages_per_eraseblock; + for (i = 1; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i - 1].size; i++) { + STORAGE_ROUND_UP_IF_UNALIGN(boot_entry[i].size, align_size); + boot_entry[i].offset = boot_entry[i-1].offset + + boot_entry[i-1].size * cal_copy + reserved_size; + reserved_size = 0; + ssp->boot_entry[i].size = boot_entry[i].size; + ssp->boot_entry[i].offset = boot_entry[i].offset; + } + return 0; } +uint8_t emmc_boot_seqs_tbl[8][2] = { + {0, 3}, {0, 2}, {0, 3}, {0, 1}, + {1, 2}, {1, 1}, {2, 1}, {0, 0} + }; + +static int _get_emmc_boot_seqs(void) +{ + uint8_t ebcfg = 0; + if (IS_FEAT_DIS_EMMC_USER()) + ebcfg |= (1<<2); + if (IS_FEAT_DIS_EMMC_BOOT_0()) + ebcfg |= (1<<1); + if (IS_FEAT_DIS_EMMC_BOOT_1()) + ebcfg |= (1<<0); + + return ebcfg; +} + +static int storage_get_emmc_boot_seqs(void) +{ + return emmc_boot_seqs_tbl[_get_emmc_boot_seqs()][1];; +} + +static int storage_get_emmc_boot_start(void) +{ + return emmc_boot_seqs_tbl[_get_emmc_boot_seqs()][0];; +} + +#define NAND_RSV_BLOCK_NUM 48 +#define NSP_PAGE0_DISABLE 1 +static int storage_get_and_parse_ssp(void) +{ + struct storage_startup_parameter *ssp; + union storage_independent_parameter *sip; + + ssp = &g_ssp; + memset(ssp, 0, BL2E_STORAGE_PARAM_SIZE); + sip = &ssp->sip; + + ssp->boot_device = current->type; + //ssp->boot_seq = get_bootcopy(); + + switch (ssp->boot_device) { + case BOOT_EMMC: + //ssp->sip.esp.setup.d32 = readl(SYSCTRL_SEC_STATUS_REG5); + ssp->boot_bakups = storage_get_emmc_boot_seqs(); + break; + case BOOT_SNOR: + if (IS_FEAT_EN_4BL2_SNOR()) + ssp->boot_bakups = 4; + else if (IS_FEAT_DIS_NBL2_SNOR()) + ssp->boot_bakups = 1; + else + ssp->boot_bakups = 2; + break; + case BOOT_SNAND: + if (IS_FEAT_EN_8BL2_SNAND()) + ssp->boot_bakups = 8; + else if (IS_FEAT_DIS_NBL2_SNAND()) + ssp->boot_bakups = 1; + else + ssp->boot_bakups = 4; + + sip->snasp.pagesize = 2048; + sip->snasp.pages_per_eraseblock = 64; + sip->snasp.eraseblocks_per_lun = 1024; + sip->snasp.planes_per_lun = 1; + sip->snasp.luns_per_target = 1; + sip->snasp.ntargets = 1; + /* TODO caculate it by reserve filed from startup parameter */ + sip->snasp.layout_reserve_size = NAND_RSV_BLOCK_NUM * sip->snasp.pagesize + * sip->snasp.pages_per_eraseblock; + break; + case BOOT_NAND_NFTL: + case BOOT_NAND_MTD: + if (IS_FEAT_DIS_8BL2_NAND()) + ssp->boot_bakups = 4; + if (IS_FEAT_DIS_NBL2_NAND()) + ssp->boot_bakups = 1; + ssp->boot_bakups = 8; //FIXIT?? efuse do not work now. + sip->nsp.page_size = 0x1000; /*TODO get it from startup parameter */ + sip->nsp.block_size = 0x80000; + sip->nsp.pages_per_block = 64; + sip->nsp.layout_reserve_size = NAND_RSV_BLOCK_NUM * sip->nsp.block_size; /*TODO caculate it by reserve filed from startup parameter */ + /*TODO get it from startup parameter */ + sip->nsp.setup_data = (2 << 20) | \ + (0 << 19) | \ + (1 << 17) | \ + (1 << 14) | \ + (0 << 13) | \ + (64 << 6) | \ + (8 << 0); + sip->nsp.page0_disable = NSP_PAGE0_DISABLE; + break; + default: + /* do nothing. */ + break; + } + if (ssp->boot_seq >= ssp->boot_bakups) + return -1; + + printf("boot_device:%d\n", ssp->boot_device); + printf("boot_seq:%d\n", ssp->boot_seq); + printf("boot_bakups:%d\n", ssp->boot_bakups); + + return 0; +} + +int storage_post_init(void) +{ + int ret = -1; + + ret = storage_get_and_parse_ssp(); + if (ret < 0) + return -1; + storage_boot_layout_general_setting(&general_boot_layout); + storage_boot_layout_debug_info(&general_boot_layout); + + return ret; +} + int store_init(u32 init_flag) { - int i, ret; - int record = 0; + cpu_id_t cpu_id = get_cpu_id(); + int i, ret = 0; + u8 record = 0; - for (i = 0; i < ARRAY_SIZE(device_list); i++) + /*1. pre scan*/ + for (i = 0; i < ARRAY_SIZE(device_list); i++) { if (!device_list[i].pre()) { - ret = device_list[i].probe(init_flag); - if (!ret) - record |= device_list[i].index; + record |= BIT(i); } + } + + if (!record) { + pr_info("No Valid storage device\n"); + return record; + } + + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) + storage_post_init(); + + /*2. Enter the probe of the valid device*/ + for (i = 0; i < ARRAY_SIZE(device_list); i++) { + if (record & BIT(i)) { + ret = device_list[i].probe(init_flag); + if (ret) + pr_info("the 0x%x storage device probe failed\n", + device_list[i].index); + } + } return record; } @@ -263,6 +472,69 @@ return store->get_copies(name); } + +#ifndef SYSCTRL_SEC_STATUS_REG2 +static u32 fake_reg = 0; +#define SYSCTRL_SEC_STATUS_REG2 (&fake_reg) +#endif +u8 store_boot_copy_start(void) +{ + struct storage_t *store = store_get_current(); + cpu_id_t cpu_id = get_cpu_id(); + + if (!store) { + pr_info("%s %d please init storage device first\n", + __func__, __LINE__); + return 0; + } + if (store->type != BOOT_EMMC) + return 0; + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) + return storage_get_emmc_boot_start(); + return 0; +} + +u8 store_bootup_bootidx(const char *name) +{ + cpu_id_t cpu_id = get_cpu_id(); + u8 bl2_idx = 0, fip_idx = 0; + u32 val = 0; + + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { + bl2_idx = readl(SYSCTRL_SEC_STATUS_REG2) & 0xF; + //TODO: fixme after robust devfip is finished. + fip_idx = bl2_idx; + } else { + /* accroding to the: + commit 975b4acbcfa686601999d56843471d98e9c0a2cd + storage: robust boot: record bootlog in SEC_AO_SEC_GP_CFG2 [1/2] + PD#SWPL-4850 + ... + record the bootup bl2/fip into SEC_AO_SEC_GP_CFG2 + bit[27-25] bl2 + bit[24-22] fip + */ + val = readl(SEC_AO_SEC_GP_CFG2); + bl2_idx = (val >> 25) & 0x7; + fip_idx = (val >> 22) & 0x7; + } + if (!strncmp(name, "bl2", sizeof("bl2")) || + !strncmp(name, "spl", sizeof("spl"))) + return bl2_idx; + else + return fip_idx; +} + +void store_restore_bootidx(void) +{ + cpu_id_t cpu_id = get_cpu_id(); + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { + extern void aml_set_bootsequence(uint32_t val); + aml_set_bootsequence(0x55); + } + return; +} + u64 store_boot_copy_size(const char *name) { struct storage_t *store = store_get_current(); @@ -459,7 +731,7 @@ int flag, int argc, char * const argv[]) { struct storage_t *store_dev; - int i, partitions = 0; + int i = 0, partitions = 0; int ret = 0; char name[16]; @@ -545,7 +817,8 @@ time = get_timer(time); if (size != 0) - printf("%llu bytes ", (long long unsigned)size); + printf("%lu bytes ", size); + printf("erased in %lu ms", time); if ((time > 0) && (size != 0)) { puts(" ("); @@ -593,6 +866,7 @@ if (size != 0) pr_notice("%llu bytes ", (long long unsigned)size); + pr_notice("read in %lu ms", time); if ((time > 0) && (size != 0)) { pr_notice(" ("); @@ -604,6 +878,82 @@ return ret; } +static int name2index(struct boot_layout *boot_layout, const char *img) +{ + boot_area_entry_t *boot_entry = NULL; + int i; + + boot_entry = boot_layout->boot_entry; + for (i = 1; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i].size; i++) { + if (!strncmp(img, boot_entry[i].name, strlen(boot_entry[i].name))) + return i; + } + + return -1; +} + +static int do_store_write_bl2img(cmd_tbl_t *cmdtp, + int flag, int argc, char * const argv[]) +{ + struct storage_t *store = store_get_current(); + unsigned long offset, addr; + size_t size, size_src; + char *name = NULL; + int ret = -1, index; + struct boot_layout *boot_layout = &general_boot_layout; + + if (!store) { + pr_info("%s %d please init your storage device first!\n", + __func__, __LINE__); + return CMD_RET_FAILURE; + } + + addr = simple_strtoul(argv[2], NULL, 16); + name = argv[3]; + size = simple_strtoul(argv[4], NULL, 16); + + index = name2index(&general_boot_layout, name); + offset = boot_layout->boot_entry[index].offset; + size_src = boot_layout->boot_entry[index].size; + printf("[%s] offset:0x%lx, index:%d\n", name, offset, index); + + if (size_src != size) + printf("new img size:0x%lx != img src:0x%lx\n", size, size_src); + + ret = store->boot_write(name, offset, size, (u_char *)addr); + + return ret; +} + +int store_write_bl2img(void* addr, const char *name, size_t size) +{ + struct storage_t *store = store_get_current(); + unsigned long offset; + size_t size_src; + int ret = -1, index; + struct boot_layout *boot_layout = &general_boot_layout; + + if (!store) { + pr_info("%s %d please init your storage device first!\n", + __func__, __LINE__); + return CMD_RET_FAILURE; + } + + index = name2index(&general_boot_layout, name); + offset = boot_layout->boot_entry[index].offset; + size_src = boot_layout->boot_entry[index].size; + printf("[%s] offset:0x%lx, index:%d\n", name, offset, index); + + if (size_src != size) + printf("new img size:0x%zx != img src:0x%zx\n", size, size_src); + + ret = store->boot_write(name, offset, size, (u_char *)addr); + if (size != 0) + printf("[%s][%d]%lx bytes\n", __func__, __LINE__, size); + + return ret; +} + static int do_store_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -639,7 +989,8 @@ time = get_timer(time); if (size != 0) - printf("%llu bytes ", (long long unsigned)size); + printf("%lu bytes ", size); + printf("write in %lu ms", time); if ((time > 0) && (size != 0)) { puts(" ("); @@ -786,6 +1137,7 @@ U_BOOT_CMD_MKENT(erase, 5, 0, do_store_erase, "", ""), U_BOOT_CMD_MKENT(read, 6, 0, do_store_read, "", ""), U_BOOT_CMD_MKENT(write, 7, 0, do_store_write, "", ""), + U_BOOT_CMD_MKENT(write_bl2img, 5, 0, do_store_write_bl2img, "", ""), U_BOOT_CMD_MKENT(boot_read, 6, 0, do_store_boot_read, "", ""), U_BOOT_CMD_MKENT(boot_write, 6, 0, do_store_boot_write, "", ""), U_BOOT_CMD_MKENT(boot_erase, 4, 0, do_store_boot_erase, "", ""),
diff --git a/cmd/usb.c b/cmd/usb.c index 0ccb1b5..961631b 100644 --- a/cmd/usb.c +++ b/cmd/usb.c
@@ -730,6 +730,24 @@ #endif /* CONFIG_USB_STORAGE */ } +int do_usb_detect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + if (argc >= 2) { + return usb_aml_detect_operation(argc, argv); + } + return 0; +} + +U_BOOT_CMD( + musb, 5, 1, do_usb_detect, + "using for get USB information", + "info ----default operation to get dts information\n" + "musb disable ----disable USB PHY\n" +); + + U_BOOT_CMD( usb, 5, 1, do_usb, "USB sub-system",
diff --git a/cmd/watchdog.c b/cmd/watchdog.c index ca245d6..317f7d4 100644 --- a/cmd/watchdog.c +++ b/cmd/watchdog.c
@@ -41,7 +41,7 @@ return CMD_RET_USAGE; /* enable the watchdog and set timeout */ - wdt_start(watchdog_devp, timeout, 0); + wdt_start(watchdog_devp, timeout * 1000, 0); wdt_reset(watchdog_devp); return CMD_RET_SUCCESS;
diff --git a/common/Makefile b/common/Makefile index d64795f..a27b419 100644 --- a/common/Makefile +++ b/common/Makefile
@@ -138,3 +138,13 @@ obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_AVB_VERIFY) += avb_verify.o +obj-$(CONFIG_MDUMP_COMPRESS) += ramdump.o + +ifeq ($(CONFIG_LED_AW2026), y) +obj-y += leds-aw2026.o +else ifeq ($(CONFIG_LED_AW210XX), y) +obj-y += leds-aw210xx.o +else +obj-y += led.o +endif +obj-${CONFIG_SCHUMACHER_SSR} += ssr.o
diff --git a/common/aml_dt.c b/common/aml_dt.c index 0f6712d..8af0c79 100644 --- a/common/aml_dt.c +++ b/common/aml_dt.c
@@ -10,6 +10,7 @@ #include <malloc.h> #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> +#include <partition_table.h> //#define AML_DT_DEBUG #ifdef AML_DT_DEBUG @@ -18,6 +19,333 @@ #define dbg_printf(...) ((void)0) #endif +#define AML_MULTI_DTB_API_NEW +//#define AML_MULTI_DTB_CHECK_CMD //command for multi-dtb test + +#ifdef AML_MULTI_DTB_API_NEW + +/*for multi-dtb gzip buffer*/ +#define GUNZIP_BUF_SIZE (1<<20) /*1MB is enough?*/ + +/*magic for multi-dtb*/ +#define MAGIC_GZIP_MASK (0x0000FFFF) +#define MAGIC_GZIP_ID (0x00008B1F) +#define IS_GZIP_PACKED(nMagic) (MAGIC_GZIP_ID == (MAGIC_GZIP_MASK & nMagic)) +#define MAGIC_DTB_SGL_ID (0xedfe0dd0) +#define MAGIC_DTB_MLT_ID (0x5f4c4d41) + +/*amlogic multi-dtb version*/ +#define AML_MUL_DTB_VER_1 (1) +#define AML_MUL_DTB_VER_2 (2) + +/*max char for dtb name, fixed to soc_package_board format*/ +#define AML_MAX_DTB_NAME_SIZE (128) +#define AML_DTB_TOKEN_MAX_COUNT (AML_MAX_DTB_NAME_SIZE>>1) + +typedef struct{ + unsigned int nMagic; + unsigned int nVersion; + unsigned int nDTBCount; +}st_dtb_hdr_t,*p_st_dtb_hdr_t; + +/*v1,v2 multi-dtb only support max to 3 tokens for each DTB name*/ +#define MULTI_DTB_TOKEN_MAX_COUNT (3) +#define MULTI_DTB_TOKEN_UNIT_SIZE_V1 (4) //v1 support 4bytes for each token +#define MULTI_DTB_TOKEN_UNIT_SIZE_V2 (16) //v2 support 16bytes for each token + +/*v1 multi-dtb*/ +typedef struct{ + unsigned char szToken[MULTI_DTB_TOKEN_MAX_COUNT][MULTI_DTB_TOKEN_UNIT_SIZE_V1]; + int nDTBOffset; + int nDTBIMGSize; +}st_dtb_token_v1_t,*p_st_dtb_token_v1_t; + +typedef struct{ + st_dtb_hdr_t hdr; + st_dtb_token_v1_t dtb[1]; +}st_dtb_v1_t,*p_st_dtb_v1_t; + + +/*v2 multi-dtb*/ +typedef struct{ + unsigned char szToken[MULTI_DTB_TOKEN_MAX_COUNT][MULTI_DTB_TOKEN_UNIT_SIZE_V2]; + int nDTBOffset; + int nDTBIMGSize; +}st_dtb_token_v2_t,*p_st_dtb_token_v2_t; + +typedef struct{ + st_dtb_hdr_t hdr; + st_dtb_token_v2_t dtb[1]; +}st_dtb_v2_t,*p_st_dtb_v2_t; + + +/*to get the valid DTB index with matched DTB name*/ +static int get_dtb_index(const char aml_dt_buf[128],unsigned long fdt_addr) +{ + int nReturn = -1; + + if (!aml_dt_buf) + goto exit; + + p_st_dtb_hdr_t pDTBHdr = (p_st_dtb_hdr_t)fdt_addr; + char sz_aml_dt_msb[10][MULTI_DTB_TOKEN_UNIT_SIZE_V2]; + memset(sz_aml_dt_msb,0,sizeof(sz_aml_dt_msb)); + + /* split aml_dt with token '_', e.g "tm2-revb_t962x3_ab301" */ + //printf(" aml_dt : %s\n",aml_dt_buf); + + char *tokens[AML_DTB_TOKEN_MAX_COUNT]; + char sz_temp[AML_MAX_DTB_NAME_SIZE+4]; + memset(tokens,0,sizeof(tokens)); + memset(sz_temp,0,sizeof(sz_temp)); + strncpy(sz_temp,aml_dt_buf,128); + int i,j; + int nLen = strlen(sz_temp); + sz_temp[nLen]='_'; + sz_temp[nLen+1]='\0'; + nLen +=1; + tokens[0]=sz_temp; + for (i = 1; i < sizeof(tokens)/sizeof(tokens[0]); i++) + { + tokens[i] = strstr(tokens[i-1],"_"); + if (!tokens[i]) + break; + + *tokens[i]='\0'; + + tokens[i]=tokens[i]+1; + + if (!(*tokens[i])) + { + tokens[i] = 0; + break; + } + } + + //for (i=0;i<10 && tokens[i];++i) + // printf("token-%d:%s\n",i,tokens[i]); + + int nTokenLen = 0; + + switch (pDTBHdr->nVersion) + { + case AML_MUL_DTB_VER_1: + { + nTokenLen = MULTI_DTB_TOKEN_UNIT_SIZE_V1; + }break; + case AML_MUL_DTB_VER_2: + { + nTokenLen = MULTI_DTB_TOKEN_UNIT_SIZE_V2; + }break; + default: goto exit; break; + } + + + for (i = 0;i<MULTI_DTB_TOKEN_MAX_COUNT;++i) + { + if (tokens[i]) + { + char *pbyswap = (char*)sz_aml_dt_msb+(nTokenLen*i); + strcpy(pbyswap,tokens[i]); + unsigned int nValSwap; + for (j = 0;j< nTokenLen;j+=4) + { + int m; + /*swap byte order with unit@4bytes*/ + nValSwap = *(unsigned int *)(pbyswap+j); + for (m=0;m<4;m++) + pbyswap[j+m] = (nValSwap >> ((3-m)<<3)) & 0xFF; + + /*replace 0 with 0x20*/ + for (m=0;m<MULTI_DTB_TOKEN_UNIT_SIZE_V2;++m) + if (0 == pbyswap[m]) + pbyswap[m]=0x20; + } + } + else + break; + } + + switch (pDTBHdr->nVersion) + { + case AML_MUL_DTB_VER_1: + { + p_st_dtb_v1_t pDTB_V1 = (p_st_dtb_v1_t)fdt_addr; + for (i=0;i< pDTB_V1->hdr.nDTBCount;++i) + { + if (!memcmp(pDTB_V1->dtb[i].szToken,sz_aml_dt_msb, + MULTI_DTB_TOKEN_MAX_COUNT*nTokenLen)) + { + nReturn = i; + break; + } + } + + }break; + case AML_MUL_DTB_VER_2: + { + p_st_dtb_v2_t pDTB_V2 = (p_st_dtb_v2_t)fdt_addr; + for (i=0;i< pDTB_V2->hdr.nDTBCount;++i) + { + if (!memcmp(pDTB_V2->dtb[i].szToken,sz_aml_dt_msb, + MULTI_DTB_TOKEN_MAX_COUNT*nTokenLen)) + { + nReturn = i; + break; + } + } + + }break; + default: goto exit; break; + } + +exit: + + return nReturn; + +} + +unsigned long __attribute__((unused)) get_multi_dt_entry(unsigned long fdt_addr) +{ + unsigned long lReturn = 0; //return buffer for valid DTB; + void * gzip_buf = NULL; + unsigned long pInputFDT = fdt_addr; + p_st_dtb_hdr_t pDTBHdr = (p_st_dtb_hdr_t)pInputFDT; + unsigned long unzip_size = GUNZIP_BUF_SIZE; + + printf(" Amlogic Multi-DTB tool\n"); + + /* first check the blob header, support GZIP format */ + if ( IS_GZIP_PACKED(pDTBHdr->nMagic)) + { + printf(" GZIP format, decompress...\n"); + gzip_buf = malloc(GUNZIP_BUF_SIZE); + if (!gzip_buf) + { + printf(" ERROR! fail to allocate memory for GUNZIP...\n"); + goto exit; + } + memset(gzip_buf, 0, GUNZIP_BUF_SIZE); + if (gunzip(gzip_buf, GUNZIP_BUF_SIZE, (void *)pInputFDT, &unzip_size) < 0) + { + printf(" ERROR! GUNZIP process fail...\n"); + goto exit; + } + if (unzip_size > GUNZIP_BUF_SIZE) + { + printf(" ERROR! GUNZIP overflow...\n"); + goto exit; + } + //memcpy((void*)fdt_addr,gzip_buf,unzip_size); + pInputFDT = (unsigned long)gzip_buf; + pDTBHdr = (p_st_dtb_hdr_t)pInputFDT; + } + + + switch (pDTBHdr->nMagic) + { + case MAGIC_DTB_SGL_ID: + { + printf(" Single DTB detected\n"); + + if (fdt_addr != (unsigned long)pInputFDT) //in case of GZIP single DTB + memcpy((void*)fdt_addr,(void*)pInputFDT,unzip_size); + + lReturn = fdt_addr; + + }break; + case MAGIC_DTB_MLT_ID: + { + printf(" Multi DTB detected.\n"); + printf(" Multi DTB tool version: v%d.\n", pDTBHdr->nVersion); + printf(" Support %d DTBS.\n", pDTBHdr->nDTBCount); + + + /* check and set aml_dt */ + char aml_dt_buf[AML_MAX_DTB_NAME_SIZE+4]; + memset(aml_dt_buf, 0, sizeof(aml_dt_buf)); + + /* update 2016.07.27, checkhw and setenv everytime, + or else aml_dt will set only once if it is reserved */ + extern int checkhw(char * name); +#if 1 + if (checkhw(aml_dt_buf) < 0 || strlen(aml_dt_buf) <= 0) + { + printf(" Get env aml_dt failed!\n"); + goto exit; + } +#else + char *aml_dt = getenv(AML_DT_UBOOT_ENV); + /* if aml_dt not exist or env not ready, get correct dtb by name */ + if (NULL == aml_dt) + checkhw(aml_dt_buf); + else + memcpy(aml_dt_buf, aml_dt, + (strlen(aml_dt)>AML_MAX_DTB_NAME_SIZE?AML_MAX_DTB_NAME_SIZE:(strlen(aml_dt)+1))); +#endif + + int dtb_match_num = get_dtb_index(aml_dt_buf,(unsigned long)pInputFDT); + + /*check valid dtb index*/ + if (dtb_match_num < 0 || dtb_match_num >= pDTBHdr->nDTBCount) + { + printf(" NOT found matched DTB for \"%s\"\n",aml_dt_buf); + goto exit; + } + + printf(" Found DTB for \"%s\"\n",aml_dt_buf); + + switch (pDTBHdr->nVersion) + { + case AML_MUL_DTB_VER_1: + { + p_st_dtb_v1_t pDTB_V1 = (p_st_dtb_v1_t)pInputFDT; + lReturn = pDTB_V1->dtb[dtb_match_num].nDTBOffset + pInputFDT; + + if (pInputFDT != fdt_addr) + { + memcpy((void*)fdt_addr, (void*)lReturn,pDTB_V1->dtb[dtb_match_num].nDTBIMGSize); + lReturn = fdt_addr; + } + + }break; + case AML_MUL_DTB_VER_2: + { + p_st_dtb_v2_t pDTB_V2 = (p_st_dtb_v2_t)pInputFDT; + lReturn = pDTB_V2->dtb[dtb_match_num].nDTBOffset + pInputFDT; + + if (pInputFDT != fdt_addr) + { + memcpy((void*)fdt_addr, (void*)lReturn,pDTB_V2->dtb[dtb_match_num].nDTBIMGSize); + lReturn = fdt_addr; + } + + }break; + default: + { + printf(" Invalid Multi-DTB Version [%d]!\n", + pDTBHdr->nVersion); + goto exit; + }break; + } + + }break; + default: goto exit; break; + } + +exit: + + if (gzip_buf) + { + free(gzip_buf); + gzip_buf = 0; + } + + return lReturn; +} + +#else //#ifdef AML_MULTI_DTB_API_NEW + #define AML_DT_IND_LENGTH_V1 4 /*fixed*/ #define AML_DT_IND_LENGTH_V2 16 /*fixed*/ @@ -40,7 +368,7 @@ #define IS_GZIP_FORMAT(data) ((data & (0x0000FFFF)) == (0x00008B1F)) #define GUNZIP_BUF_SIZE (0x500000) /* 5MB */ -#define DTB_MAX_SIZE (0x40000) /* 256KB */ +#define DTB_MAX_SIZE (AML_DTB_IMG_MAX_SZ) //#define readl(addr) (*(volatile unsigned int*)(addr)) extern int checkhw(char * name); @@ -74,7 +402,6 @@ dbg_printf(" DBG: fdt_addr: 0x%x\n", (unsigned int)fdt_addr); dbg_printf(" DBG: dt_magic: 0x%x\n", (unsigned int)dt_magic); - dbg_printf(" DBG: gzip_format: %d\n", gzip_format); /*printf(" Process device tree. dt magic: %x\n", dt_magic);*/ if (dt_magic == DT_HEADER_MAGIC) {/*normal dtb*/ @@ -93,6 +420,7 @@ int i = 0; char *aml_dt_buf; aml_dt_buf = (char *)malloc(sizeof(char)*64); + printf("Multi dtb malloc aml_dt_buf addr = %p\n", aml_dt_buf); memset(aml_dt_buf, 0, sizeof(aml_dt_buf)); /* update 2016.07.27, checkhw and setenv everytime, @@ -113,6 +441,8 @@ printf(" Get env aml_dt failed!\n"); if (aml_dt_buf) free(aml_dt_buf); + if (gzip_buf) + free(gzip_buf); return fdt_addr; } @@ -139,8 +469,8 @@ for (i = 0; i < AML_DT_ID_VARI_TOTAL; i++) { tokens[i] = strsep(&aml_dt_buf, "_"); } - if (aml_dt_buf) - free(aml_dt_buf); + //if (aml_dt_buf) + //free(aml_dt_buf); printf(" aml_dt soc: %s platform: %s variant: %s\n", tokens[0], tokens[1], tokens[2]); /*match and print result*/ @@ -222,7 +552,34 @@ } else { printf(" Cannot find legal dtb!\n"); + if (gzip_buf) + free(gzip_buf); return fdt_addr; } +} +#endif //#ifdef AML_MULTI_DTB_API_NEW + +extern int check_valid_dts(unsigned char *buffer); +#ifdef AML_MULTI_DTB_CHECK_CMD +static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned long loadaddr = 0x1080000; + + if (argc > 1) + loadaddr = simple_strtoul(argv[1],NULL,16); + + check_valid_dts((void*)loadaddr); + return 0; } + +U_BOOT_CMD( + dtb_chk, //command name + 2, //maxargs + 0, //repeatable + do_test, //command function + "multi-dtb check command", //description + " argv: dtb_chk <dtbLoadaddr> \n" //usage + " do dtb check, which already loaded at <dtbLoadaddr>.\n" +); +#endif //#ifdef AML_MULTI_DTB_CHECK_CMD
diff --git a/common/board_r.c b/common/board_r.c index beea370..cbc256d 100644 --- a/common/board_r.c +++ b/common/board_r.c
@@ -330,7 +330,8 @@ #ifdef CONFIG_AML_STORAGE static int initr_storage(void) { - return !store_init(0); + store_init(0); + return 0; } #else #if defined(CONFIG_MTD_NOR_FLASH)
diff --git a/common/bootm.c b/common/bootm.c index 197af17..3303403 100644 --- a/common/bootm.c +++ b/common/bootm.c
@@ -5,6 +5,8 @@ */ #ifndef USE_HOSTCC +#include <image-android-dt.h> +#include <dt_table.h> #include <common.h> #include <bootstage.h> #include <bzlib.h> @@ -19,6 +21,8 @@ #include <lzma/LzmaDec.h> #include <lzma/LzmaTools.h> #include <time_logging.h> +#include <android_image.h> +#include <amlogic/storage.h> #if defined(CONFIG_CMD_USB) #include <usb.h> #endif @@ -30,6 +34,10 @@ #include <bootm.h> #include <image.h> +#ifdef CONFIG_OF_LIBFDT_OVERLAY +#include <ext_common.h> +#endif + #ifndef CONFIG_SYS_BOOTM_LEN /* use 8MByte as default max gunzip size */ #define CONFIG_SYS_BOOTM_LEN 0x800000 @@ -37,6 +45,10 @@ #define IH_INITRD_ARCH IH_ARCH_DEFAULT +#ifdef CONFIG_MDUMP_COMPRESS +#include <ramdump.h> +#endif + #ifndef USE_HOSTCC DECLARE_GLOBAL_DATA_PTR; @@ -245,6 +257,152 @@ return 0; } +/* + * load dtb overlay partition to mem +*/ +#ifdef CONFIG_OF_LIBFDT_OVERLAY +static int read_fdto_partition(void) +{ + char cmd[128]; + int ret = 0; + u64 tmp = 0; + void *dtbo_mem_addr = NULL; + char dtbo_partition[32]; + char *s1; + struct dt_table_header hdr; + + //run_command("get_valid_slot;", 0); + s1 = env_get("active_slot"); + printf("active_slot is %s\n", s1); + if (strcmp(s1, "normal") == 0) { + strcpy(dtbo_partition, "dtbo"); + } else if (strcmp(s1, "_a") == 0) { + strcpy(dtbo_partition, "dtbo_a"); + } else if (strcmp(s1, "_b") == 0) { + strcpy(dtbo_partition, "dtbo_b"); + } + + /* + * Though it is really no need to parse the dtimg infos + * here, but wasting time to read the whole dtbo image + * partition is unacceptable + */ + printf("Start read %s partition datas!\n", dtbo_partition); + if (store_read(dtbo_partition, 0, + sizeof(struct dt_table_header), &hdr) < 0) { + printf("Fail to read header of DTBO partition\n"); + return -1; + } + +#ifdef CONFIG_CMD_DTIMG + if (!android_dt_check_header((ulong)&hdr)) { + printf("DTBO partition header is incorrect\n"); + return -1; + } +#endif + + dtbo_mem_addr = malloc(fdt32_to_cpu(hdr.total_size)); + if (!dtbo_mem_addr) { + printf("out of memory\n"); + return -1; + } else { + if (store_read(dtbo_partition, 0, + fdt32_to_cpu(hdr.total_size), dtbo_mem_addr) < 0) { + printf("Fail to read DTBO partition\n"); + free(dtbo_mem_addr); + return -1; + } + else { + sprintf(cmd, "0x%p", dtbo_mem_addr); + env_set("dtbo_mem_addr",cmd); + } + } + + return 0; +} +#endif + +#ifdef CONFIG_OF_LIBFDT_OVERLAY +static int get_fdto_totalsize(u32 *tz) +{ + unsigned long long dtbo_mem_addr = NULL; + int ret; + + ret = read_fdto_partition(); + if (ret != 0) + return ret; + + dtbo_mem_addr = simple_strtoul(env_get("dtbo_mem_addr"), NULL, 16); +#ifdef CONFIG_CMD_DTIMG + *tz = android_dt_get_totalsize(dtbo_mem_addr); +#endif + return 0; +} +#endif + +#ifdef CONFIG_OF_LIBFDT_OVERLAY +static int do_fdt_overlay(void) +{ + unsigned long long dtbo_mem_addr = NULL; + int dtbo_num = 0; + int i; + char cmd[128]; + unsigned long long dtbo_start; + char *dtbo_idx = NULL; + char idx[32]; + + if (!env_get("dtbo_mem_addr")) { + printf("No valid dtbo image found\n"); + return -1; + } + + dtbo_mem_addr = simple_strtoul(env_get("dtbo_mem_addr"), NULL, 16); +#ifdef CONFIG_CMD_DTIMG + if (!android_dt_check_header(dtbo_mem_addr)) { + printf("Error: DTBO image header is incorrect\n"); + return -1; + } +#endif + + /* android_dt_print_contents(dtbo_mem_addr); */ + dtbo_num = fdt32_to_cpu(( + (const struct dt_table_header *)dtbo_mem_addr)->dt_entry_count); + printf("find %d dtbos\n", dtbo_num); + + dtbo_idx = env_get("androidboot.dtbo_idx"); + if (!dtbo_idx) { + printf("No androidboot.dtbo_idx configured\n"); + printf("And no dtbos will be applied\n"); + return -1; + } + printf("dtbos to be applied: %s\n", dtbo_idx); + + #ifndef CONFIG_CMD_DTIMG + printf("Error: No dtimg support found\n"); + return -1; + #endif + + for (i = 0; i < dtbo_num; i++) { + memset(idx, 0x00, sizeof(idx)); + sprintf(idx, "%d", i); + if (strstr(dtbo_idx, idx)) { + printf("Apply dtbo %d\n", i); + sprintf(cmd, "dtimg start 0x%llx %d dtbo_start", + dtbo_mem_addr, i); + run_command(cmd, 0); + dtbo_start = simple_strtoul( + env_get("dtbo_start"), NULL, 16); + + sprintf(cmd, "fdt apply 0x%llx", dtbo_start); + run_command(cmd, 0); + } + } + + free((void *)dtbo_mem_addr); + return 0; +} +#endif + /** * bootm_find_images - wrapper to find and locate various images * @flag: Ignored Argument @@ -264,6 +422,9 @@ int bootm_find_images(int flag, int argc, char * const argv[]) { int ret; +#ifdef CONFIG_OF_LIBFDT_OVERLAY + u32 fdto_totalsize = 0; +#endif /* find ramdisk */ ret = boot_get_ramdisk(argc, argv, &images, IH_INITRD_ARCH, @@ -318,6 +479,14 @@ return 1; } set_working_fdt_addr(map_to_sysmem(images.ft_addr)); + +#ifdef CONFIG_OF_LIBFDT_OVERLAY + if (get_fdto_totalsize(&fdto_totalsize) == 0) + fdt_set_totalsize(images.ft_addr, fdt_get_header(images.ft_addr, + totalsize) + fdto_totalsize); + images.ft_len = fdt_get_header(images.ft_addr, totalsize); + do_fdt_overlay(); +#endif #endif #if IMAGE_ENABLE_FIT @@ -723,6 +892,9 @@ if (!ret && (states & BOOTM_STATE_FINDOTHER)) ret = bootm_find_other(cmdtp, flag, argc, argv); +#ifdef CONFIG_MDUMP_COMPRESS + check_ramdump(); +#endif /* Load the OS */ if (!ret && (states & BOOTM_STATE_LOADOS)) { @@ -912,7 +1084,7 @@ pr_info("avb2: %s\n", avb_s); if (strcmp(avb_s, "1") != 0) { #ifdef CONFIG_AML_ANTIROLLBACK - struct andr_img_hdr **tmp_img_hdr = (struct andr_img_hdr **)&buf; + boot_img_hdr_t **tmp_img_hdr = (boot_img_hdr_t **)&buf; #endif }
diff --git a/common/image-android-dt.c b/common/image-android-dt.c index c0683ee..d174413 100644 --- a/common/image-android-dt.c +++ b/common/image-android-dt.c
@@ -28,6 +28,18 @@ return magic == DT_TABLE_MAGIC; } +u32 android_dt_get_totalsize(ulong hdr_addr) +{ + const struct dt_table_header *hdr; + u32 totalsize; + + hdr = map_sysmem(hdr_addr, sizeof(*hdr)); + totalsize = fdt32_to_cpu(hdr->total_size); + unmap_sysmem(hdr); + + return totalsize; +} + /** * Get the address of FDT (dtb or dtbo) in memory by its index in image. *
diff --git a/common/image-android.c b/common/image-android.c old mode 100644 new mode 100755 index 4e28240..fe267ed --- a/common/image-android.c +++ b/common/image-android.c
@@ -70,6 +70,48 @@ static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; +#ifdef CONFIG_OF_LIBFDT_OVERLAY +static int save_dtbo_idx(const char *cmdline) +{ + char *dtbo_chosen_idx_start = NULL; + char *dtbo_chosen_idx_end = NULL; + char *dtbo_idx = NULL; + + if (!env_get("androidboot.dtbo_idx")) { + if (!cmdline) + return -1; + + dtbo_chosen_idx_start = strstr(cmdline, "androidboot.dtbo_idx"); + if (!dtbo_chosen_idx_start) { + printf("No androidboot.dtbo_idx configured"); + return -1; + } + + dtbo_chosen_idx_end = strchr(dtbo_chosen_idx_start, ' '); + if (dtbo_chosen_idx_end) { + dtbo_idx = malloc(dtbo_chosen_idx_end - + dtbo_chosen_idx_start + 1); + if (!dtbo_idx) { + printf("dtbo out of memory\n"); + return -1; + } + memset(dtbo_idx, 0x00, + dtbo_chosen_idx_end - dtbo_chosen_idx_start + 1); + strncpy(dtbo_idx, dtbo_chosen_idx_start, + dtbo_chosen_idx_end - dtbo_chosen_idx_start); + } else + strncpy(dtbo_idx, dtbo_chosen_idx_start, + strlen(dtbo_chosen_idx_start)); + + env_set("androidboot.dtbo_idx", + dtbo_idx + strlen("androidboot.dtbo_idx=")); + } + + free(dtbo_idx); + return 0; +} +#endif + static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr) { /* @@ -129,6 +171,9 @@ len += strlen(hdr->cmdline); } +#ifdef CONFIG_OF_LIBFDT_OVERLAY + save_dtbo_idx(hdr->cmdline); +#endif char *bootargs = env_get("bootargs"); if (bootargs) len += strlen(bootargs);
diff --git a/common/image.c b/common/image.c index 8b1d397..71786ba 100644 --- a/common/image.c +++ b/common/image.c
@@ -214,11 +214,18 @@ int image_check_dcrc(const image_header_t *hdr) { + +#ifdef CONFIG_PXP_EMULATOR + puts("PXP skip CRC..."); + return 1; +#else ulong data = image_get_data(hdr); ulong len = image_get_data_size(hdr); ulong dcrc = crc32_wd(0, (unsigned char *)data, len, CHUNKSZ_CRC32); return (dcrc == image_get_dcrc(hdr)); +#endif + } /**
diff --git a/common/led.c b/common/led.c new file mode 100644 index 0000000..53f54ef --- /dev/null +++ b/common/led.c
@@ -0,0 +1,215 @@ +#include <amlogic/led_aw2015.h> +#include <dm.h> + +#if defined(CONFIG_C2_VENUS_P1) || defined(CONFIG_C2_VENUS_P2) || \ + defined(CONFIG_C2_VENUS_BX) || defined(CONFIG_C2_BSV3_P1) +#define CAL_FILENAME "status_led_calibration_LUT.txt" +#define AW2015_MAX_CURRENT AW2015_LED_25_5mA +#else +#define CAL_FILENAME "led_calibration_LUT.txt" +#define AW2015_MAX_CURRENT AW2015_LED_12_25mA +#endif + +// Copied from +// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 +// Reads "led_calibration_LUT.txt" from the factory partition. +// Forwards errors, returns 0 on success. +int get_cal_string(char *buf, int len) +{ + int ret; + loff_t len_read; + const loff_t seek = 21; + + ret = fs_set_blk_dev("mmc", "1:4", FS_TYPE_EXT); + if (ret) { + pr_err("LED: fs_set_blk_dev error=%d\n", ret); + return ret; + } + // Leave space for terminator + ret = fs_read(CAL_FILENAME, buf, seek, len - 1, + &len_read); + if (ret) { + pr_err("LED: fs_read error=%d\n", ret); + return ret; + } + // fs_read does not add a null terminator + buf[len_read] = '\0'; + + return 0; +} + +// Copied from +// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 +// Gets calibration settings for the status LED: +// pwm_r, pwm_g, pwm_b, current_r, current_g, current_b +// On failure, |settings| is not modified. +void get_cal_settings(unsigned int *settings, const char color_header[]) +{ + int i; + unsigned long settings_[N_CAL_SETTINGS]; + + // Max length to cover all color lines + // 9 colors * (color_name + ":4095:" + xxx[,|;|\n] * 6) + // 9 * (14 + 6 + 4 * 6 ) + const unsigned int max_chars = 396; + // Add one for null terminator + char buf[max_chars]; + + if (get_cal_string(&buf, max_chars)) + return; + + const char *p, *p_next; + + p = strstr(buf, color_header); + if (!p) { + pr_err("LED: \"%s\" not found in cal file segment: %s\n", + color_header, buf); + return; + } + p += strlen(color_header); + + for (i = 0; i < N_CAL_SETTINGS; ++i) { + unsigned long value = simple_strtoul(p, &p_next, 10); + + if (value > 255) { + pr_err("LED: value %d is too large: %lu\n", + settings_[i]); + return; + } + settings_[i] = value; + + // Skip check that |p_next| is valid on last iteration + if (i == 5) + break; + // Is there not a separator, or not another number + if ((*p_next != ',' && *p_next != ';') || + !isdigit(p_next[1])) { + // Is this the first current + if (i == 3) { + // One current instead of RGB current + settings_[4] = value; + settings_[5] = value; + break; + } + // Invalid + pr_err("LED calibration file is malformed\n"); + return; + } + + p = p_next + 1; + } + + for (i = 0; i < N_CAL_SETTINGS; ++i) + settings[i] = (unsigned int)settings_[i]; +} + +void reg_write(struct udevice *led_devp, int reg, int mask, int val) { + int old_val; + int new_val; + + old_val = dm_i2c_reg_read(led_devp, reg); + if (old_val < 0) { + pr_err("LED: read %d reg failed\n", reg); + return; + } + new_val = (old_val & ~mask) | (val & mask); + dm_i2c_reg_write(led_devp, reg, new_val); +} + +void sys_led_init(enum LED_ANIMATION led_animation) +{ +#ifdef CONFIG_SYS_I2C_MESON + int ret; + struct udevice *led_devp = NULL; + ret = i2c_get_chip_for_busnum(BUS_NUM, I2C_LED_REG, 1, &led_devp); + if (ret) { + pr_err("LED: i2c get bus fail\n"); + return; + } + + reg_write(led_devp, AW2015_REG_RSTIDR, AW2015_LED_RSTIDR_MASK, + AW2015_LED_RSTIDR_RESET); + reg_write(led_devp, AW2015_REG_GCR, AW2015_LED_CHIPEN_MASK, + AW2015_LED_CHIP_ENABLE); + reg_write(led_devp, AW2015_REG_GCR, AW2015_LED_CHARGE_DISABLE_MASK, + AW2015_LED_CHARGE_DISABLE); + reg_write(led_devp, AW2015_REG_IMAX, AW2015_LED_IMX_MASK, + AW2015_MAX_CURRENT); + reg_write(led_devp, AW2015_REG_LEDCTR, AW2015_LED_PWMLOG_MASK, + AW2015_LED_PWMLOG_LEANER); + reg_write(led_devp, AW2015_REG_LEDEN, AW2015_LED_LEDEN_MASK, + AW2015_LED_LEDEN_TURN_ON_ALL); + + switch(led_animation) { + case WHITE: + turn_on_white_led(led_devp); + break; + case YELLOW: + turn_on_yellow_led(led_devp); + break; + case BLINK_YELLOW: + blink_yellow_led(led_devp); + break; + default: + pr_err("LED: unknown led animation\n"); + } +#endif // CONFIG_SYS_I2C_MESON +} + +void turn_on_white_led(struct udevice *led_devp) { + unsigned int cal_settings[N_CAL_SETTINGS] = + {128, 0, 128, 100, 100, 100}; + int i; + get_cal_settings(&cal_settings, "White:4095:"); + for(i = 0; i < 3; ++i) { + reg_write(led_devp, AW2015_REG_LCFG1 + i, AW2015_LED_LEDMD_MASK, + AW2015_LED_ON_MODE); + reg_write(led_devp, AW2015_REG_PWM1 + i, AW2015_LED_PWM_MASK, + cal_settings[i]); + reg_write(led_devp, AW2015_REG_ILED1 + i, AW2015_LED_ILED_MASK, + cal_settings[3+i]); + } +} + +void turn_on_yellow_led(struct udevice *led_devp) { + unsigned int cal_settings[N_CAL_SETTINGS] = + {255, 255, 255, 0xff, 0xef, 0}; + int i; + get_cal_settings(&cal_settings, "NestYellow:4095:"); + for(i = 0; i < 3; ++i) { + reg_write(led_devp, AW2015_REG_LCFG1 + i, AW2015_LED_LEDMD_MASK, + AW2015_LED_ON_MODE); + reg_write(led_devp, AW2015_REG_PWM1 + i, AW2015_LED_PWM_MASK, + cal_settings[i]); + reg_write(led_devp, AW2015_REG_ILED1 + i, AW2015_LED_ILED_MASK, + cal_settings[3+i]); + } +} + +void blink_yellow_led(struct udevice *led_devp) { + int i; + int val; + + turn_on_yellow_led(led_devp); + + for(i = 0; i < 3; ++i) { + reg_write(led_devp, AW2015_REG_PAT1_T1 + i * PAT_FIELD_NUMBER, + AW2015_LED_PAT_TRISE_MASK, 0x0); + reg_write(led_devp, AW2015_REG_PAT1_T2 + i * PAT_FIELD_NUMBER, + AW2015_LED_PAT_TFALL_MASK, 0x0); + reg_write(led_devp, AW2015_REG_PAT1_T1 + i * PAT_FIELD_NUMBER, + AW2015_LED_PAT_TON_MASK, + AW2015_LED_PAT_ON_1SEC); + reg_write(led_devp, AW2015_REG_PAT1_T2 + i * PAT_FIELD_NUMBER, + AW2015_LED_PAT_TOFF_MASK, + AW2015_LED_PAT_OFF_1SEC); + reg_write(led_devp, AW2015_REG_PAT1_T4 + i * PAT_FIELD_NUMBER, + AW2015_LED_PAT_CTR_MASK, + AW2015_LED_PAT_CTR_INF_LOOP); + reg_write(led_devp, AW2015_REG_LCFG1 + i, + AW2015_LED_LEDMD_MASK, + AW2015_LED_BLINK_MODE); + } + reg_write(led_devp, AW2015_REG_PATRUN, AW2015_LED_PATRUN_MASK, + AW2015_LED_PATRUN_START_ALL); +}
diff --git a/common/leds-aw2026.c b/common/leds-aw2026.c new file mode 100644 index 0000000..d8e67f7 --- /dev/null +++ b/common/leds-aw2026.c
@@ -0,0 +1,207 @@ +#include <amlogic/leds-aw2026.h> +#include <dm.h> + +#define CAL_FILENAME "led_calibration_LUT.txt" +#define AW2026_MAX_CURRENT AW2026_LED_3_1875mA + +// Copied from +// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 +// Reads "led_calibration_LUT.txt" from the factory partition. +// Forwards errors, returns 0 on success. +int get_cal_string(char *buf, int len) +{ + int ret; + loff_t len_read; + const loff_t seek = 21; + + ret = fs_set_blk_dev("mmc", "1:4", FS_TYPE_EXT); + if (ret) { + pr_err("LED: fs_set_blk_dev error=%d\n", ret); + return ret; + } + // Leave space for terminator + ret = fs_read(CAL_FILENAME, buf, seek, len - 1, + &len_read); + if (ret) { + pr_err("LED: fs_read error=%d\n", ret); + return ret; + } + // fs_read does not add a null terminator + buf[len_read] = '\0'; + + return 0; +} + +// Copied from +// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 +// Gets calibration settings for the status LED: +// pwm_r, pwm_g, pwm_b, current_r, current_g, current_b +// On failure, |settings| is not modified. +void get_cal_settings(unsigned int *settings, const char color_header[]) +{ + int i; + unsigned long settings_[N_CAL_SETTINGS]; + + // Max length to cover all color lines + // 9 colors * (color_name + ":4095:" + xxx[,|;|\n] * 6) + // 9 * (14 + 6 + 4 * 6 ) + const unsigned int max_chars = 396; + // Add one for null terminator + char buf[max_chars]; + + if (get_cal_string(&buf, max_chars)) + return; + + const char *p, *p_next; + + p = strstr(buf, color_header); + if (!p) { + pr_err("LED: \"%s\" not found in cal file segment: %s\n", + color_header, buf); + return; + } + p += strlen(color_header); + + for (i = 0; i < N_CAL_SETTINGS; ++i) { + unsigned long value = simple_strtoul(p, &p_next, 10); + + if (value > 255) { + pr_err("LED: value %d is too large: %lu\n", + settings_[i]); + return; + } + settings_[i] = value; + + // Skip check that |p_next| is valid on last iteration + if (i == 5) + break; + // Is there not a separator, or not another number + if ((*p_next != ',' && *p_next != ';') || + !isdigit(p_next[1])) { + // Is this the first current + if (i == 3) { + // One current instead of RGB current + settings_[4] = value; + settings_[5] = value; + break; + } + // Invalid + pr_err("LED calibration file is malformed\n"); + return; + } + + p = p_next + 1; + } + + for (i = 0; i < N_CAL_SETTINGS; ++i) + settings[i] = (unsigned int)settings_[i]; +} + +void reg_write(struct udevice *led_devp, int reg, int mask, int val) { + int old_val; + int new_val; + + old_val = dm_i2c_reg_read(led_devp, reg); + if (old_val < 0) { + pr_err("LED: read %d reg failed\n", reg); + return; + } + new_val = (old_val & ~mask) | (val & mask); + dm_i2c_reg_write(led_devp, reg, new_val); +} + +void sys_led_init(enum LED_ANIMATION led_animation) +{ +#ifdef CONFIG_SYS_I2C_MESON + int ret; + struct udevice *led_devp = NULL; + ret = i2c_get_chip_for_busnum(I2C_BUS_NUM, I2C_LED_REG, 1, &led_devp); + if (ret) { + pr_err("LED: i2c get bus fail\n"); + return; + } + + reg_write(led_devp, AW2026_REG_RSTIDR, AW2026_LED_RSTIDR_MASK, + AW2026_LED_RSTIDR_RESET); + reg_write(led_devp, AW2026_REG_GCR, AW2026_LED_CHIPEN_MASK, + AW2026_LED_CHIP_ENABLE); + reg_write(led_devp, AW2026_REG_IMAX, AW2026_LED_IMX_MASK, + AW2026_MAX_CURRENT); + reg_write(led_devp, AW2026_REG_LEDCTR, AW2026_LED_PWMLOG_MASK, + AW2026_LED_PWMLOG_LEANER); + reg_write(led_devp, AW2026_REG_LEDEN, AW2026_LED_LEDEN_MASK, + AW2026_LED_LEDEN_TURN_ON_ALL); + + switch(led_animation) { + case WHITE: + turn_on_white_led(led_devp); + break; + case YELLOW: + turn_on_yellow_led(led_devp); + break; + case BLINK_YELLOW: + blink_yellow_led(led_devp); + break; + default: + pr_err("LED: unknown led animation\n"); + } +#endif // CONFIG_SYS_I2C_MESON +} + +void turn_on_white_led(struct udevice *led_devp) { + unsigned int cal_settings[N_CAL_SETTINGS] = + {128, 0, 128, 100, 100, 100}; + int i; + get_cal_settings(&cal_settings, "white:0:"); + for(i = 0; i < 3; ++i) { + reg_write(led_devp, AW2026_REG_LCFG1 + i, AW2026_LED_LEDMD_MASK, + AW2026_LED_ON_MODE); + reg_write(led_devp, AW2026_REG_PWM1 + i, AW2026_LED_PWM_MASK, + cal_settings[i]); + reg_write(led_devp, AW2026_REG_ILED1 + i, AW2026_LED_ILED_MASK, + cal_settings[3+i]); + } +} + +void turn_on_yellow_led(struct udevice *led_devp) { + unsigned int cal_settings[N_CAL_SETTINGS] = + {255, 255, 255, 0xff, 0xef, 0}; + int i; + get_cal_settings(&cal_settings, "amber:0:"); + for(i = 0; i < 3; ++i) { + reg_write(led_devp, AW2026_REG_LCFG1 + i, AW2026_LED_LEDMD_MASK, + AW2026_LED_ON_MODE); + reg_write(led_devp, AW2026_REG_PWM1 + i, AW2026_LED_PWM_MASK, + cal_settings[i]); + reg_write(led_devp, AW2026_REG_ILED1 + i, AW2026_LED_ILED_MASK, + cal_settings[3+i]); + } +} + +void blink_yellow_led(struct udevice *led_devp) { + int i; + int val; + + turn_on_yellow_led(led_devp); + + for(i = 0; i < 3; ++i) { + reg_write(led_devp, AW2026_REG_PAT1_T1 + i * PAT_FIELD_NUMBER, + AW2026_LED_PAT_TRISE_MASK, 0x0); + reg_write(led_devp, AW2026_REG_PAT1_T2 + i * PAT_FIELD_NUMBER, + AW2026_LED_PAT_TFALL_MASK, 0x0); + reg_write(led_devp, AW2026_REG_PAT1_T1 + i * PAT_FIELD_NUMBER, + AW2026_LED_PAT_TON_MASK, + AW2026_LED_PAT_ON_1SEC); + reg_write(led_devp, AW2026_REG_PAT1_T2 + i * PAT_FIELD_NUMBER, + AW2026_LED_PAT_TOFF_MASK, + AW2026_LED_PAT_OFF_1SEC); + reg_write(led_devp, AW2026_REG_PAT1_T4 + i * PAT_FIELD_NUMBER, + AW2026_LED_PAT_CTR_MASK, + AW2026_LED_PAT_CTR_INF_LOOP); + reg_write(led_devp, AW2026_REG_LCFG1 + i, + AW2026_LED_LEDMD_MASK, + AW2026_LED_BLINK_MODE); + } + reg_write(led_devp, AW2026_REG_PATRUN, AW2026_LED_PATRUN_MASK, + AW2026_LED_PATRUN_START_ALL); +}
diff --git a/common/leds-aw210xx.c b/common/leds-aw210xx.c new file mode 100644 index 0000000..b51dd1e --- /dev/null +++ b/common/leds-aw210xx.c
@@ -0,0 +1,248 @@ +#include <amlogic/leds-aw210xx.h> +#include <dm.h> + +#define CAL_FILENAME "led_calibration_LUT.txt" + +// Copied from +// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 +// Reads "led_calibration_LUT.txt" from the factory partition. +// Forwards errors, returns 0 on success. +int get_cal_string(char *buf, int len) +{ + int ret; + loff_t len_read; + const loff_t seek = 21; + + ret = fs_set_blk_dev("mmc", "1:4", FS_TYPE_EXT); + if (ret) { + pr_err("LED: fs_set_blk_dev error=%d\n", ret); + return ret; + } + // Leave space for terminator + ret = fs_read(CAL_FILENAME, buf, seek, len - 1, + &len_read); + if (ret) { + pr_err("LED: fs_read error=%d\n", ret); + return ret; + } + // fs_read does not add a null terminator + buf[len_read] = '\0'; + + return 0; +} + +// Copied from +// https://eureka-partner-review.googlesource.com/c/amlogic/u-boot/+/149113 +// Gets calibration settings for the status LED: +// pwm_r, pwm_g, pwm_b, current_r, current_g, current_b +// On failure, |settings| is not modified. +void get_cal_settings(unsigned int *settings, const char color_header[]) +{ + int i; + unsigned long settings_[N_CAL_SETTINGS]; + + // Max length to cover all color lines + // 9 colors * (color_name + ":4095:" + xxx[,|;|\n] * 6) + // 9 * (14 + 6 + 4 * 6 ) + const unsigned int max_chars = 396; + // Add one for null terminator + char buf[max_chars]; + + if (get_cal_string(&buf, max_chars)) + return; + + const char *p, *p_next; + + p = strstr(buf, color_header); + if (!p) { + pr_err("LED: \"%s\" not found in cal file segment: %s\n", + color_header, buf); + return; + } + p += strlen(color_header); + + for (i = 0; i < N_CAL_SETTINGS; ++i) { + unsigned long value = simple_strtoul(p, &p_next, 10); + + if (value > 255) { + pr_err("LED: value %d is too large: %lu\n", + settings_[i]); + return; + } + settings_[i] = value; + + // Skip check that |p_next| is valid on last iteration + if (i == 5) + break; + // Is there not a separator, or not another number + if ((*p_next != ',' && *p_next != ';') || + !isdigit(p_next[1])) { + // Is this the first current + if (i == 3) { + // One current instead of RGB current + settings_[4] = value; + settings_[5] = value; + break; + } + // Invalid + pr_err("LED calibration file is malformed\n"); + return; + } + + p = p_next + 1; + } + + for (i = 0; i < N_CAL_SETTINGS; ++i) + settings[i] = (unsigned int)settings_[i]; +} + +void reg_write(struct udevice *led_devp, int reg, int mask, int val) { + int old_val; + int new_val; + + old_val = dm_i2c_reg_read(led_devp, reg); + if (old_val < 0) { + pr_err("LED: read %d reg failed\n", reg); + return; + } + new_val = (old_val & ~mask) | (val & mask); + dm_i2c_reg_write(led_devp, reg, new_val); +} + +void sys_led_init(enum LED_ANIMATION led_animation) +{ +#ifdef CONFIG_SYS_I2C_MESON + int ret; + struct udevice *led_devp = NULL; + ret = i2c_get_chip_for_busnum(I2C_BUS_NUM, I2C_LED_REG, 1, &led_devp); + if (ret) { + pr_err("LED: i2c get bus fail\n"); + return; + } + + reg_write(led_devp, AW210XX_REG_RESET, AW210XX_RESET_MASK, + AW210XX_RESET_CHIP); + reg_write(led_devp, AW210XX_REG_GCR, AW210XX_BIT_CHIPEN_MASK, + AW210XX_BIT_CHIPEN_ENABLE); + reg_write(led_devp, AW210XX_REG_GCR, AW210XX_BIT_APSE_MASK, + AW210XX_BIT_APSE_ENABLE); + reg_write(led_devp, AW210XX_REG_GCCR, AW210XX_GLOBAL_CURRENT_MASK, + AW210xx_MAX_CURRENT); + reg_write(led_devp, AW210XX_REG_PHCR, AW210XX_PDE_MASK, + AW210XX_PDE_ENABLE); + + switch(led_animation) { + case WHITE: + turn_on_white_led(led_devp); + break; + case YELLOW: + turn_on_yellow_led(led_devp); + break; + case BLINK_YELLOW: + blink_yellow_led(led_devp); + break; + default: + pr_err("LED: unknown led animation\n"); + } +#endif // CONFIG_SYS_I2C_MESON +} + +void turn_on_white_led(struct udevice *led_devp) { + unsigned int cal_settings[N_CAL_SETTINGS] = + {128, 0, 128, 100, 100, 100}; + int i; + get_cal_settings(&cal_settings, "white:255:"); + // HW design: LED7 is blue, LED8 is red, LED9 is green + // Calibration file is: R,G,B + for(i = 0; i < 3; ++i) { + if (i == 2) { + // blue led + reg_write(led_devp, AW210XX_REG_SL06, AW210XX_SLXX_MASK, + cal_settings[3+i]); + reg_write(led_devp, AW210XX_REG_BR06L, + AW210XX_BRXX_MASK, cal_settings[i]); + } { + // red led and green led + reg_write(led_devp, AW210XX_REG_SL07 + i, + AW210XX_SLXX_MASK, cal_settings[3+i]); + reg_write(led_devp, AW210XX_REG_BR07L + i*2, + AW210XX_BRXX_MASK, cal_settings[i]); + } + } + reg_write(led_devp, AW210XX_REG_UPDATE, AW210XX_UPDATE_MASK, + AW210XX_UPDATE_ENABLE); +} + +void turn_on_yellow_led(struct udevice *led_devp) { + unsigned int cal_settings[N_CAL_SETTINGS] = + {255, 255, 255, 0xff, 0xef, 0}; + int i; + + get_cal_settings(&cal_settings, "amber:255:"); + // HW design: LED7 is blue, LED8 is red, LED9 is green + // Calibration file is: R,G,B + for(i = 0; i < 3; ++i) { + if (i == 2) { + // blue led + reg_write(led_devp, AW210XX_REG_SL06, AW210XX_SLXX_MASK, + cal_settings[3+i]); + reg_write(led_devp, AW210XX_REG_BR06L, + AW210XX_BRXX_MASK, cal_settings[i]); + } else { + // red led and green led + reg_write(led_devp, AW210XX_REG_SL07 + i, + AW210XX_SLXX_MASK, cal_settings[3+i]); + reg_write(led_devp, AW210XX_REG_BR07L + i*2, + AW210XX_BRXX_MASK, cal_settings[i]); + } + } + reg_write(led_devp, AW210XX_REG_UPDATE, AW210XX_UPDATE_MASK, + AW210XX_UPDATE_ENABLE); +} + +void blink_yellow_led(struct udevice *led_devp) { + unsigned int cal_settings[N_CAL_SETTINGS] = + {255, 255, 255, 0xff, 0xef, 0}; + int i; + + reg_write(led_devp, AW210XX_REG_GCFG, AW210XX_GE_MASK, + AW210XX_GE2_SET); + reg_write(led_devp, AW210XX_REG_ABMCFG, AW210XX_PATCFG_MASK, + AW210XX_PATE_ENABLE | AW210XX_PATMD_AUTO); + reg_write(led_devp, AW210XX_REG_ABMT0, AW210XX_PAT_RISE_MASK, + AW210XX_PAT_RISE_TIME); + reg_write(led_devp, AW210XX_REG_ABMT1, AW210XX_PAT_FALL_MASK, + AW210XX_PAT_FALL_TIME); + reg_write(led_devp, AW210XX_REG_ABMT0, AW210XX_PAT_ON_MASK, + AW210XX_PAT_ON_TIME); + reg_write(led_devp, AW210XX_REG_ABMT1, AW210XX_PAT_OFF_MASK, + AW210XX_PAT_OFF_TIME); + + get_cal_settings(&cal_settings, "amber:255:"); + // HW design: LED7 is blue, LED8 is red, LED9 is green + // datasheet: in group mode + // GSLR: for ledx(x=1,4,7) + // GSLG: for ledx(x=2,5,8) + // GSLB: for ledx(x=3,6,9) + for(i = 0; i < 3; ++i) { + if (i == 2) { + // blue led + reg_write(led_devp, AW210XX_REG_GSLR, AW210XX_SLXX_MASK, + cal_settings[3+i]); + } else { + // red led and green led + reg_write(led_devp, AW210XX_REG_GSLG + i, + AW210XX_SLXX_MASK, cal_settings[3+i]); + } + } + + // set brightness range + reg_write(led_devp, AW210XX_REG_GBRH, AW210XX_BRXX_MASK, + AW210xx_MAX_BRIGHTNESS); + reg_write(led_devp, AW210XX_REG_GBRL, AW210XX_BRXX_MASK, + AW210xx_MIN_BRIGHTNESS); + + // start run + reg_write(led_devp, AW210XX_REG_ABMGO, AW210XX_PAT_RUN_MASK, + AW210XX_PAT_RUN); +}
diff --git a/common/main.c b/common/main.c index 40baa13..e951c45 100644 --- a/common/main.c +++ b/common/main.c
@@ -44,6 +44,10 @@ bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); +#ifdef CONFIG_MDUMP_COMPRESS + ramdump_init(); +#endif + if (IS_ENABLED(CONFIG_VERSION_VARIABLE)) env_set("ver", version_string); /* set version variable */
diff --git a/common/partitions.c b/common/partitions.c index 1a5faa3..b94ed1a 100644 --- a/common/partitions.c +++ b/common/partitions.c
@@ -24,7 +24,8 @@ static int parts_total_num; int has_boot_slot = 0; int has_system_slot = 0; - +bool dynamic_partition = false; +bool vendor_boot_partition = false; int get_partitions_table(struct partitions **table) { @@ -108,6 +109,14 @@ if ( buffer == NULL) goto _err; + + ret = check_valid_dts(buffer); + pr_debug("%s() %d: ret %d\n",__func__, __LINE__, ret); + if ( ret < 0 ) + { + printf("%s() %d: ret %d\n",__func__, __LINE__, ret); + goto _err; + } #ifdef CONFIG_MULTI_DTB dt_addr = (char *)get_multi_dt_entry((unsigned long)buffer); #else @@ -134,6 +143,10 @@ memset(part_table, 0, sizeof(struct partitions)*(be32_to_cpup((u32*)parts_num))); parts_total_num = be32_to_cpup((u32*)parts_num); } + dynamic_partition = false; + env_set("partiton_mode","normal"); + vendor_boot_partition = false; + env_set("vendor_boot_mode","false"); for (index = 0; index < be32_to_cpup((u32*)parts_num); index++) { sprintf(propname,"part-%d", index); @@ -176,6 +189,18 @@ has_system_slot = 1; else if (strcmp(uname, "system") == 0) has_system_slot = 0; + + if (strcmp(uname, "super") == 0) { + dynamic_partition = true; + env_set("partiton_mode","dynamic"); + printf("enable dynamic_partition\n"); + } + + if (strncmp(uname, "vendor_boot", 11) == 0) { + vendor_boot_partition = true; + env_set("vendor_boot_mode","true"); + printf("enable vendor_boot\n"); + } } return 0;
diff --git a/common/ramdump.c b/common/ramdump.c new file mode 100644 index 0000000..e105311 --- /dev/null +++ b/common/ramdump.c
@@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/arch/bl31_apis.h> +#include <asm/arch/secure_apb.h> +#include <ramdump.h> +#include <emmc_partitions.h> + +#define DEBUG_RAMDUMP 0 +#define AMLOGIC_KERNEL_PANIC 0x0c +#define AMLOGIC_WATCHDOG_REBOOT 0x0d + + +unsigned long ramdump_base = 0; +unsigned long ramdump_size = 0; +unsigned int get_reboot_mode(void) +{ + uint32_t reboot_mode_val = ((readl(AO_SEC_SD_CFG15) >> 12) & 0xf); + return reboot_mode_val; +} + +void ramdump_init(void) +{ + unsigned int data; + + ramdump_base = readl(P_AO_SEC_GP_CFG12); + ramdump_size = readl(P_AO_SEC_GP_CFG13); + + data = readl(PREG_STICKY_REG8); + writel(data & ~RAMDUMP_STICKY_DATA_MASK, PREG_STICKY_REG8); + printf("%s, add:%lx, size:%lx\n", __func__, ramdump_base, ramdump_size); +} + +/* + * NOTE: this is a default impemention for writing compressed ramdump data + * to /data/ partition for Android platform. You can read out dumpfile in + * path /data/crashdump-1.bin when enter Android for crash analyze. + * by default, /data/ partion for android is EXT4 fs. + * + * TODO: + * If you are using different fs or OS on your platform, implement compress + * data save command for your fs and OS in your board.c with same function + * name "ramdump_save_compress_data". + */ +__weak int ramdump_save_compress_data(void) +{ + int data_pid; + char cmd[128] = {0}; + + data_pid = get_partition_num_by_name("data"); + if (data_pid < 0) { + printf("can't find data partition\n"); + return -1; + } + sprintf(cmd, "ext4write mmc 1:%x %lx /crashdump-1.bin %lx\n", + data_pid, ramdump_base, ramdump_size); + printf("CMD:%s\n", cmd); + run_command(cmd, 1); + return 0; +} + +static void ramdump_env_setup(unsigned long addr, unsigned long size) +{ + unsigned int data[10] = { + 0x8E9C929F, 0x9E9C9791, + 0xD28C9191, 0x97949B8D, + 0x888B92, 0xCEBB97, + 0x938E9B90, 0x978D8D97, + 0xC8009B8A, 0xB99CDB + }; + char *line, *p1, *p2, *o; + unsigned char *p; + int i; + + p = (unsigned char *)data; + for (i = 0; i < 40; i++) + p[i] = ~(p[i] - 1); + + /* + * TODO: Make sure address for fdt_high and initrd_high + * are suitable for all boards + * + * usually kernel load address is 0x010800000 + * Make sure: + * (kernel image size + ramdisk size) < + * (initrd_high - 0x010800000) + * dts file size < (fdt_high - initrd_high) + */ + env_set("initrd_high", "0x04400000"); + env_set("fdt_high", "0x04E00000"); + line = env_get("bootargs"); + if (!line) + return; + + i = strlen(line); + o = malloc(i + 128); + if (!o) + return; + + memset(o, 0, i + 128); + memcpy(o, line, i); + line = o + i + 128; + p1 = strstr(o, (const char *)p); + if (p1) { + p2 = strchr(p1, ' '); + if (!p2) + p2 = p1; + memmove(p1, p2, line - p2); + } + i = strlen(o); + p1 = o + i; + p1[0] = ' '; + sprintf(p1 + 1, "%s=%s ramdump=%lx,%lx", + (char *)data, (char *)(data + 6), addr, size); + env_set("bootargs", o); + +#if DEBUG_RAMDUMP + run_command("printenv bootargs", 1); +#endif + free(o); +} + +void check_ramdump(void) +{ + unsigned long size = 0; + unsigned long addr = 0; + char *env; + int reboot_mode; + + env = env_get("ramdump_enable"); + if (env) { + printf("%s,%s\n", __func__, env); + if (!strcmp(env, "1")) { + reboot_mode = get_reboot_mode(); + if ((reboot_mode == AMLOGIC_WATCHDOG_REBOOT || + reboot_mode == AMLOGIC_KERNEL_PANIC)) { + addr = ramdump_base; + size = ramdump_size; + printf("%s, addr:%lx, size:%lx\n", + __func__, addr, size); + if (addr && size) + ramdump_env_setup(addr, size); + } + } + } +}
diff --git a/common/ssr.c b/common/ssr.c new file mode 100644 index 0000000..b86ceb6 --- /dev/null +++ b/common/ssr.c
@@ -0,0 +1,164 @@ +#include <common.h> +#include <dm/device.h> +#include <i2c.h> +#include <linux/ssr/ps13216.h> + +// AC power threshold in bootloader is set to 90 percent of the peak voltage +// (22.6V) of the lowest allowed VAC (16VAC), which is ~20V. The driver returns +// the squared value of HVSENSE voltage, hence the criteria for boot check is +// +// sqrt(V_squared) / 1024 * 60 > 20 => V_squared * 9 > 1024 * 1024 +// +#define AC_VOLTAGE_THRESHOLD_NUM (1 << 20) +#define AC_VOLTAGE_THRESHOLD_DEN 9 + +// Setting a 16V relaxed hard limit to AC voltage detection in u-boot. +// TODO(tzupengwang): Remove this once the threshold is finalized. +// +// sqrt(V_squared) / 1024 * 60 > 16 => V_squared * 625 > 2^24 +// +#define AC_VOLTAGE_HARD_THRESHOLD_NUM (1 << 24) +#define AC_VOLTAGE_HARD_THRESHOLD_DEN 225 + +// For development purpose, allow device boot with 5V USB power. The USB power +// introduces ~4.3V power to ACDCBUCK_IN. +// +// sqrt(V_squared) / 1024 * 60 > 4 => V_squared * 625 > 1024 * 1024 +// sqrt(V_squared) / 1024 * 60 < 5 => V_squared * 9 < 256 * 256 +// +#define VAC_USB_UPPER_THRESHOLD_NUM (1 << 16) +#define VAC_USB_UPPER_THRESHOLD_DEN 9 +#define VAC_USB_LOWER_THRESHOLD_NUM (1 << 20) +#define VAC_USB_LOWER_THRESHOLD_DEN 225 + +// The V_rms is equal to the V_peak for DC power, while the V_rms is equal to +// V_peak/sqrt(2) for AC power. Considering the precision of the measurement, +// choose ratio 0.9 as the criteria for DC power check. +// +// V_rms > 0.9 * V_peak +// => V_rms * V_rms > 0.81 * V_peak * V_peak +// => 100 * V_rms * V_rms > 81 * V_peak * V_peak +// +#define DC_VOLTAGE_RMS_PEAK_RATIO_NUM 81 +#define DC_VOLTAGE_RMS_PEAK_RATIO_DEN 100 + +#define PS13216_I2C_REG 0x10 + +enum ssr_power_type { + SSR_AC_POWER, + SSR_DC_POWER, +}; + +static int last_squared_ac_voltage; + +int ssr_probe(struct udevice **dev) +{ + int err; + + err = uclass_get_device_by_name(UCLASS_I2C_GENERIC, + "ps13216@10", dev); + if (err) { + pr_err("Can't find ps13216 ssr (%d)\n", err); + return err; + } + + err = dm_i2c_probe((*dev)->parent, PS13216_I2C_REG, 0, dev); + if (err) { + pr_err("Can't probe ps13216 ssr (%d)\n", err); + return err; + } + + return 0; +} + +static bool check_ac_voltage(int squared_voltage) +{ + return squared_voltage * AC_VOLTAGE_HARD_THRESHOLD_DEN > + AC_VOLTAGE_HARD_THRESHOLD_NUM; +} + +static bool check_usb_voltage(int squared_voltage) +{ + return squared_voltage * VAC_USB_LOWER_THRESHOLD_DEN > + VAC_USB_LOWER_THRESHOLD_NUM && + squared_voltage * VAC_USB_UPPER_THRESHOLD_DEN < + VAC_USB_UPPER_THRESHOLD_NUM; +} + +int check_power(struct udevice *dev, enum gpio_state pgood_state) +{ + int err; + int squared_voltage; + int peak_voltage; + enum ssr_power_type type; + + err = get_ssr_hvsense_voltage(dev, &squared_voltage, &peak_voltage); + + if (err) { + pr_err("Failed to get SSR HV_Sense voltage: %d\n", err); + return err; + } + + pr_info("mean_squared: %d, peak: %d, squared_peak: %d\n", + squared_voltage, peak_voltage, peak_voltage * peak_voltage); + + if (squared_voltage * DC_VOLTAGE_RMS_PEAK_RATIO_DEN > + peak_voltage * peak_voltage * DC_VOLTAGE_RMS_PEAK_RATIO_NUM) { + type = SSR_DC_POWER; + } else { + type = SSR_AC_POWER; + } + + last_squared_ac_voltage = squared_voltage; + + pr_info("detected %s power (%d)\n", + (type == SSR_AC_POWER) ? "AC" : "DC", squared_voltage); + + // PX board + if (pgood_state == NOT_AVAILABLE) { + // Allow boot if voltage is sufficient AC power or USB power + if (check_ac_voltage(squared_voltage) || + check_usb_voltage(squared_voltage)) { + return 0; + } + } + + // BX board with sufficient AC power + if (pgood_state == HIGH && check_ac_voltage(squared_voltage)) { + return 0; + } + + // BX board with USB power + if (pgood_state == LOW && type == SSR_DC_POWER && + check_usb_voltage(squared_voltage)) { + pr_info("Allow boot with usb power\n"); + return 0; + } + + // return error if detected AC voltage does not satisfy the criteria + if (squared_voltage * AC_VOLTAGE_THRESHOLD_DEN < + AC_VOLTAGE_THRESHOLD_NUM) { + pr_warn("AC transformer voltage (%d) is lower than 20V\n", + squared_voltage); + } + + return -EAGAIN; +} + +static int do_get_boot_ac_voltage(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + char voltage_str[10] = {0}; + + if (argc != 1) + return CMD_RET_USAGE; + + snprintf(voltage_str, sizeof(voltage_str), "%d", last_squared_ac_voltage); + env_set("boot_ac_voltage", voltage_str); + return 0; +} + +U_BOOT_CMD( + get_boot_ac_voltage, 1, 0, do_get_boot_ac_voltage, + "env_set 'boot_ac_voltage'", "get_boot_ac_voltage" +);
diff --git a/disk/part_efi.c b/disk/part_efi.c index c9fe53f..cdedb59 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c
@@ -441,6 +441,7 @@ le64_to_cpu(gpt_h->last_usable_lba); int i, k; size_t efiname_len, dosname_len; +#ifndef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY #if CONFIG_IS_ENABLED(PARTITION_UUIDS) char *str_uuid; unsigned char *bin_uuid; @@ -449,6 +450,7 @@ char *str_type_guid; unsigned char *bin_type_guid; #endif +#endif size_t hdr_start = gpt_h->my_lba; size_t hdr_end = hdr_start + 1; @@ -493,12 +495,11 @@ gpt_e[i].ending_lba = cpu_to_le64(offset - 1); #ifdef CONFIG_PARTITION_TYPE_GUID +#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY + memcpy(gpt_e[i].partition_type_guid.b, partitions[i].partition_type_guid.b, sizeof(efi_guid_t)); +#else str_type_guid = partitions[i].type_guid; bin_type_guid = gpt_e[i].partition_type_guid.b; -/*Copy the unchanged data in the backup GPT to GPT ENTRY and GPT HEAD identically*/ -#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY - memcpy(bin_type_guid, str_type_guid, sizeof(efi_guid_t)); -#else if (strlen(str_type_guid)) { if (uuid_str_to_bin(str_type_guid, bin_type_guid, UUID_STR_FORMAT_GUID)) { @@ -526,12 +527,13 @@ #endif #if CONFIG_IS_ENABLED(PARTITION_UUIDS) +#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY + memcpy(gpt_e[i].unique_partition_guid.b, + partitions[i].unique_partition_guid.b, sizeof(efi_guid_t)); +#else str_uuid = partitions[i].uuid; bin_uuid = gpt_e[i].unique_partition_guid.b; -#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY - memcpy(bin_uuid, str_uuid, sizeof(efi_guid_t)); -#else if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_GUID)) { printf("Partition no. %d: invalid guid: %s\n", i, str_uuid);
diff --git a/drivers/Kconfig b/drivers/Kconfig index 7ec8962..7e5ccf3 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig
@@ -128,6 +128,8 @@ source "drivers/efuse/Kconfig" +source "drivers/ssr/Kconfig" + config PHYS_TO_BUS bool "Custom physical to bus address mapping" help
diff --git a/drivers/Makefile b/drivers/Makefile index 0b60dad..010203b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_AML_DRIVER) += amlogic/ obj-$(CONFIG_SPI_NAND) += mtd/nand/spi-nand/ obj-$(CONFIG_MESON_NFC) += mtd/nand/raw/aml_nand/ +obj-$(CONFIG_SCHUMACHER_SSR) += ssr/ ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index e719c38..d383ab1 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig
@@ -30,10 +30,24 @@ - single and multi-channel conversion mode config SARADC_MESON - bool "Enable Amlogic Meson SARADC driver" + bool imply REGMAP + +config SARADC_MESON_G12A + bool "Enable Amlogic Meson-G12A SARADC driver" + select SARADC_MESON help - This enables driver for Amlogic Meson SARADC. + This enables driver for Amlogic Meson-G12A SARADC. + It provides: + - 8 analog input channels + - 1O or 12 bits resolution + - Up to 1MSPS of sample rate + +config SARADC_MESON_C2 + bool "Enable Amlogic Meson-C2 SARADC driver" + select SARADC_MESON + help + This enables driver for Amlogic Meson-C2 SARADC. It provides: - 8 analog input channels - 1O or 12 bits resolution
diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index c1387f3..dcb5628 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile
@@ -8,5 +8,7 @@ obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o obj-$(CONFIG_ADC_SANDBOX) += sandbox.o obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o -obj-$(CONFIG_SARADC_MESON) += meson-saradc.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o +obj-$(CONFIG_SARADC_MESON) += meson-saradc.o +obj-$(CONFIG_SARADC_MESON_C2) += meson-saradc-c2.o +obj-$(CONFIG_SARADC_MESON_G12A) += meson-saradc-g12a.o
diff --git a/drivers/adc/meson-saradc-c2.c b/drivers/adc/meson-saradc-c2.c new file mode 100644 index 0000000..88883fe --- /dev/null +++ b/drivers/adc/meson-saradc-c2.c
@@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <dm.h> +#include <amlogic/saradc.h> +#include <asm/io.h> + +#define SARADC_C2_DISCARD_DATA_CNT 30 +#define SARADC_C2_SAVE_DATA_CNT 1 + +#define SARADC_C2_FIFO_RD 0x18 + #define SARADC_C2_FIFO_RD_CHAN_ID_SHIFT (22) + #define SARADC_C2_FIFO_RD_CHAN_ID_MASK GENMASK(24, 22) + #define SARADC_C2_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(21, 0) + +#define SARADC_C2_REG11 0x2c + #define SARADC_C2_REG11_CALIB_FACTOR_MASK GENMASK(18, 12) + +#define SARADC_C2_REG13 0x34 + #define SARADC_C2_REG13_VREF_SEL BIT(19) + +#define SARADC_C2_CH0_CTRL1 0x4c + #define SARADC_C2_CH0_CTRL1_CHAN_MUX_SEL_MASK GENMASK(23, 21) + #define SARADC_C2_CH0_CTRL1_CHAN_MUX_SEL_SHIFT (21) + #define SARADC_C2_CH0_CTRL1_AUX_DIFF_EN BIT(17) + #define SARADC_C2_CH0_CTRL1_AUX_MODE_SEL BIT(0) + +#define SARADC_C2_CH0_CTRL2 0x50 +#define SARADC_C2_CH0_CTRL3 0x54 + +/* + * bit[19] = 0 default; 0=vref_buf, 1=avdd + * bit[18] = 0 default; 0=vref_buf, 1=vcm_0p9 + * bit[17] = 1 default; 1=differential; 0=single-ended + * bit[16] = 0 default; 0=vbg, 1=vcm_0p9 + * bit[0] = 0 default; 0=new continuous mode; 1=normal mode + */ +static void meson_c2_enable_decim_filter(struct meson_saradc *priv, int ch, + unsigned int mode) +{ + int reg_off; + + reg_off = ch * 12; + clrsetbits_le32(priv->base + SARADC_C2_CH0_CTRL1 + reg_off, + SARADC_C2_CH0_CTRL1_AUX_DIFF_EN, 0); + + if (mode & ADC_CAPACITY_DECIM_FILTER) { + clrsetbits_le32(priv->base + SARADC_C2_CH0_CTRL1 + reg_off, + SARADC_C2_CH0_CTRL1_AUX_MODE_SEL, + 0); + } else { + clrsetbits_le32(priv->base + SARADC_C2_CH0_CTRL1 + reg_off, + SARADC_C2_CH0_CTRL1_AUX_MODE_SEL, + SARADC_C2_CH0_CTRL1_AUX_MODE_SEL); + } + + writel(SARADC_C2_DISCARD_DATA_CNT, priv->base + SARADC_C2_CH0_CTRL2 + reg_off); + writel(SARADC_C2_SAVE_DATA_CNT, priv->base + SARADC_C2_CH0_CTRL3 + reg_off); +} + +static void meson_c2_set_ref_voltage(struct meson_saradc *priv, + unsigned int mode) +{ + if (mode & ADC_CAPACITY_HIGH_PRECISION_VREF) { + if (readl(priv->base + SARADC_C2_REG11) & + SARADC_C2_REG11_CALIB_FACTOR_MASK) { + clrsetbits_le32(priv->base + SARADC_C2_REG13, + SARADC_C2_REG13_VREF_SEL, + SARADC_C2_REG13_VREF_SEL); + } else { + clrsetbits_le32(priv->base + SARADC_C2_REG13, + SARADC_C2_REG13_VREF_SEL, + 0); + pr_notice("calib factor is null,\ + select the vdda as vref\n"); + } + } else { + clrsetbits_le32(priv->base + SARADC_C2_REG13, + SARADC_C2_REG13_VREF_SEL, + SARADC_C2_REG13_VREF_SEL); + } +} + +static void meson_c2_set_ch7_mux(struct meson_saradc *priv, int ch, int mux) +{ + clrsetbits_le32(priv->base + SARADC_C2_CH0_CTRL1 + ch * 12, + SARADC_C2_CH0_CTRL1_CHAN_MUX_SEL_MASK, + (mux & 0x7) << SARADC_C2_CH0_CTRL1_CHAN_MUX_SEL_SHIFT); +} + +static int meson_c2_get_fifo_channel(int val) +{ + return (val >> SARADC_C2_FIFO_RD_CHAN_ID_SHIFT) & 0x7; +} + +static int meson_c2_get_fifo_data(struct meson_saradc *priv, + struct adc_uclass_platdata *uc_pdata, int val) +{ + unsigned int data; + + if (priv->current_mode & ADC_CAPACITY_DECIM_FILTER) { + /* return the 22-bit sampling value */ + data = val & ((1 << SARADC_22BIT) - 1); + + //check whether data is negative + if ((data >> (SARADC_22BIT - 1)) == 1) + data = data - (1 << SARADC_22BIT); + //convert to unsigned int + data = (data + (1 << (SARADC_22BIT - 1))); + } else { + /* return the 10-bit sampling value */ + data = val & uc_pdata->data_mask; + if (priv->data->resolution == SARADC_12BIT) + data = data >> 2; + } + + return data; +} + +static struct meson_saradc_diff_ops meson_c2_diff_ops = { + .enable_decim_filter = meson_c2_enable_decim_filter, + .set_ref_voltage = meson_c2_set_ref_voltage, + .get_fifo_channel = meson_c2_get_fifo_channel, + .set_ch7_mux = meson_c2_set_ch7_mux, + .get_fifo_data = meson_c2_get_fifo_data, +}; + +struct meson_saradc_data meson_saradc_c2_data = { + .has_bl30_integration = true, + .self_test_channel = SARADC_CH_SELF_TEST, + .num_channels = MESON_SARADC_CH_MAX, + .resolution = SARADC_12BIT, + .dops = &meson_c2_diff_ops, + .capacity = ADC_CAPACITY_AVERAGE | + ADC_CAPACITY_HIGH_PRECISION_VREF | + ADC_CAPACITY_DECIM_FILTER, + /* There are 2 reasons for showing down saradc clock in C2: + * 1. To save cost, there is no input buffer before saradc. + * The value of inside resister of input source can not be too high. + * And resister value which can be tolerant is inversely of + * frequency of saradc clock. + * 2. The drive capability of channel 7 internal input is too weak. + */ + .clock_rate = 600000, +}; + +static const struct udevice_id meson_c2_saradc_ids[] = { + { + .compatible = "amlogic,meson-c2-saradc", + .data = (ulong)&meson_saradc_c2_data, + }, + { } +}; + +U_BOOT_DRIVER(meson_c2_saradc) = { + .name = "meson_c2_saradc", + .id = UCLASS_ADC, + .of_match = meson_c2_saradc_ids, + .ops = &meson_saradc_ops, + .probe = meson_saradc_probe, + .remove = meson_saradc_remove, + .ofdata_to_platdata = meson_saradc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct meson_saradc), +};
diff --git a/drivers/adc/meson-saradc-g12a.c b/drivers/adc/meson-saradc-g12a.c new file mode 100644 index 0000000..10d3d62 --- /dev/null +++ b/drivers/adc/meson-saradc-g12a.c
@@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <dm.h> +#include <amlogic/saradc.h> +#include <asm/io.h> + +#define SARADC_REG3 0x0c + #define SARADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23) + #define SARADC_REG3_CTRL_CHAN7_MUX_SEL_SHIFT (23) + +#define SARADC_FIFO_RD 0x18 + #define SARADC_FIFO_RD_CHAN_ID_SHIFT (12) + #define SARADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12) + #define SARADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0) + +#define SARADC_REG11 0x2c + #define SARADC_REG11_VREF_SEL BIT(0) + #define SARADC_REG11_EOC BIT(1) + #define SARADC_REG11_VREF_EN BIT(5) + #define SARADC_REG11_CMV_SEL BIT(6) + #define SARADC_REG11_BANDGAP_EN BIT(13) + +#define SARADC_REG13 0x34 + #define SARADC_REG13_CALIB_FACTOR_MASK GENMASK(13, 8) + +static void meson_g12a_extra_init(struct meson_saradc *priv) +{ + clrsetbits_le32(priv->base + SARADC_REG11, + SARADC_REG11_CMV_SEL | + SARADC_REG11_VREF_EN | + SARADC_REG11_EOC | + SARADC_REG11_BANDGAP_EN, + (priv->data->reg11_cmv_sel ? + SARADC_REG11_CMV_SEL : 0) | + (priv->data->reg11_vref_en ? + SARADC_REG11_VREF_EN : 0) | + (priv->data->reg11_eoc ? + SARADC_REG11_EOC : 0) | + SARADC_REG11_BANDGAP_EN); +} + +static void meson_g12a_set_ref_voltage(struct meson_saradc *priv, + unsigned int mode) +{ + if (mode & ADC_CAPACITY_HIGH_PRECISION_VREF) { + if (readl(priv->base + SARADC_REG13) & + SARADC_REG13_CALIB_FACTOR_MASK) { + /* select the internal voltage as reference voltage */ + clrsetbits_le32(priv->base + SARADC_REG11, + SARADC_REG11_VREF_SEL, 0); + } else { + /* select the VDDA as reference voltage */ + clrsetbits_le32(priv->base + SARADC_REG11, + SARADC_REG11_VREF_SEL, + SARADC_REG11_VREF_SEL); + + pr_notice("calib factor is null,\ + select the vdda as vref\n"); + } + } else { + /* select the VDDA as reference voltage */ + clrsetbits_le32(priv->base + SARADC_REG11, + SARADC_REG11_VREF_SEL, + SARADC_REG11_VREF_SEL); + } + + +} + +static int meson_g12a_get_fifo_channel(int val) +{ + return (val >> SARADC_FIFO_RD_CHAN_ID_SHIFT) & 0x7; +} + +static void meson_g12a_set_ch7_mux(struct meson_saradc *priv, int ch, int mux) +{ + clrsetbits_le32(priv->base + SARADC_REG3, + SARADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, + (mux & 0x7) << SARADC_REG3_CTRL_CHAN7_MUX_SEL_SHIFT); +} + +static int meson_g12a_get_fifo_data(struct meson_saradc *priv, + struct adc_uclass_platdata *uc_pdata, int val) +{ + unsigned int data; + + data = val & uc_pdata->data_mask; + + /* return the 10-bit sampling value */ + if (priv->data->resolution == SARADC_12BIT) + data = data >> 2; + + return data; +} + +static struct meson_saradc_diff_ops meson_g12a_diff_ops = { + .extra_init = meson_g12a_extra_init, + .set_ref_voltage = meson_g12a_set_ref_voltage, + .get_fifo_channel = meson_g12a_get_fifo_channel, + .set_ch7_mux = meson_g12a_set_ch7_mux, + .get_fifo_data = meson_g12a_get_fifo_data, +}; + +struct meson_saradc_data meson_saradc_g12a_data = { + .reg3_ring_counter_disable = BIT_HIGH, + .reg11_vref_en = BIT_LOW, + .reg11_cmv_sel = BIT_LOW, + .reg11_eoc = BIT_HIGH, + .has_bl30_integration = true, + .self_test_channel = SARADC_CH_SELF_TEST, + .num_channels = MESON_SARADC_CH_MAX, + .resolution = SARADC_12BIT, + .dops = &meson_g12a_diff_ops, + .capacity = ADC_CAPACITY_AVERAGE | + ADC_CAPACITY_HIGH_PRECISION_VREF, + .clock_rate = 1200000, +}; + +static const struct udevice_id meson_g12a_saradc_ids[] = { + { + .compatible = "amlogic,meson-g12a-saradc", + .data = (ulong)&meson_saradc_g12a_data, + }, + { } +}; + +U_BOOT_DRIVER(meson_g12a_saradc) = { + .name = "meson_g12a_saradc", + .id = UCLASS_ADC, + .of_match = meson_g12a_saradc_ids, + .ops = &meson_saradc_ops, + .probe = meson_saradc_probe, + .remove = meson_saradc_remove, + .ofdata_to_platdata = meson_saradc_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct meson_saradc), +};
diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c index 6d0eeb6..be24be3 100644 --- a/drivers/adc/meson-saradc.c +++ b/drivers/adc/meson-saradc.c
@@ -56,8 +56,6 @@ #define SARADC_REG3 0x0c #define SARADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27) #define SARADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26) - #define SARADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23) - #define SARADC_REG3_CTRL_CHAN7_MUX_SEL_SHIFT (23) #define SARADC_REG3_ADC_EN BIT(21) #define SARADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) #define SARADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) @@ -73,9 +71,6 @@ #define SARADC_LAST_RD 0x14 #define SARADC_FIFO_RD 0x18 - #define SARADC_FIFO_RD_CHAN_ID_SHIFT (12) - #define SARADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12) - #define SARADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0) #define SARADC_AUX_SW 0x1c #define SARADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \ @@ -92,73 +87,6 @@ #define SARADC_DELTA_10 0x28 -#define SARADC_REG11 0x2c - #define SARADC_REG11_VREF_SEL BIT(0) - #define SARADC_REG11_EOC BIT(1) - #define SARADC_REG11_VREF_EN BIT(5) - #define SARADC_REG11_CMV_SEL BIT(6) - #define SARADC_REG11_BANDGAP_EN BIT(13) - -#define SARADC_REG13 0x34 - #define SARADC_REG13_CALIB_FACTOR_MASK GENMASK(13, 8) - -enum MESON_SARADC_AVG_MODE { - NO_AVERAGING = 0x0, - MEAN_AVERAGING = 0x1, - MEDIAN_AVERAGING = 0x2, -}; - -enum MESON_SARADC_NUM_SAMPLES { - ONE_SAMPLE = 0x0, - TWO_SAMPLES = 0x1, - FOUR_SAMPLES = 0x2, - EIGHT_SAMPLES = 0x3, -}; - -enum MESON_SARADC_RESOLUTION { - SARADC_10BIT = 10, - SARADC_12BIT = 12, -}; - -enum MESON_SARADC_BIT_STATE { - BIT_LOW = 0, - BIT_HIGH = 1, -}; - -/* - * struct meson_saradc_data - describe the differences of different platform - * - * @reg3_ring_counter_disable: to disable continuous ring counter. - * gxl and later: 1; others(gxtvbb etc): 0 - * @reg11_vref_en: g12a and later: 0; others(axg etc): 1 - * @reg11_cmv_sel: g12a and later: 0; others(axg etc): 1 - * @reg11_eoc: g12a and later: 1; others(axg etc): 0 - * @has_bl30_integration: - * @num_channels: the number of adc channels - * @self_test_channel: channel of self-test - * @resolution: gxl and later: 12bit; others(gxtvbb etc): 10bit - */ -struct meson_saradc_data { - bool reg3_ring_counter_disable; - bool reg11_vref_en; - bool reg11_cmv_sel; - bool reg11_eoc; - bool has_bl30_integration; - unsigned char self_test_channel; - unsigned char num_channels; - unsigned int resolution; -}; - -struct meson_saradc { - phys_addr_t base; - int active_channel; - struct clk xtal; - struct clk adc_mux; - struct clk adc_div; - struct clk adc_gate; - struct meson_saradc_data *data; -}; - static int meson_saradc_clk_init(struct udevice *dev) { struct meson_saradc *priv = dev_get_priv(dev); @@ -194,9 +122,9 @@ return ret; } - ret = clk_set_rate(&priv->adc_div, 1200000); + ret = clk_set_rate(&priv->adc_div, priv->data->clock_rate); if (ret) { - pr_err("%s: failed to set rate to 1.2M\n", dev->name); + pr_err("%s: failed to set rate\n", dev->name); return ret; } @@ -230,18 +158,8 @@ static void meson_saradc_hw_enable(struct meson_saradc *priv) { - clrsetbits_le32(priv->base + SARADC_REG11, - SARADC_REG11_CMV_SEL | - SARADC_REG11_VREF_EN | - SARADC_REG11_EOC | - SARADC_REG11_BANDGAP_EN, - (priv->data->reg11_cmv_sel ? - SARADC_REG11_CMV_SEL : 0) | - (priv->data->reg11_vref_en ? - SARADC_REG11_VREF_EN : 0) | - (priv->data->reg11_eoc ? - SARADC_REG11_EOC : 0) | - SARADC_REG11_BANDGAP_EN); + if (priv->data->dops->extra_init) + priv->data->dops->extra_init(priv); clk_enable(&priv->adc_gate); @@ -340,10 +258,23 @@ SARADC_REG0_SAMPLING_START); } +static int meson_saradc_check_mode(struct meson_saradc *priv, unsigned int mode) +{ + if (mode & ~priv->data->capacity) + return -EINVAL; + + return 0; +} + static int meson_saradc_set_mode(struct udevice *dev, int ch, unsigned int mode) { + int ret; struct meson_saradc *priv = dev_get_priv(dev); + ret = meson_saradc_check_mode(priv, mode); + if (ret < 0) + return ret; + if (mode & ADC_CAPACITY_AVERAGE) { clrsetbits_le32(priv->base + SARADC_AVG_CNTL, SARADC_AVG_CNTL_NUM_SAMPLES_MASK(ch), @@ -358,32 +289,13 @@ NO_AVERAGING << SARADC_AVG_CNTL_AVG_MODE_SHIFT(ch)); } - /* - * the precision of internal voltage is approximately equal to 10mv, - * but the VDDA is approximately equal to 36mv(2% x 1800mv). - */ - if (mode & ADC_CAPACITY_HIGH_PRECISION_VREF) { - if (readl(priv->base + SARADC_REG13) & - SARADC_REG13_CALIB_FACTOR_MASK) { - /* select the internal voltage as reference voltage */ - clrsetbits_le32(priv->base + SARADC_REG11, - SARADC_REG11_VREF_SEL, 0); - } else { - /* select the VDDA as reference voltage */ - clrsetbits_le32(priv->base + SARADC_REG11, - SARADC_REG11_VREF_SEL, - SARADC_REG11_VREF_SEL); + priv->data->dops->set_ref_voltage(priv, mode); - pr_notice("%s: calib factor is null, \ - please set it in bl30 first\n", - dev->name); - } - } else { - /* select the VDDA as reference voltage */ - clrsetbits_le32(priv->base + SARADC_REG11, - SARADC_REG11_VREF_SEL, - SARADC_REG11_VREF_SEL); - } + priv->current_mode = mode; + + if (priv->data->dops->enable_decim_filter) + priv->data->dops->enable_decim_filter(priv, ch, + priv->current_mode); return 0; } @@ -439,7 +351,8 @@ return -EBUSY; val = readl(priv->base + SARADC_FIFO_RD); - fifo_ch = (val >> SARADC_FIFO_RD_CHAN_ID_SHIFT) & 0x7; + + fifo_ch = priv->data->dops->get_fifo_channel(val); if (fifo_ch != channel) { pr_err("%s: channel mismatch: exp[%d] - act[%d]\n", @@ -447,11 +360,7 @@ return -EINVAL; } - *data = val & uc_pdata->data_mask; - - /* return the 10-bit sampling value */ - if (priv->data->resolution == SARADC_12BIT) - *data = *data >> 2; + *data = priv->data->dops->get_fifo_data(priv, uc_pdata, val); priv->active_channel = -1; @@ -471,14 +380,12 @@ return -EINVAL; } - clrsetbits_le32(priv->base + SARADC_REG3, - SARADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, - (mux & 0x7) << SARADC_REG3_CTRL_CHAN7_MUX_SEL_SHIFT); + priv->data->dops->set_ch7_mux(priv, channel, mux); return 0; } -static const struct adc_ops meson_saradc_ops = { +const struct adc_ops meson_saradc_ops = { .set_mode = meson_saradc_set_mode, .start_channel = meson_saradc_start_channel, .channel_data = meson_saradc_channel_data, @@ -486,7 +393,7 @@ .select_input_voltage = meson_saradc_select_input_voltage, }; -static int meson_saradc_probe(struct udevice *dev) +int meson_saradc_probe(struct udevice *dev) { struct meson_saradc *priv = dev_get_priv(dev); int ret; @@ -510,7 +417,7 @@ return 0; } -static int meson_saradc_remove(struct udevice *dev) +int meson_saradc_remove(struct udevice *dev) { struct meson_saradc *priv = dev_get_priv(dev); @@ -519,7 +426,7 @@ return 0; } -static int meson_saradc_ofdata_to_platdata(struct udevice *dev) +int meson_saradc_ofdata_to_platdata(struct udevice *dev) { struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); struct meson_saradc *priv = dev_get_priv(dev); @@ -534,33 +441,3 @@ return 0; } - -static struct meson_saradc_data meson_saradc_g12a_data = { - .reg3_ring_counter_disable = BIT_HIGH, - .reg11_vref_en = BIT_LOW, - .reg11_cmv_sel = BIT_LOW, - .reg11_eoc = BIT_HIGH, - .has_bl30_integration = true, - .self_test_channel = SARADC_CH_SELF_TEST, - .num_channels = MESON_SARADC_CH_MAX, - .resolution = SARADC_12BIT, -}; - -static const struct udevice_id meson_saradc_ids[] = { - { - .compatible = "amlogic,meson-g12a-saradc", - .data = (ulong)&meson_saradc_g12a_data, - }, - { } -}; - -U_BOOT_DRIVER(meson_saradc) = { - .name = "meson_saradc", - .id = UCLASS_ADC, - .of_match = meson_saradc_ids, - .ops = &meson_saradc_ops, - .probe = meson_saradc_probe, - .remove = meson_saradc_remove, - .ofdata_to_platdata = meson_saradc_ofdata_to_platdata, - .priv_auto_alloc_size = sizeof(struct meson_saradc), -};
diff --git a/drivers/amlogic/Kconfig b/drivers/amlogic/Kconfig index c8746f8..91fc951 100644 --- a/drivers/amlogic/Kconfig +++ b/drivers/amlogic/Kconfig
@@ -13,4 +13,6 @@ source "drivers/amlogic/power/Kconfig" +source "drivers/amlogic/provision/Kconfig" + endmenu
diff --git a/drivers/amlogic/keymanage/Kconfig b/drivers/amlogic/keymanage/Kconfig index d4cc261..0074ef2 100644 --- a/drivers/amlogic/keymanage/Kconfig +++ b/drivers/amlogic/keymanage/Kconfig
@@ -12,4 +12,9 @@ select SHA256 help "security key wrapper for APIs bl31" + config KEYMAN_PROVISION_KEY + bool "Amlogic burn provision key" + default y + help + "provision key wrapper for burn tool" endif #if UNIFY_KEY_MANAGE
diff --git a/drivers/amlogic/keymanage/Makefile b/drivers/amlogic/keymanage/Makefile index b54587f..08dd44e 100644 --- a/drivers/amlogic/keymanage/Makefile +++ b/drivers/amlogic/keymanage/Makefile
@@ -28,4 +28,5 @@ aml_key_manage-$(CONFIG_OF_LIBFDT) += km_dts.o aml_key_manage-$(CONFIG_EFUSE) += km_efuse_key.o aml_key_manage-$(CONFIG_AML_SECURITY_KEY) += km_secure_key.o +aml_key_manage-$(CONFIG_KEYMAN_PROVISION_KEY) += km_provision_key.o
diff --git a/drivers/amlogic/keymanage/amlkey_if.h b/drivers/amlogic/keymanage/amlkey_if.h deleted file mode 100644 index 81f1c7c..0000000 --- a/drivers/amlogic/keymanage/amlkey_if.h +++ /dev/null
@@ -1,45 +0,0 @@ -/* - * \file amlkey_if.h - * \brief APIs of secure key for users - * - * \version 1.0.0 - * \date 15/07/10 - * \author Sam.Wu <yihui.wu@amlgic.com> - * - * Copyright (c) 2015 Amlogic. All Rights Reserved. - * - */ -#ifndef __AMLKEY_IF_H__ -#define __AMLKEY_IF_H__ - -#define AMLKEY_NAME_LEN_MAX (80) -//1.init -int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type); - -//2. query if the key already programmed, exsit 1, non 0 -int32_t amlkey_isexsit(const uint8_t * name); - -//3. query attr, key must exsit before those functions were called. - //3.1 whether the prgrammed key is secure, secure 1, non 0 -int32_t amlkey_issecure(const uint8_t * name); - //3.2 whether the prgrammed key is encrypt, encrypt 1, non 0 -int32_t amlkey_isencrypt(const uint8_t * name); - -//4. actual bytes of key value -ssize_t amlkey_size(const uint8_t *name); - -//5. read non-secure key in bytes, return byets readback actully. -ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) ; - -//6.write key with attribute in bytes , return byets readback actully - //attr: bit0: secure/non-secure; - // bit8: encrypt/non-encrypt -#define UNIFYKEY_ATTR_SECURE_MASK (1<<0) -#define UNIFYKEY_ATTR_ENCRYPT_MASK (1<<8) -ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr); - -//7. get the hash value of programmed secure key | 32bytes length, sha256 -int32_t amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash); - -#endif// #ifndef __AMLKEY_IF_H__ -
diff --git a/drivers/amlogic/keymanage/key_manage.h b/drivers/amlogic/keymanage/key_manage.h index b573aca..511b407 100644 --- a/drivers/amlogic/keymanage/key_manage.h +++ b/drivers/amlogic/keymanage/key_manage.h
@@ -11,6 +11,7 @@ KEY_M_EFUSE_NORMAL, KEY_M_SECURE_KEY, //secure nandkey/emmckey KEY_M_NORAML_KEY, //non-secure nandkey/emmckey + KEY_M_PROVISION_KEY, //provision key KEY_M_MAX_DEV, };
diff --git a/drivers/amlogic/keymanage/key_manage_i.h b/drivers/amlogic/keymanage/key_manage_i.h index b570ae6..ffa2543 100644 --- a/drivers/amlogic/keymanage/key_manage_i.h +++ b/drivers/amlogic/keymanage/key_manage_i.h
@@ -46,5 +46,14 @@ int keymanage_secukey_can_read(const char* keyname); int keymanage_secukey_read(const char* keyname, void* databuf, unsigned buflen); +//provision key ops +int keymanage_provision_init(const char *buf, int len); +int keymanage_provision_exit(void); +int keymanage_provision_write(const char *keyname, const void* keydata, unsigned int datalen); +ssize_t keymanage_provision_size(const char* keyname); +int keymanage_provision_exist(const char* keyname); +int keymanage_provision_query_can_read(const char* keyname); +int keymanage_provision_read(const char *keyname, void* databuf, const unsigned bufSz); + #endif//#ifndef __KEY_MANAGE_I_H__
diff --git a/drivers/amlogic/keymanage/key_unify.c b/drivers/amlogic/keymanage/key_unify.c index 0afcfd5..b3cdc93 100644 --- a/drivers/amlogic/keymanage/key_unify.c +++ b/drivers/amlogic/keymanage/key_unify.c
@@ -57,12 +57,34 @@ }; #endif//#if defined(CONFIG_EFUSE) +#if defined(CONFIG_KEYMAN_PROVISION_KEY) +static KmDevKeyOps _provisionKeyOps = { + .pInitFunc = keymanage_provision_init , + .pUninitFunc = keymanage_provision_exit , + .pWriteFunc = keymanage_provision_write , + .pGetSize = keymanage_provision_size , + .pKeyExist = keymanage_provision_exist , + .pKeyCanRead = keymanage_provision_query_can_read , + .pReadFunc = keymanage_provision_read , + + .can_overwrite = 1 , +}; +#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY) + #define _KM_DEV_INDEX_SECUREKEY 0 +#define _KM_DEV_INDEX_PROVISION 1 +#if defined(CONFIG_KEYMAN_PROVISION_KEY) +#define _KM_DEV_INDEX_EFUSE 2 +#else #define _KM_DEV_INDEX_EFUSE 1 +#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY) static KmDevKeyOps* _km_devKeyOpsArr[] = { [_KM_DEV_INDEX_SECUREKEY] = &_SecukeyOps, -#if 1 +#if defined(CONFIG_KEYMAN_PROVISION_KEY) + [_KM_DEV_INDEX_PROVISION] = &_provisionKeyOps, +#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY) +#if defined(CONFIG_EFUSE) [_KM_DEV_INDEX_EFUSE] = &_efuseKeyOps, #endif//#if defined(CONFIG_EFUSE) }; @@ -175,6 +197,12 @@ KM_ERR("Seed is 0 err\n"); return __LINE__; } + + if (amlkey_if_init(dtbLoadaddr)) { + KM_ERR("amlkey interface init fail\n"); + return __LINE__; + } + for (i=0; i < _KM_DEVCNT; i++) { KmDevKeyOps* theDevOps = _km_devKeyOpsArr[i]; @@ -232,6 +260,10 @@ } break; + case KEY_M_PROVISION_KEY: + theDevOps = _km_devKeyOpsArr[_KM_DEV_INDEX_PROVISION]; + break; + case KEY_M_UNKNOW_DEV: default: KM_ERR("key %s not know device %d\n", keyname, theDevice); @@ -327,7 +359,6 @@ int key_unify_query_size(const char* keyname, ssize_t* keysize) { - int ret = 0; const KmDevKeyOps* theDevOps = NULL; theDevOps = _get_km_ops_by_name(keyname); @@ -336,11 +367,13 @@ return __LINE__; } - ret = theDevOps->pKeyCanRead(keyname); +#if 0 + int ret = theDevOps->pKeyCanRead(keyname); if (!ret) { KM_ERR("key[%s] can't read as it's secure\n", keyname); return __LINE__; } +#endif *keysize = theDevOps->pGetSize(keyname);
diff --git a/drivers/amlogic/keymanage/km_dts.c b/drivers/amlogic/keymanage/km_dts.c index 27ab628..09f203e 100644 --- a/drivers/amlogic/keymanage/km_dts.c +++ b/drivers/amlogic/keymanage/km_dts.c
@@ -11,9 +11,10 @@ #define UNIFYKEY_DATAFORMAT_HEXASCII "hexascii" #define UNIFYKEY_DATAFORMAT_ALLASCII "allascii" -#define UNIFYKEY_DEVICE_EFUSEKEY "efuse" -#define UNIFYKEY_DEVICE_NORMAL "normal" -#define UNIFYKEY_DEVICE_SECURESKEY "secure" +#define UNIFYKEY_DEVICE_EFUSEKEY "efuse" +#define UNIFYKEY_DEVICE_NORMAL "normal" +#define UNIFYKEY_DEVICE_SECURESKEY "secure" +#define UNIFYKEY_DEVICE_PROVISIONKEY "provision" #define UNIFYKEY_PERMIT_READ "read" #define UNIFYKEY_PERMIT_WRITE "write" @@ -21,6 +22,8 @@ static struct key_info_t unify_key_info={.key_num =0, .key_flag = 0, .efuse_version = -1, .encrypt_type = 0}; static struct key_item_t *unifykey_item=NULL; +static struct key_item_t* _defProvisonItem =NULL;//keyname start with "KEY_PROVISION_" and device is "provison" +#define _PROVSION_DEFAULT_KEY_NAME "KEY_PROVISION_XXX" static int unifykey_item_verify_check(struct key_item_t *key_item) { @@ -49,6 +52,10 @@ return pre_item; } } + + if (!strncmp(_PROVSION_DEFAULT_KEY_NAME, name, strlen(_PROVSION_DEFAULT_KEY_NAME) - 3)) { + return _defProvisonItem; + } return NULL; } @@ -220,14 +227,6 @@ strcpy(temp_item->keyType, propdata); } -#if 0 - propdata = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "key-dataformat",NULL); - if (!propdata) { - KM_ERR("%s get key-dataformat fail at key_%d\n",item_path, id); - return __LINE__; - } -#endif - prop = (struct fdt_property*)fdt_get_property((const void *)dt_addr,nodeoffset,"key-permit",NULL) ; if (!prop) { KM_ERR("%s get key-permit fail at key_%d\n",item_path, id); @@ -286,7 +285,8 @@ { int ret = 0; int child; - int nodeoffset; + int nodeoffset, provisionOffset; + int unifykeyNum = 0, provisionNum = 0; char *punifykey_num, *encrypt_type; if (fdt_check_header(dt_addr)!= 0) { @@ -309,8 +309,16 @@ unify_key_info.key_num = 0; fdt_for_each_subnode(child, dt_addr, nodeoffset) { - unify_key_info.key_num++; + unifykeyNum++; } + + provisionOffset = fdt_path_offset(dt_addr, "/provisionkey"); + if (provisionOffset >= 0) { + fdt_for_each_subnode(child, dt_addr, provisionOffset) { + provisionNum++; + } + } + unify_key_info.key_num = unifykeyNum + provisionNum; KM_MSG("key_num: %d\n", unify_key_info.key_num); unify_key_info.encrypt_type = -1; @@ -323,7 +331,7 @@ KM_ERR("unifykey-num is not configured\n"); return __LINE__; } - if (unify_key_info.key_num > 32) { + if (unify_key_info.key_num > 256) { KM_ERR("Cfg key_num is %d > 32,pls check!\n", unify_key_info.key_num); return __LINE__; } @@ -335,9 +343,55 @@ unifykey_item = (struct key_item_t*)malloc(keyInfBufLen); memset(unifykey_item, 0 , keyInfBufLen); - ret = unifykey_item_create(dt_addr,unify_key_info.key_num); + ret = unifykey_item_create(dt_addr,unifykeyNum); unify_key_info.key_flag = ret ? 0 : 1; + if (provisionOffset >= 0) + { + KM_DBG("dts: in find /provisionkey.\n"); + + int defPermits = 0; + const struct fdt_property *prop = fdt_get_property(dt_addr, provisionOffset,"key-permit-default",NULL) ; + if (prop) { + const int propLen = prop->len > 512 ? strnlen(prop->data, 512) : prop->len; + if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_READ)) { + defPermits |= KEY_M_PERMIT_READ; + } + if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_WRITE)) { + defPermits |= KEY_M_PERMIT_WRITE; + } + if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_DEL)) { + defPermits |= KEY_M_PERMIT_DEL; + } + } + + int node = 0; + int id = unifykeyNum; + int szlen = 0; + fdt_for_each_subnode(node, dt_addr, provisionOffset) { + int len = 0; + const char* keyName = fdt_get_name(dt_addr, node, &len); + KM_DBG("provisionkey[%s] len %d\n", keyName, len); + + struct key_item_t *pItem= unifykey_item + id; + + szlen = strnlen(keyName, KEY_UNIFY_NAME_LEN - 1); + memcpy(pItem->name, keyName, szlen); + if (szlen < KEY_UNIFY_NAME_LEN) pItem->name[szlen] = '\0'; + + strcpy(pItem->keyType, "raw"); + pItem->dev = KEY_M_PROVISION_KEY; + pItem->permit = defPermits; + pItem->id = id++; + if (!strcmp(_PROVSION_DEFAULT_KEY_NAME, keyName)) _defProvisonItem = pItem; + } + + if ((node < 0) && (node != -FDT_ERR_NOTFOUND)) { + KM_ERR("in parse /provisionkey, err(%s)\n", fdt_strerror(node)); + return __LINE__; + } + } + return ret; }
diff --git a/drivers/amlogic/keymanage/km_provision_key.c b/drivers/amlogic/keymanage/km_provision_key.c new file mode 100644 index 0000000..30c46b9 --- /dev/null +++ b/drivers/amlogic/keymanage/km_provision_key.c
@@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include "key_manage_i.h" +#define _CMD_BUF_LEN 512 +static char _cmdBuf[_CMD_BUF_LEN]; + +int keymanage_provision_init(const char *buf, int len) +{ + KM_DBG("f(%s)L%d\n", __func__, __LINE__); + return 0; +} + +int keymanage_provision_exit(void) +{ + KM_DBG("f(%s)L%d\n", __func__, __LINE__); + return 0; +} + +//must be hexdata if stored in efuse +int keymanage_provision_write(const char *keyname, const void* keydata, unsigned int datalen) +{ + KM_DBG("f(%s)L%d\n", __func__, __LINE__); + + snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision write %s 0x%p 0x%x", keyname, keydata, datalen); + int iRet = run_command(_cmdBuf, 0); + KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet); + + return iRet; +} + +ssize_t keymanage_provision_size(const char* keyname) +{ + KM_DBG("f(%s)L%d\n", __func__, __LINE__); + uint32_t retBuf[12]; + snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s 0x%p", keyname, retBuf); + int iRet = run_command(_cmdBuf, 0); + if (iRet) { + KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet); + return 0; + } + + return retBuf[0]; +} + +int keymanage_provision_exist(const char* keyname) +{ + KM_DBG("f(%s)L%d\n", __func__, __LINE__); + snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s", keyname); + int iRet = run_command(_cmdBuf, 0); + if (iRet) KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet); + + return !iRet; +} + +int keymanage_provision_query_can_read(const char* keyname) +{ + KM_DBG("f(%s)L%d\n", __func__, __LINE__); + + return 0;//always cannot be read +} + +//read hash instead of actual value +int keymanage_provision_read(const char *keyname, void* databuf, const unsigned bufSz) +{ + KM_DBG("f(%s)L%d\n", __func__, __LINE__); + uint32_t retBuf[12]; + snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s 0x%p", keyname, retBuf); + int iRet = run_command(_cmdBuf, 0); + if (iRet) { + KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet); + return __LINE__; + } + if (bufSz < 32) { + KM_ERR("bufsz %d not enough for sha256sum\n", bufSz); + return -__LINE__; + } + + KM_MSG("provision read return sha256sum, but not original data\n"); + memcpy(databuf, retBuf + 1, 32); + return 0;// +} +
diff --git a/drivers/amlogic/media/Kconfig b/drivers/amlogic/media/Kconfig index 543cae9..9463725 100644 --- a/drivers/amlogic/media/Kconfig +++ b/drivers/amlogic/media/Kconfig
@@ -4,7 +4,7 @@ Enable support for the Amlogic Media drivers. config AML_VOUT - bool "Driver support for video" + bool "Driver support for video output" help Enable support for amlogic video output lcd,cvbs... @@ -19,6 +19,8 @@ help Enable support for amlogic canvas driver. +source "drivers/amlogic/media/osd/Kconfig" + source "drivers/amlogic/media/common/Kconfig" source "drivers/amlogic/media/vout/Kconfig"
diff --git a/drivers/amlogic/media/canvas/canvas.c b/drivers/amlogic/media/canvas/canvas.c index 62bd1b9..e9c5d37 100644 --- a/drivers/amlogic/media/canvas/canvas.c +++ b/drivers/amlogic/media/canvas/canvas.c
@@ -22,13 +22,34 @@ #define canvas_log(fmt, args...) #endif -#define canvas_reg_read(reg) readl(DMC_REG_BASE + reg) -#define canvas_reg_write(val, reg) writel(val, (DMC_REG_BASE + reg)) +#ifndef DMC_REG_BASE +#define DMC_REG_BASE (0xFF638000L) +#endif +#define REG_CANVAS_ADDR(reg) (reg + 0L) #define CANVAS_NUM 256 static canvas_t canvasPool[CANVAS_NUM]; static int canvas_inited = 0; +static inline u32 canvas_reg_read(u32 reg) +{ + u32 val; + + if (reg > 0x10000) + val = *(volatile unsigned int *)REG_CANVAS_ADDR(reg); + else + val = readl(DMC_REG_BASE + reg); + return val; +} + +static inline void canvas_reg_write(const u32 val, u32 reg) +{ + if (reg > 0x10000) + *(volatile unsigned int *)REG_CANVAS_ADDR(reg) = (val); + else + writel(val, (DMC_REG_BASE + reg)); +} + void canvas_init(void) { int index = 0;
diff --git a/drivers/amlogic/media/common/vpp/Makefile b/drivers/amlogic/media/common/vpp/Makefile index 28a8aad..4b75097 100644 --- a/drivers/amlogic/media/common/vpp/Makefile +++ b/drivers/amlogic/media/common/vpp/Makefile
@@ -1,2 +1,2 @@ obj-$(CONFIG_AML_VPP) += vpp.o - +obj-$(CONFIG_AML_VPP) += hdr2.o
diff --git a/drivers/amlogic/media/common/vpp/hdr2.c b/drivers/amlogic/media/common/vpp/hdr2.c new file mode 100644 index 0000000..3d0c42a --- /dev/null +++ b/drivers/amlogic/media/common/vpp/hdr2.c
@@ -0,0 +1,1401 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <amlogic/cpu_id.h> +#include <malloc.h> +#include "hdr2.h" +#include "vpp_reg.h" +#include <common.h> + +int cgain_lut0[65] = { + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x4c0, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x40e, + 0x429, 0x444, 0x45f, 0x479, 0x492, 0x4ab, 0x4c3, 0x4db, 0x4f2, + 0x509, 0x520, 0x536, 0x54c, 0x561, 0x576, 0x58b, 0x59f, 0x5b3, + 0x5c0, 0x5d0, 0x5f2, 0x609, 0x620, 0x636, 0x64c, 0x661, 0x676, + 0x68b, 0x69f +}; + +int cgain_lut1[65] = { + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x40e, + 0x419, 0x424, 0x43f, 0x449, 0x452, 0x46b, 0x473, 0x48b, 0x492, + 0x4a9, 0x4b0, 0x4c6, 0x4dc, 0x4e1, 0x4f6, 0x50b, 0x51f, 0x523, + 0x530, 0x540 +}; + +int cgain_lut_bypass[65] = { + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, + 0x400, 0x400 +}; + +int cgain_lut2[65] = { + 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, + 0xc00, 0xc00, 0xc0e, 0xc79, 0xcdb, 0xd36, 0xd8b, 0xdda, 0xe25, + 0xe6b, 0xead, 0xeec, 0xf28, 0xf61, 0xf98, 0xfcc, 0xfff, 0x102f, + 0x105d, 0x108a, 0x10b5, 0x10df, 0x1107, 0x112e, 0x1154, 0x1178, 0x119c, + 0x11bf, 0x11e0, 0x1201, 0x1221, 0x1240, 0x125e, 0x127c, 0x1299, 0x12b5, + 0x12d1, 0x12ec, 0x1306, 0x1320, 0x1339, 0x1352, 0x136b, 0x1383, 0x139a, + 0x13b1, 0x13c7, 0x13de, 0x13f3, 0x1409, 0x141e, 0x1432, 0x1447, 0x145b, + 0x146e, 0x1482 +}; + +int eo_y_lut_hdr[143] = { + 132288, 136832, 165440, 181832, 193440, 202088, 210400, 216476, 221882, + 227920, 231986, 235648, 239639, 243964, 247193, 249698, 252377, 271330, + 285261, 297148, 306377, 314682, 321922, 329204, 334486, 340750, 346085, + 350369, 355325, 360734, 363991, 367697, 371896, 376636, 379400, 382389, + 385731, 389458, 393410, 395711, 398260, 401078, 404188, 407615, 410492, + 412562, 414834, 417322, 420045, 423021, 426127, 427900, 429831, 431934, + 434222, 436709, 439410, 442342, 443945, 445668, 447230, 448187, 449224, + 450344, 451555, 452864, 454277, 455803, 457449, 458988, 459945, 460977, + 462089, 463286, 464576, 465964, 467458, 469066, 470795, 472655, 474655, + 475971, 477126, 478368, 479702, 481136, 482676, 484330, 486107, 488015, + 490063, 491891, 493071, 494339, 495699, 497159, 498727, 500409, 502262, + 504308, 506503, 508381, 509646, 511003, 512460, 512934, 513098, 513279, + 513477, 513691, 513923, 514172, 514438, 514720, 515017, 515328, 515650, + 515981, 516320, 516662, 517006, 517349, 517689, 518022, 518347, 518662, + 518968, 519263, 519549, 519827, 520097, 520363, 520625, 520888, 521155, + 521431, 521727, 522054, 522431, 522871, 523371, 523881, 524287 +}; + +int eo_y_lut_hlg[143] = { + 0, 169296, 202068, 221184, 234837, 246442, 253952, 262485, 267605, + 273408, 279210, 282794, 286720, 290986, 295253, 297728, 300373, 319488, + 333141, 344746, 352256, 360789, 365909, 371712, 377514, 381098, 385024, + 389290, 393557, 396032, 398677, 401493, 404480, 407637, 410282, 412032, + 413866, 415786, 417792, 419882, 422058, 424320, 426325, 427541, 428800, + 430101, 431445, 432832, 434261, 435733, 437248, 438805, 440405, 442048, + 443050, 443914, 444800, 445706, 446634, 447584, 448554, 449546, 450560, + 451594, 452650, 453728, 454826, 455946, 457088, 458250, 459093, 459696, + 460309, 460933, 461568, 462213, 462869, 463536, 464213, 464911, 465640, + 466401, 467197, 468028, 468896, 469803, 470750, 471740, 472774, 473854, + 474982, 475648, 476264, 476907, 477579, 478281, 479014, 479780, 480580, + 481416, 482289, 483201, 484154, 485150, 486190, 487276, 488411, 489597, + 490835, 491824, 492500, 493206, 493944, 494714, 495519, 496360, 497238, + 498156, 499114, 500115, 501161, 502254, 503396, 504588, 505834, 507135, + 508199, 508909, 509651, 510426, 511236, 512081, 512965, 513888, 514852, + 515859, 516911, 518010, 519158, 520358, 521611, 522920, 524287 +}; + +int eo_y_lut_sdr[143] = { + 0, 163808, 199044, 219568, 234610, 247036, 255751, 264272, 270593, + 277939, 282430, 287163, 292441, 296593, 299792, 303278, 307054, 328697, + 344063, 354448, 364052, 372123, 379268, 384835, 391196, 395793, 399793, + 404214, 409063, 411973, 414834, 417919, 421229, 424767, 427260, 429261, + 431380, 433618, 435975, 438453, 441054, 443072, 444496, 445981, 447530, + 449142, 450817, 452556, 454360, 456229, 458163, 459457, 460489, 461555, + 462654, 463787, 464953, 466153, 467387, 468655, 469957, 471294, 472665, + 474071, 475324, 476062, 476817, 477590, 478381, 479190, 480016, 480861, + 481723, 482603, 483502, 484418, 485353, 486306, 487278, 488267, 489276, + 490302, 491348, 491966, 492507, 493057, 493618, 494187, 494766, 495354, + 495952, 496559, 497176, 497803, 498439, 499084, 499740, 500405, 501079, + 501764, 502458, 503161, 503875, 504598, 505332, 506075, 506828, 507590, + 508133, 508525, 508921, 509322, 509728, 510140, 510556, 510977, 511404, + 511835, 512272, 512713, 513160, 513611, 514068, 514530, 514997, 515469, + 515946, 516429, 516916, 517409, 517907, 518410, 518918, 519432, 519950, + 520474, 521003, 521537, 522077, 522622, 523172, 523727, 524287 +}; + +int eo_y_lut_bypass[143] = { + 0, 360448, 376832, 385024, 393216, 397312, 401408, 405504, 409600, + 411648, 413696, 415744, 417792, 419840, 421888, 423936, 425984, 434176, + 442368, 446464, 450560, 454656, 458752, 460800, 462848, 464896, 466944, + 468992, 471040, 473088, 475136, 476160, 477184, 478208, 479232, 480256, + 481280, 482304, 483328, 484352, 485376, 486400, 487424, 488448, 489472, + 490496, 491520, 492032, 492544, 493056, 493568, 494080, 494592, 495104, + 495616, 496128, 496640, 497152, 497664, 498176, 498688, 499200, 499712, + 500224, 500736, 501248, 501760, 502272, 502784, 503296, 503808, 504320, + 504832, 505344, 505856, 506368, 506880, 507392, 507904, 508160, 508416, + 508672, 508928, 509184, 509440, 509696, 509952, 510208, 510464, 510720, + 510976, 511232, 511488, 511744, 512000, 512256, 512512, 512768, 513024, + 513280, 513536, 513792, 514048, 514304, 514560, 514816, 515072, 515328, + 515584, 515840, 516096, 516352, 516608, 516864, 517120, 517376, 517632, + 517888, 518144, 518400, 518656, 518912, 519168, 519424, 519680, 519936, + 520192, 520448, 520704, 520960, 521216, 521472, 521728, 521984, 522240, + 522496, 522752, 523008, 523264, 523520, 523776, 524032, 524287 +}; + +int oe_y_lut_hdr[149] = {0, 3, 5, 8, 12, 19, 28, 41, 60, 67, 74, 80, 85, + 96, 105, 113, 120, 134, 146, 157, 167, 184, 200, 214, 227, 250, 270, + 288, 304, 332, 357, 380, 400, 435, 465, 492, 517, 559, 595, 628, 656, + 706, 749, 787, 820, 850, 878, 903, 927, 949, 970, 989, 1008, 1042, 1073, + 1102, 1129, 1154, 1177, 1199, 1219, 1258, 1292, 1324, 1354, 1381, 1407, + 1431, 1453, 1495, 1533, 1568, 1600, 1630, 1657, 1683, 1708, 1753, 1794, + 1831, 1865, 1897, 1926, 1954, 1980, 2028, 2071, 2110, 2146, 2179, 2210, + 2239, 2267, 2317, 2361, 2402, 2440, 2474, 2506, 2536, 2564, 2616, 2662, + 2704, 2742, 2778, 2810, 2841, 2870, 2922, 2969, 3011, 3050, 3086, 3119, + 3150, 3179, 3231, 3278, 3321, 3360, 3396, 3429, 3459, 3488, 3540, 3587, + 3629, 3668, 3703, 3736, 3766, 3795, 3821, 3846, 3870, 3892, 3913, 3934, + 3953, 3971, 3989, 4006, 4022, 4038, 4053, 4068, 4082, 4095 +}; + +int oe_y_lut_hlg[149] = {0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 6, 6, 6, 7, 8, 9, + 9, 10, 12, 12, 13, 15, 16, 18, 19, 21, 24, 25, 27, 30, 33, 36, 39, + 43, 48, 51, 55, 61, 67, 73, 78, 87, 96, 103, 110, 117, 123, 129, 135, + 141, 146, 151, 156, 166, 175, 183, 192, 199, 207, 214, 221, 235, 247, + 259, 271, 282, 293, 303, 313, 332, 350, 367, 384, 399, 414, 429, 443, + 470, 495, 519, 543, 565, 586, 607, 627, 665, 701, 735, 768, 799, 829, + 858, 886, 940, 991, 1039, 1086, 1130, 1173, 1214, 1254, 1330, 1402, + 1470, 1536, 1598, 1659, 1717, 1773, 1881, 1982, 2079, 2165, 2243, + 2313, 2377, 2436, 2541, 2633, 2714, 2788, 2855, 2916, 2972, 3025, + 3119, 3203, 3279, 3347, 3409, 3467, 3520, 3570, 3616, 3660, 3701, + 3740, 3778, 3813, 3847, 3879, 3910, 3939, 3968, 3995, 4022, 4047, + 4072, 4095 +}; + +int oe_y_lut_sdr[149] = {0, 1, 1, 2, 2, 3, 5, 7, 9, 10, 11, 12, 12, 13, + 15, 16, 16, 18, 20, 21, 22, 24, 26, 28, 30, 33, 35, 38, 40, 44, 47, + 50, 53, 59, 63, 67, 71, 78, 85, 90, 95, 105, 113, 121, 127, 134, 140, + 146, 151, 156, 161, 166, 170, 179, 187, 195, 202, 209, 215, 222, 228, + 239, 250, 260, 270, 279, 287, 296, 304, 319, 334, 347, 360, 372, 384, + 395, 406, 426, 445, 464, 481, 497, 513, 528, 542, 569, 595, 619, 642, + 664, 684, 704, 724, 760, 794, 826, 857, 886, 914, 940, 966, 1015, 1060, + 1103, 1144, 1183, 1220, 1255, 1290, 1355, 1415, 1473, 1527, 1579, 1628, + 1676, 1722, 1808, 1889, 1966, 2039, 2108, 2174, 2237, 2298, 2414, 2522, + 2624, 2721, 2814, 2902, 2987, 3068, 3147, 3222, 3296, 3367, 3436, 3503, + 3569, 3633, 3695, 3756, 3816, 3874, 3931, 3987, 4042, 4095 +}; + +static int oe_y_lut_bypass[149] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, + 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24, + 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, + 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, + 320, 352, 384, 416, 448, 480, 512, 576, 640, 704, 768, 832, 896, + 960, 1024, 1152, 1280, 1408, 1536, 1664, 1792, 1920, 2048, 2176, + 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200, 3328, 3456, 3584, + 3712, 3840, 3968, 4095 +}; + +int oo_y_lut_hdr_hlg[149] = { + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 3917, 3776, 3662, 3565, 3410, 3288, 3188, 3104, 2968, 2862, 2775, + 2702, 2639, 2584, 2535, 2491, 2452, 2416, 2383, 2352, 2297, 2249, + 2207, 2169, 2134, 2103, 2074, 2047, 2000, 1958, 1921, 1888, 1858, + 1831, 1806, 1782, 1741, 1705, 1672, 1644, 1617, 1594, 1572, 1552, + 1515, 1484, 1456, 1431, 1408, 1387, 1368, 1351, 1319, 1292, 1267, + 1245, 1226, 1208, 1191, 1176, 1148, 1124, 1103, 1084, 1067, 1051, + 1037, 1023, 1000, 979, 960, 944, 929, 915, 903, 891, 870, 852, + 836, 822, 808, 797, 786, 776, 757, 742, 728, 715, 704, 693, 684, + 675, 659, 646, 633, 622, 613, 604, 595, 588, 581, 574, 568, 562, + 557, 551, 546, 542, 537, 533, 529, 525, 522, 518, 515, 512 +}; + +int oo_y_lut_hdr_sdr[149] = { + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255 +}; + +int oo_y_lut_bypass[149] = { + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, + 255, 255, 255, 255, 255, 255 +}; + +int oo_y_lut_hlg_hdr[149] = { + 4, 8, 9, 11, 12, 14, 16, 19, 22, 23, 24, 24, 25, 26, 27, 28, 29, + 30, 31, 32, 33, 35, 36, 37, 38, 40, 42, 43, 44, 46, 48, 49, 51, + 53, 55, 57, 58, 61, 63, 65, 67, 70, 73, 75, 77, 79, 81, 82, 84, + 85, 86, 88, 89, 91, 93, 95, 96, 98, 99, 101, 102, 104, 107, 109, + 111, 112, 114, 116, 117, 120, 122, 125, 127, 129, 131, 133, 135, + 138, 141, 144, 146, 148, 151, 153, 155, 158, 162, 165, 168, 171, + 173, 176, 178, 182, 186, 190, 193, 196, 199, 202, 204, 209, 214, + 218, 222, 225, 229, 232, 235, 240, 245, 250, 255, 259, 263, 266, + 270, 276, 282, 288, 293, 297, 302, 306, 310, 317, 324, 330, 336, + 342, 347, 352, 356, 360, 365, 369, 372, 376, 380, 383, 386, 389, + 392, 395, 398, 401, 404, 407, 409 +}; + +int oo_y_lut_sdr_hdr[149] = { + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16 +}; + +int oo_y_lut_hlg_sdr[149] = { + 245, 269, 275, 282, 288, 295, 302, 309, 316, 318, 320, 322, 323, + 326, 327, 329, 331, 333, 335, 337, 338, 341, 343, 345, 346, 349, + 351, 353, 354, 357, 359, 361, 362, 365, 367, 369, 371, 373, 376, + 378, 379, 382, 384, 386, 388, 390, 391, 392, 393, 394, 395, 396, + 397, 399, 400, 401, 402, 403, 404, 405, 406, 408, 409, 410, 412, + 413, 414, 415, 416, 417, 419, 420, 421, 422, 423, 424, 425, 427, + 428, 430, 431, 432, 433, 434, 435, 437, 438, 440, 441, 442, 443, + 444, 445, 447, 448, 450, 451, 452, 453, 454, 455, 457, 459, 460, + 462, 463, 464, 465, 466, 468, 469, 471, 472, 473, 475, 476, 477, + 479, 480, 482, 483, 484, 486, 487, 488, 490, 491, 493, 494, 496, + 497, 498, 499, 500, 501, 502, 503, 503, 504, 505, 506, 506, 507, + 508, 508, 509, 509, 510, 510 +}; + +int oo_y_lut_sdr_hlg[149] = { + 1060, 967, 946, 924, 903, 883, 863, 844, 825, 819, 814, 810, 806, + 800, 795, 791, 788, 782, 777, 773, 770, 764, 760, 756, 753, + 747, 743, 739, 736, 730, 726, 722, 719, 714, 710, 706, 703, + 698, 694, 690, 687, 682, 678, 674, 671, 669, 667, 664, 663, + 661, 659, 658, 656, 654, 651, 649, 648, 646, 644, 643, 641, + 639, 637, 635, 633, 631, 630, 628, 627, 625, 622, 620, 619, + 617, 616, 614, 613, 610, 608, 606, 605, 603, 602, 600, 599, + 597, 595, 593, 591, 590, 588, 587, 585, 583, 581, 579, 578, + 576, 575, 573, 572, 570, 568, 566, 565, 563, 562, 561, 559, + 557, 555, 554, 552, 550, 549, 548, 547, 545, 543, 541, 539, + 538, 537, 536, 534, 532, 530, 529, 527, 526, 525, 523, 522, + 521, 520, 519, 518, 518, 517, 516, 515, 515, 514, 513, 513, + 512, 512, 511, 511 +}; + +int oo_y_lut_1[149] = { + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, + 4095, 4095, 4095, 4095, 4095, 4095 +}; + +static uint out_luma = 5; +static uint in_luma = 1;/*1 as 100luminance*/ +static uint adp_scal_shift = 10;/*1 as 100luminance*/ + +int ncl_2020_709[9] = { + 2684, -489, -147, -201, 2266, -17, -29, -171, 2248}; + +int ncl_709_2020[9] = {1285, 674, 89, 142, 1883, 23, 34, 180, 1834}; + +int rgb2yuvpre[3] = {0, 0, 0}; +int rgb2yuvpos[3] = {64, 512, 512}; +int yuv2rgbpre[3] = {-64, -512, -512}; +int yuv2rgbpos[3] = {0, 0, 0}; +int bypass_pre[3] = {0, 0, 0}; +int bypass_pos[3] = {0, 0, 0}; + +int yuv2rgbmat[15] = { + 1197, 0, 0, 1197, 1851, 0, 1197, 0, 1163, 1197, 2271, 0, 1197, 0, 2011}; +int rgb2ycbcr[15] = { + 230, 594, 52, -125, -323, 448, 448, -412, -36, 0, 0, 0, 0, 0, 0}; +int rgb2ycbcr_ncl2020[15] = { + 230, 594, 52, -125, -323, 448, 448, -412, -36, 0, 0, 0, 0, 0, 0}; +int rgb2ycbcr_709[15] = { + 186, 627, 63, -103, -345, 448, 448, -407, -41, 0, 0, 0, 0, 0, 0}; +int ycbcr2rgb_709[15] = { + 1192, 0, 1836, 1192, -217, -546, 1192, 2166, 0, 0, 0, 0, 0, 0, 0}; +int ycbcr2rgb_ncl2020[15] = { + 1197, 0, 1726, 1197, -193, -669, 1197, 2202, 0, 0, 0, 0, 0, 0, 0}; + +static int bypass_coeff[15] = { + 1024, 0, 0, + 0, 1024, 0, + 0, 0, 1024, + 0, 0, 0, + 0, 0, 0, +}; + +void set_hdr_matrix(enum hdr_module_sel module_sel, + enum hdr_matrix_sel mtx_sel, + struct hdr_proc_mtx_param_s *hdr_mtx_param) +{ + unsigned int MATRIXI_COEF00_01 = 0; + unsigned int MATRIXI_COEF02_10 = 0; + unsigned int MATRIXI_COEF11_12 = 0; + unsigned int MATRIXI_COEF20_21 = 0; + unsigned int MATRIXI_COEF22 = 0; + /*unsigned int MATRIXI_COEF30_31 = 0;*/ + /*unsigned int MATRIXI_COEF32_40 = 0;*/ + /*unsigned int MATRIXI_COEF41_42 = 0;*/ + unsigned int MATRIXI_OFFSET0_1 = 0; + unsigned int MATRIXI_OFFSET2 = 0; + unsigned int MATRIXI_PRE_OFFSET0_1 = 0; + unsigned int MATRIXI_PRE_OFFSET2 = 0; + /*unsigned int MATRIXI_CLIP = 0;*/ + unsigned int MATRIXI_EN_CTRL = 0; + + unsigned int MATRIXO_COEF00_01 = 0; + unsigned int MATRIXO_COEF02_10 = 0; + unsigned int MATRIXO_COEF11_12 = 0; + unsigned int MATRIXO_COEF20_21 = 0; + unsigned int MATRIXO_COEF22 = 0; + /*unsigned int MATRIXO_COEF30_31 = 0;*/ + /*unsigned int MATRIXO_COEF32_40 = 0;*/ + /*unsigned int MATRIXO_COEF41_42 = 0;*/ + unsigned int MATRIXO_OFFSET0_1 = 0; + unsigned int MATRIXO_OFFSET2 = 0; + unsigned int MATRIXO_PRE_OFFSET0_1 = 0; + unsigned int MATRIXO_PRE_OFFSET2 = 0; + /*unsigned int MATRIXO_CLIP = 0;*/ + unsigned int MATRIXO_EN_CTRL = 0; + + unsigned int CGAIN_OFFT = 0; + unsigned int CGAIN_COEF0 = 0; + unsigned int CGAIN_COEF1 = 0; + unsigned int ADPS_CTRL = 0; + unsigned int ADPS_ALPHA0 = 0; + unsigned int ADPS_ALPHA1 = 0; + unsigned int ADPS_BETA0 = 0; + unsigned int ADPS_BETA1 = 0; + unsigned int ADPS_BETA2 = 0; + unsigned int ADPS_COEF0 = 0; + unsigned int ADPS_COEF1 = 0; + unsigned int GMUT_CTRL = 0; + unsigned int GMUT_COEF0 = 0; + unsigned int GMUT_COEF1 = 0; + unsigned int GMUT_COEF2 = 0; + unsigned int GMUT_COEF3 = 0; + unsigned int GMUT_COEF4 = 0; + + unsigned int hdr_ctrl = 0; + + int adpscl_mode = 0; + + int c_gain_lim_coef[3]; + int gmut_coef[3][3]; + int gmut_shift; + int adpscl_enable[3]; + int adpscl_alpha[3] = {0, 0, 0}; + int adpscl_shift[3]; + int adpscl_ys_coef[3] = {0, 0, 0}; + int adpscl_beta[3]; + int adpscl_beta_s[3]; + + int i = 0; + int mtx[15] = { + 1024, 0, 0, + 0, 1024, 0, + 0, 0, 1024, + 0, 0, 0, + 0, 0, 0, + }; + + if (module_sel & VD1_HDR) { + MATRIXI_COEF00_01 = VD1_HDR2_MATRIXI_COEF00_01; + MATRIXI_COEF00_01 = VD1_HDR2_MATRIXI_COEF00_01; + MATRIXI_COEF02_10 = VD1_HDR2_MATRIXI_COEF02_10; + MATRIXI_COEF11_12 = VD1_HDR2_MATRIXI_COEF11_12; + MATRIXI_COEF20_21 = VD1_HDR2_MATRIXI_COEF20_21; + MATRIXI_COEF22 = VD1_HDR2_MATRIXI_COEF22; + /*MATRIXI_COEF30_31 = VD1_HDR2_MATRIXI_COEF30_31;*/ + /*MATRIXI_COEF32_40 = VD1_HDR2_MATRIXI_COEF32_40;*/ + /*MATRIXI_COEF41_42 = VD1_HDR2_MATRIXI_COEF41_42;*/ + MATRIXI_OFFSET0_1 = VD1_HDR2_MATRIXI_OFFSET0_1; + MATRIXI_OFFSET2 = VD1_HDR2_MATRIXI_OFFSET2; + MATRIXI_PRE_OFFSET0_1 = VD1_HDR2_MATRIXI_PRE_OFFSET0_1; + MATRIXI_PRE_OFFSET2 = VD1_HDR2_MATRIXI_PRE_OFFSET2; + /*MATRIXI_CLIP = VD1_HDR2_MATRIXI_CLIP;*/ + MATRIXI_EN_CTRL = VD1_HDR2_MATRIXI_EN_CTRL; + + MATRIXO_COEF00_01 = VD1_HDR2_MATRIXO_COEF00_01; + MATRIXO_COEF00_01 = VD1_HDR2_MATRIXO_COEF00_01; + MATRIXO_COEF02_10 = VD1_HDR2_MATRIXO_COEF02_10; + MATRIXO_COEF11_12 = VD1_HDR2_MATRIXO_COEF11_12; + MATRIXO_COEF20_21 = VD1_HDR2_MATRIXO_COEF20_21; + MATRIXO_COEF22 = VD1_HDR2_MATRIXO_COEF22; + /*MATRIXO_COEF30_31 = VD1_HDR2_MATRIXO_COEF30_31;*/ + /*MATRIXO_COEF32_40 = VD1_HDR2_MATRIXO_COEF32_40;*/ + /*MATRIXO_COEF41_42 = VD1_HDR2_MATRIXO_COEF41_42;*/ + MATRIXO_OFFSET0_1 = VD1_HDR2_MATRIXO_OFFSET0_1; + MATRIXO_OFFSET2 = VD1_HDR2_MATRIXO_OFFSET2; + MATRIXO_PRE_OFFSET0_1 = VD1_HDR2_MATRIXO_PRE_OFFSET0_1; + MATRIXO_PRE_OFFSET2 = VD1_HDR2_MATRIXO_PRE_OFFSET2; + /*MATRIXO_CLIP = VD1_HDR2_MATRIXO_CLIP;*/ + MATRIXO_EN_CTRL = VD1_HDR2_MATRIXO_EN_CTRL; + + CGAIN_OFFT = VD1_HDR2_CGAIN_OFFT; + CGAIN_COEF0 = VD1_HDR2_CGAIN_COEF0; + CGAIN_COEF1 = VD1_HDR2_CGAIN_COEF1; + ADPS_CTRL = VD1_HDR2_ADPS_CTRL; + ADPS_ALPHA0 = VD1_HDR2_ADPS_ALPHA0; + ADPS_ALPHA1 = VD1_HDR2_ADPS_ALPHA1; + ADPS_BETA0 = VD1_HDR2_ADPS_BETA0; + ADPS_BETA1 = VD1_HDR2_ADPS_BETA1; + ADPS_BETA2 = VD1_HDR2_ADPS_BETA2; + ADPS_COEF0 = VD1_HDR2_ADPS_COEF0; + ADPS_COEF1 = VD1_HDR2_ADPS_COEF1; + GMUT_CTRL = VD1_HDR2_GMUT_CTRL; + GMUT_COEF0 = VD1_HDR2_GMUT_COEF0; + GMUT_COEF1 = VD1_HDR2_GMUT_COEF1; + GMUT_COEF2 = VD1_HDR2_GMUT_COEF2; + GMUT_COEF3 = VD1_HDR2_GMUT_COEF3; + GMUT_COEF4 = VD1_HDR2_GMUT_COEF4; + + hdr_ctrl = VD1_HDR2_CTRL; + } else if (module_sel & VD2_HDR) { + MATRIXI_COEF00_01 = VD2_HDR2_MATRIXI_COEF00_01; + MATRIXI_COEF00_01 = VD2_HDR2_MATRIXI_COEF00_01; + MATRIXI_COEF02_10 = VD2_HDR2_MATRIXI_COEF02_10; + MATRIXI_COEF11_12 = VD2_HDR2_MATRIXI_COEF11_12; + MATRIXI_COEF20_21 = VD2_HDR2_MATRIXI_COEF20_21; + MATRIXI_COEF22 = VD2_HDR2_MATRIXI_COEF22; + /*MATRIXI_COEF30_31 = VD2_HDR2_MATRIXI_COEF30_31;*/ + /*MATRIXI_COEF32_40 = VD2_HDR2_MATRIXI_COEF32_40;*/ + /*MATRIXI_COEF41_42 = VD2_HDR2_MATRIXI_COEF41_42;*/ + MATRIXI_OFFSET0_1 = VD2_HDR2_MATRIXI_OFFSET0_1; + MATRIXI_OFFSET2 = VD2_HDR2_MATRIXI_OFFSET2; + MATRIXI_PRE_OFFSET0_1 = VD2_HDR2_MATRIXI_PRE_OFFSET0_1; + MATRIXI_PRE_OFFSET2 = VD2_HDR2_MATRIXI_PRE_OFFSET2; + /*MATRIXI_CLIP = VD2_HDR2_MATRIXI_CLIP;*/ + MATRIXI_EN_CTRL = VD2_HDR2_MATRIXI_EN_CTRL; + + MATRIXO_COEF00_01 = VD2_HDR2_MATRIXO_COEF00_01; + MATRIXO_COEF00_01 = VD2_HDR2_MATRIXO_COEF00_01; + MATRIXO_COEF02_10 = VD2_HDR2_MATRIXO_COEF02_10; + MATRIXO_COEF11_12 = VD2_HDR2_MATRIXO_COEF11_12; + MATRIXO_COEF20_21 = VD2_HDR2_MATRIXO_COEF20_21; + MATRIXO_COEF22 = VD2_HDR2_MATRIXO_COEF22; + /*MATRIXO_COEF30_31 = VD2_HDR2_MATRIXO_COEF30_31;*/ + /*MATRIXO_COEF32_40 = VD2_HDR2_MATRIXO_COEF32_40;*/ + /*MATRIXO_COEF41_42 = VD2_HDR2_MATRIXO_COEF41_42;*/ + MATRIXO_OFFSET0_1 = VD2_HDR2_MATRIXO_OFFSET0_1; + MATRIXO_OFFSET2 = VD2_HDR2_MATRIXO_OFFSET2; + MATRIXO_PRE_OFFSET0_1 = VD2_HDR2_MATRIXO_PRE_OFFSET0_1; + MATRIXO_PRE_OFFSET2 = VD2_HDR2_MATRIXO_PRE_OFFSET2; + /*MATRIXO_CLIP = VD2_HDR2_MATRIXO_CLIP;*/ + MATRIXO_EN_CTRL = VD2_HDR2_MATRIXO_EN_CTRL; + + CGAIN_OFFT = VD2_HDR2_CGAIN_OFFT; + CGAIN_COEF0 = VD2_HDR2_CGAIN_COEF0; + CGAIN_COEF1 = VD2_HDR2_CGAIN_COEF1; + ADPS_CTRL = VD2_HDR2_ADPS_CTRL; + ADPS_ALPHA0 = VD2_HDR2_ADPS_ALPHA0; + ADPS_ALPHA1 = VD2_HDR2_ADPS_ALPHA1; + ADPS_BETA0 = VD2_HDR2_ADPS_BETA0; + ADPS_BETA1 = VD2_HDR2_ADPS_BETA1; + ADPS_BETA2 = VD2_HDR2_ADPS_BETA2; + ADPS_COEF0 = VD2_HDR2_ADPS_COEF0; + ADPS_COEF1 = VD2_HDR2_ADPS_COEF1; + GMUT_CTRL = VD2_HDR2_GMUT_CTRL; + GMUT_COEF0 = VD2_HDR2_GMUT_COEF0; + GMUT_COEF1 = VD2_HDR2_GMUT_COEF1; + GMUT_COEF2 = VD2_HDR2_GMUT_COEF2; + GMUT_COEF3 = VD2_HDR2_GMUT_COEF3; + GMUT_COEF4 = VD2_HDR2_GMUT_COEF4; + + hdr_ctrl = VD2_HDR2_CTRL; + } else if (module_sel & OSD1_HDR) { + MATRIXI_COEF00_01 = OSD1_HDR2_MATRIXI_COEF00_01; + MATRIXI_COEF00_01 = OSD1_HDR2_MATRIXI_COEF00_01; + MATRIXI_COEF02_10 = OSD1_HDR2_MATRIXI_COEF02_10; + MATRIXI_COEF11_12 = OSD1_HDR2_MATRIXI_COEF11_12; + MATRIXI_COEF20_21 = OSD1_HDR2_MATRIXI_COEF20_21; + MATRIXI_COEF22 = OSD1_HDR2_MATRIXI_COEF22; + /*MATRIXI_COEF30_31 = OSD1_HDR2_MATRIXI_COEF30_31;*/ + /*MATRIXI_COEF32_40 = OSD1_HDR2_MATRIXI_COEF32_40;*/ + /*MATRIXI_COEF41_42 = OSD1_HDR2_MATRIXI_COEF41_42;*/ + MATRIXI_OFFSET0_1 = OSD1_HDR2_MATRIXI_OFFSET0_1; + MATRIXI_OFFSET2 = OSD1_HDR2_MATRIXI_OFFSET2; + MATRIXI_PRE_OFFSET0_1 = OSD1_HDR2_MATRIXI_PRE_OFFSET0_1; + MATRIXI_PRE_OFFSET2 = OSD1_HDR2_MATRIXI_PRE_OFFSET2; + /*MATRIXI_CLIP = OSD1_HDR2_MATRIXI_CLIP;*/ + MATRIXI_EN_CTRL = OSD1_HDR2_MATRIXI_EN_CTRL; + + MATRIXO_COEF00_01 = OSD1_HDR2_MATRIXO_COEF00_01; + MATRIXO_COEF00_01 = OSD1_HDR2_MATRIXO_COEF00_01; + MATRIXO_COEF02_10 = OSD1_HDR2_MATRIXO_COEF02_10; + MATRIXO_COEF11_12 = OSD1_HDR2_MATRIXO_COEF11_12; + MATRIXO_COEF20_21 = OSD1_HDR2_MATRIXO_COEF20_21; + MATRIXO_COEF22 = OSD1_HDR2_MATRIXO_COEF22; + /*MATRIXO_COEF30_31 = OSD1_HDR2_MATRIXO_COEF30_31;*/ + /*MATRIXO_COEF32_40 = OSD1_HDR2_MATRIXO_COEF32_40;*/ + /*MATRIXO_COEF41_42 = OSD1_HDR2_MATRIXO_COEF41_42;*/ + MATRIXO_OFFSET0_1 = OSD1_HDR2_MATRIXO_OFFSET0_1; + MATRIXO_OFFSET2 = OSD1_HDR2_MATRIXO_OFFSET2; + MATRIXO_PRE_OFFSET0_1 = OSD1_HDR2_MATRIXO_PRE_OFFSET0_1; + MATRIXO_PRE_OFFSET2 = OSD1_HDR2_MATRIXO_PRE_OFFSET2; + /*MATRIXO_CLIP = OSD1_HDR2_MATRIXO_CLIP;*/ + MATRIXO_EN_CTRL = OSD1_HDR2_MATRIXO_EN_CTRL; + + CGAIN_OFFT = OSD1_HDR2_CGAIN_OFFT; + CGAIN_COEF0 = OSD1_HDR2_CGAIN_COEF0; + CGAIN_COEF1 = OSD1_HDR2_CGAIN_COEF1; + ADPS_CTRL = OSD1_HDR2_ADPS_CTRL; + ADPS_ALPHA0 = OSD1_HDR2_ADPS_ALPHA0; + ADPS_ALPHA1 = OSD1_HDR2_ADPS_ALPHA1; + ADPS_BETA0 = OSD1_HDR2_ADPS_BETA0; + ADPS_BETA1 = OSD1_HDR2_ADPS_BETA1; + ADPS_BETA2 = OSD1_HDR2_ADPS_BETA2; + ADPS_COEF0 = OSD1_HDR2_ADPS_COEF0; + ADPS_COEF1 = OSD1_HDR2_ADPS_COEF1; + GMUT_CTRL = OSD1_HDR2_GMUT_CTRL; + GMUT_COEF0 = OSD1_HDR2_GMUT_COEF0; + GMUT_COEF1 = OSD1_HDR2_GMUT_COEF1; + GMUT_COEF2 = OSD1_HDR2_GMUT_COEF2; + GMUT_COEF3 = OSD1_HDR2_GMUT_COEF3; + GMUT_COEF4 = OSD1_HDR2_GMUT_COEF4; + + hdr_ctrl = OSD1_HDR2_CTRL; + } + + if (!hdr_mtx_param) + return; + vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_on, 13, 1); + + if (mtx_sel & HDR_IN_MTX) { + for (i = 0; i < 15; i++) + mtx[i] = hdr_mtx_param->mtx_in[i]; + + if (hdr_mtx_param->mtx_only == MTX_ONLY && + !hdr_mtx_param->mtx_on) + vpp_reg_write(MATRIXI_EN_CTRL, 1); + else + vpp_reg_write(MATRIXI_EN_CTRL, + hdr_mtx_param->mtx_on); + /*yuv in*/ + vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_on, 4, 1); + + vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_only, + 16, 1); + vpp_reg_setb(hdr_ctrl, 0, 17, 1); + /*mtx in en*/ + vpp_reg_setb(hdr_ctrl, 1, 14, 1); + + vpp_reg_write(MATRIXI_COEF00_01, + (mtx[0 * 3 + 0] << 16) | + (mtx[0 * 3 + 1] & 0x1FFF)); + vpp_reg_write(MATRIXI_COEF02_10, + (mtx[0 * 3 + 2] << 16) | + (mtx[1 * 3 + 0] & 0x1FFF)); + vpp_reg_write(MATRIXI_COEF11_12, + (mtx[1 * 3 + 1] << 16) | + (mtx[1 * 3 + 2] & 0x1FFF)); + vpp_reg_write(MATRIXI_COEF20_21, + (mtx[2 * 3 + 0] << 16) | + (mtx[2 * 3 + 1] & 0x1FFF)); + vpp_reg_write(MATRIXI_COEF22, + mtx[2 * 3 + 2]); + vpp_reg_write(MATRIXI_OFFSET0_1, + (hdr_mtx_param->mtxi_pos_offset[0] << 16) | + (hdr_mtx_param->mtxi_pos_offset[1] & 0xFFF)); + vpp_reg_write(MATRIXI_OFFSET2, + hdr_mtx_param->mtxi_pos_offset[2]); + vpp_reg_write(MATRIXI_PRE_OFFSET0_1, + (hdr_mtx_param->mtxi_pre_offset[0] << 16) | + (hdr_mtx_param->mtxi_pre_offset[1] & 0xFFF)); + vpp_reg_write(MATRIXI_PRE_OFFSET2, + hdr_mtx_param->mtxi_pre_offset[2]); + + } else if (mtx_sel & HDR_GAMUT_MTX) { + for (i = 0; i < 9; i++) + gmut_coef[i / 3][i % 3] = + hdr_mtx_param->mtx_gamut[i]; + /*for g12a/g12b osd blend shift rtl bug*/ + if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) && + (hdr_mtx_param->p_sel & HDR_BYPASS) && + (module_sel & OSD1_HDR)) + gmut_shift = 10; + else + gmut_shift = 11; + + for (i = 0; i < 3; i++) + c_gain_lim_coef[i] = + hdr_mtx_param->mtx_cgain[i] << 2; + /*0, nolinear input, 1, max linear, 2, adpscl mode*/ + adpscl_mode = 1; + for (i = 0; i < 3; i++) { + if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) && + (hdr_mtx_param->p_sel & HDR_BYPASS) && + (module_sel & OSD1_HDR)) + adpscl_enable[i] = 1; + else + adpscl_enable[i] = 0; + if (hdr_mtx_param->p_sel & HDR_SDR) + adpscl_alpha[i] = + (1 << adp_scal_shift); + else if (hdr_mtx_param->p_sel & SDR_HDR) + adpscl_alpha[i] = + (1 << adp_scal_shift); + else if (hdr_mtx_param->p_sel & HDR_BYPASS) + adpscl_alpha[i] = out_luma * + (1 << adp_scal_shift) / in_luma; + else if (hdr_mtx_param->p_sel & HLG_SDR) { + adpscl_alpha[i] = out_luma * + (1 << adp_scal_shift) / in_luma; + adpscl_mode = 2; + } else if (hdr_mtx_param->p_sel & HLG_HDR) + adpscl_alpha[i] = 1 * + (1 << adp_scal_shift) / in_luma; + else if (hdr_mtx_param->p_sel & SDR_HLG) + adpscl_alpha[i] = 10 * in_luma * + (1 << adp_scal_shift) / out_luma; + + if (hdr_mtx_param->p_sel & HDR_SDR) { + if (i == 0) + adpscl_shift[i] = adp_scal_shift; + else + adpscl_shift[i] = adp_scal_shift - 2; + } else { + /* shift value keep consistent with kernel */ + if (i == 1) + adpscl_shift[i] = adp_scal_shift - 1; + else + adpscl_shift[i] = adp_scal_shift; + } + + adpscl_ys_coef[i] = + 1 << adp_scal_shift; + adpscl_beta_s[i] = 0; + adpscl_beta[i] = 0; + } + + /*gamut mode: 1->gamut before ootf*/ + /*2->gamut after ootf*/ + /*other->disable gamut*/ + vpp_reg_setb(hdr_ctrl, 1, 6, 2); + + vpp_reg_write(GMUT_CTRL, gmut_shift); + vpp_reg_write(GMUT_COEF0, + (gmut_coef[0][1] & 0xffff) << 16 | + (gmut_coef[0][0] & 0xffff)); + vpp_reg_write(GMUT_COEF1, + (gmut_coef[1][0] & 0xffff) << 16 | + (gmut_coef[0][2] & 0xffff)); + vpp_reg_write(GMUT_COEF2, + (gmut_coef[1][2] & 0xffff) << 16 | + (gmut_coef[1][1] & 0xffff)); + vpp_reg_write(GMUT_COEF3, + (gmut_coef[2][1] & 0xffff) << 16 | + (gmut_coef[2][0] & 0xffff)); + vpp_reg_write(GMUT_COEF4, + gmut_coef[2][2] & 0xffff); + + vpp_reg_write(CGAIN_COEF0, + c_gain_lim_coef[1] << 16 | + c_gain_lim_coef[0]); + vpp_reg_write(CGAIN_COEF1, c_gain_lim_coef[2] | + 0x1000 << 16); + + vpp_reg_write(ADPS_CTRL, adpscl_enable[2] << 6 | + adpscl_enable[1] << 5 | + adpscl_enable[0] << 4 | + adpscl_mode); + vpp_reg_write(ADPS_ALPHA0, + adpscl_alpha[1] << 16 | adpscl_alpha[0]); + vpp_reg_write(ADPS_ALPHA1, adpscl_shift[0] << 24 | + adpscl_shift[1] << 20 | + adpscl_shift[2] << 16 | + adpscl_alpha[2]); + vpp_reg_write(ADPS_BETA0, + adpscl_beta_s[0] << 20 | adpscl_beta[0]); + vpp_reg_write(ADPS_BETA1, + adpscl_beta_s[1] << 20 | adpscl_beta[1]); + vpp_reg_write(ADPS_BETA2, + adpscl_beta_s[2] << 20 | adpscl_beta[2]); + vpp_reg_write(ADPS_COEF0, + adpscl_ys_coef[1] << 16 | adpscl_ys_coef[0]); + vpp_reg_write(ADPS_COEF1, adpscl_ys_coef[2]); + + } else if (mtx_sel & HDR_OUT_MTX) { + for (i = 0; i < 15; i++) + mtx[i] = hdr_mtx_param->mtx_out[i]; + vpp_reg_write(CGAIN_OFFT, + (rgb2yuvpos[2] << 16) | rgb2yuvpos[1]); + vpp_reg_write(MATRIXO_EN_CTRL, hdr_mtx_param->mtx_on); + /*yuv in*/ + vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_on, 4, 1); + + vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_only, + 16, 1); + vpp_reg_setb(hdr_ctrl, 0, 17, 1); + /*mtx out en*/ + vpp_reg_setb(hdr_ctrl, 1, 15, 1); + + vpp_reg_write(MATRIXO_COEF00_01, + (mtx[0 * 3 + 0] << 16) | + (mtx[0 * 3 + 1] & 0x1FFF)); + vpp_reg_write(MATRIXO_COEF02_10, + (mtx[0 * 3 + 2] << 16) | + (mtx[1 * 3 + 0] & 0x1FFF)); + vpp_reg_write(MATRIXO_COEF11_12, + (mtx[1 * 3 + 1] << 16) | + (mtx[1 * 3 + 2] & 0x1FFF)); + vpp_reg_write(MATRIXO_COEF20_21, + (mtx[2 * 3 + 0] << 16) | + (mtx[2 * 3 + 1] & 0x1FFF)); + vpp_reg_write(MATRIXO_COEF22, + mtx[2 * 3 + 2]); + vpp_reg_write(MATRIXO_OFFSET0_1, + (hdr_mtx_param->mtxo_pos_offset[0] << 16) | + (hdr_mtx_param->mtxo_pos_offset[1] & 0xFFF)); + vpp_reg_write(MATRIXO_OFFSET2, + hdr_mtx_param->mtxo_pos_offset[2]); + vpp_reg_write(MATRIXO_PRE_OFFSET0_1, + (hdr_mtx_param->mtxo_pre_offset[0] << 16) | + (hdr_mtx_param->mtxo_pre_offset[1] & 0xFFF)); + vpp_reg_write(MATRIXO_PRE_OFFSET2, + hdr_mtx_param->mtxo_pre_offset[2]); + } +} + +void set_eotf_lut(enum hdr_module_sel module_sel, + struct hdr_proc_lut_param_s *hdr_lut_param) +{ + unsigned int lut[HDR2_EOTF_LUT_SIZE]; + unsigned int eotf_lut_addr_port = 0; + unsigned int eotf_lut_data_port = 0; + unsigned int hdr_ctrl = 0; + unsigned int i = 0; + + if (module_sel & VD1_HDR) { + eotf_lut_addr_port = VD1_EOTF_LUT_ADDR_PORT; + eotf_lut_data_port = VD1_EOTF_LUT_DATA_PORT; + hdr_ctrl = VD1_HDR2_CTRL; + } else if (module_sel & VD2_HDR) { + eotf_lut_addr_port = VD2_EOTF_LUT_ADDR_PORT; + eotf_lut_data_port = VD2_EOTF_LUT_DATA_PORT; + hdr_ctrl = VD2_HDR2_CTRL; + } else if (module_sel & OSD1_HDR) { + eotf_lut_addr_port = OSD1_EOTF_LUT_ADDR_PORT; + eotf_lut_data_port = OSD1_EOTF_LUT_DATA_PORT; + hdr_ctrl = OSD1_HDR2_CTRL; + } + + for (i = 0; i < HDR2_EOTF_LUT_SIZE; i++) + lut[i] = hdr_lut_param->eotf_lut[i]; + + vpp_reg_setb(hdr_ctrl, hdr_lut_param->lut_on, 3, 1); + + if (!hdr_lut_param->lut_on) + return; + + vpp_reg_write(eotf_lut_addr_port, 0x0); + for (i = 0; i < HDR2_EOTF_LUT_SIZE; i++) + vpp_reg_write(eotf_lut_data_port, lut[i]); +} + +void set_ootf_lut(enum hdr_module_sel module_sel, + struct hdr_proc_lut_param_s *hdr_lut_param) +{ + unsigned int lut[HDR2_OOTF_LUT_SIZE]; + unsigned int ootf_lut_addr_port = 0; + unsigned int ootf_lut_data_port = 0; + unsigned int hdr_ctrl = 0; + unsigned int i = 0; + + if (module_sel & VD1_HDR) { + ootf_lut_addr_port = VD1_OGAIN_LUT_ADDR_PORT; + ootf_lut_data_port = VD1_OGAIN_LUT_DATA_PORT; + hdr_ctrl = VD1_HDR2_CTRL; + } else if (module_sel & VD2_HDR) { + ootf_lut_addr_port = VD2_OGAIN_LUT_ADDR_PORT; + ootf_lut_data_port = VD2_OGAIN_LUT_DATA_PORT; + hdr_ctrl = VD2_HDR2_CTRL; + } else if (module_sel & OSD1_HDR) { + ootf_lut_addr_port = OSD1_OGAIN_LUT_ADDR_PORT; + ootf_lut_data_port = OSD1_OGAIN_LUT_DATA_PORT; + hdr_ctrl = OSD1_HDR2_CTRL; + } + + for (i = 0; i < HDR2_OOTF_LUT_SIZE; i++) + lut[i] = hdr_lut_param->ogain_lut[i]; + + vpp_reg_setb(hdr_ctrl, hdr_lut_param->lut_on, 1, 1); + + if (!hdr_lut_param->lut_on) + return; + + vpp_reg_write(ootf_lut_addr_port, 0x0); + for (i = 0; i < HDR2_OOTF_LUT_SIZE / 2; i++) + vpp_reg_write(ootf_lut_data_port, + (lut[i * 2 + 1] << 16) + + lut[i * 2]); + vpp_reg_write(ootf_lut_data_port, lut[148]); +} + +void set_oetf_lut(enum hdr_module_sel module_sel, + struct hdr_proc_lut_param_s *hdr_lut_param) +{ + unsigned int lut[HDR2_OETF_LUT_SIZE]; + unsigned int oetf_lut_addr_port = 0; + unsigned int oetf_lut_data_port = 0; + unsigned int hdr_ctrl = 0; + unsigned int i = 0; + + if (module_sel & VD1_HDR) { + oetf_lut_addr_port = VD1_OETF_LUT_ADDR_PORT; + oetf_lut_data_port = VD1_OETF_LUT_DATA_PORT; + hdr_ctrl = VD1_HDR2_CTRL; + } else if (module_sel & VD2_HDR) { + oetf_lut_addr_port = VD2_OETF_LUT_ADDR_PORT; + oetf_lut_data_port = VD2_OETF_LUT_DATA_PORT; + hdr_ctrl = VD2_HDR2_CTRL; + } else if (module_sel & OSD1_HDR) { + oetf_lut_addr_port = OSD1_OETF_LUT_ADDR_PORT; + oetf_lut_data_port = OSD1_OETF_LUT_DATA_PORT; + hdr_ctrl = OSD1_HDR2_CTRL; + } + + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) + lut[i] = hdr_lut_param->oetf_lut[i]; + + vpp_reg_setb(hdr_ctrl, hdr_lut_param->lut_on, 2, 1); + + if (!hdr_lut_param->lut_on) + return; + + vpp_reg_write(oetf_lut_addr_port, 0x0); + for (i = 0; i < HDR2_OETF_LUT_SIZE / 2; i++) { + if (hdr_lut_param->bitdepth == 10) + vpp_reg_write(oetf_lut_data_port, + ((lut[i * 2 + 1] >> 2) << 16) + + (lut[i * 2] >> 2)); + else + vpp_reg_write(oetf_lut_data_port, + (lut[i * 2 + 1] << 16) + + lut[i * 2]); + } + vpp_reg_write(oetf_lut_data_port, lut[148]); +} + +void set_c_gain(enum hdr_module_sel module_sel, + struct hdr_proc_lut_param_s *hdr_lut_param) +{ + unsigned int lut[HDR2_CGAIN_LUT_SIZE]; + unsigned int cgain_lut_addr_port = 0; + unsigned int cgain_lut_data_port = 0; + unsigned int hdr_ctrl = 0; + unsigned int i = 0; + + if (module_sel & VD1_HDR) { + cgain_lut_addr_port = VD1_CGAIN_LUT_ADDR_PORT; + cgain_lut_data_port = VD1_CGAIN_LUT_DATA_PORT; + hdr_ctrl = VD1_HDR2_CTRL; + } else if (module_sel & VD2_HDR) { + cgain_lut_addr_port = VD2_CGAIN_LUT_ADDR_PORT; + cgain_lut_data_port = VD2_CGAIN_LUT_DATA_PORT; + hdr_ctrl = VD2_HDR2_CTRL; + } else if (module_sel & OSD1_HDR) { + cgain_lut_addr_port = OSD1_CGAIN_LUT_ADDR_PORT; + cgain_lut_data_port = OSD1_CGAIN_LUT_DATA_PORT; + hdr_ctrl = OSD1_HDR2_CTRL; + } + + for (i = 0; i < HDR2_CGAIN_LUT_SIZE; i++) + lut[i] = hdr_lut_param->cgain_lut[i]; + + /*cgain mode: 0->y domin*/ + /*cgain mode: 1->rgb domin, use r/g/b max*/ + vpp_reg_setb(hdr_ctrl, 0, 12, 1); + vpp_reg_setb(hdr_ctrl, hdr_lut_param->cgain_en, 0, 1); + + if (!hdr_lut_param->cgain_en) + return; + + vpp_reg_write(cgain_lut_addr_port, 0x0); + for (i = 0; i < HDR2_CGAIN_LUT_SIZE / 2; i++) + vpp_reg_write(cgain_lut_data_port, + (lut[i * 2 + 1] << 16) + lut[i * 2]); + vpp_reg_write(cgain_lut_data_port, lut[64]); +} + +struct hdr_proc_lut_param_s hdr_lut_param; + +void hdr_func(enum hdr_module_sel module_sel, + enum hdr_process_sel hdr_process_select) +{ + int bit_depth; + unsigned int i = 0; + struct hdr_proc_mtx_param_s hdr_mtx_param; + + printf("%s: %d, hdr_process_select 0x%x\n", + __func__, module_sel, hdr_process_select); + + memset(&hdr_mtx_param, 0, sizeof(struct hdr_proc_mtx_param_s)); + memset(&hdr_lut_param, 0, sizeof(struct hdr_proc_lut_param_s)); + + if (module_sel & (VD1_HDR | VD2_HDR | OSD1_HDR)) + bit_depth = 12; + else if (module_sel & (VDIN0_HDR | VDIN1_HDR | DI_HDR)) + bit_depth = 10; + else + return; + /*lut parameters*/ + if (hdr_process_select & (HDR_BYPASS | RGB_BYPASS)) { + /*for g12a/g12b osd blend shift rtl bug*/ + if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) && + (module_sel & (OSD1_HDR | VD1_HDR | VD2_HDR))) { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_bypass[i]; + hdr_lut_param.ogain_lut[i] = oo_y_lut_bypass[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = + eo_y_lut_bypass[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = + cgain_lut_bypass[i] - 1; + } + hdr_lut_param.lut_on = LUT_ON; + hdr_lut_param.bitdepth = bit_depth; + hdr_lut_param.cgain_en = LUT_ON; + } else { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i]; + hdr_lut_param.ogain_lut[i] = + oo_y_lut_hdr_sdr[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = + eo_y_lut_hdr[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = + cgain_lut1[i] - 1; + } + hdr_lut_param.lut_on = LUT_OFF; + hdr_lut_param.bitdepth = bit_depth; + hdr_lut_param.cgain_en = LUT_OFF; + } + } else if (hdr_process_select & HDR_SDR) { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i]; + hdr_lut_param.ogain_lut[i] = oo_y_lut_hdr_sdr[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = eo_y_lut_hdr[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = cgain_lut1[i] - 1; + } + hdr_lut_param.lut_on = LUT_ON; + hdr_lut_param.bitdepth = bit_depth; + hdr_lut_param.cgain_en = LUT_ON; + } else if (hdr_process_select & SDR_HDR) { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i]; + hdr_lut_param.ogain_lut[i] = oo_y_lut_sdr_hdr[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = eo_y_lut_sdr[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = + cgain_lut_bypass[i] - 1; + } + hdr_lut_param.lut_on = LUT_ON; + hdr_lut_param.bitdepth = bit_depth; + /*for g12a/g12b osd blend shift rtl bug*/ + if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) && + (module_sel & OSD1_HDR)) + hdr_lut_param.cgain_en = LUT_ON; + else + hdr_lut_param.cgain_en = LUT_OFF; + } else if (hdr_process_select & HLG_BYPASS) { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i]; + hdr_lut_param.ogain_lut[i] = oo_y_lut_hdr_sdr[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = eo_y_lut_hlg[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = cgain_lut1[i] - 1; + } + hdr_lut_param.lut_on = LUT_OFF; + hdr_lut_param.bitdepth = bit_depth; + hdr_lut_param.cgain_en = LUT_OFF; + } else if (hdr_process_select & HLG_SDR) { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i]; + hdr_lut_param.ogain_lut[i] = oo_y_lut_hlg_sdr[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = eo_y_lut_hlg[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = cgain_lut1[i] - 1; + } + hdr_lut_param.lut_on = LUT_ON; + hdr_lut_param.bitdepth = bit_depth; + hdr_lut_param.cgain_en = LUT_ON; + } else if (hdr_process_select & HLG_HDR) { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i]; + hdr_lut_param.ogain_lut[i] = oo_y_lut_hlg_hdr[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = eo_y_lut_hlg[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = cgain_lut1[i] - 1; + } + hdr_lut_param.lut_on = LUT_ON; + hdr_lut_param.bitdepth = bit_depth; + hdr_lut_param.cgain_en = LUT_ON; + } else if (hdr_process_select & SDR_HLG) { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_hlg[i]; + hdr_lut_param.ogain_lut[i] = oo_y_lut_sdr_hlg[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = eo_y_lut_sdr[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = + cgain_lut_bypass[i] - 1; + } + hdr_lut_param.lut_on = LUT_ON; + hdr_lut_param.bitdepth = bit_depth; + /*for g12a/g12b osd blend shift rtl bug*/ + if (((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)) && + (module_sel & OSD1_HDR)) + hdr_lut_param.cgain_en = LUT_ON; + else + hdr_lut_param.cgain_en = LUT_OFF; + } else if (hdr_process_select & HDR_OFF) { + for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) { + hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i]; + hdr_lut_param.ogain_lut[i] = + oo_y_lut_hdr_sdr[i]; + if (i < HDR2_EOTF_LUT_SIZE) + hdr_lut_param.eotf_lut[i] = + eo_y_lut_hdr[i]; + if (i < HDR2_CGAIN_LUT_SIZE) + hdr_lut_param.cgain_lut[i] = + cgain_lut1[i] - 1; + } + hdr_lut_param.lut_on = LUT_OFF; + hdr_lut_param.bitdepth = bit_depth; + hdr_lut_param.cgain_en = LUT_OFF; + } else { + return; + } + /*mtx parameters*/ + if (hdr_process_select & (HDR_BYPASS | HLG_BYPASS)) { + hdr_mtx_param.mtx_only = HDR_ONLY; + /*for g12a/g12b osd blend shift rtl bug*/ + if (((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || + (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B && + get_cpu_id().chip_rev == MESON_CPU_CHIP_REVISION_A)) && + (hdr_process_select & HDR_BYPASS) && + (module_sel & (OSD1_HDR | VD1_HDR | VD2_HDR))) { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i]; + if (module_sel & OSD1_HDR) + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_709[i]; + else + hdr_mtx_param.mtx_out[i] = bypass_coeff[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + bypass_coeff[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pos[i]; + if (module_sel & OSD1_HDR) { + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } else { + hdr_mtx_param.mtxo_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + bypass_pos[i]; + } + } + } + hdr_mtx_param.mtx_on = MTX_ON; + hdr_mtx_param.p_sel = HDR_BYPASS; + } else if (((get_cpu_id().family_id >= + MESON_CPU_MAJOR_ID_SM1) || + (get_cpu_id().family_id == + MESON_CPU_MAJOR_ID_G12B && + get_cpu_id().chip_rev == + MESON_CPU_CHIP_REVISION_B)) && + (module_sel & (OSD1_HDR | VD1_HDR | VD2_HDR))) { + for (i = 0; i < 15; i++) { + if (module_sel & OSD1_HDR) + hdr_mtx_param.mtx_in[i] = rgb2ycbcr_709[i]; + else + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_out[i] = bypass_coeff[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + bypass_coeff[i]; + if (i < 3) { + if (module_sel & OSD1_HDR) { + hdr_mtx_param.mtxi_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + rgb2yuvpos[i]; + } else { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pos[i]; + } + hdr_mtx_param.mtxo_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + bypass_pos[i]; + } + } + if (module_sel & OSD1_HDR) { + hdr_mtx_param.mtx_on = MTX_OFF; + hdr_mtx_param.p_sel = HDR_BYPASS; + hdr_mtx_param.mtx_only = MTX_ONLY; + } else { + hdr_mtx_param.mtx_on = MTX_ON; + hdr_mtx_param.p_sel = HDR_BYPASS; + hdr_mtx_param.mtx_only = HDR_ONLY; + } + } else { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_out[i] = bypass_coeff[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + bypass_coeff[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + bypass_pos[i]; + } + } + hdr_mtx_param.mtx_on = MTX_OFF; + hdr_mtx_param.p_sel = HDR_BYPASS; + } + } else if (hdr_process_select & (HDR_SDR | HLG_SDR)) { + hdr_mtx_param.mtx_only = HDR_ONLY; + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = ycbcr2rgb_ncl2020[i]; + hdr_mtx_param.mtx_cgain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_709[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = ncl_2020_709[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + yuv2rgbpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + yuv2rgbpos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } + hdr_mtx_param.mtx_on = MTX_ON; + + if (hdr_process_select & HDR_SDR) + hdr_mtx_param.p_sel = HDR_SDR; + else if (hdr_process_select & HLG_SDR) + hdr_mtx_param.p_sel = HLG_SDR; + } else if (hdr_process_select & SDR_HDR) { + hdr_mtx_param.mtx_only = HDR_ONLY; + if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) && + (module_sel & OSD1_HDR)) { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_cgain[i] = + rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + ncl_709_2020[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } + } else { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i]; + hdr_mtx_param.mtx_cgain[i] = + rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + ncl_709_2020[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + yuv2rgbpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + yuv2rgbpos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } + } + hdr_mtx_param.mtx_on = MTX_ON; + hdr_mtx_param.p_sel = SDR_HDR; + } else if (hdr_process_select & HLG_HDR) { + hdr_mtx_param.mtx_only = HDR_ONLY; + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = ycbcr2rgb_ncl2020[i]; + hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = bypass_coeff[i]; + } + hdr_mtx_param.mtx_on = MTX_ON; + hdr_mtx_param.p_sel = HLG_HDR; + } else if (hdr_process_select & SDR_HLG) { + hdr_mtx_param.mtx_only = HDR_ONLY; + if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) && + (module_sel & OSD1_HDR)) { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_cgain[i] = + rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + ncl_709_2020[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } + } else { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i]; + hdr_mtx_param.mtx_cgain[i] = + rgb2ycbcr_ncl2020[i]; + hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + ncl_709_2020[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + yuv2rgbpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + yuv2rgbpos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + rgb2yuvpos[i]; + } + } + } + hdr_mtx_param.mtx_on = MTX_ON; + hdr_mtx_param.p_sel = SDR_HLG; + } else if (hdr_process_select & HDR_OFF) { + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = rgb2ycbcr_709[i]; + hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_out[i] = bypass_coeff[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + bypass_coeff[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + rgb2yuvpre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + rgb2yuvpos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + bypass_pos[i]; + } + } + hdr_mtx_param.mtx_on = MTX_OFF; + hdr_mtx_param.p_sel = HDR_BYPASS; + hdr_mtx_param.mtx_only = HDR_ONLY; + } else if (hdr_process_select & RGB_BYPASS) { + if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A)) { + /*DV HDR_BYPASS need bypass coeff*/ + for (i = 0; i < 15; i++) { + hdr_mtx_param.mtx_in[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i]; + hdr_mtx_param.mtx_out[i] = bypass_coeff[i]; + if (i < 9) + hdr_mtx_param.mtx_gamut[i] = + bypass_coeff[i]; + if (i < 3) { + hdr_mtx_param.mtxi_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxi_pos_offset[i] = + bypass_pos[i]; + hdr_mtx_param.mtxo_pre_offset[i] = + bypass_pre[i]; + hdr_mtx_param.mtxo_pos_offset[i] = + bypass_pos[i]; + } + } + hdr_mtx_param.mtx_on = MTX_ON; + hdr_mtx_param.p_sel = HDR_BYPASS; + } + } + + set_hdr_matrix(module_sel, HDR_IN_MTX, &hdr_mtx_param); + + set_eotf_lut(module_sel, &hdr_lut_param); + + set_hdr_matrix(module_sel, HDR_GAMUT_MTX, &hdr_mtx_param); + + set_ootf_lut(module_sel, &hdr_lut_param); + + set_oetf_lut(module_sel, &hdr_lut_param); + + set_hdr_matrix(module_sel, HDR_OUT_MTX, &hdr_mtx_param); + + set_c_gain(module_sel, &hdr_lut_param); +}
diff --git a/drivers/amlogic/media/common/vpp/hdr2.h b/drivers/amlogic/media/common/vpp/hdr2.h new file mode 100644 index 0000000..9569826 --- /dev/null +++ b/drivers/amlogic/media/common/vpp/hdr2.h
@@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDR2_H__ +#define __HDR2_H__ + +enum hdr_module_sel { + VD1_HDR = 0x1, + VD2_HDR = 0x2, + OSD1_HDR = 0x4, + VDIN0_HDR = 0x8, + VDIN1_HDR = 0x10, + DI_HDR = 0x20, + HDR_MAX +}; + +enum hdr_matrix_sel { + HDR_IN_MTX = 0x1, + HDR_GAMUT_MTX = 0x2, + HDR_OUT_MTX = 0x4, + HDR_MTX_MAX +}; + +enum hdr_lut_sel { + HDR_EOTF_LUT = 0x1, + HDR_OOTF_LUT = 0x2, + HDR_OETF_LUT = 0x4, + HDR_CGAIN_LUT = 0x8, + HDR_LUT_MAX +}; + +enum hdr_process_sel { + HDR_BYPASS = 0x1, + HDR_SDR = 0x2, + SDR_HDR = 0x4, + HLG_BYPASS = 0x8, + HLG_SDR = 0x10, + HLG_HDR = 0x20, + SDR_HLG = 0X40, + HDRPLUS_SDR = 0x80, + HDR_OFF = 0x100, + RGB_BYPASS = 0x200, + HDR_p_MAX +}; + +#define MTX_ON 1 +#define MTX_OFF 0 + +#define MTX_ONLY 1 +#define HDR_ONLY 0 + +#define LUT_ON 1 +#define LUT_OFF 0 + +#define HDR2_EOTF_LUT_SIZE 143 +#define HDR2_OOTF_LUT_SIZE 149 +#define HDR2_OETF_LUT_SIZE 149 +#define HDR2_CGAIN_LUT_SIZE 65 + +struct hdr_proc_mtx_param_s { + int mtx_only; + int mtx_in[15]; + int mtx_gamut[9]; + int mtx_cgain[15]; + int mtx_ogain[15]; + int mtx_out[15]; + int mtxi_pre_offset[3]; + int mtxi_pos_offset[3]; + int mtxo_pre_offset[3]; + int mtxo_pos_offset[3]; + unsigned int mtx_on; + enum hdr_process_sel p_sel; +}; + +struct hdr_proc_lut_param_s { + int eotf_lut[143]; + int oetf_lut[149]; + int ogain_lut[149]; + int cgain_lut[65]; + unsigned int lut_on; + unsigned int bitdepth; + unsigned int cgain_en; +}; + +void hdr_func(enum hdr_module_sel module_sel, + enum hdr_process_sel hdr_process_select); + +#endif
diff --git a/drivers/amlogic/media/common/vpp/vpp.c b/drivers/amlogic/media/common/vpp/vpp.c index 8283ac9..a511927 100644 --- a/drivers/amlogic/media/common/vpp/vpp.c +++ b/drivers/amlogic/media/common/vpp/vpp.c
@@ -7,8 +7,11 @@ #include <config.h> #include <common.h> #include <amlogic/media/vpp/vpp.h> +#include <amlogic/media/vout/hdmitx/hdmi_common.h> +#include <amlogic/media/vout/hdmitx/hdmitx_module.h> #include "vpp_reg.h" #include "vpp.h" +#include "hdr2.h" #define VPP_PR(fmt, args...) printf("vpp: "fmt"", ## args) @@ -463,6 +466,36 @@ #define FRAC(a) ((((a) >= 0) ? \ ((a) & 0x3ff) : ((~(a) + 1) & 0x3ff)) * 10000 / 1024) +#define INORM 50000 +static u32 bt2020_primaries[3][2] = { + {0.17 * INORM + 0.5, 0.797 * INORM + 0.5}, /* G */ + {0.131 * INORM + 0.5, 0.046 * INORM + 0.5}, /* B */ + {0.708 * INORM + 0.5, 0.292 * INORM + 0.5}, /* R */ +}; + +static u32 bt2020_white_point[2] = { + 0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5 +}; + +static int vpp_get_chip_type(void) +{ + unsigned int cpu_type; + + cpu_type = get_cpu_id().family_id; + return cpu_type; +} + +int is_osd_high_version(void) +{ + u32 family_id = get_cpu_id().family_id; + + if (family_id == MESON_CPU_MAJOR_ID_G12A || + family_id == MESON_CPU_MAJOR_ID_G12B || + family_id >= MESON_CPU_MAJOR_ID_SM1) + return 1; + else + return 0; +} /* OSD csc defines end */ @@ -478,9 +511,7 @@ int *m = NULL; - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1)){ + if (is_osd_high_version()) { /* POST2 matrix: YUV limit -> RGB default is 12bit*/ m = YUV709l_to_RGB709_coeff12; @@ -851,7 +882,7 @@ for (i = 0; i < 16; i++) vpp_reg_write(data_port, g_map[i * 2 + 1] - | (b_map[i * 2 + 2] << 16)); + | (g_map[i * 2 + 2] << 16)); for (i = 0; i < 16; i++) vpp_reg_write(data_port, b_map[i * 2] @@ -896,10 +927,7 @@ { int *m = NULL; - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) { + if (is_osd_high_version()) { /* RGB -> 709 limit */ m = RGB709_to_YUV709l_coeff; @@ -959,10 +987,7 @@ { int *m = NULL; - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) { + if (is_osd_high_version()) { /* RGB -> 709 limit */ m = RGB709_to_YUV709l_coeff; @@ -1000,9 +1025,7 @@ { int *m = NULL; - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) { + if (is_osd_high_version()) { /* RGB -> 709 limit */ m = RGB709_to_YUV709l_coeff; @@ -1033,52 +1056,78 @@ } } +static void set_viu2_osd_matrix_rgb2yuv(bool on) +{ + int *m = RGB709_to_YUV709l_coeff; + + /* RGB -> 709 limit */ + if (is_osd_high_version()) { + /* VPP WRAP OSD3 matrix */ + vpp_reg_write(VIU2_OSD1_MATRIX_PRE_OFFSET0_1, + ((m[0] & 0xfff) << 16) | (m[1] & 0xfff)); + vpp_reg_write(VIU2_OSD1_MATRIX_PRE_OFFSET2, + m[2] & 0xfff); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF00_01, + ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff)); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF02_10, + ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff)); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF11_12, + ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff)); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF20_21, + ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff)); + vpp_reg_write(VIU2_OSD1_MATRIX_COEF22, + m[11] & 0x1fff); + + vpp_reg_write(VIU2_OSD1_MATRIX_OFFSET0_1, + ((m[18] & 0xfff) << 16) | (m[19] & 0xfff)); + vpp_reg_write(VIU2_OSD1_MATRIX_OFFSET2, + m[20] & 0xfff); + + vpp_reg_setb(VIU2_OSD1_MATRIX_EN_CTRL, on, 0, 1); + } +} + +static void set_vpp_osd2_rgb2yuv(bool on) +{ + int *m = NULL; + + /* RGB -> 709 limit */ + m = RGB709_to_YUV709l_coeff; + + /* VPP WRAP OSD3 matrix */ + vpp_reg_write(VPP_OSD2_MATRIX_PRE_OFFSET0_1, + ((m[0] & 0xfff) << 16) | (m[1] & 0xfff)); + vpp_reg_write(VPP_OSD2_MATRIX_PRE_OFFSET2, + m[2] & 0xfff); + vpp_reg_write(VPP_OSD2_MATRIX_COEF00_01, + ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff)); + vpp_reg_write(VPP_OSD2_MATRIX_COEF02_10, + ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff)); + vpp_reg_write(VPP_OSD2_MATRIX_COEF11_12, + ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff)); + vpp_reg_write(VPP_OSD2_MATRIX_COEF20_21, + ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff)); + vpp_reg_write(VPP_OSD2_MATRIX_COEF22, + m[11] & 0x1fff); + vpp_reg_write(VPP_OSD2_MATRIX_OFFSET0_1, + ((m[18] & 0xfff) << 16) | (m[19] & 0xfff)); + vpp_reg_write(VPP_OSD2_MATRIX_OFFSET2, + m[20] & 0xfff); + vpp_reg_setb(VPP_OSD2_MATRIX_EN_CTRL, on, 0, 1); + VPP_PR("vpp osd2 matrix rgb2yuv..............\n"); +} + /* for txlx, set vpp default data path to u10 */ static void set_vpp_bitdepth(void) { - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) || - (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) { + if (is_osd_high_version()) { /*after this step vd1 output data is U12,*/ vpp_reg_write(DOLBY_PATH_CTRL, 0xf); } } -static void vpp_set_post_matrix_rgb2ycbcr(int mode) -{ - /* enable post matrix */ - vpp_reg_setb(VPP_MATRIX_CTRL, 1, 0, 1); - vpp_reg_setb(VPP_MATRIX_CTRL, 0, 8, 3); - vpp_reg_setb(VPP_MATRIX_CTRL, 0, 1, 2); - - if (mode == 0) { - /* RGB -> 709 limit */ - vpp_reg_write(VPP_MATRIX_COEF00_01, 0x00bb0275); - vpp_reg_write(VPP_MATRIX_COEF02_10, 0x003f1f99); - vpp_reg_write(VPP_MATRIX_COEF11_12, 0x1ea601c2); - vpp_reg_write(VPP_MATRIX_COEF20_21, 0x01c21e67); - vpp_reg_write(VPP_MATRIX_COEF22, 0x00001fd7); - vpp_reg_write(VPP_MATRIX_OFFSET0_1, 0x00400200); - vpp_reg_write(VPP_MATRIX_OFFSET2, 0x00000200); - vpp_reg_write(VPP_MATRIX_PRE_OFFSET0_1, 0x0); - vpp_reg_write(VPP_MATRIX_PRE_OFFSET2, 0x0); - } else { - /* RGB -> 709 full */ - vpp_reg_write(VPP_MATRIX_COEF00_01, 0xda02dc); - vpp_reg_write(VPP_MATRIX_COEF02_10, 0x4a1f8a); - vpp_reg_write(VPP_MATRIX_COEF11_12, 0x1e760200); - vpp_reg_write(VPP_MATRIX_COEF20_21, 0x2001e2f); - vpp_reg_write(VPP_MATRIX_COEF22, 0x1fd1); - vpp_reg_write(VPP_MATRIX_OFFSET0_1, 0x200); - vpp_reg_write(VPP_MATRIX_OFFSET2, 0x200); - vpp_reg_write(VPP_MATRIX_PRE_OFFSET0_1, 0x0); - vpp_reg_write(VPP_MATRIX_PRE_OFFSET2, 0x0); - } -} - /* osd+video brightness */ static void video_adj2_brightness(int val) { @@ -1261,6 +1310,9 @@ if (!(vpp_reg_read(ENCL_VIDEO_EN) & 0x1)) return; + vpp_reg_setb(L_GAMMA_CNTL_PORT, + 0, GAMMA_EN, 1); + while (!(vpp_reg_read(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY))) { udelay(10); if (cnt++ > GAMMA_RETRY) @@ -1322,6 +1374,30 @@ } } +void vpp_viu2_matrix_update(int type) +{ + if (vpp_init_flag == 0) + return; + + if (get_cpu_id().family_id < MESON_CPU_MAJOR_ID_G12A) + return; + + VPP_PR("%s: %d\n", __func__, type); + + switch (type) { + case VPP_CM_RGB: + /* default RGB */ + set_viu2_osd_matrix_rgb2yuv(0); + break; + case VPP_CM_YUV: + /* RGB to 709 limit */ + set_viu2_osd_matrix_rgb2yuv(1); + break; + default: + break; + } +} + static void vpp_ofifo_init(void) { unsigned int data32; @@ -1334,10 +1410,84 @@ vpp_reg_write(VPP_HOLD_LINES, data32); } +static void amvecm_cp_hdr_info(struct master_display_info_s *hdr_data) +{ + int i, j; + + hdr_data->features = + (0 << 30) /*sdr output 709*/ + | (1 << 29) /*video available*/ + | (5 << 26) /* unspecified */ + | (0 << 25) /* limit */ + | (1 << 24) /* color available */ + | (9 << 16) /* bt2020 */ + | (16 << 8) /* bt2020-10 */ + | (10 << 0); /* bt2020c */ + + for (i = 0; i < 3; i++) + for (j = 0; j < 2; j++) + hdr_data->primaries[i][j] = + bt2020_primaries[i][j]; + hdr_data->white_point[0] = bt2020_white_point[0]; + hdr_data->white_point[1] = bt2020_white_point[1]; + /* default luminance */ + hdr_data->luminance[0] = 1000 * 10000; + hdr_data->luminance[1] = 50; + + /* content_light_level */ + hdr_data->max_content = 0; + hdr_data->max_frame_average = 0; + hdr_data->luminance[0] = hdr_data->luminance[0] / 10000; + hdr_data->present_flag = 1; +} + +void hdr_tx_pkt_cb(void) +{ + int hdr_policy = 0; + struct master_display_info_s hdr_data; + struct hdr_info *hdrinfo; + const char *hdr_policy_env = env_get("hdr_policy"); + + if (!hdr_policy_env) + return; + + hdr_policy = simple_strtoul(hdr_policy_env, NULL, 10); + hdrinfo = hdmitx_get_rx_hdr_info(); + + if ((hdrinfo && hdrinfo->hdr_sup_eotf_smpte_st_2084) && + hdr_policy == 0) { + hdr_func(OSD1_HDR, SDR_HDR); + hdr_func(VD1_HDR, SDR_HDR); + amvecm_cp_hdr_info(&hdr_data); + hdmitx_set_drm_pkt(&hdr_data); + } + + VPP_PR("hdr_policy = %d\n", hdr_policy); + if (hdrinfo) + VPP_PR("Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = %d\n", + hdrinfo->hdr_sup_eotf_smpte_st_2084); +} + +static bool is_vpp_supported(int chip_id) +{ + if ((chip_id == MESON_CPU_MAJOR_ID_A1) || + (chip_id == MESON_CPU_MAJOR_ID_C1) || + (chip_id == MESON_CPU_MAJOR_ID_C2)) + return false; + else + return true; +} + void vpp_init(void) { - VPP_PR("%s\n", __func__); + int chip_id; + chip_id = vpp_get_chip_type(); + //VPP_PR("%s, chip_id=%d\n", __func__, chip_id); + if (!is_vpp_supported(chip_id)) { + VPP_PR("%s, vpp not supported\n", __func__); + return; + } vpp_init_flag = 1; /* init vpu fifo control register */ @@ -1345,36 +1495,19 @@ vpp_set_matrix_default_init(); - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) { - /* osd1: rgb->yuv limit,osd2: rgb2yuv limit,osd3: rgb2yuv limit*/ - set_osd1_rgb2yuv(1); - set_osd2_rgb2yuv(1); - set_osd3_rgb2yuv(1); + if (is_osd_high_version()) { + /* >= g12a: osd out is rgb */ + set_osd1_rgb2yuv(0); + set_osd2_rgb2yuv(0); + if (chip_id != MESON_CPU_MAJOR_ID_TL1) + set_osd3_rgb2yuv(0); + set_vpp_osd2_rgb2yuv(1); /* set vpp data path to u12 */ set_vpp_bitdepth(); - } else if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) { - /* osd1: rgb->yuv limit,osd2: rgb2yuv limit,osd3: rgb2yuv limit*/ - set_osd1_rgb2yuv(1); - set_osd2_rgb2yuv(1); - set_osd3_rgb2yuv(1); - - /* set vpp data path to u12 */ - set_vpp_bitdepth(); - } else if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) { - set_osd1_rgb2yuv(1); - set_osd2_rgb2yuv(1); - - /* set vpp data path to u12 */ - set_vpp_bitdepth(); - } else if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1) { - /* osd1: rgb->yuv limit,osd2: rgb2yuv limit,osd3: rgb2yuv limit*/ - set_osd1_rgb2yuv(1); - set_osd2_rgb2yuv(1); - set_osd3_rgb2yuv(1); - - /* set vpp data path to u12 */ - set_vpp_bitdepth(); + hdr_func(OSD1_HDR, HDR_BYPASS); + hdr_func(VD1_HDR, HDR_BYPASS); + hdr_func(VD2_HDR, HDR_BYPASS); } else { /* set dummy data default YUV black */ vpp_reg_write(VPP_DUMMY_DATA1, 0x108080);
diff --git a/drivers/amlogic/media/common/vpp/vpp_reg.h b/drivers/amlogic/media/common/vpp/vpp_reg.h index a890a6c..7c423db 100644 --- a/drivers/amlogic/media/common/vpp/vpp_reg.h +++ b/drivers/amlogic/media/common/vpp/vpp_reg.h
@@ -11,12 +11,17 @@ /* ******************************** * register define * ********************************* */ +#ifndef REG_BASE_VCBUS +#define REG_BASE_VCBUS (0xFF900000L) +#endif /* base & offset */ //#define REG_BASE_VCBUS (0xd0100000L) #define REG_OFFSET_VCBUS(reg) ((reg) << 2) /* memory mapping */ #define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg)) +#define REG_VPP_ADDR(reg) (reg + 0L) + #ifdef VPP_EOTF_CTL #define VIU_EOTF_CTL VPP_EOTF_CTL #endif @@ -193,6 +198,105 @@ #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd #endif +#ifndef VIU2_OSD1_MATRIX_COEF00_01 +#define VIU2_OSD1_MATRIX_COEF00_01 0x1e70 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF02_10 +#define VIU2_OSD1_MATRIX_COEF02_10 0x1e71 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF11_12 +#define VIU2_OSD1_MATRIX_COEF11_12 0x1e72 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF20_21 +#define VIU2_OSD1_MATRIX_COEF20_21 0x1e73 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF22 +#define VIU2_OSD1_MATRIX_COEF22 0x1e74 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF13_14 +#define VIU2_OSD1_MATRIX_COEF13_14 0x1e75 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF23_24 +#define VIU2_OSD1_MATRIX_COEF23_24 0x1e76 +#endif +#ifndef VIU2_OSD1_MATRIX_COEF15_25 +#define VIU2_OSD1_MATRIX_COEF15_25 0x1e77 +#endif +#ifndef VIU2_OSD1_MATRIX_CLIP +#define VIU2_OSD1_MATRIX_CLIP 0x1e78 +#endif +#ifndef VIU2_OSD1_MATRIX_OFFSET0_1 +#define VIU2_OSD1_MATRIX_OFFSET0_1 0x1e79 +#endif +#ifndef VIU2_OSD1_MATRIX_OFFSET2 +#define VIU2_OSD1_MATRIX_OFFSET2 0x1e7a +#endif +#ifndef VIU2_OSD1_MATRIX_PRE_OFFSET0_1 +#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 0x1e7b +#endif +#ifndef VIU2_OSD1_MATRIX_PRE_OFFSET2 +#define VIU2_OSD1_MATRIX_PRE_OFFSET2 0x1e7c +#endif +#ifndef VIU2_OSD1_MATRIX_EN_CTRL +#define VIU2_OSD1_MATRIX_EN_CTRL 0x1e7d +#endif + +#ifndef VPP_OSD2_MATRIX_COEF00_01 +#define VPP_OSD2_MATRIX_COEF00_01 0x3920 +#endif + +#ifndef VPP_OSD2_MATRIX_COEF02_10 +#define VPP_OSD2_MATRIX_COEF02_10 0x3921 +#endif + +#ifndef VPP_OSD2_MATRIX_COEF11_12 +#define VPP_OSD2_MATRIX_COEF11_12 0x3922 +#endif + +#ifndef VPP_OSD2_MATRIX_COEF20_21 +#define VPP_OSD2_MATRIX_COEF20_21 0x3923 +#endif + +#ifndef VPP_OSD2_MATRIX_COEF22 +#define VPP_OSD2_MATRIX_COEF22 0x3924 +#endif + +#ifndef VPP_OSD2_MATRIX_COEF13_14 +#define VPP_OSD2_MATRIX_COEF13_14 0x3925 +#endif + +#ifndef VPP_OSD2_MATRIX_COEF23_24 +#define VPP_OSD2_MATRIX_COEF23_24 0x3926 +#endif + +#ifndef VPP_OSD2_MATRIX_COEF15_25 +#define VPP_OSD2_MATRIX_COEF15_25 0x3927 +#endif + +#ifndef VPP_OSD2_MATRIX_CLIP +#define VPP_OSD2_MATRIX_CLIP 0x3928 +#endif + +#ifndef VPP_OSD2_MATRIX_OFFSET0_1 +#define VPP_OSD2_MATRIX_OFFSET0_1 0x3929 +#endif + +#ifndef VPP_OSD2_MATRIX_OFFSET2 +#define VPP_OSD2_MATRIX_OFFSET2 0x392a +#endif + +#ifndef VPP_OSD2_MATRIX_PRE_OFFSET0_1 +#define VPP_OSD2_MATRIX_PRE_OFFSET0_1 0x392b +#endif + +#ifndef VPP_OSD2_MATRIX_PRE_OFFSET2 +#define VPP_OSD2_MATRIX_PRE_OFFSET2 0x392c +#endif + +#ifndef VPP_OSD2_MATRIX_EN_CTRL +#define VPP_OSD2_MATRIX_EN_CTRL 0x392d +#endif + #ifndef DOLBY_PATH_CTRL #define DOLBY_PATH_CTRL 0x1a0c #endif @@ -223,12 +327,21 @@ static inline unsigned int vpp_reg_read(unsigned int _reg) { - return (*(volatile unsigned int *)REG_ADDR_VCBUS(_reg)); + unsigned int val; + + if (_reg > 0x10000) + val = *(volatile unsigned int *)REG_VPP_ADDR(_reg); + else + val = *(volatile unsigned int *)REG_ADDR_VCBUS(_reg); + return val; }; static inline void vpp_reg_write(unsigned int _reg, unsigned int _value) { - *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value); + if (_reg > 0x10000) + *(volatile unsigned int *)REG_VPP_ADDR(_reg) = (_value); + else + *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value); }; static inline void vpp_reg_setb(unsigned int _reg, unsigned int _value,
diff --git a/drivers/amlogic/media/common/vpu/vpu.c b/drivers/amlogic/media/common/vpu/vpu.c index a3b713b..7e83727 100644 --- a/drivers/amlogic/media/common/vpu/vpu.c +++ b/drivers/amlogic/media/common/vpu/vpu.c
@@ -13,7 +13,8 @@ /* v20181009: init version */ /* v20190313: add sm1 support */ -#define VPU_VERION "v20190313" +/* v20200521: add sc2 support */ +#define VPU_VERION "v20200521" DECLARE_GLOBAL_DATA_PTR; @@ -31,16 +32,25 @@ .clk_level_max = CLK_LEVEL_MAX_G12A, .gp_pll_valid = 0, + .vpu_clk_reg = HHI_VPU_CLK_CNTL, + .vapb_clk_reg = HHI_VAPBCLK_CNTL, + .vid_clk_reg = HHI_VID_CLK_CNTL2, + + .pwrctrl_id = VPU_PWR_ID_INVALID, + .fclk_div_table = fclk_div_table_g12a, .vpu_clk_table = vpu_clk_table, .mem_pd_table = vpu_mem_pd_g12a, - .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb, - .hdmi_iso_table = vpu_hdmi_iso_gxb, + .power_table = vpu_pwr_gxb, + .iso_table = vpu_iso_gxb, .reset_table = vpu_reset_g12a, .module_init_table_cnt = 0, .module_init_table = NULL, + + .power_on = vpu_power_on, + .power_off = vpu_power_off, }; static struct vpu_data_s vpu_data_g12b = { @@ -50,16 +60,25 @@ .clk_level_max = CLK_LEVEL_MAX_G12A, .gp_pll_valid = 0, + .vpu_clk_reg = HHI_VPU_CLK_CNTL, + .vapb_clk_reg = HHI_VAPBCLK_CNTL, + .vid_clk_reg = HHI_VID_CLK_CNTL2, + + .pwrctrl_id = VPU_PWR_ID_INVALID, + .fclk_div_table = fclk_div_table_g12a, .vpu_clk_table = vpu_clk_table, .mem_pd_table = vpu_mem_pd_g12a, - .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb, - .hdmi_iso_table = vpu_hdmi_iso_gxb, + .power_table = vpu_pwr_gxb, + .iso_table = vpu_iso_gxb, .reset_table = vpu_reset_g12a, .module_init_table_cnt = 0, .module_init_table = NULL, + + .power_on = vpu_power_on, + .power_off = vpu_power_off, }; static struct vpu_data_s vpu_data_tl1 = { @@ -69,16 +88,25 @@ .clk_level_max = CLK_LEVEL_MAX_G12A, .gp_pll_valid = 0, + .vpu_clk_reg = HHI_VPU_CLK_CNTL, + .vapb_clk_reg = HHI_VAPBCLK_CNTL, + .vid_clk_reg = HHI_VID_CLK_CNTL2, + + .pwrctrl_id = VPU_PWR_ID_INVALID, + .fclk_div_table = fclk_div_table_g12a, .vpu_clk_table = vpu_clk_table, .mem_pd_table = vpu_mem_pd_tl1, - .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb, - .hdmi_iso_table = vpu_hdmi_iso_gxb, + .power_table = vpu_pwr_gxb, + .iso_table = vpu_iso_gxb, .reset_table = vpu_reset_tl1, .module_init_table_cnt = 0, .module_init_table = NULL, + + .power_on = vpu_power_on, + .power_off = vpu_power_off, }; /* static struct vpu_data_s vpu_data_sm1 = { @@ -88,16 +116,25 @@ .clk_level_max = CLK_LEVEL_MAX_G12A, .gp_pll_valid = 0, + .vpu_clk_reg = HHI_VPU_CLK_CNTL, + .vapb_clk_reg = HHI_VAPBCLK_CNTL, + .vid_clk_reg = HHI_VID_CLK_CNTL2, + + .pwrctrl_id = VPU_PWR_ID_INVALID, + .fclk_div_table = fclk_div_table_g12a, .vpu_clk_table = vpu_clk_table, .mem_pd_table = vpu_mem_pd_tl1, - .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb, - .hdmi_iso_table = vpu_hdmi_iso_sm1, + .power_table = vpu_pwr_gxb, + .iso_table = vpu_iso_sm1, .reset_table = vpu_reset_gx, .module_init_table_cnt = 0, .module_init_table = NULL, + + .power_on = vpu_power_on, + .power_off = vpu_power_off, }; */ @@ -108,16 +145,53 @@ .clk_level_max = CLK_LEVEL_MAX_G12A, .gp_pll_valid = 0, + .vpu_clk_reg = HHI_VPU_CLK_CNTL, + .vapb_clk_reg = HHI_VAPBCLK_CNTL, + .vid_clk_reg = HHI_VID_CLK_CNTL2, + + .pwrctrl_id = VPU_PWR_ID_INVALID, + .fclk_div_table = fclk_div_table_g12a, .vpu_clk_table = vpu_clk_table, .mem_pd_table = vpu_mem_pd_tm2, - .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb, - .hdmi_iso_table = vpu_hdmi_iso_sm1, + .power_table = vpu_pwr_gxb, + .iso_table = vpu_iso_sm1, .reset_table = vpu_reset_tl1, .module_init_table_cnt = 0, .module_init_table = NULL, + + .power_on = vpu_power_on, + .power_off = vpu_power_off, +}; + +static struct vpu_data_s vpu_data_sc2 = { + .chip_type = VPU_CHIP_SC2, + .chip_name = "sc2", + .clk_level_dft = CLK_LEVEL_DFT_G12A, + .clk_level_max = CLK_LEVEL_MAX_G12A, + .gp_pll_valid = 0, + + .vpu_clk_reg = CLKCTRL_VPU_CLK_CTRL, + .vapb_clk_reg = CLKCTRL_VAPBCLK_CTRL, + .vid_clk_reg = CLKCTRL_VID_CLK_CTRL2, + + .pwrctrl_id = PM_VPU_HDMI, + + .fclk_div_table = fclk_div_table_g12a, + .vpu_clk_table = vpu_clk_table, + + .mem_pd_table = NULL, + .power_table = NULL, + .iso_table = NULL, + .reset_table = NULL, + + .module_init_table_cnt = 0, + .module_init_table = NULL, + + .power_on = vpu_power_on_new, + .power_off = vpu_power_off_new, }; static void vpu_chip_detect(void) @@ -142,8 +216,11 @@ case MESON_CPU_MAJOR_ID_TM2: vpu_conf.data = &vpu_data_tm2; break; + case MESON_CPU_MAJOR_ID_SC2: + vpu_conf.data = &vpu_data_sc2; + break; default: - vpu_conf.data = &vpu_data_g12a; + vpu_conf.data = &vpu_data_sc2; break; } #else @@ -182,6 +259,7 @@ case VPU_CHIP_TL1: case VPU_CHIP_SM1: case VPU_CHIP_TM2: + case VPU_CHIP_SC2: ret = 0; break; default: @@ -233,7 +311,7 @@ struct fclk_div_s *fclk_div; unsigned int i, mux, mux_id; - mux = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 9, 3); + mux = vpu_hiu_getb(vpu_conf.data->vpu_clk_reg, 9, 3); mux_id = mux; for (i = 0; i < FCLK_DIV_MAX; i++) { fclk_div = vpu_conf.data->fclk_div_table + i; @@ -289,7 +367,7 @@ break; } - div = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 0, 7) + 1; + div = vpu_hiu_getb(vpu_conf.data->vpu_clk_reg, 0, 7) + 1; clk_freq = ((clk_source * 100 / div) + 99) / 100; return (unsigned int)clk_freq; @@ -314,7 +392,7 @@ { struct vpu_clk_s *clk_table; unsigned int vpu_clk; - unsigned int mux, div; + unsigned int mux, div, clk_reg, vapb_reg; int ret = 0; /* vpu clk */ @@ -333,24 +411,26 @@ vpu_clk = clk_table->freq; mux = get_vpu_clk_mux(clk_table->mux); div = clk_table->div; + clk_reg = vpu_conf.data->vpu_clk_reg; + vapb_reg = vpu_conf.data->vapb_clk_reg; - vpu_hiu_write(HHI_VPU_CLK_CNTL, ((mux << 9) | (div << 0))); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 1, 8, 1); + vpu_hiu_write(clk_reg, ((mux << 9) | (div << 0))); + vpu_hiu_setb(clk_reg, 1, 8, 1); /* vapb clk */ if (vpu_clk >= 250000000) { - vpu_hiu_write(HHI_VAPBCLK_CNTL, (1 << 30) | /* turn on ge2d clock */ + vpu_hiu_write(vapb_reg, (1 << 30) | /* turn on ge2d clock */ (0 << 9) | /* clk_sel //250Mhz */ (1 << 0)); /* clk_div */ } else { - vpu_hiu_write(HHI_VAPBCLK_CNTL, (1 << 30) | /* turn on ge2d clock */ + vpu_hiu_write(vapb_reg, (1 << 30) | /* turn on ge2d clock */ (clk_table->mux << 9) | /* clk_sel */ (div << 0)); /* clk_div */ } - vpu_hiu_setb(HHI_VAPBCLK_CNTL, 1, 8, 1); + vpu_hiu_setb(vapb_reg, 1, 8, 1); VPUPR("set clk: %uHz, readback: %uHz(0x%x)\n", - vpu_clk, get_vpu_clk(), (vpu_hiu_read(HHI_VPU_CLK_CNTL))); + vpu_clk, get_vpu_clk(), (vpu_hiu_read(clk_reg))); return ret; } @@ -436,9 +516,9 @@ return -1; ret = get_vpu_config(); - vpu_power_on(); + if (vpu_conf.data->power_on) + vpu_conf.data->power_on(); set_vpu_clk(vpu_conf.clk_level); - //vpu_power_on(); /* vpu module init off, for power save, and special module init */ vpu_mem_pd_init_off(); @@ -453,36 +533,40 @@ return -1; VPUPR("vpu remove\n"); - vpu_power_off(); + if (vpu_conf.data->power_off) + vpu_conf.data->power_off(); + return 0; } static void vpu_clk_switch(void) { struct vpu_clk_s *clk_table; - unsigned int mux, div; + unsigned int mux, div, clk_reg; + + clk_reg = vpu_conf.data->vpu_clk_reg; /* step 1: switch to 2nd vpu clk patch */ clk_table = vpu_conf.data->vpu_clk_table + vpu_conf.data->clk_level_dft; mux = get_vpu_clk_mux(clk_table->mux); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, mux, 25, 3); + vpu_hiu_setb(clk_reg, mux, 25, 3); div = clk_table->div; - vpu_hiu_setb(HHI_VPU_CLK_CNTL, div, 16, 7); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 1, 24, 1); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 1, 31, 1); + vpu_hiu_setb(clk_reg, div, 16, 7); + vpu_hiu_setb(clk_reg, 1, 24, 1); + vpu_hiu_setb(clk_reg, 1, 31, 1); udelay(10); /* step 2: adjust 1st vpu clk frequency */ clk_table = vpu_conf.data->vpu_clk_table + vpu_conf.clk_level; - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 8, 1); + vpu_hiu_setb(clk_reg, 0, 8, 1); mux = get_vpu_clk_mux(clk_table->mux); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, mux, 9, 3); + vpu_hiu_setb(clk_reg, mux, 9, 3); div = clk_table->div; - vpu_hiu_setb(HHI_VPU_CLK_CNTL, div, 0, 7); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 1, 8, 1); + vpu_hiu_setb(clk_reg, div, 0, 7); + vpu_hiu_setb(clk_reg, 1, 8, 1); udelay(20); /* step 3: switch back to 1st vpu clk patch */ - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 31, 1); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 24, 1); + vpu_hiu_setb(clk_reg, 0, 31, 1); + vpu_hiu_setb(clk_reg, 0, 24, 1); } int vpu_clk_change(int level) @@ -512,7 +596,7 @@ vpu_clk_switch(); VPUPR("set clk: %uHz, readback: %uHz(0x%x)\n", - vpu_clk, get_vpu_clk(), vpu_hiu_read(HHI_VPU_CLK_CNTL)); + vpu_clk, get_vpu_clk(), vpu_hiu_read(vpu_conf.data->vpu_clk_reg)); return 0; } @@ -523,7 +607,7 @@ VPUPR("clk_level: %u, clk: %uHz, reg: 0x%x\n", vpu_conf.clk_level, get_vpu_clk(), - vpu_hiu_read(HHI_VPU_CLK_CNTL)); + vpu_hiu_read(vpu_conf.data->vpu_clk_reg)); } void vpu_info_print(void) @@ -548,10 +632,10 @@ #define VCBUS_REG_CNT_MAX 4 static unsigned int vcbus_reg[VCBUS_REG_CNT_MAX] = { - 0x1b7f, /* VENC_VDAC_TST_VAL */ - 0x1c30, /* ENCP_DVI_HSO_BEGIN */ - 0x1d00, /* VPP_DUMMY_DATA */ - 0x2730, /* VPU_VPU_PWM_V0 */ + VENC_VDAC_TST_VAL, + ENCP_DVI_HSO_BEGIN, + VPP_DUMMY_DATA, + VPU_VPU_PWM_V0, }; void vcbus_test(void)
diff --git a/drivers/amlogic/media/common/vpu/vpu.h b/drivers/amlogic/media/common/vpu/vpu.h index d5d9e6e..e08f41a 100644 --- a/drivers/amlogic/media/common/vpu/vpu.h +++ b/drivers/amlogic/media/common/vpu/vpu.h
@@ -5,6 +5,9 @@ #ifndef __VPU_PARA_H__ #define __VPU_PARA_H__ +#ifdef CONFIG_SECURE_POWER_CONTROL +#include <asm/arch/pwr_ctrl.h> +#endif /* #define VPU_DEBUG_PRINT */ #define VPUPR(fmt, args...) printf("vpu: "fmt"", ## args) @@ -13,15 +16,24 @@ enum vpu_chip_e { VPU_CHIP_G12A = 0, VPU_CHIP_G12B, /* 1 */ - VPU_CHIP_TL1, /* 10 */ - VPU_CHIP_SM1, /* 11 */ - VPU_CHIP_TM2, /* 12 */ + VPU_CHIP_TL1, /* 2 */ + VPU_CHIP_SM1, /* 3 */ + VPU_CHIP_TM2, /* 4 */ + VPU_CHIP_SC2, /* 5 */ VPU_CHIP_MAX, }; +#define VPU_PWR_ON 1 +#define VPU_PWR_OFF 0 +#define VPU_PWR_ID_INVALID 0xffff +#ifndef PM_VPU_HDMI +#define PM_VPU_HDMI 5 +#endif + #define VPU_REG_END 0xffff #define VPU_MEM_PD_CNT_MAX 10 -#define VPU_HDMI_ISO_CNT_MAX 5 +#define VPU_ISO_CNT_MAX 5 +#define VPU_PWR_CNT_MAX 5 #define VPU_RESET_CNT_MAX 10 struct fclk_div_s { @@ -55,16 +67,25 @@ unsigned char clk_level_max; unsigned char gp_pll_valid; + unsigned int vpu_clk_reg; + unsigned int vapb_clk_reg; + unsigned int vid_clk_reg; + + unsigned int pwrctrl_id; + struct fclk_div_s *fclk_div_table; struct vpu_clk_s *vpu_clk_table; struct vpu_ctrl_s *mem_pd_table; - struct vpu_ctrl_s *hdmi_iso_pre_table; - struct vpu_ctrl_s *hdmi_iso_table; + struct vpu_ctrl_s *power_table; + struct vpu_ctrl_s *iso_table; struct vpu_reset_s *reset_table; unsigned int module_init_table_cnt; struct vpu_ctrl_s *module_init_table; + + void (*power_on)(void); + void (*power_off)(void); }; struct vpu_conf_s { @@ -89,5 +110,7 @@ extern void vpu_power_on(void); extern void vpu_power_off(void); +extern void vpu_power_on_new(void); +extern void vpu_power_off_new(void); #endif
diff --git a/drivers/amlogic/media/common/vpu/vpu_ctrl.h b/drivers/amlogic/media/common/vpu/vpu_ctrl.h index 64c32e5..b0dab07 100644 --- a/drivers/amlogic/media/common/vpu/vpu_ctrl.h +++ b/drivers/amlogic/media/common/vpu/vpu_ctrl.h
@@ -102,48 +102,30 @@ }; /* ******************************************************* */ -/* VPU_HDMI ISO pre: before reset */ +/* VPU_HDMI POWER */ /* ******************************************************* */ -static struct vpu_ctrl_s vpu_hdmi_iso_pre_gxb[] = { +static struct vpu_ctrl_s vpu_pwr_gxb[] = { /* reg, val, bit, len */ - {AO_RTI_GEN_PWR_SLEEP0, 1, 8, 1}, + {AO_RTI_GEN_PWR_SLEEP0, 0, 8, 1}, {VPU_REG_END, 0, 0, 0}, }; /* ******************************************************* */ /* VPU_HDMI ISO */ /* ******************************************************* */ -static struct vpu_ctrl_s vpu_hdmi_iso_gxb[] = { +static struct vpu_ctrl_s vpu_iso_gxb[] = { /* reg, val, bit, len */ - {AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1}, + {AO_RTI_GEN_PWR_SLEEP0, 0, 9, 1}, {VPU_REG_END, 0, 0, 0}, }; -static struct vpu_ctrl_s vpu_hdmi_iso_sm1[] = { +static struct vpu_ctrl_s vpu_iso_sm1[] = { /* reg, val, bit, len */ - {AO_RTI_GEN_PWR_ISO0, 1, 8, 1}, + {AO_RTI_GEN_PWR_ISO0, 0, 8, 1}, {VPU_REG_END, 0, 0, 0}, }; /* ******************************************************* */ -/* VPU module init table */ -/* ******************************************************* */ -#if 0 -static struct vpu_ctrl_s vpu_module_init_txlx[] = { - /* reg, val, bit, len */ - {DOLBY_TV_CLKGATE_CTRL, 1, 10, 2}, - {DOLBY_TV_CLKGATE_CTRL, 1, 2, 2}, - {DOLBY_TV_CLKGATE_CTRL, 1, 4, 2}, - {DOLBY_CORE2A_CLKGATE_CTRL, 1, 10, 2}, - {DOLBY_CORE2A_CLKGATE_CTRL, 1, 2, 2}, - {DOLBY_CORE2A_CLKGATE_CTRL, 1, 4, 2}, - {DOLBY_CORE3_CLKGATE_CTRL, 0, 1, 1}, - {DOLBY_CORE3_CLKGATE_CTRL, 1, 2, 2}, - {VPU_REG_END, 0, 0, 0}, -}; -#endif - -/* ******************************************************* */ /* VPU reset table */ /* ******************************************************* */ static struct vpu_reset_s vpu_reset_g12a[] = { @@ -165,4 +147,22 @@ {RESET7_LEVEL, (1<<7)}, {VPU_REG_END, 0}, }; + +/* ******************************************************* */ +/* VPU module init table */ +/* ******************************************************* */ +#if 0 +static struct vpu_ctrl_s vpu_module_init_txlx[] = { + /* reg, val, bit, len */ + {DOLBY_TV_CLKGATE_CTRL, 1, 10, 2}, + {DOLBY_TV_CLKGATE_CTRL, 1, 2, 2}, + {DOLBY_TV_CLKGATE_CTRL, 1, 4, 2}, + {DOLBY_CORE2A_CLKGATE_CTRL, 1, 10, 2}, + {DOLBY_CORE2A_CLKGATE_CTRL, 1, 2, 2}, + {DOLBY_CORE2A_CLKGATE_CTRL, 1, 4, 2}, + {DOLBY_CORE3_CLKGATE_CTRL, 0, 1, 1}, + {DOLBY_CORE3_CLKGATE_CTRL, 1, 2, 2}, + {VPU_REG_END, 0, 0, 0}, +}; +#endif #endif
diff --git a/drivers/amlogic/media/common/vpu/vpu_dummy_reg.h b/drivers/amlogic/media/common/vpu/vpu_dummy_reg.h index 4e8beb2..5bddb5b 100644 --- a/drivers/amlogic/media/common/vpu/vpu_dummy_reg.h +++ b/drivers/amlogic/media/common/vpu/vpu_dummy_reg.h
@@ -8,6 +8,14 @@ #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> +#ifndef REG_BASE_CBUS +#define REG_BASE_CBUS (0xffd00000L) +#endif + +#ifndef REG_BASE_VCBUS +#define REG_BASE_VCBUS (0xff900000L) +#endif + #ifndef HHI_GP_PLL_CNTL #define HHI_GP_PLL_CNTL (0xc1100000 + (0x1010 << 2)) #endif @@ -35,18 +43,126 @@ #define HHI_VPU_MEM_PD_REG4 (0xff63c000 + (0x4c << 2)) #endif -#ifndef DOLBY_TV_CLKGATE_CTRL -#define DOLBY_TV_CLKGATE_CTRL (0x33f1) +#ifndef VENC_VDAC_TST_VAL +#define VENC_VDAC_TST_VAL (0x1b7f) #endif -#ifndef DOLBY_CORE1_CLKGATE_CTRL -#define DOLBY_CORE1_CLKGATE_CTRL (0x33f2) +#ifndef ENCP_DVI_HSO_BEGIN +#define ENCP_DVI_HSO_BEGIN (0x1c30) #endif -#ifndef DOLBY_CORE2A_CLKGATE_CTRL -#define DOLBY_CORE2A_CLKGATE_CTRL (0x3432) +#ifndef VPP_DUMMY_DATA +#define VPP_DUMMY_DATA (0x1d00) #endif -#ifndef DOLBY_CORE3_CLKGATE_CTRL -#define DOLBY_CORE3_CLKGATE_CTRL (0x36f0) +#ifndef VPU_VPU_PWM_V0 +#define VPU_VPU_PWM_V0 (0x2730) #endif +#ifndef HHI_VPU_CLK_CNTL +#define HHI_VPU_CLK_CNTL (0xc883c000 + (0x6f << 2)) +#endif + +#ifndef HHI_VAPBCLK_CNTL +#define HHI_VAPBCLK_CNTL (0xc883c000 + (0x7d << 2)) +#endif + +#ifndef HHI_VID_CLK_CNTL2 +#define HHI_VID_CLK_CNTL2 (0xff63c000 + (0x065 << 2)) +#endif + +#ifndef AO_RTI_GEN_PWR_SLEEP0 +#define AO_RTI_GEN_PWR_SLEEP0 (0xff800000 + (0x03a << 2)) +#endif + +#ifndef AO_RTI_GEN_PWR_ISO0 +#define AO_RTI_GEN_PWR_ISO0 (0xff800000 + (0x03b << 2)) +#endif + +#ifndef HHI_VPU_MEM_PD_REG0 +#define HHI_VPU_MEM_PD_REG0 (0xff63c000 + (0x041 << 2)) +#endif + +#ifndef HHI_VPU_MEM_PD_REG1 +#define HHI_VPU_MEM_PD_REG1 (0xff63c000 + (0x042 << 2)) +#endif + +#ifndef HHI_VPU_MEM_PD_REG2 +#define HHI_VPU_MEM_PD_REG2 (0xff63c000 + (0x04d << 2)) +#endif + +#ifndef HHI_VPU_MEM_PD_REG3 +#define HHI_VPU_MEM_PD_REG3 (0xff63c000 + (0x043 << 2)) +#endif + +#ifndef HHI_VPU_MEM_PD_REG4 +#define HHI_VPU_MEM_PD_REG4 (0xff63c000 + (0x044 << 2)) +#endif + +#ifndef RESET0_LEVEL +#define RESET0_LEVEL (0x0420) +#endif +#ifndef RESET1_LEVEL +#define RESET1_LEVEL (0x0421) +#endif +#ifndef RESET2_LEVEL +#define RESET2_LEVEL (0x0422) +#endif +#ifndef RESET4_LEVEL +#define RESET4_LEVEL (0x0424) +#endif +#ifndef RESET7_LEVEL +#define RESET7_LEVEL (0x0427) +#endif + +/* new mmap */ +#ifndef CLKCTRL_VPU_CLK_CTRL +#define CLKCTRL_VPU_CLK_CTRL ((0x003a << 2) + 0xfe000000) +#endif + +#ifndef CLKCTRL_VAPBCLK_CTRL +#define CLKCTRL_VAPBCLK_CTRL ((0x003f << 2) + 0xfe000000) +#endif + +#ifndef CLKCTRL_VID_CLK_CTRL2 +#define CLKCTRL_VID_CLK_CTRL2 ((0x0031 << 2) + 0xfe000000) +#endif + +#ifndef PWRCTRL_PWR_ACK0 +#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_PWR_OFF0 +#define PWRCTRL_PWR_OFF0 ((0x0004 << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_ISO_EN0 +#define PWRCTRL_ISO_EN0 ((0x0008 << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_FOCRST0 +#define PWRCTRL_FOCRST0 ((0x000c << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_MEM_PD5 +#define PWRCTRL_MEM_PD5 ((0x0015 << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_MEM_PD6 +#define PWRCTRL_MEM_PD6 ((0x0016 << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_MEM_PD7 +#define PWRCTRL_MEM_PD7 ((0x0017 << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_MEM_PD8 +#define PWRCTRL_MEM_PD8 ((0x0018 << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_MEM_PD9 +#define PWRCTRL_MEM_PD9 ((0x0019 << 2) + 0xfe00c000) +#endif + +#ifndef PWRCTRL_MEM_PD11 +#define PWRCTRL_MEM_PD11 ((0x001b << 2) + 0xfe00c000) +#endif #endif
diff --git a/drivers/amlogic/media/common/vpu/vpu_power_init.c b/drivers/amlogic/media/common/vpu/vpu_power_init.c index 80dc527..a34e6de 100644 --- a/drivers/amlogic/media/common/vpu/vpu_power_init.c +++ b/drivers/amlogic/media/common/vpu/vpu_power_init.c
@@ -38,7 +38,7 @@ i++; } } - vpu_hiu_setb(HHI_VID_CLK_CNTL2, 0, 0, 8); + vpu_hiu_setb(vpu_conf.data->vid_clk_reg, 0, 0, 8); /* dmc_arb_config */ vpu_vcbus_write(VPU_RDARB_MODE_L1C1, 0x0); //0x210000 @@ -54,13 +54,13 @@ struct vpu_ctrl_s *ctrl_table; struct vpu_reset_s *reset_table; unsigned int _reg, _val, _start, _end, _len, mask; - int i = 0, j; + int i, j; - /* power on VPU_HDMI ISO */ - ctrl_table = vpu_conf.data->hdmi_iso_pre_table; + /* power on VPU_HDMI */ + ctrl_table = vpu_conf.data->power_table; if (ctrl_table) { i = 0; - while (i < VPU_HDMI_ISO_CNT_MAX) { + while (i < VPU_PWR_CNT_MAX) { if (ctrl_table[i].reg == VPU_REG_END) break; _reg = ctrl_table[i].reg; @@ -75,6 +75,7 @@ /* power up memories */ ctrl_table = vpu_conf.data->mem_pd_table; + i = 0; while (i < VPU_MEM_PD_CNT_MAX) { if (ctrl_table[i].reg == VPU_REG_END) break; @@ -119,10 +120,10 @@ } /* Remove VPU_HDMI ISO */ - ctrl_table = vpu_conf.data->hdmi_iso_table; + ctrl_table = vpu_conf.data->iso_table; if (ctrl_table) { i = 0; - while (i < VPU_HDMI_ISO_CNT_MAX) { + while (i < VPU_ISO_CNT_MAX) { if (ctrl_table[i].reg == VPU_REG_END) break; _reg = ctrl_table[i].reg; @@ -141,16 +142,16 @@ { struct vpu_ctrl_s *ctrl_table; unsigned int _reg, _start, _end, _len, _val; - int i = 0, j; + int i, j; - /* Power down VPU_HDMI */ /* Enable Isolation */ - ctrl_table = vpu_conf.data->hdmi_iso_table; - while (i < VPU_HDMI_ISO_CNT_MAX) { + ctrl_table = vpu_conf.data->iso_table; + i = 0; + while (i < VPU_ISO_CNT_MAX) { if (ctrl_table[i].reg == VPU_REG_END) break; _reg = ctrl_table[i].reg; - _val = ctrl_table[i].val; + _val = 1; _start = ctrl_table[i].bit; _len = ctrl_table[i].len; vpu_ao_setb(_reg, _val, _start, _len); @@ -180,14 +181,14 @@ udelay(20); /* Power down VPU domain */ - ctrl_table = vpu_conf.data->hdmi_iso_pre_table; + ctrl_table = vpu_conf.data->power_table; if (ctrl_table) { i = 0; - while (i < VPU_HDMI_ISO_CNT_MAX) { + while (i < VPU_PWR_CNT_MAX) { if (ctrl_table[i].reg == VPU_REG_END) break; _reg = ctrl_table[i].reg; - _val = ctrl_table[i].val; + _val = 1; _start = ctrl_table[i].bit; _len = ctrl_table[i].len; vpu_ao_setb(_reg, _val, _start, _len); @@ -195,8 +196,33 @@ } } - vpu_hiu_setb(HHI_VAPBCLK_CNTL, 0, 8, 1); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 8, 1); + vpu_hiu_setb(vpu_conf.data->vapb_clk_reg, 0, 8, 1); + vpu_hiu_setb(vpu_conf.data->vpu_clk_reg, 0, 8, 1); VPUPR("%s\n", __func__); } + +void vpu_power_on_new(void) +{ +#ifdef CONFIG_SECURE_POWER_CONTROL + if (vpu_conf.data->pwrctrl_id < VPU_PWR_ID_INVALID) + pwr_ctrl_psci_smc(vpu_conf.data->pwrctrl_id, 1); + VPUPR("%s\n", __func__); +#else + VPUERR("%s: no CONFIG_SECURE_POWER_CONTROL\n", __func__); +#endif +} + +void vpu_power_off_new(void) +{ +#ifdef CONFIG_SECURE_POWER_CONTROL + VPUPR("%s\n", __func__); + if (vpu_conf.data->pwrctrl_id < VPU_PWR_ID_INVALID) + pwr_ctrl_psci_smc(vpu_conf.data->pwrctrl_id, 0); +#else + VPUERR("%s: no CONFIG_SECURE_POWER_CONTROL\n", __func__); +#endif + + vpu_hiu_setb(vpu_conf.data->vapb_clk_reg, 0, 8, 1); + vpu_hiu_setb(vpu_conf.data->vpu_clk_reg, 0, 8, 1); +}
diff --git a/drivers/amlogic/media/common/vpu/vpu_reg.h b/drivers/amlogic/media/common/vpu/vpu_reg.h index 033127d..0baf8ca 100644 --- a/drivers/amlogic/media/common/vpu/vpu_reg.h +++ b/drivers/amlogic/media/common/vpu/vpu_reg.h
@@ -23,9 +23,49 @@ #define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg)) #define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg)) +#define REG_VPU_ADDR(reg) (reg + 0L) + /* ******************************** * register access api * ********************************* */ +static inline unsigned int vpu_reg_read(unsigned int _reg) +{ + unsigned int val = 0; + + val = *(volatile unsigned int *)(REG_VPU_ADDR(_reg)); + + return val; +}; + +static inline void vpu_reg_write(unsigned int _reg, unsigned int _value) +{ + *(volatile unsigned int *)REG_VPU_ADDR(_reg) = (_value); +}; + +static inline void vpu_reg_setb(unsigned int _reg, unsigned int _value, + unsigned int _start, unsigned int _len) +{ + vpu_reg_write(_reg, ((vpu_reg_read(_reg) & + ~(((1L << (_len))-1) << (_start))) | + (((_value)&((1L<<(_len))-1)) << (_start)))); +} + +static inline unsigned int vpu_reg_getb(unsigned int _reg, + unsigned int _start, unsigned int _len) +{ + return (vpu_reg_read(_reg) >> (_start)) & ((1L << (_len)) - 1); +} + +static inline void vpu_reg_set_mask(unsigned int _reg, unsigned int _mask) +{ + vpu_reg_write(_reg, (vpu_reg_read(_reg) | (_mask))); +} + +static inline void vpu_reg_clr_mask(unsigned int _reg, unsigned int _mask) +{ + vpu_reg_write(_reg, (vpu_reg_read(_reg) & (~(_mask)))); +} + static inline unsigned int vpu_hiu_read(unsigned int _reg) { unsigned int val = 0; @@ -67,13 +107,20 @@ static inline unsigned int vpu_vcbus_read(unsigned int _reg) { unsigned int val = 0; - val = *(volatile unsigned int *)(REG_ADDR_VCBUS(_reg)); + + if (_reg > 0x10000) + val = vpu_reg_read(_reg); + else + val = *(volatile unsigned int *)(REG_ADDR_VCBUS(_reg)); return val; }; static inline void vpu_vcbus_write(unsigned int _reg, unsigned int _value) { - *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value); + if (_reg > 0x10000) + vpu_reg_write(_reg, _value); + else + *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value); }; static inline void vpu_vcbus_setb(unsigned int _reg, unsigned int _value, @@ -87,13 +134,20 @@ static inline unsigned int vpu_cbus_read(unsigned int _reg) { unsigned int val = 0; - val = *(volatile unsigned int *)(REG_ADDR_CBUS(_reg)); + + if (_reg > 0x10000) + val = vpu_reg_read(_reg); + else + val = *(volatile unsigned int *)(REG_ADDR_CBUS(_reg)); return val; }; static inline void vpu_cbus_write(unsigned int _reg, unsigned int _value) { - *(volatile unsigned int *)REG_ADDR_CBUS(_reg) = (_value); + if (_reg > 0x10000) + vpu_reg_write(_reg, _value); + else + *(volatile unsigned int *)REG_ADDR_CBUS(_reg) = (_value); }; static inline void vpu_cbus_setb(unsigned int _reg, unsigned int _value,
diff --git a/drivers/amlogic/media/osd/Kconfig b/drivers/amlogic/media/osd/Kconfig index e69de29..2ff2ccf 100644 --- a/drivers/amlogic/media/osd/Kconfig +++ b/drivers/amlogic/media/osd/Kconfig
@@ -0,0 +1,4 @@ +config AML_DOLBY + bool "AML DOLBY driver support" + help + Enable support for the Amlogic DOLBY driver.
diff --git a/drivers/amlogic/media/osd/hdr2.h b/drivers/amlogic/media/osd/hdr2.h new file mode 100644 index 0000000..26daaf5 --- /dev/null +++ b/drivers/amlogic/media/osd/hdr2.h
@@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDR2_H__ +#define __HDR2_H__ + +enum hdr_module_sel { + VD1_HDR = 0x1, + VD2_HDR = 0x2, + OSD1_HDR = 0x4, + VDIN0_HDR = 0x8, + VDIN1_HDR = 0x10, + DI_HDR = 0x20, + HDR_MAX +}; + +enum hdr_process_sel { + HDR_BYPASS = 0x1, + HDR_SDR = 0x2, + SDR_HDR = 0x4, + HLG_BYPASS = 0x8, + HLG_SDR = 0x10, + HLG_HDR = 0x20, + SDR_HLG = 0X40, + HDRPLUS_SDR = 0x80, + HDR_OFF = 0x100, + RGB_BYPASS = 0x200, + HDR_p_MAX +}; + +extern void hdr_func(enum hdr_module_sel module_sel, + enum hdr_process_sel hdr_process_select); + +#endif
diff --git a/drivers/amlogic/media/osd/osd.h b/drivers/amlogic/media/osd/osd.h index 733f70b..54943c6 100644 --- a/drivers/amlogic/media/osd/osd.h +++ b/drivers/amlogic/media/osd/osd.h
@@ -42,7 +42,7 @@ #define KEYCOLOR_FLAG_ONHOLD 2 #define KEYCOLOR_FLAG_CURRENT 4 -#define HW_OSD_COUNT 2 +#define HW_OSD_COUNT 3 /* OSD block definition */ #define HW_OSD_BLOCK_COUNT 4 #define HW_OSD_BLOCK_REG_COUNT (HW_OSD_BLOCK_COUNT*2) @@ -72,11 +72,6 @@ #define OSD_MAX_BUF_NUM 3 /* fence relative */ -enum osd_index_e { - OSD1 = 0, - OSD2 -}; - enum osd_enable_e { DISABLE = 0, ENABLE @@ -256,6 +251,7 @@ u32 clone[HW_OSD_COUNT]; u32 bot_type; u32 osd_ver; + u32 shift_line; }; #endif /* _OSD_H_ */
diff --git a/drivers/amlogic/media/osd/osd_canvas.h b/drivers/amlogic/media/osd/osd_canvas.h index 63c058c..78371a1 100644 --- a/drivers/amlogic/media/osd/osd_canvas.h +++ b/drivers/amlogic/media/osd/osd_canvas.h
@@ -9,7 +9,7 @@ #define OSD1_CANVAS_INDEX 0x40 #define OSD2_CANVAS_INDEX 0x43 #define OSD3_CANVAS_INDEX 0x41 -#define OSD4_CANVAS_INDEX 0x42 +#define OSD4_CANVAS_INDEX 0x47 #define ALLOC_CANVAS_INDEX 0x44 #endif
diff --git a/drivers/amlogic/media/osd/osd_debug.c b/drivers/amlogic/media/osd/osd_debug.c index a6a70f0..ae74e24 100644 --- a/drivers/amlogic/media/osd/osd_debug.c +++ b/drivers/amlogic/media/osd/osd_debug.c
@@ -187,6 +187,26 @@ reg = VIU_OSD2_BLK0_CFG_W4; osd_logi("reg[0x%x]: 0x%08x\n\n", reg, osd_reg_read(reg)); } + +#ifdef CONFIG_AML_MESON_G12A + /* for viu2_osd */ + if (!strcmp(env_get("display_layer"), "viu2_osd0")) { + reg = VIU2_OSD1_FIFO_CTRL_STAT; + osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VIU2_OSD1_CTRL_STAT; + osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VIU2_OSD1_BLK0_CFG_W0; + osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VIU2_OSD1_BLK0_CFG_W1; + osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VIU2_OSD1_BLK0_CFG_W2; + osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VIU2_OSD1_BLK0_CFG_W3; + osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VIU2_OSD1_BLK0_CFG_W4; + osd_logi("reg[0x%x]: 0x%08x\n\n", reg, osd_reg_read(reg)); + } +#endif } static void osd_test_colorbar(void)
diff --git a/drivers/amlogic/media/osd/osd_fb.c b/drivers/amlogic/media/osd/osd_fb.c index bec6ae2..0de7508 100644 --- a/drivers/amlogic/media/osd/osd_fb.c +++ b/drivers/amlogic/media/osd/osd_fb.c
@@ -166,7 +166,9 @@ }pic_info_t; static pic_info_t g_pic_info; static int img_video_init = 0; -static int fb_index = -1; +#if defined(CONFIG_AML_MINUI) +extern int in_fastboot_mode; +#endif static void osd_layer_init(GraphicDevice *gdev, int layer) @@ -186,20 +188,26 @@ const struct color_bit_define_s *color = &default_color_format_array[gdev->gdfIndex]; -#ifdef OSD_SCALE_ENABLE - xres = gdev->fb_width; - yres = gdev->fb_height; - xres_virtual = gdev->fb_width; - yres_virtual = gdev->fb_height * 2; - disp_end_x = gdev->fb_width - 1; - disp_end_y = gdev->fb_height - 1; -#else - xres = gdev->winSizeX; - yres = gdev->winSizeY; - xres_virtual = gdev->winSizeX; - yres_virtual = gdev->winSizeY * 2; - disp_end_x = gdev->winSizeX - 1; - disp_end_y = gdev->winSizeY - 1; + if (index >= VIU2_OSD1) { + xres = gdev->winSizeX; + yres = gdev->winSizeY; + xres_virtual = gdev->winSizeX; + yres_virtual = gdev->winSizeY * 2; + disp_end_x = gdev->winSizeX - 1; + disp_end_y = gdev->winSizeY - 1; + } else { + xres = gdev->fb_width; + yres = gdev->fb_height; + xres_virtual = gdev->fb_width; + yres_virtual = gdev->fb_height * 2; + disp_end_x = gdev->fb_width - 1; + disp_end_y = gdev->fb_height - 1; + } + +#ifdef AML_OSD_HIGH_VERSION + if (index >= VIU2_OSD1) + osd_init_hw_viu2(); + else #endif osd_init_hw(); osd_setup_hw(index, @@ -264,35 +272,73 @@ unsigned long get_fb_addr(void) { + char *dt_addr = NULL; unsigned long fb_addr = 0; static int initrd_set = 0; char str_fb_addr[32]; -#ifdef CONFIG_OF_LIBFDT - const void *dt_addr = NULL; char fdt_node[32]; + int dt_loaded = 0; +#ifdef CONFIG_OF_LIBFDT int parent_offset = 0; char *propdata = NULL; #endif fb_addr = env_strtoul("fb_addr", 16); - #ifdef CONFIG_OF_LIBFDT - dt_addr = gd->fdt_blob; - if ((dt_addr == NULL) || (fdt_check_header(dt_addr) < 0)) { - osd_logi("check dts: %s, load default fb_addr parameters\n", - fdt_strerror(fdt_check_header(dt_addr))); - } else { - strcpy(fdt_node, "/meson-fb"); - osd_logi("load fb addr from dts:%s\n", fdt_node); - parent_offset = get_dts_node(dt_addr, fdt_node); - if (parent_offset < 0) { - strcpy(fdt_node, "/drm-vpu"); +#if defined(CONFIG_AML_MINUI) + if (in_fastboot_mode == 1) { + osd_logi("in fastboot mode, load default fb_addr parameters \n"); + } else +#endif + { + dt_addr = env_get_ulong("dtb_mem_addr", 16, 0x1000000); + if (dt_addr == NULL) { + osd_logi("dt_addr is null, load default parameters\n"); + } + if (fdt_check_header(dt_addr) < 0) { + dt_addr = dt_addr = gd->fdt_blob; + if (fdt_check_header(dt_addr) < 0) { + dt_loaded = -1; + osd_logi("check dts: %s, load default fb_addr parameters\n", + fdt_strerror(fdt_check_header(dt_addr))); + } + } + if (dt_loaded < 0) { + osd_logi("check dts: %s, load default fb_addr parameters\n", + fdt_strerror(fdt_check_header(dt_addr))); + } else { + strcpy(fdt_node, "/fb"); osd_logi("load fb addr from dts:%s\n", fdt_node); parent_offset = get_dts_node(dt_addr, fdt_node); if (parent_offset < 0) { - osd_logi("not find node: %s\n",fdt_strerror(parent_offset)); - osd_logi("use default fb_addr parameters\n"); + if (parent_offset < 0) { + strcpy(fdt_node, "/drm-vpu"); + osd_logi("load fb addr from dts:%s\n", fdt_node); + parent_offset = get_dts_node(dt_addr, fdt_node); + if (parent_offset < 0) { + osd_logi("not find node: %s\n",fdt_strerror(parent_offset)); + osd_logi("use default fb_addr parameters\n"); + } else { + /* check fb_addr */ + propdata = (char *)fdt_getprop(dt_addr, parent_offset, "logo_addr", NULL); + if (propdata == NULL) { + osd_logi("failed to get fb addr for logo\n"); + osd_logi("use default fb_addr parameters\n"); + } else { + fb_addr = simple_strtoul(propdata, NULL, 16); + } + } + } else { + /* check fb_addr */ + propdata = (char *)fdt_getprop(dt_addr, parent_offset, "logo_addr", NULL); + if (propdata == NULL) { + osd_logi("failed to get fb addr for logo\n"); + osd_logi("use default fb_addr parameters\n"); + } else { + fb_addr = simple_strtoul(propdata, NULL, 16); + } + } } else { /* check fb_addr */ propdata = (char *)fdt_getprop(dt_addr, parent_offset, "logo_addr", NULL); @@ -303,19 +349,10 @@ fb_addr = simple_strtoul(propdata, NULL, 16); } } - } else { - /* check fb_addr */ - propdata = (char *)fdt_getprop(dt_addr, parent_offset, "logo_addr", NULL); - if (propdata == NULL) { - osd_logi("failed to get fb addr for logo\n"); - osd_logi("use default fb_addr parameters\n"); - } else { - fb_addr = simple_strtoul(propdata, NULL, 16); - } } } #endif - if ((!initrd_set) && (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_AXG)) { + if ((!initrd_set) && (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_AXG)) { sprintf(str_fb_addr,"%lx",fb_addr); env_set("initrd_high", str_fb_addr); initrd_set = 1; @@ -328,7 +365,7 @@ static void get_osd_version(void) { - u32 family_id = get_cpu_id().family_id; + u32 family_id = osd_get_chip_type(); if (family_id == MESON_CPU_MAJOR_ID_AXG) osd_hw.osd_ver = OSD_SIMPLE; @@ -338,21 +375,34 @@ osd_hw.osd_ver = OSD_HIGH_ONE; } -static int get_osd_layer(void) +int get_osd_layer(void) { char *layer_str; int osd_index = -1; - if (fb_index < 0) { - layer_str = env_get("display_layer"); - if (strcmp(layer_str, "osd0") == 0) - osd_index = OSD1; - else if (strcmp(layer_str, "osd1") == 0) - osd_index = OSD2; - fb_index = osd_index; - } - return fb_index; + layer_str = env_get("display_layer"); + if (strcmp(layer_str, "osd0") == 0) + osd_index = OSD1; + else if (strcmp(layer_str, "osd1") == 0) + osd_index = OSD2; + else if (strcmp(layer_str, "viu2_osd0") == 0) + osd_index = VIU2_OSD1; + else + osd_loge("%s, error found\n", __func__); + + return osd_index; } + +static bool is_osd_supported(int chip_id) +{ + if ((chip_id == MESON_CPU_MAJOR_ID_A1) || + (chip_id == MESON_CPU_MAJOR_ID_C1) || + (chip_id == MESON_CPU_MAJOR_ID_C2)) + return false; + else + return true; +} + static void *osd_hw_init(void) { int osd_index = -1; @@ -382,8 +432,13 @@ return NULL; } osd_layer_init(&fb_gdev, OSD2); - } - else { + } else if (osd_index == VIU2_OSD1) { + if (osd_hw.osd_ver == OSD_SIMPLE) { + osd_loge("AXG not support viu2 osd0\n"); + return NULL; + } + osd_layer_init(&fb_gdev, VIU2_OSD1); + } else { osd_loge("display_layer(%d) invalid\n", osd_index); return NULL; } @@ -399,10 +454,14 @@ u32 fg = 0; u32 bg = 0; u32 fb_width = 0; - u32 fb_height = 0;; + u32 fb_height = 0; + if (!is_osd_supported(osd_get_chip_type())) + return NULL; get_osd_version(); +#ifdef CONFIG_AML_VOUT vout_init(); +#endif fb_addr = get_fb_addr(); switch (display_mode) { case MIDDLE_MODE: @@ -554,18 +613,14 @@ uchar *fb; bmp_image_t *bmp = (bmp_image_t *)bmp_image; uchar *bmap; - ushort padded_line; unsigned long width, height; -#ifdef OSD_SCALE_ENABLE - unsigned long pheight = fb_gdev.fb_height; - unsigned long pwidth = fb_gdev.fb_width; -#else - unsigned long pheight = info->width; - unsigned long pwidth = info->height; -#endif + unsigned long pheight; + unsigned long pwidth; unsigned colors, bpix, bmp_bpix; - int lcd_line_length = (pwidth * NBITS(info->vl_bpix)) / 8; + uint lcd_line_length; int osd_index = -1; + int bmp_line_bytes; + int bmp_line_align_offset; osd_index = get_osd_layer(); if (osd_index < 0) { @@ -573,6 +628,16 @@ return (-1); } + /* viu1 has scaler, viu2 has no scaler */ + if (osd_index >= VIU2_OSD1) { + pwidth = info->width; + pheight = info->height; + } else { + pheight = fb_gdev.fb_height; + pwidth = fb_gdev.fb_width; + } + + lcd_line_length = CANVAS_ALIGNED((pwidth * NBITS(info->vl_bpix)) / 8); if (fb_gdev.mode != FULL_SCREEN_MODE) if (parse_bmp_info(bmp_image)) return -1; @@ -637,21 +702,24 @@ * their own ways, so make the converting to be MCC200 * specific. */ - padded_line = (width & 0x3) ? ((width & ~0x3) + 4) : (width); + bmp_line_bytes = width * bmp_bpix / 8; + bmp_line_bytes = (bmp_line_bytes & 0x3) ? + ((bmp_line_bytes & ~0x3) + 4) : (bmp_line_bytes); + + bmp_line_align_offset = bmp_line_bytes - width * bmp_bpix / 8; if ((x + width) > pwidth) width = pwidth - x; if ((y + height) > pheight) height = pheight - y; - osd_enable_hw(osd_index, 1); - bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset); - fb = (uchar *)(info->vd_base + + fb = (uchar *)(osd_hw.fb_gem[osd_index].addr + (y + height - 1) * lcd_line_length + x * fb_gdev.gdfBytesPP); - osd_logd("fb=0x%p; bmap=0x%p, width=%ld, height= %ld, lcd_line_length=%d, padded_line=%d, fb_gdev.fb_width=%d, fb_gdev.fb_height=%d \n", - fb, bmap, width, height, lcd_line_length, padded_line,fb_gdev.fb_width,fb_gdev.fb_height); + osd_logd("fb=0x%p; bmap=0x%p, width=%ld, height= %ld, lcd_line_length=%d, bmp_line_bytes=%d, fb_gdev.fb_width=%d, fb_gdev.fb_height=%d \n", + fb, bmap, width, height, lcd_line_length, bmp_line_bytes, + fb_gdev.fb_width, fb_gdev.fb_height); if (bmp_bpix == 8) { /* decode of RLE8 */ @@ -688,7 +756,7 @@ } */ } - buffer_rgb += (padded_line - width); + buffer_rgb += bmp_line_align_offset; fb -= (byte_width * 4 + lcd_line_length); } buffer_rgb -= width*height*4; @@ -701,7 +769,7 @@ *(fb++) = *(bmap++); *(fb++) = *(bmap++); } - bmap += (padded_line - width) * 2; + bmap += bmp_line_align_offset; fb -= (width * 2 + lcd_line_length); } break; @@ -715,7 +783,7 @@ *(fb++) = *(bmap++); *(fb++) = 0xff; } - bmap += (padded_line - width); + bmap += bmp_line_align_offset; fb -= (width * 4 + lcd_line_length); } } else { @@ -726,7 +794,7 @@ *(fb++) = *(bmap++); *(fb++) = *(bmap++); } - bmap += (padded_line - width); + bmap += bmp_line_align_offset; fb -= (width * 3 + lcd_line_length); } } @@ -740,7 +808,7 @@ *(fb++) = *(bmap++); *(fb++) = *(bmap++); } - bmap += (padded_line - width); + bmap += bmp_line_align_offset; fb -= (width * 4 + lcd_line_length); } break; @@ -751,8 +819,8 @@ buffer_rgb = NULL; ptr_rgb = NULL; - flush_cache((unsigned long)info->vd_base, - pheight * pwidth * info->vl_bpix / 8); + flush_cache((unsigned long)osd_hw.fb_gem[osd_index].addr, + pheight * CANVAS_ALIGNED(pwidth * info->vl_bpix / 8)); return (0); } @@ -935,16 +1003,20 @@ osd_logd2("video_scale_bitmap src w=%d, h=%d, dst w=%d, dst h=%d\n", fb_gdev.fb_width, fb_gdev.fb_height, fb_gdev.winSizeX, fb_gdev.winSizeY); - layer_str = env_get("display_layer"); vout_get_current_axis(axis); + layer_str = env_get("display_layer"); if (strcmp(layer_str, "osd0") == 0) - osd_index = 0; + osd_index = OSD1; else if (strcmp(layer_str, "osd1") == 0) - osd_index = 1; - else { + osd_index = OSD2; + else if (strcmp(layer_str, "viu2_osd0") == 0) { + osd_index = VIU2_OSD1; + goto no_scale; + } else { osd_logd2("video_scale_bitmap: invalid display_layer\n"); return (-1); } + #ifdef OSD_SUPERSCALE_ENABLE if ((fb_gdev.fb_width * 2 != fb_gdev.winSizeX) || (fb_gdev.fb_height * 2 != fb_gdev.winSizeY)) { @@ -960,12 +1032,14 @@ osd_set_window_axis_hw(osd_index, axis[0], axis[1], axis[0] + axis[2] - 1, axis[1] + axis[3] - 1); osd_set_free_scale_enable_hw(osd_index, 0x10001); + +no_scale: #ifdef AML_OSD_HIGH_VERSION disp_data.x_start = axis[0]; disp_data.y_start = axis[1]; disp_data.x_end = axis[0] + axis[2] - 1; disp_data.y_end = axis[1] + axis[3] - 1; - if (osd_hw.osd_ver == OSD_HIGH_ONE) + if (osd_hw.osd_ver == OSD_HIGH_ONE && osd_index < VIU2_OSD1) osd_update_blend(&disp_data); #endif osd_enable_hw(osd_index, 1); @@ -1130,11 +1204,12 @@ u32 fg = 0; u32 bg = 0; u32 fb_width = 0; - u32 fb_height = 0;; + u32 fb_height = 0; get_osd_version(); - +#ifdef CONFIG_AML_VOUT vout_init(); +#endif fb_addr = get_fb_addr(); #ifdef OSD_SCALE_ENABLE fb_width = env_strtoul("fb_width", 10); @@ -1188,10 +1263,6 @@ return 0; } - - - - static int video_display_osd(u32 osd_index) { struct vinfo_s *info = NULL; @@ -1243,7 +1314,7 @@ void hist_set_golden_data(void) { u32 i = 0; - u32 family_id = get_cpu_id().family_id; + u32 family_id = osd_get_chip_type(); char *str = NULL; char *hist_env_key[12] = {"hist_max_min_osd0","hist_spl_val_osd0","hist_spl_pix_cnt_osd0","hist_cheoma_sum_osd0", "hist_max_min_osd1","hist_spl_val_osd1","hist_spl_pix_cnt_osd1","hist_cheoma_sum_osd1", @@ -1283,7 +1354,19 @@ hist_cheoma_sum[OSD1][MESON_CPU_MAJOR_ID_G12A] = hist_cheoma_sum[OSD2][MESON_CPU_MAJOR_ID_G12A] = 0xd4ffdc; - + //SC2 + hist_max_min[OSD1][MESON_CPU_MAJOR_ID_SC2] + = hist_max_min[OSD2][MESON_CPU_MAJOR_ID_SC2] + = 0xf700; + hist_spl_val[OSD1][MESON_CPU_MAJOR_ID_SC2] + = hist_spl_val[OSD2][MESON_CPU_MAJOR_ID_SC2] + = 0x1e873c00; + hist_spl_pix_cnt[OSD1][MESON_CPU_MAJOR_ID_SC2] + = hist_spl_pix_cnt[OSD2][MESON_CPU_MAJOR_ID_SC2] + = 0x1fa409; + hist_cheoma_sum[OSD1][MESON_CPU_MAJOR_ID_SC2] + = hist_cheoma_sum[OSD2][MESON_CPU_MAJOR_ID_SC2] + = 0xfd20480; for (i = 0; i < 12; i++) { str = env_get(hist_env_key[i]); if (str) { @@ -1309,8 +1392,9 @@ { u32 i = osd_index, osd_max = 1; u32 hist_result[4]; - u32 family_id = get_cpu_id().family_id; + u32 family_id = osd_get_chip_type(); + get_osd_version(); if (osd_hw.osd_ver == OSD_SIMPLE) { osd_max = 0; } else if (osd_hw.osd_ver == OSD_HIGH_ONE) {
diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c index 6dd7e71..ee54e65 100644 --- a/drivers/amlogic/media/osd/osd_hw.c +++ b/drivers/amlogic/media/osd/osd_hw.c
@@ -9,6 +9,7 @@ #include <asm/arch/io.h> #include <amlogic/cpu_id.h> #include <asm/arch/cpu.h> +#include <asm/arch/timer.h> /* Local Headers */ #include <amlogic/media/vout/aml_vmode.h> @@ -18,6 +19,8 @@ #ifdef CONFIG_AML_VOUT #include <amlogic/media/vout/aml_vout.h> #endif +#include <amlogic/fb.h> +#include <video_fb.h> /* Local Headers */ #include "osd_canvas.h" @@ -27,6 +30,7 @@ #include "osd_hw_def.h" #include "vpp.h" +#include <amlogic/media/dv/dolby_vision.h> static bool vsync_hit; static bool osd_vf_need_update; @@ -51,6 +55,7 @@ static unsigned int osd_h_filter_mode = 1; static unsigned int osd_v_filter_mode = 1; +extern GraphicDevice fb_gdev; static unsigned int osd_filter_coefs_bicubic_sharp[] = { 0x01fa008c, 0x01fa0100, 0xff7f0200, 0xfe7f0300, @@ -171,9 +176,22 @@ #define OSD_TYPE_TOP_FIELD 0 #define OSD_TYPE_BOT_FIELD 1 +int osd_get_chip_type(void) +{ + unsigned int cpu_type; + + cpu_type = get_cpu_id().family_id; + return cpu_type; +} + static void osd_vpu_power_on(void) { } +#ifdef AML_OSD_HIGH_VERSION +static void osd_vpu_power_on_viu2(void) +{ +} +#endif static void osd_super_scale_mem_power_on(void) { @@ -222,25 +240,151 @@ #endif -static inline void osd_update_3d_mode(int enable_osd1, int enable_osd2) +static inline void osd_update_3d_mode(int enable_osd1, int enable_osd2, + int enable_viu2_osd1) { if (enable_osd1) osd1_update_disp_3d_mode(); if (enable_osd2) osd2_update_disp_3d_mode(); + if (enable_viu2_osd1) + viu2_osd1_update_disp_3d_mode(); +} + +#if 1 +static void get_encp_line(int *enc_line, int *active_line_begin) +{ + unsigned int reg = 0; + unsigned int viu_sel; + int osd_index; + + osd_index = get_osd_layer(); + if (osd_index < VIU2_OSD1) + viu_sel = osd_reg_read(VPU_VIU_VENC_MUX_CTRL) & 0x3; + else + viu_sel = (osd_reg_read(VPU_VIU_VENC_MUX_CTRL) >> 2) & 0x3; + + switch (viu_sel) { + case 0: + reg = osd_reg_read(ENCL_INFO_READ); + *active_line_begin = + osd_reg_read(ENCL_VIDEO_VAVON_BLINE); + + break; + case 1: + reg = osd_reg_read(ENCI_INFO_READ); + *active_line_begin = + osd_reg_read(ENCI_VFIFO2VD_LINE_TOP_START); + break; + case 2: + reg = osd_reg_read(ENCP_INFO_READ); + *active_line_begin = + osd_reg_read(ENCP_VIDEO_VAVON_BLINE); + break; + case 3: + reg = osd_reg_read(ENCT_INFO_READ); + *active_line_begin = + osd_reg_read(ENCT_VIDEO_VAVON_BLINE); + break; + } + *enc_line = (reg >> 16) & 0x1fff; + *enc_line -= (*active_line_begin); } static inline void wait_vsync_wakeup(void) { + int i = 0; + int enc_line = 0; + int active_line_begin; + int vsync_line = 0; + struct vinfo_s *info = NULL; + int line_after = 0; + +#ifdef CONFIG_AML_VOUT + info = vout_get_current_vinfo(); + vsync_line = info->field_height; +#endif + + get_encp_line(&enc_line, &active_line_begin); + + /* if current line is always zero */ + if (enc_line == (0 - active_line_begin)) { + _udelay(50); + get_encp_line(&line_after, &active_line_begin); + if (enc_line == (0 - active_line_begin)) + goto vsync_hit_flag; + } + + while (enc_line < vsync_line) { + if (i > 100000) { + osd_logi("wait_vsync_wakeup exit\n"); + break; + } + i++; + get_encp_line(&enc_line, &active_line_begin); + } + +vsync_hit_flag: vsync_hit = true; } +#else + +static int get_encp_line(int *enc_line) +{ + int vsync_get = 0; + unsigned int reg = 0; + int field_status = 0; + static int pre_field_status = 0; + + switch (osd_reg_read(VPU_VIU_VENC_MUX_CTRL) & 0x3) { + case 0: + reg = osd_reg_read(ENCL_INFO_READ); + break; + case 1: + reg = osd_reg_read(ENCI_INFO_READ); + break; + case 2: + reg = osd_reg_read(ENCP_INFO_READ); + break; + case 3: + reg = osd_reg_read(ENCT_INFO_READ); + break; + } + *enc_line = (reg >> 16) & 0x1fff; + field_status = (reg >> 29) & 0x7; + if (field_status != pre_field_status) + vsync_get = 1; + pre_field_status = field_status; + return vsync_get; +} + +static inline void wait_vsync_wakeup(void) +{ + int i = 0; + int line = 0; + int vsync_get = 0; + + vsync_get = get_encp_line(&line); + if ((line > 0) || vsync_get) { + while (!vsync_get) { + if (i>100000) { + osd_logi("wait_vsync_wakeup exit, i=%d\n", i); + break; + } + i++; + vsync_get = get_encp_line(&line); + } + } + vsync_hit = true; +} +#endif static inline void walk_through_update_list(void) { u32 i, j; for (i = 0; i < HW_OSD_COUNT; i++) { j = 0; - while (osd_hw.updated[i] && j < 32) { + while (osd_hw.updated[i] && j < HW_REG_INDEX_MAX) { if (osd_hw.updated[i] & (1 << j)) { osd_hw.reg[i][j].update_func(); remove_from_update_list(i, j); @@ -321,17 +465,18 @@ osd_reg_write(VIU_OSD2_BLK0_CFG_W0, fb1_cfg_w0); } /* go through update list */ - walk_through_update_list(); - osd_update_3d_mode(osd_hw.mode_3d[OSD1].enable, - osd_hw.mode_3d[OSD2].enable); - if (!vsync_hit) wait_vsync_wakeup(); + + walk_through_update_list(); + osd_update_3d_mode(osd_hw.mode_3d[OSD1].enable, + osd_hw.mode_3d[OSD2].enable, + osd_hw.mode_3d[VIU2_OSD1].enable); } void osd_wait_vsync_hw(void) { - mdelay(16); + //mdelay(16); vsync_isr(); vsync_hit = false; } @@ -512,7 +657,7 @@ struct pandata_s disp_data; struct pandata_s pan_data; - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) { + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) { if (index == OSD2) return; } @@ -602,10 +747,10 @@ void osd_setting_default_hwc(u32 index, struct pandata_s *disp_data) { u32 width, height; - u32 blend2_premult_en = 0, din_premult_en = 0; - u32 blend_din_en = 0x1; + u32 blend2_premult_en = 3, din_premult_en = 0; + u32 blend_din_en = 0x5; /* blend_din0 input to blend0 */ - u32 din0_byp_blend = 1; + u32 din0_byp_blend = 0; /* blend1_dout to blend2 */ u32 din2_osd_sel = 0; /* blend1_din3 input to blend1 */ @@ -614,11 +759,14 @@ u32 postbld_src3_sel = 3, postbld_src4_sel = 0; u32 postbld_osd1_premult = 0, postbld_osd2_premult = 0; u32 reg_offset = 2; + u32 shift_line = osd_hw.shift_line; + if (osd_get_chip_type() > MESON_CPU_MAJOR_ID_TM2) + reg_offset = 8; if (index == OSD1) - din_reoder_sel = 1; + din_reoder_sel = 0x4441; else if (index == OSD2) - din_reoder_sel = 2; + din_reoder_sel = 0x4442; /* depend on din0_premult_en */ postbld_osd1_premult = 0; /* depend on din_premult_en bit 4 */ @@ -661,7 +809,7 @@ 0x0); width = disp_data->x_end - disp_data->x_start + 1; - height = disp_data->y_end - disp_data->y_start + 1; + height = disp_data->y_end - disp_data->y_start + 1 + shift_line; /* it is setting for osdx */ osd_reg_write( VIU_OSD_BLEND_DIN0_SCOPE_H + reg_offset * index, @@ -669,19 +817,38 @@ disp_data->x_start); osd_reg_write( VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * index, - disp_data->y_end << 16 | - disp_data->y_start); + (disp_data->y_end + shift_line) << 16 | + (disp_data->y_start + shift_line)); + if (index == OSD1) { + int i; + + for (i = 1; i < 4; i++) + osd_reg_write( + VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * i, + 0xffffffff); + } else if (index == OSD2) { + int i = 0; + + osd_reg_write( + VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * i, + 0xffffffff); + for (i = 2; i < 4; i++) + osd_reg_write( + VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * i, + 0xffffffff); + } + osd_reg_write(VIU_OSD_BLEND_BLEND0_SIZE, height << 16 | width); osd_reg_write(VIU_OSD_BLEND_BLEND1_SIZE, height << 16 | width); - osd_reg_set_bits(DOLBY_PATH_CTRL, - 0x3, 2, 2); - osd_reg_write(VPP_OSD1_IN_SIZE, height << 16 | width); + if (!is_dolby_enable()) + osd_reg_set_bits(DOLBY_PATH_CTRL, + 0x3, 2, 2); /* setting blend scope */ osd_reg_write(VPP_OSD1_BLD_H_SCOPE, @@ -694,7 +861,28 @@ void osd_update_blend(struct pandata_s *disp_data) { u32 width, height; + int vmode = -1; +#ifdef CONFIG_AML_VOUT + vmode = vout_get_current_vmode(); +#endif + switch (vmode) { + /* case VMODE_LCD: */ + case VMODE_480I: + case VMODE_480CVBS: + case VMODE_576I: + case VMODE_576CVBS: + case VMODE_1080I: + case VMODE_1080I_50HZ: +#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION + case VMODE_1080I_59HZ: +#endif + disp_data->y_start /=2; + disp_data->y_end /= 2; + break; + default: + break; + } width = disp_data->x_end - disp_data->x_start + 1; height = disp_data->y_end - disp_data->y_start + 1; @@ -730,7 +918,7 @@ u32 w = (color->bpp * xres_virtual + 7) >> 3; if (osd_hw.osd_ver == OSD_SIMPLE) { - if (index == OSD2) { + if (index >= OSD2) { osd_loge("AXG not support osd2\n"); return ; } @@ -773,14 +961,7 @@ osd_hw.fb_gem[index].addr = fbmem; osd_hw.fb_gem[index].width = w; osd_hw.fb_gem[index].height = yres_virtual; - osd_logd("osd[%d] canvas.idx =0x%x\n", - index, osd_hw.fb_gem[index].canvas_idx); - osd_logd("osd[%d] canvas.addr=0x%x\n", - index, osd_hw.fb_gem[index].addr); - osd_logd("osd[%d] canvas.width=%d\n", - index, osd_hw.fb_gem[index].width); - osd_logd("osd[%d] canvas.height=%d\n", - index, osd_hw.fb_gem[index].height); + if (osd_hw.osd_ver == OSD_SIMPLE) { u32 line_stride, fmt_mode, bpp; @@ -798,13 +979,31 @@ } #ifdef CONFIG_AML_CANVAS else { - canvas_config(osd_hw.fb_gem[index].canvas_idx, - osd_hw.fb_gem[index].addr, - osd_hw.fb_gem[index].width, - osd_hw.fb_gem[index].height, - CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + if (index < VIU2_OSD1) { + canvas_config(osd_hw.fb_gem[index].canvas_idx, + osd_hw.fb_gem[index].addr, + CANVAS_ALIGNED(osd_hw.fb_gem[index].width), + osd_hw.fb_gem[index].height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + } else { + /* for dual logo display */ + osd_hw.fb_gem[index].addr += fb_gdev.fb_height * CANVAS_ALIGNED(fb_gdev.fb_width * color->bpp >> 3); + canvas_config(osd_hw.fb_gem[index].canvas_idx, + osd_hw.fb_gem[index].addr, + CANVAS_ALIGNED(osd_hw.fb_gem[index].width), + osd_hw.fb_gem[index].height, + CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR); + } } #endif + osd_logd("osd[%d] canvas.idx =0x%x\n", + index, osd_hw.fb_gem[index].canvas_idx); + osd_logd("osd[%d] canvas.addr=0x%x\n", + index, osd_hw.fb_gem[index].addr); + osd_logd("osd[%d] canvas.width=%d\n", + index, CANVAS_ALIGNED(osd_hw.fb_gem[index].width)); + osd_logd("osd[%d] canvas.height=%d\n", + index, osd_hw.fb_gem[index].height); } /* osd blank only control by /sys/class/graphcis/fbx/blank */ #if 0 @@ -830,7 +1029,7 @@ add_to_update_list(index, DISP_GEOMETRY); add_to_update_list(index, DISP_OSD_REVERSE); #ifdef AML_OSD_HIGH_VERSION - if (osd_hw.osd_ver == OSD_HIGH_ONE) + if (osd_hw.osd_ver == OSD_HIGH_ONE && index < VIU2_OSD1) osd_setting_default_hwc(index, &disp_data); #endif osd_wait_vsync_hw(); @@ -1264,12 +1463,12 @@ osd_hw.dispdata[index].y_end = osd_hw.dispdata[OSD1].y_start + g_rotation_width; } else { - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) { + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) { osd_reg_set_mask(VPU_SW_RESET, 1 << 8); osd_reg_clr_mask(VPU_SW_RESET, 1 << 8); } if (index == OSD1) { - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) { + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) { osd_reg_set_mask(VIU_SW_RESET, 1 << 0); osd_reg_clr_mask(VIU_SW_RESET, 1 << 0); } @@ -1423,6 +1622,22 @@ } } +static void viu2_osd1_update_disp_scale_enable(void) +{ + if (osd_hw.scale[VIU2_OSD1].h_enable) + VSYNCOSD_SET_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0, 3 << 12); + else + VSYNCOSD_CLR_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0, 3 << 12); + if (osd_hw.scan_mode != SCAN_MODE_INTERLACE) { + if (osd_hw.scale[VIU2_OSD1].v_enable) + VSYNCOSD_SET_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0, + 1 << 14); + else + VSYNCOSD_CLR_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0, + 1 << 14); + } +} + static void osd_super_scale_enable(u32 index) { u32 data32 = 0x0; @@ -1479,6 +1694,7 @@ int hf_bank_len = 4; int vf_bank_len = 0; u32 data32 = 0x0; + u32 shift_line = osd_hw.shift_line; osd_logi("osd1_update_disp_freescale_enable\n"); if (osd_hw.scale_workaround) @@ -1506,7 +1722,7 @@ osd_hw.free_dst_data[OSD1].x_start + 1; dst_h = osd_hw.free_dst_data[OSD1].y_end - osd_hw.free_dst_data[OSD1].y_start + 1; - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_MG9TV) { + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_MG9TV) { /* super scaler mode */ if (osd_hw.free_scale_mode[OSD1] & 0x2) { if (osd_hw.free_scale_enable[OSD1]) @@ -1538,9 +1754,12 @@ bot_ini_phase = 0; vf_phase_step = (vf_phase_step << 4); /* config osd scaler in/out hv size */ + if (shift_line) + vsc_ini_rcv_num++; + data32 = 0x0; if (osd_hw.free_scale_enable[OSD1]) { - data32 = (((src_h - 1) & 0x1fff) + data32 = (((src_h - 1 + shift_line) & 0x1fff) | ((src_w - 1) & 0x1fff) << 16); VSYNCOSD_WR_MPEG_REG(VPP_OSD_SCI_WH_M1, data32); data32 = ((osd_hw.free_dst_data[OSD1].x_end & 0xfff) | @@ -1640,6 +1859,8 @@ int hf_bank_len = 4; int vf_bank_len = 4; u32 data32 = 0x0; + u32 shift_line = osd_hw.shift_line; + if (osd_hw.scale_workaround) vf_bank_len = 2; hsc_ini_rcv_num = hf_bank_len; @@ -1653,7 +1874,7 @@ osd_hw.free_dst_data[OSD2].x_start + 1; dst_h = osd_hw.free_dst_data[OSD2].y_end - osd_hw.free_dst_data[OSD2].y_start + 1; - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_MG9TV) { + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_MG9TV) { /* super scaler mode */ if (osd_hw.free_scale_mode[OSD2] & 0x2) { if (osd_hw.free_scale_enable[OSD2]) @@ -1687,9 +1908,11 @@ bot_ini_phase = 0; vf_phase_step = (vf_phase_step << 4); /* config osd scaler in/out hv size */ + if (shift_line) + vsc_ini_rcv_num++; data32 = 0x0; if (osd_hw.free_scale_enable[OSD2]) { - data32 = (((src_h - 1) & 0x1fff) + data32 = (((src_h - 1 + shift_line) & 0x1fff) | ((src_w - 1) & 0x1fff) << 16); VSYNCOSD_WR_MPEG_REG(VPP_OSD_SCI_WH_M1, data32); data32 = ((osd_hw.free_dst_data[OSD2].x_end & 0xfff) | @@ -1778,6 +2001,57 @@ remove_from_update_list(OSD2, OSD_FREESCALE_COEF); } +static void viu2_osd1_update_disp_freescale_enable(void) +{ + /* do nothing */ + + remove_from_update_list(VIU2_OSD1, DISP_FREESCALE_ENABLE); +} + +static void viu2_osd1_update_coef(void) +{ + int i; + bool need_update_coef = false; + int hf_coef_wren = 1; + int vf_coef_wren = 1; + unsigned int *hf_coef, *vf_coef; + if (osd_hw.scale_workaround) { + if (use_v_filter_mode != 3) { + use_v_filter_mode = 3; + need_update_coef = true; + } else + need_update_coef = false; + } else { + if (use_v_filter_mode != osd_v_filter_mode) { + use_v_filter_mode = osd_v_filter_mode; + need_update_coef = true; + } else + need_update_coef = false; + } + if (need_update_coef) { + vf_coef = filter_table[use_v_filter_mode]; + if (vf_coef_wren) { + osd_reg_set_bits(VPP_OSD_SCALE_COEF_IDX, 0x0000, 0, 9); + for (i = 0; i < 33; i++) + osd_reg_write(VPP_OSD_SCALE_COEF, vf_coef[i]); + } + } + need_update_coef = false; + if (use_h_filter_mode != osd_h_filter_mode) { + use_h_filter_mode = osd_h_filter_mode; + need_update_coef = true; + } + hf_coef = filter_table[use_h_filter_mode]; + if (need_update_coef) { + if (hf_coef_wren) { + osd_reg_set_bits(VPP_OSD_SCALE_COEF_IDX, 0x0100, 0, 9); + for (i = 0; i < 33; i++) + osd_reg_write(VPP_OSD_SCALE_COEF, hf_coef[i]); + } + } + remove_from_update_list(VIU2_OSD1, OSD_FREESCALE_COEF); +} + static void osd1_update_color_mode(void) { u32 data32 = 0; @@ -1789,7 +2063,7 @@ if (!osd_hw.rotate[OSD1].on_off) data32 |= OSD_DATA_LITTLE_ENDIAN << 15; data32 |= osd_hw.color_info[OSD1]->hw_colormat << 2; - if (get_cpu_id().family_id < MESON_CPU_MAJOR_ID_GXTVBB) { + if (osd_get_chip_type() < MESON_CPU_MAJOR_ID_GXTVBB) { if (osd_hw.color_info[OSD1]->color_index < COLOR_INDEX_YUV_422) data32 |= 1 << 7; /* yuv enable */ @@ -1812,7 +2086,7 @@ if (!osd_hw.rotate[OSD2].on_off) data32 |= OSD_DATA_LITTLE_ENDIAN << 15; data32 |= osd_hw.color_info[OSD2]->hw_colormat << 2; - if (get_cpu_id().family_id != MESON_CPU_MAJOR_ID_GXTVBB) { + if (osd_get_chip_type() != MESON_CPU_MAJOR_ID_GXTVBB) { if (osd_hw.color_info[OSD2]->color_index < COLOR_INDEX_YUV_422) data32 |= 1 << 7; /* yuv enable */ @@ -1824,6 +2098,25 @@ remove_from_update_list(OSD2, OSD_COLOR_MODE); } +static void viu2_osd1_update_color_mode(void) +{ + u32 data32 = 0; + if (osd_hw.color_info[VIU2_OSD1] != NULL) { + data32 = (osd_hw.scan_mode == SCAN_MODE_INTERLACE) ? 2 : 0; + data32 |= VSYNCOSD_RD_MPEG_REG(VIU2_OSD1_BLK0_CFG_W0) + & 0x30007040; + data32 |= osd_hw.fb_gem[VIU2_OSD1].canvas_idx << 16; + if (!osd_hw.rotate[VIU2_OSD1].on_off) + data32 |= OSD_DATA_LITTLE_ENDIAN << 15; + data32 |= osd_hw.color_info[VIU2_OSD1]->hw_colormat << 2; + + /* osd_blk_mode */ + data32 |= osd_hw.color_info[VIU2_OSD1]->hw_blkmode << 8; + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W0, data32); + } + remove_from_update_list(VIU2_OSD1, OSD_COLOR_MODE); +} + static void osd1_update_enable(void) { u32 video_enable = 0; @@ -1833,9 +2126,9 @@ if (osd_hw.osd_ver <= OSD_NORMAL) VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC, VPP_OSD1_POSTBLEND | VPP_POSTBLEND_EN); - VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD1_CTRL_STAT, 1 << 21); + VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD1_CTRL_STAT, 1 << 0); } else { - VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD1_CTRL_STAT, 1 << 21); + VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD1_CTRL_STAT, 1 << 0); if (osd_hw.osd_ver <= OSD_NORMAL) VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC, VPP_OSD1_POSTBLEND); @@ -1876,36 +2169,37 @@ u32 video_enable = 0; if (osd_hw.free_scale_mode[OSD2]) { - if (osd_hw.enable[OSD2] == ENABLE) { + if (osd_hw.enable[OSD2] == ENABLE) + VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT, + 1 << 0); + else + VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT, + 1 << 0); + + /* for older chips than g12a: + * freescale output always on VPP_OSD1_POSTBLEND + * if freescale is enable, VPP_OSD1_POSTBLEND to control OSD1&OSD2 + * if freescale is disable, VPP_OSD2_POSTBLEND to control OSD2 + */ + if (osd_hw.osd_ver <= OSD_NORMAL) { if (osd_hw.free_scale_enable[OSD2]) { - if (osd_hw.osd_ver <= OSD_NORMAL) - VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC, - VPP_OSD1_POSTBLEND - | VPP_POSTBLEND_EN); - VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT, - 1 << 21); + if (osd_hw.enable[OSD2] == ENABLE) + VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC, + VPP_OSD1_POSTBLEND + | VPP_POSTBLEND_EN); + else + if (!osd_hw.enable[OSD1]) + VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC, + VPP_OSD1_POSTBLEND); } else { - VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT, - 1 << 21); -#ifndef CONFIG_FB_OSD2_CURSOR - /* - VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC, - VPP_OSD1_POSTBLEND); - */ -#endif - if (osd_hw.osd_ver <= OSD_NORMAL) - VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC, - VPP_OSD2_POSTBLEND - | VPP_POSTBLEND_EN); + if (osd_hw.enable[OSD2] == ENABLE) + VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC, + VPP_OSD2_POSTBLEND + | VPP_POSTBLEND_EN); + else + VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC, + VPP_OSD2_POSTBLEND); } - } else { - if (osd_hw.enable[OSD1] == ENABLE) - VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC, - VPP_OSD2_POSTBLEND); - else - VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC, - VPP_OSD1_POSTBLEND - | VPP_OSD2_POSTBLEND); } } else if (osd_hw.osd_ver <= OSD_NORMAL){ video_enable |= VSYNCOSD_RD_MPEG_REG(VPP_MISC)&VPP_VD1_PREBLEND; @@ -1937,6 +2231,17 @@ remove_from_update_list(OSD2, OSD_ENABLE); } +static void viu2_osd1_update_enable(void) +{ + /* do nothing for VPP2_MISC */ + if (osd_hw.enable[VIU2_OSD1] == ENABLE) + VSYNCOSD_SET_MPEG_REG_MASK(VIU2_OSD1_CTRL_STAT, 1 << 0); + else + VSYNCOSD_CLR_MPEG_REG_MASK(VIU2_OSD1_CTRL_STAT, 1 << 0); + + remove_from_update_list(VIU2_OSD1, OSD_ENABLE); +} + static void osd1_update_disp_osd_reverse(void) { if (osd_hw.osd_reverse[OSD1]) @@ -1954,6 +2259,16 @@ VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_BLK0_CFG_W0, 3 << 28); remove_from_update_list(OSD2, DISP_OSD_REVERSE); } + +static void viu2_osd1_update_disp_osd_reverse(void) +{ + if (osd_hw.osd_reverse[VIU2_OSD1]) + VSYNCOSD_WR_MPEG_REG_BITS(VIU2_OSD1_BLK0_CFG_W0, 3, 28, 2); + else + VSYNCOSD_CLR_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0, 3 << 28); + remove_from_update_list(VIU2_OSD1, DISP_OSD_REVERSE); +} + static void osd1_update_disp_osd_rotate(void) { #if 0 @@ -1993,7 +2308,7 @@ y_start = osd_hw.rotation_pandata[OSD1].y_start; y_end = osd_hw.rotation_pandata[OSD1].y_end; y_len_m1 = y_end - y_start; - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) { + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) { osd_set_prot( x_rev, y_rev, @@ -2063,7 +2378,7 @@ y_start = osd_hw.rotation_pandata[OSD2].y_start; y_end = osd_hw.rotation_pandata[OSD2].y_end; y_len_m1 = y_end - y_start; - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) { + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) { osd_set_prot( x_rev, y_rev, @@ -2094,6 +2409,12 @@ remove_from_update_list(OSD2, DISP_OSD_ROTATE); } +static void viu2_osd1_update_disp_osd_rotate(void) +{ + /* do nothing*/ + + remove_from_update_list(VIU2_OSD1, DISP_OSD_ROTATE); +} static void osd1_update_color_key(void) { @@ -2107,6 +2428,12 @@ remove_from_update_list(OSD2, OSD_COLOR_KEY); } +static void viu2_osd1_update_color_key(void) +{ + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_TCOLOR_AG0, osd_hw.color_key[VIU2_OSD1]); + remove_from_update_list(VIU2_OSD1, OSD_COLOR_KEY); +} + static void osd1_update_color_key_enable(void) { u32 data32; @@ -2126,7 +2453,18 @@ VSYNCOSD_WR_MPEG_REG(VIU_OSD2_BLK0_CFG_W0, data32); remove_from_update_list(OSD2, OSD_COLOR_KEY_ENABLE); } -static void osd1_update_gbl_alpha(void) + +static void viu2_osd1_update_color_key_enable(void) +{ + u32 data32; + data32 = VSYNCOSD_RD_MPEG_REG(VIU2_OSD1_BLK0_CFG_W0); + data32 &= ~(1 << 6); + data32 |= (osd_hw.color_key_enable[VIU2_OSD1] << 6); + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W0, data32); + remove_from_update_list(VIU2_OSD1, OSD_COLOR_KEY_ENABLE); +} + +static void osd1_update_gbl_alpha(void) { u32 data32; data32 = VSYNCOSD_RD_MPEG_REG(VIU_OSD1_CTRL_STAT); @@ -2135,7 +2473,8 @@ VSYNCOSD_WR_MPEG_REG(VIU_OSD1_CTRL_STAT, data32); remove_from_update_list(OSD1, OSD_GBL_ALPHA); } -static void osd2_update_gbl_alpha(void) + +static void osd2_update_gbl_alpha(void) { u32 data32; data32 = VSYNCOSD_RD_MPEG_REG(VIU_OSD2_CTRL_STAT); @@ -2144,7 +2483,18 @@ VSYNCOSD_WR_MPEG_REG(VIU_OSD2_CTRL_STAT, data32); remove_from_update_list(OSD2, OSD_GBL_ALPHA); } -static void osd2_update_order(void) + +static void viu2_osd1_update_gbl_alpha(void) +{ + u32 data32; + data32 = VSYNCOSD_RD_MPEG_REG(VIU2_OSD1_CTRL_STAT); + data32 &= ~(0x1ff << 12); + data32 |= osd_hw.gbl_alpha[VIU2_OSD1] << 12; + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_CTRL_STAT, data32); + remove_from_update_list(VIU2_OSD1, OSD_GBL_ALPHA); +} + +static void osd2_update_order(void) { switch (osd_hw.order) { case OSD_ORDER_01: @@ -2158,7 +2508,8 @@ } remove_from_update_list(OSD2, OSD_CHANGE_ORDER); } -static void osd1_update_order(void) + +static void osd1_update_order(void) { switch (osd_hw.order) { case OSD_ORDER_01: @@ -2173,6 +2524,13 @@ remove_from_update_list(OSD1, OSD_CHANGE_ORDER); } +static void viu2_osd1_update_order(void) +{ + /* do nothing */ + + remove_from_update_list(VIU2_OSD1, OSD_CHANGE_ORDER); +} + static void osd1_2x_scale_update_geometry(void) { u32 data32; @@ -2237,7 +2595,7 @@ { u32 data32; - if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_M8) { + if (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_M8) { data32 = (osd_hw.dispdata[OSD1].x_start & 0xfff) | (osd_hw.dispdata[OSD1].x_end & 0xfff) << 16; VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W3 , data32); @@ -2331,7 +2689,7 @@ | ((osd_hw.rotation_pandata[OSD1].y_end + osd_hw.pandata[OSD1].y_start) & 0x1fff) << 16; VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W2, data32); - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) VSYNCOSD_WR_MPEG_REG(VPU_PROT1_Y_START_END, data32); } else if (osd_hw.rotate[OSD1].on_off && osd_hw.rotate[OSD1].angle > 0) { @@ -2344,7 +2702,7 @@ | ((osd_hw.rotation_pandata[OSD1].y_end + osd_hw.pandata[OSD1].y_start) & 0x1fff) << 16; VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W2, data32); - if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) + if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) VSYNCOSD_WR_MPEG_REG(VPU_PROT1_Y_START_END, data32); } else { /* normal mode */ @@ -2355,10 +2713,6 @@ | (osd_hw.pandata[OSD1].y_end & 0x1fff) << 16; VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W2, data32); } - data32 = osd_reg_read(VIU_OSD1_CTRL_STAT); - data32 &= 0xfffffff0; - data32 |= HW_OSD_BLOCK_ENABLE_0; - osd_reg_write(VIU_OSD1_CTRL_STAT, data32); } static void osd1_update_disp_geometry(void) @@ -2421,7 +2775,33 @@ } remove_from_update_list(OSD2, DISP_GEOMETRY); } -static void osd1_update_disp_3d_mode(void) + +static void viu2_osd1_update_disp_geometry(void) +{ + u32 data32; + data32 = (osd_hw.dispdata[VIU2_OSD1].x_start & 0xfff) + | (osd_hw.dispdata[VIU2_OSD1].x_end & 0xfff) << 16; + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W3 , data32); + if (osd_hw.scan_mode == SCAN_MODE_INTERLACE) + data32 = ((osd_hw.dispdata[VIU2_OSD1].y_start >> 1) & 0xfff) + | ((((osd_hw.dispdata[VIU2_OSD1].y_end + 1) >> 1) - 1) + & 0xfff) << 16; + else + data32 = (osd_hw.dispdata[VIU2_OSD1].y_start & 0xfff) + | (osd_hw.dispdata[VIU2_OSD1].y_end & 0xfff) << 16; + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W4, data32); + + data32 = (osd_hw.pandata[VIU2_OSD1].x_start & 0x1fff) + | (osd_hw.pandata[VIU2_OSD1].x_end & 0x1fff) << 16; + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W1, data32); + data32 = (osd_hw.pandata[VIU2_OSD1].y_start & 0x1fff) + | (osd_hw.pandata[VIU2_OSD1].y_end & 0x1fff) << 16; + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W2, data32); + + remove_from_update_list(VIU2_OSD1, DISP_GEOMETRY); +} + +static void osd1_update_disp_3d_mode(void) { /*step 1 . set pan data */ u32 data32; @@ -2452,6 +2832,21 @@ osd_hw.mode_3d[OSD2].left_right ^= 1; } +static void viu2_osd1_update_disp_3d_mode(void) +{ + u32 data32; + if (osd_hw.mode_3d[VIU2_OSD1].left_right == OSD_LEFT) { + data32 = (osd_hw.mode_3d[VIU2_OSD1].l_start & 0x1fff) + | (osd_hw.mode_3d[VIU2_OSD1].l_end & 0x1fff) << 16; + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W1, data32); + } else { + data32 = (osd_hw.mode_3d[VIU2_OSD1].r_start & 0x1fff) + | (osd_hw.mode_3d[VIU2_OSD1].r_end & 0x1fff) << 16; + VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W1, data32); + } + osd_hw.mode_3d[VIU2_OSD1].left_right ^= 1; +} + void osd_hist_enable(u32 osd_index) { if (osd_hw.osd_ver == OSD_HIGH_ONE) { @@ -2481,6 +2876,90 @@ return 0; } +#ifdef AML_OSD_HIGH_VERSION +void osd_init_hw_viu2(void) +{ + u32 group, idx, data32; + char *osd_reverse; + + osd_reverse = env_get("osd_reverse"); + for (group = 0; group < HW_OSD_COUNT; group++) + for (idx = 0; idx < HW_REG_INDEX_MAX; idx++) + osd_hw.reg[group][idx].update_func = + hw_func_array[group][idx]; + + osd_hw.updated[VIU2_OSD1] = 0; + + osd_vpu_power_on_viu2(); + + osd_reg_write(VPP2_OFIFO_SIZE, 0x7ff00800); + + /* init osd fifo control register */ + /* set DDR request priority to be urgent */ + data32 = 1; + /* hold_fifo_lines */ + data32 |= 4 << 5; + /* burst_len_sel: 3=64 */ + data32 |= 1 << 10; + data32 |= 1 << 31; + + /* + * bit 23:22, fifo_ctrl + * 00 : for 1 word in 1 burst + * 01 : for 2 words in 1 burst + * 10 : for 4 words in 1 burst + * 11 : reserved + */ + data32 |= 2 << 22; + /* bit 28:24, fifo_lim */ + data32 |= 2 << 24; + /* fifo_depth_val: 32 or 64 *8 = 256 or 512 */ + data32 |= 64 << 12; + + osd_reg_write(VIU2_OSD1_FIFO_CTRL_STAT, data32); + + /* disable osd */ + data32 = 0x0 << 0; + data32 |= OSD_GLOBAL_ALPHA_DEF << 12; + data32 |= 0x80000000; + osd_reg_write(VIU2_OSD1_CTRL_STAT , data32); + + /* set replaced_alpha */ + data32 = 0x1 << 14; + data32 |= 0xff << 6; + osd_reg_write(VIU2_OSD1_CTRL_STAT2 , data32); + osd_hw.enable[VIU2_OSD1] = DISABLE; + + osd_hw.fb_gem[VIU2_OSD1].canvas_idx = OSD4_CANVAS_INDEX; + osd_hw.gbl_alpha[VIU2_OSD1] = OSD_GLOBAL_ALPHA_DEF; + osd_hw.color_info[VIU2_OSD1] = NULL; + osd_hw.color_key[VIU2_OSD1] = 0xffffffff; + osd_hw.scale[VIU2_OSD1].h_enable = osd_hw.scale[VIU2_OSD1].v_enable = 0; + osd_hw.mode_3d[VIU2_OSD1].enable = 0; + if (osd_reverse != NULL && strcmp(osd_reverse, "all,true") == 0) { + osd_hw.osd_reverse[VIU2_OSD1] = 1; + } else { + osd_hw.osd_reverse[VIU2_OSD1] = 0; + } + osd_hw.rotation_pandata[VIU2_OSD1].x_start = 0; + osd_hw.rotation_pandata[VIU2_OSD1].y_start = 0; +} +#endif + +static void set_vpp_super_position(void) +{ +#define PREBLD_SR0_VD1_SCALER (1 << 1) +#define DNLP_SR1_CM (1 << 3) + + if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_G12A) || + (osd_get_chip_type() == MESON_CPU_MAJOR_ID_G12B) || + (osd_get_chip_type() == MESON_CPU_MAJOR_ID_SM1)) + osd_reg_set_mask(VPP_MISC, PREBLD_SR0_VD1_SCALER); + else if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_TL1) || + (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_TM2)) + osd_reg_set_mask(VPP_MISC, DNLP_SR1_CM); +} + void osd_init_hw(void) { u32 group, idx, data32, data2; @@ -2502,7 +2981,8 @@ data32 = osd_reg_read(VPP_OFIFO_SIZE); osd_logi("VPP_OFIFO_SIZE:0x%x\n", data32); if (osd_hw.osd_ver == OSD_HIGH_ONE) { - data32 = 0xfff << 20; + data32 &= ~((0xfff << 20) | 0x3fff); + data32 |= (0xfff << 20); data32 |= (0xfff + 1); osd_reg_write(VPP_OFIFO_SIZE, data32); } @@ -2510,14 +2990,17 @@ /* init osd fifo control register */ /* set DDR request priority to be urgent */ data32 = 1; - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M6TV) - || (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_MTVD)) { + if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_M6TV) + || (osd_get_chip_type() == MESON_CPU_MAJOR_ID_MTVD)) { data32 |= 18 << 5; /* hold_fifo_lines */ } else if (osd_hw.osd_ver == OSD_SIMPLE) { data32 &= ~(0x1f << 5); /* bit[9:5] HOLD_FIFO_LINES */ data32 |= 0x18 << 5; } else { - data32 |= 4 << 5; /* hold_fifo_lines */ + if (osd_hw.osd_ver == OSD_HIGH_ONE) + data32 |= 8 << 5; /* hold_fifo_lines */ + else + data32 |= 4 << 5; /* hold_fifo_lines */ } /* burst_len_sel: 3=64 */ if (osd_hw.osd_ver == OSD_HIGH_ONE) { @@ -2526,7 +3009,7 @@ } else data32 |= 3 << 10; - if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_GXBB) { + if (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_GXBB) { /* * bit 23:22, fifo_ctrl * 00 : for 1 word in 1 burst @@ -2540,8 +3023,8 @@ } data2 = data32; /* fifo_depth_val: 32*8=256 */ - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXL) - || (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXLX)) + if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_TXL) + || (osd_get_chip_type() == MESON_CPU_MAJOR_ID_TXLX)) data32 |= 64 << 12; else data32 |= 32 << 12; @@ -2554,18 +3037,21 @@ osd_reg_clr_mask(VPP_MISC, VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | VPP_VD1_POSTBLEND); /* just disable osd to avoid booting hang up */ - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M6TV) - || (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_MTVD)) { - data32 = 0x0 << 0; /* osd_blk_enable */ - } else - data32 = 0x1 << 0; + data32 = 0x0 << 0; data32 |= OSD_GLOBAL_ALPHA_DEF << 12; - data32 |= (1 << 21); osd_reg_write(VIU_OSD1_CTRL_STAT , data32); osd_reg_write(VIU_OSD2_CTRL_STAT , data32); + + /* set replaced_alpha */ + data32 = 0x1 << 14; + data32 |= 0xff << 6; + osd_reg_write(VIU_OSD1_CTRL_STAT2 , data32); + osd_reg_write(VIU_OSD2_CTRL_STAT2 , data32); } if (osd_hw.osd_ver <= OSD_NORMAL) osd_reg_clr_mask(VPP_MISC, VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2); + else if (osd_hw.osd_ver > OSD_NORMAL) + set_vpp_super_position(); osd_hw.order = OSD_ORDER_01; osd_hw.enable[OSD2] = osd_hw.enable[OSD1] = DISABLE; osd_hw.fb_gem[OSD1].canvas_idx = OSD1_CANVAS_INDEX; @@ -2593,7 +3079,7 @@ osd_hw.rotation_pandata[OSD2].x_start = 0; osd_hw.rotation_pandata[OSD2].y_start = 0; osd_hw.antiflicker_mode = 0; - if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_M8) { + if (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_M8) { osd_hw.free_scale_data[OSD1].x_start = 0; osd_hw.free_scale_data[OSD1].x_end = 0; osd_hw.free_scale_data[OSD1].y_start = 0; @@ -2604,10 +3090,10 @@ osd_hw.free_scale_data[OSD2].y_end = 0; osd_hw.free_scale_mode[OSD1] = 1; osd_hw.free_scale_mode[OSD2] = 1; - if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM) - ||(get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXLX)) + if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_GXM) + ||(osd_get_chip_type() == MESON_CPU_MAJOR_ID_TXLX)) osd_reg_write(VPP_OSD_SC_DUMMY_DATA, 0x00202000); - else if (get_cpu_id().family_id == + else if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_GXTVBB) osd_reg_write(VPP_OSD_SC_DUMMY_DATA, 0xff); else @@ -2617,7 +3103,12 @@ osd_hw.free_scale_mode[OSD2] = 0; } memset(osd_hw.rotate, 0, sizeof(struct osd_rotate_s)); - + if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_G12A) || + ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_G12B) && + (get_cpu_id().chip_rev == MESON_CPU_CHIP_REVISION_A))) + osd_hw.shift_line = 1; + else + osd_hw.shift_line = 0; return; }
diff --git a/drivers/amlogic/media/osd/osd_hw.h b/drivers/amlogic/media/osd/osd_hw.h index 9dc9d5c..5679bc6 100644 --- a/drivers/amlogic/media/osd/osd_hw.h +++ b/drivers/amlogic/media/osd/osd_hw.h
@@ -11,6 +11,7 @@ #define REG_OFFSET (0x20) #define OSD_RELATIVE_BITS 0x33370 +extern int osd_get_chip_type(void); extern void osd_init_hw(void); extern void osd_set_color_key_hw(u32 index, u32 bpp, u32 colorkey); extern void osd_srckey_enable_hw(u32 index, u8 enable);
diff --git a/drivers/amlogic/media/osd/osd_hw_def.h b/drivers/amlogic/media/osd/osd_hw_def.h index 4b0af8e..559ed10 100644 --- a/drivers/amlogic/media/osd/osd_hw_def.h +++ b/drivers/amlogic/media/osd/osd_hw_def.h
@@ -36,6 +36,20 @@ static void osd2_update_disp_scale_enable(void); static void osd2_update_disp_3d_mode(void); +static void viu2_osd1_update_color_mode(void); +static void viu2_osd1_update_enable(void); +static void viu2_osd1_update_color_key(void); +static void viu2_osd1_update_color_key_enable(void); +static void viu2_osd1_update_gbl_alpha(void); +static void viu2_osd1_update_order(void); +static void viu2_osd1_update_disp_geometry(void); +static void viu2_osd1_update_coef(void); +static void viu2_osd1_update_disp_freescale_enable(void); +static void viu2_osd1_update_disp_osd_reverse(void); +static void viu2_osd1_update_disp_osd_rotate(void); +static void viu2_osd1_update_disp_scale_enable(void); +static void viu2_osd1_update_disp_3d_mode(void); + extern struct hw_para_s osd_hw; static update_func_t hw_func_array[HW_OSD_COUNT][HW_REG_INDEX_MAX] = { { @@ -66,6 +80,20 @@ osd2_update_disp_osd_reverse, osd2_update_disp_osd_rotate, }, + { + viu2_osd1_update_color_mode, + viu2_osd1_update_enable, + viu2_osd1_update_color_key, + viu2_osd1_update_color_key_enable, + viu2_osd1_update_gbl_alpha, + viu2_osd1_update_order, + viu2_osd1_update_coef, + viu2_osd1_update_disp_geometry, + viu2_osd1_update_disp_scale_enable, + viu2_osd1_update_disp_freescale_enable, + viu2_osd1_update_disp_osd_reverse, + viu2_osd1_update_disp_osd_rotate, + }, }; #define add_to_update_list(osd_idx, cmd_idx) \
diff --git a/drivers/amlogic/media/osd/osd_io.h b/drivers/amlogic/media/osd/osd_io.h index fdd030a..b1a02ae 100644 --- a/drivers/amlogic/media/osd/osd_io.h +++ b/drivers/amlogic/media/osd/osd_io.h
@@ -9,34 +9,97 @@ #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> +#ifndef REG_BASE_VCBUS +#define REG_BASE_VCBUS (0xFF900000L) +#endif -#define REG_OFFSET_CBUS(reg) ((reg << 2)) +/* osd super scale */ +#ifndef OSDSR_HV_SIZEIN +#define OSDSR_HV_SIZEIN VPP_OSDSC_DITHER_CTRL +#endif + +#ifndef OSDSR_CTRL_MODE +#define OSDSR_CTRL_MODE VPP_OSDSC_DITHER_LUT_1 +#endif + +#ifdef OSDSR_ABIC_HCOEF +#define OSDSR_ABIC_HCOEF VPP_OSDSC_DITHER_LUT_2 +#endif + +#ifndef OSDSR_YBIC_HCOEF +#define OSDSR_YBIC_HCOEF VPP_OSDSC_DITHER_LUT_3 +#endif + +#ifndef OSDSR_CBIC_HCOEF +#define OSDSR_CBIC_HCOEF VPP_OSDSC_DITHER_LUT_4 +#endif + +#ifndef OSDSR_ABIC_VCOEF +#define OSDSR_ABIC_VCOEF VPP_OSDSC_DITHER_LUT_5 +#endif + +#ifndef OSDSR_YBIC_VCOEF +#define OSDSR_YBIC_VCOEF VPP_OSDSC_DITHER_LUT_6 +#endif + +#ifndef OSDSR_CBIC_VCOEF +#define OSDSR_CBIC_VCOEF VPP_OSDSC_DITHER_LUT_7 +#endif + +#ifndef OSDSR_VAR_PARA +#define OSDSR_VAR_PARA VPP_OSDSC_DITHER_LUT_8 +#endif + +#ifndef OSDSR_CONST_PARA +#define OSDSR_CONST_PARA VPP_OSDSC_DITHER_LUT_9 +#endif + +#ifndef OSDSR_RKE_EXTWIN +#define OSDSR_RKE_EXTWIN VPP_OSDSC_DITHER_LUT_10 +#endif + +#ifndef OSDSR_UK_GRAD2DDIAG_TH_RATE +#define OSDSR_UK_GRAD2DDIAG_TH_RATE VPP_OSDSC_DITHER_LUT_11 +#endif + +#ifndef OSDSR_UK_GRAD2DDIAG_LIMIT +#define OSDSR_UK_GRAD2DDIAG_LIMIT VPP_OSDSC_DITHER_LUT_12 +#endif + +#ifndef OSDSR_UK_GRAD2DADJA_TH_RATE +#define OSDSR_UK_GRAD2DADJA_TH_RATE VPP_OSDSC_DITHER_LUT_13 +#endif + +#ifndef OSDSR_UK_GRAD2DADJA_LIMIT +#define OSDSR_UK_GRAD2DADJA_LIMIT VPP_OSDSC_DITHER_LUT_14 +#endif + +#ifndef OSDSR_UK_BST_GAIN +#define OSDSR_UK_BST_GAIN VPP_OSDSC_DITHER_LUT_15 +#endif + #define REG_OFFSET_VCBUS(reg) ((reg << 2)) - -#define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg)) #define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg)) - -static inline u32 osd_cbus_read(u32 reg) -{ - return (*(volatile unsigned int *)REG_ADDR_CBUS(reg)); -} - -static inline void osd_cbus_write(u32 reg, - const u32 val) -{ - *(volatile unsigned int *)REG_ADDR_CBUS(reg) = (val); -} - +#define REG_OSD_ADDR(reg) (reg + 0L) static inline u32 osd_reg_read(u32 reg) { - return (*(volatile unsigned int *)REG_ADDR_VCBUS(reg)); + u32 val; + + if (reg > 0x10000) + val = *(volatile unsigned int *)REG_OSD_ADDR(reg); + else + val = *(volatile unsigned int *)REG_ADDR_VCBUS(reg); + return val; } static inline void osd_reg_write(u32 reg, const u32 val) { - *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val); + if (reg > 0x10000) + *(volatile unsigned int *)REG_OSD_ADDR(reg) = (val); + else + *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val); } static inline void osd_reg_set_mask(u32 reg,
diff --git a/drivers/amlogic/media/osd/vpp.h b/drivers/amlogic/media/osd/vpp.h index c699c50..b1eb2c7 100644 --- a/drivers/amlogic/media/osd/vpp.h +++ b/drivers/amlogic/media/osd/vpp.h
@@ -19,4 +19,6 @@ #define VPP_PREBLEND_EN (1 << 6) #define VPP_POST_FG_OSD2 (1 << 4) +void set_vpp_matrix(int m_select, int *s, int on); + #endif
diff --git a/drivers/amlogic/media/vout/Makefile b/drivers/amlogic/media/vout/Makefile index 1369907..1b345cf 100644 --- a/drivers/amlogic/media/vout/Makefile +++ b/drivers/amlogic/media/vout/Makefile
@@ -4,6 +4,6 @@ obj-$(CONFIG_AML_CVBS) += cvbs/ -obj-$(CONFIG_AML_HDMITX) += hdmitx/ - obj-$(CONFIG_AML_LCD) += lcd/ + +obj-$(CONFIG_AML_HDMITX) += hdmitx/
diff --git a/drivers/amlogic/media/vout/cvbs/Makefile b/drivers/amlogic/media/vout/cvbs/Makefile index 3199606..2d21bd6 100644 --- a/drivers/amlogic/media/vout/cvbs/Makefile +++ b/drivers/amlogic/media/vout/cvbs/Makefile
@@ -1 +1 @@ -obj-$(CONFIG_AML_CVBS) += aml_cvbs.o \ No newline at end of file +obj-$(CONFIG_AML_CVBS) += cvbs.o vdac.o \ No newline at end of file
diff --git a/drivers/amlogic/media/vout/cvbs/aml_cvbs.c b/drivers/amlogic/media/vout/cvbs/aml_cvbs.c deleted file mode 100644 index c887e7c..0000000 --- a/drivers/amlogic/media/vout/cvbs/aml_cvbs.c +++ /dev/null
@@ -1,834 +0,0 @@ -/* - * drivers/display/vout/cvbs.c - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * Author: jets.yan@amlogic.com - * -*/ -#include <common.h> -#include <asm/arch/io.h> -#include <asm/arch/secure_apb.h> -#include <asm/arch/cpu.h> -#include <amlogic/cpu_id.h> -#include "aml_cvbs_regs.h" -#include "aml_cvbs_config.h" - -/*----------------------------------------------------------------------------*/ -// global variables -enum CVBS_MODE_e -{ - VMODE_PAL, - VMODE_NTSC, - VMODE_PAL_M, - VMODE_PAL_N, - VMODE_NTSC_M, - VMODE_MAX -}; - -unsigned int cvbs_mode = VMODE_MAX; -/*bit[0]: 0=vid_pll, 1=gp0_pll*/ -/*bit[1]: 0=vid2_clk, 1=vid1_clk*/ -/*path 0:vid_pll vid2_clk*/ -/*path 1:gp0_pll vid2_clk*/ -/*path 2:vid_pll vid1_clk*/ -/*path 3:gp0_pll vid1_clk*/ -static unsigned int s_enci_clk_path = 0; - -/*----------------------------------------------------------------------------*/ -// interface for registers of soc - -#define REG_OFFSET_VCBUS(reg) (((reg) << 2)) -#define REG_OFFSET_CBUS(reg) (((reg) << 2)) - -/* memory mapping */ -#define REG_ADDR_HIU(reg) (reg + 0L) -#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg)) -#define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg)) - -static unsigned int cvbs_get_hiu_logic_addr(unsigned int addr_offset) -{ - return (REG_BASE_HIU + ((addr_offset&0xff)<<2)); -} - -static int cvbs_write_cbus(unsigned int addr_offset, unsigned int value) -{ - *(volatile unsigned int *)REG_ADDR_CBUS(addr_offset) = (value); - return 0; -} - -static int cvbs_read_cbus(unsigned int addr_offset) -{ - unsigned int val = 0; - - val = *(volatile unsigned int *)(REG_ADDR_CBUS(addr_offset)); - return val; -} - -static int cvbs_write_hiu(unsigned int addr, unsigned int value) -{ - *(volatile unsigned int *)REG_ADDR_HIU(addr) = (value); - return 0; -} - -static int cvbs_read_hiu(unsigned int addr) -{ - unsigned int val = 0; - - val = *(volatile unsigned int *)(REG_ADDR_HIU(addr)); - return val; -} - -static int cvbs_set_hiu_bits(unsigned int addr, unsigned int value, unsigned int start, unsigned int len) -{ - cvbs_write_hiu(addr, ((cvbs_read_hiu(addr) & - ~(((1L << (len))-1) << (start))) | - (((value)&((1L<<(len))-1)) << (start)))); - return 0; -} - -static int cvbs_get_hiu_bits(unsigned int addr, unsigned int start, unsigned int len) -{ - return (cvbs_read_hiu(addr) >> (start)) & ((1L << (len)) - 1); -} - -static unsigned int cvbs_read_vcbus(unsigned int addr_offset) -{ - unsigned int val = 0; - - val = *(volatile unsigned int *)(REG_ADDR_VCBUS(addr_offset)); - return val; -} - -static int cvbs_write_vcbus(unsigned int addr_offset, unsigned int value) -{ - *(volatile unsigned int *)REG_ADDR_VCBUS(addr_offset) = (value); - return 0; -} - -static int cvbs_set_vcbus_bits(unsigned int addr_offset, unsigned int value, unsigned int start, unsigned int len) -{ - cvbs_write_vcbus(addr_offset, ((cvbs_read_vcbus(addr_offset) & - ~(((1L << (len))-1) << (start))) | - (((value)&((1L<<(len))-1)) << (start)))); - return 0; -} -#if 0 -static int cvbs_get_vcbus_bits(unsigned int addr_offset, unsigned int start, unsigned int len) -{ - return (cvbs_read_vcbus(addr_offset) >> (start)) & ((1L << (len)) - 1);} -#endif - -/*----------------------------------------------------------------------------*/ -// interface for cpu id checking - -static int check_cpu_type(unsigned int cpu_type) -{ - return (cvbs_read_cbus(ASSIST_HW_REV)==cpu_type); -} - -static bool inline is_equal_after_meson_cpu(unsigned int id) -{ - return (get_cpu_id().family_id >= id)?1:0; -} - -static bool inline is_meson_gxl_cpu(void) -{ - return (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL)? - 1:0; -} - -static bool inline is_meson_gxlx_cpu(void) -{ - return (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXLX)? - 1:0; -} - -static bool inline is_meson_g12a_cpu(void) -{ - return (get_cpu_id().family_id == - MESON_CPU_MAJOR_ID_G12A) ? 1 : 0; -} - -static inline bool is_meson_g12b_cpu(void) -{ - return (get_cpu_id().family_id == - MESON_CPU_MAJOR_ID_G12B) ? 1 : 0; -} - -static bool inline is_meson_txl_cpu(void) -{ - return (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXL)? - 1:0; -} - -static bool inline is_meson_gxm_cpu(void) -{ - return (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM)? - 1:0; - -} -static bool inline is_meson_gxl_package_905X(void) -{ - return ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) && - (get_cpu_id().package_id == MESON_CPU_PACKAGE_ID_905X))? - 1:0; -} - -static bool inline is_meson_gxl_package_905L(void) -{ - return ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) && - (get_cpu_id().package_id == MESON_CPU_PACKAGE_ID_905L))? - 1:0; -} - -/*----------------------------------------------------------------------------*/ -// configuration for enci bist -int cvbs_set_bist(char* bist_mode) -{ - if (!strcmp(bist_mode, "off")) - { - cvbs_write_vcbus(ENCI_VIDEO_MODE_ADV, 0x26); - cvbs_write_vcbus(ENCI_TST_EN, 0x0); - } else - { - unsigned int mode = 0; - - if (!strcmp(bist_mode, "fixval") || !strcmp(bist_mode, "0")) - mode = 0; - else if (!strcmp(bist_mode, "colorbar") || !strcmp(bist_mode, "1")) - mode = 1; - else if (!strcmp(bist_mode, "thinline") || !strcmp(bist_mode, "2")) - mode = 2; - else if (!strcmp(bist_mode, "dotgrid") || !strcmp(bist_mode, "3")) - mode = 3; - - cvbs_write_vcbus(ENCI_VIDEO_MODE_ADV, 0x2); - cvbs_write_vcbus(ENCI_TST_MDSEL, mode); - cvbs_write_vcbus(ENCI_TST_CLRBAR_STRT, 0x112); - cvbs_write_vcbus(ENCI_TST_CLRBAR_WIDTH, 0xb4); - cvbs_write_vcbus(ENCI_TST_EN, 0x1); - } - - return 0; -} - -/*----------------------------------------------------------------------------*/ -// configuration for vdac pin of the soc. -// config vdac path: -// 0 : close -// 1 : enci -// 2 : atv -// 3 : passthrough -int cvbs_set_vdac(int status) -{ - switch (status) - { - case 0:// close vdac - cvbs_write_hiu(HHI_VDAC_CNTL0, 0); - if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_TXL) && - !is_meson_gxlx_cpu() && !is_meson_g12a_cpu() && - !is_meson_g12b_cpu()) - cvbs_write_hiu(HHI_VDAC_CNTL1, 0); - else - cvbs_write_hiu(HHI_VDAC_CNTL1, 8); - break; - case 1:// from enci to vdac - cvbs_set_vcbus_bits(VENC_VDAC_DACSEL0, 0, 5, 1); - if (is_meson_g12a_cpu()) - cvbs_write_hiu(HHI_VDAC_CNTL0, 0x906001); - else if (is_meson_g12b_cpu()) - cvbs_write_hiu(HHI_VDAC_CNTL0, 0x8f6001); - else if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_GXL)) { - if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_TXL) && - !is_meson_gxlx_cpu()) - cvbs_write_hiu(HHI_VDAC_CNTL0, 0x620001); - else - cvbs_write_hiu(HHI_VDAC_CNTL0, 0xb0001); - } else - cvbs_write_hiu(HHI_VDAC_CNTL0, 1); - - if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_TXL) && - !is_meson_gxlx_cpu() && !is_meson_g12a_cpu() && - !is_meson_g12b_cpu()) - cvbs_write_hiu(HHI_VDAC_CNTL1, 8); - else - cvbs_write_hiu(HHI_VDAC_CNTL1, 0); - break; - case 2:// from atv to vdac - cvbs_set_vcbus_bits(VENC_VDAC_DACSEL0, 1, 5, 1); - cvbs_write_hiu(HHI_VDAC_CNTL0, 1); - cvbs_write_hiu(HHI_VDAC_CNTL1, 0); - break; - case 3:// from cvbs_in passthrough to cvbs_out with vdac disabled - cvbs_write_hiu(HHI_VDAC_CNTL0, 0x400); - cvbs_write_hiu(HHI_VDAC_CNTL1, 8); - break; - default: - break; - } - - return 0; -} - -/*----------------------------------------------------------------------------*/ -// interface for debug -static void cvbs_dump_cvbs_regs(void) -{ - struct reg_s *p = NULL; - - if (VMODE_PAL == cvbs_mode) { - // 576cvbs - p = (struct reg_s*)&tvregs_576cvbs_enc[0]; - - } else if (VMODE_NTSC == cvbs_mode) { - // 480cvbs - p = (struct reg_s*)&tvregs_480cvbs_enc[0]; - } - - if (NULL == p) { - printf("it's not in cvbs mode!\n"); - return; - } - - if (MREG_END_MARKER != p->reg) - printf("cvbs enci registers:\n"); - while (MREG_END_MARKER != p->reg) { - printf(" vcbus[0x%.2x] = 0x%.4x\n", p->reg, cvbs_read_vcbus(p->reg)); - p ++; - } - - return; -} - -unsigned int cvbs_clk_regs[] = { - HHI_HDMI_PLL_CNTL0, - HHI_HDMI_PLL_CNTL1, - HHI_HDMI_PLL_CNTL2, - HHI_HDMI_PLL_CNTL3, - HHI_HDMI_PLL_CNTL4, - HHI_HDMI_PLL_CNTL5, - HHI_HDMI_PLL_CNTL6, - HHI_VID_PLL_CLK_DIV, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_DIV, - HHI_VID_CLK_CNTL2, - MREG_END_MARKER -}; - -static void cvbs_dump_clock_regs(void) -{ - unsigned int *p = &cvbs_clk_regs[0]; - - if (MREG_END_MARKER != *p) - printf("cvbs clock registers:\n"); - while (MREG_END_MARKER != *p) { - printf(" hiu[0x%.2x] = 0x%.4x\n", *p, cvbs_read_hiu(*p)); - p ++; - } - - return; -} - -int cvbs_reg_debug(int argc, char* const argv[]) -{ - unsigned int addr, start, end, value; - - if (!strcmp(argv[1], "r")) - { - if (argc != 4) - goto fail_cmd; - - addr = simple_strtoul(argv[3], NULL, 16); - if (!strcmp(argv[2], "c")) - printf("cvbs read cbus[0x%.2x] = 0x%.4x\n", addr, cvbs_read_cbus(addr)); - else if (!strcmp(argv[2], "h")) - printf("cvbs read hiu[0x%.2x] = 0x%.4x\n", addr, cvbs_read_hiu(cvbs_get_hiu_logic_addr(addr))); - else if (!strcmp(argv[2], "v")) - printf("cvbs read vcbus[0x%.2x] = 0x%.4x\n", addr, cvbs_read_vcbus(addr)); - } else if (!strcmp(argv[1], "w")) { - if (argc != 5) - goto fail_cmd; - - addr = simple_strtoul(argv[4], NULL, 16); - value = simple_strtoul(argv[2], NULL, 16); - if (!strcmp(argv[3], "c")) { - cvbs_write_cbus(addr, value); - printf("cvbs write cbus[0x%.2x] = 0x%.4x\n", addr, cvbs_read_cbus(addr)); - } else if (!strcmp(argv[3], "h")) { - cvbs_write_hiu(cvbs_get_hiu_logic_addr(addr), value); - printf("cvbs write hiu[0x%.2x] = 0x%.4x\n", addr, cvbs_read_hiu(cvbs_get_hiu_logic_addr(addr))); - } else if (!strcmp(argv[3], "v")) { - cvbs_write_vcbus(addr, value); - printf("cvbs write hiu[0x%.2x] = 0x%.4x\n", addr, cvbs_read_vcbus(addr)); - } - } else if (!strcmp(argv[1], "dump")) { - unsigned int i = 0; - unsigned int type = 0xff; - - if (argc != 5) - goto fail_cmd; - - if (!strcmp(argv[2], "h")) - type = BUS_TYPE_CBUS; - if (!strcmp(argv[2], "h")) - type = BUS_TYPE_HIU; - else if (!strcmp(argv[2], "v")) - type = BUS_TYPE_VCBUS; - - if (type == 0xff) - goto fail_cmd; - - start = simple_strtoul(argv[3], NULL, 16); - end = simple_strtoul(argv[4], NULL, 16); - - if (type == BUS_TYPE_CBUS) { - for (i=start; i<=end; i++) - printf("cvbs read cbus[0x%.2x] = 0x%.4x\n", i, cvbs_read_cbus(i)); - } if (type == BUS_TYPE_HIU) { - for (i=start; i<=end; i++) - printf("cvbs read hiu[0x%.2x] = 0x%.4x\n", i, cvbs_read_hiu(cvbs_get_hiu_logic_addr(i))); - } else if (type == BUS_TYPE_VCBUS) { - for (i=start; i<=end; i++) - printf("cvbs read vcbus[0x%.2x] = 0x%.4x\n", i, cvbs_read_vcbus(i)); - } - } else if (!strcmp(argv[1], "clock")) { - if (argc != 2) - goto fail_cmd; - - cvbs_dump_clock_regs(); - } else if (!strcmp(argv[1], "enci")) { - if (argc != 2) - goto fail_cmd; - - cvbs_dump_cvbs_regs(); - } else if (!strcmp(argv[1], "set_clkpath")) { - if (argc != 3) - goto fail_cmd; - value = simple_strtoul(argv[2], NULL, 0); - if (check_cpu_type(MESON_CPU_MAJOR_ID_G12A) || - check_cpu_type(MESON_CPU_MAJOR_ID_G12B)) { - if (value == 1 || value == 2 || - value == 3 || value == 0) { - s_enci_clk_path = value; - printf("path 0:vid_pll vid2_clk\n"); - printf("path 1:gp0_pll vid2_clk\n"); - printf("path 2:vid_pll vid1_clk\n"); - printf("path 3:gp0_pll vid1_clk\n"); - printf("you select path %d\n", s_enci_clk_path); - } else { - printf("invalid value, only 0/1/2/3\n"); - printf("bit[0]: 0=vid_pll, 1=gp0_pll\n"); - printf("bit[1]: 0=vid2_clk, 1=vid1_clk\n"); - } - } else - printf("only support G12A chip"); - } - - return 0; - -fail_cmd: - return 1; -} - -/*----------------------------------------------------------------------------*/ -// configuration for clock -#define WAIT_FOR_PLL_LOCKED(reg) \ - do { \ - unsigned int pll_lock; \ - unsigned int time_out = 0; \ - do { \ - udelay(20); \ - pll_lock = cvbs_get_hiu_bits(reg, 31, 1); \ - time_out ++; \ - } while ((pll_lock == 0) && (time_out < 10000)); \ - if (pll_lock == 0) \ - printf("[error]: cvbs pll lock failed\n"); \ - } while(0); - -static void cvbs_config_hdmipll_gxl(void) -{ -#if (defined(AML_MESON_GXL)) - printf("%s\n", __func__); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL, 0x4000027b); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL1, 0x800cb300); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL2, 0xa6212844); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL3, 0x0c4d000c); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL4, 0x001fa729); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL5, 0x01a31500); - cvbs_set_hiu_bits(HHI_HDMI_PLL_CNTL, 0x1, 28, 1); - cvbs_set_hiu_bits(HHI_HDMI_PLL_CNTL, 0x0, 28, 1); - WAIT_FOR_PLL_LOCKED(HHI_HDMI_PLL_CNTL); -#endif - return; -} - -static void cvbs_config_hdmipll_g12a(void) -{ - printf("%s\n", __func__); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x1a0504f7); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL1, 0x00010000); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL2, 0x00000000); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL3, 0x6a28dc00); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL4, 0x65771290); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL5, 0x39272000); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL6, 0x56540000); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x3a0504f7); - udelay(100); - cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x1a0504f7); - WAIT_FOR_PLL_LOCKED(HHI_HDMI_PLL_CNTL0); - return; -} - -static void cvbs_config_gp0pll_g12a(void) -{ - printf("%s\n", __func__); - cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x180204f7); - cvbs_write_hiu(HHI_GP0_PLL_CNTL1, 0x00010000); - cvbs_write_hiu(HHI_GP0_PLL_CNTL2, 0x00000000); - cvbs_write_hiu(HHI_GP0_PLL_CNTL3, 0x6a28dc00); - cvbs_write_hiu(HHI_GP0_PLL_CNTL4, 0x65771290); - cvbs_write_hiu(HHI_GP0_PLL_CNTL5, 0x39272000); - cvbs_write_hiu(HHI_GP0_PLL_CNTL6, 0x56540000); - cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x380204f7); - udelay(100); - cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x180204f7); - WAIT_FOR_PLL_LOCKED(HHI_GP0_PLL_CNTL0); - return; -} - -static void cvbs_set_vid1_clk(unsigned int src_pll) -{ - int sel = 0; - - printf("%s\n", __func__); - if (src_pll == 0) { /* hpll */ - /* divider: 1 */ - /* Disable the div output clock */ - cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 0, 19, 1); - cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 0, 15, 1); - - cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 1, 18, 1); - /* Enable the final output clock */ - cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 1, 19, 1); - sel = 0; - } else { /* gp0_pll */ - sel = 1; - } - - /* xd: 55 */ - /* setup the XD divider value */ - cvbs_set_hiu_bits(HHI_VID_CLK_DIV, (55 - 1), VCLK_XD0, 8); - //udelay(5); - /*0x59[16]/0x5f[19]/0x5f[20]*/ - cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, sel, VCLK_CLK_IN_SEL, 3); - cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, 1, VCLK_EN0, 1); - //udelay(2); - - /* vclk: 27M */ - /* [31:28]=0 enci_clk_sel, select vclk_div1 */ - cvbs_set_hiu_bits(HHI_VID_CLK_DIV, 0, 28, 4); - cvbs_set_hiu_bits(HHI_VIID_CLK_DIV, 0, 28, 4); - /* release vclk_div_reset and enable vclk_div */ - cvbs_set_hiu_bits(HHI_VID_CLK_DIV, 1, VCLK_XD_EN, 2); - //udelay(5); - - cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, 1, VCLK_DIV1_EN, 1); - - cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, 1, VCLK_SOFT_RST, 1); - //udelay(10); - cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, 0, VCLK_SOFT_RST, 1); - //udelay(5); -} - -static void cvbs_set_vid2_clk(unsigned int src_pll) -{ - int sel = 0; - - printf("%s\n", __func__); - if (src_pll == 0) { /* hpll */ - /* divider: 1 */ - /* Disable the div output clock */ - cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 0, 19, 1); - cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 0, 15, 1); - - cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 1, 18, 1); - /* Enable the final output clock */ - cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 1, 19, 1); - sel = 0; - } else { /* gp0_pll */ - sel = 1; - } - - /* xd: 55 */ - /* setup the XD divider value */ - cvbs_set_hiu_bits(HHI_VIID_CLK_DIV, (55 - 1), VCLK2_XD, 8); - //udelay(5); - /* Bit[18:16] - v2_cntl_clk_in_sel: vid_pll */ - cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, sel, VCLK2_CLK_IN_SEL, 3); - cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, 1, VCLK2_EN, 1); - //udelay(2); - - /* vclk: 27M */ - /* [31:28]=8 enci_clk_sel, select vclk2_div1 */ - cvbs_set_hiu_bits(HHI_VID_CLK_DIV, 8, 28, 4); - cvbs_set_hiu_bits(HHI_VIID_CLK_DIV, 8, 28, 4); - /* release vclk2_div_reset and enable vclk2_div */ - cvbs_set_hiu_bits(HHI_VIID_CLK_DIV, 1, VCLK2_XD_EN, 2); - //udelay(5); - - cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, 1, VCLK2_DIV1_EN, 1); - cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, 1, VCLK2_SOFT_RST, 1); - //udelay(10); - cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, 0, VCLK2_SOFT_RST, 1); - //udelay(5); -} - -static int cvbs_config_clock(void) -{ - /* pll output 1485M */ - if (check_cpu_type(MESON_CPU_MAJOR_ID_G12A) || - check_cpu_type(MESON_CPU_MAJOR_ID_G12B)) { - if (s_enci_clk_path & 0x1) - cvbs_config_gp0pll_g12a(); - else - cvbs_config_hdmipll_g12a(); - } - else if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_GXL)) - cvbs_config_hdmipll_gxl(); - - if (check_cpu_type(MESON_CPU_MAJOR_ID_G12A) || - check_cpu_type(MESON_CPU_MAJOR_ID_G12B)) { - if (s_enci_clk_path & 0x2) - cvbs_set_vid1_clk(s_enci_clk_path & 0x1); - else - cvbs_set_vid2_clk(s_enci_clk_path & 0x1); - } else { - cvbs_set_vid2_clk(0); - } - - cvbs_set_hiu_bits(HHI_VID_CLK_CNTL2, 1, 0, 1); - cvbs_set_hiu_bits(HHI_VID_CLK_CNTL2, 1, 4, 1); - - return 0; -} - -/*----------------------------------------------------------------------------*/ -// configuration for enci -static void cvbs_write_vcbus_array(struct reg_s *s) -{ - if (s == NULL) - return ; - - while (s && (MREG_END_MARKER != s->reg)) - { - cvbs_write_vcbus(s->reg, s->val); - //printf("reg[0x%.2x] = 0x%.4x\n", s->reg, s->val); - s ++; - } - return ; -} - -#ifdef AML_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT - -void cvbs_performance_config(void) -{ - int actived = AML_CVBS_PERFORMANCE_ACTIVED; - char buf[32]; - - sprintf(buf, "setenv cvbs_drv %d", actived); - run_command(buf, 0); - - return ; -} - -static void cvbs_performance_enhancement(int mode) -{ - unsigned int index = AML_CVBS_PERFORMANCE_ACTIVED; - unsigned int max = 0; - unsigned int type = 0; - const struct reg_s *s = NULL; - - if (VMODE_PAL != mode && VMODE_PAL_M != mode && VMODE_PAL_N != mode) - return; - - if (0xff == index) - return; - - if (check_cpu_type(MESON_CPU_MAJOR_ID_M8B)) { - max = sizeof(tvregs_576cvbs_performance_m8b) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_m8b[index]; - type = 1; - } else if (check_cpu_type(MESON_CPU_MAJOR_ID_M8M2)) { - max = sizeof(tvregs_576cvbs_performance_m8m2) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_m8m2[index]; - type = 2; - } else if (check_cpu_type(MESON_CPU_MAJOR_ID_M8)) { - max = sizeof(tvregs_576cvbs_performance_m8) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_m8[index]; - type = 3; - } else if (check_cpu_type(MESON_CPU_MAJOR_ID_GXBB)) { - max = sizeof(tvregs_576cvbs_performance_gxbb) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_gxbb[index]; - type = 4; - } else if (check_cpu_type(MESON_CPU_MAJOR_ID_GXTVBB)) { - max = sizeof(tvregs_576cvbs_performance_gxtvbb) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_gxtvbb[index]; - type = 5; - } else if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) { - max = sizeof(tvregs_576cvbs_performance_g12a) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_g12a[index]; - type = 9; - } else if (is_meson_gxlx_cpu()) { - max = sizeof(tvregs_576cvbs_performance_905l) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_905l[index]; - type = 7; - } else if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_TXL)) { - max = sizeof(tvregs_576cvbs_performance_txl) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_txl[index]; - type = 8; - } else if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_GXL)) { - if (is_meson_gxl_package_905L()) { - max = sizeof(tvregs_576cvbs_performance_905l) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_905l[index]; - type = 7; - } else { - max = sizeof(tvregs_576cvbs_performance_905x) - / sizeof(struct reg_s *); - index = (index >= max) ? 0 : index; - s = tvregs_576cvbs_performance_905x[index]; - type = 6; - } - } - - printf("cvbs performance type = %d, table = %d\n", type, index); - cvbs_write_vcbus_array((struct reg_s*)s); - - return; -} - -#endif - -static int cvbs_config_enci(int vmode) -{ - if (VMODE_PAL == vmode) - cvbs_write_vcbus_array((struct reg_s*)&tvregs_576cvbs_enc[0]); - else if (VMODE_NTSC == vmode) - cvbs_write_vcbus_array((struct reg_s*)&tvregs_480cvbs_enc[0]); - else if (VMODE_NTSC_M == vmode) - cvbs_write_vcbus_array((struct reg_s*)&tvregs_480cvbs_enc[0]); - else if (VMODE_PAL_M == vmode) - cvbs_write_vcbus_array((struct reg_s*)&tvregs_pal_m_enc[0]); - else if (VMODE_PAL_N == vmode) - cvbs_write_vcbus_array((struct reg_s*)&tvregs_pal_n_enc[0]); - - cvbs_performance_enhancement(vmode); - - return 0; -} - -/*----------------------------------------------------------------------------*/ -// configuration for output -// output vmode: 576cvbs, 480cvbs -int cvbs_set_vmode(char* vmode_name) -{ - if (!strncmp(vmode_name, "576cvbs", strlen("576cvbs"))) { - cvbs_mode = VMODE_PAL; - cvbs_config_enci(0); - cvbs_config_clock(); - cvbs_set_vdac(1); - return 0; - } else if (!strncmp(vmode_name, "480cvbs", strlen("480cvbs"))) { - cvbs_mode = VMODE_NTSC; - cvbs_config_enci(1); - cvbs_config_clock(); - cvbs_set_vdac(1); - return 0; - } else if (!strncmp(vmode_name, "ntsc_m", strlen("ntsc_m"))) { - cvbs_mode = VMODE_NTSC_M; - cvbs_config_enci(VMODE_NTSC_M); - cvbs_config_clock(); - cvbs_set_vdac(1); - return 0; - } else if (!strncmp(vmode_name, "pal_m", strlen("pal_m"))) { - cvbs_mode = VMODE_PAL_M; - cvbs_config_enci(VMODE_PAL_M); - cvbs_config_clock(); - cvbs_set_vdac(1); - return 0; - } else if (!strncmp(vmode_name, "pal_n", strlen("pal_n"))) { - cvbs_mode = VMODE_PAL_N; - cvbs_config_enci(VMODE_PAL_N); - cvbs_config_clock(); - cvbs_set_vdac(1); - return 0; - } else { - printf("[%s] is invalid for cvbs.\n", vmode_name); - return -1; - } - - return 0; -} - -/*----------------------------------------------------------------------------*/ -// check for valid video mode -int cvbs_outputmode_check(char *vmode_name) -{ - if ((!strncmp(vmode_name, "576cvbs", strlen("576cvbs"))) || - (!strncmp(vmode_name, "480cvbs", strlen("480cvbs"))) || - (!strncmp(vmode_name, "ntsc_m", strlen("ntsc_m"))) || - (!strncmp(vmode_name, "pal_m", strlen("pal_m"))) || - (!strncmp(vmode_name, "pal_n", strlen("pal_n")))) { - return 0; - } - - printf("cvbs: outputmode[%s] is invalid\n", vmode_name); - return -1; -} - -/*----------------------------------------------------------------------------*/ -// list for valid video mode -void cvbs_show_valid_vmode(void) -{ - printf("576cvbs\n""480cvbs\n""ntsc_m\n""pal_m\n""pal_n\n"); - return; -} - -void cvbs_init(void) -{ -#ifdef AML_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT - cvbs_performance_config(); -#endif - - return; -} -
diff --git a/drivers/amlogic/media/vout/cvbs/aml_cvbs_config.h b/drivers/amlogic/media/vout/cvbs/aml_cvbs_config.h deleted file mode 100644 index c22dc7c..0000000 --- a/drivers/amlogic/media/vout/cvbs/aml_cvbs_config.h +++ /dev/null
@@ -1,493 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -struct reg_s { - unsigned int reg; - unsigned int val; -}; - -#define MREG_END_MARKER 0xFFFF - -#ifdef AML_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT -static const struct reg_s tvregs_576cvbs_china_sarft_m8[] = { - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_m8[] = { - {ENCI_SYNC_ADJ, 0x8060 }, - {ENCI_VIDEO_SAT, 0xfe }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_m8[] = { - {ENCI_SYNC_ADJ, 0x8060 }, - {ENCI_VIDEO_SAT, 0xfe }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_m8[] = { - tvregs_576cvbs_china_sarft_m8, - tvregs_576cvbs_china_telecom_m8, - tvregs_576cvbs_china_mobile_m8 -}; - -static const struct reg_s tvregs_576cvbs_china_sarft_m8m2[] = { - {ENCI_YC_DELAY, 0x343 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_m8m2[] = { - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_m8m2[] = { - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_m8m2[] = { - tvregs_576cvbs_china_sarft_m8m2, - tvregs_576cvbs_china_telecom_m8m2, - tvregs_576cvbs_china_mobile_m8m2 -}; - -static const struct reg_s tvregs_576cvbs_china_sarft_m8b[] = { - {ENCI_YC_DELAY, 0x343 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_m8b[] = { - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_m8b[] = { - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_m8b[] = { - tvregs_576cvbs_china_sarft_m8b, - tvregs_576cvbs_china_telecom_m8b, - tvregs_576cvbs_china_mobile_m8b -}; - -static const struct reg_s tvregs_576cvbs_china_sarft_gxbb[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x343}, - {ENCI_VIDEO_SAT, 0x9 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_gxbb[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_gxbb[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_gxbb[] = { - tvregs_576cvbs_china_sarft_gxbb, - tvregs_576cvbs_china_telecom_gxbb, - tvregs_576cvbs_china_mobile_gxbb -}; - -static const struct reg_s tvregs_576cvbs_china_sarft_gxtvbb[] = { - {ENCI_YC_DELAY, 0x333 }, - {ENCI_VIDEO_SAT, 0xfb }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xff42 }, - {ENCI_SYNC_ADJ, 0x8c00 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_gxtvbb[] = { - {ENCI_YC_DELAY, 0x333 }, - {ENCI_VIDEO_SAT, 0xfb }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xff42 }, - {ENCI_SYNC_ADJ, 0x8c00 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_gxtvbb[] = { - {ENCI_YC_DELAY, 0x333 }, - {ENCI_VIDEO_SAT, 0xfb }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xff42 }, - {ENCI_SYNC_ADJ, 0x8c00 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_gxtvbb[] = { - tvregs_576cvbs_china_sarft_gxtvbb, - tvregs_576cvbs_china_telecom_gxtvbb, - tvregs_576cvbs_china_mobile_gxtvbb -}; - -static const struct reg_s tvregs_576cvbs_china_sarft_905x[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x343}, - {ENCI_VIDEO_SAT, 0x9 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_905x[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf752 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_905x[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf752 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_905x[] = { - tvregs_576cvbs_china_sarft_905x, - tvregs_576cvbs_china_telecom_905x, - tvregs_576cvbs_china_mobile_905x -}; - -static const struct reg_s tvregs_576cvbs_china_sarft_905l[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x0 }, - {ENCI_VIDEO_SAT, 0x9 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_905l[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x333 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_905l[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x343 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_905l[] = { - tvregs_576cvbs_china_sarft_905l, - tvregs_576cvbs_china_telecom_905l, - tvregs_576cvbs_china_mobile_905l -}; - -static const struct reg_s tvregs_576cvbs_china_sarft_txl[] = { - {ENCI_YC_DELAY, 0x333 }, - {ENCI_VIDEO_SAT, 0xf4 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {ENCI_SYNC_ADJ, 0x8c00 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_txl[] = { - {ENCI_YC_DELAY, 0x333 }, - {ENCI_VIDEO_SAT, 0xf4 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {ENCI_SYNC_ADJ, 0x8c00 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_txl[] = { - {ENCI_YC_DELAY, 0x333 }, - {ENCI_VIDEO_SAT, 0xf4 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {ENCI_SYNC_ADJ, 0x8c00 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_txl[] = { - tvregs_576cvbs_china_sarft_txl, - tvregs_576cvbs_china_telecom_txl, - tvregs_576cvbs_china_mobile_txl -}; - -static const struct reg_s tvregs_576cvbs_china_sarft_g12a[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x333 }, - {ENCI_SYNC_ADJ, 0x0 }, - {ENCI_VIDEO_SAT, 0x9 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_telecom_g12a[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x333 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_g12a[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x333 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0xfd }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_576cvbs_china_mobile_g12a_revB[] = { - {VENC_VDAC_DAC0_GAINCTRL, 0x9 }, - {ENCI_YC_DELAY, 0x546 }, - {ENCI_SYNC_ADJ, 0x8080 }, - {ENCI_VIDEO_SAT, 0x9 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s *tvregs_576cvbs_performance_g12a[] = { - tvregs_576cvbs_china_sarft_g12a, - tvregs_576cvbs_china_telecom_g12a, - tvregs_576cvbs_china_mobile_g12a, - tvregs_576cvbs_china_mobile_g12a_revB -}; - -#endif - -static const struct reg_s tvregs_576cvbs_enc[] = { - {ENCI_CFILT_CTRL, 0x12, }, - {ENCI_CFILT_CTRL2, 0x12, }, - {VENC_DVI_SETTING, 0, }, - {ENCI_VIDEO_MODE, 0, }, - {ENCI_VIDEO_MODE_ADV, 0, }, - {ENCI_SYNC_HSO_BEGIN, 3, }, - {ENCI_SYNC_HSO_END, 129, }, - {ENCI_SYNC_VSO_EVNLN, 0x0003 }, - {ENCI_SYNC_VSO_ODDLN, 0x0104 }, - {ENCI_MACV_MAX_AMP, 0x8107 }, - {VENC_VIDEO_PROG_MODE, 0xff }, - {ENCI_VIDEO_MODE, 0x13 }, - {ENCI_VIDEO_MODE_ADV, 0x26, }, - {ENCI_VIDEO_SCH, 0x28, }, - {ENCI_SYNC_MODE, 0x07, }, - {ENCI_YC_DELAY, 0x333, }, - {ENCI_VFIFO2VD_PIXEL_START, 0x0fb }, - {ENCI_VFIFO2VD_PIXEL_END, 0x069b }, - {ENCI_VFIFO2VD_LINE_TOP_START, 0x0016 }, - {ENCI_VFIFO2VD_LINE_TOP_END, 0x0136 }, - {ENCI_VFIFO2VD_LINE_BOT_START, 0x0017 }, - {ENCI_VFIFO2VD_LINE_BOT_END, 0x0137 }, - {VENC_SYNC_ROUTE, 0, }, - {ENCI_DBG_PX_RST, 0, }, - {VENC_INTCTRL, 0x2, }, - {ENCI_VFIFO2VD_CTL, 0x4e01, }, - {VENC_VDAC_SETTING, 0, }, - {VENC_UPSAMPLE_CTRL0, 0x0061, }, - {VENC_UPSAMPLE_CTRL1, 0x4061, }, - {VENC_UPSAMPLE_CTRL2, 0x5061, }, - {VENC_VDAC_DACSEL0, 0x0000, }, - {VENC_VDAC_DACSEL1, 0x0000, }, - {VENC_VDAC_DACSEL2, 0x0000, }, - {VENC_VDAC_DACSEL3, 0x0000, }, - {VENC_VDAC_DACSEL4, 0x0000, }, - {VENC_VDAC_DACSEL5, 0x0000, }, - {VPU_VIU_VENC_MUX_CTRL, 0x0005, }, - {VENC_VDAC_FIFO_CTRL, 0x2000, }, - {ENCI_DACSEL_0, 0x0011 }, - {ENCI_DACSEL_1, 0x11 }, - {ENCI_VIDEO_EN, 1, }, - {ENCI_VIDEO_SAT, 0x7 }, - {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {ENCI_MACV_N0, 0x0 }, - {ENCI_VIDEO_CONT, 0x0 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_480cvbs_enc[] = { - {ENCI_CFILT_CTRL, 0x12, }, - {ENCI_CFILT_CTRL2, 0x12, }, - {VENC_DVI_SETTING, 0, }, - {ENCI_VIDEO_MODE, 0, }, - {ENCI_VIDEO_MODE_ADV, 0, }, - {ENCI_SYNC_HSO_BEGIN, 5, }, - {ENCI_SYNC_HSO_END, 129, }, - {ENCI_SYNC_VSO_EVNLN, 0x0003 }, - {ENCI_SYNC_VSO_ODDLN, 0x0104 }, - {ENCI_MACV_MAX_AMP, 0x810b }, - {VENC_VIDEO_PROG_MODE, 0xf0 }, - {ENCI_VIDEO_MODE, 0x08 }, - {ENCI_VIDEO_MODE_ADV, 0x26, }, - {ENCI_VIDEO_SCH, 0x20, }, - {ENCI_SYNC_MODE, 0x07, }, - {ENCI_YC_DELAY, 0x333, }, - {ENCI_VFIFO2VD_PIXEL_START, 0xe3, }, - {ENCI_VFIFO2VD_PIXEL_END, 0x0683, }, - {ENCI_VFIFO2VD_LINE_TOP_START, 0x12, }, - {ENCI_VFIFO2VD_LINE_TOP_END, 0x102, }, - {ENCI_VFIFO2VD_LINE_BOT_START, 0x13, }, - {ENCI_VFIFO2VD_LINE_BOT_END, 0x103, }, - {VENC_SYNC_ROUTE, 0, }, - {ENCI_DBG_PX_RST, 0, }, - {VENC_INTCTRL, 0x2, }, - {ENCI_VFIFO2VD_CTL, 0x4e01, }, - {VENC_VDAC_SETTING, 0, }, - {VENC_UPSAMPLE_CTRL0, 0x0061, }, - {VENC_UPSAMPLE_CTRL1, 0x4061, }, - {VENC_UPSAMPLE_CTRL2, 0x5061, }, - {VENC_VDAC_DACSEL0, 0x0000, }, - {VENC_VDAC_DACSEL1, 0x0000, }, - {VENC_VDAC_DACSEL2, 0x0000, }, - {VENC_VDAC_DACSEL3, 0x0000, }, - {VENC_VDAC_DACSEL4, 0x0000, }, - {VENC_VDAC_DACSEL5, 0x0000, }, - {VPU_VIU_VENC_MUX_CTRL, 0x0005, }, - {VENC_VDAC_FIFO_CTRL, 0x2000, }, - {ENCI_DACSEL_0, 0x0011 }, - {ENCI_DACSEL_1, 0x11 }, - {ENCI_VIDEO_EN, 1, }, - {ENCI_VIDEO_SAT, 0x12 }, - {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {ENCI_MACV_N0, 0x0 }, - {ENCI_SYNC_ADJ, 0x9c00 }, - {ENCI_VIDEO_CONT, 0x3 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_pal_m_enc[] = { - {ENCI_CFILT_CTRL, 0x12, }, - {ENCI_CFILT_CTRL2, 0x12, }, - {VENC_DVI_SETTING, 0, }, - {ENCI_VIDEO_MODE, 0, }, - {ENCI_VIDEO_MODE_ADV, 0, }, - {ENCI_SYNC_HSO_BEGIN, 5, }, - {ENCI_SYNC_HSO_END, 129, }, - {ENCI_SYNC_VSO_EVNLN, 0x0003 }, - {ENCI_SYNC_VSO_ODDLN, 0x0104 }, - {ENCI_MACV_MAX_AMP, 0x810b }, - {VENC_VIDEO_PROG_MODE, 0xf0 }, - {ENCI_VIDEO_MODE, 0x2a }, - {ENCI_VIDEO_MODE_ADV, 0x26, }, - {ENCI_VIDEO_SCH, 0x20, }, - {ENCI_SYNC_MODE, 0x07, }, - {ENCI_YC_DELAY, 0x333, }, - {ENCI_VFIFO2VD_PIXEL_START, 0xe3, }, - {ENCI_VFIFO2VD_PIXEL_END, 0x0683,}, - {ENCI_VFIFO2VD_LINE_TOP_START, 0x12, }, - {ENCI_VFIFO2VD_LINE_TOP_END, 0x102, }, - {ENCI_VFIFO2VD_LINE_BOT_START, 0x13, }, - {ENCI_VFIFO2VD_LINE_BOT_END, 0x103, }, - {VENC_SYNC_ROUTE, 0, }, - {ENCI_DBG_PX_RST, 0, }, - {VENC_INTCTRL, 0x2, }, - {ENCI_VFIFO2VD_CTL, 0x4e01,}, - {VENC_VDAC_SETTING, 0, }, - {VENC_UPSAMPLE_CTRL0, 0x0061,}, - {VENC_UPSAMPLE_CTRL1, 0x4061,}, - {VENC_UPSAMPLE_CTRL2, 0x5061,}, - {VENC_VDAC_DACSEL0, 0x0000,}, - {VENC_VDAC_DACSEL1, 0x0000,}, - {VENC_VDAC_DACSEL2, 0x0000,}, - {VENC_VDAC_DACSEL3, 0x0000,}, - {VENC_VDAC_DACSEL4, 0x0000,}, - {VENC_VDAC_DACSEL5, 0x0000,}, - {VPU_VIU_VENC_MUX_CTRL, 0x0005,}, - {VENC_VDAC_FIFO_CTRL, 0x2000,}, - {ENCI_DACSEL_0, 0x0011 }, - {ENCI_DACSEL_1, 0x11 }, - {ENCI_VIDEO_EN, 1, }, - {ENCI_VIDEO_SAT, 0x12 }, - {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {ENCI_MACV_N0, 0x0 }, - {ENCI_SYNC_ADJ, 0x9c00 }, - {ENCI_VIDEO_CONT, 0x3 }, - {MREG_END_MARKER, 0 } -}; - -static const struct reg_s tvregs_pal_n_enc[] = { - {ENCI_CFILT_CTRL, 0x12, }, - {ENCI_CFILT_CTRL2, 0x12, }, - {VENC_DVI_SETTING, 0, }, - {ENCI_VIDEO_MODE, 0, }, - {ENCI_VIDEO_MODE_ADV, 0, }, - {ENCI_SYNC_HSO_BEGIN, 3, }, - {ENCI_SYNC_HSO_END, 129, }, - {ENCI_SYNC_VSO_EVNLN, 0x0003 }, - {ENCI_SYNC_VSO_ODDLN, 0x0104 }, - {ENCI_MACV_MAX_AMP, 0x8107 }, - {VENC_VIDEO_PROG_MODE, 0xff }, - {ENCI_VIDEO_MODE, 0x3b }, - {ENCI_VIDEO_MODE_ADV, 0x26, }, - {ENCI_VIDEO_SCH, 0x28, }, - {ENCI_SYNC_MODE, 0x07, }, - {ENCI_YC_DELAY, 0x333, }, - {ENCI_VFIFO2VD_PIXEL_START, 0x0fb }, - {ENCI_VFIFO2VD_PIXEL_END, 0x069b }, - {ENCI_VFIFO2VD_LINE_TOP_START, 0x0016 }, - {ENCI_VFIFO2VD_LINE_TOP_END, 0x0136 }, - {ENCI_VFIFO2VD_LINE_BOT_START, 0x0017 }, - {ENCI_VFIFO2VD_LINE_BOT_END, 0x0137 }, - {VENC_SYNC_ROUTE, 0, }, - {ENCI_DBG_PX_RST, 0, }, - {VENC_INTCTRL, 0x2, }, - {ENCI_VFIFO2VD_CTL, 0x4e01, }, - {VENC_VDAC_SETTING, 0, }, - {VENC_UPSAMPLE_CTRL0, 0x0061, }, - {VENC_UPSAMPLE_CTRL1, 0x4061, }, - {VENC_UPSAMPLE_CTRL2, 0x5061, }, - {VENC_VDAC_DACSEL0, 0x0000, }, - {VENC_VDAC_DACSEL1, 0x0000, }, - {VENC_VDAC_DACSEL2, 0x0000, }, - {VENC_VDAC_DACSEL3, 0x0000, }, - {VENC_VDAC_DACSEL4, 0x0000, }, - {VENC_VDAC_DACSEL5, 0x0000, }, - {VPU_VIU_VENC_MUX_CTRL, 0x0005, }, - {VENC_VDAC_FIFO_CTRL, 0x2000, }, - {ENCI_DACSEL_0, 0x0011 }, - {ENCI_DACSEL_1, 0x11 }, - {ENCI_VIDEO_EN, 1, }, - {ENCI_VIDEO_SAT, 0x7 }, - {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 }, - {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, - {ENCI_MACV_N0, 0x0 }, - {ENCI_VIDEO_CONT, 0x0 }, - {MREG_END_MARKER, 0 } -}; -
diff --git a/drivers/amlogic/media/vout/cvbs/aml_cvbs_regs.h b/drivers/amlogic/media/vout/cvbs/aml_cvbs_regs.h deleted file mode 100644 index 19f3882..0000000 --- a/drivers/amlogic/media/vout/cvbs/aml_cvbs_regs.h +++ /dev/null
@@ -1,238 +0,0 @@ -/* - * drivers/display/vout/aml_cvbs_regs.h - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * -*/ - -/*-------------------------------------------------------------------------------*/ -// hiu registers - -/*-------------------------------------------------------------------------------*/ -// encoder registers -#define BUS_TYPE_CBUS 0 -#define BUS_TYPE_HIU 1 -#define BUS_TYPE_VCBUS 2 -#if 0/*defined in secure_apb.h*/ -#define MESON_CPU_MAJOR_ID_M6 0x16 -#define MESON_CPU_MAJOR_ID_M6TV 0x17 -#define MESON_CPU_MAJOR_ID_M6TVL 0x18 -#define MESON_CPU_MAJOR_ID_M8 0x19 -#define MESON_CPU_MAJOR_ID_MTVD 0x1A -#define MESON_CPU_MAJOR_ID_M8B 0x1B -#define MESON_CPU_MAJOR_ID_MG9TV 0x1C -#define MESON_CPU_MAJOR_ID_M8M2 0x1D -#define MESON_CPU_MAJOR_ID_GXBB 0x1F -#define MESON_CPU_MAJOR_ID_GXTVBB 0x20 -#define MESON_CPU_MAJOR_ID_GXL 0x21 -#define MESON_CPU_MAJOR_ID_GXM 0x22 -#define MESON_CPU_MAJOR_ID_TXL 0x23 -#define MESON_CPU_MAJOR_ID_TXLX 0x24 - -#define ASSIST_HW_REV 0x1f53 -#endif - -#define DAC0_CLK_SEL 28 -#define DAC1_CLK_SEL 24 -#define DAC2_CLK_SEL 20 -#define VCLK2_XD_RST 17 -#define VCLK2_XD_EN 16 -#define ENCL_CLK_SEL 12 -#define VCLK2_XD 0 -#define VCLK_XD0 0 -#define VCLK_CLK_IN_SEL 16 -#define VCLK_EN0 19 -#define VCLK_XD_EN 16 -#define VCLK_DIV1_EN 0 -#define VCLK_SOFT_RST 15 - -#define VCLK2_EN 19 -#define VCLK2_CLK_IN_SEL 16 -#define VCLK2_SOFT_RST 15 -#define VCLK2_DIV12_EN 4 -#define VCLK2_DIV6_EN 3 -#define VCLK2_DIV4_EN 2 -#define VCLK2_DIV2_EN 1 -#define VCLK2_DIV1_EN 0 -#if 0/*defined in secure_apb.h*/ -#define ENCI_VIDEO_MODE 0x1b00 -#define ENCI_VIDEO_MODE_ADV 0x1b01 -#define ENCI_VIDEO_FSC_ADJ 0x1b02 -#define ENCI_VIDEO_BRIGHT 0x1b03 -#define ENCI_VIDEO_CONT 0x1b04 -#define ENCI_VIDEO_SAT 0x1b05 -#define ENCI_VIDEO_HUE 0x1b06 -#define ENCI_VIDEO_SCH 0x1b07 -#define ENCI_SYNC_MODE 0x1b08 -#define ENCI_SYNC_CTRL 0x1b09 -#define ENCI_SYNC_HSO_BEGIN 0x1b0a -#define ENCI_SYNC_HSO_END 0x1b0b -#define ENCI_SYNC_VSO_EVN 0x1b0c -#define ENCI_SYNC_VSO_ODD 0x1b0d -#define ENCI_SYNC_VSO_EVNLN 0x1b0e -#define ENCI_SYNC_VSO_ODDLN 0x1b0f -#define ENCI_SYNC_HOFFST 0x1b10 -#define ENCI_SYNC_VOFFST 0x1b11 -#define ENCI_SYNC_ADJ 0x1b12 -#define ENCI_RGB_SETTING 0x1b13 - -#define ENCI_DE_H_BEGIN 0x1b16 -#define ENCI_DE_H_END 0x1b17 -#define ENCI_DE_V_BEGIN_EVEN 0x1b18 -#define ENCI_DE_V_END_EVEN 0x1b19 -#define ENCI_DE_V_BEGIN_ODD 0x1b1a -#define ENCI_DE_V_END_ODD 0x1b1b -#define ENCI_VBI_SETTING 0x1b20 -#define ENCI_VBI_CCDT_EVN 0x1b21 -#define ENCI_VBI_CCDT_ODD 0x1b22 -#define ENCI_VBI_CC525_LN 0x1b23 -#define ENCI_VBI_CC625_LN 0x1b24 -#define ENCI_VBI_WSSDT 0x1b25 -#define ENCI_VBI_WSS_LN 0x1b26 -#define ENCI_VBI_CGMSDT_L 0x1b27 -#define ENCI_VBI_CGMSDT_H 0x1b28 -#define ENCI_VBI_CGMS_LN 0x1b29 -#define ENCI_VBI_TTX_HTIME 0x1b2a -#define ENCI_VBI_TTX_LN 0x1b2b -#define ENCI_VBI_TTXDT0 0x1b2c -#define ENCI_VBI_TTXDT1 0x1b2d -#define ENCI_VBI_TTXDT2 0x1b2e -#define ENCI_VBI_TTXDT3 0x1b2f -#define ENCI_MACV_N0 0x1b30 -#define ENCI_MACV_N1 0x1b31 -#define ENCI_MACV_N2 0x1b32 -#define ENCI_MACV_N3 0x1b33 -#define ENCI_MACV_N4 0x1b34 -#define ENCI_MACV_N5 0x1b35 -#define ENCI_MACV_N6 0x1b36 -#define ENCI_MACV_N7 0x1b37 -#define ENCI_MACV_N8 0x1b38 -#define ENCI_MACV_N9 0x1b39 -#define ENCI_MACV_N10 0x1b3a -#define ENCI_MACV_N11 0x1b3b -#define ENCI_MACV_N12 0x1b3c -#define ENCI_MACV_N13 0x1b3d -#define ENCI_MACV_N14 0x1b3e -#define ENCI_MACV_N15 0x1b3f -#define ENCI_MACV_N16 0x1b40 -#define ENCI_MACV_N17 0x1b41 -#define ENCI_MACV_N18 0x1b42 -#define ENCI_MACV_N19 0x1b43 -#define ENCI_MACV_N20 0x1b44 -#define ENCI_MACV_N21 0x1b45 -#define ENCI_MACV_N22 0x1b46 - -#define ENCI_DBG_PX_RST 0x1b48 -#define ENCI_DBG_FLDLN_RST 0x1b49 -#define ENCI_DBG_PX_INT 0x1b4a -#define ENCI_DBG_FLDLN_INT 0x1b4b -#define ENCI_DBG_MAXPX 0x1b4c -#define ENCI_DBG_MAXLN 0x1b4d -#define ENCI_MACV_MAX_AMP 0x1b50 -#define ENCI_MACV_PULSE_LO 0x1b51 -#define ENCI_MACV_PULSE_HI 0x1b52 -#define ENCI_MACV_BKP_MAX 0x1b53 -#define ENCI_CFILT_CTRL 0x1b54 -#define ENCI_CFILT7 0x1b55 -#define ENCI_YC_DELAY 0x1b56 -#define ENCI_VIDEO_EN 0x1b57 - -#define ENCI_DVI_HSO_BEGIN 0x1c00 -#define ENCI_DVI_HSO_END 0x1c01 -#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 -#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 -#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 -#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 -#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 -#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 -#define ENCI_DVI_VSO_END_EVN 0x1c08 -#define ENCI_DVI_VSO_END_ODD 0x1c09 - -#define ENCI_CFILT_CTRL2 0x1c0a -#define ENCI_DACSEL_0 0x1c0b -#define ENCI_DACSEL_1 0x1c0c -#define ENCI_TST_EN 0x1c10 -#define ENCI_TST_MDSEL 0x1c11 -#define ENCI_TST_Y 0x1c12 -#define ENCI_TST_CB 0x1c13 -#define ENCI_TST_CR 0x1c14 -#define ENCI_TST_CLRBAR_STRT 0x1c15 -#define ENCI_TST_CLRBAR_WIDTH 0x1c16 -#define ENCI_TST_VDCNT_STSET 0x1c17 - -#define ENCI_VFIFO2VD_CTL 0x1c18 -#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 -#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a -#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b -#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c -#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d -#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e -#define ENCI_VFIFO2VD_CTL2 0x1c1f - -#define ENCI_SYNC_LINE_LENGTH 0x1c40 -#define ENCI_SYNC_PIXEL_EN 0x1c41 -#define ENCI_SYNC_TO_LINE_EN 0x1c42 -#define ENCI_SYNC_TO_PIXEL 0x1c43 - -#define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54 -#define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55 -#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 -#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57 - -#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 -#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 -#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a -#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b -#define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c -#define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d -#define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e -#define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f - - -#define VENC_SYNC_ROUTE 0x1b60 -#define VENC_VIDEO_EXSRC 0x1b61 -#define VENC_DVI_SETTING 0x1b62 -#define VENC_C656_CTRL 0x1b63 -#define VENC_UPSAMPLE_CTRL0 0x1b64 -#define VENC_UPSAMPLE_CTRL1 0x1b65 -#define VENC_UPSAMPLE_CTRL2 0x1b66 -#define VENC_VIDEO_PROG_MODE 0x1b68 - -#define VENC_INTCTRL 0x1b6e -#define VENC_INTFLAG 0x1b6f - -#define VENC_VDAC_DACSEL0 0x1b78 -#define VENC_VDAC_DACSEL1 0x1b79 -#define VENC_VDAC_DACSEL2 0x1b7a -#define VENC_VDAC_DACSEL3 0x1b7b -#define VENC_VDAC_DACSEL4 0x1b7c -#define VENC_VDAC_DACSEL5 0x1b7d -#define VENC_VDAC_SETTING 0x1b7e -#define VENC_VDAC_TST_VAL 0x1b7f -#define VENC_VDAC_DAC0_GAINCTRL 0x1bf0 -#define VENC_VDAC_DAC0_OFFSET 0x1bf1 -#define VENC_VDAC_DAC1_GAINCTRL 0x1bf2 -#define VENC_VDAC_DAC1_OFFSET 0x1bf3 -#define VENC_VDAC_DAC2_GAINCTRL 0x1bf4 -#define VENC_VDAC_DAC2_OFFSET 0x1bf5 -#define VENC_VDAC_DAC3_GAINCTRL 0x1bf6 -#define VENC_VDAC_DAC3_OFFSET 0x1bf7 -#define VENC_VDAC_DAC4_GAINCTRL 0x1bf8 -#define VENC_VDAC_DAC4_OFFSET 0x1bf9 -#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa -#define VENC_VDAC_DAC5_OFFSET 0x1bfb -#define VENC_VDAC_FIFO_CTRL 0x1bfc - -#define VPU_VIU_VENC_MUX_CTRL 0x271a -#endif -
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs.c b/drivers/amlogic/media/vout/cvbs/cvbs.c new file mode 100644 index 0000000..4d53962 --- /dev/null +++ b/drivers/amlogic/media/vout/cvbs/cvbs.c
@@ -0,0 +1,799 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <malloc.h> +#include <fdtdec.h> +#include <dm.h> +#include <asm/arch/cpu.h> +#include <amlogic/cpu_id.h> +#include <amlogic/media/vout/aml_cvbs.h> +#include "cvbs_reg.h" +#include "cvbs_config.h" +#include "cvbs.h" +#include "vdac.h" + +/*----------------------------------------------------------------------------*/ +static struct cvbs_drv_s cvbs_drv = { + .data = NULL, +}; + +static struct cvbs_data_s cvbs_data_g12a = { + .chip_type = CVBS_CHIP_G12A, + + .reg_vid_pll_clk_div = HHI_VID_PLL_CLK_DIV, + .reg_vid_clk_div = HHI_VID_CLK_DIV, + .reg_vid_clk_ctrl = HHI_VID_CLK_CNTL, + .reg_vid2_clk_div = HHI_VIID_CLK_DIV, + .reg_vid2_clk_ctrl = HHI_VIID_CLK_CNTL, + .reg_vid_clk_ctrl2 = HHI_VID_CLK_CNTL2, + + .vdac_vref_adj = 0x10, + .vdac_gsw = 0x0, +}; + +static struct cvbs_data_s cvbs_data_g12b = { + .chip_type = CVBS_CHIP_G12B, + + .reg_vid_pll_clk_div = HHI_VID_PLL_CLK_DIV, + .reg_vid_clk_div = HHI_VID_CLK_DIV, + .reg_vid_clk_ctrl = HHI_VID_CLK_CNTL, + .reg_vid2_clk_div = HHI_VIID_CLK_DIV, + .reg_vid2_clk_ctrl = HHI_VIID_CLK_CNTL, + .reg_vid_clk_ctrl2 = HHI_VID_CLK_CNTL2, + + .vdac_vref_adj = 0xf, + .vdac_gsw = 0x0, +}; + +static struct cvbs_data_s cvbs_data_sc2 = { + .chip_type = CVBS_CHIP_SC2, + + .reg_vid_pll_clk_div = CLKCTRL_VID_PLL_CLK_DIV, + .reg_vid_clk_div = CLKCTRL_VID_CLK_DIV, + .reg_vid_clk_ctrl = CLKCTRL_VID_CLK_CTRL, + .reg_vid2_clk_div = CLKCTRL_VIID_CLK_DIV, + .reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK_CTRL, + .reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK_CTRL2, + + .vdac_vref_adj = 0x10, + .vdac_gsw = 0x0, +}; + +unsigned int cvbs_mode = VMODE_MAX; +/*bit[0]: 0=vid_pll, 1=gp0_pll*/ +/*bit[1]: 0=vid2_clk, 1=vid1_clk*/ +/*path 0:vid_pll vid2_clk*/ +/*path 1:gp0_pll vid2_clk*/ +/*path 2:vid_pll vid1_clk*/ +/*path 3:gp0_pll vid1_clk*/ +static unsigned int s_enci_clk_path = 0; + +/*----------------------------------------------------------------------------*/ +// configuration for enci bist +int cvbs_set_bist(char* bist_mode) +{ + if (!strcmp(bist_mode, "off")) { + cvbs_write_vcbus(ENCI_VIDEO_MODE_ADV, 0x26); + cvbs_write_vcbus(ENCI_TST_EN, 0x0); + } else { + unsigned int mode = 0; + + if (!strcmp(bist_mode, "fixval") || !strcmp(bist_mode, "0")) + mode = 0; + else if (!strcmp(bist_mode, "colorbar") || !strcmp(bist_mode, "1")) + mode = 1; + else if (!strcmp(bist_mode, "thinline") || !strcmp(bist_mode, "2")) + mode = 2; + else if (!strcmp(bist_mode, "dotgrid") || !strcmp(bist_mode, "3")) + mode = 3; + + cvbs_write_vcbus(ENCI_VIDEO_MODE_ADV, 0x2); + cvbs_write_vcbus(ENCI_TST_MDSEL, mode); + cvbs_write_vcbus(ENCI_TST_CLRBAR_STRT, 0x112); + cvbs_write_vcbus(ENCI_TST_CLRBAR_WIDTH, 0xb4); + cvbs_write_vcbus(ENCI_TST_EN, 0x1); + } + + return 0; +} + +/*----------------------------------------------------------------------------*/ +int cvbs_set_vdac(int status) +{ + switch (status) { + case 0:// close vdac + if (cvbs_drv.data) + vdac_enable(0, VDAC_MODULE_CVBS_OUT); + else + printf("cvbs ERROR:need run cvbs init.\n"); + break; + case 1:// from enci to vdac + cvbs_set_vcbus_bits(VENC_VDAC_DACSEL0, 0, 5, 1); + if (cvbs_drv.data) { + vdac_ctrl_vref_adj(cvbs_drv.data->vdac_vref_adj); + vdac_ctrl_gsw_adj(cvbs_drv.data->vdac_gsw); + vdac_enable(1, VDAC_MODULE_CVBS_OUT); + } else { + printf("cvbs ERROR:need run cvbs init.\n"); + } + break; + default: + break; + } + + return 0; +} + +/*----------------------------------------------------------------------------*/ +// interface for debug +static void cvbs_dump_cvbs_regs(void) +{ + struct reg_s *p = NULL; + + if (VMODE_PAL == cvbs_mode) { + // 576cvbs + p = (struct reg_s*)&tvregs_576cvbs_enc[0]; + + } else if (VMODE_NTSC == cvbs_mode) { + // 480cvbs + p = (struct reg_s*)&tvregs_480cvbs_enc[0]; + } + + if (NULL == p) { + printf("it's not in cvbs mode!\n"); + return; + } + + if (MREG_END_MARKER != p->reg) + printf("cvbs enci registers:\n"); + while (MREG_END_MARKER != p->reg) { + printf(" vcbus[0x%.2x] = 0x%.4x\n", p->reg, cvbs_read_vcbus(p->reg)); + p ++; + } + + return; +} + +unsigned int cvbs_clk_regs[] = { + HHI_HDMI_PLL_CNTL0, + HHI_HDMI_PLL_CNTL1, + HHI_HDMI_PLL_CNTL2, + HHI_HDMI_PLL_CNTL3, + HHI_HDMI_PLL_CNTL4, + HHI_HDMI_PLL_CNTL5, + HHI_HDMI_PLL_CNTL6, + HHI_VID_PLL_CLK_DIV, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_DIV, + HHI_VID_CLK_CNTL2, + MREG_END_MARKER +}; + +static void cvbs_dump_clock_regs(void) +{ + unsigned int *p = &cvbs_clk_regs[0]; + + if (MREG_END_MARKER != *p) + printf("cvbs clock registers:\n"); + while (MREG_END_MARKER != *p) { + printf(" hiu[0x%.2x] = 0x%.4x\n", *p, cvbs_read_hiu(*p)); + p ++; + } + + return; +} + +int cvbs_reg_debug(int argc, char* const argv[]) +{ + unsigned int value; + + if (!cvbs_drv.data) { + printf("cvbs: error: %s: no cvbs data\n", __func__); + return -1; + } + + if (!strcmp(argv[1], "clock")) { + if (argc != 2) + goto fail_cmd; + + cvbs_dump_clock_regs(); + } else if (!strcmp(argv[1], "enci")) { + if (argc != 2) + goto fail_cmd; + + cvbs_dump_cvbs_regs(); + } else if (!strcmp(argv[1], "clkpath")) { + if (argc != 3) + goto fail_cmd; + value = simple_strtoul(argv[2], NULL, 0); + if ((cvbs_drv.data->chip_type = CVBS_CHIP_G12A) || + (cvbs_drv.data->chip_type = CVBS_CHIP_G12B)) { + if (value == 1 || value == 2 || + value == 3 || value == 0) { + s_enci_clk_path = value; + printf("path 0:vid_pll vid2_clk\n"); + printf("path 1:gp0_pll vid2_clk\n"); + printf("path 2:vid_pll vid1_clk\n"); + printf("path 3:gp0_pll vid1_clk\n"); + printf("you select path %d\n", s_enci_clk_path); + } else { + printf("invalid value, only 0/1/2/3\n"); + printf("bit[0]: 0=vid_pll, 1=gp0_pll\n"); + printf("bit[1]: 0=vid2_clk, 1=vid1_clk\n"); + } + } else + printf("only support G12A chip"); + } + + return 0; + +fail_cmd: + return 1; +} + +/*----------------------------------------------------------------------------*/ +// configuration for clock +#define WAIT_FOR_PLL_LOCKED(reg) \ + do { \ + unsigned int pll_lock; \ + unsigned int time_out = 0; \ + do { \ + udelay(20); \ + pll_lock = cvbs_get_hiu_bits(reg, 31, 1); \ + time_out ++; \ + } while ((pll_lock == 0) && (time_out < 10000)); \ + if (pll_lock == 0) \ + printf("[error]: cvbs pll lock failed\n"); \ + } while(0); + +static void cvbs_config_hdmipll_g12a(void) +{ + printf("%s\n", __func__); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x1a0504f7); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL1, 0x00010000); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL2, 0x00000000); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL3, 0x6a28dc00); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL4, 0x65771290); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL5, 0x39272000); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL6, 0x56540000); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x3a0504f7); + udelay(100); + cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x1a0504f7); + WAIT_FOR_PLL_LOCKED(HHI_HDMI_PLL_CNTL0); + return; +} + +static void cvbs_config_gp0pll_g12a(void) +{ + printf("%s\n", __func__); + cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x180204f7); + cvbs_write_hiu(HHI_GP0_PLL_CNTL1, 0x00010000); + cvbs_write_hiu(HHI_GP0_PLL_CNTL2, 0x00000000); + cvbs_write_hiu(HHI_GP0_PLL_CNTL3, 0x6a28dc00); + cvbs_write_hiu(HHI_GP0_PLL_CNTL4, 0x65771290); + cvbs_write_hiu(HHI_GP0_PLL_CNTL5, 0x39272000); + cvbs_write_hiu(HHI_GP0_PLL_CNTL6, 0x56540000); + cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x380204f7); + udelay(100); + cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x180204f7); + WAIT_FOR_PLL_LOCKED(HHI_GP0_PLL_CNTL0); + return; +} + +static void cvbs_config_hdmipll_sc2(void) +{ + printf("%s\n", __func__); + cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL0, 0x3b01047b); + cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL1, 0x00018000); + cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL2, 0x00000000); + cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL3, 0x0a691c00); + cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL4, 0x33771290); + cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL5, 0x39270000); + cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL6, 0x50540000); + udelay(100); + cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL0, 0x1b01047b); + WAIT_FOR_PLL_LOCKED(ANACTRL_HDMIPLL_CTRL0); +} + +static void cvbs_set_vid1_clk(unsigned int src_pll) +{ + int sel = 0; + + if (!cvbs_drv.data) { + printf("cvbs: error: %s: no cvbs data\n", __func__); + return; + } + + printf("%s\n", __func__); + if (src_pll == 0) { /* hpll */ + /* divider: 1 */ + /* Disable the div output clock */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 0, 19, 1); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 0, 15, 1); + + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 1, 18, 1); + /* Enable the final output clock */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 1, 19, 1); + sel = 0; + } else { /* gp0_pll */ + sel = 1; + } + + /* xd: 55 */ + /* setup the XD divider value */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_div, (55 - 1), VCLK_XD0, 8); + //udelay(5); + /*0x59[16]/0x5f[19]/0x5f[20]*/ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, sel, VCLK_CLK_IN_SEL, 3); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, 1, VCLK_EN0, 1); + //udelay(2); + + /* vclk: 27M */ + /* [31:28]=0 enci_clk_sel, select vclk_div1 */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_div, 0, 28, 4); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_div, 0, 28, 4); + /* release vclk_div_reset and enable vclk_div */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_div, 1, VCLK_XD_EN, 2); + //udelay(5); + + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, 1, VCLK_DIV1_EN, 1); + + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, 1, VCLK_SOFT_RST, 1); + //udelay(10); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, 0, VCLK_SOFT_RST, 1); + //udelay(5); +} + +static void cvbs_set_vid2_clk(unsigned int src_pll) +{ + int sel = 0; + + if (!cvbs_drv.data) { + printf("cvbs: error: %s: no cvbs data\n", __func__); + return; + } + + printf("%s\n", __func__); + if (src_pll == 0) { /* hpll */ + /* divider: 1 */ + /* Disable the div output clock */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 0, 19, 1); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 0, 15, 1); + + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 1, 18, 1); + /* Enable the final output clock */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 1, 19, 1); + sel = 0; + } else { /* gp0_pll */ + sel = 1; + } + + /* xd: 55 */ + /* setup the XD divider value */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_div, (55 - 1), VCLK2_XD, 8); + //udelay(5); + /* Bit[18:16] - v2_cntl_clk_in_sel: vid_pll */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, sel, VCLK2_CLK_IN_SEL, 3); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, 1, VCLK2_EN, 1); + //udelay(2); + + /* vclk: 27M */ + /* [31:28]=8 enci_clk_sel, select vclk2_div1 */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_div, 8, 28, 4); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_div, 8, 28, 4); + /* release vclk2_div_reset and enable vclk2_div */ + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_div, 1, VCLK2_XD_EN, 2); + //udelay(5); + + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, 1, VCLK2_DIV1_EN, 1); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, 1, VCLK2_SOFT_RST, 1); + //udelay(10); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, 0, VCLK2_SOFT_RST, 1); + //udelay(5); +} + +static int cvbs_config_clock(void) +{ + if (!cvbs_drv.data) { + printf("cvbs: error: %s: no cvbs data\n", __func__); + return -1; + } + + /* pll output 1485M */ + switch (cvbs_drv.data->chip_type) { + case CVBS_CHIP_G12A: + case CVBS_CHIP_G12B: + if (s_enci_clk_path & 0x1) + cvbs_config_gp0pll_g12a(); + else + cvbs_config_hdmipll_g12a(); + if (s_enci_clk_path & 0x2) + cvbs_set_vid1_clk(s_enci_clk_path & 0x1); + else + cvbs_set_vid2_clk(s_enci_clk_path & 0x1); + break; + case CVBS_CHIP_SC2: + cvbs_config_hdmipll_sc2(); + cvbs_set_vid2_clk(0); + break; + default: + printf("cvbs: %s: invalid chip type\n", __func__); + return -1; + } + + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl2, 1, 0, 1); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl2, 1, 4, 1); + + return 0; +} + +static void cvbs_disable_clock(void) +{ + if (!cvbs_drv.data) { + printf("cvbs: error: %s: no cvbs data\n", __func__); + return; + } + + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl2, 0, 4, 1); + cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl2, 0, 0, 1); +} + +/*----------------------------------------------------------------------------*/ +// configuration for enci +static void cvbs_performance_enhancement(int mode) +{ + const struct reg_s *s = NULL; + struct performance_config_s *perfconf = NULL; + int i = 0; + + switch (mode) { + case VMODE_PAL: + perfconf = &cvbs_drv.perf_conf_pal; + break; + case VMODE_NTSC: + case VMODE_NTSC_M: + perfconf = &cvbs_drv.perf_conf_ntsc; + break; + default: + break; + } + if (!perfconf) + return; + + if (!perfconf->reg_table) { + printf("no performance table\n"); + return; + } + + i = 0; + s = perfconf->reg_table; + while (i < perfconf->reg_cnt) { + cvbs_write_vcbus(s->reg, s->val); + //printf("vcbus reg[0x%04x] = 0x%08x\n", s->reg, s->val); + + s++; + i++; + } + + printf("%s\n", __func__); +} + +static int cvbs_config_enci(int vmode) +{ + const struct reg_s *s = NULL; + + switch (vmode) { + case VMODE_PAL: + s = &tvregs_576cvbs_enc[0]; + break; + case VMODE_NTSC: + case VMODE_NTSC_M: + s = &tvregs_480cvbs_enc[0]; + break; + case VMODE_PAL_M: + s = &tvregs_pal_m_enc[0]; + break; + case VMODE_PAL_N: + s = &tvregs_pal_n_enc[0]; + break; + default: + break; + } + if (s == NULL) + return -1; + + while ((s->reg != MREG_END_MARKER)) { + cvbs_write_vcbus(s->reg, s->val); + //printf("reg[0x%.2x] = 0x%.4x\n", s->reg, s->val); + s ++; + } + + cvbs_performance_enhancement(vmode); + + return 0; +} + +/*----------------------------------------------------------------------------*/ +// configuration for output +// output vmode: 576cvbs, 480cvbs +int cvbs_set_vmode(char* vmode_name) +{ + if (!strncmp(vmode_name, "576cvbs", strlen("576cvbs"))) { + cvbs_mode = VMODE_PAL; + cvbs_config_enci(0); + cvbs_config_clock(); + cvbs_set_vdac(1); + return 0; + } else if (!strncmp(vmode_name, "480cvbs", strlen("480cvbs"))) { + cvbs_mode = VMODE_NTSC; + cvbs_config_enci(1); + cvbs_config_clock(); + cvbs_set_vdac(1); + return 0; + } else if (!strncmp(vmode_name, "ntsc_m", strlen("ntsc_m"))) { + cvbs_mode = VMODE_NTSC_M; + cvbs_config_enci(VMODE_NTSC_M); + cvbs_config_clock(); + cvbs_set_vdac(1); + return 0; + } else if (!strncmp(vmode_name, "pal_m", strlen("pal_m"))) { + cvbs_mode = VMODE_PAL_M; + cvbs_config_enci(VMODE_PAL_M); + cvbs_config_clock(); + cvbs_set_vdac(1); + return 0; + } else if (!strncmp(vmode_name, "pal_n", strlen("pal_n"))) { + cvbs_mode = VMODE_PAL_N; + cvbs_config_enci(VMODE_PAL_N); + cvbs_config_clock(); + cvbs_set_vdac(1); + return 0; + } else if (!strncmp(vmode_name, "disable", strlen("disable"))) { + cvbs_set_vdac(0); + cvbs_write_vcbus(ENCI_VIDEO_EN, 0); + cvbs_disable_clock(); + return 0; + } else { + printf("[%s] is invalid for cvbs.\n", vmode_name); + return -1; + } + + return 0; +} + +/*----------------------------------------------------------------------------*/ +#define CVBS_MODE_CNT 5 +static char *cvbs_mode_str[CVBS_MODE_CNT] = { + "576cvbs", + "480cvbs", + "ntsc_m", + "pal_m", + "pal_n", +}; + +// check for valid video mode +int cvbs_outputmode_check(char *vmode_name, unsigned int frac) +{ + unsigned int i; + + if (frac) { + printf("cvbs: don't support frac\n"); + return -1; + } + + for (i = 0; i < CVBS_MODE_CNT; i++) { + if (!strncmp(vmode_name, cvbs_mode_str[i], strlen(cvbs_mode_str[i]))) + return 0; + } + + printf("cvbs: outputmode[%s] is invalid\n", vmode_name); + return -1; +} + +// list for valid video mode +void cvbs_show_valid_vmode(void) +{ + unsigned int i; + + for (i = 0; i < CVBS_MODE_CNT; i++) + printf("%s\n", cvbs_mode_str[i]); +} + +static unsigned char cvbs_get_trimming_version(unsigned int flag) +{ + unsigned char version = 0xff; + + if ((flag & 0xf0) == 0xa0) + version = 5; + else if ((flag & 0xf0) == 0x40) + version = 2; + else if ((flag & 0xc0) == 0x80) + version = 1; + else if ((flag & 0xc0) == 0x00) + version = 0; + return version; +} + +static unsigned int cvbs_config_vdac(unsigned int value) +{ + unsigned char version = 0; + unsigned int cfg_valid, gsw_cfg; + + version = cvbs_get_trimming_version((value >> 8) & 0xff); + /* flag 1/0 for validity of vdac config */ + if ((version == 1) || (version == 2) || (version == 5)) { + cfg_valid = 1; + gsw_cfg = value & 0x7; + } else { + cfg_valid = 0; + gsw_cfg = 0xffff; + } + if (cfg_valid) { + printf("cvbs: %s: cvbs trimming 0x%x: %d.v%d, 0x%x\n", + __func__, value, cfg_valid, version, gsw_cfg); + } + + return gsw_cfg; +} + +static char *cvbsout_performance_str[] = { + "performance", /* default for pal */ + "performance_pal", + "performance_ntsc", +}; + +static void cvbs_get_config(void) +{ + const void *dt_blob = NULL; + int node; + char *propdata; + const char *str; + struct reg_s *s; + unsigned int i, j, temp, cnt; + int ret; + + dt_blob = gd->fdt_blob; + if (!dt_blob) { + printf("cvbs: error: dt_blob is null, load default setting\n"); + return; + } + + ret = fdt_check_header(dt_blob); + if (ret < 0) { + printf("cvbs: error: check dts: %s, load default setting\n", + fdt_strerror(ret)); + return; + } + + node = fdt_path_offset(dt_blob, "/cvbsout"); + if (node < 0) { + printf("not find /cvbsout node: %s\n", + fdt_strerror(node)); + return; + } + + /* clk_path */ + propdata = (char *)fdt_getprop(dt_blob, node, "clk_path", NULL); + if (propdata) { + s_enci_clk_path = be32_to_cpup((u32*)propdata); + printf("cvbs: find clk_path: 0x%x\n", s_enci_clk_path); + } + + /* vdac config */ + propdata = (char *)fdt_getprop(dt_blob, node, "vdac_config", NULL); + if (propdata) { + temp = cvbs_config_vdac(be32_to_cpup((u32*)propdata)); + if (temp < 0xff) + cvbs_drv.data->vdac_gsw = temp; + } + + /* performance */ + str = cvbsout_performance_str[1]; + propdata = (char *)fdt_getprop(dt_blob, node, str, NULL); + if (!propdata) { + str = cvbsout_performance_str[0]; + propdata = (char *)fdt_getprop(dt_blob, node, str, NULL); + if (!propdata) + goto cvbs_performance_config_ntsc; + } + cnt = 0; + while (cnt < CVBS_PERFORMANCE_CNT_MAX) { + j = 2 * cnt; + temp = be32_to_cpup((((u32*)propdata)+j)); + if (temp == MREG_END_MARKER) /* ending */ + break; + cnt++; + } + if (cnt >= CVBS_PERFORMANCE_CNT_MAX) + cnt = 0; + if (cnt > 0) { + printf("cvbs: find performance_pal config\n"); + cvbs_drv.perf_conf_pal.reg_table = malloc(sizeof(struct reg_s) * cnt); + if (!cvbs_drv.perf_conf_pal.reg_table) { + printf("cvbs: error: failed to alloc %s table\n", str); + cnt = 0; + } + memset(cvbs_drv.perf_conf_pal.reg_table, 0, (sizeof(struct reg_s) * cnt)); + cvbs_drv.perf_conf_pal.reg_cnt = cnt; + + i = 0; + s = cvbs_drv.perf_conf_pal.reg_table; + while (i < cvbs_drv.perf_conf_pal.reg_cnt) { + j = 2 * i; + s->reg = be32_to_cpup((((u32*)propdata)+j)); + s->val = be32_to_cpup((((u32*)propdata)+j+1)); + /* printf("%p: 0x%04x = 0x%x\n", s, s->reg, s->val); */ + + s++; + i++; + } + } + +cvbs_performance_config_ntsc: + str = cvbsout_performance_str[2]; + propdata = (char *)fdt_getprop(dt_blob, node, str, NULL); + if (!propdata) + return; + cnt = 0; + while (cnt < CVBS_PERFORMANCE_CNT_MAX) { + j = 2 * cnt; + temp = be32_to_cpup((((u32*)propdata)+j)); + if (temp == MREG_END_MARKER) /* ending */ + break; + cnt++; + } + if (cnt >= CVBS_PERFORMANCE_CNT_MAX) + cnt = 0; + if (cnt > 0) { + printf("cvbs: find performance_ntsc config\n"); + cvbs_drv.perf_conf_ntsc.reg_table = malloc(sizeof(struct reg_s) * cnt); + if (!cvbs_drv.perf_conf_ntsc.reg_table) { + printf("cvbs: error: failed to alloc %s table\n", str); + cnt = 0; + } + memset(cvbs_drv.perf_conf_ntsc.reg_table, 0, (sizeof(struct reg_s) * cnt)); + cvbs_drv.perf_conf_ntsc.reg_cnt = cnt; + + i = 0; + s = cvbs_drv.perf_conf_ntsc.reg_table; + while (i < cvbs_drv.perf_conf_ntsc.reg_cnt) { + j = 2 * i; + s->reg = be32_to_cpup((((u32*)propdata)+j)); + s->val = be32_to_cpup((((u32*)propdata)+j+1)); + /* printf("%p: 0x%04x = 0x%x\n", s, s->reg, s->val); */ + + s++; + i++; + } + } +} + +void vdac_data_config(void) +{ + printf("cvbs: cpuid:0x%x\n", get_cpu_id().family_id); + switch (get_cpu_id().family_id) { + case MESON_CPU_MAJOR_ID_G12A: + cvbs_drv.data = &cvbs_data_g12a; + break; + case MESON_CPU_MAJOR_ID_G12B: + cvbs_drv.data = &cvbs_data_g12b; + break; + case MESON_CPU_MAJOR_ID_SC2: + cvbs_drv.data = &cvbs_data_sc2; + break; + default: + break; + } +} + +void cvbs_init(void) +{ + vdac_data_config(); + vdac_ctrl_config_probe(); + cvbs_get_config(); +} +
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs.h b/drivers/amlogic/media/vout/cvbs/cvbs.h new file mode 100644 index 0000000..27f618c --- /dev/null +++ b/drivers/amlogic/media/vout/cvbs/cvbs.h
@@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _AML_CVBS_H +#define _AML_CVBS_H + +#define CONFIG_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT 1 + +#define CONFIG_CVBS_CHINASARFT 0x0 +#define CONFIG_CVBS_CHINATELECOM 0x1 +#define CONFIG_CVBS_CHINAMOBILE 0x2 +#define CONFIG_CVBS_PERFORMANCE_ACTIVED CONFIG_CVBS_CHINASARFT + +#define MREG_END_MARKER 0xFFFF + +enum cvbs_chip_e { + CVBS_CHIP_G12A = 0, + CVBS_CHIP_G12B, /* 1 */ + CVBS_CHIP_SC2, /* 2 */ + CVBS_CHIP_MAX, +}; + +enum CVBS_MODE_e { + VMODE_PAL, + VMODE_NTSC, + VMODE_PAL_M, + VMODE_PAL_N, + VMODE_NTSC_M, + VMODE_MAX +}; + +struct cvbs_data_s { + enum cvbs_chip_e chip_type; + + unsigned int reg_vid_pll_clk_div; + unsigned int reg_vid_clk_div; + unsigned int reg_vid_clk_ctrl; + unsigned int reg_vid2_clk_div; + unsigned int reg_vid2_clk_ctrl; + unsigned int reg_vid_clk_ctrl2; + + unsigned int vdac_vref_adj; + unsigned int vdac_gsw; +}; + +struct reg_s { + unsigned int reg; + unsigned int val; +}; + +#define CVBS_PERFORMANCE_CNT_MAX 20 +struct performance_config_s { + unsigned int reg_cnt; + struct reg_s *reg_table; +}; + +struct cvbs_drv_s { + struct cvbs_data_s *data; + struct performance_config_s perf_conf_pal; + struct performance_config_s perf_conf_ntsc; +}; + +#endif
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_config.h b/drivers/amlogic/media/vout/cvbs/cvbs_config.h new file mode 100644 index 0000000..3b3309c --- /dev/null +++ b/drivers/amlogic/media/vout/cvbs/cvbs_config.h
@@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include "cvbs_reg.h" +#include "cvbs.h" + +static const struct reg_s tvregs_576cvbs_enc[] = { + {ENCI_CFILT_CTRL, 0x12, }, + {ENCI_CFILT_CTRL2, 0x12, }, + {VENC_DVI_SETTING, 0, }, + {ENCI_VIDEO_MODE, 0, }, + {ENCI_VIDEO_MODE_ADV, 0, }, + {ENCI_SYNC_HSO_BEGIN, 3, }, + {ENCI_SYNC_HSO_END, 129, }, + {ENCI_SYNC_VSO_EVNLN, 0x0003 }, + {ENCI_SYNC_VSO_ODDLN, 0x0104 }, + {ENCI_MACV_MAX_AMP, 0x8107 }, + {VENC_VIDEO_PROG_MODE, 0xff }, + {ENCI_VIDEO_MODE, 0x13 }, + {ENCI_VIDEO_MODE_ADV, 0x26, }, + {ENCI_VIDEO_SCH, 0x28, }, + {ENCI_SYNC_MODE, 0x07, }, + {ENCI_YC_DELAY, 0x333, }, + {ENCI_VFIFO2VD_PIXEL_START, 0x0fb }, + {ENCI_VFIFO2VD_PIXEL_END, 0x069b }, + {ENCI_VFIFO2VD_LINE_TOP_START, 0x0016 }, + {ENCI_VFIFO2VD_LINE_TOP_END, 0x0136 }, + {ENCI_VFIFO2VD_LINE_BOT_START, 0x0017 }, + {ENCI_VFIFO2VD_LINE_BOT_END, 0x0137 }, + {VENC_SYNC_ROUTE, 0, }, + {ENCI_DBG_PX_RST, 0, }, + {VENC_INTCTRL, 0x2, }, + {ENCI_VFIFO2VD_CTL, 0x4e01, }, + {VENC_VDAC_SETTING, 0, }, + {VENC_UPSAMPLE_CTRL0, 0x0061, }, + {VENC_UPSAMPLE_CTRL1, 0x4061, }, + {VENC_UPSAMPLE_CTRL2, 0x5061, }, + {VENC_VDAC_DACSEL0, 0x0000, }, + {VENC_VDAC_DACSEL1, 0x0000, }, + {VENC_VDAC_DACSEL2, 0x0000, }, + {VENC_VDAC_DACSEL3, 0x0000, }, + {VENC_VDAC_DACSEL4, 0x0000, }, + {VENC_VDAC_DACSEL5, 0x0000, }, + {VENC_VDAC_FIFO_CTRL, 0x2000, }, + {ENCI_DACSEL_0, 0x0011 }, + {ENCI_DACSEL_1, 0x11 }, + {ENCI_VIDEO_EN, 1, }, + {ENCI_VIDEO_SAT, 0x7 }, + {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 }, + {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, + {ENCI_MACV_N0, 0x0 }, + {ENCI_VIDEO_CONT, 0x0 }, + {MREG_END_MARKER, 0 } +}; + +static const struct reg_s tvregs_480cvbs_enc[] = { + {ENCI_CFILT_CTRL, 0x12, }, + {ENCI_CFILT_CTRL2, 0x12, }, + {VENC_DVI_SETTING, 0, }, + {ENCI_VIDEO_MODE, 0, }, + {ENCI_VIDEO_MODE_ADV, 0, }, + {ENCI_SYNC_HSO_BEGIN, 5, }, + {ENCI_SYNC_HSO_END, 129, }, + {ENCI_SYNC_VSO_EVNLN, 0x0003 }, + {ENCI_SYNC_VSO_ODDLN, 0x0104 }, + {ENCI_MACV_MAX_AMP, 0x810b }, + {VENC_VIDEO_PROG_MODE, 0xf0 }, + {ENCI_VIDEO_MODE, 0x08 }, + {ENCI_VIDEO_MODE_ADV, 0x26, }, + {ENCI_VIDEO_SCH, 0x20, }, + {ENCI_SYNC_MODE, 0x07, }, + {ENCI_YC_DELAY, 0x333, }, + {ENCI_VFIFO2VD_PIXEL_START, 0xe3, }, + {ENCI_VFIFO2VD_PIXEL_END, 0x0683, }, + {ENCI_VFIFO2VD_LINE_TOP_START, 0x12, }, + {ENCI_VFIFO2VD_LINE_TOP_END, 0x102, }, + {ENCI_VFIFO2VD_LINE_BOT_START, 0x13, }, + {ENCI_VFIFO2VD_LINE_BOT_END, 0x103, }, + {VENC_SYNC_ROUTE, 0, }, + {ENCI_DBG_PX_RST, 0, }, + {VENC_INTCTRL, 0x2, }, + {ENCI_VFIFO2VD_CTL, 0x4e01, }, + {VENC_VDAC_SETTING, 0, }, + {VENC_UPSAMPLE_CTRL0, 0x0061, }, + {VENC_UPSAMPLE_CTRL1, 0x4061, }, + {VENC_UPSAMPLE_CTRL2, 0x5061, }, + {VENC_VDAC_DACSEL0, 0x0000, }, + {VENC_VDAC_DACSEL1, 0x0000, }, + {VENC_VDAC_DACSEL2, 0x0000, }, + {VENC_VDAC_DACSEL3, 0x0000, }, + {VENC_VDAC_DACSEL4, 0x0000, }, + {VENC_VDAC_DACSEL5, 0x0000, }, + {VENC_VDAC_FIFO_CTRL, 0x2000, }, + {ENCI_DACSEL_0, 0x0011 }, + {ENCI_DACSEL_1, 0x11 }, + {ENCI_VIDEO_EN, 1, }, + {ENCI_VIDEO_SAT, 0x12 }, + {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 }, + {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, + {ENCI_MACV_N0, 0x0 }, + {ENCI_SYNC_ADJ, 0x9c00 }, + {ENCI_VIDEO_CONT, 0x3 }, + {MREG_END_MARKER, 0 } +}; + +static const struct reg_s tvregs_pal_m_enc[] = { + {ENCI_CFILT_CTRL, 0x12, }, + {ENCI_CFILT_CTRL2, 0x12, }, + {VENC_DVI_SETTING, 0, }, + {ENCI_VIDEO_MODE, 0, }, + {ENCI_VIDEO_MODE_ADV, 0, }, + {ENCI_SYNC_HSO_BEGIN, 5, }, + {ENCI_SYNC_HSO_END, 129, }, + {ENCI_SYNC_VSO_EVNLN, 0x0003 }, + {ENCI_SYNC_VSO_ODDLN, 0x0104 }, + {ENCI_MACV_MAX_AMP, 0x810b }, + {VENC_VIDEO_PROG_MODE, 0xf0 }, + {ENCI_VIDEO_MODE, 0x2a }, + {ENCI_VIDEO_MODE_ADV, 0x26, }, + {ENCI_VIDEO_SCH, 0x20, }, + {ENCI_SYNC_MODE, 0x07, }, + {ENCI_YC_DELAY, 0x333, }, + {ENCI_VFIFO2VD_PIXEL_START, 0xe3, }, + {ENCI_VFIFO2VD_PIXEL_END, 0x0683,}, + {ENCI_VFIFO2VD_LINE_TOP_START, 0x12, }, + {ENCI_VFIFO2VD_LINE_TOP_END, 0x102, }, + {ENCI_VFIFO2VD_LINE_BOT_START, 0x13, }, + {ENCI_VFIFO2VD_LINE_BOT_END, 0x103, }, + {VENC_SYNC_ROUTE, 0, }, + {ENCI_DBG_PX_RST, 0, }, + {VENC_INTCTRL, 0x2, }, + {ENCI_VFIFO2VD_CTL, 0x4e01,}, + {VENC_VDAC_SETTING, 0, }, + {VENC_UPSAMPLE_CTRL0, 0x0061,}, + {VENC_UPSAMPLE_CTRL1, 0x4061,}, + {VENC_UPSAMPLE_CTRL2, 0x5061,}, + {VENC_VDAC_DACSEL0, 0x0000,}, + {VENC_VDAC_DACSEL1, 0x0000,}, + {VENC_VDAC_DACSEL2, 0x0000,}, + {VENC_VDAC_DACSEL3, 0x0000,}, + {VENC_VDAC_DACSEL4, 0x0000,}, + {VENC_VDAC_DACSEL5, 0x0000,}, + {VENC_VDAC_FIFO_CTRL, 0x2000,}, + {ENCI_DACSEL_0, 0x0011 }, + {ENCI_DACSEL_1, 0x11 }, + {ENCI_VIDEO_EN, 1, }, + {ENCI_VIDEO_SAT, 0x12 }, + {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 }, + {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, + {ENCI_MACV_N0, 0x0 }, + {ENCI_SYNC_ADJ, 0x9c00 }, + {ENCI_VIDEO_CONT, 0x3 }, + {MREG_END_MARKER, 0 } +}; + +static const struct reg_s tvregs_pal_n_enc[] = { + {ENCI_CFILT_CTRL, 0x12, }, + {ENCI_CFILT_CTRL2, 0x12, }, + {VENC_DVI_SETTING, 0, }, + {ENCI_VIDEO_MODE, 0, }, + {ENCI_VIDEO_MODE_ADV, 0, }, + {ENCI_SYNC_HSO_BEGIN, 3, }, + {ENCI_SYNC_HSO_END, 129, }, + {ENCI_SYNC_VSO_EVNLN, 0x0003 }, + {ENCI_SYNC_VSO_ODDLN, 0x0104 }, + {ENCI_MACV_MAX_AMP, 0x8107 }, + {VENC_VIDEO_PROG_MODE, 0xff }, + {ENCI_VIDEO_MODE, 0x3b }, + {ENCI_VIDEO_MODE_ADV, 0x26, }, + {ENCI_VIDEO_SCH, 0x28, }, + {ENCI_SYNC_MODE, 0x07, }, + {ENCI_YC_DELAY, 0x333, }, + {ENCI_VFIFO2VD_PIXEL_START, 0x0fb }, + {ENCI_VFIFO2VD_PIXEL_END, 0x069b }, + {ENCI_VFIFO2VD_LINE_TOP_START, 0x0016 }, + {ENCI_VFIFO2VD_LINE_TOP_END, 0x0136 }, + {ENCI_VFIFO2VD_LINE_BOT_START, 0x0017 }, + {ENCI_VFIFO2VD_LINE_BOT_END, 0x0137 }, + {VENC_SYNC_ROUTE, 0, }, + {ENCI_DBG_PX_RST, 0, }, + {VENC_INTCTRL, 0x2, }, + {ENCI_VFIFO2VD_CTL, 0x4e01, }, + {VENC_VDAC_SETTING, 0, }, + {VENC_UPSAMPLE_CTRL0, 0x0061, }, + {VENC_UPSAMPLE_CTRL1, 0x4061, }, + {VENC_UPSAMPLE_CTRL2, 0x5061, }, + {VENC_VDAC_DACSEL0, 0x0000, }, + {VENC_VDAC_DACSEL1, 0x0000, }, + {VENC_VDAC_DACSEL2, 0x0000, }, + {VENC_VDAC_DACSEL3, 0x0000, }, + {VENC_VDAC_DACSEL4, 0x0000, }, + {VENC_VDAC_DACSEL5, 0x0000, }, + {VENC_VDAC_FIFO_CTRL, 0x2000, }, + {ENCI_DACSEL_0, 0x0011 }, + {ENCI_DACSEL_1, 0x11 }, + {ENCI_VIDEO_EN, 1, }, + {ENCI_VIDEO_SAT, 0x7 }, + {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 }, + {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 }, + {ENCI_MACV_N0, 0x0 }, + {ENCI_VIDEO_CONT, 0x0 }, + {MREG_END_MARKER, 0 } +}; +
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_dummy_reg.h b/drivers/amlogic/media/vout/cvbs/cvbs_dummy_reg.h new file mode 100644 index 0000000..434235f --- /dev/null +++ b/drivers/amlogic/media/vout/cvbs/cvbs_dummy_reg.h
@@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CVBS_DUMMY_REG_H__ +#define __CVBS_DUMMY_REG_H__ + +#ifndef REG_BASE_VCBUS +#define REG_BASE_VCBUS (0xff900000L) +#endif + +#ifndef HHI_VDAC_CNTL0 +#define HHI_VDAC_CNTL0 (0xff63c000 + (0x0bb << 2)) +#endif +#ifndef HHI_VDAC_CNTL1 +#define HHI_VDAC_CNTL1 (0xff63c000 + (0x0bc << 2)) +#endif + +#ifndef ANACTRL_VDAC_CTRL0 +#define ANACTRL_VDAC_CTRL0 ((0x00b0 << 2) + 0xfe008000) +#endif +#ifndef ANACTRL_VDAC_CTRL1 +#define ANACTRL_VDAC_CTRL1 ((0x00b1 << 2) + 0xfe008000) +#endif + +#ifndef HHI_GP0_PLL_CNTL0 +#define HHI_GP0_PLL_CNTL0 (0xff63c000 + (0x010 << 2)) +#endif +#ifndef HHI_GP0_PLL_CNTL1 +#define HHI_GP0_PLL_CNTL1 (0xff63c000 + (0x11 << 2)) +#endif +#ifndef HHI_GP0_PLL_CNTL2 +#define HHI_GP0_PLL_CNTL2 (0xff63c000 + (0x12 << 2)) +#endif +#ifndef HHI_GP0_PLL_CNTL3 +#define HHI_GP0_PLL_CNTL3 (0xff63c000 + (0x13 << 2)) +#endif +#ifndef HHI_GP0_PLL_CNTL4 +#define HHI_GP0_PLL_CNTL4 (0xff63c000 + (0x14 << 2)) +#endif +#ifndef HHI_GP0_PLL_CNTL5 +#define HHI_GP0_PLL_CNTL5 (0xff63c000 + (0x15 << 2)) +#endif +#ifndef HHI_GP0_PLL_CNTL6 +#define HHI_GP0_PLL_CNTL6 (0xff63c000 + (0x016 << 2)) +#endif + +#ifndef HHI_HDMI_PLL_CNTL +#define HHI_HDMI_PLL_CNTL (0xff63c000 + (0xc8 << 2)) +#endif +#ifndef HHI_HDMI_PLL_CNTL0 +#define HHI_HDMI_PLL_CNTL0 (0xff63c000 + (0xc8 << 2)) +#endif +#ifndef HHI_HDMI_PLL_CNTL1 +#define HHI_HDMI_PLL_CNTL1 (0xff63c000 + (0xc9 << 2)) +#endif +#ifndef HHI_HDMI_PLL_CNTL2 +#define HHI_HDMI_PLL_CNTL2 (0xff63c000 + (0xca << 2)) +#endif +#ifndef HHI_HDMI_PLL_CNTL3 +#define HHI_HDMI_PLL_CNTL3 (0xff63c000 + (0xcb << 2)) +#endif +#ifndef HHI_HDMI_PLL_CNTL4 +#define HHI_HDMI_PLL_CNTL4 (0xff63c000 + (0xcd << 2)) +#endif +#ifndef HHI_HDMI_PLL_CNTL5 +#define HHI_HDMI_PLL_CNTL5 (0xff63c000 + (0xcd << 2)) +#endif +#ifndef HHI_HDMI_PLL_CNTL6 +#define HHI_HDMI_PLL_CNTL6 (0xff63c000 + (0xce << 2)) +#endif + +#ifndef HHI_VID_PLL_CLK_DIV +#define HHI_VID_PLL_CLK_DIV (0xff63c000 + (0x068 << 2)) +#endif + +#ifndef HHI_VIID_CLK_DIV +#define HHI_VIID_CLK_DIV (0xff63c000 + (0x04a << 2)) +#endif + +#ifndef HHI_VIID_CLK_CNTL +#define HHI_VIID_CLK_CNTL (0xff63c000 + (0x04b << 2)) +#endif + +#ifndef HHI_VID_CLK_DIV +#define HHI_VID_CLK_DIV (0xff63c000 + (0x059 << 2)) +#endif + +#ifndef HHI_VID_CLK_CNTL2 +#define HHI_VID_CLK_CNTL2 (0xff63c000 + (0x065 << 2)) +#endif + +#ifndef HHI_VID_CLK_CNTL +#define HHI_VID_CLK_CNTL (0xff63c000 + (0x05f << 2)) +#endif + +#ifndef ANACTRL_HDMIPLL_CTRL0 +#define ANACTRL_HDMIPLL_CTRL0 ((0x0070 << 2) + 0xfe008000) +#endif +#ifndef ANACTRL_HDMIPLL_CTRL1 +#define ANACTRL_HDMIPLL_CTRL1 ((0x0071 << 2) + 0xfe008000) +#endif +#ifndef ANACTRL_HDMIPLL_CTRL2 +#define ANACTRL_HDMIPLL_CTRL2 ((0x0072 << 2) + 0xfe008000) +#endif +#ifndef ANACTRL_HDMIPLL_CTRL3 +#define ANACTRL_HDMIPLL_CTRL3 ((0x0073 << 2) + 0xfe008000) +#endif +#ifndef ANACTRL_HDMIPLL_CTRL4 +#define ANACTRL_HDMIPLL_CTRL4 ((0x0074 << 2) + 0xfe008000) +#endif +#ifndef ANACTRL_HDMIPLL_CTRL5 +#define ANACTRL_HDMIPLL_CTRL5 ((0x0075 << 2) + 0xfe008000) +#endif +#ifndef ANACTRL_HDMIPLL_CTRL6 +#define ANACTRL_HDMIPLL_CTRL6 ((0x0076 << 2) + 0xfe008000) +#endif + +#ifndef CLKCTRL_VID_CLK_CTRL +#define CLKCTRL_VID_CLK_CTRL ((0x0030 << 2) + 0xfe000000) +#endif +#ifndef CLKCTRL_VID_CLK_CTRL2 +#define CLKCTRL_VID_CLK_CTRL2 ((0x0031 << 2) + 0xfe000000) +#endif +#ifndef CLKCTRL_VID_CLK_DIV +#define CLKCTRL_VID_CLK_DIV ((0x0032 << 2) + 0xfe000000) +#endif +#ifndef CLKCTRL_VIID_CLK_DIV +#define CLKCTRL_VIID_CLK_DIV ((0x0033 << 2) + 0xfe000000) +#endif +#ifndef CLKCTRL_VIID_CLK_CTRL +#define CLKCTRL_VIID_CLK_CTRL ((0x0034 << 2) + 0xfe000000) +#endif +#ifndef CLKCTRL_VID_PLL_CLK_DIV +#define CLKCTRL_VID_PLL_CLK_DIV ((0x0039 << 2) + 0xfe000000) +#endif + +#endif \ No newline at end of file
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_reg.h b/drivers/amlogic/media/vout/cvbs/cvbs_reg.h new file mode 100644 index 0000000..c3ee332 --- /dev/null +++ b/drivers/amlogic/media/vout/cvbs/cvbs_reg.h
@@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __CVBS_REG_H__ +#define __CVBS_REG_H__ +#include <asm/arch/io.h> +#include <asm/arch/secure_apb.h> +#include "cvbs.h" +#include "cvbs_dummy_reg.h" + +// encoder registers +#define BUS_TYPE_CBUS 0 +#define BUS_TYPE_HIU 1 +#define BUS_TYPE_VCBUS 2 + +#define DAC0_CLK_SEL 28 +#define DAC1_CLK_SEL 24 +#define DAC2_CLK_SEL 20 +#define VCLK2_XD_RST 17 +#define VCLK2_XD_EN 16 +#define ENCL_CLK_SEL 12 +#define VCLK2_XD 0 +#define VCLK_XD0 0 +#define VCLK_CLK_IN_SEL 16 +#define VCLK_EN0 19 +#define VCLK_XD_EN 16 +#define VCLK_DIV1_EN 0 +#define VCLK_SOFT_RST 15 + +#define VCLK2_EN 19 +#define VCLK2_CLK_IN_SEL 16 +#define VCLK2_SOFT_RST 15 +#define VCLK2_DIV12_EN 4 +#define VCLK2_DIV6_EN 3 +#define VCLK2_DIV4_EN 2 +#define VCLK2_DIV2_EN 1 +#define VCLK2_DIV1_EN 0 + +/* ******************************** + * register define + * ********************************* */ + +#define CVBS_REG_OFFSET_VCBUS(reg) (((reg) << 2)) + +#define CVBS_REG_ADDR(reg) (reg + 0L) +#define CVBS_REG_ADDR_HIU(reg) (reg + 0L) +#define CVBS_REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + CVBS_REG_OFFSET_VCBUS(reg)) + +/* ******************************** + * register access api + * ********************************* */ +static inline int cvbs_write_hiu(unsigned int addr, unsigned int value) +{ + *(volatile unsigned int *)CVBS_REG_ADDR_HIU(addr) = (value); + return 0; +} + +static inline int cvbs_read_hiu(unsigned int addr) +{ + unsigned int val = 0; + + val = *(volatile unsigned int *)(CVBS_REG_ADDR_HIU(addr)); + return val; +} + +static inline int cvbs_set_hiu_bits(unsigned int addr, unsigned int value, unsigned int start, unsigned int len) +{ + cvbs_write_hiu(addr, ((cvbs_read_hiu(addr) & + ~(((1L << (len))-1) << (start))) | + (((value)&((1L<<(len))-1)) << (start)))); + return 0; +} + +static inline int cvbs_get_hiu_bits(unsigned int addr, unsigned int start, unsigned int len) +{ + return (cvbs_read_hiu(addr) >> (start)) & ((1L << (len)) - 1); +} + +static inline unsigned int cvbs_read_vcbus(unsigned int addr_offset) +{ + unsigned int val = 0; + + if (addr_offset > 0x10000) + val = *(volatile unsigned int *)(CVBS_REG_ADDR(addr_offset)); + else + val = *(volatile unsigned int *)(CVBS_REG_ADDR_VCBUS(addr_offset)); + return val; +} + +static inline int cvbs_write_vcbus(unsigned int addr_offset, unsigned int value) +{ + if (addr_offset > 0x10000) + *(volatile unsigned int *)CVBS_REG_ADDR(addr_offset) = (value); + else + *(volatile unsigned int *)CVBS_REG_ADDR_VCBUS(addr_offset) = (value); + return 0; +} + +static inline int cvbs_set_vcbus_bits(unsigned int addr_offset, unsigned int value, unsigned int start, unsigned int len) +{ + cvbs_write_vcbus(addr_offset, ((cvbs_read_vcbus(addr_offset) & + ~(((1L << (len))-1) << (start))) | + (((value)&((1L<<(len))-1)) << (start)))); + return 0; +} + +#endif
diff --git a/drivers/amlogic/media/vout/cvbs/vdac.c b/drivers/amlogic/media/vout/cvbs/vdac.c new file mode 100644 index 0000000..05de4bc --- /dev/null +++ b/drivers/amlogic/media/vout/cvbs/vdac.c
@@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <amlogic/cpu_id.h> +#include "vdac.h" +#include "cvbs_reg.h" + +static struct vdac_data_s *vdac_data; +static unsigned int pri_flag; + +#define REG_ADDR_VDAC(reg) (reg + 0L) + +static void vdac_write_reg(unsigned int addr, unsigned int val) +{ + *(volatile unsigned int *)REG_ADDR_VDAC(addr) = (val); +} + +static unsigned int vdac_read_reg(unsigned int addr) +{ + return *(volatile unsigned int *)(REG_ADDR_VDAC(addr)); +} + +static void vdac_set_reg_bits(unsigned int addr, unsigned int val, + unsigned int start, unsigned int len) +{ + vdac_write_reg(addr, ((vdac_read_reg(addr) & + ~(((1L << (len))-1) << (start))) | + (((val)&((1L<<(len))-1)) << (start)))); +} + +static int vdac_ctrl_config(bool on, unsigned int reg, unsigned int bit) +{ + struct meson_vdac_ctrl_s *vdac_ctrl; + unsigned int val; + int i = 0; + int ret = -1; + + if (!vdac_data) { + printf("%s: vdac_data is NULL\n", __func__); + return ret; + } + + if (!vdac_data->vdac_ctrl) { + printf("%s: vdac_ctrl is NULL\n", __func__); + return ret; + } + + vdac_ctrl = vdac_data->vdac_ctrl; + while (i < VDAC_CTRL_MAX) { + if (vdac_ctrl[i].reg == VDAC_REG_MAX) + break; + if ((vdac_ctrl[i].reg == reg) && (vdac_ctrl[i].bit == bit)) { + if (on) + val = vdac_ctrl[i].val; + else + val = vdac_ctrl[i].val ? 0 : 1; + vdac_set_reg_bits(reg, val, bit, vdac_ctrl[i].len); + //if (vdac_debug_print) { + // printf("vdac: reg=0x%02x set bit%d=%d, readback=0x%08x\n", + // reg, bit, val, vdac_hiu_reg_read(reg)); + //} + ret = 0; + break; + } + i++; + } + + return ret; +} + +static void vdac_enable_cvbs_out(bool on) +{ + unsigned int reg_cntl0; + unsigned int reg_cntl1; + + if (!vdac_data) { + printf("%s: vdac_data is NULL\n", __func__); + return; + } + + reg_cntl0 = vdac_data->reg_ctrl0; + reg_cntl1 = vdac_data->reg_ctrl1; + + if (on) { + vdac_set_reg_bits(reg_cntl0, 0x6, 12, 4); + vdac_ctrl_config(1, reg_cntl1, 3); + vdac_ctrl_config(1, reg_cntl0, 0); + vdac_ctrl_config(1, reg_cntl0, 9); + } else { + vdac_ctrl_config(0, reg_cntl0, 9); + vdac_ctrl_config(0, reg_cntl0, 0); + vdac_ctrl_config(0, reg_cntl1, 3); + } +} + +void vdac_enable(bool on, unsigned int module_sel) +{ + if (!vdac_data) { + printf("%s: vdac_data is NULL\n", __func__); + return; + } + + printf("%s: %d, module_sel:0x%x\n", __func__, on, module_sel); + + switch (module_sel) { + case VDAC_MODULE_CVBS_OUT: + if (on) { + pri_flag |= VDAC_MODULE_CVBS_OUT; + vdac_enable_cvbs_out(1); + } else { + pri_flag &= ~VDAC_MODULE_CVBS_OUT; + vdac_enable_cvbs_out(0); + } + break; + default: + printf("%s:module_sel: 0x%x wrong module index !! ", + __func__, module_sel); + break; + } +} + +int vdac_ctrl_vref_adj(unsigned int value) +{ + struct meson_vdac_ctrl_s *vdac_ctrl; + unsigned int reg; + unsigned int bit = 16; + int i = 0; + int ret = -1; + + if (!vdac_data) { + printf("%s: vdac_data is NULL\n", __func__); + return ret; + } + + if (!vdac_data->vdac_ctrl) { + printf("%s: vdac_ctrl is NULL\n", __func__); + return ret; + } + + vdac_ctrl = vdac_data->vdac_ctrl; + reg = vdac_data->reg_ctrl0; + while (i < VDAC_CTRL_MAX) { + if (vdac_ctrl[i].reg == VDAC_REG_MAX) + break; + if ((vdac_ctrl[i].reg == reg) && (vdac_ctrl[i].bit == bit)) { + vdac_set_reg_bits(reg, value, bit, vdac_ctrl[i].len); + //if (vdac_debug_print) { + // printf("vdac: reg=0x%x set bit%d=0x%x, readback=0x%08x\n", + // reg, bit, value, vdac_hiu_reg_read(reg)); + //} + ret = 0; + break; + } + i++; + } + + return ret; +} + +int vdac_ctrl_gsw_adj(unsigned int value) +{ + struct meson_vdac_ctrl_s *vdac_ctrl; + unsigned int reg; + unsigned int bit = 0; + int i = 0; + int ret = -1; + + if (!vdac_data) { + printf("%s: vdac_data is NULL\n", __func__); + return ret; + } + + if (!vdac_data->vdac_ctrl) { + printf("%s: vdac_ctrl is NULL\n", __func__); + return ret; + } + + vdac_ctrl = vdac_data->vdac_ctrl; + reg = vdac_data->reg_ctrl1; + while (i < VDAC_CTRL_MAX) { + if (vdac_ctrl[i].reg == VDAC_REG_MAX) + break; + if ((vdac_ctrl[i].reg == reg) && (vdac_ctrl[i].bit == bit)) { + vdac_set_reg_bits(reg, value, bit, vdac_ctrl[i].len); + //if (vdac_debug_print) { + // printf("vdac: reg=0x%x set bit%d=0x%x, readback=0x%08x\n", + // reg, bit, value, vdac_hiu_reg_read(reg)); + //} + ret = 0; + break; + } + i++; + } + + return ret; +} + +static struct meson_vdac_ctrl_s vdac_ctrl_enable_g12ab[] = { + {HHI_VDAC_CNTL0, 0, 9, 1}, + {HHI_VDAC_CNTL0, 1, 0, 1}, + {HHI_VDAC_CNTL0, 0, 16, 5}, /* vref adj */ + {HHI_VDAC_CNTL1, 0, 0, 3}, /*gsw */ + {HHI_VDAC_CNTL1, 0, 3, 1}, + {VDAC_REG_MAX, 0, 0, 0}, +}; + +static struct meson_vdac_ctrl_s vdac_ctrl_enable_sc2[] = { + {ANACTRL_VDAC_CTRL0, 0, 9, 1}, + {ANACTRL_VDAC_CTRL0, 1, 0, 1}, + {ANACTRL_VDAC_CTRL0, 0, 16, 5}, /* vref adj */ + {ANACTRL_VDAC_CTRL1, 0, 0, 3}, /*gsw */ + {ANACTRL_VDAC_CTRL1, 0, 3, 1}, + {ANACTRL_VDAC_CTRL1, 0, 7, 1}, /* bandgap */ + {VDAC_REG_MAX, 0, 0, 0}, +}; + +struct vdac_data_s vdac_data_g12ab = { + .reg_ctrl0 = HHI_VDAC_CNTL0, + .reg_ctrl1 = HHI_VDAC_CNTL1, + .vdac_ctrl = vdac_ctrl_enable_g12ab, +}; + +struct vdac_data_s vdac_data_sc2 = { + .reg_ctrl0 = ANACTRL_VDAC_CTRL0, + .reg_ctrl1 = ANACTRL_VDAC_CTRL1, + .vdac_ctrl = vdac_ctrl_enable_sc2, +}; + +void vdac_ctrl_config_probe(void) +{ + pri_flag = 0; + + switch (get_cpu_id().family_id) { + case MESON_CPU_MAJOR_ID_G12A: + case MESON_CPU_MAJOR_ID_G12B: + vdac_data = &vdac_data_g12ab; + break; + case MESON_CPU_MAJOR_ID_SC2: + vdac_data = &vdac_data_sc2; + break; + default: + break; + } + + return; +}
diff --git a/drivers/amlogic/media/vout/cvbs/vdac.h b/drivers/amlogic/media/vout/cvbs/vdac.h new file mode 100644 index 0000000..9da7395 --- /dev/null +++ b/drivers/amlogic/media/vout/cvbs/vdac.h
@@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _AML_VDAC_H +#define _AML_VDAC_H + +#define VDAC_MODULE_MASK (0x1f) +#define VDAC_MODULE_AVOUT_ATV (1 << 0) /*0x1*/ +#define VDAC_MODULE_DTV_DEMOD (1 << 1) /*0x2*/ +#define VDAC_MODULE_AVOUT_AV (1 << 2) /*0x4*/ +#define VDAC_MODULE_CVBS_OUT (1 << 3) /*0x8*/ +#define VDAC_MODULE_AUDIO_OUT (1 << 4) /*0x10*/ + +#define VDAC_CTRL_MAX 10 + +#define VDAC_REG_MAX 0xffff + +struct meson_vdac_ctrl_s { + unsigned int reg; + unsigned int val; + unsigned int bit; + unsigned int len; +}; + +struct vdac_data_s { + unsigned int reg_ctrl0; + unsigned int reg_ctrl1; + struct meson_vdac_ctrl_s *vdac_ctrl; +}; + +void vdac_enable(bool on, unsigned int module_sel); +int vdac_ctrl_vref_adj(unsigned int value); +int vdac_ctrl_gsw_adj(unsigned int value); +void vdac_ctrl_config_probe(void); + +#endif
diff --git a/drivers/amlogic/media/vout/hdmitx/Kconfig b/drivers/amlogic/media/vout/hdmitx/Kconfig index 4817412..2250598 100644 --- a/drivers/amlogic/media/vout/hdmitx/Kconfig +++ b/drivers/amlogic/media/vout/hdmitx/Kconfig
@@ -1,5 +1,11 @@ +menu "AMLOGIC HDMI TX Drivers" + config AML_HDMITX - bool "AML Hdmitx drivers Support" + bool "Amlogic HDMITX drivers Support" + depends on AML_VOUT help HDMITX Output Enable +source "drivers/amlogic/media/vout/hdmitx/hdmitx20/Kconfig" + +endmenu
diff --git a/drivers/amlogic/media/vout/hdmitx/Makefile b/drivers/amlogic/media/vout/hdmitx/Makefile index 70b1813..53bab1c 100644 --- a/drivers/amlogic/media/vout/hdmitx/Makefile +++ b/drivers/amlogic/media/vout/hdmitx/Makefile
@@ -1,11 +1,4 @@ -# -# (C) Copyright 2018 -# +# SPDX-License-Identifier: GPL-2.0+ -#EXTRA_CFLAGS = -Idrivers/video/include/ - -obj-y += hdmitx.o - -hdmitx-y := hdmitx_set.o hdmitx_tvenc.o enc_clk_config.o hdmi_edid_parsing.o hdmi_parameters.o -#aml_hdmitx20-$(CONFIG_AML_HDMITX20_HDCP) += hdmitx_hdcp.o - +obj-$(CONFIG_AML_HDMITX20) += hdmitx20/ +obj-$(CONFIG_AML_HDMITX20) += sound.o
diff --git a/drivers/amlogic/media/vout/hdmitx/enc_clk_config.c b/drivers/amlogic/media/vout/hdmitx/enc_clk_config.c deleted file mode 100644 index 646a1f0..0000000 --- a/drivers/amlogic/media/vout/hdmitx/enc_clk_config.c +++ /dev/null
@@ -1,632 +0,0 @@ -/* - * driver/amlogic/media/vout/hdmitx/enc_clk_config.c - * - * Copyright (C) 2018 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <common.h> -#include <amlogic/enc_clk_config.h> -#include <asm/arch/register.h> -#include <asm/arch/secure_apb.h> - -#include "hdmitx_common.h" -#include <amlogic/media/vout/hdmitx.h> - -#define msleep(i) udelay(i*1000) - -#define check_clk_config(para)\ - if (para == -1)\ - return; - -#define check_div() \ - if (div == -1)\ - return ;\ - switch (div) {\ - case 1:\ - div = 0; break;\ - case 2:\ - div = 1; break;\ - case 4:\ - div = 2; break;\ - case 6:\ - div = 3; break;\ - case 12:\ - div = 4; break;\ - default:\ - break;\ - } - -/* viu_channel_sel: 1 or 2*/ -/* viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.*/ -int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel) -{ - if ((viu_channel_sel > 2) || (viu_channel_sel == 0)) - return -1; - if (viu_channel_sel == 1) - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2); - else - /* viu_channel_sel ==2*/ - hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2); - return 0; -} - -static void set_hdmitx_sys_clk(void) -{ - hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3); - hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 0, 7); - hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 1, 8, 1); -} - - -/* -------------------------------------------------- - * clocks_set_vid_clk_div - * -------------------------------------------------- - * wire clk_final_en = control[19]; - * wire clk_div1 = control[18]; - * wire [1:0] clk_sel = control[17:16]; - * wire set_preset = control[15]; - * wire [14:0] shift_preset = control[14:0]; - */ -static void set_hpll_od3_clk_div(int div_sel) -{ - int shift_val = 0; - int shift_sel = 0; - - /* When div 6.25, need to reset vid_pll_div */ - if (div_sel == CLK_UTIL_VID_PLL_DIV_6p25) { - msleep(1); - hd_set_reg_bits(P_RESET0_REGISTER, 1, 7, 1); - } - /* Disable the output clock */ - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 19, 1); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1); - - switch (div_sel) { - case CLK_UTIL_VID_PLL_DIV_1: shift_val = 0xFFFF; shift_sel = 0; break; - case CLK_UTIL_VID_PLL_DIV_2: shift_val = 0x0aaa; shift_sel = 0; break; - case CLK_UTIL_VID_PLL_DIV_3: shift_val = 0x0db6; shift_sel = 0; break; - case CLK_UTIL_VID_PLL_DIV_3p5: shift_val = 0x36cc; shift_sel = 1; break; - case CLK_UTIL_VID_PLL_DIV_3p75: shift_val = 0x6666; shift_sel = 2; break; - case CLK_UTIL_VID_PLL_DIV_4: shift_val = 0x0ccc; shift_sel = 0; break; - case CLK_UTIL_VID_PLL_DIV_5: shift_val = 0x739c; shift_sel = 2; break; - case CLK_UTIL_VID_PLL_DIV_6: shift_val = 0x0e38; shift_sel = 0; break; - case CLK_UTIL_VID_PLL_DIV_6p25: shift_val = 0x0000; shift_sel = 3; break; - case CLK_UTIL_VID_PLL_DIV_7: shift_val = 0x3c78; shift_sel = 1; break; - case CLK_UTIL_VID_PLL_DIV_7p5: shift_val = 0x78f0; shift_sel = 2; break; - case CLK_UTIL_VID_PLL_DIV_12: shift_val = 0x0fc0; shift_sel = 0; break; - case CLK_UTIL_VID_PLL_DIV_14: shift_val = 0x3f80; shift_sel = 1; break; - case CLK_UTIL_VID_PLL_DIV_15: shift_val = 0x7f80; shift_sel = 2; break; - case CLK_UTIL_VID_PLL_DIV_2p5: shift_val = 0x5294; shift_sel = 2; break; - case CLK_UTIL_VID_PLL_DIV_3p25: shift_val = 0x66cc; shift_sel = 2; break; - default: - printk("Error: clocks_set_vid_clk_div: Invalid parameter\n"); - break; - } - - if (shift_val == 0xffff ) { /*if divide by 1*/ - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 18, 1); - } else { - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14); - - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14); - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1); - } - /*Enable the final output clock*/ - hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 19, 1); -} - -static void set_vid_clk_div(unsigned div) -{ - check_clk_config(div); - if (div == 0) - div = 1; - hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 0, 16, 3); /*select vid_pll_clk*/ - hd_set_reg_bits(P_HHI_VID_CLK_DIV, div-1, 0, 8); - hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 7, 0, 3); -} - -static void set_hdmi_tx_pixel_div(unsigned div) -{ - check_div(); - hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, div, 16, 4); - hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 5, 1); /*enable gate*/ -} - -static void set_encp_div(unsigned div) -{ - check_div(); - hd_set_reg_bits(P_HHI_VID_CLK_DIV, div, 24, 4); - hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 2, 1); /*enable gate*/ - hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1); -} - -static void set_enci_div(unsigned div) -{ - check_div(); - hd_set_reg_bits(P_HHI_VID_CLK_DIV, div, 28, 4); - hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 0, 1); /*enable gate*/ - hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1); -} - -/* mode hpll_clk_out od1 od2(PHY) od3 - * vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div - */ -/* For colordepth 8bits */ -static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = { - { - { - HDMI_720x480i60_16x9, HDMI_720x576i50_16x9, GROUP_END - }, - 1, VIU_ENCI, 4324320, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, -1, 2 - }, - { - { - HDMI_720x576p50_16x9, HDMI_720x480p60_16x9, GROUP_END - }, - 1, VIU_ENCP, 4324320, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1 - }, - { - { - HDMI_720x576p100_16x9, HDMI_720x480p120_16x9, GROUP_END - }, - 1, VIU_ENCP, 4324320, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1 - }, - { - { - HDMI_1280x720p50_16x9, HDMI_1280x720p60_16x9, GROUP_END - }, - 1, VIU_ENCP, 5940000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080i60_16x9, HDMI_1920x1080i50_16x9, GROUP_END - }, - 1, VIU_ENCP, 5940000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080i100_16x9, HDMI_1920x1080i120_16x9, - HDMI_1280x720p100_16x9, HDMI_1280x720p120_16x9, - GROUP_END - }, - 1, VIU_ENCP, 5940000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080p60_16x9, HDMI_1920x1080p50_16x9, GROUP_END - }, - 1, VIU_ENCP, 5940000, 2, 2, 2, CLK_UTIL_VID_PLL_DIV_5, 1, 1, 1, -1 - }, - { - { - HDMI_1920x1080p30_16x9, HDMI_1920x1080p24_16x9, - HDMI_1920x1080p25_16x9, GROUP_END - }, - 1, VIU_ENCP, 5940000, 4, 2, 2, CLK_UTIL_VID_PLL_DIV_5, 1, 1, 1, -1 - }, - { - { - HDMI_3840x2160p30_16x9, HDMI_3840x2160p25_16x9, - HDMI_3840x2160p24_16x9, HDMI_4096x2160p24_256x135, - HDMI_4096x2160p25_256x135, HDMI_4096x2160p30_256x135, - HDMI_1920x1080p100_16x9, HDMI_1920x1080p120_16x9, - GROUP_END - }, - 1, VIU_ENCP, 5940000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_2160x1200p90hz, GROUP_END - }, - 1, VIU_ENCP, 5371100, 1, 2, 2, CLK_UTIL_VID_PLL_DIV_5, 1, 1, 1, -1 - }, - { - { - HDMI_3840x2160p60_16x9, HDMI_3840x2160p50_16x9, - HDMI_4096x2160p60_256x135, HDMI_4096x2160p50_256x135, - GROUP_END - }, - 1, VIU_ENCP, 5940000, 1, 1, 2, CLK_UTIL_VID_PLL_DIV_5, 1, 1, 1, -1 - }, - { - { - HDMI_4096x2160p60_256x135_Y420, - HDMI_4096x2160p50_256x135_Y420, - HDMI_3840x2160p60_16x9_Y420, - HDMI_3840x2160p50_16x9_Y420, - GROUP_END - }, - 1, VIU_ENCP, 5940000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1 - }, - /* pll setting for VESA modes */ - { - { - HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */ - GROUP_END - }, - 1, VIU_ENCP, 4028000, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_800x480p60hz, GROUP_END - }, - 1, VIU_ENCP, 4761600, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_800x600p60hz, GROUP_END - }, - 1, VIU_ENCP, 3200000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_852x480p60hz, HDMIV_854x480p60hz, GROUP_END - }, - 1, VIU_ENCP, 4838400, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1024x600p60hz, GROUP_END - }, - 1, VIU_ENCP, 4115866, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1024x768p60hz, GROUP_END - }, - 1, VIU_ENCP, 5200000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1280x768p60hz, GROUP_END - }, - 1, VIU_ENCP, 3180000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1280x800p60hz,GROUP_END - }, - 1, VIU_ENCP, 5680000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1152x864p75hz, HDMIV_1280x960p60hz, - HDMIV_1280x1024p60hz, HDMIV_1600x900p60hz, - GROUP_END - }, - 1, VIU_ENCP, 4320000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1600x1200p60hz, GROUP_END - }, - 1, VIU_ENCP, 3240000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1360x768p60hz, HDMIV_1366x768p60hz, GROUP_END - }, - 1, VIU_ENCP, 3420000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1400x1050p60hz, GROUP_END - }, - 1, VIU_ENCP, 4870000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1440x900p60hz, GROUP_END - }, - 1, VIU_ENCP, 4260000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1440x2560p60hz, GROUP_END - }, - 1, VIU_ENCP, 4897000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1440x2560p70hz, GROUP_END - }, - 1, VIU_ENCP, 5600000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1680x1050p60hz, GROUP_END - }, - 1, VIU_ENCP, 5850000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_1920x1200p60hz, GROUP_END - }, - 1, VIU_ENCP, 3865000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, - { - { - HDMIV_2560x1600p60hz, GROUP_END - }, - 1, VIU_ENCP, 3485000, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1 - }, -}; - -/* For colordepth 10bits */ -static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = { - { - { - HDMI_720x480i60_16x9, HDMI_720x576i50_16x9, GROUP_END - }, - 1, VIU_ENCI, 5405400, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, -1, 2 - }, - { - { - HDMI_720x576p50_16x9, HDMI_720x480p60_16x9, GROUP_END - }, - 1, VIU_ENCP, 5405400, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1 - }, - { - { - HDMI_720x576p100_16x9, HDMI_720x480p120_16x9, GROUP_END - }, - 1, VIU_ENCP, 5405400, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1 - }, - { - { - HDMI_1280x720p50_16x9, HDMI_1280x720p60_16x9, GROUP_END - }, - 1, VIU_ENCP, 3712500, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080i60_16x9, HDMI_1920x1080i50_16x9, GROUP_END - }, - 1, VIU_ENCP, 3712500, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080i120_16x9, HDMI_1920x1080i100_16x9, - HDMI_1280x720p100_16x9, HDMI_1280x720p120_16x9, GROUP_END - }, - 1, VIU_ENCP, 3712500, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080p60_16x9, HDMI_1920x1080p50_16x9, GROUP_END - }, - 1, VIU_ENCP, 3712500, 1, 2, 2, CLK_UTIL_VID_PLL_DIV_6p25, 1, 1, 1, -1 - }, - { - { - HDMI_1920x1080p120_16x9, HDMI_1920x1080p100_16x9, GROUP_END - }, - 1, VIU_ENCP, 3712500, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 2, -1 - }, - { - { - HDMI_1920x1080p30_16x9, HDMI_1920x1080p24_16x9, - HDMI_1920x1080p25_16x9, GROUP_END - }, - 1, VIU_ENCP, 3712500, 2, 2, 2, CLK_UTIL_VID_PLL_DIV_6p25, 1, 1, 1, -1 - }, - { - { - HDMI_4096x2160p60_256x135_Y420, HDMI_4096x2160p50_256x135_Y420, - HDMI_3840x2160p60_16x9_Y420, HDMI_3840x2160p50_16x9_Y420, GROUP_END - }, - 1, VIU_ENCP, 3712500, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1 - }, - { - { - HDMI_3840x2160p24_16x9, HDMI_3840x2160p25_16x9, - HDMI_3840x2160p30_16x9, HDMI_4096x2160p24_256x135, - HDMI_4096x2160p25_256x135, HDMI_4096x2160p30_256x135, GROUP_END - }, - 1, VIU_ENCP, 3712500, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 2, -1 - }, -}; - -/* For colordepth 12bits */ -static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = { - { - { - HDMI_720x480i60_16x9, HDMI_720x576i50_16x9, GROUP_END - }, - 1, VIU_ENCI, 3243240, 2, 4, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, -1, 2 - }, - { - { - HDMI_720x576p50_16x9, HDMI_720x480p60_16x9, GROUP_END - }, - 1, VIU_ENCP, 3243240, 2, 4, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1 - }, - { - { - HDMI_720x576p100_16x9, HDMI_720x480p120_16x9, GROUP_END - }, - 1, VIU_ENCP, 3243240, 2, 2, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1 - }, - { - { - HDMI_1280x720p50_16x9, HDMI_1280x720p60_16x9, GROUP_END - }, - 1, VIU_ENCP, 4455000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080i60_16x9, HDMI_1920x1080i50_16x9, GROUP_END - }, - 1, VIU_ENCP, 4455000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080i120_16x9, HDMI_1920x1080i100_16x9, - HDMI_1280x720p100_16x9, HDMI_1280x720p120_16x9, GROUP_END - }, - 1, VIU_ENCP, 4455000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1 - }, - { - { - HDMI_1920x1080p60_16x9, HDMI_1920x1080p50_16x9, GROUP_END - }, - 1, VIU_ENCP, 4455000, 1, 2, 2, CLK_UTIL_VID_PLL_DIV_7p5, 1, 1, 1, -1 - }, - { - { - HDMI_1920x1080p120_16x9, HDMI_1920x1080p100_16x9, GROUP_END - }, - 1, VIU_ENCP, 4455000, 1, 1, 2, CLK_UTIL_VID_PLL_DIV_3p25, 1, 2, 2, -1 - }, - { - { - HDMI_1920x1080p30_16x9, HDMI_1920x1080p24_16x9, - HDMI_1920x1080p25_16x9, GROUP_END - }, - 1, VIU_ENCP, 4455000, 2, 2, 2, CLK_UTIL_VID_PLL_DIV_7p5, 1, 1, 1, -1 - }, - { - { - HDMI_4096x2160p60_256x135_Y420, - HDMI_4096x2160p50_256x135_Y420, - HDMI_3840x2160p60_16x9_Y420, - HDMI_3840x2160p50_16x9_Y420, - GROUP_END - }, - 1, VIU_ENCP, 4455000, 1, 1, 2, CLK_UTIL_VID_PLL_DIV_3p25, 1, 2, 1, -1 - }, - { - { - HDMI_3840x2160p24_16x9, - HDMI_3840x2160p25_16x9, - HDMI_3840x2160p30_16x9, - HDMI_4096x2160p24_256x135, - HDMI_4096x2160p25_256x135, - HDMI_4096x2160p30_256x135, - GROUP_END - }, - 1, VIU_ENCP, 4455000, 1, 1, 2, CLK_UTIL_VID_PLL_DIV_3p25, 1, 2, 2, -1 - }, -}; - -void hdmitx_set_clk_(struct hdmitx_dev *hdev) -{ - int i = 0; - int j = 0; - struct hw_enc_clk_val_group *p_enc =NULL; - enum hdmi_vic vic = hdev->vic; - enum hdmi_color_format cs = hdev->para->cs; - enum hdmi_color_depth cd = hdev->para->cd; - - /* YUV 422 always use 24B mode */ - if (cs == HDMI_COLOR_FORMAT_422) - cd = HDMI_COLOR_DEPTH_24B; - - if (cd == HDMI_COLOR_DEPTH_24B) { - p_enc = &setting_enc_clk_val_24[0]; - for (j = 0; j < sizeof(setting_enc_clk_val_24) - / sizeof(struct hw_enc_clk_val_group); j++) { - for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] - != GROUP_END)); i++) { - if (vic == p_enc[j].group[i]) - goto next; - } - } - if (j == sizeof(setting_enc_clk_val_24) - / sizeof(struct hw_enc_clk_val_group)) { - pr_info("Not find VIC = %d for hpll setting\n", vic); - return; - } - } else if (cd == HDMI_COLOR_DEPTH_30B) { - p_enc = &setting_enc_clk_val_30[0]; - for (j = 0; j < sizeof(setting_enc_clk_val_30) - / sizeof(struct hw_enc_clk_val_group); j++) { - for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] - != GROUP_END)); i++) { - if (vic == p_enc[j].group[i]) - goto next; - } - } - if (j == sizeof(setting_enc_clk_val_30) / - sizeof(struct hw_enc_clk_val_group)) { - pr_info("Not find VIC = %d for hpll setting\n", vic); - return; - } - } else if (cd == HDMI_COLOR_DEPTH_36B) { - p_enc = &setting_enc_clk_val_36[0]; - for (j = 0; j < sizeof(setting_enc_clk_val_36) - / sizeof(struct hw_enc_clk_val_group); j++) { - for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] - != GROUP_END)); i++) { - if (vic == p_enc[j].group[i]) - goto next; - } - } - if (j == sizeof(setting_enc_clk_val_36) / - sizeof(struct hw_enc_clk_val_group)) { - pr_info("Not find VIC = %d for hpll setting\n", vic); - return; - } - } else { - pr_info("not support colordepth 48bits\n"); - return; - } - -next: - set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type); - set_hdmitx_sys_clk(); - set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev); - if (!env_get("sspll_dis")) - set_hpll_sspll(hdev); - set_hpll_od1(p_enc[j].od1); - set_hpll_od2(p_enc[j].od2); - set_hpll_od3(p_enc[j].od3); - set_hpll_od3_clk_div(p_enc[j].vid_pll_div); - printk("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div); - set_vid_clk_div(p_enc[j].vid_clk_div); - set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div); - set_encp_div(p_enc[j].encp_div); - set_enci_div(p_enc[j].enci_div); -} - -static int likely_frac_rate_mode(char *m) -{ - if (strstr(m, "24hz") || strstr(m, "30hz") || strstr(m, "60hz") - || strstr(m, "120hz") || strstr(m, "240hz")) - return 1; - else - return 0; -} - -void hdmitx_set_clk(struct hdmitx_dev *hdev) -{ - char *frac_rate_str = NULL; - - frac_rate_str = env_get("frac_rate_policy"); - if (frac_rate_str && (frac_rate_str[0] == '0')) - hdev->frac_rate_policy = 0; - else if (likely_frac_rate_mode(hdev->para->ext_name)) - hdev->frac_rate_policy = 1; - - hdmitx_set_clk_(hdev); -} -
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_edid_parsing.c b/drivers/amlogic/media/vout/hdmitx/hdmi_edid_parsing.c deleted file mode 100644 index 22906cb..0000000 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_edid_parsing.c +++ /dev/null
@@ -1,496 +0,0 @@ -#include <common.h> -#include <linux/stddef.h> -#include <amlogic/media/vout/hdmitx.h> - -#define CEA_DATA_BLOCK_COLLECTION_ADDR_1StP 0x04 -#define VIDEO_TAG 0x40 -#define AUDIO_TAG 0x20 -#define VENDOR_TAG 0x60 -#define SPEAKER_TAG 0x80 - -#define HDMI_EDID_BLOCK_TYPE_RESERVED 0 -#define HDMI_EDID_BLOCK_TYPE_AUDIO 1 -#define HDMI_EDID_BLOCK_TYPE_VIDEO 2 -#define HDMI_EDID_BLOCK_TYPE_VENDER 3 -#define HDMI_EDID_BLOCK_TYPE_SPEAKER 4 -#define HDMI_EDID_BLOCK_TYPE_VESA 5 -#define HDMI_EDID_BLOCK_TYPE_RESERVED2 6 -#define HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG 7 - -#define EXTENSION_VENDOR_SPECIFIC 0x1 -#define EXTENSION_COLORMETRY_TAG 0x5 -/* DRM stands for "Dynamic Range and Mastering " */ -#define EXTENSION_DRM_TAG 0x6 -/* Video Format Preference Data block */ -#define EXTENSION_VFPDB_TAG 0xd -#define EXTENSION_Y420_VDB_TAG 0xe -#define EXTENSION_Y420_CMDB_TAG 0xf - -#define EDID_DETAILED_TIMING_DES_BLOCK0_POS 0x36 -#define EDID_DETAILED_TIMING_DES_BLOCK1_POS 0x48 -#define EDID_DETAILED_TIMING_DES_BLOCK2_POS 0x5A -#define EDID_DETAILED_TIMING_DES_BLOCK3_POS 0x6C - -/* EDID Descrptor Tag */ -#define TAG_PRODUCT_SERIAL_NUMBER 0xFF -#define TAG_ALPHA_DATA_STRING 0xFE -#define TAG_RANGE_LIMITS 0xFD -#define TAG_DISPLAY_PRODUCT_NAME_STRING 0xFC /* MONITOR NAME */ -#define TAG_COLOR_POINT_DATA 0xFB -#define TAG_STANDARD_TIMINGS 0xFA -#define TAG_DISPLAY_COLOR_MANAGEMENT 0xF9 -#define TAG_CVT_TIMING_CODES 0xF8 -#define TAG_ESTABLISHED_TIMING_III 0xF7 -#define TAG_DUMMY_DES 0x10 - -/* retrun 1 valid edid */ -static int check_dvi_hdmi_edid_valid(unsigned char *buf) -{ - unsigned int chksum = 0; - unsigned int i = 0; - - /* check block 0 first 8 bytes */ - if ((buf[0] != 0) && (buf[7] != 0)) - return 0; - for (i = 1; i < 7; i++) { - if (buf[i] != 0xff) - return 0; - } - - /* check block 0 checksum */ - for (chksum = 0, i = 0; i < 0x80; i++) - chksum += buf[i]; - if ((chksum & 0xff) != 0) - return 0; - - if (buf[0x7e] == 0)/* check Extension flag at block 0 */ - return 1; - /* check block 1 extension tag */ - else if (!((buf[0x80] == 0x2) || (buf[0x80] == 0xf0))) - return 0; - - /* check block 1 checksum */ - for (chksum = 0, i = 0x80; i < 0x100; i++) - chksum += buf[i]; - if ((chksum & 0xff) != 0) - return 0; - - /* check block 2 checksum */ - if (buf[0x7e] > 1) { - for (chksum = 0, i = 0x100; i < 0x180; i++) - chksum += buf[i]; - if ((chksum & 0xff) != 0) - return 0; - } - - /* check block 3 checksum */ - if (buf[0x7e] > 2) { - for (chksum = 0, i = 0x180; i < 0x200; i++) - chksum += buf[i]; - if ((chksum & 0xff) != 0) - return 0; - } - - return 1; -} - -static void dump_dtd_info(struct dtd *t) -{ - return; /* debug only */ - printk("%s[%d]\n", __func__, __LINE__); -#define PR(a) pr_info("%s %d\n", #a, t->a) - PR(pixel_clock); - PR(h_active); - PR(h_blank); - PR(v_active); - PR(v_blank); - PR(h_sync_offset); - PR(h_sync); - PR(v_sync_offset); - PR(v_sync); -} - -static void Edid_DTD_parsing(struct rx_cap *pRXCap, unsigned char *data) -{ - struct hdmi_format_para *para = NULL; - struct dtd *t = &pRXCap->dtd[pRXCap->dtd_idx]; - - memset(t, 0, sizeof(struct dtd)); - t->pixel_clock = data[0] + (data[1] << 8); - t->h_active = (((data[4] >> 4) & 0xf) << 8) + data[2]; - t->h_blank = ((data[4] & 0xf) << 8) + data[3]; - t->v_active = (((data[7] >> 4) & 0xf) << 8) + data[5]; - t->v_blank = ((data[7] & 0xf) << 8) + data[6]; - t->h_sync_offset = (((data[11] >> 6) & 0x3) << 8) + data[8]; - t->h_sync = (((data[11] >> 4) & 0x3) << 8) + data[9]; - t->v_sync_offset = (((data[11] >> 2) & 0x3) << 4) + - ((data[10] >> 4) & 0xf); - t->v_sync = (((data[11] >> 0) & 0x3) << 4) + ((data[10] >> 0) & 0xf); -/* - * Special handling of 1080i60hz, 1080i50hz - */ - if ((t->pixel_clock == 7425) && (t->h_active == 1920) && - (t->v_active == 1080)) { - t->v_active = t->v_active / 2; - t->v_blank = t->v_blank / 2; - } -/* - * Special handling of 480i60hz, 576i50hz - */ - if (((((t->flags) >> 1) & 0x3) == 0) && (t->h_active == 1440)) { - if (t->pixel_clock == 2700) /* 576i50hz */ - goto next; - if ((t->pixel_clock - 2700) < 10) /* 480i60hz */ - t->pixel_clock = 2702; -next: - t->v_active = t->v_active / 2; - t->v_blank = t->v_blank / 2; - } -/* - * call hdmi_match_dtd_paras() to check t is matched with VIC - */ - para = hdmi_match_dtd_paras(t); - if (para) { - t->vic = para->vic; - pRXCap->preferred_mode = pRXCap->dtd[0].vic; /* Select dtd0 */ - if (0) /* debug only */ - pr_info("hdmitx: get dtd%d vic: %d\n", - pRXCap->dtd_idx, para->vic); - pRXCap->dtd_idx++; - } else - dump_dtd_info(t); -} - -/* parse Sink 4k2k information */ -static void hdmitx_edid_4k2k_parse(struct rx_cap *pRXCap, unsigned char *dat, - unsigned size) -{ - if ((size > 4) || (size == 0)) { - return; - } - while (size--) { - if (*dat == 1) - pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p30_16x9; - else if (*dat == 2) - pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p25_16x9; - else if (*dat == 3) - pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p24_16x9; - else if (*dat == 4) - pRXCap->VIC[pRXCap->VIC_count] = HDMI_4096x2160p24_256x135; - else - ; - dat++; - pRXCap->VIC_count++; - } -} - -static void set_vsdb_dc_420_cap(struct rx_cap *pRXCap, - unsigned char *edid_offset) -{ - pRXCap->dc_30bit_420 = !!(edid_offset[6] & (1 << 0)); - pRXCap->dc_36bit_420 = !!(edid_offset[6] & (1 << 1)); - pRXCap->dc_48bit_420 = !!(edid_offset[6] & (1 << 2)); -} - -static int Edid_ParsingY420VDBBlock(struct rx_cap *pRXCap, - unsigned char *buf) -{ - unsigned char tag = 0, ext_tag = 0, data_end = 0; - unsigned int pos = 0; - int i = 0, found = 0; - - tag = (buf[pos] >> 5) & 0x7; - data_end = (buf[pos] & 0x1f)+1; - pos++; - ext_tag = buf[pos]; - - if ((tag != 0x7) || (ext_tag != 0xe)) - goto INVALID_Y420VDB; - - pos++; - while (pos < data_end) { - if (pRXCap->VIC_count < VIC_MAX_NUM) { - for (i = 0; i < pRXCap->VIC_count; i++) { - if (pRXCap->VIC[i] == buf[pos]) { - pRXCap->VIC[i] = - HDMITX_VIC420_OFFSET + buf[pos]; - found = 1; - /* Here we do not break,because - some EDID may have the same - repeated VICs - */ - } - } - if (0 == found) { - pRXCap->VIC[pRXCap->VIC_count] = - HDMITX_VIC420_OFFSET + buf[pos]; - pRXCap->VIC_count++; - } - } - pos++; - } - - return 0; - -INVALID_Y420VDB: - pr_info("[%s] it's not a valid y420vdb!\n", __func__); - return -1; -} - -static int Edid_ParsingY420CMDBBlock(struct rx_cap *pRXCap, - unsigned char *buf) -{ - /* TODO */ - return 0; -} - -static int Edid_Y420CMDB_PostProcess(struct rx_cap *pRXCap) -{ - /* TODO */ - return 0; -} - -static int Edid_ParsingVFPDB(struct rx_cap *pRXCap, unsigned char *buf) -{ - unsigned int len = buf[0] & 0x1f; - enum hdmi_vic svr = HDMI_unkown; - - if (buf[1] != EXTENSION_VFPDB_TAG) - return 0; - if (len < 2) - return 0; - - svr = buf[2]; - if (((svr >= 1) && (svr <= 127)) || - ((svr >= 193) && (svr <= 253))) { - pRXCap->flag_vfpdb = 1; - pRXCap->preferred_mode = svr; - pr_info("preferred mode 0 srv %d\n", pRXCap->preferred_mode); - return 1; - } - if ((svr >= 129) && (svr <= 144)) { - pRXCap->flag_vfpdb = 1; - pRXCap->preferred_mode = pRXCap->dtd[svr - 129].vic; - pr_info("preferred mode 0 dtd %d\n", pRXCap->preferred_mode); - return 1; - } - return 0; -} - -static int hdmitx_edid_block_parse(struct rx_cap *pRXCap, - unsigned char *BlockBuf) -{ - unsigned char offset, End; - unsigned char count; - unsigned char tag; - int i, tmp, idx; - unsigned char *vfpdb_offset = NULL; - - if (BlockBuf[0] != 0x02) - return -1; /* not a CEA BLOCK. */ - End = BlockBuf[2]; /* CEA description. */ - pRXCap->native_Mode = BlockBuf[3]; - pRXCap->number_of_dtd += BlockBuf[3] & 0xf; - /* bit 5 (YCBCR 4:4:4) = 1 if sink device supports YCBCR 4:4:4 - * in addition to RGB; - * bit 4 (YCBCR 4:2:2) = 1 if sink device supports YCBCR 4:2:2 - * in addition to RGB - */ - pRXCap->pref_colorspace = BlockBuf[3] & 0x30; - - pRXCap->native_VIC = 0xff; - - for (offset = 4 ; offset < End ; ) { - tag = BlockBuf[offset] >> 5; - count = BlockBuf[offset] & 0x1f; - switch (tag) { - case HDMI_EDID_BLOCK_TYPE_AUDIO: - offset++; - offset += count; - break; - - case HDMI_EDID_BLOCK_TYPE_VIDEO: - offset++; - for (i = 0 ; i < count ; i++) { - unsigned char VIC; - VIC = BlockBuf[offset + i] & (~0x80); - pRXCap->VIC[pRXCap->VIC_count] = VIC; - if (BlockBuf[offset + i] & 0x80) - pRXCap->native_VIC = VIC; - pRXCap->VIC_count++; - } - offset += count; - break; - - case HDMI_EDID_BLOCK_TYPE_VENDER: - offset++; - if ((BlockBuf[offset] == 0x03) && - (BlockBuf[offset+1] == 0x0c) && - (BlockBuf[offset+2] == 0x00)) - pRXCap->IEEEOUI = 0x000c03; - else - goto case_hf; - pRXCap->ColorDeepSupport = - (unsigned long)BlockBuf[offset+5]; - pRXCap->Max_TMDS_Clock1 = - (unsigned long)BlockBuf[offset+6]; - if (count > 7) { - tmp = BlockBuf[offset+7]; - idx = offset + 8; - if (tmp & (1<<6)) - idx += 2; - if (tmp & (1<<7)) - idx += 2; - if (tmp & (1<<5)) { - idx += 1; - /* valid 4k */ - if (BlockBuf[idx] & 0xe0) { - hdmitx_edid_4k2k_parse( - pRXCap, - &BlockBuf[idx + 1], - BlockBuf[idx] >> 5); - } - } - } - goto case_next; -case_hf: - if ((BlockBuf[offset] == 0xd8) && - (BlockBuf[offset+1] == 0x5d) && - (BlockBuf[offset+2] == 0xc4)) - pRXCap->HF_IEEEOUI = 0xd85dc4; - pRXCap->Max_TMDS_Clock2 = BlockBuf[offset+4]; - pRXCap->scdc_present = - !!(BlockBuf[offset+5] & (1 << 7)); - pRXCap->scdc_rr_capable = - !!(BlockBuf[offset+5] & (1 << 6)); - pRXCap->lte_340mcsc_scramble = - !!(BlockBuf[offset+5] & (1 << 3)); - set_vsdb_dc_420_cap(pRXCap, - &BlockBuf[offset]); -case_next: - offset += count; /* ignore the remaind. */ - break; - - case HDMI_EDID_BLOCK_TYPE_SPEAKER: - offset++; - offset += count; - break; - - case HDMI_EDID_BLOCK_TYPE_VESA: - offset++; - offset += count; - break; - - case HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG: - { - unsigned char ext_tag = 0; - - ext_tag = BlockBuf[offset+1]; - switch (ext_tag) { - case EXTENSION_VENDOR_SPECIFIC: - break; - case EXTENSION_COLORMETRY_TAG: - pRXCap->colorimetry_data = - BlockBuf[offset + 2]; - break; - case EXTENSION_DRM_TAG: - break; - case EXTENSION_VFPDB_TAG: -/* Just record VFPDB offset address, call Edid_ParsingVFPDB() after DTD - * parsing, in case that - * SVR >=129 and SVR <=144, Interpret as the Kth DTD in the EDID, - * where K = SVR – 128 (for K=1 to 16) - */ - vfpdb_offset = &BlockBuf[offset]; - break; - case EXTENSION_Y420_VDB_TAG: - Edid_ParsingY420VDBBlock(pRXCap, - &BlockBuf[offset]); - break; - case EXTENSION_Y420_CMDB_TAG: - Edid_ParsingY420CMDBBlock(pRXCap, - &BlockBuf[offset]); - break; - default: - break; - } - } - offset += count+1; - break; - - case HDMI_EDID_BLOCK_TYPE_RESERVED: - offset++; - offset += count; - break; - - case HDMI_EDID_BLOCK_TYPE_RESERVED2: - offset++; - offset += count; - break; - - default: - break; - } - } - - Edid_Y420CMDB_PostProcess(pRXCap); - idx = BlockBuf[3] & 0xf; - for (i = 0; i < idx; i++) - Edid_DTD_parsing(pRXCap, &BlockBuf[BlockBuf[2] + i * 18]); - if (vfpdb_offset) - Edid_ParsingVFPDB(pRXCap, vfpdb_offset); - - return 0; -} - -/* - * Parsing RAW EDID data from edid to pRXCap - */ -unsigned int hdmi_edid_parsing(unsigned char *EDID_buf, struct rx_cap *pRXCap) -{ - int i; - int BlockCount = EDID_buf[126] + 1; - int idx[4]; - - /* Clear all parsing data */ - memset(pRXCap, 0, sizeof(struct rx_cap)); - pRXCap->IEEEOUI = 0x000c03; /* Default is HDMI device */ - - /* If edid data corrupted, no parse */ - if (check_dvi_hdmi_edid_valid(EDID_buf) == 0) - return 0; - - idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS; - idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS; - idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS; - idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS; - for (i = 0; i < 4; i++) { - if ((EDID_buf[idx[i]]) && (EDID_buf[idx[i] + 1])) - Edid_DTD_parsing(pRXCap, &EDID_buf[idx[i]]); - } - - if (BlockCount == 1) - pRXCap->IEEEOUI = 0; - - for (i = 1 ; i <= BlockCount ; i++) { - if (EDID_buf[i*128+0] == 0x2) - hdmitx_edid_block_parse(pRXCap, &(EDID_buf[i*128])); - } - -/* - * Because DTDs are not able to represent some Video Formats, which can be - * represented as SVDs and might be preferred by Sinks, the first DTD in the - * base EDID data structure and the first SVD in the first CEA Extension can - * differ. When the first DTD and SVD do not match and the total number of - * DTDs defining Native Video Formats in the whole EDID is zero, the first - * SVD shall take precedence. - */ - if (!pRXCap->flag_vfpdb && (pRXCap->preferred_mode != pRXCap->VIC[0]) && - (pRXCap->number_of_dtd == 0)) { - pr_info("hdmitx: edid: change preferred_mode from %d to %d\n", - pRXCap->preferred_mode, pRXCap->VIC[0]); - pRXCap->preferred_mode = pRXCap->VIC[0]; - } - - return 1; -}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmi_parameters.c deleted file mode 100644 index 1e796ed..0000000 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_parameters.c +++ /dev/null
@@ -1,2163 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#include <common.h> -#include <linux/stddef.h> -#include <amlogic/media/vout/hdmitx.h> - -static struct hdmi_format_para fmt_para_1920x1080p60_16x9 = { - .vic = HDMI_1920x1080p60_16x9, - .name = "1920x1080p60hz", - .sname = "1080p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 148500, - .timing = { - .pixel_freq = 148500, - .h_freq = 67500, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2200, - .h_blank = 280, - .h_front = 88, - .h_sync = 44, - .h_back = 148, - .v_active = 1080, - .v_total = 1125, - .v_blank = 45, - .v_front = 4, - .v_sync = 5, - .v_back = 36, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080p30_16x9 = { - .vic = HDMI_1920x1080p30_16x9, - .name = "1920x1080p30hz", - .sname = "1080p30hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 74250, - .timing = { - .pixel_freq = 74250, - .h_freq = 67500, - .v_freq = 30000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2200, - .h_blank = 280, - .h_front = 88, - .h_sync = 44, - .h_back = 148, - .v_active = 1080, - .v_total = 1125, - .v_blank = 45, - .v_front = 4, - .v_sync = 5, - .v_back = 36, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080p50_16x9 = { - .vic = HDMI_1920x1080p50_16x9, - .name = "1920x1080p50hz", - .sname = "1080p50hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 148500, - .timing = { - .pixel_freq = 148500, - .h_freq = 56250, - .v_freq = 50000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2640, - .h_blank = 720, - .h_front = 528, - .h_sync = 44, - .h_back = 148, - .v_active = 1080, - .v_total = 1125, - .v_blank = 45, - .v_front = 4, - .v_sync = 5, - .v_back = 36, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080p100_16x9 = { - .vic = HDMI_1920x1080p100_16x9, - .name = "1920x1080p100hz", - .sname = "1080p100hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 297000, - .h_freq = 112500, - .v_freq = 100000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2640, - .h_blank = 720, - .h_front = 528, - .h_sync = 44, - .h_back = 148, - .v_active = 1080, - .v_total = 1125, - .v_blank = 45, - .v_front = 4, - .v_sync = 5, - .v_back = 36, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080p120_16x9 = { - .vic = HDMI_1920x1080p120_16x9, - .name = "1920x1080p120hz", - .sname = "1080p120hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 297000, - .h_freq = 135000, - .v_freq = 120000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2200, - .h_blank = 280, - .h_front = 88, - .h_sync = 44, - .h_back = 148, - .v_active = 1080, - .v_total = 1125, - .v_blank = 45, - .v_front = 4, - .v_sync = 5, - .v_back = 36, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080p25_16x9 = { - .vic = HDMI_1920x1080p25_16x9, - .name = "1920x1080p25hz", - .sname = "1080p25hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 148500, - .timing = { - .pixel_freq = 148500, - .h_freq = 56250, - .v_freq = 50000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2640, - .h_blank = 720, - .h_front = 528, - .h_sync = 44, - .h_back = 148, - .v_active = 1080, - .v_total = 1125, - .v_blank = 45, - .v_front = 4, - .v_sync = 5, - .v_back = 36, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080p24_16x9 = { - .vic = HDMI_1920x1080p24_16x9, - .name = "1920x1080p24hz", - .sname = "1080p24hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 74250, - .timing = { - .pixel_freq = 74250, - .h_freq = 27000, - .v_freq = 24000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2750, - .h_blank = 830, - .h_front = 638, - .h_sync = 44, - .h_back = 148, - .v_active = 1080, - .v_total = 1125, - .v_blank = 45, - .v_front = 4, - .v_sync = 5, - .v_back = 36, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_3840x2160p30_16x9 = { - .vic = HDMI_3840x2160p30_16x9, - .name = "3840x2160p30hz", - .sname = "2160p30hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 297000, - .h_freq = 67500, - .v_freq = 30000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 3840, - .h_total = 4400, - .h_blank = 560, - .h_front = 176, - .h_sync = 88, - .h_back = 296, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_3840x2160p60_16x9 = { - .vic = HDMI_3840x2160p60_16x9, - .name = "3840x2160p60hz", - .sname = "2160p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 1, - .tmds_clk_div40 = 1, - .tmds_clk = 594000, - .timing = { - .pixel_freq = 594000, - .h_freq = 135000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 3840, - .h_total = 4400, - .h_blank = 560, - .h_front = 176, - .h_sync = 88, - .h_back = 296, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_3840x2160p60_y420_16x9 = { - .vic = HDMI_3840x2160p60_16x9_Y420, - .name = "3840x2160p60hz420", - .sname = "2160p60hz420", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 1, - .tmds_clk_div40 = 1, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 594000, - .h_freq = 135000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 3840 / 2, - .h_total = 4400 / 2, - .h_blank = 560 / 2, - .h_front = 176 / 2, - .h_sync = 88 / 2, - .h_back = 296 / 2, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_3840x2160p50_16x9 = { - .vic = HDMI_3840x2160p50_16x9, - .name = "3840x2160p50hz", - .sname = "2160p50hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 1, - .tmds_clk_div40 = 1, - .tmds_clk = 594000, - .timing = { - .pixel_freq = 594000, - .h_freq = 112500, - .v_freq = 50000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 3840, - .h_total = 5280, - .h_blank = 1440, - .h_front = 1056, - .h_sync = 88, - .h_back = 296, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_3840x2160p50_y420_16x9 = { - .vic = HDMI_3840x2160p50_16x9_Y420, - .name = "3840x2160p50hz420", - .sname = "2160p50hz420", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 1, - .tmds_clk_div40 = 1, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 594000, - .h_freq = 112500, - .v_freq = 50000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 3840 / 2, - .h_total = 5280 / 2, - .h_blank = 1440 / 2, - .h_front = 1056 / 2, - .h_sync = 88 / 2, - .h_back = 296 / 2, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_3840x2160p25_16x9 = { - .vic = HDMI_3840x2160p25_16x9, - .name = "3840x2160p25hz", - .sname = "2160p25hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 297000, - .h_freq = 56250, - .v_freq = 25000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 3840, - .h_total = 5280, - .h_blank = 1440, - .h_front = 1056, - .h_sync = 88, - .h_back = 296, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_3840x2160p24_16x9 = { - .vic = HDMI_3840x2160p24_16x9, - .name = "3840x2160p24hz", - .sname = "2160p24hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 297000, - .h_freq = 54000, - .v_freq = 24000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 3840, - .h_total = 5500, - .h_blank = 1660, - .h_front = 1276, - .h_sync = 88, - .h_back = 296, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_4096x2160p24_256x135 = { - .vic = HDMI_4096x2160p24_256x135, - .name = "4096x2160p24hz", - .sname = "smpte24hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 297000, - .h_freq = 54000, - .v_freq = 24000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 4096, - .h_total = 5500, - .h_blank = 1404, - .h_front = 1020, - .h_sync = 88, - .h_back = 296, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_4096x2160p25_256x135 = { - .vic = HDMI_4096x2160p25_256x135, - .name = "4096x2160p25hz", - .sname = "smpte25hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 297000, - .h_freq = 56250, - .v_freq = 25000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 4096, - .h_total = 5280, - .h_blank = 1184, - .h_front = 968, - .h_sync = 88, - .h_back = 128, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_4096x2160p30_256x135 = { - .vic = HDMI_4096x2160p30_256x135, - .name = "4096x2160p30hz", - .sname = "smpte30hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 297000, - .h_freq = 67500, - .v_freq = 30000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 4096, - .h_total = 4400, - .h_blank = 304, - .h_front = 88, - .h_sync = 88, - .h_back = 128, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_4096x2160p50_256x135 = { - .vic = HDMI_4096x2160p50_256x135, - .name = "4096x2160p50hz", - .sname = "smpte50hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 1, - .tmds_clk_div40 = 1, - .tmds_clk = 594000, - .timing = { - .pixel_freq = 594000, - .h_freq = 112500, - .v_freq = 50000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 4096, - .h_total = 5280, - .h_blank = 1184, - .h_front = 968, - .h_sync = 88, - .h_back = 128, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_4096x2160p50_y420_256x135 = { - .vic = HDMI_4096x2160p50_256x135_Y420, - .name = "4096x2160p50hz420", - .sname = "smpte50hz420", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 1, - .tmds_clk_div40 = 1, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 594000, - .h_freq = 112500, - .v_freq = 50000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 4096 / 2, - .h_total = 5280 / 2, - .h_blank = 1184 / 2, - .h_front = 968 / 2, - .h_sync = 88 / 2, - .h_back = 128 / 2, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_4096x2160p60_256x135 = { - .vic = HDMI_4096x2160p60_256x135, - .name = "4096x2160p60hz", - .sname = "smpte60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 1, - .tmds_clk_div40 = 1, - .tmds_clk = 594000, - .timing = { - .pixel_freq = 594000, - .h_freq = 135000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 4096, - .h_total = 4400, - .h_blank = 304, - .h_front = 88, - .h_sync = 88, - .h_back = 128, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_4096x2160p60_y420_256x135 = { - .vic = HDMI_4096x2160p60_256x135_Y420, - .name = "4096x2160p60hz420", - .sname = "smpte60hz420", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 1, - .tmds_clk_div40 = 1, - .tmds_clk = 297000, - .timing = { - .pixel_freq = 594000, - .h_freq = 135000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 4096 / 2, - .h_total = 4400 / 2, - .h_blank = 304 / 2, - .h_front = 88 / 2, - .h_sync = 88 / 2, - .h_back = 128 / 2, - .v_active = 2160, - .v_total = 2250, - .v_blank = 90, - .v_front = 8, - .v_sync = 10, - .v_back = 72, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080i60_16x9 = { - .vic = HDMI_1920x1080i60_16x9, - .name = "1920x1080i60hz", - .sname = "1080i60hz", - .pixel_repetition_factor = 0, - .progress_mode = 0, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 74250, - .timing = { - .pixel_freq = 74250, - .h_freq = 33750, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2200, - .h_blank = 280, - .h_front = 88, - .h_sync = 44, - .h_back = 148, - .v_active = 1080/2, - .v_total = 1125, - .v_blank = 45/2, - .v_front = 2, - .v_sync = 5, - .v_back = 15, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080i50_16x9 = { - .vic = HDMI_1920x1080i50_16x9, - .name = "1920x1080i50hz", - .sname = "1080i50hz", - .pixel_repetition_factor = 0, - .progress_mode = 0, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 74250, - .timing = { - .pixel_freq = 74250, - .h_freq = 28125, - .v_freq = 50000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2640, - .h_blank = 720, - .h_front = 528, - .h_sync = 44, - .h_back = 148, - .v_active = 1080/2, - .v_total = 1125, - .v_blank = 45/2, - .v_front = 2, - .v_sync = 5, - .v_back = 15, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080i100_16x9 = { - .vic = HDMI_1920x1080i100_16x9, - .name = "1920x1080i100hz", - .sname = "1080i100hz", - .pixel_repetition_factor = 0, - .progress_mode = 0, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 148500, - .timing = { - .pixel_freq = 148500, - .h_freq = 56250, - .v_freq = 100000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2640, - .h_blank = 720, - .h_front = 528, - .h_sync = 44, - .h_back = 148, - .v_active = 1080/2, - .v_total = 1125, - .v_blank = 45/2, - .v_front = 2, - .v_sync = 5, - .v_back = 15, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1920x1080i120_16x9 = { - .vic = HDMI_1920x1080i120_16x9, - .name = "1920x1080i120hz", - .sname = "1080i120hz", - .pixel_repetition_factor = 0, - .progress_mode = 0, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 148500, - .timing = { - .pixel_freq = 148500, - .h_freq = 67500, - .v_freq = 120000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2200, - .h_blank = 280, - .h_front = 88, - .h_sync = 44, - .h_back = 148, - .v_active = 1080/2, - .v_total = 1125, - .v_blank = 45/2, - .v_front = 2, - .v_sync = 5, - .v_back = 15, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1280x720p60_16x9 = { - .vic = HDMI_1280x720p60_16x9, - .name = "1280x720p60hz", - .sname = "720p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 74250, - .timing = { - .pixel_freq = 74250, - .h_freq = 45000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = 1650, - .h_blank = 370, - .h_front = 110, - .h_sync = 40, - .h_back = 220, - .v_active = 720, - .v_total = 750, - .v_blank = 30, - .v_front = 5, - .v_sync = 5, - .v_back = 20, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1280x720p50_16x9 = { - .vic = HDMI_1280x720p50_16x9, - .name = "1280x720p50hz", - .sname = "720p50hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 74250, - .timing = { - .pixel_freq = 74250, - .h_freq = 37500, - .v_freq = 50000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = 1980, - .h_blank = 700, - .h_front = 440, - .h_sync = 40, - .h_back = 220, - .v_active = 720, - .v_total = 750, - .v_blank = 30, - .v_front = 5, - .v_sync = 5, - .v_back = 20, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1280x720p100_16x9 = { - .vic = HDMI_1280x720p100_16x9, - .name = "1280x720p100hz", - .sname = "720p100hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 148500, - .timing = { - .pixel_freq = 148500, - .h_freq = 75000, - .v_freq = 100000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = 1980, - .h_blank = 700, - .h_front = 440, - .h_sync = 40, - .h_back = 220, - .v_active = 720, - .v_total = 750, - .v_blank = 30, - .v_front = 5, - .v_sync = 5, - .v_back = 20, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_1280x720p120_16x9 = { - .vic = HDMI_1280x720p120_16x9, - .name = "1280x720p120hz", - .sname = "720p120hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 148500, - .timing = { - .pixel_freq = 148500, - .h_freq = 90000, - .v_freq = 120000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = 1650, - .h_blank = 370, - .h_front = 110, - .h_sync = 40, - .h_back = 220, - .v_active = 720, - .v_total = 750, - .v_blank = 30, - .v_front = 5, - .v_sync = 5, - .v_back = 20, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_720x480p60_16x9 = { - .vic = HDMI_720x480p60_16x9, - .name = "720x480p60hz", - .sname = "480p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 27000, - .timing = { - .pixel_freq = 27000, - .h_freq = 31469, - .v_freq = 59940, - .vsync_polarity = 0, - .hsync_polarity = 0, - .h_active = 720, - .h_total = 858, - .h_blank = 138, - .h_front = 16, - .h_sync = 62, - .h_back = 60, - .v_active = 480, - .v_total = 525, - .v_blank = 45, - .v_front = 9, - .v_sync = 6, - .v_back = 30, - .v_sync_ln = 7, - }, -}; - -static struct hdmi_format_para fmt_para_720x480p120_16x9 = { - .vic = HDMI_720x480p120_16x9, - .name = "720x480p120hz", - .sname = "480p120hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 54000, - .timing = { - .pixel_freq = 54000, - .h_freq = 62937, - .v_freq = 119880, - .vsync_polarity = 0, - .hsync_polarity = 0, - .h_active = 720, - .h_total = 858, - .h_blank = 138, - .h_front = 16, - .h_sync = 62, - .h_back = 60, - .v_active = 480, - .v_total = 525, - .v_blank = 45, - .v_front = 9, - .v_sync = 6, - .v_back = 30, - .v_sync_ln = 7, - }, -}; - -static struct hdmi_format_para fmt_para_720x480i60_16x9 = { - .vic = HDMI_720x480i60_16x9, - .name = "720x480i60hz", - .sname = "480i60hz", - .pixel_repetition_factor = 1, - .progress_mode = 0, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 27000, - .timing = { - .pixel_freq = 27000, - .h_freq = 15734, - .v_freq = 59940, - .vsync_polarity = 0, - .hsync_polarity = 0, - .h_active = 1440, - .h_total = 1716, - .h_blank = 276, - .h_front = 38, - .h_sync = 124, - .h_back = 114, - .v_active = 480/2, - .v_total = 525, - .v_blank = 45/2, - .v_front = 4, - .v_sync = 3, - .v_back = 15, - .v_sync_ln = 4, - }, -}; - -static struct hdmi_format_para fmt_para_720x576p50_16x9 = { - .vic = HDMI_720x576p50_16x9, - .name = "720x576p50hz", - .sname = "576p50hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 27000, - .timing = { - .pixel_freq = 27000, - .h_freq = 31250, - .v_freq = 50000, - .vsync_polarity = 0, - .hsync_polarity = 0, - .h_active = 720, - .h_total = 864, - .h_blank = 144, - .h_front = 12, - .h_sync = 64, - .h_back = 68, - .v_active = 576, - .v_total = 625, - .v_blank = 49, - .v_front = 5, - .v_sync = 5, - .v_back = 39, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_720x576p100_16x9 = { - .vic = HDMI_720x576p100_16x9, - .name = "720x576p100hz", - .sname = "576p100hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 54000, - .timing = { - .pixel_freq = 54000, - .h_freq = 62500, - .v_freq = 100000, - .vsync_polarity = 0, - .hsync_polarity = 0, - .h_active = 720, - .h_total = 864, - .h_blank = 144, - .h_front = 12, - .h_sync = 64, - .h_back = 68, - .v_active = 576, - .v_total = 625, - .v_blank = 49, - .v_front = 5, - .v_sync = 5, - .v_back = 39, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_720x576i50_16x9 = { - .vic = HDMI_720x576i50_16x9, - .name = "720x576i50hz", - .sname = "576i50hz", - .pixel_repetition_factor = 1, - .progress_mode = 0, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 27000, - .timing = { - .pixel_freq = 27000, - .h_freq = 15625, - .v_freq = 50000, - .vsync_polarity = 0, - .hsync_polarity = 0, - .h_active = 1440, - .h_total = 1728, - .h_blank = 288, - .h_front = 24, - .h_sync = 126, - .h_back = 138, - .v_active = 576/2, - .v_total = 625, - .v_blank = 49/2, - .v_front = 2, - .v_sync = 3, - .v_back = 19, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_non_hdmi_fmt = { - .vic = HDMI_unkown, - .name = "invalid", - .sname = "invalid", -}; - -static struct hdmi_format_para fmt_para_vesa_640x480p60_4x3 = { - .vic = HDMIV_640x480p60hz, - .name = "640x480p60hz", - .sname = "640x480p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 25175, - .timing = { - .pixel_freq = 25175, - .h_freq = 26218, - .v_freq = 59940, - .vsync_polarity = 0, - .hsync_polarity = 0, - .h_active = 640, - .h_total = 800, - .h_blank = 160, - .h_front = 16, - .h_sync = 96, - .h_back = 48, - .v_active = 480, - .v_total = 525, - .v_blank = 45, - .v_front = 10, - .v_sync = 2, - .v_back = 33, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_800x480p60_4x3 = { - .vic = HDMIV_800x480p60hz, - .name = "800x480p60hz", - .sname = "800x480p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 29760, - .timing = { - .pixel_freq = 29760, - .h_freq = 30000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 800, - .h_total = 992, - .h_blank = 192, - .h_front = 24, - .h_sync = 72, - .h_back = 96, - .v_active = 480, - .v_total = 500, - .v_blank = 20, - .v_front = 3, - .v_sync = 7, - .v_back = 10, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = { - .vic = HDMIV_800x600p60hz, - .name = "800x600p60hz", - .sname = "800x600p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 40000, - .timing = { - .pixel_freq = 66666, - .h_freq = 37879, - .v_freq = 60317, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 800, - .h_total = 1056, - .h_blank = 256, - .h_front = 40, - .h_sync = 128, - .h_back = 88, - .v_active = 600, - .v_total = 628, - .v_blank = 28, - .v_front = 1, - .v_sync = 4, - .v_back = 23, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_852x480p60_213x120 = { - .vic = HDMIV_852x480p60hz, - .name = "852x480p60hz", - .sname = "852x480p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 30240, - .timing = { - .pixel_freq = 30240, - .h_freq = 31900, - .v_freq = 59960, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 852, - .h_total = 948, - .h_blank = 96, - .h_front = 40, - .h_sync = 16, - .h_back = 40, - .v_active = 480, - .v_total = 532, - .v_blank = 52, - .v_front = 10, - .v_sync = 2, - .v_back = 40, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_854x480p60_427x240 = { - .vic = HDMIV_854x480p60hz, - .name = "854x480p60hz", - .sname = "854x480p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 30240, - .timing = { - .pixel_freq = 30240, - .h_freq = 31830, - .v_freq = 59950, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 854, - .h_total = 950, - .h_blank = 96, - .h_front = 40, - .h_sync = 16, - .h_back = 40, - .v_active = 480, - .v_total = 531, - .v_blank = 51, - .v_front = 10, - .v_sync = 2, - .v_back = 39, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1024x600p60_17x10 = { - .vic = HDMIV_1024x600p60hz, - .name = "1024x600p60hz", - .sname = "1024x600p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 50400, - .timing = { - .pixel_freq = 50400, - .h_freq = 38280, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1024, - .h_total = 1344, - .h_blank = 320, - .h_front = 24, - .h_sync = 136, - .h_back = 160, - .v_active = 600, - .v_total = 638, - .v_blank = 38, - .v_front = 3, - .v_sync = 6, - .v_back = 29, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1024x768p60_4x3 = { - .vic = HDMIV_1024x768p60hz, - .name = "1024x768p60hz", - .sname = "1024x768p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 79500, - .timing = { - .pixel_freq = 79500, - .h_freq = 48360, - .v_freq = 60004, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1024, - .h_total = 1344, - .h_blank = 320, - .h_front = 24, - .h_sync = 136, - .h_back = 160, - .v_active = 768, - .v_total = 806, - .v_blank = 38, - .v_front = 3, - .v_sync = 6, - .v_back = 29, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1152x864p75_4x3 = { - .vic = HDMIV_1152x864p75hz, - .name = "1152x864p75hz", - .sname = "1152x864p75hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 108000, - .timing = { - .pixel_freq = 108000, - .h_freq = 67500, - .v_freq = 75000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1152, - .h_total = 1600, - .h_blank = 448, - .h_front = 64, - .h_sync = 128, - .h_back = 256, - .v_active = 864, - .v_total = 900, - .v_blank = 36, - .v_front = 1, - .v_sync = 3, - .v_back = 32, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1280x600p60_32x15 = { -#if 0 /* TODO */ - .vic = HDMIV_1280x600p60hz, - .name = "1280x600p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = , - .timing = { - .pixel_freq = , - .h_freq = , - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = , - .h_blank = , - .h_front = , - .h_sync = , - .h_back = , - .v_active = 600, - .v_total = , - .v_blank = , - .v_front = , - .v_sync = , - .v_back = , - .v_sync_ln = 1, - }, -#endif -}; - -static struct hdmi_format_para fmt_para_vesa_1280x768p60_5x3 = { - .vic = HDMIV_1280x768p60hz, - .name = "1280x768p60hz", - .sname = "1280x768p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 79500, - .timing = { - .pixel_freq = 79500, - .h_freq = 47776, - .v_freq = 59870, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = 1664, - .h_blank = 384, - .h_front = 64, - .h_sync = 128, - .h_back = 192, - .v_active = 768, - .v_total = 798, - .v_blank = 30, - .v_front = 3, - .v_sync = 7, - .v_back = 20, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1280x800p60_8x5 = { - .vic = HDMIV_1280x800p60hz, - .name = "1280x800p60hz", - .sname = "1280x800p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 83500, - .timing = { - .pixel_freq = 83500, - .h_freq = 49380, - .v_freq = 59910, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = 1440, - .h_blank = 160, - .h_front = 48, - .h_sync = 32, - .h_back = 80, - .v_active = 800, - .v_total = 823, - .v_blank = 23, - .v_front = 3, - .v_sync = 6, - .v_back = 14, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1280x960p60_4x3 = { - .vic = HDMIV_1280x960p60hz, - .name = "1280x960p60hz", - .sname = "1280x960p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 108000, - .timing = { - .pixel_freq = 108000, - .h_freq = 60000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = 1440, - .h_blank = 520, - .h_front = 96, - .h_sync = 112, - .h_back = 312, - .v_active = 960, - .v_total = 1000, - .v_blank = 40, - .v_front = 1, - .v_sync = 3, - .v_back = 36, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1280x1024p60_5x4 = { - .vic = HDMIV_1280x1024p60hz, - .name = "1280x1024p60hz", - .sname = "1280x1024p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 108000, - .timing = { - .pixel_freq = 108000, - .h_freq = 64080, - .v_freq = 60020, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1280, - .h_total = 1688, - .h_blank = 408, - .h_front = 48, - .h_sync = 112, - .h_back = 248, - .v_active = 1024, - .v_total = 1066, - .v_blank = 42, - .v_front = 1, - .v_sync = 3, - .v_back = 38, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1360x768p60_16x9 = { - .vic = HDMIV_1360x768p60hz, - .name = "1360x768p60hz", - .sname = "1360x768p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 855000, - .timing = { - .pixel_freq = 855000, - .h_freq = 47700, - .v_freq = 60015, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1360, - .h_total = 1792, - .h_blank = 432, - .h_front = 64, - .h_sync = 112, - .h_back = 256, - .v_active = 768, - .v_total = 795, - .v_blank = 27, - .v_front = 3, - .v_sync = 6, - .v_back = 18, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1366x768p60_16x9 = { - .vic = HDMIV_1366x768p60hz, - .name = "1366x768p60hz", - .sname = "1366x768p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 85500, - .timing = { - .pixel_freq = 85500, - .h_freq = 47880, - .v_freq = 59790, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1366, - .h_total = 1792, - .h_blank = 426, - .h_front = 70, - .h_sync = 143, - .h_back = 213, - .v_active = 768, - .v_total = 798, - .v_blank = 30, - .v_front = 3, - .v_sync = 3, - .v_back = 24, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1400x1050p60_4x3 = { - .vic = HDMIV_1400x1050p60hz, - .name = "1400x1050p60hz", - .sname = "1400x1050p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 121750, - .timing = { - .pixel_freq = 121750, - .h_freq = 65317, - .v_freq = 59978, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1400, - .h_total = 1864, - .h_blank = 464, - .h_front = 88, - .h_sync = 144, - .h_back = 232, - .v_active = 1050, - .v_total = 1089, - .v_blank = 39, - .v_front = 3, - .v_sync = 4, - .v_back = 32, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1440x900p60_8x5 = { - .vic = HDMIV_1440x900p60hz, - .name = "1440x900p60hz", - .sname = "1440x900p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 106500, - .timing = { - .pixel_freq = 106500, - .h_freq = 56040, - .v_freq = 59887, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1440, - .h_total = 1904, - .h_blank = 464, - .h_front = 80, - .h_sync = 152, - .h_back = 232, - .v_active = 900, - .v_total = 934, - .v_blank = 34, - .v_front = 3, - .v_sync = 6, - .v_back = 25, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1440x2560p60_9x16 = { - .vic = HDMIV_1440x2560p60hz, - .name = "1440x2560p60hz", - .sname = "1440x2560p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 244850, - .timing = { - .pixel_freq = 244850, - .h_freq = 155760, - .v_freq = 59999, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1440, - .h_total = 1572, - .h_blank = 132, - .h_front = 64, - .h_sync = 4, - .h_back = 64, - .v_active = 2560, - .v_total = 2596, - .v_blank = 36, - .v_front = 16, - .v_sync = 4, - .v_back = 16, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1440x2560p70_9x16 = { - .vic = HDMIV_1440x2560p70hz, - .name = "1440x2560p70hz", - .sname = "1440x2560p70hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 280000, - .timing = { - .pixel_freq = 280000, - .h_freq = 180320, - .v_freq = 70100, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1440, - .h_total = 1550, - .h_blank = 110, - .h_front = 68, - .h_sync = 16, - .h_back = 26, - .v_active = 2560, - .v_total = 2576, - .v_blank = 16, - .v_front = 6, - .v_sync = 6, - .v_back = 4, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1600x900p60_16x9 = { - .vic = HDMIV_1600x900p60hz, - .name = "1600x900p60hz", - .sname = "1600x900p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 108000, - .timing = { - .pixel_freq = 108000, - .h_freq = 60000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1600, - .h_total = 1800, - .h_blank = 200, - .h_front = 24, - .h_sync = 80, - .h_back = 96, - .v_active = 900, - .v_total = 1000, - .v_blank = 100, - .v_front = 1, - .v_sync = 3, - .v_back = 96, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1600x1200p60_4x3 = { - .vic = HDMIV_1600x1200p60hz, - .name = "1600x1200p60hz", - .sname = "1600x1200p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 162000, - .timing = { - .pixel_freq = 162000, - .h_freq = 75000, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1600, - .h_total = 2160, - .h_blank = 560, - .h_front = 64, - .h_sync = 192, - .h_back = 304, - .v_active = 1200, - .v_total = 1250, - .v_blank = 50, - .v_front = 1, - .v_sync = 3, - .v_back = 46, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1680x1050p60_8x5 = { - .vic = HDMIV_1680x1050p60hz, - .name = "1680x1050p60hz", - .sname = "1680x1050p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 146250, - .timing = { - .pixel_freq = 146250, - .h_freq = 65340, - .v_freq = 59954, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1680, - .h_total = 2240, - .h_blank = 560, - .h_front = 104, - .h_sync = 176, - .h_back = 280, - .v_active = 1050, - .v_total = 1089, - .v_blank = 39, - .v_front = 3, - .v_sync = 6, - .v_back = 30, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_1920x1200p60_8x5 = { - .vic = HDMIV_1920x1200p60hz, - .name = "1920x1200p60hz", - .sname = "1920x1200p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 193250, - .timing = { - .pixel_freq = 193250, - .h_freq = 74700, - .v_freq = 59885, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2592, - .h_blank = 672, - .h_front = 136, - .h_sync = 200, - .h_back = 336, - .v_active = 1200, - .v_total = 1245, - .v_blank = 45, - .v_front = 3, - .v_sync = 6, - .v_back = 36, - .v_sync_ln = 1, - }, -}; -static struct hdmi_format_para fmt_para_vesa_2160x1200p90_9x5 = { - .vic = HDMIV_2160x1200p90hz, - .name = "2160x1200p90hz", - .sname = "2160x1200p90hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 268550, - .timing = { - .pixel_freq = 268550, - .h_freq = 109080, - .v_freq = 90000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 2160, - .h_total = 2462, - .h_blank = 302, - .h_front = 190, - .h_sync = 32, - .h_back = 80, - .v_active = 1200, - .v_total = 1212, - .v_blank = 12, - .v_front = 6, - .v_sync = 3, - .v_back = 3, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_2560x1080p60_64x27 = { -#if 0 /* TODO */ - .vic = HDMIV_2560x1080p60hz, - .name = "2560x1080p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 193250, - .timing = { - .pixel_freq = 193250, - .h_freq = 74700, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2592, - .h_blank = 672, - .h_front = 136, - .h_sync = 200, - .h_back = 336, - .v_active = 1200, - .v_total = 1245, - .v_blank = 45, - .v_front = 3, - .v_sync = 6, - .v_back = 36, - .v_sync_ln = 1, - }, -#endif -}; - -static struct hdmi_format_para fmt_para_vesa_2560x1440p60_16x9 = { -#if 0 /* TODO */ - .vic = HDMIV_2560x1440p60hz, - .name = "2560x1440p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 193250, - .timing = { - .pixel_freq = 193250, - .h_freq = 74700, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2592, - .h_blank = 672, - .h_front = 136, - .h_sync = 200, - .h_back = 336, - .v_active = 1200, - .v_total = 1245, - .v_blank = 45, - .v_front = 3, - .v_sync = 6, - .v_back = 36, - .v_sync_ln = 1, - }, -#endif -}; - -static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = { - .vic = HDMIV_2560x1600p60hz, - .name = "2560x1600p60hz", - .sname = "2560x1600p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 348500, - .timing = { - .pixel_freq = 348500, - .h_freq = 99458, - .v_freq = 59987, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 2560, - .h_total = 3504, - .h_blank = 944, - .h_front = 192, - .h_sync = 280, - .h_back = 472, - .v_active = 1600, - .v_total = 1658, - .v_blank = 58, - .v_front = 3, - .v_sync = 6, - .v_back = 49, - .v_sync_ln = 1, - }, -}; - -static struct hdmi_format_para fmt_para_vesa_3440x1440p60_43x18 = { -#if 0 /* TODO */ - .vic = HDMIV_3440x1440p60hz, - .name = "3440x1440p60hz", - .pixel_repetition_factor = 0, - .progress_mode = 1, - .scrambler_en = 0, - .tmds_clk_div40 = 0, - .tmds_clk = 193250, - .timing = { - .pixel_freq = 193250, - .h_freq = 74700, - .v_freq = 60000, - .vsync_polarity = 1, - .hsync_polarity = 1, - .h_active = 1920, - .h_total = 2592, - .h_blank = 672, - .h_front = 136, - .h_sync = 200, - .h_back = 336, - .v_active = 1200, - .v_total = 1245, - .v_blank = 45, - .v_front = 3, - .v_sync = 6, - .v_back = 36, - .v_sync_ln = 1, - }, -#endif -}; - -static struct hdmi_format_para *all_fmt_paras[] = { - &fmt_para_3840x2160p60_y420_16x9, - &fmt_para_3840x2160p60_16x9, - &fmt_para_3840x2160p50_y420_16x9, - &fmt_para_3840x2160p50_16x9, - &fmt_para_3840x2160p30_16x9, - &fmt_para_3840x2160p25_16x9, - &fmt_para_3840x2160p24_16x9, - &fmt_para_4096x2160p24_256x135, - &fmt_para_4096x2160p25_256x135, - &fmt_para_4096x2160p30_256x135, - &fmt_para_4096x2160p50_y420_256x135, - &fmt_para_4096x2160p50_256x135, - &fmt_para_4096x2160p60_y420_256x135, - &fmt_para_4096x2160p60_256x135, - &fmt_para_1920x1080p50_16x9, - &fmt_para_1920x1080p60_16x9, - &fmt_para_1920x1080p30_16x9, - &fmt_para_1920x1080p25_16x9, - &fmt_para_1920x1080p24_16x9, - &fmt_para_1920x1080p100_16x9, - &fmt_para_1920x1080p120_16x9, - &fmt_para_1920x1080i60_16x9, - &fmt_para_1920x1080i50_16x9, - &fmt_para_1920x1080i100_16x9, - &fmt_para_1920x1080i120_16x9, - &fmt_para_1280x720p60_16x9, - &fmt_para_1280x720p50_16x9, - &fmt_para_1280x720p100_16x9, - &fmt_para_1280x720p120_16x9, - &fmt_para_720x480p60_16x9, - &fmt_para_720x480p120_16x9, - &fmt_para_720x480i60_16x9, - &fmt_para_720x576p50_16x9, - &fmt_para_720x576p100_16x9, - &fmt_para_720x576i50_16x9, - &fmt_para_vesa_640x480p60_4x3, - &fmt_para_vesa_800x480p60_4x3, - &fmt_para_vesa_800x600p60_4x3, - &fmt_para_vesa_852x480p60_213x120, - &fmt_para_vesa_854x480p60_427x240, - &fmt_para_vesa_1024x600p60_17x10, - &fmt_para_vesa_1024x768p60_4x3, - &fmt_para_vesa_1152x864p75_4x3, - &fmt_para_vesa_1280x600p60_32x15, - &fmt_para_vesa_1280x768p60_5x3, - &fmt_para_vesa_1280x800p60_8x5, - &fmt_para_vesa_1280x960p60_4x3, - &fmt_para_vesa_1280x1024p60_5x4, - &fmt_para_vesa_1360x768p60_16x9, - &fmt_para_vesa_1366x768p60_16x9, - &fmt_para_vesa_1400x1050p60_4x3, - &fmt_para_vesa_1440x900p60_8x5, - &fmt_para_vesa_1440x2560p60_9x16, - &fmt_para_vesa_1440x2560p70_9x16, - &fmt_para_vesa_1600x900p60_16x9, - &fmt_para_vesa_1600x1200p60_4x3, - &fmt_para_vesa_1680x1050p60_8x5, - &fmt_para_vesa_1920x1200p60_8x5, - &fmt_para_vesa_2160x1200p90_9x5, - &fmt_para_vesa_2560x1080p60_64x27, - &fmt_para_vesa_2560x1440p60_16x9, - &fmt_para_vesa_2560x1600p60_8x5, - &fmt_para_vesa_3440x1440p60_43x18, - &fmt_para_non_hdmi_fmt, - NULL, -}; - -struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic) -{ - int i; - - for (i = 0; all_fmt_paras[i] != NULL; i++) { - if (vic == all_fmt_paras[i]->vic) - return all_fmt_paras[i]; - } - return NULL; -} - -static struct parse_cd parse_cd_[] = { - {HDMI_COLOR_DEPTH_24B, "8bit",}, - {HDMI_COLOR_DEPTH_30B, "10bit"}, - {HDMI_COLOR_DEPTH_36B, "12bit"}, - {HDMI_COLOR_DEPTH_48B, "16bit"}, -}; - -static struct parse_cs parse_cs_[] = { - {HDMI_COLOR_FORMAT_RGB, "rgb",}, - {HDMI_COLOR_FORMAT_444, "444",}, - {HDMI_COLOR_FORMAT_422, "422",}, - {HDMI_COLOR_FORMAT_420, "420",}, -}; - -static struct parse_cr parse_cr_[] = { - {HDMI_COLOR_RANGE_LIM, "limit",}, - {HDMI_COLOR_RANGE_FUL, "full",}, -}; - -/* parse the string from "hdmitx output FORMAT" */ -void hdmi_parse_attr(struct hdmi_format_para *para, char const *name) -{ - int i; - - /* parse color depth */ - for (i = 0; i < sizeof(parse_cd_) / sizeof(struct parse_cd); i++) { - if (strstr(name, parse_cd_[i].name)) { - para->cd = parse_cd_[i].cd; - break; - } - } - /* set default value */ - if (i == sizeof(parse_cd_) / sizeof(struct parse_cd)) - para->cd = HDMI_COLOR_DEPTH_24B; - - /* parse color space */ - for (i = 0; i < sizeof(parse_cs_) / sizeof(struct parse_cs); i++) { - if (strstr(name, parse_cs_[i].name)) { - para->cs = parse_cs_[i].cs; - break; - } - } - /* set default value */ - if (i == sizeof(parse_cs_) / sizeof(struct parse_cs)) - para->cs = HDMI_COLOR_FORMAT_444; - - /* parse color range */ - for (i = 0; i < sizeof(parse_cr_) / sizeof(struct parse_cr); i++) { - if (strstr(name, parse_cr_[i].name)) { - para->cr = parse_cr_[i].cr; - break; - } - } - /* set default value */ - if (i == sizeof(parse_cr_) / sizeof(struct parse_cr)) - para->cr = HDMI_COLOR_RANGE_FUL; -} - -/* - * Paramter 'name' can be 1080p60hz, or 1920x1080p60hz - * or 3840x2160p60hz, 2160p60hz - * or 3840x2160p60hz420, 2160p60hz420 (Y420 mode) - */ -enum hdmi_vic hdmi_get_fmt_vic(char const *name) -{ - int i; - char *lname; - enum hdmi_vic vic = HDMI_unkown; - struct hdmi_format_para *para = NULL; - - if (!name) - return HDMI_unkown; - for (i = 0; all_fmt_paras[i] != NULL; i++) { - lname = all_fmt_paras[i]->name; - if (lname && (strncmp(name, lname, strlen(lname)) == 0)) { - vic = all_fmt_paras[i]->vic; - break; - } - lname = all_fmt_paras[i]->sname; - if (lname && (strncmp(name, lname, strlen(lname)) == 0)) { - vic = all_fmt_paras[i]->vic; - break; - } - } - if ((vic != HDMI_unkown) && (all_fmt_paras[i] != NULL)) { - para = all_fmt_paras[i]; - memset(¶->ext_name[0], 0, sizeof(para->ext_name)); - memcpy(¶->ext_name[0], name, strlen(name)); - hdmi_parse_attr(para, name); - } - return vic; -} - -struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t) -{ - int i; - - if (!t) - return NULL; - for (i = 0; all_fmt_paras[i]; i++) { - if ((abs(all_fmt_paras[i]->timing.pixel_freq / 10 - - t->pixel_clock) <= (t->pixel_clock + 1000) / 1000) && - (t->h_active == all_fmt_paras[i]->timing.h_active) && - (t->h_blank == all_fmt_paras[i]->timing.h_blank) && - (t->v_active == all_fmt_paras[i]->timing.v_active) && - (t->v_blank == all_fmt_paras[i]->timing.v_blank) && - (t->h_sync_offset == all_fmt_paras[i]->timing.h_front) && - (t->h_sync == all_fmt_paras[i]->timing.h_sync) && - (t->v_sync_offset == all_fmt_paras[i]->timing.v_front) && - (t->v_sync == all_fmt_paras[i]->timing.v_sync) - ) - return all_fmt_paras[i]; - } - - return NULL; -}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/Kconfig b/drivers/amlogic/media/vout/hdmitx/hdmitx20/Kconfig new file mode 100644 index 0000000..25302b3 --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/Kconfig
@@ -0,0 +1,5 @@ +config AML_HDMITX20 + bool "Amlogic HDMITX20 drivers Support" + depends on AML_HDMITX + help + HDMITX20 Output Enable
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/Makefile b/drivers/amlogic/media/vout/hdmitx/hdmitx20/Makefile new file mode 100644 index 0000000..fb00f4a --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/Makefile
@@ -0,0 +1,9 @@ +# +# (C) Copyright 2020 +# + +#EXTRA_CFLAGS = -Idrivers/video/include/ + +obj-y += hdmitx20.o + +hdmitx20-y := hdmitx_drv.o hdmitx_tvenc.o hdmi_edid_parsing.o hdmi_parameters.o hdmi_tx_compliance.o hdmitx_policy.o
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_edid_parsing.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_edid_parsing.c new file mode 100644 index 0000000..f9e0e99 --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_edid_parsing.c
@@ -0,0 +1,1397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <linux/stddef.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> + +#define CEA_DATA_BLOCK_COLLECTION_ADDR_1StP 0x04 +#define VIDEO_TAG 0x40 +#define AUDIO_TAG 0x20 +#define VENDOR_TAG 0x60 +#define SPEAKER_TAG 0x80 + +#define HDMI_EDID_BLOCK_TYPE_RESERVED 0 +#define HDMI_EDID_BLOCK_TYPE_AUDIO 1 +#define HDMI_EDID_BLOCK_TYPE_VIDEO 2 +#define HDMI_EDID_BLOCK_TYPE_VENDER 3 +#define HDMI_EDID_BLOCK_TYPE_SPEAKER 4 +#define HDMI_EDID_BLOCK_TYPE_VESA 5 +#define HDMI_EDID_BLOCK_TYPE_RESERVED2 6 +#define HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG 7 + +#define EXTENSION_VENDOR_SPECIFIC 0x1 +#define EXTENSION_COLORMETRY_TAG 0x5 +/* DRM stands for "Dynamic Range and Mastering " */ +#define EXTENSION_DRM_STATIC_TAG 0x6 +/* Video Format Preference Data block */ +#define EXTENSION_VFPDB_TAG 0xd +#define EXTENSION_Y420_VDB_TAG 0xe +#define EXTENSION_Y420_CMDB_TAG 0xf + +#define EDID_DETAILED_TIMING_DES_BLOCK0_POS 0x36 +#define EDID_DETAILED_TIMING_DES_BLOCK1_POS 0x48 +#define EDID_DETAILED_TIMING_DES_BLOCK2_POS 0x5A +#define EDID_DETAILED_TIMING_DES_BLOCK3_POS 0x6C + +/* EDID Descrptor Tag */ +#define TAG_PRODUCT_SERIAL_NUMBER 0xFF +#define TAG_ALPHA_DATA_STRING 0xFE +#define TAG_RANGE_LIMITS 0xFD +#define TAG_DISPLAY_PRODUCT_NAME_STRING 0xFC /* MONITOR NAME */ +#define TAG_COLOR_POINT_DATA 0xFB +#define TAG_STANDARD_TIMINGS 0xFA +#define TAG_DISPLAY_COLOR_MANAGEMENT 0xF9 +#define TAG_CVT_TIMING_CODES 0xF8 +#define TAG_ESTABLISHED_TIMING_III 0xF7 +#define TAG_DUMMY_DES 0x10 + +static struct dispmode_vic dispmode_vic_tab[] = { + {"480i60hz_4x3", HDMI_720x480i60_4x3}, + {"480p60hz_4x3", HDMI_720x480p60_4x3}, + {"576i50hz_4x3", HDMI_720x576i50_4x3}, + {"576p50hz_4x3", HDMI_720x576p50_4x3}, + {"480i60hz", HDMI_720x480i60_16x9}, + {"480p60hz", HDMI_720x480p60_16x9}, + {"576i50hz", HDMI_720x576i50_16x9}, + {"576p50hz", HDMI_720x576p50_16x9}, + {"720p50hz", HDMI_720p50}, + {"720p60hz", HDMI_720p60}, + {"1080i50hz", HDMI_1080i50}, + {"1080i60hz", HDMI_1080i60}, + {"1080p50hz", HDMI_1080p50}, + {"1080p30hz", HDMI_1080p30}, + {"1080p25hz", HDMI_1080p25}, + {"1080p24hz", HDMI_1080p24}, + {"1080p60hz", HDMI_1080p60}, + {"1080p120hz", HDMI_1080p120}, + {"2560x1080p50hz", HDMI_2560x1080p50_64x27}, + {"2560x1080p60hz", HDMI_2560x1080p60_64x27}, + {"2160p30hz", HDMI_4k2k_30}, + {"2160p25hz", HDMI_4k2k_25}, + {"2160p24hz", HDMI_4k2k_24}, + {"smpte24hz", HDMI_4k2k_smpte_24}, + {"smpte25hz", HDMI_4096x2160p25_256x135}, + {"smpte30hz", HDMI_4096x2160p30_256x135}, + {"smpte50hz420", HDMI_4096x2160p50_256x135_Y420}, + {"smpte60hz420", HDMI_4096x2160p60_256x135_Y420}, + {"2160p60hz420", HDMI_3840x2160p60_16x9_Y420}, + {"2160p50hz420", HDMI_3840x2160p50_16x9_Y420}, + {"smpte50hz", HDMI_4096x2160p50_256x135}, + {"smpte60hz", HDMI_4096x2160p60_256x135}, + {"2160p60hz", HDMI_4k2k_60}, + {"2160p50hz", HDMI_4k2k_50}, + {"640x480p60hz", HDMIV_640x480p60hz}, + {"800x480p60hz", HDMIV_800x480p60hz}, + {"800x600p60hz", HDMIV_800x600p60hz}, + {"852x480p60hz", HDMIV_852x480p60hz}, + {"854x480p60hz", HDMIV_854x480p60hz}, + {"1024x600p60hz", HDMIV_1024x600p60hz}, + {"1024x768p60hz", HDMIV_1024x768p60hz}, + {"1152x864p75hz", HDMIV_1152x864p75hz}, + {"1280x600p60hz", HDMIV_1280x600p60hz}, + {"1280x768p60hz", HDMIV_1280x768p60hz}, + {"1280x800p60hz", HDMIV_1280x800p60hz}, + {"1280x960p60hz", HDMIV_1280x960p60hz}, + {"1280x1024p60hz", HDMIV_1280x1024p60hz}, + {"1280x1024", HDMIV_1280x1024p60hz}, /* alias of "1280x1024p60hz" */ + {"1360x768p60hz", HDMIV_1360x768p60hz}, + {"1366x768p60hz", HDMIV_1366x768p60hz}, + {"1400x1050p60hz", HDMIV_1400x1050p60hz}, + {"1440x900p60hz", HDMIV_1440x900p60hz}, + {"1440x2560p60hz", HDMIV_1440x2560p60hz}, + {"1600x900p60hz", HDMIV_1600x900p60hz}, + {"1600x1200p60hz", HDMIV_1600x1200p60hz}, + {"1680x1050p60hz", HDMIV_1680x1050p60hz}, + {"1920x1200p60hz", HDMIV_1920x1200p60hz}, + {"2160x1200p90hz", HDMIV_2160x1200p90hz}, + {"2560x1080p60hz", HDMIV_2560x1080p60hz}, + {"2560x1440p60hz", HDMIV_2560x1440p60hz}, + {"2560x1600p60hz", HDMIV_2560x1600p60hz}, + {"3440x1440p60hz", HDMIV_3440x1440p60hz}, + {"2400x1200p90hz", HDMIV_2400x1200p90hz} +}; + +#if 0 +/* retrun 1 valid edid */ +static int check_dvi_hdmi_edid_valid(unsigned char *buf) +{ + unsigned int chksum = 0; + unsigned int i = 0; + + /* check block 0 first 8 bytes */ + if ((buf[0] != 0) && (buf[7] != 0)) + return 0; + for (i = 1; i < 7; i++) { + if (buf[i] != 0xff) + return 0; + } + + /* check block 0 checksum */ + for (chksum = 0, i = 0; i < 0x80; i++) + chksum += buf[i]; + if ((chksum & 0xff) != 0) + return 0; + + if (buf[0x7e] == 0)/* check Extension flag at block 0 */ + return 1; + /* check block 1 extension tag */ + else if (!((buf[0x80] == 0x2) || (buf[0x80] == 0xf0))) + return 0; + + /* check block 1 checksum */ + for (chksum = 0, i = 0x80; i < 0x100; i++) + chksum += buf[i]; + if ((chksum & 0xff) != 0) + return 0; + + /* check block 2 checksum */ + if (buf[0x7e] > 1) { + for (chksum = 0, i = 0x100; i < 0x180; i++) + chksum += buf[i]; + if ((chksum & 0xff) != 0) + return 0; + } + + /* check block 3 checksum */ + if (buf[0x7e] > 2) { + for (chksum = 0, i = 0x180; i < 0x200; i++) + chksum += buf[i]; + if ((chksum & 0xff) != 0) + return 0; + } + + return 1; +} +#endif +static void dump_dtd_info(struct dtd *t) +{ + return; /* debug only */ + printk("%s[%d]\n", __func__, __LINE__); +#define PR(a) pr_info("%s %d\n", #a, t->a) + PR(pixel_clock); + PR(h_active); + PR(h_blank); + PR(v_active); + PR(v_blank); + PR(h_sync_offset); + PR(h_sync); + PR(v_sync_offset); + PR(v_sync); +} + +static int Edid_ParsingDRMStaticBlock(struct rx_cap *pRXCap, + unsigned char *buf) +{ + unsigned char tag = 0, ext_tag = 0, data_end = 0; + unsigned int pos = 0; + + tag = (buf[pos] >> 5) & 0x7; + data_end = (buf[pos] & 0x1f); + memset(pRXCap->hdr_info.rawdata, 0, 7); + memcpy(pRXCap->hdr_info.rawdata, buf, data_end + 1); + pos++; + ext_tag = buf[pos]; + if ((tag != HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG) + || (ext_tag != EXTENSION_DRM_STATIC_TAG)) + goto INVALID_DRM_STATIC; + pos++; + pRXCap->hdr_info.hdr_sup_eotf_sdr = !!(buf[pos] & (0x1 << 0)); + pRXCap->hdr_info.hdr_sup_eotf_hdr = !!(buf[pos] & (0x1 << 1)); + pRXCap->hdr_info.hdr_sup_eotf_smpte_st_2084 = !!(buf[pos] & (0x1 << 2)); + pRXCap->hdr_info.hdr_sup_eotf_hlg = !!(buf[pos] & (0x1 << 3)); + pos++; + pRXCap->hdr_info.hdr_sup_SMD_type1 = !!(buf[pos] & (0x1 << 0)); + pos++; + if (data_end == 3) + return 0; + if (data_end == 4) { + pRXCap->hdr_info.hdr_lum_max = buf[pos]; + return 0; + } + if (data_end == 5) { + pRXCap->hdr_info.hdr_lum_max = buf[pos]; + pRXCap->hdr_info.hdr_lum_avg = buf[pos + 1]; + return 0; + } + if (data_end == 6) { + pRXCap->hdr_info.hdr_lum_max = buf[pos]; + pRXCap->hdr_info.hdr_lum_avg = buf[pos + 1]; + pRXCap->hdr_info.hdr_lum_min = buf[pos + 2]; + return 0; + } + return 0; +INVALID_DRM_STATIC: + printf("[%s] it's not a valid DRM STATIC BLOCK\n", __func__); + return -1; +} + +static void Edid_ParsingVendSpec(struct rx_cap *pRXCap, + unsigned char *buf) +{ + struct dv_info *dv = &pRXCap->dv_info; + struct hdr10_plus_info *hdr10_plus = &pRXCap->hdr10plus_info; + unsigned char *dat = buf; + unsigned char pos = 0; + unsigned int ieeeoui = 0; + u8 length = 0; + + length = dat[pos] & 0x1f; + pos++; + + if (dat[pos] != 1) { + printf("hdmitx: edid: parsing fail %s[%d]\n", __func__, + __LINE__); + return; + } + + pos++; + ieeeoui = dat[pos++]; + ieeeoui += dat[pos++] << 8; + ieeeoui += dat[pos++] << 16; + printf("Edid_ParsingVendSpec:ieeeoui=0x%x,len=%u\n", ieeeoui, length); + + /*HDR10+ use vsvdb*/ + if (ieeeoui == HDR10_PLUS_IEEE_OUI) { + memset(hdr10_plus, 0, sizeof(struct hdr10_plus_info)); + hdr10_plus->length = length; + hdr10_plus->ieeeoui = ieeeoui; + hdr10_plus->application_version = dat[pos] & 0x3; + pos++; + return; + } + + if (ieeeoui != DV_IEEE_OUI) { + dv->block_flag = ERROR_OUI; + return; + } + /* it is a Dovi block*/ + memset(dv, 0, sizeof(struct dv_info)); + dv->block_flag = CORRECT; + dv->length = length; + memcpy(dv->rawdata, dat, dv->length + 1); + dv->ieeeoui = ieeeoui; + dv->ver = (dat[pos] >> 5) & 0x7; + if ((dv->ver) > 2) { + dv->block_flag = ERROR_VER; + return; + } + /* Refer to DV 2.9 Page 27 */ + if (dv->ver == 0) { + if (dv->length == 0x19) { + dv->sup_yuv422_12bit = dat[pos] & 0x1; + dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1; + dv->sup_global_dimming = (dat[pos] >> 2) & 0x1; + pos++; + dv->Rx = + (dat[pos+1] << 4) | (dat[pos] >> 4); + dv->Ry = + (dat[pos+2] << 4) | (dat[pos] & 0xf); + pos += 3; + dv->Gx = + (dat[pos+1] << 4) | (dat[pos] >> 4); + dv->Gy = + (dat[pos+2] << 4) | (dat[pos] & 0xf); + pos += 3; + dv->Bx = + (dat[pos+1] << 4) | (dat[pos] >> 4); + dv->By = + (dat[pos+2] << 4) | (dat[pos] & 0xf); + pos += 3; + dv->Wx = + (dat[pos+1] << 4) | (dat[pos] >> 4); + dv->Wy = + (dat[pos+2] << 4) | (dat[pos] & 0xf); + pos += 3; + dv->tminPQ = + (dat[pos+1] << 4) | (dat[pos] >> 4); + dv->tmaxPQ = + (dat[pos+2] << 4) | (dat[pos] & 0xf); + pos += 3; + dv->dm_major_ver = dat[pos] >> 4; + dv->dm_minor_ver = dat[pos] & 0xf; + pos++; + dv->support_DV_RGB_444_8BIT = 1; + printf("v0 VSVDB: len=%d, sup_2160p60hz=%d\n", + dv->length, dv->sup_2160p60hz); + } else + dv->block_flag = ERROR_LENGTH; + } + + if (dv->ver == 1) { + if (dv->length == 0x0B) {/* Refer to DV 2.9 Page 33 */ + dv->dm_version = (dat[pos] >> 2) & 0x7; + dv->sup_yuv422_12bit = dat[pos] & 0x1; + dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1; + pos++; + dv->sup_global_dimming = dat[pos] & 0x1; + dv->tmaxLUM = dat[pos] >> 1; + pos++; + dv->colorimetry = dat[pos] & 0x1; + dv->tminLUM = dat[pos] >> 1; + pos++; + dv->low_latency = dat[pos] & 0x3; + dv->Bx = 0x20 | ((dat[pos] >> 5) & 0x7); + dv->By = 0x08 | ((dat[pos] >> 2) & 0x7); + pos++; + dv->Gx = 0x00 | (dat[pos] >> 1); + dv->Ry = 0x40 | ((dat[pos] & 0x1) | + ((dat[pos + 1] & 0x1) << 1) | + ((dat[pos + 2] & 0x3) << 2)); + pos++; + dv->Gy = 0x80 | (dat[pos] >> 1); + pos++; + dv->Rx = 0xA0 | (dat[pos] >> 3); + pos++; + dv->support_DV_RGB_444_8BIT = 1; + if (dv->low_latency == 0x01) + dv->support_LL_YCbCr_422_12BIT = 1; + printf("v1 VSVDB: len=%d, sup_2160p60hz=%d, low_latency=%d\n", + dv->length, dv->sup_2160p60hz, dv->low_latency); + } else if (dv->length == 0x0E) { + dv->dm_version = (dat[pos] >> 2) & 0x7; + dv->sup_yuv422_12bit = dat[pos] & 0x1; + dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1; + pos++; + dv->sup_global_dimming = dat[pos] & 0x1; + dv->tmaxLUM = dat[pos] >> 1; + pos++; + dv->colorimetry = dat[pos] & 0x1; + dv->tminLUM = dat[pos] >> 1; + pos += 2; /* byte8 is reserved as 0 */ + dv->Rx = dat[pos++]; + dv->Ry = dat[pos++]; + dv->Gx = dat[pos++]; + dv->Gy = dat[pos++]; + dv->Bx = dat[pos++]; + dv->By = dat[pos++]; + dv->support_DV_RGB_444_8BIT = 1; + printf("v1 VSVDB: len=%d, sup_2160p60hz=%d\n", + dv->length, dv->sup_2160p60hz); + } else + dv->block_flag = ERROR_LENGTH; + } + if (dv->ver == 2) { + /* v2 VSVDB length could be greater than 0xB + * and should not be treated as unrecognized + * block. Instead, we should parse it as a regular + * v2 VSVDB using just the remaining 11 bytes here + */ + if (dv->length >= 0x0B) { + dv->sup_2160p60hz = 0x1;/*default*/ + dv->dm_version = (dat[pos] >> 2) & 0x7; + dv->sup_yuv422_12bit = dat[pos] & 0x1; + dv->sup_backlight_control = (dat[pos] >> 1) & 0x1; + pos++; + dv->sup_global_dimming = (dat[pos] >> 2) & 0x1; + dv->backlt_min_luma = dat[pos] & 0x3; + dv->tminPQ = dat[pos] >> 3; + pos++; + dv->Interface = dat[pos] & 0x3; + dv->tmaxPQ = dat[pos] >> 3; + pos++; + dv->sup_10b_12b_444 = ((dat[pos] & 0x1) << 1) | + (dat[pos + 1] & 0x1); + dv->Gx = 0x00 | (dat[pos] >> 1); + pos++; + dv->Gy = 0x80 | (dat[pos] >> 1); + pos++; + dv->Rx = 0xA0 | (dat[pos] >> 3); + dv->Bx = 0x20 | (dat[pos] & 0x7); + pos++; + dv->Ry = 0x40 | (dat[pos] >> 3); + dv->By = 0x08 | (dat[pos] & 0x7); + pos++; + if ((dv->Interface != 0x00) && + (dv->Interface != 0x01)) + dv->support_DV_RGB_444_8BIT = 1; + + dv->support_LL_YCbCr_422_12BIT = 1; + if ((dv->Interface == 0x01) || + (dv->Interface == 0x03)) { + if (dv->sup_10b_12b_444 == 0x1) + dv->support_LL_RGB_444_10BIT = 1; + if (dv->sup_10b_12b_444 == 0x2) + dv->support_LL_RGB_444_12BIT = 1; + } + printf("v2 VSVDB: len=%d, sup_2160p60hz=%d, Interface=%d\n", + dv->length, dv->sup_2160p60hz, dv->Interface); + } else + dv->block_flag = ERROR_LENGTH; + } + + if (pos > dv->length + 1) + printf("hdmitx: edid: maybe invalid dv%d data\n", dv->ver); +} + +static void Edid_DTD_parsing(struct rx_cap *pRXCap, unsigned char *data) +{ + struct hdmi_format_para *para = NULL; + struct dtd *t = &pRXCap->dtd[pRXCap->dtd_idx]; + + memset(t, 0, sizeof(struct dtd)); + t->pixel_clock = data[0] + (data[1] << 8); + t->h_active = (((data[4] >> 4) & 0xf) << 8) + data[2]; + t->h_blank = ((data[4] & 0xf) << 8) + data[3]; + t->v_active = (((data[7] >> 4) & 0xf) << 8) + data[5]; + t->v_blank = ((data[7] & 0xf) << 8) + data[6]; + t->h_sync_offset = (((data[11] >> 6) & 0x3) << 8) + data[8]; + t->h_sync = (((data[11] >> 4) & 0x3) << 8) + data[9]; + t->v_sync_offset = (((data[11] >> 2) & 0x3) << 4) + + ((data[10] >> 4) & 0xf); + t->v_sync = (((data[11] >> 0) & 0x3) << 4) + ((data[10] >> 0) & 0xf); +/* + * Special handling of 1080i60hz, 1080i50hz + */ + if ((t->pixel_clock == 7425) && (t->h_active == 1920) && + (t->v_active == 1080)) { + t->v_active = t->v_active / 2; + t->v_blank = t->v_blank / 2; + } +/* + * Special handling of 480i60hz, 576i50hz + */ + if (((((t->flags) >> 1) & 0x3) == 0) && (t->h_active == 1440)) { + if (t->pixel_clock == 2700) /* 576i50hz */ + goto next; + if ((t->pixel_clock - 2700) < 10) /* 480i60hz */ + t->pixel_clock = 2702; +next: + t->v_active = t->v_active / 2; + t->v_blank = t->v_blank / 2; + } +/* + * call hdmi_match_dtd_paras() to check t is matched with VIC + */ + para = hdmi_match_dtd_paras(t); + if (para) { + t->vic = para->vic; + pRXCap->preferred_mode = pRXCap->dtd[0].vic; /* Select dtd0 */ + if (0) /* debug only */ + pr_info("hdmitx: get dtd%d vic: %d\n", + pRXCap->dtd_idx, para->vic); + pRXCap->dtd_idx++; + } else + dump_dtd_info(t); +} + +/* parse Sink 4k2k information */ +static void hdmitx_edid_4k2k_parse(struct rx_cap *pRXCap, unsigned char *dat, + unsigned size) +{ + if ((size > 4) || (size == 0)) { + return; + } + while (size--) { + if (*dat == 1) + pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p30_16x9; + else if (*dat == 2) + pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p25_16x9; + else if (*dat == 3) + pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p24_16x9; + else if (*dat == 4) + pRXCap->VIC[pRXCap->VIC_count] = HDMI_4096x2160p24_256x135; + else + ; + dat++; + pRXCap->VIC_count++; + } +} + +static void set_vsdb_dc_cap(struct rx_cap *pRXCap) +{ + pRXCap->dc_y444 = !!(pRXCap->ColorDeepSupport & (1 << 3)); + pRXCap->dc_30bit = !!(pRXCap->ColorDeepSupport & (1 << 4)); + pRXCap->dc_36bit = !!(pRXCap->ColorDeepSupport & (1 << 5)); + pRXCap->dc_48bit = !!(pRXCap->ColorDeepSupport & (1 << 6)); +} + +static void set_vsdb_dc_420_cap(struct rx_cap *pRXCap, + unsigned char *edid_offset) +{ + pRXCap->dc_30bit_420 = !!(edid_offset[6] & (1 << 0)); + pRXCap->dc_36bit_420 = !!(edid_offset[6] & (1 << 1)); + pRXCap->dc_48bit_420 = !!(edid_offset[6] & (1 << 2)); +} + +static int Edid_ParsingY420VDBBlock(struct rx_cap *pRXCap, + unsigned char *buf) +{ + unsigned char tag = 0, ext_tag = 0, data_end = 0; + unsigned int pos = 0; + int i = 0, found = 0; + + tag = (buf[pos] >> 5) & 0x7; + data_end = (buf[pos] & 0x1f)+1; + pos++; + ext_tag = buf[pos]; + + if ((tag != 0x7) || (ext_tag != 0xe)) + goto INVALID_Y420VDB; + + pRXCap->dc_y420 = 1; + pos++; + while (pos < data_end) { + if (pRXCap->VIC_count < VIC_MAX_NUM) { + for (i = 0; i < pRXCap->VIC_count; i++) { + if (pRXCap->VIC[i] == buf[pos]) { + pRXCap->VIC[i] = + HDMITX_VIC420_OFFSET + buf[pos]; + found = 1; + /* Here we do not break,because + some EDID may have the same + repeated VICs + */ + } + } + if (0 == found) { + pRXCap->VIC[pRXCap->VIC_count] = + HDMITX_VIC420_OFFSET + buf[pos]; + pRXCap->VIC_count++; + } + } + pos++; + } + + return 0; + +INVALID_Y420VDB: + printf("[%s] it's not a valid y420vdb!\n", __func__); + return -1; +} + +static int Edid_ParsingY420CMDBBlock(struct rx_cap *pRXCap, + unsigned char *buf) +{ + unsigned char tag = 0, ext_tag = 0, length = 0, data_end = 0; + unsigned int pos = 0, i = 0; + + tag = (buf[pos] >> 5) & 0x7; + length = buf[pos] & 0x1f; + data_end = length + 1; + pos++; + ext_tag = buf[pos]; + + if ((tag != 0x7) || (ext_tag != 0xf)) + goto INVALID_Y420CMDB; + + if (length == 1) { + pRXCap->y420_all_vic = 1; + return 0; + } + + pRXCap->bitmap_length = 0; + pRXCap->bitmap_valid = 0; + memset(pRXCap->y420cmdb_bitmap, 0x00, Y420CMDB_MAX); + + pos++; + if (pos < data_end) { + pRXCap->bitmap_length = data_end - pos; + pRXCap->bitmap_valid = 1; + } + while (pos < data_end) { + if (i < Y420CMDB_MAX) + pRXCap->y420cmdb_bitmap[i] = buf[pos]; + pos++; + i++; + } + + return 0; + +INVALID_Y420CMDB: + printf("[%s] it's not a valid y420cmdb!\n", __func__); + return -1; +} + +static int Edid_Y420CMDB_fill_all_vic(struct rx_cap *pRXCap) +{ + unsigned int count = pRXCap->VIC_count; + unsigned int a, b; + + if (pRXCap->y420_all_vic != 1) + return 1; + + a = count/8; + a = (a >= Y420CMDB_MAX)?Y420CMDB_MAX:a; + b = count%8; + + if (a > 0) + memset(&(pRXCap->y420cmdb_bitmap[0]), 0xff, a); + + if ((b != 0) && (a < Y420CMDB_MAX)) + pRXCap->y420cmdb_bitmap[a] = (((1 << b) - 1) << (8-b)); + + pRXCap->bitmap_length = (b == 0) ? a : (a + 1); + pRXCap->bitmap_valid = (pRXCap->bitmap_length != 0)?1:0; + + return 0; +} + +static int Edid_Y420CMDB_PostProcess(struct rx_cap *pRXCap) +{ + unsigned int i = 0, j = 0, valid = 0; + unsigned char *p = NULL; + + if (pRXCap->y420_all_vic == 1) + Edid_Y420CMDB_fill_all_vic(pRXCap); + + if (pRXCap->bitmap_valid == 0) + goto PROCESS_END; + + pRXCap->dc_y420 = 1; + for (i = 0; i < pRXCap->bitmap_length; i++) { + p = &(pRXCap->y420cmdb_bitmap[i]); + for (j = 0; j < 8; j++) { + valid = ((*p >> j) & 0x1); + if (valid != 0) { + pRXCap->VIC[pRXCap->VIC_count] = + HDMITX_VIC420_OFFSET + pRXCap->VIC[i*8+j]; + pRXCap->VIC_count++; + } + } + } + +PROCESS_END: + return 0; +} + +static int Edid_ParsingVFPDB(struct rx_cap *pRXCap, unsigned char *buf) +{ + unsigned int len = buf[0] & 0x1f; + enum hdmi_vic svr = HDMI_unkown; + + if (buf[1] != EXTENSION_VFPDB_TAG) + return 0; + if (len < 2) + return 0; + + svr = buf[2]; + if (((svr >= 1) && (svr <= 127)) || + ((svr >= 193) && (svr <= 253))) { + pRXCap->flag_vfpdb = 1; + pRXCap->preferred_mode = svr; + pr_info("preferred mode 0 srv %d\n", pRXCap->preferred_mode); + return 1; + } + if ((svr >= 129) && (svr <= 144)) { + pRXCap->flag_vfpdb = 1; + pRXCap->preferred_mode = pRXCap->dtd[svr - 129].vic; + pr_info("preferred mode 0 dtd %d\n", pRXCap->preferred_mode); + return 1; + } + return 0; +} + +static int hdmitx_edid_block_parse(struct rx_cap *pRXCap, + unsigned char *BlockBuf) +{ + unsigned char offset, End; + unsigned char count; + unsigned char tag; + int i, tmp, idx; + unsigned char *vfpdb_offset = NULL; + + if (BlockBuf[0] != 0x02) + return -1; /* not a CEA BLOCK. */ + End = BlockBuf[2]; /* CEA description. */ + pRXCap->native_Mode = BlockBuf[3]; + pRXCap->number_of_dtd += BlockBuf[3] & 0xf; + /* bit 5 (YCBCR 4:4:4) = 1 if sink device supports YCBCR 4:4:4 + * in addition to RGB; + * bit 4 (YCBCR 4:2:2) = 1 if sink device supports YCBCR 4:2:2 + * in addition to RGB + */ + pRXCap->pref_colorspace = BlockBuf[3] & 0x30; + + pRXCap->native_VIC = 0xff; + + for (offset = 4 ; offset < End ; ) { + tag = BlockBuf[offset] >> 5; + count = BlockBuf[offset] & 0x1f; + switch (tag) { + case HDMI_EDID_BLOCK_TYPE_AUDIO: + offset++; + offset += count; + break; + + case HDMI_EDID_BLOCK_TYPE_VIDEO: + offset++; + for (i = 0 ; i < count ; i++) { + unsigned char VIC; + VIC = BlockBuf[offset + i] & (~0x80); + pRXCap->VIC[pRXCap->VIC_count] = VIC; + if (BlockBuf[offset + i] & 0x80) + pRXCap->native_VIC = VIC; + pRXCap->VIC_count++; + } + offset += count; + break; + + case HDMI_EDID_BLOCK_TYPE_VENDER: + offset++; + if ((BlockBuf[offset] == 0x03) && + (BlockBuf[offset+1] == 0x0c) && + (BlockBuf[offset+2] == 0x00)) + pRXCap->IEEEOUI = 0x000c03; + else + goto case_hf; + pRXCap->ColorDeepSupport = + (unsigned long)BlockBuf[offset+5]; + printf("HDMI_EDID_BLOCK_TYPE_VENDER: pRXCap->ColorDeepSupport=0x%x\n", pRXCap->ColorDeepSupport); + set_vsdb_dc_cap(pRXCap); + pRXCap->Max_TMDS_Clock1 = + (unsigned long)BlockBuf[offset+6]; + if (count > 7) { + tmp = BlockBuf[offset+7]; + idx = offset + 8; + if (tmp & (1<<6)) + idx += 2; + if (tmp & (1<<7)) + idx += 2; + if (tmp & (1<<5)) { + idx += 1; + /* valid 4k */ + if (BlockBuf[idx] & 0xe0) { + hdmitx_edid_4k2k_parse( + pRXCap, + &BlockBuf[idx + 1], + BlockBuf[idx] >> 5); + } + } + } + goto case_next; +case_hf: + if ((BlockBuf[offset] == 0xd8) && + (BlockBuf[offset+1] == 0x5d) && + (BlockBuf[offset+2] == 0xc4)) + pRXCap->HF_IEEEOUI = 0xd85dc4; + pRXCap->Max_TMDS_Clock2 = BlockBuf[offset+4]; + pRXCap->scdc_present = + !!(BlockBuf[offset+5] & (1 << 7)); + pRXCap->scdc_rr_capable = + !!(BlockBuf[offset+5] & (1 << 6)); + pRXCap->lte_340mcsc_scramble = + !!(BlockBuf[offset+5] & (1 << 3)); + set_vsdb_dc_420_cap(pRXCap, + &BlockBuf[offset]); +case_next: + offset += count; /* ignore the remaind. */ + break; + + case HDMI_EDID_BLOCK_TYPE_SPEAKER: + offset++; + offset += count; + break; + + case HDMI_EDID_BLOCK_TYPE_VESA: + offset++; + offset += count; + break; + + case HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG: + { + unsigned char ext_tag = 0; + + ext_tag = BlockBuf[offset+1]; + switch (ext_tag) { + case EXTENSION_VENDOR_SPECIFIC: + Edid_ParsingVendSpec(pRXCap, + &BlockBuf[offset]); + break; + case EXTENSION_COLORMETRY_TAG: + pRXCap->colorimetry_data = + BlockBuf[offset + 2]; + break; + case EXTENSION_DRM_STATIC_TAG: + Edid_ParsingDRMStaticBlock(pRXCap, + &BlockBuf[offset]); + break; + case EXTENSION_VFPDB_TAG: +/* Just record VFPDB offset address, call Edid_ParsingVFPDB() after DTD + * parsing, in case that + * SVR >=129 and SVR <=144, Interpret as the Kth DTD in the EDID, + * where K = SVR – 128 (for K=1 to 16) + */ + vfpdb_offset = &BlockBuf[offset]; + break; + case EXTENSION_Y420_VDB_TAG: + Edid_ParsingY420VDBBlock(pRXCap, + &BlockBuf[offset]); + break; + case EXTENSION_Y420_CMDB_TAG: + Edid_ParsingY420CMDBBlock(pRXCap, + &BlockBuf[offset]); + break; + default: + break; + } + } + offset += count+1; + break; + + case HDMI_EDID_BLOCK_TYPE_RESERVED: + offset++; + offset += count; + break; + + case HDMI_EDID_BLOCK_TYPE_RESERVED2: + offset++; + offset += count; + break; + + default: + break; + } + } + + Edid_Y420CMDB_PostProcess(pRXCap); + idx = BlockBuf[3] & 0xf; + for (i = 0; i < idx; i++) + Edid_DTD_parsing(pRXCap, &BlockBuf[BlockBuf[2] + i * 18]); + if (vfpdb_offset) + Edid_ParsingVFPDB(pRXCap, vfpdb_offset); + + return 0; +} + +void Edid_MonitorCapable861(struct rx_cap *pRXCap, + unsigned char edid_flag) +{ + if (edid_flag & 0x20) + pRXCap->support_ycbcr444_flag = 1; + if (edid_flag & 0x10) + pRXCap->support_ycbcr422_flag = 1; + printf("Edid_MonitorCapable861: ycbcr444=%d, ycbcr422=%d\n", + pRXCap->support_ycbcr444_flag, pRXCap->support_ycbcr422_flag); +} + +static bool is_4k60_supported(struct rx_cap *prxcap) +{ + int i = 0; + + if (!prxcap) + return false; + + for (i = 0; (i < prxcap->VIC_count) && (i < VIC_MAX_NUM); i++) { + if (((prxcap->VIC[i] & 0xff) == HDMI_3840x2160p50_16x9) || + ((prxcap->VIC[i] & 0xff) == HDMI_3840x2160p60_16x9)) { + return true; + } + } + return false; +} + +static void check_dv_truly_support(struct rx_cap *prxcap, struct dv_info *dv) +{ + unsigned int max_tmds_clk = 0; + + if (!prxcap || !dv) + return; + if ((dv->ieeeoui == DV_IEEE_OUI) && (dv->ver <= 2)) { + /* check max tmds rate to determine if 4k60 DV can truly be + * supported. + */ + if (prxcap->Max_TMDS_Clock2) { + max_tmds_clk = prxcap->Max_TMDS_Clock2 * 5; + } else { + /* Default min is 74.25 / 5 */ + if (prxcap->Max_TMDS_Clock1 < 0xf) + prxcap->Max_TMDS_Clock1 = 0x1e; + max_tmds_clk = prxcap->Max_TMDS_Clock1 * 5; + } + if (dv->ver == 0) + dv->sup_2160p60hz = dv->sup_2160p60hz && + (max_tmds_clk >= 594); + + if ((dv->ver == 1) && (dv->length == 0xB)) { + if (dv->low_latency == 0x00) { + /*standard mode */ + dv->sup_2160p60hz = dv->sup_2160p60hz && + (max_tmds_clk >= 594); + } else if (dv->low_latency == 0x01) { + /* both standard and LL are supported. 4k60 LL + * DV support should/can be determined using + * video formats supported inthe E-EDID as flag + * sup_2160p60hz might not be set. + */ + if ((dv->sup_2160p60hz || + is_4k60_supported(prxcap)) && + (max_tmds_clk >= 594)) + dv->sup_2160p60hz = 1; + else + dv->sup_2160p60hz = 0; + } + } + + if ((dv->ver == 1) && (dv->length == 0xE)) + dv->sup_2160p60hz = dv->sup_2160p60hz && + (max_tmds_clk >= 594); + + if (dv->ver == 2) { + /* 4k60 DV support should be determined using video + * formats supported in the EEDID as flag sup_2160p60hz + * is not applicable for VSVDB V2. + */ + if (is_4k60_supported(prxcap) && (max_tmds_clk >= 594)) + dv->sup_2160p60hz = 1; + else + dv->sup_2160p60hz = 0; + } + } +} + +/* + * Parsing RAW EDID data from edid to pRXCap + */ +unsigned int hdmi_edid_parsing(unsigned char *EDID_buf, struct rx_cap *pRXCap) +{ + int i, j; + int BlockCount = EDID_buf[126]; + int idx[4]; + unsigned char CheckSum; + struct dv_info *dv = &pRXCap->dv_info; + + /* Clear all parsing data */ + memset(pRXCap, 0, sizeof(struct rx_cap)); + pRXCap->IEEEOUI = 0x000c03; /* Default is HDMI device */ + + /* If edid data corrupted, no parse */ + /* + if (check_dvi_hdmi_edid_valid(EDID_buf) == 0) + return 0; + */ + + idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS; + idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS; + idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS; + idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS; + for (i = 0; i < 4; i++) { + if ((EDID_buf[idx[i]]) && (EDID_buf[idx[i] + 1])) + Edid_DTD_parsing(pRXCap, &EDID_buf[idx[i]]); + } + + if (BlockCount == 0) + pRXCap->IEEEOUI = 0; + + for (i = 1; i <= BlockCount; i++) { + if ((BlockCount > 1) && (i == 1)) + CheckSum = 0; /* ignore the block1 data */ + else { + for (j = 0, CheckSum = 0 ; j < 128 ; j++) { + CheckSum += EDID_buf[i*128 + j]; + CheckSum &= 0xFF; + } + if (CheckSum == 0) { + Edid_MonitorCapable861( + pRXCap, + EDID_buf[i * 128 + 3]); + } + } + if (EDID_buf[i*128+0] == 0x2) + hdmitx_edid_block_parse(pRXCap, &(EDID_buf[i*128])); + } + check_dv_truly_support(pRXCap, dv); +/* + * Because DTDs are not able to represent some Video Formats, which can be + * represented as SVDs and might be preferred by Sinks, the first DTD in the + * base EDID data structure and the first SVD in the first CEA Extension can + * differ. When the first DTD and SVD do not match and the total number of + * DTDs defining Native Video Formats in the whole EDID is zero, the first + * SVD shall take precedence. + */ + if (!pRXCap->flag_vfpdb && (pRXCap->preferred_mode != pRXCap->VIC[0]) && + (pRXCap->number_of_dtd == 0)) { + pr_info("hdmitx: edid: change preferred_mode from %d to %d\n", + pRXCap->preferred_mode, pRXCap->VIC[0]); + pRXCap->preferred_mode = pRXCap->VIC[0]; + } + + return 1; +} + +int hdmitx_edid_VIC_support(enum hdmi_vic vic) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) { + if (vic == dispmode_vic_tab[i].VIC) + return 1; + } + + return 0; +} + +enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode) +{ + enum hdmi_vic vic = HDMI_unkown; + int i; + + for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) { + if (strncmp(disp_mode, dispmode_vic_tab[i].disp_mode, + strlen(dispmode_vic_tab[i].disp_mode)) == 0) { + vic = dispmode_vic_tab[i].VIC; + break; + } + } + + if (vic == HDMI_unkown) + printf("not find mapped vic\n"); + + return vic; +} + +const char *hdmitx_edid_vic_tab_map_string(enum hdmi_vic vic) +{ + int i; + const char *disp_str = NULL; + + for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) { + if (vic == dispmode_vic_tab[i].VIC) { + disp_str = dispmode_vic_tab[i].disp_mode; + break; + } + } + + return disp_str; +} + +const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic) +{ + int i; + const char *disp_str = NULL; + + for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) { + if (vic == dispmode_vic_tab[i].VIC) { + disp_str = dispmode_vic_tab[i].disp_mode; + break; + } + } + + return disp_str; +} + +static bool is_rx_support_y420(struct hdmitx_dev *hdev) +{ + enum hdmi_vic vic = HDMI_unkown; + + vic = hdmitx_edid_get_VIC(hdev, "2160p60hz420", 0); + if (vic != HDMI_unkown) + return 1; + + vic = hdmitx_edid_get_VIC(hdev, "2160p50hz420", 0); + if (vic != HDMI_unkown) + return 1; + + vic = hdmitx_edid_get_VIC(hdev, "smpte60hz420", 0); + if (vic != HDMI_unkown) + return 1; + + vic = hdmitx_edid_get_VIC(hdev, "smpte50hz420", 0); + if (vic != HDMI_unkown) + return 1; + + return 0; +} + +/* For some TV's EDID, there maybe exist some information ambiguous. + * Such as EDID declears support 2160p60hz(Y444 8bit), but no valid + * Max_TMDS_Clock2 to indicate that it can support 5.94G signal. + */ +bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev, + struct hdmi_format_para *para) +{ + bool valid = 0; + struct rx_cap *prxcap = NULL; + struct dv_info *dv = &hdev->RXCap.dv_info; + unsigned int rx_max_tmds_clk = 0; + unsigned int calc_tmds_clk = 0; + int i = 0; + int svd_flag = 0; + /* Default max color depth is 24 bit */ + enum hdmi_color_depth rx_y444_max_dc = HDMI_COLOR_DEPTH_24B; + enum hdmi_color_depth rx_y422_max_dc = HDMI_COLOR_DEPTH_24B; + enum hdmi_color_depth rx_y420_max_dc = HDMI_COLOR_DEPTH_24B; + enum hdmi_color_depth rx_rgb_max_dc = HDMI_COLOR_DEPTH_24B; + + if (!hdev || !para) + return 0; + + if (strcmp(para->sname, "invalid") == 0) + return 0; + /* exclude such as: 2160p60hz YCbCr444 10bit */ + switch (para->vic) { + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p60_256x135: + case HDMI_3840x2160p50_64x27: + case HDMI_3840x2160p60_64x27: + if ((para->cs == HDMI_COLOR_FORMAT_RGB) || + (para->cs == HDMI_COLOR_FORMAT_444)) + if (para->cd != HDMI_COLOR_DEPTH_24B) + return 0; + break; + default: + break; + } + + prxcap = &hdev->RXCap; + + /* DVI case, only 8bit */ + if (prxcap->IEEEOUI != HDMI_IEEEOUI) { + if (para->cd != HDMI_COLOR_DEPTH_24B) + return 0; + } + + /* target mode is not contained at RX SVD */ + for (i = 0; (i < prxcap->VIC_count) && (i < VIC_MAX_NUM); i++) { + if ((para->vic & 0xff) == (prxcap->VIC[i] & 0xff)) + svd_flag = 1; + } + if (svd_flag == 0) + return 0; + + /* Get RX Max_TMDS_Clock */ + if (prxcap->Max_TMDS_Clock2) { + rx_max_tmds_clk = prxcap->Max_TMDS_Clock2 * 5; + } else { + /* Default min is 74.25 / 5 */ + if (prxcap->Max_TMDS_Clock1 < 0xf) + prxcap->Max_TMDS_Clock1 = 0x1e; + rx_max_tmds_clk = prxcap->Max_TMDS_Clock1 * 5; + } + + calc_tmds_clk = para->tmds_clk; + if (para->cs == HDMI_COLOR_FORMAT_420) + calc_tmds_clk = calc_tmds_clk / 2; + if (para->cs != HDMI_COLOR_FORMAT_422) { + switch (para->cd) { + case HDMI_COLOR_DEPTH_30B: + calc_tmds_clk = calc_tmds_clk * 5 / 4; + break; + case HDMI_COLOR_DEPTH_36B: + calc_tmds_clk = calc_tmds_clk * 3 / 2; + break; + case HDMI_COLOR_DEPTH_48B: + calc_tmds_clk = calc_tmds_clk * 2; + break; + case HDMI_COLOR_DEPTH_24B: + default: + calc_tmds_clk = calc_tmds_clk * 1; + break; + } + } + calc_tmds_clk = calc_tmds_clk / 1000; + printf("RX tmds clk: %d Calc clk: %d\n", + rx_max_tmds_clk, calc_tmds_clk); + if (calc_tmds_clk < rx_max_tmds_clk) + valid = 1; + else + return 0; + + if (para->cs == HDMI_COLOR_FORMAT_444) { + /* Rx may not support Y444 */ + if (!(prxcap->native_Mode & (1 << 5))) + return 0; + if ((prxcap->dc_y444 && prxcap->dc_30bit) || + (dv->sup_10b_12b_444 == 0x1)) + rx_y444_max_dc = HDMI_COLOR_DEPTH_30B; + if ((prxcap->dc_y444 && prxcap->dc_36bit) || + (dv->sup_10b_12b_444 == 0x2)) + rx_y444_max_dc = HDMI_COLOR_DEPTH_36B; + if (para->cd <= rx_y444_max_dc) + valid = 1; + else + valid = 0; + return valid; + } + if (para->cs == HDMI_COLOR_FORMAT_422) { + /* Rx may not support Y422 */ + if (!(prxcap->native_Mode & (1 << 4))) + return 0; + if (prxcap->dc_y444 && prxcap->dc_30bit) + rx_y422_max_dc = HDMI_COLOR_DEPTH_30B; + if ((prxcap->dc_y444 && prxcap->dc_36bit) || + (dv->sup_yuv422_12bit)) + rx_y422_max_dc = HDMI_COLOR_DEPTH_36B; + if (para->cd <= rx_y422_max_dc) + valid = 1; + else + valid = 0; + return valid; + } + if (para->cs == HDMI_COLOR_FORMAT_RGB) { + /* Always assume RX supports RGB444 */ + if ((prxcap->dc_30bit) || (dv->sup_10b_12b_444 == 0x1)) + rx_rgb_max_dc = HDMI_COLOR_DEPTH_30B; + if ((prxcap->dc_36bit) || (dv->sup_10b_12b_444 == 0x2)) + rx_rgb_max_dc = HDMI_COLOR_DEPTH_36B; + if (para->cd <= rx_rgb_max_dc) + valid = 1; + else + valid = 0; + return valid; + } + if (para->cs == HDMI_COLOR_FORMAT_420) { + if (!is_rx_support_y420(hdev)) + return 0; + if (prxcap->dc_30bit_420) + rx_y420_max_dc = HDMI_COLOR_DEPTH_30B; + if (prxcap->dc_36bit_420) + rx_y420_max_dc = HDMI_COLOR_DEPTH_36B; + if (para->cd <= rx_y420_max_dc) + valid = 1; + else + valid = 0; + return valid; + } + + return valid; +} + +bool is_supported_mode_attr(hdmi_data_t *hdmi_data, char *mode_attr) +{ + struct hdmi_format_para *para = NULL; + struct hdmitx_dev *hdev = NULL; + + if (!hdmi_data || !mode_attr) + return false; + hdev = container_of(hdmi_data->pRXCap, + struct hdmitx_dev, RXCap); + + if (mode_attr[0]) { + if (!pre_process_str(mode_attr)) + return false; + para = hdmi_tst_fmt_name(mode_attr, mode_attr); + } + if (para) { + printf("sname = %s\n", para->sname); + printf("char_clk = %d\n", para->tmds_clk); + printf("cd = %d\n", para->cd); + printf("cs = %d\n", para->cs); + } + + return hdmitx_edid_check_valid_mode(hdev, para); +} + +/* force_flag: 0 means check with RX's edid */ +/* 1 means no check wich RX's edid */ +enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev, + const char *disp_mode, char force_flag) +{ + struct rx_cap *prxcap = &hdev->RXCap; + int j; + enum hdmi_vic vic = hdmitx_edid_vic_tab_map_vic(disp_mode); + #if 0 + struct hdmi_format_para *para = NULL; + enum hdmi_vic *vesa_t = &hdev->RXCap.vesa_timing[0]; + enum hdmi_vic vesa_vic; + + if (vic >= HDMITX_VESA_OFFSET) + vesa_vic = vic; + else + vesa_vic = HDMI_unkown; + #endif + if (vic != HDMI_unkown) { + if (force_flag == 0) { + for (j = 0 ; j < prxcap->VIC_count ; j++) { + if (prxcap->VIC[j] == vic) + break; + } + if (j >= prxcap->VIC_count) + vic = HDMI_unkown; + } + } + #if 0 + if ((vic == HDMI_unkown) && + (vesa_vic != HDMI_unkown)) { + for (j = 0; vesa_t[j] && j < VESA_MAX_TIMING; j++) { + para = hdmi_get_fmt_paras(vesa_t[j]); + if (para) { + if ((para->vic >= HDMITX_VESA_OFFSET) && + (vesa_vic == para->vic)) { + vic = para->vic; + break; + } + } + } + } + #endif + return vic; +} + +#define EDID_MAX_BLOCK 4 +static bool hdmitx_check_edid_all_zeros(unsigned char *buf) +{ + unsigned int i = 0, j = 0; + unsigned int chksum = 0; + + for (j = 0; j < EDID_MAX_BLOCK; j++) { + chksum = 0; + for (i = 0; i < 128; i++) + chksum += buf[i + j * 128]; + if (chksum != 0) + return false; + } + return true; +} + +static bool hdmitx_edid_header_invalid(unsigned char *buf) +{ + bool base_blk_invalid = false; + bool ext_blk_invalid = false; + bool ret = false; + int i = 0; + + if ((buf[0] != 0) || (buf[7] != 0)) { + base_blk_invalid = true; + } else { + for (i = 1; i < 7; i++) { + if (buf[i] != 0xff) { + base_blk_invalid = true; + break; + } + } + } + /* judge header strickly, only if both header invalid */ + if (buf[0x7e] > 0) { + if ((buf[0x80] != 0x2) && (buf[0x80] != 0xf0)) + ext_blk_invalid = true; + ret = base_blk_invalid && ext_blk_invalid; + } else { + ret = base_blk_invalid; + } + + return ret; +} + +static bool hdmitx_edid_notify_ng(unsigned char *buf) +{ + if (!buf) + return true; + /* notify EDID NG to systemcontrol */ + if (hdmitx_check_edid_all_zeros(buf)) { + printf("ERR: edid all zero\n"); + return true; + } else if ((buf[0x7e] > 3) && + hdmitx_edid_header_invalid(buf)) { + printf("ERR: edid header invalid\n"); + return true; + } + /* may extend NG case here */ + + return false; +} + +bool edid_parsing_ok(struct hdmitx_dev *hdev) +{ + if (!hdev) + return false; + + if (hdmitx_edid_notify_ng(hdev->rawedid)) + return false; + return true; +} +
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_parameters.c new file mode 100644 index 0000000..8758581 --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_parameters.c
@@ -0,0 +1,2440 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <linux/stddef.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> + +static struct hdmi_format_para fmt_para_1920x1080p60_16x9 = { + .vic = HDMI_1920x1080p60_16x9, + .name = "1920x1080p60hz", + .sname = "1080p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 148500, + .timing = { + .pixel_freq = 148500, + .h_freq = 67500, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2200, + .h_blank = 280, + .h_front = 88, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1125, + .v_blank = 45, + .v_front = 4, + .v_sync = 5, + .v_back = 36, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080p30_16x9 = { + .vic = HDMI_1920x1080p30_16x9, + .name = "1920x1080p30hz", + .sname = "1080p30hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 74250, + .timing = { + .pixel_freq = 74250, + .h_freq = 67500, + .v_freq = 30000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2200, + .h_blank = 280, + .h_front = 88, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1125, + .v_blank = 45, + .v_front = 4, + .v_sync = 5, + .v_back = 36, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080p50_16x9 = { + .vic = HDMI_1920x1080p50_16x9, + .name = "1920x1080p50hz", + .sname = "1080p50hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 148500, + .timing = { + .pixel_freq = 148500, + .h_freq = 56250, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2640, + .h_blank = 720, + .h_front = 528, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1125, + .v_blank = 45, + .v_front = 4, + .v_sync = 5, + .v_back = 36, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080p100_16x9 = { + .vic = HDMI_1920x1080p100_16x9, + .name = "1920x1080p100hz", + .sname = "1080p100hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 297000, + .h_freq = 112500, + .v_freq = 100000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2640, + .h_blank = 720, + .h_front = 528, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1125, + .v_blank = 45, + .v_front = 4, + .v_sync = 5, + .v_back = 36, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080p120_16x9 = { + .vic = HDMI_1920x1080p120_16x9, + .name = "1920x1080p120hz", + .sname = "1080p120hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 297000, + .h_freq = 135000, + .v_freq = 120000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2200, + .h_blank = 280, + .h_front = 88, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1125, + .v_blank = 45, + .v_front = 4, + .v_sync = 5, + .v_back = 36, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080p25_16x9 = { + .vic = HDMI_1920x1080p25_16x9, + .name = "1920x1080p25hz", + .sname = "1080p25hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 148500, + .timing = { + .pixel_freq = 148500, + .h_freq = 56250, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2640, + .h_blank = 720, + .h_front = 528, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1125, + .v_blank = 45, + .v_front = 4, + .v_sync = 5, + .v_back = 36, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080p24_16x9 = { + .vic = HDMI_1920x1080p24_16x9, + .name = "1920x1080p24hz", + .sname = "1080p24hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 74250, + .timing = { + .pixel_freq = 74250, + .h_freq = 27000, + .v_freq = 24000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2750, + .h_blank = 830, + .h_front = 638, + .h_sync = 44, + .h_back = 148, + .v_active = 1080, + .v_total = 1125, + .v_blank = 45, + .v_front = 4, + .v_sync = 5, + .v_back = 36, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_3840x2160p30_16x9 = { + .vic = HDMI_3840x2160p30_16x9, + .name = "3840x2160p30hz", + .sname = "2160p30hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 297000, + .h_freq = 67500, + .v_freq = 30000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 3840, + .h_total = 4400, + .h_blank = 560, + .h_front = 176, + .h_sync = 88, + .h_back = 296, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_3840x2160p60_16x9 = { + .vic = HDMI_3840x2160p60_16x9, + .name = "3840x2160p60hz", + .sname = "2160p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 1, + .tmds_clk_div40 = 1, + .tmds_clk = 594000, + .timing = { + .pixel_freq = 594000, + .h_freq = 135000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 3840, + .h_total = 4400, + .h_blank = 560, + .h_front = 176, + .h_sync = 88, + .h_back = 296, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_3840x2160p60_y420_16x9 = { + .vic = HDMI_3840x2160p60_16x9_Y420, + .name = "3840x2160p60hz420", + .sname = "2160p60hz420", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 1, + .tmds_clk_div40 = 1, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 594000, + .h_freq = 135000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 3840 / 2, + .h_total = 4400 / 2, + .h_blank = 560 / 2, + .h_front = 176 / 2, + .h_sync = 88 / 2, + .h_back = 296 / 2, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_3840x2160p50_16x9 = { + .vic = HDMI_3840x2160p50_16x9, + .name = "3840x2160p50hz", + .sname = "2160p50hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 1, + .tmds_clk_div40 = 1, + .tmds_clk = 594000, + .timing = { + .pixel_freq = 594000, + .h_freq = 112500, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 3840, + .h_total = 5280, + .h_blank = 1440, + .h_front = 1056, + .h_sync = 88, + .h_back = 296, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_3840x2160p50_y420_16x9 = { + .vic = HDMI_3840x2160p50_16x9_Y420, + .name = "3840x2160p50hz420", + .sname = "2160p50hz420", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 1, + .tmds_clk_div40 = 1, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 594000, + .h_freq = 112500, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 3840 / 2, + .h_total = 5280 / 2, + .h_blank = 1440 / 2, + .h_front = 1056 / 2, + .h_sync = 88 / 2, + .h_back = 296 / 2, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_3840x2160p25_16x9 = { + .vic = HDMI_3840x2160p25_16x9, + .name = "3840x2160p25hz", + .sname = "2160p25hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 297000, + .h_freq = 56250, + .v_freq = 25000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 3840, + .h_total = 5280, + .h_blank = 1440, + .h_front = 1056, + .h_sync = 88, + .h_back = 296, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_3840x2160p24_16x9 = { + .vic = HDMI_3840x2160p24_16x9, + .name = "3840x2160p24hz", + .sname = "2160p24hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 297000, + .h_freq = 54000, + .v_freq = 24000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 3840, + .h_total = 5500, + .h_blank = 1660, + .h_front = 1276, + .h_sync = 88, + .h_back = 296, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_4096x2160p24_256x135 = { + .vic = HDMI_4096x2160p24_256x135, + .name = "4096x2160p24hz", + .sname = "smpte24hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 297000, + .h_freq = 54000, + .v_freq = 24000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 4096, + .h_total = 5500, + .h_blank = 1404, + .h_front = 1020, + .h_sync = 88, + .h_back = 296, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_4096x2160p25_256x135 = { + .vic = HDMI_4096x2160p25_256x135, + .name = "4096x2160p25hz", + .sname = "smpte25hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 297000, + .h_freq = 56250, + .v_freq = 25000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 4096, + .h_total = 5280, + .h_blank = 1184, + .h_front = 968, + .h_sync = 88, + .h_back = 128, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_4096x2160p30_256x135 = { + .vic = HDMI_4096x2160p30_256x135, + .name = "4096x2160p30hz", + .sname = "smpte30hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 297000, + .h_freq = 67500, + .v_freq = 30000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 4096, + .h_total = 4400, + .h_blank = 304, + .h_front = 88, + .h_sync = 88, + .h_back = 128, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_4096x2160p50_256x135 = { + .vic = HDMI_4096x2160p50_256x135, + .name = "4096x2160p50hz", + .sname = "smpte50hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 1, + .tmds_clk_div40 = 1, + .tmds_clk = 594000, + .timing = { + .pixel_freq = 594000, + .h_freq = 112500, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 4096, + .h_total = 5280, + .h_blank = 1184, + .h_front = 968, + .h_sync = 88, + .h_back = 128, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_4096x2160p50_y420_256x135 = { + .vic = HDMI_4096x2160p50_256x135_Y420, + .name = "4096x2160p50hz420", + .sname = "smpte50hz420", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 1, + .tmds_clk_div40 = 1, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 594000, + .h_freq = 112500, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 4096 / 2, + .h_total = 5280 / 2, + .h_blank = 1184 / 2, + .h_front = 968 / 2, + .h_sync = 88 / 2, + .h_back = 128 / 2, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_4096x2160p60_256x135 = { + .vic = HDMI_4096x2160p60_256x135, + .name = "4096x2160p60hz", + .sname = "smpte60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 1, + .tmds_clk_div40 = 1, + .tmds_clk = 594000, + .timing = { + .pixel_freq = 594000, + .h_freq = 135000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 4096, + .h_total = 4400, + .h_blank = 304, + .h_front = 88, + .h_sync = 88, + .h_back = 128, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_4096x2160p60_y420_256x135 = { + .vic = HDMI_4096x2160p60_256x135_Y420, + .name = "4096x2160p60hz420", + .sname = "smpte60hz420", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 1, + .tmds_clk_div40 = 1, + .tmds_clk = 297000, + .timing = { + .pixel_freq = 594000, + .h_freq = 135000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 4096 / 2, + .h_total = 4400 / 2, + .h_blank = 304 / 2, + .h_front = 88 / 2, + .h_sync = 88 / 2, + .h_back = 128 / 2, + .v_active = 2160, + .v_total = 2250, + .v_blank = 90, + .v_front = 8, + .v_sync = 10, + .v_back = 72, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080i60_16x9 = { + .vic = HDMI_1920x1080i60_16x9, + .name = "1920x1080i60hz", + .sname = "1080i60hz", + .pixel_repetition_factor = 0, + .progress_mode = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 74250, + .timing = { + .pixel_freq = 74250, + .h_freq = 33750, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2200, + .h_blank = 280, + .h_front = 88, + .h_sync = 44, + .h_back = 148, + .v_active = 1080/2, + .v_total = 1125, + .v_blank = 45/2, + .v_front = 2, + .v_sync = 5, + .v_back = 15, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080i50_16x9 = { + .vic = HDMI_1920x1080i50_16x9, + .name = "1920x1080i50hz", + .sname = "1080i50hz", + .pixel_repetition_factor = 0, + .progress_mode = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 74250, + .timing = { + .pixel_freq = 74250, + .h_freq = 28125, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2640, + .h_blank = 720, + .h_front = 528, + .h_sync = 44, + .h_back = 148, + .v_active = 1080/2, + .v_total = 1125, + .v_blank = 45/2, + .v_front = 2, + .v_sync = 5, + .v_back = 15, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080i100_16x9 = { + .vic = HDMI_1920x1080i100_16x9, + .name = "1920x1080i100hz", + .sname = "1080i100hz", + .pixel_repetition_factor = 0, + .progress_mode = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 148500, + .timing = { + .pixel_freq = 148500, + .h_freq = 56250, + .v_freq = 100000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2640, + .h_blank = 720, + .h_front = 528, + .h_sync = 44, + .h_back = 148, + .v_active = 1080/2, + .v_total = 1125, + .v_blank = 45/2, + .v_front = 2, + .v_sync = 5, + .v_back = 15, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1920x1080i120_16x9 = { + .vic = HDMI_1920x1080i120_16x9, + .name = "1920x1080i120hz", + .sname = "1080i120hz", + .pixel_repetition_factor = 0, + .progress_mode = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 148500, + .timing = { + .pixel_freq = 148500, + .h_freq = 67500, + .v_freq = 120000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2200, + .h_blank = 280, + .h_front = 88, + .h_sync = 44, + .h_back = 148, + .v_active = 1080/2, + .v_total = 1125, + .v_blank = 45/2, + .v_front = 2, + .v_sync = 5, + .v_back = 15, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1280x720p60_16x9 = { + .vic = HDMI_1280x720p60_16x9, + .name = "1280x720p60hz", + .sname = "720p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 74250, + .timing = { + .pixel_freq = 74250, + .h_freq = 45000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1650, + .h_blank = 370, + .h_front = 110, + .h_sync = 40, + .h_back = 220, + .v_active = 720, + .v_total = 750, + .v_blank = 30, + .v_front = 5, + .v_sync = 5, + .v_back = 20, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1280x720p50_16x9 = { + .vic = HDMI_1280x720p50_16x9, + .name = "1280x720p50hz", + .sname = "720p50hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 74250, + .timing = { + .pixel_freq = 74250, + .h_freq = 37500, + .v_freq = 50000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1980, + .h_blank = 700, + .h_front = 440, + .h_sync = 40, + .h_back = 220, + .v_active = 720, + .v_total = 750, + .v_blank = 30, + .v_front = 5, + .v_sync = 5, + .v_back = 20, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1280x720p100_16x9 = { + .vic = HDMI_1280x720p100_16x9, + .name = "1280x720p100hz", + .sname = "720p100hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 148500, + .timing = { + .pixel_freq = 148500, + .h_freq = 75000, + .v_freq = 100000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1980, + .h_blank = 700, + .h_front = 440, + .h_sync = 40, + .h_back = 220, + .v_active = 720, + .v_total = 750, + .v_blank = 30, + .v_front = 5, + .v_sync = 5, + .v_back = 20, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_1280x720p120_16x9 = { + .vic = HDMI_1280x720p120_16x9, + .name = "1280x720p120hz", + .sname = "720p120hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 148500, + .timing = { + .pixel_freq = 148500, + .h_freq = 90000, + .v_freq = 120000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1650, + .h_blank = 370, + .h_front = 110, + .h_sync = 40, + .h_back = 220, + .v_active = 720, + .v_total = 750, + .v_blank = 30, + .v_front = 5, + .v_sync = 5, + .v_back = 20, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_720x480p60_16x9 = { + .vic = HDMI_720x480p60_16x9, + .name = "720x480p60hz", + .sname = "480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 27000, + .timing = { + .pixel_freq = 27000, + .h_freq = 31469, + .v_freq = 59940, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 720, + .h_total = 858, + .h_blank = 138, + .h_front = 16, + .h_sync = 62, + .h_back = 60, + .v_active = 480, + .v_total = 525, + .v_blank = 45, + .v_front = 9, + .v_sync = 6, + .v_back = 30, + .v_sync_ln = 7, + }, +}; + +static struct hdmi_format_para fmt_para_720x480p60_4x3 = { + .vic = HDMI_720x480p60_4x3, + .name = "720x480p60hz_4x3", + .sname = "480p60hz_4x3", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 27000, + .timing = { + .pixel_freq = 27000, + .h_freq = 31469, + .v_freq = 59940, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 720, + .h_total = 858, + .h_blank = 138, + .h_front = 16, + .h_sync = 62, + .h_back = 60, + .v_active = 480, + .v_total = 525, + .v_blank = 45, + .v_front = 9, + .v_sync = 6, + .v_back = 30, + .v_sync_ln = 7, + }, +}; + +static struct hdmi_format_para fmt_para_720x480p120_16x9 = { + .vic = HDMI_720x480p120_16x9, + .name = "720x480p120hz", + .sname = "480p120hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 54000, + .timing = { + .pixel_freq = 54000, + .h_freq = 62937, + .v_freq = 119880, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 720, + .h_total = 858, + .h_blank = 138, + .h_front = 16, + .h_sync = 62, + .h_back = 60, + .v_active = 480, + .v_total = 525, + .v_blank = 45, + .v_front = 9, + .v_sync = 6, + .v_back = 30, + .v_sync_ln = 7, + }, +}; + +static struct hdmi_format_para fmt_para_720x480i60_16x9 = { + .vic = HDMI_720x480i60_16x9, + .name = "720x480i60hz", + .sname = "480i60hz", + .pixel_repetition_factor = 1, + .progress_mode = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 27000, + .timing = { + .pixel_freq = 27000, + .h_freq = 15734, + .v_freq = 59940, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 1440, + .h_total = 1716, + .h_blank = 276, + .h_front = 38, + .h_sync = 124, + .h_back = 114, + .v_active = 480/2, + .v_total = 525, + .v_blank = 45/2, + .v_front = 4, + .v_sync = 3, + .v_back = 15, + .v_sync_ln = 4, + }, +}; + +static struct hdmi_format_para fmt_para_720x480i60_4x3 = { + .vic = HDMI_720x480i60_4x3, + .name = "720x480i60hz_4x3", + .sname = "480i60hz_4x3", + .pixel_repetition_factor = 1, + .progress_mode = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 27000, + .timing = { + .pixel_freq = 27000, + .h_freq = 15734, + .v_freq = 59940, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 1440, + .h_total = 1716, + .h_blank = 276, + .h_front = 38, + .h_sync = 124, + .h_back = 114, + .v_active = 480/2, + .v_total = 525, + .v_blank = 45/2, + .v_front = 4, + .v_sync = 3, + .v_back = 15, + .v_sync_ln = 4, + }, +}; + +static struct hdmi_format_para fmt_para_720x576p50_16x9 = { + .vic = HDMI_720x576p50_16x9, + .name = "720x576p50hz", + .sname = "576p50hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 27000, + .timing = { + .pixel_freq = 27000, + .h_freq = 31250, + .v_freq = 50000, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 720, + .h_total = 864, + .h_blank = 144, + .h_front = 12, + .h_sync = 64, + .h_back = 68, + .v_active = 576, + .v_total = 625, + .v_blank = 49, + .v_front = 5, + .v_sync = 5, + .v_back = 39, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_720x576p50_4x3 = { + .vic = HDMI_720x576p50_4x3, + .name = "720x576p50hz_4x3", + .sname = "576p50hz_4x3", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 27000, + .timing = { + .pixel_freq = 27000, + .h_freq = 31250, + .v_freq = 50000, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 720, + .h_total = 864, + .h_blank = 144, + .h_front = 12, + .h_sync = 64, + .h_back = 68, + .v_active = 576, + .v_total = 625, + .v_blank = 49, + .v_front = 5, + .v_sync = 5, + .v_back = 39, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_720x576p100_16x9 = { + .vic = HDMI_720x576p100_16x9, + .name = "720x576p100hz", + .sname = "576p100hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 54000, + .timing = { + .pixel_freq = 54000, + .h_freq = 62500, + .v_freq = 100000, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 720, + .h_total = 864, + .h_blank = 144, + .h_front = 12, + .h_sync = 64, + .h_back = 68, + .v_active = 576, + .v_total = 625, + .v_blank = 49, + .v_front = 5, + .v_sync = 5, + .v_back = 39, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_720x576i50_16x9 = { + .vic = HDMI_720x576i50_16x9, + .name = "720x576i50hz", + .sname = "576i50hz", + .pixel_repetition_factor = 1, + .progress_mode = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 27000, + .timing = { + .pixel_freq = 27000, + .h_freq = 15625, + .v_freq = 50000, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 1440, + .h_total = 1728, + .h_blank = 288, + .h_front = 24, + .h_sync = 126, + .h_back = 138, + .v_active = 576/2, + .v_total = 625, + .v_blank = 49/2, + .v_front = 2, + .v_sync = 3, + .v_back = 19, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_720x576i50_4x3 = { + .vic = HDMI_720x576i50_4x3, + .name = "720x576i50hz_4x3", + .sname = "576i50hz_4x3", + .pixel_repetition_factor = 1, + .progress_mode = 0, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 27000, + .timing = { + .pixel_freq = 27000, + .h_freq = 15625, + .v_freq = 50000, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 1440, + .h_total = 1728, + .h_blank = 288, + .h_front = 24, + .h_sync = 126, + .h_back = 138, + .v_active = 576/2, + .v_total = 625, + .v_blank = 49/2, + .v_front = 2, + .v_sync = 3, + .v_back = 19, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_non_hdmi_fmt = { + .vic = HDMI_unkown, + .name = "invalid", + .sname = "invalid", +}; + +static struct hdmi_format_para fmt_para_vesa_640x480p60_4x3 = { + .vic = HDMIV_640x480p60hz, + .name = "640x480p60hz", + .sname = "640x480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 25175, + .timing = { + .pixel_freq = 25175, + .h_freq = 26218, + .v_freq = 59940, + .vsync_polarity = 0, + .hsync_polarity = 0, + .h_active = 640, + .h_total = 800, + .h_blank = 160, + .h_front = 16, + .h_sync = 96, + .h_back = 48, + .v_active = 480, + .v_total = 525, + .v_blank = 45, + .v_front = 10, + .v_sync = 2, + .v_back = 33, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_800x480p60_4x3 = { + .vic = HDMIV_800x480p60hz, + .name = "800x480p60hz", + .sname = "800x480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 29760, + .timing = { + .pixel_freq = 29760, + .h_freq = 30000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 800, + .h_total = 992, + .h_blank = 192, + .h_front = 24, + .h_sync = 72, + .h_back = 96, + .v_active = 480, + .v_total = 500, + .v_blank = 20, + .v_front = 3, + .v_sync = 7, + .v_back = 10, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = { + .vic = HDMIV_800x600p60hz, + .name = "800x600p60hz", + .sname = "800x600p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 40000, + .timing = { + .pixel_freq = 66666, + .h_freq = 37879, + .v_freq = 60317, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 800, + .h_total = 1056, + .h_blank = 256, + .h_front = 40, + .h_sync = 128, + .h_back = 88, + .v_active = 600, + .v_total = 628, + .v_blank = 28, + .v_front = 1, + .v_sync = 4, + .v_back = 23, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_852x480p60_213x120 = { + .vic = HDMIV_852x480p60hz, + .name = "852x480p60hz", + .sname = "852x480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 30240, + .timing = { + .pixel_freq = 30240, + .h_freq = 31900, + .v_freq = 59960, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 852, + .h_total = 948, + .h_blank = 96, + .h_front = 40, + .h_sync = 16, + .h_back = 40, + .v_active = 480, + .v_total = 532, + .v_blank = 52, + .v_front = 10, + .v_sync = 2, + .v_back = 40, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_854x480p60_427x240 = { + .vic = HDMIV_854x480p60hz, + .name = "854x480p60hz", + .sname = "854x480p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 30240, + .timing = { + .pixel_freq = 30240, + .h_freq = 31830, + .v_freq = 59950, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 854, + .h_total = 950, + .h_blank = 96, + .h_front = 40, + .h_sync = 16, + .h_back = 40, + .v_active = 480, + .v_total = 531, + .v_blank = 51, + .v_front = 10, + .v_sync = 2, + .v_back = 39, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1024x600p60_17x10 = { + .vic = HDMIV_1024x600p60hz, + .name = "1024x600p60hz", + .sname = "1024x600p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 50400, + .timing = { + .pixel_freq = 50400, + .h_freq = 38280, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1024, + .h_total = 1344, + .h_blank = 320, + .h_front = 24, + .h_sync = 136, + .h_back = 160, + .v_active = 600, + .v_total = 638, + .v_blank = 38, + .v_front = 3, + .v_sync = 6, + .v_back = 29, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1024x768p60_4x3 = { + .vic = HDMIV_1024x768p60hz, + .name = "1024x768p60hz", + .sname = "1024x768p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 79500, + .timing = { + .pixel_freq = 79500, + .h_freq = 48360, + .v_freq = 60004, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1024, + .h_total = 1344, + .h_blank = 320, + .h_front = 24, + .h_sync = 136, + .h_back = 160, + .v_active = 768, + .v_total = 806, + .v_blank = 38, + .v_front = 3, + .v_sync = 6, + .v_back = 29, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1152x864p75_4x3 = { + .vic = HDMIV_1152x864p75hz, + .name = "1152x864p75hz", + .sname = "1152x864p75hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 108000, + .timing = { + .pixel_freq = 108000, + .h_freq = 67500, + .v_freq = 75000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1152, + .h_total = 1600, + .h_blank = 448, + .h_front = 64, + .h_sync = 128, + .h_back = 256, + .v_active = 864, + .v_total = 900, + .v_blank = 36, + .v_front = 1, + .v_sync = 3, + .v_back = 32, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1280x600p60_32x15 = { +#if 0 /* TODO */ + .vic = HDMIV_1280x600p60hz, + .name = "1280x600p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = , + .timing = { + .pixel_freq = , + .h_freq = , + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = , + .h_blank = , + .h_front = , + .h_sync = , + .h_back = , + .v_active = 600, + .v_total = , + .v_blank = , + .v_front = , + .v_sync = , + .v_back = , + .v_sync_ln = 1, + }, +#endif +}; + +static struct hdmi_format_para fmt_para_vesa_1280x768p60_5x3 = { + .vic = HDMIV_1280x768p60hz, + .name = "1280x768p60hz", + .sname = "1280x768p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 79500, + .timing = { + .pixel_freq = 79500, + .h_freq = 47776, + .v_freq = 59870, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1664, + .h_blank = 384, + .h_front = 64, + .h_sync = 128, + .h_back = 192, + .v_active = 768, + .v_total = 798, + .v_blank = 30, + .v_front = 3, + .v_sync = 7, + .v_back = 20, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1280x800p60_8x5 = { + .vic = HDMIV_1280x800p60hz, + .name = "1280x800p60hz", + .sname = "1280x800p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 83500, + .timing = { + .pixel_freq = 83500, + .h_freq = 49380, + .v_freq = 59910, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1440, + .h_blank = 160, + .h_front = 48, + .h_sync = 32, + .h_back = 80, + .v_active = 800, + .v_total = 823, + .v_blank = 23, + .v_front = 3, + .v_sync = 6, + .v_back = 14, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1280x960p60_4x3 = { + .vic = HDMIV_1280x960p60hz, + .name = "1280x960p60hz", + .sname = "1280x960p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 108000, + .timing = { + .pixel_freq = 108000, + .h_freq = 60000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1440, + .h_blank = 520, + .h_front = 96, + .h_sync = 112, + .h_back = 312, + .v_active = 960, + .v_total = 1000, + .v_blank = 40, + .v_front = 1, + .v_sync = 3, + .v_back = 36, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1280x1024p60_5x4 = { + .vic = HDMIV_1280x1024p60hz, + .name = "1280x1024p60hz", + .sname = "1280x1024p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 108000, + .timing = { + .pixel_freq = 108000, + .h_freq = 63981, + .v_freq = 60020, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1280, + .h_total = 1688, + .h_blank = 408, + .h_front = 48, + .h_sync = 112, + .h_back = 248, + .v_active = 1024, + .v_total = 1066, + .v_blank = 42, + .v_front = 1, + .v_sync = 3, + .v_back = 38, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1360x768p60_16x9 = { + .vic = HDMIV_1360x768p60hz, + .name = "1360x768p60hz", + .sname = "1360x768p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 855000, + .timing = { + .pixel_freq = 855000, + .h_freq = 47700, + .v_freq = 60015, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1360, + .h_total = 1792, + .h_blank = 432, + .h_front = 64, + .h_sync = 112, + .h_back = 256, + .v_active = 768, + .v_total = 795, + .v_blank = 27, + .v_front = 3, + .v_sync = 6, + .v_back = 18, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1366x768p60_16x9 = { + .vic = HDMIV_1366x768p60hz, + .name = "1366x768p60hz", + .sname = "1366x768p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 85500, + .timing = { + .pixel_freq = 85500, + .h_freq = 47880, + .v_freq = 59790, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1366, + .h_total = 1792, + .h_blank = 426, + .h_front = 70, + .h_sync = 143, + .h_back = 213, + .v_active = 768, + .v_total = 798, + .v_blank = 30, + .v_front = 3, + .v_sync = 3, + .v_back = 24, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1400x1050p60_4x3 = { + .vic = HDMIV_1400x1050p60hz, + .name = "1400x1050p60hz", + .sname = "1400x1050p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 121750, + .timing = { + .pixel_freq = 121750, + .h_freq = 65317, + .v_freq = 59978, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1400, + .h_total = 1864, + .h_blank = 464, + .h_front = 88, + .h_sync = 144, + .h_back = 232, + .v_active = 1050, + .v_total = 1089, + .v_blank = 39, + .v_front = 3, + .v_sync = 4, + .v_back = 32, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1440x900p60_8x5 = { + .vic = HDMIV_1440x900p60hz, + .name = "1440x900p60hz", + .sname = "1440x900p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 106500, + .timing = { + .pixel_freq = 106500, + .h_freq = 56040, + .v_freq = 59887, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1440, + .h_total = 1904, + .h_blank = 464, + .h_front = 80, + .h_sync = 152, + .h_back = 232, + .v_active = 900, + .v_total = 934, + .v_blank = 34, + .v_front = 3, + .v_sync = 6, + .v_back = 25, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1440x2560p60_9x16 = { + .vic = HDMIV_1440x2560p60hz, + .name = "1440x2560p60hz", + .sname = "1440x2560p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 244850, + .timing = { + .pixel_freq = 244850, + .h_freq = 155760, + .v_freq = 59999, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1440, + .h_total = 1572, + .h_blank = 132, + .h_front = 64, + .h_sync = 4, + .h_back = 64, + .v_active = 2560, + .v_total = 2596, + .v_blank = 36, + .v_front = 16, + .v_sync = 4, + .v_back = 16, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1440x2560p70_9x16 = { + .vic = HDMIV_1440x2560p70hz, + .name = "1440x2560p70hz", + .sname = "1440x2560p70hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 280000, + .timing = { + .pixel_freq = 280000, + .h_freq = 180320, + .v_freq = 70100, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1440, + .h_total = 1550, + .h_blank = 110, + .h_front = 68, + .h_sync = 16, + .h_back = 26, + .v_active = 2560, + .v_total = 2576, + .v_blank = 16, + .v_front = 6, + .v_sync = 6, + .v_back = 4, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1600x900p60_16x9 = { + .vic = HDMIV_1600x900p60hz, + .name = "1600x900p60hz", + .sname = "1600x900p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 108000, + .timing = { + .pixel_freq = 108000, + .h_freq = 60000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1600, + .h_total = 1800, + .h_blank = 200, + .h_front = 24, + .h_sync = 80, + .h_back = 96, + .v_active = 900, + .v_total = 1000, + .v_blank = 100, + .v_front = 1, + .v_sync = 3, + .v_back = 96, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1600x1200p60_4x3 = { + .vic = HDMIV_1600x1200p60hz, + .name = "1600x1200p60hz", + .sname = "1600x1200p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 162000, + .timing = { + .pixel_freq = 162000, + .h_freq = 75000, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1600, + .h_total = 2160, + .h_blank = 560, + .h_front = 64, + .h_sync = 192, + .h_back = 304, + .v_active = 1200, + .v_total = 1250, + .v_blank = 50, + .v_front = 1, + .v_sync = 3, + .v_back = 46, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1680x1050p60_8x5 = { + .vic = HDMIV_1680x1050p60hz, + .name = "1680x1050p60hz", + .sname = "1680x1050p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 146250, + .timing = { + .pixel_freq = 146250, + .h_freq = 65290, + .v_freq = 59954, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1680, + .h_total = 2240, + .h_blank = 560, + .h_front = 104, + .h_sync = 176, + .h_back = 280, + .v_active = 1050, + .v_total = 1089, + .v_blank = 39, + .v_front = 3, + .v_sync = 6, + .v_back = 30, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_1920x1200p60_8x5 = { + .vic = HDMIV_1920x1200p60hz, + .name = "1920x1200p60hz", + .sname = "1920x1200p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 193250, + .timing = { + .pixel_freq = 193250, + .h_freq = 74700, + .v_freq = 59885, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2592, + .h_blank = 672, + .h_front = 136, + .h_sync = 200, + .h_back = 336, + .v_active = 1200, + .v_total = 1245, + .v_blank = 45, + .v_front = 3, + .v_sync = 6, + .v_back = 36, + .v_sync_ln = 1, + }, +}; +static struct hdmi_format_para fmt_para_vesa_2160x1200p90_9x5 = { + .vic = HDMIV_2160x1200p90hz, + .name = "2160x1200p90hz", + .sname = "2160x1200p90hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 268550, + .timing = { + .pixel_freq = 268550, + .h_freq = 109080, + .v_freq = 90000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 2160, + .h_total = 2462, + .h_blank = 302, + .h_front = 190, + .h_sync = 32, + .h_back = 80, + .v_active = 1200, + .v_total = 1212, + .v_blank = 12, + .v_front = 6, + .v_sync = 3, + .v_back = 3, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_2560x1080p60_64x27 = { +#if 0 /* TODO */ + .vic = HDMIV_2560x1080p60hz, + .name = "2560x1080p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 193250, + .timing = { + .pixel_freq = 193250, + .h_freq = 74700, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2592, + .h_blank = 672, + .h_front = 136, + .h_sync = 200, + .h_back = 336, + .v_active = 1200, + .v_total = 1245, + .v_blank = 45, + .v_front = 3, + .v_sync = 6, + .v_back = 36, + .v_sync_ln = 1, + }, +#endif +}; + +static struct hdmi_format_para fmt_para_vesa_2560x1440p60_16x9 = { +#if 0 /* TODO */ + .vic = HDMIV_2560x1440p60hz, + .name = "2560x1440p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 193250, + .timing = { + .pixel_freq = 193250, + .h_freq = 74700, + .v_freq = 60000, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 1920, + .h_total = 2592, + .h_blank = 672, + .h_front = 136, + .h_sync = 200, + .h_back = 336, + .v_active = 1200, + .v_total = 1245, + .v_blank = 45, + .v_front = 3, + .v_sync = 6, + .v_back = 36, + .v_sync_ln = 1, + }, +#endif +}; + +static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = { + .vic = HDMIV_2560x1600p60hz, + .name = "2560x1600p60hz", + .sname = "2560x1600p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 348500, + .timing = { + .pixel_freq = 348500, + .h_freq = 99458, + .v_freq = 59987, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 2560, + .h_total = 3504, + .h_blank = 944, + .h_front = 192, + .h_sync = 280, + .h_back = 472, + .v_active = 1600, + .v_total = 1658, + .v_blank = 58, + .v_front = 3, + .v_sync = 6, + .v_back = 49, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_3440x1440p60_43x18 = { + .vic = HDMIV_3440x1440p60hz, + .name = "3440x1440p60hz", + .sname = "3440x1440p60hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 319750, + .timing = { + .pixel_freq = 319750, + .h_freq = 88819, + .v_freq = 59973, + .vsync_polarity = 1, /* +VSync */ + .hsync_polarity = 1, /* +HSync */ + .h_active = 3440, + .h_total = 3600, + .h_blank = 160, + .h_front = 48, + .h_sync = 32, + .h_back = 80, + .v_active = 1440, + .v_total = 1481, + .v_blank = 41, + .v_front = 3, + .v_sync = 10, + .v_back = 28, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para fmt_para_vesa_2400x1200p90_2x1 = { + .vic = HDMIV_2400x1200p90hz, + .name = "2400x1200p90hz", + .sname = "2400x1200p90hz", + .pixel_repetition_factor = 0, + .progress_mode = 1, + .scrambler_en = 0, + .tmds_clk_div40 = 0, + .tmds_clk = 280000, + .timing = { + .pixel_freq = 280000, + .h_freq = 112812, + .v_freq = 90106, + .vsync_polarity = 1, + .hsync_polarity = 1, + .h_active = 2400, + .h_total = 2482, + .h_blank = 82, + .h_front = 20, + .h_sync = 30, + .h_back = 32, + .v_active = 1200, + .v_total = 1252, + .v_blank = 52, + .v_front = 17, + .v_sync = 5, + .v_back = 30, + .v_sync_ln = 1, + }, +}; + +static struct hdmi_format_para *all_fmt_paras[] = { + &fmt_para_3840x2160p60_y420_16x9, + &fmt_para_3840x2160p60_16x9, + &fmt_para_3840x2160p50_y420_16x9, + &fmt_para_3840x2160p50_16x9, + &fmt_para_3840x2160p30_16x9, + &fmt_para_3840x2160p25_16x9, + &fmt_para_3840x2160p24_16x9, + &fmt_para_4096x2160p24_256x135, + &fmt_para_4096x2160p25_256x135, + &fmt_para_4096x2160p30_256x135, + &fmt_para_4096x2160p50_y420_256x135, + &fmt_para_4096x2160p50_256x135, + &fmt_para_4096x2160p60_y420_256x135, + &fmt_para_4096x2160p60_256x135, + &fmt_para_1920x1080p50_16x9, + &fmt_para_1920x1080p60_16x9, + &fmt_para_1920x1080p30_16x9, + &fmt_para_1920x1080p25_16x9, + &fmt_para_1920x1080p24_16x9, + &fmt_para_1920x1080p100_16x9, + &fmt_para_1920x1080p120_16x9, + &fmt_para_1920x1080i60_16x9, + &fmt_para_1920x1080i50_16x9, + &fmt_para_1920x1080i100_16x9, + &fmt_para_1920x1080i120_16x9, + &fmt_para_1280x720p60_16x9, + &fmt_para_1280x720p50_16x9, + &fmt_para_1280x720p100_16x9, + &fmt_para_1280x720p120_16x9, + &fmt_para_720x480p60_16x9, + &fmt_para_720x480p120_16x9, + &fmt_para_720x480p60_4x3, + &fmt_para_720x480i60_16x9, + &fmt_para_720x480i60_4x3, + &fmt_para_720x576p50_16x9, + &fmt_para_720x576p100_16x9, + &fmt_para_720x576p50_4x3, + &fmt_para_720x576i50_16x9, + &fmt_para_720x576i50_4x3, + &fmt_para_vesa_640x480p60_4x3, + &fmt_para_vesa_800x480p60_4x3, + &fmt_para_vesa_800x600p60_4x3, + &fmt_para_vesa_852x480p60_213x120, + &fmt_para_vesa_854x480p60_427x240, + &fmt_para_vesa_1024x600p60_17x10, + &fmt_para_vesa_1024x768p60_4x3, + &fmt_para_vesa_1152x864p75_4x3, + &fmt_para_vesa_1280x600p60_32x15, + &fmt_para_vesa_1280x768p60_5x3, + &fmt_para_vesa_1280x800p60_8x5, + &fmt_para_vesa_1280x960p60_4x3, + &fmt_para_vesa_1280x1024p60_5x4, + &fmt_para_vesa_1360x768p60_16x9, + &fmt_para_vesa_1366x768p60_16x9, + &fmt_para_vesa_1400x1050p60_4x3, + &fmt_para_vesa_1440x900p60_8x5, + &fmt_para_vesa_1440x2560p60_9x16, + &fmt_para_vesa_1440x2560p70_9x16, + &fmt_para_vesa_1600x900p60_16x9, + &fmt_para_vesa_1600x1200p60_4x3, + &fmt_para_vesa_1680x1050p60_8x5, + &fmt_para_vesa_1920x1200p60_8x5, + &fmt_para_vesa_2160x1200p90_9x5, + &fmt_para_vesa_2560x1080p60_64x27, + &fmt_para_vesa_2560x1440p60_16x9, + &fmt_para_vesa_2560x1600p60_8x5, + &fmt_para_vesa_3440x1440p60_43x18, + &fmt_para_vesa_2400x1200p90_2x1, + &fmt_para_non_hdmi_fmt, + NULL, +}; + +struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic) +{ + int i; + + for (i = 0; all_fmt_paras[i] != NULL; i++) { + if (vic == all_fmt_paras[i]->vic) + return all_fmt_paras[i]; + } + return NULL; +} + +static struct parse_cd parse_cd_[] = { + {HDMI_COLOR_DEPTH_24B, "8bit",}, + {HDMI_COLOR_DEPTH_30B, "10bit"}, + {HDMI_COLOR_DEPTH_36B, "12bit"}, + {HDMI_COLOR_DEPTH_48B, "16bit"}, +}; + +static struct parse_cs parse_cs_[] = { + {HDMI_COLOR_FORMAT_RGB, "rgb",}, + {HDMI_COLOR_FORMAT_444, "444",}, + {HDMI_COLOR_FORMAT_422, "422",}, + {HDMI_COLOR_FORMAT_420, "420",}, +}; + +static struct parse_cr parse_cr_[] = { + {HDMI_COLOR_RANGE_LIM, "limit",}, + {HDMI_COLOR_RANGE_FUL, "full",}, +}; + +/* parse the string from "hdmitx output FORMAT" */ +void hdmi_parse_attr(struct hdmi_format_para *para, char const *name) +{ + int i; + + /* parse color depth */ + for (i = 0; i < sizeof(parse_cd_) / sizeof(struct parse_cd); i++) { + if (strstr(name, parse_cd_[i].name)) { + para->cd = parse_cd_[i].cd; + break; + } + } + /* set default value */ + if (i == sizeof(parse_cd_) / sizeof(struct parse_cd)) + para->cd = HDMI_COLOR_DEPTH_24B; + + /* parse color space */ + for (i = 0; i < sizeof(parse_cs_) / sizeof(struct parse_cs); i++) { + if (strstr(name, parse_cs_[i].name)) { + para->cs = parse_cs_[i].cs; + break; + } + } + /* set default value */ + if (i == sizeof(parse_cs_) / sizeof(struct parse_cs)) + para->cs = HDMI_COLOR_FORMAT_444; + + /* parse color range */ + for (i = 0; i < sizeof(parse_cr_) / sizeof(struct parse_cr); i++) { + if (strstr(name, parse_cr_[i].name)) { + para->cr = parse_cr_[i].cr; + break; + } + } + /* set default value */ + if (i == sizeof(parse_cr_) / sizeof(struct parse_cr)) + para->cr = HDMI_COLOR_RANGE_FUL; +} + +/* + * Paramter 'name' can be 1080p60hz, or 1920x1080p60hz + * or 3840x2160p60hz, 2160p60hz + * or 3840x2160p60hz420, 2160p60hz420 (Y420 mode) + */ +enum hdmi_vic hdmi_get_fmt_vic(char const *name) +{ + int i; + unsigned int name_len; + char *lname; + enum hdmi_vic vic = HDMI_unkown; + struct hdmi_format_para *para = NULL; + + if (!name) + return HDMI_unkown; + for (i = 0; all_fmt_paras[i] != NULL; i++) { + lname = all_fmt_paras[i]->name; + if (lname && (strncmp(name, lname, strlen(lname)) == 0)) { + vic = all_fmt_paras[i]->vic; + break; + } + lname = all_fmt_paras[i]->sname; + if (lname && (strncmp(name, lname, strlen(lname)) == 0)) { + vic = all_fmt_paras[i]->vic; + break; + } + } + if ((vic != HDMI_unkown) && (all_fmt_paras[i] != NULL)) { + para = all_fmt_paras[i]; + memset(¶->ext_name[0], 0, sizeof(para->ext_name)); + name_len = strlen(name); + if (name_len > sizeof(para->ext_name) - 1) + name_len = sizeof(para->ext_name) - 1; + memcpy(¶->ext_name[0], name, name_len); + hdmi_parse_attr(para, name); + } + return vic; +} + +struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t) +{ + int i; + + if (!t) + return NULL; + for (i = 0; all_fmt_paras[i]; i++) { + if ((abs(all_fmt_paras[i]->timing.pixel_freq / 10 + - t->pixel_clock) <= (t->pixel_clock + 1000) / 1000) && + (t->h_active == all_fmt_paras[i]->timing.h_active) && + (t->h_blank == all_fmt_paras[i]->timing.h_blank) && + (t->v_active == all_fmt_paras[i]->timing.v_active) && + (t->v_blank == all_fmt_paras[i]->timing.v_blank) && + (t->h_sync_offset == all_fmt_paras[i]->timing.h_front) && + (t->h_sync == all_fmt_paras[i]->timing.h_sync) && + (t->v_sync_offset == all_fmt_paras[i]->timing.v_front) && + (t->v_sync == all_fmt_paras[i]->timing.v_sync) + ) + return all_fmt_paras[i]; + } + + return NULL; +} + +/* 1080i still uses encp, not enci */ +bool hdmimode_is_interlaced(enum hdmi_vic vic) +{ + switch (vic) { + case HDMI_720x480i60_4x3: + case HDMI_720x480i60_16x9: + case HDMI_2880x480i60_4x3: + case HDMI_2880x480i60_16x9: + case HDMI_720x576i50_4x3: + case HDMI_720x576i50_16x9: + case HDMI_2880x576i50_4x3: + case HDMI_2880x576i50_16x9: + case HDMI_720x576i100_4x3: + case HDMI_720x576i100_16x9: + case HDMI_720x480i120_4x3: + case HDMI_720x480i120_16x9: + case HDMI_720x576i200_4x3: + case HDMI_720x576i200_16x9: + case HDMI_720x480i240_4x3: + case HDMI_720x480i240_16x9: + return 1; + break; + default: + return 0; + break; + } +} + +static struct hdmi_format_para tst_para; +static inline void copy_para(struct hdmi_format_para *des, + struct hdmi_format_para *src) +{ + if (!des || !src) + return; + memcpy(des, src, sizeof(struct hdmi_format_para)); +} + +bool pre_process_str(char *name) +{ + int i; + unsigned int flag = 0; + char *color_format[4] = {"444", "422", "420", "rgb"}; + + for (i = 0 ; i < 4 ; i++) { + if (strstr(name, color_format[i]) != NULL) + flag++; + } + if (flag >= 2) + return false; + else + return true; +} + +struct hdmi_format_para *hdmi_tst_fmt_name(char const *name, char const *attr) +{ + int i; + char *lname; + enum hdmi_vic vic = HDMI_unkown; + unsigned int copy_len; + + copy_para(&tst_para, &fmt_para_non_hdmi_fmt); + if (!name) + return &tst_para; + + for (i = 0; all_fmt_paras[i]; i++) { + lname = all_fmt_paras[i]->name; + if (lname && (strncmp(name, lname, strlen(lname)) == 0)) { + vic = all_fmt_paras[i]->vic; + break; + } + lname = all_fmt_paras[i]->sname; + if (lname && (strncmp(name, lname, strlen(lname)) == 0)) { + vic = all_fmt_paras[i]->vic; + break; + } + } + if ((vic != HDMI_unkown) && (i != sizeof(all_fmt_paras) / + sizeof(struct hdmi_format_para *))) { + copy_para(&tst_para, all_fmt_paras[i]); + memset(&tst_para.ext_name[0], 0, sizeof(tst_para.ext_name)); + copy_len = strlen(name); + if (copy_len >= sizeof(tst_para.ext_name)) + copy_len = sizeof(tst_para.ext_name) - 1; + memcpy(&tst_para.ext_name[0], name, copy_len); + hdmi_parse_attr(&tst_para, name); + hdmi_parse_attr(&tst_para, attr); + } else { + copy_para(&tst_para, &fmt_para_non_hdmi_fmt); + hdmi_parse_attr(&tst_para, name); + hdmi_parse_attr(&tst_para, attr); + } + if (strstr(name, "420")) + tst_para.cs = HDMI_COLOR_FORMAT_420; + + /* only 2160p60/50hz smpte60/50hz have Y420 mode */ + if (tst_para.cs == HDMI_COLOR_FORMAT_420) { + switch ((tst_para.vic) & 0xff) { + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p60_256x135: + case HDMI_3840x2160p50_64x27: + case HDMI_3840x2160p60_64x27: + break; + default: + copy_para(&tst_para, &fmt_para_non_hdmi_fmt); + break; + } + } + + return &tst_para; +} +
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_tx_compliance.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_tx_compliance.c new file mode 100644 index 0000000..0bc43f5 --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_tx_compliance.c
@@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <linux/types.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> +/* Base Block, Vendor/Product Information, byte[8]~[17] */ +struct edid_venddat_t { + unsigned char data[10]; +}; + +static struct edid_venddat_t vendor_6g[] = { + /* SAMSUNG UA55KS7300JXXZ */ + { {0x4c, 0x2d, 0x3b, 0x0d, 0x00, 0x06, 0x00, 0x01, 0x01, 0x1a} }, + /* Add new vendor data here */ +}; + +bool hdmitx_find_vendor(struct hdmitx_dev *hdev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(vendor_6g); i++) { + if (memcmp(&hdev->rawedid[8], vendor_6g[i].data, + sizeof(vendor_6g[i].data)) == 0) + return true; + } + return false; +}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.c new file mode 100755 index 0000000..322f6ff --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.c
@@ -0,0 +1,3217 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/io.h> +#include <amlogic/media/vout/aml_vout.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> +#include <amlogic/auge_sound.h> +#include "hdmitx_drv.h" + +/* TODO */ +const static char *vend_name = "Amlogic"; /* Max 8 bytes */ +const static char *prod_desc = "MBox Meson Ref"; /* Max 16 bytes */ + +static struct hdmitx_dev hdmitx_device; + +struct hdmitx_dev *hdmitx_get_hdev(void) +{ + return &hdmitx_device; +} + +static void hdmi_tvenc_set(enum hdmi_vic vic); +extern void _udelay(unsigned int us); +static void set_tmds_clk_div40(unsigned int div40); + +#define HSYNC_POLARITY 1 /*HSYNC polarity: active high*/ +#define VSYNC_POLARITY 1 /*VSYNC polarity: active high*/ + +/*Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/ +#define TX_INPUT_COLOR_FORMAT HDMI_COLOR_FORMAT_444 +/*Pixel range: 0=limited; 1=full.*/ +#define TX_INPUT_COLOR_RANGE HDMI_COLOR_RANGE_LIM +/*Pixel range: 0=limited; 1=full.*/ +#define TX_OUTPUT_COLOR_RANGE HDMI_COLOR_RANGE_LIM + +static void hdelay(int us) +{ + _udelay(us * 1000); +} + +#define mdelay(i) hdelay(i) +#define msleep(i) hdelay(i) + +static void hdmitx_set_hw(struct hdmitx_dev *hdev); +static int hdmitx_set_audmode(struct hdmitx_dev *hdev); + +/*Internal functions:*/ +static void hdmitx_csc_config (unsigned char input_color_format, + unsigned char output_color_format, + unsigned char color_depth); + +static void dump_regs(void) +{ + unsigned int reg_adr; + unsigned int reg_val; + unsigned int ladr; + + for (reg_adr = 0x0000; reg_adr < 0x0100; reg_adr++) { + ladr = PERIPHS_REG_ADDR(0x0) + (reg_adr << 2); + reg_val = hd_read_reg(ladr); + printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val); + } + for (reg_adr = 0x0000; reg_adr < 0x0100; reg_adr++) { + ladr = HHI_REG_ADDR(0x0) + (reg_adr << 2); + reg_val = hd_read_reg(ladr); + printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val); + } + for (reg_adr = 0x0000; reg_adr < 0x0100; reg_adr++) { + ladr = ANACTRL_REG_ADDR(0x0) + (reg_adr << 2); + reg_val = hd_read_reg(ladr); + printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val); + } +#define VPU_REG_ADDR(reg) ((VCBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2)) + for (reg_adr = 0x1b00; reg_adr < 0x1c00; reg_adr++) { + ladr = VPU_REG_ADDR(reg_adr); + reg_val = hd_read_reg(ladr); + printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val); + } + for (reg_adr = 0x1c01; reg_adr < 0x1d00; reg_adr++) { + ladr = VPU_REG_ADDR(reg_adr); + reg_val = hd_read_reg(ladr); + printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val); + } + for (reg_adr = 0x2700; reg_adr < 0x2780; reg_adr++) { + ladr = VPU_REG_ADDR(reg_adr); + reg_val = hd_read_reg(ladr); + printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val); + } + for (reg_adr = HDMITX_TOP_SW_RESET; reg_adr < HDMITX_TOP_DONT_TOUCH1 + 1; reg_adr++) { + reg_val = hdmitx_rd_reg(reg_adr); + printk("TOP[0x%x]: 0x%x\n", reg_adr, reg_val); + } + for (reg_adr = HDMITX_DWC_DESIGN_ID; reg_adr < HDMITX_DWC_I2CM_SCDC_UPDATE1 + 1; reg_adr++) { + if ((reg_adr > (DWC_OFFSET_MASK + 0x5016)) && (reg_adr < (DWC_OFFSET_MASK + 0x7800))) + reg_val = 0;//hdmitx_rd_reg(reg_adr); + else + reg_val = hdmitx_rd_reg(reg_adr); + if (reg_val) + printk("hdmitx: [0x%x]: 0x%x\n", reg_adr, reg_val); + } +} + +static void hdmitx_hw_init(void) +{ + static int hw_init_flag; + + if (hw_init_flag) + return; + else + hw_init_flag = 1; + + /* Enable clocks and bring out of reset */ + + /* Enable hdmitx_sys_clk */ + /* .clk0 ( cts_oscin_clk ), */ + /* .clk1 ( fclk_div4 ), */ + /* .clk2 ( fclk_div3 ), */ + /* .clk3 ( fclk_div5 ), */ + hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0x0100, 0, 16); + + /* Enable clk81_hdmitx_pclk */ + hd_set_reg_bits(P_CLKCTRL_SYS_CLK_EN0_REG2, 1, 4, 1); + + /* wire wr_enable = control[3]; */ + /* wire fifo_enable = control[2]; */ + /* assign phy_clk_en = control[1]; */ + /* Enable tmds_clk */ + /* Bring HDMITX MEM output of power down */ + hd_set_reg_bits(P_PWRCTRL_MEM_PD11, 0, 8, 8); + /* reset HDMITX APB & TX & PHY */ + + /* Refer to SC2-system-Registers.docx */ + hd_write_reg(P_RESETCTRL_RESET0, 1 << 29); /* hdmi_tx */ + hd_write_reg(P_RESETCTRL_RESET0, 1 << 22); /* hdmitxphy */ + hd_write_reg(P_RESETCTRL_RESET0, 1 << 19); /* vid_pll_div */ + hd_write_reg(P_RESETCTRL_RESET0, 1 << 16); /* hdmitx_apb */ + + /* Bring out of reset */ + hdmitx_wr_reg(HDMITX_TOP_SW_RESET, 0); + _udelay(200); + /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */ + hdmitx_wr_reg(HDMITX_TOP_CLK_CNTL, 0x000000ff); + + hdmitx_wr_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff); + + hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0x00); +} + +/* + * Note: read 8 Bytes of EDID data every time + */ +static int read_edid_8bytes(unsigned char *rx_edid, unsigned char addr, + unsigned char blk_no) +{ + unsigned int timeout = 0; + unsigned int i = 0; + /*Program SLAVE/SEGMENT/ADDR*/ + hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x50); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR, 0x30); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGPTR, 1); + hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, addr); + if (blk_no < 2) + hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 2); + else + hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 3); + timeout = 0; + while ((!(hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 1))) && (timeout < 5)) { + mdelay(1); + timeout ++; + } + if (timeout == 5) { + printk("ddc timeout\n"); + return 0; + } + /* add extra delay time for reading segment block */ + if (blk_no >= 2) + mdelay(1); + hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 1 << 1); /*clear INT*/ + /*Read back 8 bytes*/ + for (i = 0; i < 8; i ++) { + rx_edid[i] = hdmitx_rd_reg(HDMITX_DWC_I2CM_READ_BUFF0 + i); + } + return 1; +} + +static void ddc_init_(void) +{ + static int ddc_init_flag; + unsigned int data32 = 0; + + hdmitx_hw_init(); + if (ddc_init_flag) + return; + else + ddc_init_flag = 1; + + hdmitx_ddc_init(); + + data32 = 0; + data32 |= (0 << 6); /*[ 6] read_req_mask*/ + data32 |= (0 << 2); /*[ 2] done_mask*/ + hdmitx_wr_reg(HDMITX_DWC_I2CM_INT, data32); + + data32 = 0; + data32 |= (0 << 6); /*[ 6] nack_mask*/ + data32 |= (0 << 2); /*[ 2] arbitration_error_mask*/ + hdmitx_wr_reg(HDMITX_DWC_I2CM_CTLINT, data32); + + data32 = 0; + data32 |= (0 << 3); /*[ 3] i2c_fast_mode: 0=standard mode; 1=fast mode.*/ + hdmitx_wr_reg(HDMITX_DWC_I2CM_DIV, data32); + + hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_1, 0); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0xcf); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_1, 0); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_0, 0xff); + hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_1, 0); + hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_0, 0x0f); + hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_1, 0); + hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_0, 0x20); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SDA_HOLD, 0x08); + + data32 = 0; + data32 |= (0 << 5); /*[ 5] updt_rd_vsyncpoll_en*/ + data32 |= (0 << 4); /*[ 4] read_request_en scdc*/ + data32 |= (0 << 0); /*[ 0] read_update*/ + hdmitx_wr_reg(HDMITX_DWC_I2CM_SCDC_UPDATE, data32); +} + +static int hdmitx_read_edid(unsigned char *buf, unsigned char addr, + unsigned char blk_no) +{ + ddc_init_(); + return read_edid_8bytes(buf, (addr + blk_no * 128) & 0xff, blk_no); +} + +static void scdc_rd_sink(unsigned char adr, unsigned char *val) +{ + hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x54); + hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, adr); + hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1); + _udelay(2000); + *val = (unsigned char)hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI); +} + +static void scdc_wr_sink(unsigned char adr, unsigned char val) +{ + hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x54); + hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, adr); + hdmitx_wr_reg(HDMITX_DWC_I2CM_DATAO, val); + hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 0x10); + _udelay(2000); +} + +static void scdc_prepare(unsigned int div) +{ + unsigned char rx_ver = 0; + + scdc_rd_sink(SINK_VER, &rx_ver); + if (rx_ver != 1) + scdc_rd_sink(SINK_VER, &rx_ver); /* Recheck */ + if (0) + printf("rx version is %s div=%d\n", + (rx_ver == 1) ? "2.0" : "1.4 or below", + div ? 40 : 10); + + scdc_wr_sink(SOURCE_VER, 0x1); + scdc_wr_sink(SOURCE_VER, 0x1); + scdc_wr_sink(TMDS_CFG, div ? 0x3 : 0); /* TMDS 1/40 & Scramble */ + scdc_wr_sink(TMDS_CFG, div ? 0x3 : 0); /* TMDS 1/40 & Scramble */ +} + +static struct hdmi_support_mode gxbb_modes[] = { + {HDMI_3840x2160p60_16x9, "2160p60hz", 0}, + {HDMI_3840x2160p50_16x9, "2160p50hz", 0}, + {HDMI_3840x2160p30_16x9, "2160p30hz", 0}, + {HDMI_3840x2160p25_16x9, "2160p25hz", 0}, + {HDMI_3840x2160p24_16x9, "2160p24hz", 0}, + {HDMI_4096x2160p60_256x135, "smpte60hz", 0}, + {HDMI_4096x2160p50_256x135, "smpte50hz", 0}, + {HDMI_4096x2160p30_256x135, "smpte30hz", 0}, + {HDMI_4096x2160p25_256x135, "smpte25hz", 0}, + {HDMI_4096x2160p24_256x135, "smpte24hz", 0}, + {HDMI_3840x2160p60_16x9, "2160p60hz420", 1}, + {HDMI_3840x2160p50_16x9, "2160p50hz420", 1}, + {HDMI_4096x2160p50_256x135, "smpte50hz420", 1}, + {HDMI_4096x2160p60_256x135, "smpte60hz420", 1}, + {HDMI_1920x1080p60_16x9, "1080p60hz", 0}, + {HDMI_1920x1080p50_16x9, "1080p50hz", 0}, + {HDMI_1920x1080p30_16x9, "1080p30hz", 0}, + {HDMI_1920x1080p25_16x9, "1080p25hz", 0}, + {HDMI_1920x1080p24_16x9, "1080p24hz", 0}, + {HDMI_1920x1080i60_16x9, "1080i60hz", 0}, + {HDMI_1920x1080i50_16x9, "1080i50hz", 0}, + {HDMI_1280x720p60_16x9, "720p60hz", 0}, + {HDMI_1280x720p50_16x9, "720p50hz", 0}, + {HDMI_720x576p50_16x9, "576p50hz", 0}, + {HDMI_720x480p60_16x9, "480p60hz", 0}, + {HDMI_720x576i50_16x9, "576i50hz", 0}, + {HDMI_720x480i60_16x9, "480i60hz", 0}, + {HDMI_720x576p50_4x3, "576p50hz_4x3", 0}, + {HDMI_720x480p60_4x3, "480p60hz_4x3", 0}, + {HDMI_720x576i50_4x3, "576i50hz_4x3", 0}, + {HDMI_720x480i60_4x3, "480i60hz_4x3", 0}, + {HDMIV_1440x2560p60hz, "1440x2560p60hz", 0}, + {HDMIV_3440x1440p60hz, "3440x1440p60hz", 0}, + {HDMIV_2400x1200p90hz, "2400x1200p90hz", 0}, + {HDMIV_1280x1024p60hz, "1280x1024p60hz", 0}, + {HDMIV_1680x1050p60hz, "1680x1050p60hz", 0}, + {HDMIV_1024x600p60hz, "1024x600p60hz", 0}, +}; + +static void hdmitx_list_support_modes(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) + printf("%s\n", gxbb_modes[i].sname); +} + + void hdmitx_test_bist(unsigned int mode) +{ + switch (mode) { + case 1: + case 2: + case 3: + hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 0, 3, 1); + hd_write_reg(P_VENC_VIDEO_TST_EN, 1); + hd_write_reg(P_VENC_VIDEO_TST_MDSEL, mode); + break; + case 0: + default: + hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 1, 3, 1); + hd_write_reg(P_VENC_VIDEO_TST_EN, 0); + break; + } +} + +static void hdmitx_output_blank(unsigned int blank) +{ + if (blank == 1) + hd_write_reg(P_VPU_HDMI_DATA_OVR, + ((1 << 31) | (1 << 29) | (1 << 9))); + if (blank == 0) + hd_write_reg(P_VPU_HDMI_DATA_OVR, 0); +} + +void hdmitx_set_div40(bool div40) +{ + set_tmds_clk_div40(div40); +} + +void hdmitx_init(void) +{ + struct hdmitx_dev *hdev = hdmitx_get_hdev(); + char *dongle_mode = NULL; + + dongle_mode = env_get("dongle_mode"); + if (dongle_mode && (dongle_mode[0] == '1')) + hdev->dongle_mode = 1; + hdev->hwop.get_hpd_state = hdmitx_get_hpd_state; + hdev->hwop.read_edid = hdmitx_read_edid; + hdev->hwop.turn_off = hdmitx_turnoff; + hdev->hwop.list_support_modes = hdmitx_list_support_modes; + hdev->hwop.dump_regs = dump_regs; + hdev->hwop.test_bist = hdmitx_test_bist; + hdev->hwop.test_prbs = hdmitx_test_prbs; + hdev->hwop.set_div40 = hdmitx_set_div40; + hdev->hwop.output_blank = hdmitx_output_blank; +} + +void hdmi_tx_set(struct hdmitx_dev *hdev) +{ + unsigned char checksum[11]; + char *p_tmp; + aml_audio_init(); /* Init audio hw firstly */ + hdmitx_hw_init(); + ddc_init_(); + hdmitx_set_hw(hdev); + /* add audio */ + hdmitx_set_audmode(hdev); + //kernel will determine output mode on its own + p_tmp = env_get("outputmode"); + if (NULL != p_tmp) + env_set("hdmimode", p_tmp); + + /* null char needed to terminate the string + otherwise garbage in checksum logopara */ + memcpy(checksum, hdev->RXCap.checksum, 10); + checksum[10] = '\0'; + env_set("hdmichecksum", (const char*)checksum); + printf("hdmi_tx_set: save mode: %s, attr: %s, hdmichecksum: %s\n", + env_get("outputmode"), env_get("colorattribute"), env_get("hdmichecksum")); + run_command("saveenv", 0); + return; + +#if 0 + hdmi_tx_gate(vic); + hdmi_tx_clk(vic); + hdmi_tx_misc(vic); + hdmi_tx_enc(vic); + hdmi_tx_set_vend_spec_infofram(vic); + hdmi_tx_phy(vic); +#endif +} + +int hdmi_outputmode_check(char *mode, unsigned int frac) +{ + int i, ret = 0xff; + + for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { + if (!strcmp(mode, gxbb_modes[i].sname)) { + ret = 0; + break; + } + } + + if (ret) { + printf("hdmitx: outputmode[%s] is invalid\n", mode); + return ret; + } + + if (frac) { + if (hdmitx_likely_frac_rate_mode(mode) == 0) { + printf("hdmitx: outputmode[%s] don't support frac\n", mode); + return ret; + } + } + + if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz"))) + ret = VIU_MUX_ENCI; + else + ret = VIU_MUX_ENCP; + return ret; +} + +static int hdmitx_set_audmode(struct hdmitx_dev *hdev) +{ + int i; + unsigned int data32; + unsigned int aud_n_para; + + pr_info("hdmtix: set audio\n"); + hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 3, 2, 2); + hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 0, 1); + hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 3, 1); +#if 0 /* TODO */ + /* Disable HDMI audio clock input and its I2S input */ + hd_write_reg(P_AIU_HDMI_CLK_DATA_CTRL, 0); + + /* Enable HDMI I2S input from the selected source */ + hd_write_reg(P_AIU_HDMI_CLK_DATA_CTRL, 0x22); +#endif + /* I2S Sampler config */ + data32 = 0; +/* [ 3] fifo_empty_mask: 0=enable int; 1=mask int. */ + data32 |= (1 << 3); +/* [ 2] fifo_full_mask: 0=enable int; 1=mask int. */ + data32 |= (1 << 2); + hdmitx_wr_reg(HDMITX_DWC_AUD_INT, data32); + + data32 = 0; +/* [ 4] fifo_overrun_mask: 0=enable int; 1=mask int. + * Enable it later when audio starts. */ + data32 |= (1 << 4); + hdmitx_wr_reg(HDMITX_DWC_AUD_INT1, data32); +/* [ 5] 0=select SPDIF; 1=select I2S. */ + data32 = 0; + data32 |= (0 << 7); /* [ 7] sw_audio_fifo_rst */ + data32 |= (0 << 5); + data32 |= (0 << 0); /* [3:0] i2s_in_en: enable it later in test.c */ +/* if enable it now, fifo_overrun will happen, because packet don't get sent + * out until initial DE detected. */ + hdmitx_wr_reg(HDMITX_DWC_AUD_CONF0, data32); + + data32 = 0; + data32 |= (0 << 5); /* [7:5] i2s_mode: 0=standard I2S mode */ + data32 |= (24 << 0); /* [4:0] i2s_width */ + hdmitx_wr_reg(HDMITX_DWC_AUD_CONF1, data32); + + data32 = 0; + data32 |= (0 << 1); /* [ 1] NLPCM */ + data32 |= (0 << 0); /* [ 0] HBR */ + hdmitx_wr_reg(HDMITX_DWC_AUD_CONF2, data32); + + /* spdif sampler config */ + /* [ 2] SPDIF fifo_full_mask: 0=enable int; 1=mask int. */ + /* [ 3] SPDIF fifo_empty_mask: 0=enable int; 1=mask int. */ + data32 = 0; + data32 |= (1 << 3); + data32 |= (1 << 2); + hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT, data32); + /* [ 4] SPDIF fifo_overrun_mask: 0=enable int; 1=mask int. */ + data32 = 0; + data32 |= (0 << 4); + hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT1, data32); + + data32 = 0; + data32 |= (0 << 7); /* [ 7] sw_audio_fifo_rst */ + hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF0, data32); + + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDICONF0, 0, 0, 4); /* CT */ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDICONF0, 1, 4, 3); /* CC */ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDICONF1, 0, 0, 3); /* SF */ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDICONF1, 0, 4, 2); /* SS */ + hdmitx_wr_reg(HDMITX_DWC_FC_AUDICONF2, 0x00); + hdmitx_wr_reg(HDMITX_DWC_FC_AUDICONF3, 0); + + /* audio packetizer config */ + hdmitx_wr_reg(HDMITX_DWC_AUD_INPUTCLKFS, 0); + + /* 48kHz 2ch PCM as default */ + aud_n_para = 6144; + switch (hdev->vic) { + case HDMI_3840x2160p24_16x9: + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p30_16x9: + case HDMI_4096x2160p24_256x135: + case HDMI_4096x2160p25_256x135: + case HDMI_4096x2160p30_256x135: + aud_n_para = 5120; + break; + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + case HDMI_3840x2160p50_64x27: + case HDMI_3840x2160p60_64x27: + if (hdev->para->cs == HDMI_COLOR_FORMAT_420) + aud_n_para = 5120; + break; + default: + break; + } + + /* ACR packet configuration */ + data32 = 0; + data32 |= (1 << 7); /* [ 7] ncts_atomic_write */ + data32 |= (0 << 0); /* [3:0] AudN[19:16] */ + hdmitx_wr_reg(HDMITX_DWC_AUD_N3, data32); + + data32 = 0; + data32 |= (0 << 7); /* [7:5] N_shift */ + data32 |= (0 << 4); /* [ 4] CTS_manual */ + data32 |= (0 << 0); /* [3:0] manual AudCTS[19:16] */ + hdmitx_wr_reg(HDMITX_DWC_AUD_CTS3, data32); + + hdmitx_wr_reg(HDMITX_DWC_AUD_CTS2, 0); /* manual AudCTS[15:8] */ + hdmitx_wr_reg(HDMITX_DWC_AUD_CTS1, 0); /* manual AudCTS[7:0] */ + + data32 = 0; + data32 |= (1 << 7); /* [ 7] ncts_atomic_write */ + data32 |= (((aud_n_para>>16)&0xf) << 0); /* [3:0] AudN[19:16] */ + hdmitx_wr_reg(HDMITX_DWC_AUD_N3, data32); + hdmitx_wr_reg(HDMITX_DWC_AUD_N2, (aud_n_para>>8)&0xff); /* AudN[15:8] */ + hdmitx_wr_reg(HDMITX_DWC_AUD_N1, aud_n_para&0xff); /* AudN[7:0] */ + for (i = 0; i < 9; i++) + hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS0+i, 0x00); + hdmitx_wr_reg(HDMITX_DWC_FC_AUDSV, 0x11); + hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS7, 0x02); + hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS8, 0xd2); + hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS3, 0x00); + hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS5, 0x00); + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS7, + 0x2, 0, 4); /*CSB 27:24*/ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS7, 0x0, 6, 2); /*CSB 31:30*/ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS7, 0x0, 4, 2); /*CSB 29:28*/ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS8, 0x2, 0, 4); /*CSB 35:32*/ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS8, /* CSB 39:36 */ + 0xd, 4, 4); + + hdmitx_set_reg_bits(HDMITX_DWC_AUD_CONF0, 0, 5, 1); + /* reset audio fifo */ + hdmitx_set_reg_bits(HDMITX_DWC_AUD_CONF0, 1, 7, 1); + hdmitx_set_reg_bits(HDMITX_DWC_AUD_CONF0, 0, 7, 1); + hdmitx_set_reg_bits(HDMITX_DWC_AUD_SPDIF0, 1, 7, 1); + hdmitx_set_reg_bits(HDMITX_DWC_AUD_SPDIF0, 0, 7, 1); + hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0xe7); + /* need reset again */ + hdmitx_set_reg_bits(HDMITX_DWC_AUD_SPDIF0, 1, 7, 1); + hdmitx_set_reg_bits(HDMITX_DWC_AUD_SPDIF0, 0, 7, 1); + hdmitx_wr_reg(HDMITX_DWC_AUD_N1, hdmitx_rd_reg(HDMITX_DWC_AUD_N1)); + hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO3, 1, 0, 1); + return 0; +} + +/* + * set Source Product Description InfoFrame + */ +static void hdmitx_set_spdinfo(void) +{ + int i; + + if (!(vend_name && prod_desc)) + return; + + for (i = 0; (i < 8) && vend_name[i]; i++) + hdmitx_wr_reg(HDMITX_DWC_FC_SPDVENDORNAME0 + i, vend_name[i]); + for (i = 0; (i < 16) && prod_desc[i]; i++) + hdmitx_wr_reg(HDMITX_DWC_FC_SDPPRODUCTNAME0 + i, prod_desc[i]); + hdmitx_wr_reg(HDMITX_DWC_FC_SPDDEVICEINF, 0x1); + hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 4, 1); + hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO2, 1, 4, 4); + hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1); +} + +#define NUM_INT_VSYNC INT_VEC_VIU1_VSYNC + +static unsigned long modulo(unsigned long a, unsigned long b); +static signed int to_signed(unsigned int a); + +/*Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit. + *Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420. + *Pixel range: 0=limited; 1=full. + *Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420. + *Pixel range: 0=limited; 1=full. + *0:TMDS_CLK_rate=TMDS_Character_rate; 1:TMDS_CLK_rate=TMDS_Character_rate/4, + *for TMDS_Character_rate>340Mcsc. + */ +static void config_hdmi20_tx ( enum hdmi_vic vic, struct hdmi_format_para *para, + unsigned char color_depth, unsigned char input_color_format, + unsigned char input_color_range, unsigned char output_color_format, + unsigned char output_color_range) +{ + struct hdmi_cea_timing *t = ¶->timing; + unsigned long data32; + unsigned char vid_map; + unsigned char csc_en; + unsigned char default_phase = 0; + unsigned char tmp = 0; + +#define GET_TIMING(name) (t->name) + + hdmitx_hw_init(); + data32 = 0; + data32 |= (1 << 12); + data32 |= (0 << 8); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_TOP_BIST_CNTL, data32); + + /* Configure video */ + + /*Configure video sampler*/ + vid_map = ( input_color_format == HDMI_COLOR_FORMAT_RGB )? ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x01 : + (color_depth == HDMI_COLOR_DEPTH_30B)? 0x03 : + (color_depth == HDMI_COLOR_DEPTH_36B)? 0x05 : + 0x07) : + ((input_color_format == HDMI_COLOR_FORMAT_444) || + (input_color_format == HDMI_COLOR_FORMAT_420))? ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x09 : + (color_depth == HDMI_COLOR_DEPTH_30B)? 0x0b : + (color_depth == HDMI_COLOR_DEPTH_36B)? 0x0d : + 0x0f) : + ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x16 : + (color_depth == HDMI_COLOR_DEPTH_30B)? 0x14 : + 0x12); + + data32 = 0; + data32 |= (0 << 7); + data32 |= (vid_map << 0); + hdmitx_wr_reg(HDMITX_DWC_TX_INVID0, data32); + + data32 = 0; + data32 |= (0 << 2); + data32 |= (0 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_TX_INSTUFFING, data32); + hdmitx_wr_reg(HDMITX_DWC_TX_GYDATA0, 0x00); + hdmitx_wr_reg(HDMITX_DWC_TX_GYDATA1, 0x00); + hdmitx_wr_reg(HDMITX_DWC_TX_RCRDATA0, 0x00); + hdmitx_wr_reg(HDMITX_DWC_TX_RCRDATA1, 0x00); + hdmitx_wr_reg(HDMITX_DWC_TX_BCBDATA0, 0x00); + hdmitx_wr_reg(HDMITX_DWC_TX_BCBDATA1, 0x00); + + /* Configure Color Space Converter */ + + csc_en = (input_color_format != output_color_format) ? 1 : 0; + + data32 = 0; + data32 |= (csc_en << 0); + hdmitx_wr_reg(HDMITX_DWC_MC_FLOWCTRL, data32); + + data32 = 0; + data32 |= ((((input_color_format ==HDMI_COLOR_FORMAT_422) && + (output_color_format!=HDMI_COLOR_FORMAT_422))? 2 : 0 ) << 4); /*[5:4] intmode*/ + data32 |= ((((input_color_format !=HDMI_COLOR_FORMAT_422) && + (output_color_format==HDMI_COLOR_FORMAT_422))? 2 : 0 ) << 0); /*[1:0] decmode*/ + hdmitx_wr_reg(HDMITX_DWC_CSC_CFG, data32); + + hdmitx_csc_config(input_color_format, output_color_format, color_depth); + + /* Configure video packetizer */ + + /* Video Packet color depth and pixel repetition */ + data32 = 0; + data32 |= (((output_color_format==HDMI_COLOR_FORMAT_422)? + HDMI_COLOR_DEPTH_24B : color_depth) << 4); /*[7:4] color_depth*/ + data32 |= (0 << 0); + if ((data32 & 0xf0) == 0x40 ) + data32 &= ~(0xf << 4); + hdmitx_wr_reg(HDMITX_DWC_VP_PR_CD, data32); + if (output_color_format == HDMI_COLOR_FORMAT_422) { + switch (color_depth) { + case HDMI_COLOR_DEPTH_24B: + tmp = 4; + break; + default: + tmp = 0; + break; + } + hdmitx_set_reg_bits(HDMITX_DWC_VP_PR_CD, tmp, 4, 4); + } + + /* Video Packet Stuffing */ + data32 = 0; + data32 |= (default_phase << 5); + data32 |= (0 << 2); + data32 |= (0 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_VP_STUFF, data32); + + /* Video Packet YCC color remapping */ + data32 = 0; + hdmitx_wr_reg(HDMITX_DWC_VP_REMAP, data32); + if (output_color_format == HDMI_COLOR_FORMAT_422) { + switch (color_depth) { + case HDMI_COLOR_DEPTH_36B: + tmp = 2; + break; + case HDMI_COLOR_DEPTH_30B: + tmp = 1; + break; + case HDMI_COLOR_DEPTH_24B: + tmp = 0; + break; + } + } + hdmitx_set_reg_bits(HDMITX_DWC_VP_REMAP, tmp, 0, 2); /*[1:0] ycc422_size*/ + + /* Video Packet configuration */ + data32 = 0; + data32 |= ((((output_color_format != HDMI_COLOR_FORMAT_422) && + (color_depth == HDMI_COLOR_DEPTH_24B))? 1 : 0) << 6); /*[ 6] bypass_en*/ + data32 |= ((((output_color_format == HDMI_COLOR_FORMAT_422) || + (color_depth == HDMI_COLOR_DEPTH_24B))? 0 : 1) << 5); /*[ 5] pp_en*/ + data32 |= (0 << 4); /*[ 4] pr_en*/ + data32 |= (((output_color_format == HDMI_COLOR_FORMAT_422)? 1 : 0) << 3); /*[ 3] ycc422_en*/ + data32 |= (1 << 2); /*[ 2] pr_bypass_select*/ + data32 |= (((output_color_format == HDMI_COLOR_FORMAT_422)? 1 : + (color_depth == HDMI_COLOR_DEPTH_24B)? 2 : 0) << 0); + /*[1:0] output_selector: 0=pixel packing; 1=YCC422 remap; 2/3=8-bit bypass*/ + hdmitx_wr_reg(HDMITX_DWC_VP_CONF, data32); + + data32 = 0; + data32 |= (1 << 7); + data32 |= (1 << 6); + data32 |= (1 << 5); + data32 |= (1 << 4); + data32 |= (1 << 3); + data32 |= (1 << 2); + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_VP_MASK, data32); + + /* Configure audio */ + /* I2S Sampler config */ + + data32 = 0; + data32 |= (1 << 3); + data32 |= (1 << 2); + hdmitx_wr_reg(HDMITX_DWC_AUD_INT, data32); + + data32 = 0; + data32 |= (1 << 4); + hdmitx_wr_reg(HDMITX_DWC_AUD_INT1, data32); + + hdmitx_wr_reg(HDMITX_DWC_FC_MULTISTREAM_CTRL, 0); + +/* if enable it now, fifo_overrun will happen, because packet don't get + * sent out until initial DE detected. + */ + data32 = 0; + data32 |= (0 << 7); + data32 |= (1 << 5); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_AUD_CONF0, data32); + + data32 = 0; + data32 |= (0 << 5); + data32 |= (24 << 0); + hdmitx_wr_reg(HDMITX_DWC_AUD_CONF1, data32); + + data32 = 0; + data32 |= (0 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_AUD_CONF2, data32); + + /* spdif sampler config */ + + data32 = 0; + data32 |= (1 << 3); + data32 |= (1 << 2); + hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT, data32); + + data32 = 0; + data32 |= (0 << 4); + hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT1, data32); + + data32 = 0; + data32 |= (0 << 7); + hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF0, data32); + + data32 = 0; + data32 |= (0 << 7); + data32 |= (0 << 6); + data32 |= (24 << 0); + hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF1, data32); + + /* Frame Composer configuration */ + + /* Video definitions, as per output video(for packet gen/schedulling) */ + + data32 = 0; + data32 |= (1 << 7); + data32 |= (GET_TIMING(vsync_polarity) << 6); + data32 |= (GET_TIMING(hsync_polarity) << 5); + data32 |= (1 << 4); + data32 |= (1 << 3); + data32 |= (!(para->progress_mode) << 1); + data32 |= (!(para->progress_mode) << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_INVIDCONF, data32); + + data32 = GET_TIMING(h_active)&0xff; + hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV0, data32); + data32 = (GET_TIMING(h_active)>>8) & 0x3f; + hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV1, data32); + + data32 = GET_TIMING(h_blank) & 0xff; + hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK0, data32); + data32 = (GET_TIMING(h_blank)>>8)&0x1f; + hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK1, data32); + + data32 = GET_TIMING(v_active)&0xff; + hdmitx_wr_reg(HDMITX_DWC_FC_INVACTV0, data32); + data32 = (GET_TIMING(v_active)>>8)&0x1f; + hdmitx_wr_reg(HDMITX_DWC_FC_INVACTV1, data32); + + data32 = GET_TIMING(v_blank)&0xff; + hdmitx_wr_reg(HDMITX_DWC_FC_INVBLANK, data32); + + data32 = GET_TIMING(h_front)&0xff; + hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY0, data32); + data32 = (GET_TIMING(h_front)>>8)&0x1f; + hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY1, data32); + + data32 = GET_TIMING(h_sync)&0xff; + hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH0, data32); + data32 = (GET_TIMING(h_sync)>>8)&0x3; + hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH1, data32); + + data32 = GET_TIMING(v_front)&0xff; + hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINDELAY, data32); + + data32 = GET_TIMING(v_sync)&0x3f; + hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH, data32); + + /* control period duration (typ 12 tmds periods) */ + hdmitx_wr_reg(HDMITX_DWC_FC_CTRLDUR, 12); + /* extended control period duration (typ 32 tmds periods) */ + hdmitx_wr_reg(HDMITX_DWC_FC_EXCTRLDUR, 32); + /* max interval betwen extended control period duration (typ 50) */ + hdmitx_wr_reg(HDMITX_DWC_FC_EXCTRLSPAC, 1); + /* preamble filler */ + hdmitx_wr_reg(HDMITX_DWC_FC_CH0PREAM, 0x0b); + hdmitx_wr_reg(HDMITX_DWC_FC_CH1PREAM, 0x16); + hdmitx_wr_reg(HDMITX_DWC_FC_CH2PREAM, 0x21); + + /* write GCP packet configuration */ + data32 = 0; + data32 |= (default_phase << 2); + data32 |= (0 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_GCP, data32); + + /* write AVI Infoframe packet configuration */ + + data32 = 0; + data32 |= (((output_color_format>>2)&0x1) << 7); + data32 |= (1 << 6); + data32 |= (0 << 4); + data32 |= (0 << 2); + data32 |= (0x2 << 0); /* FIXED YCBCR 444 */ + hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF0, data32); + switch (output_color_format) { + case HDMI_COLOR_FORMAT_RGB: + tmp = 0; + break; + case HDMI_COLOR_FORMAT_422: + tmp = 1; + break; + case HDMI_COLOR_FORMAT_420: + tmp = 3; + break; + case HDMI_COLOR_FORMAT_444: + default: + tmp = 2; + break; + } + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF0, tmp, 0, 2); + + hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF1, 0x8); + hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF2, 0); + + /* set Aspect Ratio in AVIInfo */ + switch (para->vic) { + case HDMI_640x480p60_4x3: + case HDMI_720x480p60_4x3: + case HDMI_720x480i60_4x3: + case HDMI_720x240p60_4x3: + case HDMI_2880x480i60_4x3: + case HDMI_2880x240p60_4x3: + case HDMI_1440x480p60_4x3: + case HDMI_720x576p50_4x3: + case HDMI_720x576i50_4x3: + case HDMI_720x288p_4x3: + case HDMI_2880x576i50_4x3: + case HDMI_2880x288p50_4x3: + case HDMI_1440x576p_4x3: + case HDMI_2880x480p60_4x3: + case HDMI_2880x576p50_4x3: + case HDMI_720x576p100_4x3: + case HDMI_720x576i100_4x3: + case HDMI_720x480p120_4x3: + case HDMI_720x480i120_4x3: + case HDMI_720x576p200_4x3: + case HDMI_720x576i200_4x3: + case HDMI_720x480p240_4x3: + case HDMI_720x480i240_4x3: + /* Picture Aspect Ratio M1/M0 4:3 */ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x1, 4, 2); + break; + default: + /* Picture Aspect Ratio M1/M0 16:9 */ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x2, 4, 2); + break; + } + /* Active Format Aspect Ratio R3~R0 Same as picture aspect ratio */ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x8, 0, 4); + + /* set Colorimetry in AVIInfo */ + switch (para->vic) { + case HDMI_640x480p60_4x3: + case HDMI_720x480p60_4x3: + case HDMI_720x480p60_16x9: + case HDMI_720x480i60_4x3: + case HDMI_720x480i60_16x9: + case HDMI_720x240p60_4x3: + case HDMI_720x240p60_16x9: + case HDMI_2880x480i60_4x3: + case HDMI_2880x480i60_16x9: + case HDMI_2880x240p60_4x3: + case HDMI_2880x240p60_16x9: + case HDMI_1440x480p60_4x3: + case HDMI_1440x480p60_16x9: + case HDMI_720x576p50_4x3: + case HDMI_720x576p50_16x9: + case HDMI_720x576i50_4x3: + case HDMI_720x576i50_16x9: + case HDMI_720x288p_4x3: + case HDMI_720x288p_16x9: + case HDMI_2880x576i50_4x3: + case HDMI_2880x576i50_16x9: + case HDMI_2880x288p50_4x3: + case HDMI_2880x288p50_16x9: + case HDMI_1440x576p_4x3: + case HDMI_1440x576p_16x9: + case HDMI_2880x480p60_4x3: + case HDMI_2880x480p60_16x9: + case HDMI_2880x576p50_4x3: + case HDMI_2880x576p50_16x9: + case HDMI_720x576p100_4x3: + case HDMI_720x576p100_16x9: + case HDMI_720x576i100_4x3: + case HDMI_720x576i100_16x9: + case HDMI_720x480p120_4x3: + case HDMI_720x480p120_16x9: + case HDMI_720x480i120_4x3: + case HDMI_720x480i120_16x9: + case HDMI_720x576p200_4x3: + case HDMI_720x576p200_16x9: + case HDMI_720x576i200_4x3: + case HDMI_720x576i200_16x9: + case HDMI_720x480p240_4x3: + case HDMI_720x480p240_16x9: + case HDMI_720x480i240_4x3: + case HDMI_720x480i240_16x9: + /* C1C0 601 , now is 709*/ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 1, 6, 2); + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3); + break; + default: + /* C1C0 709 */ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 2, 6, 2); + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3); + break; + } + + data32 = 0; + data32 |= (((output_color_range == HDMI_COLOR_RANGE_FUL)?1:0) << 2); /*[3:2] YQ*/ + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF3, data32); + + if (para->vic >= HDMITX_VESA_OFFSET) + hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0); + else + hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, para->vic); + +/* the audio setting bellow are only used for I2S audio IEC60958-3 frame + * insertion + */ + + /* packet queue priority (auto mode) */ + hdmitx_wr_reg(HDMITX_DWC_FC_CTRLQHIGH, 15); + hdmitx_wr_reg(HDMITX_DWC_FC_CTRLQLOW, 3); + + /* packet scheduller configuration for SPD, VSD, ISRC1/2, ACP. */ + data32 = 0; + data32 |= (0 << 4); + data32 |= (0 << 3); + data32 |= (0 << 2); + data32 |= (0 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO0, data32); + hdmitx_set_spdinfo(); + hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_DATMAN, 0); + + /* packet scheduller configuration for AVI, GCP, AUDI, ACR. */ + data32 = 0; + data32 |= (0 << 5); + data32 |= (0 << 4); + data32 |= (0 << 3); + data32 |= (1 << 2); + data32 |= (1 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO3, data32); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB0, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB1, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB2, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB3, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB4, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB5, 0); + /* AVI info usb RDRB mode and place in line 10*/ + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB6, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB7, 0x1a); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB8, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB9, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB10, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_RDRB11, 0); + + /* Packet transmission enable */ + data32 = 0; + data32 |= (0 << 6); + data32 |= (0 << 5); + data32 |= (0 << 4); + data32 |= (1 << 3); + data32 |= (1 << 2); + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_PACKET_TX_EN, data32); + + /* For 3D video */ + data32 = 0; + data32 |= (0 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_ACTSPC_HDLR_CFG, data32); + + data32 = GET_TIMING(v_active)&0xff; + hdmitx_wr_reg(HDMITX_DWC_FC_INVACT_2D_0, data32); + data32 = (GET_TIMING(v_active)>>8)&0xf; + hdmitx_wr_reg(HDMITX_DWC_FC_INVACT_2D_1, data32); + + /* Do not enable these interrupt below, we can check them at RX side. */ + data32 = 0; + data32 |= (1 << 7); + data32 |= (1 << 6); + data32 |= (1 << 5); + data32 |= (1 << 2); + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_MASK0, data32); + + data32 = 0; + data32 |= (1 << 7); + data32 |= (1 << 6); + data32 |= (1 << 5); + data32 |= (1 << 4); + data32 |= (1 << 3); + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_MASK1, data32); + + data32 = 0; + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_MASK2, data32); + + /* Pixel repetition ratio the input and output video */ + data32 = 0; + data32 |= ((para->pixel_repetition_factor+1) << 4); + data32 |= (para->pixel_repetition_factor << 0); + hdmitx_wr_reg(HDMITX_DWC_FC_PRCONF, data32); + + /* Configure HDCP */ + data32 = 0; + data32 |= (0 << 7); + data32 |= (0 << 6); + data32 |= (0 << 4); + data32 |= (0 << 3); + data32 |= (0 << 2); + data32 |= (0 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_A_APIINTMSK, data32); + + data32 = 0; + data32 |= (0 << 5); + data32 |= (1 << 4); + data32 |= (1 << 3); + data32 |= (1 << 1); + hdmitx_wr_reg(HDMITX_DWC_A_VIDPOLCFG, data32); + + hdmitx_wr_reg(HDMITX_DWC_A_OESSWCFG, 0x40); + hdmitx_hdcp_init(); + + /* Interrupts */ + /* Clear interrupts */ + hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT0, 0xff); + hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT1, 0xff); + hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT2, 0xff); + hdmitx_wr_reg(HDMITX_DWC_IH_AS_STAT0, 0xff); + hdmitx_wr_reg(HDMITX_DWC_IH_PHY_STAT0, 0xff); + hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0xff); + hdmitx_wr_reg(HDMITX_DWC_IH_CEC_STAT0, 0xff); + hdmitx_wr_reg(HDMITX_DWC_IH_VP_STAT0, 0xff); + hdmitx_wr_reg(HDMITX_DWC_IH_I2CMPHY_STAT0, 0xff); + hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, 0xff); + hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_STAT, 0xff); + + hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, 0x0000001f); + + /* Selectively enable/mute interrupt sources */ + data32 = 0; + data32 |= (1 << 7); + data32 |= (1 << 6); + data32 |= (1 << 5); + data32 |= (1 << 4); + data32 |= (1 << 3); + data32 |= (1 << 2); + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT0, data32); + + data32 = 0; + data32 |= (1 << 7); + data32 |= (1 << 6); + data32 |= (1 << 5); + data32 |= (1 << 4); + data32 |= (1 << 3); + data32 |= (1 << 2); + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT1, data32); + + data32 = 0; + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT2, data32); + + data32 = 0; + data32 |= (0 << 4); + data32 |= (0 << 3); + data32 |= (1 << 2); + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_AS_STAT0, data32); + + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_PHY_STAT0, 0x3f); + + data32 = 0; + data32 |= (0 << 2); + data32 |= (1 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CM_STAT0, data32); + + data32 = 0; + data32 |= (0 << 6); + data32 |= (0 << 5); + data32 |= (0 << 4); + data32 |= (0 << 3); + data32 |= (0 << 2); + data32 |= (0 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_CEC_STAT0, data32); + + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_VP_STAT0, 0xff); + + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0, 0x03); + + data32 = 0; + data32 |= (0 << 1); + data32 |= (0 << 0); + hdmitx_wr_reg(HDMITX_DWC_IH_MUTE, data32); + + data32 = 0; + data32 |= (1 << 4); + data32 |= (1 << 3); + data32 |= (1 << 2); + data32 |= (1 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_TOP_INTR_MASKN, data32); + + /* Reset pulse */ + hdmitx_rd_check_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff, 0x9f); + + hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0); + mdelay(10); + + data32 = 0; + data32 |= (1 << 7); + data32 |= (1 << 6); + data32 |= (1 << 4); + data32 |= (1 << 3); + data32 |= (1 << 2); + data32 |= (0 << 1); + data32 |= (1 << 0); + hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, data32); + hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH, + hdmitx_rd_reg(HDMITX_DWC_FC_VSYNCINWIDTH)); +} /* config_hdmi20_tx */ + +/* Set TV encoder for HDMI */ +static void hdmitx_enc(enum hdmi_vic vic) +{ + set_vmode_enc_hw(vic); + hdmi_tvenc_set(vic); + return; +} + +static void hdmitx_set_pll(struct hdmitx_dev *hdev) +{ + hdmitx_set_clk(hdev); +} + +/* + * mode: 1 means Progressive; 0 means interlaced + */ +static void enc_vpu_bridge_reset(int mode) +{ + unsigned int wr_clk = 0; + + wr_clk = (hd_read_reg(P_VPU_HDMI_SETTING) & 0xf00) >> 8; + if (mode) { + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/ + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/ + mdelay(1); + hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4); + mdelay(1); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 2, 0, 2); /*[ 0] src_sel_enci: Enable ENCP output to HDMI*/ + } else { + hd_write_reg(P_ENCI_VIDEO_EN, 0); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2); /*[ 0] src_sel_enci: Disable ENCI output to HDMI*/ + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/ + mdelay(1); + hd_write_reg(P_ENCI_VIDEO_EN, 1); + mdelay(1); + hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4); + mdelay(1); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 2); /*[ 0] src_sel_enci: Enable ENCI output to HDMI*/ + } +} + +static void hdmi_tvenc1080i_set(enum hdmi_vic vic) +{ + unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; + unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0, + PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0; + unsigned FRONT_PORCH = 88, HSYNC_PIXELS = 0, ACTIVE_LINES = 0, + INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0, + VSYNC_LINES = 0; + unsigned LINES_F0 = 0, LINES_F1 = 563, BACK_PORCH = 0; + + unsigned long total_pixels_venc = 0; + unsigned long active_pixels_venc = 0; + unsigned long front_porch_venc = 0; + unsigned long hsync_pixels_venc = 0; + + unsigned long de_h_begin = 0, de_h_end = 0; + unsigned long de_v_begin_even = 0, de_v_end_even = 0, + de_v_begin_odd = 0, de_v_end_odd = 0; + unsigned long hs_begin = 0, hs_end = 0; + unsigned long vs_adjust = 0; + unsigned long vs_bline_evn = 0, vs_eline_evn = 0, + vs_bline_odd = 0, vs_eline_odd = 0; + unsigned long vso_begin_evn = 0, vso_begin_odd = 0; + + if ((vic == HDMI_1920x1080i60_16x9) || + (vic == HDMI_1920x1080i120_16x9)) { + INTERLACE_MODE = 1; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); + LINES_F0 = 562; + LINES_F1 = 563; + FRONT_PORCH = 88; + HSYNC_PIXELS = 44; + BACK_PORCH = 148; + VSYNC_LINES = 5; + SOF_LINES = 15; + } else if ((vic == HDMI_1920x1080i50_16x9) || + (vic == HDMI_1920x1080i100_16x9)) { + INTERLACE_MODE = 1; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); + LINES_F0 = 562; + LINES_F1 = 563; + FRONT_PORCH = 528; + HSYNC_PIXELS = 44; + BACK_PORCH = 148; + VSYNC_LINES = 5; + SOF_LINES = 15; + } + TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); + TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE)); + + total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + hsync_pixels_venc = + (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); + + hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14)); + + /* Program DE timing */ + de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) + + VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); + de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); + hd_write_reg(P_ENCP_DE_H_END, de_h_end); + /* Program DE timing for even field */ + de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE); + de_v_end_even = de_v_begin_even + ACTIVE_LINES; + hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); + hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); + /* Program DE timing for odd field if needed */ + if (INTERLACE_MODE) { + de_v_begin_odd = to_signed(( + hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4) + + de_v_begin_even + (TOTAL_LINES-1)/2; + de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; + hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);/* 583 */ + hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd); /* 1123 */ + } + + /* Program Hsync timing */ + if (de_h_end + front_porch_venc >= total_pixels_venc) { + hs_begin = de_h_end + front_porch_venc - total_pixels_venc; + vs_adjust = 1; + } else { + hs_begin = de_h_end + front_porch_venc; + vs_adjust = 0; + } + hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin); + hd_write_reg(P_ENCP_DVI_HSO_END, hs_end); + + /* Program Vsync timing for even field */ + if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust)) + vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES + - (1-vs_adjust); + else + vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES + - VSYNC_LINES - (1-vs_adjust); + + vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); + hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 0 */ + hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 5 */ + vso_begin_evn = hs_begin; /* 2 */ + hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 2 */ + hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 2 */ + /* Program Vsync timing for odd field if needed */ + if (INTERLACE_MODE) { + vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES; + vs_eline_odd = de_v_begin_odd-1 - SOF_LINES; + vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), + total_pixels_venc); + hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd); + hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd); + hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd); + hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd); + } + + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (HSYNC_POLARITY << 2) | + (VSYNC_POLARITY << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + +} + +static bool is_hdmi4k_420(enum hdmi_vic vic) +{ + if ((vic & HDMITX_VIC420_OFFSET) == HDMITX_VIC420_OFFSET) + return 1; + return 0; +} + +static void hdmi_tvenc4k2k_set(enum hdmi_vic vic) +{ + unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; + unsigned long TOTAL_PIXELS = 4400, PIXEL_REPEAT_HDMI = 0, + PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 3840; + unsigned FRONT_PORCH = 1020, HSYNC_PIXELS = 0, ACTIVE_LINES = 2160, + INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0, + VSYNC_LINES = 0; + unsigned LINES_F0 = 2250, LINES_F1 = 2250, BACK_PORCH = 0; + + unsigned long total_pixels_venc = 0; + unsigned long active_pixels_venc = 0; + unsigned long front_porch_venc = 0; + unsigned long hsync_pixels_venc = 0; + + unsigned long de_h_begin = 0, de_h_end = 0; + unsigned long de_v_begin_even = 0, de_v_end_even = 0; + unsigned long hs_begin = 0, hs_end = 0; + unsigned long vs_adjust = 0; + unsigned long vs_adjust_420 = 0; + unsigned long vs_bline_evn = 0, vs_eline_evn = 0; + unsigned long vso_begin_evn = 0; + +/* Due to 444->420 line buffer latency, the active line output from + * 444->420 conversion will be delayed by 1 line. So for 420 mode, + * we need to delay Vsync by 1 line as well, to meet the timing + */ + if (is_hdmi4k_420(vic)) + vs_adjust_420 = 1; + + switch (vic) { + case HDMI_3840x2160p30_16x9: + case HDMI_3840x2160p60_16x9: + case HDMI_3840x2160p60_16x9_Y420: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); + LINES_F0 = 2250; + LINES_F1 = 2250; + FRONT_PORCH = 176; + HSYNC_PIXELS = 88; + BACK_PORCH = 296; + VSYNC_LINES = 10; + SOF_LINES = 72 + 1; + break; + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p50_16x9_Y420: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); + LINES_F0 = 2250; + LINES_F1 = 2250; + FRONT_PORCH = 1056; + HSYNC_PIXELS = 88; + BACK_PORCH = 296; + VSYNC_LINES = 10; + SOF_LINES = 72 + 1; + break; + case HDMI_3840x2160p24_16x9: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); + LINES_F0 = 2250; + LINES_F1 = 2250; + FRONT_PORCH = 1276; + HSYNC_PIXELS = 88; + BACK_PORCH = 296; + VSYNC_LINES = 10; + SOF_LINES = 72 + 1; + break; + case HDMI_4096x2160p24_256x135: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); + LINES_F0 = 2250; + LINES_F1 = 2250; + FRONT_PORCH = 1020; + HSYNC_PIXELS = 88; + BACK_PORCH = 296; + VSYNC_LINES = 10; + SOF_LINES = 72 + 1; + break; + case HDMI_4096x2160p25_256x135: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p50_256x135_Y420: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); + LINES_F0 = 2250; + LINES_F1 = 2250; + FRONT_PORCH = 968; + HSYNC_PIXELS = 88; + BACK_PORCH = 128; + VSYNC_LINES = 10; + SOF_LINES = 72; + break; + case HDMI_4096x2160p30_256x135: + case HDMI_4096x2160p60_256x135: + case HDMI_4096x2160p60_256x135_Y420: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); + LINES_F0 = 2250; + LINES_F1 = 2250; + FRONT_PORCH = 88; + HSYNC_PIXELS = 88; + BACK_PORCH = 128; + VSYNC_LINES = 10; + SOF_LINES = 72; + break; + default: + printk("hdmitx20: no setting for VIC = %d\n", vic); + break; + } + + TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); + TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE)); + + total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + + de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) + + VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); + de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); + hd_write_reg(P_ENCP_DE_H_END, de_h_end); + /* Program DE timing for even field */ + de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE); + de_v_end_even = modulo(de_v_begin_even + ACTIVE_LINES, TOTAL_LINES); + hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); + hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); + + /* Program Hsync timing */ + if (de_h_end + front_porch_venc >= total_pixels_venc) { + hs_begin = de_h_end + front_porch_venc - total_pixels_venc; + vs_adjust = 1; + } else { + hs_begin = de_h_end + front_porch_venc; + vs_adjust = 1; + } + hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin); + hd_write_reg(P_ENCP_DVI_HSO_END, hs_end); + + /* Program Vsync timing for even field */ + if (de_v_begin_even + vs_adjust_420 >= + SOF_LINES + VSYNC_LINES + (1 - vs_adjust)) + vs_bline_evn = de_v_begin_even + vs_adjust_420 - SOF_LINES - + VSYNC_LINES - (1 - vs_adjust); + else + vs_bline_evn = TOTAL_LINES + de_v_begin_even + vs_adjust_420 - + SOF_LINES - VSYNC_LINES - (1 - vs_adjust); + vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); + hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); + hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); + vso_begin_evn = hs_begin; + hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); + hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (HSYNC_POLARITY << 2) | + (VSYNC_POLARITY << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + if (is_hdmi4k_420(vic)) { + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 1); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 20, 1); + } + + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); +} + +static void hdmi_tvenc480i_set(enum hdmi_vic vic) +{ + unsigned long VFIFO2VD_TO_HDMI_LATENCY = 1; + unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0, + PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0; + unsigned FRONT_PORCH = 38, HSYNC_PIXELS = 124, ACTIVE_LINES = 0, + INTERLACE_MODE = 0, VSYNC_LINES = 0; + unsigned LINES_F0 = 262, LINES_F1 = 263, BACK_PORCH = 114, + EOF_LINES = 2; + + unsigned long total_pixels_venc = 0; + unsigned long active_pixels_venc = 0; + unsigned long front_porch_venc = 0; + unsigned long hsync_pixels_venc = 0; + + unsigned long de_h_begin = 0, de_h_end = 0; + unsigned long de_v_begin_even = 0, de_v_end_even = 0, + de_v_begin_odd = 0, de_v_end_odd = 0; + unsigned long hs_begin = 0, hs_end = 0; + unsigned long vs_adjust = 0; + unsigned long vs_bline_evn = 0, vs_eline_evn = 0, + vs_bline_odd = 0, vs_eline_odd = 0; + unsigned long vso_begin_evn = 0, vso_begin_odd = 0; + + /* hd_set_reg_bits(P_HHI_GCLK_OTHER, 1, 8, 1); TODO */ + switch (vic) { + case HDMI_720x480i60_4x3: + case HDMI_720x480i60_16x9: + case HDMI_720x480i120_4x3: + case HDMI_720x480i120_16x9: + case HDMI_720x480i240_4x3: + case HDMI_720x480i240_16x9: + INTERLACE_MODE = 1; + PIXEL_REPEAT_VENC = 1; + PIXEL_REPEAT_HDMI = 1; + ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (480/(1+INTERLACE_MODE)); + LINES_F0 = 262; + LINES_F1 = 263; + FRONT_PORCH = 38; + HSYNC_PIXELS = 124; + BACK_PORCH = 114; + EOF_LINES = 4; + VSYNC_LINES = 3; + break; + case HDMI_720x576i50_4x3: + case HDMI_720x576i50_16x9: + case HDMI_720x576i100_4x3: + case HDMI_720x576i100_16x9: + case HDMI_720x576i200_4x3: + case HDMI_720x576i200_16x9: + INTERLACE_MODE = 1; + PIXEL_REPEAT_VENC = 1; + PIXEL_REPEAT_HDMI = 1; + ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (576/(1+INTERLACE_MODE)); + LINES_F0 = 312; + LINES_F1 = 313; + FRONT_PORCH = 24; + HSYNC_PIXELS = 126; + BACK_PORCH = 138; + EOF_LINES = 2; + VSYNC_LINES = 3; + break; + default: + break; + } + + TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); + + total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); /* 1716 / 2 * 2 = 1716 */ + active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); /* 38 / 2 * 2 = 38 */ + hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); /* 124 / 2 * 2 = 124 */ + + de_h_begin = modulo(hd_read_reg(P_ENCI_VFIFO2VD_PIXEL_START) + + VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); + de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCI_DE_H_BEGIN, de_h_begin); /* 235 */ + hd_write_reg(P_ENCI_DE_H_END, de_h_end); /* 1675 */ + + de_v_begin_even = hd_read_reg(P_ENCI_VFIFO2VD_LINE_TOP_START); + de_v_end_even = de_v_begin_even + ACTIVE_LINES; + de_v_begin_odd = hd_read_reg(P_ENCI_VFIFO2VD_LINE_BOT_START); + de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; + hd_write_reg(P_ENCI_DE_V_BEGIN_EVEN, de_v_begin_even); + hd_write_reg(P_ENCI_DE_V_END_EVEN, de_v_end_even); + hd_write_reg(P_ENCI_DE_V_BEGIN_ODD, de_v_begin_odd); + hd_write_reg(P_ENCI_DE_V_END_ODD, de_v_end_odd); + + /* Program Hsync timing */ + if (de_h_end + front_porch_venc >= total_pixels_venc) { + hs_begin = de_h_end + front_porch_venc - total_pixels_venc; + vs_adjust = 1; + } else { + hs_begin = de_h_end + front_porch_venc; + vs_adjust = 0; + } + hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCI_DVI_HSO_BEGIN, hs_begin); /* 1713 */ + hd_write_reg(P_ENCI_DVI_HSO_END, hs_end); /* 121 */ + + /* Program Vsync timing for even field */ + if (de_v_end_odd-1 + EOF_LINES + vs_adjust >= LINES_F1) { + vs_bline_evn = de_v_end_odd-1 + EOF_LINES + vs_adjust + - LINES_F1; + vs_eline_evn = vs_bline_evn + VSYNC_LINES; + hd_write_reg(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn); + /* vso_bline_evn_reg_wr_cnt ++; */ + hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn); + /* vso_eline_evn_reg_wr_cnt ++; */ + hd_write_reg(P_ENCI_DVI_VSO_BEGIN_EVN, hs_begin); + hd_write_reg(P_ENCI_DVI_VSO_END_EVN, hs_begin); + } else { + vs_bline_odd = de_v_end_odd-1 + EOF_LINES + vs_adjust; + hd_write_reg(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd); + /* vso_bline_odd_reg_wr_cnt ++; */ + hd_write_reg(P_ENCI_DVI_VSO_BEGIN_ODD, hs_begin); + if (vs_bline_odd + VSYNC_LINES >= LINES_F1) { + vs_eline_evn = vs_bline_odd + VSYNC_LINES - LINES_F1; + hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn); + /* vso_eline_evn_reg_wr_cnt ++; */ + hd_write_reg(P_ENCI_DVI_VSO_END_EVN, hs_begin); + } else { + vs_eline_odd = vs_bline_odd + VSYNC_LINES; + hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd); + /* vso_eline_odd_reg_wr_cnt ++; */ + hd_write_reg(P_ENCI_DVI_VSO_END_ODD, hs_begin); + } + } + /* Program Vsync timing for odd field */ + if (de_v_end_even-1 + EOF_LINES + 1 >= LINES_F0) { + vs_bline_odd = de_v_end_even-1 + EOF_LINES + 1 - LINES_F0; + vs_eline_odd = vs_bline_odd + VSYNC_LINES; + hd_write_reg(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd); + /* vso_bline_odd_reg_wr_cnt ++; */ + hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd); + /* vso_eline_odd_reg_wr_cnt ++; */ + vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), + total_pixels_venc); + hd_write_reg(P_ENCI_DVI_VSO_BEGIN_ODD, vso_begin_odd); + hd_write_reg(P_ENCI_DVI_VSO_END_ODD, vso_begin_odd); + } else { + vs_bline_evn = de_v_end_even-1 + EOF_LINES + 1; + hd_write_reg(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 261 */ + /* vso_bline_evn_reg_wr_cnt ++; */ + vso_begin_evn = modulo(hs_begin + (total_pixels_venc>>1), + total_pixels_venc); + hd_write_reg(P_ENCI_DVI_VSO_BEGIN_EVN, vso_begin_evn); + if (vs_bline_evn + VSYNC_LINES >= LINES_F0) { + vs_eline_odd = vs_bline_evn + VSYNC_LINES - LINES_F0; + hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd); + /* vso_eline_odd_reg_wr_cnt ++; */ + hd_write_reg(P_ENCI_DVI_VSO_END_ODD, vso_begin_evn); + } else { + vs_eline_evn = vs_bline_evn + VSYNC_LINES; + hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn); + /* vso_eline_evn_reg_wr_cnt ++; */ + hd_write_reg(P_ENCI_DVI_VSO_END_EVN, vso_begin_evn); + } + } + + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (0 << 2) | + (0 << 3) | + (0 << 4) | + (4 << 5) | + (1 << 8) | + (1 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); +} + +static void hdmi_tvenc_set_def(enum hdmi_vic vic) +{ + unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; + unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0, + PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0; + unsigned FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0, + INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0, + VSYNC_LINES = 0; + unsigned LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0; + + unsigned long total_pixels_venc = 0; + unsigned long active_pixels_venc = 0; + unsigned long front_porch_venc = 0; + unsigned long hsync_pixels_venc = 0; + + unsigned long de_h_begin = 0, de_h_end = 0; + unsigned long de_v_begin_even = 0, de_v_end_even = 0; + unsigned long hs_begin = 0, hs_end = 0; + unsigned long vs_adjust = 0; + unsigned long vs_bline_evn = 0, vs_eline_evn = 0; + unsigned long vso_begin_evn = 0; + + + switch (vic) { + case HDMI_720x480p60_16x9: + case HDMI_720x480p120_16x9: + case HDMI_720x480p60_4x3: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (480/(1+INTERLACE_MODE)); + LINES_F0 = 525; + LINES_F1 = 525; + FRONT_PORCH = 16; + HSYNC_PIXELS = 62; + BACK_PORCH = 60; + VSYNC_LINES = 6; + SOF_LINES = 30; + break; + case HDMI_720x576p50_16x9: + case HDMI_720x576p100_16x9: + case HDMI_720x576p50_4x3: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (576/(1+INTERLACE_MODE)); + LINES_F0 = 625; + LINES_F1 = 625; + FRONT_PORCH = 12; + HSYNC_PIXELS = 64; + BACK_PORCH = 68; + VSYNC_LINES = 5; + SOF_LINES = 39; + break; + case HDMI_1280x720p60_16x9: + case HDMI_1280x720p120_16x9: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (720/(1+INTERLACE_MODE)); + LINES_F0 = 750; + LINES_F1 = 750; + FRONT_PORCH = 110; + HSYNC_PIXELS = 40; + BACK_PORCH = 220; + VSYNC_LINES = 5; + SOF_LINES = 20; + break; + case HDMI_1280x720p50_16x9: + case HDMI_1280x720p100_16x9: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (720/(1+INTERLACE_MODE)); + LINES_F0 = 750; + LINES_F1 = 750; + FRONT_PORCH = 440; + HSYNC_PIXELS = 40; + BACK_PORCH = 220; + VSYNC_LINES = 5; + SOF_LINES = 20; + break; + case HDMI_1920x1080p50_16x9: + case HDMI_1920x1080p25_16x9: + case HDMI_1920x1080p100_16x9: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); + LINES_F0 = 1125; + LINES_F1 = 1125; + FRONT_PORCH = 528; + HSYNC_PIXELS = 44; + BACK_PORCH = 148; + VSYNC_LINES = 5; + SOF_LINES = 36; + break; + case HDMI_1920x1080p24_16x9: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); + LINES_F0 = 1125; + LINES_F1 = 1125; + FRONT_PORCH = 638; + HSYNC_PIXELS = 44; + BACK_PORCH = 148; + VSYNC_LINES = 5; + SOF_LINES = 36; + break; + case HDMI_1920x1080p60_16x9: + case HDMI_1920x1080p30_16x9: + case HDMI_1920x1080p120_16x9: + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); + ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); + LINES_F0 = 1125; + LINES_F1 = 1125; + FRONT_PORCH = 88; + HSYNC_PIXELS = 44; + BACK_PORCH = 148; + VSYNC_LINES = 5; + SOF_LINES = 36; + break; + default: + break; + } + + TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); + TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE)); + + total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + + hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14)); + /* Program DE timing */ + de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) + + VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); + de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); /* 220 */ + hd_write_reg(P_ENCP_DE_H_END, de_h_end); /* 1660 */ + /* Program DE timing for even field */ + de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE); + de_v_end_even = de_v_begin_even + ACTIVE_LINES; + hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); + hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */ + + /* Program Hsync timing */ + if (de_h_end + front_porch_venc >= total_pixels_venc) { + hs_begin = de_h_end + front_porch_venc - total_pixels_venc; + vs_adjust = 1; + } else { + hs_begin = de_h_end + front_porch_venc; + vs_adjust = 0; + } + hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin); + hd_write_reg(P_ENCP_DVI_HSO_END, hs_end); + + /* Program Vsync timing for even field */ + if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust)) + vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES - + (1-vs_adjust); + else + vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES - + VSYNC_LINES - (1-vs_adjust); + vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); + hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 5 */ + hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 11 */ + vso_begin_evn = hs_begin; /* 1692 */ + hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */ + hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */ + + switch (vic) { + case HDMI_720x480i60_16x9: + case HDMI_720x576i50_16x9: + case HDMI_720x480i60_4x3: + case HDMI_720x576i50_4x3: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (0 << 2) | + (0 << 3) | + (0 << 4) | + (4 << 5) | + (1 << 8) | + (1 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); + break; + case HDMI_1920x1080i60_16x9: + case HDMI_1920x1080i50_16x9: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (HSYNC_POLARITY << 2) | + (VSYNC_POLARITY << 3) | + (0 << 4) | + (((TX_INPUT_COLOR_FORMAT == 0) ? 1 : 0) << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + break; + case HDMI_3840x2160p30_16x9: + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p24_16x9: + case HDMI_4096x2160p24_256x135: + case HDMI_4096x2160p25_256x135: + case HDMI_4096x2160p30_256x135: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p60_256x135: + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (HSYNC_POLARITY << 2) | + (VSYNC_POLARITY << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + break; + case HDMI_720x480p60_16x9: + case HDMI_720x576p50_16x9: + case HDMI_720x480p60_4x3: + case HDMI_720x576p50_4x3: + case HDMI_720x480p120_16x9: + case HDMI_720x576p100_16x9: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (0 << 2) | + (0 << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + break; + case HDMI_1280x720p60_16x9: + case HDMI_1280x720p50_16x9: + case HDMI_1280x720p100_16x9: + case HDMI_1280x720p120_16x9: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (HSYNC_POLARITY << 2) | + (VSYNC_POLARITY << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + break; + default: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | /* [ 1] src_sel_encp */ + (HSYNC_POLARITY << 2) | + (VSYNC_POLARITY << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + } + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); +} + +static void hdmi_tvenc_vesa_set(enum hdmi_vic vic) +{ + unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; + unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0, + PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0; + unsigned FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0, + INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0, + VSYNC_LINES = 0; + unsigned LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0; + + unsigned long total_pixels_venc = 0; + unsigned long active_pixels_venc = 0; + unsigned long front_porch_venc = 0; + unsigned long hsync_pixels_venc = 0; + + unsigned long de_h_begin = 0, de_h_end = 0; + unsigned long de_v_begin_even = 0, de_v_end_even = 0; + unsigned long hs_begin = 0, hs_end = 0; + unsigned long vs_adjust = 0; + unsigned long vs_bline_evn = 0, vs_eline_evn = 0; + unsigned long vso_begin_evn = 0; + struct hdmi_format_para *vpara = NULL; + struct hdmi_cea_timing *vtiming = NULL; + + vpara = hdmi_get_fmt_paras(vic); + if (vpara == NULL) { + printf("hdmitx: don't find Paras for VESA %d\n", vic); + return; + } else + vtiming = &vpara->timing; + + INTERLACE_MODE = 0; + PIXEL_REPEAT_VENC = 0; + PIXEL_REPEAT_HDMI = 0; + ACTIVE_PIXELS = vtiming->h_active; + ACTIVE_LINES = vtiming->v_active; + LINES_F0 = vtiming->v_total; + LINES_F1 = vtiming->v_total; + FRONT_PORCH = vtiming->h_front; + HSYNC_PIXELS = vtiming->h_sync; + BACK_PORCH = vtiming->h_back; + VSYNC_LINES = vtiming->v_sync; + SOF_LINES = vtiming->v_back; + + TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); + TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE)); + + total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * + (1+PIXEL_REPEAT_VENC); + + hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14)); + /* Program DE timing */ + de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) + + VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); + de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); /* 220 */ + hd_write_reg(P_ENCP_DE_H_END, de_h_end); /* 1660 */ + /* Program DE timing for even field */ + de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE); + de_v_end_even = de_v_begin_even + ACTIVE_LINES; + hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); + hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */ + + /* Program Hsync timing */ + if (de_h_end + front_porch_venc >= total_pixels_venc) { + hs_begin = de_h_end + front_porch_venc - total_pixels_venc; + vs_adjust = 1; + } else { + hs_begin = de_h_end + front_porch_venc; + vs_adjust = 0; + } + hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); + hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin); + hd_write_reg(P_ENCP_DVI_HSO_END, hs_end); + + /* Program Vsync timing for even field */ + if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust)) + vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES - + (1-vs_adjust); + else + vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES - + VSYNC_LINES - (1-vs_adjust); + vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); + hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 5 */ + hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 11 */ + vso_begin_evn = hs_begin; /* 1692 */ + hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */ + hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */ + + switch (vic) { + case HDMIV_640x480p60hz: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | + (0 << 2) | + (0 << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + break; + default: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | + (0 << 1) | /* [ 1] src_sel_encp */ + (HSYNC_POLARITY << 2) | + (VSYNC_POLARITY << 3) | + (0 << 4) | + (4 << 5) | + (0 << 8) | + (0 << 12) + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); + } + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); +} + +static void hdmi_tvenc_set(enum hdmi_vic vic) +{ + if ((vic & HDMITX_VESA_OFFSET) == HDMITX_VESA_OFFSET) { + /* VESA modes setting */ + hdmi_tvenc_vesa_set(vic); + return; + } + + switch (vic) { + case HDMI_720x480i60_16x9: + case HDMI_720x576i50_16x9: + case HDMI_720x480i60_4x3: + case HDMI_720x576i50_4x3: + hdmi_tvenc480i_set(vic); + break; + case HDMI_1920x1080i60_16x9: + case HDMI_1920x1080i50_16x9: + case HDMI_1920x1080i100_16x9: + case HDMI_1920x1080i120_16x9: + hdmi_tvenc1080i_set(vic); + break; + case HDMI_3840x2160p30_16x9: + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p24_16x9: + case HDMI_4096x2160p24_256x135: + case HDMI_4096x2160p25_256x135: + case HDMI_4096x2160p30_256x135: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p60_256x135: + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + case HDMI_4096x2160p50_256x135_Y420: + case HDMI_4096x2160p60_256x135_Y420: + case HDMI_3840x2160p50_16x9_Y420: + case HDMI_3840x2160p60_16x9_Y420: + hdmi_tvenc4k2k_set(vic); + break; + default: + hdmi_tvenc_set_def(vic); + break; + } + + switch (vic) { + case HDMI_720x480i60_16x9: + case HDMI_720x576i50_16x9: + case HDMI_720x480i60_4x3: + case HDMI_720x576i50_4x3: + /* Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /* [ 0] src_sel_enci*/ + (0 << 1) | /* [ 1] src_sel_encp*/ + (0 << 2) | /* [ 2] inv_hsync. 1=Invert Hsync polarity.*/ + (0 << 3) | /* [ 3] inv_vsync. 1=Invert Vsync polarity.*/ + (0 << 4) | /* [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ + (4 << 5) | /* [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ + /* 0=output CrYCb(BRG);*/ + /* 1=output YCbCr(RGB);*/ + /* 2=output YCrCb(RBG);*/ + /* 3=output CbCrY(GBR);*/ + /* 4=output CbYCr(GRB);*/ + /* 5=output CrCbY(BGR);*/ + /* 6,7=Rsrv.*/ + (1 << 8) | /* [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ + (1 <<12) /* [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); // [ 0] src_sel_enci: Enable ENCI output to HDMI*/ + break; + case HDMI_1920x1080i60_16x9: + case HDMI_1920x1080i50_16x9: + case HDMI_1920x1080i100_16x9: + case HDMI_1920x1080i120_16x9: + /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ + (0 << 1) | /*[ 1] src_sel_encp*/ + (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ + (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ + (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ + (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ + /* 0=output CrYCb(BRG);*/ + /* 1=output YCbCr(RGB);*/ + /* 2=output YCrCb(RBG);*/ + /* 3=output CbCrY(GBR);*/ + /* 4=output CbYCr(GRB);*/ + /* 5=output CrCbY(BGR);*/ + /* 6,7=Rsrv.*/ + (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ + (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ + break; + case HDMI_3840x2160p30_16x9: + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p24_16x9: + case HDMI_4096x2160p24_256x135: + case HDMI_4096x2160p25_256x135: + case HDMI_4096x2160p30_256x135: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p60_256x135: + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ + (0 << 1) | /*[ 1] src_sel_encp*/ + (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ + (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ + (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ + (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ + /* 0=output CrYCb(BRG);*/ + /* 1=output YCbCr(RGB);*/ + /* 2=output YCrCb(RBG);*/ + /* 3=output CbCrY(GBR);*/ + /* 4=output CbYCr(GRB);*/ + /* 5=output CrCbY(BGR);*/ + /* 6,7=Rsrv.*/ + (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ + (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ + ); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ + break; + case HDMI_720x480p60_16x9: + case HDMI_720x576p50_16x9: + case HDMI_720x480p60_4x3: + case HDMI_720x576p50_4x3: + case HDMI_720x480p120_16x9: + case HDMI_720x576p100_16x9: + /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ + (0 << 1) | /*[ 1] src_sel_encp*/ + (0 << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ + (0 << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ + (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ + (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ + /* 0=output CrYCb(BRG);*/ + /* 1=output YCbCr(RGB);*/ + /* 2=output YCrCb(RBG);*/ + /* 3=output CbCrY(GBR);*/ + /* 4=output CbYCr(GRB);*/ + /* 5=output CrCbY(BGR);*/ + /* 6,7=Rsrv.*/ + (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ + (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ + ); + /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ + break; + case HDMI_1280x720p60_16x9: + case HDMI_1280x720p50_16x9: + case HDMI_1280x720p100_16x9: + case HDMI_1280x720p120_16x9: + /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ + (0 << 1) | /*[ 1] src_sel_encp*/ + (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ + (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ + (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ + (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ + /* 0=output CrYCb(BRG);*/ + /* 1=output YCbCr(RGB);*/ + /* 2=output YCrCb(RBG);*/ + /* 3=output CbCrY(GBR);*/ + /* 4=output CbYCr(GRB);*/ + /* 5=output CrCbY(BGR);*/ + /* 6,7=Rsrv.*/ + (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ + (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ + ); + /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ + break; + default: + /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ + hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ + (0 << 1) | /*[ 1] src_sel_encp*/ + (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ + (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ + (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ + (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ + /* 0=output CrYCb(BRG);*/ + /* 1=output YCbCr(RGB);*/ + /* 2=output YCrCb(RBG);*/ + /* 3=output CbCrY(GBR);*/ + /* 4=output CbYCr(GRB);*/ + /* 5=output CrCbY(BGR);*/ + /* 6,7=Rsrv.*/ + (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ + (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ + ); + if (is_hdmi4k_420(vic)) { + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 1); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 20, 1); + } + /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ + hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ + } +} + +static void hdmitx_set_dith(struct hdmitx_dev* hdev) +{ + unsigned int hs_flag = 0; + + switch (hdev->para->cd) { + case HDMI_COLOR_DEPTH_30B: + case HDMI_COLOR_DEPTH_36B: + case HDMI_COLOR_DEPTH_48B: + /* 12-10 dithering on */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 4, 1); + hs_flag = (hd_read_reg(P_VPU_HDMI_SETTING) >> 2) & 0x3; + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 2, 2); + /* 12-10 rounding off */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 10, 1); + /* 10-8 dithering off (2x2 old dither) */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 0, 4, 1); + /* set hsync/vsync */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, hs_flag, 2, 2); + break; + default: + /* 12-10 dithering off */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 4, 1); + /* 12-10 rounding on */ + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 1, 10, 1); + /* 10-8 dithering on (2x2 old dither) */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 1, 4, 1); + /* set hsync/vsync as default 0 */ + hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 0, 2, 2); + break; + } +} + +static void set_tmds_clk_div40(unsigned int div40) +{ + if (div40 == 1) { + hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_01, 0); /*[25:16] tmds_clk_pttn[19:10] [ 9: 0] tmds_clk_pttn[ 9: 0]*/ + hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_23, 0x03ff03ff); /*[25:16] tmds_clk_pttn[39:30] [ 9: 0] tmds_clk_pttn[29:20]*/ + } else { + hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f); + hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f); + } + hdmitx_set_reg_bits(HDMITX_DWC_FC_SCRAMBLER_CTRL, (div40 == 1) ? 1 : 0, 0, 1); + + hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); /*0xc*/ + msleep(2); + hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); /*0xc*/ + scdc_prepare((div40 == 1) ? 1:0); +} + +static void hdmitx_set_vsi_pkt(enum hdmi_vic vic) +{ + /* convert to HDMI_VIC */ + if (vic == HDMI_3840x2160p30_16x9) + vic = 1; + else if (vic == HDMI_3840x2160p25_16x9) + vic = 2; + else if (vic == HDMI_3840x2160p24_16x9) + vic = 3; + else + vic = 4; + + hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID0, 0x03); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID1, 0x0c); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID2, 0x00); + hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD0, 0x20); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, vic); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 5); + hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 3, 1); + hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0x10); + hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1); +} + +static void hdmitx_set_packet(int type, unsigned char *DB, unsigned char *HB) +{ + unsigned int i; + + switch (type) { + case HDMI_PACKET_VEND: + if ((!DB) || (!HB)) { + hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 0, 3, 1); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 0x0); + return; + } + hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID0, DB[0]); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID1, DB[1]); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID2, DB[2]); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD0, DB[3]); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, HB[2]); + if (DB[3] == 0x20) { /* set HDMI VIC */ + hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, DB[4]); + } + if (HB[2] == 0x1b) {/*set dolby vsif data information*/ + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, DB[4]); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD2, DB[5]); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD3, DB[6]); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD4, DB[7]); + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD5, DB[8]); + } + + /*set hdr 10+ vsif data information*/ + if ((DB[0] == 0x8b) && (DB[1] == 0x84) && (DB[2] == 0x90)) { + for (i = 0; i < 23; i++) + hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1 + i, + DB[4 + i]); + } + + /* Enable VSI packet */ + hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 3, 1); + hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0); + hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0x10); + hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1); + break; + case HDMI_PACKET_DRM: + if ((!DB) || (!HB)) { + hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO3, 0, 6, 1); + hdmitx_set_reg_bits( + HDMITX_DWC_FC_PACKET_TX_EN, 0, 7, 1); + return; + } + /* Ignore HB[0] */ + hdmitx_wr_reg(HDMITX_DWC_FC_DRM_HB01, HB[1]); + hdmitx_wr_reg(HDMITX_DWC_FC_DRM_HB02, HB[2]); + for (i = 0; i < 26; i++) + hdmitx_wr_reg(HDMITX_DWC_FC_DRM_PB00 + i, DB[i]); + hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO3, 1, 6, 1); + hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 7, 1); + break; + default: + break; + } +} + +static int hdmitx_cntl_config(struct hdmitx_dev *hdev, unsigned int cmd, + unsigned int argv) +{ + int ret = 0; + + switch (cmd) { + case CONF_AVI_BT2020: + if (argv == SET_AVI_BT2020) { + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 3, 6, 2); + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 6, 4, 3); + } + if (argv == CLR_AVI_BT2020) {/*bt709*/ + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 2, 6, 2); + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3); + } + break; + case CONF_AVI_RGBYCC_INDIC: + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF0, argv, 0, 2); + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF0, 0, 7, 1); + break; + case CONF_AVI_Q01: + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, argv, 2, 2); + break; + case CONF_AVI_YQ01: + hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF3, argv, 2, 2); + break; + default: + break; + } + + return ret; +} + +#define GET_LOW8BIT(a) ((a) & 0xff) +#define GET_HIGH8BIT(a) (((a) >> 8) & 0xff) +void hdmitx_set_drm_pkt(struct master_display_info_s *data) +{ + struct hdmitx_dev *hdev = &hdmitx_device; + unsigned char DRM_HB[3] = {0x87, 0x1, 26}; + unsigned char DRM_DB[26] = {0x0}; + unsigned int hdr_transfer_feature = 0; + unsigned int hdr_color_feature = 0; + unsigned int hdr_mode = 0; + /* + *hdr_color_feature: bit 23-16: color_primaries + * 1:bt709 0x9:bt2020 + *hdr_transfer_feature: bit 15-8: transfer_characteristic + * 1:bt709 0xe:bt2020-10 0x10:smpte-st-2084 0x12:hlg(todo) + */ + if (NULL == data) { + return; + } + hdr_transfer_feature = (data->features >> 8) & 0xff; + hdr_color_feature = (data->features >> 16) & 0xff; + DRM_DB[1] = 0x0; + DRM_DB[2] = GET_LOW8BIT(data->primaries[0][0]); + DRM_DB[3] = GET_HIGH8BIT(data->primaries[0][0]); + DRM_DB[4] = GET_LOW8BIT(data->primaries[0][1]); + DRM_DB[5] = GET_HIGH8BIT(data->primaries[0][1]); + DRM_DB[6] = GET_LOW8BIT(data->primaries[1][0]); + DRM_DB[7] = GET_HIGH8BIT(data->primaries[1][0]); + DRM_DB[8] = GET_LOW8BIT(data->primaries[1][1]); + DRM_DB[9] = GET_HIGH8BIT(data->primaries[1][1]); + DRM_DB[10] = GET_LOW8BIT(data->primaries[2][0]); + DRM_DB[11] = GET_HIGH8BIT(data->primaries[2][0]); + DRM_DB[12] = GET_LOW8BIT(data->primaries[2][1]); + DRM_DB[13] = GET_HIGH8BIT(data->primaries[2][1]); + DRM_DB[14] = GET_LOW8BIT(data->white_point[0]); + DRM_DB[15] = GET_HIGH8BIT(data->white_point[0]); + DRM_DB[16] = GET_LOW8BIT(data->white_point[1]); + DRM_DB[17] = GET_HIGH8BIT(data->white_point[1]); + DRM_DB[18] = GET_LOW8BIT(data->luminance[0]); + DRM_DB[19] = GET_HIGH8BIT(data->luminance[0]); + DRM_DB[20] = GET_LOW8BIT(data->luminance[1]); + DRM_DB[21] = GET_HIGH8BIT(data->luminance[1]); + DRM_DB[22] = GET_LOW8BIT(data->max_content); + DRM_DB[23] = GET_HIGH8BIT(data->max_content); + DRM_DB[24] = GET_LOW8BIT(data->max_frame_average); + DRM_DB[25] = GET_HIGH8BIT(data->max_frame_average); + + + /* SMPTE ST 2084 and (BT2020 or NON_STANDARD) */ + if (hdr_transfer_feature == T_SMPTE_ST_2084 && + hdr_color_feature == C_BT2020) + hdr_mode = 1; + else if (hdr_transfer_feature == T_SMPTE_ST_2084 && + hdr_color_feature != C_BT2020) + hdr_mode = 2; + + /*HLG and BT2020*/ + if (hdr_color_feature == C_BT2020 && + (hdr_transfer_feature == T_BT2020_10 || + hdr_transfer_feature == T_HLG)) + hdr_mode = 3; + + switch (hdr_mode) { + case 1: + /*standard HDR*/ + DRM_DB[0] = 0x02; /* SMPTE ST 2084 */ + hdmitx_set_packet(HDMI_PACKET_DRM, DRM_DB, DRM_HB); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, SET_AVI_BT2020); + break; + case 2: + /*non standard*/ + DRM_DB[0] = 0x02; /* no standard SMPTE ST 2084 */ + hdmitx_set_packet(HDMI_PACKET_DRM, DRM_DB, DRM_HB); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, CLR_AVI_BT2020); + break; + case 3: + /*HLG*/ + DRM_DB[0] = 0x03;/* HLG is 0x03 */ + hdmitx_set_packet(HDMI_PACKET_DRM, DRM_DB, DRM_HB); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, SET_AVI_BT2020); + break; + case 0: + default: + /*other case*/ + hdmitx_set_packet(HDMI_PACKET_DRM, NULL, NULL); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, CLR_AVI_BT2020); + break; + } +} + +void hdmitx_set_vsif_pkt(enum eotf_type type, + enum mode_type tunnel_mode, struct dv_vsif_para *data) +{ + struct hdmitx_dev *hdev = &hdmitx_device; + struct dv_vsif_para para = {0}; + unsigned char VEN_HB[3] = {0x81, 0x01}; + unsigned char VEN_DB1[24] = {0x00}; + unsigned char VEN_DB2[27] = {0x00}; + unsigned char len = 0; + unsigned int vic = hdev->vic; + unsigned int hdmi_vic_4k_flag = 0; + + if ((hdev->RXCap.dv_info.ieeeoui != DV_IEEE_OUI)) + return; + + hdev->hdmi_current_eotf_type = type; + hdev->hdmi_current_tunnel_mode = tunnel_mode; + /*ver0 and ver1_15 and ver1_12bit with ll= 0 use hdmi 1.4b VSIF*/ + if ((hdev->RXCap.dv_info.ver == 0) || ((hdev->RXCap.dv_info.ver == 1) + && (hdev->RXCap.dv_info.length == 0xE)) + || ((hdev->RXCap.dv_info.ver == 1) + && (hdev->RXCap.dv_info.length == 0xB) + && (hdev->RXCap.dv_info.low_latency == 0))) { + if ((vic == HDMI_3840x2160p30_16x9) || + (vic == HDMI_3840x2160p25_16x9) || + (vic == HDMI_3840x2160p24_16x9) || + (vic == HDMI_4096x2160p24_256x135)) + hdmi_vic_4k_flag = 1; + + switch (type) { + case EOTF_T_DOLBYVISION: + len = 0x18; + break; + case EOTF_T_HDR10: + case EOTF_T_SDR: + case EOTF_T_NULL: + default: + len = 0x05; + break; + } + + VEN_HB[2] = len; + VEN_DB1[0] = 0x03; + VEN_DB1[1] = 0x0c; + VEN_DB1[2] = 0x00; + VEN_DB1[3] = 0x00; + + if (hdmi_vic_4k_flag) { + VEN_DB1[3] = 0x20; + if (vic == HDMI_3840x2160p30_16x9) + VEN_DB1[4] = 0x1; + else if (vic == HDMI_3840x2160p25_16x9) + VEN_DB1[4] = 0x2; + else if (vic == HDMI_3840x2160p24_16x9) + VEN_DB1[4] = 0x3; + else/*vic == HDMI_4096x2160p24_256x135*/ + VEN_DB1[4] = 0x4; + } + if (type == EOTF_T_DOLBYVISION) { + hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB1, VEN_HB); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, + CLR_AVI_BT2020);/*BT709*/ + if (tunnel_mode == RGB_8BIT) { + hdmitx_cntl_config(hdev,CONF_AVI_RGBYCC_INDIC, + HDMI_COLOR_FORMAT_RGB); + hdmitx_cntl_config(hdev, CONF_AVI_Q01, + RGB_RANGE_FUL); + } else { + hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC, + HDMI_COLOR_FORMAT_422); + hdmitx_cntl_config(hdev, CONF_AVI_YQ01, + YCC_RANGE_FUL); + } + } else { + if (hdmi_vic_4k_flag) + hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB1, VEN_HB); + else + hdmitx_set_packet(HDMI_PACKET_VEND, NULL, NULL); + hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC, + hdev->para->cs); + hdmitx_cntl_config(hdev, CONF_AVI_Q01, RGB_RANGE_LIM); + hdmitx_cntl_config(hdev, CONF_AVI_YQ01, + YCC_RANGE_LIM); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, + CLR_AVI_BT2020);/*BT709*/ + } + + } + /*ver1_12 with low_latency = 1 and ver2 use Dolby VSIF*/ + if ((hdev->RXCap.dv_info.ver == 2) || ((hdev->RXCap.dv_info.ver == 1) + && (hdev->RXCap.dv_info.length == 0xB) + && (hdev->RXCap.dv_info.low_latency == 1)) + || (type == EOTF_T_LL_MODE)) { + + if (data == NULL) + data = ¶ + /*4k vsif package */ + if ((vic == HDMI_3840x2160p30_16x9) || + (vic == HDMI_3840x2160p25_16x9) || + (vic == HDMI_3840x2160p24_16x9) || + (vic == HDMI_4096x2160p24_256x135)) + hdmi_vic_4k_flag = 1; + + switch (type) { + case EOTF_T_DOLBYVISION: + case EOTF_T_LL_MODE: + len = 0x1b; + break; + case EOTF_T_HDR10: + case EOTF_T_SDR: + case EOTF_T_NULL: + default: + len = 0x5; + break; + } + VEN_HB[2] = len; + VEN_DB2[0] = 0x46; + VEN_DB2[1] = 0xd0; + VEN_DB2[2] = 0x00; + VEN_DB2[3] = (data->vers.ver2.low_latency) | + (data->vers.ver2.dobly_vision_signal << 1); + VEN_DB2[4] = (data->vers.ver2.eff_tmax_PQ_hi) + | (data->vers.ver2.auxiliary_MD_present << 6) + | (data->vers.ver2.backlt_ctrl_MD_present << 7); + VEN_DB2[5] = data->vers.ver2.eff_tmax_PQ_low; + VEN_DB2[6] = data->vers.ver2.auxiliary_runmode; + VEN_DB2[7] = data->vers.ver2.auxiliary_runversion; + VEN_DB2[8] = data->vers.ver2.auxiliary_debug0; + + /*Dolby Vision standard case*/ + if (type == EOTF_T_DOLBYVISION) { + hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB2, VEN_HB); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, + CLR_AVI_BT2020);/*BT709*/ + if (tunnel_mode == RGB_8BIT) {/*RGB444*/ + hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC, + HDMI_COLOR_FORMAT_RGB); + hdmitx_cntl_config(hdev, CONF_AVI_Q01, + RGB_RANGE_FUL); + } else {/*YUV422*/ + hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC, + HDMI_COLOR_FORMAT_422); + hdmitx_cntl_config(hdev, CONF_AVI_YQ01, + YCC_RANGE_FUL); + } + } + /*Dolby Vision low-latency case*/ + else if (type == EOTF_T_LL_MODE) { + hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB2, VEN_HB); + if (hdev->RXCap.colorimetry_data & 0xe0) + /*if RX support BT2020, then output BT2020*/ + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, + SET_AVI_BT2020);/*BT2020*/ + else + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, + CLR_AVI_BT2020);/*BT709*/ + if (tunnel_mode == RGB_10_12BIT) {/*10/12bit RGB444*/ + hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC, + HDMI_COLOR_FORMAT_RGB); + hdmitx_cntl_config(hdev, CONF_AVI_Q01, + RGB_RANGE_LIM); + } else if (tunnel_mode == YUV444_10_12BIT) { + /*10/12bit YUV444*/ + hdmitx_cntl_config(hdev, + CONF_AVI_RGBYCC_INDIC, + HDMI_COLOR_FORMAT_444); + hdmitx_cntl_config(hdev, CONF_AVI_YQ01, + YCC_RANGE_LIM); + } else {/*YUV422*/ + hdmitx_cntl_config(hdev, + CONF_AVI_RGBYCC_INDIC, + HDMI_COLOR_FORMAT_422); + hdmitx_cntl_config(hdev, CONF_AVI_YQ01, + YCC_RANGE_LIM); + } + } + /*SDR case*/ + else { + if (hdmi_vic_4k_flag) { + VEN_DB1[0] = 0x03; + VEN_DB1[1] = 0x0c; + VEN_DB1[2] = 0x00; + hdmitx_set_packet(HDMI_PACKET_VEND, + VEN_DB2, VEN_HB); + } else + hdmitx_set_packet(HDMI_PACKET_VEND, + NULL, NULL); + hdmitx_cntl_config(hdev, + CONF_AVI_RGBYCC_INDIC, hdev->para->cs); + hdmitx_cntl_config(hdev, + CONF_AVI_Q01, RGB_RANGE_LIM); + hdmitx_cntl_config(hdev, + CONF_AVI_YQ01, YCC_RANGE_LIM); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, + CLR_AVI_BT2020);/*BT709*/ + } + } +} + +void hdmitx_set_hdr10plus_pkt(unsigned int flag, + struct hdr10plus_para *data) +{ + struct hdmitx_dev *hdev = &hdmitx_device; + unsigned char VEN_HB[3] = {0x81, 0x01, 0x1b}; + unsigned char VEN_DB[27] = {0x00}; + + if ((!data) || (!flag)) { + hdmitx_set_packet(HDMI_PACKET_VEND, NULL, NULL); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, + CLR_AVI_BT2020); + return; + } + + VEN_DB[0] = 0x8b; + VEN_DB[1] = 0x84; + VEN_DB[2] = 0x90; + + VEN_DB[3] = ((data->application_version & 0x3) << 6) | + ((data->targeted_max_lum & 0x1f) << 1); + VEN_DB[4] = data->average_maxrgb; + VEN_DB[5] = data->distribution_values[0]; + VEN_DB[6] = data->distribution_values[1]; + VEN_DB[7] = data->distribution_values[2]; + VEN_DB[8] = data->distribution_values[3]; + VEN_DB[9] = data->distribution_values[4]; + VEN_DB[10] = data->distribution_values[5]; + VEN_DB[11] = data->distribution_values[6]; + VEN_DB[12] = data->distribution_values[7]; + VEN_DB[13] = data->distribution_values[8]; + VEN_DB[14] = ((data->num_bezier_curve_anchors & 0xf) << 4) | + ((data->knee_point_x >> 6) & 0xf); + VEN_DB[15] = ((data->knee_point_x & 0x3f) << 2) | + ((data->knee_point_y >> 8) & 0x3); + VEN_DB[16] = data->knee_point_y & 0xff; + VEN_DB[17] = data->bezier_curve_anchors[0]; + VEN_DB[18] = data->bezier_curve_anchors[1]; + VEN_DB[19] = data->bezier_curve_anchors[2]; + VEN_DB[20] = data->bezier_curve_anchors[3]; + VEN_DB[21] = data->bezier_curve_anchors[4]; + VEN_DB[22] = data->bezier_curve_anchors[5]; + VEN_DB[23] = data->bezier_curve_anchors[6]; + VEN_DB[24] = data->bezier_curve_anchors[7]; + VEN_DB[25] = data->bezier_curve_anchors[8]; + VEN_DB[26] = ((data->graphics_overlay_flag & 0x1) << 7)| + ((data->no_delay_flag & 0x1) << 6); + + hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB, VEN_HB); + hdmitx_cntl_config(hdev, CONF_AVI_BT2020, + SET_AVI_BT2020); + +} +/* record HDMITX current format */ +/* ISA_DEBUG_REG0 0x2600 + * bit[11]: Y420 + * bit[10:8]: HDMI VIC + * bit[7:0]: CEA VIC + */ +static void save_hdmitx_format(enum hdmi_vic vic, int y420) +{ + unsigned int data32; + + data32 = vic & 0xff; + data32 |= (hdmitx_rd_reg(HDMITX_DWC_FC_VSDPAYLOAD1) & 0x7) << 8; + data32 |= (!!y420) << 11; + hd_write_reg(P_SYSCTRL_DEBUG_REG0, data32); +} + +static void hdmitx_set_phy(struct hdmitx_dev *hdev) +{ + if (!hdev) + return; + + switch (hdev->vic) { + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p60_256x135: + if ((hdev->para->cs == HDMI_COLOR_FORMAT_420) + && (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) + hdmitx_set_phypara(HDMI_PHYPARA_3G); + else + hdmitx_set_phypara(HDMI_PHYPARA_6G); + break; + case HDMI_3840x2160p50_16x9_Y420: + case HDMI_3840x2160p60_16x9_Y420: + case HDMI_4096x2160p50_256x135_Y420: + case HDMI_4096x2160p60_256x135_Y420: + if (hdev->para->cd == HDMI_COLOR_DEPTH_24B) + hdmitx_set_phypara(HDMI_PHYPARA_3G); + else + hdmitx_set_phypara(HDMI_PHYPARA_4p5G); + break; + case HDMI_3840x2160p24_16x9: + case HDMI_3840x2160p24_64x27: + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p25_64x27: + case HDMI_3840x2160p30_16x9: + case HDMI_3840x2160p30_64x27: + case HDMI_4096x2160p24_256x135: + case HDMI_4096x2160p25_256x135: + case HDMI_4096x2160p30_256x135: + if ((hdev->para->cs == HDMI_COLOR_FORMAT_422) + || (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) + hdmitx_set_phypara(HDMI_PHYPARA_3G); + else + hdmitx_set_phypara(HDMI_PHYPARA_4p5G); + break; + case HDMI_1920x1080p60_16x9: + case HDMI_1920x1080p50_16x9: + case HDMI_1920x1080i100_16x9: + case HDMI_1920x1080i120_16x9: + case HDMI_1280x720p100_16x9: + case HDMI_1280x720p120_16x9: + hdmitx_set_phypara(HDMI_PHYPARA_DEF); + break; + default: + hdmitx_set_phypara(HDMI_PHYPARA_270M); + break; + } + debug("hdmitx phy setting done\n"); +} + +static void hdmitx_set_hw(struct hdmitx_dev* hdev) +{ + struct hdmi_format_para *para = NULL; + + para = hdmi_get_fmt_paras(hdev->vic); + if (para == NULL) { + printk("error at %s[%d]\n", __func__, __LINE__); + return; + } + hdmitx_set_pll(hdev); + hdmitx_enc(hdev->vic); + hdmitx_set_dith(hdev); + hdmitx_set_phy(hdev); + + /* --------------------------------------------------------*/ + /* Set up HDMI*/ + /* --------------------------------------------------------*/ + config_hdmi20_tx(hdev->vic, para, /*pixel_repeat*/ + hdev->para->cd, /*Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit.*/ + TX_INPUT_COLOR_FORMAT, /*input_color_format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/ + TX_INPUT_COLOR_RANGE, /*input_color_range: 0=limited; 1=full.*/ + hdev->para->cs, /*output_color_format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/ + TX_OUTPUT_COLOR_RANGE /*output_color_range: 0=limited; 1=full.*/ + ); + + /* switch HDMI_VIC for 2160p30/25/24hz */ + switch (hdev->vic) { + case HDMI_3840x2160p24_16x9: + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p30_16x9: + case HDMI_4096x2160p24_256x135: + hdmitx_set_vsi_pkt(hdev->vic); + break; + default: + break; + } + + /* Using ISA_DEBUG_REG0 to record HDMITX current format */ + save_hdmitx_format(hdev->vic, (hdev->para->cs == HDMI_COLOR_FORMAT_420)); + + hd_write_reg(P_VPU_HDMI_FMT_CTRL, + (((TX_INPUT_COLOR_FORMAT==HDMI_COLOR_FORMAT_420)?2:0) << 0) | + /*[ 1: 0] hdmi_vid_fmt. 0=444; 1=convert to 422; 2=convert to 420.*/ + (2 << 2) | /*[ 3: 2] chroma_dnsmp. 0=use pixel 0; 1=use pixel 1; 2=use average.*/ + (0 << 4) | /*[ 4] dith_en. 1=enable dithering before HDMI TX input.*/ + (0 << 5) | /*[ 5] hdmi_dith_md: random noise selector.*/ + (0 << 6)); /*[ 9: 6] hdmi_dith10_cntl.*/ + if (hdev->para->cs == HDMI_COLOR_FORMAT_420) { + hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 2, 0, 2); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 4, 4); + hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 1); + } + switch (hdev->vic) { + case HDMI_720x480i60_16x9: + case HDMI_720x576i50_16x9: + case HDMI_720x480i60_4x3: + case HDMI_720x576i50_4x3: + enc_vpu_bridge_reset(0); + break; + default: + enc_vpu_bridge_reset(1); + break; + } + + switch (hdev->vic) { + case HDMI_3840x2160p50_16x9: + case HDMI_3840x2160p60_16x9: + case HDMI_4096x2160p50_256x135: + case HDMI_4096x2160p60_256x135: + if ((hdev->para->cs == HDMI_COLOR_FORMAT_420) + && (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) + set_tmds_clk_div40(0); + else + set_tmds_clk_div40(1); + break; + case HDMI_3840x2160p50_16x9_Y420: + case HDMI_3840x2160p60_16x9_Y420: + case HDMI_4096x2160p50_256x135_Y420: + case HDMI_4096x2160p60_256x135_Y420: + if ((hdev->para->cs == HDMI_COLOR_FORMAT_420) + && (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) + set_tmds_clk_div40(0); + else + set_tmds_clk_div40(1); + break; + case HDMI_3840x2160p24_16x9: + case HDMI_3840x2160p24_64x27: + case HDMI_4096x2160p24_256x135: + case HDMI_3840x2160p25_16x9: + case HDMI_3840x2160p25_64x27: + case HDMI_4096x2160p25_256x135: + case HDMI_3840x2160p30_16x9: + case HDMI_3840x2160p30_64x27: + case HDMI_4096x2160p30_256x135: + case HDMI_1920x1080p100_16x9: + case HDMI_1920x1080p120_16x9: + if ((hdev->para->cs == HDMI_COLOR_FORMAT_422) + || (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) + set_tmds_clk_div40(0); + else + set_tmds_clk_div40(1); + break; + default: + set_tmds_clk_div40(0); + break; + } + hd_write_reg(P_ENCP_VIDEO_EN, 1); /* enable it finially */ +} + +/*Use this self-made function rather than %, + *because % appears to produce wrong + *value for divisor which are not 2's exponential. + */ +static unsigned long modulo(unsigned long a, unsigned long b) +{ + if (a >= b) { + return(a-b); + } else { + return(a); + } +} + +static signed int to_signed(unsigned int a) +{ + if (a <= 7) { + return(a); + } else { + return(a-16); + } +} + +static void hdmitx_csc_config (unsigned char input_color_format, + unsigned char output_color_format, + unsigned char color_depth) +{ + unsigned char conv_en; + unsigned long csc_coeff_a1, csc_coeff_a2, csc_coeff_a3, csc_coeff_a4; + unsigned long csc_coeff_b1, csc_coeff_b2, csc_coeff_b3, csc_coeff_b4; + unsigned long csc_coeff_c1, csc_coeff_c2, csc_coeff_c3, csc_coeff_c4; + unsigned char csc_scale; + unsigned long data32; + + conv_en = (((input_color_format == HDMI_COLOR_FORMAT_RGB) || + (output_color_format == HDMI_COLOR_FORMAT_RGB)) && + ( input_color_format != output_color_format))? 1 : 0; + + if (conv_en) { + if (output_color_format == HDMI_COLOR_FORMAT_RGB) { + csc_coeff_a1 = 0x2000; + csc_coeff_a2 = 0x6926; + csc_coeff_a3 = 0x74fd; + csc_coeff_a4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x010e : + (color_depth==HDMI_COLOR_DEPTH_30B)? 0x043b : + (color_depth==HDMI_COLOR_DEPTH_36B)? 0x10ee : + (color_depth==HDMI_COLOR_DEPTH_48B)? 0x10ee : 0x010e; + csc_coeff_b1 = 0x2000; + csc_coeff_b2 = 0x2cdd; + csc_coeff_b3 = 0x0000; + csc_coeff_b4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x7e9a : + (color_depth==HDMI_COLOR_DEPTH_30B)? 0x7a65 : + (color_depth==HDMI_COLOR_DEPTH_36B)? 0x6992 : + (color_depth==HDMI_COLOR_DEPTH_48B)? 0x6992 : 0x7e9a; + csc_coeff_c1 = 0x2000; + csc_coeff_c2 = 0x0000; + csc_coeff_c3 = 0x38b4; + csc_coeff_c4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x7e3b : + (color_depth==HDMI_COLOR_DEPTH_30B)? 0x78ea : + (color_depth==HDMI_COLOR_DEPTH_36B)? 0x63a6 : + (color_depth==HDMI_COLOR_DEPTH_48B)? 0x63a6 : 0x7e3b; + csc_scale = 1; + } else { /*input_color_format == HDMI_COLOR_FORMAT_RGB*/ + csc_coeff_a1 = 0x2591; + csc_coeff_a2 = 0x1322; + csc_coeff_a3 = 0x074b; + csc_coeff_a4 = 0x0000; + csc_coeff_b1 = 0x6535; + csc_coeff_b2 = 0x2000; + csc_coeff_b3 = 0x7acc; + csc_coeff_b4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x0200 : + (color_depth==HDMI_COLOR_DEPTH_30B)? 0x0800 : + (color_depth==HDMI_COLOR_DEPTH_36B)? 0x2000 : + (color_depth==HDMI_COLOR_DEPTH_48B)? 0x2000 : 0x0200; + csc_coeff_c1 = 0x6acd; + csc_coeff_c2 = 0x7534; + csc_coeff_c3 = 0x2000; + csc_coeff_c4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x0200 : + (color_depth==HDMI_COLOR_DEPTH_30B)? 0x0800 : + (color_depth==HDMI_COLOR_DEPTH_36B)? 0x2000 : + (color_depth==HDMI_COLOR_DEPTH_48B)? 0x2000 : 0x0200; + csc_scale = 0; + } + } else { + csc_coeff_a1 = 0x2000; + csc_coeff_a2 = 0x0000; + csc_coeff_a3 = 0x0000; + csc_coeff_a4 = 0x0000; + csc_coeff_b1 = 0x0000; + csc_coeff_b2 = 0x2000; + csc_coeff_b3 = 0x0000; + csc_coeff_b4 = 0x0000; + csc_coeff_c1 = 0x0000; + csc_coeff_c2 = 0x0000; + csc_coeff_c3 = 0x2000; + csc_coeff_c4 = 0x0000; + csc_scale = 1; + } + + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A1_MSB, (csc_coeff_a1>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A1_LSB, csc_coeff_a1&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A2_MSB, (csc_coeff_a2>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A2_LSB, csc_coeff_a2&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A3_MSB, (csc_coeff_a3>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A3_LSB, csc_coeff_a3&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A4_MSB, (csc_coeff_a4>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A4_LSB, csc_coeff_a4&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B1_MSB, (csc_coeff_b1>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B1_LSB, csc_coeff_b1&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B2_MSB, (csc_coeff_b2>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B2_LSB, csc_coeff_b2&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B3_MSB, (csc_coeff_b3>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B3_LSB, csc_coeff_b3&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B4_MSB, (csc_coeff_b4>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B4_LSB, csc_coeff_b4&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C1_MSB, (csc_coeff_c1>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C1_LSB, csc_coeff_c1&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C2_MSB, (csc_coeff_c2>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C2_LSB, csc_coeff_c2&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C3_MSB, (csc_coeff_c3>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C3_LSB, csc_coeff_c3&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C4_MSB, (csc_coeff_c4>>8)&0xff); + hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C4_LSB, csc_coeff_c4&0xff); + + data32 = 0; + data32 |= (color_depth << 4); /* [7:4] csc_color_depth*/ + data32 |= (csc_scale << 0); /* [1:0] cscscale*/ + hdmitx_wr_reg(HDMITX_DWC_CSC_SCALE, data32); +} /* hdmitx_csc_config */
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.h b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.h new file mode 100644 index 0000000..7708a9e --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.h
@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMITX_DRV_H__ +#define __HDMITX_DRV_H__ + +#include <amlogic/media/vout/hdmitx/hdmitx.h> +void set_vmode_enc_hw(enum hdmi_vic vic); + +#endif
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_policy.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_policy.c new file mode 100644 index 0000000..fc98375 --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_policy.c
@@ -0,0 +1,836 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <malloc.h> +#include <asm/byteorder.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> +#include <amlogic/media/dv/dolby_vision.h> +#include <asm/arch/cpu.h> +#include <amlogic/cpu_id.h> + +#define DV_MODE_720P50HZ "720p50hz" +#define DV_MODE_720P "720p60hz" +#define DV_MODE_1080P24HZ "1080p24hz" +#define DV_MODE_1080P50HZ "1080p50hz" +#define DV_MODE_1080P "1080p60hz" +#define DV_MODE_4K2K24HZ "2160p24hz" +#define DV_MODE_4K2K25HZ "2160p25hz" +#define DV_MODE_4K2K30HZ "2160p30hz" +#define DV_MODE_4K2K50HZ "2160p50hz" +#define DV_MODE_4K2K60HZ "2160p60hz" +#define DV_MODE_LIST_SIZE 10 + +#define MODE_480I "480i60hz" +#define MODE_480P "480p60hz" +#define MODE_480CVBS "480cvbs" +#define MODE_576I "576i50hz" +#define MODE_576P "576p50hz" +#define MODE_576CVBS "576cvbs" +#define MODE_720P50HZ "720p50hz" +#define MODE_720P "720p60hz" +#define MODE_768P "768p60hz" +#define MODE_1080P24HZ "1080p24hz" +#define MODE_1080I50HZ "1080i50hz" +#define MODE_1080P50HZ "1080p50hz" +#define MODE_1080I "1080i60hz" +#define MODE_1080P "1080p60hz" +#define MODE_4K2K24HZ "2160p24hz" +#define MODE_4K2K25HZ "2160p25hz" +#define MODE_4K2K30HZ "2160p30hz" +#define MODE_4K2K50HZ "2160p50hz" +#define MODE_4K2K60HZ "2160p60hz" +#define MODE_4K2KSMPTE "smpte24hz" +#define MODE_4K2KSMPTE30HZ "smpte30hz" +#define MODE_4K2KSMPTE50HZ "smpte50hz" +#define MODE_4K2KSMPTE60HZ "smpte60hz" +#define MODE_PANEL "panel" +#define MODE_PAL_M "pal_m" +#define MODE_PAL_N "pal_n" +#define MODE_NTSC_M "ntsc_m" + +#define DEFAULT_COLOR_FORMAT_4K "420,8bit" +#define DEFAULT_COLOR_FORMAT "444,8bit" + +#define DEFAULT_HDMI_MODE "480p60hz" + + +#define COLOR_YCBCR444_12BIT "444,12bit" +#define COLOR_YCBCR444_10BIT "444,10bit" +#define COLOR_YCBCR444_8BIT "444,8bit" +#define COLOR_YCBCR422_12BIT "422,12bit" +#define COLOR_YCBCR422_10BIT "422,10bit" +#define COLOR_YCBCR422_8BIT "422,8bit" +#define COLOR_YCBCR420_12BIT "420,12bit" +#define COLOR_YCBCR420_10BIT "420,10bit" +#define COLOR_YCBCR420_8BIT "420,8bit" +#define COLOR_RGB_12BIT "rgb,12bit" +#define COLOR_RGB_10BIT "rgb,10bit" +#define COLOR_RGB_8BIT "rgb,8bit" + +static const char *DISPLAY_MODE_LIST[] = { + MODE_480I, + MODE_480P, + /* MODE_480CVBS, */ + MODE_576I, + MODE_576P, + /* MODE_576CVBS, */ + MODE_720P, + MODE_720P50HZ, + MODE_1080P24HZ, + MODE_1080I50HZ, + MODE_1080P50HZ, + MODE_1080I, + MODE_1080P, + MODE_4K2K24HZ, + MODE_4K2K25HZ, + MODE_4K2K30HZ, + MODE_4K2K50HZ, + MODE_4K2K60HZ, + MODE_4K2KSMPTE, + MODE_4K2KSMPTE30HZ, + MODE_4K2KSMPTE50HZ, + MODE_4K2KSMPTE60HZ + /* MODE_768P, */ + /* MODE_PANEL, */ + /* MODE_PAL_M, */ + /* MODE_PAL_N, */ + /* MODE_NTSC_M, */ +}; + +static const char *MODE_RESOLUTION_FIRST[] = { + MODE_480I, + MODE_576I, + MODE_480P, + MODE_576P, + MODE_720P50HZ, + MODE_720P, + MODE_1080I50HZ, + MODE_1080I, + MODE_1080P50HZ, + MODE_1080P, + MODE_4K2K24HZ, + MODE_4K2K25HZ, + MODE_4K2K30HZ, + MODE_4K2K50HZ, + MODE_4K2K60HZ +}; + +static const char *MODE_FRAMERATE_FIRST[] = { + MODE_480I, + MODE_576I, + MODE_480P, + MODE_576P, + MODE_720P50HZ, + MODE_720P, + MODE_1080I50HZ, + MODE_1080I, + MODE_4K2K24HZ, + MODE_4K2K25HZ, + MODE_4K2K30HZ, + MODE_1080P50HZ, + MODE_1080P, + MODE_4K2K50HZ, + MODE_4K2K60HZ +}; + +/* this is prior selected list of + * 4k2k50hz, 4k2k60hz smpte50hz, smpte60hz + */ +static const char *COLOR_ATTRIBUTE_LIST1[] = { + COLOR_YCBCR420_10BIT, + COLOR_YCBCR422_12BIT, + COLOR_YCBCR420_8BIT, + COLOR_YCBCR444_8BIT, + COLOR_RGB_8BIT +}; + +/* this is prior selected list of other display mode */ +static const char *COLOR_ATTRIBUTE_LIST2[] = { + COLOR_YCBCR444_10BIT, + COLOR_YCBCR422_12BIT, + COLOR_RGB_10BIT, + COLOR_YCBCR444_8BIT, + COLOR_RGB_8BIT +}; + +/* this is prior selected list of Low Power Mode + * 4k2k50hz, 4k2k60hz smpte50hz, smpte60hz + */ +static const char *COLOR_ATTRIBUTE_LIST3[] = { + COLOR_YCBCR420_8BIT, + COLOR_YCBCR420_10BIT, + COLOR_YCBCR422_8BIT, + COLOR_YCBCR422_10BIT, + COLOR_YCBCR444_8BIT, + COLOR_RGB_8BIT, + COLOR_YCBCR420_12BIT, + COLOR_YCBCR422_12BIT +}; + +/* this is prior selected list of + * Low Power Mode other display mode + */ +static const char *COLOR_ATTRIBUTE_LIST4[] = { + COLOR_YCBCR444_8BIT, + COLOR_YCBCR422_8BIT, + COLOR_RGB_8BIT, + COLOR_YCBCR444_10BIT, + COLOR_YCBCR422_10BIT, + COLOR_RGB_10BIT, + COLOR_YCBCR444_12BIT, + COLOR_YCBCR422_12BIT, + COLOR_RGB_12BIT +}; + +/* support format lists */ +static const char *disp_mode_t[] = { + "480i60hz", /* 16:9 */ + "576i50hz", + "480p60hz", + "576p50hz", + "720p60hz", + "1080i60hz", + "1080p60hz", + "1080p120hz", + "720p50hz", + "1080i50hz", + "1080p30hz", + "1080p50hz", + "1080p25hz", + "1080p24hz", + "2560x1080p50hz", + "2560x1080p60hz", + "2160p30hz", + "2160p25hz", + "2160p24hz", + "smpte24hz", + "smpte25hz", + "smpte30hz", + "smpte50hz", + "smpte60hz", + "2160p50hz", + "2160p60hz", + /* VESA modes */ + "640x480p60hz", + "800x480p60hz", + "800x600p60hz", + "852x480p60hz", + "854x480p60hz", + "1024x600p60hz", + "1024x768p60hz", + "1152x864p75hz", + "1280x600p60hz", + "1280x768p60hz", + "1280x800p60hz", + "1280x960p60hz", + "1280x1024p60hz", + "1360x768p60hz", + "1366x768p60hz", + "1400x1050p60hz", + "1440x900p60hz", + "1440x2560p60hz", + "1600x900p60hz", + "1600x1200p60hz", + "1680x1050p60hz", + "1920x1200p60hz", + "2160x1200p90hz", + "2560x1080p60hz", + "2560x1440p60hz", + "2560x1600p60hz", + "3440x1440p60hz", + "2400x1200p90hz", + NULL +}; + +static bool is_best_outputmode(void) +{ + char *is_bestmode = env_get("is.bestmode"); + + return !is_bestmode || (strcmp(is_bestmode, "true") == 0); +} + +static bool is_framerate_priority(void) +{ + char *framerate_priority = env_get("framerate_priority"); + + return !framerate_priority || (strcmp(framerate_priority, "true") == 0); +} + +/* import from kernel */ +static inline bool package_id_is(unsigned int id) +{ + return get_cpu_id().package_id == id; +} + +static inline bool is_meson_gxl_cpu(void) +{ + return get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL; +} + +static inline bool is_meson_gxl_package_805X(void) +{ + return is_meson_gxl_cpu() && package_id_is(0x30); +} + +static inline bool is_meson_gxl_package_805Y(void) +{ + return is_meson_gxl_cpu() && package_id_is(0xb0); +} + +/* below items has feature limited, may need extra judgement */ +static bool hdmitx_limited_1080p(void) +{ + if (is_meson_gxl_package_805X()) + return true; + else if (is_meson_gxl_package_805Y()) + return true; + else + return false; +} + +static bool is_support_4k(void) +{ + if (hdmitx_limited_1080p()) + return false; + return true; +} + +static bool is_support_4k30hz(void) +{ + return is_support_4k(); +} + +static bool is_support_deepcolor(void) +{ + return true; +} + +static bool is_low_powermode(void) +{ + return false; +} + +static int is_4k50_fmt(char *mode) +{ + int i; + static char const *hdmi4k50[] = { + "2160p50hz", + "2160p60hz", + "smpte50hz", + "smpte60hz", + NULL + }; + + for (i = 0; hdmi4k50[i]; i++) { + if (strcmp(hdmi4k50[i], mode) == 0) + return 1; + } + return 0; +} + +static int is_4k_fmt(char *mode) +{ + int i; + static char const *hdmi4k[] = { + "2160p", + "smpte", + NULL + }; + + for (i = 0; hdmi4k[i]; i++) { + if (strstr(mode, hdmi4k[i])) + return 1; + } + return 0; +} + +bool is_tv_support_dv(struct hdmitx_dev *hdev) +{ + /*todo*/ + struct dv_info *dv; + char *hdr_priority = env_get("hdr_priority"); + + if (!hdev) + return false; + dv = &(hdev->RXCap.dv_info); + if (hdr_priority && (strcmp(hdr_priority, "1") == 0)) + return false; + if ((dv->ieeeoui != DV_IEEE_OUI) || (dv->block_flag != CORRECT)) + return false; + return true; +} + +int get_ubootenv_dv_type(void) +{ + char *dolby_status = NULL; + + dolby_status = env_get("dolby_status"); + + if (!dolby_status) { + printf("no ubootenv dolby_status\n"); + return DOLBY_VISION_DISABLE; + } + if (!strcmp(dolby_status, DOLBY_VISION_SET_STD)) + return DOLBY_VISION_STD_ENABLE; + else if (!strcmp(dolby_status, DOLBY_VISION_SET_LL_YUV)) + return DOLBY_VISION_LL_YUV; + else if (!strcmp(dolby_status, DOLBY_VISION_SET_LL_RGB)) + return DOLBY_VISION_LL_RGB; + else + return DOLBY_VISION_DISABLE; +} + +bool is_dolby_enabled(void) +{ + if (get_ubootenv_dv_type() != DOLBY_VISION_DISABLE) + return true; + else + return false; +} + +static int resolve_resolution_value(const char *mode) +{ + bool validmode = false; + int i; + + if (!mode) + return -1; + + if (strlen(mode) != 0) { + for (i = 0; i < ARRAY_SIZE(DISPLAY_MODE_LIST); i++) { + if (strcmp(mode, DISPLAY_MODE_LIST[i]) == 0) { + validmode = true; + break; + } + } + } + if (!validmode) { + printf("the resolveResolution mode [%s] is not valid\n", mode); + return -1; + } + + if (is_framerate_priority()) { + for (i = 0; i < ARRAY_SIZE(MODE_FRAMERATE_FIRST); i++) { + if (strcmp(mode, MODE_FRAMERATE_FIRST[i]) == 0) + return i; + } + } else { + for (i = 0; i < ARRAY_SIZE(MODE_RESOLUTION_FIRST); i++) { + if (strcmp(mode, MODE_RESOLUTION_FIRST[i]) == 0) + return i; + } + } + + return -1; +} + +/* need update DV CAP */ +static int update_dv_type(hdmi_data_t *hdmi_data) +{ + /* 1.read dolby vision mode from prop(env) */ + int type; + struct dv_info *dv = NULL; + + if (!hdmi_data) + return DOLBY_VISION_DISABLE; + + type = hdmi_data->ubootenv_dv_type; + dv = &(hdmi_data->pRXCap->dv_info); + + /* 2.check tv support or not */ + if ((type == 1) && (dv->support_DV_RGB_444_8BIT == 1)) { + return DOLBY_VISION_STD_ENABLE; + } else if ((type == 2) && (dv->support_LL_YCbCr_422_12BIT == 1)) { + return DOLBY_VISION_LL_YUV; + } else if ((type == 3) && + ((dv->support_LL_RGB_444_10BIT == 1) || + (dv->support_LL_RGB_444_12BIT == 1))) { + return DOLBY_VISION_LL_RGB; + } else if (type == 0) { + return DOLBY_VISION_DISABLE; + } + + /* 3.dolby vision best policy: + * STD->LL_YUV->LL_RGB for netflix request + * LL_YUV->STD->LL_RGB for dolby vision request + */ + printf("NOTE: DV type is changed!\n"); + if ((dv->support_DV_RGB_444_8BIT == 1) || + (dv->support_LL_YCbCr_422_12BIT == 1)) { + if (dv->support_DV_RGB_444_8BIT == 1) + return DOLBY_VISION_STD_ENABLE; + else if (dv->support_LL_YCbCr_422_12BIT == 1) + return DOLBY_VISION_LL_YUV; + } else if ((dv->support_LL_RGB_444_10BIT == 1) || + (dv->support_LL_RGB_444_12BIT == 1)) { + return DOLBY_VISION_LL_RGB; + } + + return DOLBY_VISION_DISABLE; +} + +static void update_dv_attr(hdmi_data_t *hdmi_data, char *dv_attr) +{ + int dv_type; + struct dv_info *dv = NULL; + if (!hdmi_data || !dv_attr) + return; + + dv_type = hdmi_data->ubootenv_dv_type; + dv = &(hdmi_data->pRXCap->dv_info); + + switch (dv_type) { + case DOLBY_VISION_STD_ENABLE: + strcpy(dv_attr, "444,8bit"); + break; + case DOLBY_VISION_LL_YUV: + strcpy(dv_attr, "422,12bit"); + break; + case DOLBY_VISION_LL_RGB: + if (dv->support_LL_RGB_444_12BIT == 1) + strcpy(dv_attr, "444,12bit"); + else if (dv->support_LL_RGB_444_10BIT == 1) + strcpy(dv_attr, "444,10bit"); + + break; + default: + strcpy(dv_attr, "444,8bit"); + break; + } + + printf("dv_type :%d dv_attr:%s", dv_type, dv_attr); +} + +static void update_dv_displaymode(hdmi_data_t *hdmi_data, + char *final_displaymode) +{ + char dv_displaymode[MODE_LEN] = {0}; + char cur_outputmode[MODE_LEN] = {0}; + int dv_type; + struct dv_info *dv = NULL; + + if (!hdmi_data || !final_displaymode) + return; + dv_type = hdmi_data->ubootenv_dv_type; + strcpy(cur_outputmode, hdmi_data->ubootenv_hdmimode); + dv = &(hdmi_data->pRXCap->dv_info); + if (dv->sup_2160p60hz == 1) + strcpy(dv_displaymode, DV_MODE_4K2K60HZ); + else + strcpy(dv_displaymode, DV_MODE_4K2K30HZ); + if (is_best_outputmode()) { + if (!strcmp(dv_displaymode, DV_MODE_4K2K60HZ)) { + if (dv_type == DOLBY_VISION_LL_RGB) + strcpy(final_displaymode, DV_MODE_1080P); + else + strcpy(final_displaymode, DV_MODE_4K2K60HZ); + } else { + if (!strcmp(dv_displaymode, DV_MODE_4K2K30HZ) || + !strcmp(dv_displaymode, DV_MODE_4K2K25HZ) || + !strcmp(dv_displaymode, DV_MODE_4K2K24HZ)) + strcpy(final_displaymode, DV_MODE_1080P); + else + strcpy(final_displaymode, dv_displaymode); + } + } else { + /* if current disp_mode is outside of maximum dv disp_mode */ + if ((resolve_resolution_value(cur_outputmode) > + resolve_resolution_value(dv_displaymode)) || + (strstr(cur_outputmode, "smpte") != NULL) || + (strstr(cur_outputmode, "i") != NULL)) + strcpy(final_displaymode, dv_displaymode); + else + strcpy(final_displaymode, cur_outputmode); + } + + printf("final_displaymode:%s, cur_outputmode:%s, dv_displaymode:%s", + final_displaymode, cur_outputmode, dv_displaymode); +} + +/* get the highest hdmi mode by edid */ +static void get_highest_hdmimode(hdmi_data_t *hdmi_data, char *mode) +{ + char value[MODE_LEN] = {0}; + char mode_tmp[MODE_LEN]; + enum hdmi_vic vic; + int i; + struct hdmitx_dev *hdev = NULL; + + if (!hdmi_data || !mode) + return; + hdev = container_of(hdmi_data->pRXCap, + struct hdmitx_dev, RXCap); + + strcpy(value, DEFAULT_HDMI_MODE); + + for (i = 0; disp_mode_t[i]; i++) { + memset(mode_tmp, 0, sizeof(mode_tmp)); + strncpy(mode_tmp, disp_mode_t[i], MODE_LEN - 1); + if (!is_support_4k() && is_4k_fmt(mode_tmp)) { + printf("This platform not support : %s\n", mode_tmp); + continue; + } + /* refer to disp_cap sysfs */ + vic = hdmitx_edid_get_VIC(hdev, mode_tmp, 0); + /* Handling only 4k420 mode */ + if (vic == HDMI_unkown) { + if (is_4k50_fmt(mode_tmp)) { + strcat(mode_tmp, "420"); + vic = hdmitx_edid_get_VIC(hdev, + mode_tmp, 0); + } + if (vic == HDMI_unkown) + continue; + } + if (!is_support_4k30hz() && + ((resolve_resolution_value(mode_tmp) > + resolve_resolution_value("2160p30hz")) || + strstr(mode_tmp, "smpte"))) { + printf("This platform not support the mode over 2160p30hz\n"); + continue; + } + if (resolve_resolution_value(mode_tmp) > + resolve_resolution_value(value)) { + memset(value, 0, MODE_LEN); + strcpy(value, mode_tmp); + } + } + + strcpy(mode, value); + printf("set HDMI to highest edid mode: %s\n", mode); +} + +/* check if the edid support current hdmi mode */ +static void filter_hdmimode(hdmi_data_t *hdmi_data, char *mode) +{ + struct hdmitx_dev *hdev = NULL; + + if (!hdmi_data || !mode) + return; + hdev = container_of(hdmi_data->pRXCap, + struct hdmitx_dev, RXCap); + + if (hdmitx_edid_get_VIC(hdev, hdmi_data->ubootenv_hdmimode, 0) + != HDMI_unkown) { + strcpy(mode, hdmi_data->ubootenv_hdmimode); + } else { + /* old mode is not support in this TV, + * so switch to best mode. + */ + get_highest_hdmimode(hdmi_data, mode); + } +} + +static void get_hdmi_outputmode(hdmi_data_t *hdmi_data, char *mode) +{ + struct hdmitx_dev *hdev = NULL; + + if (!hdmi_data || !mode) + return; + + hdev = container_of(hdmi_data->pRXCap, + struct hdmitx_dev, RXCap); + + /* Fall back to 480p if EDID can't be parsed */ + if (!edid_parsing_ok(hdev)) { + strcpy(mode, DEFAULT_HDMI_MODE); + printf("EDID parsing error detected\n"); + return; + } + + if (is_best_outputmode()) + get_highest_hdmimode(hdmi_data, mode); + else + filter_hdmimode(hdmi_data, mode); + printf("set HDMI mode to %s\n", mode); +} + +static void get_best_color_attr(hdmi_data_t *hdmi_data, + const char *outputmode, char *colorattribute) +{ + int length = 0; + const char **color_list = NULL; + char temp_mode[MODE_LEN] = {0}; + int i; + + if (!hdmi_data || !outputmode || !colorattribute) + return; + + /* filter some color value options, aimed at some modes. */ + if (!strcmp(outputmode, MODE_4K2K60HZ) || + !strcmp(outputmode, MODE_4K2K50HZ) || + !strcmp(outputmode, MODE_4K2KSMPTE60HZ) || + !strcmp(outputmode, MODE_4K2KSMPTE50HZ)) { + if (is_low_powermode()) { + color_list = COLOR_ATTRIBUTE_LIST3; + length = ARRAY_SIZE(COLOR_ATTRIBUTE_LIST3); + } else { + color_list = COLOR_ATTRIBUTE_LIST1; + length = ARRAY_SIZE(COLOR_ATTRIBUTE_LIST1); + } + } else { + if (is_low_powermode()) { + color_list = COLOR_ATTRIBUTE_LIST4; + length = ARRAY_SIZE(COLOR_ATTRIBUTE_LIST4); + } else { + color_list = COLOR_ATTRIBUTE_LIST2; + length = ARRAY_SIZE(COLOR_ATTRIBUTE_LIST2); + } + } + + for (i = 0; i < length; i++) { + strcpy(temp_mode, outputmode); + strcat(temp_mode, color_list[i]); + if (is_supported_mode_attr(hdmi_data, temp_mode)) { + printf("support current mode:[%s], deep color:[%s]\n", + outputmode, color_list[i]); + strcpy(colorattribute, color_list[i]); + break; + } + } +} + +static void get_hdmi_colorattribute(hdmi_data_t *hdmi_data, + const char *outputmode, char *colorattribute) +{ + char temp_mode[MODE_LEN] = {0}; + + if (!hdmi_data || !outputmode || !colorattribute) + return; + /* if dc_cap is null, use default color format */ + /* should never encounter this case */ + if (false) { + if (!strcmp(outputmode, MODE_4K2K60HZ) || + !strcmp(outputmode, MODE_4K2K50HZ) || + !strcmp(outputmode, MODE_4K2KSMPTE60HZ) || + !strcmp(outputmode, MODE_4K2KSMPTE50HZ)) { + strcpy(colorattribute, DEFAULT_COLOR_FORMAT_4K); + } else { + strcpy(colorattribute, DEFAULT_COLOR_FORMAT); + } + + printf("Do not find sink color list, use default color attribute:%s\n", + colorattribute); + return; + } + + /* if bestpolicy is disabled, use ubootenv.var.colorattribute */ + if (!is_best_outputmode()) { + strcpy(temp_mode, hdmi_data->ubootenv_hdmimode); + strcat(temp_mode, hdmi_data->ubootenv_colorattribute); + if (is_supported_mode_attr(hdmi_data, temp_mode)) + strcpy(colorattribute, + hdmi_data->ubootenv_colorattribute); + else + get_best_color_attr(hdmi_data, outputmode, + colorattribute); + } else { + get_best_color_attr(hdmi_data, outputmode, colorattribute); + } + + /* if colorAttr is null above steps, + * will defines a initial value + */ + if (!strstr(colorattribute, "bit")) + strcpy(colorattribute, DEFAULT_COLOR_FORMAT); + + printf("get hdmi color attribute: [%s], outputmode is: [%s]\n", + colorattribute, outputmode); +} + +static void update_hdmi_deepcolor(hdmi_data_t *hdmi_data, + const char *outputmode, char *colorattribute) +{ + if (!hdmi_data || !outputmode || !colorattribute) + return; + if (is_support_deepcolor()) + get_hdmi_colorattribute(hdmi_data, outputmode, colorattribute); + else + strcpy(colorattribute, "default"); + + printf("colorattribute = %s\n", colorattribute); +} + +void dolbyvision_scene_process(hdmi_data_t *hdmi_data, + scene_output_info_t *output_info) +{ + int dv_type = DOLBY_VISION_DISABLE; + + if (!hdmi_data || !output_info) + return; + /* 1.update dolby vision output type */ + dv_type = update_dv_type(hdmi_data); + output_info->final_dv_type = dv_type; + printf("dv final_type:%d\n", output_info->final_dv_type); + + /* update param */ + hdmi_data->ubootenv_dv_type = dv_type; + /* 2. update dolby vision output output mode and colorspace */ + /* 2.1 update dolby vision deepcolor */ + update_dv_attr(hdmi_data, output_info->final_deepcolor); + printf("dv final_deepcolor:%s\n", output_info->final_deepcolor); + + /* 2.2 update dolby vision output mode */ + update_dv_displaymode(hdmi_data, output_info->final_displaymode); + printf("dv final_displaymode:%s", output_info->final_displaymode); +} + +/* currently, SDR/HDR share the same policy process */ +void sdr_scene_process(hdmi_data_t *hdmi_data, scene_output_info_t *output_info) +{ + char outputmode[MODE_LEN] = {0}; + char colorattribute[MODE_LEN] = {0}; + + if (!hdmi_data || !output_info) + return; + /* 1.choose resolution, frame rate */ + get_hdmi_outputmode(hdmi_data, outputmode); + if (strlen(outputmode) == 0) + strcpy(outputmode, DEFAULT_HDMI_MODE); + strcpy(output_info->final_displaymode, outputmode); + printf("sdr final_displaymode:%s\n", + output_info->final_displaymode); + + /* 2.choose color format, bit-depth */ + update_hdmi_deepcolor(hdmi_data, outputmode, colorattribute); + strcpy(output_info->final_deepcolor, colorattribute); + printf("sdr final_deepcolor:%s\n", output_info->final_deepcolor); +} + +void get_hdmi_data(struct hdmitx_dev *hdev, hdmi_data_t *data) +{ + char *hdmimode; + char *colorattribute; + + if (!hdev || !data) + return; + + hdmimode = env_get("hdmimode"); + colorattribute = env_get("colorattribute"); + + strcpy(data->ubootenv_hdmimode, hdmimode); + strcpy(data->ubootenv_colorattribute, colorattribute); + data->ubootenv_dv_type = get_ubootenv_dv_type(); + #if 0 + data->isbestpolicy = is_best_outputmode(); + data->isSupport4K30Hz = is_support_4k30hz(); + data->isSupport4K = is_support_4k(); + data->isDeepColor = is_support_deepcolor(); + data->isLowPowerMode = is_low_powermode(); + data->isframeratepriority = is_framerate_priority(); + #endif + data->pRXCap = &(hdev->RXCap); + /* memcpy(&(data->pRXCap), &(hdev->RXCap), sizeof(hdev->RXCap)); */ + printf("ubootenv hdmimode: %s, cscd: %s, dv_type: %d\n", + data->ubootenv_hdmimode, + data->ubootenv_colorattribute, + data->ubootenv_dv_type); + printf("ubootenv best_output: %d, framerate_priority: %d\n", + is_best_outputmode(), + is_framerate_priority()); +}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_tvenc.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_tvenc.c new file mode 100644 index 0000000..8359125 --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_tvenc.c
@@ -0,0 +1,1399 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <amlogic/media/vout/hdmitx/hdmitx.h> +#include "hdmitx_drv.h" + +#define MREG_END_MARKER 0xFFFF + +static const struct reg_s tvregs_720p[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + + {P_VENC_DVI_SETTING, 0x2029}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_YFP1_HTIME, 648}, + {P_ENCP_VIDEO_YFP2_HTIME, 3207}, + {P_ENCP_VIDEO_MAX_PXCNT, 1649}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 80}, + {P_ENCP_VIDEO_HSPULS_END, 240}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 80}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 688}, + {P_ENCP_VIDEO_VSPULS_END, 3248}, + {P_ENCP_VIDEO_VSPULS_BLINE, 4}, + {P_ENCP_VIDEO_VSPULS_ELINE, 8}, + {P_ENCP_VIDEO_HAVON_BEGIN, 260}, + {P_ENCP_VIDEO_HAVON_END, 1539}, + {P_ENCP_VIDEO_VAVON_BLINE, 29}, + {P_ENCP_VIDEO_VAVON_ELINE, 749}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 168}, + {P_ENCP_VIDEO_VSO_BEGIN, 168}, + {P_ENCP_VIDEO_VSO_END, 256}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_MAX_LNCNT, 749}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_720p_50hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0x202d}, + {P_ENCP_VIDEO_MAX_PXCNT, 1979}, + {P_ENCP_VIDEO_MAX_LNCNT, 749}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 80}, + {P_ENCP_VIDEO_HSPULS_END, 240}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 80}, + {P_ENCP_VIDEO_HAVON_BEGIN, 260}, + {P_ENCP_VIDEO_HAVON_END, 1539}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 40}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 688}, + {P_ENCP_VIDEO_VSPULS_END, 3248}, + {P_ENCP_VIDEO_VSPULS_BLINE, 4}, + {P_ENCP_VIDEO_VSPULS_ELINE, 8}, + {P_ENCP_VIDEO_VAVON_BLINE, 25}, + {P_ENCP_VIDEO_VAVON_ELINE, 744}, + {P_ENCP_VIDEO_VSO_BEGIN, 30}, + {P_ENCP_VIDEO_VSO_END, 50}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 648}, + {P_ENCP_VIDEO_YFP2_HTIME, 3207}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x407}, + {P_ENCP_VIDEO_YC_DLY, 0}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_480i[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCI_CFILT_CTRL, 0x12}, + {P_ENCI_CFILT_CTRL2, 0x12}, + {P_VENC_DVI_SETTING, 0}, + {P_ENCI_VIDEO_MODE, 0}, + {P_ENCI_VIDEO_MODE_ADV, 0}, + {P_ENCI_SYNC_HSO_BEGIN, 5}, + {P_ENCI_SYNC_HSO_END, 129}, + {P_ENCI_SYNC_VSO_EVNLN, 0x0003}, + {P_ENCI_SYNC_VSO_ODDLN, 0x0104}, + {P_ENCI_MACV_MAX_AMP, 0x810b}, + {P_VENC_VIDEO_PROG_MODE, 0xf0}, + {P_ENCI_VIDEO_MODE, 0x08}, + {P_ENCI_VIDEO_MODE_ADV, 0x26}, + {P_ENCI_VIDEO_SCH, 0x20}, + {P_ENCI_SYNC_MODE, 0x07}, + {P_ENCI_DBG_PX_RST, 0}, + {P_ENCI_VFIFO2VD_CTL, 0x4e01}, + {P_ENCI_VFIFO2VD_PIXEL_START, 0xf3,}, + {P_ENCI_VFIFO2VD_PIXEL_END, 0x0693,}, + {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x12,}, + {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, + {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, + {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, + {P_ENCI_VIDEO_EN, 1}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_480p[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_FILT_CTRL, 0x2052}, + {P_VENC_DVI_SETTING, 0x21}, + {P_ENCP_VIDEO_MODE, 0x4000}, + {P_ENCP_VIDEO_MODE_ADV, 8}, + {P_ENCP_VIDEO_YFP1_HTIME, 244}, + {P_ENCP_VIDEO_YFP2_HTIME, 1630}, + {P_ENCP_VIDEO_MAX_PXCNT, 857}, + {P_ENCP_VIDEO_MAX_LNCNT, 524}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 0x22}, + {P_ENCP_VIDEO_HSPULS_END, 0xa0}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 88}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 0}, + {P_ENCP_VIDEO_VSPULS_END, 1589}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 5}, + {P_ENCP_VIDEO_HAVON_BEGIN, 122}, + {P_ENCP_VIDEO_HAVON_END, 841}, + {P_ENCP_VIDEO_VAVON_BLINE, 36}, + {P_ENCP_VIDEO_VAVON_ELINE, 515}, + {P_ENCP_VIDEO_SYNC_MODE, 0x07}, + {P_VENC_VIDEO_PROG_MODE, 0x0}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 62}, + {P_ENCP_VIDEO_VSO_BEGIN, 30}, + {P_ENCP_VIDEO_VSO_END, 50}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 6}, + {P_ENCP_VIDEO_SY_VAL, 8}, + {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, + {P_ENCP_DACSEL_0, 0x3102}, + {P_ENCP_DACSEL_1, 0x0054}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_576i[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0}, + {P_ENCI_VIDEO_MODE, 0}, + {P_ENCI_VIDEO_MODE_ADV, 0}, + {P_ENCI_SYNC_HSO_BEGIN, 3}, + {P_ENCI_SYNC_HSO_END, 129}, + {P_ENCI_SYNC_VSO_EVNLN, 0x0003}, + {P_ENCI_SYNC_VSO_ODDLN, 0x0104}, + {P_ENCI_MACV_MAX_AMP, 0x8107}, + {P_VENC_VIDEO_PROG_MODE, 0xff}, + {P_ENCI_VIDEO_MODE, 0x13}, + {P_ENCI_VIDEO_MODE_ADV, 0x26}, + {P_ENCI_VIDEO_SCH, 0x28}, + {P_ENCI_SYNC_MODE, 0x07}, + {P_ENCI_YC_DELAY, 0x333}, + {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b}, + {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab}, + {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016}, + {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, + {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, + {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, + {P_ENCI_DBG_PX_RST, 0}, + {P_ENCI_VFIFO2VD_CTL, 0x4e01}, + {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b}, + {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab}, + {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016}, + {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, + {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, + {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, + {P_ENCI_VIDEO_EN, 1}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_576p[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_FILT_CTRL, 0x52}, + {P_VENC_DVI_SETTING, 0x21}, + {P_ENCP_VIDEO_MODE, 0x4000}, + {P_ENCP_VIDEO_MODE_ADV, 8}, + {P_ENCP_VIDEO_YFP1_HTIME, 235}, + {P_ENCP_VIDEO_YFP2_HTIME, 1674}, + {P_ENCP_VIDEO_MAX_PXCNT, 863}, + {P_ENCP_VIDEO_MAX_LNCNT, 624}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 0}, + {P_ENCP_VIDEO_HSPULS_END, 0x80}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 88}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 0}, + {P_ENCP_VIDEO_VSPULS_END, 1599}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_HAVON_BEGIN, 132}, + {P_ENCP_VIDEO_HAVON_END, 851}, + {P_ENCP_VIDEO_VAVON_BLINE, 44}, + {P_ENCP_VIDEO_VAVON_ELINE, 619}, + {P_ENCP_VIDEO_SYNC_MODE, 0x07}, + {P_VENC_VIDEO_PROG_MODE, 0x0}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 64}, + {P_ENCP_VIDEO_VSO_BEGIN, 30}, + {P_ENCP_VIDEO_VSO_END, 50}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_BLINE, 5}, + {P_ENCP_VIDEO_SY_VAL, 8}, + {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_1080i[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0x2029}, + {P_ENCP_VIDEO_MAX_PXCNT, 2199}, + {P_ENCP_VIDEO_MAX_LNCNT, 1124}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 88}, + {P_ENCP_VIDEO_HSPULS_END, 264}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 88}, + {P_ENCP_VIDEO_HAVON_BEGIN, 192}, + {P_ENCP_VIDEO_HAVON_END, 2111}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 44}, + {P_ENCP_VIDEO_EQPULS_BEGIN, 2288}, + {P_ENCP_VIDEO_EQPULS_END, 2464}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 440}, + {P_ENCP_VIDEO_VSPULS_END, 2200}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_EQPULS_BLINE, 0}, + {P_ENCP_VIDEO_EQPULS_ELINE, 4}, + {P_ENCP_VIDEO_VAVON_BLINE, 20}, + {P_ENCP_VIDEO_VAVON_ELINE, 559}, + {P_ENCP_VIDEO_VSO_BEGIN, 30}, + {P_ENCP_VIDEO_VSO_END, 50}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 516}, + {P_ENCP_VIDEO_YFP2_HTIME, 4355}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11}, + {P_ENCP_VIDEO_MODE, 0x5ffc}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x207}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_1080i_50hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0x202d}, + {P_ENCP_VIDEO_MAX_PXCNT, 2639}, + {P_ENCP_VIDEO_MAX_LNCNT, 1124}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 88}, + {P_ENCP_VIDEO_HSPULS_END, 264}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 88}, + {P_ENCP_VIDEO_HAVON_BEGIN, 192}, + {P_ENCP_VIDEO_HAVON_END, 2111}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 440}, + {P_ENCP_VIDEO_VSPULS_END, 2200}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_VAVON_BLINE, 20}, + {P_ENCP_VIDEO_VAVON_ELINE, 559}, + {P_ENCP_VIDEO_VSO_BEGIN, 30}, + {P_ENCP_VIDEO_VSO_END, 50}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 526}, + {P_ENCP_VIDEO_YFP2_HTIME, 4365}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11}, + {P_ENCP_VIDEO_MODE, 0x5ffc}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x7}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_1080p[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_FILT_CTRL, 0x1052}, + {P_VENC_DVI_SETTING, 0x0001}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_YFP1_HTIME, 140}, + {P_ENCP_VIDEO_YFP2_HTIME, 2060}, + {P_ENCP_VIDEO_MAX_PXCNT, 2199}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 2156}, + {P_ENCP_VIDEO_HSPULS_END, 44}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, + {P_ENCP_VIDEO_VSPULS_END, 2059}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_HAVON_BEGIN, 148}, + {P_ENCP_VIDEO_HAVON_END, 2067}, + {P_ENCP_VIDEO_VAVON_BLINE, 42}, + {P_ENCP_VIDEO_VAVON_ELINE, 1121}, + {P_ENCP_VIDEO_HSO_BEGIN, 44}, + {P_ENCP_VIDEO_HSO_END, 2156}, + {P_ENCP_VIDEO_VSO_BEGIN, 2100}, + {P_ENCP_VIDEO_VSO_END, 2164}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_MAX_LNCNT, 1124}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_1080p_50hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0x000d}, + {P_ENCP_VIDEO_MAX_PXCNT, 2639}, + {P_ENCP_VIDEO_MAX_LNCNT, 1124}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 44}, + {P_ENCP_VIDEO_HSPULS_END, 132}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_HAVON_BEGIN, 271}, + {P_ENCP_VIDEO_HAVON_END, 2190}, + {P_ENCP_VIDEO_HSO_BEGIN, 79}, + {P_ENCP_VIDEO_HSO_END, 123}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 220}, + {P_ENCP_VIDEO_VSPULS_END, 2140}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_EQPULS_BLINE, 0}, + {P_ENCP_VIDEO_EQPULS_ELINE, 4}, + {P_ENCP_VIDEO_VAVON_BLINE, 41}, + {P_ENCP_VIDEO_VAVON_ELINE, 1120}, + {P_ENCP_VIDEO_VSO_BEGIN, 79}, + {P_ENCP_VIDEO_VSO_END, 79}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 271}, + {P_ENCP_VIDEO_YFP2_HTIME, 2190}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x7}, + {P_ENCP_VIDEO_YC_DLY, 0}, + {P_ENCP_VIDEO_RGB_CTRL, 2}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_1080p_24hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_FILT_CTRL, 0x1052}, + {P_VENC_DVI_SETTING, 0x000d}, + {P_ENCP_VIDEO_MAX_PXCNT, 2749}, + {P_ENCP_VIDEO_MAX_LNCNT, 1124}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 44}, + {P_ENCP_VIDEO_HSPULS_END, 132}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_HAVON_BEGIN, 271}, + {P_ENCP_VIDEO_HAVON_END, 2190}, + {P_ENCP_VIDEO_HSO_BEGIN, 79}, + {P_ENCP_VIDEO_HSO_END, 123}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 220}, + {P_ENCP_VIDEO_VSPULS_END, 2140}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_EQPULS_BLINE, 0}, + {P_ENCP_VIDEO_EQPULS_ELINE, 4}, + {P_ENCP_VIDEO_VAVON_BLINE, 41}, + {P_ENCP_VIDEO_VAVON_ELINE, 1120}, + {P_ENCP_VIDEO_VSO_BEGIN, 79}, + {P_ENCP_VIDEO_VSO_END, 79}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 271}, + {P_ENCP_VIDEO_YFP2_HTIME, 2190}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x7}, + {P_ENCP_VIDEO_YC_DLY, 0}, + {P_ENCP_VIDEO_RGB_CTRL, 2}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_4k2k_30hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0008}, + {P_ENCP_VIDEO_YFP1_HTIME, 140}, + {P_ENCP_VIDEO_YFP2_HTIME, 140+3840}, + {P_ENCP_VIDEO_MAX_PXCNT, 3840+560-1}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920}, + {P_ENCP_VIDEO_HSPULS_END, 44}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, + {P_ENCP_VIDEO_VSPULS_END, 2059+1920}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_HAVON_BEGIN, 148}, + {P_ENCP_VIDEO_HAVON_END, 3987}, + {P_ENCP_VIDEO_VAVON_BLINE, 89}, + {P_ENCP_VIDEO_VAVON_ELINE, 2248}, + {P_ENCP_VIDEO_HSO_BEGIN, 44}, + {P_ENCP_VIDEO_HSO_END, 2156+1920}, + {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920}, + {P_ENCP_VIDEO_VSO_END, 2164+1920}, + {P_ENCP_VIDEO_VSO_BLINE, 51}, + {P_ENCP_VIDEO_VSO_ELINE, 53}, + {P_ENCP_VIDEO_MAX_LNCNT, 2249}, + {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_4k2k_25hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0008}, + {P_ENCP_VIDEO_YFP1_HTIME, 140}, + {P_ENCP_VIDEO_YFP2_HTIME, 140+3840}, + {P_ENCP_VIDEO_MAX_PXCNT, 3840+1440-1}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920}, + {P_ENCP_VIDEO_HSPULS_END, 44}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, + {P_ENCP_VIDEO_VSPULS_END, 2059+1920}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_HAVON_BEGIN, 148}, + {P_ENCP_VIDEO_HAVON_END, 3987}, + {P_ENCP_VIDEO_VAVON_BLINE, 89}, + {P_ENCP_VIDEO_VAVON_ELINE, 2248}, + {P_ENCP_VIDEO_HSO_BEGIN, 44}, + {P_ENCP_VIDEO_HSO_END, 2156+1920}, + {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920}, + {P_ENCP_VIDEO_VSO_END, 2164+1920}, + {P_ENCP_VIDEO_VSO_BLINE, 51}, + {P_ENCP_VIDEO_VSO_ELINE, 53}, + {P_ENCP_VIDEO_MAX_LNCNT, 2249}, + {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_4k2k_24hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0008}, + {P_ENCP_VIDEO_YFP1_HTIME, 140}, + {P_ENCP_VIDEO_YFP2_HTIME, 140+3840}, + {P_ENCP_VIDEO_MAX_PXCNT, 3840+1660-1}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920}, + {P_ENCP_VIDEO_HSPULS_END, 44}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, + {P_ENCP_VIDEO_VSPULS_END, 2059+1920}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_HAVON_BEGIN, 148}, + {P_ENCP_VIDEO_HAVON_END, 3987}, + {P_ENCP_VIDEO_VAVON_BLINE, 89}, + {P_ENCP_VIDEO_VAVON_ELINE, 2248}, + {P_ENCP_VIDEO_HSO_BEGIN, 44}, + {P_ENCP_VIDEO_HSO_END, 2156+1920}, + {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920}, + {P_ENCP_VIDEO_VSO_END, 2164+1920}, + {P_ENCP_VIDEO_VSO_BLINE, 51}, + {P_ENCP_VIDEO_VSO_ELINE, 53}, + {P_ENCP_VIDEO_MAX_LNCNT, 2249}, + {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_4k2k_smpte[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0008}, + {P_ENCP_VIDEO_YFP1_HTIME, 140}, + {P_ENCP_VIDEO_YFP2_HTIME, 140+3840+256}, + {P_ENCP_VIDEO_MAX_PXCNT, 4096+1404-1}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920}, + {P_ENCP_VIDEO_HSPULS_END, 44}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, + {P_ENCP_VIDEO_VSPULS_END, 2059+1920}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_HAVON_BEGIN, 148}, + {P_ENCP_VIDEO_HAVON_END, 3987+256}, + {P_ENCP_VIDEO_VAVON_BLINE, 89}, + {P_ENCP_VIDEO_VAVON_ELINE, 2248}, + {P_ENCP_VIDEO_HSO_BEGIN, 44}, + {P_ENCP_VIDEO_HSO_END, 2156+1920+256}, + {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920+256}, + {P_ENCP_VIDEO_VSO_END, 2164+1920+256}, + {P_ENCP_VIDEO_VSO_BLINE, 51}, + {P_ENCP_VIDEO_VSO_ELINE, 53}, + {P_ENCP_VIDEO_MAX_LNCNT, 2249}, + {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_4k2k_smpte_25hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x149F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,}, + {P_ENCP_VIDEO_HAVON_END, 0x10D7,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x52,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x58,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_4k2k_smpte_30hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x112F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,}, + {P_ENCP_VIDEO_HAVON_END, 0x10D7,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x52,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x58,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_4k2k_smpte_50hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x149F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,}, + {P_ENCP_VIDEO_HAVON_END, 0x10D7,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x52,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x58,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_4k2k_smpte_60hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x112F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,}, + {P_ENCP_VIDEO_HAVON_END, 0x10D7,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x52,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x58,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_2560x1080p50hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0x000d}, + {P_ENCP_VIDEO_MAX_PXCNT, 3299}, + {P_ENCP_VIDEO_MAX_LNCNT, 1124}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 44}, + {P_ENCP_VIDEO_HSPULS_END, 132}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_HAVON_BEGIN, 192}, + {P_ENCP_VIDEO_HAVON_END, 2751}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 220}, + {P_ENCP_VIDEO_VSPULS_END, 2140}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_EQPULS_BLINE, 0}, + {P_ENCP_VIDEO_EQPULS_ELINE, 4}, + {P_ENCP_VIDEO_VAVON_BLINE, 41}, + {P_ENCP_VIDEO_VAVON_ELINE, 1120}, + {P_ENCP_VIDEO_VSO_BEGIN, 79}, + {P_ENCP_VIDEO_VSO_END, 79}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 271}, + {P_ENCP_VIDEO_YFP2_HTIME, 2190}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x7}, + {P_ENCP_VIDEO_YC_DLY, 0}, + {P_ENCP_VIDEO_RGB_CTRL, 2}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_2560x1080p60hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_DVI_SETTING, 0x000d}, + {P_ENCP_VIDEO_MAX_PXCNT, 2999}, + {P_ENCP_VIDEO_MAX_LNCNT, 1099}, + {P_ENCP_VIDEO_HSPULS_BEGIN, 44}, + {P_ENCP_VIDEO_HSPULS_END, 132}, + {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, + {P_ENCP_VIDEO_HAVON_BEGIN, 192}, + {P_ENCP_VIDEO_HAVON_END, 2751}, + {P_ENCP_VIDEO_HSO_BEGIN, 0}, + {P_ENCP_VIDEO_HSO_END, 44}, + {P_ENCP_VIDEO_VSPULS_BEGIN, 220}, + {P_ENCP_VIDEO_VSPULS_END, 2140}, + {P_ENCP_VIDEO_VSPULS_BLINE, 0}, + {P_ENCP_VIDEO_VSPULS_ELINE, 4}, + {P_ENCP_VIDEO_EQPULS_BLINE, 0}, + {P_ENCP_VIDEO_EQPULS_ELINE, 4}, + {P_ENCP_VIDEO_VAVON_BLINE, 16}, + {P_ENCP_VIDEO_VAVON_ELINE, 1095}, + {P_ENCP_VIDEO_VSO_BEGIN, 79}, + {P_ENCP_VIDEO_VSO_END, 79}, + {P_ENCP_VIDEO_VSO_BLINE, 0}, + {P_ENCP_VIDEO_VSO_ELINE, 5}, + {P_ENCP_VIDEO_YFP1_HTIME, 271}, + {P_ENCP_VIDEO_YFP2_HTIME, 2190}, + {P_VENC_VIDEO_PROG_MODE, 0x100}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x0018}, + {P_ENCP_VIDEO_SYNC_MODE, 0x7}, + {P_ENCP_VIDEO_YC_DLY, 0}, + {P_ENCP_VIDEO_RGB_CTRL, 2}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_vesa_640x480p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x31F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x20C,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x90,}, + {P_ENCP_VIDEO_HAVON_END, 0x30F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x202,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x60,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x2,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_800x600p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x41F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x273,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,}, + {P_ENCP_VIDEO_HAVON_END, 0x3F7,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x272,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x80,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_800x480p60hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + {P_VENC_VDAC_SETTING, 0xff}, + {P_ENCP_VIDEO_MODE, 0x4040}, + {P_ENCP_VIDEO_MODE_ADV, 0x18}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x3DF}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x1F3}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xA8}, + {P_ENCP_VIDEO_HAVON_END, 0x3C7}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x11}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x1F0}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0}, + {P_ENCP_VIDEO_HSO_END, 0x48}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E}, + {P_ENCP_VIDEO_VSO_END, 0x32}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0}, + {P_ENCP_VIDEO_VSO_ELINE, 0x7}, + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_vesa_852x480p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x3B3,},/*947//htotal-1*/ + {P_ENCP_VIDEO_MAX_LNCNT, 0x213,},/*531//vtotal-1*/ + {P_ENCP_VIDEO_HAVON_BEGIN, 0x38,},/*56//hblank-hfront*/ + {P_ENCP_VIDEO_HAVON_END, 0x38B,},/*907//htotal-hfront-1*/ + {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},/*42//vblank-vfront*/ + {P_ENCP_VIDEO_VAVON_ELINE, 0x209,},/*521//vtotal-vfront-1*/ + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x10,},/*16/hor sync time*/ + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/ + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_854x480p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x3B5,},/*949//htotal-1*/ + {P_ENCP_VIDEO_MAX_LNCNT, 0x212,},/*530//vtotal-1*/ + {P_ENCP_VIDEO_HAVON_BEGIN, 0x38,},/*56//hblank-hfront*/ + {P_ENCP_VIDEO_HAVON_END, 0x38D,},/*909//htotal-hfront-1*/ + {P_ENCP_VIDEO_VAVON_BLINE, 0x29,},/*41//vblank-vfront*/ + {P_ENCP_VIDEO_VAVON_ELINE, 0x208,},/*520//vtotal-vfront-1*/ + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x10,},/*16//hor sync time*/ + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/ + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1024x600p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x53F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x27D,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x128,}, + {P_ENCP_VIDEO_HAVON_END, 0x527,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x27A,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x88,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1024x768p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x53F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x325,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x128,}, + {P_ENCP_VIDEO_HAVON_END, 0x527,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x322,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x88,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1152x864p75hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x63F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x383,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x180,}, + {P_ENCP_VIDEO_HAVON_END, 0x5FF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x382,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x80,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1280x600p60hz[] = { +#if 0 + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x59F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x336,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,}, + {P_ENCP_VIDEO_HAVON_END, 0x56F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x14,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x333,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x20,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +#endif +}; + +static const struct reg_s tvregs_vesa_1280x768p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x67F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x31D,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x140,}, + {P_ENCP_VIDEO_HAVON_END, 0x63F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x31A,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x80,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x7,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1280x800p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x59F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x336,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,}, + {P_ENCP_VIDEO_HAVON_END, 0x56F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x14,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x333,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x20,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1280x960p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x707,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x1A8,}, + {P_ENCP_VIDEO_HAVON_END, 0x6A7,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x27,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x70,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1280x1024p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x697,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x429,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x168,}, + {P_ENCP_VIDEO_HAVON_END, 0x667,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x29,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x428,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x70,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1360x768p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x31A,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x170,}, + {P_ENCP_VIDEO_HAVON_END, 0x6BF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x18,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x317,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x70,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1366x768p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x31D,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x164,}, + {P_ENCP_VIDEO_HAVON_END, 0x6B9,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x31A,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x8F,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1400x1050p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x747,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x440,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x178,}, + {P_ENCP_VIDEO_HAVON_END, 0x6EF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x24,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x43D,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x90,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1440x900p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x76F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x3A5,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x180,}, + {P_ENCP_VIDEO_HAVON_END, 0x71F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x1F,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x3A2,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x98,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1440x2560p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x623,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0xA23,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x44,}, + {P_ENCP_VIDEO_HAVON_END, 0x5E3,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x14,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0xA13,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x4,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x4,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1600x900p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x707,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0xB0,}, + {P_ENCP_VIDEO_HAVON_END, 0x6EF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x63,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x50,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1600x1200p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x86F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4E1,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x1F0,}, + {P_ENCP_VIDEO_HAVON_END, 0x82F,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x31,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4E0,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xC0,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1680x1050p60hz[] = { + {P_VENC_VDAC_SETTING, 0xff,}, + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x8BF,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x440,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x1C8,}, + {P_ENCP_VIDEO_HAVON_END, 0x857,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x24,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x43D,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xB0,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0,}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_1920x1200p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x218,}, + {P_ENCP_VIDEO_HAVON_END, 0x997,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0xC8,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_2160x1200p90hz[] = { + {P_ENCP_VIDEO_EN, 0}, + {P_ENCI_VIDEO_EN, 0}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x99D,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4BB,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,}, + {P_ENCP_VIDEO_HAVON_END, 0x8DF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x6,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4B5,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x20,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x3,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0}, +}; + +static const struct reg_s tvregs_vesa_2560x1600p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0xDAF,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x679,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x2F0,}, + {P_ENCP_VIDEO_HAVON_END, 0xCEF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x37,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x676,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x118,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x6,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_3440x1440p60hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0xE0F,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x5C8,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,}, + {P_ENCP_VIDEO_HAVON_END, 0xDDF,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x26,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x5C5,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x20,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +}; + +static const struct reg_s tvregs_vesa_2400x1200p90hz[] = { + {P_ENCP_VIDEO_EN, 0,}, + {P_ENCI_VIDEO_EN, 0,}, + {P_VENC_VDAC_SETTING, 0xff,}, + + {P_ENCP_VIDEO_MODE, 0x4040,}, + {P_ENCP_VIDEO_MODE_ADV, 0x18,}, + {P_ENCP_VIDEO_MAX_PXCNT, 0x9B1,}, + {P_ENCP_VIDEO_MAX_LNCNT, 0x4E3,}, + {P_ENCP_VIDEO_HAVON_BEGIN, 0x3E,}, + {P_ENCP_VIDEO_HAVON_END, 0x99D,}, + {P_ENCP_VIDEO_VAVON_BLINE, 0x23,}, + {P_ENCP_VIDEO_VAVON_ELINE, 0x4D2,}, + {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, + {P_ENCP_VIDEO_HSO_END, 0x1E,}, + {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, + {P_ENCP_VIDEO_VSO_END, 0x32,}, + {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, + {P_ENCP_VIDEO_VSO_ELINE, 0x5,}, + + {P_ENCI_VIDEO_EN, 0}, + {MREG_END_MARKER, 0} +}; + +struct vic_tvregs_set { + enum hdmi_vic vic; + const struct reg_s *reg_setting; +}; + +/* Using HDMI VIC as index */ +static struct vic_tvregs_set tvregsTab[] = { + {HDMI_720x480i60_16x9, tvregs_480i}, + {HDMI_720x480i60_4x3, tvregs_480i}, + {HDMI_2880x480i60_16x9, tvregs_480i}, + {HDMI_720x480p60_16x9, tvregs_480p}, + {HDMI_720x480p60_4x3, tvregs_480p}, + {HDMI_2880x240p60_16x9, tvregs_480p}, + {HDMI_720x576i50_16x9, tvregs_576i}, + {HDMI_720x576i50_4x3, tvregs_576i}, + {HDMI_2880x576i50_16x9, tvregs_576i}, + {HDMI_720x576p50_16x9, tvregs_576p}, + {HDMI_720x576p50_4x3, tvregs_576p}, + {HDMI_2880x576p50_16x9, tvregs_576p}, + {HDMI_1280x720p60_16x9, tvregs_720p}, + {HDMI_1920x1080i60_16x9, tvregs_1080i}, + {HDMI_1920x1080p60_16x9, tvregs_1080p}, + {HDMI_1280x720p50_16x9, tvregs_720p_50hz}, + {HDMI_1920x1080i50_16x9, tvregs_1080i_50hz}, + {HDMI_1920x1080p50_16x9, tvregs_1080p_50hz}, + {HDMI_1920x1080p25_16x9, tvregs_1080p_50hz}, + {HDMI_1920x1080p30_16x9, tvregs_1080p}, + {HDMI_1920x1080p24_16x9, tvregs_1080p_24hz}, + {HDMI_3840x2160p30_16x9, tvregs_4k2k_30hz}, + {HDMI_3840x2160p25_16x9, tvregs_4k2k_25hz}, + {HDMI_3840x2160p24_16x9, tvregs_4k2k_24hz}, + {HDMI_4096x2160p24_256x135, tvregs_4k2k_smpte}, + {HDMI_4096x2160p25_256x135, tvregs_4k2k_smpte_25hz}, + {HDMI_4096x2160p30_256x135, tvregs_4k2k_smpte_30hz}, + {HDMI_4096x2160p50_256x135, tvregs_4k2k_smpte_50hz}, + {HDMI_4096x2160p60_256x135, tvregs_4k2k_smpte_60hz}, + {HDMI_4096x2160p60_256x135_Y420, tvregs_4k2k_smpte_60hz}, + {HDMI_4096x2160p50_256x135_Y420, tvregs_4k2k_smpte_50hz}, + {HDMI_3840x2160p60_16x9, tvregs_4k2k_30hz}, + {HDMI_3840x2160p50_16x9, tvregs_4k2k_25hz}, + {HDMI_3840x2160p60_16x9_Y420, tvregs_4k2k_30hz}, + {HDMI_3840x2160p50_16x9_Y420, tvregs_4k2k_25hz}, + {HDMI_2560x1080p50_64x27, tvregs_2560x1080p50hz}, + {HDMI_2560x1080p60_64x27, tvregs_2560x1080p60hz}, + {HDMIV_640x480p60hz, tvregs_vesa_640x480p60hz}, + {HDMIV_800x480p60hz, tvregs_vesa_800x480p60hz}, + {HDMIV_800x600p60hz, tvregs_vesa_800x600p60hz}, + {HDMIV_852x480p60hz, tvregs_vesa_852x480p60hz}, + {HDMIV_854x480p60hz, tvregs_vesa_854x480p60hz}, + {HDMIV_1024x600p60hz, tvregs_vesa_1024x600p60hz}, + {HDMIV_1024x768p60hz, tvregs_vesa_1024x768p60hz}, + {HDMIV_1152x864p75hz, tvregs_vesa_1152x864p75hz}, + {HDMIV_1280x600p60hz, tvregs_vesa_1280x600p60hz}, + {HDMIV_1280x768p60hz, tvregs_vesa_1280x768p60hz}, + {HDMIV_1280x800p60hz, tvregs_vesa_1280x800p60hz}, + {HDMIV_1280x960p60hz, tvregs_vesa_1280x960p60hz}, + {HDMIV_1280x1024p60hz, tvregs_vesa_1280x1024p60hz}, + {HDMIV_1360x768p60hz, tvregs_vesa_1360x768p60hz}, + {HDMIV_1366x768p60hz, tvregs_vesa_1366x768p60hz}, + {HDMIV_1400x1050p60hz, tvregs_vesa_1400x1050p60hz}, + {HDMIV_1440x900p60hz, tvregs_vesa_1440x900p60hz}, + {HDMIV_1440x2560p60hz, tvregs_vesa_1440x2560p60hz}, + {HDMIV_1600x900p60hz, tvregs_vesa_1600x900p60hz}, + {HDMIV_1600x1200p60hz, tvregs_vesa_1600x1200p60hz}, + {HDMIV_1680x1050p60hz, tvregs_vesa_1680x1050p60hz}, + {HDMIV_1920x1200p60hz, tvregs_vesa_1920x1200p60hz}, + {HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz}, + {HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz}, + {HDMIV_3440x1440p60hz, tvregs_vesa_3440x1440p60hz}, + {HDMIV_2400x1200p90hz, tvregs_vesa_2400x1200p90hz}, +}; + +static inline void setreg(const struct reg_s *r) +{ + hd_write_reg(r->reg, r->val); + /* printk("[0x%x] = 0x%x\n", r->reg, r->val); */ +} + +static const struct reg_s *tvregs_setting_mode(enum hdmi_vic vic) +{ + int i = 0; + for (i = 0; i < ARRAY_SIZE(tvregsTab); i++) { + if (vic == tvregsTab[i].vic) + return tvregsTab[i].reg_setting; + } + return NULL; +} + +void set_vmode_enc_hw(enum hdmi_vic vic) +{ + const struct reg_s *s = tvregs_setting_mode(vic); + + if (s) { + pr_info("hdmitx: set enc for VIC: %d\n", vic); + while (s->reg != MREG_END_MARKER) + setreg(s++); + } else + printf("hdmitx: not find VIC: %d\n", vic); +}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_common.h b/drivers/amlogic/media/vout/hdmitx/hdmitx_common.h deleted file mode 100644 index 5bba929..0000000 --- a/drivers/amlogic/media/vout/hdmitx/hdmitx_common.h +++ /dev/null
@@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#ifndef __HDMITX_COMMON_H__ -#define __HDMITX_COMMON_H__ - -#include <common.h> -#include <amlogic/media/vout/hdmitx.h> - -#define CLK_UTIL_VID_PLL_DIV_1 0 -#define CLK_UTIL_VID_PLL_DIV_2 1 -#define CLK_UTIL_VID_PLL_DIV_3 2 -#define CLK_UTIL_VID_PLL_DIV_3p5 3 -#define CLK_UTIL_VID_PLL_DIV_3p75 4 -#define CLK_UTIL_VID_PLL_DIV_4 5 -#define CLK_UTIL_VID_PLL_DIV_5 6 -#define CLK_UTIL_VID_PLL_DIV_6 7 -#define CLK_UTIL_VID_PLL_DIV_6p25 8 -#define CLK_UTIL_VID_PLL_DIV_7 9 -#define CLK_UTIL_VID_PLL_DIV_7p5 10 -#define CLK_UTIL_VID_PLL_DIV_12 11 -#define CLK_UTIL_VID_PLL_DIV_14 12 -#define CLK_UTIL_VID_PLL_DIV_15 13 -#define CLK_UTIL_VID_PLL_DIV_2p5 14 -#define CLK_UTIL_VID_PLL_DIV_3p25 15 - -enum viu_type { - VIU_ENCL = 0, - VIU_ENCI, - VIU_ENCP, - VIU_ENCT, -}; - -typedef struct{ - enum hdmi_vic vic; - unsigned viu_path; - enum viu_type viu_type; - unsigned hpll_clk_out; - unsigned od1; - unsigned od2; - unsigned od3; - unsigned vid_pll_div; - unsigned vid_clk_div; - unsigned hdmi_tx_pixel_div; - unsigned encp_div; - unsigned enci_div; -}hw_enc_clk_val_t; - -#define GROUP_MAX 10 -#define GROUP_END -1 -struct hw_enc_clk_val_group { - enum hdmi_vic group[GROUP_MAX]; - unsigned viu_path; - enum viu_type viu_type; - unsigned hpll_clk_out; - unsigned od1; - unsigned od2; - unsigned od3; - unsigned vid_pll_div; - unsigned vid_clk_div; - unsigned hdmi_tx_pixel_div; - unsigned encp_div; - unsigned enci_div; -}; - -struct reg_t { - volatile unsigned int* reg; - unsigned int val; -}; - -extern void hdmitx_set_clk(struct hdmitx_dev *hdev); -extern void set_hdmitx_clk_420(void); -extern void set_vmode_enc_hw(enum hdmi_vic vic); - -#endif
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_hdcp.c b/drivers/amlogic/media/vout/hdmitx/hdmitx_hdcp.c deleted file mode 100644 index c64c121..0000000 --- a/drivers/amlogic/media/vout/hdmitx/hdmitx_hdcp.c +++ /dev/null
@@ -1,85 +0,0 @@ - -/* - * arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_hdcp.c - * - * Copyright (C) 2015 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <asm/arch/io.h> -#include <common.h> -#include "hdmi_tx_reg.h" - -// if the following bits are 0, then access HDMI IP Port will cause system hungup -#define GATE_NUM 2 - -static struct Hdmi_Gate_s{ - unsigned short cbus_addr; - unsigned char gate_bit; -}hdmi_gate[GATE_NUM] = { {HHI_HDMI_CLK_CNTL, 8}, - {HHI_GCLK_MPEG2 , 4}, - }; - -// In order to prevent system hangup, add check_cts_hdmi_sys_clk_status() to check -static void check_cts_hdmi_sys_clk_status(void) -{ - int i; - - for (i = 0; i < GATE_NUM; i++) { - if (!(READ_CBUS_REG(hdmi_gate[i].cbus_addr) & (1<<hdmi_gate[i].gate_bit))) { -// printf("HDMI Gate Clock is off, turn on now\n"); - WRITE_CBUS_REG_BITS(hdmi_gate[i].cbus_addr, 1, hdmi_gate[i].gate_bit, 1); - } - } -} - -unsigned long hdmi_hdcp_rd_reg(unsigned long addr) -{ - unsigned long data; - check_cts_hdmi_sys_clk_status(); - WRITE_APB_REG(HDMI_ADDR_PORT, addr); - WRITE_APB_REG(HDMI_ADDR_PORT, addr); - - data = READ_APB_REG(HDMI_DATA_PORT); - - return (data); -} - -void hdmi_hdcp_wr_reg(unsigned long addr, unsigned long data) -{ - check_cts_hdmi_sys_clk_status(); - WRITE_APB_REG(HDMI_ADDR_PORT, addr); - WRITE_APB_REG(HDMI_ADDR_PORT, addr); - - WRITE_APB_REG(HDMI_DATA_PORT, data); -} - -#define TX_HDCP_KSV_OFFSET 0x540 -#define TX_HDCP_KSV_SIZE 5 -// Must be done by system init -// In kenrel hdmi driver, it will get AKSV value -// If equals to 0, then kernel won't enable HDCP -extern int hdmi_hdcp_clear_ksv_ram(void); -int hdmi_hdcp_clear_ksv_ram(void) -{ - int i; - for (i = 0; i < TX_HDCP_KSV_SIZE; i++) { - hdmi_hdcp_wr_reg(TX_HDCP_KSV_OFFSET + i, 0x00); - } - printf("clr h-ram\n"); - return 0; -} -
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_reg.h b/drivers/amlogic/media/vout/hdmitx/hdmitx_reg.h deleted file mode 100644 index 7229df6..0000000 --- a/drivers/amlogic/media/vout/hdmitx/hdmitx_reg.h +++ /dev/null
@@ -1,998 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#ifndef _HDMI_TX_REG_H -#define _HDMI_TX_REG_H - -/* TOP-level wrapper registers addresses */ -/* bit24: 1 means secure access */ -/* bit28: 1 means DWC, 0 means TOP */ -#define SEC_OFFSET (0x1UL << 24) -#define TOP_OFFSET_MASK (0x0UL << 24) -#define TOP_SEC_OFFSET_MASK ((TOP_OFFSET_MASK) | (SEC_OFFSET)) -#define DWC_OFFSET_MASK (0x10UL << 24) -#define DWC_SEC_OFFSET_MASK ((DWC_OFFSET_MASK) | (SEC_OFFSET)) - -/* Bit 7 RW Reserved. Default 1. */ -/* Bit 6 RW Reserved. Default 1. */ -/* Bit 5 RW Reserved. Default 1. */ -/* Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. - * Default 1. - * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; - * 0=Release from reset. Default 1. - * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset. - * Default 1. - * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset; - * 0=Release from reset. Default 1. - * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset; - * 0=Release from reset. Default 1. - */ -#define HDMITX_TOP_SW_RESET (TOP_OFFSET_MASK + 0x000) - -/* Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. */ -/* Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. */ -/* Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. */ -/* Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. */ -/* Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. */ -/* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. */ -/* Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. */ -/* Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. */ -/* Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. */ -/* Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. */ -#define HDMITX_TOP_CLK_CNTL (TOP_OFFSET_MASK + 0x001) - -/* Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. */ -/* Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. */ -#define HDMITX_TOP_HPD_FILTER (TOP_OFFSET_MASK + 0x002) - -/* intr_maskn: MASK_N, one bit per interrupt source. - * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. - * [ 4] hdcp22_rndnum_err - * [ 3] nonce_rfrsh_rise - * [ 2] hpd_fall_intr - * [ 1] hpd_rise_intr - * [ 0] core_intr - */ -#define HDMITX_TOP_INTR_MASKN (TOP_OFFSET_MASK + 0x003) - -/* Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt - * bit, read back the interrupt status. */ -/* Bit 31 R IP interrupt status */ -/* Bit 2 RW hpd_fall */ -/* Bit 1 RW hpd_rise */ -/* Bit 0 RW IP interrupt */ -#define HDMITX_TOP_INTR_STAT (TOP_OFFSET_MASK + 0x004) - -/* [4] hdcp22_rndnum_err */ -/* [3] nonce_rfrsh_rise */ -/* [2] hpd_fall */ -/* [1] hpd_rise */ -/* [0] core_intr_rise */ -#define HDMITX_TOP_INTR_STAT_CLR (TOP_OFFSET_MASK + 0x005) - -/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; - * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. - * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern - * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. - * Bit 8 RW shift_pttn_en: 1= Eanble shift pattern generator; 0=Disable. - * Default 0. - * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0. - * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern; - * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0. - * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0. - */ -#define HDMITX_TOP_BIST_CNTL (TOP_OFFSET_MASK + 0x006) - -/* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */ -/* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */ -/* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */ -#define HDMITX_TOP_SHIFT_PTTN_012 (TOP_OFFSET_MASK + 0x007) - -/* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */ -/* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */ -/* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */ -#define HDMITX_TOP_SHIFT_PTTN_345 (TOP_OFFSET_MASK + 0x008) - -/* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */ -/* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */ -#define HDMITX_TOP_SHIFT_PTTN_67 (TOP_OFFSET_MASK + 0x009) - -/* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */ -/* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */ -#define HDMITX_TOP_TMDS_CLK_PTTN_01 (TOP_OFFSET_MASK + 0x00A) - -/* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */ -/* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ -#define HDMITX_TOP_TMDS_CLK_PTTN_23 (TOP_OFFSET_MASK + 0x00B) - -/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, - * used when TMDS CLK rate = TMDS character rate /4. Default 0. - * Bit 0 R Reserved. Default 0. - */ -/* [ 1] shift_tmds_clk_pttn */ -/* [ 0] load_tmds_clk_pttn */ -#define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (TOP_OFFSET_MASK + 0x00C) - -/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM - * failure, write 1 to clear the failure flag. Default 0. - */ -#define HDMITX_TOP_REVOCMEM_STAT (TOP_OFFSET_MASK + 0x00D) - -/* Bit 0 R filtered HPD status. */ -#define HDMITX_TOP_STAT0 (TOP_OFFSET_MASK + 0x00E) -#define HDMITX_TOP_SKP_CNTL_STAT (TOP_SEC_OFFSET_MASK + 0x010) -#define HDMITX_TOP_NONCE_0 (TOP_SEC_OFFSET_MASK + 0x011) -#define HDMITX_TOP_NONCE_1 (TOP_SEC_OFFSET_MASK + 0x012) -#define HDMITX_TOP_NONCE_2 (TOP_SEC_OFFSET_MASK + 0x013) -#define HDMITX_TOP_NONCE_3 (TOP_SEC_OFFSET_MASK + 0x014) -#define HDMITX_TOP_PKF_0 (TOP_SEC_OFFSET_MASK + 0x015) -#define HDMITX_TOP_PKF_1 (TOP_SEC_OFFSET_MASK + 0x016) -#define HDMITX_TOP_PKF_2 (TOP_SEC_OFFSET_MASK + 0x017) -#define HDMITX_TOP_PKF_3 (TOP_SEC_OFFSET_MASK + 0x018) -#define HDMITX_TOP_DUK_0 (TOP_SEC_OFFSET_MASK + 0x019) -#define HDMITX_TOP_DUK_1 (TOP_SEC_OFFSET_MASK + 0x01A) -#define HDMITX_TOP_DUK_2 (TOP_SEC_OFFSET_MASK + 0x01B) -#define HDMITX_TOP_DUK_3 (TOP_SEC_OFFSET_MASK + 0x01C) -/* [26:24] infilter_ddc_intern_clk_divide */ -/* [23:16] infilter_ddc_sample_clk_divide */ -/* [10: 8] infilter_cec_intern_clk_divide */ -/* [ 7: 0] infilter_cec_sample_clk_divide */ -#define HDMITX_TOP_INFILTER (TOP_OFFSET_MASK + 0x01D) -#define HDMITX_TOP_NSEC_SCRATCH (TOP_OFFSET_MASK + 0x01E) -#define HDMITX_TOP_SEC_SCRATCH (TOP_SEC_OFFSET_MASK + 0x01F) -#define HDMITX_TOP_EMP_CNTL0 (TOP_OFFSET_MASK + 0x020) -#define HDMITX_TOP_EMP_CNTL1 (TOP_OFFSET_MASK + 0x021) -#define HDMITX_TOP_EMP_MEMADDR_START (TOP_OFFSET_MASK + 0x022) -#define HDMITX_TOP_EMP_STAT0 (TOP_OFFSET_MASK + 0x023) -#define HDMITX_TOP_EMP_STAT1 (TOP_OFFSET_MASK + 0x024) -#define HDMITX_TOP_AXI_ASYNC_CNTL0 (TOP_OFFSET_MASK + 0x025) -#define HDMITX_TOP_AXI_ASYNC_CNTL1 (TOP_OFFSET_MASK + 0x026) -#define HDMITX_TOP_AXI_ASYNC_STAT0 (TOP_OFFSET_MASK + 0x027) -#define HDMITX_TOP_I2C_BUSY_CNT_MAX (TOP_OFFSET_MASK + 0x028) -#define HDMITX_TOP_I2C_BUSY_CNT_STAT (TOP_OFFSET_MASK + 0x029) -#define HDMITX_TOP_HDCP22_BSOD (TOP_OFFSET_MASK + 0x02A) -#define HDMITX_TOP_DDC_CNTL (TOP_OFFSET_MASK + 0x02B) -#define HDMITX_TOP_REVOCMEM_ADDR_S (TOP_OFFSET_MASK + 0x2000) -#define HDMITX_TOP_REVOCMEM_ADDR_E (TOP_OFFSET_MASK + 0x365E) - -#define HDMITX_TOP_DONT_TOUCH0 (TOP_OFFSET_MASK + 0x0FE) -#define HDMITX_TOP_DONT_TOUCH1 (TOP_OFFSET_MASK + 0x0FF) - -/* DWC_HDMI_TX Controller registers addresses */ - -/* Identification Registers */ -#define HDMITX_DWC_DESIGN_ID (DWC_OFFSET_MASK + 0x0000) -#define HDMITX_DWC_REVISION_ID (DWC_OFFSET_MASK + 0x0001) -#define HDMITX_DWC_PRODUCT_ID0 (DWC_OFFSET_MASK + 0x0002) -#define HDMITX_DWC_PRODUCT_ID1 (DWC_OFFSET_MASK + 0x0003) -#define HDMITX_DWC_CONFIG0_ID (DWC_OFFSET_MASK + 0x0004) -#define HDMITX_DWC_CONFIG1_ID (DWC_OFFSET_MASK + 0x0005) -#define HDMITX_DWC_CONFIG2_ID (DWC_OFFSET_MASK + 0x0006) -#define HDMITX_DWC_CONFIG3_ID (DWC_OFFSET_MASK + 0x0007) - -/* Interrupt Registers */ -#define HDMITX_DWC_IH_FC_STAT0 (DWC_OFFSET_MASK + 0x0100) -#define HDMITX_DWC_IH_FC_STAT1 (DWC_OFFSET_MASK + 0x0101) -#define HDMITX_DWC_IH_FC_STAT2 (DWC_OFFSET_MASK + 0x0102) -#define HDMITX_DWC_IH_AS_STAT0 (DWC_OFFSET_MASK + 0x0103) -#define HDMITX_DWC_IH_PHY_STAT0 (DWC_OFFSET_MASK + 0x0104) -#define HDMITX_DWC_IH_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0105) -#define HDMITX_DWC_IH_CEC_STAT0 (DWC_OFFSET_MASK + 0x0106) -#define HDMITX_DWC_IH_VP_STAT0 (DWC_OFFSET_MASK + 0x0107) -#define HDMITX_DWC_IH_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0108) -#define HDMITX_DWC_IH_DECODE (DWC_OFFSET_MASK + 0x0170) -/* [ 7] mute_AUDI */ -/* [ 6] mute_ACP */ -/* [ 5] mute_HBR */ -/* [ 4] mute_MAS */ -/* [ 3] mute_NVBI */ -/* [ 2] mute_AUDS */ -/* [ 1] mute_ACR */ -/* [ 0] mute_NULL */ -#define HDMITX_DWC_IH_MUTE_FC_STAT0 (DWC_OFFSET_MASK + 0x0180) -/* [ 7] mute_GMD */ -/* [ 6] mute_ISRC1 */ -/* [ 5] mute_ISRC2 */ -/* [ 4] mute_VSD */ -/* [ 3] mute_SPD */ -/* [ 2] mute_AMP */ -/* [ 1] mute_AVI */ -/* [ 0] mute_GCP */ -#define HDMITX_DWC_IH_MUTE_FC_STAT1 (DWC_OFFSET_MASK + 0x0181) -/* [ 1] mute_LowPriority_fifo_full */ -/* [ 0] mute_HighPriority_fifo_full */ -#define HDMITX_DWC_IH_MUTE_FC_STAT2 (DWC_OFFSET_MASK + 0x0182) -/* [ 4] mute_aud_fifo_underrun */ -/* [ 3] mute_aud_fifo_overrun */ -/* [ 2] mute_aud_fifo_empty_thr. oififoemptythr tied to 0. */ -/* [ 1] mute_aud_fifo_empty */ -/* [ 0] mute_aud_fifo_full */ -#define HDMITX_DWC_IH_MUTE_AS_STAT0 (DWC_OFFSET_MASK + 0x0183) -#define HDMITX_DWC_IH_MUTE_PHY_STAT0 (DWC_OFFSET_MASK + 0x0184) -/* [ 2] mute_scdc_readreq */ -/* [ 1] mute_edid_i2c_master_done */ -/* [ 0] mute_edid_i2c_master_error */ -#define HDMITX_DWC_IH_MUTE_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0185) -/* [ 6] cec_wakeup */ -/* [ 5] cec_error_follower */ -/* [ 4] cec_error_initiator */ -/* [ 3] cec_arb_lost */ -/* [ 2] cec_nack */ -/* [ 1] cec_eom */ -/* [ 0] cec_done */ -#define HDMITX_DWC_IH_MUTE_CEC_STAT0 (DWC_OFFSET_MASK + 0x0186) -#define HDMITX_DWC_IH_MUTE_VP_STAT0 (DWC_OFFSET_MASK + 0x0187) -#define HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0188) -/* [ 1] mute_wakeup_interrupt */ -/* [ 0] mute_all_interrupt */ -#define HDMITX_DWC_IH_MUTE (DWC_OFFSET_MASK + 0x01FF) - -/* Video Sampler Registers */ -/* [ 7] internal_de_generator */ -/* [4:0] video_mapping */ -#define HDMITX_DWC_TX_INVID0 (DWC_OFFSET_MASK + 0x0200) -/* [ 2] bcbdata_stuffing */ -/* [ 1] rcrdata_stuffing */ -/* [ 0] gydata_stuffing */ -#define HDMITX_DWC_TX_INSTUFFING (DWC_OFFSET_MASK + 0x0201) -#define HDMITX_DWC_TX_GYDATA0 (DWC_OFFSET_MASK + 0x0202) -#define HDMITX_DWC_TX_GYDATA1 (DWC_OFFSET_MASK + 0x0203) -#define HDMITX_DWC_TX_RCRDATA0 (DWC_OFFSET_MASK + 0x0204) -#define HDMITX_DWC_TX_RCRDATA1 (DWC_OFFSET_MASK + 0x0205) -#define HDMITX_DWC_TX_BCBDATA0 (DWC_OFFSET_MASK + 0x0206) -#define HDMITX_DWC_TX_BCBDATA1 (DWC_OFFSET_MASK + 0x0207) - -/* Video Packetizer Registers */ -#define HDMITX_DWC_VP_STATUS (DWC_OFFSET_MASK + 0x0800) -/* [3:0] desired_pr_factor */ -#define HDMITX_DWC_VP_PR_CD (DWC_OFFSET_MASK + 0x0801) -/* [ 5] default_phase */ -/* [ 2] ycc422_stuffing */ -/* [ 1] pp_stuffing */ -/* [ 0] pr_stuffing */ -#define HDMITX_DWC_VP_STUFF (DWC_OFFSET_MASK + 0x0802) -#define HDMITX_DWC_VP_REMAP (DWC_OFFSET_MASK + 0x0803) -#define HDMITX_DWC_VP_CONF (DWC_OFFSET_MASK + 0x0804) -/* [ 7] mask_int_full_prpt */ -/* [ 6] mask_int_empty_prpt */ -/* [ 5] mask_int_full_ppack */ -/* [ 4] mask_int_empty_ppack */ -/* [ 3] mask_int_full_remap */ -/* [ 2] mask_int_empty_remap */ -/* [ 1] mask_int_full_byp */ -/* [ 0] mask_int_empty_byp */ -#define HDMITX_DWC_VP_MASK (DWC_OFFSET_MASK + 0x0807) - -/* Frmae Composer Registers */ -/* [ 7] HDCP_keepout */ -/* [ 6] vs_in_pol: 0=active low; 1=active high. */ -/* [ 5] hs_in_pol: 0=active low; 1=active high. */ -/* [ 4] de_in_pol: 0=active low; 1=active high. */ -/* [ 3] dvi_modez: 0=dvi; 1=hdmi. */ -/* [ 1] r_v_blank_in_osc */ -/* [ 0] in_I_P: 0=progressive; 1=interlaced. */ -#define HDMITX_DWC_FC_INVIDCONF (DWC_OFFSET_MASK + 0x1000) -/* [7:0] H_in_active[7:0] */ -#define HDMITX_DWC_FC_INHACTV0 (DWC_OFFSET_MASK + 0x1001) -/* [5:0] H_in_active[13:8] */ -#define HDMITX_DWC_FC_INHACTV1 (DWC_OFFSET_MASK + 0x1002) -/* [7:0] H_in_blank[7:0] */ -#define HDMITX_DWC_FC_INHBLANK0 (DWC_OFFSET_MASK + 0x1003) -/* [4:0] H_in_blank[12:8] */ -#define HDMITX_DWC_FC_INHBLANK1 (DWC_OFFSET_MASK + 0x1004) -/* [7:0] V_in_active[7:0] */ -#define HDMITX_DWC_FC_INVACTV0 (DWC_OFFSET_MASK + 0x1005) -/* [4:0] V_in_active[12:8] */ -#define HDMITX_DWC_FC_INVACTV1 (DWC_OFFSET_MASK + 0x1006) -/* [7:0] V_in_blank */ -#define HDMITX_DWC_FC_INVBLANK (DWC_OFFSET_MASK + 0x1007) -/* [7:0] H_in_delay[7:0] */ -#define HDMITX_DWC_FC_HSYNCINDELAY0 (DWC_OFFSET_MASK + 0x1008) -/* [4:0] H_in_delay[12:8] */ -#define HDMITX_DWC_FC_HSYNCINDELAY1 (DWC_OFFSET_MASK + 0x1009) -/* [7:0] H_in_width[7:0] */ -#define HDMITX_DWC_FC_HSYNCINWIDTH0 (DWC_OFFSET_MASK + 0x100A) -/* [1:0] H_in_width[9:8] */ -#define HDMITX_DWC_FC_HSYNCINWIDTH1 (DWC_OFFSET_MASK + 0x100B) -/* [7:0] V_in_delay */ -#define HDMITX_DWC_FC_VSYNCINDELAY (DWC_OFFSET_MASK + 0x100C) -/* [5:0] V_in_width */ -#define HDMITX_DWC_FC_VSYNCINWIDTH (DWC_OFFSET_MASK + 0x100D) -#define HDMITX_DWC_FC_INFREQ0 (DWC_OFFSET_MASK + 0x100E) -#define HDMITX_DWC_FC_INFREQ1 (DWC_OFFSET_MASK + 0x100F) -#define HDMITX_DWC_FC_INFREQ2 (DWC_OFFSET_MASK + 0x1010) -#define HDMITX_DWC_FC_CTRLDUR (DWC_OFFSET_MASK + 0x1011) -#define HDMITX_DWC_FC_EXCTRLDUR (DWC_OFFSET_MASK + 0x1012) -#define HDMITX_DWC_FC_EXCTRLSPAC (DWC_OFFSET_MASK + 0x1013) -#define HDMITX_DWC_FC_CH0PREAM (DWC_OFFSET_MASK + 0x1014) -#define HDMITX_DWC_FC_CH1PREAM (DWC_OFFSET_MASK + 0x1015) -#define HDMITX_DWC_FC_CH2PREAM (DWC_OFFSET_MASK + 0x1016) -/* [3:2] YQ */ -/* [1:0] CN */ -#define HDMITX_DWC_FC_AVICONF3 (DWC_OFFSET_MASK + 0x1017) -/* [ 2] default_phase */ -/* [ 1] set_avmute */ -/* [ 0] clear_avmute */ -#define HDMITX_DWC_FC_GCP (DWC_OFFSET_MASK + 0x1018) -/* [ 7] rgb_ycc_indication[2] */ -/* [ 6] active_format_present */ -/* [5:4] scan_information */ -/* [3:2] bar_information */ -/* [1:0] rgb_ycc_indication[1:0] */ -#define HDMITX_DWC_FC_AVICONF0 (DWC_OFFSET_MASK + 0x1019) -/* [7:6] colorimetry */ -/* [5:4] picture_aspect_ratio */ -/* [3:0] active_aspect_ratio */ -#define HDMITX_DWC_FC_AVICONF1 (DWC_OFFSET_MASK + 0x101A) -/* [ 7] IT_content */ -/* [6:4] extended_colorimetry */ -/* [3:2] quantization_range */ -/* [1:0] non_uniform_picture_scaling */ -#define HDMITX_DWC_FC_AVICONF2 (DWC_OFFSET_MASK + 0x101B) -#define HDMITX_DWC_FC_AVIVID (DWC_OFFSET_MASK + 0x101C) -#define HDMITX_DWC_FC_AVIETB0 (DWC_OFFSET_MASK + 0x101D) -#define HDMITX_DWC_FC_AVIETB1 (DWC_OFFSET_MASK + 0x101E) -#define HDMITX_DWC_FC_AVISBB0 (DWC_OFFSET_MASK + 0x101F) -#define HDMITX_DWC_FC_AVISBB1 (DWC_OFFSET_MASK + 0x1020) -#define HDMITX_DWC_FC_AVIELB0 (DWC_OFFSET_MASK + 0x1021) -#define HDMITX_DWC_FC_AVIELB1 (DWC_OFFSET_MASK + 0x1022) -#define HDMITX_DWC_FC_AVISRB0 (DWC_OFFSET_MASK + 0x1023) -#define HDMITX_DWC_FC_AVISRB1 (DWC_OFFSET_MASK + 0x1024) -/* [3:0] CT: coding type */ -#define HDMITX_DWC_FC_AUDICONF0 (DWC_OFFSET_MASK + 0x1025) -/* [5:4] SS: sampling size */ -/* [2:0] SF: sampling frequency */ -#define HDMITX_DWC_FC_AUDICONF1 (DWC_OFFSET_MASK + 0x1026) -/* CA: channel allocation */ -#define HDMITX_DWC_FC_AUDICONF2 (DWC_OFFSET_MASK + 0x1027) -/* [6:5] LFEPBL: LFE playback info */ -/* [ 4] DM_INH: down mix enable */ -/* [3:0] LSv: Level shift value */ -#define HDMITX_DWC_FC_AUDICONF3 (DWC_OFFSET_MASK + 0x1028) -#define HDMITX_DWC_FC_VSDIEEEID0 (DWC_OFFSET_MASK + 0x1029) -#define HDMITX_DWC_FC_VSDSIZE (DWC_OFFSET_MASK + 0x102A) -#define HDMITX_DWC_FC_VSDIEEEID1 (DWC_OFFSET_MASK + 0x1030) -#define HDMITX_DWC_FC_VSDIEEEID2 (DWC_OFFSET_MASK + 0x1031) -#define HDMITX_DWC_FC_VSDPAYLOAD0 (DWC_OFFSET_MASK + 0x1032) -#define HDMITX_DWC_FC_VSDPAYLOAD1 (DWC_OFFSET_MASK + 0x1033) -#define HDMITX_DWC_FC_VSDPAYLOAD2 (DWC_OFFSET_MASK + 0x1034) -#define HDMITX_DWC_FC_VSDPAYLOAD3 (DWC_OFFSET_MASK + 0x1035) -#define HDMITX_DWC_FC_VSDPAYLOAD4 (DWC_OFFSET_MASK + 0x1036) -#define HDMITX_DWC_FC_VSDPAYLOAD5 (DWC_OFFSET_MASK + 0x1037) -#define HDMITX_DWC_FC_VSDPAYLOAD6 (DWC_OFFSET_MASK + 0x1038) -#define HDMITX_DWC_FC_VSDPAYLOAD7 (DWC_OFFSET_MASK + 0x1039) -#define HDMITX_DWC_FC_VSDPAYLOAD8 (DWC_OFFSET_MASK + 0x103A) -#define HDMITX_DWC_FC_VSDPAYLOAD9 (DWC_OFFSET_MASK + 0x103B) -#define HDMITX_DWC_FC_VSDPAYLOAD10 (DWC_OFFSET_MASK + 0x103C) -#define HDMITX_DWC_FC_VSDPAYLOAD11 (DWC_OFFSET_MASK + 0x103D) -#define HDMITX_DWC_FC_VSDPAYLOAD12 (DWC_OFFSET_MASK + 0x103E) -#define HDMITX_DWC_FC_VSDPAYLOAD13 (DWC_OFFSET_MASK + 0x103F) -#define HDMITX_DWC_FC_VSDPAYLOAD14 (DWC_OFFSET_MASK + 0x1040) -#define HDMITX_DWC_FC_VSDPAYLOAD15 (DWC_OFFSET_MASK + 0x1041) -#define HDMITX_DWC_FC_VSDPAYLOAD16 (DWC_OFFSET_MASK + 0x1042) -#define HDMITX_DWC_FC_VSDPAYLOAD17 (DWC_OFFSET_MASK + 0x1043) -#define HDMITX_DWC_FC_VSDPAYLOAD18 (DWC_OFFSET_MASK + 0x1044) -#define HDMITX_DWC_FC_VSDPAYLOAD19 (DWC_OFFSET_MASK + 0x1045) -#define HDMITX_DWC_FC_VSDPAYLOAD20 (DWC_OFFSET_MASK + 0x1046) -#define HDMITX_DWC_FC_VSDPAYLOAD21 (DWC_OFFSET_MASK + 0x1047) -#define HDMITX_DWC_FC_VSDPAYLOAD22 (DWC_OFFSET_MASK + 0x1048) -#define HDMITX_DWC_FC_VSDPAYLOAD23 (DWC_OFFSET_MASK + 0x1049) -#define HDMITX_DWC_FC_SPDVENDORNAME0 (DWC_OFFSET_MASK + 0x104A) -#define HDMITX_DWC_FC_SPDVENDORNAME1 (DWC_OFFSET_MASK + 0x104B) -#define HDMITX_DWC_FC_SPDVENDORNAME2 (DWC_OFFSET_MASK + 0x104C) -#define HDMITX_DWC_FC_SPDVENDORNAME3 (DWC_OFFSET_MASK + 0x104D) -#define HDMITX_DWC_FC_SPDVENDORNAME4 (DWC_OFFSET_MASK + 0x104E) -#define HDMITX_DWC_FC_SPDVENDORNAME5 (DWC_OFFSET_MASK + 0x104F) -#define HDMITX_DWC_FC_SPDVENDORNAME6 (DWC_OFFSET_MASK + 0x1050) -#define HDMITX_DWC_FC_SPDVENDORNAME7 (DWC_OFFSET_MASK + 0x1051) -#define HDMITX_DWC_FC_SDPPRODUCTNAME0 (DWC_OFFSET_MASK + 0x1052) -#define HDMITX_DWC_FC_SDPPRODUCTNAME1 (DWC_OFFSET_MASK + 0x1053) -#define HDMITX_DWC_FC_SDPPRODUCTNAME2 (DWC_OFFSET_MASK + 0x1054) -#define HDMITX_DWC_FC_SDPPRODUCTNAME3 (DWC_OFFSET_MASK + 0x1055) -#define HDMITX_DWC_FC_SDPPRODUCTNAME4 (DWC_OFFSET_MASK + 0x1056) -#define HDMITX_DWC_FC_SDPPRODUCTNAME5 (DWC_OFFSET_MASK + 0x1057) -#define HDMITX_DWC_FC_SDPPRODUCTNAME6 (DWC_OFFSET_MASK + 0x1058) -#define HDMITX_DWC_FC_SDPPRODUCTNAME7 (DWC_OFFSET_MASK + 0x1059) -#define HDMITX_DWC_FC_SDPPRODUCTNAME8 (DWC_OFFSET_MASK + 0x105A) -#define HDMITX_DWC_FC_SDPPRODUCTNAME9 (DWC_OFFSET_MASK + 0x105B) -#define HDMITX_DWC_FC_SDPPRODUCTNAME10 (DWC_OFFSET_MASK + 0x105C) -#define HDMITX_DWC_FC_SDPPRODUCTNAME11 (DWC_OFFSET_MASK + 0x105D) -#define HDMITX_DWC_FC_SDPPRODUCTNAME12 (DWC_OFFSET_MASK + 0x105E) -#define HDMITX_DWC_FC_SDPPRODUCTNAME13 (DWC_OFFSET_MASK + 0x105F) -#define HDMITX_DWC_FC_SDPPRODUCTNAME14 (DWC_OFFSET_MASK + 0x1060) -#define HDMITX_DWC_FC_SPDPRODUCTNAME15 (DWC_OFFSET_MASK + 0x1061) -#define HDMITX_DWC_FC_SPDDEVICEINF (DWC_OFFSET_MASK + 0x1062) -/* [7:4] aud_packet_sampflat */ -/* [ 0] aud_packet_layout */ -#define HDMITX_DWC_FC_AUDSCONF (DWC_OFFSET_MASK + 0x1063) -#define HDMITX_DWC_FC_AUDSSTAT (DWC_OFFSET_MASK + 0x1064) -/* [ 7] V3r */ -/* [ 6] V2r */ -/* [ 5] V1r */ -/* [ 4] V0r */ -/* [ 3] V3l */ -/* [ 2] V2l */ -/* [ 1] V1l */ -/* [ 0] V0l */ -#define HDMITX_DWC_FC_AUDSV (DWC_OFFSET_MASK + 0x1065) -#define HDMITX_DWC_FC_AUDSU (DWC_OFFSET_MASK + 0x1066) -#define HDMITX_DWC_FC_AUDSCHNLS0 (DWC_OFFSET_MASK + 0x1067) -#define HDMITX_DWC_FC_AUDSCHNLS1 (DWC_OFFSET_MASK + 0x1068) -#define HDMITX_DWC_FC_AUDSCHNLS2 (DWC_OFFSET_MASK + 0x1069) -#define HDMITX_DWC_FC_AUDSCHNLS3 (DWC_OFFSET_MASK + 0x106A) -#define HDMITX_DWC_FC_AUDSCHNLS4 (DWC_OFFSET_MASK + 0x106B) -#define HDMITX_DWC_FC_AUDSCHNLS5 (DWC_OFFSET_MASK + 0x106C) -#define HDMITX_DWC_FC_AUDSCHNLS6 (DWC_OFFSET_MASK + 0x106D) -#define HDMITX_DWC_FC_AUDSCHNLS7 (DWC_OFFSET_MASK + 0x106E) -#define HDMITX_DWC_FC_AUDSCHNLS8 (DWC_OFFSET_MASK + 0x106F) -#define HDMITX_DWC_FC_DATACH0FILL (DWC_OFFSET_MASK + 0x1070) -#define HDMITX_DWC_FC_DATACH1FILL (DWC_OFFSET_MASK + 0x1071) -#define HDMITX_DWC_FC_DATACH2FILL (DWC_OFFSET_MASK + 0x1072) -#define HDMITX_DWC_FC_CTRLQHIGH (DWC_OFFSET_MASK + 0x1073) -#define HDMITX_DWC_FC_CTRLQLOW (DWC_OFFSET_MASK + 0x1074) -#define HDMITX_DWC_FC_ACP0 (DWC_OFFSET_MASK + 0x1075) -#define HDMITX_DWC_FC_ACP16 (DWC_OFFSET_MASK + 0x1082) -#define HDMITX_DWC_FC_ACP15 (DWC_OFFSET_MASK + 0x1083) -#define HDMITX_DWC_FC_ACP14 (DWC_OFFSET_MASK + 0x1084) -#define HDMITX_DWC_FC_ACP13 (DWC_OFFSET_MASK + 0x1085) -#define HDMITX_DWC_FC_ACP12 (DWC_OFFSET_MASK + 0x1086) -#define HDMITX_DWC_FC_ACP11 (DWC_OFFSET_MASK + 0x1087) -#define HDMITX_DWC_FC_ACP10 (DWC_OFFSET_MASK + 0x1088) -#define HDMITX_DWC_FC_ACP9 (DWC_OFFSET_MASK + 0x1089) -#define HDMITX_DWC_FC_ACP8 (DWC_OFFSET_MASK + 0x108A) -#define HDMITX_DWC_FC_ACP7 (DWC_OFFSET_MASK + 0x108B) -#define HDMITX_DWC_FC_ACP6 (DWC_OFFSET_MASK + 0x108C) -#define HDMITX_DWC_FC_ACP5 (DWC_OFFSET_MASK + 0x108D) -#define HDMITX_DWC_FC_ACP4 (DWC_OFFSET_MASK + 0x108E) -#define HDMITX_DWC_FC_ACP3 (DWC_OFFSET_MASK + 0x108F) -#define HDMITX_DWC_FC_ACP2 (DWC_OFFSET_MASK + 0x1090) -#define HDMITX_DWC_FC_ACP1 (DWC_OFFSET_MASK + 0x1091) -#define HDMITX_DWC_FC_ISCR1_0 (DWC_OFFSET_MASK + 0x1092) -#define HDMITX_DWC_FC_ISCR1_16 (DWC_OFFSET_MASK + 0x1093) -#define HDMITX_DWC_FC_ISCR1_15 (DWC_OFFSET_MASK + 0x1094) -#define HDMITX_DWC_FC_ISCR1_14 (DWC_OFFSET_MASK + 0x1095) -#define HDMITX_DWC_FC_ISCR1_13 (DWC_OFFSET_MASK + 0x1096) -#define HDMITX_DWC_FC_ISCR1_12 (DWC_OFFSET_MASK + 0x1097) -#define HDMITX_DWC_FC_ISCR1_11 (DWC_OFFSET_MASK + 0x1098) -#define HDMITX_DWC_FC_ISCR1_10 (DWC_OFFSET_MASK + 0x1099) -#define HDMITX_DWC_FC_ISCR1_9 (DWC_OFFSET_MASK + 0x109A) -#define HDMITX_DWC_FC_ISCR1_8 (DWC_OFFSET_MASK + 0x109B) -#define HDMITX_DWC_FC_ISCR1_7 (DWC_OFFSET_MASK + 0x109C) -#define HDMITX_DWC_FC_ISCR1_6 (DWC_OFFSET_MASK + 0x109D) -#define HDMITX_DWC_FC_ISCR1_5 (DWC_OFFSET_MASK + 0x109E) -#define HDMITX_DWC_FC_ISCR1_4 (DWC_OFFSET_MASK + 0x109F) -#define HDMITX_DWC_FC_ISCR1_3 (DWC_OFFSET_MASK + 0x10A0) -#define HDMITX_DWC_FC_ISCR1_2 (DWC_OFFSET_MASK + 0x10A1) -#define HDMITX_DWC_FC_ISCR1_1 (DWC_OFFSET_MASK + 0x10A2) -#define HDMITX_DWC_FC_ISCR0_15 (DWC_OFFSET_MASK + 0x10A3) -#define HDMITX_DWC_FC_ISCR0_14 (DWC_OFFSET_MASK + 0x10A4) -#define HDMITX_DWC_FC_ISCR0_13 (DWC_OFFSET_MASK + 0x10A5) -#define HDMITX_DWC_FC_ISCR0_12 (DWC_OFFSET_MASK + 0x10A6) -#define HDMITX_DWC_FC_ISCR0_11 (DWC_OFFSET_MASK + 0x10A7) -#define HDMITX_DWC_FC_ISCR0_10 (DWC_OFFSET_MASK + 0x10A8) -#define HDMITX_DWC_FC_ISCR0_9 (DWC_OFFSET_MASK + 0x10A9) -#define HDMITX_DWC_FC_ISCR0_8 (DWC_OFFSET_MASK + 0x10AA) -#define HDMITX_DWC_FC_ISCR0_7 (DWC_OFFSET_MASK + 0x10AB) -#define HDMITX_DWC_FC_ISCR0_6 (DWC_OFFSET_MASK + 0x10AC) -#define HDMITX_DWC_FC_ISCR0_5 (DWC_OFFSET_MASK + 0x10AD) -#define HDMITX_DWC_FC_ISCR0_4 (DWC_OFFSET_MASK + 0x10AE) -#define HDMITX_DWC_FC_ISCR0_3 (DWC_OFFSET_MASK + 0x10AF) -#define HDMITX_DWC_FC_ISCR0_2 (DWC_OFFSET_MASK + 0x10B0) -#define HDMITX_DWC_FC_ISCR0_1 (DWC_OFFSET_MASK + 0x10B1) -#define HDMITX_DWC_FC_ISCR0_0 (DWC_OFFSET_MASK + 0x10B2) -/* [ 4] spd_auto */ -/* [ 3] vsd_auto */ -/* [ 2] isrc2_auto */ -/* [ 1] isrc1_auto */ -/* [ 0] acp_auto */ -#define HDMITX_DWC_FC_DATAUTO0 (DWC_OFFSET_MASK + 0x10B3) -#define HDMITX_DWC_FC_DATAUTO1 (DWC_OFFSET_MASK + 0x10B4) -#define HDMITX_DWC_FC_DATAUTO2 (DWC_OFFSET_MASK + 0x10B5) -#define HDMITX_DWC_FC_DATMAN (DWC_OFFSET_MASK + 0x10B6) -/* [ 5] nvbi_auto: insert on Vsync */ -/* [ 4] amp_auto: insert on Vsync */ -/* [ 3] avi_auto: insert on Vsync */ -/* [ 2] gcp_auto: insert on Vsync */ -/* [ 1] audi_auto: insert on Vsync */ -/* [ 0] acr_auto: insert on CTS update. Assert this bit later to avoid - * inital packets with false CTS value - */ -#define HDMITX_DWC_FC_DATAUTO3 (DWC_OFFSET_MASK + 0x10B7) -#define HDMITX_DWC_FC_RDRB0 (DWC_OFFSET_MASK + 0x10B8) -#define HDMITX_DWC_FC_RDRB1 (DWC_OFFSET_MASK + 0x10B9) -#define HDMITX_DWC_FC_RDRB2 (DWC_OFFSET_MASK + 0x10BA) -#define HDMITX_DWC_FC_RDRB3 (DWC_OFFSET_MASK + 0x10BB) -#define HDMITX_DWC_FC_RDRB4 (DWC_OFFSET_MASK + 0x10BC) -#define HDMITX_DWC_FC_RDRB5 (DWC_OFFSET_MASK + 0x10BD) -#define HDMITX_DWC_FC_RDRB6 (DWC_OFFSET_MASK + 0x10BE) -#define HDMITX_DWC_FC_RDRB7 (DWC_OFFSET_MASK + 0x10BF) -#define HDMITX_DWC_FC_RDRB8 (DWC_OFFSET_MASK + 0x10C0) -#define HDMITX_DWC_FC_RDRB9 (DWC_OFFSET_MASK + 0x10C1) -#define HDMITX_DWC_FC_RDRB10 (DWC_OFFSET_MASK + 0x10C2) -#define HDMITX_DWC_FC_RDRB11 (DWC_OFFSET_MASK + 0x10C3) -/* [ 7] AUDI_int_mask */ -/* [ 6] ACP_int_mask */ -/* [ 5] HBR_int_mask */ -/* [ 2] AUDS_int_mask */ -/* [ 1] ACR_int_mask */ -/* [ 0] NULL_int_mask */ -#define HDMITX_DWC_FC_MASK0 (DWC_OFFSET_MASK + 0x10D2) -/* [ 7] GMD_int_mask */ -/* [ 6] ISRC1_int_mask */ -/* [ 5] ISRC2_int_mask */ -/* [ 4] VSD_int_mask */ -/* [ 3] SPD_int_mask */ -/* [ 1] AVI_int_mask */ -/* [ 0] GCP_int_mask */ -#define HDMITX_DWC_FC_MASK1 (DWC_OFFSET_MASK + 0x10D6) -/* [ 1] LowPriority_fifo_full */ -/* [ 0] HighPriority_fifo_full */ -#define HDMITX_DWC_FC_MASK2 (DWC_OFFSET_MASK + 0x10DA) -/* [7:4] incoming_pr_factor */ -/* [3:0] output_pr_factor */ -#define HDMITX_DWC_FC_PRCONF (DWC_OFFSET_MASK + 0x10E0) -/* [ 4] scrambler_ucp_line */ -/* [ 0] scrambler_en. Only update this bit once we've sent SCDC message*/ -#define HDMITX_DWC_FC_SCRAMBLER_CTRL (DWC_OFFSET_MASK + 0x10E1) -#define HDMITX_DWC_FC_MULTISTREAM_CTRL (DWC_OFFSET_MASK + 0x10E2) -/* [ 6] nvbi_tx_en */ -/* [ 5] amp_tx_en */ -/* [ 4] aut_tx_en */ -/* [ 3] audi_tx_en */ -/* [ 2] avi_tx_en */ -/* [ 1] gcp_tx_en */ -/* [ 0] acr_tx_en */ -#define HDMITX_DWC_FC_PACKET_TX_EN (DWC_OFFSET_MASK + 0x10E3) -/* [ 1] actspc_hdlr_tgl */ -/* [ 0] actspc_hdlr_en */ -#define HDMITX_DWC_FC_ACTSPC_HDLR_CFG (DWC_OFFSET_MASK + 0x10E8) -#define HDMITX_DWC_FC_INVACT_2D_0 (DWC_OFFSET_MASK + 0x10E9) -/* [3:0] fc_invact_2d_0[11:8] */ -/* [7:0] fc_invact_2d_0[7:0] */ -#define HDMITX_DWC_FC_INVACT_2D_1 (DWC_OFFSET_MASK + 0x10EA) - -#define HDMITX_DWC_FC_GMD_STAT (DWC_OFFSET_MASK + 0x1100) -#define HDMITX_DWC_FC_GMD_EN (DWC_OFFSET_MASK + 0x1101) -#define HDMITX_DWC_FC_GMD_UP (DWC_OFFSET_MASK + 0x1102) -#define HDMITX_DWC_FC_GMD_CONF (DWC_OFFSET_MASK + 0x1103) -#define HDMITX_DWC_FC_GMD_HB (DWC_OFFSET_MASK + 0x1104) -#define HDMITX_DWC_FC_GMD_PB0 (DWC_OFFSET_MASK + 0x1105) -#define HDMITX_DWC_FC_GMD_PB1 (DWC_OFFSET_MASK + 0x1106) -#define HDMITX_DWC_FC_GMD_PB2 (DWC_OFFSET_MASK + 0x1107) -#define HDMITX_DWC_FC_GMD_PB3 (DWC_OFFSET_MASK + 0x1108) -#define HDMITX_DWC_FC_GMD_PB4 (DWC_OFFSET_MASK + 0x1109) -#define HDMITX_DWC_FC_GMD_PB5 (DWC_OFFSET_MASK + 0x110A) -#define HDMITX_DWC_FC_GMD_PB6 (DWC_OFFSET_MASK + 0x110B) -#define HDMITX_DWC_FC_GMD_PB7 (DWC_OFFSET_MASK + 0x110C) -#define HDMITX_DWC_FC_GMD_PB8 (DWC_OFFSET_MASK + 0x110D) -#define HDMITX_DWC_FC_GMD_PB9 (DWC_OFFSET_MASK + 0x110E) -#define HDMITX_DWC_FC_GMD_PB10 (DWC_OFFSET_MASK + 0x110F) -#define HDMITX_DWC_FC_GMD_PB11 (DWC_OFFSET_MASK + 0x1110) -#define HDMITX_DWC_FC_GMD_PB12 (DWC_OFFSET_MASK + 0x1111) -#define HDMITX_DWC_FC_GMD_PB13 (DWC_OFFSET_MASK + 0x1112) -#define HDMITX_DWC_FC_GMD_PB14 (DWC_OFFSET_MASK + 0x1113) -#define HDMITX_DWC_FC_GMD_PB15 (DWC_OFFSET_MASK + 0x1114) -#define HDMITX_DWC_FC_GMD_PB16 (DWC_OFFSET_MASK + 0x1115) -#define HDMITX_DWC_FC_GMD_PB17 (DWC_OFFSET_MASK + 0x1116) -#define HDMITX_DWC_FC_GMD_PB18 (DWC_OFFSET_MASK + 0x1117) -#define HDMITX_DWC_FC_GMD_PB19 (DWC_OFFSET_MASK + 0x1118) -#define HDMITX_DWC_FC_GMD_PB20 (DWC_OFFSET_MASK + 0x1119) -#define HDMITX_DWC_FC_GMD_PB21 (DWC_OFFSET_MASK + 0x111A) -#define HDMITX_DWC_FC_GMD_PB22 (DWC_OFFSET_MASK + 0x111B) -#define HDMITX_DWC_FC_GMD_PB23 (DWC_OFFSET_MASK + 0x111C) -#define HDMITX_DWC_FC_GMD_PB24 (DWC_OFFSET_MASK + 0x111D) -#define HDMITX_DWC_FC_GMD_PB25 (DWC_OFFSET_MASK + 0x111E) -#define HDMITX_DWC_FC_GMD_PB26 (DWC_OFFSET_MASK + 0x111F) -#define HDMITX_DWC_FC_GMD_PB27 (DWC_OFFSET_MASK + 0x1120) - -/* Audio Metadata Packet Registers */ -#define HDMITX_DWC_FC_AMP_HB01 (DWC_OFFSET_MASK + 0x1128) -#define HDMITX_DWC_FC_AMP_HB02 (DWC_OFFSET_MASK + 0x1129) -#define HDMITX_DWC_FC_AMP_PB00 (DWC_OFFSET_MASK + 0x112A) -#define HDMITX_DWC_FC_AMP_PB01 (DWC_OFFSET_MASK + 0x112B) -#define HDMITX_DWC_FC_AMP_PB02 (DWC_OFFSET_MASK + 0x112C) -#define HDMITX_DWC_FC_AMP_PB03 (DWC_OFFSET_MASK + 0x112D) -#define HDMITX_DWC_FC_AMP_PB04 (DWC_OFFSET_MASK + 0x112E) -#define HDMITX_DWC_FC_AMP_PB05 (DWC_OFFSET_MASK + 0x112F) -#define HDMITX_DWC_FC_AMP_PB06 (DWC_OFFSET_MASK + 0x1130) -#define HDMITX_DWC_FC_AMP_PB07 (DWC_OFFSET_MASK + 0x1131) -#define HDMITX_DWC_FC_AMP_PB08 (DWC_OFFSET_MASK + 0x1132) -#define HDMITX_DWC_FC_AMP_PB09 (DWC_OFFSET_MASK + 0x1133) -#define HDMITX_DWC_FC_AMP_PB10 (DWC_OFFSET_MASK + 0x1134) -#define HDMITX_DWC_FC_AMP_PB11 (DWC_OFFSET_MASK + 0x1135) -#define HDMITX_DWC_FC_AMP_PB12 (DWC_OFFSET_MASK + 0x1136) -#define HDMITX_DWC_FC_AMP_PB13 (DWC_OFFSET_MASK + 0x1137) -#define HDMITX_DWC_FC_AMP_PB14 (DWC_OFFSET_MASK + 0x1138) -#define HDMITX_DWC_FC_AMP_PB15 (DWC_OFFSET_MASK + 0x1139) -#define HDMITX_DWC_FC_AMP_PB16 (DWC_OFFSET_MASK + 0x113A) -#define HDMITX_DWC_FC_AMP_PB17 (DWC_OFFSET_MASK + 0x113B) -#define HDMITX_DWC_FC_AMP_PB18 (DWC_OFFSET_MASK + 0x113C) -#define HDMITX_DWC_FC_AMP_PB19 (DWC_OFFSET_MASK + 0x113D) -#define HDMITX_DWC_FC_AMP_PB20 (DWC_OFFSET_MASK + 0x113E) -#define HDMITX_DWC_FC_AMP_PB21 (DWC_OFFSET_MASK + 0x113F) -#define HDMITX_DWC_FC_AMP_PB22 (DWC_OFFSET_MASK + 0x1140) -#define HDMITX_DWC_FC_AMP_PB23 (DWC_OFFSET_MASK + 0x1141) -#define HDMITX_DWC_FC_AMP_PB24 (DWC_OFFSET_MASK + 0x1142) -#define HDMITX_DWC_FC_AMP_PB25 (DWC_OFFSET_MASK + 0x1143) -#define HDMITX_DWC_FC_AMP_PB26 (DWC_OFFSET_MASK + 0x1144) -#define HDMITX_DWC_FC_AMP_PB27 (DWC_OFFSET_MASK + 0x1145) - -/* NTSC VBI Packet Registers */ -#define HDMITX_DWC_FC_NVBI_HB01 (DWC_OFFSET_MASK + 0x1148) -#define HDMITX_DWC_FC_NVBI_HB02 (DWC_OFFSET_MASK + 0x1149) -#define HDMITX_DWC_FC_NVBI_PB01 (DWC_OFFSET_MASK + 0x114A) -#define HDMITX_DWC_FC_NVBI_PB02 (DWC_OFFSET_MASK + 0x114B) -#define HDMITX_DWC_FC_NVBI_PB03 (DWC_OFFSET_MASK + 0x114C) -#define HDMITX_DWC_FC_NVBI_PB04 (DWC_OFFSET_MASK + 0x114D) -#define HDMITX_DWC_FC_NVBI_PB05 (DWC_OFFSET_MASK + 0x114E) -#define HDMITX_DWC_FC_NVBI_PB06 (DWC_OFFSET_MASK + 0x114F) -#define HDMITX_DWC_FC_NVBI_PB07 (DWC_OFFSET_MASK + 0x1150) -#define HDMITX_DWC_FC_NVBI_PB08 (DWC_OFFSET_MASK + 0x1151) -#define HDMITX_DWC_FC_NVBI_PB09 (DWC_OFFSET_MASK + 0x1152) -#define HDMITX_DWC_FC_NVBI_PB10 (DWC_OFFSET_MASK + 0x1153) -#define HDMITX_DWC_FC_NVBI_PB11 (DWC_OFFSET_MASK + 0x1154) -#define HDMITX_DWC_FC_NVBI_PB12 (DWC_OFFSET_MASK + 0x1155) -#define HDMITX_DWC_FC_NVBI_PB13 (DWC_OFFSET_MASK + 0x1156) -#define HDMITX_DWC_FC_NVBI_PB14 (DWC_OFFSET_MASK + 0x1157) -#define HDMITX_DWC_FC_NVBI_PB15 (DWC_OFFSET_MASK + 0x1158) -#define HDMITX_DWC_FC_NVBI_PB16 (DWC_OFFSET_MASK + 0x1159) -#define HDMITX_DWC_FC_NVBI_PB17 (DWC_OFFSET_MASK + 0x115A) -#define HDMITX_DWC_FC_NVBI_PB18 (DWC_OFFSET_MASK + 0x115B) -#define HDMITX_DWC_FC_NVBI_PB19 (DWC_OFFSET_MASK + 0x115C) -#define HDMITX_DWC_FC_NVBI_PB20 (DWC_OFFSET_MASK + 0x115D) -#define HDMITX_DWC_FC_NVBI_PB21 (DWC_OFFSET_MASK + 0x115E) -#define HDMITX_DWC_FC_NVBI_PB22 (DWC_OFFSET_MASK + 0x115F) -#define HDMITX_DWC_FC_NVBI_PB23 (DWC_OFFSET_MASK + 0x1160) -#define HDMITX_DWC_FC_NVBI_PB24 (DWC_OFFSET_MASK + 0x1161) -#define HDMITX_DWC_FC_NVBI_PB25 (DWC_OFFSET_MASK + 0x1162) -#define HDMITX_DWC_FC_NVBI_PB26 (DWC_OFFSET_MASK + 0x1163) -#define HDMITX_DWC_FC_NVBI_PB27 (DWC_OFFSET_MASK + 0x1164) - -#define HDMITX_DWC_FC_DBGFORCE (DWC_OFFSET_MASK + 0x1200) -#define HDMITX_DWC_FC_DBGAUD0CH0 (DWC_OFFSET_MASK + 0x1201) -#define HDMITX_DWC_FC_DBGAUD1CH0 (DWC_OFFSET_MASK + 0x1202) -#define HDMITX_DWC_FC_DBGAUD2CH0 (DWC_OFFSET_MASK + 0x1203) -#define HDMITX_DWC_FC_DBGAUD0CH1 (DWC_OFFSET_MASK + 0x1204) -#define HDMITX_DWC_FC_DBGAUD1CH1 (DWC_OFFSET_MASK + 0x1205) -#define HDMITX_DWC_FC_DBGAUD2CH1 (DWC_OFFSET_MASK + 0x1206) -#define HDMITX_DWC_FC_DBGAUD0CH2 (DWC_OFFSET_MASK + 0x1207) -#define HDMITX_DWC_FC_DBGAUD1CH2 (DWC_OFFSET_MASK + 0x1208) -#define HDMITX_DWC_FC_DBGAUD2CH2 (DWC_OFFSET_MASK + 0x1209) -#define HDMITX_DWC_FC_DBGAUD0CH3 (DWC_OFFSET_MASK + 0x120A) -#define HDMITX_DWC_FC_DBGAUD1CH3 (DWC_OFFSET_MASK + 0x120B) -#define HDMITX_DWC_FC_DBGAUD2CH3 (DWC_OFFSET_MASK + 0x120C) -#define HDMITX_DWC_FC_DBGAUD0CH4 (DWC_OFFSET_MASK + 0x120D) -#define HDMITX_DWC_FC_DBGAUD1CH4 (DWC_OFFSET_MASK + 0x120E) -#define HDMITX_DWC_FC_DBGAUD2CH4 (DWC_OFFSET_MASK + 0x120F) -#define HDMITX_DWC_FC_DBGAUD0CH5 (DWC_OFFSET_MASK + 0x1210) -#define HDMITX_DWC_FC_DBGAUD1CH5 (DWC_OFFSET_MASK + 0x1211) -#define HDMITX_DWC_FC_DBGAUD2CH5 (DWC_OFFSET_MASK + 0x1212) -#define HDMITX_DWC_FC_DBGAUD0CH6 (DWC_OFFSET_MASK + 0x1213) -#define HDMITX_DWC_FC_DBGAUD1CH6 (DWC_OFFSET_MASK + 0x1214) -#define HDMITX_DWC_FC_DBGAUD2CH6 (DWC_OFFSET_MASK + 0x1215) -#define HDMITX_DWC_FC_DBGAUD0CH7 (DWC_OFFSET_MASK + 0x1216) -#define HDMITX_DWC_FC_DBGAUD1CH7 (DWC_OFFSET_MASK + 0x1217) -#define HDMITX_DWC_FC_DBGAUD2CH7 (DWC_OFFSET_MASK + 0x1218) -#define HDMITX_DWC_FC_DBGTMDS0 (DWC_OFFSET_MASK + 0x1219) -#define HDMITX_DWC_FC_DBGTMDS1 (DWC_OFFSET_MASK + 0x121A) -#define HDMITX_DWC_FC_DBGTMDS2 (DWC_OFFSET_MASK + 0x121B) - -/* HDMI Source PHY Registers */ -#define HDMITX_DWC_PHY_CONF0 (DWC_OFFSET_MASK + 0x3000) -#define HDMITX_DWC_PHY_TST0 (DWC_OFFSET_MASK + 0x3001) -#define HDMITX_DWC_PHY_TST1 (DWC_OFFSET_MASK + 0x3002) -#define HDMITX_DWC_PHY_TST2 (DWC_OFFSET_MASK + 0x3003) -#define HDMITX_DWC_PHY_STAT0 (DWC_OFFSET_MASK + 0x3004) -#define HDMITX_DWC_PHY_INT0 (DWC_OFFSET_MASK + 0x3005) -#define HDMITX_DWC_PHY_MASK0 (DWC_OFFSET_MASK + 0x3006) -#define HDMITX_DWC_PHY_POL0 (DWC_OFFSET_MASK + 0x3007) - -/* I2C Master PHY Registers */ -#define HDMITX_DWC_I2CM_PHY_SLAVE (DWC_OFFSET_MASK + 0x3020) -#define HDMITX_DWC_I2CM_PHY_ADDRESS (DWC_OFFSET_MASK + 0x3021) -#define HDMITX_DWC_I2CM_PHY_DATAO_1 (DWC_OFFSET_MASK + 0x3022) -#define HDMITX_DWC_I2CM_PHY_DATAO_0 (DWC_OFFSET_MASK + 0x3023) -#define HDMITX_DWC_I2CM_PHY_DATAI_1 (DWC_OFFSET_MASK + 0x3024) -#define HDMITX_DWC_I2CM_PHY_DATAI_0 (DWC_OFFSET_MASK + 0x3025) -#define HDMITX_DWC_I2CM_PHY_OPERATION (DWC_OFFSET_MASK + 0x3026) -#define HDMITX_DWC_I2CM_PHY_INT (DWC_OFFSET_MASK + 0x3027) -#define HDMITX_DWC_I2CM_PHY_CTLINT (DWC_OFFSET_MASK + 0x3028) -#define HDMITX_DWC_I2CM_PHY_DIV (DWC_OFFSET_MASK + 0x3029) -#define HDMITX_DWC_I2CM_PHY_SOFTRSTZ (DWC_OFFSET_MASK + 0x302A) -#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302B) -#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x302C) -#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x302D) -#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x302E) -#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302F) -#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x3030) -#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x3031) -#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x3032) -#define HDMITX_DWC_I2CM_PHY_SDA_HOLD (DWC_OFFSET_MASK + 0x3033) - -/* Audio Sampler Registers */ - - /* [ 7] sw_audio_fifo_rst */ - /* [ 5] 0=select SPDIF; 1=select I2S. */ - /* [3:0] i2s_in_en: enable it later in test.c */ - -#define HDMITX_DWC_AUD_CONF0 (DWC_OFFSET_MASK + 0x3100) -/* [4:0] i2s_width */ -/* [7:5] i2s_mode: 0=standard I2S mode */ -#define HDMITX_DWC_AUD_CONF1 (DWC_OFFSET_MASK + 0x3101) -/* [ 3] fifo_empty_mask: 0=enable int; 1=mask int. */ -/* [ 2] fifo_full_mask: 0=enable int; 1=mask int. */ -#define HDMITX_DWC_AUD_INT (DWC_OFFSET_MASK + 0x3102) - /* [ 1] NLPCM */ -#define HDMITX_DWC_AUD_CONF2 (DWC_OFFSET_MASK + 0x3103) - -/* [ 4] fifo_overrun_mask: 0=enable int; 1=mask int. - * Enable it later when audio starts. - */ -#define HDMITX_DWC_AUD_INT1 (DWC_OFFSET_MASK + 0x3104) - -#define HDMITX_DWC_AUD_N1 (DWC_OFFSET_MASK + 0x3200) -#define HDMITX_DWC_AUD_N2 (DWC_OFFSET_MASK + 0x3201) -#define HDMITX_DWC_AUD_N3 (DWC_OFFSET_MASK + 0x3202) -#define HDMITX_DWC_AUD_CTS1 (DWC_OFFSET_MASK + 0x3203) -#define HDMITX_DWC_AUD_CTS2 (DWC_OFFSET_MASK + 0x3204) -#define HDMITX_DWC_AUD_CTS3 (DWC_OFFSET_MASK + 0x3205) -#define HDMITX_DWC_AUD_INPUTCLKFS (DWC_OFFSET_MASK + 0x3206) -/* [ 7] sw_audio_fifo_rst */ -#define HDMITX_DWC_AUD_SPDIF0 (DWC_OFFSET_MASK + 0x3300) -/* [4:0] spdif_width */ -/* [ 7] setnlpcm */ -#define HDMITX_DWC_AUD_SPDIF1 (DWC_OFFSET_MASK + 0x3301) -/* [ 3] SPDIF fifo_empty_mask: 0=enable int; 1=mask int. */ -/* [ 2] SPDIF fifo_full_mask: 0=enable int; 1=mask int. */ -#define HDMITX_DWC_AUD_SPDIFINT (DWC_OFFSET_MASK + 0x3302) -/* [ 4] SPDIF fifo_overrun_mask: 0=enable int; 1=mask int. */ -#define HDMITX_DWC_AUD_SPDIFINT1 (DWC_OFFSET_MASK + 0x3303) - -/* Generic Parallel Audio Interface Registers (DWC_OFFSET_MASK + 0x3500) */ -/* Audio DMA Registers (DWC_OFFSET_MASK + 0x3600) */ - -/* Main Controller Registers */ -/* [ 6] hdcpclk_disable */ -/* [ 5] cecclk_disable */ -/* [ 4] cscclk_disable */ -/* [ 3] audclk_disable */ -/* [ 2] prepclk_disable */ -/* [ 1] tmdsclk_disable */ -/* [ 0] pixelclk_disable */ -#define HDMITX_DWC_MC_CLKDIS (DWC_OFFSET_MASK + 0x4001) -/* - * [ 7] gpaswrst_req: 0=generate reset pulse; 1=no reset. - * [ 6] cecswrst_req: 0=generate reset pulse; 1=no reset. - * [ 4] spdifswrst_req: 0=generate reset pulse; 1=no reset. - * [ 3] i2sswrst_req: 0=generate reset pulse; 1=no reset. - * [ 2] prepswrst_req: 0=generate reset pulse; 1=no reset. - * [ 1] tmdsswrst_req: 0=generate reset pulse; 1=no reset. - * [ 0] pixelswrst_req: 0=generate reset pulse; 1=no reset. - */ -#define HDMITX_DWC_MC_SWRSTZREQ (DWC_OFFSET_MASK + 0x4002) -#define HDMITX_DWC_MC_OPCTRL (DWC_OFFSET_MASK + 0x4003) -/* [ 0] CSC enable */ -#define HDMITX_DWC_MC_FLOWCTRL (DWC_OFFSET_MASK + 0x4004) -#define HDMITX_DWC_MC_PHYRSTZ (DWC_OFFSET_MASK + 0x4005) -#define HDMITX_DWC_MC_LOCKONCLOCK (DWC_OFFSET_MASK + 0x4006) - -/* Color Space Converter Registers */ -/* [ 7] csc_limit */ -#define HDMITX_DWC_CSC_CFG (DWC_OFFSET_MASK + 0x4100) -#define HDMITX_DWC_CSC_SCALE (DWC_OFFSET_MASK + 0x4101) -#define HDMITX_DWC_CSC_COEF_A1_MSB (DWC_OFFSET_MASK + 0x4102) -#define HDMITX_DWC_CSC_COEF_A1_LSB (DWC_OFFSET_MASK + 0x4103) -#define HDMITX_DWC_CSC_COEF_A2_MSB (DWC_OFFSET_MASK + 0x4104) -#define HDMITX_DWC_CSC_COEF_A2_LSB (DWC_OFFSET_MASK + 0x4105) -#define HDMITX_DWC_CSC_COEF_A3_MSB (DWC_OFFSET_MASK + 0x4106) -#define HDMITX_DWC_CSC_COEF_A3_LSB (DWC_OFFSET_MASK + 0x4107) -#define HDMITX_DWC_CSC_COEF_A4_MSB (DWC_OFFSET_MASK + 0x4108) -#define HDMITX_DWC_CSC_COEF_A4_LSB (DWC_OFFSET_MASK + 0x4109) -#define HDMITX_DWC_CSC_COEF_B1_MSB (DWC_OFFSET_MASK + 0x410A) -#define HDMITX_DWC_CSC_COEF_B1_LSB (DWC_OFFSET_MASK + 0x410B) -#define HDMITX_DWC_CSC_COEF_B2_MSB (DWC_OFFSET_MASK + 0x410C) -#define HDMITX_DWC_CSC_COEF_B2_LSB (DWC_OFFSET_MASK + 0x410D) -#define HDMITX_DWC_CSC_COEF_B3_MSB (DWC_OFFSET_MASK + 0x410E) -#define HDMITX_DWC_CSC_COEF_B3_LSB (DWC_OFFSET_MASK + 0x410F) -#define HDMITX_DWC_CSC_COEF_B4_MSB (DWC_OFFSET_MASK + 0x4110) -#define HDMITX_DWC_CSC_COEF_B4_LSB (DWC_OFFSET_MASK + 0x4111) -#define HDMITX_DWC_CSC_COEF_C1_MSB (DWC_OFFSET_MASK + 0x4112) -#define HDMITX_DWC_CSC_COEF_C1_LSB (DWC_OFFSET_MASK + 0x4113) -#define HDMITX_DWC_CSC_COEF_C2_MSB (DWC_OFFSET_MASK + 0x4114) -#define HDMITX_DWC_CSC_COEF_C2_LSB (DWC_OFFSET_MASK + 0x4115) -#define HDMITX_DWC_CSC_COEF_C3_MSB (DWC_OFFSET_MASK + 0x4116) -#define HDMITX_DWC_CSC_COEF_C3_LSB (DWC_OFFSET_MASK + 0x4117) -#define HDMITX_DWC_CSC_COEF_C4_MSB (DWC_OFFSET_MASK + 0x4118) -#define HDMITX_DWC_CSC_COEF_C4_LSB (DWC_OFFSET_MASK + 0x4119) -#define HDMITX_DWC_CSC_LIMIT_UP_MSB (DWC_OFFSET_MASK + 0x411A) -#define HDMITX_DWC_CSC_LIMIT_UP_LSB (DWC_OFFSET_MASK + 0x411B) -#define HDMITX_DWC_CSC_LIMIT_DN_MSB (DWC_OFFSET_MASK + 0x411C) -#define HDMITX_DWC_CSC_LIMIT_DN_LSB (DWC_OFFSET_MASK + 0x411D) - -/* HDCP Encryption Engine Registers */ -#define HDMITX_DWC_A_HDCPCFG0 (DWC_SEC_OFFSET_MASK + 0x5000) -/* [ 4] hdcp_lock */ -/* [ 3] dissha1check */ -/* [ 2] ph2upshiftenc */ -/* [ 1] encryptiondisable */ -/* [ 0] swresetn. Write 0 to activate, self-clear to 1. */ -#define HDMITX_DWC_A_HDCPCFG1 (DWC_SEC_OFFSET_MASK + 0x5001) -#define HDMITX_DWC_A_HDCPOBS0 (DWC_OFFSET_MASK + 0x5002) -#define HDMITX_DWC_A_HDCPOBS1 (DWC_OFFSET_MASK + 0x5003) -#define HDMITX_DWC_A_HDCPOBS2 (DWC_OFFSET_MASK + 0x5004) -#define HDMITX_DWC_A_HDCPOBS3 (DWC_OFFSET_MASK + 0x5005) -#define HDMITX_DWC_A_APIINTCLR (DWC_OFFSET_MASK + 0x5006) -#define HDMITX_DWC_A_APIINTSTAT (DWC_OFFSET_MASK + 0x5007) -/* [ 7] hdcp_engaged_int_mask */ -/* [ 6] hdcp_failed_int_mask */ -/* [ 4] i2c_nack_int_mask */ -/* [ 3] lost_arbitration_int_mask */ -/* [ 2] keepout_error_int_mask */ -/* [ 1] ksv_sha1_calc_int_mask */ -/* [ 0] ksv_access_int_mask */ -#define HDMITX_DWC_A_APIINTMSK (DWC_OFFSET_MASK + 0x5008) -/* [6:5] unencryptconf */ -/* [ 4] dataenpol */ -/* [ 3] vsyncpol */ -/* [ 1] hsyncpol */ -#define HDMITX_DWC_A_VIDPOLCFG (DWC_OFFSET_MASK + 0x5009) -#define HDMITX_DWC_A_OESSWCFG (DWC_OFFSET_MASK + 0x500A) -#define HDMITX_DWC_A_COREVERLSB (DWC_OFFSET_MASK + 0x5014) -#define HDMITX_DWC_A_COREVERMSB (DWC_OFFSET_MASK + 0x5015) -/* [ 3] sha1_fail */ -/* [ 2] ksv_ctrl_update */ -/* [ 1] Rsvd for read-only ksv_mem_access */ -/* [ 0] ksv_mem_request */ -#define HDMITX_DWC_A_KSVMEMCTRL (DWC_OFFSET_MASK + 0x5016) -#define HDMITX_DWC_HDCP_BSTATUS_0 (TOP_OFFSET_MASK + 0x2000) -#define HDMITX_DWC_HDCP_BSTATUS_1 (TOP_OFFSET_MASK + 0x2001) -#define HDMITX_DWC_HDCP_M0_0 (TOP_OFFSET_MASK + 0x2002) -#define HDMITX_DWC_HDCP_M0_1 (TOP_OFFSET_MASK + 0x2003) -#define HDMITX_DWC_HDCP_M0_2 (TOP_OFFSET_MASK + 0x2004) -#define HDMITX_DWC_HDCP_M0_3 (TOP_OFFSET_MASK + 0x2005) -#define HDMITX_DWC_HDCP_M0_4 (TOP_OFFSET_MASK + 0x2006) -#define HDMITX_DWC_HDCP_M0_5 (TOP_OFFSET_MASK + 0x2007) -#define HDMITX_DWC_HDCP_M0_6 (TOP_OFFSET_MASK + 0x2008) -#define HDMITX_DWC_HDCP_M0_7 (TOP_OFFSET_MASK + 0x2009) -#define HDMITX_DWC_HDCP_KSV (TOP_OFFSET_MASK + 0x200A) -#define HDMITX_DWC_HDCP_VH (TOP_OFFSET_MASK + 0x2285) -#define HDMITX_DWC_HDCP_REVOC_SIZE_0 (TOP_OFFSET_MASK + 0x2299) -#define HDMITX_DWC_HDCP_REVOC_SIZE_1 (TOP_OFFSET_MASK + 0x229A) -#define HDMITX_DWC_HDCP_REVOC_LIST (TOP_OFFSET_MASK + 0x229B) -#define HDMITX_DWC_HDCP_REVOC_LIST_END (TOP_OFFSET_MASK + 0x365E) - - -/* HDCP BKSV Registers */ -#define HDMITX_DWC_HDCPREG_BKSV0 (DWC_OFFSET_MASK + 0x7800) -#define HDMITX_DWC_HDCPREG_BKSV1 (DWC_OFFSET_MASK + 0x7801) -#define HDMITX_DWC_HDCPREG_BKSV2 (DWC_OFFSET_MASK + 0x7802) -#define HDMITX_DWC_HDCPREG_BKSV3 (DWC_OFFSET_MASK + 0x7803) -#define HDMITX_DWC_HDCPREG_BKSV4 (DWC_OFFSET_MASK + 0x7804) - -/* HDCP AN Registers */ -#define HDMITX_DWC_HDCPREG_ANCONF (DWC_OFFSET_MASK + 0x7805) -#define HDMITX_DWC_HDCPREG_AN0 (DWC_OFFSET_MASK + 0x7806) -#define HDMITX_DWC_HDCPREG_AN1 (DWC_OFFSET_MASK + 0x7807) -#define HDMITX_DWC_HDCPREG_AN2 (DWC_OFFSET_MASK + 0x7808) -#define HDMITX_DWC_HDCPREG_AN3 (DWC_OFFSET_MASK + 0x7809) -#define HDMITX_DWC_HDCPREG_AN4 (DWC_OFFSET_MASK + 0x780A) -#define HDMITX_DWC_HDCPREG_AN5 (DWC_OFFSET_MASK + 0x780B) -#define HDMITX_DWC_HDCPREG_AN6 (DWC_OFFSET_MASK + 0x780C) -#define HDMITX_DWC_HDCPREG_AN7 (DWC_OFFSET_MASK + 0x780D) -#define HDMITX_DWC_HDCPREG_RMLCTL (DWC_OFFSET_MASK + 0x780E) - -/* Encrypted DPK Embedded Storage Registers */ -#define HDMITX_DWC_HDCPREG_RMLSTS (DWC_OFFSET_MASK + 0x780F) -#define HDMITX_DWC_HDCPREG_SEED0 (DWC_SEC_OFFSET_MASK + 0x7810) -#define HDMITX_DWC_HDCPREG_SEED1 (DWC_SEC_OFFSET_MASK + 0x7811) -#define HDMITX_DWC_HDCPREG_DPK0 (DWC_SEC_OFFSET_MASK + 0x7812) -#define HDMITX_DWC_HDCPREG_DPK1 (DWC_SEC_OFFSET_MASK + 0x7813) -#define HDMITX_DWC_HDCPREG_DPK2 (DWC_SEC_OFFSET_MASK + 0x7814) -#define HDMITX_DWC_HDCPREG_DPK3 (DWC_SEC_OFFSET_MASK + 0x7815) -#define HDMITX_DWC_HDCPREG_DPK4 (DWC_SEC_OFFSET_MASK + 0x7816) -#define HDMITX_DWC_HDCPREG_DPK5 (DWC_SEC_OFFSET_MASK + 0x7817) -#define HDMITX_DWC_HDCPREG_DPK6 (DWC_SEC_OFFSET_MASK + 0x7818) - -/* HDCP22 Registers */ -#define HDMITX_DWC_HDCP22REG_ID (DWC_OFFSET_MASK + 0x7900) -#define HDMITX_DWC_HDCP22REG_CTRL (DWC_SEC_OFFSET_MASK + 0x7904) -#define HDMITX_DWC_HDCP22REG_CTRL1 (DWC_OFFSET_MASK + 0x7905) -#define HDMITX_DWC_HDCP22REG_STS (DWC_OFFSET_MASK + 0x7908) -#define HDMITX_DWC_HDCP22REG_MASK (DWC_OFFSET_MASK + 0x790C) -#define HDMITX_DWC_HDCP22REG_STAT (DWC_OFFSET_MASK + 0x790D) -#define HDMITX_DWC_HDCP22REG_MUTE (DWC_OFFSET_MASK + 0x790E) - - -/* ********** CEC related ********** */ - -/* CEC 2.0 Engine Registers */ -#define HDMITX_DWC_CEC_CTRL (DWC_OFFSET_MASK + 0x7D00) -#define HDMITX_DWC_CEC_INTR_MASK (DWC_OFFSET_MASK + 0x7D02) -#define HDMITX_DWC_CEC_LADD_LOW (DWC_OFFSET_MASK + 0x7D05) -#define HDMITX_DWC_CEC_LADD_HIGH (DWC_OFFSET_MASK + 0x7D06) -#define HDMITX_DWC_CEC_TX_CNT (DWC_OFFSET_MASK + 0x7D07) -#define HDMITX_DWC_CEC_RX_CNT (DWC_OFFSET_MASK + 0x7D08) -#define HDMITX_DWC_CEC_TX_DATA00 (DWC_OFFSET_MASK + 0x7D10) -#define HDMITX_DWC_CEC_TX_DATA01 (DWC_OFFSET_MASK + 0x7D11) -#define HDMITX_DWC_CEC_TX_DATA02 (DWC_OFFSET_MASK + 0x7D12) -#define HDMITX_DWC_CEC_TX_DATA03 (DWC_OFFSET_MASK + 0x7D13) -#define HDMITX_DWC_CEC_TX_DATA04 (DWC_OFFSET_MASK + 0x7D14) -#define HDMITX_DWC_CEC_TX_DATA05 (DWC_OFFSET_MASK + 0x7D15) -#define HDMITX_DWC_CEC_TX_DATA06 (DWC_OFFSET_MASK + 0x7D16) -#define HDMITX_DWC_CEC_TX_DATA07 (DWC_OFFSET_MASK + 0x7D17) -#define HDMITX_DWC_CEC_TX_DATA08 (DWC_OFFSET_MASK + 0x7D18) -#define HDMITX_DWC_CEC_TX_DATA09 (DWC_OFFSET_MASK + 0x7D19) -#define HDMITX_DWC_CEC_TX_DATA10 (DWC_OFFSET_MASK + 0x7D1A) -#define HDMITX_DWC_CEC_TX_DATA11 (DWC_OFFSET_MASK + 0x7D1B) -#define HDMITX_DWC_CEC_TX_DATA12 (DWC_OFFSET_MASK + 0x7D1C) -#define HDMITX_DWC_CEC_TX_DATA13 (DWC_OFFSET_MASK + 0x7D1D) -#define HDMITX_DWC_CEC_TX_DATA14 (DWC_OFFSET_MASK + 0x7D1E) -#define HDMITX_DWC_CEC_TX_DATA15 (DWC_OFFSET_MASK + 0x7D1F) -#define HDMITX_DWC_CEC_RX_DATA00 (DWC_OFFSET_MASK + 0x7D20) -#define HDMITX_DWC_CEC_RX_DATA01 (DWC_OFFSET_MASK + 0x7D21) -#define HDMITX_DWC_CEC_RX_DATA02 (DWC_OFFSET_MASK + 0x7D22) -#define HDMITX_DWC_CEC_RX_DATA03 (DWC_OFFSET_MASK + 0x7D23) -#define HDMITX_DWC_CEC_RX_DATA04 (DWC_OFFSET_MASK + 0x7D24) -#define HDMITX_DWC_CEC_RX_DATA05 (DWC_OFFSET_MASK + 0x7D25) -#define HDMITX_DWC_CEC_RX_DATA06 (DWC_OFFSET_MASK + 0x7D26) -#define HDMITX_DWC_CEC_RX_DATA07 (DWC_OFFSET_MASK + 0x7D27) -#define HDMITX_DWC_CEC_RX_DATA08 (DWC_OFFSET_MASK + 0x7D28) -#define HDMITX_DWC_CEC_RX_DATA09 (DWC_OFFSET_MASK + 0x7D29) -#define HDMITX_DWC_CEC_RX_DATA10 (DWC_OFFSET_MASK + 0x7D2A) -#define HDMITX_DWC_CEC_RX_DATA11 (DWC_OFFSET_MASK + 0x7D2B) -#define HDMITX_DWC_CEC_RX_DATA12 (DWC_OFFSET_MASK + 0x7D2C) -#define HDMITX_DWC_CEC_RX_DATA13 (DWC_OFFSET_MASK + 0x7D2D) -#define HDMITX_DWC_CEC_RX_DATA14 (DWC_OFFSET_MASK + 0x7D2E) -#define HDMITX_DWC_CEC_RX_DATA15 (DWC_OFFSET_MASK + 0x7D2F) -#define HDMITX_DWC_CEC_LOCK_BUF (DWC_OFFSET_MASK + 0x7D30) -#define HDMITX_DWC_CEC_WAKEUPCTRL (DWC_OFFSET_MASK + 0x7D31) - -/* I2C Master Registers(E-DDC/SCDC) */ -#define HDMITX_DWC_I2CM_SLAVE (DWC_OFFSET_MASK + 0x7E00) -#define HDMITX_DWC_I2CM_ADDRESS (DWC_OFFSET_MASK + 0x7E01) -#define HDMITX_DWC_I2CM_DATAO (DWC_OFFSET_MASK + 0x7E02) -#define HDMITX_DWC_I2CM_DATAI (DWC_OFFSET_MASK + 0x7E03) -#define HDMITX_DWC_I2CM_OPERATION (DWC_OFFSET_MASK + 0x7E04) -/* [ 2] done_mask */ -/* [ 6] read_req_mask */ -#define HDMITX_DWC_I2CM_INT (DWC_OFFSET_MASK + 0x7E05) -/* [ 6] nack_mask */ -/* [ 2] arbitration_error_mask */ -#define HDMITX_DWC_I2CM_CTLINT (DWC_OFFSET_MASK + 0x7E06) -/* [ 3] i2c_fast_mode: 0=standard mode; 1=fast mode. */ -#define HDMITX_DWC_I2CM_DIV (DWC_OFFSET_MASK + 0x7E07) -#define HDMITX_DWC_I2CM_SEGADDR (DWC_OFFSET_MASK + 0x7E08) -#define HDMITX_DWC_I2CM_SOFTRSTZ (DWC_OFFSET_MASK + 0x7E09) -#define HDMITX_DWC_I2CM_SEGPTR (DWC_OFFSET_MASK + 0x7E0A) -/* I2CM_SS_SCL_HCNT = RndUp(min_ss_scl_htime*Freq(sfrclkInMHz)/1000) */ -/* I2CM_SS_SCL_LCNT = RndUp(min_ss_scl_ltime*Freq(sfrclkInMHz)/1000) */ -/* I2CM_FS_SCL_HCNT = RndUp(min_fs_scl_htime*Freq(sfrclkInMHz)/1000) */ -/* I2CM_FS_SCL_LCNT = RndUp(min_fs_scl_ltime*Freq(sfrclkInMHz)/1000) */ -/* Where Freq(sfrclkInMHz)=24; */ -#define HDMITX_DWC_I2CM_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0B) -#define HDMITX_DWC_I2CM_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E0C) -#define HDMITX_DWC_I2CM_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E0D) -#define HDMITX_DWC_I2CM_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E0E) -#define HDMITX_DWC_I2CM_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0F) -#define HDMITX_DWC_I2CM_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E10) -#define HDMITX_DWC_I2CM_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E11) -#define HDMITX_DWC_I2CM_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E12) -#define HDMITX_DWC_I2CM_SDA_HOLD (DWC_OFFSET_MASK + 0x7E13) -/* [ 5] updt_rd_vsyncpoll_en */ -/* [ 4] read_request_en */ -/* [ 0] read_update */ -#define HDMITX_DWC_I2CM_SCDC_UPDATE (DWC_OFFSET_MASK + 0x7E14) -#define HDMITX_DWC_I2CM_READ_BUFF0 (DWC_OFFSET_MASK + 0x7E20) -#define HDMITX_DWC_I2CM_READ_BUFF1 (DWC_OFFSET_MASK + 0x7E21) -#define HDMITX_DWC_I2CM_READ_BUFF2 (DWC_OFFSET_MASK + 0x7E22) -#define HDMITX_DWC_I2CM_READ_BUFF3 (DWC_OFFSET_MASK + 0x7E23) -#define HDMITX_DWC_I2CM_READ_BUFF4 (DWC_OFFSET_MASK + 0x7E24) -#define HDMITX_DWC_I2CM_READ_BUFF5 (DWC_OFFSET_MASK + 0x7E25) -#define HDMITX_DWC_I2CM_READ_BUFF6 (DWC_OFFSET_MASK + 0x7E26) -#define HDMITX_DWC_I2CM_READ_BUFF7 (DWC_OFFSET_MASK + 0x7E27) -#define HDMITX_DWC_I2CM_SCDC_UPDATE0 (DWC_OFFSET_MASK + 0x7E30) -#define HDMITX_DWC_I2CM_SCDC_UPDATE1 (DWC_OFFSET_MASK + 0x7E31) - -#endif /* __HDMI_TX_REG_H_ */
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_set.c b/drivers/amlogic/media/vout/hdmitx/hdmitx_set.c deleted file mode 100644 index ff66fbe..0000000 --- a/drivers/amlogic/media/vout/hdmitx/hdmitx_set.c +++ /dev/null
@@ -1,2412 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/secure_apb.h> - -#include <amlogic/media/vout/hdmitx.h> -#include "hdmitx_reg.h" -#include "hdmitx_common.h" - -const static char *vend_name = "Amlogic"; /* Max 8 bytes */ -const static char *prod_desc = "MBox Meson Ref"; /* Max 16 bytes */ - -struct hdmitx_dev hdmitx_device; - -static void hdmi_tvenc_set(enum hdmi_vic vic); -extern void _udelay(unsigned int us); -static void set_tmds_clk_div40(unsigned int div40); - -#define HSYNC_POLARITY 1 /*HSYNC polarity: active high*/ -#define VSYNC_POLARITY 1 /*VSYNC polarity: active high*/ - -/*Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/ -#define TX_INPUT_COLOR_FORMAT HDMI_COLOR_FORMAT_444 -/*Pixel range: 0=limited; 1=full.*/ -#define TX_INPUT_COLOR_RANGE HDMI_COLOR_RANGE_LIM -/*Pixel range: 0=limited; 1=full.*/ -#define TX_OUTPUT_COLOR_RANGE HDMI_COLOR_RANGE_LIM - -static void hdelay(int us) -{ - _udelay(us * 1000); -} - -#define mdelay(i) hdelay(i) -#define msleep(i) hdelay(i) - -static void hdmitx_set_hw(struct hdmitx_dev *hdev); - -/*Internal functions:*/ -static void hdmitx_csc_config (unsigned char input_color_format, - unsigned char output_color_format, - unsigned char color_depth); - -static void dump_regs(void) -{ - unsigned int reg_adr; - - for (reg_adr = 0x0; reg_adr < 0x100; reg_adr ++) - printk("[0x%08lx] = 0x%lx\n", REG_BASE_HIU + (reg_adr << 2), - hd_read_reg((volatile unsigned int *)(REG_BASE_HIU + (reg_adr << 2)))); - - for (reg_adr = 0x1b00; reg_adr < (0x1b00 + 0x200); reg_adr ++) - printk("[0x%08lx] = 0x%lx\n", REG_BASE_VCBUS + (reg_adr << 2), - hd_read_reg((volatile unsigned int *)(REG_BASE_VCBUS + (reg_adr << 2)))); - - for (reg_adr = 0x2700; reg_adr < (0x2700 + 0x100); reg_adr ++) - printk("[0x%08lx] = 0x%lx\n", REG_BASE_VCBUS + (reg_adr << 2), - hd_read_reg((volatile unsigned int *)(REG_BASE_VCBUS + (reg_adr << 2)))); - - for (reg_adr = HDMITX_TOP_SW_RESET; reg_adr < - HDMITX_TOP_DDC_CNTL; reg_adr ++) - printk("[0x%08x] = 0x%X\n", reg_adr, - hdmitx_rd_reg(reg_adr)); - - for (reg_adr = HDMITX_DWC_DESIGN_ID; reg_adr < - HDMITX_DWC_A_COREVERMSB; reg_adr ++) - printk("[0x%08x] = 0x%X\n", reg_adr, - hdmitx_rd_reg(reg_adr)); - - for (reg_adr = HDMITX_DWC_HDCPREG_BKSV0; reg_adr < - HDMITX_DWC_I2CM_SCDC_UPDATE1; reg_adr ++) - printk("[0x%08x] = 0x%X\n", reg_adr, - hdmitx_rd_reg(reg_adr)); - -} - -static void hdmitx_hw_init(void) -{ - static int hw_init_flag; - - if (hw_init_flag) - return; - else - hw_init_flag = 1; - - /* Enable clocks and bring out of reset */ - - /* Enable hdmitx_sys_clk */ - /* .clk0 ( cts_oscin_clk ), */ - /* .clk1 ( fclk_div4 ), */ - /* .clk2 ( fclk_div3 ), */ - /* .clk3 ( fclk_div5 ), */ - hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0x0100, 0, 16); - - /* Enable clk81_hdmitx_pclk */ - hd_set_reg_bits(P_HHI_GCLK_MPEG2, 1, 4, 1); - - /* wire wr_enable = control[3]; */ - /* wire fifo_enable = control[2]; */ - /* assign phy_clk_en = control[1]; */ - /* Enable tmds_clk */ - /* Bring HDMITX MEM output of power down */ - hd_set_reg_bits(P_HHI_MEM_PD_REG0, 0, 8, 8); - /* reset HDMITX APB & TX & PHY */ - - hd_set_reg_bits(P_RESET0_REGISTER, 1, 19, 1); - hd_set_reg_bits(P_RESET2_REGISTER, 1, 15, 1); - hd_set_reg_bits(P_RESET2_REGISTER, 1, 2, 1); - - /* Enable APB3 fail on error */ - hdmitx_enable_apb3(); - - /* Bring out of reset */ - hdmitx_wr_reg(HDMITX_TOP_SW_RESET, 0); - _udelay(200); - /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */ - hdmitx_wr_reg(HDMITX_TOP_CLK_CNTL, 0x000000ff); - - hdmitx_wr_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff); - - hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0x00); -} - -/* - * Note: read 8 Bytes of EDID data every time - */ -static int read_edid_8bytes(unsigned char *rx_edid, unsigned char addr) -{ - unsigned int timeout = 0; - unsigned int i = 0; - /*Program SLAVE/SEGMENT/ADDR*/ - hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x50); - hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR, 0x30); - hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGPTR, 0); - hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, addr & 0xff); - hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 3); - timeout = 0; - while ((!(hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 1))) && (timeout < 3)) { - mdelay(2); - timeout ++; - } - if (timeout == 3) { - printk("ddc timeout\n"); - return 0; - } - hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 1 << 1); /*clear INT*/ - /*Read back 8 bytes*/ - for (i = 0; i < 8; i ++) { - rx_edid[i] = hdmitx_rd_reg(HDMITX_DWC_I2CM_READ_BUFF0 + i); - } - return 1; -} - -static void ddc_init(void) -{ - static int ddc_init_flag; - unsigned int data32 = 0; - - - if (ddc_init_flag) - return; - else - ddc_init_flag = 1; - - ddc_pinmux_init(); - - data32 = 0; - data32 |= (0 << 6); /*[ 6] read_req_mask*/ - data32 |= (0 << 2); /*[ 2] done_mask*/ - hdmitx_wr_reg(HDMITX_DWC_I2CM_INT, data32); - - data32 = 0; - data32 |= (0 << 6); /*[ 6] nack_mask*/ - data32 |= (0 << 2); /*[ 2] arbitration_error_mask*/ - hdmitx_wr_reg(HDMITX_DWC_I2CM_CTLINT, data32); - - data32 = 0; - data32 |= (0 << 3); /*[ 3] i2c_fast_mode: 0=standard mode; 1=fast mode.*/ - hdmitx_wr_reg(HDMITX_DWC_I2CM_DIV, data32); - - hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_1, 0); - hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0xcf); - hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_1, 0); - hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_0, 0xff); - hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_1, 0); - hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_0, 0x0f); - hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_1, 0); - hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_0, 0x20); - hdmitx_wr_reg(HDMITX_DWC_I2CM_SDA_HOLD, 0x08); - - data32 = 0; - data32 |= (0 << 5); /*[ 5] updt_rd_vsyncpoll_en*/ - data32 |= (0 << 4); /*[ 4] read_request_en scdc*/ - data32 |= (0 << 0); /*[ 0] read_update*/ - hdmitx_wr_reg(HDMITX_DWC_I2CM_SCDC_UPDATE, data32); -} - -static int hdmitx_read_edid(unsigned char *buf, unsigned char addr, unsigned char size) -{ - ddc_init(); - if ((addr + size) > 256) - return 0; - return read_edid_8bytes(buf, addr); -} - -static void scdc_rd_sink(unsigned char adr, unsigned char *val) -{ - hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x54); - hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, adr); - hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1); - _udelay(2000); - *val = (unsigned char)hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI); -} - -static void scdc_wr_sink(unsigned char adr, unsigned char val) -{ - hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x54); - hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, adr); - hdmitx_wr_reg(HDMITX_DWC_I2CM_DATAO, val); - hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 0x10); - _udelay(2000); -} - -static void scdc_prepare(unsigned int div) -{ - unsigned char rx_ver = 0; - - scdc_rd_sink(SINK_VER, &rx_ver); - if (rx_ver != 1) - scdc_rd_sink(SINK_VER, &rx_ver); /* Recheck */ - printf("rx version is %s div=%d\n", - (rx_ver == 1) ? "2.0" : "1.4 or below", - div ? 40 : 10); - - scdc_wr_sink(SOURCE_VER, 0x1); - scdc_wr_sink(SOURCE_VER, 0x1); - scdc_wr_sink(TMDS_CFG, div ? 0x3 : 0); /* TMDS 1/40 & Scramble */ - scdc_wr_sink(TMDS_CFG, div ? 0x3 : 0); /* TMDS 1/40 & Scramble */ -} - -static struct hdmi_support_mode gxbb_modes[] = { - {HDMI_3840x2160p60_16x9, "2160p60hz", 0}, - {HDMI_3840x2160p50_16x9, "2160p50hz", 0}, - {HDMI_3840x2160p30_16x9, "2160p30hz", 0}, - {HDMI_3840x2160p25_16x9, "2160p25hz", 0}, - {HDMI_3840x2160p24_16x9, "2160p24hz", 0}, - {HDMI_4096x2160p60_256x135, "smpte60hz", 0}, - {HDMI_4096x2160p50_256x135, "smpte50hz", 0}, - {HDMI_4096x2160p30_256x135, "smpte30hz", 0}, - {HDMI_4096x2160p25_256x135, "smpte25hz", 0}, - {HDMI_4096x2160p24_256x135, "smpte24hz", 0}, - {HDMI_3840x2160p60_16x9, "2160p60hz420", 1}, - {HDMI_3840x2160p50_16x9, "2160p50hz420", 1}, - {HDMI_4096x2160p50_256x135, "smpte50hz420", 1}, - {HDMI_4096x2160p60_256x135, "smpte60hz420", 1}, - {HDMI_1920x1080p60_16x9, "1080p60hz", 0}, - {HDMI_1920x1080p50_16x9, "1080p50hz", 0}, - {HDMI_1920x1080p30_16x9, "1080p30hz", 0}, - {HDMI_1920x1080p25_16x9, "1080p25hz", 0}, - {HDMI_1920x1080p24_16x9, "1080p24hz", 0}, - {HDMI_1920x1080i60_16x9, "1080i60hz", 0}, - {HDMI_1920x1080i50_16x9, "1080i50hz", 0}, - {HDMI_1280x720p60_16x9, "720p60hz", 0}, - {HDMI_1280x720p50_16x9, "720p50hz", 0}, - {HDMI_720x576p50_16x9, "576p50hz", 0}, - {HDMI_720x480p60_16x9, "480p60hz", 0}, - {HDMI_720x576i50_16x9, "576i50hz", 0}, - {HDMI_720x480i60_16x9, "480i60hz", 0}, -}; - -static void hdmitx_list_support_modes(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) - printf("%s\n", gxbb_modes[i].sname); -} - -static void hdmitx_test_bist(unsigned int mode) -{ - switch (mode) { - case 0: - hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 1, 3, 1); - hd_write_reg(P_VENC_VIDEO_TST_EN, 0); - break; - case 1: - case 2: - case 3: - hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 0, 3, 1); - hd_write_reg(P_VENC_VIDEO_TST_EN, 1); - hd_write_reg(P_VENC_VIDEO_TST_MDSEL, mode); - break; - case 10: - hdmitx_prbs(); - break; - case 11: - set_tmds_clk_div40(1); - break; - default: - pr_info("hdmitx commands have no this parameter\n"); - break; - } -} - -static void hdmitx_output_blank(unsigned int blank) -{ - if (blank == 1) - hd_write_reg(P_VPU_HDMI_DATA_OVR, - ((1 << 31) | (1 << 29) | (1 << 9))); - if (blank == 0) - hd_write_reg(P_VPU_HDMI_DATA_OVR, 0); -} - -void hdmi_tx_init(void) -{ - hdmitx_device.HWOp.get_hpd_state = hdmitx_get_hpd_state; - hdmitx_device.HWOp.read_edid = hdmitx_read_edid; - hdmitx_device.HWOp.turn_off = hdmitx_turnoff; - hdmitx_device.HWOp.list_support_modes = hdmitx_list_support_modes; - hdmitx_device.HWOp.dump_regs = dump_regs; - hdmitx_device.HWOp.test_bist = hdmitx_test_bist; - hdmitx_device.HWOp.output_blank = hdmitx_output_blank; -} - -void hdmi_tx_set(struct hdmitx_dev *hdev) -{ - hdmitx_hw_init(); - ddc_init(); - hdmitx_set_hw(hdev); - return; - -#if 0 - hdmi_tx_gate(vic); - hdmi_tx_clk(vic); - hdmi_tx_misc(vic); - hdmi_tx_enc(vic); - hdmi_tx_set_vend_spec_infofram(vic); - hdmi_tx_phy(vic); -#endif -} - -int hdmi_outputmode_check(char *mode) -{ - int i, ret = -1; - - for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) { - if (!strcmp(mode, gxbb_modes[i].sname)) { - ret = 0; - break; - } - } - - if (ret) - printf("hdmitx: outputmode[%s] is invalid\n", mode); - return ret; -} - -#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" -static void hdcp14_init(void) -{ - register long x0 asm("x0") = 0x82000012; - asm volatile( - __asmeq("%0", "x0") - "smc #0\n" - : : "r"(x0) - ); -} - -/* - * set Source Product Description InfoFrame - */ -static void hdmitx_set_spdinfo(void) -{ - int i; - - if (!(vend_name && prod_desc)) - return; - - for (i = 0; (i < 8) && vend_name[i]; i++) - hdmitx_wr_reg(HDMITX_DWC_FC_SPDVENDORNAME0 + i, vend_name[i]); - for (i = 0; (i < 16) && prod_desc[i]; i++) - hdmitx_wr_reg(HDMITX_DWC_FC_SDPPRODUCTNAME0 + i, prod_desc[i]); - hdmitx_wr_reg(HDMITX_DWC_FC_SPDDEVICEINF, 0x1); - hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 4, 1); - hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO2, 1, 4, 4); - hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1); -} - -#define NUM_INT_VSYNC INT_VEC_VIU1_VSYNC - -static unsigned long modulo(unsigned long a, unsigned long b); -static signed int to_signed(unsigned int a); - -/*Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit. - *Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420. - *Pixel range: 0=limited; 1=full. - *Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420. - *Pixel range: 0=limited; 1=full. - *0:TMDS_CLK_rate=TMDS_Character_rate; 1:TMDS_CLK_rate=TMDS_Character_rate/4, - *for TMDS_Character_rate>340Mcsc. - */ -static void config_hdmi20_tx ( enum hdmi_vic vic, struct hdmi_format_para *para, - unsigned char color_depth, unsigned char input_color_format, - unsigned char input_color_range, unsigned char output_color_format, - unsigned char output_color_range) -{ - struct hdmi_cea_timing *t = ¶->timing; - unsigned long data32; - unsigned char vid_map; - unsigned char csc_en; - unsigned char default_phase = 0; - unsigned char tmp = 0; - -#define GET_TIMING(name) (t->name) - - hdmitx_hw_init(); - - data32 = 0; - data32 |= (1 << 12); - data32 |= (0 << 8); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_TOP_BIST_CNTL, data32); - - /* Configure video */ - - /*Configure video sampler*/ - vid_map = ( input_color_format == HDMI_COLOR_FORMAT_RGB )? ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x01 : - (color_depth == HDMI_COLOR_DEPTH_30B)? 0x03 : - (color_depth == HDMI_COLOR_DEPTH_36B)? 0x05 : - 0x07) : - ((input_color_format == HDMI_COLOR_FORMAT_444) || - (input_color_format == HDMI_COLOR_FORMAT_420))? ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x09 : - (color_depth == HDMI_COLOR_DEPTH_30B)? 0x0b : - (color_depth == HDMI_COLOR_DEPTH_36B)? 0x0d : - 0x0f) : - ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x16 : - (color_depth == HDMI_COLOR_DEPTH_30B)? 0x14 : - 0x12); - - data32 = 0; - data32 |= (0 << 7); - data32 |= (vid_map << 0); - hdmitx_wr_reg(HDMITX_DWC_TX_INVID0, data32); - - data32 = 0; - data32 |= (0 << 2); - data32 |= (0 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_TX_INSTUFFING, data32); - hdmitx_wr_reg(HDMITX_DWC_TX_GYDATA0, 0x00); - hdmitx_wr_reg(HDMITX_DWC_TX_GYDATA1, 0x00); - hdmitx_wr_reg(HDMITX_DWC_TX_RCRDATA0, 0x00); - hdmitx_wr_reg(HDMITX_DWC_TX_RCRDATA1, 0x00); - hdmitx_wr_reg(HDMITX_DWC_TX_BCBDATA0, 0x00); - hdmitx_wr_reg(HDMITX_DWC_TX_BCBDATA1, 0x00); - - /* Configure Color Space Converter */ - - csc_en = (input_color_format != output_color_format) ? 1 : 0; - - data32 = 0; - data32 |= (csc_en << 0); - hdmitx_wr_reg(HDMITX_DWC_MC_FLOWCTRL, data32); - - data32 = 0; - data32 |= ((((input_color_format ==HDMI_COLOR_FORMAT_422) && - (output_color_format!=HDMI_COLOR_FORMAT_422))? 2 : 0 ) << 4); /*[5:4] intmode*/ - data32 |= ((((input_color_format !=HDMI_COLOR_FORMAT_422) && - (output_color_format==HDMI_COLOR_FORMAT_422))? 2 : 0 ) << 0); /*[1:0] decmode*/ - hdmitx_wr_reg(HDMITX_DWC_CSC_CFG, data32); - - hdmitx_csc_config(input_color_format, output_color_format, color_depth); - - /* Configure video packetizer */ - - /* Video Packet color depth and pixel repetition */ - data32 = 0; - data32 |= (((output_color_format==HDMI_COLOR_FORMAT_422)? - HDMI_COLOR_DEPTH_24B : color_depth) << 4); /*[7:4] color_depth*/ - data32 |= (0 << 0); - if ((data32 & 0xf0) == 0x40 ) - data32 &= ~(0xf << 4); - hdmitx_wr_reg(HDMITX_DWC_VP_PR_CD, data32); - if (output_color_format == HDMI_COLOR_FORMAT_422) { - switch (color_depth) { - case HDMI_COLOR_DEPTH_24B: - tmp = 4; - break; - default: - tmp = 0; - break; - } - hdmitx_set_reg_bits(HDMITX_DWC_VP_PR_CD, tmp, 4, 4); - } - - /* Video Packet Stuffing */ - data32 = 0; - data32 |= (default_phase << 5); - data32 |= (0 << 2); - data32 |= (0 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_VP_STUFF, data32); - - /* Video Packet YCC color remapping */ - data32 = 0; - hdmitx_wr_reg(HDMITX_DWC_VP_REMAP, data32); - if (output_color_format == HDMI_COLOR_FORMAT_422) { - switch (color_depth) { - case HDMI_COLOR_DEPTH_36B: - tmp = 2; - break; - case HDMI_COLOR_DEPTH_30B: - tmp = 1; - break; - case HDMI_COLOR_DEPTH_24B: - tmp = 0; - break; - } - } - hdmitx_set_reg_bits(HDMITX_DWC_VP_REMAP, tmp, 0, 2); /*[1:0] ycc422_size*/ - - /* Video Packet configuration */ - data32 = 0; - data32 |= ((((output_color_format != HDMI_COLOR_FORMAT_422) && - (color_depth == HDMI_COLOR_DEPTH_24B))? 1 : 0) << 6); /*[ 6] bypass_en*/ - data32 |= ((((output_color_format == HDMI_COLOR_FORMAT_422) || - (color_depth == HDMI_COLOR_DEPTH_24B))? 0 : 1) << 5); /*[ 5] pp_en*/ - data32 |= (0 << 4); /*[ 4] pr_en*/ - data32 |= (((output_color_format == HDMI_COLOR_FORMAT_422)? 1 : 0) << 3); /*[ 3] ycc422_en*/ - data32 |= (1 << 2); /*[ 2] pr_bypass_select*/ - data32 |= (((output_color_format == HDMI_COLOR_FORMAT_422)? 1 : - (color_depth == HDMI_COLOR_DEPTH_24B)? 2 : 0) << 0); - /*[1:0] output_selector: 0=pixel packing; 1=YCC422 remap; 2/3=8-bit bypass*/ - hdmitx_wr_reg(HDMITX_DWC_VP_CONF, data32); - - data32 = 0; - data32 |= (1 << 7); - data32 |= (1 << 6); - data32 |= (1 << 5); - data32 |= (1 << 4); - data32 |= (1 << 3); - data32 |= (1 << 2); - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_VP_MASK, data32); - - /* Configure audio */ - /* I2S Sampler config */ - - data32 = 0; - data32 |= (1 << 3); - data32 |= (1 << 2); - hdmitx_wr_reg(HDMITX_DWC_AUD_INT, data32); - - data32 = 0; - data32 |= (1 << 4); - hdmitx_wr_reg(HDMITX_DWC_AUD_INT1, data32); - - hdmitx_wr_reg(HDMITX_DWC_FC_MULTISTREAM_CTRL, 0); - -/* if enable it now, fifo_overrun will happen, because packet don't get - * sent out until initial DE detected. - */ - data32 = 0; - data32 |= (0 << 7); - data32 |= (1 << 5); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_AUD_CONF0, data32); - - data32 = 0; - data32 |= (0 << 5); - data32 |= (24 << 0); - hdmitx_wr_reg(HDMITX_DWC_AUD_CONF1, data32); - - data32 = 0; - data32 |= (0 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_AUD_CONF2, data32); - - /* spdif sampler config */ - - data32 = 0; - data32 |= (1 << 3); - data32 |= (1 << 2); - hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT, data32); - - data32 = 0; - data32 |= (0 << 4); - hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT1, data32); - - data32 = 0; - data32 |= (0 << 7); - hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF0, data32); - - data32 = 0; - data32 |= (0 << 7); - data32 |= (0 << 6); - data32 |= (24 << 0); - hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF1, data32); - - /* Frame Composer configuration */ - - /* Video definitions, as per output video(for packet gen/schedulling) */ - - data32 = 0; - data32 |= (1 << 7); - data32 |= (GET_TIMING(vsync_polarity) << 6); - data32 |= (GET_TIMING(hsync_polarity) << 5); - data32 |= (1 << 4); - data32 |= (1 << 3); - data32 |= (!(para->progress_mode) << 1); - data32 |= (!(para->progress_mode) << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_INVIDCONF, data32); - - data32 = GET_TIMING(h_active)&0xff; - hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV0, data32); - data32 = (GET_TIMING(h_active)>>8) & 0x3f; - hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV1, data32); - - data32 = GET_TIMING(h_blank) & 0xff; - hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK0, data32); - data32 = (GET_TIMING(h_blank)>>8)&0x1f; - hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK1, data32); - - data32 = GET_TIMING(v_active)&0xff; - hdmitx_wr_reg(HDMITX_DWC_FC_INVACTV0, data32); - data32 = (GET_TIMING(v_active)>>8)&0x1f; - hdmitx_wr_reg(HDMITX_DWC_FC_INVACTV1, data32); - - data32 = GET_TIMING(v_blank)&0xff; - hdmitx_wr_reg(HDMITX_DWC_FC_INVBLANK, data32); - - data32 = GET_TIMING(h_front)&0xff; - hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY0, data32); - data32 = (GET_TIMING(h_front)>>8)&0x1f; - hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY1, data32); - - data32 = GET_TIMING(h_sync)&0xff; - hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH0, data32); - data32 = (GET_TIMING(h_sync)>>8)&0x3; - hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH1, data32); - - data32 = GET_TIMING(v_front)&0xff; - hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINDELAY, data32); - - data32 = GET_TIMING(v_sync)&0x3f; - hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH, data32); - - /* control period duration (typ 12 tmds periods) */ - hdmitx_wr_reg(HDMITX_DWC_FC_CTRLDUR, 12); - /* extended control period duration (typ 32 tmds periods) */ - hdmitx_wr_reg(HDMITX_DWC_FC_EXCTRLDUR, 32); - /* max interval betwen extended control period duration (typ 50) */ - hdmitx_wr_reg(HDMITX_DWC_FC_EXCTRLSPAC, 1); - /* preamble filler */ - hdmitx_wr_reg(HDMITX_DWC_FC_CH0PREAM, 0x0b); - hdmitx_wr_reg(HDMITX_DWC_FC_CH1PREAM, 0x16); - hdmitx_wr_reg(HDMITX_DWC_FC_CH2PREAM, 0x21); - - /* write GCP packet configuration */ - data32 = 0; - data32 |= (default_phase << 2); - data32 |= (0 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_GCP, data32); - - /* write AVI Infoframe packet configuration */ - - data32 = 0; - data32 |= (((output_color_format>>2)&0x1) << 7); - data32 |= (1 << 6); - data32 |= (0 << 4); - data32 |= (0 << 2); - data32 |= (0x2 << 0); /* FIXED YCBCR 444 */ - hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF0, data32); - switch (output_color_format) { - case HDMI_COLOR_FORMAT_RGB: - tmp = 0; - break; - case HDMI_COLOR_FORMAT_422: - tmp = 1; - break; - case HDMI_COLOR_FORMAT_420: - tmp = 3; - break; - case HDMI_COLOR_FORMAT_444: - default: - tmp = 2; - break; - } - hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF0, tmp, 0, 2); - - hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF1, 0x8); - hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF2, 0); - - /* set Aspect Ratio in AVIInfo */ - switch (para->vic) { - case HDMI_640x480p60_4x3: - case HDMI_720x480p60_4x3: - case HDMI_720x480i60_4x3: - case HDMI_720x240p60_4x3: - case HDMI_2880x480i60_4x3: - case HDMI_2880x240p60_4x3: - case HDMI_1440x480p60_4x3: - case HDMI_720x576p50_4x3: - case HDMI_720x576i50_4x3: - case HDMI_720x288p_4x3: - case HDMI_2880x576i50_4x3: - case HDMI_2880x288p50_4x3: - case HDMI_1440x576p_4x3: - case HDMI_2880x480p60_4x3: - case HDMI_2880x576p50_4x3: - case HDMI_720x576p100_4x3: - case HDMI_720x576i100_4x3: - case HDMI_720x480p120_4x3: - case HDMI_720x480i120_4x3: - case HDMI_720x576p200_4x3: - case HDMI_720x576i200_4x3: - case HDMI_720x480p240_4x3: - case HDMI_720x480i240_4x3: - /* Picture Aspect Ratio M1/M0 4:3 */ - hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x1, 4, 2); - break; - default: - /* Picture Aspect Ratio M1/M0 16:9 */ - hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x2, 4, 2); - break; - } - /* Active Format Aspect Ratio R3~R0 Same as picture aspect ratio */ - hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x8, 0, 4); - - /* set Colorimetry in AVIInfo */ - switch (para->vic) { - case HDMI_640x480p60_4x3: - case HDMI_720x480p60_4x3: - case HDMI_720x480p60_16x9: - case HDMI_720x480i60_4x3: - case HDMI_720x480i60_16x9: - case HDMI_720x240p60_4x3: - case HDMI_720x240p60_16x9: - case HDMI_2880x480i60_4x3: - case HDMI_2880x480i60_16x9: - case HDMI_2880x240p60_4x3: - case HDMI_2880x240p60_16x9: - case HDMI_1440x480p60_4x3: - case HDMI_1440x480p60_16x9: - case HDMI_720x576p50_4x3: - case HDMI_720x576p50_16x9: - case HDMI_720x576i50_4x3: - case HDMI_720x576i50_16x9: - case HDMI_720x288p_4x3: - case HDMI_720x288p_16x9: - case HDMI_2880x576i50_4x3: - case HDMI_2880x576i50_16x9: - case HDMI_2880x288p50_4x3: - case HDMI_2880x288p50_16x9: - case HDMI_1440x576p_4x3: - case HDMI_1440x576p_16x9: - case HDMI_2880x480p60_4x3: - case HDMI_2880x480p60_16x9: - case HDMI_2880x576p50_4x3: - case HDMI_2880x576p50_16x9: - case HDMI_720x576p100_4x3: - case HDMI_720x576p100_16x9: - case HDMI_720x576i100_4x3: - case HDMI_720x576i100_16x9: - case HDMI_720x480p120_4x3: - case HDMI_720x480p120_16x9: - case HDMI_720x480i120_4x3: - case HDMI_720x480i120_16x9: - case HDMI_720x576p200_4x3: - case HDMI_720x576p200_16x9: - case HDMI_720x576i200_4x3: - case HDMI_720x576i200_16x9: - case HDMI_720x480p240_4x3: - case HDMI_720x480p240_16x9: - case HDMI_720x480i240_4x3: - case HDMI_720x480i240_16x9: - /* C1C0 601 , now is 709*/ - hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 1, 6, 2); - hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3); - break; - default: - /* C1C0 709 */ - hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 2, 6, 2); - hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3); - break; - } - - data32 = 0; - data32 |= (((output_color_range == HDMI_COLOR_RANGE_FUL)?1:0) << 2); /*[3:2] YQ*/ - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF3, data32); - - hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, para->vic); - -/* the audio setting bellow are only used for I2S audio IEC60958-3 frame - * insertion - */ - - /* packet queue priority (auto mode) */ - hdmitx_wr_reg(HDMITX_DWC_FC_CTRLQHIGH, 15); - hdmitx_wr_reg(HDMITX_DWC_FC_CTRLQLOW, 3); - - /* packet scheduller configuration for SPD, VSD, ISRC1/2, ACP. */ - data32 = 0; - data32 |= (0 << 4); - data32 |= (0 << 3); - data32 |= (0 << 2); - data32 |= (0 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO0, data32); - hdmitx_set_spdinfo(); - hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_DATMAN, 0); - - /* packet scheduller configuration for AVI, GCP, AUDI, ACR. */ - data32 = 0; - data32 |= (0 << 5); - data32 |= (0 << 4); - data32 |= (0 << 3); - data32 |= (1 << 2); - data32 |= (1 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO3, data32); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB0, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB1, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB2, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB3, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB4, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB5, 0); - /* AVI info usb RDRB mode and place in line 10*/ - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB6, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB7, 0x1a); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB8, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB9, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB10, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_RDRB11, 0); - - /* Packet transmission enable */ - data32 = 0; - data32 |= (0 << 6); - data32 |= (0 << 5); - data32 |= (0 << 4); - data32 |= (1 << 3); - data32 |= (1 << 2); - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_PACKET_TX_EN, data32); - - /* For 3D video */ - data32 = 0; - data32 |= (0 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_ACTSPC_HDLR_CFG, data32); - - data32 = GET_TIMING(v_active)&0xff; - hdmitx_wr_reg(HDMITX_DWC_FC_INVACT_2D_0, data32); - data32 = (GET_TIMING(v_active)>>8)&0xf; - hdmitx_wr_reg(HDMITX_DWC_FC_INVACT_2D_1, data32); - - /* Do not enable these interrupt below, we can check them at RX side. */ - data32 = 0; - data32 |= (1 << 7); - data32 |= (1 << 6); - data32 |= (1 << 5); - data32 |= (1 << 2); - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_MASK0, data32); - - data32 = 0; - data32 |= (1 << 7); - data32 |= (1 << 6); - data32 |= (1 << 5); - data32 |= (1 << 4); - data32 |= (1 << 3); - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_MASK1, data32); - - data32 = 0; - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_MASK2, data32); - - /* Pixel repetition ratio the input and output video */ - data32 = 0; - data32 |= ((para->pixel_repetition_factor+1) << 4); - data32 |= (para->pixel_repetition_factor << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_PRCONF, data32); - - /* Configure HDCP */ - data32 = 0; - data32 |= (0 << 7); - data32 |= (0 << 6); - data32 |= (0 << 4); - data32 |= (0 << 3); - data32 |= (0 << 2); - data32 |= (0 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_A_APIINTMSK, data32); - - data32 = 0; - data32 |= (0 << 5); - data32 |= (1 << 4); - data32 |= (1 << 3); - data32 |= (1 << 1); - hdmitx_wr_reg(HDMITX_DWC_A_VIDPOLCFG, data32); - - hdmitx_wr_reg(HDMITX_DWC_A_OESSWCFG, 0x40); - - hdcp14_init(); - - /* Interrupts */ - /* Clear interrupts */ - hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT0, 0xff); - hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT1, 0xff); - hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT2, 0xff); - hdmitx_wr_reg(HDMITX_DWC_IH_AS_STAT0, 0xff); - hdmitx_wr_reg(HDMITX_DWC_IH_PHY_STAT0, 0xff); - hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0xff); - hdmitx_wr_reg(HDMITX_DWC_IH_CEC_STAT0, 0xff); - hdmitx_wr_reg(HDMITX_DWC_IH_VP_STAT0, 0xff); - hdmitx_wr_reg(HDMITX_DWC_IH_I2CMPHY_STAT0, 0xff); - hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, 0xff); - hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_STAT, 0xff); - - hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, 0x0000001f); - - /* Selectively enable/mute interrupt sources */ - data32 = 0; - data32 |= (1 << 7); - data32 |= (1 << 6); - data32 |= (1 << 5); - data32 |= (1 << 4); - data32 |= (1 << 3); - data32 |= (1 << 2); - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT0, data32); - - data32 = 0; - data32 |= (1 << 7); - data32 |= (1 << 6); - data32 |= (1 << 5); - data32 |= (1 << 4); - data32 |= (1 << 3); - data32 |= (1 << 2); - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT1, data32); - - data32 = 0; - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT2, data32); - - data32 = 0; - data32 |= (0 << 4); - data32 |= (0 << 3); - data32 |= (1 << 2); - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_AS_STAT0, data32); - - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_PHY_STAT0, 0x3f); - - data32 = 0; - data32 |= (0 << 2); - data32 |= (1 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CM_STAT0, data32); - - data32 = 0; - data32 |= (0 << 6); - data32 |= (0 << 5); - data32 |= (0 << 4); - data32 |= (0 << 3); - data32 |= (0 << 2); - data32 |= (0 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_CEC_STAT0, data32); - - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_VP_STAT0, 0xff); - - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0, 0x03); - - data32 = 0; - data32 |= (0 << 1); - data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_IH_MUTE, data32); - - data32 = 0; - data32 |= (1 << 4); - data32 |= (1 << 3); - data32 |= (1 << 2); - data32 |= (1 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_TOP_INTR_MASKN, data32); - - /* Reset pulse */ - hdmitx_rd_check_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff, 0x9f); - - hd_write_reg(P_ENCP_VIDEO_EN, 0); - hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0xdf); - - hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0); - mdelay(10); - - data32 = 0; - data32 |= (1 << 7); - data32 |= (1 << 6); - data32 |= (1 << 4); - data32 |= (1 << 3); - data32 |= (1 << 2); - data32 |= (0 << 1); - data32 |= (1 << 0); - hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, data32); - hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH, - hdmitx_rd_reg(HDMITX_DWC_FC_VSYNCINWIDTH)); - - hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0); - hd_write_reg(P_ENCP_VIDEO_EN, 0xff); -} /* config_hdmi20_tx */ - -/* Set TV encoder for HDMI */ -static void hdmitx_enc(enum hdmi_vic vic) -{ - set_vmode_enc_hw(vic); - hdmi_tvenc_set(vic); - return; -} - -static void hdmitx_set_pll(struct hdmitx_dev *hdev) -{ - hdmitx_set_clk(hdev); -} - -/* - * mode: 1 means Progressive; 0 means interlaced - */ -static void enc_vpu_bridge_reset(int mode) -{ - unsigned int wr_clk = 0; - - printk("%s[%d]\n", __func__, __LINE__); - wr_clk = (hd_read_reg(P_VPU_HDMI_SETTING) & 0xf00) >> 8; - if (mode) { - hd_write_reg(P_ENCP_VIDEO_EN, 0); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/ - hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/ - mdelay(1); - hd_write_reg(P_ENCP_VIDEO_EN, 1); - mdelay(1); - hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4); - mdelay(1); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 2, 0, 2); /*[ 0] src_sel_enci: Enable ENCP output to HDMI*/ - } else { - hd_write_reg(P_ENCI_VIDEO_EN, 0); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2); /*[ 0] src_sel_enci: Disable ENCI output to HDMI*/ - hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/ - mdelay(1); - hd_write_reg(P_ENCI_VIDEO_EN, 1); - mdelay(1); - hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4); - mdelay(1); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 2); /*[ 0] src_sel_enci: Enable ENCI output to HDMI*/ - } -} - -static void hdmi_tvenc1080i_set(enum hdmi_vic vic) -{ - unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; - unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0, - PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0; - unsigned FRONT_PORCH = 88, HSYNC_PIXELS = 0, ACTIVE_LINES = 0, - INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0, - VSYNC_LINES = 0; - unsigned LINES_F0 = 0, LINES_F1 = 563, BACK_PORCH = 0; - - unsigned long total_pixels_venc = 0; - unsigned long active_pixels_venc = 0; - unsigned long front_porch_venc = 0; - unsigned long hsync_pixels_venc = 0; - - unsigned long de_h_begin = 0, de_h_end = 0; - unsigned long de_v_begin_even = 0, de_v_end_even = 0, - de_v_begin_odd = 0, de_v_end_odd = 0; - unsigned long hs_begin = 0, hs_end = 0; - unsigned long vs_adjust = 0; - unsigned long vs_bline_evn = 0, vs_eline_evn = 0, - vs_bline_odd = 0, vs_eline_odd = 0; - unsigned long vso_begin_evn = 0, vso_begin_odd = 0; - - if ((vic == HDMI_1920x1080i60_16x9) || - (vic == HDMI_1920x1080i120_16x9)) { - INTERLACE_MODE = 1; - PIXEL_REPEAT_VENC = 1; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); - LINES_F0 = 562; - LINES_F1 = 563; - FRONT_PORCH = 88; - HSYNC_PIXELS = 44; - BACK_PORCH = 148; - VSYNC_LINES = 5; - SOF_LINES = 15; - } else if ((vic == HDMI_1920x1080i50_16x9) || - (vic == HDMI_1920x1080i100_16x9)) { - INTERLACE_MODE = 1; - PIXEL_REPEAT_VENC = 1; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); - LINES_F0 = 562; - LINES_F1 = 563; - FRONT_PORCH = 528; - HSYNC_PIXELS = 44; - BACK_PORCH = 148; - VSYNC_LINES = 5; - SOF_LINES = 15; - } - TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); - TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE)); - - total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - hsync_pixels_venc = - (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC); - - hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14)); - - /* Program DE timing */ - de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) + - VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); - de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); - hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); - hd_write_reg(P_ENCP_DE_H_END, de_h_end); - /* Program DE timing for even field */ - de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE); - de_v_end_even = de_v_begin_even + ACTIVE_LINES; - hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); - hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); - /* Program DE timing for odd field if needed */ - if (INTERLACE_MODE) { - de_v_begin_odd = to_signed(( - hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4) - + de_v_begin_even + (TOTAL_LINES-1)/2; - de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; - hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);/* 583 */ - hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd); /* 1123 */ - } - - /* Program Hsync timing */ - if (de_h_end + front_porch_venc >= total_pixels_venc) { - hs_begin = de_h_end + front_porch_venc - total_pixels_venc; - vs_adjust = 1; - } else { - hs_begin = de_h_end + front_porch_venc; - vs_adjust = 0; - } - hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); - hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin); - hd_write_reg(P_ENCP_DVI_HSO_END, hs_end); - - /* Program Vsync timing for even field */ - if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust)) - vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES - - (1-vs_adjust); - else - vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES - - VSYNC_LINES - (1-vs_adjust); - - vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); - hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 0 */ - hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 5 */ - vso_begin_evn = hs_begin; /* 2 */ - hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 2 */ - hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 2 */ - /* Program Vsync timing for odd field if needed */ - if (INTERLACE_MODE) { - vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES; - vs_eline_odd = de_v_begin_odd-1 - SOF_LINES; - vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), - total_pixels_venc); - hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd); - hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd); - hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd); - hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd); - } - - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | - (HSYNC_POLARITY << 2) | - (VSYNC_POLARITY << 3) | - (0 << 4) | - (4 << 5) | - (0 << 8) | - (0 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); - -} - -static void hdmi_tvenc4k2k_set(enum hdmi_vic vic) -{ - unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; - unsigned long TOTAL_PIXELS = 4400, PIXEL_REPEAT_HDMI = 0, - PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 3840; - unsigned FRONT_PORCH = 1020, HSYNC_PIXELS = 0, ACTIVE_LINES = 2160, - INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0, - VSYNC_LINES = 0; - unsigned LINES_F0 = 2250, LINES_F1 = 2250, BACK_PORCH = 0; - - unsigned long total_pixels_venc = 0; - unsigned long active_pixels_venc = 0; - unsigned long front_porch_venc = 0; - unsigned long hsync_pixels_venc = 0; - - unsigned long de_h_begin = 0, de_h_end = 0; - unsigned long de_v_begin_even = 0, de_v_end_even = 0, - de_v_begin_odd = 0, de_v_end_odd = 0; - unsigned long hs_begin = 0, hs_end = 0; - unsigned long vs_adjust = 0; - unsigned long vs_bline_evn = 0, vs_eline_evn = 0, vs_bline_odd = 0, - vs_eline_odd = 0; - unsigned long vso_begin_evn = 0, vso_begin_odd = 0; - - switch (vic) { - case HDMI_3840x2160p30_16x9: - case HDMI_3840x2160p60_16x9: - case HDMI_3840x2160p60_16x9_Y420: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); - LINES_F0 = 2250; - LINES_F1 = 2250; - FRONT_PORCH = 176; - HSYNC_PIXELS = 88; - BACK_PORCH = 296; - VSYNC_LINES = 10; - SOF_LINES = 72 + 1; - break; - case HDMI_3840x2160p25_16x9: - case HDMI_3840x2160p50_16x9: - case HDMI_3840x2160p50_16x9_Y420: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); - LINES_F0 = 2250; - LINES_F1 = 2250; - FRONT_PORCH = 1056; - HSYNC_PIXELS = 88; - BACK_PORCH = 296; - VSYNC_LINES = 10; - SOF_LINES = 72 + 1; - break; - case HDMI_3840x2160p24_16x9: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); - LINES_F0 = 2250; - LINES_F1 = 2250; - FRONT_PORCH = 1276; - HSYNC_PIXELS = 88; - BACK_PORCH = 296; - VSYNC_LINES = 10; - SOF_LINES = 72 + 1; - break; - case HDMI_4096x2160p24_256x135: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); - LINES_F0 = 2250; - LINES_F1 = 2250; - FRONT_PORCH = 1020; - HSYNC_PIXELS = 88; - BACK_PORCH = 296; - VSYNC_LINES = 10; - SOF_LINES = 72 + 1; - break; - case HDMI_4096x2160p25_256x135: - case HDMI_4096x2160p50_256x135: - case HDMI_4096x2160p50_256x135_Y420: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); - LINES_F0 = 2250; - LINES_F1 = 2250; - FRONT_PORCH = 968; - HSYNC_PIXELS = 88; - BACK_PORCH = 128; - VSYNC_LINES = 10; - SOF_LINES = 72; - break; - case HDMI_4096x2160p30_256x135: - case HDMI_4096x2160p60_256x135: - case HDMI_4096x2160p60_256x135_Y420: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (2160/(1+INTERLACE_MODE)); - LINES_F0 = 2250; - LINES_F1 = 2250; - FRONT_PORCH = 88; - HSYNC_PIXELS = 88; - BACK_PORCH = 128; - VSYNC_LINES = 10; - SOF_LINES = 72; - break; - default: - printk("hdmitx20: no setting for VIC = %d\n", vic); - break; - } - - TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); - TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE)); - - total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - - de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) + - VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); - de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); - hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); - hd_write_reg(P_ENCP_DE_H_END, de_h_end); - /* Program DE timing for even field */ - de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE); - de_v_end_even = modulo(de_v_begin_even + ACTIVE_LINES, TOTAL_LINES); - hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); - hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); - /* Program DE timing for odd field if needed */ - if (INTERLACE_MODE) { - de_v_begin_odd = to_signed( - (hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4) - + de_v_begin_even + (TOTAL_LINES-1)/2; - de_v_end_odd = modulo(de_v_begin_odd + ACTIVE_LINES, - TOTAL_LINES); - hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd); - hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd); - } - - /* Program Hsync timing */ - if (de_h_end + front_porch_venc >= total_pixels_venc) { - hs_begin = de_h_end + front_porch_venc - total_pixels_venc; - vs_adjust = 1; - } else { - hs_begin = de_h_end + front_porch_venc; - vs_adjust = 1; - } - hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); - hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin); - hd_write_reg(P_ENCP_DVI_HSO_END, hs_end); - - /* Program Vsync timing for even field */ - if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust)) - vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES - - (1-vs_adjust); - else - vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES - - VSYNC_LINES - (1-vs_adjust); - vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); - hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); - hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); - vso_begin_evn = hs_begin; - hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); - hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); - /* Program Vsync timing for odd field if needed */ - if (INTERLACE_MODE) { - vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES; - vs_eline_odd = de_v_begin_odd-1 - SOF_LINES; - vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), - total_pixels_venc); - hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd); - hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd); - hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd); - hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd); - } - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | - (HSYNC_POLARITY << 2) | - (VSYNC_POLARITY << 3) | - (0 << 4) | - (4 << 5) | - (0 << 8) | - (0 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); - hd_write_reg(P_ENCP_VIDEO_EN, 1); -} - -static void hdmi_tvenc480i_set(enum hdmi_vic vic) -{ - unsigned long VFIFO2VD_TO_HDMI_LATENCY = 1; - unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0, - PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0; - unsigned FRONT_PORCH = 38, HSYNC_PIXELS = 124, ACTIVE_LINES = 0, - INTERLACE_MODE = 0, VSYNC_LINES = 0; - unsigned LINES_F0 = 262, LINES_F1 = 263, BACK_PORCH = 114, - EOF_LINES = 2; - - unsigned long total_pixels_venc = 0; - unsigned long active_pixels_venc = 0; - unsigned long front_porch_venc = 0; - unsigned long hsync_pixels_venc = 0; - - unsigned long de_h_begin = 0, de_h_end = 0; - unsigned long de_v_begin_even = 0, de_v_end_even = 0, - de_v_begin_odd = 0, de_v_end_odd = 0; - unsigned long hs_begin = 0, hs_end = 0; - unsigned long vs_adjust = 0; - unsigned long vs_bline_evn = 0, vs_eline_evn = 0, - vs_bline_odd = 0, vs_eline_odd = 0; - unsigned long vso_begin_evn = 0, vso_begin_odd = 0; - - hd_set_reg_bits(P_HHI_GCLK_OTHER, 1, 8, 1); - switch (vic) { - case HDMI_720x480i60_16x9: - INTERLACE_MODE = 1; - PIXEL_REPEAT_VENC = 1; - PIXEL_REPEAT_HDMI = 1; - ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (480/(1+INTERLACE_MODE)); - LINES_F0 = 262; - LINES_F1 = 263; - FRONT_PORCH = 38; - HSYNC_PIXELS = 124; - BACK_PORCH = 114; - EOF_LINES = 4; - VSYNC_LINES = 3; - break; - case HDMI_720x576i50_16x9: - INTERLACE_MODE = 1; - PIXEL_REPEAT_VENC = 1; - PIXEL_REPEAT_HDMI = 1; - ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (576/(1+INTERLACE_MODE)); - LINES_F0 = 312; - LINES_F1 = 313; - FRONT_PORCH = 24; - HSYNC_PIXELS = 126; - BACK_PORCH = 138; - EOF_LINES = 2; - VSYNC_LINES = 3; - break; - default: - break; - } - - TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); - - total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); /* 1716 / 2 * 2 = 1716 */ - active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); /* 38 / 2 * 2 = 38 */ - hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); /* 124 / 2 * 2 = 124 */ - - de_h_begin = modulo(hd_read_reg(P_ENCI_VFIFO2VD_PIXEL_START) + - VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); - de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); - hd_write_reg(P_ENCI_DE_H_BEGIN, de_h_begin); /* 235 */ - hd_write_reg(P_ENCI_DE_H_END, de_h_end); /* 1675 */ - - de_v_begin_even = hd_read_reg(P_ENCI_VFIFO2VD_LINE_TOP_START); - de_v_end_even = de_v_begin_even + ACTIVE_LINES; - de_v_begin_odd = hd_read_reg(P_ENCI_VFIFO2VD_LINE_BOT_START); - de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; - hd_write_reg(P_ENCI_DE_V_BEGIN_EVEN, de_v_begin_even); - hd_write_reg(P_ENCI_DE_V_END_EVEN, de_v_end_even); - hd_write_reg(P_ENCI_DE_V_BEGIN_ODD, de_v_begin_odd); - hd_write_reg(P_ENCI_DE_V_END_ODD, de_v_end_odd); - - /* Program Hsync timing */ - if (de_h_end + front_porch_venc >= total_pixels_venc) { - hs_begin = de_h_end + front_porch_venc - total_pixels_venc; - vs_adjust = 1; - } else { - hs_begin = de_h_end + front_porch_venc; - vs_adjust = 0; - } - hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); - hd_write_reg(P_ENCI_DVI_HSO_BEGIN, hs_begin); /* 1713 */ - hd_write_reg(P_ENCI_DVI_HSO_END, hs_end); /* 121 */ - - /* Program Vsync timing for even field */ - if (de_v_end_odd-1 + EOF_LINES + vs_adjust >= LINES_F1) { - vs_bline_evn = de_v_end_odd-1 + EOF_LINES + vs_adjust - - LINES_F1; - vs_eline_evn = vs_bline_evn + VSYNC_LINES; - hd_write_reg(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn); - /* vso_bline_evn_reg_wr_cnt ++; */ - hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn); - /* vso_eline_evn_reg_wr_cnt ++; */ - hd_write_reg(P_ENCI_DVI_VSO_BEGIN_EVN, hs_begin); - hd_write_reg(P_ENCI_DVI_VSO_END_EVN, hs_begin); - } else { - vs_bline_odd = de_v_end_odd-1 + EOF_LINES + vs_adjust; - hd_write_reg(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd); - /* vso_bline_odd_reg_wr_cnt ++; */ - hd_write_reg(P_ENCI_DVI_VSO_BEGIN_ODD, hs_begin); - if (vs_bline_odd + VSYNC_LINES >= LINES_F1) { - vs_eline_evn = vs_bline_odd + VSYNC_LINES - LINES_F1; - hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn); - /* vso_eline_evn_reg_wr_cnt ++; */ - hd_write_reg(P_ENCI_DVI_VSO_END_EVN, hs_begin); - } else { - vs_eline_odd = vs_bline_odd + VSYNC_LINES; - hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd); - /* vso_eline_odd_reg_wr_cnt ++; */ - hd_write_reg(P_ENCI_DVI_VSO_END_ODD, hs_begin); - } - } - /* Program Vsync timing for odd field */ - if (de_v_end_even-1 + EOF_LINES + 1 >= LINES_F0) { - vs_bline_odd = de_v_end_even-1 + EOF_LINES + 1 - LINES_F0; - vs_eline_odd = vs_bline_odd + VSYNC_LINES; - hd_write_reg(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd); - /* vso_bline_odd_reg_wr_cnt ++; */ - hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd); - /* vso_eline_odd_reg_wr_cnt ++; */ - vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), - total_pixels_venc); - hd_write_reg(P_ENCI_DVI_VSO_BEGIN_ODD, vso_begin_odd); - hd_write_reg(P_ENCI_DVI_VSO_END_ODD, vso_begin_odd); - } else { - vs_bline_evn = de_v_end_even-1 + EOF_LINES + 1; - hd_write_reg(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 261 */ - /* vso_bline_evn_reg_wr_cnt ++; */ - vso_begin_evn = modulo(hs_begin + (total_pixels_venc>>1), - total_pixels_venc); - hd_write_reg(P_ENCI_DVI_VSO_BEGIN_EVN, vso_begin_evn); - if (vs_bline_evn + VSYNC_LINES >= LINES_F0) { - vs_eline_odd = vs_bline_evn + VSYNC_LINES - LINES_F0; - hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd); - /* vso_eline_odd_reg_wr_cnt ++; */ - hd_write_reg(P_ENCI_DVI_VSO_END_ODD, vso_begin_evn); - } else { - vs_eline_evn = vs_bline_evn + VSYNC_LINES; - hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn); - /* vso_eline_evn_reg_wr_cnt ++; */ - hd_write_reg(P_ENCI_DVI_VSO_END_EVN, vso_begin_evn); - } - } - - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | - (0 << 2) | - (0 << 3) | - (0 << 4) | - (4 << 5) | - (1 << 8) | - (1 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); -} - -static void hdmi_tvenc_set_def(enum hdmi_vic vic) -{ - unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2; - unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0, - PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0; - unsigned FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0, - INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0, - VSYNC_LINES = 0; - unsigned LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0; - - unsigned long total_pixels_venc = 0; - unsigned long active_pixels_venc = 0; - unsigned long front_porch_venc = 0; - unsigned long hsync_pixels_venc = 0; - - unsigned long de_h_begin = 0, de_h_end = 0; - unsigned long de_v_begin_even = 0, de_v_end_even = 0, - de_v_begin_odd = 0, de_v_end_odd = 0; - unsigned long hs_begin = 0, hs_end = 0; - unsigned long vs_adjust = 0; - unsigned long vs_bline_evn = 0, vs_eline_evn = 0, - vs_bline_odd = 0, vs_eline_odd = 0; - unsigned long vso_begin_evn = 0, vso_begin_odd = 0; - - switch (vic) { - case HDMI_720x480p60_16x9: - case HDMI_720x480p120_16x9: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 1; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (480/(1+INTERLACE_MODE)); - LINES_F0 = 525; - LINES_F1 = 525; - FRONT_PORCH = 16; - HSYNC_PIXELS = 62; - BACK_PORCH = 60; - VSYNC_LINES = 6; - SOF_LINES = 30; - break; - case HDMI_720x576p50_16x9: - case HDMI_720x576p100_16x9: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 1; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (576/(1+INTERLACE_MODE)); - LINES_F0 = 625; - LINES_F1 = 625; - FRONT_PORCH = 12; - HSYNC_PIXELS = 64; - BACK_PORCH = 68; - VSYNC_LINES = 5; - SOF_LINES = 39; - break; - case HDMI_1280x720p60_16x9: - case HDMI_1280x720p120_16x9: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 1; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (720/(1+INTERLACE_MODE)); - LINES_F0 = 750; - LINES_F1 = 750; - FRONT_PORCH = 110; - HSYNC_PIXELS = 40; - BACK_PORCH = 220; - VSYNC_LINES = 5; - SOF_LINES = 20; - break; - case HDMI_1280x720p50_16x9: - case HDMI_1280x720p100_16x9: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 1; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (720/(1+INTERLACE_MODE)); - LINES_F0 = 750; - LINES_F1 = 750; - FRONT_PORCH = 440; - HSYNC_PIXELS = 40; - BACK_PORCH = 220; - VSYNC_LINES = 5; - SOF_LINES = 20; - break; - case HDMI_1920x1080p50_16x9: - case HDMI_1920x1080p25_16x9: - case HDMI_1920x1080p100_16x9: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); - LINES_F0 = 1125; - LINES_F1 = 1125; - FRONT_PORCH = 528; - HSYNC_PIXELS = 44; - BACK_PORCH = 148; - VSYNC_LINES = 5; - SOF_LINES = 36; - break; - case HDMI_1920x1080p24_16x9: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); - LINES_F0 = 1125; - LINES_F1 = 1125; - FRONT_PORCH = 638; - HSYNC_PIXELS = 44; - BACK_PORCH = 148; - VSYNC_LINES = 5; - SOF_LINES = 36; - break; - case HDMI_1920x1080p60_16x9: - case HDMI_1920x1080p30_16x9: - case HDMI_1920x1080p120_16x9: - INTERLACE_MODE = 0; - PIXEL_REPEAT_VENC = 0; - PIXEL_REPEAT_HDMI = 0; - ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI)); - ACTIVE_LINES = (1080/(1+INTERLACE_MODE)); - LINES_F0 = 1125; - LINES_F1 = 1125; - FRONT_PORCH = 88; - HSYNC_PIXELS = 44; - BACK_PORCH = 148; - VSYNC_LINES = 5; - SOF_LINES = 36; - break; - default: - break; - } - - TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS); - TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE)); - - total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * - (1+PIXEL_REPEAT_VENC); - - hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14)); - /* Program DE timing */ - de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) + - VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc); - de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc); - hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); /* 220 */ - hd_write_reg(P_ENCP_DE_H_END, de_h_end); /* 1660 */ - /* Program DE timing for even field */ - de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE); - de_v_end_even = de_v_begin_even + ACTIVE_LINES; - hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even); - hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */ - /* Program DE timing for odd field if needed */ - if (INTERLACE_MODE) { - de_v_begin_odd = to_signed( - (hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) - & 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2; - de_v_end_odd = de_v_begin_odd + ACTIVE_LINES; - hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd); - hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd); - } - - /* Program Hsync timing */ - if (de_h_end + front_porch_venc >= total_pixels_venc) { - hs_begin = de_h_end + front_porch_venc - total_pixels_venc; - vs_adjust = 1; - } else { - hs_begin = de_h_end + front_porch_venc; - vs_adjust = 0; - } - hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc); - hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin); - hd_write_reg(P_ENCP_DVI_HSO_END, hs_end); - - /* Program Vsync timing for even field */ - if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust)) - vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES - - (1-vs_adjust); - else - vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES - - VSYNC_LINES - (1-vs_adjust); - vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES); - hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 5 */ - hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 11 */ - vso_begin_evn = hs_begin; /* 1692 */ - hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */ - hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */ - /* Program Vsync timing for odd field if needed */ - if (INTERLACE_MODE) { - vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES; - vs_eline_odd = de_v_begin_odd-1 - SOF_LINES; - vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1), - total_pixels_venc); - hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd); - hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd); - hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd); - hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd); - } - switch (vic) { - case HDMI_720x480i60_16x9: - case HDMI_720x576i50_16x9: - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | - (0 << 2) | - (0 << 3) | - (0 << 4) | - (4 << 5) | - (1 << 8) | - (1 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); - break; - case HDMI_1920x1080i60_16x9: - case HDMI_1920x1080i50_16x9: - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | - (HSYNC_POLARITY << 2) | - (VSYNC_POLARITY << 3) | - (0 << 4) | - (((TX_INPUT_COLOR_FORMAT == 0) ? 1 : 0) << 5) | - (1 << 8) | - (0 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); - break; - case HDMI_3840x2160p30_16x9: - case HDMI_3840x2160p25_16x9: - case HDMI_3840x2160p24_16x9: - case HDMI_4096x2160p24_256x135: - case HDMI_4096x2160p25_256x135: - case HDMI_4096x2160p30_256x135: - case HDMI_4096x2160p50_256x135: - case HDMI_4096x2160p60_256x135: - case HDMI_3840x2160p50_16x9: - case HDMI_3840x2160p60_16x9: - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | - (HSYNC_POLARITY << 2) | - (VSYNC_POLARITY << 3) | - (0 << 4) | - (4 << 5) | - (0 << 8) | - (0 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); - hd_write_reg(P_ENCP_VIDEO_EN, 1); /* Enable VENC */ - break; - case HDMI_720x480p60_16x9: - case HDMI_720x576p50_16x9: - case HDMI_720x480p120_16x9: - case HDMI_720x576p100_16x9: - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | - (0 << 2) | - (0 << 3) | - (0 << 4) | - (4 << 5) | - (1 << 8) | - (0 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); - break; - case HDMI_1280x720p60_16x9: - case HDMI_1280x720p50_16x9: - case HDMI_1280x720p100_16x9: - case HDMI_1280x720p120_16x9: - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | - (HSYNC_POLARITY << 2) | - (VSYNC_POLARITY << 3) | - (0 << 4) | - (4 << 5) | - (1 << 8) | - (0 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); - break; - default: - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | - (0 << 1) | /* [ 1] src_sel_encp */ - (HSYNC_POLARITY << 2) | - (VSYNC_POLARITY << 3) | - (0 << 4) | - (4 << 5) | - (0 << 8) | - (0 << 12) - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); - } - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); -} - -static void hdmi_tvenc_set(enum hdmi_vic vic) -{ - switch (vic) { - case HDMI_720x480i60_16x9: - case HDMI_720x576i50_16x9: - hdmi_tvenc480i_set(vic); - break; - case HDMI_1920x1080i60_16x9: - case HDMI_1920x1080i50_16x9: - case HDMI_1920x1080i100_16x9: - case HDMI_1920x1080i120_16x9: - hdmi_tvenc1080i_set(vic); - break; - case HDMI_3840x2160p30_16x9: - case HDMI_3840x2160p25_16x9: - case HDMI_3840x2160p24_16x9: - case HDMI_4096x2160p24_256x135: - case HDMI_4096x2160p25_256x135: - case HDMI_4096x2160p30_256x135: - case HDMI_4096x2160p50_256x135: - case HDMI_4096x2160p60_256x135: - case HDMI_3840x2160p50_16x9: - case HDMI_3840x2160p60_16x9: - case HDMI_4096x2160p50_256x135_Y420: - case HDMI_4096x2160p60_256x135_Y420: - case HDMI_3840x2160p50_16x9_Y420: - case HDMI_3840x2160p60_16x9_Y420: - hdmi_tvenc4k2k_set(vic); - break; - default: - hdmi_tvenc_set_def(vic); - break; - } - - switch (vic) { - case HDMI_720x480i60_16x9: - case HDMI_720x576i50_16x9: - /* Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /* [ 0] src_sel_enci*/ - (0 << 1) | /* [ 1] src_sel_encp*/ - (0 << 2) | /* [ 2] inv_hsync. 1=Invert Hsync polarity.*/ - (0 << 3) | /* [ 3] inv_vsync. 1=Invert Vsync polarity.*/ - (0 << 4) | /* [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ - (4 << 5) | /* [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ - /* 0=output CrYCb(BRG);*/ - /* 1=output YCbCr(RGB);*/ - /* 2=output YCrCb(RBG);*/ - /* 3=output CbCrY(GBR);*/ - /* 4=output CbYCr(GRB);*/ - /* 5=output CrCbY(BGR);*/ - /* 6,7=Rsrv.*/ - (1 << 8) | /* [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ - (1 <<12) /* [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); // [ 0] src_sel_enci: Enable ENCI output to HDMI*/ - break; - case HDMI_1920x1080i60_16x9: - case HDMI_1920x1080i50_16x9: - case HDMI_1920x1080i100_16x9: - case HDMI_1920x1080i120_16x9: - /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ - (0 << 1) | /*[ 1] src_sel_encp*/ - (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ - (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ - (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ - (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ - /* 0=output CrYCb(BRG);*/ - /* 1=output YCbCr(RGB);*/ - /* 2=output YCrCb(RBG);*/ - /* 3=output CbCrY(GBR);*/ - /* 4=output CbYCr(GRB);*/ - /* 5=output CrCbY(BGR);*/ - /* 6,7=Rsrv.*/ - (1 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ - (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ - break; - case HDMI_3840x2160p30_16x9: - case HDMI_3840x2160p25_16x9: - case HDMI_3840x2160p24_16x9: - case HDMI_4096x2160p24_256x135: - case HDMI_4096x2160p25_256x135: - case HDMI_4096x2160p30_256x135: - case HDMI_4096x2160p50_256x135: - case HDMI_4096x2160p60_256x135: - case HDMI_3840x2160p50_16x9: - case HDMI_3840x2160p60_16x9: - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ - (0 << 1) | /*[ 1] src_sel_encp*/ - (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ - (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ - (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ - (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ - /* 0=output CrYCb(BRG);*/ - /* 1=output YCbCr(RGB);*/ - /* 2=output YCrCb(RBG);*/ - /* 3=output CbCrY(GBR);*/ - /* 4=output CbYCr(GRB);*/ - /* 5=output CrCbY(BGR);*/ - /* 6,7=Rsrv.*/ - (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ - (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ - ); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ - hd_write_reg(P_ENCP_VIDEO_EN, 1); /*Enable VENC*/ - break; - case HDMI_720x480p60_16x9: - case HDMI_720x576p50_16x9: - case HDMI_720x480p120_16x9: - case HDMI_720x576p100_16x9: - /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ - (0 << 1) | /*[ 1] src_sel_encp*/ - (0 << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ - (0 << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ - (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ - (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ - /* 0=output CrYCb(BRG);*/ - /* 1=output YCbCr(RGB);*/ - /* 2=output YCrCb(RBG);*/ - /* 3=output CbCrY(GBR);*/ - /* 4=output CbYCr(GRB);*/ - /* 5=output CrCbY(BGR);*/ - /* 6,7=Rsrv.*/ - (1 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ - (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ - ); - /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ - break; - case HDMI_1280x720p60_16x9: - case HDMI_1280x720p50_16x9: - case HDMI_1280x720p100_16x9: - case HDMI_1280x720p120_16x9: - /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ - (0 << 1) | /*[ 1] src_sel_encp*/ - (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ - (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ - (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ - (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ - /* 0=output CrYCb(BRG);*/ - /* 1=output YCbCr(RGB);*/ - /* 2=output YCrCb(RBG);*/ - /* 3=output CbCrY(GBR);*/ - /* 4=output CbYCr(GRB);*/ - /* 5=output CrCbY(BGR);*/ - /* 6,7=Rsrv.*/ - (1 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ - (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ - ); - /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ - break; - default: - /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ - hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/ - (0 << 1) | /*[ 1] src_sel_encp*/ - (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/ - (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/ - (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/ - (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/ - /* 0=output CrYCb(BRG);*/ - /* 1=output YCbCr(RGB);*/ - /* 2=output YCrCb(RBG);*/ - /* 3=output CbCrY(GBR);*/ - /* 4=output CbYCr(GRB);*/ - /* 5=output CrCbY(BGR);*/ - /* 6,7=Rsrv.*/ - (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/ - (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/ - ); - /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/ - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/ - } -} - -static void mode420_half_horizontal_para(void) -{ - unsigned int hactive = 0; - unsigned int hblank = 0; - unsigned int hfront = 0; - unsigned int hsync = 0; - - printk("%s[%d]\n", __func__, __LINE__); - hactive = hdmitx_rd_reg(HDMITX_DWC_FC_INHACTV0); - hactive += (hdmitx_rd_reg(HDMITX_DWC_FC_INHACTV1) & 0x3f) << 8; - hblank = hdmitx_rd_reg(HDMITX_DWC_FC_INHBLANK0); - hblank += (hdmitx_rd_reg(HDMITX_DWC_FC_INHBLANK1) & 0x1f) << 8; - hfront = hdmitx_rd_reg(HDMITX_DWC_FC_HSYNCINDELAY0); - hfront += (hdmitx_rd_reg(HDMITX_DWC_FC_HSYNCINDELAY1) & 0x1f) << 8; - hsync = hdmitx_rd_reg(HDMITX_DWC_FC_HSYNCINWIDTH0); - hsync += (hdmitx_rd_reg(HDMITX_DWC_FC_HSYNCINWIDTH1) & 0x3) << 8; - - hactive = hactive / 2; - hblank = hblank / 2; - hfront = hfront / 2; - hsync = hsync / 2; - - hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV0, (hactive & 0xff)); - hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV1, ((hactive >> 8) & 0x3f)); - hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK0, (hblank & 0xff)); - hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK1, ((hblank >> 8) & 0x1f)); - hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY0, (hfront & 0xff)); - hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY1, ((hfront >> 8) & 0x1f)); - hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH0, (hsync & 0xff)); - hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH1, ((hsync >> 8) & 0x3)); -} - -static void set_tmds_clk_div40(unsigned int div40) -{ - if (div40 == 1) { - hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_01, 0); /*[25:16] tmds_clk_pttn[19:10] [ 9: 0] tmds_clk_pttn[ 9: 0]*/ - hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_23, 0x03ff03ff); /*[25:16] tmds_clk_pttn[39:30] [ 9: 0] tmds_clk_pttn[29:20]*/ - } else { - hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f); - hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f); - } - hdmitx_set_reg_bits(HDMITX_DWC_FC_SCRAMBLER_CTRL, (div40 == 1) ? 1 : 0, 0, 1); - - hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); /*0xc*/ - msleep(2); - hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); /*0xc*/ - scdc_prepare((div40 == 1) ? 1:0); -} - -static void hdmitx_set_vsi_pkt(enum hdmi_vic vic) -{ - /* convert to HDMI_VIC */ - if (vic == HDMI_3840x2160p30_16x9) - vic = 1; - else if (vic == HDMI_3840x2160p25_16x9) - vic = 2; - else if (vic == HDMI_3840x2160p24_16x9) - vic = 3; - else - vic = 4; - - hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID0, 0x03); - hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID1, 0x0c); - hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID2, 0x00); - hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD0, 0x20); - hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, vic); - hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 5); - hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 3, 1); - hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0); - hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0x10); - hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1); -} - -/* record HDMITX current format */ -/* ISA_DEBUG_REG0 0x2600 - * bit[11]: Y420 - * bit[10:8]: HDMI VIC - * bit[7:0]: CEA VIC - */ -static void save_hdmitx_format(enum hdmi_vic vic, int y420) -{ - unsigned int data32; - - data32 = vic & 0xff; - data32 |= (hdmitx_rd_reg(HDMITX_DWC_FC_VSDPAYLOAD1) & 0x7) << 8; - data32 |= (!!y420) << 11; - hd_write_reg(P_ISA_DEBUG_REG0, data32); -} - -static void hdmitx_set_vdac(unsigned int enable) -{ - if (0 == enable) - { - hd_write_reg(P_HHI_VDAC_CNTL0, 0); - hd_write_reg(P_HHI_VDAC_CNTL1, 8); - } - else if (1 == enable) - { - hd_write_reg(P_HHI_VDAC_CNTL0, 1); - hd_write_reg(P_HHI_VDAC_CNTL1, 0); - } - - return ; -} - -static void hdmitx_set_hw(struct hdmitx_dev* hdev) -{ - struct hdmi_format_para *para = NULL; - - para = hdmi_get_fmt_paras(hdev->vic); - if (para == NULL) { - printk("error at %s[%d]\n", __func__, __LINE__); - return; - } - hdmitx_set_pll(hdev); - hdmitx_set_phy(hdev); - hdmitx_enc(hdev->vic); - hdmitx_set_vdac(0); - - /* --------------------------------------------------------*/ - /* Set up HDMI*/ - /* --------------------------------------------------------*/ - config_hdmi20_tx(hdev->vic, para, /*pixel_repeat*/ - hdev->para->cd, /*Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit.*/ - TX_INPUT_COLOR_FORMAT, /*input_color_format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/ - TX_INPUT_COLOR_RANGE, /*input_color_range: 0=limited; 1=full.*/ - hdev->para->cs, /*output_color_format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/ - TX_OUTPUT_COLOR_RANGE /*output_color_range: 0=limited; 1=full.*/ - ); - - /* switch HDMI_VIC for 2160p30/25/24hz */ - switch (hdev->vic) { - case HDMI_3840x2160p24_16x9: - case HDMI_3840x2160p25_16x9: - case HDMI_3840x2160p30_16x9: - case HDMI_4096x2160p24_256x135: - hdmitx_set_vsi_pkt(hdev->vic); - break; - default: - break; - } - - /* Using ISA_DEBUG_REG0 to record HDMITX current format */ - save_hdmitx_format(hdev->vic, (hdev->para->cs == HDMI_COLOR_FORMAT_420)); - - hd_write_reg(P_VPU_HDMI_FMT_CTRL, - (((TX_INPUT_COLOR_FORMAT==HDMI_COLOR_FORMAT_420)?2:0) << 0) | - /*[ 1: 0] hdmi_vid_fmt. 0=444; 1=convert to 422; 2=convert to 420.*/ - (2 << 2) | /*[ 3: 2] chroma_dnsmp. 0=use pixel 0; 1=use pixel 1; 2=use average.*/ - (0 << 4) | /*[ 4] dith_en. 1=enable dithering before HDMI TX input.*/ - (0 << 5) | /*[ 5] hdmi_dith_md: random noise selector.*/ - (0 << 6)); /*[ 9: 6] hdmi_dith10_cntl.*/ - if (hdev->para->cs == HDMI_COLOR_FORMAT_420) { - hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 2, 0, 2); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 4, 4); - hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 8, 1); - } - switch (hdev->vic) { - case HDMI_720x480i60_16x9: - case HDMI_720x576i50_16x9: - enc_vpu_bridge_reset(0); - break; - default: - enc_vpu_bridge_reset(1); - break; - } - - if (hdev->para->cs == HDMI_COLOR_FORMAT_420) - mode420_half_horizontal_para(); - - switch (hdev->vic) { - case HDMI_3840x2160p50_16x9: - case HDMI_3840x2160p60_16x9: - case HDMI_4096x2160p50_256x135: - case HDMI_4096x2160p60_256x135: - if ((hdev->para->cs == HDMI_COLOR_FORMAT_420) - && (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) - set_tmds_clk_div40(0); - else - set_tmds_clk_div40(1); - break; - case HDMI_3840x2160p50_16x9_Y420: - case HDMI_3840x2160p60_16x9_Y420: - case HDMI_4096x2160p50_256x135_Y420: - case HDMI_4096x2160p60_256x135_Y420: - if ((hdev->para->cs == HDMI_COLOR_FORMAT_420) - && (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) - set_tmds_clk_div40(0); - else - set_tmds_clk_div40(1); - break; - case HDMI_3840x2160p24_16x9: - case HDMI_3840x2160p24_64x27: - case HDMI_4096x2160p24_256x135: - case HDMI_3840x2160p25_16x9: - case HDMI_3840x2160p25_64x27: - case HDMI_4096x2160p25_256x135: - case HDMI_3840x2160p30_16x9: - case HDMI_3840x2160p30_64x27: - case HDMI_4096x2160p30_256x135: - case HDMI_1920x1080p100_16x9: - case HDMI_1920x1080p120_16x9: - if ((hdev->para->cs == HDMI_COLOR_FORMAT_422) - || (hdev->para->cd == HDMI_COLOR_DEPTH_24B)) - set_tmds_clk_div40(0); - else - set_tmds_clk_div40(1); - break; - default: - set_tmds_clk_div40(0); - break; - } - hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 0, 3, 1); - msleep(1); - hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 1, 3, 1); -} - -/*Use this self-made function rather than %, - *because % appears to produce wrong - *value for divisor which are not 2's exponential. - */ -static unsigned long modulo(unsigned long a, unsigned long b) -{ - if (a >= b) { - return(a-b); - } else { - return(a); - } -} - -static signed int to_signed(unsigned int a) -{ - if (a <= 7) { - return(a); - } else { - return(a-16); - } -} - -/*TODO*/ -static void hdmitx_csc_config (unsigned char input_color_format, - unsigned char output_color_format, - unsigned char color_depth) -{ - unsigned char conv_en; - unsigned long csc_coeff_a1, csc_coeff_a2, csc_coeff_a3, csc_coeff_a4; - unsigned long csc_coeff_b1, csc_coeff_b2, csc_coeff_b3, csc_coeff_b4; - unsigned long csc_coeff_c1, csc_coeff_c2, csc_coeff_c3, csc_coeff_c4; - unsigned char csc_scale; - unsigned long data32; - - conv_en = (((input_color_format == HDMI_COLOR_FORMAT_RGB) || - (output_color_format == HDMI_COLOR_FORMAT_RGB)) && - ( input_color_format != output_color_format))? 1 : 0; - - if (conv_en) { - if (output_color_format == HDMI_COLOR_FORMAT_RGB) { - csc_coeff_a1 = 0x2000; - csc_coeff_a2 = 0x6926; - csc_coeff_a3 = 0x74fd; - csc_coeff_a4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x010e : - (color_depth==HDMI_COLOR_DEPTH_30B)? 0x043b : - (color_depth==HDMI_COLOR_DEPTH_36B)? 0x10ee : - (color_depth==HDMI_COLOR_DEPTH_48B)? 0x10ee : 0x010e; - csc_coeff_b1 = 0x2000; - csc_coeff_b2 = 0x2cdd; - csc_coeff_b3 = 0x0000; - csc_coeff_b4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x7e9a : - (color_depth==HDMI_COLOR_DEPTH_30B)? 0x7a65 : - (color_depth==HDMI_COLOR_DEPTH_36B)? 0x6992 : - (color_depth==HDMI_COLOR_DEPTH_48B)? 0x6992 : 0x7e9a; - csc_coeff_c1 = 0x2000; - csc_coeff_c2 = 0x0000; - csc_coeff_c3 = 0x38b4; - csc_coeff_c4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x7e3b : - (color_depth==HDMI_COLOR_DEPTH_30B)? 0x78ea : - (color_depth==HDMI_COLOR_DEPTH_36B)? 0x63a6 : - (color_depth==HDMI_COLOR_DEPTH_48B)? 0x63a6 : 0x7e3b; - csc_scale = 1; - } else { /*input_color_format == HDMI_COLOR_FORMAT_RGB*/ - csc_coeff_a1 = 0x2591; - csc_coeff_a2 = 0x1322; - csc_coeff_a3 = 0x074b; - csc_coeff_a4 = 0x0000; - csc_coeff_b1 = 0x6535; - csc_coeff_b2 = 0x2000; - csc_coeff_b3 = 0x7acc; - csc_coeff_b4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x0200 : - (color_depth==HDMI_COLOR_DEPTH_30B)? 0x0800 : - (color_depth==HDMI_COLOR_DEPTH_36B)? 0x2000 : - (color_depth==HDMI_COLOR_DEPTH_48B)? 0x2000 : 0x0200; - csc_coeff_c1 = 0x6acd; - csc_coeff_c2 = 0x7534; - csc_coeff_c3 = 0x2000; - csc_coeff_c4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x0200 : - (color_depth==HDMI_COLOR_DEPTH_30B)? 0x0800 : - (color_depth==HDMI_COLOR_DEPTH_36B)? 0x2000 : - (color_depth==HDMI_COLOR_DEPTH_48B)? 0x2000 : 0x0200; - csc_scale = 0; - } - } else { - csc_coeff_a1 = 0x2000; - csc_coeff_a2 = 0x0000; - csc_coeff_a3 = 0x0000; - csc_coeff_a4 = 0x0000; - csc_coeff_b1 = 0x0000; - csc_coeff_b2 = 0x2000; - csc_coeff_b3 = 0x0000; - csc_coeff_b4 = 0x0000; - csc_coeff_c1 = 0x0000; - csc_coeff_c2 = 0x0000; - csc_coeff_c3 = 0x2000; - csc_coeff_c4 = 0x0000; - csc_scale = 1; - } - - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A1_MSB, (csc_coeff_a1>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A1_LSB, csc_coeff_a1&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A2_MSB, (csc_coeff_a2>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A2_LSB, csc_coeff_a2&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A3_MSB, (csc_coeff_a3>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A3_LSB, csc_coeff_a3&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A4_MSB, (csc_coeff_a4>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A4_LSB, csc_coeff_a4&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B1_MSB, (csc_coeff_b1>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B1_LSB, csc_coeff_b1&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B2_MSB, (csc_coeff_b2>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B2_LSB, csc_coeff_b2&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B3_MSB, (csc_coeff_b3>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B3_LSB, csc_coeff_b3&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B4_MSB, (csc_coeff_b4>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B4_LSB, csc_coeff_b4&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C1_MSB, (csc_coeff_c1>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C1_LSB, csc_coeff_c1&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C2_MSB, (csc_coeff_c2>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C2_LSB, csc_coeff_c2&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C3_MSB, (csc_coeff_c3>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C3_LSB, csc_coeff_c3&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C4_MSB, (csc_coeff_c4>>8)&0xff); - hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C4_LSB, csc_coeff_c4&0xff); - - data32 = 0; - data32 |= (color_depth << 4); /* [7:4] csc_color_depth*/ - data32 |= (csc_scale << 0); /* [1:0] cscscale*/ - hdmitx_wr_reg(HDMITX_DWC_CSC_SCALE, data32); -} /* hdmitx_csc_config */
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_tvenc.c b/drivers/amlogic/media/vout/hdmitx/hdmitx_tvenc.c deleted file mode 100644 index 06ca302..0000000 --- a/drivers/amlogic/media/vout/hdmitx/hdmitx_tvenc.c +++ /dev/null
@@ -1,675 +0,0 @@ -/* - * driver/amlogic/media/vout/hdmitx/hdmitx_tvenc.c - * - * Copyright (C) 2018 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. -*/ - -#include <asm/arch/register.h> -#include <asm/arch/secure_apb.h> - -#include "hdmitx_common.h" - -#define MREG_END_MARKER (volatile unsigned int *)0xFFFF - -static const struct reg_t tvregs_720p[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - - {P_VENC_DVI_SETTING, 0x2029}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0019}, - {P_ENCP_VIDEO_YFP1_HTIME, 648}, - {P_ENCP_VIDEO_YFP2_HTIME, 3207}, - {P_ENCP_VIDEO_MAX_PXCNT, 3299}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 80}, - {P_ENCP_VIDEO_HSPULS_END, 240}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 80}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 688}, - {P_ENCP_VIDEO_VSPULS_END, 3248}, - {P_ENCP_VIDEO_VSPULS_BLINE, 4}, - {P_ENCP_VIDEO_VSPULS_ELINE, 8}, - {P_ENCP_VIDEO_HAVON_BEGIN, 648}, - {P_ENCP_VIDEO_HAVON_END, 3207}, - {P_ENCP_VIDEO_VAVON_BLINE, 29}, - {P_ENCP_VIDEO_VAVON_ELINE, 748}, - {P_ENCP_VIDEO_HSO_BEGIN, 256}, - {P_ENCP_VIDEO_HSO_END, 168}, - {P_ENCP_VIDEO_VSO_BEGIN, 168}, - {P_ENCP_VIDEO_VSO_END, 256}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_VSO_ELINE, 5}, - {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCP_VIDEO_EN, 1}, - {P_ENCI_VIDEO_EN, 0}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_720p_50hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_VENC_DVI_SETTING, 0x202d}, - {P_ENCP_VIDEO_MAX_PXCNT, 3959}, - {P_ENCP_VIDEO_MAX_LNCNT, 749}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 80}, - {P_ENCP_VIDEO_HSPULS_END, 240}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 80}, - {P_ENCP_VIDEO_HAVON_BEGIN, 648}, - {P_ENCP_VIDEO_HAVON_END, 3207}, - {P_ENCP_VIDEO_HSO_BEGIN, 128}, - {P_ENCP_VIDEO_HSO_END, 208}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 688}, - {P_ENCP_VIDEO_VSPULS_END, 3248}, - {P_ENCP_VIDEO_VSPULS_BLINE, 4}, - {P_ENCP_VIDEO_VSPULS_ELINE, 8}, - {P_ENCP_VIDEO_VAVON_BLINE, 29}, - {P_ENCP_VIDEO_VAVON_ELINE, 748}, - {P_ENCP_VIDEO_VSO_BEGIN, 128}, - {P_ENCP_VIDEO_VSO_END, 128}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_VSO_ELINE, 5}, - {P_ENCP_VIDEO_YFP1_HTIME, 648}, - {P_ENCP_VIDEO_YFP2_HTIME, 3207}, - {P_VENC_VIDEO_PROG_MODE, 0x100}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0019}, - {P_ENCP_VIDEO_SYNC_MODE, 0x407}, - {P_ENCP_VIDEO_YC_DLY, 0}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCP_VIDEO_EN, 1}, - {P_ENCI_VIDEO_EN, 0}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_480i[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCI_CFILT_CTRL, 0x12}, - {P_ENCI_CFILT_CTRL2, 0x12}, - {P_VENC_DVI_SETTING, 0}, - {P_ENCI_VIDEO_MODE, 0}, - {P_ENCI_VIDEO_MODE_ADV, 0}, - {P_ENCI_SYNC_HSO_BEGIN, 5}, - {P_ENCI_SYNC_HSO_END, 129}, - {P_ENCI_SYNC_VSO_EVNLN, 0x0003}, - {P_ENCI_SYNC_VSO_ODDLN, 0x0104}, - {P_ENCI_MACV_MAX_AMP, 0x810b}, - {P_VENC_VIDEO_PROG_MODE, 0xf0}, - {P_ENCI_VIDEO_MODE, 0x08}, - {P_ENCI_VIDEO_MODE_ADV, 0x26}, - {P_ENCI_VIDEO_SCH, 0x20}, - {P_ENCI_SYNC_MODE, 0x07}, - {P_ENCI_DBG_PX_RST, 0}, - {P_ENCI_VFIFO2VD_CTL, 0x4e01}, - {P_ENCI_VFIFO2VD_PIXEL_START, 0xf3,}, - {P_ENCI_VFIFO2VD_PIXEL_END, 0x0693,}, - {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x12,}, - {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,}, - {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,}, - {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_480p[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_FILT_CTRL, 0x2052}, - {P_VENC_DVI_SETTING, 0x21}, - {P_ENCP_VIDEO_MODE, 0x4000}, - {P_ENCP_VIDEO_MODE_ADV, 9}, - {P_ENCP_VIDEO_YFP1_HTIME, 244}, - {P_ENCP_VIDEO_YFP2_HTIME, 1630}, - {P_ENCP_VIDEO_MAX_PXCNT, 1715}, - {P_ENCP_VIDEO_MAX_LNCNT, 524}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 0x22}, - {P_ENCP_VIDEO_HSPULS_END, 0xa0}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 88}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 0}, - {P_ENCP_VIDEO_VSPULS_END, 1589}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 5}, - {P_ENCP_VIDEO_HAVON_BEGIN, 249}, - {P_ENCP_VIDEO_HAVON_END, 1689}, - {P_ENCP_VIDEO_VAVON_BLINE, 42}, - {P_ENCP_VIDEO_VAVON_ELINE, 521}, - {P_ENCP_VIDEO_SYNC_MODE, 0x07}, - {P_VENC_VIDEO_PROG_MODE, 0x0}, - {P_ENCP_VIDEO_HSO_BEGIN, 0x3}, - {P_ENCP_VIDEO_HSO_END, 0x5}, - {P_ENCP_VIDEO_VSO_BEGIN, 0x3}, - {P_ENCP_VIDEO_VSO_END, 0x5}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_SY_VAL, 8}, - {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_576i[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_VENC_DVI_SETTING, 0}, - {P_ENCI_VIDEO_MODE, 0}, - {P_ENCI_VIDEO_MODE_ADV, 0}, - {P_ENCI_SYNC_HSO_BEGIN, 3}, - {P_ENCI_SYNC_HSO_END, 129}, - {P_ENCI_SYNC_VSO_EVNLN, 0x0003}, - {P_ENCI_SYNC_VSO_ODDLN, 0x0104}, - {P_ENCI_MACV_MAX_AMP, 0x8107}, - {P_VENC_VIDEO_PROG_MODE, 0xff}, - {P_ENCI_VIDEO_MODE, 0x13}, - {P_ENCI_VIDEO_MODE_ADV, 0x26}, - {P_ENCI_VIDEO_SCH, 0x28}, - {P_ENCI_SYNC_MODE, 0x07}, - {P_ENCI_YC_DELAY, 0x333}, - {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b}, - {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab}, - {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016}, - {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, - {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, - {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_ENCI_DBG_PX_RST, 0}, - {P_ENCI_VFIFO2VD_CTL, 0x4e01}, - {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b}, - {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab}, - {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016}, - {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136}, - {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017}, - {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137}, - {P_VPU_VIU_VENC_MUX_CTRL, 0x5}, - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_576p[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_FILT_CTRL, 0x52}, - {P_VENC_DVI_SETTING, 0x21}, - {P_ENCP_VIDEO_MODE, 0x4000}, - {P_ENCP_VIDEO_MODE_ADV, 9}, - {P_ENCP_VIDEO_YFP1_HTIME, 235}, - {P_ENCP_VIDEO_YFP2_HTIME, 1674}, - {P_ENCP_VIDEO_MAX_PXCNT, 1727}, - {P_ENCP_VIDEO_MAX_LNCNT, 624}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 0}, - {P_ENCP_VIDEO_HSPULS_END, 0x80}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 88}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 0}, - {P_ENCP_VIDEO_VSPULS_END, 1599}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_HAVON_BEGIN, 235}, - {P_ENCP_VIDEO_HAVON_END, 1674}, - {P_ENCP_VIDEO_VAVON_BLINE, 44}, - {P_ENCP_VIDEO_VAVON_ELINE, 619}, - {P_ENCP_VIDEO_SYNC_MODE, 0x07}, - {P_VENC_VIDEO_PROG_MODE, 0x0}, - {P_ENCP_VIDEO_HSO_BEGIN, 0x80}, - {P_ENCP_VIDEO_HSO_END, 0x0}, - {P_ENCP_VIDEO_VSO_BEGIN, 0x0}, - {P_ENCP_VIDEO_VSO_END, 0x5}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_SY_VAL, 8}, - {P_ENCP_VIDEO_SY2_VAL, 0x1d8}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_1080i[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_VENC_DVI_SETTING, 0x2029}, - {P_ENCP_VIDEO_MAX_PXCNT, 4399}, - {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 88}, - {P_ENCP_VIDEO_HSPULS_END, 264}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 88}, - {P_ENCP_VIDEO_HAVON_BEGIN, 516}, - {P_ENCP_VIDEO_HAVON_END, 4355}, - {P_ENCP_VIDEO_HSO_BEGIN, 264}, - {P_ENCP_VIDEO_HSO_END, 176}, - {P_ENCP_VIDEO_EQPULS_BEGIN, 2288}, - {P_ENCP_VIDEO_EQPULS_END, 2464}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 440}, - {P_ENCP_VIDEO_VSPULS_END, 2200}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_EQPULS_BLINE, 0}, - {P_ENCP_VIDEO_EQPULS_ELINE, 4}, - {P_ENCP_VIDEO_VAVON_BLINE, 20}, - {P_ENCP_VIDEO_VAVON_ELINE, 559}, - {P_ENCP_VIDEO_VSO_BEGIN, 88}, - {P_ENCP_VIDEO_VSO_END, 88}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_VSO_ELINE, 5}, - {P_ENCP_VIDEO_YFP1_HTIME, 516}, - {P_ENCP_VIDEO_YFP2_HTIME, 4355}, - {P_VENC_VIDEO_PROG_MODE, 0x100}, - {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11}, - {P_ENCP_VIDEO_MODE, 0x5ffc}, - {P_ENCP_VIDEO_MODE_ADV, 0x0019}, - {P_ENCP_VIDEO_SYNC_MODE, 0x207}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_1080i_50hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_VENC_DVI_SETTING, 0x202d}, - {P_ENCP_VIDEO_MAX_PXCNT, 5279}, - {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 88}, - {P_ENCP_VIDEO_HSPULS_END, 264}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 88}, - {P_ENCP_VIDEO_HAVON_BEGIN, 526}, - {P_ENCP_VIDEO_HAVON_END, 4365}, - {P_ENCP_VIDEO_HSO_BEGIN, 142}, - {P_ENCP_VIDEO_HSO_END, 230}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 440}, - {P_ENCP_VIDEO_VSPULS_END, 2200}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_VAVON_BLINE, 20}, - {P_ENCP_VIDEO_VAVON_ELINE, 559}, - {P_ENCP_VIDEO_VSO_BEGIN, 142}, - {P_ENCP_VIDEO_VSO_END, 142}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_VSO_ELINE, 5}, - {P_ENCP_VIDEO_YFP1_HTIME, 526}, - {P_ENCP_VIDEO_YFP2_HTIME, 4365}, - {P_VENC_VIDEO_PROG_MODE, 0x100}, - {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11}, - {P_ENCP_VIDEO_MODE, 0x5ffc}, - {P_ENCP_VIDEO_MODE_ADV, 0x0019}, - {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_1080p[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_FILT_CTRL, 0x1052}, - {P_VENC_DVI_SETTING, 0x0001}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0018}, - {P_ENCP_VIDEO_YFP1_HTIME, 140}, - {P_ENCP_VIDEO_YFP2_HTIME, 2060}, - {P_ENCP_VIDEO_MAX_PXCNT, 2199}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 2156}, - {P_ENCP_VIDEO_HSPULS_END, 44}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, - {P_ENCP_VIDEO_VSPULS_END, 2059}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_HAVON_BEGIN, 148}, - {P_ENCP_VIDEO_HAVON_END, 2067}, - {P_ENCP_VIDEO_VAVON_BLINE, 41}, - {P_ENCP_VIDEO_VAVON_ELINE, 1120}, - {P_ENCP_VIDEO_HSO_BEGIN, 44}, - {P_ENCP_VIDEO_HSO_END, 2156}, - {P_ENCP_VIDEO_VSO_BEGIN, 2100}, - {P_ENCP_VIDEO_VSO_END, 2164}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_VSO_ELINE, 5}, - {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_VENC_VIDEO_PROG_MODE, 0x100}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_1080p_50hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_VENC_DVI_SETTING, 0x000d}, - {P_ENCP_VIDEO_MAX_PXCNT, 2639}, - {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 44}, - {P_ENCP_VIDEO_HSPULS_END, 132}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, - {P_ENCP_VIDEO_HAVON_BEGIN, 271}, - {P_ENCP_VIDEO_HAVON_END, 2190}, - {P_ENCP_VIDEO_HSO_BEGIN, 79}, - {P_ENCP_VIDEO_HSO_END, 123}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 220}, - {P_ENCP_VIDEO_VSPULS_END, 2140}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_EQPULS_BLINE, 0}, - {P_ENCP_VIDEO_EQPULS_ELINE, 4}, - {P_ENCP_VIDEO_VAVON_BLINE, 41}, - {P_ENCP_VIDEO_VAVON_ELINE, 1120}, - {P_ENCP_VIDEO_VSO_BEGIN, 79}, - {P_ENCP_VIDEO_VSO_END, 79}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_VSO_ELINE, 5}, - {P_ENCP_VIDEO_YFP1_HTIME, 271}, - {P_ENCP_VIDEO_YFP2_HTIME, 2190}, - {P_VENC_VIDEO_PROG_MODE, 0x100}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0018}, - {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_ENCP_VIDEO_YC_DLY, 0}, - {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_1080p_24hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_FILT_CTRL, 0x1052}, - {P_VENC_DVI_SETTING, 0x000d}, - {P_ENCP_VIDEO_MAX_PXCNT, 2749}, - {P_ENCP_VIDEO_MAX_LNCNT, 1124}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 44}, - {P_ENCP_VIDEO_HSPULS_END, 132}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, - {P_ENCP_VIDEO_HAVON_BEGIN, 271}, - {P_ENCP_VIDEO_HAVON_END, 2190}, - {P_ENCP_VIDEO_HSO_BEGIN, 79}, - {P_ENCP_VIDEO_HSO_END, 123}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 220}, - {P_ENCP_VIDEO_VSPULS_END, 2140}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_EQPULS_BLINE, 0}, - {P_ENCP_VIDEO_EQPULS_ELINE, 4}, - {P_ENCP_VIDEO_VAVON_BLINE, 41}, - {P_ENCP_VIDEO_VAVON_ELINE, 1120}, - {P_ENCP_VIDEO_VSO_BEGIN, 79}, - {P_ENCP_VIDEO_VSO_END, 79}, - {P_ENCP_VIDEO_VSO_BLINE, 0}, - {P_ENCP_VIDEO_VSO_ELINE, 5}, - {P_ENCP_VIDEO_YFP1_HTIME, 271}, - {P_ENCP_VIDEO_YFP2_HTIME, 2190}, - {P_VENC_VIDEO_PROG_MODE, 0x100}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0018}, - {P_ENCP_VIDEO_SYNC_MODE, 0x7}, - {P_ENCP_VIDEO_YC_DLY, 0}, - {P_ENCP_VIDEO_RGB_CTRL, 2}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_EN, 1}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_4k2k_30hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0008}, - {P_ENCP_VIDEO_YFP1_HTIME, 140}, - {P_ENCP_VIDEO_YFP2_HTIME, 140+3840}, - {P_ENCP_VIDEO_MAX_PXCNT, 3840+560-1}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920}, - {P_ENCP_VIDEO_HSPULS_END, 44}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, - {P_ENCP_VIDEO_VSPULS_END, 2059+1920}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_HAVON_BEGIN, 148}, - {P_ENCP_VIDEO_HAVON_END, 3987}, - {P_ENCP_VIDEO_VAVON_BLINE, 89}, - {P_ENCP_VIDEO_VAVON_ELINE, 2248}, - {P_ENCP_VIDEO_HSO_BEGIN, 44}, - {P_ENCP_VIDEO_HSO_END, 2156+1920}, - {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920}, - {P_ENCP_VIDEO_VSO_END, 2164+1920}, - {P_ENCP_VIDEO_VSO_BLINE, 51}, - {P_ENCP_VIDEO_VSO_ELINE, 53}, - {P_ENCP_VIDEO_MAX_LNCNT, 2249}, - {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCP_VIDEO_EN, 1}, - {P_ENCI_VIDEO_EN, 0}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_4k2k_25hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0008}, - {P_ENCP_VIDEO_YFP1_HTIME, 140}, - {P_ENCP_VIDEO_YFP2_HTIME, 140+3840}, - {P_ENCP_VIDEO_MAX_PXCNT, 3840+1440-1}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920}, - {P_ENCP_VIDEO_HSPULS_END, 44}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, - {P_ENCP_VIDEO_VSPULS_END, 2059+1920}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_HAVON_BEGIN, 148}, - {P_ENCP_VIDEO_HAVON_END, 3987}, - {P_ENCP_VIDEO_VAVON_BLINE, 89}, - {P_ENCP_VIDEO_VAVON_ELINE, 2248}, - {P_ENCP_VIDEO_HSO_BEGIN, 44}, - {P_ENCP_VIDEO_HSO_END, 2156+1920}, - {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920}, - {P_ENCP_VIDEO_VSO_END, 2164+1920}, - {P_ENCP_VIDEO_VSO_BLINE, 51}, - {P_ENCP_VIDEO_VSO_ELINE, 53}, - {P_ENCP_VIDEO_MAX_LNCNT, 2249}, - {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCP_VIDEO_EN, 1}, - {P_ENCI_VIDEO_EN, 0}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_4k2k_24hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0008}, - {P_ENCP_VIDEO_YFP1_HTIME, 140}, - {P_ENCP_VIDEO_YFP2_HTIME, 140+3840}, - {P_ENCP_VIDEO_MAX_PXCNT, 3840+1660-1}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920}, - {P_ENCP_VIDEO_HSPULS_END, 44}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, - {P_ENCP_VIDEO_VSPULS_END, 2059+1920}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_HAVON_BEGIN, 148}, - {P_ENCP_VIDEO_HAVON_END, 3987}, - {P_ENCP_VIDEO_VAVON_BLINE, 89}, - {P_ENCP_VIDEO_VAVON_ELINE, 2248}, - {P_ENCP_VIDEO_HSO_BEGIN, 44}, - {P_ENCP_VIDEO_HSO_END, 2156+1920}, - {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920}, - {P_ENCP_VIDEO_VSO_END, 2164+1920}, - {P_ENCP_VIDEO_VSO_BLINE, 51}, - {P_ENCP_VIDEO_VSO_ELINE, 53}, - {P_ENCP_VIDEO_MAX_LNCNT, 2249}, - {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCP_VIDEO_EN, 1}, - {P_ENCI_VIDEO_EN, 0}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_4k2k_smpte[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_MODE, 0x4040}, - {P_ENCP_VIDEO_MODE_ADV, 0x0008}, - {P_ENCP_VIDEO_YFP1_HTIME, 140}, - {P_ENCP_VIDEO_YFP2_HTIME, 140+3840+256}, - {P_ENCP_VIDEO_MAX_PXCNT, 4096+1404-1}, - {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920}, - {P_ENCP_VIDEO_HSPULS_END, 44}, - {P_ENCP_VIDEO_HSPULS_SWITCH, 44}, - {P_ENCP_VIDEO_VSPULS_BEGIN, 140}, - {P_ENCP_VIDEO_VSPULS_END, 2059+1920}, - {P_ENCP_VIDEO_VSPULS_BLINE, 0}, - {P_ENCP_VIDEO_VSPULS_ELINE, 4}, - {P_ENCP_VIDEO_HAVON_BEGIN, 148}, - {P_ENCP_VIDEO_HAVON_END, 3987+256}, - {P_ENCP_VIDEO_VAVON_BLINE, 89}, - {P_ENCP_VIDEO_VAVON_ELINE, 2248}, - {P_ENCP_VIDEO_HSO_BEGIN, 44}, - {P_ENCP_VIDEO_HSO_END, 2156+1920+256}, - {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920+256}, - {P_ENCP_VIDEO_VSO_END, 2164+1920+256}, - {P_ENCP_VIDEO_VSO_BLINE, 51}, - {P_ENCP_VIDEO_VSO_ELINE, 53}, - {P_ENCP_VIDEO_MAX_LNCNT, 2249}, - {P_ENCP_VIDEO_FILT_CTRL, 0x1000}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCP_VIDEO_EN, 1}, - {P_ENCI_VIDEO_EN, 0}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_4k2k_smpte_25hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_MODE, 0x4040,}, - {P_ENCP_VIDEO_MODE_ADV, 0x18,}, - {P_ENCP_VIDEO_MAX_PXCNT, 0x149F,}, - {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,}, - {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,}, - {P_ENCP_VIDEO_HAVON_END, 0x10D7,}, - {P_ENCP_VIDEO_VAVON_BLINE, 0x52,}, - {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,}, - {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, - {P_ENCP_VIDEO_HSO_END, 0x58,}, - {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, - {P_ENCP_VIDEO_VSO_END, 0x32,}, - {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, - {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCP_VIDEO_EN, 1}, - {P_ENCI_VIDEO_EN, 0}, - {MREG_END_MARKER, 0}, -}; - -static const struct reg_t tvregs_4k2k_smpte_30hz[] = { - {P_ENCP_VIDEO_EN, 0}, - {P_ENCI_VIDEO_EN, 0}, - {P_ENCP_VIDEO_MODE, 0x4040,}, - {P_ENCP_VIDEO_MODE_ADV, 0x18,}, - {P_ENCP_VIDEO_MAX_PXCNT, 0x112F,}, - {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,}, - {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,}, - {P_ENCP_VIDEO_HAVON_END, 0x10D7,}, - {P_ENCP_VIDEO_VAVON_BLINE, 0x52,}, - {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,}, - {P_ENCP_VIDEO_HSO_BEGIN, 0x0,}, - {P_ENCP_VIDEO_HSO_END, 0x58,}, - {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,}, - {P_ENCP_VIDEO_VSO_END, 0x32,}, - {P_ENCP_VIDEO_VSO_BLINE, 0x0,}, - {P_ENCP_VIDEO_VSO_ELINE, 0xA,}, - {P_VPU_VIU_VENC_MUX_CTRL, 0xA}, - {P_ENCP_VIDEO_EN, 1}, - {P_ENCI_VIDEO_EN, 0}, - {MREG_END_MARKER, 0}, -}; - -struct vic_tvregs_set { - enum hdmi_vic vic; - const struct reg_t *reg_setting; -}; - -/* Using HDMI vic as index */ -static struct vic_tvregs_set tvregsTab[] = { - {HDMI_720x480i60_16x9, tvregs_480i}, - {HDMI_2880x480i60_16x9, tvregs_480i}, - {HDMI_720x480p60_16x9, tvregs_480p}, - {HDMI_2880x240p60_16x9, tvregs_480p}, - {HDMI_720x576i50_16x9, tvregs_576i}, - {HDMI_2880x576i50_16x9, tvregs_576i}, - {HDMI_720x576p50_16x9, tvregs_576p}, - {HDMI_2880x576p50_16x9, tvregs_576p}, - {HDMI_1280x720p60_16x9, tvregs_720p}, - {HDMI_1920x1080i60_16x9, tvregs_1080i}, - {HDMI_1920x1080p60_16x9, tvregs_1080p}, - {HDMI_1920x1080p30_16x9, tvregs_1080p}, - {HDMI_1280x720p50_16x9, tvregs_720p_50hz}, - {HDMI_1920x1080i50_16x9, tvregs_1080i_50hz}, - {HDMI_1920x1080p50_16x9, tvregs_1080p_50hz}, - {HDMI_1920x1080p25_16x9, tvregs_1080p_50hz}, - {HDMI_1920x1080p24_16x9, tvregs_1080p_24hz}, - {HDMI_3840x2160p30_16x9, tvregs_4k2k_30hz}, - {HDMI_3840x2160p25_16x9, tvregs_4k2k_25hz}, - {HDMI_3840x2160p24_16x9, tvregs_4k2k_24hz}, - {HDMI_4096x2160p24_256x135, tvregs_4k2k_smpte}, - {HDMI_4096x2160p25_256x135, tvregs_4k2k_smpte_25hz}, - {HDMI_4096x2160p30_256x135, tvregs_4k2k_smpte_30hz}, - {HDMI_4096x2160p50_256x135, tvregs_4k2k_smpte_25hz}, - {HDMI_4096x2160p60_256x135, tvregs_4k2k_smpte_30hz}, - {HDMI_4096x2160p50_256x135_Y420, tvregs_4k2k_smpte_25hz}, - {HDMI_4096x2160p60_256x135_Y420, tvregs_4k2k_smpte_30hz}, - {HDMI_3840x2160p60_16x9, tvregs_4k2k_30hz}, - {HDMI_3840x2160p50_16x9, tvregs_4k2k_25hz}, - {HDMI_3840x2160p60_16x9_Y420, tvregs_4k2k_30hz}, - {HDMI_3840x2160p50_16x9_Y420, tvregs_4k2k_25hz}, -}; - -static inline void setreg(const struct reg_t *r) -{ - hd_write_reg(r->reg, r->val); - /* printk("[0x%x] = 0x%x\n", r->reg, r->val); */ -} - -static const struct reg_t *tvregs_setting_mode(enum hdmi_vic vic) -{ - int i = 0; - for (i = 0; i < ARRAY_SIZE(tvregsTab); i++) { - if (vic == tvregsTab[i].vic) - return tvregsTab[i].reg_setting; - } - return NULL; -} - -void set_vmode_enc_hw(enum hdmi_vic vic) -{ - const struct reg_t *s = tvregs_setting_mode(vic); - - if (s) { - pr_info("hdmitx: set enc for VIC: %d\n", vic); - while (MREG_END_MARKER != s->reg) - setreg(s++); - } else - pr_info("hdmitx: not find VIC: %d\n", vic); -}
diff --git a/drivers/amlogic/media/vout/hdmitx/sound.c b/drivers/amlogic/media/vout/hdmitx/sound.c new file mode 100644 index 0000000..e03dde9 --- /dev/null +++ b/drivers/amlogic/media/vout/hdmitx/sound.c
@@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <asm/arch/io.h> +#include <asm/arch/register.h> +#include <common.h> +#include <amlogic/auge_sound.h> +#include <asm/arch/cpu.h> +#include <amlogic/cpu_id.h> + +struct aiu_958_channel_status { + unsigned short chstat0_l; + unsigned short chstat1_l; + unsigned short chstat0_r; + unsigned short chstat1_r; +}; + +static int audiobus_read(unsigned long reg, unsigned int *val) +{ + *val = readl(reg); + return 0; +} + +static void hhi_write(unsigned long reg, unsigned int val) +{ + writel(val, reg); +} + +static void audiobus_write(unsigned long reg, unsigned int val) +{ + writel(val, reg); +} + +static int audiobus_update_bits(unsigned int reg, unsigned int mask, + unsigned int value) +{ + bool change; + unsigned int old, new; + + audiobus_read(reg, &old); + + new = (old & ~mask) | (value & mask); + change = old != new; + if (change) + audiobus_write(reg, new); + + return change; +} + +static void aml_set_audio_spdif_clk(void) +{ + /*mpll0: 25m*/ + hhi_write(ANACTRL_MPLL_CTRL0, 0x543); + hhi_write(ANACTRL_MPLL_CTRL1, 0xC5101856); + hhi_write(ANACTRL_MPLL_CTRL2, 0x40000033); + + /* audio clk gate */ + audiobus_write(EE_AUDIO_CLK_GATE_EN0, + 1 << 17 /* spdifout */ + | 1 << 9 /* frddra */ + | 1 << 0 /* ddr_arb */); + + /*SPDIFOUT_CTRL clk:6m*/ + audiobus_write(EE_AUDIO_CLK_SPDIFOUT_CTRL, + 1 << 31 /* enable */ + | 0 << 24 /* mpll0 */ + | 3 << 0 /* dividor */); +} + +static void aml_spdif_fifo_ctrl(void) +{ + /* reg mute val */ + audiobus_write(EE_AUDIO_SPDIFOUT_MUTE_VAL, 0x0); + + /* mask lane0 L/R, lsb first, insert data from 31bits */ + audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, + 0x1<<22 | 0x1<<21 | 0x1 << 20 | 0x1 << 19 | 0xffff << 0, + 0x1<<22 | 0x1<<21 | 0x0 << 20 | 0x0 << 19 | 0x3 << 0); + + /* split 64bits ddr data to 2 sample */ + /* msb position of data */ + /* frddr_A */ + audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL1, + 0x3 << 24 | 0x1f << 8 | 0x7 << 4, + 0 << 24 | (32 - 1) << 8 | 3 << 4); + + audiobus_write(EE_AUDIO_SPDIFOUT_SWAP, 0x1 << 4); +} + +static void spdifout_set_pcm_chsts(struct aiu_958_channel_status *set) +{ + if (!set) { + printf("%s(), error set NULL point\n", __func__); + return; + } + + audiobus_write(EE_AUDIO_SPDIFOUT_CHSTS0, + set->chstat1_l << 16 | set->chstat0_l); + audiobus_write(EE_AUDIO_SPDIFOUT_CHSTS6, + set->chstat1_r << 16 | set->chstat0_r); +} + +void frddr_init_without_mngr(void) +{ + unsigned int start_addr, end_addr, int_addr; + static int buf[256]; + + memset(buf, 0x0, sizeof(buf)); + start_addr = virt_to_phys(buf); + end_addr = start_addr + sizeof(buf) - 1; + int_addr = sizeof(buf) / 64; + + audiobus_write(EE_AUDIO_ARB_CTRL0, 0x800000ff); + + audiobus_write(EE_AUDIO_FRDDR_A_START_ADDR, start_addr); + + audiobus_write(EE_AUDIO_FRDDR_A_INIT_ADDR, start_addr); + + audiobus_write(EE_AUDIO_FRDDR_A_FINISH_ADDR, end_addr); + + audiobus_write(EE_AUDIO_FRDDR_A_INT_ADDR, int_addr); + + audiobus_write(EE_AUDIO_FRDDR_A_CTRL1, + (0x40 - 1) << 24 | (0x20 - 1) << 16 | 2 << 8 | 0 << 0); + + audiobus_write(EE_AUDIO_FRDDR_A_CTRL0, + 1 << 31 + | 0 << 24 + | 4 << 16 + ); + + /* src0 enable, src0 select spdifout */ + audiobus_write(EE_AUDIO_FRDDR_A_CTRL2, 1 << 4 | 3 << 0); +} + +static void aml_spdif_enable(void) +{ + /* reset */ + audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, 3 << 28, 0); + audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, 1 << 29, 1 << 29); + audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, 1 << 28, 1 << 28); + /* enable */ + audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, 1 << 31, 1 << 31); + + /* tohdmitx enable */ + audiobus_write(EE_AUDIO_TOHDMITX_CTRL0, + 1 << 3 /* spdif_clk_cap_inv */ + | 0 << 2 /* spdif_clk_inv */ + | 0 << 1 /* spdif_out */ + | 0 << 0 /* spdif_clk */ + ); + audiobus_update_bits(EE_AUDIO_TOHDMITX_CTRL0, + 0x1 << 30, 0x1 << 30); + + audiobus_update_bits(EE_AUDIO_TOHDMITX_CTRL0, + 0x1 << 31, 0x1 << 31); +} + +static void aml_spdif_play(void) +{ + struct aiu_958_channel_status chstat; + + chstat.chstat0_l = 0x0100; + chstat.chstat0_r = 0x0100; + chstat.chstat1_l = 0X200; + chstat.chstat1_r = 0X200; + + aml_spdif_fifo_ctrl(); + spdifout_set_pcm_chsts(&chstat); + frddr_init_without_mngr(); + aml_spdif_enable(); +} + +int aml_audio_init(void) +{ + printf("%s\n", __func__); + + aml_set_audio_spdif_clk(); + aml_spdif_play(); + + return 0; +} +
diff --git a/drivers/amlogic/media/vout/lcd/Kconfig b/drivers/amlogic/media/vout/lcd/Kconfig index 1c3fb81..42a0b5e 100644 --- a/drivers/amlogic/media/vout/lcd/Kconfig +++ b/drivers/amlogic/media/vout/lcd/Kconfig
@@ -1,3 +1,5 @@ +menu "AMLOGIC LCD Drivers" + config AML_LCD bool "lcd output for video" depends on AML_VOUT @@ -12,3 +14,5 @@ source "drivers/amlogic/media/vout/lcd/bl_ldim/Kconfig" source "drivers/amlogic/media/vout/lcd/bl_extern/Kconfig" endif + +endmenu
diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.h b/drivers/amlogic/media/vout/lcd/lcd_common.h index dedcba3..a14e79e 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_common.h +++ b/drivers/amlogic/media/vout/lcd/lcd_common.h
@@ -12,7 +12,9 @@ /* 20181106: init version */ #define LCD_DRV_VERSION "20181106" -#define VPP_OUT_SATURATE (1 << 0) +#define LCD_STATUS_IF_ON (1 << 0) +#define LCD_STATUS_ENCL_ON (1 << 1) +#define VPP_OUT_SATURATE (1 << 0) /* -------------------------- */ /* lvsd phy parameters define */
diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.c b/drivers/amlogic/media/vout/lcd/lcd_debug.c index fd48bb8..db7dd32 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_debug.c +++ b/drivers/amlogic/media/vout/lcd/lcd_debug.c
@@ -575,8 +575,8 @@ lcd_clk = (pconf->lcd_timing.lcd_clk / 1000); sync_duration = pconf->lcd_timing.sync_duration_num; - sync_duration = (sync_duration * 10 / pconf->lcd_timing.sync_duration_den); - LCDPR("%s, %s %ubit, %ux%u@%u.%uHz\n" + sync_duration = (sync_duration * 100 / pconf->lcd_timing.sync_duration_den); + LCDPR("%s, %s %ubit, %ux%u@%u.%2uHz\n" "fr_adj_type %d\n" "lcd_clk %u.%03uMHz\n" "ss_level %u\n\n", @@ -584,7 +584,7 @@ lcd_type_type_to_str(pconf->lcd_basic.lcd_type), pconf->lcd_basic.lcd_bits, pconf->lcd_basic.h_active, pconf->lcd_basic.v_active, - (sync_duration / 10), (sync_duration % 10), + (sync_duration / 100), (sync_duration % 100), pconf->lcd_timing.fr_adjust_type, (lcd_clk / 1000), (lcd_clk % 1000), pconf->lcd_timing.ss_level);
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c index acf472a..03156b2 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
@@ -306,8 +306,6 @@ lcd_vcbus_write(ENCL_VIDEO_EN, 0); - /* viu1 select encl | viu2 select encl */ - lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, (0 << 0) | (0 << 2)); lcd_vcbus_write(ENCL_VIDEO_MODE, 0x8000); /* bit[15] shadown en */ lcd_vcbus_write(ENCL_VIDEO_MODE_ADV, 0x0418); /* Sampling rate: 1 */
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c index 70e1964..297e4eb 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c
@@ -13,8 +13,13 @@ #include "lcd_tablet.h" #include "mipi_dsi_util.h" -static int check_lcd_output_mode(char *mode) +static int check_lcd_output_mode(char *mode, unsigned int frac) { + if (frac) { + LCDERR("don't support frac\n"); + return -1; + } + if (strcmp(mode, "panel") != 0) { LCDERR("outputmode[%s] is not support\n", mode); return -1; @@ -820,11 +825,11 @@ lcd_clk_generate_parameter(pconf); } -static int lcd_config_check(char *mode) +static int lcd_config_check(char *mode, unsigned int frac) { int ret; - ret = check_lcd_output_mode(mode); + ret = check_lcd_output_mode(mode, frac); if (ret) return -1;
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c index b2330b1..64e017b 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
@@ -217,8 +217,6 @@ lcd_vcbus_write(ENCL_VIDEO_EN, 0); - /* viu1 select encl | viu2 select encl */ - lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, (0 << 0) | (0 << 2)); lcd_vcbus_write(ENCL_VIDEO_MODE, 0x8000); /* bit[15] shadown en */ lcd_vcbus_write(ENCL_VIDEO_MODE_ADV, 0x0418); /* Sampling rate: 1 */
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c index 63bff47..578a0f8 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
@@ -28,6 +28,7 @@ unsigned int width; unsigned int height; unsigned int frame_rate; + unsigned int frac; }; @@ -46,6 +47,7 @@ .width = 1024, .height = 600, .frame_rate = 60, + .frac = 0, }, { .name = "768p", @@ -53,6 +55,7 @@ .width = 1366, .height = 768, .frame_rate = 60, + .frac = 0, }, { .name = "1080p", @@ -60,6 +63,7 @@ .width = 1920, .height = 1080, .frame_rate = 60, + .frac = 0, }, { .name = "2160p", @@ -67,6 +71,7 @@ .width = 3840, .height = 2160, .frame_rate = 60, + .frac = 0, }, { .name = "invalid", @@ -74,6 +79,7 @@ .width = 1920, .height = 1080, .frame_rate = 60, + .frac = 0, }, }; @@ -86,7 +92,7 @@ return -1; } -static int lcd_outputmode_to_lcd_vmode(const char *mode) +static int lcd_outputmode_to_vmode(const char *mode) { int lcd_vmode = LCD_VMODE_MAX; int i, count = ARRAY_SIZE(lcd_vmode_info) - 1; @@ -111,7 +117,7 @@ return lcd_vmode; } -static int lcd_outputmode_to_lcd_frame_rate(const char *mode) +static int lcd_outputmode_to_frame_rate(const char *mode) { int frame_rate = 0; char temp[30], *p; @@ -139,7 +145,7 @@ return frame_rate; } -static int check_lcd_output_mode(struct lcd_config_s *pconf, char *mode) +static int check_lcd_output_mode(struct lcd_config_s *pconf, char *mode, unsigned int frac) { int lcd_vmode, frame_rate; int ret; @@ -147,18 +153,12 @@ if (mode == NULL) return LCD_VMODE_MAX; - lcd_vmode = lcd_outputmode_to_lcd_vmode(mode); + lcd_vmode = lcd_outputmode_to_vmode(mode); if (lcd_vmode >= LCD_VMODE_MAX) { LCDERR("%s: outputmode %s is not support\n", __func__, mode); return LCD_VMODE_MAX; } - frame_rate = lcd_outputmode_to_lcd_frame_rate(mode); - if (frame_rate == 0) { - LCDERR("%s: frame_rate is not support\n", __func__); - return LCD_VMODE_MAX; - } else { - lcd_vmode_info[lcd_vmode].frame_rate = frame_rate; - } + ret = lcd_vmode_is_mached(pconf, lcd_vmode); if (ret) { LCDERR("outputmode[%s] and panel_type is not match\n", @@ -166,6 +166,22 @@ return LCD_VMODE_MAX; } + frame_rate = lcd_outputmode_to_frame_rate(mode); + if (frame_rate == 0) { + LCDERR("%s: frame_rate is not support\n", __func__); + return LCD_VMODE_MAX; + } + if (frac) { + if (frame_rate != 60) { + LCDERR("%s: don't support frac under mode %s\n", __func__, mode); + return LCD_VMODE_MAX; + } + lcd_vmode_info[lcd_vmode].frac = 1; + } else { + lcd_vmode_info[lcd_vmode].frac = 0; + } + lcd_vmode_info[lcd_vmode].frame_rate = frame_rate; + return lcd_vmode; } @@ -1018,29 +1034,34 @@ lcd_timing_init_config(pconf); } -static int lcd_outputmode_check(char *mode) +static int lcd_outputmode_check(char *mode, unsigned int frac) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); int lcd_vmode; - lcd_vmode = check_lcd_output_mode(lcd_drv->lcd_config, mode); + lcd_vmode = check_lcd_output_mode(lcd_drv->lcd_config, mode, frac); if (lcd_vmode >= LCD_VMODE_MAX) return -1; return 0; } -static int lcd_config_check(char *mode) +static int lcd_config_check(char *mode, unsigned int frac) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); int lcd_vmode; - lcd_vmode = check_lcd_output_mode(lcd_drv->lcd_config, mode); + lcd_vmode = check_lcd_output_mode(lcd_drv->lcd_config, mode, frac); if (lcd_vmode >= LCD_VMODE_MAX) return -1; - lcd_drv->lcd_config->lcd_timing.sync_duration_num = lcd_vmode_info[lcd_vmode].frame_rate; - lcd_drv->lcd_config->lcd_timing.sync_duration_den = 1; + if (lcd_vmode_info[lcd_vmode].frac) { + lcd_drv->lcd_config->lcd_timing.sync_duration_num = 5994; + lcd_drv->lcd_config->lcd_timing.sync_duration_den = 100; + } else { + lcd_drv->lcd_config->lcd_timing.sync_duration_num = lcd_vmode_info[lcd_vmode].frame_rate; + lcd_drv->lcd_config->lcd_timing.sync_duration_den = 1; + } /* update clk & timing config */ lcd_vmode_change(lcd_drv->lcd_config); lcd_tv_config_update(lcd_drv->lcd_config);
diff --git a/drivers/amlogic/media/vout/lcd/lcd_vout.c b/drivers/amlogic/media/vout/lcd/lcd_vout.c index 6f5c207..9dd1999 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_vout.c +++ b/drivers/amlogic/media/vout/lcd/lcd_vout.c
@@ -143,29 +143,22 @@ LCDPR("%s: %d\n", __func__, status); } -static void lcd_module_enable(char *mode) +static void lcd_encl_on(void) { - unsigned int sync_duration; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - struct lcd_config_s *pconf = lcd_drv->lcd_config; - int ret; - - ret = lcd_drv->config_check(mode); - if (ret) { - LCDERR("init exit\n"); - return; - } - - sync_duration = pconf->lcd_timing.sync_duration_num; - sync_duration = (sync_duration * 10 / pconf->lcd_timing.sync_duration_den); - LCDPR("enable: %s, %s, %ux%u@%u.%uHz\n", pconf->lcd_basic.model_name, - lcd_type_type_to_str(pconf->lcd_basic.lcd_type), - pconf->lcd_basic.h_active, pconf->lcd_basic.v_active, - (sync_duration / 10), (sync_duration % 10)); lcd_drv->driver_init_pre(); - lcd_power_ctrl(1); + lcd_vcbus_write(VENC_INTCTRL, 0x200); + lcd_drv->lcd_status |= LCD_STATUS_ENCL_ON; +} + +static void lcd_interface_on(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf = lcd_drv->lcd_config; + + lcd_power_ctrl(1); pconf->retry_enable_cnt = 0; while (pconf->retry_enable_flag) { if (pconf->retry_enable_cnt++ >= LCD_ENABLE_RETRY_MAX) @@ -176,16 +169,55 @@ lcd_power_ctrl(1); } pconf->retry_enable_cnt = 0; + lcd_drv->lcd_status |= LCD_STATUS_IF_ON; +} - lcd_vcbus_write(VPP_POSTBLEND_H_SIZE, pconf->lcd_basic.h_active); - lcd_vcbus_write(VENC_INTCTRL, 0x200); +static void lcd_backlight_enable(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); bl_pwm_config_update(lcd_drv->bl_config); bl_set_level(lcd_drv->bl_config->level_default); bl_power_ctrl(1); - lcd_mute_setting(0); +} - lcd_drv->lcd_status = 1; +static void lcd_module_enable(char *mode, unsigned int frac) +{ + unsigned int sync_duration; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf = lcd_drv->lcd_config; + int ret; + + ret = lcd_drv->config_check(mode, frac); + if (ret) { + LCDERR("init exit\n"); + return; + } + + sync_duration = pconf->lcd_timing.sync_duration_num; + sync_duration = (sync_duration * 100 / pconf->lcd_timing.sync_duration_den); + LCDPR("enable: %s, %s, %ux%u@%u.%2uHz\n", pconf->lcd_basic.model_name, + lcd_type_type_to_str(pconf->lcd_basic.lcd_type), + pconf->lcd_basic.h_active, pconf->lcd_basic.v_active, + (sync_duration / 100), (sync_duration % 100)); + + if ((lcd_drv->lcd_status & LCD_STATUS_ENCL_ON) == 0) + lcd_encl_on(); + if ((lcd_drv->lcd_status & LCD_STATUS_IF_ON) == 0) { + lcd_interface_on(); + lcd_backlight_enable(); + } + + pconf->retry_enable_cnt = 0; + while (pconf->retry_enable_flag) { + if (pconf->retry_enable_cnt++ >= LCD_ENABLE_RETRY_MAX) + break; + LCDPR("retry enable...%d\n", pconf->retry_enable_cnt); + lcd_power_ctrl(0); + mdelay(1000); + lcd_power_ctrl(1); + } + lcd_mute_setting(0); } static void lcd_module_disable(void) @@ -195,13 +227,29 @@ LCDPR("disable: %s\n", lcd_drv->lcd_config->lcd_basic.model_name); lcd_mute_setting(1); - bl_power_ctrl(0); - - lcd_power_ctrl(0); + if (lcd_drv->lcd_status & LCD_STATUS_IF_ON) { + bl_power_ctrl(0); + lcd_power_ctrl(0); + } lcd_drv->lcd_status = 0; } +static void lcd_module_prepare(char *mode, unsigned int frac) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + int ret; + + ret = lcd_drv->config_check(mode, frac); + if (ret) { + LCDERR("prepare exit\n"); + return; + } + + if ((lcd_drv->lcd_status & LCD_STATUS_ENCL_ON) == 0) + lcd_encl_on(); +} + static void lcd_vbyone_filter_flag_print(struct lcd_config_s *pconf) { struct vbyone_config_s *vx1_conf = pconf->lcd_control.vbyone_config; @@ -626,30 +674,40 @@ /* ********************************************** * lcd driver API * ********************************************** */ -static int lcd_outputmode_check(char *mode) +static int lcd_outputmode_check(char *mode, unsigned int frac) { if (aml_lcd_driver.outputmode_check) - return aml_lcd_driver.outputmode_check(mode); + return aml_lcd_driver.outputmode_check(mode, frac); LCDERR("invalid lcd config\n"); return -1; } -static void lcd_enable(char *mode) +static void lcd_prepare(char *mode, unsigned int frac) { if (lcd_check_valid()) return; - if (aml_lcd_driver.lcd_status) + if (aml_lcd_driver.lcd_status & LCD_STATUS_ENCL_ON) LCDPR("already enabled\n"); else - lcd_module_enable(mode); + lcd_module_prepare(mode, frac); +} + +static void lcd_enable(char *mode, unsigned int frac) +{ + if (lcd_check_valid()) + return; + if (aml_lcd_driver.lcd_status & LCD_STATUS_IF_ON) + LCDPR("already enabled\n"); + else + lcd_module_enable(mode, frac); } static void lcd_disable(void) { if (lcd_check_valid()) return; - if (aml_lcd_driver.lcd_status) + if (aml_lcd_driver.lcd_status & LCD_STATUS_ENCL_ON) lcd_module_disable(); else LCDPR("already disabled\n"); @@ -783,6 +841,7 @@ .config_check = NULL, .lcd_probe = lcd_probe, .lcd_outputmode_check = lcd_outputmode_check, + .lcd_prepare = lcd_prepare, .lcd_enable = lcd_enable, .lcd_disable = lcd_disable, .lcd_set_ss = lcd_set_ss,
diff --git a/drivers/amlogic/media/vout/vout.c b/drivers/amlogic/media/vout/vout.c index 26713d4..678298c 100644 --- a/drivers/amlogic/media/vout/vout.c +++ b/drivers/amlogic/media/vout/vout.c
@@ -6,6 +6,8 @@ #include <common.h> #include <asm/arch/io.h> #include <asm/arch/secure_apb.h> +#include <amlogic/cpu_id.h> +#include <amlogic/media/vpp/vpp.h> #include <amlogic/media/vout/aml_vmode.h> #include <amlogic/media/vout/aml_vout.h> #ifdef CONFIG_AML_LCD @@ -21,9 +23,15 @@ vout_log("%s:%d\n", __func__, __LINE__); \ } while (0) +#ifndef REG_BASE_VCBUS +#define REG_BASE_VCBUS (0xff900000L) +#endif #define REG_OFFSET_VCBUS(reg) ((reg << 2)) #define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg)) +#define REG_CLK_ADDR(reg) (reg + 0L) +#define REG_VOUT_ADDR(reg) (reg + 0L) + static int g_vmode = -1; typedef struct vout_set_s { @@ -32,6 +40,8 @@ ulong width; ulong height; ulong field_height; + int viu_color_fmt; + enum viu_mux_e viu_mux; } vout_set_t; @@ -42,6 +52,8 @@ .width = 720, .height = 480, .field_height = 240, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCI, }, { /* VMODE_480CVBS*/ .name = "480cvbs", @@ -49,6 +61,8 @@ .width = 720, .height = 480, .field_height = 240, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCI, }, { /* VMODE_480P */ .name = "480p", @@ -56,6 +70,8 @@ .width = 720, .height = 480, .field_height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_576I */ .name = "576i", @@ -63,6 +79,8 @@ .width = 720, .height = 576, .field_height = 288, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCI, }, { /* VMODE_576I */ .name = "576cvbs", @@ -70,6 +88,8 @@ .width = 720, .height = 576, .field_height = 288, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCI, }, { /* VMODE_576P */ .name = "576p", @@ -77,6 +97,8 @@ .width = 720, .height = 576, .field_height = 576, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_720P */ .name = "720p", @@ -84,6 +106,8 @@ .width = 1280, .height = 720, .field_height = 720, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_768P */ .name = "768p", @@ -91,6 +115,8 @@ .width = 1366, .height = 768, .field_height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1080I */ .name = "1080i", @@ -98,6 +124,8 @@ .width = 1920, .height = 1080, .field_height = 540, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1080P */ .name = "1080p", @@ -105,6 +133,8 @@ .width = 1920, .height = 1080, .field_height = 1080, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_4K2K_60HZ */ .name = "2160p", @@ -112,6 +142,8 @@ .width = 3840, .height = 2160, .field_height = 2160, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_4K2K_SMPTE */ .name = "smpte", @@ -119,6 +151,8 @@ .width = 4096, .height = 2160, .field_height = 2160, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_vga */ .name = "vga", @@ -126,6 +160,8 @@ .width = 640, .height = 480, .field_height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_SVGA */ .name = "svga", @@ -133,6 +169,8 @@ .width = 800, .height = 600, .field_height = 600, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_XGA */ .name = "xga", @@ -140,6 +178,8 @@ .width = 1024, .height = 768, .field_height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_sxga */ .name = "sxga", @@ -147,6 +187,8 @@ .width = 1280, .height = 1024, .field_height = 1024, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_wsxga */ .name = "wsxga", @@ -154,6 +196,8 @@ .width = 1440, .height = 900, .field_height = 900, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_fhdvga */ .name = "fhdvga", @@ -161,6 +205,8 @@ .width = 1920, .height = 1080, .field_height = 1080, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_LCD */ .name = "panel", @@ -168,150 +214,200 @@ .width = 1920, .height = 1080, .field_height = 1080, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_640x480p60hz */ .name = "640x480p60hz", .mode = VMODE_640x480p60hz, .width = 640, .height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_800x480p60hz */ .name = "800x480p60hz", .mode = VMODE_800x480p60hz, .width = 800, .height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_800x600p60hz */ .name = "800x600p60hz", .mode = VMODE_800x600p60hz, .width = 800, .height = 600, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_852x480p60hz */ .name = "852x480p60hz", .mode = VMODE_852x480p60hz, .width = 852, .height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_854x480p60hz */ .name = "854x480p60hz", .mode = VMODE_854x480p60hz, .width = 854, .height = 480, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1024x768p60hz */ .name = "1024x768p60hz", .mode = VMODE_1024x768p60hz, .width = 1024, .height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1152x864p75hz */ .name = "1152x864p75hz", .mode = VMODE_1152x864p75hz, .width = 1152, .height = 864, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x600p60hz */ .name = "1280x600p60hz", .mode = VMODE_1280x600p60hz, .width = 1280, .height = 600, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x768p60hz */ .name = "1280x768p60hz", .mode = VMODE_1280x768p60hz, .width = 1280, .height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x800p60hz */ .name = "1280x800p60hz", .mode = VMODE_1280x800p60hz, .width = 1280, .height = 800, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x960p60hz */ .name = "1280x960p60hz", .mode = VMODE_1280x960p60hz, .width = 1280, .height = 960, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1280x1024p60hz */ .name = "1280x1024p60hz", .mode = VMODE_1280x1024p60hz, .width = 1280, .height = 1024, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1360x768p60hz */ .name = "1360x768p60hz", .mode = VMODE_1360x768p60hz, .width = 1360, .height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1366x768p60hz */ .name = "1366x768p60hz", .mode = VMODE_1366x768p60hz, .width = 1366, .height = 768, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1400x1050p60hz */ .name = "1400x1050p60hz", .mode = VMODE_1400x1050p60hz, .width = 1400, .height = 1050, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1440x900p60hz */ .name = "1440x900p60hz", .mode = VMODE_1440x900p60hz, .width = 1440, .height = 900, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1440x2560p60hz */ .name = "1440x2560p60hz", .mode = VMODE_1440x2560p60hz, .width = 1440, .height = 2560, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1440x2560p70hz */ .name = "1440x2560p70hz", .mode = VMODE_1440x2560p70hz, .width = 1440, .height = 2560, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1600x900p60hz */ .name = "1600x900p60hz", .mode = VMODE_1600x900p60hz, .width = 1600, .height = 900, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1600x1200p60hz */ .name = "1600x1200p60hz", .mode = VMODE_1600x1200p60hz, .width = 1600, .height = 1200, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1680x1050p60hz */ .name = "1680x1050p60hz", .mode = VMODE_1680x1050p60hz, .width = 1680, .height = 1050, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_1920x1200p60hz */ .name = "1920x1200p60hz", .mode = VMODE_1920x1200p60hz, .width = 1920, .height = 1200, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_2160x1200p90hz */ .name = "2160x1200p90hz", .mode = VMODE_2160x1200p90hz, .width = 2160, .height = 1200, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, { /* VMODE_2560x1080p60hz */ .name = "2560x1080p60hz", .mode = VMODE_2560x1080p60hz, .width = 2560, .height = 1080, + .viu_color_fmt = VPP_CM_YUV, + .viu_mux = VIU_MUX_ENCP, }, }; @@ -332,9 +428,60 @@ .priv = NULL, /* Pointer to driver-specific data */ }; +#ifndef HHI_VPU_CLKC_CNTL +#define HHI_VPU_CLKC_CNTL (0xff63c000 + (0x06d << 2)) +#endif +#ifndef CLKCTRL_VPU_CLKC_CTRL +#define CLKCTRL_VPU_CLKC_CTRL ((0x003c << 2) + 0xfe000000) +#endif +#ifndef VPU_VENCX_CLK_CTRL +#define VPU_VENCX_CLK_CTRL 0x2785 +#endif + +static inline unsigned int vout_reg_read(u32 reg) +{ + unsigned int val; + + if (reg > 0x10000) + val = *(volatile unsigned int *)REG_VOUT_ADDR(reg); + else + val = (*(volatile unsigned int *)REG_ADDR_VCBUS(reg)); + + return val; +} + static inline void vout_reg_write(u32 reg, const u32 val) { - *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val); + if (reg > 0x10000) + *(volatile unsigned int *)REG_VOUT_ADDR(reg) = (val); + else + *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val); +} + +static inline void vout_reg_setb(unsigned int reg, unsigned int val, + unsigned int start, unsigned int len) +{ + vout_reg_write(reg, ((vout_reg_read(reg) & + ~(((1L << (len))-1) << (start))) | + (((val)&((1L<<(len))-1)) << (start)))); +} + +static inline unsigned int vout_clk_read(u32 reg) +{ + return *(volatile unsigned int *)(REG_CLK_ADDR(reg)); +} + +static inline void vout_clk_write(u32 reg, const u32 val) +{ + *(volatile unsigned int *)REG_CLK_ADDR(reg) = (val); +} + +static inline void vout_clk_setb(unsigned int reg, unsigned int val, + unsigned int start, unsigned int len) +{ + vout_clk_write(reg, ((vout_clk_read(reg) & + ~(((1L << (len))-1) << (start))) | + (((val)&((1L<<(len))-1)) << (start)))); } static int vout_find_mode_by_name(const char *name) @@ -398,15 +545,20 @@ return height; } +static unsigned int vout_env2uint(const char *name, int base) +{ + return (unsigned int)env_get_ulong(name, base, 0); +} + static void vout_vinfo_init(ulong width, ulong height, ulong field_height) { vout_info.width = width; vout_info.height = height; vout_info.field_height = field_height; vout_info.vd_base = (void *)get_fb_addr(); - vout_info.vl_bpix = simple_strtoul(env_get("display_bpp"), NULL, 10); - vout_info.vd_color_fg = simple_strtoul(env_get("display_color_fg"), NULL, 0); - vout_info.vd_color_bg = simple_strtoul(env_get("display_color_bg"), NULL, 0); + vout_info.vl_bpix = (unsigned char)vout_env2uint("display_bpp", 10); + vout_info.vd_color_fg = vout_env2uint("display_color_fg", 0); + vout_info.vd_color_bg = vout_env2uint("display_color_bg", 0); } static void vout_axis_init(ulong w, ulong h) @@ -598,6 +750,73 @@ vout_log("vinfo.vd_color_bg: %d\n", info->vd_color_bg); } +static unsigned int vout_viu1_mux = VIU_MUX_MAX; +static unsigned int vout_viu2_mux = VIU_MUX_MAX; +void vout_viu_mux(int viu_sel, int venc_sel) +{ + unsigned int clk_bit = 0xff, clk_sel = 0; + unsigned int viu2_valid = 0; + unsigned int vout_viu_sel = 0xf; + + switch (get_cpu_id().family_id) { + case MESON_CPU_MAJOR_ID_G12A: + case MESON_CPU_MAJOR_ID_G12B: + case MESON_CPU_MAJOR_ID_TL1: + case MESON_CPU_MAJOR_ID_TM2: + case MESON_CPU_MAJOR_ID_SM1: + viu2_valid = 1; + break; + default: + break; + } + + switch (viu_sel) { + case VOUT_VIU2_SEL: + if (viu2_valid) { + /* set cts_vpu_clkc to 200MHz*/ + vout_clk_setb(HHI_VPU_CLKC_CNTL, 2, 9, 3); + vout_clk_setb(HHI_VPU_CLKC_CNTL, 1, 0, 1); + vout_clk_setb(HHI_VPU_CLKC_CNTL, 1, 8, 3); + clk_sel = 1; + } + if (venc_sel == vout_viu1_mux) + vout_viu1_mux = VIU_MUX_MAX; + vout_viu2_mux = venc_sel; + break; + case VOUT_VIU1_SEL: + if (viu2_valid) + vout_clk_setb(HHI_VPU_CLKC_CNTL, 0, 8, 1); + clk_sel = 0; + if (venc_sel == vout_viu2_mux) + vout_viu2_mux = VIU_MUX_MAX; + vout_viu1_mux = venc_sel; + break; + default: + break; + } + vout_viu_sel = (vout_viu1_mux | (vout_viu2_mux << 2)); + + switch (venc_sel) { + case VIU_MUX_ENCL: + clk_bit = 1; + break; + case VIU_MUX_ENCI: + clk_bit = 2; + break; + case VIU_MUX_ENCP: + clk_bit = 0; + break; + default: + break; + } + + vout_reg_setb(VPU_VIU_VENC_MUX_CTRL, vout_viu_sel, 0, 4); + if (viu2_valid) { + if (clk_bit < 0xff) + vout_reg_setb(VPU_VENCX_CLK_CTRL, clk_sel, clk_bit, 1); + } +} + void vout_init(void) { vout_logl();
diff --git a/drivers/amlogic/provision/Kconfig b/drivers/amlogic/provision/Kconfig new file mode 100644 index 0000000..b258e45 --- /dev/null +++ b/drivers/amlogic/provision/Kconfig
@@ -0,0 +1,4 @@ +config FAT_WRITE + bool "enable fat write" +config AML_FACTORY_PROVISION + bool "enable factory provision"
diff --git a/drivers/amlogic/storagekey/Makefile b/drivers/amlogic/storagekey/Makefile index d7ae8cd..6e7ccb4 100644 --- a/drivers/amlogic/storagekey/Makefile +++ b/drivers/amlogic/storagekey/Makefile
@@ -1,2 +1,3 @@ obj-$(CONFIG_SECURE_STORAGE) += storagekey.o obj-$(CONFIG_SECURE_STORAGE) += securestorage.o +obj-$(CONFIG_SECURE_STORAGE) += normal_key.o
diff --git a/drivers/amlogic/storagekey/normal_key.c b/drivers/amlogic/storagekey/normal_key.c new file mode 100644 index 0000000..bd0a346 --- /dev/null +++ b/drivers/amlogic/storagekey/normal_key.c
@@ -0,0 +1,657 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <linux/types.h> +#include <linux/list.h> +#include <u-boot/sha256.h> +#include <malloc.h> +#include "normal_key.h" + +#undef pr_info +#define pr_info(fmt ...) printf("[KM]Msg:"fmt) +#undef pr_err +#define pr_err(fmt ...) printf("[KM]Error:f[%s]L%d:", __func__, __LINE__),printf(fmt) + +#define DBG 0 + +/* Storage BLOCK RAW HEAD: fixed 512B*/ +#define ENC_TYPE_DEFAULT 0 +#define ENC_TYPE_EFUSE 1 +#define ENC_TYPE_FIXED 2 + +#define STORAGE_BLOCK_RAW_HEAD_SIZE 512 + +#define BLOCK_VERSION_0 0 + +#define ERR_HEADER 0x1 +#define ERR_KEYMEMFAIL 0x2 +#define ERR_KEYRDFAIL 0x4 +#define ERR_KEYCHKFAIL 0x8 +#define ERR_ENCHDFAIL 0x10 +#define ERR_DATASZ 0x20 +struct storage_block_raw_head { + u8 mark[16]; /* AMLNORMAL*/ + u32 version; + u32 enctype; /*from EFUSE, from default, from fixed*/ + u32 keycnt; + u32 initcnt; + u32 wrtcnt; + u32 errcnt; + u32 flags; + u8 headhash[32]; + u8 hash[32]; +}; + +/* Storage BLOCK ENC HEAD: fixed 512B*/ +#define STORAGE_BLOCK_ENC_HEAD_SIZE 512 +struct storage_block_enc_head { + u32 blocksize; + u32 flashsize; +}; + +/* Storage Format: TLV*/ +enum emTLVTag { + EMTLVNONE, + + EMTLVHEAD, + EMTLVHEADSIZE, + + EMTLVOBJECT, + EMTLVOBJNAMESIZE, + EMTLVOBJNAME, + EMTLVOBJDATASIZE, + EMTLVOBJDATABUF, + EMTLVOBJTYPE, + EMTLVOBJATTR, + EMTLVOBJHASHBUF, + + EMTLVHEADFLASHSIZE, +}; + +struct storage_node { + struct list_head node; + struct storage_object object; +}; + +static LIST_HEAD(keys); +static int blockinited; +static struct storage_block_raw_head rawhead; +static struct storage_block_enc_head enchead; +static char *blockmark = "AMLNORMAL"; + +#if DBG +static void dump_raw_head(struct storage_block_raw_head *prawhead) +{ + pr_info("rawhead:\n"); + pr_info("mark: %s\n", prawhead->mark); + pr_info("keycnt: %u\n", prawhead->keycnt); + pr_info("initcnt: %u\n", prawhead->initcnt); + pr_info("wrtcnt: %u\n", prawhead->wrtcnt); + pr_info("errcnt: %u\n", prawhead->errcnt); + pr_info("flags: 0x%x\n", prawhead->flags); +} + +static void dump_enc_head(struct storage_block_enc_head *penchead) +{ + pr_info("enchead:\n"); + pr_info("blocksize: %u\n", penchead->blocksize); + pr_info("flashsize: %u\n", penchead->flashsize); +} + +static void dump_mem(const u8 *p, int len) +{ + int idx = 0, j, tmp; + char buf[64]; + int total; + + while (idx < len) { + total = 0; + tmp = min(((int)len - idx), 16); + for (j = 0; j < tmp; j++) + total += snprintf(buf + total, 64 - total, + "%02x ", p[idx + j]); + buf[total] = 0; + pr_info("%s\n", buf); + idx += tmp; + } +} + +static void dump_object(struct storage_object *obj) +{ + pr_info("key: [%u, %.*s, %x, %x, %u]\n", + obj->namesize, obj->namesize, obj->name, + obj->type, obj->attribute, obj->datasize); + if (obj->dataptr) { + pr_info("data:\n"); + dump_mem(obj->dataptr, obj->datasize); + } +} +#endif + +static u32 Tlv_WriteUint32(u8 *output, s32 len, + u32 tag, u32 value) +{ + u32 *out = (u32 *)output; + + if (len < 12) + return 0; + + out[0] = tag; + out[1] = 4; + out[2] = value; + return 12; +} + +static u32 Tlv_WriteBuf(u8 *output, s32 len, + u32 tag, + u32 length, u8 *input) +{ + u8 *out = output; + u32 tmplen = (((length + 3) / 4) * 4); + + if (len < (s32)(8 + tmplen)) + return 0; + + *((u32 *)out) = tag; + *((u32 *)(out + 4)) = tmplen; + memset(out + 8, 0, tmplen); + memcpy(out + 8, input, length); + + return tmplen + 8; +} + +static u32 Tlv_ReadTl(u8 *input, int32_t len, + u32 *tag, u32 *length, + u32 *idx) +{ + if (len < 8) + return 0; + + *tag = *((u32 *)input); + *length = *((u32 *)(input + 4)); + + if ((8 + *length) > len) + return 0; + *idx += 8; + + return 8; +} + +static u32 Tlv_ReadHead(u8 *input, int32_t len, + struct storage_block_enc_head *pblockhead) +{ + u32 tag; + u32 sum; + u32 length; + u32 idx = 0; + u32 ret; + + ret = Tlv_ReadTl(input, len, + &tag, &sum, &idx); + if (!ret) + return 0; + + if (tag != EMTLVHEAD) + return 0; + + sum += ret; + while (idx < sum) { + ret = Tlv_ReadTl(input + idx, len - idx, + &tag, &length, &idx); + if (!ret) + return 0; + + switch (tag) { + case EMTLVHEADSIZE: + pblockhead->blocksize = *((u32 *)(input + idx)); + break; + case EMTLVHEADFLASHSIZE: + pblockhead->flashsize = *((u32 *)(input + idx)); + break; + default: + break; + } + idx += length; + } + return sum; +} + +static u32 Tlv_ReadObject(u8 *input, int32_t len, + struct storage_object *pcontent) +{ + u32 tag; + u32 length; + u32 sum; + u32 idx = 0; + u32 ret; + + memset(pcontent, 0, sizeof(*pcontent)); + ret = Tlv_ReadTl(input, len, + &tag, &sum, &idx); + if (!ret) + return 0; + + if (tag != EMTLVOBJECT) + return 0; + + sum += ret; + while (idx < sum) { + ret = Tlv_ReadTl(input + idx, len - idx, + &tag, &length, &idx); + if (!ret) + goto tlv_readkeycontent_err; + + switch (tag) { + case EMTLVOBJNAMESIZE: + pcontent->namesize = *((u32 *)(input + idx)); + break; + case EMTLVOBJNAME: + memset(pcontent->name, 0, MAX_OBJ_NAME_LEN); + memcpy(pcontent->name, input + idx, pcontent->namesize); + break; + case EMTLVOBJTYPE: + pcontent->type = *((u32 *)(input + idx)); + break; + case EMTLVOBJATTR: + pcontent->attribute = *((u32 *)(input + idx)); + break; + case EMTLVOBJDATASIZE: + pcontent->datasize = *((u32 *)(input + idx)); + break; + case EMTLVOBJHASHBUF: + if (length != 32) + goto tlv_readkeycontent_err; + memcpy(pcontent->hashptr, input + idx, length); + break; + case EMTLVOBJDATABUF: + pcontent->dataptr = malloc(pcontent->datasize); + if (!pcontent->dataptr) + goto tlv_readkeycontent_err; + memcpy(pcontent->dataptr, + input + idx, pcontent->datasize); + break; + default: + break; + } + idx += length; + } + return sum; + +tlv_readkeycontent_err: + free(pcontent->dataptr); + return 0; +} + +#define WRT_UINT32(tag, field) \ + ({ \ + u32 __tmp; \ + __tmp = Tlv_WriteUint32(output + idx, len - idx, \ + tag, field); \ + if (__tmp) \ + idx += __tmp; \ + __tmp; \ + }) + +#define WRT_BUF(tag, buflen, buf) \ + ({ \ + u32 __tmp; \ + __tmp = Tlv_WriteBuf(output + idx, len - idx, \ + tag, buflen, buf); \ + if (__tmp) \ + idx += __tmp; \ + __tmp; \ + }) + +u32 Tlv_WriteHead(struct storage_block_enc_head *enchead, + u8 *output, int32_t len) +{ + u32 *sum; + u32 idx = 0; + + if (len < 8) + return 0; + + *(u32 *)output = EMTLVHEAD; + sum = (u32 *)(output + 4); + idx += 8; + + if (!WRT_UINT32(EMTLVHEADSIZE, enchead->blocksize)) + return 0; + if (!WRT_UINT32(EMTLVHEADFLASHSIZE, enchead->flashsize)) + return 0; + + *sum = idx - 8; + return idx; +} + +u32 Tlv_WriteObject(struct storage_object *object, + u8 *output, int32_t len) +{ + u32 *sum; + u32 idx = 0; + + if (len < 8) + return 0; + + *(u32 *)output = EMTLVOBJECT; + sum = (u32 *)(output + 4); + idx += 8; + + if (object->namesize != 0) { + if (!WRT_UINT32(EMTLVOBJNAMESIZE, object->namesize)) + return 0; + if (!WRT_BUF(EMTLVOBJNAME, object->namesize, + (u8 *)object->name)) + return 0; + } + + if (object->dataptr && object->datasize != 0) { + if (!WRT_UINT32(EMTLVOBJDATASIZE, object->datasize)) + return 0; + if (!WRT_BUF(EMTLVOBJDATABUF, object->datasize, + object->dataptr)) + return 0; + } + + if (!WRT_BUF(EMTLVOBJHASHBUF, 32, object->hashptr)) + return 0; + if (!WRT_UINT32(EMTLVOBJTYPE, object->type)) + return 0; + if (!WRT_UINT32(EMTLVOBJATTR, object->attribute)) + return 0; + + *sum = idx - 8; + return idx; +} + +static int normalkey_hash(u8 *data, u32 len, u8 *hash) +{ + sha256_context ctx; + sha256_starts(&ctx); + sha256_update(&ctx, data, len); + sha256_finish(&ctx, hash); + return 0; +} + +int normalkey_init(void) +{ + if (blockinited) + return 0; + + blockinited = 1; + return 0; +} + +void normalkey_deinit(void) +{ + struct storage_node *pos, *n; + + if (!blockinited) + return; + + blockinited = 0; + + list_for_each_entry_safe(pos, n, &keys, node) { + list_del(&pos->node); + free(pos->object.dataptr); + free(pos); + } +} + +struct storage_object *normalkey_get(const u8 *name) +{ + struct storage_node *pos; + struct storage_object *obj; + u32 len; + + if (!name) + return NULL; + + len = strlen((const char*)name); + list_for_each_entry(pos, &keys, node) { + obj = &pos->object; + if (len == obj->namesize && + !memcmp(name, obj->name, len)) + return obj; + } + + return NULL; +} + +int normalkey_add(const u8 *name, u8 *buffer, u32 len, u32 attr) +{ + struct storage_object *obj; + struct storage_node *node; + u32 namelen; + u8 *data; + + if (blockinited != 2) + return -1; + + if (!name || !buffer || !len || (attr & OBJ_ATTR_SECURE)) + return -1; + + namelen = strlen((const char*)name); + if (namelen > MAX_OBJ_NAME_LEN) + return -1; + + obj = normalkey_get(name); + if (obj) { + if (attr != obj->attribute) + return -1; + if (len > obj->datasize) { + data = malloc(len); + if (!data) + return -1; + free(obj->dataptr); + obj->dataptr = data; + } + } else { + node = malloc(sizeof(*node)); + if (!node) + return -1; + data = malloc(len); + if (!data) { + free(node); + return -1; + } + obj = &node->object; + memcpy(obj->name, name, namelen); + obj->namesize = namelen; + obj->attribute = attr; + obj->type = OBJ_TYPE_GENERIC; + obj->dataptr = data; + list_add(&node->node, &keys); + } + obj->datasize = len; + memcpy(obj->dataptr, buffer, len); + normalkey_hash(buffer, len, obj->hashptr); + return 0; +} + +int normalkey_del(const u8 *name) +{ + struct storage_object *obj; + struct storage_node *node; + + if (blockinited != 2) + return -1; + + obj = normalkey_get(name); + if (!obj) + return -1; + + node = container_of(obj, struct storage_node, object); + list_del(&node->node); + free(obj->dataptr); + free(node); + + return 0; +} + +int normalkey_readfromblock(void *block, unsigned long size) +{ + struct storage_block_raw_head *prawhead; + u8 *penchead, *pdata; + struct storage_node *node = NULL; + u8 hash[32]; + u32 idx; + u32 ret; + + if (blockinited != 1) + return -1; + + prawhead = (struct storage_block_raw_head *)block; + penchead = (u8 *)block + STORAGE_BLOCK_RAW_HEAD_SIZE; + pdata = penchead + STORAGE_BLOCK_ENC_HEAD_SIZE; + + if (!block || size <= + (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE)) + return -1; + + blockinited = 2; + + memset(&rawhead, 0, sizeof(rawhead)); + strncpy((char*)rawhead.mark, blockmark, 15); + rawhead.version = BLOCK_VERSION_0; + + enchead.flashsize = size; + if (strcmp((const char *)prawhead->mark, blockmark) != 0) { + pr_info("mark is not found\n"); + return 0; + } + + normalkey_hash((u8 *)prawhead, sizeof(*prawhead) - 64, + rawhead.headhash); + if (memcmp(rawhead.headhash, prawhead->headhash, 32)) { + pr_info("rawhead hash check fail\n"); + rawhead.flags |= ERR_HEADER; + } else { + pr_info("rawhead hash check successful\n"); + rawhead.keycnt = prawhead->keycnt; + rawhead.initcnt = prawhead->initcnt; + rawhead.wrtcnt = prawhead->wrtcnt; + rawhead.errcnt = prawhead->errcnt; + rawhead.flags = prawhead->flags; + } + + rawhead.initcnt++; + +#if DBG + dump_raw_head(&rawhead); +#endif + + normalkey_hash(penchead, size - STORAGE_BLOCK_RAW_HEAD_SIZE, + rawhead.hash); + if (memcmp(rawhead.hash, prawhead->hash, 32)) { + pr_info("data hash check fail\n"); + rawhead.errcnt++; + return 0; + } + + ret = Tlv_ReadHead(penchead, STORAGE_BLOCK_ENC_HEAD_SIZE, + &enchead); + if (!ret) { + pr_info("read head fail\n"); + rawhead.flags |= ERR_ENCHDFAIL; + return 0; + } + +#if DBG + dump_enc_head(&enchead); +#endif + + if (size < (enchead.blocksize + STORAGE_BLOCK_ENC_HEAD_SIZE + + STORAGE_BLOCK_RAW_HEAD_SIZE)) { + rawhead.flags |= ERR_DATASZ; + return 0; + } + + idx = 0; + while (idx < enchead.blocksize) { + struct storage_object *obj = NULL; + + if (!node) { + node = malloc(sizeof(*node)); + if (!node) { + rawhead.flags |= ERR_KEYMEMFAIL; + break; + } + } + obj = &node->object; + ret = Tlv_ReadObject(pdata + idx, + enchead.blocksize - idx, obj); + if (!ret) { + rawhead.flags |= ERR_KEYRDFAIL; + break; + } + idx += ret; + + normalkey_hash(obj->dataptr, obj->datasize, hash); + if (memcmp(hash, obj->hashptr, 32)) { + free(obj->dataptr); + rawhead.flags |= ERR_KEYCHKFAIL; + continue; + } +#if DBG + dump_object(obj); +#endif + list_add(&node->node, &keys); + node = NULL; + } + + free(node); + return 0; +} + +int normalkey_writetoblock(void *block, unsigned long size) +{ + u8 *prawhead; + u8 *penchead, *pdata; + struct storage_object *obj = NULL; + struct storage_node *node = NULL; + u32 idx; + u32 ret; + + if (blockinited != 2) + return -1; + + prawhead = (u8 *)block; + penchead = prawhead + STORAGE_BLOCK_RAW_HEAD_SIZE; + pdata = penchead + STORAGE_BLOCK_ENC_HEAD_SIZE; + + if (!block || size <= + (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE)) + return -1; + + enchead.flashsize = size; + size -= (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE); + idx = 0; + rawhead.keycnt = 0; + list_for_each_entry(node, &keys, node) { + obj = &node->object; + ret = Tlv_WriteObject(obj, pdata + idx, size - idx); + if (!ret) + return -1; + idx += ret; + rawhead.keycnt++; + } + enchead.blocksize = idx; + + ret = Tlv_WriteHead(&enchead, penchead, STORAGE_BLOCK_ENC_HEAD_SIZE); + if (!ret) + return -1; + + rawhead.wrtcnt++; + normalkey_hash((u8 *)&rawhead, sizeof(rawhead) - 64, + rawhead.headhash); + normalkey_hash(penchead, + enchead.flashsize - STORAGE_BLOCK_RAW_HEAD_SIZE, + rawhead.hash); + memcpy(prawhead, &rawhead, sizeof(rawhead)); + + return 0; +}
diff --git a/drivers/amlogic/storagekey/normal_key.h b/drivers/amlogic/storagekey/normal_key.h new file mode 100644 index 0000000..a95b821 --- /dev/null +++ b/drivers/amlogic/storagekey/normal_key.h
@@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _AML_NORMAL_KEY_H_ +#define _AML_NORMAL_KEY_H_ + +#define MAX_OBJ_NAME_LEN 80 + +/*Attribute*/ +#define OBJ_ATTR_SECURE BIT(0) +#define OBJ_ATTR_OTP BIT(1) +#define OBJ_ATTR_ENC BIT(8) + +/* Type */ +#define OBJ_TYPE_GENERIC 0xA00000BF + +struct storage_object { + char name[MAX_OBJ_NAME_LEN]; + u32 namesize; + u32 attribute; /*secure, OTP*/ + u32 type; /*AES, RSA, GENERIC, ...*/ + u32 datasize; + u8 *dataptr; + u8 hashptr[32]; +}; + +int normalkey_init(void); +void normalkey_deinit(void); +struct storage_object *normalkey_get(const u8 *name); +int normalkey_add(const u8 *name, u8 *buffer, u32 len, u32 attr); +int normalkey_del(const u8 *name); +int normalkey_readfromblock(void *block, unsigned long size); +int normalkey_writetoblock(void *block, unsigned long size); + +#endif
diff --git a/drivers/amlogic/storagekey/storagekey.c b/drivers/amlogic/storagekey/storagekey.c index c13c92d..f3e06ba 100644 --- a/drivers/amlogic/storagekey/storagekey.c +++ b/drivers/amlogic/storagekey/storagekey.c
@@ -20,6 +20,7 @@ #ifdef CONFIG_STORE_COMPATIBLE #include <partition_table.h> #endif +#include "normal_key.h" /* key buffer status */ /* bit0, dirty flag*/ @@ -45,7 +46,7 @@ *1.init * return ok 0, fail 1 */ -int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type) +static int32_t _amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type) { int32_t ret = 0; uint32_t buffer_size, actual_size; @@ -105,7 +106,7 @@ *2. query if the key already programmed * return: exsit 1, non 0 */ -int32_t amlkey_isexsit(const uint8_t * name) +static int32_t _amlkey_isexsit(const uint8_t * name) { int32_t ret = 0; uint32_t retval; @@ -124,7 +125,7 @@ return (int32_t)retval; } -static int32_t amlkey_get_attr(const uint8_t * name) +static uint32_t _amlkey_get_attr(const uint8_t * name) { int32_t ret = 0; uint32_t retval; @@ -140,7 +141,7 @@ retval = 0; } - return (int32_t)(retval); + return retval; } /** @@ -164,7 +165,7 @@ * 4. actual bytes of key value * return actual size. */ -ssize_t amlkey_size(const uint8_t *name) +static ssize_t _amlkey_size(const uint8_t *name) { ssize_t size = 0; int32_t ret = 0; @@ -188,7 +189,7 @@ *5. read non-secure key in bytes, return bytes readback actully. * return actual size read back. */ -ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) +static ssize_t _amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) { int32_t ret = 0; ssize_t retval = 0; @@ -215,7 +216,7 @@ * bit8, encrypt/non-encrypt; * return actual size write down. */ -ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr) +static ssize_t _amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr) { int32_t ret = 0; ssize_t retval = 0; @@ -250,7 +251,7 @@ * 7. get the hash value of programmed secure key | 32bytes length, sha256 * return success 0, fail -1 */ -int32_t amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash) +static int32_t _amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash) { int32_t ret = 0; @@ -263,7 +264,7 @@ * 7. del key by name * return success 0, fail -1 */ -int32_t amlkey_del(const uint8_t * name) +static int32_t _amlkey_del(const uint8_t * name) { int32_t ret = 0; uint32_t actual_size; @@ -284,3 +285,287 @@ return ret; } + + +#define DEFINE_MUTEX(...) +#define mutex_lock(...) +#define mutex_unlock(...) +#define PAGE_ALIGNED(a) (((a)&0xFFF)==0) +#undef pr_info +#define pr_info(fmt ...) printf("[KM]Msg:"fmt) +#undef pr_err +#define pr_err(fmt ...) printf("[KM]Error:f[%s]L%d:", __func__, __LINE__),printf(fmt) + +#define DEF_NORMAL_BLOCK_SIZE (256 * 1024) +//static DEFINE_MUTEX(normalkey_lock); +static uint32_t normal_blksz = DEF_NORMAL_BLOCK_SIZE; +static uint32_t normal_flashsize = DEF_NORMAL_BLOCK_SIZE; +static uint8_t *normal_block; + +static int _store_key_read(uint8_t * buffer, uint32_t length, uint32_t *actual_lenth) +{ + int ret; + uint32_t actual_size; + actual_size = store_rsv_size("key"); + if (actual_size <= 1024) + return -1; + + length = min_t(uint32_t, actual_size, length); + ret = store_rsv_read("key", length, buffer); + /* When the key is invalid at the first burn, it should be initialized again. */ + if (ret && ret != RSV_UNVAIL) { + printf("amlkey init rsv read key faill\n"); + return -1; + } + if (actual_lenth) + *actual_lenth = length; + return 0; +} +static int _store_key_write(uint8_t * buffer, uint32_t length, uint32_t *actual_lenth) +{ + int32_t ret; + ret = store_rsv_write("key", length, buffer); + if (ret) + return -1; + if (actual_lenth) + *actual_lenth = length; + return 0; +} + +static int32_t _amlkey_init_normal(uint8_t *seed, uint32_t len, int encrypt_type) +{ + static int inited = 0; + int ret; + + if (inited) + return 0; + inited = 1; + + if (!normal_block) + return -1; + + if (normalkey_init()) + return -1; + + mutex_lock(&normalkey_lock); + ret = _store_key_read(normal_block, + normal_blksz, + &normal_flashsize); + if (ret) { + pr_err("read storage fail\n"); + goto finish; + } + + ret = normalkey_readfromblock(normal_block, normal_flashsize); + if (ret) { + pr_err("init block key fail\n"); + goto finish; + } + +#ifdef CONFIG_STORE_COMPATIBLE + info_disprotect &= ~DISPROTECT_KEY; //protect +#endif + ret = 0; +finish: + if (ret) + normalkey_deinit(); + mutex_unlock(&normalkey_lock); + + return ret; +} + +static int32_t _amlkey_exist_normal(const uint8_t *name) +{ + struct storage_object *obj; + + mutex_lock(&normalkey_lock); + obj = normalkey_get(name); + mutex_unlock(&normalkey_lock); + + return !!obj; +} + +static uint32_t _amlkey_get_attr_normal(const uint8_t *name) +{ + uint32_t attr = 0; + struct storage_object *obj; + + mutex_lock(&normalkey_lock); + obj = normalkey_get(name); + if (obj) + attr = obj->attribute; + mutex_unlock(&normalkey_lock); + + return attr; +} + +static ssize_t _amlkey_size_normal(const uint8_t *name) +{ + unsigned int size = 0; + struct storage_object *obj; + + mutex_lock(&normalkey_lock); + obj = normalkey_get(name); + if (obj) + size = obj->datasize; + mutex_unlock(&normalkey_lock); + + return size; +} + +static ssize_t _amlkey_read_normal(const uint8_t *name, uint8_t *buffer, uint32_t len) +{ + unsigned int size = 0; + struct storage_object *obj; + + mutex_lock(&normalkey_lock); + obj = normalkey_get(name); + if (obj && len >= obj->datasize) { + size = obj->datasize; + memcpy(buffer, obj->dataptr, size); + } + mutex_unlock(&normalkey_lock); + + return size; +} + +static ssize_t _amlkey_write_normal(const uint8_t *name, uint8_t *buffer, + uint32_t len, uint32_t attr) +{ + int ret; + uint32_t wrtsz = 0; + + if (attr & OBJ_ATTR_SECURE) { + pr_err("can't write secure key\n"); + return 0; + } + + mutex_lock(&normalkey_lock); + ret = normalkey_add(name, buffer, len, attr); + if (ret) { + pr_err("write key fail\n"); + ret = 0; + goto unlock; + } + + ret = normalkey_writetoblock(normal_block, normal_flashsize); + if (ret) { + pr_err("write block fail\n"); + ret = 0; + goto unlock; + } + + ret = _store_key_write(normal_block, + normal_flashsize, + &wrtsz); + if (ret) { + pr_err("write storage fail\n"); + ret = 0; + goto unlock; + } + ret = len; +unlock: + mutex_unlock(&normalkey_lock); + return ret; +} + +static int32_t _amlkey_hash_normal(const uint8_t *name, uint8_t *hash) +{ + int ret = -1; + struct storage_object *obj; + + mutex_lock(&normalkey_lock); + obj = normalkey_get(name); + if (obj) { + ret = 0; + memcpy(hash, obj->hashptr, 32); + } + mutex_unlock(&normalkey_lock); + + return ret; +} + +int normal_key_init(const void* dt_addr) +{ + uint32_t blksz = 0; + int nodeoffset; + char *pblksz; + + if (!dt_addr || fdt_check_header(dt_addr)!= 0) { + goto blkalloc; + } + + nodeoffset = fdt_path_offset(dt_addr, "/unifykey"); + if (nodeoffset < 0) { + goto blkalloc; + } + + pblksz = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "blocksize",NULL); + if (pblksz) { + blksz = be32_to_cpup((unsigned int*)pblksz); + } + + if (blksz && PAGE_ALIGNED(blksz)) { + normal_blksz = blksz; + pr_info("block size from config: %x\n", blksz); + } + +blkalloc: + normal_block = malloc(normal_blksz); + if (!normal_block) { + pr_err("malloc block buffer fail: %x\n", normal_blksz); + return -1; + } + + return 0; +} + +enum amlkey_if_type { + IFTYPE_SECURE_STORAGE, + IFTYPE_NORMAL_STORAGE, + IFTYPE_MAX +}; + +struct amlkey_if amlkey_ifs[] = { + [IFTYPE_SECURE_STORAGE] = { + .init = _amlkey_init, + .exsit = _amlkey_isexsit, + .get_attr = _amlkey_get_attr, + .size = _amlkey_size, + .read = _amlkey_read, + .write = _amlkey_write, + .hash = _amlkey_hash_4_secure, + }, + [IFTYPE_NORMAL_STORAGE] = { + .init = _amlkey_init_normal, + .exsit = _amlkey_exist_normal, + .get_attr = _amlkey_get_attr_normal, + .size = _amlkey_size_normal, + .read = _amlkey_read_normal, + .write = _amlkey_write_normal, + .hash = _amlkey_hash_normal, + } +}; + +struct amlkey_if *amlkey_if = &amlkey_ifs[IFTYPE_SECURE_STORAGE]; +int amlkey_if_init(const void* dt_addr) +{ + static int inited = 0; + uint32_t buffer_size; + int ret = 0; + + if (inited) + return 0; + inited = 1; + + if (secure_storage_getbuffer(&buffer_size)) { + amlkey_if = &amlkey_ifs[IFTYPE_SECURE_STORAGE]; + return ret; + } + + pr_info("normal key used!\n"); + ret = normal_key_init(dt_addr); + amlkey_if = &amlkey_ifs[IFTYPE_NORMAL_STORAGE]; + + return ret; +}
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 868040b..62daade 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig
@@ -17,3 +17,17 @@ help This option is used to enable the meson c1 clock driver. + +config CLK_MESON_SC2 + bool "Support SC2 Clock" + depends on CLK + help + This option is used to enable the meson c1 clock + driver + +config CLK_MESON_C2 + bool "Support C2 Clock" + depends on CLK + help + This option is used to enable the meson c2 clock + driver.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 18dac47..7ece18b 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile
@@ -7,3 +7,5 @@ obj-$(CONFIG_CLK_MESON_G12) += clk_meson_g12.o obj-$(CONFIG_CLK_MESON_A1) += clk_meson_a1.o clk_measure.o obj-$(CONFIG_CLK_MESON_C1) += clk_meson_c1.o clk_measure.o +obj-$(CONFIG_CLK_MESON_SC2) += clk_meson_sc2.o clk_measure.o +obj-$(CONFIG_CLK_MESON_C2) += clk_meson_c2.o clk_measure.o
diff --git a/drivers/clk/meson/clk.c b/drivers/clk/meson/clk.c index cd5550b..76afe1c 100644 --- a/drivers/clk/meson/clk.c +++ b/drivers/clk/meson/clk.c
@@ -118,10 +118,11 @@ unsigned int div_val) { unsigned int val; + unsigned int div_max = (1 << div->width) - 1; val = readl(priv->addr + div->reg); - val &= ~((1 << div->width) - 1); - val |= (div_val & ((1 << div->width) - 1)) << div->shift; + val &= ~(div_max << div->shift); + val |= min_t(unsigned int, div_val, div_max) << div->shift; writel(val, priv->addr + div->reg); return 0;
diff --git a/drivers/clk/meson/clk_meson.h b/drivers/clk/meson/clk_meson.h index c7c30e6..ce39682 100644 --- a/drivers/clk/meson/clk_meson.h +++ b/drivers/clk/meson/clk_meson.h
@@ -53,6 +53,7 @@ struct meson_clk { void __iomem *addr; struct clk clkin; + u32 actual_rate; }; /* MPLL Parameters */
diff --git a/drivers/clk/meson/clk_meson_a1.c b/drivers/clk/meson/clk_meson_a1.c index 60fad9b..83b155c 100644 --- a/drivers/clk/meson/clk_meson_a1.c +++ b/drivers/clk/meson/clk_meson_a1.c
@@ -19,6 +19,7 @@ static struct meson_gate gates[] = { {CLKID_SPIFC_XTAL_GATE, A1_SPIFC_CLK_CTRL, 15}, {CLKID_SPIFC_GATE, A1_SPIFC_CLK_CTRL, 8}, + {CLKID_SPICC_A_GATE, A1_SPICC_CLK_CTRL, 8}, {CLKID_SAR_ADC_GATE, A1_SAR_ADC_CLK_CTRL, 8}, {CLKID_SD_EMMC_XTAL_GATE, A1_SD_EMMC_CLK_CTRL, 15}, {CLKID_SD_EMMC_GATE, A1_SD_EMMC_CLK_CTRL, 8}, @@ -37,12 +38,14 @@ static struct meson_mux muxes[] = { {CLKID_SPIFC_MUX, A1_SPIFC_CLK_CTRL, 9, 0x3, spifc_parents, ARRAY_SIZE(spifc_parents)}, + {CLKID_SPICC_A_MUX, A1_SPICC_CLK_CTRL, 9, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)}, {CLKID_SARADC_MUX, A1_SAR_ADC_CLK_CTRL, 9, 0x1, saradc_parents, ARRAY_SIZE(saradc_parents)}, {CLKID_SD_EMMC_MUX, A1_SD_EMMC_CLK_CTRL, 9, 0x3, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)}, }; static struct meson_div divs[] = { {CLKID_SPIFC_DIV, A1_SPIFC_CLK_CTRL, 0, 8, CLKID_SPIFC_MUX}, + {CLKID_SPICC_A_DIV, A1_SPICC_CLK_CTRL, 0, 8, CLKID_SPICC_A_MUX}, {CLKID_SARADC_DIV, A1_SAR_ADC_CLK_CTRL, 0, 8, CLKID_SARADC_MUX}, {CLKID_SD_EMMC_DIV, A1_SD_EMMC_CLK_CTRL, 0, 8, CLKID_SD_EMMC_MUX}, }; @@ -137,8 +140,7 @@ rate = SYS_CLK; break; default: - pr_err("Unknown clock, Can not get its rate\n"); - rate = 0; + rate = priv->actual_rate; break; } @@ -169,6 +171,7 @@ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; + priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1); meson_clk_set_div(priv, div, div_val); return 0;
diff --git a/drivers/clk/meson/clk_meson_c1.c b/drivers/clk/meson/clk_meson_c1.c index 043c058..2b0d31b 100644 --- a/drivers/clk/meson/clk_meson_c1.c +++ b/drivers/clk/meson/clk_meson_c1.c
@@ -19,12 +19,16 @@ static struct meson_gate gates[] = { {CLKID_SYS_SPIFC, C1_SYS_CLK_EN1, 28}, {CLKID_SPIFC_GATE, C1_SPIFC_CLK_CTRL, 8}, + {CLKID_SPIFC_XTAL_GATE, C1_SPIFC_CLK_CTRL, 15}, {CLKID_SAR_ADC_GATE, C1_SAR_ADC_CLK_CTRL, 8}, {CLKID_SPICC_A_GATE, C1_SPICC_CLK_CTRL, 8}, {CLKID_SPICC_B_GATE, C1_SPICC_CLK_CTRL, 24}, {CLKID_SD_EMMC_A_GATE, C1_SD_EMMC_CLK_CTRL, 8}, + {CLKID_SD_EMMC_A_XTAL_GATE, C1_SD_EMMC_CLK_CTRL, 15}, {CLKID_SD_EMMC_B_GATE, C1_SD_EMMC_CLK_CTRL, 24}, + {CLKID_SD_EMMC_B_XTAL_GATE, C1_SD_EMMC_CLK_CTRL, 31}, {CLKID_SD_EMMC_C_GATE, C1_SD_EMMC_CLK_CTRL1, 8}, + {CLKID_SD_EMMC_C_XTAL_GATE, C1_SD_EMMC_CLK_CTRL1, 15}, }; static unsigned int spifc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3, @@ -51,7 +55,7 @@ {CLKID_SPIFC_DIV, C1_SPIFC_CLK_CTRL, 0, 8, CLKID_SPIFC_MUX}, {CLKID_SARADC_DIV, C1_SAR_ADC_CLK_CTRL, 0, 8, CLKID_SARADC_MUX}, {CLKID_SPICC_A_DIV, C1_SPICC_CLK_CTRL, 0, 8, CLKID_SPICC_A_MUX}, - {CLKID_SPICC_B_DIV, C1_SPICC_CLK_CTRL, 16, 8, CLKID_SPICC_A_MUX}, + {CLKID_SPICC_B_DIV, C1_SPICC_CLK_CTRL, 16, 8, CLKID_SPICC_B_MUX}, {CLKID_SD_EMMC_A_DIV, C1_SD_EMMC_CLK_CTRL, 0, 8, CLKID_SD_EMMC_A_MUX}, {CLKID_SD_EMMC_B_DIV, C1_SD_EMMC_CLK_CTRL, 16, 8, CLKID_SD_EMMC_B_MUX}, {CLKID_SD_EMMC_C_DIV, C1_SD_EMMC_CLK_CTRL1, 0, 8, CLKID_SD_EMMC_C_MUX}, @@ -151,8 +155,7 @@ rate = SYS_CLK; break; default: - pr_err("Unknown clock, Can not get its rate\n"); - rate = 0; + rate = priv->actual_rate; break; } @@ -183,6 +186,7 @@ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; + priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1); meson_clk_set_div(priv, div, div_val); return 0;
diff --git a/drivers/clk/meson/clk_meson_c2.c b/drivers/clk/meson/clk_meson_c2.c new file mode 100644 index 0000000..fa67f91 --- /dev/null +++ b/drivers/clk/meson/clk_meson_c2.c
@@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> +#include <dt-bindings/clock/c2-clkc.h> +#include "clk_meson.h" + +/* change it later */ +#define SYS_CLK 166666666 + +/* clk81 gates */ +static struct meson_gate gates[] = { + {CLKID_SYS_SPIFC, C2_SYS_CLK_EN1, 28}, + {CLKID_SPIFC_GATE, C2_SPIFC_CLK_CTRL, 8}, + {CLKID_SPIFC_XTAL_GATE, C2_SPIFC_CLK_CTRL, 15}, + {CLKID_SAR_ADC_GATE, C2_SAR_ADC_CLK_CTRL, 8}, + {CLKID_SPICC_A_GATE, C2_SPICC_CLK_CTRL, 8}, + {CLKID_SPICC_B_GATE, C2_SPICC_CLK_CTRL, 24}, + {CLKID_SD_EMMC_A_GATE, C2_SD_EMMC_CLK_CTRL, 8}, + {CLKID_SD_EMMC_A_XTAL_GATE, C2_SD_EMMC_CLK_CTRL, 15}, + {CLKID_SD_EMMC_B_GATE, C2_SD_EMMC_CLK_CTRL, 24}, + {CLKID_SD_EMMC_B_XTAL_GATE, C2_SD_EMMC_CLK_CTRL, 31}, + {CLKID_SD_EMMC_C_GATE, C2_SD_EMMC_CLK_CTRL1, 8}, + {CLKID_SD_EMMC_C_XTAL_GATE, C2_SD_EMMC_CLK_CTRL1, 15}, +}; + +static unsigned int spifc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3, +CLKID_FCLK_DIV2P5, CLKID_UNREALIZED, CLKID_UNREALIZED, +CLKID_FCLK_DIV4, CLKID_FCLK_DIV5, CLKID_FCLK_DIV7}; + +static unsigned int saradc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK}; + +static unsigned int sd_emmc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3, +CLKID_FCLK_DIV2P5, CLKID_UNREALIZED, CLKID_UNREALIZED, +CLKID_FCLK_DIV4, CLKID_FCLK_DIV5, CLKID_FCLK_DIV7}; + +static struct meson_mux muxes[] = { + {CLKID_SPIFC_MUX, C2_SPIFC_CLK_CTRL, 9, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)}, + {CLKID_SARADC_MUX, C2_SAR_ADC_CLK_CTRL, 9, 0x1, saradc_parents, ARRAY_SIZE(saradc_parents)}, + {CLKID_SPICC_A_MUX, C2_SPICC_CLK_CTRL, 9, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)}, + {CLKID_SPICC_B_MUX, C2_SPICC_CLK_CTRL, 25, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)}, + {CLKID_SD_EMMC_A_MUX, C2_SD_EMMC_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)}, + {CLKID_SD_EMMC_B_MUX, C2_SD_EMMC_CLK_CTRL, 25, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)}, + {CLKID_SD_EMMC_C_MUX, C2_SD_EMMC_CLK_CTRL1, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)}, +}; + +static struct meson_div divs[] = { + {CLKID_SPIFC_DIV, C2_SPIFC_CLK_CTRL, 0, 8, CLKID_SPIFC_MUX}, + {CLKID_SARADC_DIV, C2_SAR_ADC_CLK_CTRL, 0, 8, CLKID_SARADC_MUX}, + {CLKID_SPICC_A_DIV, C2_SPICC_CLK_CTRL, 0, 8, CLKID_SPICC_A_MUX}, + {CLKID_SPICC_B_DIV, C2_SPICC_CLK_CTRL, 16, 8, CLKID_SPICC_B_MUX}, + {CLKID_SD_EMMC_A_DIV, C2_SD_EMMC_CLK_CTRL, 0, 8, CLKID_SD_EMMC_A_MUX}, + {CLKID_SD_EMMC_B_DIV, C2_SD_EMMC_CLK_CTRL, 16, 8, CLKID_SD_EMMC_B_MUX}, + {CLKID_SD_EMMC_C_DIV, C2_SD_EMMC_CLK_CTRL1, 0, 8, CLKID_SD_EMMC_C_MUX}, +}; + +static struct parm meson_fixed_pll_parm[3] = { + {C2_ANACTRL_FIXPLL_CTRL0, 0, 8}, /* pm */ + {C2_ANACTRL_FIXPLL_CTRL0, 10, 5}, /* pn */ + {C2_ANACTRL_FIXPLL_CTRL0, 16, 2}, /* pod */ +}; + +static struct parm meson_sys_pll_parm[3] = { + {C2_ANACTRL_SYSPLL_CTRL0, 0, 8}, /* pm */ + {C2_ANACTRL_SYSPLL_CTRL0, 10, 5}, /* pn */ + {C2_ANACTRL_SYSPLL_CTRL0, 24, 2}, /* pod */ +}; + +static int meson_clk_enable(struct clk *clk) +{ + return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), true); +} + +static int meson_clk_disable(struct clk *clk) +{ + return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), false); +} + +static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *pm, *pn, *pod; + unsigned long parent_rate_mhz = clk_get_rate(&priv->clkin)/1000000; + u16 n, m, od; + u32 reg; + + switch (id) { + case CLKID_FIXED_PLL: + pm = &meson_fixed_pll_parm[0]; + pn = &meson_fixed_pll_parm[1]; + pod = &meson_fixed_pll_parm[2]; + break; + case CLKID_SYS_PLL: + pm = &meson_sys_pll_parm[0]; + pn = &meson_sys_pll_parm[1]; + pod = &meson_sys_pll_parm[2]; + break; + default: + return -ENOENT; + } + + reg = readl(priv->addr + pn->reg_off); + n = PARM_GET(pn->width, pn->shift, reg); + + reg = readl(priv->addr + pm->reg_off); + m = PARM_GET(pm->width, pm->shift, reg); + + /* there is OD in C1 */ + reg = readl(priv->addr + pod->reg_off); + od = PARM_GET(pod->width, pod->shift, reg); + + return ((parent_rate_mhz * m * 2 / n) >> od) * 1000000; +} + +static ulong meson_clk_get_rate_by_id(struct clk *clk, ulong id) +{ + ulong rate; + struct meson_clk *priv = dev_get_priv(clk->dev); + + switch (id) { + case CLKID_XTAL: + rate = clk_get_rate(&priv->clkin); + break; + case CLKID_FIXED_PLL: + case CLKID_SYS_PLL: + rate = meson_pll_get_rate(clk, id); + break; + case CLKID_FCLK_DIV2: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2; + break; + case CLKID_FCLK_DIV3: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3; + break; + case CLKID_FCLK_DIV4: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4; + break; + case CLKID_FCLK_DIV5: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5; + break; + case CLKID_FCLK_DIV7: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7; + break; + case CLKID_FCLK_DIV2P5: + rate = (meson_pll_get_rate(clk, CLKID_FIXED_PLL) * 2) / 5; + break; + /* sys clk has realized in rom code*/ + case CLKID_SYS_CLK: + rate = SYS_CLK; + break; + default: + rate = priv->actual_rate; + break; + } + + return rate; +} + +static ulong meson_clk_get_rate(struct clk *clk) +{ + return meson_clk_get_rate_by_id(clk, clk->id); +} + +static ulong meson_clk_set_rate(struct clk *clk, ulong rate) +{ + ulong div_parent, mux_parent, parent_rate; + unsigned int div_val; + struct meson_clk *priv = dev_get_priv(clk->dev); + unsigned int i; + struct meson_div *div = NULL; + + for (i = 0; i < ARRAY_SIZE(divs); i++) { + if (clk->id == divs[i].index) + div = &divs[i]; + } + div_parent = div->parent_index; + mux_parent = meson_clk_get_mux_parent(clk, muxes, + ARRAY_SIZE(muxes), div_parent); + parent_rate = meson_clk_get_rate_by_id(clk, mux_parent); + + div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; + + priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1); + meson_clk_set_div(priv, div, div_val); + + return 0; +} + +static int meson_clk_set_parent(struct clk* clk, struct clk* parent_clk) +{ + return meson_mux_set_parent_by_id(clk, muxes, ARRAY_SIZE(muxes), parent_clk); +} + +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, + .get_rate = meson_clk_get_rate, + .set_rate = meson_clk_set_rate, + .set_parent = meson_clk_set_parent, +}; + +static int meson_clk_probe(struct udevice *dev) +{ + struct meson_clk *priv = dev_get_priv(dev); + + clk_get_by_name(dev, "xtal", &priv->clkin); + priv->addr = dev_read_addr_ptr(dev); + + debug("meson-clk: probed at addr %p\n", priv->addr); + + return 0; +} + +static const struct udevice_id meson_clk_ids[] = { + { .compatible = "amlogic,c1-clkc" }, + { } +}; + +U_BOOT_DRIVER(meson_clk) = { + .name = "meson-clk-c2", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto_alloc_size = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +};
diff --git a/drivers/clk/meson/clk_meson_g12.c b/drivers/clk/meson/clk_meson_g12.c index 1201695..b1123f9 100644 --- a/drivers/clk/meson/clk_meson_g12.c +++ b/drivers/clk/meson/clk_meson_g12.c
@@ -72,7 +72,7 @@ static struct meson_div divs[] = { {CLKID_SPICC0_DIV, HHI_SPICC_CLK_CNTL, 0, 6, CLKID_SPICC0_MUX}, - {CLKID_SPICC1_DIV, HHI_SPICC_CLK_CNTL, 16, 7, CLKID_SPICC1_MUX}, + {CLKID_SPICC1_DIV, HHI_SPICC_CLK_CNTL, 16, 6, CLKID_SPICC1_MUX}, {CLKID_SARADC_DIV, AO_SAR_CLK, 0, 8, CLKID_SARADC_MUX}, {CLKID_SD_EMMC_A_P0_DIV, HHI_SD_EMMC_CLK_CNTL, 0, 7, CLKID_SD_EMMC_A_P0_MUX}, {CLKID_SD_EMMC_B_P0_DIV, HHI_SD_EMMC_CLK_CNTL, 16, 7, CLKID_SD_EMMC_B_P0_MUX}, @@ -170,8 +170,7 @@ rate = CLK81_RATE; break; default: - pr_err("Unknown clock, Can not get its rate\n"); - rate = 0; + rate = priv->actual_rate; break; } @@ -202,6 +201,7 @@ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; + priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1); meson_clk_set_div(priv, div, div_val); return 0;
diff --git a/drivers/clk/meson/clk_meson_sc2.c b/drivers/clk/meson/clk_meson_sc2.c new file mode 100644 index 0000000..93b8529 --- /dev/null +++ b/drivers/clk/meson/clk_meson_sc2.c
@@ -0,0 +1,225 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> +#include <dt-bindings/clock/sc2-clkc.h> +#include "clk_meson.h" + +/* change it later */ +#define SYS_CLK 166666666 + +/* clk81 gates, sys_clk */ +static struct meson_gate gates[] = { +// {CLKID_SYS_SPIFC, SC2_CLKCTRL_SYS_CLK_EN0_REG0, 29}, + {CLKID_SPICC_A_GATE, SC2_CLKCTRL_SPICC_CLK_CTRL, 6}, + {CLKID_SPICC_B_GATE, SC2_CLKCTRL_SPICC_CLK_CTRL, 22}, + {CLKID_SAR_ADC_GATE, SC2_CLKCTRL_SAR_CLK_CTRL0, 8}, + {CLKID_SD_EMMC_A_GATE, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 7}, + {CLKID_SD_EMMC_B_GATE, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 23}, + {CLKID_SD_EMMC_C_GATE, SC2_CLKCTRL_NAND_CLK_CTRL, 7}, +}; + +static unsigned int spicc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK, +CLKID_FCLK_DIV4, CLKID_FCLK_DIV3, CLKID_FCLK_DIV2, +CLKID_FCLK_DIV5, CLKID_FCLK_DIV7, CLKID_UNREALIZED}; + +static unsigned int saradc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK}; + +static unsigned int sd_emmc_parents[] = {CLKID_XTAL, CLKID_FCLK_DIV2, +CLKID_FCLK_DIV3, CLKID_UNREALIZED, CLKID_UNREALIZED, +CLKID_UNREALIZED, CLKID_UNREALIZED, CLKID_UNREALIZED}; + +static struct meson_mux muxes[] = { + {CLKID_SPICC_A_MUX, SC2_CLKCTRL_SPICC_CLK_CTRL, 7, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)}, + {CLKID_SPICC_B_MUX, SC2_CLKCTRL_SPICC_CLK_CTRL, 23, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)}, + {CLKID_SARADC_MUX, SC2_CLKCTRL_SAR_CLK_CTRL0, 9, 0x3, saradc_parents, ARRAY_SIZE(saradc_parents)}, + {CLKID_SD_EMMC_A_MUX, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)}, + {CLKID_SD_EMMC_B_MUX, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 25, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)}, + {CLKID_SD_EMMC_C_MUX, SC2_CLKCTRL_NAND_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)}, +}; + +static struct meson_div divs[] = { + {CLKID_SPICC_A_DIV, SC2_CLKCTRL_SPICC_CLK_CTRL, 0, 6, CLKID_SPICC_A_MUX}, + {CLKID_SPICC_B_DIV, SC2_CLKCTRL_SPICC_CLK_CTRL, 16, 6, CLKID_SPICC_B_MUX}, + {CLKID_SARADC_DIV, SC2_CLKCTRL_SAR_CLK_CTRL0, 0, 8, CLKID_SARADC_MUX}, + {CLKID_SD_EMMC_A_DIV, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 0, 7, CLKID_SD_EMMC_A_MUX}, + {CLKID_SD_EMMC_B_DIV, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 16, 7, CLKID_SD_EMMC_B_MUX}, + {CLKID_SD_EMMC_C_DIV, SC2_CLKCTRL_NAND_CLK_CTRL, 0, 7, CLKID_SD_EMMC_C_MUX}, +}; + +static struct parm meson_fixed_pll_parm[3] = { + {SC2_ANACTRL_FIXPLL_CTRL0, 0, 8}, /* pm */ + {SC2_ANACTRL_FIXPLL_CTRL0, 10, 5}, /* pn */ + {SC2_ANACTRL_FIXPLL_CTRL0, 16, 2}, /* pod */ +}; + +static struct parm meson_sys_pll_parm[3] = { + {SC2_ANACTRL_SYSPLL_CTRL0, 0, 8}, /* pm */ + {SC2_ANACTRL_SYSPLL_CTRL0, 10, 5}, /* pn */ + {SC2_ANACTRL_SYSPLL_CTRL0, 16, 3}, /* pod */ +}; + +static int meson_clk_enable(struct clk *clk) +{ + return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), true); +} + +static int meson_clk_disable(struct clk *clk) +{ + return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), false); +} + +static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) +{ + struct meson_clk *priv = dev_get_priv(clk->dev); + struct parm *pm, *pn, *pod; + unsigned long parent_rate_mhz = clk_get_rate(&priv->clkin)/1000000; + u16 n, m, od; + u32 reg; + + switch (id) { + case CLKID_FIXED_PLL: + pm = &meson_fixed_pll_parm[0]; + pn = &meson_fixed_pll_parm[1]; + pod = &meson_fixed_pll_parm[2]; + break; + case CLKID_SYS_PLL: + pm = &meson_sys_pll_parm[0]; + pn = &meson_sys_pll_parm[1]; + pod = &meson_sys_pll_parm[2]; + break; + default: + return -ENOENT; + } + + reg = readl(priv->addr + pn->reg_off); + n = PARM_GET(pn->width, pn->shift, reg); + + reg = readl(priv->addr + pm->reg_off); + m = PARM_GET(pm->width, pm->shift, reg); + + /* there is OD in C1 */ + reg = readl(priv->addr + pod->reg_off); + od = PARM_GET(pod->width, pod->shift, reg); + + return ((parent_rate_mhz * m / n) >> od) * 1000000; +} + +static ulong meson_clk_get_rate_by_id(struct clk *clk, ulong id) +{ + ulong rate; + struct meson_clk *priv = dev_get_priv(clk->dev); + + switch (id) { + case CLKID_XTAL: + rate = clk_get_rate(&priv->clkin); + break; + case CLKID_FIXED_PLL: + case CLKID_SYS_PLL: + rate = meson_pll_get_rate(clk, id); + break; + case CLKID_FCLK_DIV2: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2; + break; + case CLKID_FCLK_DIV3: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3; + break; + case CLKID_FCLK_DIV4: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4; + break; + case CLKID_FCLK_DIV5: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5; + break; + case CLKID_FCLK_DIV7: + rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7; + break; + case CLKID_FCLK_DIV2P5: + rate = (meson_pll_get_rate(clk, CLKID_FIXED_PLL) * 2) / 5; + break; + /* sys clk has realized in rom code*/ + case CLKID_SYS_CLK: + rate = SYS_CLK; + break; + default: + rate = priv->actual_rate; + break; + } + + return rate; +} + +static ulong meson_clk_get_rate(struct clk *clk) +{ + return meson_clk_get_rate_by_id(clk, clk->id); +} + +static ulong meson_clk_set_rate(struct clk *clk, ulong rate) +{ + ulong div_parent, mux_parent, parent_rate; + unsigned int div_val; + struct meson_clk *priv = dev_get_priv(clk->dev); + unsigned int i; + struct meson_div *div = NULL; + + for (i = 0; i < ARRAY_SIZE(divs); i++) { + if (clk->id == divs[i].index) + div = &divs[i]; + } + div_parent = div->parent_index; + mux_parent = meson_clk_get_mux_parent(clk, muxes, + ARRAY_SIZE(muxes), div_parent); + parent_rate = meson_clk_get_rate_by_id(clk, mux_parent); + + div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; + + priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1); + meson_clk_set_div(priv, div, div_val); + + return 0; +} + +static int meson_clk_set_parent(struct clk* clk, struct clk* parent_clk) +{ + return meson_mux_set_parent_by_id(clk, muxes, ARRAY_SIZE(muxes), parent_clk); +} + +static struct clk_ops meson_clk_ops = { + .disable = meson_clk_disable, + .enable = meson_clk_enable, + .get_rate = meson_clk_get_rate, + .set_rate = meson_clk_set_rate, + .set_parent = meson_clk_set_parent, +}; + +static int meson_clk_probe(struct udevice *dev) +{ + struct meson_clk *priv = dev_get_priv(dev); + + clk_get_by_name(dev, "xtal", &priv->clkin); + priv->addr = dev_read_addr_ptr(dev); + + debug("meson-clk: probed at addr %p\n", priv->addr); + + return 0; +} + +static const struct udevice_id meson_clk_ids[] = { + { .compatible = "amlogic,sc2-clkc" }, + { } +}; + +U_BOOT_DRIVER(meson_clk) = { + .name = "meson-clk-sc2", + .id = UCLASS_CLK, + .of_match = meson_clk_ids, + .priv_auto_alloc_size = sizeof(struct meson_clk), + .ops = &meson_clk_ops, + .probe = meson_clk_probe, +};
diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index 65eacfb..ad55a7c 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c
@@ -10,6 +10,7 @@ #include <fb_nand.h> #include <part.h> #include <stdlib.h> +#include <emmc_partitions.h> /** * image_size - final fastboot image size @@ -26,6 +27,8 @@ */ static u32 fastboot_bytes_expected; +int busy_flag; + static void okay(char *, char *); static void getvar(char *, char *); static void download(char *, char *); @@ -33,10 +36,21 @@ static void flash(char *, char *); static void erase(char *, char *); #endif +#ifndef CONFIG_NO_FASTBOOT_FLASHING +static void flashing(char *, char *); +#endif //CONFIG_NO_FASTBOOT_FLASHING static void reboot_bootloader(char *, char *); +static void reboot_fastboot(char *, char *); #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) static void oem_format(char *, char *); #endif +static void oem_cmd(char *, char *); +static void set_active_cmd(char *, char *); +static void snapshot_update_cmd(char *, char *); + +#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK +extern int is_partition_logical(char* parition_name); +#endif #ifdef CONFIG_G_AB_SYSTEM static void set_active(char *, char *); @@ -54,6 +68,12 @@ .command = "download", .dispatch = download }, +#ifndef CONFIG_NO_FASTBOOT_FLASHING + [FASTBOOT_COMMAND_FLASHING] = { + .command = "flashing", + .dispatch = flashing + }, +#endif //CONFIG_NO_FASTBOOT_FLASHING #if CONFIG_IS_ENABLED(FASTBOOT_FLASH) [FASTBOOT_COMMAND_FLASH] = { .command = "flash", @@ -72,14 +92,18 @@ .command = "continue", .dispatch = okay }, - [FASTBOOT_COMMAND_REBOOT] = { - .command = "reboot", - .dispatch = okay - }, [FASTBOOT_COMMAND_REBOOT_BOOTLOADER] = { .command = "reboot-bootloader", .dispatch = reboot_bootloader }, + [FASTBOOT_COMMAND_REBOOT_FASTBOOT] = { + .command = "reboot-fastboot", + .dispatch = reboot_fastboot + }, + [FASTBOOT_COMMAND_REBOOT] = { + .command = "reboot", + .dispatch = okay + }, [FASTBOOT_COMMAND_SET_ACTIVE] = { .command = "set_active", #ifdef CONFIG_G_AB_SYSTEM @@ -88,14 +112,29 @@ .dispatch = okay #endif }, + [FASTBOOT_COMMAND_SNAOSHOT_UPDATE] = { + .command = "snapshot-update", + .dispatch = snapshot_update_cmd + }, #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) [FASTBOOT_COMMAND_OEM_FORMAT] = { .command = "oem format", .dispatch = oem_format, }, #endif + [FASTBOOT_COMMAND_OEM] = { + .command = "oem", + .dispatch = oem_cmd, + }, }; +static int strcmp_l1(const char *s1, const char *s2) +{ + if (!s1 || !s2) + return -1; + return strncmp(s1, s2, strlen(s1)); +} + /** * fastboot_handle_command - Handle fastboot command * @@ -113,10 +152,15 @@ strsep(&cmd_parameter, ":"); for (i = 0; i < FASTBOOT_COMMAND_COUNT; i++) { - if (!strcmp(commands[i].command, cmd_string)) { + if (!strcmp_l1(commands[i].command, cmd_string)) { if (commands[i].dispatch) { - commands[i].dispatch(cmd_parameter, + if (strcmp(cmd_parameter, NULL)) { + commands[i].dispatch(cmd_parameter, response); + } else { + commands[i].dispatch(cmd_string, + response); + } return i; } else { break; @@ -144,6 +188,66 @@ fastboot_okay(NULL, response); } +void dump_lock_info(LockData_t* info) +{ + printf("info->version_major = %d\n", info->version_major); + printf("info->version_minor = %d\n", info->version_minor); + printf("info->unlock_ability = %d\n", info->unlock_ability); + printf("info->lock_state = %d\n", info->lock_state); + printf("info->lock_critical_state = %d\n", info->lock_critical_state); + printf("info->lock_bootloader = %d\n", info->lock_bootloader); +} + +static const char* getvar_list[] = { + "version-baseband", "version-bootloader", "version", "hw-revision", "max-download-size", + "serialno", "product", "off-mode-charge", "variant", "battery-soc-ok", + "battery-voltage", "partition-type:boot", "partition-size:boot", + "partition-type:system", "partition-size:system", "partition-type:vendor", "partition-size:vendor", + "partition-type:odm", "partition-size:odm", "partition-type:data", "partition-size:data", + "erase-block-size", "logical-block-size", "secure", "unlocked", +}; + +static const char* getvar_list_dynamic[] = { + "hw-revision", "battery-voltage", "is-userspace", "is-logical:data", + "is-logical:metadata", "is-logical:misc", "is-logical:super", "is-logical:boot", + "is-logical:system", "is-logical:vendor", "is-logical:product", "is-logical:odm", + "slot-count", "max-download-size", "serialno", "product", "unlocked", + "secure", "super-partition-name", "version-baseband", "version-bootloader", + "partition-size:boot", "partition-size:metadata", "partition-size:misc", + "partition-size:super", "partition-size:data", "version", +}; + +static const char* getvar_list_dynamic_ab[] = { + "hw-revision", "battery-voltage", "is-userspace", "is-logical:data", + "is-logical:misc", "is-logical:super", + "is-logical:boot_a", "is-logical:boot_b", "is-logical:system_a", "is-logical:system_b", + "is-logical:vendor_a", "is-logical:vendor_b", "is-logical:product_a", "is-logical:product_b", + "is-logical:odm_a", "is-logical:odm_b", + "slot-count", "max-download-size", "serialno", "product", "unlocked", "has-slot:data", + "has-slot:metadata", "has-slot:misc", "has-slot:super", "has-slot:boot", + "has-slot:system", "has-slot:vendor", "has-slot:product", "has-slot:odm", "current-slot", + "secure", "super-partition-name", "version-baseband", "version-bootloader", + "partition-size:super", + "partition-size:boot_a", "partition-size:boot_b", "partition-size:misc", + "partition-size:data", "version", +}; + + +static const char* getvar_list_ab[] = { + "version-baseband", "version-bootloader", "version", "hw-revision", "max-download-size", + "serialno", "product", "off-mode-charge", "variant", "battery-soc-ok", + "battery-voltage", "partition-type:boot_a", "partition-size:boot_a", + "partition-type:system_a", "partition-size:system_a", "partition-type:vendor_a", "partition-size:vendor_a", + "partition-type:odm_a", "partition-size:odm_a", "partition-type:data", "partition-size:data", + "erase-block-size", "logical-block-size", "secure", "unlocked", + "slot-count", "slot-suffixes","current-slot", "has-slot:bootloader", "has-slot:boot", + "has-slot:system", "has-slot:vendor", "has-slot:odm", "has-slot:vbmeta", + "has-slot:metadata", "has-slot:product", "has-slot:dtbo", + "slot-successful:a", "slot-unbootable:a", "slot-retry-count:a", + "slot-successful:b", "slot-unbootable:b", "slot-retry-count:b", +}; + + /** * getvar() - Read a config/version variable * @@ -152,7 +256,40 @@ */ static void getvar(char *cmd_parameter, char *response) { - fastboot_getvar(cmd_parameter, response); + run_command("get_valid_slot", 0); + if (!strncmp(cmd_parameter, "all", 3)) { + static int cmdIndex = 0; + int getvar_num = 0; + char* cmd=cmd_parameter; + + busy_flag = 1; + + if (dynamic_partition && has_boot_slot == 1 && strlen(getvar_list_dynamic_ab[cmdIndex]) < 64) { + strncpy(cmd, getvar_list_dynamic_ab[cmdIndex], 64); + getvar_num = (sizeof(getvar_list_dynamic_ab) / sizeof(getvar_list_dynamic_ab[0])); + } else if (has_boot_slot == 1 && strlen(getvar_list_ab[cmdIndex]) < 64) { + strncpy(cmd, getvar_list_ab[cmdIndex], 64); + getvar_num = (sizeof(getvar_list_ab) / sizeof(getvar_list_ab[0])); + } else if (dynamic_partition && strlen(getvar_list_dynamic[cmdIndex]) < 64) { + strncpy(cmd, getvar_list_dynamic[cmdIndex], 64);//only support no-arg cmd + getvar_num = (sizeof(getvar_list_dynamic) / sizeof(getvar_list_dynamic[0])); + } else if (strlen(getvar_list[cmdIndex]) < 64) { + strncpy(cmd, getvar_list[cmdIndex], 64);//only support no-arg cmd + getvar_num = (sizeof(getvar_list) / sizeof(getvar_list[0])); + } + //printf("getvar_num: %d\n", getvar_num); + //printf("all cmd:%s\n", cmd); + if ( ++cmdIndex >= getvar_num) { + cmdIndex = 0; + busy_flag = 0; + fastboot_okay(NULL, response); + } else { + fastboot_getvar(cmd, response); + } + + }else { + fastboot_getvar(cmd_parameter, response); + } } /** @@ -274,12 +411,37 @@ */ static void flash(char *cmd_parameter, char *response) { + char name[32]; + + if (strcmp(cmd_parameter, "userdata") == 0 && !vendor_boot_partition) + strncpy(name, "data", 4); + else if (strcmp(cmd_parameter, "dts") == 0) + strncpy(name, "dtb", 3); + else + strncpy(name, cmd_parameter, 32); + + if (check_lock()) { + printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n"); + fastboot_fail("locked device", response); + return; + } + +#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK + if (dynamic_partition) { + if (is_partition_logical(name) == 0) { + printf("%s is logic partition, can not write here.......\n", name); + fastboot_fail("logic partition", response); + return; + } + } +#endif + #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) - fastboot_mmc_flash_write(cmd_parameter, fastboot_buf_addr, image_size, + fastboot_mmc_flash_write(name, fastboot_buf_addr, image_size, response); #endif #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND) - fastboot_nand_flash_write(cmd_parameter, fastboot_buf_addr, image_size, + fastboot_nand_flash_write(name, fastboot_buf_addr, image_size, response); #endif } @@ -295,15 +457,278 @@ */ static void erase(char *cmd_parameter, char *response) { + char name[32]; + + if (check_lock()) { + printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n"); + fastboot_fail("locked device", response); + return; + } + + struct misc_virtual_ab_message message; + get_mergestatus(&message); + + if (strcmp(cmd_parameter, "userdata") == 0 && !vendor_boot_partition) { + strncpy(name, "data", 4); + if (message.merge_status == SNAPSHOTTED || message.merge_status == MERGING) { + fastboot_fail("in merge state, cannot erase data", response); + return; + } + } else if (strcmp(cmd_parameter, "dts") == 0) + strncpy(name, "dtb", 3); + else + strncpy(name, cmd_parameter, 32); + +#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK + if (dynamic_partition) { + if (is_partition_logical(name) == 0) { + printf("%s is logic partition, can not erase here.......\n", name); + fastboot_fail("logic partition", response); + return; + } + } +#endif + #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) - fastboot_mmc_erase(cmd_parameter, response); + fastboot_mmc_erase(name, response); #endif #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND) - fastboot_nand_erase(cmd_parameter, response); + fastboot_nand_erase(name, response); #endif } #endif +static void set_active_cmd(char *cmd_parameter, char *response) +{ + char *cmd; + int ret = 0; + char str[128]; + + printf("cmd cb_set_active is %s\n", cmd_parameter); + cmd = cmd_parameter; + + if (check_lock()) { + printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n"); + fastboot_fail("locked device", response); + return; + } + + struct misc_virtual_ab_message message; + get_mergestatus(&message); + if (message.merge_status == MERGING) { + fastboot_fail("in merge state, cannot set active", response); + return; + } + + sprintf(str, "set_active_slot %s", cmd); + printf("command: %s\n", str); + ret = run_command(str, 0); + printf("ret = %d\n", ret); + if (ret == 0) + fastboot_okay(NULL, response); + else + fastboot_fail("set slot error", response); +} + +static void snapshot_update_cmd(char *cmd_parameter, char *response) +{ + char *cmd; + int ret = 0; + char str[128]; + + printf("cmd snapshot_update_cmd is %s\n", cmd_parameter); + cmd = cmd_parameter; + + if (check_lock()) { + printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n"); + fastboot_fail("locked device", response); + return; + } + + if (!strcmp_l1("cancel", cmd)) { + struct misc_virtual_ab_message message; + set_mergestatus_cancel(&message); + } + fastboot_okay(NULL, response); +} + +#ifndef CONFIG_NO_FASTBOOT_FLASHING +/** + * flashing() - lock/unlock. + * + * @cmd_parameter: Pointer to partition name + * @response: Pointer to fastboot response buffer + * + * Writes the previously downloaded image to the partition indicated by + * cmd_parameter. Writes to response. + */ +static void flashing(char *cmd_parameter, char *response) +{ + char *cmd; + char* lock_s; + LockData_t* info; + char lock_d[LOCK_DATA_SIZE]; + + lock_s = env_get("lock"); + if (!lock_s) { + printf("lock state is NULL \n"); + strncpy(lock_d, "10101000", 8); + lock_s = "10101000"; + env_set("lock", "10101000"); + run_command("defenv_reserv; saveenv;", 0); + } else { + printf("lock state: %s\n", lock_s); + if (strlen(lock_s) > 15) + strncpy(lock_d, lock_s, 15); + else + strncpy(lock_d, lock_s, strlen(lock_s)); + } + + info = malloc(sizeof(struct LockData)); + if (!info) { + printf("malloc error\n"); + fastboot_fail("malloc error", response); + return; + } + memset(info,0,LOCK_DATA_SIZE); + info->version_major = (int)(lock_d[0] - '0'); + info->version_minor = (int)(lock_d[1] - '0'); + info->unlock_ability = (int)(lock_d[2] - '0'); + info->lock_state = (int)(lock_d[4] - '0'); + info->lock_critical_state = (int)(lock_d[5] - '0'); + info->lock_bootloader = (int)(lock_d[6] - '0'); + + printf("cb_flashing cmd_parameter: %s\n", cmd_parameter); + cmd = cmd_parameter; + strsep(&cmd, " "); + printf("cb_flashing: %s\n", cmd); + if (!cmd) { + printf("missing variable\n"); + fastboot_fail("missing var", response); + free(info); + return; + } + + if (!strcmp_l1("unlock_critical", cmd)) { + info->lock_critical_state = 0; + fastboot_okay(NULL, response); + } else if (!strcmp_l1("lock_critical", cmd)) { + info->lock_critical_state = 1; + fastboot_okay(NULL, response); + } else if (!strcmp_l1("get_unlock_ability", cmd)) { + char str[32]; + static bool is_unlock_ability_sent = false; + if (is_unlock_ability_sent) { + is_unlock_ability_sent = false; + fastboot_okay(NULL, response); + busy_flag = 0; + } else { + sprintf(str, "get_unlock_ability: %d", + info->unlock_ability); + fastboot_response("INFO", response, "%s", str); + is_unlock_ability_sent = true; + busy_flag = 1; + } + free(info); + return; + } else if (!strcmp_l1("get_unlock_bootloader_nonce", cmd)) { + char str_num[8]; + sprintf(str_num, "%d", info->lock_critical_state); + fastboot_response("OKAY", response, "%s", str_num); + } else if (!strcmp_l1("lock_bootloader", cmd)) { + info->lock_bootloader = 1; + } else if (!strcmp_l1("unlock", cmd)) { + if (info->unlock_ability == 1 ) { + if (info->lock_state == 1 ) { + char *avb_s; + avb_s = env_get("avb2"); + if (avb_s == NULL) { + run_command("get_avb_mode;", 0); + avb_s = env_get("avb2"); + } + printf("avb2: %s\n", avb_s); + if (strcmp(avb_s, "1") == 0) { +#ifdef CONFIG_AML_ANTIROLLBACK + if (avb_unlock()) { + printf("unlocking device. Erasing userdata partition!\n"); + if (vendor_boot_partition) + run_command("store erase userdata 0 0", 0); + else + run_command("store erase data 0 0", 0); + printf("unlocking device. Erasing metadata partition!\n"); + run_command("store erase metadata 0 0", 0); + } else { + printf("unlock failed!\n"); + } +#else + printf("unlocking device. Erasing userdata partition!\n"); + if (vendor_boot_partition) + run_command("store erase userdata 0 0", 0); + else + run_command("store erase data 0 0", 0); + printf("unlocking device. Erasing metadata partition!\n"); + run_command("store erase metadata 0 0", 0); +#endif + } + } + info->lock_state = 0; + info->lock_critical_state = 0; + env_set("lock_state", "green"); + fastboot_okay(NULL, response); + } else { + printf("unlock_ability is 0, can not unlock, please set it in android setting\n"); + fastboot_response("FAIL", response, "%s", "unlock_ability is 0, can not unlock"); + } + } else if (!strcmp_l1("lock", cmd)) { + if (info->lock_state == 0 ) { + char *avb_s; + avb_s = env_get("avb2"); + if (avb_s == NULL) { + run_command("get_avb_mode;", 0); + avb_s = env_get("avb2"); + } + printf("avb2: %s\n", avb_s); + if (strcmp(avb_s, "1") == 0) { +#ifdef CONFIG_AML_ANTIROLLBACK + if (avb_lock()) { + printf("lock failed!\n"); + } else { + printf("locking device. Erasing userdata partition!\n"); + if (vendor_boot_partition) + run_command("store erase userdata 0 0", 0); + else + run_command("store erase data 0 0", 0); + printf("unlocking device. Erasing metadata partition!\n"); + run_command("store erase metadata 0 0", 0); + } +#else + printf("locking device. Erasing userdata partition!\n"); + if (vendor_boot_partition) + run_command("store erase userdata 0 0", 0); + else + run_command("store erase data 0 0", 0); + printf("unlocking device. Erasing metadata partition!\n"); + run_command("store erase metadata 0 0", 0); + +#endif + } + } + info->lock_state = 1; + env_set("lock_state", "orange"); + fastboot_okay(NULL, response); + } else { + printf("unknown variable: %s\n", cmd); + fastboot_response("FAIL", response, "%s", "Variable not implemented"); + } + + sprintf(lock_d, "%d%d%d0%d%d%d0", info->version_major, info->version_minor, info->unlock_ability, info->lock_state, info->lock_critical_state, info->lock_bootloader); + printf("lock_d state: %s\n", lock_d); + env_set("lock", lock_d); + run_command("saveenv;", 0); + free(info); + return; +} +#endif //CONFIG_NO_FASTBOOT_FLASHING /** * reboot_bootloader() - Sets reboot bootloader flag. * @@ -312,12 +737,46 @@ */ static void reboot_bootloader(char *cmd_parameter, char *response) { - if (fastboot_set_reboot_flag()) - fastboot_fail("Cannot set reboot flag", response); - else - fastboot_okay(NULL, response); + fastboot_okay(NULL, response); } +/** + * reboot_fastboot() - Sets reboot fastboot flag. + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void reboot_fastboot(char *cmd_parameter, char *response) +{ + fastboot_okay(NULL, response); +} + +static void oem_cmd(char *cmd_parameter, char *response) +{ + char *cmd; + int i = 0, len = 0, j = 0; + char cmd_str[FASTBOOT_RESPONSE_LEN]; + printf("oem cmd_parameter: %s\n", cmd_parameter); + cmd = cmd_parameter; + strsep(&cmd, " "); + printf("To run cmd[%s]\n", cmd); + + len = strlen(cmd); + for (i = 0; i < len; i++) { + if (cmd[i] != '\'') { + cmd_str[j++] = cmd[i]; + } + } + cmd_str[j] = '\0'; + printf("cmd_str2: %s\n", cmd_str); + + run_command(cmd_str, 0); + + fastboot_okay(NULL, response); + return; +} + + #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) /** * oem_format() - Execute the OEM format command
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 8d36341..fef9437 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c
@@ -13,6 +13,10 @@ #include <common.h> #include <fastboot.h> #include <net/fastboot.h> +#include <emmc_partitions.h> +#include <amlogic/storage.h> + +#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000 /** * fastboot_buf_addr - base address of the fastboot download buffer @@ -63,6 +67,17 @@ } /** + * fastboot_busy() - Write a INFO response of the form "INFO$reason". + * + * @reason: Pointer to returned reason string + * @response: Pointer to fastboot response buffer + */ +void fastboot_busy(const char *reason, char *response) +{ + fastboot_response("INFO", response, "%s", reason); +} + +/** * fastboot_okay() - Write an OKAY response of the form "OKAY$reason". * * @reason: Pointer to returned reason string, or NULL to send a bare "OKAY" @@ -77,6 +92,107 @@ } /** + *check lock state + *return 1 if locked + *return 0 if unlocked + */ +int check_lock(void) +{ + char *lock_s; + LockData_t* info; + + lock_s = env_get("lock"); + if (!lock_s) { + printf("lock state is NULL \n"); + lock_s = "10101000"; + env_set("lock", "10101000"); + run_command("defenv_reserv; saveenv;", 0); + } + printf("lock state: %s\n", lock_s); + + info = malloc(sizeof(struct LockData)); + if (info) { + memset(info,0,LOCK_DATA_SIZE); + info->version_major = (int)(lock_s[0] - '0'); + info->version_minor = (int)(lock_s[1] - '0'); + info->unlock_ability = (int)(lock_s[2] - '0'); + info->lock_state = (int)(lock_s[4] - '0'); + info->lock_critical_state = (int)(lock_s[5] - '0'); + info->lock_bootloader = (int)(lock_s[6] - '0'); + + dump_lock_info(info); + } else + return 0; + + if ((info->lock_state == 1 ) || ( info->lock_critical_state == 1 )) { + free (info); + return 1; + } + else { + free (info); + return 0; + } +} + +/** + *get merge status +*/ +int get_mergestatus(struct misc_virtual_ab_message *message) +{ + char *partition = "misc"; + char vab_buf[1024] = {0}; + + if (store_read((unsigned char *)partition, + SYSTEM_SPACE_OFFSET_IN_MISC, 1024, (unsigned char *)vab_buf) < 0) { + printf("failed to store read %s.\n", partition); + return -1; + } + + run_command("get_valid_slot", 0); + int current_slot = 0; + char *slot; + slot = getenv("slot-suffixes"); + if (strcmp(slot, "0") == 0) { + current_slot = 0; + } else if (strcmp(slot, "1") == 0) { + current_slot = 1; + } + + memcpy(message, vab_buf, sizeof(struct misc_virtual_ab_message)); + printf("message.merge_status: %d\n", message->merge_status); + printf("message.source_slot: %d\n", message->source_slot); + if (message->merge_status == SNAPSHOTTED && current_slot == message->source_slot) { + message->merge_status = NONE; + printf("set message.merge_status NONE\n"); + } + return 0; +} + +/** + *set merge status +*/ +int set_mergestatus_cancel(struct misc_virtual_ab_message *message) +{ + char *partition = "misc"; + char vab_buf[1024] = {0}; + + if (store_read((unsigned char *)partition, + SYSTEM_SPACE_OFFSET_IN_MISC, 1024, (unsigned char *)vab_buf) < 0) { + printf("failed to store read %s.\n", partition); + return -1; + } + + memcpy(message, vab_buf, sizeof(struct misc_virtual_ab_message)); + printf("message.merge_status: %d\n", message->merge_status); + if (message->merge_status == SNAPSHOTTED || message->merge_status == MERGING) { + message->merge_status = CANCELLED; + printf("set message.merge_status CANCELLED\n"); + } + store_write((unsigned char *)partition, SYSTEM_SPACE_OFFSET_IN_MISC, 1024, (unsigned char *)vab_buf); + return 0; +} + +/** * fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader * * Set flag which indicates that we should reboot into the bootloader @@ -165,5 +281,11 @@ fastboot_buf_addr = buf_addr ? buf_addr : (void *)CONFIG_FASTBOOT_BUF_ADDR; fastboot_buf_size = buf_size ? buf_size : CONFIG_FASTBOOT_BUF_SIZE; + +#if defined CONFIG_FASTBOOT_MAX_DOWN_SIZE + if (fastboot_buf_size > CONFIG_FASTBOOT_MAX_DOWN_SIZE) + fastboot_buf_size = CONFIG_FASTBOOT_MAX_DOWN_SIZE; +#endif + fastboot_set_progress_callback(NULL); }
diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 46cb26e..944221e 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c
@@ -10,18 +10,32 @@ #include <fb_nand.h> #include <fs.h> #include <version.h> +#include <partition_table.h> static void getvar_version(char *var_parameter, char *response); static void getvar_bootloader_version(char *var_parameter, char *response); static void getvar_downloadsize(char *var_parameter, char *response); static void getvar_serialno(char *var_parameter, char *response); static void getvar_version_baseband(char *var_parameter, char *response); +static void getvar_hw_revision(char *var_parameter, char *response); +static void getvar_off_mode_charge(char *var_parameter, char *response); +static void getvar_variant(char *var_parameter, char *response); +static void getvar_battery_soc_ok(char *var_parameter, char *response); +static void getvar_battery_voltage(char *var_parameter, char *response); +static void getvar_block_size(char *var_parameter, char *response); +static void getvar_secure(char *var_parameter, char *response); +static void getvar_unlocked(char *var_parameter, char *response); +static void getvar_is_userspace(char *var_parameter, char *response); +static void getvar_is_logical(char *var_parameter, char *response); +static void getvar_slot_count(char *var_parameter, char *response); +static void getvar_super_partition_name(char *var_parameter, char *response); +static void getvar_snapshot_update_status(char *var_parameter, char *response); + static void getvar_product(char *var_parameter, char *response); static void getvar_current_slot(char *var_parameter, char *response); static void getvar_slot_suffixes(char *var_parameter, char *response); static void getvar_has_slot(char *var_parameter, char *response); #ifdef CONFIG_G_AB_SYSTEM -static void getvar_slot_count(char *var_parameter, char *response); static void getvar_slot_successful(char *var_parameter, char *response); static void getvar_slot_unbootable(char *var_parameter, char *response); static void getvar_slot_retry_count(char *var_parameter, char *response); @@ -30,9 +44,15 @@ static void getvar_partition_type(char *part_name, char *response); #endif #if CONFIG_IS_ENABLED(FASTBOOT_FLASH) +static void getvar_partition_type(char *part_name, char *response); static void getvar_partition_size(char *part_name, char *response); #endif +#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK +extern int is_partition_logical(char* parition_name); +#endif + + static const struct { const char *variable; void (*dispatch)(char *var_parameter, char *response); @@ -47,6 +67,42 @@ .variable = "version-bootloader", .dispatch = getvar_bootloader_version }, { + .variable = "off-mode-charge", + .dispatch = getvar_off_mode_charge + }, { + .variable = "hw-revision", + .dispatch = getvar_hw_revision + }, { + .variable = "variant", + .dispatch = getvar_variant + }, { + .variable = "battery-soc-ok", + .dispatch = getvar_battery_soc_ok + }, { + .variable = "battery-voltage", + .dispatch = getvar_battery_voltage + }, { + .variable = "erase-block-size", + .dispatch = getvar_block_size + }, { + .variable = "logical-block-size", + .dispatch = getvar_block_size + }, { + .variable = "secure", + .dispatch = getvar_secure + }, { + .variable = "unlocked", + .dispatch = getvar_unlocked + }, { + .variable = "is-userspace", + .dispatch = getvar_is_userspace + }, { + .variable = "is-logical", + .dispatch = getvar_is_logical + }, { + .variable = "super-partition-name", + .dispatch = getvar_super_partition_name + }, { .variable = "downloadsize", .dispatch = getvar_downloadsize }, { @@ -65,16 +121,19 @@ .variable = "current-slot", .dispatch = getvar_current_slot }, { + .variable = "slot-count", + .dispatch = getvar_slot_count + }, { .variable = "slot-suffixes", .dispatch = getvar_slot_suffixes }, { - .variable = "has_slot", + .variable = "snapshot-update-status", + .dispatch = getvar_snapshot_update_status + }, { + .variable = "has-slot", .dispatch = getvar_has_slot #ifdef CONFIG_G_AB_SYSTEM }, { - .variable = "slot-count", - .dispatch = getvar_slot_count - }, { .variable = "slot-successful", .dispatch = getvar_slot_successful }, { @@ -84,7 +143,7 @@ .variable = "slot-retry-count", .dispatch = getvar_slot_retry_count #endif -#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) }, { .variable = "partition-type", .dispatch = getvar_partition_type @@ -99,59 +158,343 @@ static void getvar_version(char *var_parameter, char *response) { - fastboot_okay(FASTBOOT_VERSION, response); + if (busy_flag == 1) + fastboot_response("INFOversion: ", response, "%s", FASTBOOT_VERSION); + else + fastboot_okay(FASTBOOT_VERSION, response); } static void getvar_bootloader_version(char *var_parameter, char *response) { - fastboot_okay(U_BOOT_VERSION, response); + char s_version[32]; + strncpy(s_version, "01.01.", 6); + strcat(s_version, U_BOOT_BUILD_DATE); + printf("s_version: %s\n", s_version); + if (busy_flag == 1) { + fastboot_response("INFOversion-bootloader: ", response, "%s", s_version); + } else + fastboot_okay(s_version, response); +} + +static void getvar_hw_revision(char *var_parameter, char *response) +{ + if (busy_flag == 1) + fastboot_busy("hw-revision: 0", response); + else + fastboot_okay("0", response); +} + +static void getvar_off_mode_charge(char *var_parameter, char *response) +{ + if (busy_flag == 1) + fastboot_busy("off-mode-charge: 0", response); + else + fastboot_okay("0", response); +} + +static void getvar_variant(char *var_parameter, char *response) +{ + if (busy_flag == 1) + fastboot_busy("variant: US", response); + else + fastboot_okay("US", response); +} + +static void getvar_battery_soc_ok(char *var_parameter, char *response) +{ + if (busy_flag == 1) + fastboot_busy("battery-soc-ok: yes", response); + else + fastboot_okay("yes", response); +} + +static void getvar_battery_voltage(char *var_parameter, char *response) +{ + if (busy_flag == 1) + fastboot_busy("battery-voltage: 4", response); + else + fastboot_okay("4", response); +} + +static void getvar_block_size(char *var_parameter, char *response) +{ + if (busy_flag == 1) + fastboot_busy("block-size: 2000", response); + else + fastboot_okay("2000", response); +} + +static void getvar_secure(char *var_parameter, char *response) +{ + if (check_lock()) { + if (busy_flag == 1) + fastboot_busy("secure: yes", response); + else + fastboot_okay("yes", response); + } else { + if (busy_flag == 1) + fastboot_busy("secure: no", response); + else + fastboot_okay("no", response); + } +} + +static void getvar_unlocked(char *var_parameter, char *response) +{ + if (check_lock()) { + if (busy_flag == 1) + fastboot_busy("secure: no", response); + else + fastboot_okay("no", response); + } else { + if (busy_flag == 1) + fastboot_busy("secure: yes", response); + else + fastboot_okay("yes", response); + } +} + +static void getvar_is_userspace(char *var_parameter, char *response) +{ + if (dynamic_partition) { + if (busy_flag == 1) + fastboot_busy("is-userspace: no", response); + else + fastboot_okay("no", response); + } else { + if (busy_flag == 1) + fastboot_busy("is-userspace: do not use dynamic", response); + else + fastboot_fail("do not use dynamic", response); + } +} + +static void getvar_super_partition_name(char *var_parameter, char *response) +{ + char *slot_name; + slot_name = env_get("slot-suffixes"); + char name[64]; + if (has_boot_slot == 0) { + strncpy(name, "super-partition-name: super", 64); + } else { + printf("slot-suffixes: %s\n", slot_name); + if (strcmp(slot_name, "0") == 0) { + strncpy(name, "super-partition-name: super_a", 64); + } else if (strcmp(slot_name, "1") == 0) { + strncpy(name, "super-partition-name: super_b", 64); + } + } + if (busy_flag == 1) + fastboot_busy(name, response); + else + fastboot_okay(name, response); +} + +static void getvar_is_logical(char *var_parameter, char *response) +{ + char name[64] = {0}; + strncpy(name, var_parameter, strnlen(var_parameter, 64)); + name[63] = 0; + if (has_boot_slot == 1) { + char *slot_name; + slot_name = env_get("slot-suffixes"); + if ((strcmp(var_parameter, "system") == 0) || (strcmp(var_parameter, "vendor") == 0) + || (strcmp(var_parameter, "odm") == 0) || (strcmp(var_parameter, "product") == 0) + || (strcmp(var_parameter, "system_ext") == 0) || (strcmp(var_parameter, "dtbo") == 0) + || (strcmp(var_parameter, "boot") == 0) || (strcmp(var_parameter, "recovery") == 0) + || (strcmp(var_parameter, "vendor_boot") == 0) || (strcmp(var_parameter, "vbmeta") == 0)) { + if (strcmp(slot_name, "0") == 0) { + strcat(name, "_a"); + } else if (strcmp(slot_name, "1") == 0) { + strcat(name, "_b"); + } + } + } + printf("partition name is %s\n", name); + + if (!dynamic_partition) { + if (busy_flag == 1) + fastboot_response("INFOis_logical:", response, "%s: no", var_parameter); + else + fastboot_okay("no", response); + } else { + if (busy_flag == 1) { +#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK + if (is_partition_logical(name) == 0) { + printf("%s is logic partition\n", name); + fastboot_response("INFOis_logical:", response, "%s: yes", name); + } else { + fastboot_response("INFOis_logical:", response, "%s: no", name); + } +#else + fastboot_response("INFOis_logical:", response, "%s: no", name); +#endif + } else { +#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK + if (is_partition_logical(name) == 0) { + printf("%s is logic partition\n", name); + fastboot_okay("yes", response); + } else { + fastboot_okay("no", response); + } +#else + fastboot_okay("no", response); +#endif + } + } +} + +static void getvar_slot_count(char *var_parameter, char *response) +{ +#ifdef CONFIG_G_AB_SYSTEM + fastboot_okay("2", response); +#else + if (has_boot_slot == 1) { + if (busy_flag == 1) + fastboot_busy("slot-count: 2", response); + else + fastboot_okay("2", response); + } + else { + if (busy_flag == 1) + fastboot_busy("slot-count: 0", response); + else + fastboot_okay("0", response); + } +#endif } static void getvar_downloadsize(char *var_parameter, char *response) { - fastboot_response("OKAY", response, "0x%08x", fastboot_buf_size); + if (busy_flag == 1) + fastboot_response("INFOdownloadsize: ", response, "0x%08x", fastboot_buf_size); + else + fastboot_response("OKAY", response, "0x%08x", fastboot_buf_size); } static void getvar_serialno(char *var_parameter, char *response) { const char *tmp = env_get("serial#"); - if (tmp) - fastboot_okay(tmp, response); - else - fastboot_fail("Value not set", response); + if (busy_flag == 1) { + if (tmp) + fastboot_response("INFOserialno: ", response, "%s", tmp); + else + fastboot_busy("serialno: Value not set", response); + } else { + if (tmp) + fastboot_okay(tmp, response); + else + fastboot_fail("Value not set", response); + } } static void getvar_version_baseband(char *var_parameter, char *response) { - fastboot_okay("N/A", response); + if (busy_flag == 1) + fastboot_busy("version-baseband: N/A", response); + else + fastboot_okay("N/A", response); } static void getvar_product(char *var_parameter, char *response) { const char *board = env_get("board"); - if (board) - fastboot_okay(board, response); - else - fastboot_fail("Board not set", response); + if (busy_flag == 1) { + if (board) + fastboot_response("INFOproduct: ", response, "%s", board); + else + fastboot_busy("product: Board not set", response); + } else { + if (board) + fastboot_okay(board, response); + else + fastboot_fail("Board not set", response); + } } static void getvar_current_slot(char *var_parameter, char *response) { + char *slot; + slot = env_get("slot-suffixes"); + printf("slot-suffixes: %s\n", slot); /* A/B not implemented, for now always return _a */ #ifdef CONFIG_G_AB_SYSTEM const char *s = env_get("active_slot"); printf("active_slot: %s\n", s); fastboot_okay(s, response); #else - fastboot_okay("_a", response); + if (busy_flag == 1) { + if (strcmp(slot, "0") == 0) + fastboot_busy("current-slot: a", response); + else if (strcmp(slot, "1") == 0) + fastboot_busy("current-slot: b", response); + } + else { + if (strcmp(slot, "0") == 0) + fastboot_okay("a", response); + else if (strcmp(slot, "1") == 0) + fastboot_okay("b", response); + } #endif } +static void getvar_snapshot_update_status(char *var_parameter, char *response) +{ + struct misc_virtual_ab_message message; + get_mergestatus(&message); + if (busy_flag == 1) { + if (has_boot_slot == 1) { + switch (message.merge_status) { + case SNAPSHOTTED: + fastboot_busy("snapshotted", response); + break; + case MERGING: + fastboot_busy("merging", response); + break; + default: + fastboot_busy("none", response); + break; + } + } else + fastboot_busy("none", response); + } + else { + if (has_boot_slot == 1) { + switch (message.merge_status) { + case SNAPSHOTTED: + fastboot_okay("snapshotted", response); + break; + case MERGING: + fastboot_okay("merging", response); + break; + default: + fastboot_okay("none", response); + break; + } + } else + fastboot_fail("not ab mode", response); + } +} + static void getvar_slot_suffixes(char *var_parameter, char *response) { - fastboot_okay("_a,_b", response); + char *s; + s = env_get("slot-suffixes"); + printf("slot-suffixes: %s\n", s); + if (busy_flag == 1) { + if (!strcmp(s, "-1") == 0) + fastboot_response("INFOslot-suffixes:", response, "%s", s); + else + fastboot_busy("slot-suffixes: 0", response); + } + else { + if (!strcmp(s, "-1") == 0) + fastboot_okay(s, response); + else + fastboot_okay("0", response); + } } static void getvar_has_slot(char *part_name, char *response) @@ -171,11 +514,6 @@ } #ifdef CONFIG_G_AB_SYSTEM -static void getvar_slot_count(char *var_parameter, char *response) -{ - fastboot_okay("2", response); -} - static void getvar_slot_successful(char *var_parameter, char *response) { char str[128]; @@ -242,7 +580,7 @@ #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) static void getvar_partition_type(char *part_name, char *response) { - int r; + /*int r; struct blk_desc *dev_desc; disk_partition_t part_info; @@ -250,38 +588,82 @@ response); if (r >= 0) { r = fs_set_blk_dev_with_part(dev_desc, r); - if (r < 0) - fastboot_fail("failed to set partition", response); + if (r < 0) { + if (busy_flag == 1) + fastboot_response("INFOpartition-type:", response, "%s: failed to set partition", part_name); + else + fastboot_fail("failed to set partition", response); + } else { + if (busy_flag == 1) + fastboot_busy(fs_get_type_name(), response); + else + fastboot_okay(fs_get_type_name(), response); + } + }*/ + if ((strcmp(part_name, "system") == 0) || (strcmp(part_name, "vendor") == 0) + || (strcmp(part_name, "odm") == 0) || (strcmp(part_name, "product") == 0) + || (strcmp(part_name, "system_ext") == 0) || (strcmp(part_name, "dtbo") == 0) + || (strcmp(part_name, "metadata") == 0) || (strcmp(part_name, "vbmeta") == 0) + || (strcmp(part_name, "data") == 0) || (strcmp(part_name, "userdata") == 0)){ + if (busy_flag == 1) + fastboot_response("INFOpartition-type:", response, "%s: ext4", part_name); else - fastboot_okay(fs_get_type_name(), response); + fastboot_okay("ext4", response); + } else if (strcmp(part_name, "cache") == 0) { + if (has_boot_slot == 0) { + if (busy_flag == 1) + fastboot_response("INFOpartition-type:", response, "%s: ext4", part_name); + else + fastboot_okay("ext4", response); + } + } else { + if (busy_flag == 1) + fastboot_response("INFOpartition-type:", response, "%s: raw", part_name); + else + fastboot_okay("raw", response); } } -#endif -#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) static void getvar_partition_size(char *part_name, char *response) { int r; size_t size; + char name[32]; + + if (strcmp(part_name, "userdata") == 0 && !vendor_boot_partition) + strncpy(name, "data", 4); + else if (strcmp(part_name, "data") == 0 && vendor_boot_partition) + strncpy(name, "userdata", 8); + else + strncpy(name, part_name, 32); #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) struct blk_desc *dev_desc; disk_partition_t part_info; - r = fastboot_mmc_get_part_info(part_name, &dev_desc, &part_info, + r = fastboot_mmc_get_part_info(name, &dev_desc, &part_info, response); if (r >= 0) - size = part_info.size; + size = part_info.size * 512; #endif #if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND) struct part_info *part_info; - r = fastboot_nand_get_part_info(part_name, &part_info, response); + r = fastboot_nand_get_part_info(name, &part_info, response); if (r >= 0) - size = part_info->size; + size = part_info->size * 512; #endif - if (r >= 0) - fastboot_response("OKAY", response, "0x%016zx", size); + if (r >= 0) { + if (busy_flag == 1) { + char name[64]; + strncpy(name, "INFOpartition-size:", 64); + strcat(name, part_name); + strcat(name, ": "); + fastboot_response(name, response, "0x%016zx", size); + } + else + fastboot_response("OKAY", response, "0x%016zx", size); + } } #endif @@ -317,6 +699,8 @@ return; } + printf("fastboot_getvar cmd_parameter: %s\n", cmd_parameter); + strsep(&var_parameter, ":"); for (i = 0; i < ARRAY_SIZE(getvar_dispatch); ++i) { if (!strcmp(getvar_dispatch[i].variable,
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 4c1c7fd..7f085d9 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c
@@ -15,6 +15,7 @@ #include <div64.h> #include <linux/compat.h> #include <android_image.h> +#include <amlogic/aml_mmc.h> #define FASTBOOT_MAX_BLK_WRITE 16384 @@ -36,7 +37,7 @@ char *aliased_part_name; /* check for alias */ - strcpy(env_alias_name, "fastboot_partition_alias_"); + strncpy(env_alias_name, "fastboot_partition_alias_", 26); strncat(env_alias_name, name, 32); aliased_part_name = env_get(env_alias_name); if (aliased_part_name != NULL) @@ -63,21 +64,22 @@ lbaint_t blks = 0; int i; - for (i = 0; i < blkcnt; i += FASTBOOT_MAX_BLK_WRITE) { - cur_blkcnt = min((int)blkcnt - i, FASTBOOT_MAX_BLK_WRITE); - if (buffer) { + if (buffer) { + for (i = 0; i < blkcnt; i += FASTBOOT_MAX_BLK_WRITE) { + cur_blkcnt = min((int)blkcnt - i, FASTBOOT_MAX_BLK_WRITE); if (fastboot_progress_callback) fastboot_progress_callback("writing"); blks_written = blk_dwrite(block_dev, blk, cur_blkcnt, buffer + (i * block_dev->blksz)); - } else { - if (fastboot_progress_callback) - fastboot_progress_callback("erasing"); - blks_written = blk_derase(block_dev, blk, cur_blkcnt); + blk += blks_written; + blks += blks_written; } - blk += blks_written; - blks += blks_written; + } else { + if (fastboot_progress_callback) + fastboot_progress_callback("erasing"); + blks = blk_derase(block_dev, start, blkcnt); } + return blks; } @@ -138,9 +140,10 @@ * * @return Boot image header sectors count or 0 on error */ +typedef struct andr_img_hdr boot_img_hdr_t; static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc, disk_partition_t *info, - struct andr_img_hdr *hdr, + boot_img_hdr_t *hdr, char *response) { ulong sector_size; /* boot partition sector size */ @@ -149,7 +152,7 @@ /* Calculate boot image sectors count */ sector_size = info->blksz; - hdr_sectors = DIV_ROUND_UP(sizeof(struct andr_img_hdr), sector_size); + hdr_sectors = DIV_ROUND_UP(sizeof(boot_img_hdr_t), sector_size); if (hdr_sectors == 0) { pr_err("invalid number of boot sectors: 0\n"); fastboot_fail("invalid number of boot sectors: 0", response); @@ -191,7 +194,7 @@ char *response) { uintptr_t hdr_addr; /* boot image header address */ - struct andr_img_hdr *hdr; /* boot image header */ + boot_img_hdr_t *hdr; /* boot image header */ lbaint_t hdr_sectors; /* boot image header sectors */ u8 *ramdisk_buffer; u32 ramdisk_sector_start; @@ -214,7 +217,7 @@ /* Put boot image header in fastboot buffer after downloaded zImage */ hdr_addr = (uintptr_t)download_buffer + ALIGN(download_bytes, PAGE_SIZE); - hdr = (struct andr_img_hdr *)hdr_addr; + hdr = (boot_img_hdr_t *)hdr_addr; /* Read boot image header */ hdr_sectors = fb_mmc_get_boot_header(dev_desc, &info, hdr, response); @@ -322,6 +325,68 @@ return r; } +/* erase or flash, when buffer is not NULL, it's write */ +static void fb_mmc_bootloader_ops(const char *cmd, + struct blk_desc *dev_desc, + void *buffer, unsigned int bytes, + char *response) +{ + char *delim = "-"; + char *hwpart; + int map = 0, ret = 0; + char *scmd = (char *) cmd; + char *ops[] = {"erase", "write"}; + + hwpart = strchr(scmd, (int)*delim); + + if (!hwpart) { + map = AML_BL_USER; + } else if (!strcmp(hwpart, "-boot0")) { + map = AML_BL_BOOT0; + } else if (!strcmp(hwpart, "-boot1")) { + map = AML_BL_BOOT1; + } + if (map) { + if (buffer) + ret = amlmmc_write_bootloader(CONFIG_FASTBOOT_FLASH_MMC_DEV, map, + bytes, buffer); + else + ret = amlmmc_erase_bootloader(CONFIG_FASTBOOT_FLASH_MMC_DEV, map); + if (ret) { + printf("failed %s %s from device %d", (buffer? ops[1]: ops[0]), + cmd, dev_desc->devnum); + fastboot_fail("failed bootloader operating to device", response); + return; + } + printf("........ %s %s\n", (buffer? ops[1]: ops[0]), cmd); + fastboot_okay("", response); + } else + fastboot_fail("failed opearting from device", response); + return; +} + +/** + * write bootloader on user/boot0/boot1 + * according to bootloader name. + */ +static void fb_mmc_write_bootloader(const char *cmd, + struct blk_desc *dev_desc, + void *buffer, unsigned int bytes, + char *response) +{ + return fb_mmc_bootloader_ops(cmd, dev_desc, buffer, bytes, response); +} + +/** + * erase bootloader on user/boot0/boot1 + * according to bootloader name. + */ +static void fb_mmc_erase_bootloader(const char *cmd, struct blk_desc *dev_desc, + char *response) +{ + return fb_mmc_bootloader_ops(cmd, dev_desc, NULL, 0, response); +} + /** * fastboot_mmc_flash_write() - Write image to eMMC for fastboot * @@ -334,6 +399,7 @@ u32 download_bytes, char *response) { struct blk_desc *dev_desc; + int ret = 0; disk_partition_t info; dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); @@ -394,37 +460,57 @@ } #endif - if (part_get_info_by_name_or_alias(dev_desc, cmd, &info) < 0) { - pr_err("cannot find partition: '%s'\n", cmd); - fastboot_fail("cannot find partition", response); + if (strcmp(cmd, "dtb") == 0) { +#ifndef DTB_BIND_KERNEL + ret = dtb_write(download_buffer); + if (ret) + fastboot_fail("fastboot write dtb fail", response); + else { + /* renew partition table @ once*/ + if (renew_partition_tbl(download_buffer)) + fastboot_fail("fastboot write dtb fail", response); + fastboot_okay("", response); + } +#else + fastboot_fail("dtb is bind in kernel, return", response); +#endif + } else if (!strncmp(cmd, "bootloader", strlen("bootloader"))) { + fb_mmc_write_bootloader(cmd, dev_desc, download_buffer, + download_bytes, response); return; - } - - if (is_sparse_image(download_buffer)) { - struct fb_mmc_sparse sparse_priv; - struct sparse_storage sparse; - int err; - - sparse_priv.dev_desc = dev_desc; - - sparse.blksz = info.blksz; - sparse.start = info.start; - sparse.size = info.size; - sparse.write = fb_mmc_sparse_write; - sparse.reserve = fb_mmc_sparse_reserve; - sparse.mssg = fastboot_fail; - - printf("Flashing sparse image at offset " LBAFU "\n", - sparse.start); - - sparse.priv = &sparse_priv; - err = write_sparse_image(&sparse, cmd, download_buffer, - response); - if (!err) - fastboot_okay(NULL, response); } else { - write_raw_image(dev_desc, &info, cmd, download_buffer, - download_bytes, response); + if (part_get_info_by_name_or_alias(dev_desc, cmd, &info) < 0) { + pr_err("cannot find partition: '%s'\n", cmd); + fastboot_fail("cannot find partition", response); + return; + } + + if (is_sparse_image(download_buffer)) { + struct fb_mmc_sparse sparse_priv; + struct sparse_storage sparse; + int err; + + sparse_priv.dev_desc = dev_desc; + + sparse.blksz = info.blksz; + sparse.start = info.start; + sparse.size = info.size; + sparse.write = fb_mmc_sparse_write; + sparse.reserve = fb_mmc_sparse_reserve; + sparse.mssg = fastboot_fail; + + printf("Flashing sparse image at offset " LBAFU "\n", + sparse.start); + + sparse.priv = &sparse_priv; + err = write_sparse_image(&sparse, cmd, download_buffer, + response); + if (!err) + fastboot_okay(NULL, response); + } else { + write_raw_image(dev_desc, &info, cmd, download_buffer, + download_bytes, response); + } } } @@ -455,34 +541,50 @@ return; } - ret = part_get_info_by_name_or_alias(dev_desc, cmd, &info); - if (ret < 0) { - pr_err("cannot find partition: '%s'\n", cmd); - fastboot_fail("cannot find partition", response); + if (strcmp(cmd, "dtb") == 0) { +#ifndef DTB_BIND_KERNEL + ret = emmc_erase_rsv(mmc, cmd); + if (ret) { + fastboot_fail("fastboot erase dtb fail", response); + return; + } + fastboot_okay(NULL, response); +#else + fastboot_fail("dtb is bind in kernel, return", response); +#endif + } else if (!strncmp(cmd, "bootloader", strlen("bootloader"))) { + fb_mmc_erase_bootloader(cmd, dev_desc, response); return; + } else { + ret = part_get_info_by_name_or_alias(dev_desc, cmd, &info); + if (ret < 0) { + pr_err("cannot find partition: '%s'\n", cmd); + fastboot_fail("cannot find partition", response); + return; + } + + /* Align blocks to erase group size to avoid erasing other partitions */ + grp_size = mmc->erase_grp_size; + blks_start = (info.start + grp_size - 1) & ~(grp_size - 1); + if (info.size >= grp_size) + blks_size = (info.size - (blks_start - info.start)) & + (~(grp_size - 1)); + else + blks_size = 0; + + printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n", + blks_start, blks_start + blks_size); + + blks = fb_mmc_blk_write(dev_desc, blks_start, blks_size, NULL); + + if (blks) { + pr_err("failed erasing from device %d\n", dev_desc->devnum); + fastboot_fail("failed erasing from device", response); + return; + } + + printf("........ erased " LBAFU " bytes from '%s'\n", + blks_size * info.blksz, cmd); + fastboot_okay(NULL, response); } - - /* Align blocks to erase group size to avoid erasing other partitions */ - grp_size = mmc->erase_grp_size; - blks_start = (info.start + grp_size - 1) & ~(grp_size - 1); - if (info.size >= grp_size) - blks_size = (info.size - (blks_start - info.start)) & - (~(grp_size - 1)); - else - blks_size = 0; - - printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n", - blks_start, blks_start + blks_size); - - blks = fb_mmc_blk_write(dev_desc, blks_start, blks_size, NULL); - - if (blks != blks_size) { - pr_err("failed erasing from device %d\n", dev_desc->devnum); - fastboot_fail("failed erasing from device", response); - return; - } - - printf("........ erased " LBAFU " bytes from '%s'\n", - blks_size * info.blksz, cmd); - fastboot_okay(NULL, response); }
diff --git a/drivers/fastboot/fb_nand.c b/drivers/fastboot/fb_nand.c index 526bc12..ab237d1 100644 --- a/drivers/fastboot/fb_nand.c +++ b/drivers/fastboot/fb_nand.c
@@ -13,6 +13,10 @@ #include <linux/mtd/mtd.h> #include <jffs2/jffs2.h> #include <nand.h> +#include <amlogic/storage.h> +#include <amlogic/aml_mtd.h> +#include <amlogic/aml_nand.h> +#include <amlogic/aml_rsv.h> struct fb_nand_sparse { struct mtd_info *mtd; @@ -45,6 +49,8 @@ return ret; } + if (strcmp(partname, "dtb") == 0) + return 0; ret = find_dev_and_part(partname, &dev, &pnum, part); if (ret) { pr_err("cannot find partition: '%s'", partname); @@ -173,7 +179,10 @@ { struct part_info *part; struct mtd_info *mtd = NULL; - int ret; + int ret, err; + int copy_num = 0, i = 0; + u64 off = 0; + size_t rwsize = 0, limit = 0; ret = fb_nand_lookup(cmd, &mtd, &part, response); if (ret) { @@ -182,6 +191,67 @@ return; } + if (strcmp(cmd, "bootloader") == 0) { + rwsize = download_bytes; +#ifdef CONFIG_DISCRETE_BOOTLOADER + copy_num = CONFIG_BL2_COPY_NUM; + limit = mtd->size / copy_num; +#else + copy_num = get_boot_num(mtd, rwsize); + limit = mtd->size / copy_num; +#endif + for (i = 0; i < copy_num; i++) { + printf("off = 0x%llx,wsize = 0x%lx\n", + off, rwsize); + err = nand_write_skip_bad(mtd, off, &rwsize, + NULL, limit, + (u_char *)download_buffer, 0); + if (err) { + rwsize = download_bytes; + printf("bootloader write err,code = %d\n",err); + } + off += limit; + } + fastboot_okay("write bootloader", response); + return; + } + +#ifdef CONFIG_DISCRETE_BOOTLOADER + if (strcmp(cmd, "tpl") == 0) { + copy_num = CONFIG_TPL_COPY_NUM; + rwsize = download_bytes; + limit = CONFIG_TPL_SIZE_PER_COPY; + off = 1024 * mtd->writesize + + NAND_RSV_BLOCK_NUM * mtd->erasesize; + + for (i = 0; i < copy_num; i++) { + printf("off = 0x%llx,wsize = 0x%lx\n", off, rwsize); + err = nand_write_skip_bad(mtd, off, &rwsize, + NULL, limit, + (u_char *)download_buffer, 0); + if (err) { + rwsize = download_bytes; + printf("tpl write err,code = %d\n",err); + } + off += CONFIG_TPL_SIZE_PER_COPY; + } + fastboot_okay("write tpl", response); + return; + } +#endif + + if (strcmp(cmd, "dtb") == 0) { + ret = store_rsv_write("dtb", download_bytes, (u8 *)download_buffer); + printf("Flashing dtb...len:0x%x\n", download_bytes); + if (ret) { + printf("write dtb fail,result code %d\n", ret); + fastboot_fail("write dtb", response); + } else { + fastboot_okay("write dtb", response); + } + return; + } + ret = board_fastboot_write_partition_setup(part->name); if (ret) return; @@ -246,6 +316,18 @@ return; } + if (strcmp(cmd, "dtb") == 0) { + ret = store_rsv_erase("dtb"); + if (ret) { + pr_err("erase dtb fail,ret = %d\n", ret); + fastboot_fail("erase dtb", + response); + } else { + fastboot_okay("erase dtb", response); + } + return; + } + ret = board_fastboot_erase_partition_setup(part->name); if (ret) return;
diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c index 4e8fa21..d77aa77 100644 --- a/drivers/i2c/i2c-gpio.c +++ b/drivers/i2c/i2c-gpio.c
@@ -24,6 +24,8 @@ PIN_COUNT, }; +static unsigned int is_odpin; + struct i2c_gpio_bus { /** * udelay - delay [us] between GPIO toggle operations, @@ -51,6 +53,15 @@ { ulong flags = GPIOD_IS_OUT; + if (is_odpin) { + if (bit) + dm_gpio_set_dir_flags(scl, GPIOD_IS_IN); + else + dm_gpio_set_dir_flags(scl, flags | GPIOD_IS_OUT_ACTIVE); + + return; + } + if (bit) flags |= GPIOD_IS_OUT_ACTIVE; dm_gpio_set_dir_flags(scl, flags); @@ -320,6 +331,8 @@ bus->udelay = fdtdec_get_int(blob, node, "i2c-gpio,delay-us", DEFAULT_UDELAY); + is_odpin = fdtdec_get_int(blob, node, "is_odpin", 0); + return 0; error: pr_err("Can't get %s gpios! Error: %d", dev->name, ret);
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 3ce0da2..6752d8d 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig
@@ -18,6 +18,12 @@ help Enable write access to MMC and SD Cards +config MMC_FBOOT + bool "support for MMC fast boot" + default n + help + Enable MMC fast boot + config MMC_BROKEN_CD bool "Poll for broken card detection case" help
diff --git a/drivers/mmc/aml_emmc_partition.c b/drivers/mmc/aml_emmc_partition.c index c55f7e6..c6ca618 100755 --- a/drivers/mmc/aml_emmc_partition.c +++ b/drivers/mmc/aml_emmc_partition.c
@@ -32,7 +32,12 @@ #endif /* debug info*/ #define CONFIG_MPT_DEBUG (0) + +#ifdef AML_ENABLE_PRODUCTION_MODE #define GPT_PRIORITY (1) +#else +#define GPT_PRIORITY (0) +#endif #ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY #define FALSE 0 @@ -129,6 +134,8 @@ #endif VIRTUAL_PARTITION_ELEMENT(MMC_KEY_NAME, EMMCKEY_RESERVE_OFFSET, MMC_KEY_SIZE), VIRTUAL_PARTITION_ELEMENT(MMC_PATTERN_NAME, CALI_PATTERN_OFFSET, CALI_PATTERN_SIZE), + VIRTUAL_PARTITION_ELEMENT(MMC_MAGIC_NAME, MAGIC_OFFSET, MAGIC_SIZE), + VIRTUAL_PARTITION_ELEMENT(MMC_RANDOM_NAME, RANDOM_OFFSET, RANDOM_SIZE), #ifndef DTB_BIND_KERNEL VIRTUAL_PARTITION_ELEMENT(MMC_DTB_NAME, DTB_OFFSET, DTB_SIZE), #endif @@ -1189,8 +1196,8 @@ partitions[i].mask_flags = (uint32_t)le64_to_cpu(gpt_pte[i].attributes.fields.reserved); #ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY - memcpy(partitions[i].type_guid, gpt_pte[i].partition_type_guid.b, sizeof(efi_guid_t)); - memcpy(partitions[i].uuid, gpt_pte[i].unique_partition_guid.b, sizeof(efi_guid_t)); + memcpy(partitions[i].type_guid.b, gpt_pte[i].partition_type_guid.b, sizeof(efi_guid_t)); + memcpy(partitions[i].uuid.b, gpt_pte[i].unique_partition_guid.b, sizeof(efi_guid_t)); memcpy(&(partitions[i].attributes), &(gpt_pte[i].attributes), sizeof(gpt_entry_attributes)); #endif /* partition name */ @@ -1220,25 +1227,64 @@ strcpy((char *)disk_part[i].name, part[i].name); /* store maskflag into type, 8bits ONLY! */ disk_part[i].type[0] = (uchar)part[i].mask_flags; - #ifdef CONFIG_PARTITION_TYPE_GUID #ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY #ifdef CONFIG_ARCH_MESON if (disk_part[i].type[0]) disk_part[i].attributes.fields.reserved = disk_part[i].type[0]; #endif /* CONFIG_ARCH_MESON */ if (gpt_broken_status) { - memcpy(disk_part[i].type_guid, part[i].type_guid, sizeof(efi_guid_t)); - memcpy(disk_part[i].uuid, part[i].uuid, sizeof(efi_guid_t)); + memcpy(disk_part[i].partition_type_guid.b, part[i].type_guid.b, sizeof(efi_guid_t)); + memcpy(disk_part[i].unique_partition_guid.b, part[i].uuid.b, sizeof(efi_guid_t)); memcpy(&(disk_part[i].attributes), &(part[i].attributes), sizeof(gpt_entry_attributes)); } else { +#if CONFIG_IS_ENABLED(PARTITION_UUIDS) + char *str_uuid; + unsigned char *bin_uuid; #endif +#ifdef CONFIG_PARTITION_TYPE_GUID + char *str_type_guid; + unsigned char *bin_type_guid; +#endif +#ifdef CONFIG_PARTITION_TYPE_GUID + str_type_guid = part[i].name; + bin_type_guid = disk_part[i].partition_type_guid.b; +#endif +#if CONFIG_IS_ENABLED(PARTITION_UUIDS) + gen_rand_uuid_str(disk_part[i].uuid, UUID_STR_FORMAT_STD); + str_uuid = disk_part[i].uuid; + bin_uuid = disk_part[i].unique_partition_guid.b; +#endif +#ifdef CONFIG_PARTITION_TYPE_GUID + if (strlen(str_type_guid)) { + if (uuid_str_to_bin(str_type_guid, bin_type_guid, + UUID_STR_FORMAT_GUID)) { +#ifdef CONFIG_AML_GPT + char str[8] = {"default"}; + uuid_str_to_bin(str, bin_type_guid, + UUID_STR_FORMAT_GUID); + } + } +#else + printf("Partition no. %d: invalid type guid: %s\n", + i, str_type_guid); + return; + } + } +#endif +#endif +#if CONFIG_IS_ENABLED(PARTITION_UUIDS) + if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_GUID)) { + printf("Partition no. %d: invalid guid: %s\n", + i, str_uuid); + return; + } +#endif + } +#else strcpy((char *)disk_part[i].type_guid, part[i].name); - #endif #ifdef CONFIG_RANDOM_UUID gen_rand_uuid_str(disk_part[i].uuid, UUID_STR_FORMAT_STD); #endif -#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY - } #endif disk_part[i].bootable = 0; if ( i == (count - 1)) @@ -1249,9 +1295,6 @@ return; } - - - #endif /***************************************************
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 8acf17e..55d8be8 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c
@@ -16,6 +16,7 @@ #include <linux/log2.h> #include <dm/pinctrl.h> #include "mmc_private.h" +#include <asm/arch/register.h> static inline void *get_regbase(const struct mmc *mmc) { @@ -112,15 +113,21 @@ return; if (mmc->clock > 12000000) { - clk = 1200000000; - clk_src = 0; - /*config emmc clk tree use gp_pll(1.2G)*/ - writel(0x900, ((0x0048<<2) + 0xfe000800)); + clk = 1000000000; + clk_src = 1; + clk_disable(&host->xtal); + clk_set_parent(&host->mux, &host->div2); + clk_set_rate(&host->div, clk); } else { clk = 24000000; clk_src = 0; - writel(0x8100, ((0x0048<<2) + 0xfe000800)); + clk_enable(&host->xtal); + clk_set_rate(&host->div, clk); } + clk_div = (clk / mmc->clock) + (!!(clk % mmc->clock)); + + //printf("sd_emmc_clk_ctrl:0x%x\n", readl(((0x0038<<2) + 0xfe000800))); + //printf("sd_emmc_clk_ctrl1:0x%x\n", readl(((0x0048<<2) + 0xfe000800))); clk_div = clk / mmc->clock; if (clk % mmc->clock) @@ -143,6 +150,8 @@ dev_read_u32(mmc->dev, "hs_tx_phase", &tx_phase); break; case SD_HS: + dev_read_u32(mmc->dev, "sd_hs_co_phase", &co_phase); + dev_read_u32(mmc->dev, "sd_hs_tx_phase", &tx_phase); break; case MMC_HS_200: dev_read_u32(mmc->dev, "hs2_co_phase", &co_phase); @@ -175,7 +184,7 @@ (clk_src << Cfg_src) | (clk_div << Cfg_div)); - writel(meson_mmc_clk, 0xfe012000); + meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK); } static int meson_dm_mmc_set_ios(struct udevice *dev) @@ -202,18 +211,6 @@ else return -EINVAL; - /* 512 bytes block length */ - meson_mmc_cfg &= ~CFG_BL_LEN_MASK; - meson_mmc_cfg |= CFG_BL_LEN_512; - - /* Response timeout 256 clk */ - meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK; - meson_mmc_cfg |= CFG_RESP_TIMEOUT_256; - - /* Command-command gap 16 clk */ - meson_mmc_cfg &= ~CFG_RC_CC_MASK; - meson_mmc_cfg |= CFG_RC_CC_16; - meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG); return 0; @@ -732,6 +729,11 @@ int curr_win_start = -1, curr_win_size = 0; u8 rx_tuning_result[25] = { 0 }; + if (opcode == MMC_SD_HS_TUNING) { + meson_write(mmc, 0x2000, MESON_SD_EMMC_ADJUST); + return 0; + } + if (host->blk_test == NULL) return -EINVAL; @@ -964,25 +966,30 @@ uclass_get_device_by_name(UCLASS_CLK, "amlogic,g12a-clkc", &clk_udevice); - clk_get_by_name(dev, "core", &host->core); - clk_get_by_name(dev, "clkin0", &host->xtal); - clk_get_by_name(dev, "clkin1", &host->div2); + clk_get_by_name(dev, "clkin", &host->div2); + clk_get_by_name(dev, "xtal", &host->xtal); clk_get_by_name(dev, "mux", &host->mux); clk_get_by_name(dev, "div", &host->div); clk_get_by_name(dev, "gate", &host->gate); //clk_enable(&host->core); - //clk_enable(&host->gate); + clk_enable(&host->gate); return 0; } -void mmc_set_source_clock(void) +/*void mmc_set_source_clock(struct udevice *dev) { - writel(0x81008100, ((0x0038<<2) + 0xfe000800)); - writel(0x8100, ((0x0048<<2) + 0xfe000800)); - pr_debug("===========0x%x\n", readl(((0x0038<<2) + 0xfe000800))); -} + struct meson_host *host = dev_get_priv(dev); + unsigned long rate; + + clk_set_rate(&host->div, 1000000000); + clk_disable(&host->xtal); + clk_enable(&host->gate); + + printf("sd_emmc_clk_ctrl:0x%x\n", readl(((0x0038<<2) + 0xfe000800))); + printf("sd_emmc_clk_ctrl1:0x%x\n", readl(((0x0048<<2) + 0xfe000800))); +}*/ static int meson_mmc_probe(struct udevice *dev) { @@ -1017,7 +1024,7 @@ mmc->priv = pdata; upriv->mmc = mmc; - mmc_set_source_clock(); + //mmc_set_source_clock(dev); mmc_set_clock(mmc, cfg->f_min, false); @@ -1031,12 +1038,24 @@ val = meson_read(mmc, MESON_SD_EMMC_CFG); val &= ~CFG_SDCLK_ALWAYS_ON; val |= CFG_AUTO_CLK; + + /* 512 bytes block length */ + val &= ~CFG_BL_LEN_MASK; + val |= CFG_BL_LEN_512; + + /* Response timeout 256 clk */ + val &= ~CFG_RESP_TIMEOUT_MASK; + val |= CFG_RESP_TIMEOUT_256; + + /* Command-command gap 16 clk */ + val &= ~CFG_RC_CC_MASK; + val |= CFG_RC_CC_16; meson_write(mmc, val, MESON_SD_EMMC_CFG); - pr_info("%s: probe success!\n", mmc->cfg->name); + printf("[%s]%s: probe success!\n", __func__, mmc->cfg->name); return 0; err: - pr_err("%s: probe fail, ret = %d!\n", mmc->cfg->name, ret); + pr_err("[%s]%s: probe fail, ret = %d!\n", __func__, mmc->cfg->name, ret); if (host->blk_test) free(host->blk_test); if (host->desc_buf)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 7d4e7f0..6534df0 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c
@@ -28,6 +28,11 @@ static int amlmmc_init = 0; +struct aml_pattern aml_pattern_table[] = { + AML_PATTERN_ELEMENT(MMC_PATTERN_NAME, CALI_PATTERN), + AML_PATTERN_ELEMENT(MMC_MAGIC_NAME, MAGIC_PATTERN), + AML_PATTERN_ELEMENT(MMC_RANDOM_NAME, RANDOM_PATTERN), +}; static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); static int mmc_power_cycle(struct mmc *mmc); #if !CONFIG_IS_ENABLED(MMC_TINY) @@ -1886,6 +1891,9 @@ { .mode = MMC_HS_52, .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, +#ifdef MMC_SUPPORTS_TUNING + .tuning = MMC_SD_HS_TUNING +#endif }, { .mode = MMC_HS, @@ -1992,8 +2000,6 @@ return -ENOTSUPP; } - mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE); - for_each_mmc_mode_by_pref(card_caps, mwt) { for_each_supported_width(card_caps & mwt->widths, mmc_is_mode_ddr(mwt->mode), ecbw) { @@ -2306,6 +2312,7 @@ } #endif +#ifdef CONFIG_MMC_FBOOT if (emmc_boot_chk(mmc)) { mmc_switch_part(mmc, 0); @@ -2331,6 +2338,7 @@ memcpy(mmc->cid, cmd.response, 16); } else { +#endif /* Put the Card in Identify Mode */ cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ @@ -2377,7 +2385,9 @@ if (IS_SD(mmc)) mmc->rca = (cmd.response[0] >> 16) & 0xffff; } +#ifdef CONFIG_MMC_FBOOT } +#endif /* Get the Card-Specific Data */ cmd.cmdidx = MMC_CMD_SEND_CSD; @@ -2793,11 +2803,13 @@ return -ENOMEDIUM; } +#ifdef CONFIG_MMC_FBOOT if (emmc_boot_chk(mmc)) { mmc->high_capacity = 1; mmc->rca = 1; mmc->version = MMC_VERSION_UNKNOWN; } else +#endif err = mmc_get_op_cond(mmc); if (!err) @@ -2861,9 +2873,68 @@ return mmc_set_ext_csd(mmc, 16, 57); } +void mmc_write_cali_mattern(void *addr, struct aml_pattern *table) +{ + int i = 0; + unsigned int s = 10; + u32 *mattern = (u32 *)addr; + struct virtual_partition *vpart = + aml_get_virtual_partition_by_name(table->name); + for (i = 0;i < (vpart->size)/4 - 1;i++) { + if (!strcmp(table->name, "random")) + mattern[i] = rand_r(&s); + else + mattern[i] = table->pattern; + } + mattern[i] = crc32(0, (u8 *)addr, (vpart->size - 4)); + return; +} + +int mmc_pattern_check(struct mmc *mmc, struct aml_pattern *table) +{ + void *addr = NULL; + u64 cnt = 0, n = 0, blk = 0; + u32 *buf = NULL; + u32 crc32_s = 0; + struct partitions *part = NULL; + struct virtual_partition *vpart = NULL; + + vpart = aml_get_virtual_partition_by_name(table->name); + + addr = (void *)malloc(vpart->size); + if (!addr) { + printf("%s malloc failed\n", table->name); + return 1; + } + part = aml_get_partition_by_name(MMC_RESERVED_NAME); + blk = (part->offset + vpart->offset) / mmc->read_bl_len; + cnt = vpart->size / mmc->read_bl_len; + n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr); + if (n != cnt) { + printf("read pattern failed\n"); + free(addr); + return 1; + } else { + buf = (u32 *)addr; + crc32_s = crc32(0, (u8 *)addr, (vpart->size - 4)); + if (crc32_s != buf[vpart->size/4 - 1]) { + printf("check %s failed,need to write\n", + table->name); + mmc_write_cali_mattern(addr, table); + n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr); + printf("several 0x%x pattern blocks write %s\n", + table->pattern, (n == cnt) ? "OK" : "ERROR"); + } + printf("crc32_s:0x%x == storage crc_pattern:0x%x!!!\n", + crc32_s, buf[vpart->size/4 - 1]); + } + free(addr); + return (n == cnt) ? 0 : 1; +} + int mmc_init(struct mmc *mmc) { - int err = 0; + int err = 0, i; __maybe_unused ulong start; #if CONFIG_IS_ENABLED(DM_MMC) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); @@ -2886,8 +2957,10 @@ if (IS_MMC(mmc)) { if (!is_partition_checked) { if (mmc_device_init(mmc) == 0) { - is_partition_checked = true; - pr_info("eMMC/TSD partition table have been checked OK!\n"); + is_partition_checked = true; + pr_info("eMMC/TSD partition table have been checked OK!\n"); + for (i = 0; i < ARRAY_SIZE(aml_pattern_table); i++) + mmc_pattern_check(mmc, &aml_pattern_table[i]); } } @@ -2969,6 +3042,8 @@ ffu_addr = SAMSUNG_FFU_ADDR; } else if ((mmc->cid[0] >> 24) == KINGSTON_MID) { ffu_addr = KINGSTON_FFU_ADDR; + } else if ((mmc->cid[0] >> 24) == BIWIN_MID) { + ffu_addr = BIWIN_FFU_ADDR; } else { pr_info("FFU update for this manufacturer not support yet\n"); return -1; @@ -2986,8 +3061,13 @@ supported_modes = ext_csd_ffu[EXT_CSD_SUPPORTED_MODES] & 0x1; fw_cfg = ext_csd_ffu[EXT_CSD_FW_CFG] & 0x1; - for (i = 0; i < 8; i++) - fw_ver |= (ext_csd_ffu[EXT_CSD_FW_VERSION + i] << (i * 8)); + for (i = 0; i < 8; i++) { + fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i]; + if (i < 7) + fw_ver <<= 8; + } + if ((mmc->cid[0] >> 24) == BIWIN_MID) + fw_ver = ((fw_ver >> 16) & 0xffffffff); pr_info("old fw_ver = %llx\n", fw_ver); if (!supported_modes || fw_cfg || (fw_ver >= ffu_ver)) return -1; @@ -3011,8 +3091,13 @@ if (err) return err; - for (i = 0; i < 8; i++) - fw_ver |= (ext_csd_ffu[EXT_CSD_FW_VERSION + i] << (i * 8)); + for (i = 0; i < 8; i++) { + fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i]; + if (i < 7) + fw_ver <<= 8; + } + if ((mmc->cid[0] >> 24) == BIWIN_MID) + fw_ver = ((fw_ver >> 16) & 0xffffffff); pr_info("new fw_ver = %llx\n", fw_ver); if ((mmc->cid[0] >> 24) == SAMSUNG_MID) { /* Set Normal Mode */ @@ -3039,8 +3124,13 @@ return err; ffu_status = ext_csd_ffu[EXT_CSD_FFU_STATUS] & 0xff; fw_ver = 0; - for (i = 0; i < 8; i++) - fw_ver |= (ext_csd_ffu[EXT_CSD_FW_VERSION + i] << (i * 8)); + for (i = 0; i < 8; i++) { + fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i]; + if (i < 7) + fw_ver <<= 8; + } + if ((mmc->cid[0] >> 24) == BIWIN_MID) + fw_ver = ((fw_ver >> 16) & 0xffffffff); pr_info("new fw_ver = %llx\n", fw_ver); if (ffu_status || (fw_ver != ffu_ver)) return ffu_status; @@ -3263,3 +3353,4 @@ } +
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 05674e2..777afbe 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h
@@ -14,8 +14,10 @@ #define SAMSUNG_MID 0x15 #define KINGSTON_MID 0x70 +#define BIWIN_MID 0xf4 #define SAMSUNG_FFU_ADDR 0xc7810000 #define KINGSTON_FFU_ADDR 0x0000ffff +#define BIWIN_FFU_ADDR 0x0 #define MAX_TUNING_RETRY (4) #define CALI_BLK_CNT (1024) #define REFIX_BLK_CNT (100)
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index c53a624..1daf483 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c
@@ -95,6 +95,7 @@ return -1; if (blkcnt == 0) { blkcnt = mmc->capacity/512 - (mmc->capacity/512)% mmc->erase_grp_size; // erase whole + blkcnt = blkcnt - start; printf("blkcnt = %lu\n",blkcnt); } /*
diff --git a/drivers/mmc/storage_emmc.c b/drivers/mmc/storage_emmc.c index ec6d8dd..01bf5e4 100755 --- a/drivers/mmc/storage_emmc.c +++ b/drivers/mmc/storage_emmc.c
@@ -60,6 +60,13 @@ printf("error partition name!\n"); return 1; } + if ((part_info->mask_flags & PART_PROTECT_FLAG) && + !(info_disprotect & DISPROTECT_KEY)) { + printf("%s is protected, pls open it in Dts\n", + part_info->name); + return 1; + } + *off = part_info->offset+offset; if (offset >= part_info->size) { printf("Start address out #%s# partition'address region,(off < 0x%llx)\n", @@ -268,6 +275,36 @@ return ret; } +static int storage_mmc_erase_user(struct mmc *mmc) { + int ret = 0, i; + struct partitions *part_info = NULL; + + if (info_disprotect & DISPROTECT_KEY) {//key disprotect,erase all + ret = blk_derase(mmc_get_blk_desc(mmc), 0, 0); + } else {//key protect partition with the protect_flag + for (i = 0;;i++) { + part_info = get_partition_info_by_num(i); + if (part_info == NULL) + break; + if (!strcmp("reserved", part_info->name)) { + printf("Part:reserved is skiped\n"); + continue; + } + if (part_info->mask_flags & PART_PROTECT_FLAG) { + printf("Part:%s is protected\n", part_info->name); + continue; + } + ret = blk_derase(mmc_get_blk_desc(mmc), + part_info->offset / BLOCK_SIZE, + part_info->size / BLOCK_SIZE); + printf("Erased: %s %s\n", + part_info->name, + (ret == 0)? "OK" : "ERR"); + } + } + printf("User partition erased: %s\n", (ret == 0) ? "OK" : "ERROR"); + return ret; +} static int storage_mmc_erase(int flag, struct mmc *mmc) { @@ -275,12 +312,8 @@ loff_t off = 0; size_t size = 0; - if (flag >= ERASE_ALL) {//erase all - - info_disprotect |= DISPROTECT_KEY; - ret = blk_derase(mmc_get_blk_desc(mmc), 0, 0); - printf("user partition erased: %s\n", (ret == 0) ? "OK" : "ERROR"); - info_disprotect &= ~DISPROTECT_KEY; + if (flag >= ERASE_ALL) {//erase all except reserved + ret = storage_mmc_erase_user(mmc); if (ret != 0) { return -1; } @@ -400,13 +433,9 @@ return 1; if (!part_name) {//the operating object is the device,the unit of operation is block. - info_disprotect |= DISPROTECT_KEY; - ret = blk_derase(mmc_get_blk_desc(mmc), off, size); - info_disprotect &= ~DISPROTECT_KEY; - printf("%d blocks erased: %s\n", ret, (ret == 0) ? "OK" : "ERROR"); + ret = storage_mmc_erase(ERASE_ALL, mmc); return (ret == 0) ? 0 : 1; } else {//the opering object is partition,the unit of operation is byte. - ret = storage_erase_in_part(part_name, off, size); } return ret; @@ -825,19 +854,16 @@ if (!strcmp("dtb", rsv_name)) { ret = dtb_write(buf); ret |= renew_partition_tbl(buf); - return ret; + } else { + if (!strcmp("key", rsv_name)) + info_disprotect |= DISPROTECT_KEY; + ret = storage_byte_write(mmc, off, size, buf); + if (!strcmp("key", rsv_name)) + info_disprotect &= ~DISPROTECT_KEY; } - if (!strcmp("key", rsv_name)) - info_disprotect |= DISPROTECT_KEY; - if (!strcmp("ddr-parameter", rsv_name)) - amlmmc_check_and_update_boot_info(); - ret = storage_byte_write(mmc, off, size, buf); - if (!strcmp("key", rsv_name)) - info_disprotect &= ~DISPROTECT_KEY; - if (ret != 0) { - printf("write resv failed\n"); - } + if (ret != 0) + printf("write rsv failed\n"); return ret; } @@ -887,6 +913,41 @@ } +void config_storage_dev_func(struct storage_t *dev, struct mmc* mmc) +{ + /******basic info*******/ + dev->type = BOOT_EMMC; + printf("store flag: %d, types: %d\n", dev->init_flag, dev->type); + /*dev->info.name = mmc->cid[0] & 0xff, + (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, + (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff; + dev->info.id = mmc->cid[0] >> 24;*/ + dev->info.read_unit = mmc->read_bl_len; + dev->info.write_unit = mmc->write_bl_len; + dev->info.erase_unit = mmc->erase_grp_size; + dev->info.caps = mmc->capacity_user; + dev->info.mode = COMPACT_BOOTLOADER; + + dev->get_part_size = mmc_storage_get_part_size; + dev->read = mmc_storage_read; + dev->write = mmc_storage_write; + dev->erase = mmc_storage_erase; + + dev->get_copies = mmc_storage_get_copies; + dev->get_copy_size = mmc_get_copy_size; + dev->boot_read = mmc_boot_read; + dev->boot_write = mmc_boot_write; + dev->boot_erase = mmc_boot_erase; + + dev->get_rsv_size = mmc_get_rsv_size; + dev->read_rsv = mmc_read_rsv; + dev->write_rsv = mmc_write_rsv; + dev->erase_rsv = mmc_erase_rsv; + dev->protect_rsv = mmc_protect_rsv; + + return; +} + DECLARE_GLOBAL_DATA_PTR; int sdcard_pre(void) { @@ -903,13 +964,24 @@ { char ret = 1; struct mmc *mmc; + static struct storage_t *storage_dev = NULL; + mmc_initialize(gd->bd); mmc = find_mmc_device(STORAGE_EMMC); ret = mmc_start_init(mmc); - if (ret == 0) - pr_notice("emmc init success!\n"); - else - printf("emmc init fail!\n"); + if (ret == 0) { + /*struct store_operation *storage_opera = NULL;*/ + storage_dev = kzalloc(sizeof(struct storage_t), GFP_KERNEL); + if (storage_dev == NULL) { + printf("malloc failed for storage_dev\n"); + ret = -1; + return ret; + } + config_storage_dev_func(storage_dev, mmc); + store_register(storage_dev); + printf("emmc init success!\n"); + } else + printf("emmc init fail!\n"); return ret; } @@ -917,54 +989,13 @@ int emmc_probe(uint32_t init_flag) { char ret = 0; - struct mmc *mmc; - static struct storage_t *storage_dev = NULL; - /*struct store_operation *storage_opera = NULL;*/ - storage_dev = kzalloc(sizeof(struct storage_t), GFP_KERNEL); - if (storage_dev == NULL) { - printf("malloc failed for storage_dev\n"); - ret = -1; - goto exit_error; - } - mmc = find_mmc_device(STORAGE_EMMC); + ret = mmc_storage_init(init_flag); /*flag 0*/ if (ret) { printf("mmc init failed ret:%x\n", ret); goto exit_error; } - /******basic info*******/ - storage_dev->init_flag = init_flag; - storage_dev->type = BOOT_EMMC; - - pr_info("store flag: %d, types: %d\n",storage_dev->init_flag,storage_dev->type); - /*storage_dev->info.name = mmc->cid[0] & 0xff, - (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, - (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff; - storage_dev->info.id = mmc->cid[0] >> 24;*/ - storage_dev->info.read_unit = mmc->read_bl_len; - storage_dev->info.write_unit = mmc->write_bl_len; - storage_dev->info.erase_unit = mmc->erase_grp_size; - storage_dev->info.caps = mmc->capacity_user; - storage_dev->info.mode = COMPACT_BOOTLOADER; - - storage_dev->get_part_size = mmc_storage_get_part_size; - storage_dev->read = mmc_storage_read; - storage_dev->write = mmc_storage_write; - storage_dev->erase = mmc_storage_erase; - - storage_dev->get_copies = mmc_storage_get_copies; - storage_dev->get_copy_size = mmc_get_copy_size; - storage_dev->boot_read = mmc_boot_read; - storage_dev->boot_write = mmc_boot_write; - storage_dev->boot_erase = mmc_boot_erase; - - storage_dev->get_rsv_size = mmc_get_rsv_size; - storage_dev->read_rsv = mmc_read_rsv; - storage_dev->write_rsv = mmc_write_rsv; - storage_dev->erase_rsv = mmc_erase_rsv; - storage_dev->protect_rsv = mmc_protect_rsv; - store_register(storage_dev); - pr_info("emmc probe success\n"); + printf("emmc probe success\n"); exit_error: return ret;
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 0b626d1..cb158b1 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig
@@ -103,7 +103,7 @@ config AML_MTD bool "support AML MTD for Raw NAND or SPI NAND or SPI NOR" - default y if MESON_NFC || SPI_NAND || SPI_FLASH + default y if MESON_NFC || SPI_NAND || SPI_FLASH || MTD_SPI_NAND help This option, if enabled, support for AML MTD
diff --git a/drivers/mtd/aml_rsv.c b/drivers/mtd/aml_rsv.c index aaf4328..ae8ae10 100644 --- a/drivers/mtd/aml_rsv.c +++ b/drivers/mtd/aml_rsv.c
@@ -71,7 +71,6 @@ } - int meson_rsv_erase_protect(struct meson_rsv_handler_t *handler, u32 block_addr) { @@ -689,8 +688,14 @@ /* reduce memory usage in sram */ handler->dtb->size = mtd->erasesize >> 1; } else { + #ifdef CONFIG_MTD_SPI_NAND + /* Reduce space use, malloc may fail */ + handler->key->size = mtd->erasesize >> 2; + handler->dtb->size = mtd->erasesize >> 1; + #else handler->key->size = 0x40000; handler->dtb->size = 0x40000; + #endif } if ((vernier - start) > NAND_RSV_BLOCK_NUM) { @@ -757,7 +762,7 @@ len = rsv_handler->bbt->size; temp = kzalloc(len, GFP_KERNEL); if (!temp) { - pr_err("%s %d kzalloc fail size = 0x%x\n", + pr_err("%s %d kzalloc fail size = %ld\n", __func__, __LINE__, len); return -ENOMEM; } @@ -798,7 +803,7 @@ len = rsv_handler->key->size; temp = kzalloc(len, GFP_KERNEL); if (!temp) { - pr_err("%s %d kzalloc fail size = 0x%x\n", + pr_err("%s %d kzalloc fail size = 0x%lx\n", __func__, __LINE__, len); return -ENOMEM; } @@ -838,7 +843,7 @@ len = rsv_handler->env->size; temp = kzalloc(len, GFP_KERNEL); if (!temp) { - pr_err("%s %d kzalloc fail size = 0x%x\n", + pr_err("%s %d kzalloc fail size = 0x%lx\n", __func__, __LINE__, len); return -ENOMEM; } @@ -859,7 +864,7 @@ if (!rsv_handler || !rsv_handler->dtb) { - pr_info("%s %d rsv info not inited yet!\n", + pr_info("%s %d rsv info %s not inited yet!\n", __func__, __LINE__, rsv_handler->dtb->name); return 1; @@ -878,7 +883,7 @@ len = rsv_handler->dtb->size; temp = kzalloc(len, GFP_KERNEL); if (!temp) { - pr_err("%s %d kzalloc fail size = 0x%x\n", + pr_err("%s %d kzalloc fail size = 0x%lx\n", __func__, __LINE__, len); return -ENOMEM; } @@ -912,7 +917,7 @@ len = rsv_handler->bbt->size; temp = kzalloc(len, GFP_KERNEL); if (!temp) { - pr_err("%s %d kzalloc fail size = 0x%x\n", + pr_err("%s %d kzalloc fail size = 0x%lx\n", __func__, __LINE__, len); return -ENOMEM; } @@ -945,7 +950,7 @@ len = rsv_handler->key->size; temp = kzalloc(len, GFP_KERNEL); if (!temp) { - pr_err("%s %d kzalloc fail size = 0x%x\n", + pr_err("%s %d kzalloc fail size = 0x%lx\n", __func__, __LINE__, len); return -ENOMEM; } @@ -978,7 +983,7 @@ len = rsv_handler->env->size; temp = kzalloc(len, GFP_KERNEL); if (!temp) { - pr_err("%s %d kzalloc fail size = 0x%x\n", + pr_err("%s %d kzalloc fail size = 0x%lx\n", __func__, __LINE__, len); return -ENOMEM; } @@ -1011,7 +1016,7 @@ len = rsv_handler->dtb->size; temp = kzalloc(len, GFP_KERNEL); if (!temp) { - pr_err("%s %d kzalloc fail size = 0x%x\n", + pr_err("%s %d kzalloc fail size = 0x%lx\n", __func__, __LINE__, len); return -ENOMEM; }
diff --git a/drivers/mtd/aml_storage.c b/drivers/mtd/aml_storage.c index 4e3e6ee..590c01e 100644 --- a/drivers/mtd/aml_storage.c +++ b/drivers/mtd/aml_storage.c
@@ -14,6 +14,7 @@ #include <amlogic/storage.h> #include <amlogic/aml_mtd.h> #include <amlogic/aml_rsv.h> +#include <amlogic/cpu_id.h> #include <asm/arch/cpu_config.h> #include <partition_table.h> #include <time.h> @@ -31,10 +32,11 @@ #endif static struct mtd_info *mtd_store_list[MAX_MTD_CNT]; extern int info_disprotect; +extern struct storage_startup_parameter g_ssp; struct mtd_info *mtd_store_get(int dev) { -#if defined(CONFIG_SPI_FLASH) || defined(CONFIG_SPI_NAND) +#if defined(CONFIG_SPI_FLASH) || defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND) return mtd_store_list[0]; #else return mtd_store_list[dev]; @@ -53,27 +55,20 @@ int boot) { #ifndef CONFIG_DISCRETE_BOOTLOADER - if (!strcmp(part_name, BOOT_LOADER)) { + if (!strcmp(part_name, BOOT_LOADER)) return mtd_store_get(0); #else if (!strcmp(part_name, BOOT_BL2) || - !strcmp(part_name, BOOT_SPL)) { + !strcmp(part_name, BOOT_SPL) || + !strcmp(part_name, BAE_BB1ST)) return mtd_store_get(0); - } else if (!strcmp(part_name, BOOT_TPL) || - !strcmp(part_name, BOOT_FIP)) { - return mtd_store_get(1); #endif - } else if (boot) { - pr_info("%s %d invalid name: %s\n", - __func__, __LINE__, part_name); - return ERR_PTR(-ENXIO); - } return mtd_store_get(1); } void mtd_store_set(struct mtd_info *mtd, int dev) { -#if defined(CONFIG_SPI_FLASH) || defined(CONFIG_SPI_NAND) +#if defined(CONFIG_SPI_FLASH) || defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND) mtd_store_list[0] = mtd; #else mtd_store_list[dev] = mtd; @@ -442,53 +437,34 @@ } #endif -static int mtd_store_get_offset(const char *partname, - loff_t *retoff, loff_t off) +static int mtd_store_get_offset(const char *partname, loff_t *retoff, loff_t off) { int ret = 0; loff_t offset; #if defined(CONFIG_CMD_MTDPARTS) - u8 pnum; struct mtd_device *dev; struct part_info *part; + char tmp_part_name[20] = {0}; + u8 pnum; #endif + *retoff = 0; - if (!partname) { + if (!partname) offset = off; - } + #if defined(CONFIG_CMD_MTDPARTS) else if (!mtdparts_init()) { + strncpy(tmp_part_name, partname, strlen(partname)); #ifdef CONFIG_DISCRETE_BOOTLOADER if (!strcmp(partname, BOOT_BL2) || - !strcmp(partname, BOOT_SPL)) { - ret = find_dev_and_part(BOOT_LOADER, - &dev, - &pnum, - &part); - if (ret) - return ret; /* avoid operates null pointer */ - *retoff = part->offset + off; - return 0; - } - if (!strcmp(partname, BOOT_TPL) || - !strcmp(partname, BOOT_FIP)) { - ret = find_dev_and_part(BOOT_TPL, - &dev, - &pnum, - &part); - if (ret) - return ret; - *retoff = part->offset + off; - return 0; - } + !strcmp(partname, BOOT_SPL) || + !strcmp(partname, BAE_BB1ST)) + strncpy(tmp_part_name, BOOT_LOADER, strlen(BOOT_LOADER)); #endif - ret = find_dev_and_part(partname, - &dev, - &pnum, - &part); + ret = find_dev_and_part(tmp_part_name, &dev, &pnum, &part); if (ret) { pr_info("%s %d can not find part:%s\n", - __func__, __LINE__, partname); + __func__, __LINE__, tmp_part_name); ret = -EINVAL; } offset = part->offset + off; @@ -499,14 +475,17 @@ __func__, __LINE__); offset = off; } + if (!ret) *retoff = offset; + return ret; } extern int get_aml_mtdpart_count(void); static int mtd_store_count(void) { + mtdparts_init(); return get_aml_mtdpart_count(); } @@ -724,19 +703,24 @@ static u8 mtd_store_boot_copy_num(const char *part_name) { + cpu_id_t cpu_id = get_cpu_id(); + if (!part_name) { pr_info("%s %d invalid name!\n", __func__, __LINE__); return 0; } #ifdef CONFIG_DISCRETE_BOOTLOADER - if (!strcmp(part_name, BOOT_BL2) || - !strcmp(part_name, BOOT_SPL)) - return CONFIG_BL2_COPY_NUM; - if (!strcmp(part_name, BOOT_TPL) || - !strcmp(part_name, BOOT_FIP)) + !strcmp(part_name, BOOT_FIP) || + !strcmp(part_name, BOOT_DEVFIP)) return CONFIG_TPL_COPY_NUM; + else { + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) + return g_ssp.boot_bakups; + else + return CONFIG_BL2_COPY_NUM; + } #else if (!strcmp(part_name, BOOT_LOADER)) return boot_num_get(); @@ -770,27 +754,69 @@ return 0; } + +char *boot_entry_old[] = {BOOT_BL2, BOOT_TPL}; +char *boot_entry_sc2[] = {BOOT_BL2, BOOT_BL2E, BOOT_BL2X, BOOT_DDRFIP, BOOT_DEVFIP}; +static char **get_bootloader_entry(int *boot_count) +{ + cpu_id_t cpu_id = get_cpu_id(); + char **boot_entry = boot_entry_old; + + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { + *boot_count = 5; + boot_entry = boot_entry_sc2; + } + return boot_entry; + +} + static u64 mtd_store_boot_copy_size(const char *part_name) { + cpu_id_t cpu_id = get_cpu_id(); struct mtd_info *mtd = mtd_store_get(0); - int pages_per_copy = 0; - u64 size; + int pages_per_copy = 0, boot_count = 2 , i; + u64 size = 0; + char **boot_entry; if (!part_name) { - pr_info("%s %d invalid name!\n", - __func__, __LINE__); + pr_info("%s %d invalid name!\n", __func__, __LINE__); return 0; } #ifdef CONFIG_DISCRETE_BOOTLOADER if (!strcmp(part_name, BOOT_BL2) || - !strcmp(part_name, BOOT_SPL)) { - pages_per_copy = BOOT_TOTAL_PAGES / CONFIG_BL2_COPY_NUM; - return mtd->writesize * pages_per_copy; + !strcmp(part_name, BOOT_SPL) || + !strcmp(part_name, BAE_BB1ST)) { + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) + return g_ssp.boot_entry[BOOT_AREA_BB1ST].size; + else { + pages_per_copy = BOOT_TOTAL_PAGES / CONFIG_BL2_COPY_NUM; + return mtd->writesize * pages_per_copy; + } } else if (!strcmp(part_name, BOOT_TPL) || - !strcmp(part_name, BOOT_FIP)) { - return CONFIG_TPL_SIZE_PER_COPY; - } - return 0; + !strcmp(part_name, BOOT_FIP) || + !strcmp(part_name, BOOT_DEVFIP)) { + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) + return g_ssp.boot_entry[BOOT_AREA_DEVFIP].size; + else + return CONFIG_TPL_SIZE_PER_COPY; + } else if (!strcmp(part_name, BOOT_BL2E)) + return g_ssp.boot_entry[BOOT_AREA_BL2E].size; + else if (!strcmp(part_name, BOOT_BL2X)) + return g_ssp.boot_entry[BOOT_AREA_BL2X].size; + else if (!strcmp(part_name, BOOT_DDRFIP)) + return g_ssp.boot_entry[BOOT_AREA_DDRFIP].size; + else if (!strcmp(part_name, BOOT_LOADER)) { + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { + boot_entry = get_bootloader_entry(&boot_count); + for (i = 0; i < boot_count; i++, boot_entry++) + size += g_ssp.boot_entry[i].size; + } else + size = CONFIG_TPL_SIZE_PER_COPY + + (BOOT_TOTAL_PAGES / CONFIG_BL2_COPY_NUM)*mtd->writesize; + return size; + + } else + return 0; #else u8 num; @@ -801,7 +827,6 @@ return 0; pages_per_copy = BOOT_TOTAL_PAGES / num; - /* spinor using size from table */ if (mtd->writesize == 1) size = mtd_store_size(BOOT_LOADER); else @@ -825,7 +850,7 @@ __func__, __LINE__); return -ENXIO; } - mtd = mtd_store_get_by_name(part_name, 1);/*fixed me liuxj*/ + mtd = mtd_store_get_by_name(part_name, 1); if (IS_ERR(mtd)) return -ENXIO; ret = mtd_store_get_offset(part_name, &offset, 0); @@ -845,7 +870,7 @@ } offset += (cpy * size_per_copy); limit = offset + size_per_copy; -#if defined(CONFIG_SPI_NAND) +#if defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND) /** * TODO: * Need delete this part of code when we fix the @@ -927,10 +952,14 @@ size_per_copy = mtd_store_boot_copy_size(part_name); if (size_per_copy == 0) return -ENXIO; + + if (size > size_per_copy) + return -EINVAL; + if (cpy != BOOT_OPS_ALL) { if (cpy >= num) { pr_info("error: write cpy:0x%x >= num: 0x%x\ - please input again\n", + please input again\n", cpy, num); return -ENXIO; } @@ -943,7 +972,7 @@ pr_info("write %lx bytes to %llx\n", size, offset); limit = offset + size_per_copy; -#if defined(CONFIG_SPI_NAND) +#if defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND) /** * TODO: * 1.Need delete this part of code when we fix the @@ -954,7 +983,8 @@ * block skiped or not. */ if (!strcmp(part_name, BOOT_BL2) || - !strcmp(part_name, BOOT_SPL)) { + !strcmp(part_name, BOOT_SPL) || + !strcmp(part_name, BAE_BB1ST)) { int i, write_cnt; loff_t off = offset; size_t sz_write = SZ_2K; @@ -1030,8 +1060,14 @@ static int mtd_store_boot_erase(const char *part_name, u8 cpy) { - u8 num; +#ifdef CONFIG_DISCRETE_BOOTLOADER + cpu_id_t cpu_id = get_cpu_id(); + char *boot_entry_old[] = {"bl2", "tpl"}; + char *boot_entry_sc2[] = {"bl2", "bl2e", "bl2x", "ddrfip", "devfip"}; + char **boot_entry = boot_entry_old; + u8 num, i = 0, boot_entry_cnt = 2; int ret; +#endif if (!part_name) { pr_info("%s %d invalid name!\n", @@ -1039,6 +1075,10 @@ return 1; } #ifdef CONFIG_DISCRETE_BOOTLOADER + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { + boot_entry = boot_entry_sc2; + boot_entry_cnt = 5; + } if (!strcmp(part_name, BOOT_LOADER)) { num = CONFIG_BL2_COPY_NUM; if (num < CONFIG_TPL_COPY_NUM) @@ -1052,15 +1092,11 @@ CONFIG_TPL_COPY_NUM); return 1; } else { - //erase bl2 & tpl - part_name = BOOT_BL2; - ret = _mtd_store_boot_erase(part_name, cpy); - if (!ret) { - part_name = BOOT_TPL; - ret = _mtd_store_boot_erase(part_name, cpy); + for (i = 0; i < boot_entry_cnt; i++, boot_entry++) { + ret = _mtd_store_boot_erase(*boot_entry, cpy); + if (ret) + pr_info("boot partition erase failed\n"); } - if (ret) - pr_info("!!!BL2 & TPL partition erase failed\n"); } return ret; } @@ -1207,7 +1243,6 @@ return mtd_read(mtd, offset, length, &length, buf); } - static int nor_rsv_erase(const char *name) { struct mtd_info *mtd; @@ -1254,7 +1289,7 @@ if (ret) return ret; /* special path for erase */ - if (!strcmp(name, RSV_ENV)) { + if (!strcmp(name, RSV_ENV) || !strcmp(name, RSV_DTB) || !strcmp(name, RSV_KEY)) { erase.mtd = mtd; erase.addr = offset; erase.callback = NULL; @@ -1271,7 +1306,6 @@ return mtd_write(mtd, offset, length, &length, buf); } - static int nor_rsv_protect(const char *name, bool ops) { pr_info("spi nor flash not support this yet!\n");
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 8ecd8af..0cef1eb 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c
@@ -875,7 +875,6 @@ int get_aml_mtdpart_name(struct mtd_info *master, int idx, char *name) { - int i; struct part_info *temp; struct mtd_device *dentry; if (idx >= get_aml_mtdpart_count()) @@ -894,12 +893,11 @@ void list_aml_mtd_partitions(struct mtd_info *master) { - //struct mtd_info *slave, *next; struct mtd_info *slave; - int i; + int i = 0; list_for_each_entry(slave, &master->partitions, node) - printf("%2d: %-20s0x%08x\t0x%08x\n", + printf("%2d: %-20s0x%08llx\t0x%08llx\n", i++, slave->name, slave->size, slave->offset); return; } @@ -1062,7 +1060,7 @@ #ifdef CONFIG_MESON_NFC cnt = MAX_MTD_CNT; #endif -#if defined(CONFIG_SPI_FLASH) || defined(CONFIG_SPI_NAND) +#if defined(CONFIG_SPI_FLASH) || defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND) cnt = MAX_MTD_CNT - 1; #endif
diff --git a/drivers/mtd/nand/bbt.c b/drivers/mtd/nand/bbt.c index 7e0ad31..2d04edf 100644 --- a/drivers/mtd/nand/bbt.c +++ b/drivers/mtd/nand/bbt.c
@@ -10,6 +10,7 @@ #define pr_fmt(fmt) "nand-bbt: " fmt #include <linux/mtd/nand.h> +#include <linux/bitops.h> #ifndef __UBOOT__ #include <linux/slab.h> #endif
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 0b79369..8ed6e79 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c
@@ -7,13 +7,16 @@ * Peter Pan <peterpandong@micron.com> */ -#define pr_fmt(fmt) "nand: " fmt - +//#define pr_fmt(fmt) "nand: " fmt +#include <linux/bitops.h> #ifndef __UBOOT__ #include <linux/module.h> #endif #include <linux/mtd/nand.h> - +#ifdef CONFIG_MTD_SPI_NAND +#include <linux/mtd/spinand.h> +#include <amlogic/aml_rsv.h> +#endif /** * nanddev_isbad() - Check if a block is bad * @nand: NAND device @@ -23,6 +26,31 @@ */ bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) { +#ifdef CONFIG_MTD_SPI_NAND + struct spinand_device *spinand = nand_to_spinand(nand); + u8 bad_block; + + /* If bbt is already initialized, use the bbt of meson + * to manage bad blocks. + */ + if (spinand->bbt && !spinand->bbt_scan) { + bad_block = spinand->bbt[pos->eraseblock]; + if (bad_block != NAND_BLOCK_BAD && + bad_block != NAND_FACTORY_BAD && + bad_block != NAND_BLOCK_GOOD) { + pr_err("bad block table is mixed\n"); + return true; + } + + if (bad_block == NAND_BLOCK_GOOD) + return false; + + pr_err("meson %s bad block at 0x%x\n", + (bad_block == NAND_FACTORY_BAD) ? "factory" : "user", + pos->eraseblock*(u32)nanddev_eraseblock_size(nand)); + return true; + } +#endif if (nanddev_bbt_is_initialized(nand)) { unsigned int entry; int status; @@ -71,9 +99,39 @@ ret = nand->ops->markbad(nand, pos); if (ret) - pr_warn("failed to write BBM to block @%llx (err = %d)\n", + pr_err("failed to write BBM to block @%llx (err = %d)\n", nanddev_pos_to_offs(nand, pos), ret); +#ifdef CONFIG_MTD_SPI_NAND + extern int meson_rsv_bbt_write(u_char *source, size_t size); + struct spinand_device *spinand = nand_to_spinand(nand); + u8 bad_block; + u8 *buf = NULL; + + /* If bbt is already initialized, use the bbt of meson + * to manage bad blocks. + */ + if (spinand->bbt && !spinand->bbt_scan) { + bad_block = spinand->bbt[pos->eraseblock]; + if (bad_block != NAND_BLOCK_BAD && + bad_block != NAND_FACTORY_BAD && + bad_block != NAND_BLOCK_GOOD) { + pr_err("bad block table is mixed\n"); + return -EINVAL; + } + + if (bad_block == NAND_BLOCK_GOOD) { + buf = spinand->bbt; + buf[pos->eraseblock] = NAND_BLOCK_BAD; + meson_rsv_bbt_write((u_char *)buf, + spinand->rsv->bbt->size); + } + } else { + pr_err("meson bbt table is not initial"); + return -EINVAL; + } +#endif + if (!nanddev_bbt_is_initialized(nand)) goto out; @@ -106,6 +164,10 @@ unsigned int entry; int status; +#ifdef CONFIG_MTD_SPI_NAND + return false; +#endif + if (!nanddev_bbt_is_initialized(nand)) return false;
diff --git a/drivers/mtd/nand/raw/aml_nand/aml_hwctrl.h b/drivers/mtd/nand/raw/aml_nand/aml_hwctrl.h index 3547121..6d1ace7 100644 --- a/drivers/mtd/nand/raw/aml_nand/aml_hwctrl.h +++ b/drivers/mtd/nand/raw/aml_nand/aml_hwctrl.h
@@ -14,19 +14,6 @@ #define NAND_TWB_TIME_CYCLE 10 #define HHI_NAND_CLK_CNTL1 (0xff63c000 + (0x097 << 2)) -#define P_PAD_PULL_UP_EN_REG2 (volatile uint32_t *)(0xff634400 + (0x04a << 2)) -#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x0b7 << 2)) -#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x0b4 << 2)) -#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x0b0 << 2)) -#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x0b5 << 2)) -#define P_PAD_PULL_UP_EN_REG4 (volatile uint32_t *)(0xff634400 + (0x04c << 2)) -#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x0b1 << 2)) -#define P_PAD_PULL_UP_EN_REG0 (volatile uint32_t *)(0xff634400 + (0x048 << 2)) -#define P_PAD_PULL_UP_REG2 (volatile uint32_t *)(0xff634400 + (0x03c << 2)) -#define P_PAD_PULL_UP_REG4 (volatile uint32_t *)(0xff634400 + (0x03e << 2)) -#define P_PAD_PULL_UP_REG0 (volatile uint32_t *)(0xff634400 + (0x03a << 2)) - -#define CONFIG_AMLOGIC_DM_FLASH #define CE_PAD_DEFAULT \ ((AML_NAND_CE0) | \ @@ -39,19 +26,19 @@ /*** HW controller configuration ***/ struct hw_controller { -#ifdef CONFIG_AMLOGIC_DM_FLASH struct udevice *device; -#endif u32 chip_selected; u32 rb_received; u8 chip_num; u32 ce_enable[MAX_CHIP_NUM]; u32 rb_enable[MAX_CHIP_NUM]; - struct clk clk[4]; - + struct clk xtal; + struct clk fdiv2; + struct clk mux; + struct clk div; + struct clk gate; void __iomem *reg_base; void __iomem *nand_clk_reg; - void __iomem *nand_clk_reg1; u32 irq; }; @@ -537,4 +524,4 @@ #define NAND_BCH50_1K_ECC_SIZE 88 #define NAND_BCH60_1K_ECC_SIZE 106 -#endif /* __HW_CTRL_H__ */ \ No newline at end of file +#endif /* __HW_CTRL_H__ */
diff --git a/drivers/mtd/nand/raw/aml_nand/aml_nand.c b/drivers/mtd/nand/raw/aml_nand/aml_nand.c index b3b4fa4..0bc2eeb 100644 --- a/drivers/mtd/nand/raw/aml_nand/aml_nand.c +++ b/drivers/mtd/nand/raw/aml_nand/aml_nand.c
@@ -10,7 +10,7 @@ #include <malloc.h> #include <linux/err.h> #include <asm/cache.h> -//#include <asm/arch/secure_apb.h> +#include <amlogic/storage.h> #include <amlogic/cpu_id.h> #include <linux/log2.h> #include <dm/pinctrl.h> @@ -20,14 +20,8 @@ #include "aml_nand.h" #include <time.h> /*test*/ -#if 0 -#define aml_nand_debug(a...) \ - { printk("%s()[%s,%d]",__func__,__FILE__,__LINE__); printk(a); } -#else #define aml_nand_debug(a...) -#endif -//extern int aml_nand_scan_bbt(struct mtd_info *mtd); extern int aml_nand_scan_shipped_bbt(struct mtd_info *mtd); uint8_t nand_boot_flag = 0; @@ -41,62 +35,6 @@ #define SZ_1M 0x100000 extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; -/* -* mtd nand partition table, only care the size! -* offset will be calculated by nand driver. -*/ -static struct mtd_partition normal_partition_info[] = { -#ifdef CONFIG_DISCRETE_BOOTLOADER -/* MUST NOT CHANGE this part unless u know what you are doing! -* inherent parition for descrete bootloader to store fip -* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM -* name must be same with TPL_PART_NAME -*/ -{ - .name = "tpl", - .offset = 0, - .size = 0, -}, -#endif -{ - .name = "logo", - .offset = 0, - .size = 2*SZ_1M, -}, -{ - .name = "recovery", - .offset = 0, - .size = 16*SZ_1M, -}, -{ - .name = "boot", - .offset = 0, - .size = 16*SZ_1M, -}, -{ - .name = "system", - .offset = 0, - .size = 64*SZ_1M, -}, -/* last partition get the rest capacity */ -{ - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, -}, -}; - -struct mtd_partition *get_aml_mtd_partition(void) -{ - return normal_partition_info; -} - -int get_aml_partition_count(void) -{ - return ARRAY_SIZE(normal_partition_info); -} - - static struct nand_ecclayout aml_nand_uboot_oob = { .eccbytes = 84, .oobfree = { @@ -229,12 +167,15 @@ return 0; } -/****get partition table****/ +extern struct mtd_partition *get_aml_mtd_partition(void); +extern int get_aml_partition_count(void); +extern struct storage_startup_parameter g_ssp; static int aml_nand_add_partition(struct aml_nand_chip *aml_chip) { struct nand_chip *chip = &aml_chip->chip; struct mtd_info *mtd = &chip->mtd; struct aml_nand_platform *plat = aml_chip->platform; + cpu_id_t cpu_id = get_cpu_id(); #ifdef CONFIG_MTD_PARTITIONS struct mtd_partition *temp_parts = NULL; struct mtd_partition *parts; @@ -243,17 +184,14 @@ uint64_t part_size = 0; int reserved_part_blk_num = NAND_RSV_BLOCK_NUM; uint64_t fip_part_size = 0; - int normal_base = 0; #ifndef CONFIG_NOT_SKIP_BAD_BLOCK - int phys_erase_shift, error = 0; + int phys_erase_shift, error = 0, internal_part_count = 0; uint64_t start_blk = 0, part_blk = 0; loff_t offset; phys_erase_shift = fls(mtd->erasesize) - 1; #endif - - if (!strncmp((char*)plat->name, - NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) {\ + if (!strncmp((char*)plat->name, NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) { /* boot partition must be set as this because of romboot restrict */ parts = kzalloc(sizeof(struct mtd_partition), GFP_KERNEL); @@ -263,42 +201,34 @@ parts->offset = 0; parts->size = (mtd->writesize * 1024); nr = 1; - nand_boot_flag = 1; } else { /* normal partitions */ parts = get_aml_mtd_partition(); nr = get_aml_partition_count(); - if (nand_boot_flag) - adjust_offset = - (1024 * mtd->writesize / aml_chip->plane_num); - #ifdef CONFIG_DISCRETE_BOOTLOADER - /* reserved area size is fixed 48 blocks and - * have fip between rsv and normal, so - * don't skip factory bad block and set fip part size. - */ - fip_part_size = CONFIG_TPL_SIZE_PER_COPY * CONFIG_TPL_COPY_NUM; - /* TODO: add fip 2 partition list */ - temp_parts = parts; - if (strcmp(BOOT_TPL, temp_parts->name)) { - printf("nand: double check your mtd partition table!\n"); - printf("%s should be the 1st part!, temp_parts->name:%s\n", BOOT_TPL, temp_parts->name); - return -ENODEV; + adjust_offset = 1024 * mtd->writesize + reserved_part_blk_num * mtd->erasesize; +#ifdef CONFIG_DISCRETE_BOOTLOADER + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { + fip_part_size = g_ssp.boot_entry[BOOT_AREA_DEVFIP].size * CONFIG_TPL_COPY_NUM; + adjust_offset = g_ssp.boot_entry[BOOT_AREA_DEVFIP].offset + fip_part_size; + internal_part_count = 4; + } else { + fip_part_size = CONFIG_TPL_SIZE_PER_COPY * CONFIG_TPL_COPY_NUM; + internal_part_count = 1; } - if (temp_parts->size) { - printf("nand: size of %s should not be pre-set\n", - temp_parts->name); - printf("it's should be determined by TPL_COPY_NUM*TPL_SIZE_PER_COPY\n"); - printf("which is %lld\n", fip_part_size); + + for (i = 0; i < internal_part_count; i++) { + temp_parts = parts + i; + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { + temp_parts->offset = g_ssp.boot_entry[i + 1].offset; + temp_parts->size = g_ssp.boot_entry[i + 1].size * g_ssp.boot_bakups; + } else { + temp_parts->offset = adjust_offset; + temp_parts->size = fip_part_size; + adjust_offset += fip_part_size; + } } - temp_parts->offset = adjust_offset + reserved_part_blk_num * mtd->erasesize; - temp_parts->size = fip_part_size; - printf("%s : off %lld, size %lld\n", temp_parts->name, - temp_parts->offset, temp_parts->size); - normal_base = 1; - #endif /* CONFIG_DISCRETE_BOOTLOADER */ - adjust_offset += reserved_part_blk_num * mtd->erasesize - + fip_part_size; - for (i = normal_base; i < nr; i++) { +#endif + for (i = internal_part_count; i < nr; i++) { temp_parts = parts + i; if (mtd->size < adjust_offset) { printf("%s %d error : over the nand size!!!\n", @@ -309,7 +239,7 @@ part_size = temp_parts->size; if (i == nr - 1) part_size = mtd->size - adjust_offset; - #ifndef CONFIG_NOT_SKIP_BAD_BLOCK +#ifndef CONFIG_NOT_SKIP_BAD_BLOCK offset = 0; start_blk = 0; part_blk = part_size >> phys_erase_shift; @@ -317,14 +247,11 @@ do { offset = adjust_offset + start_blk * mtd->erasesize; - error = mtd->_block_isbad(mtd, offset); - if (error) { pr_info("%s:%d factory bad addr=%llx\n", - __func__, __LINE__, - (uint64_t)(offset >> - phys_erase_shift)); + __func__, __LINE__, + (uint64_t)(offset >> phys_erase_shift)); if (i != nr - 1) { adjust_offset += mtd->erasesize; continue; @@ -332,15 +259,12 @@ } start_blk++; } while (start_blk < part_blk); - #endif +#endif if (temp_parts->name == NULL) { - temp_parts->name = - kzalloc(MAX_MTD_PART_NAME_LEN, - GFP_KERNEL); + temp_parts->name = kzalloc(MAX_MTD_PART_NAME_LEN, GFP_KERNEL); if (!temp_parts->name) return -ENOMEM; - sprintf((char *)temp_parts->name, - "mtd%d", nr); + sprintf((char *)temp_parts->name, "mtd%d", nr); } adjust_offset += part_size; temp_parts->size = adjust_offset - temp_parts->offset; @@ -355,6 +279,7 @@ #endif } +/* void nand_get_chip(void *chip) { @@ -368,7 +293,7 @@ } return; } - +*/ static void inline nand_release_chip(void) { @@ -386,7 +311,7 @@ nand_release_chip(); break; case 0: - nand_get_chip(aml_chip); + //nand_get_chip(aml_chip); aml_chip->aml_nand_select_chip(aml_chip, chipnr); break; case 1: @@ -1711,9 +1636,6 @@ struct nand_oobfree *oobfree = NULL; cpu_id_t cpu_id = get_cpu_id(); - chip->IO_ADDR_R = chip->IO_ADDR_W = - (void __iomem *)((volatile u32 *)(NAND_BASE_APB + P_NAND_BUF)); - chip->ecc.layout = &aml_nand_oob_64; chip->select_chip = aml_nand_select_chip; chip->cmd_ctrl = aml_nand_cmd_ctrl; @@ -1731,21 +1653,21 @@ /*use NO RB mode to detect nand chip num*/ aml_chip->ops_mode |= AML_CHIP_NONE_RB; chip->chip_delay = 100; - aml_chip->aml_nand_hw_init(aml_chip); aml_chip->toggle_mode =0; aml_chip->bch_info = NAND_ECC_BCH60_1K; if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD)|| - (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1)) + (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) || + (cpu_id.family_id == MESON_CPU_MAJOR_ID_C2)) aml_chip->bch_info = NAND_ECC_BCH8_1K; chip->options = 0; chip->options |= NAND_SKIP_BBTSCAN; chip->options |= NAND_NO_SUBPAGE_WRITE; + err = aml_nand_scan(mtd, controller->chip_num); if (err || (pre_scan->pre_scan_flag)) { - err = -ENXIO; goto exit_error; } @@ -1864,7 +1786,6 @@ for (i = 0; oobfree[i].length && i < ARRAY_SIZE(oobfree); i++) chip->ecc.layout->oobavail += oobfree[i].length; printk("oob avail size %d\n", chip->ecc.layout->oobavail); - mtd->oobavail = chip->ecc.layout->oobavail; mtd->ecclayout = chip->ecc.layout; @@ -1938,6 +1859,7 @@ meson_rsv_check(aml_chip->rsv->key); meson_rsv_check(aml_chip->rsv->dtb); } + if (aml_nand_add_partition(aml_chip) != 0) { err = -ENXIO; goto exit_error; @@ -2017,7 +1939,9 @@ else break; } else { - if (aml_chip->mfr_type == NAND_MFR_SANDISK) { + if ((aml_chip->mfr_type == NAND_MFR_SANDISK) || + (aml_chip->mfr_type == 0xc8) || + (aml_chip->mfr_type == 0xc2)) { addr = offset + read_cnt*mtd->writesize; } else addr = offset + @@ -2128,8 +2052,9 @@ //printk("col0_oob =%x\n",col0_oob); } - if ((aml_chip->mfr_type == 0xC8 )) { - if ((col0_oob != 0xFF) || (col0_data != 0xFF)) { + if ((aml_chip->mfr_type == 0xC8 ) || + (aml_chip->mfr_type == 0xC2)) { + if (col0_oob != 0xFF) { printk("detect factory Bad block:%llx blk:%d chip:%d\n", (uint64_t)addr, start_blk, i); bad_blk_cnt++; @@ -2153,15 +2078,6 @@ if (col0_oob != 0xFF) { printk("%s:%d factory ship bbt found\n", __func__, __LINE__); - if (aml_chip->mfr_type == 0xc2 ) { - if (col0_oob != 0xFF) { - printk("detect factory Bad block:%llx blk=%d chip=%d\n", - (uint64_t)addr, start_blk, i); - bad_blk_cnt++; - aml_chip->block_status[start_blk] = NAND_FACTORY_BAD; - break; - } - } if (aml_chip->mfr_type == NAND_MFR_DOSILICON || aml_chip->mfr_type == NAND_MFR_ATO ||
diff --git a/drivers/mtd/nand/raw/aml_nand/aml_nand.h b/drivers/mtd/nand/raw/aml_nand/aml_nand.h index 0261f30..abf6575 100644 --- a/drivers/mtd/nand/raw/aml_nand/aml_nand.h +++ b/drivers/mtd/nand/raw/aml_nand/aml_nand.h
@@ -19,9 +19,6 @@ #include <amlogic/aml_mtd.h> #define NAND_MAX_DEVICE 4 - -#define CONFIG_MTD_PARTITIONS 1 - /*MAX page list cnt for usrdef mode*/ #define NAND_PAGELIST_CNT 16 @@ -44,35 +41,41 @@ u8 nand_ran_mode; }; -/**must same with arch/arm/include/asm/nand.h -*ext bits: -* bit 26: pagelist enable flag, -* bit 24: a2 cmd enable flag, -* bit 23: no_rb, -* bit 22: large. large for what? -* bit 19: randomizer mode. -* bit 14-16: ecc mode -* bit 13: short mode -* bit 6-12: short page size -* bit 0-5: ecc pages. -***/ +union sc2_cmdinfo { + uint32_t d32; + struct { + unsigned cmd:22; //20-21b' code0/1 17b' WE_n(r/w->1/0b) + unsigned page_list:1; + unsigned reserved:1; + unsigned new_type:8; + } b; +}; + +typedef struct nand_setup_sc2 { + union sc2_cmdinfo cfg; + uint16_t id; + uint16_t max; // id:0x100 user, max:0 disable. +} nand_setup_sc2_t; + +union cmdinfo { + uint32_t d32; + struct { + unsigned cmd:22; + unsigned large_page:1; // 22 + unsigned no_rb:1; // 23 from efuse + unsigned a2:1; // 24 + unsigned reserved25:1; // 25 + unsigned page_list:1; // 26 + unsigned sync_mode:2; // 27 from efuse + unsigned size:2; // 29 from efuse + unsigned active:1; // 31 + } b; +}; + typedef struct nand_setup { - union { - uint32_t d32; - struct { - unsigned cmd:22; - unsigned large_page:1; //22 - unsigned no_rb:1; //23 from efuse - unsigned a2:1; //24 - unsigned reserved25:1; //25 - unsigned page_list:1; //26 - unsigned sync_mode:2; //27 from efuse - unsigned size:2; //29 from efuse - unsigned active:1; //31 - }b; - }cfg; - uint16_t id; - uint16_t max; //id:0x100 user,max:0 disable. + union cmdinfo cfg; + uint16_t id; + uint16_t max; // id:0x100 user, max:0 disable. } nand_setup_t; typedef struct _ext_info{ @@ -99,22 +102,27 @@ * partitions,please enable this macro. * #define CONFIG_NOT_SKIP_BAD_BLOCK */ - typedef struct _fip_info { uint16_t version; //version uint16_t mode; //compact or discrete uint32_t fip_start; //fip start,pages }fip_info_t; - typedef struct _nand_page0 { - nand_setup_t nand_setup; //8 - unsigned char page_list[16]; //16 - nand_cmd_t retry_usr[32]; //64(32 cmd max I/F) - ext_info_t ext_info; //72 - /*added for slc nand in mtd drivers 20170503*/ - fip_info_t fip_info; - }nand_page0_t; //384 byte max. +typedef struct _nand_page0_sc2 { + nand_setup_sc2_t nand_setup; + unsigned char page_list[32]; + nand_cmd_t retry_usr[32]; + ext_info_t ext_info; + fip_info_t fip_info; +} nand_page0_sc2_t; + typedef struct _nand_page0 { + nand_setup_t nand_setup; + unsigned char page_list[16]; + nand_cmd_t retry_usr[32]; + ext_info_t ext_info; + fip_info_t fip_info; + }nand_page0_t; typedef union nand_core_clk { /*raw register data*/
diff --git a/drivers/mtd/nand/raw/aml_nand/boot.c b/drivers/mtd/nand/raw/aml_nand/boot.c index 2109a4f..5cc44b7 100644 --- a/drivers/mtd/nand/raw/aml_nand/boot.c +++ b/drivers/mtd/nand/raw/aml_nand/boot.c
@@ -83,11 +83,13 @@ struct nand_chip *chip = &aml_chip->chip; struct mtd_info *mtd = &chip->mtd; struct aml_nand_chip *aml_chip_normal = mtd_to_nand_chip(nand_info[1]); - int nand_read_info; u32 configure_data; nand_page0_t *p_nand_page0 = NULL; + nand_page0_sc2_t *p_nand_page0_sc2 = NULL; ext_info_t *p_ext_info = NULL; nand_setup_t *p_nand_setup = NULL; + nand_setup_sc2_t * p_nand_setup_sc2 = NULL; + cpu_id_t cpu_id = get_cpu_id(); int each_boot_pages, boot_num, bbt_pages; unsigned int pages_per_blk_shift ,bbt_size; #ifdef CONFIG_DISCRETE_BOOTLOADER @@ -98,14 +100,11 @@ bbt_size = aml_chip_normal->rsv->bbt->size; #ifdef CONFIG_DISCRETE_BOOTLOADER boot_num = CONFIG_TPL_COPY_NUM; - /* fip size */ each_boot_pages = CONFIG_TPL_SIZE_PER_COPY / mtd->writesize; #else - /* fixme, boot number self-adapt but not macro */ boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num; each_boot_pages = BOOT_TOTAL_PAGES / boot_num; -#endif /* CONFIG_DISCRETE_BOOTLOADER */ - +#endif p_nand_page0 = (nand_page0_t *) page0_buf; p_nand_setup = &p_nand_page0->nand_setup; p_ext_info = &p_nand_page0->ext_info; @@ -115,29 +114,25 @@ chip->ecc.steps); memset(p_nand_page0, 0x0, sizeof(nand_page0_t)); - /* info_cfg->ext = (configure_data | (1<<23) |(1<<22) | (2<<20)); */ - /*p_nand_setup->cfg.d32 = (configure_data|(1<<23) | (1<<22) | (2<<20) | (1<<19));*/ - /* randomizer mode depends on chip's config */ - p_nand_setup->cfg.d32 = (configure_data|(1<<23) | (1<<22) | (2<<20)); - printk("cfg.d32 0x%x\n", p_nand_setup->cfg.d32); - /* need finish here for romboot retry */ - p_nand_setup->id = 0; - p_nand_setup->max = 0; - - /*fixme, alreay memset 0 */ - memset(p_nand_page0->page_list, - 0, - NAND_PAGELIST_CNT); - - /* chip_num occupy the lowest 2 bit */ - nand_read_info = controller->chip_num; - - p_ext_info->read_info = nand_read_info; + if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) { + p_nand_page0_sc2 = (nand_page0_sc2_t *) page0_buf; + p_nand_setup_sc2 = &p_nand_page0_sc2->nand_setup; + p_ext_info = &p_nand_page0_sc2->ext_info; + p_nand_setup_sc2->cfg.d32 = configure_data; + p_nand_setup_sc2->cfg.b.page_list = 0; + p_nand_setup_sc2->cfg.b.new_type = 0; + p_fip_info = &p_nand_page0_sc2->fip_info; + printk("sc2 cfg.d32 0x%x\n", p_nand_setup_sc2->cfg.d32); + } else { + p_nand_page0 = (nand_page0_t *) page0_buf; + p_nand_setup = &p_nand_page0->nand_setup; + p_ext_info = &p_nand_page0->ext_info; + p_nand_setup->cfg.d32 = (configure_data | (1<<23) | (1<<22) | (2<<20)); + memset(p_nand_page0->page_list, 0, NAND_PAGELIST_CNT); + p_fip_info = &p_nand_page0->fip_info; + printk("cfg.d32 0x%x\n", p_nand_setup->cfg.d32); + } p_ext_info->page_per_blk = aml_chip->block_size / aml_chip->page_size; - /* fixme, only ce0 is enabled! */ - p_ext_info->ce_mask = 0x01; - /* xlc is not in using for now */ - p_ext_info->xlc = 1; p_ext_info->boot_num = boot_num; p_ext_info->each_boot_pages = each_boot_pages; bbt_pages = @@ -146,7 +141,6 @@ p_ext_info->bbt_start_block = (BOOT_TOTAL_PAGES >> pages_per_blk_shift) + NAND_GAP_BLOCK_NUM; #ifdef CONFIG_DISCRETE_BOOTLOADER - p_fip_info = &p_nand_page0->fip_info; p_fip_info->version = 1; p_fip_info->mode = NAND_FIPMODE_DISCRETE; /* in pages, fixme, should it stored in amlchip? */
diff --git a/drivers/mtd/nand/raw/aml_nand/meson_nand.c b/drivers/mtd/nand/raw/aml_nand/meson_nand.c index 1fe8af7..846764b 100644 --- a/drivers/mtd/nand/raw/aml_nand/meson_nand.c +++ b/drivers/mtd/nand/raw/aml_nand/meson_nand.c
@@ -26,7 +26,6 @@ #include <linux/io.h> #include <asm/gpio.h> #include <asm/arch/clock.h> -#include <dt-bindings/clock/g12-clkc.h> #include <clk.h> #include <dm/pinctrl.h> #include <asm/arch/register.h> @@ -222,88 +221,71 @@ void aml_nfc_get_clk_name(struct hw_controller *controller) { - static struct udevice *clk_udevice; - unsigned int rate; - clk_get_by_name(controller->device, "clkin", &controller->clk[0]); - rate = clk_get_rate(&controller->clk[0]); - clk_get_by_name(controller->device, "clkin1", &controller->clk[1]); - clk_get_by_name(controller->device, "clkin2", &controller->clk[2]); - clk_get_by_name(controller->device, "clkin3", &controller->clk[3]); + struct udevice *clk_udevice, *dev = controller->device; + + uclass_get_device_by_name(UCLASS_CLK, "amlogic,g12a-clkc", &clk_udevice); + + clk_get_by_name(dev, "fdiv2", &controller->fdiv2); + clk_get_by_name(dev, "xtal", &controller->xtal); + clk_get_by_name(dev, "mux", &controller->mux); + clk_get_by_name(dev, "div", &controller->div); + clk_get_by_name(dev, "gate", &controller->gate); + + clk_enable(&controller->gate); } void get_sys_clk_rate_mtd(struct hw_controller *controller, int *rate) { - unsigned int clk; - int clk_freq = *rate; - cpu_id_t cpu_id = get_cpu_id(); - unsigned int always_on = 0x1 << 24; - /* fixme, axg clock may be the same setting with gxl/gxm */ - if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) || - (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD) || - (cpu_id.family_id >= MESON_CPU_MAJOR_ID_G12A)) - always_on = 0x1 << 28; + int bus_cycle, bus_timing; + unsigned int clk, clk_div, clk_src; + int clk_freq = *rate * 1000000; + unsigned int always_on = 0x1 << 28; - printk("%s() %d, clock setting %d!\n", - __func__, __LINE__, clk_freq); - - if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_GXBB) || - (cpu_id.family_id == MESON_CPU_MAJOR_ID_GXL) || - (cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) || - (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD) || - (cpu_id.family_id >= MESON_CPU_MAJOR_ID_G12A)) { - - switch (clk_freq) { - case 24: - clk = 0x80000201; - break; - case 112: - clk = 0x80000249; - break; - case 200: - clk = 0x80000245; - break; - case 250: - clk = 0x80000244; - break; - default: - clk = 0x80000245; - break; - } - clk |= always_on; - amlnf_write_reg32(controller->nand_clk_reg, clk); - return; + if (clk_freq <= 24) { + clk = 24000000; + clk_src = 0; + clk_enable(&controller->xtal); // for c1 clk arthitecture compatitable. xtal was not controlled by clk driver. + clk_set_rate(&controller->div, clk); + clk_div = 1; + bus_cycle = 4; + bus_timing = 3; + goto __NAND_CLK_CFG__; } else { - BUG(); + clk = 1000000000; + clk_src = 1; + clk_disable(&controller->xtal); + clk_set_parent(&controller->mux, &controller->fdiv2); + clk_set_rate(&controller->div, clk); + bus_cycle = 6; + bus_timing = bus_cycle + 1; } - return; + clk_div = clk /clk_freq; + if (clk % clk_freq) + clk_div++; +__NAND_CLK_CFG__: + AMLNF_WRITE_REG(controller->nand_clk_reg, + (clk_src << 6) | clk_div | always_on | (1 << 31) | (2 << 8)); + printf("%s:gclock=%x\n", __func__, + AMLNF_READ_REG(controller->nand_clk_reg)); + NFC_SET_CFG(controller, 0); + NFC_SET_TIMING_ASYC(controller, bus_timing, (bus_cycle - 1)); + NFC_SEND_CMD(controller, 1<<31); + printf("%s:P_NAND_CFG=%x\n", __func__, + AMLNF_READ_REG(controller->reg_base + P_NAND_CFG)); } static void m3_nand_hw_init(struct aml_nand_chip *aml_chip) { - int bus_cycle, bus_timing; int sys_clk_rate = 200; - clk_set_parent(&controller->clk[1], &controller->clk[0]); - clk_set_rate(&controller->clk[2], sys_clk_rate*1000000); - clk_enable(&controller->clk[3]); get_sys_clk_rate_mtd(controller, &sys_clk_rate); - bus_cycle = 6; - bus_timing = bus_cycle + 1; - - NFC_SET_CFG(controller, 0); - NFC_SET_TIMING_ASYC(controller, bus_timing, (bus_cycle - 1)); - NFC_SEND_CMD(controller, 1<<31); - - printf("%s:gclock=%x\n", __func__, AMLNF_READ_REG(controller->nand_clk_reg)); - printf("%s:P_NAND_CFG=%x\n", __func__, AMLNF_READ_REG(controller->reg_base + P_NAND_CFG)); - return; } static void m3_nand_adjust_timing(struct aml_nand_chip *aml_chip) { - int sys_clk_rate, bus_cycle, bus_timing; + int sys_clk_rate; if (!aml_chip->T_REA) aml_chip->T_REA = 20; @@ -317,19 +299,7 @@ else sys_clk_rate = 250; - clk_set_parent(&controller->clk[1], &controller->clk[0]); - clk_set_rate(&controller->clk[2], sys_clk_rate*1000000); - clk_enable(&controller->clk[3]); get_sys_clk_rate_mtd(controller, &sys_clk_rate); - - bus_cycle = 6; - bus_timing = bus_cycle + 1; - NFC_SET_CFG(controller , 0); - NFC_SET_TIMING_ASYC(controller, bus_timing, (bus_cycle - 1)); - NFC_SEND_CMD(controller, 1<<31); - - printf("%s:gclock=%x\n", __func__, AMLNF_READ_REG(controller->nand_clk_reg)); - printf("%s:P_NAND_CFG=%x\n", __func__, AMLNF_READ_REG(controller->reg_base + P_NAND_CFG)); } static int m3_nand_options_confirm(struct aml_nand_chip *aml_chip) @@ -344,9 +314,6 @@ int error = 0, i, valid_chip_num = 0; cpu_id_t cpu_id = get_cpu_id(); - /****bootloader only support short mode - **ecc_supports[8] is short mode ecc - ***/ if (!strncmp((char*)plat->name, NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) { @@ -402,7 +369,8 @@ if ((mtd->writesize <= 2048) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD)|| - (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1)) + (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) || + (cpu_id.family_id == MESON_CPU_MAJOR_ID_C2)) options_support = NAND_ECC_BCH8_MODE; switch (options_support) { @@ -754,6 +722,7 @@ aml_nand_block_bad_scrub_update_bbt; } +extern int slcnand_fit_storage(void); static int m3_nand_probe(struct aml_nand_platform *plat, unsigned dev_num) { struct aml_nand_chip *aml_chip = NULL; @@ -762,12 +731,6 @@ int err = 0, i, array_length; struct nand_oobfree *oobfree; - if (!plat) { - printk("no platform specific information\n"); - goto exit_error; - } - - printf("%s %d\n", __func__, __LINE__); aml_chip = kzalloc(sizeof(*aml_chip), GFP_KERNEL); if (aml_chip == NULL) { printk("no memory for flash info\n"); @@ -775,13 +738,6 @@ goto exit_error; } - plat->nand_flash_dev = kzalloc(sizeof(struct aml_nand_flash_dev), GFP_KERNEL); - if (plat->nand_flash_dev == NULL) { - printk("no memory for plat->nand_flash_dev\n"); - err = -ENOMEM; - goto exit_error; - } - /* initialize mtd info data struct */ aml_chip->controller = controller; aml_chip->platform = plat; @@ -789,7 +745,7 @@ aml_chip->max_bch_mode = sizeof(m3_bch_list) / sizeof(m3_bch_list[0]); chip = &aml_chip->chip; - chip->priv = aml_chip; //chip->priv = &aml_chip->mtd; + chip->priv = aml_chip; mtd = &chip->mtd; mtd->priv = chip; plat->aml_chip = aml_chip; @@ -798,10 +754,16 @@ register_aml_chip_contorller(aml_chip); aml_chip->ran_mode = plat->ran_mode; aml_chip->rbpin_detect = plat->rbpin_detect; - aml_nfc_get_clk_name(controller); + chip->IO_ADDR_R = chip->IO_ADDR_W = + (void __iomem *)((volatile u32 *)(NAND_BASE_APB + P_NAND_BUF)); err = aml_nand_init(aml_chip); + if (!err) { + nand_info[dev_num] = mtd; + mtd_store_set(nand_info[dev_num], dev_num); + slcnand_fit_storage(); + } if (err || pre_scan->pre_scan_flag) goto exit_error; @@ -823,17 +785,11 @@ mtd->ecclayout = chip->ecc.layout; } - nand_info[dev_num] = mtd; - printf("%s, %d, mtd: %p, dev_num: 0x%x\n", __func__, __LINE__, mtd, dev_num); - mtd_store_set(nand_info[dev_num], dev_num);/*need fix*/ - printf("mtd name: %s\n", mtd->name);/*nand name*/ return 0; exit_error: if (aml_chip) kfree(aml_chip); - if (plat->nand_flash_dev) - kfree(plat->nand_flash_dev); mtd->name = NULL; return err; } @@ -842,11 +798,6 @@ { struct aml_nand_chip *aml_chip = NULL; - if (!plat) { - printf("no platform specific information\n"); - return; - } - aml_chip = plat->aml_chip; aml_chip->aml_nand_hw_init(aml_chip); @@ -855,8 +806,6 @@ aml_chip->aml_nand_select_chip(aml_chip, 0); } - -#ifdef CONFIG_AMLOGIC_DM_FLASH static void meson_nfc_init_dm(void) { struct udevice *dev; @@ -865,42 +814,22 @@ dev; uclass_next_device(&dev)); } -#endif - -/******liuxj nand init-->DM(probe)*****/ -/**fixed me after use DM***/ void board_nand_init(void) { -#ifdef CONFIG_AMLOGIC_DM_FLASH meson_nfc_init_dm(); -#endif } -#ifdef CONFIG_AML_STORAGE - extern int slcnand_fit_storage(void); -#endif - int amlmtd_init = 0; -#ifdef CONFIG_AMLOGIC_DM_FLASH extern struct udevice *nand_dev; int meson_nfc_probe(struct udevice *dev) { - struct mtd_info *mtd; - struct aml_nand_platform *plat = NULL; const void *blob = gd->fdt_blob; - nand_dev = dev; fdt_addr_t regs, clk_regs; int node; int i, ret = 0; -#ifdef clk_tree_test - static struct udevice *clk_udvice; - struct clk w_clk; - struct clk p_clk; - unsigned int rate; -#endif - printf("%s %d\n", __func__, __LINE__); + if (1 == amlmtd_init) { ret = pinctrl_select_state(controller->device, "default"); if (ret) { @@ -911,17 +840,18 @@ return 0; } - mtd = dev_get_uclass_priv(dev); - mtd->name = (char *)dev->name; - mtd->dev = dev; - controller = kzalloc(sizeof(struct hw_controller), GFP_KERNEL); if (controller == NULL) { printk("%s kzalloc controller failed\n", __func__); return 1; } + nand_dev = dev; + controller->device = dev; - controller->device = mtd->dev; + ret = pinctrl_select_state(controller->device, "default"); + if (ret) { + printf("ERROR get pinmux failed\n"); + } controller->chip_num = 1; /* assume chip num is 1 */ for (i = 0; i < MAX_CHIP_NUM; i++) { @@ -936,7 +866,6 @@ printk("unable to find nfc node in device tree\n"); return 1; } - if (!fdtdec_get_is_enabled(blob, node)) { printk("nfc disabled in device tree\n"); return 1; @@ -947,17 +876,7 @@ printk("unabled to find nfc address in device tree\n"); return 1; } - - printk("___regs :0x%llx", regs); controller->reg_base = (void *)regs; - printk("nand register base =%p\n", controller->reg_base); - -#ifdef clk_tree_test - uclass_get_device_by_name(UCLASS_CLK, "amlogic,g12a-clkc", &clk_udvice); - clk_get_by_name(dev, "clkin", &p_clk); - rate = clk_get_rate(&p_clk); - printf("fclk rate: %d\n", rate); -#endif clk_regs = fdtdec_get_addr(blob, node, "clk_reg"); if (clk_regs == FDT_ADDR_T_NONE) { @@ -966,9 +885,6 @@ } controller->nand_clk_reg = (void *)clk_regs; - printk("nand clk register base =%p,value:0x%x\n", controller->nand_clk_reg, - readl(controller->nand_clk_reg)); - for (i=0; i<aml_nand_mid_device.dev_num; i++) { plat = &aml_nand_mid_device.aml_nand_platform[i]; if (!plat) { @@ -977,22 +893,17 @@ } ret = m3_nand_probe(plat, i); - if (pre_scan->pre_scan_flag && !i) { //Get the flash id as fastest as possible + if (pre_scan->pre_scan_flag && !i) { free(controller); return 0; } if (ret) printk("nand init failed: %d\n", ret); } - nand_curr_device = 1; //fixit amlmtd_init = 1; if (ret) free(controller); -#ifdef CONFIG_AML_STORAGE - else - slcnand_fit_storage(); -#endif return 0; } @@ -1008,5 +919,4 @@ .of_match = aml_nfc_ids, .probe = meson_nfc_probe, }; -#endif /* CONFIG_AMLOGIC_DM_FLASH */
diff --git a/drivers/mtd/nand/raw/aml_nand/nand_flash.c b/drivers/mtd/nand/raw/aml_nand/nand_flash.c index d99bc4f..e6786f3 100644 --- a/drivers/mtd/nand/raw/aml_nand/nand_flash.c +++ b/drivers/mtd/nand/raw/aml_nand/nand_flash.c
@@ -442,6 +442,18 @@ 0, (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )}, + {"Slc NAND 4Gib MX30LF4G28AD ", + {NAND_MFR_MACRONIX, 0xdc, 0x90, 0xA2, 0x57, 0x03}, + 4096, + 512, + 0x40000, + 256, + 1, + 16, + 15, + 0, + (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )}, + {"A revision NAND 128MB TC58NVG0S3HTA00 ", {NAND_MFR_TOSHIBA, 0xf1, 0x80, 0x15, 0x72}, 2048, @@ -1053,9 +1065,6 @@ printk("NAND device id: %x %x %x %x %x %x \n", dev_id[0], dev_id[1], dev_id[2], dev_id[3], dev_id[4], dev_id[5]); -#if 0 - test_timing(mtd, chip); -#endif /* Lookup the flash id */ for (i = 0; aml_nand_flash_ids[i].name != NULL; i++) { if (!strncmp((char*) aml_nand_flash_ids[i].id, @@ -1065,16 +1074,6 @@ } } - if (pre_scan->pre_scan_flag) { - if (type) { - /*printk(KERN_INFO "NAND device: Manufacturer ID:" - " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id[0], - nand_manuf_ids[maf_idx].name, type->name);*/ - pre_scan->is_nand = 1; - } - return type; - } - if (!type) { if (plat->nand_flash_dev) { if (!strncmp((char*) plat->nand_flash_dev->id, @@ -1082,14 +1081,19 @@ type = plat->nand_flash_dev; } - if (!type) - return ERR_PTR(-ENODEV); + if (!type) { + pre_scan->is_nand = 0; + return type; + } } aml_nand_check_fbb_issue(dev_id); - /**fixme**/ - if (plat->nand_flash_dev) { - plat->nand_flash_dev = type; + plat->nand_flash_dev = type; + + if (pre_scan->pre_scan_flag) { + if (type) + pre_scan->is_nand = 1; + return type; } #ifdef CONFIG_MTD_DEVICE mtd->name = type->name; @@ -1207,8 +1211,8 @@ aml_type = aml_nand_get_flash_type(mtd, chip, busw, &nand_maf_id); if (pre_scan->pre_scan_flag) { if (!aml_type) { - chip->select_chip(mtd, -1); - return PTR_ERR(aml_type); + chip->select_chip(mtd, -1); + return -ENODEV; } return 0; }
diff --git a/drivers/mtd/nand/raw/aml_nand/storage_nand.c b/drivers/mtd/nand/raw/aml_nand/storage_nand.c index 24f0a4c..57b2ce4 100644 --- a/drivers/mtd/nand/raw/aml_nand/storage_nand.c +++ b/drivers/mtd/nand/raw/aml_nand/storage_nand.c
@@ -19,31 +19,14 @@ extern void mtd_store_mount_ops(struct storage_t* store); struct aml_pre_scan *pre_scan; -static inline void set_slc_nand_storage(struct storage_t *slc_nand) -{ - slcnand_storage = slc_nand; -} - -static inline struct storage_t *get_slc_nand_storage(void) -{ - return slcnand_storage; -} - int nand_pre(void) { int ret = 0; + pre_scan->pre_scan_flag = 1; - pre_scan->is_nand = 0; board_nand_init(); - if (pre_scan->is_nand) { - printf("scan valid slc-nand\n"); - ret = 0; - } else { - ret = 1; - printf("scan no valid slc-nand\n"); - } + ret = (pre_scan->is_nand)? 0:1; pre_scan->pre_scan_flag = 0; - pre_scan->is_nand = 0; return ret; } @@ -55,9 +38,6 @@ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(nand_info[0]); struct aml_nand_flash_dev *type = NULL; - if (get_slc_nand_storage()) - return 0; - type = aml_chip->platform->nand_flash_dev; if (slc_nand == NULL) { @@ -72,7 +52,7 @@ slc_nand->init_flag = 0; printf("storage dev type: 0x%x, storage device is slc NAND\n",slc_nand->type); - memcpy(slc_nand->info.name, type->name, 32*sizeof(char)); + memcpy(slc_nand->info.name, type->name, 32 * sizeof(char)); memcpy(slc_nand->info.id, type->id, 8); printf("name: %s\n",slc_nand->info.name); @@ -86,8 +66,6 @@ #else slc_nand->info.mode = 0; #endif - - set_slc_nand_storage(slc_nand); mtd_store_mount_ops(slc_nand); #ifdef CONFIG_MTD_LOGIC_MAP @@ -96,29 +74,13 @@ return store_register(slc_nand); } -extern int amlmtd_init; -extern void board_nand_init(void); extern int meson_nfc_probe(struct udevice *dev); struct udevice *nand_dev; int nand_probe(uint32_t init_flag) { - struct storage_t *slc_nand = get_slc_nand_storage(); - - if (slc_nand) { - slc_nand->init_flag = init_flag; - printf("nand probe success1\n"); - return 0; - } meson_nfc_probe(nand_dev); - slc_nand = get_slc_nand_storage(); - if (!slc_nand) { - printf("%s %d can not get slc nand!\n", - __func__, __LINE__); - return 1; - } - slc_nand->init_flag = init_flag; - printf("nand probe success0\n"); + return 0; }
diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index 806eaa6..19d6c77 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c
@@ -156,7 +156,7 @@ initialized = 1; #ifdef CONFIG_SYS_NAND_SELF_INIT - printf("borad nand init\n"); + printf("board nand init\n"); board_nand_init(); #else int i;
diff --git a/drivers/mtd/nand/spi-nand/aml_spinand.c b/drivers/mtd/nand/spi-nand/aml_spinand.c index b115d09..dc04e34 100644 --- a/drivers/mtd/nand/spi-nand/aml_spinand.c +++ b/drivers/mtd/nand/spi-nand/aml_spinand.c
@@ -142,6 +142,7 @@ struct spinand_info { struct nand_hw_control controller; struct nand_chip chip; + unsigned int planes_per_lun; #ifndef __UBOOT__ struct spi_device *pdev; #else @@ -174,7 +175,8 @@ #define SPINAND_INFO_VER 1 u8 rd_max; /* spi nand max read io */ u8 oob_offset; /* user bytes offset */ - u8 reserved[2]; + u8 planes_per_lun; + u8 reserved; u32 fip_start; /* start pages */ u32 fip_pages; /* pages per fip */ u32 page_size; /* spi nand page size (bytes) */ @@ -377,6 +379,15 @@ .id_len = 2, .oobsize = 64 }, + {"SPI NAND TC58CVG1S3HRAIG 256MiB 3.3V", + { .id = {0x98, 0xcb} }, + .pagesize = SZ_2K, + .chipsize = SZ_256M, + .erasesize = SZ_128K, + .options = SPI_RX_QUAD, + .id_len = 2, + .oobsize = 64 + }, {"SPI NAND ZD35Q1GA 128MiB 3.3V", { .id = {0xba, 0x71} }, .pagesize = SZ_2K, @@ -386,6 +397,15 @@ .id_len = 2, .oobsize = 64 }, + {"SPI NAND ZD35Q2GA 256MiB 3.3V", + { .id = {0xba, 0x72} }, + .pagesize = SZ_2K, + .chipsize = SZ_256M, + .erasesize = SZ_128K, + .options = SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD, + .id_len = 2, + .oobsize = 64 + }, {"SPI NAND ZD35M1GA 128MiB 1.8V", { .id = {0xba, 0x21} }, .pagesize = SZ_2K, @@ -404,10 +424,25 @@ .id_len = 2, .oobsize = 64 }, + {"MT29F2G01ABAGD/F50L2G41XA 256MiB 3.3V", + { .id = {0x2c, 0x24} }, + .pagesize = SZ_2K, + .chipsize = SZ_256M, + .erasesize = SZ_128K, + .options = SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD, + .id_len = 2, + .oobsize = 64 + }, {NULL} }; +static int chip_plane_ids[][3] = { + { 0xba, 0x72, 2 }, /* ZD35Q2GA */ + { 0x2c, 0x24, 2 }, /* MT29F2G01ABAGD/F50L2G41XA */ +}; + + #ifdef CONFIG_AML_STORAGE extern int spinand_fit_storage(struct nand_chip *chip, char *name, u8 *id); #endif @@ -562,11 +597,23 @@ return NULL; } +static unsigned int plane_of_page_addr(struct mtd_info *mtd, + u32 page_addr) +{ + struct spinand_info *info = mtd_to_spinand(mtd); + struct nand_chip *chip = mtd->priv; + + return ((page_addr >> (chip->phys_erase_shift - chip->page_shift)) + % info->planes_per_lun); +} + static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { struct spinand_info *info = mtd_to_spinand(mtd); + struct nand_chip *chip = mtd->priv; + unsigned int plane; memset(info->cmd, 0, MAX_CMD_SIZE); info->cmd[0] = command; @@ -606,6 +653,10 @@ case SPINAND_CMD_PLOAD: case SPINAND_CMD_QUAD_PLOAD: + if (info->planes_per_lun > 1) { + plane = plane_of_page_addr(mtd, page_addr); + column |= plane << (chip->page_shift + 1); + } info->cmd[1] = (u8)(column >> 8); info->cmd[2] = (u8)(column); info->cmd_len = 3; @@ -615,6 +666,10 @@ case SPINAND_CMD_FAST_READ: case SPINAND_CMD_DUAL_READ: case SPINAND_CMD_QUAD_READ: + if (info->planes_per_lun > 1) { + plane = plane_of_page_addr(mtd, page_addr); + column |= plane << (chip->page_shift + 1); + } if (info->chip_ver != GIGA_SPINAND_CHIP_VER_C) { info->cmd[1] = (u8)(column >> 8); info->cmd[2] = (u8)(column); @@ -805,7 +860,7 @@ if (meson_rsv_erase_protect(info->rsv, instr->addr / mtd->erasesize)) { printf("%s blk 0x%x is protected\n", __func__, - instr->addr / mtd->erasesize); + (unsigned int)instr->addr / mtd->erasesize); goto erase_exit; } @@ -1035,7 +1090,7 @@ (info->id[0] == NAND_MFR_MACRONIX) || (info->id[0] == NAND_MFR_ZETTA))) spinand_set_qeb(mtd, chip); - chip->cmdfunc(mtd, info->read_cmd, 0, -1); + chip->cmdfunc(mtd, info->read_cmd, 0, page); if (unlikely(ops->mode == MTD_OPS_RAW)) ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, oob_required, page); @@ -1178,6 +1233,7 @@ info_page->dev.s.page_size = mtd->writesize; info_page->dev.s.page_per_blk = page_per_blk; info_page->dev.s.oob_size = mtd->oobsize; + info_page->dev.s.planes_per_lun = spinand->planes_per_lun; info_page->dev.s.oob_offset = mtd->ecclayout->oobfree[0].offset; if (spinand->rsv->bbt->valid) { info_page->dev.s.bbt_start = @@ -1239,7 +1295,7 @@ (info->id[0] == NAND_MFR_MACRONIX) || (info->id[0] == NAND_MFR_ZETTA))) spinand_set_qeb(mtd, chip); - chip->cmdfunc(mtd, info->read_cmd, mtd->writesize, -1); + chip->cmdfunc(mtd, info->read_cmd, mtd->writesize, page); if (ops->mode == MTD_OPS_RAW) ret = chip->ecc.read_oob_raw(mtd, chip, page); @@ -1414,7 +1470,7 @@ pr_debug("%s %d write info page to page %d\n", __func__, __LINE__, (page + 1)); chip->cmdfunc(mtd, SPINAND_CMD_WREN, -1, -1); - chip->cmdfunc(mtd, info->pload_cmd, 0x00, -1); + chip->cmdfunc(mtd, info->pload_cmd, 0x00, page + 1); chip->write_buf(mtd, (u8 *)info_buf, mtd->writesize); if (info->status < 0) @@ -1455,7 +1511,7 @@ (info->id[0] == NAND_MFR_ZETTA))) spinand_set_qeb(mtd, chip); chip->cmdfunc(mtd, SPINAND_CMD_WREN, -1, -1); - chip->cmdfunc(mtd, info->pload_cmd, 0x00, -1); + chip->cmdfunc(mtd, info->pload_cmd, 0x00, page); if (unlikely(raw)) status = chip->ecc.write_page_raw(mtd, chip, buf, @@ -1616,7 +1672,7 @@ (info->id[0] == NAND_MFR_ZETTA))) spinand_set_qeb(mtd, chip); chip->cmdfunc(mtd, SPINAND_CMD_WREN, -1, -1); - chip->cmdfunc(mtd, info->pload_cmd, mtd->writesize, -1); + chip->cmdfunc(mtd, info->pload_cmd, mtd->writesize, page); info->oob_required = 1; chip->write_buf(mtd, NULL, 0); @@ -1759,7 +1815,7 @@ (info->id[0] == NAND_MFR_ZETTA))) spinand_set_qeb(mtd, chip); chip->cmdfunc(mtd, info->read_cmd, - mtd->writesize + chip->badblockpos, -1); + mtd->writesize + chip->badblockpos, page); bad = chip->read_byte(mtd); if (likely(chip->badblockbits == 8)) @@ -2181,7 +2237,7 @@ do { if (mtd->_block_isbad(mtd, offset)) { printf("%s %d found bad block in 0x%llx\n", - __func__, __LINE__, off); + __func__, __LINE__, offset); end += mtd->erasesize; } offset += mtd->erasesize; @@ -2248,6 +2304,15 @@ info->pdev->mode = mode; mtd->size = chip->chipsize; info->name = type->name; + + info->planes_per_lun = 1; + for (int i=0; i<ARRAY_SIZE(chip_plane_ids); i++) + if ((maf_id == chip_plane_ids[i][0]) && + (dev_id == chip_plane_ids[i][1])) { + info->planes_per_lun = chip_plane_ids[i][2]; + break; + } + memset(info->id, 0, NAND_MAX_ID_LEN); memcpy(info->id, type->id, type->id_len); return 0;
diff --git a/drivers/mtd/nand/spi/Kconfig b/drivers/mtd/nand/spi/Kconfig index 2197cb5..e2c9090 100644 --- a/drivers/mtd/nand/spi/Kconfig +++ b/drivers/mtd/nand/spi/Kconfig
@@ -5,3 +5,14 @@ select SPI_MEM help This is the framework for the SPI NAND device drivers. + +config SPI_NAND_AML_ADVANCED + bool "SPI Nand meson advanced support" + depends on MTD_SPI_NAND + default n + help + SC2 needs to support a new burning mode (ADVANCED), we implement + it based on the original discrete modem. If say Y enabled ADVANCED + mode, spinand will use ADVANCED mode to burning. + If unsure, say N +
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index dd6baca..59b046d 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o +spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o toshiba.o zetta.o xtx.o storage_sn.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index cb8ffa3..1268186 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c
@@ -25,10 +25,20 @@ #include <spi.h> #include <spi-mem.h> #include <linux/mtd/spinand.h> +#include <linux/mtd/partitions.h> +#include <spi.h> +#include <amlogic/aml_rsv.h> +#include <amlogic/aml_mtd.h> +#include <linux/log2.h> +#include <asm/arch/cpu_config.h> +#include <amlogic/storage.h> #endif /* SPI NAND index visible in MTD names */ static int spi_nand_idx; +#ifdef CONFIG_AML_STORAGE +extern int spinand_fit_storage(struct mtd_info *info, char *name, u8 *id); +#endif static void spinand_cache_op_adjust_colum(struct spinand_device *spinand, const struct nand_page_io_req *req, @@ -207,6 +217,7 @@ spinand->op_templates.update_cache->data.buswidth == 4) enable = true; + printf("spinand qe is %s\n",enable ? "enable" : "disabled"); return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE, enable ? CFG_QUAD_ENABLE : 0); } @@ -450,12 +461,17 @@ { struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf, SPINAND_MAX_ID_LEN); - int ret; + int ret, i; ret = spi_mem_exec_op(spinand->slave, &op); if (!ret) memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN); + /* Success or failure print id */ + printf("spinand id detect\n"); + for (i = 0; i < SPINAND_MAX_ID_LEN; i++) + printf("id[%d] = 0x%x\n",i,spinand->id.data[i]); + return ret; } @@ -608,6 +624,72 @@ return ret ? ret : max_bitflips; } +/* add for meson info_page */ +#if SPINAND_MESON_INFO_PAGE +bool spinand_is_info_page(struct nand_device *nand, int page) +{ + return unlikely((page % 128) == ((BL2_SIZE / 2048) - 1) && + page < BOOT_TOTAL_PAGES); +} + +int spinand_set_info_page(struct mtd_info *mtd, void *buf) +{ + u32 page_per_blk; + struct mtd_oob_region region; + struct nand_device* dev = mtd_to_nanddev(mtd); + struct info_page *info_page = (struct info_page *)buf; + + page_per_blk = mtd->erasesize / mtd->writesize; + memcpy(info_page->magic, SPINAND_MAGIC, strlen(SPINAND_MAGIC)); + info_page->version = SPINAND_INFO_VER; + /* DISCRETE only */ + info_page->mode = 1; + info_page->bl2_num = CONFIG_BL2_COPY_NUM; + info_page->fip_num = CONFIG_TPL_COPY_NUM; + info_page->dev.s.rd_max = 2; + info_page->dev.s.fip_start = + BOOT_TOTAL_PAGES + NAND_RSV_BLOCK_NUM * page_per_blk; + info_page->dev.s.fip_pages = CONFIG_TPL_SIZE_PER_COPY / mtd->writesize; + info_page->dev.s.page_size = mtd->writesize; + info_page->dev.s.page_per_blk = page_per_blk; + info_page->dev.s.oob_size = mtd->oobsize; + mtd->ooblayout->free(mtd, 0, ®ion); + info_page->dev.s.oob_offset = region.offset; + info_page->dev.s.bbt_start = 0; + info_page->dev.s.bbt_valid = 0; + info_page->dev.s.bbt_size = 0; + info_page->dev.s.planes_per_lun = dev->memorg.planes_per_lun; + + return 0; +} + +static int spinand_append_info_page(struct mtd_info *mtd, + struct nand_page_io_req *last_req) +{ + struct spinand_device *spinand = mtd_to_spinand(mtd); + struct nand_device *nand = mtd_to_nanddev(mtd); + struct nand_page_io_req req; + int page; + u8 *buf; + int ret = 0; + + page = nanddev_pos_to_row(nand, &last_req->pos); + if (spinand_is_info_page(nand, page)) { + req = *last_req; + req.datalen = mtd->writesize; + req.dataoffs = 0; + req.ooblen = 0; + buf = kzalloc(mtd->writesize, GFP_KERNEL); + req.databuf.in = buf; + spinand_set_info_page(mtd, buf); + nanddev_pos_next_page(nand, &req.pos); + ret = spinand_write_page(spinand, &req); + kfree(buf); + pr_info("%s: %d\n", __func__, page); + } + return ret; +} +#endif static int spinand_mtd_write(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops) { @@ -637,6 +719,12 @@ if (ret) break; + /* add for meson info page */ + #if SPINAND_MESON_INFO_PAGE + ret = spinand_append_info_page(mtd, &iter.req); + if (ret) + break; + #endif ops->retlen += iter.req.datalen; ops->oobretlen += iter.req.ooblen; } @@ -747,8 +835,18 @@ { struct spinand_device *spinand = nand_to_spinand(nand); u8 status; - int ret; + int ret = 0; +#if SPINAND_MESON_RSV + unsigned int block = nanddev_pos_to_offs(nand, pos) / + (nand->memorg.pages_per_eraseblock * nand->memorg.pagesize); + + /* meson rsv protect */ + if (meson_rsv_erase_protect(spinand->rsv, block)) { + pr_err("blk 0x%x is protected\n", block); + return ret; + } +#endif ret = spinand_select_target(spinand, pos->target); if (ret) return ret; @@ -831,9 +929,12 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = { &gigadevice_spinand_manufacturer, + &toshiba_spinand_manufacturer, ¯onix_spinand_manufacturer, µn_spinand_manufacturer, &winbond_spinand_manufacturer, + &zetta_spinand_manufacturer, + &xtx_spinand_manufacturer, }; static int spinand_manufacturer_detect(struct spinand_device *spinand) @@ -937,6 +1038,8 @@ spinand->eccinfo = table[i].eccinfo; spinand->flags = table[i].flags; spinand->select_target = table[i].select_target; + /* Record the current spinand */ + spinand->model = table[i].model; op = spinand_select_op_variant(spinand, info->op_variants.read_cache); @@ -990,12 +1093,12 @@ return -EINVAL; } - dev_info(spinand->slave->dev, - "%s SPI NAND was found.\n", spinand->manufacturer->name); - dev_info(spinand->slave->dev, - "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n", + printf("%s %s SPI NAND was found.\n", spinand->manufacturer->name, spinand->model); + printf("%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n", nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10, nanddev_page_size(nand), nanddev_per_page_oobsize(nand)); + printf("read cmd: 0x%x write cmd: 0x%x\n",spinand->op_templates.read_cache->cmd.opcode, + spinand->op_templates.write_cache->cmd.opcode); return 0; } @@ -1138,6 +1241,139 @@ kfree(spinand->scratchbuf); } +#ifdef CONFIG_AML_MTDPART +/* The size of the partition must be block aligned */ +int spinand_add_partitions(struct mtd_info *mtd, + const struct mtd_partition *parts, + int nbparts) +{ + int part_num = 0, i = 0; + struct mtd_partition *temp, *parts_nm; + loff_t off; + +#ifdef CONFIG_DISCRETE_BOOTLOADER +#ifdef CONFIG_SPI_NAND_AML_ADVANCED + part_num = nbparts + 5; +#else + part_num = nbparts + 2; +#endif/* CONFIG_SPI_NAND_AML_ADVANCED */ +#else + part_num = nbparts + 1; +#endif/* CONFIG_DISCRETE_BOOTLOADER */ + temp = kzalloc(sizeof(*temp) * part_num, GFP_KERNEL); + memset(temp, 0, sizeof(*temp) * part_num); + temp[0].name = BOOT_LOADER; + temp[0].offset = 0; + temp[0].size = BOOT_TOTAL_PAGES * mtd->writesize; + if (temp[0].size % mtd->erasesize) + WARN_ON(1); + off = temp[0].size + NAND_RSV_BLOCK_NUM * mtd->erasesize; +#ifdef CONFIG_DISCRETE_BOOTLOADER +#ifdef CONFIG_SPI_NAND_AML_ADVANCED + extern struct storage_startup_parameter g_ssp; + temp[BOOT_AREA_BL2E].name = BOOT_BL2E; + temp[BOOT_AREA_BL2E].offset = g_ssp.boot_entry[BOOT_AREA_BL2E].offset; + temp[BOOT_AREA_BL2E].size = g_ssp.boot_entry[BOOT_AREA_BL2E].size * g_ssp.boot_bakups; + if (temp[0].size % mtd->erasesize) + WARN_ON(1); + + temp[BOOT_AREA_BL2X].name = BOOT_BL2X; + temp[BOOT_AREA_BL2X].offset = g_ssp.boot_entry[BOOT_AREA_BL2X].offset; + temp[BOOT_AREA_BL2X].size = g_ssp.boot_entry[BOOT_AREA_BL2X].size * g_ssp.boot_bakups; + if (temp[0].size % mtd->erasesize) + WARN_ON(1); + + temp[BOOT_AREA_DDRFIP].name = BOOT_DDRFIP; + temp[BOOT_AREA_DDRFIP].offset = g_ssp.boot_entry[BOOT_AREA_DDRFIP].offset; + temp[BOOT_AREA_DDRFIP].size = g_ssp.boot_entry[BOOT_AREA_DDRFIP].size * g_ssp.boot_bakups; + if (temp[0].size % mtd->erasesize) + WARN_ON(1); + + temp[BOOT_AREA_DEVFIP].name = BOOT_DEVFIP; + temp[BOOT_AREA_DEVFIP].offset = g_ssp.boot_entry[BOOT_AREA_DEVFIP].offset; + temp[BOOT_AREA_DEVFIP].size = g_ssp.boot_entry[BOOT_AREA_DEVFIP].size * CONFIG_TPL_COPY_NUM; + if (temp[0].size % mtd->erasesize) + WARN_ON(1); + off = temp[BOOT_AREA_DEVFIP].offset + temp[BOOT_AREA_DEVFIP].size; + parts_nm = &temp[5]; +#else + temp[1].name = BOOT_TPL; + temp[1].offset = off; + temp[1].size = CONFIG_TPL_SIZE_PER_COPY * CONFIG_TPL_COPY_NUM; + if (temp[1].size % mtd->erasesize) + WARN_ON(1); + parts_nm = &temp[2]; + off += temp[1].size; +#endif/*CONFIG_SPI_NAND_AML_ADVANCED*/ +#else + parts_nm = &temp[1]; +#endif/* CONFIG_DISCRETE_BOOTLOADER */ + for (; i < nbparts; i++) { + //printf("add_partitions ==== name = %s\n",parts[i].name); + if (!parts[i].name) { + pr_err("name can't be null! "); + pr_err("please check your %d th partition name!\n", + i + 1); + return 1; + } + if ((off + parts[i].size) > mtd->size) { + pr_err("%s %d over nand size!\n", + __func__, __LINE__); + return 1; + } + parts_nm[i].name = parts[i].name; +#ifndef CONFIG_NOT_SKIP_BAD_BLOCK + loff_t offset = off, end = off + parts[i].size; + + do { + if (mtd->_block_isbad(mtd, offset)) { + pr_err("%s %d found bad block in 0x%llx\n", + __func__, __LINE__, offset); + end += mtd->erasesize; + } + offset += mtd->erasesize; + } while (offset < end && offset < mtd->size); + parts_nm[i].size = end - off - parts[i].size; +#endif/* CONFIG_NOT_SKIP_BAD_BLOCK */ + parts_nm[i].offset = off; + if (parts[i].size % mtd->erasesize) { + pr_err("%s %d \"%s\" size auto align to block size\n", + __func__, __LINE__, parts[i].name); + parts_nm[i].size += parts[i].size % mtd->erasesize; + } + /* it's ok "+=" here because size has been set to 0 */ + parts_nm[i].size += parts[i].size; + off += parts_nm[i].size; + if (i == (nbparts - 1)) + parts_nm[i].size = mtd->size - off; + } + return add_mtd_partitions(mtd, temp, part_num); +} +#endif + +#if SPINAND_MESON_RSV /* add for meson rsv */ +static int spinand_scan_bbt(struct spinand_device *spinand, struct mtd_info *mtd) +{ + loff_t offset = 0; + u64 block_cnt = mtd->size >> mtd->erasesize_shift; + int i = 0, ret = 0; + + spinand->bbt_scan = 1; + memset(spinand->bbt, 0, block_cnt); + for (i = 0; i < block_cnt; i++) { + offset = i * mtd->erasesize; + ret = mtd->_block_isbad(mtd, offset); + if (ret) { + pr_err("%s %d detected a bad block at 0x%llx\n", + __func__, __LINE__, offset); + spinand->bbt[i] = NAND_FACTORY_BAD; + } + } + spinand->bbt_scan = 0; + return 0; +} +#endif + static int spinand_probe(struct udevice *dev) { struct spinand_device *spinand = dev_get_priv(dev); @@ -1175,15 +1411,47 @@ if (ret) return ret; +#if SPINAND_MESON_RSV /* add for meson rsv management */ + if (is_power_of_2(mtd->erasesize)) + mtd->erasesize_shift = ffs(mtd->erasesize) - 1; + else + mtd->erasesize_shift = 0; + + if (is_power_of_2(mtd->writesize)) + mtd->writesize_shift = ffs(mtd->writesize) - 1; + else + mtd->writesize_shift = 0; + + spinand->rsv = kzalloc(sizeof(*spinand->rsv), GFP_KERNEL); + meson_rsv_init(mtd, spinand->rsv); + spinand->bbt = kzalloc(mtd->size >> mtd->erasesize_shift, GFP_KERNEL); + if (meson_rsv_check(spinand->rsv->bbt)) { + pr_err("no valid bbt info, scanning!\n"); + spinand_scan_bbt(spinand, mtd); + meson_rsv_save(spinand->rsv->bbt, spinand->bbt); + } else { + pr_err("reading bbt info from %s!\n", mtd->name); + meson_rsv_read(spinand->rsv->bbt, spinand->bbt); + } + + meson_rsv_check(spinand->rsv->env); + meson_rsv_check(spinand->rsv->key); + meson_rsv_check(spinand->rsv->dtb); +#endif + #ifndef __UBOOT__ ret = mtd_device_register(mtd, NULL, 0); -#else - ret = add_mtd_device(mtd); +/*#else + ret = add_mtd_device(mtd);*/ #endif if (ret) goto err_spinand_cleanup; - return 0; +#ifdef CONFIG_AML_STORAGE + ret = spinand_fit_storage(mtd, mtd->name, spinand->id.data); +#endif + + return ret; err_spinand_cleanup: spinand_cleanup(spinand);
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index 0bade20..d1b3221 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -20,9 +20,9 @@ #define GIGADEVICE_STATUS_ECC_8_BITFLIPS (3 << 4) static SPINAND_OP_VARIANTS(read_cache_variants, - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + //SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + //SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); @@ -91,14 +91,90 @@ return -EINVAL; } +static int gd5f4gq4u_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 128; + region->length = 128; + + return 0; +} + +static int gd5f4gq4u_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* Reserve 2 bytes for the BBM. */ + region->offset = 2; + region->length = 126; + + return 0; +} + +static const struct mtd_ooblayout_ops gd5f4gq4u_ooblayout = { + .ecc = gd5f4gq4u_ooblayout_ecc, + .free = gd5f4gq4u_ooblayout_free, +}; + +static int gd5f4gq4u_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + if (status) + debug("%s (%d): status=%02x\n", __func__, __LINE__, status); + + switch (status & GIGADEVICE_STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS: + return 7; + + case GIGADEVICE_STATUS_ECC_8_BITFLIPS: + return 8; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + default: + break; + } + + return -EINVAL; +} + static const struct spinand_info gigadevice_spinand_table[] = { - SPINAND_INFO("GD5F1GQ4UC", 0xd1, + SPINAND_INFO("GD5F1GQ4UB 3.3v", 0xd1, NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 2048), + NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), - 0, + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5f1gq4u_ooblayout, + gd5f1gq4u_ecc_get_status)), + + SPINAND_INFO("GD5F4GQ4UB 3.3v", 0xd4, + NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5f4gq4u_ooblayout, + gd5f4gq4u_ecc_get_status)), + + SPINAND_INFO("GD5F2GQ5UE 3.3v", 0x52, + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&gd5f1gq4u_ooblayout, gd5f1gq4u_ecc_get_status)), }; @@ -108,16 +184,12 @@ u8 *id = spinand->id.data; int ret; - /* - * Gigadevice SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_GIGADEVICE) + if (id[0] != SPINAND_MFR_GIGADEVICE) return 0; ret = spinand_match_and_init(spinand, gigadevice_spinand_table, ARRAY_SIZE(gigadevice_spinand_table), - id[2]); + id[1]); if (ret) return ret;
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index 662c561..afbb19d 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c
@@ -12,6 +12,9 @@ #include <linux/mtd/spinand.h> #define SPINAND_MFR_MACRONIX 0xC2 +/* Read ECCSR (7Ch) command for ECC Status Read */ +#define MACRONIX_CURRENT_ECCSR_MASK 0x0F +#define MACRONIX_ACCUMULATE_ECCSR_MASK (0x0F << 4); static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -45,11 +48,34 @@ return 0; } +static int MX35LF2GE4AD_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + return -ERANGE; +} + +static int MX35LF2GE4AD_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section > 3) + return -ERANGE; + + region->offset = (16 * section) + 2; + region->length = 14; + + return 0; +} + static const struct mtd_ooblayout_ops mx35lfxge4ab_ooblayout = { .ecc = mx35lfxge4ab_ooblayout_ecc, .free = mx35lfxge4ab_ooblayout_free, }; +static const struct mtd_ooblayout_ops MX35LF2GE4AD_ooblayout = { + .ecc = MX35LF2GE4AD_ooblayout_ecc, + .free = MX35LF2GE4AD_ooblayout_free, +}; + static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr) { struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1), @@ -82,6 +108,47 @@ if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr)) return nand->eccreq.strength; + if (WARN_ON(eccsr > nand->eccreq.strength || !eccsr)) { + return nand->eccreq.strength; + } + + return eccsr; + + default: + break; + } + + return -EINVAL; +} + +static int mx35lf2ge4ad_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + struct nand_device *nand = spinand_to_nand(spinand); + u8 eccsr; + + switch (status & STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + case STATUS_ECC_HAS_BITFLIPS: + /* + * Let's try to retrieve the real maximum number of bitflips + * in order to avoid forcing the wear-leveling layer to move + * data around if it's not necessary. + */ + if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr)) + return nand->eccreq.strength; + + /* + * note: + * bit0~3 ECC Status for the current page + * bit4~7 ECC Status for the accumulated page + */ + eccsr &= MACRONIX_CURRENT_ECCSR_MASK; if (WARN_ON(eccsr > nand->eccreq.strength || !eccsr)) return nand->eccreq.strength; @@ -95,7 +162,7 @@ } static const struct spinand_info macronix_spinand_table[] = { - SPINAND_INFO("MX35LF1GE4AB", 0x12, + SPINAND_INFO("MX35LF1GE4AB 3.3v", 0x12, NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), NAND_ECCREQ(4, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -104,14 +171,16 @@ SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, mx35lf1ge4ab_ecc_get_status)), - SPINAND_INFO("MX35LF2GE4AB", 0x22, - NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), - NAND_ECCREQ(4, 512), + + SPINAND_INFO("MX35LF2GE4AD", 0x26, + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), SPINAND_HAS_QE_BIT, - SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), + SPINAND_ECCINFO(&MX35LF2GE4AD_ooblayout, + mx35lf2ge4ad_ecc_get_status)), }; static int macronix_spinand_detect(struct spinand_device *spinand) @@ -119,16 +188,12 @@ u8 *id = spinand->id.data; int ret; - /* - * Macronix SPI NAND read ID needs a dummy byte, so the first byte in - * raw_id is garbage. - */ - if (id[1] != SPINAND_MFR_MACRONIX) + if (id[0] != SPINAND_MFR_MACRONIX) return 0; ret = spinand_match_and_init(spinand, macronix_spinand_table, ARRAY_SIZE(macronix_spinand_table), - id[2]); + id[1]); if (ret) return ret;
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 83951c5..cdec93c 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c
@@ -21,9 +21,9 @@ #define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4) static SPINAND_OP_VARIANTS(read_cache_variants, - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + //SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + //SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); @@ -33,7 +33,7 @@ SPINAND_PROG_LOAD(true, 0, NULL, 0)); static SPINAND_OP_VARIANTS(update_cache_variants, - SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + //SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section, @@ -93,7 +93,7 @@ } static const struct spinand_info micron_spinand_table[] = { - SPINAND_INFO("MT29F2G01ABAGD", 0x24, + SPINAND_INFO("MT29F2G01ABAGD/F50L2G41XA", 0x24, NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1), NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, @@ -109,15 +109,11 @@ u8 *id = spinand->id.data; int ret; - /* - * Micron SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_MICRON) + if (id[0] != SPINAND_MFR_MICRON) return 0; ret = spinand_match_and_init(spinand, micron_spinand_table, - ARRAY_SIZE(micron_spinand_table), id[2]); + ARRAY_SIZE(micron_spinand_table), id[1]); if (ret) return ret;
diff --git a/drivers/mtd/nand/spi/storage_sn.c b/drivers/mtd/nand/spi/storage_sn.c new file mode 100644 index 0000000..4e1d52e --- /dev/null +++ b/drivers/mtd/nand/spi/storage_sn.c
@@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +//#include <nand.h> +#include <dm/device-internal.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/rawnand.h> +#include <linux/mtd/partitions.h> +#include <amlogic/storage.h> +#include <amlogic/aml_mtd.h> + + +static struct storage_t *snand_storage; +#ifdef CONFIG_MTD_LOGIC_MAP +extern void mtd_store_init_map(void); +#endif +extern void mtd_store_set(struct mtd_info *mtd, int dev); +extern void mtd_store_mount_ops(struct storage_t *store); +extern int spinand_add_partitions(struct mtd_info *mtd, + const struct mtd_partition *parts, + int nbparts); + +static inline void set_snand_storage(struct storage_t *snand) +{ + snand_storage = snand; +} + +static inline struct storage_t *get_snand_storage(void) +{ + return snand_storage; +} + +int board_nand_init(void) +{ + u32 bus = 0, cs = 1, speed = 0, mode = 0; + struct spi_slave *slave; + struct udevice *dev; + int ret; + + ret = spi_get_bus_and_cs(bus, cs, speed, mode, + NULL, NULL, &dev, &slave); + if (ret) { + printf("%s %d probe spi nand fail!\n", + __func__, __LINE__); + return 1; + } + + return 0; +} + +int spinand_fit_storage(struct mtd_info *info, char *name, u8 *id) +{ + struct storage_t *spi_nand = NULL; + struct mtd_info *mtd = info; + + if (get_snand_storage()) + return 0; + spi_nand = kzalloc(sizeof(*spi_nand), GFP_KERNEL); + if (!spi_nand) { + debug("%s %d no enough memory!\n", __func__, __LINE__); + return -ENOMEM; + } + spi_nand->type = BOOT_SNAND; + spi_nand->init_flag = 0; + /* TODO:set name and id parameter */ + memcpy(spi_nand->info.name, + name, strlen(name) > 32 ? 32 : strlen(name)); + memcpy(spi_nand->info.id, id, NAND_MAX_ID_LEN); + spi_nand->info.read_unit = mtd->writesize; + spi_nand->info.write_unit = mtd->writesize; + spi_nand->info.erase_unit = mtd->erasesize; + spi_nand->info.caps = mtd->size; +#ifdef CONFIG_DISCRETE_BOOTLOADER + spi_nand->info.mode = 1; +#else + spi_nand->info.mode = 0; +#endif + set_snand_storage(spi_nand); + mtd_store_mount_ops(spi_nand); + mtd_store_set(mtd, 0); +#ifdef CONFIG_MTD_LOGIC_MAP + mtd_store_init_map(); +#endif + return store_register(spi_nand); +} + +int spi_nand_pre(void) +{ + struct storage_t *spi_nand = get_snand_storage(); + + if (spi_nand) + return 0; + + return board_nand_init(); +} + +int spi_nand_probe(u32 init_flag) +{ + struct storage_t *spi_nand = get_snand_storage(); + const struct mtd_partition *spinand_partitions; + struct mtd_info *mtd; + int partition_count, ret; + static int probe_flag; + + if (probe_flag) + return 0; + +#ifdef CONFIG_AML_MTDPART + extern const struct mtd_partition *get_partition_table(int *partitions); + extern struct mtd_info *mtd_store_get(int dev); + spinand_partitions = get_partition_table(&partition_count); + mtd = mtd_store_get(0); + ret = spinand_add_partitions(mtd, spinand_partitions, + partition_count); + if (ret) { + printf("%s %d can not add spinand partition!\n", + __func__, __LINE__); + return 1; + } +#endif + + spi_nand = get_snand_storage(); + if (!spi_nand) { + printf("%s %d can not get spi nand!\n", + __func__, __LINE__); + return 1; + } + spi_nand->init_flag = init_flag; + probe_flag = 1; + + return 0; +}
diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c new file mode 100644 index 0000000..4c807fd --- /dev/null +++ b/drivers/mtd/nand/spi/toshiba.c
@@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_TOSHIBA 0x98 + +/* Bit errors were detected and corrected. + * Bit error count exceeded the bit flip detection threshold. + * The threshold is set by bits [7:4] in address 10h in the feature table + */ +#define TOSHIBA_STATUS_ECC_8_BITFLIPS (3 << 4) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + //SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int tc58cvg0s3hraig_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + /* Unable to know the layout of ECC */ + return -ERANGE; +} + +static int tc58cvg0s3hraig_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* Reserve 2 bytes for the BBM. */ + region->offset = 2; + region->length = 62; + + return 0; +} + +static const struct mtd_ooblayout_ops tc58cvg0s3hraig_ooblayout = { + .ecc = tc58cvg0s3hraig_ooblayout_ecc, + .free = tc58cvg0s3hraig_ooblayout_free, +}; + +static int tc58cvg0s3hraig_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (status & STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case STATUS_ECC_HAS_BITFLIPS: + /* + * We have no way to know exactly how many bitflips have been + * fixed, so let's return the maximum possible value so that + * wear-leveling layers move the data immediately. + */ + return 7; + + case TOSHIBA_STATUS_ECC_8_BITFLIPS: + /* + * We have no way to know exactly how many bitflips have been + * fixed, so let's return the maximum possible value so that + * wear-leveling layers move the data immediately. + */ + return 8; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info toshiba_spinand_table[] = { + SPINAND_INFO("TC58CVG0S3HRAIG 3.3V", 0xc2, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cvg0s3hraig_ooblayout, + tc58cvg0s3hraig_ecc_get_status)), + + SPINAND_INFO("TC58CYG1S3HRAIG 1.8V", 0xdb, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cvg0s3hraig_ooblayout, + tc58cvg0s3hraig_ecc_get_status)), + + SPINAND_INFO("TC58CVG1S3HRAIG 3.3V", 0xcb, + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tc58cvg0s3hraig_ooblayout, + tc58cvg0s3hraig_ecc_get_status)), +}; + +static int toshiba_spinand_detect(struct spinand_device *spinand) +{ + u8 *id = spinand->id.data; + int ret; + + if (id[0] != SPINAND_MFR_TOSHIBA) + return 0; + + ret = spinand_match_and_init(spinand, toshiba_spinand_table, + ARRAY_SIZE(toshiba_spinand_table), + id[1]); + if (ret) + return ret; + + return 1; +} + +static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { + .detect = toshiba_spinand_detect, +}; + +const struct spinand_manufacturer toshiba_spinand_manufacturer = { + .id = SPINAND_MFR_TOSHIBA, + .name = "Toshiba", + .ops = &toshiba_spinand_manuf_ops, +};
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index eac811d..4d42dac 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c
@@ -18,9 +18,9 @@ #define WINBOND_CFG_BUF_READ BIT(3) static SPINAND_OP_VARIANTS(read_cache_variants, - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + //SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), - SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + //SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); @@ -30,7 +30,7 @@ SPINAND_PROG_LOAD(true, 0, NULL, 0)); static SPINAND_OP_VARIANTS(update_cache_variants, - SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + //SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, @@ -98,15 +98,11 @@ u8 *id = spinand->id.data; int ret; - /* - * Winbond SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. - */ - if (id[1] != SPINAND_MFR_WINBOND) + if (id[0] != SPINAND_MFR_WINBOND) return 0; ret = spinand_match_and_init(spinand, winbond_spinand_table, - ARRAY_SIZE(winbond_spinand_table), id[2]); + ARRAY_SIZE(winbond_spinand_table), id[1]); if (ret) return ret;
diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c new file mode 100644 index 0000000..319b147 --- /dev/null +++ b/drivers/mtd/nand/spi/xtx.c
@@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_XTX 0x0b +#define ZETTA_STATUS_ECC_NO_BITFLIPS (0 << 2) +#define ZETTA_STATUS_ECC_1_BITFLIPS (1 << 2) +#define ZETTA_STATUS_ECC_2_BITFLIPS (2 << 2) +#define ZETTA_STATUS_ECC_3_BITFLIPS (3 << 2) +#define ZETTA_STATUS_ECC_4_BITFLIPS (4 << 2) +#define ZETTA_STATUS_ECC_5_BITFLIPS (5 << 2) +#define ZETTA_STATUS_ECC_6_BITFLIPS (6 << 2) +#define ZETTA_STATUS_ECC_7_BITFLIPS (7 << 2) +#define ZETTA_STATUS_ECC_ECC_UNCOR_ERROR (8 << 2) +#define ZETTA_STATUS_ECC_8_BITFLIPS (0xc << 2) +#define ZETTA_STATUS_ECC_MASK GENMASK(5, 2) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + //SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int ZXT26G01AWSEGA_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 48; + region->length = 16; + + return 0; + +} + +static int ZXT26G01AWSEGA_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* Reserve 2 bytes for the BBM. */ + region->offset = 2; + region->length = 46; + + return 0; +} + +static const struct mtd_ooblayout_ops ZXT26G01AWSEGA_ooblayout = { + .ecc = ZXT26G01AWSEGA_ooblayout_ecc, + .free = ZXT26G01AWSEGA_ooblayout_free, +}; + +static int ZXT26G01AWSEGA_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (status & ZETTA_STATUS_ECC_MASK) { + case ZETTA_STATUS_ECC_NO_BITFLIPS: + return 0; + + case ZETTA_STATUS_ECC_1_BITFLIPS: + return 1; + + case ZETTA_STATUS_ECC_2_BITFLIPS: + return 2; + + case ZETTA_STATUS_ECC_3_BITFLIPS: + return 3; + + case ZETTA_STATUS_ECC_4_BITFLIPS: + return 4; + + case ZETTA_STATUS_ECC_5_BITFLIPS: + return 5; + + case ZETTA_STATUS_ECC_6_BITFLIPS: + return 6; + + case ZETTA_STATUS_ECC_7_BITFLIPS: + return 7; + + case ZETTA_STATUS_ECC_8_BITFLIPS: + return 8; + + case ZETTA_STATUS_ECC_ECC_UNCOR_ERROR: + return -EBADMSG; + + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info xtx_spinand_table[] = { + SPINAND_INFO("XT26G01AWSEGA 3.3V", 0xe1, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ZXT26G01AWSEGA_ooblayout, + ZXT26G01AWSEGA_ecc_get_status)), + + SPINAND_INFO("XT26G02AWSEGA 3.3V", 0xe2, + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ZXT26G01AWSEGA_ooblayout, + ZXT26G01AWSEGA_ecc_get_status)), +}; + +static int xtx_spinand_detect(struct spinand_device *spinand) +{ + u8 *id = spinand->id.data; + int ret; + + if (id[0] != SPINAND_MFR_XTX) + return 0; + + ret = spinand_match_and_init(spinand, xtx_spinand_table, + ARRAY_SIZE(xtx_spinand_table), + id[1]); + if (ret) + return ret; + + return 1; +} + +static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = { + .detect = xtx_spinand_detect, +}; + +const struct spinand_manufacturer xtx_spinand_manufacturer = { + .id = SPINAND_MFR_XTX, + .name = "xtx", + .ops = &xtx_spinand_manuf_ops, +};
diff --git a/drivers/mtd/nand/spi/zetta.c b/drivers/mtd/nand/spi/zetta.c new file mode 100644 index 0000000..a136ed3 --- /dev/null +++ b/drivers/mtd/nand/spi/zetta.c
@@ -0,0 +1,138 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_ZETTA 0xba + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + //SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int ZD35Q1GA_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + /* the ECC parity code can be calculated + * properly and stored in the additional + * hidden spare area + */ + return -ERANGE; +} + +static int ZD35Q1GA_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* Reserve 2 bytes for the BBM. */ + region->offset = 2; + region->length = 62; + + return 0; +} + +static const struct mtd_ooblayout_ops ZD35Q1GA_ooblayout = { + .ecc = ZD35Q1GA_ooblayout_ecc, + .free = ZD35Q1GA_ooblayout_free, +}; + +static int ZD35Q1GA_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + switch (status & STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case STATUS_ECC_HAS_BITFLIPS: + /* + * We have no way to know exactly how many bitflips have been + * fixed, so let's return the maximum possible value so that + * wear-leveling layers move the data immediately. + */ + return 4; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info zetta_spinand_table[] = { + SPINAND_INFO("ZD35Q1GA 3.3V", 0x71, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ZD35Q1GA_ooblayout, + ZD35Q1GA_ecc_get_status)), +#if 0 + SPINAND_INFO("ZD35M1GA 1.8V", 0x21, + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ZD35Q1GA_ooblayout, + ZD35Q1GA_ecc_get_status)), +#endif + SPINAND_INFO("ZD35M2GA 3.3V", 0x72, + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&ZD35Q1GA_ooblayout, + ZD35Q1GA_ecc_get_status)), +}; + +static int zetta_spinand_detect(struct spinand_device *spinand) +{ + u8 *id = spinand->id.data; + int ret; + + if (id[0] != SPINAND_MFR_ZETTA) + return 0; + + ret = spinand_match_and_init(spinand, zetta_spinand_table, + ARRAY_SIZE(zetta_spinand_table), + id[1]); + if (ret) + return ret; + + return 1; +} + +static const struct spinand_manufacturer_ops zetta_spinand_manuf_ops = { + .detect = zetta_spinand_detect, +}; + +const struct spinand_manufacturer zetta_spinand_manufacturer = { + .id = SPINAND_MFR_ZETTA, + .name = "Zetta", + .ops = &zetta_spinand_manuf_ops, +};
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 76d5a1d..b810274 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig
@@ -146,4 +146,14 @@ If unsure, say N +config SPI_FLASH_AML_ADVANCED + bool "SPI Flash meson advanced support" + depends on SPI_FLASH && DM_SPI_FLASH + default n + help + SC2 needs to support a new burning mode (ADVANCED), we implement + it based on the original discrete modem. If say Y enabled ADVANCED + mode, spinor will use DISCRETE mode to burning. + If unsure, say N + endmenu # menu "SPI Flash Support"
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 4f76314..00a179e 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile
@@ -13,5 +13,7 @@ obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o +ifeq ($(CONFIG_SPI_FLASH),y) obj-$(CONFIG_AML_STORAGE) += storage_sf.o obj-$(CONFIG_AML_MTDPART) += sf_partition.o +endif
diff --git a/drivers/mtd/spi/sf_partition.c b/drivers/mtd/spi/sf_partition.c index dc80289..fe9af62 100644 --- a/drivers/mtd/spi/sf_partition.c +++ b/drivers/mtd/spi/sf_partition.c
@@ -16,11 +16,24 @@ #include <linux/errno.h> #include <mtd.h> #include <amlogic/aml_mtd.h> +#include <amlogic/storage.h> -#define SPINOR_BOOTLOADER_SIZE (SZ_1M) +/* Hard code, all partitions are aligned in block size, fast erasing */ +#define SPINOR_ALIGNED_SIZE (64 * 1024) +extern struct storage_startup_parameter g_ssp; + +/* do not use default value, rewrite this function in the board file */ +uint64_t __weak spiflash_bootloader_size(void) +{ + return SZ_2M; +} + +uint32_t __weak spiflash_rsv_block_num(void) +{ + return 0; +} + /* The size of the partition must be block aligned */ -#define SPINOR_RSV_BLOCK_NUM (32) //128k - static int _spinor_add_partitions(struct mtd_info *mtd, const struct mtd_partition *parts, int nbparts) @@ -28,32 +41,58 @@ int part_num = 0, i = 0; struct mtd_partition *temp, *parts_nm; loff_t off; + #ifdef CONFIG_DISCRETE_BOOTLOADER - part_num = nbparts + 2; + /* spinor add discrete mode for advanced */ + part_num = nbparts + 5; #else part_num = nbparts + 1; #endif/* CONFIG_DISCRETE_BOOTLOADER */ temp = kzalloc(sizeof(*temp) * part_num, GFP_KERNEL); memset(temp, 0, sizeof(*temp) * part_num); +#ifdef CONFIG_DISCRETE_BOOTLOADER + temp[BOOT_AREA_BB1ST].name = BOOT_LOADER; + temp[BOOT_AREA_BB1ST].offset = g_ssp.boot_entry[BOOT_AREA_BB1ST].offset; + temp[BOOT_AREA_BB1ST].size = g_ssp.boot_entry[BOOT_AREA_BB1ST].size * g_ssp.boot_bakups; + if (temp[BOOT_AREA_BB1ST].size % SPINOR_ALIGNED_SIZE) + WARN_ON(1); + + temp[BOOT_AREA_BL2E].name = BOOT_BL2E; + temp[BOOT_AREA_BL2E].offset = g_ssp.boot_entry[BOOT_AREA_BL2E].offset; + temp[BOOT_AREA_BL2E].size = g_ssp.boot_entry[BOOT_AREA_BL2E].size * g_ssp.boot_bakups; + if (temp[0].size % SPINOR_ALIGNED_SIZE) + WARN_ON(1); + + temp[BOOT_AREA_BL2X].name = BOOT_BL2X; + temp[BOOT_AREA_BL2X].offset = g_ssp.boot_entry[BOOT_AREA_BL2X].offset; + temp[BOOT_AREA_BL2X].size = g_ssp.boot_entry[BOOT_AREA_BL2X].size * g_ssp.boot_bakups; + if (temp[0].size % SPINOR_ALIGNED_SIZE) + WARN_ON(1); + + temp[BOOT_AREA_DDRFIP].name = BOOT_DDRFIP; + temp[BOOT_AREA_DDRFIP].offset = g_ssp.boot_entry[BOOT_AREA_DDRFIP].offset; + temp[BOOT_AREA_DDRFIP].size = g_ssp.boot_entry[BOOT_AREA_DDRFIP].size * g_ssp.boot_bakups; + if (temp[0].size % SPINOR_ALIGNED_SIZE) + WARN_ON(1); + + temp[BOOT_AREA_DEVFIP].name = BOOT_DEVFIP; + temp[BOOT_AREA_DEVFIP].offset = g_ssp.boot_entry[BOOT_AREA_DEVFIP].offset; + temp[BOOT_AREA_DEVFIP].size = g_ssp.boot_entry[BOOT_AREA_DEVFIP].size * CONFIG_TPL_COPY_NUM; + if (temp[0].size % SPINOR_ALIGNED_SIZE) + WARN_ON(1); + off = temp[BOOT_AREA_DEVFIP].offset + temp[BOOT_AREA_DEVFIP].size; + parts_nm = &temp[5]; +#else temp[0].name = BOOT_LOADER; temp[0].offset = 0; - /* fixme, yyh */ - temp[0].size = SPINOR_BOOTLOADER_SIZE; - if (temp[0].size % mtd->erasesize) + temp[0].size = spiflash_bootloader_size(); + if (temp[0].size % SPINOR_ALIGNED_SIZE) WARN_ON(1); - off = temp[0].size + SPINOR_RSV_BLOCK_NUM * mtd->erasesize; -#ifdef CONFIG_DISCRETE_BOOTLOADER - temp[1].name = BOOT_TPL; - temp[1].offset = off; - temp[1].size = CONFIG_TPL_SIZE_PER_COPY * CONFIG_TPL_COPY_NUM; - if (temp[1].size % mtd->erasesize) - WARN_ON(1); - parts_nm = &temp[2]; - off += temp[1].size; -#else + /* rsv size is aligned with blocksize(64K) */ + off = temp[0].size + spiflash_rsv_block_num() * SPINOR_ALIGNED_SIZE; parts_nm = &temp[1]; #endif/* CONFIG_DISCRETE_BOOTLOADER */ - for (; i < nbparts; i++) { + for (i = 0; i < nbparts; i++) { if (!parts[i].name) { pr_err("name can't be null! "); pr_err("please check your %d th partition name!\n", @@ -67,10 +106,10 @@ } parts_nm[i].name = parts[i].name; parts_nm[i].offset = off; - if (parts[i].size % mtd->erasesize) { + if (parts[i].size % SPINOR_ALIGNED_SIZE) { pr_err("%s %d \"%s\" size auto align to block size\n", __func__, __LINE__, parts[i].name); - parts_nm[i].size += parts[i].size % mtd->erasesize; + parts_nm[i].size += parts[i].size % SPINOR_ALIGNED_SIZE; } /* it's ok "+=" here because size has been set to 0 */ parts_nm[i].size += parts[i].size; @@ -78,6 +117,7 @@ if (i == (nbparts - 1)) parts_nm[i].size = mtd->size - off; } + return add_mtd_partitions(mtd, temp, part_num); }
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 940b2ab..761833f 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c
@@ -49,7 +49,8 @@ goto err_read_id; #ifdef CONFIG_SPI_FLASH_MTD - ret = spi_flash_mtd_register(flash); + /* for advanced support */ + //ret = spi_flash_mtd_register(flash); #ifdef CONFIG_AML_STORAGE if (!ret) ret = spi_flash_fit_storage(flash);
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 6738795..57509d2 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c
@@ -430,7 +430,7 @@ } #ifndef CONFIG_AML_SPIFCV2 -static int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, +int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, size_t len, const void *buf) #else static int _spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, @@ -1402,8 +1402,8 @@ print_size(flash->size, ""); if (flash->memory_map) printf(", mapped at %p", flash->memory_map); - printf(" erase_cmd = 0x%x read_cmd = 0x%x write_cmd = 0x%x\n", - flash->erase_cmd, flash->read_cmd, flash->write_cmd); + printf(" erase_cmd = 0x%x read_cmd = 0x%x write_cmd = 0x%x\n", + flash->erase_cmd, flash->read_cmd, flash->write_cmd); puts("\n"); #endif
diff --git a/drivers/mtd/spi/storage_sf.c b/drivers/mtd/spi/storage_sf.c index 7565aca..5ec9460 100644 --- a/drivers/mtd/spi/storage_sf.c +++ b/drivers/mtd/spi/storage_sf.c
@@ -13,6 +13,8 @@ #include "sf_internal.h" struct storage_t *snor_storage; +static struct spi_flash *spi_flash; + extern const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash); #ifdef CONFIG_MTD_LOGIC_MAP @@ -32,6 +34,16 @@ return snor_storage; } +inline void set_spi_flash(struct spi_flash *snor) +{ + spi_flash = snor; +} + +inline struct storage_t *get_spi_flash(void) +{ + return spi_flash; +} + int spi_flash_fit_storage(struct spi_flash *flash) { const struct spi_flash_info *info = NULL; @@ -70,29 +82,57 @@ int spi_nor_pre(void) { - return 0; -} - -int spi_nor_probe(u32 init_flag) -{ - u32 bus = 0, cs = 0, speed = 0x40000000, mode = 0; - struct spi_flash *flash = NULL; + u32 bus = 0, cs = 0, speed = 0, mode = 0; struct storage_t *spi_nor = get_snor_storage(); + struct spi_flash *flash = NULL; - if (spi_nor) { - spi_nor->init_flag = init_flag; + if (spi_nor) return 0; - } + flash = spi_flash_probe(bus, cs, speed, mode); if (!flash) { debug("spi flash probe fail!\n"); return 1; } - spi_nor = get_snor_storage(); - if (!spi_nor) { - debug("can not get spi nor!\n"); + + set_spi_flash(flash); + + printf("storage-sf mode 0x%x, speed %dHz\n", flash->spi->mode, + flash->spi->max_hz); + + return 0; +} + +int spi_nor_probe(u32 init_flag) +{ + static int probe_flag; + struct storage_t *spi_nor = NULL; + struct spi_flash *flash = NULL; + int ret; + + if (probe_flag) + return 0; + + flash = get_spi_flash(); + if (!flash) { + printf("get spi flash fail!\n"); return 1; } + + ret = spi_flash_mtd_register(flash); + if (ret) { + printf("spi flash mtd register fail!\n"); + return 1; + } + + spi_nor = get_snor_storage(); + if (!spi_nor) { + printf("can not get spi nor!\n"); + return 1; + } + spi_nor->init_flag = init_flag; + probe_flag = 1; + return 0; }
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 6166a3c..cf84783 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig
@@ -21,12 +21,6 @@ if MTD_UBI -config MTD_PARTITIONS - bool "Enable mtd part" - default y - help - Sometimes user want partitions their mtd device, it't helpful to their management and operates their storage device in logic partition, enable this, mtd driver will support partitions. - config MTD_UBI_WL_THRESHOLD int "UBI wear-leveling threshold" default 4096
diff --git a/drivers/nand/dev/amlnf_config.c b/drivers/nand/dev/amlnf_config.c index 92f5135..a203193 100644 --- a/drivers/nand/dev/amlnf_config.c +++ b/drivers/nand/dev/amlnf_config.c
@@ -223,7 +223,7 @@ memcpy(amlnand_config[i].name, part_table[i].name, MAX_PART_NAME_LEN); amlnand_config[i].size = part_table[i].size; amlnand_config[i].offset = part_table[i].offset; - amlnand_config[i].mask_flags = part_table[i].mask_flags; + amlnand_config[i].mask_flags = (part_table[i].mask_flags & 0x0f); if (amlnand_config[i].mask_flags == STORE_CACHE) { aml_chip->h_cache_dev = 1;/*have cache dev*/
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index a860a0c..25f9b44 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c
@@ -27,20 +27,39 @@ #ifdef CONFIG_DM_ETH #include <asm/arch/pwr_ctrl.h> +#include <asm/arch/register.h> +#include <dm/pinctrl.h> +#ifdef CONFIG_DM_GPIO +#include <asm/gpio.h> +#endif +struct dw_eth_dev *priv_tool = NULL; + +#ifndef ANACTRL_PLL_GATE_DIS +#define ANACTRL_PLL_GATE_DIS 0xffffffff #endif -#define ETH_PLL_CTL0 0x44 -#define ETH_PLL_CTL1 0x48 -#define ETH_PLL_CTL2 0x4C -#define ETH_PLL_CTL3 0x50 -#define ETH_PLL_CTL4 0x54 -#define ETH_PLL_CTL5 0x58 -#define ETH_PLL_CTL6 0x5C -#define ETH_PLL_CTL7 0x60 +#endif -#define ETH_PHY_CNTL0 0x80 -#define ETH_PHY_CNTL1 0x84 -#define ETH_PHY_CNTL2 0x88 +#define AML_ETH_PLL_CTL0 0x44 +#define AML_ETH_PLL_CTL1 0x48 +#define AML_ETH_PLL_CTL2 0x4C +#define AML_ETH_PLL_CTL3 0x50 +#define AML_ETH_PLL_CTL4 0x54 +#define AML_ETH_PLL_CTL5 0x58 +#define AML_ETH_PLL_CTL6 0x5C +#define AML_ETH_PLL_CTL7 0x60 + +#define AML_ETH_PHY_CNTL0 0x80 +#define AML_ETH_PHY_CNTL1 0x84 +#define AML_ETH_PHY_CNTL2 0x88 + +enum { + /* chip num */ + ETH_PHY = 0x0, + ETH_PHY_C1 = 0x1, + ETH_PHY_C2 = 0x2, + ETH_PHY_SC2 = 0x3, +}; static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { @@ -703,8 +722,9 @@ { int phy_cntl1 = 0; int mc_val = 0; - int pll_val[3] = {0}; - int analog_val[3] = {0}; + int chip_num = 0; + unsigned int pll_val[3] = {0}; + unsigned int analog_val[3] = {0}; int rtn = 0; struct resource eth_top, eth_cfg; @@ -718,6 +738,13 @@ printf("miss mc_val\n"); } + chip_num = dev_read_u32_default(dev, "chip_num", 4); + if (chip_num < 0) { + chip_num = 0; + printf("use 0 as default chip num\n"); + } + printf("chip num %d\n", chip_num); + rtn = dev_read_u32_array(dev, "pll_val", pll_val, ARRAY_SIZE(pll_val)); if (rtn < 0) { printf("miss pll_val\n"); @@ -745,67 +772,122 @@ if (rtn) { printf("can't get eth_cfg resource(ret = %d)\n", rtn); } - printf("wzh eth_top 0x%x eth_cfg 0x%x \n", eth_top.start, eth_cfg.start); +// printf("wzh eth_top 0x%x eth_cfg 0x%x \n", eth_top.start, eth_cfg.start); setup_tx_amp(dev); /*top*/ // setbits_le32(ETHTOP_CNTL0, mc_val); setbits_le32(eth_top.start, mc_val); /*pll*/ - writel(pll_val[0] | 0x30000000, eth_cfg.start + ETH_PLL_CTL0); - writel(pll_val[1], eth_cfg.start + ETH_PLL_CTL1); - writel(pll_val[2], eth_cfg.start + ETH_PLL_CTL2); - writel(0x00000000, eth_cfg.start + ETH_PLL_CTL3); + writel(pll_val[0] | 0x30000000, eth_cfg.start + AML_ETH_PLL_CTL0); + writel(pll_val[1], eth_cfg.start + AML_ETH_PLL_CTL1); + writel(pll_val[2], eth_cfg.start + AML_ETH_PLL_CTL2); + writel(0x00000000, eth_cfg.start + AML_ETH_PLL_CTL3); udelay(200); - writel(pll_val[0] | 0x10000000, eth_cfg.start + ETH_PLL_CTL0); + writel(pll_val[0] | 0x10000000, eth_cfg.start + AML_ETH_PLL_CTL0); /*analog*/ - writel(analog_val[0], eth_cfg.start + ETH_PLL_CTL5); - writel(analog_val[1], eth_cfg.start + ETH_PLL_CTL6); - writel(analog_val[2], eth_cfg.start + ETH_PLL_CTL7); + writel(analog_val[0], eth_cfg.start + AML_ETH_PLL_CTL5); + writel(analog_val[1], eth_cfg.start + AML_ETH_PLL_CTL6); + writel(analog_val[2], eth_cfg.start + AML_ETH_PLL_CTL7); /*ctrl*/ /*config phyid should between a 0~0xffffffff*/ /*please don't use 44000181, this has been used by internal phy*/ - writel(0x33000180, eth_cfg.start + ETH_PHY_CNTL0); + writel(0x33000180, eth_cfg.start + AML_ETH_PHY_CNTL0); /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/ - writel(0x260, eth_cfg.start + ETH_PHY_CNTL2); - writel(phy_cntl1, eth_cfg.start + ETH_PHY_CNTL1); - writel(phy_cntl1 & (~0x40000), eth_cfg.start + ETH_PHY_CNTL1); - writel(phy_cntl1, eth_cfg.start + ETH_PHY_CNTL1); + writel(0x260, eth_cfg.start + AML_ETH_PHY_CNTL2); + writel(phy_cntl1, eth_cfg.start + AML_ETH_PHY_CNTL1); + writel(phy_cntl1 & (~0x40000), eth_cfg.start + AML_ETH_PHY_CNTL1); + writel(phy_cntl1, eth_cfg.start + AML_ETH_PHY_CNTL1); udelay(200); - - clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 6)); - clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 7)); - clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 19)); + if (chip_num != ETH_PHY_SC2) { + clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 6)); + clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 7)); + clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 19)); + } } static void setup_external_phy(struct udevice *dev) { -#if 0 - u32 mc_val; + int mc_val = 0; + int cali_val = 0; + int analog_ver = 0; + int chip_num = 0; + int rtn = 0; + struct resource eth_top, eth_cfg; + /*reset phy*/ + struct gpio_desc desc; + int ret; - /*driver strength*/ - writel(0xaaaaaaa5, P_PAD_DS_REG4A); + chip_num = dev_read_u32_default(dev, "chip_num", 4); + if (chip_num < 0) { + chip_num = 0; + printf("use 0 as default chip num\n"); + } + printf("chip num %d\n", chip_num); - /*pinmux*/ - writel(0x11111111, P_PERIPHS_PIN_MUX_6); - writel(0x111111, P_PERIPHS_PIN_MUX_7); + if (chip_num != ETH_PHY_SC2) { + ret = gpio_request_by_name(dev, "reset-gpios", 0, &desc, GPIOD_IS_OUT); + if (ret) { + printf("request gpio failed!\n"); + // return ret; + } + if (dm_gpio_is_valid(&desc)) { + dm_gpio_set_value(&desc, 1); + mdelay(100); + } + dm_gpio_free(dev, &desc); + } - /*top*/ mc_val = dev_read_u32_default(dev, "mc_val", 4); - debug("mc_val = 0x%x\n", mc_val); - setbits_le32(P_PREG_ETH_REG0, mc_val); + if (mc_val < 0) { + printf("miss mc_val\n"); + } - /*switch to exphy*/ - writel(0x0, P_ETH_PHY_CNTL2); - /*81*/ - setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3); - /* power on memory */ - clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2)); -#endif + cali_val = dev_read_u32_default(dev, "cali_val", 4); + if (mc_val < 0) { + printf("miss cali_val\n"); + } + + /*set rmii pinmux*/ + if (mc_val & 0x4) { + pinctrl_select_state(dev, "external_eth_rmii_pins"); + printf("set rmii\n"); + } + /*set rgmii pinmux*/ + if (mc_val & 0x1) { + pinctrl_select_state(dev, "external_eth_rgmii_pins"); + printf("set rgmii\n"); + } + rtn = dev_read_resource_byname(dev, "eth_top", ð_top); + if (rtn) { + printf("can't get eth_top resource(ret = %d)\n", rtn); + } + + rtn = dev_read_resource_byname(dev, "eth_cfg", ð_cfg); + if (rtn) { + printf("can't get eth_cfg resource(ret = %d)\n", rtn); + } +// printf("eth_top 0x%x eth_cfg 0x%x \n", eth_top.start, eth_cfg.start); + + setbits_le32(eth_top.start, mc_val); + setbits_le32(eth_top.start + 4, cali_val); + + analog_ver = dev_read_u32_default(dev, "analog_ver", 4); + if (mc_val < 0) { + printf("miss analog_ver\n"); + } + if (analog_ver != 2) + writel(0x0, eth_cfg.start + AML_ETH_PHY_CNTL2); + + if (chip_num != ETH_PHY_SC2) { + clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 6)); + clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 7)); + clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 19)); + } } #endif @@ -827,6 +909,7 @@ setup_external_phy(dev); } udelay(1000); + return 0; } #endif /*parse dts end*/ @@ -924,6 +1007,9 @@ ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); +#ifdef CONFIG_DM_ETH + priv_tool = priv; +#endif return ret; #ifdef CONFIG_CLK @@ -951,6 +1037,63 @@ #endif } +/* amlogic debug cmd start */ +/*********************ethernet debug function****************************/ +static int do_phyreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int reg, value; + unsigned char *cmd = NULL; + unsigned int i; + + if (argc < 2) { + return cmd_usage(cmdtp); + } + + if (priv_tool == NULL || priv_tool->phydev == NULL) { + return -1; + } + + cmd = (unsigned char *)argv[1]; + switch (*cmd) { + case 'd': + printf("=== ethernet phy register dump:\n"); + for (i = 0; i < 32; i++) + printf("[reg_%d] 0x%x\n", i, phy_read(priv_tool->phydev, MDIO_DEVAD_NONE, i)); + break; + case 'r': + if (argc != 3) { + return cmd_usage(cmdtp); + } + printf("=== ethernet phy register read:\n"); + reg = simple_strtoul(argv[2], NULL, 10); + printf("[reg_%d] 0x%x\n", reg, phy_read(priv_tool->phydev, MDIO_DEVAD_NONE, reg)); + + break; + case 'w': + if (argc != 4) { + return cmd_usage(cmdtp); + } + printf("=== ethernet phy register write:\n"); + reg = simple_strtoul(argv[2], NULL, 10); + value = simple_strtoul(argv[3], NULL, 16); + phy_write(priv_tool->phydev, MDIO_DEVAD_NONE, reg, value); + printf("[reg_%d] 0x%x\n", reg, phy_read(priv_tool->phydev, MDIO_DEVAD_NONE, reg)); + break; + + default: + return cmd_usage(cmdtp); + } + + return 0; +} + +U_BOOT_CMD( + phyreg, 4, 1, do_phyreg, + "ethernet phy register read/write/dump", + "d - dump phy registers\n" + " r reg - read phy register\n" + " w reg val - write phy register" +); const struct eth_ops designware_eth_ops = { .start = designware_eth_start, .send = designware_eth_send,
diff --git a/drivers/phy/phy-aml-usb2.c b/drivers/phy/phy-aml-usb2.c index f4389f9..d1ff67e 100644 --- a/drivers/phy/phy-aml-usb2.c +++ b/drivers/phy/phy-aml-usb2.c
@@ -8,7 +8,6 @@ #include <bitfield.h> #include <dm.h> #include <errno.h> -#include <generic-phy.h> #include <regmap.h> #include <power/regulator.h> #include <clk.h> @@ -18,155 +17,12 @@ #include <linux/compat.h> #include <linux/ioport.h> -#define P_AO_RTI_GEN_PWR_SLEEP0 0xfe007808 -#define P_AO_RTI_GEN_PWR_ISO0 0xfe007804 -#define P_HHI_MEM_PD_REG0 0xfe007850 -//#define MESON_CPU_MAJOR_ID_C1 0x30 - #define RESET_COMPLETE_TIME 500 -char name[32]; - -struct phy_aml_usb2_priv { - /* controller */ - unsigned int base_addr; - unsigned int reset_addr; - /* role */ - int id_mode; - /* vbus call back */ - unsigned int usb_phy2_base_addr; - unsigned int u2_port_num; - unsigned int usbphy_reset_bit[8]; - unsigned int usbctrl_reset_bit; - unsigned int u2_ctrl_sleep_shift; - unsigned int u2_hhi_mem_pd_mask; - unsigned int u2_ctrl_iso_shift; - unsigned int u2_hhi_mem_pd_shift; - unsigned int clktree_usb_bus_ctrl; - unsigned int usb_phy2_pll_base_addr[4]; -}; - -static int Rev_flag = 0; - -/*Rev_flag == 0XB, g12b and revB, tl1 */ -/*Rev_flag == 1, sm1 */ -static void phy_aml_usb2_check_rev (void) -{ - cpu_id_t cpu_id = get_cpu_id(); - - if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) { - if (cpu_id.chip_rev == 0xb) - Rev_flag = 0xb; - else - Rev_flag = 0; - } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1) { - Rev_flag = MESON_CPU_MAJOR_ID_SM1; - } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_A1) { - Rev_flag = MESON_CPU_MAJOR_ID_A1; - } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) { - Rev_flag = MESON_CPU_MAJOR_ID_C1; - } - return; -} - -static int phy_aml_usb2_get_rev_type (void) -{ - int val = 0; - - switch (Rev_flag) { - case MESON_CPU_MAJOR_ID_SM1: - case MESON_CPU_MAJOR_ID_A1: - case MESON_CPU_MAJOR_ID_C1: - case 0xb: - val = 1; - break; - default: - printk("amlogic usb phy need tuning\n"); - val = 0; - break; - } - - return val; -} - -static void set_usb_pll(struct phy *phy, uint32_t volatile *phy2_pll_base) -{ - unsigned int pll_set1, pll_set2, pll_set3; - unsigned int tuning_disconnect_threshold = 0x34; - - dev_read_u32(phy->dev, "pll-setting-1", &pll_set1); - dev_read_u32(phy->dev, "pll-setting-2", &pll_set2); - dev_read_u32(phy->dev, "pll-setting-3", &pll_set3); - debug("pll1=0x%08x, pll2=0x%08x, pll-setting-3 =0x%08x\n", - pll_set1, pll_set2, pll_set3); - - (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40)) - = (pll_set1 | USB_PHY2_RESET | USB_PHY2_ENABLE); - (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) = - pll_set2; - (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) = - pll_set3; - udelay(100); - (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40)) - = (((pll_set1) | (USB_PHY2_ENABLE)) - & (~(USB_PHY2_RESET))); - - dev_read_u32(phy->dev, "disconnect-threshold", &tuning_disconnect_threshold); - (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) = - tuning_disconnect_threshold; - debug("tuning_disconnect_threshold=0x%x\n", tuning_disconnect_threshold); -} - -static int phy_aml_usb2_phy_init(struct phy *phy) -{ - struct u2p_aml_regs *u2p_aml_reg; +static int usb_get_priv_data (struct phy *phy){ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev); - u2p_r0_t dev_u2p_r0; - u2p_r1_t dev_u2p_r1; - int i; - int cnt, node, rev_type; - int time_dly = RESET_COMPLETE_TIME; - int usbphy_reset_bit[8] = {0}; - int usbctrl_reset_bit; - int u2_sleep_shift; - int u2_mem_pd_mask; - int u2_iso_shift; - int u2_pd_shift; - unsigned int u2portnum = 0; - - phy_aml_usb2_check_rev(); - rev_type = phy_aml_usb2_get_rev_type(); - if (rev_type && (Rev_flag != 0xb)) { - u2_sleep_shift = dev_read_u32_default(phy->dev, "u2-ctrl-sleep-shift", -1); - if (u2_sleep_shift != -1) - priv->u2_ctrl_sleep_shift = u2_sleep_shift; - else - goto sm1erro; - - u2_pd_shift = dev_read_u32_default(phy->dev, "u2-hhi-mem-pd-shift", -1); - if (u2_pd_shift != -1) - priv->u2_hhi_mem_pd_shift = u2_pd_shift; - else - goto sm1erro; - - u2_mem_pd_mask = dev_read_u32_default(phy->dev, "u2-hhi-mem-pd-mask", -1); - if (u2_mem_pd_mask != -1) - priv->u2_hhi_mem_pd_mask = u2_mem_pd_mask; - else - goto sm1erro; - - u2_iso_shift = dev_read_u32_default(phy->dev, "u2-ctrl-iso-shift", -1); - if (u2_iso_shift != -1) - priv->u2_ctrl_iso_shift = u2_iso_shift; - else - goto sm1erro; - writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << priv->u2_ctrl_sleep_shift))), - P_AO_RTI_GEN_PWR_SLEEP0); - writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << priv->u2_ctrl_iso_shift))), - P_AO_RTI_GEN_PWR_ISO0); - writel((readl(P_HHI_MEM_PD_REG0) - & (~(priv->u2_hhi_mem_pd_mask << priv->u2_hhi_mem_pd_shift))), P_HHI_MEM_PD_REG0); - } + unsigned int dwc2_reg, u2portnum = 0; + int ret, i; priv->reset_addr = dev_read_addr_index(phy->dev, 1); if (priv->reset_addr == FDT_ADDR_T_NONE) { @@ -177,34 +33,12 @@ dev_read_u32(phy->dev, "portnum", &u2portnum); priv->u2_port_num = u2portnum; - priv->clktree_usb_bus_ctrl = dev_read_addr_index(phy->dev, 2 + u2portnum); - if (priv->clktree_usb_bus_ctrl == FDT_ADDR_T_NONE) { - pr_err("Coun't get clktree_usb_bus_ctrl addr index %d\n", 2 + u2portnum); - } else { - if (Rev_flag == MESON_CPU_MAJOR_ID_C1) - *(volatile unsigned int *)priv->clktree_usb_bus_ctrl = (1 << 8) | (2 << 9) | (9 << 0); - else - *(volatile unsigned int *)priv->clktree_usb_bus_ctrl = (1 << 8) | (1 << 9) | (0 << 0); + ret = dev_read_u32(phy->dev, "dwc2_a_reg", &dwc2_reg); + if (ret) { + pr_err("Coun't get dwc2_a_reg!!!!\n"); + return -1; } - - usbctrl_reset_bit = dev_read_u32_default(phy->dev, "usb-reset-bit", -1); - if (usbctrl_reset_bit != -1) - priv->usbctrl_reset_bit = usbctrl_reset_bit; - else - priv->usbctrl_reset_bit = 2; - *(volatile unsigned int *)priv->reset_addr = (1 << priv->usbctrl_reset_bit); - - udelay(time_dly); - - for (i = 0; i < u2portnum; i++) { - memset(name, 0, 32 * sizeof(char)); - sprintf(name, "phy2%d-reset-level-bit", i); - usbphy_reset_bit[i] = dev_read_u32_default(phy->dev, name, -1); - if (usbphy_reset_bit[i] != -1) - priv->usbphy_reset_bit[i] = usbphy_reset_bit[i]; - else - priv->usbphy_reset_bit[i] = 16 + i; - } + priv->dwc2_a_addr = dwc2_reg; for (i = 2; i < (u2portnum + 2); i++) { priv->usb_phy2_pll_base_addr[i-2] = dev_read_addr_index(phy->dev, i); @@ -219,88 +53,35 @@ debug("usb2 phy: portnum=%d, addr1= 0x%08x, addr2= 0x%08x\n", u2portnum, priv->usb_phy2_pll_base_addr[0], priv->usb_phy2_pll_base_addr[1]); + debug("dwc2_a base addr: 0x%08x\n", priv->dwc2_a_addr); - for (i = 0; i < u2portnum; i++) { - u2p_aml_reg = (struct u2p_aml_regs *)((ulong)priv->base_addr + i * PHY_REGISTER_SIZE); - dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0; - dev_u2p_r0.b.host_device= 1; - dev_u2p_r0.b.POR= 0; - u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32; - udelay(10); - *(volatile unsigned int *)priv->reset_addr = (1 << priv->usbphy_reset_bit[i]); - udelay(50); - - /* wait for phy ready */ - dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; - cnt = 0; - while (dev_u2p_r1.b.phy_rdy != 1) { - dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1; - /*we wait phy ready max 1ms, common is 100us*/ - if (cnt > 200) - break; - else { - cnt++; - udelay(5); - } - } - } - - for (i = 0; i < u2portnum; i++) { - debug("------set usb pll\n"); - set_usb_pll(phy, priv->usb_phy2_pll_base_addr[i]); - } return 0; -sm1erro: - pr_err("Coun't get sm1 power shift parmeters\n"); - return -1; + } -static void phy_aml_usb2_reset(struct phy_aml_usb2_priv *priv) +static int phy_aml_usb2_getinfo(struct phy *phy) { - return; + return usb_get_priv_data(phy); } -static int phy_aml_usb2_tuning(struct phy *phy, int port) +static int phy_aml_usb2_phy_init(struct phy *phy) { + int ret = -1; + ret = usb_get_priv_data(phy); + if (ret !=0) + return ret; + + return usb2_phy_init(phy); +} + +static int phy_aml_usb2_tuning(struct phy *phy, int port) { struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev); unsigned long phy_reg_base; - unsigned int pll_set1, pll_set2, pll_set3, pll_set4; - unsigned int rev_type = 0; - - if (port > 2) - return 0; - - dev_read_u32(phy->dev, "pll-setting-4", &pll_set1); - dev_read_u32(phy->dev, "pll-setting-5", &pll_set2); - dev_read_u32(phy->dev, "pll-setting-7", &pll_set4); - dev_read_u32(phy->dev, "pll-setting-6", &pll_set3); - - debug("pll1=0x%08x, pll2=0x%08x, pll-setting-3 =0x%08x\n", - pll_set2, pll_set1, pll_set3); - phy_reg_base = priv->usb_phy2_pll_base_addr[port]; - - rev_type = phy_aml_usb2_get_rev_type(); - if (rev_type) { - (*(volatile uint32_t *)(phy_reg_base + 0x50)) = pll_set1; - (*(volatile uint32_t *)(phy_reg_base + 0x54)) = 0x2a; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set3 & (0x1f << 16); + if (phy_reg_base == 0) return 0; - } - - (*(volatile uint32_t *)(phy_reg_base + 0x10)) = pll_set2; - (*(volatile uint32_t *)(phy_reg_base + 0x50)) = pll_set1; - (*(volatile uint32_t *)(phy_reg_base + 0x38)) = pll_set4; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set3; - return 0; -} - - -static void -phy_aml_usb2_set_host_mode(struct phy_aml_usb2_priv *priv) -{ - return; + return usb2_phy_tuning(phy_reg_base, port); } static int phy_aml_usb2_power_on(struct phy *phy) @@ -318,9 +99,10 @@ .power_on = phy_aml_usb2_power_on, .power_off = phy_aml_usb2_power_off, .tuning = phy_aml_usb2_tuning, + .getinfo = phy_aml_usb2_getinfo, }; -int phy_aml_usb2_probe(struct udevice *dev) +static int phy_aml_usb2_probe(struct udevice *dev) { return 0; } @@ -330,7 +112,7 @@ { } }; -U_BOOT_DRIVER(meson_gxl_usb2_phy) = { +U_BOOT_DRIVER(meson_usb2_phy) = { .name = "amlogic_new_usb2_phy", .id = UCLASS_PHY, .of_match = phy_aml_usb2_phy_ids,
diff --git a/drivers/phy/phy-aml-usb3.c b/drivers/phy/phy-aml-usb3.c index e62f539..106ed88 100644 --- a/drivers/phy/phy-aml-usb3.c +++ b/drivers/phy/phy-aml-usb3.c
@@ -13,64 +13,83 @@ #include <clk.h> #include <asm/arch/usb.h> #include <linux/libfdt.h> -//#include <asm/gpio.h> #include <asm-generic/gpio.h> #include <linux/compat.h> #include <linux/bitfield.h> -struct phy_aml_usb3_priv { - unsigned int base_addr; - unsigned int usb3_port_num; -}; +static int phy_aml_usb3_power_info(struct phy *phy){ +#ifdef CONFIG_DM_GPIO + int ret; + //struct gpio_desc desc; + const char *usb_vbus_gpioname; + const void *fdt = gd->fdt_blob; + struct phy_aml_usb3_priv *priv = dev_get_priv(phy->dev); -static int -phy_aml_usb3_set_host_mode(struct phy_aml_usb3_priv *priv) -{ - return 0; + usb_vbus_gpioname = fdt_getprop(fdt, dev_of_offset(phy->dev), "gpio-vbus-power", NULL); + debug("usb_vbus_gpioname=%s\n", usb_vbus_gpioname); + + ret = dm_gpio_lookup_name(usb_vbus_gpioname, &priv->desc); + if (ret) { + printf("%s: not found\n", usb_vbus_gpioname); + return ret; + } + + ret = dm_gpio_request(&priv->desc, usb_vbus_gpioname); + if (ret) { + dm_gpio_free(phy->dev, &priv->desc); + dm_gpio_request(&priv->desc, usb_vbus_gpioname); + pr_info("%s: after usb stop, retry request gpio\n", + usb_vbus_gpioname); + } + + ret = dm_gpio_set_dir_flags(&priv->desc, GPIOD_IS_OUT); + if (ret) { + pr_err("%s: failed to set direction\n", usb_vbus_gpioname); + return ret; + } +#endif + return 0; } static int phy_aml_usb3_power_on(struct phy *phy){ #ifdef CONFIG_DM_GPIO int ret; - struct gpio_desc desc; - const char *usb_vbus_gpioname; - const void *fdt = gd->fdt_blob; + struct phy_aml_usb3_priv *priv = dev_get_priv(phy->dev); - usb_vbus_gpioname = fdt_getprop(fdt, dev_of_offset(phy->dev), "gpio-vbus-power", NULL); - debug("usb_vbus_gpioname=%s\n", usb_vbus_gpioname); - - ret = dm_gpio_lookup_name(usb_vbus_gpioname, &desc); - if (ret) { - printf("%s: not found\n", usb_vbus_gpioname); + ret = phy_aml_usb3_power_info(phy); + if (ret) return 0; - } - ret = dm_gpio_request(&desc, usb_vbus_gpioname); - if (ret) { - dm_gpio_free(phy->dev, &desc); - dm_gpio_request(&desc, usb_vbus_gpioname); - pr_info("%s: after usb stop, retry request gpio\n", - usb_vbus_gpioname); - } - - ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); - if (ret) { - pr_err("%s: failed to set direction\n", usb_vbus_gpioname); - return 0; - } - - dm_gpio_set_value(&desc, 1); + if (priv) + dm_gpio_set_value(&priv->desc, 1); #endif return 0; } - static int phy_aml_usb3_power_off(struct phy *phy) { return 0; } +static int phy_aml_usb3_getinfo(struct phy *phy) +{ + unsigned int u3portnum; + struct phy_aml_usb3_priv *priv = dev_get_priv(phy->dev); + + dev_read_u32(phy->dev, "portnum", &u3portnum); + priv->usb3_port_num = u3portnum; + + priv->base_addr = dev_read_addr(phy->dev); + if (priv->base_addr == FDT_ADDR_T_NONE) { + pr_err("Coun't get usb3 base addr\n"); + return -1; + } + + phy_aml_usb3_power_info(phy); + return 0; +} + static int phy_aml_usb3_init(struct phy *phy) { usb_r1_t r1 = {.d32 = 0}; @@ -103,7 +122,7 @@ } for (i = 0; i < u3portnum; i++) { - usb_aml_reg = (struct usb_aml_regs *)((ulong)priv->base_addr+i*PHY_REGISTER_SIZE); + usb_aml_reg = (struct usb_aml_regs *)((ulong)(priv->base_addr + i*PHY_REGISTER_SIZE)); r3.d32 = usb_aml_reg->usb_r3; r3.b.p30_ssc_en = 1; @@ -120,86 +139,8 @@ r1.b.u3h_fladj_30mhz_reg = 32; usb_aml_reg->usb_r1 = r1.d32; udelay(2); -#if 0 - /* - * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates - * in HS mode instead of SS mode. Workaround it by asserting - * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode - */ - data = cr_bus_read(0x102d); - data |= (1 << 7); - cr_bus_write(0x102D, data); - - data = cr_bus_read(0x1010); - data &= ~0xff0; - data |= 0x20; - cr_bus_write(0x1010, data); - - /* - * Fix RX Equalization setting as follows - * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0 - * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1 - * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3 - * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1 - */ - data = cr_bus_read(0x1006); - data &= ~(1 << 6); - data |= (1 << 7); - data &= ~(0x7 << 8); - data |= (0x3 << 8); - data |= (0x1 << 11); - cr_bus_write(0x1006, data); - - /* - * Set EQ and TX launch amplitudes as follows - * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22 - * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127 - * LANE0.TX_OVRD_DRV_LO.EN set to 1. - */ - data = cr_bus_read(0x1002); - data &= ~0x3f80; - data |= (0x16 << 7); - data &= ~0x7f; - data |= (0x7f | (1 << 14)); - cr_bus_write(0x1002, data); - - /* - * TX_FULL_SWING to 127 - */ - data = cr_bus_read(0x30); - data &= ~(0xf << 4); - cr_bus_write(0x30, data); - - /* - * TX_FULL_SWING to 127 - */ - r1.d32 = usb_aml_reg->usb_r1; - r1.b.p30_pcs_tx_swing_full = 127; - r1.b.u3h_fladj_30mhz_reg = 0x20; - usb_aml_reg->usb_r1 = r1.d32; - udelay(2); - - /* - * TX_DEEMPH_3_5DB to 22 - */ - r2.d32 = usb_aml_reg->usb_r2; - r2.b.p30_pcs_tx_deemph_3p5db = 22; - usb_aml_reg->usb_r2 = r2.d32; - - udelay(2); - /* - * LOS_BIAS to 0x5 - * LOS_LEVEL to 0x9 - */ - r3.d32 = usb_aml_reg->usb_r3; - r3.b.p30_los_bias = 0x5; - r3.b.p30_los_level = 0x9; - r3.b.p30_ssc_en = 1; - r3.b.p30_ssc_range = 2; - usb_aml_reg->usb_r3 = r3.d32; -#endif } - + usb_save_phy_dev(1, phy); return 0; } @@ -208,11 +149,11 @@ .init = phy_aml_usb3_init, .power_on = phy_aml_usb3_power_on, .power_off = phy_aml_usb3_power_off, + .getinfo = phy_aml_usb3_getinfo, }; int phy_aml_usb3_probe(struct udevice *dev) { - return 0; } @@ -221,7 +162,7 @@ { } }; -U_BOOT_DRIVER(meson_gxl_usb3_phy) = { +U_BOOT_DRIVER(meson_usb3_phy) = { .name = "amlogic_new_usb3_phy", .id = UCLASS_PHY, .of_match = phy_aml_usb3_phy_ids,
diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c index c43d702..b7f4fbb 100644 --- a/drivers/phy/phy-uclass.c +++ b/drivers/phy/phy-uclass.c
@@ -149,6 +149,13 @@ return ops->power_off ? ops->power_off(phy) : 0; } +int generic_phy_getinfo(struct phy *phy) +{ + struct phy_ops const *ops = phy_dev_ops(phy->dev); + + return ops->getinfo ? ops->getinfo(phy) : 0; +} + UCLASS_DRIVER(phy) = { .id = UCLASS_PHY, .name = "phy",
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index 5bbc6fc..2aebab8 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig
@@ -56,4 +56,20 @@ select PINCTRL_MESON select PINCTRL_MESON_AXG_PMX select PINCONF_MESON_G12A + +config PINCTRL_MESON_SC2 + bool "Amlogic Meson SC2 SoC pinctrl driver" + depends on PINCTRL_GENERIC + depends on PINCONF + select PINCTRL_MESON + select PINCTRL_MESON_AXG_PMX + select PINCONF_MESON_G12A + +config PINCTRL_MESON_C2 + bool "Amlogic Meson C2 SoC pinctrl driver" + depends on PINCTRL_GENERIC + depends on PINCONF + select PINCTRL_MESON + select PINCTRL_MESON_AXG_PMX + select PINCONF_MESON_G12A endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 6dc899f..f1422cb 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile
@@ -10,3 +10,5 @@ obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o obj-$(CONFIG_PINCTRL_MESON_C1) += pinctrl-meson-c1.o +obj-$(CONFIG_PINCTRL_MESON_SC2) += pinctrl-meson-sc2.o +obj-$(CONFIG_PINCTRL_MESON_C2) += pinctrl-meson-c2.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-c2.c b/drivers/pinctrl/meson/pinctrl-meson-c2.c new file mode 100644 index 0000000..02260da --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-c2.c
@@ -0,0 +1,1083 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dt-bindings/gpio/meson-c2-gpio.h> + +#include "pinctrl-meson.h" +#include "pinctrl-meson-axg-pmx.h" + +/*bank D func1 */ +static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int i2c_a_scl_d_pins[] = { GPIOD_2 }; +static const unsigned int i2c_a_sda_d_pins[] = { GPIOD_3 }; +static const unsigned int ir_out_d4_pins[] = { GPIOD_4 }; +static const unsigned int ir_in_d5_pins[] = { GPIOD_5 }; +static const unsigned int jtag_a_clk_pins[] = { GPIOD_6 }; +static const unsigned int jtag_a_tms_pins[] = { GPIOD_7 }; +static const unsigned int jtag_a_tdi_pins[] = { GPIOD_8 }; +static const unsigned int jtag_a_tdo_pins[] = { GPIOD_9 }; +static const unsigned int gen_clk_d_pins[] = { GPIOD_11 }; +static const unsigned int clk12_24_d_pins[] = { GPIOD_12 }; +static const unsigned int pwm_g_d13_pins[] = { GPIOD_13 }; + +/*bank D func2 */ +static const unsigned int uart_d_tx_d2_pins[] = { GPIOD_2 }; +static const unsigned int uart_d_rx_d3_pins[] = { GPIOD_3 }; +static const unsigned int swclk_pins[] = { GPIOD_6 }; +static const unsigned int swdio_pins[] = { GPIOD_7 }; +static const unsigned int ir_in_d8_pins[] = { GPIOD_8 }; +static const unsigned int ir_out_d9_pins[] = { GPIOD_9 }; +static const unsigned int clk25_d_pins[] = { GPIOD_12 }; + +/*bank D func3 */ +static const unsigned int i2c_slave_scl_pins[] = { GPIOD_2 }; +static const unsigned int i2c_slave_sda_pins[] = { GPIOD_3 }; +static const unsigned int pwm_d_pins[] = { GPIOD_5 }; +static const unsigned int pwm_c_pins[] = { GPIOD_6 }; +static const unsigned int pwm_f_d_pins[] = { GPIOD_7 }; +static const unsigned int uart_d_tx_d8_pins[] = { GPIOD_8 }; +static const unsigned int uart_d_rx_d9_pins[] = { GPIOD_9 }; +static const unsigned int pwm_g_d10_pins[] = { GPIOD_10 }; +static const unsigned int clk_32k_in_pins[] = { GPIOD_12 }; + +/*bank D func4 */ +static const unsigned int pwm_d_hiz_pins[] = { GPIOD_5 }; +static const unsigned int pwm_c_hiz_pins[] = { GPIOD_6 }; +static const unsigned int pwm_f_hiz_pins[] = { GPIOD_7 }; +static const unsigned int pwm_i_d_pins[] = { GPIOD_8 }; +static const unsigned int pwm_g_d12_pins[] = { GPIOD_12 }; + +/*bank E func1 */ +static const unsigned int uart_b_cts_pins[] = { GPIOE_0 }; +static const unsigned int uart_b_rts_pins[] = { GPIOE_1 }; +static const unsigned int pwm_h_d_pins[] = { GPIOE_2 }; + +/*bank E func2 */ +static const unsigned int uart_d_cts_e_pins[] = { GPIOE_0 }; +static const unsigned int uart_d_rts_e_pins[] = { GPIOE_1 }; +static const unsigned int clk25_e_pins[] = { GPIOE_2 }; + +/*bank E func3 */ +static const unsigned int pwm_a_pins[] = { GPIOE_0 }; +static const unsigned int pwm_b_pins[] = { GPIOE_1 }; + +/*bank E func4 */ +static const unsigned int i2c_a_scl_e_pins[] = { GPIOE_0 }; +static const unsigned int i2c_a_sda_e_pins[] = { GPIOE_1 }; + +/*bank B func1 */ +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; + +/*bank B func2 */ +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; +static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 }; +static const unsigned int nand_cle_pins[] = { GPIOB_11 }; +static const unsigned int nand_ce0_pins[] = { GPIOB_12 }; + +/*bank B func3 */ +static const unsigned int spif_hold_pins[] = { GPIOB_3 }; +static const unsigned int spif_mo_pins[] = { GPIOB_4 }; +static const unsigned int spif_mi_pins[] = { GPIOB_5 }; +static const unsigned int spif_clk_pins[] = { GPIOB_6 }; +static const unsigned int spif_wp_n_pins[] = { GPIOB_7 }; +static const unsigned int spif_cs_pins[] = { GPIOB_13 }; + +/*bank C func1 */ +static const unsigned int sdcard_d0_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 }; + +/*bank C func2 */ +static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; + +/*bank C func3 */ +static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 }; +static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 }; +static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_2 }; +static const unsigned int spi_a_sclk_c_pins[] = { GPIOC_3 }; +static const unsigned int i2c_e_sda_c_pins[] = { GPIOC_5 }; +static const unsigned int i2c_e_scl_c_pins[] = { GPIOC_6 }; + +/*bank C func4 */ +static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; + +/*bank X func1*/ +static const unsigned int sdio_d0_x_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_x_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_x_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_x_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_x_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_x_pins[] = { GPIOX_5 }; +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 }; +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 }; +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 }; +static const unsigned int uart_a_tx_x12_pins[] = { GPIOX_12 }; +static const unsigned int uart_a_rx_x13_pins[] = { GPIOX_13 }; +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; +static const unsigned int pwm_f_x_pins[] = { GPIOX_17 }; +static const unsigned int pwm_j_x_pins[] = { GPIOX_18 }; +static const unsigned int i2c_c_sda_x_pins[] = { GPIOX_19 }; +static const unsigned int i2c_c_scl_x_pins[] = { GPIOX_20 }; + +/*bank X func2*/ +static const unsigned int uart_e_tx_x_pins[] = { GPIOX_6 }; +static const unsigned int uart_e_rx_x_pins[] = { GPIOX_7 }; +static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 }; +static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 }; +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 }; +static const unsigned int i2c_d_sda_x_pins[] = { GPIOX_14 }; +static const unsigned int i2c_d_scl_x_pins[] = { GPIOX_15 }; + +/*bank X func3*/ +static const unsigned int eth_mdio_pins[] = { GPIOX_0 }; +static const unsigned int eth_mdc_pins[] = { GPIOX_1 }; +static const unsigned int eth_rx_clk_pins[] = { GPIOX_2 }; +static const unsigned int eth_rx_dv_pins[] = { GPIOX_3 }; +static const unsigned int eth_rxd0_pins[] = { GPIOX_4 }; +static const unsigned int eth_rxd1_pins[] = { GPIOX_5 }; +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOX_6 }; +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOX_7 }; +static const unsigned int eth_tx_clk_pins[] = { GPIOX_8 }; +static const unsigned int eth_txen_pins[] = { GPIOX_9 }; +static const unsigned int eth_txd0_pins[] = { GPIOX_10 }; +static const unsigned int eth_txd1_pins[] = { GPIOX_11 }; +static const unsigned int eth_txd2_rgmii_pins[] = { GPIOX_12 }; +static const unsigned int eth_txd3_rgmii_pins[] = { GPIOX_13 }; +static const unsigned int uart_a_tx_x14_pins[] = { GPIOX_14 }; +static const unsigned int uart_a_rx_x15_pins[] = { GPIOX_15 }; + +/*bank X func4*/ +static const unsigned int spi_b_mosi_x_pins[] = { GPIOX_8 }; +static const unsigned int spi_b_miso_x_pins[] = { GPIOX_9 }; +static const unsigned int spi_b_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi_b_sclk_x_pins[] = { GPIOX_11 }; +static const unsigned int pwm_h_x_pins[] = { GPIOX_14 }; +static const unsigned int pwm_g_x_pins[] = { GPIOX_15 }; + +/*bank X func5 */ +static const unsigned int clk25_x_pins[] = { GPIOX_8 }; + +/*bank M func1 */ +static const unsigned int sdio_d0_m_pins[] = { GPIOM_0 }; +static const unsigned int sdio_d1_m_pins[] = { GPIOM_1 }; +static const unsigned int sdio_d2_m_pins[] = { GPIOM_2 }; +static const unsigned int sdio_d3_m_pins[] = { GPIOM_3 }; +static const unsigned int sdio_clk_m_pins[] = { GPIOM_4 }; +static const unsigned int sdio_cmd_m_pins[] = { GPIOM_5 }; +static const unsigned int pwm_f_m_pins[] = { GPIOM_7 }; +static const unsigned int pwm_g_m_pins[] = { GPIOM_8 }; +static const unsigned int pwm_h_m_pins[] = { GPIOM_9 }; +static const unsigned int i2c_c_sda_m_pins[] = { GPIOM_12 }; +static const unsigned int i2c_c_scl_m_pins[] = { GPIOM_13 }; + +/*bank M func2 */ +static const unsigned int pwm_i_m_pins[] = { GPIOM_0 }; +static const unsigned int pwm_j_m_pins[] = { GPIOM_1 }; +static const unsigned int pwm_g_hiz_pins[] = { GPIOM_8 }; +static const unsigned int pwm_h_hiz_pins[] = { GPIOM_9 }; + +/*bank M func3 */ +static const unsigned int pdm_dclk_m_pins[] = { GPIOM_2 }; +static const unsigned int pdm_din0_m_pins[] = { GPIOM_3 }; + +/*bank M func4 */ +static const unsigned int i2c_e_sda_m_pins[] = { GPIOM_0 }; +static const unsigned int i2c_e_scl_m_pins[] = { GPIOM_1 }; +static const unsigned int i2c_b_sda_m_pins[] = { GPIOM_4 }; +static const unsigned int i2c_b_scl_m_pins[] = { GPIOM_5 }; +static const unsigned int i2c_d_sda_m_pins[] = { GPIOM_8 }; +static const unsigned int i2c_d_scl_m_pins[] = { GPIOM_9 }; + +/*bank M func5 */ +static const unsigned int uart_e_cts_pins[] = { GPIOM_2 }; +static const unsigned int uart_e_rts_pins[] = { GPIOM_3 }; +static const unsigned int uart_e_tx_m_pins[] = { GPIOM_4 }; +static const unsigned int uart_e_rx_m_pins[] = { GPIOM_5 }; +static const unsigned int mic_mute_key_pins[] = { GPIOM_6 }; +static const unsigned int mic_mute_led_pins[] = { GPIOM_7 }; + +/*bank M func6 */ +static const unsigned int gen_clk_m9_pins[] = { GPIOM_9 }; +static const unsigned int gen_clk_m10_pins[] = { GPIOM_10 }; + +/*bank A func1 */ +static const unsigned int mclk_0_pins[] = { GPIOA_0 }; +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 }; +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 }; +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 }; +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 }; +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 }; +static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 }; +static const unsigned int pwm_g_a7_pins[] = { GPIOA_7 }; +static const unsigned int pwm_h_a8_pins[] = { GPIOA_8 }; +static const unsigned int pwm_i_a9_pins[] = { GPIOA_9 }; +static const unsigned int pwm_j_a10_pins[] = { GPIOA_10 }; +static const unsigned int clk12_24_a_pins[] = { GPIOA_11 }; +static const unsigned int uart_c_tx_a12_pins[] = { GPIOA_12 }; +static const unsigned int uart_c_rx_a13_pins[] = { GPIOA_13 }; +static const unsigned int i2c_d_sda_a_pins[] = { GPIOA_14 }; +static const unsigned int i2c_d_scl_a_pins[] = { GPIOA_15 }; + +/*bank A func2 */ +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 }; +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 }; +static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 }; +static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 }; +static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 }; +static const unsigned int tdm_b_din3_pins[] = { GPIOA_6 }; +static const unsigned int uart_e_tx_a_pins[] = { GPIOA_14 }; +static const unsigned int uart_e_rx_a_pins[] = { GPIOA_15 }; + +/*bank A func3 */ +static const unsigned int pwm_g_a1_pins[] = { GPIOA_1 }; +static const unsigned int pwm_h_a2_pins[] = { GPIOA_2 }; +static const unsigned int pwm_i_a3_pins[] = { GPIOA_3 }; +static const unsigned int pwm_j_a4_pins[] = { GPIOA_4 }; +static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_5 }; +static const unsigned int spi_a_miso_a_pins[] = { GPIOA_6 }; +static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_7 }; +static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 }; +static const unsigned int spi_a_ss1_pins[] = { GPIOA_9 }; +static const unsigned int spi_a_ss2_pins[] = { GPIOA_10 }; +static const unsigned int spi_b_mosi_a_pins[] = { GPIOA_11 }; +static const unsigned int spi_b_miso_a_pins[] = { GPIOA_12 }; +static const unsigned int spi_b_sclk_a_pins[] = { GPIOA_13 }; +static const unsigned int spi_b_ss0_a_pins[] = { GPIOA_14 }; +static const unsigned int spi_b_ss1_pins[] = { GPIOA_15 }; + +/*bank A func4 */ +static const unsigned int uart_c_tx_a1_pins[] = { GPIOA_1 }; +static const unsigned int uart_c_rx_a2_pins[] = { GPIOA_2 }; +static const unsigned int uart_c_cts_pins[] = { GPIOA_3 }; +static const unsigned int uart_c_rts_pins[] = { GPIOA_4 }; +static const unsigned int uart_d_tx_a_pins[] = { GPIOA_5 }; +static const unsigned int uart_d_rx_a_pins[] = { GPIOA_6 }; +static const unsigned int uart_d_cts_a_pins[] = { GPIOA_7 }; +static const unsigned int uart_d_rts_a_pins[] = { GPIOA_8 }; +static const unsigned int i2c_e_sda_a_pins[] = { GPIOA_12 }; +static const unsigned int i2c_e_scl_a_pins[] = { GPIOA_13 }; + +/*bank A func5 */ +static const unsigned int mclk_vad_pins[] = { GPIOA_0 }; +static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 }; +static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 }; +static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 }; +static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 }; +static const unsigned int i2c_b_sda_a_pins[] = { GPIOA_7 }; +static const unsigned int i2c_b_scl_a_pins[] = { GPIOA_8 }; +static const unsigned int i2c_c_sda_a_pins[] = { GPIOA_9 }; +static const unsigned int i2c_c_scl_a_pins[] = { GPIOA_10 }; + +static struct meson_pmx_group meson_c2_periphs_groups[] = { + GPIO_GROUP(GPIOD_0), + GPIO_GROUP(GPIOD_1), + GPIO_GROUP(GPIOD_2), + GPIO_GROUP(GPIOD_3), + GPIO_GROUP(GPIOD_4), + GPIO_GROUP(GPIOD_5), + GPIO_GROUP(GPIOD_6), + GPIO_GROUP(GPIOD_7), + GPIO_GROUP(GPIOD_8), + GPIO_GROUP(GPIOD_9), + GPIO_GROUP(GPIOD_10), + GPIO_GROUP(GPIOD_11), + GPIO_GROUP(GPIOD_12), + GPIO_GROUP(GPIOD_13), + GPIO_GROUP(GPIOE_0), + GPIO_GROUP(GPIOE_1), + GPIO_GROUP(GPIOE_2), + GPIO_GROUP(GPIOB_0), + GPIO_GROUP(GPIOB_1), + GPIO_GROUP(GPIOB_2), + GPIO_GROUP(GPIOB_3), + GPIO_GROUP(GPIOB_4), + GPIO_GROUP(GPIOB_5), + GPIO_GROUP(GPIOB_6), + GPIO_GROUP(GPIOB_7), + GPIO_GROUP(GPIOB_8), + GPIO_GROUP(GPIOB_9), + GPIO_GROUP(GPIOB_10), + GPIO_GROUP(GPIOB_11), + GPIO_GROUP(GPIOB_12), + GPIO_GROUP(GPIOB_13), + GPIO_GROUP(GPIOC_0), + GPIO_GROUP(GPIOC_1), + GPIO_GROUP(GPIOC_2), + GPIO_GROUP(GPIOC_3), + GPIO_GROUP(GPIOC_4), + GPIO_GROUP(GPIOC_5), + GPIO_GROUP(GPIOC_6), + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + GPIO_GROUP(GPIOX_20), + GPIO_GROUP(GPIOM_0), + GPIO_GROUP(GPIOM_1), + GPIO_GROUP(GPIOM_2), + GPIO_GROUP(GPIOM_3), + GPIO_GROUP(GPIOM_4), + GPIO_GROUP(GPIOM_5), + GPIO_GROUP(GPIOM_6), + GPIO_GROUP(GPIOM_7), + GPIO_GROUP(GPIOM_8), + GPIO_GROUP(GPIOM_9), + GPIO_GROUP(GPIOM_10), + GPIO_GROUP(GPIOM_11), + GPIO_GROUP(GPIOM_12), + GPIO_GROUP(GPIOM_13), + GPIO_GROUP(GPIOA_0), + GPIO_GROUP(GPIOA_1), + GPIO_GROUP(GPIOA_2), + GPIO_GROUP(GPIOA_3), + GPIO_GROUP(GPIOA_4), + GPIO_GROUP(GPIOA_5), + GPIO_GROUP(GPIOA_6), + GPIO_GROUP(GPIOA_7), + GPIO_GROUP(GPIOA_8), + GPIO_GROUP(GPIOA_9), + GPIO_GROUP(GPIOA_10), + GPIO_GROUP(GPIOA_11), + GPIO_GROUP(GPIOA_12), + GPIO_GROUP(GPIOA_13), + GPIO_GROUP(GPIOA_14), + GPIO_GROUP(GPIOA_15), + GPIO_GROUP(GPIO_TEST_N), + + /* bank D func1 */ + GROUP(uart_b_tx_d, 1), + GROUP(uart_b_rx_d, 1), + GROUP(i2c_a_scl_d, 1), + GROUP(i2c_a_sda_d, 1), + GROUP(ir_out_d4, 1), + GROUP(ir_in_d5, 1), + GROUP(jtag_a_clk, 1), + GROUP(jtag_a_tms, 1), + GROUP(jtag_a_tdi, 1), + GROUP(jtag_a_tdo, 1), + GROUP(gen_clk_d, 1), + GROUP(clk12_24_d, 1), + GROUP(pwm_g_d13, 1), + + /* bank D func2 */ + GROUP(uart_d_tx_d2, 2), + GROUP(uart_d_rx_d3, 2), + GROUP(swclk, 2), + GROUP(swdio, 2), + GROUP(ir_in_d8, 2), + GROUP(ir_out_d9, 2), + GROUP(clk25_d, 2), + + /* bank D func3 */ + GROUP(i2c_slave_scl, 3), + GROUP(i2c_slave_sda, 3), + GROUP(pwm_d, 3), + GROUP(pwm_c, 3), + GROUP(pwm_f_d, 3), + GROUP(uart_d_tx_d8, 3), + GROUP(uart_d_rx_d9, 3), + GROUP(pwm_g_d10, 3), + GROUP(clk_32k_in, 3), + + /* bank D func4 */ + GROUP(pwm_d_hiz, 4), + GROUP(pwm_c_hiz, 4), + GROUP(pwm_f_hiz, 4), + GROUP(pwm_i_d, 4), + GROUP(pwm_g_d12, 4), + + /* bank E func1 */ + GROUP(uart_b_cts, 1), + GROUP(uart_b_rts, 1), + GROUP(pwm_h_d, 1), + + /* bank E func2 */ + GROUP(uart_d_cts_e, 2), + GROUP(uart_d_rts_e, 2), + GROUP(clk25_e, 2), + + /* bank E func3 */ + GROUP(pwm_a, 3), + GROUP(pwm_b, 3), + + /* bank E func4 */ + GROUP(i2c_a_scl_e, 4), + GROUP(i2c_a_sda_e, 4), + + /* bank B func1 */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_ds, 1), + + /* bank B func2 */ + GROUP(nand_wen_clk, 2), + GROUP(nand_ale, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_cle, 2), + GROUP(nand_ce0, 2), + + /* bank B func3 */ + GROUP(spif_hold, 3), + GROUP(spif_mo, 3), + GROUP(spif_mi, 3), + GROUP(spif_clk, 3), + GROUP(spif_wp_n, 3), + GROUP(spif_cs, 3), + + /* bank C func1 */ + GROUP(sdcard_d0, 1), + GROUP(sdcard_d1, 1), + GROUP(sdcard_d2, 1), + GROUP(sdcard_d3, 1), + GROUP(sdcard_clk, 1), + GROUP(sdcard_cmd, 1), + + /* bank C func2 */ + GROUP(jtag_b_tdo, 2), + GROUP(jtag_b_tdi, 2), + GROUP(uart_b_rx_c, 2), + GROUP(uart_b_tx_c, 2), + GROUP(jtag_b_clk, 2), + GROUP(jtag_b_tms, 2), + + /* bank C func3 */ + GROUP(spi_a_mosi_c, 3), + GROUP(spi_a_miso_c, 3), + GROUP(spi_a_ss0_c, 3), + GROUP(spi_a_sclk_c, 3), + GROUP(i2c_e_sda_c, 3), + GROUP(i2c_e_scl_c, 3), + + /* bank C func4 */ + GROUP(pdm_din0_c, 4), + GROUP(pdm_dclk_c, 4), + + /* bank X func1 */ + GROUP(sdio_d0_x, 1), + GROUP(sdio_d1_x, 1), + GROUP(sdio_d2_x, 1), + GROUP(sdio_d3_x, 1), + GROUP(sdio_clk_x, 1), + GROUP(sdio_cmd_x, 1), + GROUP(tdm_a_dout1, 1), + GROUP(tdm_a_dout0, 1), + GROUP(tdm_a_fs, 1), + GROUP(tdm_a_sclk, 1), + GROUP(uart_a_tx_x12, 1), + GROUP(uart_a_rx_x13, 1), + GROUP(uart_a_cts, 1), + GROUP(uart_a_rts, 1), + GROUP(pwm_e, 1), + GROUP(pwm_f_x, 1), + GROUP(pwm_j_x, 1), + GROUP(i2c_c_sda_x, 1), + GROUP(i2c_c_scl_x, 1), + + /* bank X func2 */ + GROUP(uart_e_tx_x, 2), + GROUP(uart_e_rx_x, 2), + GROUP(tdm_a_din1, 2), + GROUP(tdm_a_din0, 2), + GROUP(tdm_a_slv_fs, 2), + GROUP(tdm_a_slv_sclk, 2), + GROUP(i2c_d_sda_x, 2), + GROUP(i2c_d_scl_x, 2), + + /* bank X func3 */ + GROUP(eth_mdio, 3), + GROUP(eth_mdc, 3), + GROUP(eth_rx_clk, 3), + GROUP(eth_rx_dv, 3), + GROUP(eth_rxd0, 3), + GROUP(eth_rxd1, 3), + GROUP(eth_rxd2_rgmii, 3), + GROUP(eth_rxd3_rgmii, 3), + GROUP(eth_tx_clk, 3), + GROUP(eth_txen, 3), + GROUP(eth_txd0, 3), + GROUP(eth_txd1, 3), + GROUP(eth_txd2_rgmii, 3), + GROUP(eth_txd3_rgmii, 3), + GROUP(uart_a_tx_x14, 3), + GROUP(uart_a_rx_x15, 3), + + /* bank X func4 */ + GROUP(spi_b_mosi_x, 4), + GROUP(spi_b_miso_x, 4), + GROUP(spi_b_ss0_x, 4), + GROUP(spi_b_sclk_x, 4), + GROUP(pwm_h_x, 4), + GROUP(pwm_g_x, 4), + + /* bank X func5 */ + GROUP(clk25_x, 5), + + /* bank M func1 */ + GROUP(sdio_d0_m, 1), + GROUP(sdio_d1_m, 1), + GROUP(sdio_d2_m, 1), + GROUP(sdio_d3_m, 1), + GROUP(sdio_clk_m, 1), + GROUP(sdio_cmd_m, 1), + GROUP(pwm_f_m, 1), + GROUP(pwm_g_m, 1), + GROUP(pwm_h_m, 1), + GROUP(i2c_c_sda_m, 1), + GROUP(i2c_c_scl_m, 1), + + /* bank M func2 */ + GROUP(pwm_i_m, 2), + GROUP(pwm_j_m, 2), + GROUP(pwm_g_hiz, 2), + GROUP(pwm_h_hiz, 2), + + /* bank M func3 */ + GROUP(pdm_dclk_m, 3), + GROUP(pdm_din0_m, 3), + + /* bank M func4 */ + GROUP(i2c_e_sda_m, 4), + GROUP(i2c_e_scl_m, 4), + GROUP(i2c_b_sda_m, 4), + GROUP(i2c_b_scl_m, 4), + GROUP(i2c_d_sda_m, 4), + GROUP(i2c_d_scl_m, 4), + + /* bank M func5 */ + GROUP(uart_e_cts, 5), + GROUP(uart_e_rts, 5), + GROUP(uart_e_tx_m, 5), + GROUP(uart_e_rx_m, 5), + GROUP(mic_mute_key, 5), + GROUP(mic_mute_led, 5), + + /* bank M func6 */ + GROUP(gen_clk_m9, 6), + GROUP(gen_clk_m10, 6), + + /* bank A func1 */ + GROUP(mclk_0, 1), + GROUP(tdm_b_sclk, 1), + GROUP(tdm_b_fs, 1), + GROUP(tdm_b_dout0, 1), + GROUP(tdm_b_dout1, 1), + GROUP(tdm_b_dout2, 1), + GROUP(tdm_b_dout3, 1), + GROUP(pwm_g_a7, 1), + GROUP(pwm_h_a8, 1), + GROUP(pwm_i_a9, 1), + GROUP(pwm_j_a10, 1), + GROUP(clk12_24_a, 1), + GROUP(uart_c_tx_a12, 1), + GROUP(uart_c_rx_a13, 1), + GROUP(i2c_d_sda_a, 1), + GROUP(i2c_d_scl_a, 1), + + /* bank A func2 */ + GROUP(tdm_b_slv_sclk, 2), + GROUP(tdm_b_slv_fs, 2), + GROUP(tdm_b_din0, 2), + GROUP(tdm_b_din1, 2), + GROUP(tdm_b_din2, 2), + GROUP(tdm_b_din3, 2), + GROUP(uart_e_tx_a, 2), + GROUP(uart_e_rx_a, 2), + + /* bank A func3 */ + GROUP(pwm_g_a1, 3), + GROUP(pwm_h_a2, 3), + GROUP(pwm_i_a3, 3), + GROUP(pwm_j_a4, 3), + GROUP(spi_a_mosi_a, 3), + GROUP(spi_a_miso_a, 3), + GROUP(spi_a_sclk_a, 3), + GROUP(spi_a_ss0_a, 3), + GROUP(spi_a_ss1, 3), + GROUP(spi_a_ss2, 3), + GROUP(spi_b_mosi_a, 3), + GROUP(spi_b_miso_a, 3), + GROUP(spi_b_sclk_a, 3), + GROUP(spi_b_ss0_a, 3), + GROUP(spi_b_ss1, 3), + + /* bank A func4 */ + GROUP(uart_c_tx_a1, 4), + GROUP(uart_c_rx_a2, 4), + GROUP(uart_c_cts, 4), + GROUP(uart_c_rts, 4), + GROUP(uart_d_tx_a, 4), + GROUP(uart_d_rx_a, 4), + GROUP(uart_d_cts_a, 4), + GROUP(uart_d_rts_a, 4), + GROUP(i2c_e_sda_a, 4), + GROUP(i2c_e_scl_a, 4), + + /* bank A func5 */ + GROUP(mclk_vad, 5), + GROUP(tdm_vad_sclk_a1, 5), + GROUP(tdm_vad_fs_a2, 5), + GROUP(tdm_vad_sclk_a5, 5), + GROUP(tdm_vad_fs_a6, 5), + GROUP(i2c_b_sda_a, 5), + GROUP(i2c_b_scl_a, 5), + GROUP(i2c_c_sda_a, 5), + GROUP(i2c_c_scl_a, 5), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIO_TEST_N", + + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", + "GPIOD_5", "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", + "GPIOD_10", "GPIOD_11", "GPIOD_12", "GPIOD_13," + + "GPIOE_0", "GPIOE_1", "GPIOE_2" + + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", + "GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", + "GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", + "GPIOC_5", "GPIOC_6", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", + "GPIOX_20", + + "GPIOM_0", "GPIOM_1", "GPIOM_2", "GPIOM_3", "GPIOM_4", + "GPIOM_5", "GPIOM_6", "GPIOM_7", "GPIOM_8", "GPIOM_9", + "GPIOM_10", "GPIOM_11", "GPIOM_12", "GPIOM_13", + + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", + "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14", + "GPIOA_15", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx_x12", "uart_a_rx_x13", "uart_a_cts", "uart_a_rts", + "uart_a_tx_x14", "uart_a_rx_x15", +}; + +static const char * const uart_b_groups[] = { + "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts", "uart_b_rts", + "uart_b_rx_c", "uart_b_tx_c", +}; + +static const char * const uart_c_groups[] = { + "uart_c_tx_a12", "uart_c_rx_a13", "uart_c_tx_a1", "uart_c_rx_a2", + "uart_c_cts", "uart_c_rts", +}; + +static const char * const uart_d_groups[] = { + "uart_d_tx_d2", "uart_d_rx_d3", "uart_d_tx_d8", "uart_d_rx_d9", + "uart_d_cts_e", "uart_d_rts_e", "uart_d_tx_a", "uart_d_tx_a", + "uart_d_cts_a", "uart_d_rts_a", +}; + +static const char * const uart_e_groups[] = { + "uart_e_tx_x", "uart_e_rx_x", "uart_e_cts", "uart_e_rts", "uart_e_tx_m", + "uart_e_rx_m", "uart_e_rx_a", "uart_e_tx_a", +}; + +static const char * const i2c_a_groups[] = { + "i2c_a_scl_d", "i2c_a_sda_d", "i2c_a_scl_e", "i2c_a_sda_e", +}; + +static const char * const i2c_b_groups[] = { + "i2c_b_sda_a", "i2c_b_scl_a", "i2c_b_sda_m", "i2c_b_scl_m", +}; + +static const char * const i2c_c_groups[] = { + "i2c_c_sda_x", "i2c_c_scl_x", "i2c_c_sda_m", "i2c_c_scl_m", + "i2c_c_sda_a", "i2c_c_scl_a", +}; + +static const char * const i2c_d_groups[] = { + "i2c_d_sda_x", "i2c_d_scl_x", "i2c_d_sda_a", "i2c_d_scl_a", + "i2c_d_sda_m", "i2c_d_scl_m", +}; + +static const char * const i2c_e_groups[] = { + "i2c_e_sda_c", "i2c_e_scl_c", "i2c_e_sda_m", "i2c_e_scl_m", + "i2c_e_sda_a", "i2c_e_scl_a", +}; + +static const char * const i2c_slave_groups[] = { + "i2c_slave_scl", "i2c_slave_sda", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_d", "pwm_f_m", "pwm_f_x" +}; + +static const char * const pwm_g_groups[] = { + "pwm_g_d10", "pwm_g_x", "pwm_g_m", "pwm_g_a7", + "pwm_g_a1", "pwm_g_d12", "pwm_g_d13", +}; + +static const char * const pwm_h_groups[] = { + "pwm_h_x", "pwm_h_m", "pwm_h_a8", "pwm_h_a2", + "pwm_h_d", +}; + +static const char * const pwm_i_groups[] = { + "pwm_i_m", "pwm_i_a9", "pwm_i_a3", "pwm_i_d", +}; + +static const char * const pwm_j_groups[] = { + "pwm_j_x", "pwm_j_m", "pwm_j_a10", "pwm_j_a4", +}; + +static const char * const pwm_c_hiz_groups[] = { + "pwm_c_hiz", +}; + +static const char * const pwm_d_hiz_groups[] = { + "pwm_d_hiz", +}; + +static const char * const pwm_f_hiz_groups[] = { + "pwm_f_hiz", +}; + +static const char * const pwm_g_hiz_groups[] = { + "pwm_g_hiz", +}; + +static const char * const pwm_h_hiz_groups[] = { + "pwm_h_hiz", +}; + +static const char * const ir_out_groups[] = { + "ir_out_d4", "ir_out_d9", +}; + +static const char * const ir_in_groups[] = { + "ir_in_d5", "ir_in_d8", +}; + +static const char * const jtag_a_groups[] = { + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo", +}; + +static const char * const jtag_b_groups[] = { + "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms", +}; + +static const char * const gen_clk_groups[] = { + "gen_clk_d", "gen_clk_m10", "gen_clk_m9", +}; + +static const char * const clk12_24_groups[] = { + "clk12_24_d", "clk12_24_a", +}; + +static const char * const sw_groups[] = { + "swclk", "swdio", +}; + +static const char * const clk25_groups[] = { + "clk25_e", "clk25_x", "clk_25_d", +}; + +static const char * const clk_32k_in_groups[] = { + "clk_32k_in", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_cmd", "emmc_nand_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_nand_ds", "nand_wen_clk", "nand_ale", "nand_ren_wr", + "nand_cle", "nand_ce0", +}; + +static const char * const spif_groups[] = { + "spif_hold", "spif_mo", "spif_mi", "spif_clk", + "spif_wp_n", "spif_cs", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", + "sdcard_clk", "sdcard_cmd", +}; + +static const char * const spi_a_groups[] = { + "spi_a_mosi_c", "spi_a_miso_c", "spi_a_ss0_c", "spi_a_sclk_c", + "spi_a_mosi_a", "spi_a_miso_a", "spi_a_sclk_a", "spi_a_ss0_a", + "spi_a_ss1", "spi_a_ss2", +}; + +static const char * const pdm_groups[] = { + "pdm_din0_c", "pdm_dclk_c", "pdm_dclk_m", "pdm_din0_m", +}; + +static const char * const sdio_groups[] = { + "sdio_d0_x", "sdio_d1_x", "sdio_d2_x", "sdio_d3_x", + "sdio_clk_x", "sdio_cmd_x", + + "sdio_d0_m", "sdio_d1_m", "sdio_d2_m", "sdio_d3_m", + "sdio_clk_m", "sdio_cmd_m", +}; + +static const char * const eth_groups[] = { + "eth_mdio", "eth_mdc", "eth_rx_clk", "eth_rx_dv", + "eth_rxd0", "eth_rxd1", "eth_rxd2_rgmii", "eth_rxd3_rgmii", + "eth_tx_clk", "eth_txen", "eth_txd0", "eth_txd1", + "eth_txd2_rgmii", "eth_txd3_rgmii", +}; + +static const char * const spi_b_groups[] = { + "spi_b_mosi_x", "spi_b_miso_x", "spi_b_ss0_x", "spi_b_sclk_x", + "spi_b_mosi_a", "spi_b_miso_a", "spi_b_ss0_a", "spi_b_sclk_a", + "spi_b_ss1", +}; + +static const char * const mic_mute_groups[] = { + "mic_mute_key", "mic_mute_led", +}; + +static const char * const mclk_0_groups[] = { + "mclk_0", +}; + +static const char * const tdm_a_groups[] = { + "tdm_a_dout1", "tdm_a_dout0", "tdm_a_fs", "tdm_a_sclk", + "tdm_a_din1", "tdm_a_din0", "tdm_a_slv_fs", "tdm_a_slv_sclk", +}; + +static const char * const tdm_b_groups[] = { + "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1", + "tdm_b_dout2", "tdm_b_dout3", + + "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_din0", "tdm_b_din1", + "tdm_b_din2", "tdm_b_din3", +}; + +static const char * const tdm_vad_groups[] = { + "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6", +}; + +static const char * const mclk_vad_groups[] = { + "mclk_vad", +}; + +static struct meson_pmx_func meson_c2_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_d), + FUNCTION(uart_e), + FUNCTION(i2c_a), + FUNCTION(i2c_b), + FUNCTION(i2c_c), + FUNCTION(i2c_d), + FUNCTION(i2c_e), + FUNCTION(i2c_slave), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(pwm_g), + FUNCTION(pwm_h), + FUNCTION(pwm_i), + FUNCTION(pwm_j), + FUNCTION(pwm_c_hiz), + FUNCTION(pwm_d_hiz), + FUNCTION(pwm_f_hiz), + FUNCTION(pwm_g_hiz), + FUNCTION(pwm_h_hiz), + FUNCTION(ir_out), + FUNCTION(ir_in), + FUNCTION(jtag_a), + FUNCTION(jtag_b), + FUNCTION(gen_clk), + FUNCTION(clk12_24), + FUNCTION(sw), + FUNCTION(clk25), + FUNCTION(clk_32k_in), + FUNCTION(emmc), + FUNCTION(nand), + FUNCTION(spif), + FUNCTION(sdcard), + FUNCTION(spi_a), + FUNCTION(pdm), + FUNCTION(sdio), + FUNCTION(eth), + FUNCTION(spi_b), + FUNCTION(mic_mute), + FUNCTION(mclk_0), + FUNCTION(tdm_a), + FUNCTION(tdm_b), + FUNCTION(tdm_vad), + FUNCTION(mclk_vad), +}; + +static struct meson_bank meson_c2_periphs_banks[] = { + /* name first last irq pullen pull dir out in */ + BANK("GPIOD_", GPIOD_0, GPIOD_13, + 0x3, 0, 0x4, 0, 0x2, 0, 0x1, 0, 0x0, 0), + BANK("GPIOE_", GPIOE_0, GPIOE_2, + 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0), + BANK("GPIOB_", GPIOB_0, GPIOB_13, + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0), + BANK("GPIOC_", GPIOC_0, GPIOC_6, + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0), + BANK("GPIOX_", GPIOX_0, GPIOX_20, + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0), + BANK("GPIOM_", GPIOM_0, GPIOM_13, + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0), + BANK("GPIOA_", GPIOA_0, GPIOA_15, + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0), + BANK("GPIO_TEST_N", GPIO_TEST_N, GPIO_TEST_N, + 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0), +}; + +static struct meson_pmx_bank meson_c2_periphs_pmx_banks[] = { + /*name first lask reg offset*/ + BANK_PMX("D", GPIOD_0, GPIOD_13, 0x0, 0), + BANK_PMX("E", GPIOE_0, GPIOE_2, 0x2, 0), + BANK_PMX("B", GPIOB_0, GPIOB_13, 0x3, 0), + BANK_PMX("C", GPIOC_0, GPIOC_6, 0x5, 0), + BANK_PMX("X", GPIOX_0, GPIOX_20, 0x6, 0), + BANK_PMX("M", GPIOM_0, GPIOM_13, 0x9, 0), + BANK_PMX("A", GPIOA_0, GPIOA_15, 0xb, 0), + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0), +}; + +static struct meson_drive_bank meson_c2_periphs_drive_banks[] = { + /* name first lask reg offset*/ + BANK_DRIVE("D", GPIOD_0, GPIOD_13, 0x5, 0), + BANK_DRIVE("E", GPIOE_0, GPIOE_2, 0x15, 0), + BANK_DRIVE("B", GPIOB_0, GPIOB_13, 0x25, 0), + BANK_DRIVE("C", GPIOC_0, GPIOC_6, 0x35, 0), + BANK_DRIVE("X", GPIOX_0, GPIOX_20, 0x45, 0), + BANK_DRIVE("M", GPIOM_0, GPIOM_13, 0x55, 0), + BANK_DRIVE("A", GPIOA_0, GPIOA_15, 0x65, 0), + BANK_DRIVE("TESTN", GPIO_TEST_N, GPIO_TEST_N, 0x75, 0), +}; + +static struct meson_axg_pmx_data meson_c2_periphs_pmx_banks_data = { + .pmx_banks = meson_c2_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_c2_periphs_pmx_banks), +}; + +static struct meson_drive_data meson_c2_periphs_drive_data = { + .drive_banks = meson_c2_periphs_drive_banks, + .num_drive_banks = ARRAY_SIZE(meson_c2_periphs_drive_banks), +}; + +static struct meson_pinctrl_data meson_c2_periphs_pinctrl_data = { + .name = "periphs-banks", + .groups = meson_c2_periphs_groups, + .funcs = meson_c2_periphs_functions, + .banks = meson_c2_periphs_banks, + .num_pins = 90, + .num_groups = ARRAY_SIZE(meson_c2_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_c2_periphs_functions), + .num_banks = ARRAY_SIZE(meson_c2_periphs_banks), + .pmx_data = &meson_c2_periphs_pmx_banks_data, + .drv_data = &meson_c2_periphs_drive_data, +}; + +static const struct udevice_id meson_c2_pinctrl_match[] = { + { + .compatible = "amlogic,meson-c2-periphs-pinctrl", + .data = (ulong)&meson_c2_periphs_pinctrl_data, + }, + { }, +}; + +U_BOOT_DRIVER(meson_c2_pinctrl) = { + .name = "meson-c2-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_c2_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), + .ops = &meson_axg_pinctrl_ops, +};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-sc2.c b/drivers/pinctrl/meson/pinctrl-meson-sc2.c new file mode 100644 index 0000000..8c61003 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-sc2.c
@@ -0,0 +1,1285 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dt-bindings/gpio/meson-sc2-gpio.h> + +#include "pinctrl-meson.h" +#include "pinctrl-meson-axg-pmx.h" + +/*bank D func1 */ +static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int i2c_e_scl_d_pins[] = { GPIOD_2 }; +static const unsigned int i2c_e_sda_d_pins[] = { GPIOD_3 }; +static const unsigned int remote_out_d4_pins[] = { GPIOD_4 }; +static const unsigned int remote_input_d5_pins[] = { GPIOD_5 }; +static const unsigned int jtag_2_clk_pins[] = { GPIOD_6 }; +static const unsigned int jtag_2_tms_pins[] = { GPIOD_7 }; +static const unsigned int jtag_2_tdi_pins[] = { GPIOD_8 }; +static const unsigned int jtag_2_tdo_pins[] = { GPIOD_9 }; +static const unsigned int cec_a_d_pins[] = { GPIOD_10 }; + +/*bank D func2 */ +static const unsigned int uart_a_tx_d2_pins[] = { GPIOD_2 }; +static const unsigned int uart_a_rx_d3_pins[] = { GPIOD_3 }; +static const unsigned int clk_32k_in_pins[] = { GPIOD_4 }; +static const unsigned int remote_out_d9_pins[] = { GPIOD_9 }; +static const unsigned int cec_b_d_pins[] = { GPIOD_10 }; +static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 }; + +/*bank D func3 */ +static const unsigned int i2c_slave_scl_pins[] = { GPIOD_2 }; +static const unsigned int i2c_slave_sda_pins[] = { GPIOD_3 }; +static const unsigned int pwm_i_d4_pins[] = { GPIOD_4 }; +static const unsigned int pwm_j_d5_pins[] = { GPIOD_5 }; +static const unsigned int pwm_i_d6_pins[] = { GPIOD_6 }; +static const unsigned int uart_a_tx_d8_pins[] = { GPIOD_8 }; +static const unsigned int uart_a_rx_d9_pins[] = { GPIOD_9 }; +static const unsigned int pwm_j_d10_pins[] = { GPIOD_10 }; +static const unsigned int pwm_g_pins[] = { GPIOD_11 }; + +/*bank D func4 */ +static const unsigned int pwm_i_hiz_pins[] = { GPIOD_4 }; +static const unsigned int tsin_a_sop_d_pins[] = { GPIOD_6 }; +static const unsigned int tsin_a_din0_d_pins[] = { GPIOD_7 }; +static const unsigned int tsin_a_clk_d_pins[] = { GPIOD_8 }; +static const unsigned int tsin_a_valid_d_pins[] = { GPIOD_9 }; +static const unsigned int spdif_out_d_pins[] = { GPIOD_10 }; +static const unsigned int gen_clk_d_pins[] = { GPIOD_11 }; + +/*bank D func5 */ +static const unsigned int mic_mute_en_pins[] = { GPIOD_2 }; +static const unsigned int tdm_d0_pins[] = { GPIOD_4 }; +static const unsigned int tdm_d1_pins[] = { GPIOD_6 }; +static const unsigned int tdm_fs1_pins[] = { GPIOD_7 }; +static const unsigned int tdm_sclk1_pins[] = { GPIOD_8 }; +static const unsigned int mclk1_pins[] = { GPIOD_9 }; +static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 }; + +/*bank D func6 */ +static const unsigned int clk12_24_d_pins[] = { GPIOD_10 }; + +/*bank E func1 */ +static const unsigned int uart_b_cts_pins[] = { GPIOE_0 }; +static const unsigned int uart_b_rts_pins[] = { GPIOE_1 }; +static const unsigned int clk12_24_e_pins[] = { GPIOE_2 }; + +/*bank E funsc2 */ +static const unsigned int uart_a_cts_pins[] = { GPIOE_0 }; +static const unsigned int uart_a_rts_pins[] = { GPIOE_1 }; +static const unsigned int clk25_pins[] = { GPIOE_2 }; + +/*bank E func3 */ +static const unsigned int pwm_h_pins[] = { GPIOE_0 }; +static const unsigned int pwm_j_e_pins[] = { GPIOE_1 }; +static const unsigned int pwm_a_e_pins[] = { GPIOE_2 }; + +/*bank E func4 */ +static const unsigned int i2c_e_scl_e_pins[] = { GPIOE_0 }; +static const unsigned int i2c_e_sda_e_pins[] = { GPIOE_1 }; + +/*bank E func5 */ +static const unsigned int mic_mute_key_pins[] = { GPIOE_2 }; + +/*bank B func1 */ +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; +static const unsigned int emmc_nand_dqs_pins[] = { GPIOB_13 }; + +/*bank B funsc2 */ +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; +static const unsigned int nand_cle_pins[] = { GPIOB_10 }; +static const unsigned int nand_ce0_pins[] = { GPIOB_11 }; +static const unsigned int nand_ren_wr_pins[] = { GPIOB_12 }; +static const unsigned int nand_rb0_pins[] = { GPIOB_14 }; +static const unsigned int nand_ce1_pins[] = { GPIOB_15 }; + +/*bank B func3 */ +static const unsigned int nor_hold_pins[] = { GPIOB_3 }; +static const unsigned int nor_d_pins[] = { GPIOB_4 }; +static const unsigned int nor_q_pins[] = { GPIOB_5 }; +static const unsigned int nor_c_pins[] = { GPIOB_6 }; +static const unsigned int nor_wp_pins[] = { GPIOB_7 }; +static const unsigned int nor_cs_pins[] = { GPIOB_14 }; + +/*bank C func1 */ +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; +static const unsigned int sdcard_cd_pins[] = { GPIOC_6 }; +static const unsigned int pcieck_reqn_pins[] = { GPIOC_7 }; + +/*bank C funsc2 */ +static const unsigned int jtag_1_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_1_tdi_pins[] = { GPIOC_1 }; +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int jtag_1_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_1_tms_pins[] = { GPIOC_5 }; + +/*bank C func3 */ +static const unsigned int tsin_c_valid_c_pins[] = { GPIOC_0 }; +static const unsigned int tsin_c_sop_c_pins[] = { GPIOC_1 }; +static const unsigned int tsin_c_din0_c_pins[] = { GPIOC_2 }; +static const unsigned int tsin_c_clk_c_pins[] = { GPIOC_3 }; +static const unsigned int i2c_a_sda_c_pins[] = { GPIOC_5 }; +static const unsigned int i2c_a_scl_c_pins[] = { GPIOC_6 }; + +/*bank C func4 */ +static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 }; +static const unsigned int pdm_din1_c1_pins[] = { GPIOC_1 }; +static const unsigned int pdm_din2_c_pins[] = { GPIOC_2 }; +static const unsigned int pdm_din3_c_pins[] = { GPIOC_3 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; +static const unsigned int pdm_din1_c7_pins[] = { GPIOC_7 }; + +/*bank C func5 */ +static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 }; +static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 }; +static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_2 }; +static const unsigned int spi_a_sclk_c_pins[] = { GPIOC_3 }; +static const unsigned int pwm_c_c_pins[] = { GPIOC_4 }; +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; + +/*bank X func1*/ +static const unsigned int sdio_d0_x_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_x_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_x_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_x_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_x_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_x_pins[] = { GPIOX_5 }; +static const unsigned int pwm_a_x_pins[] = { GPIOX_6 }; +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; +static const unsigned int tdm_d3_pins[] = { GPIOX_8 }; +static const unsigned int tdm_d4_pins[] = { GPIOX_9 }; +static const unsigned int tdm_fs0_pins[] = { GPIOX_10 }; +static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 }; +static const unsigned int uart_e_tx_pins[] = { GPIOX_12 }; +static const unsigned int uart_e_rx_pins[] = { GPIOX_13 }; +static const unsigned int uart_e_cts_pins[] = { GPIOX_14 }; +static const unsigned int uart_e_rts_pins[] = { GPIOX_15 }; +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; +static const unsigned int i2c_c_sda_x_pins[] = { GPIOX_17 }; +static const unsigned int i2c_c_scl_x_pins[] = { GPIOX_18 }; +static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 }; + +/*bank X func2*/ +static const unsigned int pdm_din0_x_pins[] = { GPIOX_0 }; +static const unsigned int pdm_din1_x_pins[] = { GPIOX_1 }; +static const unsigned int pdm_din2_x_pins[] = { GPIOX_2 }; +static const unsigned int pdm_din3_x_pins[] = { GPIOX_3 }; +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_4 }; +static const unsigned int mclk_0_pins[] = { GPIOX_5 }; +static const unsigned int uart_d_tx_x6_pins[] = { GPIOX_6 }; +static const unsigned int uart_d_rx_x7_pins[] = { GPIOX_7 }; +static const unsigned int uart_d_cts_pins[] = { GPIOX_8 }; +static const unsigned int uart_d_rts_pins[] = { GPIOX_9 }; +static const unsigned int uart_d_tx_x10_pins[] = { GPIOX_10 }; +static const unsigned int uart_d_rx_x11_pins[] = { GPIOX_11}; +static const unsigned int tdm_d15_x_pins[] = { GPIOX_19}; + +/*bank X func3*/ +static const unsigned int tsin_a_din0_x_pins[] = { GPIOX_0 }; +static const unsigned int tsin_a_sop_x_pins[] = { GPIOX_1 }; +static const unsigned int tsin_a_valid_x_pins[] = { GPIOX_2 }; +static const unsigned int tsin_a_clk_x_pins[] = { GPIOX_3 }; +static const unsigned int tsin_d_sop_x_pins[] = { GPIOX_8 }; +static const unsigned int tsin_d_valid_x_pins[] = { GPIOX_9 }; +static const unsigned int tsin_d_din0_x_pins[] = { GPIOX_10 }; +static const unsigned int tsin_d_clk_x_pins[] = { GPIOX_11 }; + +/*bank X func4*/ +static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 }; +static const unsigned int pwm_c_x_pins[] = { GPIOX_5 }; +static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; +static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 }; +static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 }; +static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 }; +static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi_a_sclk_x_pins[] = { GPIOX_11 }; + +/*bank X func5 */ +static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 }; +static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 }; +static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 }; +static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 }; +static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 }; +static const unsigned int sdcard_cd_x_pins[] = { GPIOX_5 }; +static const unsigned int iso7816_clk_x_pins[] = { GPIOX_8 }; +static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 }; +static const unsigned int i2c_b_sda_x_pins[] = { GPIOX_10 }; +static const unsigned int i2c_b_scl_x_pins[] = { GPIOX_11 }; +static const unsigned int gen_clk_x_pins[] = { GPIOX_19 }; + +/*bank H func1 */ +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; +static const unsigned int hdmitx_scl_pins[] = { GPIOH_1 }; +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; +static const unsigned int spdif_in_h_pins[] = { GPIOH_5 }; +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_6 }; +static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 }; + +/*bank H func2 */ +static const unsigned int i2c_d_sda_h_pins[] = { GPIOH_0 }; +static const unsigned int i2c_d_scl_h_pins[] = { GPIOH_1 }; +static const unsigned int i2c_b_sda_h2_pins[] = { GPIOH_2 }; +static const unsigned int i2c_b_scl_h3_pins[] = { GPIOH_3 }; +static const unsigned int uart_c_rts_pins[] = { GPIOH_4 }; +static const unsigned int uart_c_cts_pins[] = { GPIOH_5 }; +static const unsigned int uart_c_rx_pins[] = { GPIOH_6 }; +static const unsigned int uart_c_tx_pins[] = { GPIOH_7 }; + +/*bank H func3 */ +static const unsigned int spi_b_mosi_h_pins[] = { GPIOH_4 }; +static const unsigned int spi_b_miso_h_pins[] = { GPIOH_5 }; +static const unsigned int spi_b_ss0_h_pins[] = { GPIOH_6 }; +static const unsigned int spi_b_sclk_h_pins[] = { GPIOH_7 }; + +/*bank H func4 */ +static const unsigned int cec_a_h_pins[] = { GPIOH_3 }; +static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; +static const unsigned int i2c_b_sda_h6_pins[] = { GPIOH_6 }; +static const unsigned int i2c_b_scl_h7_pins[] = { GPIOH_7 }; + +/*bank H func5 */ +static const unsigned int cec_b_h_pins[] = { GPIOH_3 }; +static const unsigned int tdm_d5_pins[] = { GPIOH_5 }; +static const unsigned int remote_out_h_pins[] = { GPIOH_6 }; +static const unsigned int pwm_b_h_pins[] = { GPIOH_7 }; + +/*bank H func6 */ +static const unsigned int i2c_a_sda_h_pins[] = { GPIOH_4 }; +static const unsigned int i2c_a_scl_h_pins[] = { GPIOH_5 }; + +/*bank Z func1 */ +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; +static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 }; +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; +static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 }; +static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 }; +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; +static const unsigned int eth_txen_pins[] = { GPIOZ_9 }; +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; +static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 }; +static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 }; +static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; + +/*bank Z func2 */ +static const unsigned int pwm_d_z_pins[] = { GPIOZ_2 }; +static const unsigned int clk12_24_z_pins[] = { GPIOZ_13 }; + +/*bank Z func3 */ +static const unsigned int iso7816_clk_z0_pins[] = { GPIOZ_0 }; +static const unsigned int iso7816_data_z1_pins[] = { GPIOZ_1 }; +static const unsigned int tsin_b_valid_pins[] = { GPIOZ_2 }; +static const unsigned int tsin_b_sop_pins[] = { GPIOZ_3 }; +static const unsigned int tsin_b_din0_pins[] = { GPIOZ_4 }; +static const unsigned int tsin_b_clk_pins[] = { GPIOZ_5 }; +static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 }; +static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 }; +static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 }; +static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 }; +static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 }; +static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 }; +static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 }; +static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 }; +static const unsigned int i2c_c_sda_z14_pins[] = { GPIOZ_14 }; +static const unsigned int i2c_c_scl_z15_pins[] = { GPIOZ_15 }; + +/*bank Z func4 */ +static const unsigned int i2c_a_sda_z0_pins[] = { GPIOZ_0 }; +static const unsigned int i2c_a_scl_z1_pins[] = { GPIOZ_1 }; +static const unsigned int tdm_d6_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_d7_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_d8_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_d9_pins[] = { GPIOZ_5 }; +static const unsigned int tdm_fs2_pins[] = { GPIOZ_6 }; +static const unsigned int tdm_sclk2_pins[] = { GPIOZ_7 }; +static const unsigned int mclk_2_pins[] = { GPIOZ_8 }; +static const unsigned int tdm_d10_pins[] = { GPIOZ_9 }; +static const unsigned int tdm_d11_pins[] = { GPIOZ_10 }; +static const unsigned int tdm_d12_pins[] = { GPIOZ_11 }; +static const unsigned int tdm_d13_pins[] = { GPIOZ_12 }; +static const unsigned int tdm_d14_pins[] = { GPIOZ_13 }; + +/*bank Z func5 */ +static const unsigned int pwm_b_z0_pins[] = { GPIOZ_0 }; +static const unsigned int pwm_c_z_pins[] = { GPIOZ_1 }; +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_2 }; +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_3 }; +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_4 }; +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_5 }; +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_6 }; +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_7 }; +static const unsigned int iso7816_clk_z8_pins[] = { GPIOZ_8 }; +static const unsigned int iso7816_data_z9_pins[] = { GPIOZ_9 }; +static const unsigned int remote_out_z_pins[] = { GPIOZ_10 }; +static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 }; +static const unsigned int pwm_b_z13_pins[] = { GPIOZ_13 }; + +/*bank Z func6 */ +static const unsigned int i2c_b_sda_z_pins[] = { GPIOZ_0 }; +static const unsigned int i2c_b_scl_z_pins[] = { GPIOZ_1 }; +static const unsigned int tdm_fs3_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_sclk3_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_fs4_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_sclk4_pins[] = { GPIOZ_5 }; +static const unsigned int tsin_c_valid_z_pins[] = { GPIOZ_6 }; +static const unsigned int tsin_c_sop_z_pins[] = { GPIOZ_7 }; +static const unsigned int tsin_c_din0_z_pins[] = { GPIOZ_8 }; +static const unsigned int tsin_c_clk_z_pins[] = { GPIOZ_9 }; +static const unsigned int tsin_d_valid_z_pins[] = { GPIOZ_10 }; +static const unsigned int tsin_d_sop_z_pins[] = { GPIOZ_11 }; +static const unsigned int tsin_d_din0_z_pins[] = { GPIOZ_12 }; +static const unsigned int tsin_d_clk_z_pins[] = { GPIOZ_13 }; + +/*bank Z func7 */ +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_2 }; +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_3 }; +static const unsigned int pdm_din2_z_pins[] = { GPIOZ_4 }; +static const unsigned int pdm_din3_z_pins[] = { GPIOZ_5 }; +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_6 }; +static const unsigned int i2c_a_sda_z7_pins[] = { GPIOZ_7 }; +static const unsigned int i2c_a_scl_z8_pins[] = { GPIOZ_8 }; +static const unsigned int i2c_c_sda_z10_pins[] = { GPIOZ_10 }; +static const unsigned int i2c_c_scl_z11_pins[] = { GPIOZ_11 }; +static const unsigned int gen_clk_z_pins[] = { GPIOZ_13 }; + +/*bank A func1 */ +static const unsigned int remote_input_a_pins[] = { GPIOA_15 }; +/*bank A func3 */ +static const unsigned int i2c_d_sda_a_pins[] = { GPIOA_14 }; +static const unsigned int i2c_d_scl_a_pins[] = { GPIOA_15 }; +/*bank A func5 */ +static const unsigned int pdm_din0_a_pins[] = { GPIOA_14 }; +static const unsigned int pdm_dclk_a_pins[] = { GPIOA_15 }; +/*bank A func7 */ +static const unsigned int gen_clk_a_pins[] = { GPIOA_15 }; + +static struct meson_pmx_group meson_sc2_periphs_groups[] = { + GPIO_GROUP(GPIOD_0), + GPIO_GROUP(GPIOD_1), + GPIO_GROUP(GPIOD_2), + GPIO_GROUP(GPIOD_3), + GPIO_GROUP(GPIOD_4), + GPIO_GROUP(GPIOD_5), + GPIO_GROUP(GPIOD_6), + GPIO_GROUP(GPIOD_7), + GPIO_GROUP(GPIOD_8), + GPIO_GROUP(GPIOD_9), + GPIO_GROUP(GPIOD_10), + GPIO_GROUP(GPIOD_11), + GPIO_GROUP(GPIOE_0), + GPIO_GROUP(GPIOE_1), + GPIO_GROUP(GPIOE_2), + GPIO_GROUP(GPIOB_0), + GPIO_GROUP(GPIOB_1), + GPIO_GROUP(GPIOB_2), + GPIO_GROUP(GPIOB_3), + GPIO_GROUP(GPIOB_4), + GPIO_GROUP(GPIOB_5), + GPIO_GROUP(GPIOB_6), + GPIO_GROUP(GPIOB_7), + GPIO_GROUP(GPIOB_8), + GPIO_GROUP(GPIOB_9), + GPIO_GROUP(GPIOB_10), + GPIO_GROUP(GPIOB_11), + GPIO_GROUP(GPIOB_12), + GPIO_GROUP(GPIOB_13), + GPIO_GROUP(GPIOB_14), + GPIO_GROUP(GPIOB_15), + GPIO_GROUP(GPIOC_0), + GPIO_GROUP(GPIOC_1), + GPIO_GROUP(GPIOC_2), + GPIO_GROUP(GPIOC_3), + GPIO_GROUP(GPIOC_4), + GPIO_GROUP(GPIOC_5), + GPIO_GROUP(GPIOC_6), + GPIO_GROUP(GPIOC_7), + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + GPIO_GROUP(GPIOH_4), + GPIO_GROUP(GPIOH_5), + GPIO_GROUP(GPIOH_6), + GPIO_GROUP(GPIOH_7), + GPIO_GROUP(GPIOH_8), + GPIO_GROUP(GPIOZ_0), + GPIO_GROUP(GPIOZ_1), + GPIO_GROUP(GPIOZ_2), + GPIO_GROUP(GPIOZ_3), + GPIO_GROUP(GPIOZ_4), + GPIO_GROUP(GPIOZ_5), + GPIO_GROUP(GPIOZ_6), + GPIO_GROUP(GPIOZ_7), + GPIO_GROUP(GPIOZ_8), + GPIO_GROUP(GPIOZ_9), + GPIO_GROUP(GPIOZ_10), + GPIO_GROUP(GPIOZ_11), + GPIO_GROUP(GPIOZ_12), + GPIO_GROUP(GPIOZ_13), + GPIO_GROUP(GPIOZ_14), + GPIO_GROUP(GPIOZ_15), + GPIO_GROUP(GPIOA_14), + GPIO_GROUP(GPIOA_15), + GPIO_GROUP(GPIO_TEST_N), + + /* bank D func1 */ + GROUP(uart_b_tx_d, 1), + GROUP(uart_b_rx_d, 1), + GROUP(i2c_e_scl_d, 1), + GROUP(i2c_e_sda_d, 1), + GROUP(remote_out_d4, 1), + GROUP(remote_input_d5, 1), + GROUP(jtag_2_clk, 1), + GROUP(jtag_2_tms, 1), + GROUP(jtag_2_tdi, 1), + GROUP(jtag_2_tdo, 1), + GROUP(cec_a_d, 1), + + /* bank D funsc2 */ + GROUP(uart_a_tx_d2, 2), + GROUP(uart_a_rx_d3, 2), + GROUP(clk_32k_in, 2), + GROUP(remote_out_d9, 2), + GROUP(cec_b_d, 2), + GROUP(pwm_g_hiz, 2), + + /* bank D func3 */ + GROUP(i2c_slave_scl, 3), + GROUP(i2c_slave_sda, 3), + GROUP(pwm_i_d4, 3), + GROUP(pwm_j_d5, 3), + GROUP(pwm_i_d6, 3), + GROUP(uart_a_tx_d8, 3), + GROUP(uart_a_rx_d9, 3), + GROUP(pwm_j_d10, 3), + GROUP(pwm_g, 3), + + /* bank D func4 */ + GROUP(pwm_i_hiz, 4), + GROUP(tsin_a_sop_d, 4), + GROUP(tsin_a_din0_d, 4), + GROUP(tsin_a_clk_d, 4), + GROUP(tsin_a_valid_d, 4), + GROUP(spdif_out_d, 4), + GROUP(gen_clk_d, 4), + + /* bank D func5 */ + GROUP(mic_mute_en, 4), + GROUP(tdm_d0, 4), + GROUP(tdm_d1, 4), + GROUP(tdm_fs1, 4), + GROUP(tdm_sclk1, 4), + GROUP(mclk1, 4), + GROUP(tdm_d2_d, 4), + + /* bank D func6 */ + GROUP(clk12_24_d, 4), + + /* bank E func1 */ + GROUP(uart_b_cts, 1), + GROUP(uart_b_rts, 1), + GROUP(clk12_24_e, 1), + + /* bank E funsc2 */ + GROUP(uart_a_cts, 2), + GROUP(uart_a_rts, 2), + GROUP(clk25, 2), + + /* bank E func3 */ + GROUP(pwm_h, 3), + GROUP(pwm_j_e, 3), + GROUP(pwm_a_e, 3), + + /* bank E func4 */ + GROUP(i2c_e_scl_e, 4), + GROUP(i2c_e_sda_e, 4), + + /*bank E func5 */ + GROUP(mic_mute_key, 5), + + /* bank B func1 */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_dqs, 1), + + /* bank B funsc2 */ + GROUP(nand_wen_clk, 2), + GROUP(nand_ale, 2), + GROUP(nand_cle, 2), + GROUP(nand_ce0, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_rb0, 2), + GROUP(nand_ce1, 2), + + /* bank B func3 */ + GROUP(nor_hold, 3), + GROUP(nor_d, 3), + GROUP(nor_q, 3), + GROUP(nor_c, 3), + GROUP(nor_wp, 3), + GROUP(nor_cs, 3), + + /* bank C func1 */ + GROUP(sdcard_d0_c, 1), + GROUP(sdcard_d1_c, 1), + GROUP(sdcard_d2_c, 1), + GROUP(sdcard_d3_c, 1), + GROUP(sdcard_clk_c, 1), + GROUP(sdcard_cmd_c, 1), + GROUP(sdcard_cd, 1), + GROUP(pcieck_reqn, 1), + + /* bank C funsc2 */ + GROUP(jtag_1_tdo, 2), + GROUP(jtag_1_tdi, 2), + GROUP(uart_b_rx_c, 2), + GROUP(uart_b_tx_c, 2), + GROUP(jtag_1_clk, 2), + GROUP(jtag_1_tms, 2), + + /* bank C func3 */ + GROUP(tsin_c_valid_c, 3), + GROUP(tsin_c_sop_c, 3), + GROUP(tsin_c_din0_c, 3), + GROUP(tsin_c_clk_c, 3), + GROUP(i2c_a_sda_c, 3), + GROUP(i2c_a_scl_c, 3), + + /* bank C func4 */ + GROUP(pdm_din0_c, 4), + GROUP(pdm_din1_c1, 4), + GROUP(pdm_din2_c, 4), + GROUP(pdm_din3_c, 4), + GROUP(pdm_dclk_c, 4), + GROUP(pdm_din1_c7, 4), + + /* bank C func5 */ + GROUP(spi_a_mosi_c, 4), + GROUP(spi_a_miso_c, 4), + GROUP(spi_a_ss0_c, 4), + GROUP(spi_a_sclk_c, 4), + GROUP(pwm_c_c, 4), + GROUP(iso7816_clk_c, 4), + GROUP(iso7816_data_c, 4), + + /* bank X func1 */ + GROUP(sdio_d0_x, 1), + GROUP(sdio_d1_x, 1), + GROUP(sdio_d2_x, 1), + GROUP(sdio_d3_x, 1), + GROUP(sdio_clk_x, 1), + GROUP(sdio_cmd_x, 1), + GROUP(pwm_a_x, 1), + GROUP(pwm_f_x, 1), + GROUP(tdm_d3, 1), + GROUP(tdm_d4, 1), + GROUP(tdm_fs0, 1), + GROUP(tdm_sclk0, 1), + GROUP(uart_e_tx, 1), + GROUP(uart_e_rx, 1), + GROUP(uart_e_cts, 1), + GROUP(uart_e_rts, 1), + GROUP(pwm_e, 1), + GROUP(i2c_c_sda_x, 1), + GROUP(i2c_c_scl_x, 1), + GROUP(pwm_b_x19, 1), + + /* bank X funsc2 */ + GROUP(pdm_din0_x, 2), + GROUP(pdm_din1_x, 2), + GROUP(pdm_din2_x, 2), + GROUP(pdm_din3_x, 2), + GROUP(pdm_dclk_x, 2), + GROUP(mclk_0, 2), + GROUP(uart_d_tx_x6, 2), + GROUP(uart_d_rx_x7, 2), + GROUP(uart_d_rts, 2), + GROUP(uart_d_cts, 2), + GROUP(uart_d_tx_x10, 2), + GROUP(uart_d_rx_x11, 2), + GROUP(tdm_d15_x, 2), + + /* bank X func3 */ + GROUP(tsin_a_din0_x, 3), + GROUP(tsin_a_sop_x, 3), + GROUP(tsin_a_valid_x, 3), + GROUP(tsin_a_clk_x, 3), + GROUP(tsin_d_sop_x, 3), + GROUP(tsin_d_valid_x, 3), + GROUP(tsin_d_din0_x, 3), + GROUP(tsin_d_clk_x, 3), + + /* bank X func4 */ + GROUP(pwm_d_x3, 4), + GROUP(pwm_c_x, 4), + GROUP(pwm_d_x6, 4), + GROUP(pwm_b_x7, 4), + GROUP(spi_a_mosi_x, 4), + GROUP(spi_a_miso_x, 4), + GROUP(spi_a_ss0_x, 4), + GROUP(spi_a_sclk_x, 4), + + /* bank X func5 */ + GROUP(sdcard_d0_x, 5), + GROUP(sdcard_d1_x, 5), + GROUP(sdcard_d2_x, 5), + GROUP(sdcard_d3_x, 5), + GROUP(sdcard_clk_x, 5), + GROUP(sdcard_cd_x, 5), + GROUP(iso7816_clk_x, 5), + GROUP(iso7816_data_x, 5), + GROUP(i2c_b_sda_x, 5), + GROUP(i2c_b_scl_x, 5), + GROUP(gen_clk_x, 5), + + /* bank H func1 */ + GROUP(hdmitx_sda, 1), + GROUP(hdmitx_scl, 1), + GROUP(hdmitx_hpd_in, 1), + GROUP(spdif_out_h, 1), + GROUP(spdif_in_h, 1), + GROUP(iso7816_data_h, 1), + GROUP(iso7816_clk_h, 1), + + /* bank H funsc2 */ + GROUP(i2c_d_sda_h, 2), + GROUP(i2c_d_scl_h, 2), + GROUP(i2c_b_sda_h2, 2), + GROUP(i2c_b_scl_h3, 2), + GROUP(uart_c_rts, 2), + GROUP(uart_c_cts, 2), + GROUP(uart_c_rx, 2), + GROUP(uart_c_tx, 2), + + /* bank H func3 */ + GROUP(spi_b_mosi_h, 3), + GROUP(spi_b_miso_h, 3), + GROUP(spi_b_ss0_h, 3), + GROUP(spi_b_sclk_h, 3), + + /* bank H func4 */ + GROUP(cec_a_h, 4), + GROUP(pwm_f_h, 4), + GROUP(i2c_b_sda_h6, 4), + GROUP(i2c_b_scl_h7, 4), + + /* bank H func5 */ + GROUP(cec_b_h, 5), + GROUP(tdm_d5, 5), + GROUP(remote_out_h, 5), + GROUP(pwm_b_h, 5), + + /* bank H func6 */ + GROUP(i2c_a_sda_h, 6), + GROUP(i2c_a_scl_h, 6), + + /* bank Z func1 */ + GROUP(eth_mdio, 1), + GROUP(eth_mdc, 1), + GROUP(eth_rgmii_rx_clk, 1), + GROUP(eth_rx_dv, 1), + GROUP(eth_rxd0, 1), + GROUP(eth_rxd1, 1), + GROUP(eth_rxd2_rgmii, 1), + GROUP(eth_rxd3_rgmii, 1), + GROUP(eth_rgmii_tx_clk, 1), + GROUP(eth_txen, 1), + GROUP(eth_txd0, 1), + GROUP(eth_txd1, 1), + GROUP(eth_txd2_rgmii, 1), + GROUP(eth_txd3_rgmii, 1), + GROUP(eth_link_led, 1), + GROUP(eth_act_led, 1), + + /* bank Z funsc2 */ + GROUP(pwm_d_z, 2), + GROUP(clk12_24_z, 2), + + /* bank Z func3 */ + GROUP(iso7816_clk_z0, 3), + GROUP(iso7816_data_z1, 3), + GROUP(tsin_b_valid, 3), + GROUP(tsin_b_sop, 3), + GROUP(tsin_b_din0, 3), + GROUP(tsin_b_clk, 3), + GROUP(tsin_b_fail, 3), + GROUP(tsin_b_din1, 3), + GROUP(tsin_b_din2, 3), + GROUP(tsin_b_din3, 3), + GROUP(tsin_b_din4, 3), + GROUP(tsin_b_din5, 3), + GROUP(tsin_b_din6, 3), + GROUP(tsin_b_din7, 3), + GROUP(i2c_c_sda_z14, 3), + GROUP(i2c_c_scl_z15, 3), + + /* bank Z func4 */ + GROUP(i2c_a_sda_z0, 4), + GROUP(i2c_a_scl_z1, 4), + GROUP(tdm_d6, 4), + GROUP(tdm_d7, 4), + GROUP(tdm_d8, 4), + GROUP(tdm_d9, 4), + GROUP(tdm_fs2, 4), + GROUP(tdm_sclk2, 4), + GROUP(mclk_2, 4), + GROUP(tdm_d10, 4), + GROUP(tdm_d11, 4), + GROUP(tdm_d12, 4), + GROUP(tdm_d13, 4), + GROUP(tdm_d14, 4), + + /* bank Z func5 */ + GROUP(pwm_b_z0, 5), + GROUP(pwm_c_z, 5), + GROUP(sdcard_d0_z, 5), + GROUP(sdcard_d1_z, 5), + GROUP(sdcard_d2_z, 5), + GROUP(sdcard_d3_z, 5), + GROUP(sdcard_clk_z, 5), + GROUP(sdcard_cmd_z, 5), + GROUP(iso7816_clk_z8, 5), + GROUP(iso7816_data_z9, 5), + GROUP(remote_out_z, 5), + GROUP(pwm_f_z, 5), + GROUP(pwm_b_z13, 5), + + /* bank Z func6 */ + GROUP(i2c_b_sda_z, 6), + GROUP(i2c_b_scl_z, 6), + GROUP(tdm_fs3, 6), + GROUP(tdm_sclk3, 6), + GROUP(tdm_fs4, 6), + GROUP(tdm_sclk4, 6), + GROUP(tsin_c_valid_z, 6), + GROUP(tsin_c_sop_z, 6), + GROUP(tsin_c_din0_z, 6), + GROUP(tsin_c_clk_z, 6), + GROUP(tsin_d_valid_z, 6), + GROUP(tsin_d_sop_z, 6), + GROUP(tsin_d_din0_z, 6), + GROUP(tsin_d_clk_z, 6), + + /* bank Z func7 */ + GROUP(pdm_din0_z, 7), + GROUP(pdm_din1_z, 7), + GROUP(pdm_din2_z, 7), + GROUP(pdm_din3_z, 7), + GROUP(pdm_dclk_z, 7), + GROUP(i2c_a_sda_z7, 7), + GROUP(i2c_a_scl_z8, 7), + GROUP(i2c_c_sda_z10, 7), + GROUP(i2c_c_scl_z11, 7), + GROUP(gen_clk_z, 7), + + /* bank A func1 */ + GROUP(remote_input_a, 1), + /* bank A func3 */ + GROUP(i2c_d_sda_a, 3), + GROUP(i2c_d_scl_a, 3), + /* bank A func5 */ + GROUP(pdm_din0_a, 5), + GROUP(pdm_dclk_a, 5), + /* bank A func7 */ + GROUP(gen_clk_a, 7), + +}; + +static const char * const gpio_periphs_groups[] = { + "GPIO_TEST_N", + + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", + "GPIOD_5", "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", + "GPIOD_10", "GPIOD_11", "GPIOD_12", + + "GPIOE_0", "GPIOE_1", "GPIOE_2", + + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", + "GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", + "GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13", + "GPIOB_14", "GPIOB_15", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", + "GPIOC_5", "GPIOC_6", "GPIOC_7", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", + "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", + + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", + "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", + "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", + "GPIOZ_14", "GPIOZ_15", + + "GPIOA_14", "GPIOA_15", +}; + +static const char * const uart_a_groups[] = { + "uart_a_cts", "uart_a_rts", "uart_a_tx_d2", "uart_a_rx_d3", + "uart_a_tx_d8", "uart_a_rx_d9", +}; + +static const char * const uart_b_groups[] = { + "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts", "uart_b_rts", + "uart_b_rx_c", "uart_b_tx_c", +}; + +static const char * const uart_c_groups[] = { + "uart_c_rts", "uart_c_cts", "uart_c_tx", "uart_c_rx", +}; + +static const char * const uart_d_groups[] = { + "uart_d_rts", "uart_d_cts", "uart_d_tx_x6", "uart_d_tx_x10", + "uart_d_tx_x10", "uart_d_tx_x11", +}; + +static const char * const uart_e_groups[] = { + "uart_e_tx", "uart_e_rx", "uart_e_ctx", "uart_e_rtx", +}; + +static const char * const i2c_a_groups[] = { + "i2c_a_scl_c", "i2c_a_sda_c", "i2c_a_scl_h", "i2c_a_sda_h", + "i2c_a_scl_z1", "i2c_a_sda_z0", "i2c_a_scl_z8", "i2c_a_sda_z7", +}; + +static const char * const i2c_b_groups[] = { + "i2c_b_sda_z", "i2c_b_scl_z", "i2c_b_sda_x", "i2c_b_scl_x", + "i2c_b_sda_h2", "i2c_b_scl_h3", "i2c_b_sda_h6", "i2c_b_scl_h7", +}; + +static const char * const i2c_c_groups[] = { + "i2c_c_sda_x", "i2c_c_scl_x", "i2c_c_sda_z10", "i2c_c_scl_z11", + "i2c_c_sda_z14", "i2c_c_scl_z15", +}; + +static const char * const i2c_d_groups[] = { + "i2c_d_sda_h", "i2c_d_scl_h", "i2c_d_sda_a", "i2c_d_scl_a", +}; + +static const char * const i2c_e_groups[] = { + "i2c_e_sda_d", "i2c_e_scl_d", "i2c_e_sda_e", "i2c_e_scl_e", +}; + +static const char * const i2c_slave_groups[] = { + "i2c_slave_scl", "i2c_slave_sda", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a_e", "pwm_a_x", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_h", "pwm_b_z0", "pwm_b_z13", "pwm_b_x7", + "pwm_b_x19", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_c", "pwm_c_x", "pwm_c_z", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_z", "pwm_d_x3", "pwm_d_x6", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_x", "pwm_f_h", "pwm_f_z" +}; + +static const char * const pwm_g_groups[] = { + "pwm_g", +}; + +static const char * const pwm_h_groups[] = { + "pwm_h", +}; + +static const char * const pwm_i_groups[] = { + "pwm_i_d4", "pwm_i_d6", +}; + +static const char * const pwm_j_groups[] = { + "pwm_j_e", "pwm_j_d5", "pwm_j_d10", +}; + +static const char * const pwm_i_hiz_groups[] = { + "pwm_i_hiz", +}; + +static const char * const pwm_g_hiz_groups[] = { + "pwm_g_hiz", +}; + +static const char * const remote_out_groups[] = { + "remote_out_h", "remote_out_z", "remote_out_d4", "remote_out_d9", +}; + +static const char * const remote_input_groups[] = { + "remote_input_a", "remote_input_d5", +}; + +static const char * const jtag_1_groups[] = { + "jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo", +}; + +static const char * const jtag_2_groups[] = { + "jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms", +}; + +static const char * const gen_clk_groups[] = { + "gen_clk_d", "gen_clk_z", "gen_clk_a", "gen_clk_x", +}; + +static const char * const clk12_24_groups[] = { + "clk12_24_d", "clk12_24_e", "clk12_24_z", +}; + +static const char * const clk25_groups[] = { + "clk25", +}; + +static const char * const clk_32k_in_groups[] = { + "clk_32k_in", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_cmd", "emmc_nand_dqs", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_nand_dqs", "nand_wen_clk", "nand_ale", "nand_ren_wr", + "nand_cle", "nand_ce0", "nand_ce1", "nand_rb0", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", + "sdcaed_cd_c", "sdcard_clk_c", "sdcard_cmd_c", + + "sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x", + "sdcard_clk_x", "sdcard_cmd_x", + + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", + "sdcard_clk_z", "sdcard_cmd_z", +}; + +static const char * const nor_groups[] = { + "nor_hold", "nor_d", "nor_q", "nor_c", + "nor_wp", "nor_cs", +}; + +static const char * const spi_a_groups[] = { + "spi_a_mosi_c", "spi_a_miso_c", "spi_a_ss0_c", "spi_a_sclk_c", + "spi_a_mosi_x", "spi_a_miso_x", "spi_a_sclk_x", "spi_a_ss0_x", +}; + +static const char * const spi_b_groups[] = { + "spi_b_mosi_h", "spi_b_miso_h", "spi_b_ss0_h", "spi_b_sclk_h", +}; + +static const char * const pdm_groups[] = { + "pdm_din0_c", "pdm_din1_c1", "pdm_din2_c", "pdm_din3_c", + "pdm_din1_c7", "pdm_dclk_c", + + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x", + "pdm_dclk_x", + + "pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z", + "pdm_dclk_z", + + "pdm_din0_a", "pdm_dclk_a", + +}; + +static const char * const sdio_groups[] = { + "sdio_d0_x", "sdio_d1_x", "sdio_d2_x", "sdio_d3_x", + "sdio_clk_x", "sdio_cmd_x", +}; + +static const char * const eth_groups[] = { + "eth_mdc", "eth_mdio", "eth_rxd0", "eth_rxd1", + "eth_txen", "eth_txd0", "eth_txd1", "eth_rx_dv", + "eth_act_led", "eth_link_led", "eth_rxd2_rgmii", "eth_rxd3_rgmii", + "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk", + "eth_rgmii_tx_clk", +}; + +static const char * const mic_mute_groups[] = { + "mic_mute_en", "mic_mute_key", +}; + +static const char * const mclk_groups[] = { + "mclk1", "mclk_0", "mclk_2", +}; + +static const char * const tdm_groups[] = { + "tdm_d0", "tdm_d1", "tdm_d2", "tdm_d3", + "tdm_d4", "tdm_d5", "tdm_d6", "tdm_d7", + "tdm_d8", "tdm_d9", "tdm_d10", "tdm_d11", + "tdm_d12", "tdm_d13", "tdm_d14", "tdm_d15", + "tdm_fs0", "tdm_fs1", "tdm_fs2", "tdm_fs3", + "tdm_fs4", "tdm_sclk0", "tdm_sclk1", "tdm_sclk2", + "tdm_sclk3", "tdm_sclk4", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_sop_d", "tsin_a_clk_d", "tsin_a_clk_x", "tsin_sop_x", + "tsin_din0_d", "tsin_a_din0_x", "tsin_a_valid_d", "tsin_a_valid_x", +}; + +static const char * const tsin_b_groups[] = { + "tsin_b_sop", "tsin_b_clk", "tsin_b_din0", "tsin_fail", + "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", "tsin_b_din4", + "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", "tsin_b_valid", +}; + +static const char * const tsin_c_groups[] = { + "tsin_c_sop_c", "tsin_c_clk_c", "tsin_c_sop_z", "tsin_c_clk_z", + "tsin_c_din0_c", "tsin_din0_z", "tsin_c_valid_c", "tsin_c_valid_z", +}; + +static const char * const tsin_d_groups[] = { + "tsin_d_sop_x", "tsin_d_clk_x", "tsin_d_sop_z", "tsin_d_clk_z", + "tsin_d_din0_x", "tsin_d_din0_z", "tsin_d_valid_x", "tsin_d_valid_z", +}; + +static const char * const cec_a_groups[] = { + "cec_a_h", "cec_a_d", +}; + +static const char * const cec_b_groups[] = { + "cec_b_h", "cec_b_d", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in_h", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_d", "spdif_out_h", +}; + +static const char * const pcieck_reqn_groups[] = { + "pcieck_reqn", +}; + +static const char * const iso7816_groups[] = { + "iso7816_clk_c", "iso7816_clk_h", "iso7816_data_c", "iso7816_clk_x", + "iso7816_data_x", "iso7816_data_h", "iso7816_clk_z0", + "iso7816_clk_z8", "iso7816_data_z1", "is7816_data_z9", +}; + +static const char * const hdmitx_groups[] = { + "hdmitx_sda", "hdmitx_scl", "hdmitx_hpd_in", +}; + +static struct meson_pmx_func meson_sc2_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_d), + FUNCTION(uart_e), + FUNCTION(i2c_a), + FUNCTION(i2c_b), + FUNCTION(i2c_c), + FUNCTION(i2c_d), + FUNCTION(i2c_e), + FUNCTION(i2c_slave), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(pwm_g), + FUNCTION(pwm_h), + FUNCTION(pwm_i), + FUNCTION(pwm_j), + FUNCTION(pwm_i_hiz), + FUNCTION(pwm_g_hiz), + FUNCTION(remote_out), + FUNCTION(remote_input), + FUNCTION(jtag_1), + FUNCTION(jtag_2), + FUNCTION(gen_clk), + FUNCTION(clk12_24), + FUNCTION(clk25), + FUNCTION(clk_32k_in), + FUNCTION(emmc), + FUNCTION(nand), + FUNCTION(nor), + FUNCTION(sdcard), + FUNCTION(spi_a), + FUNCTION(spi_b), + FUNCTION(pdm), + FUNCTION(sdio), + FUNCTION(eth), + FUNCTION(mic_mute), + FUNCTION(mclk), + FUNCTION(tdm), + FUNCTION(tsin_a), + FUNCTION(tsin_b), + FUNCTION(tsin_c), + FUNCTION(tsin_d), + FUNCTION(cec_a), + FUNCTION(cec_b), + FUNCTION(spdif_in), + FUNCTION(spdif_out), + FUNCTION(pcieck_reqn), + FUNCTION(iso7816), + FUNCTION(hdmitx), +}; + +static struct meson_bank meson_sc2_periphs_banks[] = { + /* name first last pullen pull dir out in */ + BANK("GPIOZ_", GPIOZ_0, GPIOZ_15, + 0x3, 0, 0x4, 0, 0x2, 0, 0x1, 0, 0x0, 0), + BANK("GPIOX_", GPIOX_0, GPIOX_19, + 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0), + BANK("GPIOH_", GPIOH_0, GPIOH_8, + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0), + BANK("GPIOD_", GPIOD_0, GPIOD_11, + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0), + BANK("GPIOE_", GPIOE_0, GPIOE_2, + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0), + BANK("GPIOC_", GPIOC_0, GPIOC_7, + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0), + BANK("GPIOB_", GPIOB_0, GPIOB_15, + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0), + BANK("GPIOA_", GPIOA_14, GPIOA_15, + 0x73, 14, 0x74, 14, 0x72, 14, 0x71, 14, 0x70, 14), + BANK("GPIO_TEST_N", GPIO_TEST_N, GPIO_TEST_N, + 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0), +}; + +static struct meson_pmx_bank meson_sc2_periphs_pmx_banks[] = { + /*name first lask reg offset*/ + BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0), + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), + BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0), + BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0), + BANK_PMX("E", GPIOE_0, GPIOE_2, 0x12, 0), + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), + BANK_PMX("B", GPIOB_0, GPIOB_15, 0x0, 0), + BANK_PMX("A", GPIOA_14, GPIOA_15, 0xe, 24), + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0), +}; + +static struct meson_drive_bank meson_sc2_periphs_drive_banks[] = { + /* name first lask reg offset*/ + BANK_DRIVE("Z", GPIOZ_0, GPIOZ_15, 0x7, 0), + BANK_DRIVE("X", GPIOX_0, GPIOX_19, 0x17, 0), + BANK_DRIVE("H", GPIOH_0, GPIOH_8, 0x27, 0), + BANK_DRIVE("D", GPIOD_0, GPIOD_11, 0x37, 0), + BANK_DRIVE("E", GPIOE_0, GPIOE_2, 0x47, 0), + BANK_DRIVE("C", GPIOC_0, GPIOC_7, 0x57, 0), + BANK_DRIVE("B", GPIOB_0, GPIOB_15, 0x67, 0), + BANK_DRIVE("A", GPIOA_14, GPIOA_15, 0x77, 28), + BANK_DRIVE("TESTN", GPIO_TEST_N, GPIO_TEST_N, 0x87, 0), +}; + +static struct meson_axg_pmx_data meson_sc2_periphs_pmx_banks_data = { + .pmx_banks = meson_sc2_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_sc2_periphs_pmx_banks), +}; + +static struct meson_drive_data meson_sc2_periphs_drive_data = { + .drive_banks = meson_sc2_periphs_drive_banks, + .num_drive_banks = ARRAY_SIZE(meson_sc2_periphs_drive_banks), +}; + +static struct meson_pinctrl_data meson_sc2_periphs_pinctrl_data = { + .name = "periphs-banks", + .groups = meson_sc2_periphs_groups, + .funcs = meson_sc2_periphs_functions, + .banks = meson_sc2_periphs_banks, + .num_pins = 87, + .num_groups = ARRAY_SIZE(meson_sc2_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_sc2_periphs_functions), + .num_banks = ARRAY_SIZE(meson_sc2_periphs_banks), + .pmx_data = &meson_sc2_periphs_pmx_banks_data, + .drv_data = &meson_sc2_periphs_drive_data, +}; + +static const struct udevice_id meson_sc2_pinctrl_match[] = { + { + .compatible = "amlogic,meson-sc2-periphs-pinctrl", + .data = &meson_sc2_periphs_pinctrl_data, + }, + { }, +}; + +U_BOOT_DRIVER(meson_sc2_pinctrl) = { + .name = "meson-sc2-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_sc2_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto_alloc_size = sizeof(struct meson_pinctrl), + .ops = &meson_axg_pinctrl_ops, +};
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index c102fe3..98f13c6 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c
@@ -113,7 +113,7 @@ struct meson_pwm_priv *priv = dev_get_priv(dev); struct meson_pwm_reg *regs = priv->regs; struct meson_pwm_state *pwm_state = priv->pwm_state; - u32 clk_addr = priv->extern_clk_addr; + fdt_addr_t clk_addr = priv->extern_clk_addr; switch (channel) { case MESON_PWM0: @@ -278,7 +278,7 @@ struct meson_pwm_priv *priv = dev_get_priv(dev); struct meson_pwm_reg *regs = priv->regs; struct meson_pwm_state *pwm_state = priv->pwm_state; - u32 clk_addr = priv->extern_clk_addr; + fdt_addr_t clk_addr = priv->extern_clk_addr; unsigned int val, val_clk, orig; switch (channel) { @@ -319,7 +319,7 @@ struct meson_pwm_priv *priv = dev_get_priv(dev); struct meson_pwm_reg *regs = priv->regs; struct meson_pwm_state *pwm_state = priv->pwm_state; - u32 clk_addr = priv->extern_clk_addr; + fdt_addr_t clk_addr = priv->extern_clk_addr; unsigned int val, val_clk, orig; switch (channel) { @@ -510,18 +510,19 @@ priv->pwm_data = (struct meson_pwm_data *)dev_get_driver_data(dev); priv->regs = (struct meson_pwm_reg *)dev_read_addr_index(dev, 0); - if (priv->regs == FDT_ADDR_T_NONE) { + if (priv->regs == (void *)FDT_ADDR_T_NONE) { pr_err("Coun't get pwm base regs addr\n"); return -1; } /* If you use external clk, get clk regs addr */ - if (priv->pwm_data->extern_clk) + if (priv->pwm_data->extern_clk) { priv->extern_clk_addr = dev_read_addr_index(dev, 1); - if (priv->regs == FDT_ADDR_T_NONE) { + if (priv->extern_clk_addr == FDT_ADDR_T_NONE) { pr_err("Coun't get pwm clk regs addr\n"); return -1; } + } priv->pwm_state = (struct meson_pwm_state *)calloc(4, sizeof(struct meson_pwm_state)); @@ -541,7 +542,7 @@ .extern_clk = 0, }; -static const struct meson_pwm_data pwm_meson_a1_data = { +static const struct meson_pwm_data pwm_meson_v2_data = { .extern_clk = 1, }; @@ -557,7 +558,7 @@ static const struct udevice_id meson_pwm_ids[] = { {.compatible = "amlogic,g12a-ee-pwm", .data = (long)&pwm_meson_g12a_data}, {.compatible = "amlogic,g12a-ao-pwm", .data = (long)&pwm_meson_g12a_data}, - {.compatible = "amlogic,a1-pwm", .data = (long)&pwm_meson_a1_data}, + {.compatible = "amlogic,meson-v2-pwm", .data = (long)&pwm_meson_v2_data}, {} };
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c index 53ac469..10c3d0d 100644 --- a/drivers/serial/serial_meson.c +++ b/drivers/serial/serial_meson.c
@@ -75,12 +75,13 @@ return readl(&uart->rfifo) & 0xff; #else - return 0; + return 0; #endif } static int meson_serial_putc(struct udevice *dev, const char ch) { +#ifndef CONFIG_SILENT_CONSOLE struct meson_serial_platdata *plat = dev->platdata; struct meson_uart *const uart = plat->reg; @@ -89,6 +90,7 @@ writel(ch, &uart->wfifo); +#endif return 0; }
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index af9aef0..e6877c7 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c
@@ -323,6 +323,8 @@ return -EIO; #else +/* meson need suppport x2 x4 */ +#ifndef CONFIG_MTD_SPI_NAND /* U-Boot does not support parallel SPI data lanes */ if ((op->cmd.buswidth != 1) || (op->addr.nbytes && op->addr.buswidth != 1) || @@ -331,7 +333,7 @@ printf("Dual/Quad raw SPI transfers not supported\n"); return -ENOTSUPP; } - +#endif if (op->data.nbytes) { if (op->data.dir == SPI_MEM_DATA_IN) rx_buf = op->data.buf.in;
diff --git a/drivers/spi/spicc.c b/drivers/spi/spicc.c index 98f8111..4ed2cb6 100644 --- a/drivers/spi/spicc.c +++ b/drivers/spi/spicc.c
@@ -180,22 +180,17 @@ bool has_enhance_clk_div; bool has_cs_pre_delay; bool has_enhance_io_delay; - bool has_comp_clk; - bool is_div_parent_comp_clk; + bool has_async_clk; + bool is_div_parent_async_clk; bool has_enhance_tt_ti_delay; }; struct meson_spicc_device { void __iomem *base; -#ifdef CONFIG_CLK_IF - struct clk core; - struct clk comp; - struct clk clk; -#else + u32 pm_id; u32 parent_clk_rate; u32 speed_hz; u32 real_speed_hz; -#endif int num_chipselect; struct gpio_desc cs_gpios[CS_GPIO_MAX]; const struct meson_spicc_data *data; @@ -242,11 +237,8 @@ mi_delay = SPICC_MI_NO_DELAY; cap_delay = SPICC_CAP_AHEAD_2_CYCLE; -#ifdef CONFIG_CLK_IF - hz = clk_get_rate(&spicc->clk); -#else + hz = spicc->real_speed_hz; -#endif if (hz >= 100000000) cap_delay = SPICC_CAP_DELAY_1_CYCLE; else if (hz >= 80000000) @@ -422,10 +414,6 @@ static int spicc_set_speed(struct udevice *bus, uint hz) { struct meson_spicc_device *spicc = dev_get_priv(bus); - -#ifdef CONFIG_CLK_IF - clk_set_rate(&spicc->clk, hz); -#else u32 sys_clk_rate, div, mid, real_hz; u32 regv; @@ -435,10 +423,9 @@ sys_clk_rate = spicc->parent_clk_rate; if (spicc->data->has_enhance_clk_div) { /* speed = sys_clk_rate / 2 / (div+1) */ - div = sys_clk_rate/hz; - if (div < 2) - div = 2; - div = (div >> 1) - 1; + div = DIV_ROUND_UP(sys_clk_rate, hz << 1); + if (div) + div--; if (div > 0xff) div = 0xff; regv = readl_relaxed(spicc->base + SPICC_ENH_CTL0); @@ -465,7 +452,6 @@ spicc->speed_hz = hz; spicc->real_speed_hz = real_hz; spicc_dbg("set speed %dHz (real %dHz)\n", hz, real_hz); -#endif meson_spicc_auto_io_delay(spicc); @@ -508,7 +494,7 @@ writel_relaxed(conf, spicc->base + SPICC_TESTREG); spicc->mode = mode; - spicc_dbg("set mode %d\n", mode); + spicc_dbg("set mode 0x%x\n", mode); return 0; } @@ -583,85 +569,29 @@ static int spicc_clk_init(struct udevice *bus) { struct meson_spicc_device *spicc = dev_get_priv(bus); -#ifdef CONFIG_CLK_IF - int ret; + struct clk clk; - /* Get core clk */ - ret = clk_get_by_name(bus, "core", &spicc->core); - if (ret) { - spicc_err("get clk_core failed(%d)\n", ret); - return ret; - } - ret = clk_enable(&spicc->core); - if (ret) { - spicc_err("enable clk_core failed(%d)\n", ret); - return ret; + spicc->parent_clk_rate = 0; + if (!clk_get_by_name(bus, "core", &clk)) { + if (!spicc->data->is_div_parent_async_clk) + spicc->parent_clk_rate = clk_get_rate(&clk); } - /* Get composite clk */ - if (spicc->data->has_comp_clk) { - ret = clk_get_by_name(bus, "comp", &spicc->comp); - if (ret) { - spicc_err("get clk_comp failed(%d)\n", ret); - return ret; + if (!clk_get_by_name(bus, "core-gate", &clk)) + clk_enable(&clk); + + if (spicc->data->has_async_clk) { + if (!clk_get_by_name(bus, "async", &clk)) { + if (spicc->data->is_div_parent_async_clk) + spicc->parent_clk_rate = clk_get_rate(&clk); } - ret = clk_enable(&spicc->comp); - if (ret) { - spicc_err("enable clk_comp failed(%d)\n", ret); - return ret; - } - clk_set_parent(&spicc->clk, &spicc->comp); + + if (!clk_get_by_name(bus, "async-gate", &clk)) + clk_enable(&clk); } - else - clk_set_parent(&spicc->clk, &spicc->core); -#elif defined CONFIG_CLK_MESON_C1 - u32 regv; - /* spicc a */ - regv = readl(CLKTREE_SPICC_CLK_CTRL); - regv &= ~0xfff; - /* src [11~9]: 0 = div2(768M) - * gate [8]: 1 - * rate[7~ 0]: 4 = 768M/4 = 192000000 - */ - regv |= (0 << 9) | (1 << 8) | (4 << 0); - writel(regv, CLKTREE_SPICC_CLK_CTRL); - spicc->parent_clk_rate = 192000000; - /* spicc b */ - regv = readl(CLKTREE_SPICC_CLK_CTRL); - regv &= ~0xfff0000; - /* src [11~25]: 0 = div2(768M) - * gate [24]: 1 - * rate[23~16]: 4 = 768M/4 = 192000000 - */ - regv |= (0 << 25) | (1 << 24) | (4 << 16); - writel(regv, CLKTREE_SPICC_CLK_CTRL); - spicc->parent_clk_rate = 192000000; -#else - u32 regv; - u8 mux=3, div = 0; - unsigned long comp_rate[] = { - 24000000, /* XTAL */ - 166666666, /* CLK81 */ - 500000000, /* FCLK_DIV4 */ - 666666666, /* FCLK_DIV3 */ - 1000000000, /* FCLK_DIV2 */ - 400000000, /* FCLK_DIV5 */ - 285700000, /* FCLK_DIV7 */ - }; - - regv = readl(P_HHI_SPICC_CLK_CNTL); - /* mux[25:23], gate[22], div[21:16] */ - regv &= ~((0x7 << 23) | (1 << 22) | (0x3f << 16)); - regv |= (mux << 23) | (1 << 22) | (div << 16); - writel(regv, P_HHI_SPICC_CLK_CNTL); - spicc->parent_clk_rate = comp_rate[mux]; - - regv = readl(P_HHI_GCLK_MPEG0); - regv |= 1 << 14; - writel(regv, P_HHI_GCLK_MPEG0); -#endif - return 0; + spicc_info("parent clk rate %d\n", spicc->parent_clk_rate); + return spicc->parent_clk_rate ? 0 : -ENODEV; } static int spicc_cs_init(struct udevice *bus) @@ -696,8 +626,10 @@ spicc->base = (void __iomem *)dev_read_addr(bus); #ifdef CONFIG_SECURE_POWER_CONTROL - /* SPICC_A enabled in bl2 already */ - pwr_ctrl_psci_smc(PM_SPICC_B, true); + if (!dev_read_u32(bus, "pm-id", &spicc->pm_id)) { + pwr_ctrl_psci_smc(spicc->pm_id, true); + spicc_info("power on %d\n", spicc->pm_id); + } #endif spicc_info("0x%p\n", spicc->base); if (spicc_clk_init(bus)) @@ -725,6 +657,9 @@ return 0; } +/* g9tv/gxbb */ + +/* gxtvbb/gxl/gxm/ (LD_CNTL) */ static const struct meson_spicc_data meson_spicc_gx_data = { .min_speed_hz = 325000, .max_speed_hz = 4166667, @@ -732,6 +667,7 @@ .fifo_size = 16, }; +/* txl/gxlx/txlx (ENHANCE_CNTL) */ static const struct meson_spicc_data meson_spicc_txlx_data = { .min_speed_hz = 325000, .max_speed_hz = 83333333, @@ -742,6 +678,7 @@ .has_cs_pre_delay = true, }; +/* axg (ENHANCE_CNTL1, async-clk is only used for delay ctrl) */ static const struct meson_spicc_data meson_spicc_axg_data = { .min_speed_hz = 325000, .max_speed_hz = 83333333, @@ -750,9 +687,11 @@ .has_enhance_clk_div = true, .has_cs_pre_delay = true, .has_enhance_io_delay = true, - .has_comp_clk = true, + .has_async_clk = true, }; +/* g12a (ENHANCE_CNTL2, async-clk can be used for spi-io-clk) + txhd hasn't ENHANCE_CNTL2 */ static const struct meson_spicc_data meson_spicc_g12a_data = { .min_speed_hz = 50000, .max_speed_hz = 166666667, @@ -761,8 +700,8 @@ .has_enhance_clk_div = true, .has_cs_pre_delay = true, .has_enhance_io_delay = true, - .has_comp_clk = true, - .is_div_parent_comp_clk = true, + .has_async_clk = true, + .is_div_parent_async_clk = true, .has_enhance_tt_ti_delay = true, };
diff --git a/drivers/spi/spifc.c b/drivers/spi/spifc.c index e359c69..1fed6ee 100644 --- a/drivers/spi/spifc.c +++ b/drivers/spi/spifc.c
@@ -19,6 +19,9 @@ #include <dm/util.h> #include <dm/pinctrl.h> + +//#define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO + DECLARE_GLOBAL_DATA_PTR; struct spifc_regs { @@ -151,6 +154,12 @@ { unsigned int val; + val = 1 << USER_CMD_INCLUDE_DIN; +#ifdef CONFIG_SPIFC_COMPATIBLE_TO_APPOLO + val |= 1 << COMPATIBLE_TO_APPOLO; +#endif + writel(val, &priv->regs->user); + val = readl(&priv->regs->ctrl); val &= ~((1 << FAST_READ_DUAL_OUT) | (1 << FAST_READ_QUAD_OUT) | @@ -171,8 +180,12 @@ static void spifc_set_tx_op_mode(struct spifc_priv *priv, unsigned int slave_mode, unsigned char cmd) { - unsigned int val = 0; + unsigned int val; + val = 1 << USER_CMD_INCLUDE_DOUT; +#ifdef CONFIG_SPIFC_COMPATIBLE_TO_APPOLO + val |= 1 << COMPATIBLE_TO_APPOLO; +#endif if (slave_mode & SPI_TX_QUAD) { if (cmd == FCMD_WRITE_QUAD_OUT) val |= 1 << FAST_WRITE_QUAD_OUT; @@ -194,17 +207,18 @@ (1 << FAST_READ_QUAD_OUT) | (1 << FAST_READ_DUAL_IO) | (1 << FAST_READ_QUAD_IO)); - writel((1 << USER_CMD_INCLUDE_CMD) | - ((!!len) << USER_CMD_INCLUDE_ADDR), - ®s->user); + writel((1 << USER_CMD_INCLUDE_CMD) +#ifdef CONFIG_SPIFC_COMPATIBLE_TO_APPOLO + | (1 << COMPATIBLE_TO_APPOLO) +#endif + | ((!!len) << USER_CMD_INCLUDE_ADDR), + ®s->user); writel((7 << USER_CMD_CMD_BITS) | (cmd << USER_CMD_CMD_VALUE), ®s->user2); writel(bits << USER_CMD_ADDR_BITS, ®s->user1); writel(addr << SPI_FLASH_ADDR_START, ®s->addr); - writel((1 << SPI_FLASH_USR) | - (cmd << SPI_FLASH_USR_CMD), - ®s->cmd); + writel(1 << SPI_FLASH_USR, ®s->cmd); while ((readl(®s->cmd) >> SPI_FLASH_USR) & 1) ; return 0; @@ -224,10 +238,7 @@ for (i = 0; i < len32; i++) writel(*p++, cache++); - setbits_le32(®s->user, 1 << USER_CMD_INCLUDE_DOUT); - writel(0, ®s->user2); writel(((len << 3) - 1) << USER_CMD_DOUT_BITS, ®s->user1); - writel(0, ®s->addr); writel(1 << SPI_FLASH_USR, ®s->cmd); while ((readl(®s->cmd) >> SPI_FLASH_USR) & 1) ; @@ -243,10 +254,7 @@ int len32, i; u8 temp_buf[SPIFC_CACHE_SIZE_IN_BYTE]; - writel(1 << USER_CMD_INCLUDE_DIN, ®s->user); - writel(0, ®s->user2); writel(((len << 3) - 1) << USER_CMD_DIN_BITS, ®s->user1); - writel(0, ®s->addr); writel(1 << SPI_FLASH_USR, ®s->cmd); while ((readl(®s->cmd) >> SPI_FLASH_USR) & 1) ; @@ -289,7 +297,7 @@ return ret; } -static int spifc_release_bus(struct udevice *bus) +static int spifc_release_bus(struct udevice *dev) { return 0; } @@ -330,8 +338,7 @@ if (div < 2) { pr_err("%s %d can not support %d speed!\n", __func__, __LINE__, hz); - if (!plat->speed) - div = 2; + div = 2; hz = SPIFC_MAX_CLK_RATE / div; } #ifdef CONFIG_SPIFC_COMPATIBLE_TO_APPOLO @@ -391,9 +398,9 @@ printf("%s: error bitlen\n", __func__); return -EINVAL; } - spifc_claim_bus(dev); - spifc_set_speed(bus, slave->max_hz); - spifc_set_mode(bus, slave->mode); +// spifc_claim_bus(dev); +// spifc_set_speed(bus, slave->max_hz); +// spifc_set_mode(bus, slave->mode); if (flags & SPI_XFER_BEGIN) { spifc_chipselect(dev, 1); buf = (u8 *)dout; @@ -443,16 +450,10 @@ priv->regs = (struct spifc_regs *)plat->reg; #if defined(CONFIG_CLK) && (CONFIG_CLK) - ret = clk_get_by_name(bus, "core", &priv->core); - if (ret) { - printf("can't get clk source!\n"); - return ret; - } - ret = clk_enable(&priv->core); - if (ret) { - printf("enable clk source fail\n"); - return ret; - } + if (clk_get_by_name(bus, "core", &priv->core)) + printf("%s can't get clk source!\n", __func__); + else if (clk_enable(&priv->core)) + printf("%s enable clk source fail\n", __func__); #endif/* CONFIG_CLK */ ret = gpio_request_by_name(bus, "cs-gpios",
diff --git a/drivers/spi/spifc_v2.c b/drivers/spi/spifc_v2.c index b373af7..9acd20a 100644 --- a/drivers/spi/spifc_v2.c +++ b/drivers/spi/spifc_v2.c
@@ -201,10 +201,20 @@ static int spifc_claim_bus(struct udevice *dev) { - return 0; + struct udevice *bus = dev->parent; + int ret = 0; + + /* In consideration of compatibility with other storage media, + * reset pinmux to spifc here. + */ + ret = pinctrl_select_state(bus, "default"); + if (ret) + pr_err("select state %s failed\n", "default"); + + return ret; } -static int spifc_release_bus(struct udevice *bus) +static int spifc_release_bus(struct udevice *dev) { return 0; } @@ -284,7 +294,8 @@ return -EINVAL; } - spifc_claim_bus(dev); + /* spi core will call back, No need to call repeatedly */ + //spifc_claim_bus(dev); spifc_set_speed(bus, slave->max_hz); spifc_set_mode(bus, slave->mode); if (flags & SPI_XFER_BEGIN) { @@ -311,6 +322,7 @@ } else priv->save_addr = 0; + priv->cmd = buf[0]; } } else if (dout && priv->cmd) { @@ -353,6 +365,15 @@ struct spifc_priv *priv = dev_get_priv(bus); int ret = 0; + /* In consideration of compatibility with other storage media, + * reset pinmux to spifc here. + */ + ret = pinctrl_select_state(bus, "default"); + if (ret) { + pr_err("select state %s failed\n", "default"); + return ret; + } + #if defined(CONFIG_CLK) && (CONFIG_CLK) ret = clk_get_by_name(bus, "fclk_source", &priv->spifc_source); if (ret) { @@ -423,15 +444,11 @@ plat->speed = fdtdec_get_uint(blob, node, "max-frequency", 40000000); - plat->io_num = fdtdec_get_uint(blob, node, - "max-io", - 2);/* default 2 because some board only have 2 spifc io */ plat->max_cs = fdtdec_get_uint(blob, node, "max-cs", 2); plat->mode = 0; - printf("spifc freq %d, max io %d, reg %p\n", - plat->speed, plat->io_num, (void *)plat->reg); + printf("spifc freq %d reg %p\n", plat->speed, (void *)plat->reg); return 0; }
diff --git a/drivers/ssr/Kconfig b/drivers/ssr/Kconfig new file mode 100644 index 0000000..766ac45 --- /dev/null +++ b/drivers/ssr/Kconfig
@@ -0,0 +1,9 @@ +# +# Schumacher (Nest PS13216 SSR) device +# + +config SCHUMACHER_SSR + tristate "Schumacher SSR" + help + Select this to enable PS13216 Solid-State Relay (SSR) support. This driver + controls the SSR via i2c bus.
diff --git a/drivers/ssr/Makefile b/drivers/ssr/Makefile new file mode 100644 index 0000000..9d4fa2b --- /dev/null +++ b/drivers/ssr/Makefile
@@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for Shumacher (SSR) devices +# + +obj-${CONFIG_SCHUMACHER_SSR} += ps13216_ssr.o +
diff --git a/drivers/ssr/ps13216_ssr.c b/drivers/ssr/ps13216_ssr.c new file mode 100644 index 0000000..d98e365 --- /dev/null +++ b/drivers/ssr/ps13216_ssr.c
@@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Author: + * Paul Wang <tzupengwang@google.com> + * + * Description: + * Driver for Schumacher (Photeon ps13216 Solid-State Relay) + * + * This simplified version of the PS13216 driver only supports HVSENSE reading. + * + * Copyright 2021 Google LLC. + */ + +#include <asm-generic/gpio.h> +#include <dm/device.h> +#include <dm/uclass-id.h> +#include <i2c.h> +#include <linux/compat.h> +#include <linux/delay.h> +#include <linux/ssr/ps13216_regs.h> +#include <linux/ssr/ps13216.h> + +/** + * Misc constants + */ + +// It takes 34 ms to go from OFF state to RUN state +#define PS13216_IF_EN_STARTUP_DELAY_MS 34 +#define PS13216_HVSENSE_ADC_CAM_DELAY_MS 128 +#define PS13216_ADC_FIFO_BANK_BYTES 256 + +// Delay value for charge pumps. ADC readings +// taken before the charge pumps have fully +// charged will be inaccurate. +#define PS13216_CHARGE_PUMP_DELAY_MS 30 + +struct ps13216_device { + struct gpio_desc *enable_gpio; + u8 adc_fifo_data[PS13216_ADC_FIFO_BANK_BYTES]; +}; + +int get_ssr_hvsense_voltage(struct udevice *dev, int *mean_squared_voltage, + int *peak_voltage) { + struct ps13216_device *ps = dev->platdata; + u16 fifo_len; + u8 *fifo_data_ptr; + size_t sample_count; + size_t idx; + int raw_voltage; + + // Clear ADC EOC (End of Conversion) event flag. + dm_i2c_reg_write(dev, PS13216_REG_EVENT1, PS13216_M_EVENT1_EOC); + + dm_i2c_reg_write(dev, PS13216_REG_ADC_CTRL, + (PS13216_V_ADC_CTRL_MODE(PS13216_ADC_MODE_CAM) | + PS13216_M_ADC_CTRL_HV_SENSE)); + mdelay(PS13216_HVSENSE_ADC_CAM_DELAY_MS); + + dm_i2c_reg_write(dev, PS13216_REG_ADC_CTRL, 0x00); + + // Read FIFO length + dm_i2c_read(dev, PS13216_REG_ADC_FIFO_FILL_CNT_LSB, (u8 *)&fifo_len, 2); + + for (idx = 0; idx < fifo_len; idx ++) { + dm_i2c_read(dev, PS13216_REG_ADC_FIFO, &ps->adc_fifo_data[idx], 1); + } + + // Each voltage read takes 2 bytes + sample_count = fifo_len / 2; + if (sample_count == 0) { + return -EAGAIN; + } + + fifo_data_ptr = ps->adc_fifo_data; + *mean_squared_voltage = 0; + *peak_voltage = INT_MIN; + + for (idx = 0; idx < sample_count; fifo_data_ptr += 2, ++idx) { + raw_voltage = ((int)fifo_data_ptr[1] << 8) | fifo_data_ptr[0]; + *mean_squared_voltage += raw_voltage * raw_voltage; + if (*peak_voltage < raw_voltage) + *peak_voltage = raw_voltage; + } + *mean_squared_voltage /= sample_count; + + return 0; +} + +static int ps13216_probe(struct udevice *dev) { + struct ps13216_device *ps = dev->platdata; + int ret; + + // Initialize SSR_EN gpio and enable Schumacher + ret = gpio_request_by_name(dev, "enable-gpios", 0, + ps->enable_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret < 0) { + dev_err(dev, "%s: failed to initialize enable_gpio.\n", __func__); + goto error; + } + mdelay(PS13216_IF_EN_STARTUP_DELAY_MS); + + dev_info(dev, "%s: probe successfully!\n", __func__); + + return 0; + +error: + dev_err(dev, "%s: error %d\n", __func__, ret); + return ret; +} + +static struct udevice_id ps13216_of_match[] = { + { + .compatible = "photeon,ps13216", + }, + { }, +}; + +U_BOOT_DRIVER(ps13216_ssr) = { + .name = "ps13216-ssr", + .id = UCLASS_I2C_GENERIC, + .of_match = ps13216_of_match, + .platdata_auto_alloc_size = sizeof(struct ps13216_device), + .probe = ps13216_probe, +};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 12c6c84..0bc204c 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig
@@ -39,6 +39,7 @@ config USB_GADGET_MANUFACTURER string "Vendor name of the USB device" default "Allwinner Technology" if ARCH_SUNXI + default "Amlogic Inc." if ARCH_MESON default "U-Boot" help Vendor name of the USB device emulated, reported to the host device. @@ -47,6 +48,7 @@ config USB_GADGET_VENDOR_NUM hex "Vendor ID of the USB device" default 0x1f3a if ARCH_SUNXI + default 0x1b8e if ARCH_MESON default 0x0 help Vendor ID of the USB device emulated, reported to the host device. @@ -56,6 +58,7 @@ config USB_GADGET_PRODUCT_NUM hex "Product ID of the USB device" default 0x1010 if ARCH_SUNXI + default 0xc004 if ARCH_MESON default 0x0 help Product ID of the USB device emulated, reported to the host device.
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 639093f..a9d8763 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile
@@ -3,7 +3,7 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o +obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o platform.o obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o obj-$(CONFIG_FASTBOOT_DWC_PCD) += fastboot/dwc_pcd.o fastboot/dwc_pcd_irq.o
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 495d225..8c37c96 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c
@@ -19,6 +19,7 @@ #include <linux/usb/composite.h> #include <linux/compiler.h> #include <g_dnl.h> +#include <partition_table.h> #define FASTBOOT_INTERFACE_CLASS 0xff #define FASTBOOT_INTERFACE_SUB_CLASS 0x42 @@ -28,6 +29,8 @@ #define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040) #define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040) +#define DEVICE_SERIAL "1234567890" + #define EP_BUFFER_SIZE 4096 /* * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size @@ -35,6 +38,8 @@ * that expect bulk OUT requests to be divisible by maxpacket size. */ +extern void f_dwc_otg_pullup(int is_on); + struct f_fastboot { struct usb_function usb_function; @@ -140,6 +145,13 @@ static void fastboot_complete(struct usb_ep *ep, struct usb_request *req) { int status = req->status; + + if ( (busy_flag == 1) && fastboot_func) { + struct usb_ep* out_ep = fastboot_func->out_ep; + struct usb_request* out_req = fastboot_func->out_req; + rx_handler_command(out_ep, out_req); + return; + } if (!status) return; printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual); @@ -185,8 +197,11 @@ } s = env_get("serial#"); - if (s) + if (s) { + printf("serial num: %s\n", s); g_dnl_set_serialnumber((char *)s); + } else + g_dnl_set_serialnumber(DEVICE_SERIAL); return 0; } @@ -319,18 +334,20 @@ static int fastboot_add(struct usb_configuration *c) { - struct f_fastboot *f_fb = fastboot_func; + struct f_fastboot *f_fb; int status; debug("%s: cdev: 0x%p\n", __func__, c->cdev); - if (!f_fb) { + if (fastboot_func == NULL) { f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb)); if (!f_fb) return -ENOMEM; fastboot_func = f_fb; memset(f_fb, 0, sizeof(*f_fb)); + } else { + f_fb = fastboot_func; } f_fb->usb_function.name = "f_fastboot"; @@ -344,7 +361,7 @@ status = usb_add_function(c, &f_fb->usb_function); if (status) { free(f_fb); - fastboot_func = f_fb; + fastboot_func = NULL; } return status; @@ -374,9 +391,26 @@ static void compl_do_reset(struct usb_ep *ep, struct usb_request *req) { + f_dwc_otg_pullup(0); do_reset(NULL, 0, 0, NULL); } +static void compl_do_reboot_bootloader(struct usb_ep *ep, struct usb_request *req) +{ + f_dwc_otg_pullup(0); + if (dynamic_partition) + run_command("reboot bootloader", 0); + else + run_command("reboot fastboot", 0); +} + +static void compl_do_reboot_fastboot(struct usb_ep *ep, struct usb_request *req) +{ + f_dwc_otg_pullup(0); + run_command("reboot fastboot", 0); +} + + static unsigned int rx_bytes_expected(struct usb_ep *ep) { int rx_remain = fastboot_data_remaining(); @@ -427,7 +461,6 @@ */ req->complete = rx_handler_command; req->length = EP_BUFFER_SIZE; - fastboot_tx_write_str(response); } else { req->length = rx_bytes_expected(ep); @@ -450,10 +483,12 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) { - char *cmdbuf = req->buf; + char cmdbuf[256]; char response[FASTBOOT_RESPONSE_LEN] = {0}; int cmd = -1; + strncpy(cmdbuf, req->buf, 256); + if (req->status != 0 || req->length == 0) return; @@ -483,13 +518,20 @@ break; case FASTBOOT_COMMAND_REBOOT: - case FASTBOOT_COMMAND_REBOOT_BOOTLOADER: fastboot_func->in_req->complete = compl_do_reset; break; + case FASTBOOT_COMMAND_REBOOT_BOOTLOADER: + fastboot_func->in_req->complete = compl_do_reboot_bootloader; + break; + case FASTBOOT_COMMAND_REBOOT_FASTBOOT: + fastboot_func->in_req->complete = compl_do_reboot_fastboot; + break; } } - *cmdbuf = '\0'; - req->actual = 0; - usb_ep_queue(ep, req, 0); + if (busy_flag == 0) { + *cmdbuf = '\0'; + req->actual = 0; + usb_ep_queue(ep, req, 0); + } }
diff --git a/drivers/usb/gadget/fastboot/dwc_pcd.c b/drivers/usb/gadget/fastboot/dwc_pcd.c index 81b4b04..dd725f6 100644 --- a/drivers/usb/gadget/fastboot/dwc_pcd.c +++ b/drivers/usb/gadget/fastboot/dwc_pcd.c
@@ -7,7 +7,7 @@ #include "usb_ch9.h" #include "dwc_pcd.h" #include "dwc_pcd_irq.h" -#include "platform.c" +#include "../platform.h" gadget_wrapper_t gadget_wrapper; @@ -122,7 +122,7 @@ DBG("\ndwc_otg core init enter!\n"); - f_set_usb_phy_config(); + set_usb_phy_config(0); if (0x4F543000 != (dwc_read_reg32(DWC_REG_GSNPSID) & 0xFFFFF000)) { ERR("Bad value for SNPSID\n"); @@ -688,7 +688,7 @@ if (!sof) { ERR("sof timeout, reset usb phy tuning\n"); - set_usb_phy21_tuning_fb_reset(); + set_usb_phy21_tuning_update_reset(); mdelay(150); }
diff --git a/drivers/usb/gadget/fastboot/dwc_pcd_irq.c b/drivers/usb/gadget/fastboot/dwc_pcd_irq.c index 7ba7380..92bb0d1 100644 --- a/drivers/usb/gadget/fastboot/dwc_pcd_irq.c +++ b/drivers/usb/gadget/fastboot/dwc_pcd_irq.c
@@ -7,7 +7,7 @@ #include "usb_ch9.h" #include "dwc_pcd.h" #include "dwc_pcd_irq.h" -#include "platform.h" +#include "../platform.h" static void ep0_out_start(void); static int ep0_complete_request( pcd_struct_t * pcd); @@ -666,7 +666,7 @@ printf("SPEED ENUM\n"); #ifdef CONFIG_USB_DEVICE_V2 - set_usb_phy21_tuning_fb(); + set_usb_phy21_tuning_update(); #endif gadget_wrapper.pcd.ep0state = EP0_IDLE;
diff --git a/drivers/usb/gadget/fastboot/platform.c b/drivers/usb/gadget/fastboot/platform.c deleted file mode 100644 index 70711e7..0000000 --- a/drivers/usb/gadget/fastboot/platform.c +++ /dev/null
@@ -1,817 +0,0 @@ -/* platform dirver header */ -/* - * (C) Copyright 2010 Amlogic, Inc - * - * Victor Wan, victor.wan@amlogic.com, - * 2010-03-24 @ Shanghai - * - */ - #include "platform.h" -#include <amlogic/cpu_id.h> -#include <asm/arch/secure_apb.h> - -/*CONFIG_AML_MESON_8 include m8, m8baby, m8m2, etc... defined in cpu.h*/ -#if !(defined(CONFIG_USB_XHCI_HCD) || defined(CONFIG_USB_DWC_OTG_294)) -#error "platform is not GX !!" -#endif -#if !(defined (CONFIG_USB_DEVICE_V2)) -#error "define CONFIG_USB_DEVICE_V2 !!" - -#endif - -#if (defined AML_USB_V2) -#define PREI_USB_PHY_2_REG_BASE 0xfe004420 -#define PREI_USB_PHY_3_REG_BASE 0xfe004480 -#define PLL_REG32_16 (0xFe004000 + 0x40) -#define PLL_REG32_17 (0xFe004000 + 0x44) -#define PLL_REG32_18 (0xFe004000 + 0x48) -#define USB_PHY2_ENABLE 0x10000000 -#define USB_PHY2_RESET 0x20000000 -#define USB_REG_B 0xFe004000 -#define USB_RESET1 (volatile unsigned long *)0xfe000004 -#define P_AO_RTI_GEN_PWR_SLEEP0 0xfe007808 -#define P_AO_RTI_GEN_PWR_ISO0 0xfe007804 -#define P_HHI_MEM_PD_REG0 0xfe007850 - -typedef struct u2p_aml_regs { - volatile uint32_t u2p_r0; - volatile uint32_t u2p_r1; -} u2p_aml_regs_t; - -typedef union u2p_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned host_device:1; - unsigned power_ok:1; - unsigned hast_mode:1; - unsigned POR:1; - unsigned IDPULLUP0:1; - unsigned DRVVBUS0:1; - unsigned reserved:26; - } b; -} u2p_r0_t; - -typedef union u2p_r1 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned phy_rdy:1; - unsigned IDDIG0:1; - unsigned OTGSESSVLD0:1; - unsigned VBUSVALID0:1; - unsigned reserved:28; - } b; -} u2p_r1_t; - -typedef struct usb_aml_regs { - volatile uint32_t usb_r0; - volatile uint32_t usb_r1; - volatile uint32_t usb_r2; - volatile uint32_t usb_r3; - volatile uint32_t usb_r4; - volatile uint32_t usb_r5; -} usb_aml_regs_t; - -typedef union usb_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned reserved:17; - unsigned p30_lane0_tx2rx_loopback:1; - unsigned p30_lane0_ext_pclk_reg:1; - unsigned p30_pcs_rx_los_mask_val:10; - unsigned u2d_ss_scaledown_mode:2; - unsigned u2d_act:1; - } b; -} usb_r0_t; - -typedef union usb_r1 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned u3h_bigendian_gs:1; - unsigned u3h_pme_en:1; - unsigned u3h_hub_port_overcurrent:3; - unsigned reserved_1:2; - unsigned u3h_hub_port_perm_attach:3; - unsigned reserved_2:2; - unsigned u3h_host_u2_port_disable:2; - unsigned reserved_3:2; - unsigned u3h_host_u3_port_disable:1; - unsigned u3h_host_port_power_control_present:1; - unsigned u3h_host_msi_enable:1; - unsigned u3h_fladj_30mhz_reg:6; - unsigned p30_pcs_tx_swing_full:7; - } b; -} usb_r1_t; - -typedef union usb_r2 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned reserved:20; - unsigned p30_pcs_tx_deemph_3p5db:6; - unsigned p30_pcs_tx_deemph_6db:6; - } b; -} usb_r2_t; - -typedef union usb_r3 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p30_ssc_en:1; - unsigned p30_ssc_range:3; - unsigned p30_ssc_ref_clk_sel:9; - unsigned p30_ref_ssp_en:1; - unsigned reserved:18; - } b; -} usb_r3_t; - -typedef union usb_r4 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p21_PORTRESET0:1; - unsigned p21_SLEEPM0:1; - unsigned mem_pd:2; - unsigned p21_only:1; - unsigned reserved:27; - } b; -} usb_r4_t; - -typedef union usb_r5 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned iddig_sync:1; - unsigned iddig_reg:1; - unsigned iddig_cfg:2; - unsigned iddig_en0:1; - unsigned iddig_en1:1; - unsigned iddig_curr:1; - unsigned usb_iddig_irq:1; - unsigned iddig_th:8; - unsigned iddig_cnt:8; - unsigned reserved:8; - } b; -} usb_r5_t; - -static void set_usb_phy21_pll(void) -{ - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16)) - = (0x09400414 | USB_PHY2_RESET | USB_PHY2_ENABLE); - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) = - 0x927e0000; - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) = - 0xAC5F69E5; - udelay(100); - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16)) - = (((0x09400414) | (USB_PHY2_ENABLE)) - & (~(USB_PHY2_RESET))); -} - -void set_usb_phy21_tuning_fb(void) -{ - unsigned long phy_reg_base = USB_REG_B; - - (*(volatile uint32_t *)(phy_reg_base + 0x54)) = 0x2a; - (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3 & (0x1f << 16); - return; -} - -void set_usb_phy21_tuning_fb_reset(void) -{ - return; -} - -void f_set_usb_phy_config(void) -{ - u2p_r0_t dev_u2p_r0; - u2p_r1_t dev_u2p_r1; - - usb_r0_t dev_usb_r0; - usb_r4_t dev_usb_r4; - - u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE; - usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE; - int cnt; - u32 val; - cpu_id_t cpu_id = get_cpu_id(); - - printf("PHY2=0x%08x\n", PREI_USB_PHY_2_REG_BASE); - - val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0; - *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<24)); - val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0; - *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<24)); - val = *(volatile uint32_t *)P_HHI_MEM_PD_REG0; - *(volatile uint32_t *)P_HHI_MEM_PD_REG0 = val & (~(0x3)); - - if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) - *(unsigned int *)(CLKTREE_USB_BUSCLK_CTRL) = 0x509; - else - *(unsigned int *)(CLKTREE_USB_BUSCLK_CTRL) = 0x300; - - if ((*(volatile uint32_t *)(USB_REG_B + 0x38)) != 0) { - set_usb_phy21_tuning_fb_reset(); - mdelay(150); - } - - //step 1: usb controller reset - *USB_RESET1 = (1 << USB_GENERAL_BIT); - - // step 3: enable usb INT internal USB - dev_usb_r0.d32 = usb_aml_regs->usb_r0; - dev_usb_r0.b.u2d_ss_scaledown_mode = 0; - dev_usb_r0.b.u2d_act = 1; - usb_aml_regs->usb_r0 = dev_usb_r0.d32; - - // step 4: disable usb phy sleep - dev_usb_r4.d32 = usb_aml_regs->usb_r4; - dev_usb_r4.b.p21_SLEEPM0 = 1; - usb_aml_regs->usb_r4 = dev_usb_r4.d32; - - // step 5: config phy21 device mode - dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; - dev_u2p_r0.b.host_device= 0; - dev_u2p_r0.b.POR= 0; - u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; - - udelay(10); - //step 6: phy21 reset - *USB_RESET1 = (1 << USB_PHY21_BIT); - - udelay(50); - // step 6: wait for phy ready - dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; - cnt = 0; - while ((dev_u2p_r1.d32 & 0x00000001) != 1) { - dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; - if (cnt > 200) - break; - else { - cnt++; - udelay(5); - } - } - - set_usb_phy21_pll(); - - //-------------------------------------------------- - - // ------------- usb phy21 initinal end ---------- - - //-------------------------------------------------- - -} - -#else - -#if (defined CONFIG_USB_XHCI_HCD) -#if (defined AML_TXLX_USB) -#define PREI_USB_PHY_2_REG_BASE 0xffe09020 -#define PREI_USB_PHY_3_REG_BASE 0xffe09080 -#else -#define PREI_USB_PHY_2_REG_BASE 0xd0078020 -#define PREI_USB_PHY_3_REG_BASE 0xd0078080 -#endif - -#if (defined CONFIG_USB_DEVICE_V2) -typedef struct u2p_aml_regs { - volatile uint32_t u2p_r0; - volatile uint32_t u2p_r1; -} u2p_aml_regs_t; - -typedef union u2p_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned host_device:1; - unsigned power_ok:1; - unsigned hast_mode:1; - unsigned POR:1; - unsigned IDPULLUP0:1; - unsigned DRVVBUS0:1; - unsigned reserved:26; - } b; -} u2p_r0_t; - -typedef union u2p_r1 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned phy_rdy:1; - unsigned IDDIG0:1; - unsigned OTGSESSVLD0:1; - unsigned VBUSVALID0:1; - unsigned reserved:28; - } b; -} u2p_r1_t; - -typedef struct usb_aml_regs { - volatile uint32_t usb_r0; - volatile uint32_t usb_r1; - volatile uint32_t usb_r2; - volatile uint32_t usb_r3; - volatile uint32_t usb_r4; - volatile uint32_t usb_r5; -} usb_aml_regs_t; - -typedef union usb_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned reserved:17; - unsigned p30_lane0_tx2rx_loopback:1; - unsigned p30_lane0_ext_pclk_reg:1; - unsigned p30_pcs_rx_los_mask_val:10; - unsigned u2d_ss_scaledown_mode:2; - unsigned u2d_act:1; - } b; -} usb_r0_t; - -typedef union usb_r1 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned u3h_bigendian_gs:1; - unsigned u3h_pme_en:1; - unsigned u3h_hub_port_overcurrent:3; - unsigned reserved_1:2; - unsigned u3h_hub_port_perm_attach:3; - unsigned reserved_2:2; - unsigned u3h_host_u2_port_disable:2; - unsigned reserved_3:2; - unsigned u3h_host_u3_port_disable:1; - unsigned u3h_host_port_power_control_present:1; - unsigned u3h_host_msi_enable:1; - unsigned u3h_fladj_30mhz_reg:6; - unsigned p30_pcs_tx_swing_full:7; - } b; -} usb_r1_t; - -typedef union usb_r2 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned reserved:20; - unsigned p30_pcs_tx_deemph_3p5db:6; - unsigned p30_pcs_tx_deemph_6db:6; - } b; -} usb_r2_t; - -typedef union usb_r3 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p30_ssc_en:1; - unsigned p30_ssc_range:3; - unsigned p30_ssc_ref_clk_sel:9; - unsigned p30_ref_ssp_en:1; - unsigned reserved:18; - } b; -} usb_r3_t; - -typedef union usb_r4 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p21_PORTRESET0:1; - unsigned p21_SLEEPM0:1; - unsigned mem_pd:2; - unsigned p21_only:1; - unsigned reserved:27; - } b; -} usb_r4_t; - -typedef union usb_r5 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned iddig_sync:1; - unsigned iddig_reg:1; - unsigned iddig_cfg:2; - unsigned iddig_en0:1; - unsigned iddig_en1:1; - unsigned iddig_curr:1; - unsigned usb_iddig_irq:1; - unsigned iddig_th:8; - unsigned iddig_cnt:8; - unsigned reserved:8; - } b; -} usb_r5_t; - -#define PLL_REG32_16 (0xFF63A000 + 0x40) -#define PLL_REG32_17 (0xFF63A000 + 0x44) -#define PLL_REG32_18 (0xFF63A000 + 0x48) -#define USB_PHY2_ENABLE 0x10000000 -#define USB_PHY2_RESET 0x20000000 - -static void set_usb_phy21_pll(void) -{ - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16)) - = (USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET | USB_PHY2_ENABLE); - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) = - USB_PHY2_PLL_PARAMETER_2; - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) = - USB_PHY2_PLL_PARAMETER_3; - udelay(100); - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16)) - = (((USB_PHY2_PLL_PARAMETER_1) | (USB_PHY2_ENABLE)) - & (~(USB_PHY2_RESET))); -} - -static int f_platform_usb_check_g12b_revb (void) -{ - int rev_flag = 0; - - cpu_id_t cpu_id = get_cpu_id(); - - if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) { - if (cpu_id.chip_rev == 0xb) - rev_flag = 1; - else - rev_flag = 0; - } else { - rev_flag = 0; - } - - return rev_flag; -} - -#ifdef CONFIG_USB_DEVICE_V2 -#define USB_REG_B 0xFF63A000 - -void set_usb_phy21_tuning_fb(void) -{ - unsigned long phy_reg_base = USB_REG_B; - - if (f_platform_usb_check_g12b_revb()) { - (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1; - (*(volatile uint32_t *)(phy_reg_base + 0x54)) = 0x2a; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3 & (0x1f << 16); - return; - } - - (*(volatile uint32_t *)(phy_reg_base + 0x10)) = USB_G12x_PHY_PLL_SETTING_2; - (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1; - (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB_G12x_PHY_PLL_SETTING_5; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3; -} - -void set_usb_phy21_tuning_fb_reset(void) -{ - unsigned long phy_reg_base = USB_REG_B; - - if (f_platform_usb_check_g12b_revb()) - return; - - (*(volatile uint32_t *)(phy_reg_base + 0x38)) = 0x0; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3; -} - -#endif - -#if (defined AML_TXLX_USB) -#define USB_RESET1 (volatile unsigned long *)0xffd04408 -#else -#define USB_RESET1 (volatile unsigned long *)0xc1104408 -#endif - -void f_set_usb_phy_config(void) -{ - u2p_r0_t dev_u2p_r0; - u2p_r1_t dev_u2p_r1; - - usb_r0_t dev_usb_r0; - usb_r4_t dev_usb_r4; - - u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE; - usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE; - int cnt; - - printf("PHY2=0x%08x\n", PREI_USB_PHY_2_REG_BASE); -#ifdef CONFIG_USB_DEVICE_V2 - if ((*(volatile uint32_t *)(USB_REG_B + 0x38)) != 0) { - set_usb_phy21_tuning_fb_reset(); - mdelay(150); - } -#endif - - //step 1: usb controller reset - *USB_RESET1 |= (1<<2); - - // step 3: enable usb INT internal USB - dev_usb_r0.d32 = usb_aml_regs->usb_r0; - dev_usb_r0.b.u2d_ss_scaledown_mode = 0; - dev_usb_r0.b.u2d_act = 1; - usb_aml_regs->usb_r0 = dev_usb_r0.d32; - - // step 4: disable usb phy sleep - dev_usb_r4.d32 = usb_aml_regs->usb_r4; - dev_usb_r4.b.p21_SLEEPM0 = 1; - usb_aml_regs->usb_r4 = dev_usb_r4.d32; - - // step 5: config phy21 device mode - dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; - dev_u2p_r0.b.host_device= 0; - dev_u2p_r0.b.POR= 0; - u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; - - udelay(10); - //step 6: phy21 reset - *USB_RESET1 |= (1<<17); - - udelay(50); - // step 6: wait for phy ready - dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; - cnt = 0; - while ((dev_u2p_r1.d32 & 0x00000001) != 1) { - dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; - if (cnt > 200) - break; - else { - cnt++; - udelay(5); - } - } - - set_usb_phy21_pll(); - //-------------------------------------------------- - - // ------------- usb phy21 initinal end ---------- - - //-------------------------------------------------- - -} - -#else -typedef struct u2p_aml_regs { - volatile uint32_t u2p_r0; - volatile uint32_t u2p_r1; - volatile uint32_t u2p_r2; -} u2p_aml_regs_t; - -typedef union u2p_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned bypass_sel:1; - unsigned bypass_dm_en:1; - unsigned bypass_dp_en:1; - unsigned txbitstuffenh:1; - unsigned txbitstuffen:1; - unsigned dmpulldown:1; - unsigned dppulldown:1; - unsigned vbusvldextsel:1; - unsigned vbusvldext:1; - unsigned adp_prb_en:1; - unsigned adp_dischrg:1; - unsigned adp_chrg:1; - unsigned drvvbus:1; - unsigned idpullup:1; - unsigned loopbackenb:1; - unsigned otgdisable:1; - unsigned commononn:1; - unsigned fsel:3; - unsigned refclksel:2; - unsigned por:1; - unsigned vatestenb:2; - unsigned set_iddq:1; - unsigned ate_reset:1; - unsigned fsv_minus:1; - unsigned fsv_plus:1; - unsigned bypass_dm_data:1; - unsigned bypass_dp_data:1; - unsigned not_used:1; - } b; -} u2p_r0_t; - -typedef struct usb_aml_regs { - volatile uint32_t usb_r0; - volatile uint32_t usb_r1; - volatile uint32_t usb_r2; - volatile uint32_t usb_r3; - volatile uint32_t usb_r4; - volatile uint32_t usb_r5; - volatile uint32_t usb_r6; -} usb_aml_regs_t; - -typedef union usb_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p30_fsel:6; - unsigned p30_phy_reset:1; - unsigned p30_test_powerdown_hsp:1; - unsigned p30_test_powerdown_ssp:1; - unsigned p30_acjt_level:5; - unsigned p30_tx_vboost_lvl:3; - unsigned p30_lane0_tx2rx_loopbk:1; - unsigned p30_lane0_ext_pclk_req:1; - unsigned p30_pcs_rx_los_mask_val:10; - unsigned u2d_ss_scaledown_mode:2; - unsigned u2d_act:1; - } b; -} usb_r0_t; - -typedef union usb_r4 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p21_PORTRESET0:1; - unsigned p21_SLEEPM0:1; - unsigned mem_pd:2; - unsigned reserved4:28; - } b; -} usb_r4_t; - -#if (defined AML_TXLX_USB) -#define P_RESET1_REGISTER (volatile unsigned long *)0xffd01008 -#define P_AO_RTC_ALT_CLK_CNTL0 (volatile uint32_t *)(0xff800000 + (0x25 << 2)) -#define P_AO_RTI_PWR_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x04 << 2)) -#else -#define P_RESET1_REGISTER (volatile unsigned long *)0xc1104408 -#define P_AO_RTC_ALT_CLK_CNTL0 (volatile uint32_t *)(0xc8100000 + (0x25 << 2)) -#define P_AO_RTI_PWR_CNTL_REG0 (volatile uint32_t *)(0xc8100000 + (0x04 << 2)) -#endif - -void f_set_usb_phy_config(void) -{ - const int time_dly = 500; - u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE; - usb_aml_regs_t * usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE; - - u2p_r0_t u2p_r0; - usb_r0_t usb_r0; - usb_r4_t usb_r4; - - *P_RESET1_REGISTER = (1<<2); - - *P_AO_RTC_ALT_CLK_CNTL0 |= (1<<31)|(1<<30); - *P_AO_RTI_PWR_CNTL_REG0 |= (4<<10); - - u2p_r0.d32 = u2p_aml_regs->u2p_r0; -#if (defined CONFIG_AML_MESON_GXTVBB) - u2p_r0.b.fsel = 5; - -#elif (defined CONFIG_AML_MESON_GXL) - u2p_r0.b.fsel = 2; -#endif - u2p_r0.b.por = 1; - u2p_r0.b.dppulldown = 0; - u2p_r0.b.dmpulldown = 0; - u2p_aml_regs->u2p_r0 = u2p_r0.d32; - - u2p_r0.d32 = u2p_aml_regs->u2p_r0; - u2p_r0.b.por = 0; - u2p_aml_regs->u2p_r0 = u2p_r0.d32; - - usb_r0.d32 = usb_aml_regs->usb_r0; - usb_r0.b.u2d_act = 1; - usb_aml_regs->usb_r0 = usb_r0.d32; - - usb_r4.d32 = usb_aml_regs->usb_r4; - usb_r4.b.p21_SLEEPM0 = 1; - usb_aml_regs->usb_r4 = usb_r4.d32; - - udelay(time_dly); - return; -} -#endif - -#endif - -#if (defined CONFIG_USB_DWC_OTG_294) - -/* - cfg = 0 : EXT clock - cfg = 1 : INT clock - */ - -#define PREI_USB_PHY_A_REG_BASE 0xC0000000 -#define PREI_USB_PHY_B_REG_BASE 0xC1108420 - -#ifdef __USE_PORT_B -#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_B_REG_BASE -#else -#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_A_REG_BASE -#endif -#define P_RESET1_REGISTER_USB (volatile unsigned long *)0xc1104408 - -#define USB_CLK_SEL_XTAL 0 -#define USB_CLK_SEL_XTAL_DIV_2 1 -#define USB_CLK_SEL_DDR_PLL 2 -#define USB_CLK_SEL_MPLL_OUT0 3 -#define USB_CLK_SEL_MPLL_OUT1 4 -#define USB_CLK_SEL_MPLL_OUT2 5 -#define USB_CLK_SEL_FCLK_DIV2 6 -#define USB_CLK_SEL_FCLK_DIV3 7 - -typedef struct usb_aml_regs { - volatile uint32_t config; - volatile uint32_t ctrl; - volatile uint32_t endp_intr; - volatile uint32_t adp_bc; - volatile uint32_t dbg_uart; - volatile uint32_t test; - volatile uint32_t tune; -} usb_aml_regs_t; - -typedef union usb_config_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned clk_en :1; - unsigned clk_sel :3; - unsigned clk_div :7; - unsigned reserved0 :1; - unsigned clk_32k_alt_sel:1; - unsigned reserved1 :15; - unsigned test_trig :1; - } b; -} usb_config_data_t; - -typedef union usb_ctrl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned soft_prst:1; - unsigned soft_hreset:1; - unsigned ss_scaledown_mode:2; - unsigned clk_det_rst:1; - unsigned intr_sel:1; - unsigned reserved:2; - unsigned clk_detected:1; - unsigned sof_sent_rcvd_tgl:1; - unsigned sof_toggle_out:1; - unsigned not_used:4; - unsigned por:1; - unsigned sleepm:1; - unsigned txbitstuffennh:1; - unsigned txbitstuffenn:1; - unsigned commononn:1; - unsigned refclksel:2; - unsigned fsel:3; - unsigned portreset:1; - unsigned thread_id:6; - } b; -} usb_ctrl_data_t; - -void f_set_usb_phy_config(void) -{ - const int time_dly = 5000; - usb_aml_regs_t * usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_REG_BASE; - usb_config_data_t config; - usb_ctrl_data_t control; - - *P_RESET1_REGISTER_USB = (1<<2); - udelay(time_dly); - - config.d32 = usb_aml_regs->config; - usb_aml_regs->config = config.d32; - - control.d32 = usb_aml_regs->ctrl; - control.b.fsel = 5; - control.b.por = 1; - usb_aml_regs->ctrl = control.d32; - udelay(time_dly); - - control.b.por = 0; - usb_aml_regs->ctrl = control.d32; - udelay(time_dly); - - control.d32 = usb_aml_regs->ctrl; - if (!control.b.clk_detected) { - printf("Error, usb phy clock not detected!\n"); - } - - return; -} - -#endif - -#endif
diff --git a/drivers/usb/gadget/fastboot/platform.h b/drivers/usb/gadget/fastboot/platform.h deleted file mode 100644 index ef68a63..0000000 --- a/drivers/usb/gadget/fastboot/platform.h +++ /dev/null
@@ -1,113 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#ifndef __PLATFORM_H__ -#define __PLATFORM_H__ - -#include <asm/arch/register.h> - -/* A3,CS2,M3 chip, PORT_A is OTG, work as ROM Boot port */ -#ifdef __USE_PORT_B -#define PORT_REG_OFFSET 0x80000 -#else -#define PORT_REG_OFFSET 0 -#endif - -#if (defined AML_USB_V2) -#define DWC_REG_BASE 0xff500000 -#else -#if (defined AML_TXLX_USB) -#if ((defined CONFIG_USB_XHCI_HCD)) -#define DWC_REG_BASE 0xff400000 -#else -#define DWC_REG_BASE (0xff500000 + PORT_REG_OFFSET) -#endif -#else -#if ((defined CONFIG_USB_XHCI_HCD)) -#define DWC_REG_BASE 0xc9100000 -#else -#define DWC_REG_BASE (0xC9000000 + PORT_REG_OFFSET) -#endif -#endif -#endif - -#define PREI_USB_PHY_A_POR (1 << 0) -#define PREI_USB_PHY_B_POR (1 << 1) -#define PREI_USB_PHY_CLK_SEL (7 << 5) -#define PREI_USB_PHY_CLK_GATE (1 << 8) -#define PREI_USB_PHY_B_AHB_RSET (1 << 11) -#define PREI_USB_PHY_B_CLK_RSET (1 << 12) -#define PREI_USB_PHY_B_PLL_RSET (1 << 13) -#define PREI_USB_PHY_A_AHB_RSET (1 << 17) -#define PREI_USB_PHY_A_CLK_RSET (1 << 18) -#define PREI_USB_PHY_A_PLL_RSET (1 << 19) -#define PREI_USB_PHY_A_DRV_VBUS (1 << 20) -#define PREI_USB_PHY_B_DRV_VBUS (1 << 21) -#define PREI_USB_PHY_B_CLK_DETECT (1 << 22) -#define PREI_USB_PHY_CLK_DIV (0x7f << 24) -#define PREI_USB_PHY_A_CLK_DETECT (1 << 31) - -#define PREI_USB_PHY_A_REG3_IDDIG_OVR (1 << 23) -#define PREI_USB_PHY_A_REG3_IDDIG_VAL (1 << 24) - -#define PREI_USB_PHY_B_REG4_IDDIG_OVR (1 << 23) -#define PREI_USB_PHY_B_REG4_IDDIG_VAL (1 << 24) - -#define IREG_TIMER_E_COUNT 0x2655 - - -#define flush_cpu_cache() - - -#define dwc_write_reg32(x, v) (*(volatile uint32_t *)(unsigned long)(x + DWC_REG_BASE))=v -#define dwc_read_reg32(x) (*(volatile uint32_t*)(unsigned long)(x + DWC_REG_BASE)) -#define dwc_modify_reg32(x, c, s) (*(volatile uint32_t *)(x + DWC_REG_BASE))=( ((dwc_read_reg32(x)) & (~c)) | (s)) - -#define get_unaligned(ptr) ( ((unsigned long)ptr & 3) ? \ - (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) : \ - (*(uint32_t*)ptr) ) -#define get_unaligned_16(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8)) -#define get_unaligned_32(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) - -#define EXT_CLOCK 0 -#define INT_CLOCK 1 - -#define USB_ROM_CONN_TIMEOUT 5*1000*1000 - - -/* Meet with spec */ -#define USB_ROM_VER_MAJOR 0 -#define USB_ROM_STAGE_MAJOR 0 -#define USB_ROM_STAGE_MINOR 16 - -#ifdef CONFIG_M6 -#define USB_ROM_VER_MINOR 8 -#else -#define USB_ROM_VER_MINOR 7 -#endif - -#define PRINTF(x...) do{}while(0) - -#define ERR(x...) printf(x) -#define DBG(x...) PRINTF(x) - -#define USB_ERR(x...) printf("USBErr:%d", __LINE__),printf(x) -#define USB_DBG(x...) PRINTF(x) - - -void f_set_usb_phy_config(void); -#ifdef CONFIG_USB_DEVICE_V2 -void set_usb_phy21_tuning_fb(void); -#endif - -void usb_parameter_init(int timeout); -int chip_utimer_set(int val); -int chip_watchdog(void); -#define udelay __udelay -#define wait_ms(a) udelay(a*1000); -int update_utime(void); -int get_utime(void); - -#endif
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index e9e1600..aa836bc 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c
@@ -45,7 +45,7 @@ static const char product[] = "USB download gadget"; static char g_dnl_serial[MAX_STRING_SERIAL]; -static const char manufacturer[] = CONFIG_USB_GADGET_MANUFACTURER; +static const char manufacturer[] = "Amlogic"; void g_dnl_set_serialnumber(char *s) { @@ -61,8 +61,8 @@ .bDeviceClass = USB_CLASS_PER_INTERFACE, .bDeviceSubClass = 0, /*0x02:CDC-modem , 0x00:CDC-serial*/ - .idVendor = __constant_cpu_to_le16(CONFIG_USB_GADGET_VENDOR_NUM), - .idProduct = __constant_cpu_to_le16(CONFIG_USB_GADGET_PRODUCT_NUM), + .idVendor = 0x18d1, + .idProduct = 0x0d02, /* .iProduct = DYNAMIC */ /* .iSerialNumber = DYNAMIC */ .bNumConfigurations = 1,
diff --git a/drivers/usb/gadget/platform.c b/drivers/usb/gadget/platform.c new file mode 100644 index 0000000..05fc07b --- /dev/null +++ b/drivers/usb/gadget/platform.c
@@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include "platform.h" +#include <amlogic/cpu_id.h> +#include <asm/arch/secure_apb.h> +#include <asm/arch/usb.h> + +void dwc_write_reg32(unsigned int x, unsigned int v) +{ + unsigned int addr; + + addr = usb_get_dwc_a_base_addr(); + (*(volatile uint32_t *)(unsigned long)(x + addr))=v; +} +unsigned int dwc_read_reg32(unsigned int x) +{ + unsigned int addr; + + addr = usb_get_dwc_a_base_addr(); + return (*(volatile uint32_t*)((unsigned long)(x + addr))); +} + +void dwc_modify_reg32(unsigned int x, unsigned int c, unsigned int s) +{ + unsigned int addr; + + addr = usb_get_dwc_a_base_addr(); + (*(volatile uint32_t *)(unsigned long)(x + addr)) = + ( ((dwc_read_reg32(x)) & (~c)) | (s)); +} + +void set_usb_phy21_tuning_update(void) +{ + unsigned long phy_reg_base = usb_get_device_mode_phy_base(); + + if (phy_reg_base == 0) + return; + usb2_phy_tuning(phy_reg_base, 1); + return; +} + +void set_usb_phy21_tuning_update_reset(void) +{ + usb_phy_tuning_reset(); +} + + +void set_usb_phy_config(int cfg) +{ + usb_device_mode_init(); +} + +//sleep sometime before and after disconnect, +// to let usb_burning_tool.exe detect both fast plug-out and plug-in +extern void dwc_otg_pullup(int is_on); +void close_usb_phy_clock(int cfg) +{ + cfg = cfg;//avoid compiler warning + + run_command("sleep 1", 0);//improve pc compatibility!! + dwc_otg_pullup(0);//disconnect + __udelay(20); + /*dwc_otg_power_off_phy();*///Don't call this as it may cause pull-down failed!!!! + run_command("sleep 1", 0); + + return; +} +
diff --git a/drivers/usb/gadget/platform.h b/drivers/usb/gadget/platform.h new file mode 100644 index 0000000..099018c --- /dev/null +++ b/drivers/usb/gadget/platform.h
@@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +#include <asm/arch/register.h> + +#define PREI_USB_PHY_A_POR (1 << 0) +#define PREI_USB_PHY_B_POR (1 << 1) +#define PREI_USB_PHY_CLK_SEL (7 << 5) +#define PREI_USB_PHY_CLK_GATE (1 << 8) +#define PREI_USB_PHY_B_AHB_RSET (1 << 11) +#define PREI_USB_PHY_B_CLK_RSET (1 << 12) +#define PREI_USB_PHY_B_PLL_RSET (1 << 13) +#define PREI_USB_PHY_A_AHB_RSET (1 << 17) +#define PREI_USB_PHY_A_CLK_RSET (1 << 18) +#define PREI_USB_PHY_A_PLL_RSET (1 << 19) +#define PREI_USB_PHY_A_DRV_VBUS (1 << 20) +#define PREI_USB_PHY_B_DRV_VBUS (1 << 21) +#define PREI_USB_PHY_B_CLK_DETECT (1 << 22) +#define PREI_USB_PHY_CLK_DIV (0x7f << 24) +#define PREI_USB_PHY_A_CLK_DETECT (1 << 31) + +#define PREI_USB_PHY_A_REG3_IDDIG_OVR (1 << 23) +#define PREI_USB_PHY_A_REG3_IDDIG_VAL (1 << 24) + +#define PREI_USB_PHY_B_REG4_IDDIG_OVR (1 << 23) +#define PREI_USB_PHY_B_REG4_IDDIG_VAL (1 << 24) + +#define IREG_TIMER_E_COUNT 0x2655 + + +#define flush_cpu_cache() + +void dwc_write_reg32(unsigned int x, unsigned int v); +unsigned int dwc_read_reg32(unsigned int x); +void dwc_modify_reg32(unsigned int x, unsigned int c, unsigned int s); + +#define get_unaligned(ptr) ( ((unsigned long)ptr & 3) ? \ + (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) : \ + (*(uint32_t*)ptr) ) +#define get_unaligned_16(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8)) +#define get_unaligned_32(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) + +#define EXT_CLOCK 0 +#define INT_CLOCK 1 + +#define USB_ROM_CONN_TIMEOUT 5*1000*1000 + + +/* Meet with spec */ +#define USB_ROM_VER_MAJOR 0 +#define USB_ROM_STAGE_MAJOR 0 +#define USB_ROM_STAGE_MINOR 16 + +#ifdef CONFIG_M6 +#define USB_ROM_VER_MINOR 8 +#else +#define USB_ROM_VER_MINOR 7 +#endif + +#define PRINTF(x...) do{}while(0) + +#define ERR(x...) printf(x) +#define DBG(x...) PRINTF(x) + +#define USB_ERR(x...) printf("USBErr:%d", __LINE__),printf(x) +#define USB_DBG(x...) PRINTF(x) + +void set_usb_phy_config(int cfg); +void set_usb_phy21_tuning_update(void); +void set_usb_phy21_tuning_update_reset(void); +void close_usb_phy_clock(int cfg); + +void usb_parameter_init(int timeout); +int chip_utimer_set(int val); +int chip_watchdog(void); +#define udelay __udelay +#define wait_ms(a) udelay(a*1000); +int update_utime(void); +int get_utime(void); + +#endif
diff --git a/drivers/usb/gadget/v2_burning/Kconfig b/drivers/usb/gadget/v2_burning/Kconfig index 8a48d66..12f793b 100644 --- a/drivers/usb/gadget/v2_burning/Kconfig +++ b/drivers/usb/gadget/v2_burning/Kconfig
@@ -15,6 +15,7 @@ Say Y here if you want to support upgrade from sdcard and usb disk config SD_BURNING_SUPPORT_UI + depends on CMD_BMP bool "AML factory sdcard and usb disk with UI progress info" ---help--- Say Y here if you want to support sdcard and usb disk with UI progress info
diff --git a/drivers/usb/gadget/v2_burning/aml_sysrecovery/aml_sysrecovery.c b/drivers/usb/gadget/v2_burning/aml_sysrecovery/aml_sysrecovery.c index 88e7adf..a81ac30 100644 --- a/drivers/usb/gadget/v2_burning/aml_sysrecovery/aml_sysrecovery.c +++ b/drivers/usb/gadget/v2_burning/aml_sysrecovery/aml_sysrecovery.c
@@ -7,7 +7,10 @@ #include "../v2_sdc_burn/optimus_sdc_burn_i.h" #include "../v2_sdc_burn/optimus_led.h" -#define CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA 1 +#ifndef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA +#define CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA "data" +#endif// #ifndef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA +extern int sdc_burn_aml_keys(HIMAGE hImg, const int keyOverWrite, int licenseKey, int imgKey); static int optimus_sysrec_check_whole_img_before_burn(const char* partName) { @@ -15,50 +18,27 @@ return 0; } -#if CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA +#ifdef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA //clear data parts then the parts will formatted when firtsboot //As fill half parttition need so much time, I just clear 2M static int optimus_sysrec_clear_usr_data_parts(void) { - const char* const _usrDataParts[] = {"data",}; + const char* const _usrDataParts[] = {CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA,}; const int dataPartsNum = sizeof(_usrDataParts)/sizeof(const char*); - const unsigned BufSz = 1U<<20;//1MB - unsigned char* clearBuf= (unsigned char*)OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR; int partIndex = 0; int ret = 0; + char cmdbuf[128]; - memset(clearBuf, 0xff, BufSz); for (partIndex = 0; partIndex < dataPartsNum; ++partIndex) { - u64 partCap = 0; - const char* thePart = _usrDataParts[partIndex]; - int rcode = 0; - u64 offset = 0; - u64 ClearSz = 2U<<20; - - DWN_MSG("To clear data part[%s]\n", thePart); - partCap = store_part_size(thePart); - if (rcode) { - DWN_ERR("Fail to get partSz for part[%s]\n", thePart); - return rcode; - } - //FIXME: If there is fschk before firstboot, the 2MB to destroy the data if not enough - /*ClearSz = partCap>>1;*/ - DWN_MSG("partCap 0x%llxMB, ClearSz=%llxMb\n", (partCap>>20), (ClearSz>>20)); - - for (; offset < ClearSz; offset += BufSz) - { - rcode = store_logic_write(thePart, offset, BufSz, clearBuf); - if (rcode) { - DWN_ERR("Failed when clear data part[%s], rcode=%d\n", thePart, rcode); - ret += rcode; - } - } + sprintf(cmdbuf, "store erase partition %s", _usrDataParts[partIndex]); + ret = run_command(cmdbuf, 0); + if (ret) { DWN_WRN("Wrn:failed in cmd:%s\n", cmdbuf); } } return ret; } -#endif//#if CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA +#endif//#ifdef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA /* *.partName: aml_sysrecovery @@ -72,8 +52,8 @@ __hdle hUiProgress = NULL; HIMAGE hImg = NULL; int ret = 0; - - ret = optimus_storage_init(0);//Init all partitions for burning + int hasBootloader = 0; + u64 datapartsSz = 0; if (verifyPackageBeforeBurn) { @@ -96,6 +76,14 @@ } show_logo_to_report_burning(); + //update dtb for keyman + ret = optimus_sdc_burn_dtb_load(hImg); + if (ITEM_NOT_EXIST != ret && ret) { + DWN_ERR("Fail in load dtb for sdc_burn\n"); + ret = __LINE__; goto _finish; + } + optimus_storage_init(0); + hUiProgress = optimus_progress_ui_request_for_sdc_burn(); if (!hUiProgress) { DWN_ERR("request progress handle failed!\n"); @@ -103,8 +91,7 @@ } optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_DISK_INIT_OK); - int hasBootloader = 0; - u64 datapartsSz = optimus_img_decoder_get_data_parts_size(hImg, &hasBootloader); + datapartsSz = optimus_img_decoder_get_data_parts_size(hImg, &hasBootloader); DWN_MSG("datapartsSz=[%8u]MB\n", (unsigned)(datapartsSz >> 20)); ret = optimus_progress_ui_set_smart_mode(hUiProgress, datapartsSz, UPGRADE_STEPS_FOR_BURN_DATA_PARTS_IN_PKG(!pSdcCfgPara->burnEx.bitsMap.mediaPath)); @@ -120,24 +107,8 @@ ret = __LINE__; goto _finish; } -#if 0 - ret = optimus_sdc_burn_dtb_load(hImg); - if (ITEM_NOT_EXIST != ret && ret) { - DWN_ERR("Fail in load dtb for sdc_burn\n"); - ret = __LINE__; goto _finish; - } - ret = optimus_save_loaded_dtb_to_flash(); - if (ret) { - DWN_ERR("FAiled in dtb wr\n"); - return __LINE__; - } -#endif - optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STPES_AFTER_BURN_DATA_PARTS_OK); -#if CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA - optimus_sysrec_clear_usr_data_parts(); -#endif// #if CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA #if 1 if (hasBootloader) {//burn bootloader @@ -153,13 +124,24 @@ } } #endif +#if CONFIG_SUPPORT_SDC_KEYBURN + ret = sdc_burn_aml_keys(hImg, 0, 0, 1); + if (ret) { + DWN_ERR("Fail in recovery keys from img\n"); + ret = __LINE__; goto _finish; + } +#endif// #if CONFIG_SUPPORT_SDC_KEYBURN +#ifdef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA + optimus_sysrec_clear_usr_data_parts(); +#endif// #ifdef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA + optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_BURN_BOOTLOADER_OK); _finish: image_close(hImg); - optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret); + if (hUiProgress) optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret); optimus_report_burn_complete_sta(ret, 1/*pSdcCfgPara->custom.rebootAfterBurn*/); - optimus_progress_ui_release(hUiProgress); + if (hUiProgress) optimus_progress_ui_release(hUiProgress); //optimus_storage_exit();//temporary not exit storage driver when failed as may continue burning after burn return ret; } @@ -183,6 +165,7 @@ optimus_led_show_in_process_of_burning(); optimus_work_mode_set(OPTIMUS_WORK_MODE_SYS_RECOVERY); + optimus_buf_manager_init(16*1024); rcode = optimus_sysrec_burn_package_from_partition(AML_SYS_RECOVERY_PART, needVerify, verifyPackageBeforeBurn); return rcode;
diff --git a/drivers/usb/gadget/v2_burning/aml_v2_burning.c b/drivers/usb/gadget/v2_burning/aml_v2_burning.c index d554de4..cd090bd 100644 --- a/drivers/usb/gadget/v2_burning/aml_v2_burning.c +++ b/drivers/usb/gadget/v2_burning/aml_v2_burning.c
@@ -5,6 +5,7 @@ #include "v2_burning_i.h" #include <mmc.h> +#include <amlogic/cpu_id.h> #ifndef BOOT_DEVICE_USB #define BOOT_DEVICE_SD 4 @@ -50,14 +51,32 @@ return 1;//is ready for sdcard producing } +#ifdef CONFIG_AML_V3_FACTORY_BURN +extern unsigned _get_romcode_boot_id(void); +#else static unsigned _get_romcode_boot_id(void) { - DWN_DBG("P_AO_SEC_GP_CFG0=0x%p\n", P_AO_SEC_GP_CFG0); - const unsigned boot_id = readl(P_AO_SEC_GP_CFG0) & 0xf; + cpu_id_t cpuid = get_cpu_id(); - DWN_DBG("boot_id()=%x\n", boot_id); - return boot_id; + unsigned boot_id = 0; +#ifdef SYSCTRL_SEC_STATUS_REG2 + if (MESON_CPU_MAJOR_ID_SC2 <= cpuid.family_id) { + boot_id = readl(SYSCTRL_SEC_STATUS_REG2); + DWN_DBG("boot_id 0x%x\n", boot_id); + boot_id = (boot_id>>4) & 0xf; + } else +#elif defined(P_AO_SEC_GP_CFG0) + { + DWN_DBG("cfg0 0x%08x\n", readl(P_AO_SEC_GP_CFG0)); + boot_id = readl(P_AO_SEC_GP_CFG0) & 0xf; + } +#else + DWN_MSG("both P_AO_SEC_GP_CFG0 and SYSCTRL_SEC_STATUS_REG2 undefined\n"); +#endif//#ifdef SYSCTRL_SEC_STATUS_REG2 + DWN_MSG("boot_id 1x%x\n", boot_id); + return boot_id; } +#endif //is the uboot loaded from usb otg int is_tpl_loaded_from_usb(void)
diff --git a/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h b/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h index d625175..a247448 100644 --- a/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h +++ b/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h
@@ -115,5 +115,13 @@ u64 optimus_img_decoder_get_data_parts_size(HIMAGE hImg, int* hasBootloader); +unsigned image_get_crc(HIMAGE hImg); + +int optimus_img_item2buf(HIMAGE hImg, const char* main, const char* sub, char* buf, int* bufsz); + +int get_subtype_nr(HIMAGE hImg, const char* main_type); + +int get_subtype_nm_by_index(HIMAGE hImg, const char* main_type, const char** sub_type, const int itemIndex); + #endif//ifndef __AMLIMAGE_IF_H__
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c index 3e698c8..2378c36 100644 --- a/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c +++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c
@@ -68,6 +68,10 @@ return OPT_DOWN_FAIL; } _bufManager.mediaAlignSz = mediaAlignSz; + *(u32*)(&_bufManager.transferUnitSz) = (OPTIMUS_WORK_MODE_USB_PRODUCE >= optimus_work_mode_get()) + ? OPTIMUS_DOWNLOAD_SLOT_SZ : OPTIMUS_LOCAL_UPGRADE_SLOT_SZ; + _bufManager.writeBackUnitSz = _bufManager.transferUnitSz; + DWN_DBG("transfer=0x%p, transferBufSz=0x%x, transferUnitSz=0x%x, writeBackUnitSz=0x%x, totalSlotNum=%d\n", _bufManager.transferBuf, _bufManager.transferBufSz, _bufManager.transferUnitSz, _bufManager.writeBackUnitSz, _bufManager.totalSlotNum); @@ -116,6 +120,7 @@ _bufManager.destMediaType = !strcmp("mem", mediaType) ? OPTIMUS_MEDIA_TYPE_MEM : OPTIMUS_MEDIA_TYPE_STORE ; if ( !cacheAll2Mem ) cacheAll2Mem = !strcmp("mem", mediaType) ; + if ( !cacheAll2Mem ) cacheAll2Mem = (pktSz4BufManager <= _bufManager.transferUnitSz); if (cacheAll2Mem) { writeBackUnitSz = pktSz4BufManager + _bufManager.transferUnitSz - 1; @@ -134,10 +139,10 @@ return OPT_DOWN_FAIL; } if (_bufManager.transferUnitSz > writeBackUnitSz) { - DWN_ERR("write back size %d < align size %d\n", writeBackUnitSz, _bufManager.mediaAlignSz); + DWN_ERR("write back size %d < align size %d\n", writeBackUnitSz, _bufManager.transferUnitSz); return OPT_DOWN_FAIL; } - DWN_DBG("writeBackUnitSz = 0x%x, pktSz4BufManager = %lld\n", writeBackUnitSz, pktSz4BufManager); + DWN_DBG("writeBackUnitSz = 0x%x, pktSz4BufManager = 0x%llx, itemSizeNotAligned 0x%x\n", writeBackUnitSz, pktSz4BufManager, itemSizeNotAligned); _bufManager.writeBackUnitSz = writeBackUnitSz; _bufManager.totalSlotNum = 0; @@ -182,7 +187,7 @@ (u8*)(u64)_bufManager.partBaseOffset ; if (wantSz < _bufManager.transferUnitSz && !isLastTransfer) { - DWN_ERR("only last transfer can less 64K, this index %d at size 0x%u illegle\n", totalSlotNum + 1, wantSz); + DWN_ERR("only last transfer can less 64K, this index %d at size 0x%x illegle\n", totalSlotNum + 1, wantSz); return OPT_DOWN_FAIL; } @@ -222,7 +227,7 @@ const u8* BufBase = (OPTIMUS_MEDIA_TYPE_MEM != _bufManager.destMediaType) ? _bufManager.transferBuf : (u8*)(u64)_bufManager.partBaseOffset ; - DWN_DBG("transferSz=0x%x\n", transferSz); + DWN_DBG("[%d]transferSz=0x%x\n", _bufManager.totalSlotNum, transferSz); //state fileds to update _bufManager.totalSlotNum += 1; if (_bufManager.totalSlotNum == _bufManager.nextWriteBackSlot) @@ -311,7 +316,7 @@ DWN_DBG("thisTransDataLen 0x%x, left 0x%x, total 0x%x\n", thisTransDataLen, (u32)leftPktSz, (u32)totalTransferSz); DWN_DBG("totalSlotNum %d, totalTransferSz 0x%x\n", totalSlotNum, (u32)totalTransferSz); - memset(cmdDataBuf, bufLen, 0); + memset(cmdDataBuf, 0, bufLen); *(unsigned*)(cmdDataBuf + 0) = 0xefe8; *(unsigned*)(cmdDataBuf + 4) = thisTransDataLen;//Fill transfer data length of this bulk transfer
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c index 64d3979..d6859e9 100644 --- a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c +++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c
@@ -245,8 +245,9 @@ int partIndex = 0; struct partitions * thePart = NULL; - if (NULL == part_table) - return 0; + if (NULL == part_table) return 0; + if (!strcmp("1", thePartName)) return 0; + for (thePart = part_table; partIndex < 36; ++thePart, ++partIndex) { if (memcmp(thePartName, thePart->name, strnlen(thePartName, MAX_PART_NAME_LEN))) continue; @@ -275,7 +276,7 @@ { int ret = 0; DWN_MSG("%s:dataSzReceived=0x%x\n", __func__, dataSzReceived); - store_erase("dtb", 0, store_rsv_size("dtb"), 0); + store_rsv_erase("dtb"); ret = store_rsv_write("dtb", dataSzReceived, (u8*)data); return ret ? 0 : dataSzReceived; @@ -304,7 +305,6 @@ { int ret = OPT_DOWN_OK; int size = dataSzReceived; - int iCopy = 0; if (dataSzReceived < pDownInfo->imgPktSz) { DWN_ERR("please write back bootloader after all data rx end.0x(%x, %x)\n", dataSzReceived, (u32)pDownInfo->imgPktSz); @@ -330,7 +330,6 @@ int ret = OPT_DOWN_OK; unsigned char* pBuf = (unsigned char*)OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR; int size = 0; - int iCopy = 0; int bootRealSz = pDownInfo->imgPktSz; size=bootRealSz;
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h index 560ca62..9929b12 100644 --- a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h +++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h
@@ -76,6 +76,7 @@ #define OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR (OPTIMUS_SPARSE_IMG_LEFT_DATA_ADDR_LOW + OPTIMUS_SPARSE_IMG_LEFT_DATA_MAX_SZ) #define OPTIMUS_DOWNLOAD_SLOT_SZ (64<<10) //64K +#define OPTIMUS_LOCAL_UPGRADE_SLOT_SZ (OPTIMUS_DOWNLOAD_SLOT_SZ * 16) //1M per time for fatload #define OPTIMUS_DOWNLOAD_SLOT_SZ_SHIFT_BITS (16) //64K #define OPTIMUS_DOWNLOAD_SLOT_NUM (OPTIMUS_DOWNLOAD_TRANSFER_BUF_TOTALSZ/OPTIMUS_DOWNLOAD_SLOT_SZ) @@ -173,6 +174,8 @@ #define OPTIMUS_WORK_MODE_SDC_UPDATE (0xefe7) #define OPTIMUS_WORK_MODE_SDC_PRODUCE (0xefe8) #define OPTIMUS_WORK_MODE_SYS_RECOVERY (0xefe9) +#define OPTIMUS_WORK_MODE_UDISK_UPDATE (0xefea) +#define OPTIMUS_WORK_MODE_UDISK_PRODUCE (0xefeb) int optimus_work_mode_get(void); int optimus_work_mode_set(int workmode); @@ -186,7 +189,9 @@ //ENV for auto jump into producing #define _ENV_TIME_OUT_TO_AUTO_BURN "identifyWaitTime" +#ifndef AML_SYS_RECOVERY_PART #define AML_SYS_RECOVERY_PART "aml_sysrecovery" +#endif// #ifndef AML_SYS_RECOVERY_PART #if defined(CONFIG_AML_MTD) && (defined(UBIFS_IMG) || defined(CONFIG_CMD_UBIFS)) #define OPTIMUS_BURN_TARGET_SUPPORT_UBIFS 1
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_download_key.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_download_key.c index 0c31e0e..c775d55 100644 --- a/drivers/usb/gadget/v2_burning/v2_common/optimus_download_key.c +++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_download_key.c
@@ -65,14 +65,40 @@ #endif//#ifndef __HDCP22_HEY_H__ #define _AML_HDCP22_RX_KEY_NAME "aml_hdcp_key2.2" -static struct { +#define _AML_HDCP22_RP_KEY_NAME "aml_hdcp_key2.2rp" +#define _AML_HDCP22_RX_TA_KEY_N "aml_hdcp_key2.2.ta" +#define _HDCP22RxTypes 3//sizeof(_hdcprx22Keys)/sizeof(_hdcprx22Keys[0]) +#define _HDCP22_MAX_KEY_NUM 4 + +static const char* _hdcprx22Keys[_HDCP22RxTypes] = { + _AML_HDCP22_RX_KEY_NAME, + _AML_HDCP22_RP_KEY_NAME, + _AML_HDCP22_RX_TA_KEY_N, +}; +static struct AmlHdcp22RxKey{ const char* keyName; + const char* itemName; int isEncrypt; } -_amlHdcp22RxKeys[] = { - [0] = {.keyName = "hdcp22_rx_private", .isEncrypt = 1}, - [1] = {.keyName = "hdcp22_rx_fw", .isEncrypt = 0}, - [2] = {.keyName = "hdcp2_rx", .isEncrypt = 0}, +_amlHdcp22RxKeys[_HDCP22RxTypes][_HDCP22_MAX_KEY_NUM] = { + {//_AML_HDCP22_RX_KEY_NAME + [0] = {.keyName = "hdcp22_rx_private", .itemName = "hdcp22_rx_private", .isEncrypt = 1}, + [1] = {.keyName = "hdcp22_rx_fw", .itemName = "extractedKey", .isEncrypt = 0}, + [2] = {.keyName = "hdcp2_rx", .itemName = "hdcp2_rx", .isEncrypt = 0}, + [3] = {.keyName = "hdcp22_rprx_fw", .itemName = "extractedKey_rxrp", .isEncrypt = 0}, + }, + {//_AML_HDCP22_RP_KEY_NAME + [0] = {.keyName = "hdcp22_rp_private", .itemName = "hdcp22_rx_private", .isEncrypt = 1}, + [1] = {.keyName = "hdcp22_rprx_fw", .itemName = "extractedKey", .isEncrypt = 0}, + [2] = {.keyName = "hdcp2_rx", .itemName = "hdcp2_rx", .isEncrypt = 0}, + [3] = {.keyName = "hdcp22_rprp_fw", .itemName = "extractedKey_rxrp", .isEncrypt = 0}, + }, + {//_AML_HDCP22_RX_TA_KEY_N + [0] = {.keyName = "KEY_PROVISION_HDCP_RX22_FW_PRIVATE", .itemName = "hdcp22_rx_private", .isEncrypt = 0}, + [1] = {.keyName = "KEY_PROVISION_HDCP_RX22_FW", .itemName = "extractedKey", .isEncrypt = 0}, + [2] = {.keyName = "KEY_PROVISION_HDCP_RX22", .itemName = "hdcp2_rx", .isEncrypt = 0}, + [3] = {.keyName = "KEY_PROVISION_HDCP_RP22_FW", .itemName = "extractedKey_rxrp", .isEncrypt = 0}, + }, }; static char generalDataChange(const char input) @@ -111,11 +137,18 @@ int ret = 0; unsigned writtenLen = 0; + int hdcprx22KeyIndex = 0; + for (; hdcprx22KeyIndex < _HDCP22RxTypes; ++hdcprx22KeyIndex) { + const char* tmpKeyN = _hdcprx22Keys[hdcprx22KeyIndex]; + if (!strcmp(keyName, tmpKeyN)) break; + } + DWN_DBG("to write key[%s] in len=%d\n", keyName, keyValLen); - if (!strcmp(keyName, _AML_HDCP22_RX_KEY_NAME)) + if (hdcprx22KeyIndex < _HDCP22RxTypes) { const AmlResImgHead_t* packedImgHead = (AmlResImgHead_t*)keyVal; const AmlResItemHead_t* packedImgItem = (AmlResItemHead_t*)(packedImgHead + 1); + const struct AmlHdcp22RxKey* _amlHdcp22RxKey = _amlHdcp22RxKeys[hdcprx22KeyIndex]; int i = 0; const unsigned gensum = add_sum(keyVal + 4, keyValLen - 4); @@ -127,18 +160,29 @@ for (i = 0; i < packedImgHead->imgItemNum; ++i) { const AmlResItemHead_t* pItem = packedImgItem + i; - const char* itemN = _amlHdcp22RxKeys[i].keyName; + const char* itemN = pItem->name; u8* itembuf = (u8*)keyVal + pItem->dataOffset; int itemSz = pItem->dataSz; + int k = 0; - if (_amlHdcp22RxKeys[i].isEncrypt) { + for (; k < _HDCP22_MAX_KEY_NUM;++k) { + ret = strcmp(_amlHdcp22RxKey[k].itemName, itemN); + if (ret) continue; + break; + } + if ( _HDCP22_MAX_KEY_NUM == k ) { + DWN_ERR("Err, cannot find keyname for item[%d] %s\n", i, itemN); + return 0; + } + if (_amlHdcp22RxKey[k].isEncrypt) { DWN_MSG("key[%s] at[%d] isEncrypted\n", itemN, i); hdcp2DataDecryption(itemSz, (char*)itembuf, (char*)itembuf); } - DWN_MSG("burnkey[%s] at sz[%d]\n", itemN, itemSz); - ret = key_manage_write(itemN, itembuf, itemSz); - if (ret) { - DWN_ERR("Fail to write key[%s] in len=%d\n", itemN, itemSz); + const char* keyN = _amlHdcp22RxKey[k].keyName; + DWN_MSG("burnkey[%s] at sz[%d]\n", keyN, itemSz); + ret = key_manage_write(keyN, itembuf, itemSz); + if (ret != 0) { + DWN_ERR("Fail to write key[[%s] in len=%d\n", keyN, itemSz); return 0; } } @@ -146,7 +190,7 @@ else { ret = key_manage_write(keyName, keyVal, keyValLen); - if (ret) { + if (ret != 0) { DWN_ERR("Fail to write key[%s] in len=%d\n", keyName, keyValLen); return 0; } @@ -223,7 +267,14 @@ const char* queryKey = subCmd_argv[1]; int keyIsBurned = 0; - if (!strcmp(_AML_HDCP22_RX_KEY_NAME, queryKey)) queryKey = _amlHdcp22RxKeys[0].keyName; + int hdcprx22KeyIndex = 0; + for (; hdcprx22KeyIndex < _HDCP22RxTypes; ++hdcprx22KeyIndex) { + const char* tmpKeyN = _hdcprx22Keys[hdcprx22KeyIndex]; + if (!strcmp(queryKey, tmpKeyN)) { + queryKey = _amlHdcp22RxKeys[hdcprx22KeyIndex][0].keyName; + break; + } + } rcode = key_manage_query_exist(queryKey, &keyIsBurned); if (rcode) { @@ -246,7 +297,14 @@ int exist = 0; int canOverWrite = 0; - if (!strcmp(_AML_HDCP22_RX_KEY_NAME, queryKey)) queryKey = _amlHdcp22RxKeys[0].keyName; + int hdcprx22KeyIndex = 0; + for (; hdcprx22KeyIndex < _HDCP22RxTypes; ++hdcprx22KeyIndex) { + const char* tmpKeyN = _hdcprx22Keys[hdcprx22KeyIndex]; + if (!strcmp(queryKey, tmpKeyN)) { + queryKey = _amlHdcp22RxKeys[hdcprx22KeyIndex][0].keyName; + break; + } + } rcode = key_manage_query_canOverWrite(queryKey, &canOverWrite); if (rcode) {
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c index ef7fd80..f630cc3 100644 --- a/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c +++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c
@@ -150,15 +150,15 @@ *s_name = DELETED_FLAG; } -static int flush_dirty_fat_buffer(fsdata *mydata); -#if !defined(CONFIG_FAT_WRITE) +//static int flush_dirty_fat_buffer(fsdata *mydata); +//#if !defined(CONFIG_FAT_WRITE) /* Stub for read only operation */ static int flush_dirty_fat_buffer(fsdata *mydata) { (void)(mydata); return 0; } -#endif +//#endif /* * Get the entry at index 'entry' in a FAT (12/16/32) table.
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c index 80fa081..200798b 100644 --- a/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c +++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c
@@ -113,6 +113,12 @@ return NULL; } +unsigned image_get_crc(HIMAGE hImg) +{ + ImgInfo_t* imgInfo = (ImgInfo_t*)hImg; + return imgInfo->imgHead.crc; +} + //close a Amlogic firmware image int image_close(HIMAGE hImg) @@ -441,6 +447,99 @@ return dataPartsSz; } +int optimus_img_item2buf(HIMAGE hImg, const char* main, const char* sub, char* buf, int* bufsz) +{ + HIMAGEITEM hImgItem = NULL; + hImgItem = image_item_open(hImg, main, sub); + + if (!hImgItem) { + DWN_WRN("Fail to open item [%s,%s]\n", main, sub); + return ITEM_NOT_EXIST; + } + + const s64 itemSz = image_item_get_size(hImgItem); + if (!itemSz) { + DWN_ERR("Item size 0\n"); + image_item_close(hImgItem); return __LINE__; + } + if (itemSz > *bufsz) { + DWN_ERR("item sz %lld > bufsz %d\n", itemSz, *bufsz); + image_item_close(hImgItem); return __LINE__; + } + + int rc = image_item_read(hImg, hImgItem, buf, (unsigned)itemSz); + if (rc) { + DWN_ERR("Fail read item data, rc %d\n", rc); + image_item_close(hImgItem); return __LINE__; + } + + image_item_close(hImgItem); + *bufsz = itemSz; + return 0; +} + +//get item num which has same main_type +int get_subtype_nr(HIMAGE hImg, const char* main_type) +{ + int i = 0; + int ret = 0; + int itemNum = 0; + const int totalItemNum = get_total_itemnr(hImg); + + for (i = 0; i < totalItemNum; i++) + { + const char* mainType = NULL; + const char* sub_type = NULL; + + ret = get_item_name(hImg, i, &mainType, &sub_type); + if (ret) { + DWN_ERR("Exception:fail to get item name!\n"); + return -__LINE__; + } + + if (strcmp(main_type, mainType)) continue; + itemNum += 1; + } + + return itemNum; +} + +int get_subtype_nm_by_index(HIMAGE hImg, const char* main_type, const char** sub_type, const int itemIndex) +{ + int i = 0; + int ret = 0; + int itemNum = 0; + const int totalItemNum = get_total_itemnr(hImg); + const int nSubType = get_subtype_nr(hImg, main_type); + + if (nSubType < 1) { + DWN_ERR("err main type[%s]\n", main_type); + return -__LINE__; + } + if (nSubType <= itemIndex) { + DWN_ERR("item index %d > max %d for main[%s]\n", itemIndex, nSubType, main_type); + return -__LINE__; + } + + for (i = 0; i < totalItemNum; i++) + { + const char* mainType = NULL; + + ret = get_item_name(hImg, i, &mainType, sub_type); + if (ret) { + DWN_ERR("Exception:fail to get item name!\n"); + return __LINE__; + } + + if (strcmp(mainType, main_type)) continue; + if (itemIndex == itemNum) return OPT_DOWN_OK; + itemNum += 1; + } + + return OPT_DOWN_FAIL; +} + + #define MYDBG 0 #if MYDBG static int test_item(HIMAGE hImg, const char* main_type, const char* sub_type, char* pBuf, const int sz)
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c index d5783bb..ab1e467 100644 --- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c +++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c
@@ -25,8 +25,8 @@ ConfigPara_t g_sdcBurnPara = { .setsBitMap.burnParts = 0, - .setsBitMap.custom = 0, - .setsBitMap.burnEx = 0, + .setsBitMap.custom = 1, + .setsBitMap.burnEx = 1, .burnParts = { .burn_num = 0, @@ -34,14 +34,14 @@ }, .custom = { - .eraseBootloader = 1,//default to erase bootloader! - .eraseFlash = 0, - .bitsMap.eraseBootloader = 0, - .bitsMap.eraseFlash = 0, + .eraseBootloader = 1,//default to erase bootloader! no effect for usb_upgrade + .eraseFlash = 1,//default erase flash for all cases + .bitsMap.eraseBootloader = 1, + .bitsMap.eraseFlash = 1, }, .burnEx = { - .bitsMap.pkgPath = 0, + .bitsMap.pkgPath = 1, .bitsMap.mediaPath = 0, }, }; @@ -84,7 +84,7 @@ return 0; } -static int print_sdc_burn_para(const ConfigPara_t* pCfgPara) +int print_sdc_burn_para(const ConfigPara_t* pCfgPara) { printf("\n=========sdc_burn_paras=====>>>\n"); @@ -130,7 +130,7 @@ return __LINE__; } - strcpy(pBurnEx->pkgPath, strVal); + strncpy(pBurnEx->pkgPath, strVal, sizeof pBurnEx->pkgPath - 1); pBurnEx->bitsMap.pkgPath = 1; return 0; @@ -144,7 +144,7 @@ } if (strVal) { - strcpy(pBurnEx->mediaPath, strVal); + strncpy(pBurnEx->mediaPath, strVal, sizeof pBurnEx->mediaPath - 1); pBurnEx->bitsMap.mediaPath = 1; } @@ -239,6 +239,19 @@ } + if (!strcmp(key, "erase_ddr_para")) + { + if (pCustome->bitsMap.eraseDdrPara) { + goto _key_dup; + } + + if (strVal) + { + pCustome->eraseDdrPara = cfgVal; + pCustome->bitsMap.eraseDdrPara = 1; + } + } + return 0; _key_dup: @@ -317,7 +330,7 @@ return __LINE__; } - strcpy(partName, strVal); + strncpy(partName, strVal, PART_NAME_LEN_MAX - 1); } return 0; @@ -393,7 +406,7 @@ return ret; } -int parse_ini_cfg_file(const char* filePath) +static int _parse_ini_cfg_file(const char* filePath, HIMAGE hImg) { const int MaxFileSz = OPTIMUS_DOWNLOAD_SLOT_SZ; char* CfgFileLoadAddr = (char*)OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR; @@ -404,7 +417,20 @@ init_config_para(&g_sdcBurnPara); - validLineNum = parse_ini_file_2_valid_lines(filePath, CfgFileLoadAddr, MaxFileSz, lines); + if (hImg) { + DWN_MSG("try to fetch para from item aml_sdc_burn.ini\n"); + int itemSz = MaxFileSz; + rcode = optimus_img_item2buf(hImg, "ini", "aml_sdc_burn", CfgFileLoadAddr, &itemSz); + if (ITEM_NOT_EXIST == rcode) { + DWN_MSG("Item ini not existed, so use hard-coded para\n"); + return ITEM_NOT_EXIST; + } else if(rcode) { + DWN_ERR("Err when get item ini, rcode %d\n", rcode); + return __LINE__; + } else + validLineNum = parse_ini_buf_2_valid_lines(CfgFileLoadAddr, itemSz, lines); + } else + validLineNum = parse_ini_file_2_valid_lines(filePath, CfgFileLoadAddr, MaxFileSz, lines); if (!validLineNum) { err("error in parse ini file\n"); return __LINE__; @@ -429,6 +455,16 @@ return 0; } +int parse_ini_cfg_file(const char* filePath) +{ + return _parse_ini_cfg_file(filePath, NULL); +} + +int parse_ini_cfg_from_item(HIMAGE hImg) +{ + return _parse_ini_cfg_file(NULL, hImg); +} + #define MYDBG 0 #if MYDBG int do_ini_parser(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini_parser.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini_parser.c index 89948e8..a201349 100644 --- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini_parser.c +++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini_parser.c
@@ -224,6 +224,28 @@ return lineNum; } +int parse_ini_buf_2_valid_lines(char* iniBuf, const unsigned bufSz, char* lines[]) +{ + const int MaxLines = 1024;// + int ret = 0; + unsigned lineNum = 0; + + iniBuf[bufSz] = 0; + + //step1:first loop to seprate buffer to lines + ret = _optimus_parse_buf_2_lines(iniBuf, bufSz, (const char**)lines, &lineNum, MaxLines); + if (ret) { + err("Fail to parse buf to lines.ret=%d\n", ret); + return 0; + } + + //step 2: abandon comment or space lines + ret = _optimus_abandon_ini_comment_lines(lines, lineNum); + + return lineNum; +} + + int optimus_ini_trans_lines_2_usr_params(const char* const lines[], const unsigned lineNum, int (*pCheckSetUseFul)(const char* setName), int (*pParseCfgVal)(const char* setName, const char* keyName, const char* keyVal))
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c index 1f2c955..63e87d6 100644 --- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c +++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c
@@ -12,9 +12,14 @@ static int is_bootloader_old(void) { - int sdc_boot = is_tpl_loaded_from_ext_sdmmc(); + const int sdc_boot = is_tpl_loaded_from_ext_sdmmc(); + const int usbDiskNewBoot = env_get_hex("usbDiskNewBoot", 0);//default old - return !sdc_boot; + switch (optimus_work_mode_get()) { + case OPTIMUS_WORK_MODE_SDC_PRODUCE: return !sdc_boot; + case OPTIMUS_WORK_MODE_UDISK_PRODUCE: return !usbDiskNewBoot; + default: return 1;//default old + } } int get_burn_parts_from_img(HIMAGE hImg, ConfigPara_t* pcfgPara) @@ -46,7 +51,7 @@ if (OPTIMUS_WORK_MODE_SYS_RECOVERY == optimus_work_mode_get()) continue; } - strcpy(partName, sub_type); + strncpy(partName, sub_type, PART_NAME_LEN_MAX - 1); pburnPartsCfg->bitsMap4BurnParts |= 1U<<burnNum; burnNum += 1; } @@ -125,7 +130,7 @@ u32 thisReadLen = 0; __hdle hImgItem = NULL; char* downTransBuf = NULL;//get buffer from optimus_buffer_manager - const unsigned ItemReadBufSz = OPTIMUS_DOWNLOAD_SLOT_SZ;//read this size from image item each time + const unsigned ItemReadBufSz = OPTIMUS_LOCAL_UPGRADE_SLOT_SZ;//read this size from image item each time unsigned sequenceNo = 0; const char* fileFmt = NULL; /*static */char _errInfo[512]; @@ -174,7 +179,7 @@ goto _finish; } - //If the item head is not alinged to FAT cluster, Read it firstly to speed up mmc read + //If the item head is not alinged to FAT cluster, Read it firstly to speed up mmc read if (itemSizeNotAligned && !sequenceNo) { if ( itemSizeNotAligned >= imgItemSz ) { @@ -185,7 +190,7 @@ rcode = __LINE__; goto _finish; } } - DWN_DBG("itemSizeNotAligned 0x%x, itemSizePreload 0x%x\n", itemSizeNotAligned, itemSizePreload); + DWN_MSG("itemSizeNotAligned 0x%x, itemSizePreload 0x%x\n", itemSizeNotAligned, itemSizePreload); rcode = image_item_read(hImg, hImgItem, downTransBuf - itemSizePreload, itemSizePreload); if (rcode) { DWN_ERR("fail in read data from item,rcode %d, len 0x%x, sequenceNo %d\n", rcode, itemSizePreload, sequenceNo); @@ -229,11 +234,11 @@ rcode = optimus_verify_partition(partName, hImg, _errInfo); if (ITEM_NOT_EXIST == rcode) { - printf("WRN:part(%s) NOT verified\n", partName); + DWN_WRN("WRN:part(%s) NOT verified\n", partName); return 0; } if (rcode) { - printf("Fail in verify part(%s)\n", partName); + DWN_ERR("Fail in verify part(%s)\n", partName); optimus_progress_ui_printf("Failed at VERIFY part[%s]\n", partName); return __LINE__; } @@ -261,8 +266,8 @@ DWN_DBG("Data part num %d\n", burnNum); } if (!burnNum) { - DWN_ERR("Data part num is 0!!\n"); - return __LINE__; + DWN_WRN("Data part num is 0!!\n"); + /*return __LINE__;*/ } for (i = 0; i < burnNum; i++) @@ -331,11 +336,14 @@ unsigned char* dtbTransferBuf = (unsigned char*)partBaseOffset; //meson1.dtb but not meson.dtb for m8 compatible +#ifdef CONFIG_CMD_EFUSE if (IS_FEAT_BOOT_VERIFY()) { DWN_MSG("SecureEnabled, use meson1_ENC\n"); hImgItem = image_item_open(hImg, partName, "meson1_ENC"); } - else { +#endif//#ifdef CONFIG_CMD_EFUSE + if (!hImgItem) + { hImgItem = image_item_open(hImg, partName, "meson1"); } if (!hImgItem) { @@ -466,7 +474,7 @@ } //burn the amlogic keys like USB_Burning_Tool -static int sdc_burn_aml_keys(HIMAGE hImg, const int keyOverWrite) +int sdc_burn_aml_keys(HIMAGE hImg, const int keyOverWrite, int licenseKey, int imgKey) { int rc = 0; const char* *keysName = NULL; @@ -474,12 +482,6 @@ const char** pCurKeysName = NULL; unsigned index = 0; - rc = run_command("aml_key_burn probe vfat sdc", 0); - if (rc) { - DWN_ERR("Fail in probe for aml_key_burn\n"); - return __LINE__; - } - { unsigned random32 = 0; unsigned seed = 0; @@ -502,7 +504,17 @@ DWN_ERR("Fail to parse keys.conf, rc =%d\n", rc); return __LINE__; } - DWN_MSG("keys.conf:\n"); + if (keysNum > 0) { + if (strcmp("1", getenv("usb_update"))) + rc = run_command("aml_key_burn probe vfat sdc", 0); + else + rc = run_command("aml_key_burn probe vfat udisk", 0); + if (rc) { + DWN_ERR("Fail in probe for aml_key_burn\n"); + return __LINE__; + } + DWN_MSG("keys.conf:\n"); + } for (index = 0; index < keysNum; ++index)printf("\tkey[%d]\t%s\n", index, keysName[index]) ; rc = optimus_sdc_keysprovider_init(); @@ -558,6 +570,40 @@ } } + const char* mainTypeKey = "AML_KEY"; + const int nrItems = get_subtype_nr(hImg, mainTypeKey); + for (index = 0; index < nrItems; ++index) + { + const char* keyName = NULL; + if (get_subtype_nm_by_index(hImg, mainTypeKey, &keyName, index)) { + DWN_ERR("fail in get key[%d] subtype\n", index); + return -__LINE__; + } + DWN_MSG("Now burn IMG key <---- [%s] ----> %d \n", keyName, index); + rc = sdc_check_key_need_to_burn(keyName, keyOverWrite); + if (rc < 0) { + DWN_ERR("Fail when when check stauts for key(%s)\n", keyName); + /*return __LINE__;*/ + } + if (!rc) continue;//not need to burn this key + + //1,using cmd_keysprovider to read a key to memory + char* keyValue = (char*)OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR; + int keySz = OPTIMUS_DOWNLOAD_SLOT_SZ;//buffer size + rc = optimus_img_item2buf(hImg, mainTypeKey, keyName, keyValue, &keySz); + if (rc) { + DWN_ERR("Fail to get value for key[%s]\n", keyName); + return __LINE__; + } + + //3, burn the key + rc = optimus_keysburn_onekey(keyName, (u8*)keyValue, keySz); + if (rc) { + DWN_ERR("Fail in burn the key[%s] at addr=%p, sz=%d\n", keyName, keyValue, keySz); + return __LINE__; + } + } + rc = optimus_sdc_keysprovider_exit(); if (rc) { DWN_ERR("Fail in optimus_sdc_keysprovider_exit\n"); @@ -585,23 +631,63 @@ ConfigPara_t* pSdcCfgPara = &g_sdcBurnPara; const char* pkgPath = pSdcCfgPara->burnEx.pkgPath; __hdle hUiProgress = NULL; + int hasBootloader = 0; + u64 datapartsSz = 0; + int eraseFlag = pSdcCfgPara->custom.eraseFlash; - ret = parse_ini_cfg_file(cfgFile); - if (ret) { - DWN_ERR("Fail to parse file %s\n", cfgFile); - ret = __LINE__; goto _finish; + optimus_buf_manager_init(16*1024); + hImg = image_open("mmc", "0", "1", cfgFile); + if (!hImg) { + DWN_MSG("cfg[%s] not valid aml pkg, parse it as ini\n", cfgFile); + ret = parse_ini_cfg_file(cfgFile); + if (ret) { + DWN_ERR("Fail to parse file %s\n", cfgFile); + ret = __LINE__; goto _finish; + } + } else {//cfg path is valid aml pkg + DWN_MSG("cfg %s is valid aml pkg\n", cfgFile); + + ret = parse_ini_cfg_from_item(hImg); + if (ITEM_NOT_EXIST == ret) { + ret = check_cfg_burn_parts(pSdcCfgPara); + if (ret) { + DWN_ERR("Fail in check burn parts.\n"); + ret = __LINE__; goto _finish; + } + extern int print_sdc_burn_para(const ConfigPara_t* pCfgPara); + print_sdc_burn_para(pSdcCfgPara); + } + memcpy((void*)pkgPath, cfgFile, strnlen(cfgFile, 128)); } - if (pSdcCfgPara->custom.eraseBootloader && strcmp("1", getenv("usb_update"))) + hImg = hImg ? hImg : image_open("mmc", "0", "1", pkgPath); + if (!hImg) { + DWN_ERR("Fail to open image %s\n", pkgPath); + ret = __LINE__; goto _finish; + } + const int eraseBootloader = pSdcCfgPara->custom.eraseBootloader; + const int usbDiskUpgrade = (OPTIMUS_WORK_MODE_UDISK_PRODUCE == optimus_work_mode_get()); + if (eraseBootloader && is_bootloader_old()) { - if (is_bootloader_old()) - { + if (usbDiskUpgrade) {//upgrade new bootloader + if (optimus_burn_bootlader(hImg)) { + DWN_ERR("Fail in burn new bootloader from usb disk\n"); + goto _finish; + } + setenv("usbDiskNewBoot", "1"); + setenv("sdcburncfg", cfgFile); + setenv("usbDiskUpgrade", "run init_display; usb_burn $sdcburncfg"); + setenv("preboot", "printenv usbDiskUpgrade; run usbDiskUpgrade"); + run_command("saveenv", 0); + } else + {//sdc_burn DWN_MSG("To erase OLD bootloader !\n"); ret = optimus_erase_bootloader("sdc"); if (ret) { DWN_ERR("Fail to erase bootloader\n"); ret = __LINE__; goto _finish; } + } #if defined(CONFIG_VIDEO_AMLLCD) //axp to low power off LCD, no-charging @@ -616,7 +702,6 @@ DWN_MSG("Reset to load NEW uboot from ext-mmc!\n"); optimus_reset(OPTIMUS_BURN_COMPLETE__REBOOT_SDC_BURN); return __LINE__;//should never reach here!! - } } if (OPTIMUS_WORK_MODE_SDC_PRODUCE == optimus_work_mode_get()) //led not depend on image res, can init early @@ -628,12 +713,6 @@ optimus_led_show_in_process_of_burning(); } - hImg = image_open("mmc", "0", "1", pkgPath); - if (!hImg) { - DWN_ERR("Fail to open image %s\n", pkgPath); - ret = __LINE__; goto _finish; - } - //update dtb for burning drivers ret = optimus_sdc_burn_dtb_load(hImg); if (ITEM_NOT_EXIST != ret && ret) { @@ -655,19 +734,39 @@ } optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_IMAGE_OPEN_OK); - int hasBootloader = 0; - u64 datapartsSz = optimus_img_decoder_get_data_parts_size(hImg, &hasBootloader); - - int eraseFlag = pSdcCfgPara->custom.eraseFlash; + datapartsSz = optimus_img_decoder_get_data_parts_size(hImg, &hasBootloader); if (!datapartsSz) { eraseFlag = 0; DWN_MSG("Disable erase as data parts size is 0\n"); } - ret = optimus_storage_init(eraseFlag); - if (ret) { - DWN_ERR("Fail to init stoarge for sdc burn, ret %d\n", ret); - return __LINE__; goto _finish; + if (eraseFlag && !strcmp("1", getenv("usb_update"))) { + ret = optimus_storage_init(0); + if (ret) { + DWN_ERR("FAil in init flash for usb upgrade\n"); + return __LINE__; + } + + DWN_MSG("store_get_type %d\n", store_get_type()); + //erase after bootloader for usb disk + if (BOOT_EMMC == store_get_type()) ret = run_command("echo amlmmc erase non_loader;amlmmc erase non_loader", 0); + else ret = run_command("echo store erase.chip; store erase.chip", 0); } + else + ret = optimus_storage_init(eraseFlag); + if (ret) { + DWN_ERR("Fail to init stoarge for sdc burn\n"); + ret = __LINE__; goto _finish; + } +#if 0 + if (pSdcCfgPara->custom.eraseDdrPara) { + extern int store_ddr_parameter_erase(void); + DWN_MSG("to erase ddr parameters\n"); + if (store_ddr_parameter_erase()) { + DWN_ERR("Fail in erase ddr parameters\n"); + return -__LINE__; + } + } +#endif optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_DISK_INIT_OK); @@ -701,37 +800,37 @@ optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STPES_AFTER_BURN_DATA_PARTS_OK); //TO burn nandkey/securekey/efusekey - ret = sdc_burn_aml_keys(hImg, pSdcCfgPara->custom.keyOverwrite); + ret = sdc_burn_aml_keys(hImg, pSdcCfgPara->custom.keyOverwrite, 1, 1); if (ret) { DWN_ERR("Fail in sdc_burn_aml_keys\n"); ret = __LINE__;goto _finish; } -#if 1 if (hasBootloader) {//burn bootloader + if (usbDiskUpgrade && env_get_hex("usbDiskNewBoot", 0)) {//already upgrade bootloader from pkg + ; + } else { ret = optimus_burn_bootlader(hImg); if (ret) { - DWN_ERR("Fail in burn bootloader\n"); - goto _finish; + DWN_ERR("Fail in burn bootloader\n"); + goto _finish; } - else - {//update bootloader ENV only when bootloader image is burned - ret = optimus_set_burn_complete_flag(); - if (ret) { - DWN_ERR("Fail in set_burn_complete_flag\n"); - ret = __LINE__; goto _finish; - } - } + } + //update bootloader ENV only when bootloader image is burned + ret = optimus_set_burn_complete_flag(); + if (ret) { + DWN_ERR("Fail in set_burn_complete_flag\n"); + ret = __LINE__; goto _finish; + } } -#endif optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_BURN_BOOTLOADER_OK); _finish: image_close(hImg); - optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret); + if (hUiProgress) optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret); optimus_report_burn_complete_sta(ret, pSdcCfgPara->custom.rebootAfterBurn); - optimus_progress_ui_release(hUiProgress); + if (hUiProgress) optimus_progress_ui_release(hUiProgress); //optimus_storage_exit();//temporary not exit storage driver when failed as may continue burning after burn return ret; } @@ -770,7 +869,7 @@ } if ( !aml_check_is_ready_for_sdc_produce() ) { - DWN_MSG("sdcard Not ready for sdc_burn\n"); + DWN_DBG("sdcard Not ready for sdc_burn\n"); return __LINE__; } @@ -790,7 +889,7 @@ U_BOOT_CMD( sdc_burn, //command name - 2, //maxargs + 5, //maxargs 0, //repeatable do_sdc_burn, //command function "Burning with amlogic format package in sdmmc ", //description
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn_i.h b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn_i.h index e8c4b6c..e5f896d 100644 --- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn_i.h +++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn_i.h
@@ -28,12 +28,14 @@ int eraseFlash; int rebootAfterBurn; int keyOverwrite; + int eraseDdrPara; struct{ unsigned eraseBootloader : 1; unsigned eraseFlash : 1; unsigned rebootAfterBurn : 1; unsigned keyOverwrite : 1; - unsigned resev : 32 - 4; + unsigned eraseDdrPara : 1; + unsigned resev : 32 - 5; }bitsMap; }CustomPara_t; @@ -68,13 +70,17 @@ //ini parser int _optimus_parse_buf_2_lines(char* pTextBuf, const unsigned textSz, const char* lines[], unsigned* totalLineNum, const unsigned MaxLines);//parse text context to linces delimitted by (\r)\n + int parse_ini_file_2_valid_lines(const char* filePath, char* iniBuf, const unsigned bufSz, char* lines[]); +int parse_ini_buf_2_valid_lines(char* iniBuf, const unsigned bufSz, char* lines[]); + int _optimus_abandon_ini_comment_lines(char* lines[], const unsigned lineNum); int optimus_ini_trans_lines_2_usr_params(const char* const lines[], const unsigned lineNum, int (*pCheckSetUseFul)(const char* setName), int (*pParseCfgVal)(const char* setName, const char* keyName, const char* keyVal)); int parse_ini_cfg_file(const char* filePath); +int parse_ini_cfg_from_item(HIMAGE hImg); int check_cfg_burn_parts(const ConfigPara_t* burnPara); int print_burn_parts_para(const BurnParts_t* pBurnParts);
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c index 4fa5d3d..4f1f91a 100644 --- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c +++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c
@@ -85,11 +85,13 @@ if (!_udiskProbe) { +#if 0 rc = run_command("usb start 0", 0); if (rc) { _AML_KEY_ERR("Fail in mmcinfo\n"); return __LINE__; } +#endif rc = optimus_device_probe("usb", "0"); if (rc) { _AML_KEY_ERR("Fail to detect device mmc 0\n"); @@ -154,39 +156,18 @@ { int rc = 0; unsigned keySz = 0; + char cmd[128]; if (DEV_FILE_FMT_VFAT == _optKeyInfo.fileFmt) { - long hFile = -1; - unsigned readSz = 0; - -#if 1//FIXME: remove this mmcinfo - /*rc = run_command("mmcinfo 0", 0);*/ - rc = optimus_sdc_burn_switch_to_extmmc(); - if (rc) { - DWN_ERR("Fail in mmcinfo\n"); - return __LINE__; - } -#endif// - keySz = (unsigned)do_fat_get_fileSz(filePath);//can support both sdc and udisk - if (!keySz) { - DWN_ERR("size is 0 of file [%s]\n", filePath); - return __LINE__; - } - - hFile = do_fat_fopen(filePath); - if (hFile < 0) { - DWN_ERR("Fail to open file[%s]\n", filePath); - return __LINE__; - } - - readSz = do_fat_fread(hFile, buf, keySz); - if (readSz != keySz) { - DWN_ERR("Want read %d bytes, but %d\n", keySz, readSz); - return __LINE__; - } - - do_fat_fclose(hFile); + if (strcmp("1", getenv("usb_update"))) + sprintf(cmd, "fatload mmc 0 %p %s", buf, filePath); + else + sprintf(cmd, "fatload usb 0 %p %s", buf, filePath); + rc = run_command(cmd, 0); + if (rc) { + DWN_ERR("Fail in load key cmd[%s]\n", cmd); + } } *keyValLen = keySz;
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c index 77d5d8c..53784f5 100644 --- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c +++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c
@@ -394,7 +394,10 @@ optimus_sdc_burn_switch_to_extmmc(); - sprintf(_cmd, "fatload mmc 0:1 0x%p %s", keyVal, licenseName); + if (strcmp("1", getenv("usb_update"))) + sprintf(_cmd, "fatload mmc 0:1 0x%p %s", keyVal, licenseName); + else + sprintf(_cmd, "fatload usb 0:1 0x%p %s", keyVal, licenseName); rc = run_command(_cmd, 0); if (rc) { errorP("failed in cmd[%s]\n", _cmd);
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_burn.c b/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_burn.c index 1378b5e..41391ed 100644 --- a/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_burn.c +++ b/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_burn.c
@@ -54,7 +54,7 @@ return __LINE__; } - optimus_work_mode_set(OPTIMUS_WORK_MODE_SDC_UPDATE); + optimus_work_mode_set(OPTIMUS_WORK_MODE_UDISK_PRODUCE); show_logo_to_report_burning();//indicate enter flow of burning! when 'run update' if (optimus_led_open(LED_TYPE_PWM)) { DWN_ERR("Fail to open led for burn\n"); @@ -70,7 +70,7 @@ // added by scy U_BOOT_CMD( usb_burn, //command name - 2, //maxargs + 5, //maxargs 0, //repeatable do_usb_burn, //command function "Burning with amlogic format package in usb ", //description
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.c index 7e542b9..29db78f 100644 --- a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.c +++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.c
@@ -4,7 +4,7 @@ */ #include "../v2_burning_i.h" -#include "platform.h" +#include "../../platform.h" #include "usb_ch9.h" #include "dwc_pcd.h" #include "dwc_pcd_irq.h"
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_core.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_core.c index 90f1385..464162a 100644 --- a/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_core.c +++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_core.c
@@ -6,11 +6,12 @@ #include <common.h> #include <command.h> -#include "platform.h" +#include "../../platform.h" #include "usb_pcd.h" #include "usb_pcd.c" -#include "platform.c" +//#include "../../platform.c" + #include "dwc_pcd.c" #include "dwc_pcd_irq.c"
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_transform.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_transform.c index ec20bdb..ab8d974 100644 --- a/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_transform.c +++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_transform.c
@@ -5,7 +5,7 @@ #include "../v2_burning_i.h" #include "usb_pcd.h" -#include "platform.h" +#include "../../platform.h" //#include <partition_table.h> #include <amlogic/cpu_id.h>
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c deleted file mode 100644 index ae81604..0000000 --- a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c +++ /dev/null
@@ -1,617 +0,0 @@ -/* platform dirver header */ -/* - * (C) Copyright 2010 Amlogic, Inc - * - * Victor Wan, victor.wan@amlogic.com, - * 2010-03-24 @ Shanghai - * - */ -#include "platform.h" -#include <asm/arch/secure_apb.h> -#include <amlogic/cpu_id.h> - -/*CONFIG_AML_MESON_8 include m8, m8baby, m8m2, etc... defined in cpu.h*/ -#if !(defined(CONFIG_USB_XHCI_HCD) || defined(CONFIG_USB_DWC_OTG_294)) -#error "platform is not GX !!" -#endif//#if - - -#if (defined CONFIG_USB_XHCI_HCD) -#if (defined AML_TXLX_USB) -#define PREI_USB_PHY_2_REG_BASE 0xffe09020 -#define PREI_USB_PHY_3_REG_BASE 0xffe09080 -#else -#define PREI_USB_PHY_2_REG_BASE 0xd0078020 -#define PREI_USB_PHY_3_REG_BASE 0xd0078080 -#endif - -#if (defined CONFIG_USB_DEVICE_V2) -typedef struct u2p_aml_regs { - volatile uint32_t u2p_r0; - volatile uint32_t u2p_r1; -} u2p_aml_regs_t; - -typedef union u2p_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned host_device:1; - unsigned power_ok:1; - unsigned hast_mode:1; - unsigned POR:1; - unsigned IDPULLUP0:1; - unsigned DRVVBUS0:1; - unsigned reserved:26; - } b; -} u2p_r0_t; - -typedef union u2p_r1 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned phy_rdy:1; - unsigned IDDIG0:1; - unsigned OTGSESSVLD0:1; - unsigned VBUSVALID0:1; - unsigned reserved:28; - } b; -} u2p_r1_t; - -typedef struct usb_aml_regs { - volatile uint32_t usb_r0; - volatile uint32_t usb_r1; - volatile uint32_t usb_r2; - volatile uint32_t usb_r3; - volatile uint32_t usb_r4; - volatile uint32_t usb_r5; -} usb_aml_regs_t; - -typedef union usb_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned reserved:17; - unsigned p30_lane0_tx2rx_loopback:1; - unsigned p30_lane0_ext_pclk_reg:1; - unsigned p30_pcs_rx_los_mask_val:10; - unsigned u2d_ss_scaledown_mode:2; - unsigned u2d_act:1; - } b; -} usb_r0_t; - -typedef union usb_r1 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned u3h_bigendian_gs:1; - unsigned u3h_pme_en:1; - unsigned u3h_hub_port_overcurrent:3; - unsigned reserved_1:2; - unsigned u3h_hub_port_perm_attach:3; - unsigned reserved_2:2; - unsigned u3h_host_u2_port_disable:2; - unsigned reserved_3:2; - unsigned u3h_host_u3_port_disable:1; - unsigned u3h_host_port_power_control_present:1; - unsigned u3h_host_msi_enable:1; - unsigned u3h_fladj_30mhz_reg:6; - unsigned p30_pcs_tx_swing_full:7; - } b; -} usb_r1_t; - -typedef union usb_r2 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned reserved:20; - unsigned p30_pcs_tx_deemph_3p5db:6; - unsigned p30_pcs_tx_deemph_6db:6; - } b; -} usb_r2_t; - -typedef union usb_r3 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p30_ssc_en:1; - unsigned p30_ssc_range:3; - unsigned p30_ssc_ref_clk_sel:9; - unsigned p30_ref_ssp_en:1; - unsigned reserved:18; - } b; -} usb_r3_t; - -typedef union usb_r4 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p21_PORTRESET0:1; - unsigned p21_SLEEPM0:1; - unsigned mem_pd:2; - unsigned p21_only:1; - unsigned reserved:27; - } b; -} usb_r4_t; - -typedef union usb_r5 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned iddig_sync:1; - unsigned iddig_reg:1; - unsigned iddig_cfg:2; - unsigned iddig_en0:1; - unsigned iddig_en1:1; - unsigned iddig_curr:1; - unsigned usb_iddig_irq:1; - unsigned iddig_th:8; - unsigned iddig_cnt:8; - unsigned reserved:8; - } b; -} usb_r5_t; - -#define PLL_REG32_16 (0xFF63A000 + 0x40) -#define PLL_REG32_17 (0xFF63A000 + 0x44) -#define PLL_REG32_18 (0xFF63A000 + 0x48) -#define USB_PHY2_ENABLE 0x10000000 -#define USB_PHY2_RESET 0x20000000 - -static void set_usb_phy21_pll(void) -{ - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16)) - = (USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET | USB_PHY2_ENABLE); - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) = - USB_PHY2_PLL_PARAMETER_2; - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) = - USB_PHY2_PLL_PARAMETER_3; - udelay(100); - (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16)) - = (((USB_PHY2_PLL_PARAMETER_1) | (USB_PHY2_ENABLE)) - & (~(USB_PHY2_RESET))); -} -#if !defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED) -static int b_platform_usb_check_g12b_revb (void) -{ - int rev_flag = 0; - - cpu_id_t cpu_id = get_cpu_id(); - - if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) { - if (cpu_id.chip_rev == 0xb) - rev_flag = 1; - else - rev_flag = 0; - } else { - rev_flag = 0; - } - - return rev_flag; -} -#endif - -#ifdef CONFIG_USB_DEVICE_V2 -#define USB_REG_B 0xFF63A000 - -void set_usb_phy21_tuning_update(void) -{ -#if !defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED) - unsigned long phy_reg_base = USB_REG_B; - - if (b_platform_usb_check_g12b_revb()) { - (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1; - (*(volatile uint32_t *)(phy_reg_base + 0x54)) = 0x2a; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3 & (0x1f << 16); - return; - } - - (*(volatile uint32_t *)(phy_reg_base + 0x10)) = USB_G12x_PHY_PLL_SETTING_2; - (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1; - (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB_G12x_PHY_PLL_SETTING_5; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3; -#endif -} - -void set_usb_phy21_tuning_update_reset(void) -{ -#if !defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED) - unsigned long phy_reg_base = USB_REG_B; - - if (b_platform_usb_check_g12b_revb()) - return; - (*(volatile uint32_t *)(phy_reg_base + 0x38)) = 0x0; - (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3; -#endif -} - -#endif - -#if 0 -void usb_phy21_pll_disable(void) -{ - (*(volatile uint32_t *)(unsigned long)PLL_REG32_16) - = ((USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET) - & (~(USB_PHY2_ENABLE))); -} -#endif - -#if (defined AML_TXLX_USB) -#define USB_RESET1 (volatile unsigned long *)0xffd01008 -#else -#define USB_RESET1 (volatile unsigned long *)0xc1104408 -#endif - -void set_usb_phy_config(int cfg) -{ - u2p_r0_t dev_u2p_r0; - u2p_r1_t dev_u2p_r1; - - usb_r0_t dev_usb_r0; - usb_r4_t dev_usb_r4; - - u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE; - usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE; - int cnt; -#ifdef CONFIG_USB_DEVICE_V2 - if ((*(volatile uint32_t *)(USB_REG_B + 0x38)) != 0) { - set_usb_phy21_tuning_update_reset(); - mdelay(150); - } -#endif - //step 1: usb controller reset - *USB_RESET1 |= (1<<2); - - // step 3: enable usb INT internal USB - dev_usb_r0.d32 = usb_aml_regs->usb_r0; - dev_usb_r0.b.u2d_ss_scaledown_mode = 0; - dev_usb_r0.b.u2d_act = 1; - usb_aml_regs->usb_r0 = dev_usb_r0.d32; - - // step 4: disable usb phy sleep - dev_usb_r4.d32 = usb_aml_regs->usb_r4; - dev_usb_r4.b.p21_SLEEPM0 = 1; - usb_aml_regs->usb_r4 = dev_usb_r4.d32; - - // step 5: config phy21 device mode - dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0; - dev_u2p_r0.b.host_device= 0; - dev_u2p_r0.b.POR= 0; - u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32; - - udelay(10); - //step 6: phy21 reset - *USB_RESET1 |= (1<<17); - - udelay(50); - // step 6: wait for phy ready - dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; - cnt = 0; - while ((dev_u2p_r1.d32 & 0x00000001) != 1) { - dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1; - if (cnt > 200) - break; - else { - cnt++; - udelay(5); - } - } - - set_usb_phy21_pll(); - //-------------------------------------------------- - - // ------------- usb phy21 initinal end ---------- - - //-------------------------------------------------- - -} - -#else -typedef struct u2p_aml_regs { - volatile uint32_t u2p_r0; - volatile uint32_t u2p_r1; - volatile uint32_t u2p_r2; -} u2p_aml_regs_t; - -typedef union u2p_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned bypass_sel:1; // 0 - unsigned bypass_dm_en:1; // 1 - unsigned bypass_dp_en:1; // 2 - unsigned txbitstuffenh:1;// 3 - unsigned txbitstuffen:1; // 4 - unsigned dmpulldown:1; // 5 - unsigned dppulldown:1; // 6 - unsigned vbusvldextsel:1;// 7 - unsigned vbusvldext:1; // 8 - unsigned adp_prb_en:1; // 9 - unsigned adp_dischrg:1; // 10 - unsigned adp_chrg:1; // 11 - unsigned drvvbus:1; // 12 - unsigned idpullup:1; // 13 - unsigned loopbackenb:1; // 14 - unsigned otgdisable:1; // 15 - unsigned commononn:1; // 16 - unsigned fsel:3; // 17 - unsigned refclksel:2; // 20 - unsigned por:1; // 22 - unsigned vatestenb:2; // 23 - unsigned set_iddq:1; // 25 - unsigned ate_reset:1; // 26 - unsigned fsv_minus:1; // 27 - unsigned fsv_plus:1; // 28 - unsigned bypass_dm_data:1; // 29 - unsigned bypass_dp_data:1; // 30 - unsigned not_used:1; - } b; -} u2p_r0_t; - -typedef struct usb_aml_regs { - volatile uint32_t usb_r0; - volatile uint32_t usb_r1; - volatile uint32_t usb_r2; - volatile uint32_t usb_r3; - volatile uint32_t usb_r4; - volatile uint32_t usb_r5; - volatile uint32_t usb_r6; -} usb_aml_regs_t; - -typedef union usb_r0 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p30_fsel:6; // 0 - unsigned p30_phy_reset:1; // 6 - unsigned p30_test_powerdown_hsp:1; // 7 - unsigned p30_test_powerdown_ssp:1; // 8 - unsigned p30_acjt_level:5; // 9 - unsigned p30_tx_vboost_lvl:3; // 14 - unsigned p30_lane0_tx2rx_loopbk:1; // 17 - unsigned p30_lane0_ext_pclk_req:1; // 18 - unsigned p30_pcs_rx_los_mask_val:10; // 19 - unsigned u2d_ss_scaledown_mode:2; // 29 - unsigned u2d_act:1; // 31 - } b; -} usb_r0_t; - -typedef union usb_r4 { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned p21_PORTRESET0:1; // 0 - unsigned p21_SLEEPM0:1; // 1 - unsigned mem_pd:2; - unsigned reserved4:28; // 31 - } b; -} usb_r4_t; -//#define P_AO_RTC_ALT_CLK_CNTL0 (volatile uint32_t *)(0xc8100000 + (0x25 << 2)) -//#define P_AO_RTI_PWR_CNTL_REG0 (volatile uint32_t *)(0xc8100000 + (0x04 << 2)) - -void set_usb_phy_config(int cfg) -{ - const int time_dly = 500; - u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE; - usb_aml_regs_t * usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE; - - u2p_r0_t u2p_r0; - usb_r0_t usb_r0; - usb_r4_t usb_r4; - //if (!IS_CLK_GATE_ON(USB0)) { - // SET_CBUS_REG_MASK(GCLK_REG_USB0, GCLK_MASK_USB0); - //} - /*printf("%s %d\n", __func__, __LINE__);*/ - cfg = cfg;//avoid compiler warning - *P_RESET1_REGISTER = (1<<2);//usb reset - //writel((1 << 2),P_RESET1_REGISTER); //usb reset - //udelay(time_dly);//by Sam: delay after reset - - *P_AO_RTC_ALT_CLK_CNTL0 |= (1<<31)|(1<<30); - *P_AO_RTI_PWR_CNTL_REG0 |= (4<<10); - - u2p_r0.d32 = u2p_aml_regs->u2p_r0; -#if (defined CONFIG_AML_MESON_GXTVBB) - u2p_r0.b.fsel = 5; - -#elif (defined CONFIG_AML_MESON_GXL) - u2p_r0.b.fsel = 2; -#endif - u2p_r0.b.por = 1; - u2p_r0.b.dppulldown = 0; - u2p_r0.b.dmpulldown = 0; - u2p_aml_regs->u2p_r0 = u2p_r0.d32; - - u2p_r0.d32 = u2p_aml_regs->u2p_r0; - u2p_r0.b.por = 0; - u2p_aml_regs->u2p_r0 = u2p_r0.d32; - - usb_r0.d32 = usb_aml_regs->usb_r0; - usb_r0.b.u2d_act = 1; - usb_aml_regs->usb_r0 = usb_r0.d32; - - usb_r4.d32 = usb_aml_regs->usb_r4; - usb_r4.b.p21_SLEEPM0 = 1; - usb_aml_regs->usb_r4 = usb_r4.d32; - - udelay(time_dly); - return; -} -#endif - -//sleep sometime before and after disconnect, -// to let usb_burning_tool.exe detect both fast plug-out and plug-in -void close_usb_phy_clock(int cfg) -{ - cfg = cfg;//avoid compiler warning - - run_command("sleep 1", 0);//improve pc compatibility!! - dwc_otg_pullup(0);//disconnect - __udelay(20); - /*dwc_otg_power_off_phy();*///Don't call this as it may cause pull-down failed!!!! - run_command("sleep 1", 0); - - return; -} -#endif - -#if (defined CONFIG_USB_DWC_OTG_294) - -/* - cfg = 0 : EXT clock - cfg = 1 : INT clock - */ - -#if 1 -#define PREI_USB_PHY_A_REG_BASE 0xC0000000 //0x2100 -#define PREI_USB_PHY_B_REG_BASE 0xC1108420 //0X2108 -#else -#define PREI_USB_PHY_A_REG_BASE P_USB_ADDR0 -#define PREI_USB_PHY_B_REG_BASE P_USB_ADDR1 -#endif//#if 0 - -#ifdef __USE_PORT_B -#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_B_REG_BASE -#else -#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_A_REG_BASE -#endif -//#define P_RESET1_REGISTER (volatile unsigned long *)0xc1104408 -#define P_RESET1_REGISTER_USB (volatile unsigned long *)0xc1104408 - -#define USB_CLK_SEL_XTAL 0 -#define USB_CLK_SEL_XTAL_DIV_2 1 -#define USB_CLK_SEL_DDR_PLL 2 -#define USB_CLK_SEL_MPLL_OUT0 3 -#define USB_CLK_SEL_MPLL_OUT1 4 -#define USB_CLK_SEL_MPLL_OUT2 5 -#define USB_CLK_SEL_FCLK_DIV2 6 -#define USB_CLK_SEL_FCLK_DIV3 7 - -typedef struct usb_aml_regs { - volatile uint32_t config; - volatile uint32_t ctrl; - volatile uint32_t endp_intr; - volatile uint32_t adp_bc; - volatile uint32_t dbg_uart; - volatile uint32_t test; - volatile uint32_t tune; -} usb_aml_regs_t; - -typedef union usb_config_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned clk_en :1; - unsigned clk_sel :3; - unsigned clk_div :7; - unsigned reserved0 :1; - unsigned clk_32k_alt_sel:1; - unsigned reserved1 :15; - unsigned test_trig :1; - } b; -} usb_config_data_t; - -typedef union usb_ctrl_data { - /** raw register data */ - uint32_t d32; - /** register bits */ - struct { - unsigned soft_prst:1; - unsigned soft_hreset:1; - unsigned ss_scaledown_mode:2; - unsigned clk_det_rst:1; - unsigned intr_sel:1; - unsigned reserved:2; - unsigned clk_detected:1; - unsigned sof_sent_rcvd_tgl:1; - unsigned sof_toggle_out:1; - unsigned not_used:4; - unsigned por:1; - unsigned sleepm:1; - unsigned txbitstuffennh:1; - unsigned txbitstuffenn:1; - unsigned commononn:1; - unsigned refclksel:2; - unsigned fsel:3; - unsigned portreset:1; - unsigned thread_id:6; - } b; -} usb_ctrl_data_t; - -void set_usb_phy_config(int cfg) -{ - - const int time_dly = 5000; - usb_aml_regs_t * usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_REG_BASE; - usb_config_data_t config; - usb_ctrl_data_t control; - - /*CLK_GATE_ON(USB0);*/ - //if(!IS_CLK_GATE_ON(USB0)){ - // SET_CBUS_REG_MASK(GCLK_REG_USB0, GCLK_MASK_USB0); - //} - /*printf("%s %d\n", __func__, __LINE__);*/ - cfg = cfg;//avoid compiler warning - /**P_RESET1_REGISTER = (1<<2);//usb reset*/ - *P_RESET1_REGISTER_USB = (1<<2);//usb reset - udelay(time_dly);//by Sam: delay after reset - - config.d32 = usb_aml_regs->config; - -// config.b.clk_sel = 0; -// config.b.clk_div = 1; -// config.b.clk_32k_alt_sel = 1; - usb_aml_regs->config = config.d32; - - control.d32 = usb_aml_regs->ctrl; - control.b.fsel = 5; - control.b.por = 1; - usb_aml_regs->ctrl = control.d32; - udelay(time_dly); - - control.b.por = 0; - usb_aml_regs->ctrl = control.d32; - udelay(time_dly);//by Sam: delay 0.5s to wait usb clam down - - control.d32 = usb_aml_regs->ctrl; - if (!control.b.clk_detected) { - printf("Error, usb phy clock not detected!\n"); - } - - return; -} - -#if 0 -int chip_watchdog(void) -{ - watchdog_clear(); - return 0; -}; -#endif - -//sleep sometime before and after disconnect, -// to let usb_burning_tool.exe detect both fast plug-out and plug-in -void close_usb_phy_clock(int cfg) -{ - cfg = cfg;//avoid compiler warning - - run_command("sleep 1", 0);//sleep sometime to improve pc compatibility!! - dwc_otg_pullup(0);//disconnect - __udelay(20); - /*dwc_otg_power_off_phy();*///Don't call this as it may cause pull-down failed!!!! - run_command("sleep 1", 0);//sleep sometime to improve pc compatibility!! - - return; -} -#endif -
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.h b/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.h deleted file mode 100644 index 9b5b3ab..0000000 --- a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.h +++ /dev/null
@@ -1,139 +0,0 @@ -/* platform header */ -/* - * (C) Copyright 2010 Amlogic, Inc - * - * Victor Wan, victor.wan@amlogic.com, - * 2010-03-24 @ Shanghai - * - */ - -#ifndef __PLATFORM_H__ -#define __PLATFORM_H__ - -#include <asm/arch/register.h> - -/* A3,CS2,M3 chip, PORT_A is OTG, work as ROM Boot port */ -#ifdef __USE_PORT_B -#define PORT_REG_OFFSET 0x80000 -#else -#define PORT_REG_OFFSET 0 -#endif - -#if (defined AML_TXLX_USB) -#if ((defined CONFIG_USB_XHCI_HCD)) -#define DWC_REG_BASE 0xff400000 -#else -#define DWC_REG_BASE (0xff500000 + PORT_REG_OFFSET) -#endif -#else -#if ((defined CONFIG_USB_XHCI_HCD)) -#define DWC_REG_BASE 0xc9100000 -#else -#define DWC_REG_BASE (0xC9000000 + PORT_REG_OFFSET) -#endif -#endif - -#define PREI_USB_PHY_A_POR (1 << 0) -#define PREI_USB_PHY_B_POR (1 << 1) -#define PREI_USB_PHY_CLK_SEL (7 << 5) // changed from A1H -#define PREI_USB_PHY_CLK_GATE (1 << 8) -#define PREI_USB_PHY_B_AHB_RSET (1 << 11) -#define PREI_USB_PHY_B_CLK_RSET (1 << 12) -#define PREI_USB_PHY_B_PLL_RSET (1 << 13) -#define PREI_USB_PHY_A_AHB_RSET (1 << 17) -#define PREI_USB_PHY_A_CLK_RSET (1 << 18) -#define PREI_USB_PHY_A_PLL_RSET (1 << 19) -#define PREI_USB_PHY_A_DRV_VBUS (1 << 20) -#define PREI_USB_PHY_B_DRV_VBUS (1 << 21) -#define PREI_USB_PHY_B_CLK_DETECT (1 << 22) -#define PREI_USB_PHY_CLK_DIV (0x7f << 24) -#define PREI_USB_PHY_A_CLK_DETECT (1 << 31) - -#define PREI_USB_PHY_A_REG3_IDDIG_OVR (1 << 23) -#define PREI_USB_PHY_A_REG3_IDDIG_VAL (1 << 24) - -#define PREI_USB_PHY_B_REG4_IDDIG_OVR (1 << 23) -#define PREI_USB_PHY_B_REG4_IDDIG_VAL (1 << 24) - -#define IREG_TIMER_E_COUNT 0x2655 - - -#define flush_cpu_cache() - - -#define dwc_write_reg32(x, v) (*(volatile uint32_t *)(unsigned long)(x + DWC_REG_BASE))=v -#define dwc_read_reg32(x) (*(volatile uint32_t*)(unsigned long)(x + DWC_REG_BASE)) -// void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask) -#define dwc_modify_reg32(x, c, s) (*(volatile uint32_t *)(x + DWC_REG_BASE))=( ((dwc_read_reg32(x)) & (~c)) | (s)) - -#define get_unaligned(ptr) ( ((unsigned long)ptr & 3) ? \ - (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) : \ - (*(uint32_t*)ptr) ) -#define get_unaligned_16(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8)) -#define get_unaligned_32(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) - -#if 0 -#define __constant_cpu_to_le16(x) (x) -#define __constant_cpu_to_le32(x) (x) -#define cpu_to_le16(x) (x) -#define cpu_to_le32(x) (x) -#define le16_to_cpu(x) (x) -#define le32_to_cpu(x) (x) - -#ifndef max -#define max(a, b) (((a) > (b))? (a): (b)) -#endif -#ifndef min -#define min(a, b) (((a) < (b))? (a): (b)) -#endif - -#endif//#if 0 - -#define EXT_CLOCK 0 -#define INT_CLOCK 1 - - -// 32 bit TimerE, 1us -#define USB_ROM_CONN_TIMEOUT 5*1000*1000 //us (5s timeout,) - - -/* Meet with spec */ -#define USB_ROM_VER_MAJOR 0 -#define USB_ROM_STAGE_MAJOR 0 -#define USB_ROM_STAGE_MINOR 16 // IPL = 0, SPL = 8, TPL = 16 - -#ifdef CONFIG_M6 -#define USB_ROM_VER_MINOR 8 // SPEC Version -#else -#define USB_ROM_VER_MINOR 7 // SPEC Version -#endif - -#if 1 -#define PRINTF(x...) do{}while(0) -#else -#define PRINTF(x...) printf(x) -#endif - -#define ERR(x...) printf(x) -#define DBG(x...) PRINTF(x) -#define USB_ERR(x...) printf("USBErr:%d", __LINE__),printf(x) -#define USB_DBG(x...) PRINTF(x) - - -void set_usb_phy_config(int cfg); -#ifdef CONFIG_USB_DEVICE_V2 -void set_usb_phy21_tuning_update(void); -#endif -void close_usb_phy_clock(int cfg); -void usb_parameter_init(int timeout); -int chip_utimer_set(int val); -int chip_watchdog(void); -#define udelay __udelay -#define wait_ms(a) udelay(a*1000); -int update_utime(void); -int get_utime(void); -//int chip_watchdog(void); -//#define usb_memcpy(dst,src,len) rom_memcpy((unsigned)src,(unsigned)dst,(unsigned)len) -//#define usb_memcpy_32bits(dst,src,len) rom_memcpy((unsigned)src,(unsigned)dst,(unsigned)len) - -#endif
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.c index b4e6523..2b68733 100644 --- a/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.c +++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.c
@@ -4,7 +4,7 @@ */ #include "../v2_burning_i.h" -#include "platform.h" +#include "../../platform.h" #include "usb_ch9.h" #include "dwc_pcd.h" #include "dwc_pcd_irq.h"
diff --git a/drivers/usb/gadget/v3_burning/Kconfig b/drivers/usb/gadget/v3_burning/Kconfig index 73b9ea4..92f1926 100644 --- a/drivers/usb/gadget/v3_burning/Kconfig +++ b/drivers/usb/gadget/v3_burning/Kconfig
@@ -30,5 +30,19 @@ default y select AML_V2_FACTORY_BURN +config SUPPORT_BACKUP_PART_NORMAL_ERASE + bool "support backup part when normal erasing" + default n + +config BACKUP_PART_NORMAL_ERASE + depends on SUPPORT_BACKUP_PART_NORMAL_ERASE + string "config backup part name" + help + This configure define part which need backup to mem before normal erase + backup before erasing, and restore it after erasing + There is probablity data lost if erasing failed or write failed + + + endif #AML_V3_FACTORY_BURN
diff --git a/drivers/usb/gadget/v3_burning/aml_v3_burning.c b/drivers/usb/gadget/v3_burning/aml_v3_burning.c index e423875..07b2548 100644 --- a/drivers/usb/gadget/v3_burning/aml_v3_burning.c +++ b/drivers/usb/gadget/v3_burning/aml_v3_burning.c
@@ -5,6 +5,7 @@ #include "include/v3_tool_def.h" #include <mmc.h> +#include <amlogic/cpu_id.h> #ifndef BOOT_DEVICE_USB #define BOOT_DEVICE_SD 4 #define BOOT_DEVICE_USB 5 @@ -13,10 +14,28 @@ extern void board_init_mem(void); -static unsigned _get_romcode_boot_id(void) +unsigned _get_romcode_boot_id(void) { - FB_DBG("cfg0 0x%08x\n", readl(P_AO_SEC_GP_CFG0)); - const unsigned boot_id = readl(P_AO_SEC_GP_CFG0) & 0xf; + const cpu_id_t cpuid = get_cpu_id(); + const int familyId = cpuid.family_id; + + unsigned boot_id = 0; +#ifdef SYSCTRL_SEC_STATUS_REG2 + if (MESON_CPU_MAJOR_ID_SC2 <= familyId && MESON_CPU_MAJOR_ID_C2 != familyId) { + boot_id = readl(SYSCTRL_SEC_STATUS_REG2); + FB_DBG("boot_id 0x%x\n", boot_id); + boot_id = (boot_id>>4) & 0xf; + } + FB_DBG("boot_id 1x%x\n", boot_id); +#endif// #ifdef SYSCTRL_SEC_STATUS_REG2 + +#if defined(P_AO_SEC_GP_CFG0) + if (MESON_CPU_MAJOR_ID_C2 >= familyId && + MESON_CPU_MAJOR_ID_SC2 != familyId) { + FB_DBG("cfg0 0x%08x\n", readl(P_AO_SEC_GP_CFG0)); + boot_id = readl(P_AO_SEC_GP_CFG0) & 0xf; + } +#endif// #if defined(P_AO_SEC_GP_CFG0) return boot_id; }
diff --git a/drivers/usb/gadget/v3_burning/include/v3_tool_def.h b/drivers/usb/gadget/v3_burning/include/v3_tool_def.h index 60d733f..dd56dee 100644 --- a/drivers/usb/gadget/v3_burning/include/v3_tool_def.h +++ b/drivers/usb/gadget/v3_burning/include/v3_tool_def.h
@@ -96,6 +96,7 @@ V3TOOL_MEDIA_TYPE_STORE = 0xefee, V3TOOL_MEDIA_TYPE_MEM , V3TOOL_MEDIA_TYPE_UNIFYKEY , + V3TOOL_MEDIA_TYPE_MMC ,//1-->emmc, 0-->sdcard }; #define V3_PART_NAME_LEN 32 @@ -216,7 +217,7 @@ void v3tool_media_set_free(const char* info); int v3tool_media_is_busy(void); -#ifndef P_AO_SEC_SD_CFG0 +#ifdef SYSCTRL_SEC_STATUS_REG4 //#define P_AO_SEC_SD_CFG9 SYSCTRL_SEC_STATUS_REG1 #define P_AO_SEC_GP_CFG0 SYSCTRL_SEC_STATUS_REG4 #define P_PREG_STICKY_REG2 SYSCTRL_SEC_STICKY_REG2
diff --git a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c index 0dd65a8..940f3b1 100644 --- a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c +++ b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c
@@ -4,6 +4,7 @@ */ #include "../include/v3_tool_def.h" +#include <mmc.h> int v3tool_simg2img_init(const ImgDownloadPara* downPara); int v3tool_simg2img_get_img(UsbDownInf* downInf); @@ -20,12 +21,6 @@ FB_ERR("burn key not supported as CONFIG_UNIFY_KEY_MANAGE undef!!"); return -1; } - -static int v2_key_command(const int argc, char * const argv[], char *info) -{ - FB_ERR("burn key not supported as CONFIG_UNIFY_KEY_MANAGE undef!!"); - return -1; -} #define key_manage_query_size(a,b) 1 #endif// //#ifdef CONFIG_V3_KEY_BURNING_SUPPORT @@ -134,6 +129,46 @@ return 0; } +static int _buffman_img_init_mmc(const char* partName, const int isDownload, const int64_t imgSize, const int64_t partStartOff) +{ +#if CONFIG_IS_ENABLED(MMC_WRITE) + int dev = -1; + + if (strcmp("1", partName) && strcmp("0", partName)) { + FBS_ERR(_ACK, "mmc part[%s] invalid\n", partName); return -__LINE__; + } + env_set("mmc_dev_id", partName); + env_set("mmc_select_dev", "mmc dev ${mmc_dev_id}"); + if (run_command("printenv mmc_select_dev; run mmc_select_dev", 0)) { + FBS_ERR(_ACK, "Fail in init mmc dev %s\n", partName); return -__LINE__; + } + + dev = partName[0] - '0'; + struct mmc* mmc = find_mmc_device(dev); + if (!mmc) { + FBS_ERR(_ACK, "no mmc device at slot %x\n", dev); return -__LINE__; + } + if (mmc_init(mmc)) { + FBS_ERR(_ACK, "fail in init mmc %d\n", dev); return -__LINE__; + } + const int64_t capacity = mmc->capacity_user; + if (capacity < partStartOff + imgSize) { + FBS_ERR(_ACK, "capacity < partStartOff + imgSize 0x:%llx %llx %llx\n", capacity, partStartOff, imgSize); + return -__LINE__; + } + if (mmc_getwp(mmc) == 1) { + FBS_ERR(_ACK, "Error: mmc(%s) is write protected!\n", partName); + return -__LINE__; + } + run_command("store rsv protect key off", 0);//disprotect key for write/dump all emmc + + return 0; +#else + FBS_ERR(_ACK, "CONFIG_MMC_WRITE not enabled\n"); + return -__LINE__; +#endif//#if CONFIG_IS_ENABLED(MMC_WRITE) +} + //@imgPara: //@isDownload: 1 if download, 0 if upload //@needVerify: 1 if need verify, if need verify, will save some info while downloading @@ -148,6 +183,8 @@ _imgTransferInfo.inited = 1; ImgCommonPara* commonInf = &imgPara->commonInf; const int64_t imgSize = commonInf->imgSzTotal; + const int64_t partStartOff = commonInf->partStartOff; + const char* partName = commonInf->partName; int ret = 0; switch (commonInf->mediaType) @@ -160,7 +197,7 @@ } break; case V3TOOL_MEDIA_TYPE_STORE: { - ret = v3tool_media_check_image_size(imgSize, commonInf->partName); + ret = v3tool_media_check_image_size(imgSize + partStartOff, partName); if ( ret ) { FB_EXIT("Fail in check img sz\n"); } @@ -179,6 +216,11 @@ } } } break; + case V3TOOL_MEDIA_TYPE_MMC: + { + ret = _buffman_img_init_mmc(partName, isDownload, imgSize, partStartOff); + if (ret) FB_EXIT("Fail in init mmc %s\n", partName); + } break; default: FB_EXIT("Exception, err media type 0x%x\n", commonInf->mediaType); } @@ -209,6 +251,7 @@ _usbDownInf.dataBuf = _imgTransferInfo.dataBuf + _rawImgFileOffset; FB_DBG("dataBuf %p, dataSize %x\n", _usbDownInf.dataBuf, _usbDownInf.dataSize); }break; + case V3TOOL_MEDIA_TYPE_MMC: case V3TOOL_MEDIA_TYPE_STORE: { _usbDownInf.fileOffset = _rawImgFileOffset; @@ -280,6 +323,29 @@ return ret; } +static int _v3tool_mmc_rw(const char* partName, const int write, const int thisTransferLen, loff_t partOffset, void* dataBuf) +{ +#if CONFIG_IS_ENABLED(MMC_WRITE) + int dev = *partName - '0'; + struct mmc *mmc = find_mmc_device(dev); + if (!mmc) { + FBS_ERR(_ACK, "no mmc device at slot %x\n", dev); return -__LINE__; + } + if (mmc_init(mmc)) { + FBS_ERR(_ACK, "fail mmc_init[%s]", partName); return -__LINE__; + } + u32 cnt = (thisTransferLen + 511) >> 9; + u32 blk = partOffset>>9; + u32 n = 0; + if (write) n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, dataBuf); + else n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, dataBuf); + return (n == cnt) ? 0 : -__LINE__; +#else + FBS_ERR(_ACK, "CONFIG_MMC_WRITE not enabled\n"); + return -__LINE__; +#endif//#if CONFIG_IS_ENABLED(MMC_WRITE) +} + int v3tool_buffman_data_complete_download(const UsbDownInf* downloadInf) { ImgCommonPara* cmnInf = &_imgTransferInfo.imgTransPara.commonInf; @@ -291,6 +357,7 @@ int ret = 0; const int thisTransferLen = downloadInf->dataSize; u8* dataBuf = (u8*)downloadInf->dataBuf; + loff_t partOffset = downloadInf->fileOffset + cmnInf->partStartOff; switch ( imgFmt ) { case V3TOOL_PART_IMG_FMT_RAW: @@ -304,7 +371,7 @@ ret = store_dtb_rw(dataBuf, thisTransferLen, 1); } else { - ret = store_logic_write(partName, downloadInf->fileOffset, thisTransferLen, dataBuf); + ret = store_logic_write(partName, partOffset, thisTransferLen, dataBuf); } } break; case V3TOOL_MEDIA_TYPE_MEM: @@ -316,6 +383,10 @@ ret = -__LINE__; } else ret = 0; break; + case V3TOOL_MEDIA_TYPE_MMC: + { + ret = _v3tool_mmc_rw(partName, 1, thisTransferLen, partOffset, dataBuf); + } break; default: FBS_ERR(fb_response_str, "err media type %d for raw img", mediaType); break; @@ -367,6 +438,7 @@ _usbUpInf.dataBuf = (char*)V3_DOWNLOAD_MEM_BASE; u8* dataBuf = (u8*)_usbUpInf.dataBuf; unsigned dataSize = _usbUpInf.dataSize; + loff_t partOffset = _rawImgFileOffset + cmnInf->partStartOff; switch (cmnInf->mediaType) { case V3TOOL_MEDIA_TYPE_MEM: { @@ -384,7 +456,7 @@ ret = store_dtb_rw(dataBuf, dataSize, 2); } else { - ret = store_logic_read(partName, _rawImgFileOffset, dataSize, dataBuf); + ret = store_logic_read(partName, _rawImgFileOffset + cmnInf->partStartOff, dataSize, dataBuf); } if (ret) { FB_ERR("Fail in read store at offset %llx\n", _rawImgFileOffset); @@ -401,6 +473,10 @@ return -__LINE__; } }break; + case V3TOOL_MEDIA_TYPE_MMC: + { + ret = _v3tool_mmc_rw(partName, 0, dataSize, partOffset, dataBuf); + } break; default: FB_ERR("unsupported media %d\n", cmnInf->mediaType); break;
diff --git a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c index 51043d7..197867e 100644 --- a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c +++ b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c
@@ -6,6 +6,7 @@ #include "../include/v3_tool_def.h" #include <fdtdec.h> #include <asm/arch/cpu_config.h> +#include <u-boot/sha256.h> #define DWN_ERR FB_ERR #define BOOTLOADER_MAX_SZ (0x2<<20) #define DTB_MAX_SZ (256<<10) @@ -61,13 +62,8 @@ if (is_bootloader_discrte(&discreteMode)) { return 0; } - if (discreteMode) { - return BL2_SIZE/*store_boot_copy_size("bl2")*/ + store_boot_copy_size("tpl"); - } else { - return store_boot_copy_size("bootloader"); - } - return 0; + return store_boot_copy_size("bootloader"); } static int _bootloader_write(u8* dataBuf, unsigned off, unsigned binSz, const char* bootName) @@ -91,17 +87,95 @@ return 0; } +static p_payload_info_t _bl2x_mode_detect(u8* dataBuf) +{ + p_payload_info_t pInfo = (p_payload_info_t)(dataBuf + BL2_SIZE); + + if (AML_MAGIC_HDR_L == pInfo->hdr.nMagicL && AML_MAGIC_HDR_R == pInfo->hdr.nMagicR) { + FB_MSG("aml log : bootloader blxx mode!\n"); + return pInfo; + } + return NULL; +} + +#ifdef CONFIG_SHA256 +static int _bl2x_mode_check_header(p_payload_info_t pInfo) +{ + p_payload_info_hdr_t hdr = &pInfo->hdr; + uint8_t gensum[SHA256_SUM_LEN]; + const int nItemNum = hdr->byItemNum; + + printf("\naml log : info parse...\n"); + printf("\tsztimes : %s\n",hdr->szTimeStamp); + printf("\tversion : %d\n",hdr->byVersion); + printf("\tItemNum : %d\n",nItemNum); + printf("\tSize : %d(0x%x)\n", hdr->nSize, hdr->nSize); + if (nItemNum > 8 || nItemNum < 3) { FBS_EXIT(_ACK, "illegal nitem num %d\n", nItemNum); } + + const int nsz = sizeof(payload_info_hdr_t) + nItemNum * sizeof(payload_info_item_t) - SHA256_SUM_LEN; + FB_MSG("nsz 0x%x\n", nsz); + sha256_context ctx; + sha256_starts(&ctx); + sha256_update(&ctx, (u8*)&(hdr->nMagicL), nsz); + sha256_finish(&ctx, gensum); + int ret = memcmp(gensum, hdr->szSHA2, SHA256_SUM_LEN); + if (ret) { FBS_EXIT(_ACK, "hdr info sha256sum not matched\n"); } + FB_MSG("hdr info sha256sum DO matched\n"); + + return 0; +} +#else +#define _bl2x_mode_check_header(...) 0 +#endif// #ifdef CONFIG_SHA256 + +static const char* _flashPayload[] = {"bl2", "bl2e", "bl2x", "ddrfip", "devfip"}; +static p_payload_info_t _blxPayloadInf = NULL; +static int _payloadInfoSz = 0; static int _discrete_bootloader_write(u8* dataBuf, unsigned off, unsigned binSz) { int bl2CopySz = BL2_SIZE/*(int)store_boot_copy_size("bl2")*/; FB_MSG("bl2CopySz 0x%x, binSz 0x%x\n", bl2CopySz, binSz); + int ret = 0; - int ret = _bootloader_write(dataBuf, 0, bl2CopySz, "bl2"); + if (binSz > bl2CopySz) + { + _blxPayloadInf = NULL; + p_payload_info_t pInfo = _bl2x_mode_detect(dataBuf); + if (!pInfo) { + ret = _bootloader_write(dataBuf + bl2CopySz, 0, binSz - bl2CopySz, "tpl"); + if (ret) FBS_EXIT(_ACK, "Fail in burn tpl\n"); + } else + { + if (_bl2x_mode_check_header(pInfo)) { + FBS_EXIT(_ACK, "Fail in check bl2x info\n"); + } + char name[8]; + int nIndex = 0; + p_payload_info_hdr_t hdr = &pInfo->hdr; + p_payload_info_item_t pItem = pInfo->arrItems; + + int offPayload = 0, szPayload = 0; + + memset(name, 0, 8); + for (nIndex = 1, pItem += 1; nIndex < hdr->byItemNum; ++nIndex, ++pItem) + { + memcpy(name, &pItem->nMagic, sizeof(unsigned int)); + offPayload = pItem->nOffset; + szPayload = pItem->nPayLoadSize; + FB_MSG("Item[%d]%4s offset 0x%08x sz 0x%x\n", nIndex, name, offPayload, szPayload); + if (!szPayload) continue; + ret = _bootloader_write(dataBuf + offPayload, 0, szPayload, _flashPayload[nIndex]); + if (ret) FBS_EXIT(_ACK, "Fail in flash payload %s\n", name); + } + _blxPayloadInf = (p_payload_info_t)V3_DOWNLOAD_VERIFY_INFO; + _payloadInfoSz = sizeof(payload_info_hdr_t) + pInfo->hdr.byItemNum * sizeof(payload_info_item_t); + memcpy(_blxPayloadInf, pInfo, _payloadInfoSz); + } + } + + ret = _bootloader_write(dataBuf, 0, bl2CopySz, "bl2"); if (ret) FBS_EXIT(_ACK, "Fail in program bl2\n"); - if (binSz <= bl2CopySz) return 0; - ret = _bootloader_write(dataBuf + bl2CopySz, 0, binSz - bl2CopySz, "tpl"); - if (ret) FBS_EXIT(_ACK, "Fail in burn tpl\n"); return 0; } @@ -150,11 +224,38 @@ FB_MSG("bl2CopySz 0x%x, binSz 0x%x\n", bl2CopySz, binSz); int ret = _bootloader_read(dataBuf, 0, bl2CopySz, "bl2"); - if (ret) FBS_EXIT(_ACK, "Fail in program bl2\n"); + if (ret) FBS_EXIT(_ACK, "Fail in read bl2\n"); if (binSz <= bl2CopySz) return 0; + memset(dataBuf + bl2CopySz, 0, bl2CopySz);//clear 2k after bl2_size - ret = _bootloader_read(dataBuf + bl2CopySz, 0, binSz - bl2CopySz, "tpl"); - if (ret) FBS_EXIT(_ACK, "Fail in burn tpl\n"); + if (!_blxPayloadInf) { + ret = _bootloader_read(dataBuf + bl2CopySz, 0, binSz - bl2CopySz, "tpl"); + if (ret) FBS_EXIT(_ACK, "Fail in read tpl\n"); + } else { + char name[8]; + int nIndex = 0; + if (!_blxPayloadInf) FBS_EXIT(_ACK, "exception, _blxPayloadInf null\n"); + + p_payload_info_t pInfo = _blxPayloadInf; + p_payload_info_hdr_t hdr = &pInfo->hdr; + p_payload_info_item_t pItem = pInfo->arrItems; + + int offPayload = 0, szPayload = 0; + + memset(name, 0, 8); + for (nIndex = 1, pItem +=1; nIndex < hdr->byItemNum; ++nIndex, ++pItem) + { + memcpy(name, &pItem->nMagic, sizeof(unsigned int)); + offPayload = pItem->nOffset; + szPayload = pItem->nPayLoadSize; + FB_MSG("Item[%d]%4s offset 0x%08x sz 0x%x\n", nIndex, name, offPayload, szPayload); + if (!szPayload) continue; + ret = _bootloader_read(dataBuf + offPayload, 0, szPayload, _flashPayload[nIndex]); + if (ret) FBS_EXIT(_ACK, "Fail in read payload %s\n", name); + } + memcpy(dataBuf + BL2_SIZE, _blxPayloadInf, _payloadInfoSz); + } + return 0; } @@ -286,6 +387,11 @@ struct mtd_partition* __attribute__((weak)) get_partition_table(int *partitions) { FB_WRN("get_partition_table undefined\n"); return NULL;} +#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE +const char* BackupPart = (const char*)(CONFIG_BACKUP_PART_NORMAL_ERASE); +char* BackupPartAddr = (char*)(V3_DOWNLOAD_MEM_BASE); +#endif// #ifdef CONFIG_BACKUP_PART_NORMAL_ERASE + int v3tool_storage_init(const int eraseFlash, unsigned dtbImgSz) { int ret = 0; @@ -315,6 +421,9 @@ if (ret <= 0) FBS_EXIT(_ACK, "Fail in store init %d, ret %d\n", 1, ret); +#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE + u32 backupPartSz = 0; +#endif//#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE int initFlag = 0; switch (eraseFlash) { case 0://NO erase @@ -323,12 +432,21 @@ break; case 3://erase all(with key) - { - if (store_rsv_protect("key", false)) - FBS_EXIT(_ACK, "Fail in disprotect key\n"); - } case 1://normal erase, store init 3 initFlag = 3; + if (3 == eraseFlash) { + if (store_rsv_protect("key", false)) + FBS_EXIT(_ACK, "Fail in disprotect key\n"); + } else { +#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE + //backup env to memory + backupPartSz = (u32)store_part_size(BackupPart); + FB_MSG("BackupPart %s sz 0x%x\n", BackupPart, backupPartSz); + if (!backupPartSz) { FBS_EXIT(_ACK, " FAil in find BackupPart %s\n", BackupPart);} + ret = store_read(BackupPart, 0, backupPartSz, BackupPartAddr); + if (ret) { FBS_EXIT(_ACK, "FAil in backup important part %s to mem\n", BackupPart);} +#endif//#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE + } break; case 4: {//force erase all @@ -350,6 +468,12 @@ } else if (initFlag > 1) { ret = store_erase(NULL, 0, 0, 0); if (ret) FBS_EXIT(_ACK, "Fail in erase flash, ret[%d]\n", ret); +#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE + if (backupPartSz) { + FB_MSG("restore BackupPart %s from mem\n", BackupPart); + store_write(BackupPart, 0, backupPartSz, BackupPartAddr); + } +#endif//#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE } if (V3TOOL_WORK_MODE_USB_PRODUCE == v3tool_work_mode_get()) {
diff --git a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_simg2img.c b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_simg2img.c index 4b032f8..113f2a8 100644 --- a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_simg2img.c +++ b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_simg2img.c
@@ -95,6 +95,15 @@ * so don't update global var in get_img, * so update @leftTransLen in v3tool_simg2img_write_img, which is after usb->ddr check ok * */ +/* + * code flow: first time, then {sz = header + first chunkinfo, offset = 0} + * else { + * offset = _spPacketStates.fileOffset; + * sz = V3_DOWNLOAD_MEM_SIZE ; + * if (sz + spare >= img left sz) then sz = img left sz + * ??write img only dispose DATA + chunkinfo, so maybe 8M > this, but not matter?? + * } + */ int v3tool_simg2img_get_img(UsbDownInf* downInf) { downInf->dataBuf = (char*)V3_DOWNLOAD_MEM_BASE; @@ -115,6 +124,7 @@ if (_spPacketStates.imgTotalLen == _spPacketStates.fileOffset) { *dataSize = 0; _downloadState = SP_DOWNLOAD_OK; + spmsg("Finish sparse img\n"); return 0; } FBS_ERR(fb_response_str, "Excep:NO leftTransLen but img not end, fileOffset %llx, leftChunkNum %d", @@ -169,7 +179,7 @@ return -__LINE__; } const int fillFieldLen = 4; - *fillVal = *(unsigned*)(chunk+1); + if (fillVal) *fillVal = *(unsigned*)(chunk+1); chunkDataLen = fillFieldLen; }break; case CHUNK_TYPE_CRC32: @@ -220,6 +230,7 @@ } while (LeftDataLen >0) { const unsigned thisWriteLen = min(LeftDataLen, BufSz); + FB_DBG("fill off/sz/val 0x%08llx %x %x\n", flashAddr, thisWriteLen, fillVal); int ret = store_logic_write(partName, flashAddr, thisWriteLen, fillBuf); if (ret) { sperr("FILL_CHUNK:Want write 0x%x Bytes, but failed\n", thisWriteLen); @@ -254,7 +265,7 @@ const chunk_header_t* nextDownInf = NULL; bool hasFileHeader = false; bool hasChunkBody = true; - bool hasNextChunkInfo = true; + bool hasNextChunkInfo = true;//nextChunkInfo //update globals not affected by rx data format _spPacketStates.fileOffset += dataSize; @@ -275,10 +286,10 @@ //2, sparse_header_t *header = (sparse_header_t*) dataBuf; - _spPacketStates.leftChunkNum = header->total_chunks - 1; + _spPacketStates.leftChunkNum = header->total_chunks - 1;//how many chunkinfo not parsed _spPacketStates.pktHeadLen = header->file_hdr_sz; _spPacketStates.sparseBlkSz = header->blk_sz;//often 4k - spmsg("totalChunkNum %d, fileHeadSz 0x%x, chunkHeadSz 0x%zx, blk 0x%x\n", _spPacketStates.leftChunkNum, + spmsg("totalChunkNum %d, fileHeadSz 0x%x, chunkHeadSz 0x%zx, blk 0x%x\n", _spPacketStates.leftChunkNum + 1, _spPacketStates.pktHeadLen, CHUNK_HEAD_SIZE, _spPacketStates.sparseBlkSz); //3, @@ -294,8 +305,8 @@ { if (lastChunk) {//img ended hasNextChunkInfo = false; - spmsg("sparse img ended\n"); - return 0; + spmsg("last chunk\n"); + /*return 0;*/ } if ( _spPacketStates.leftTransLen ) {//only data body hasNextChunkInfo = false; @@ -310,13 +321,14 @@ { const chunk_header_t* pChunk = _spPacketStates.chunkInfo;//this download info const char* part = downPara->commonInf.partName; - int64_t flashAddr = _spPacketStates.nextFlashAddr; + int64_t flashAddr = _spPacketStates.nextFlashAddr + downPara->commonInf.partStartOff; unsigned flashWrLen = dataSize; const unsigned chunkFlashSpace = pChunk->chunk_sz * _spPacketStates.sparseBlkSz;; //spmsg("chunkInfo %p, %x\n", pChunk, pChunk->chunk_type); const unsigned chunkType = pChunk->chunk_type; if (CHUNK_TYPE_RAW == chunkType) { + FB_DBG("raw wr: off/sz 0x%08llx flashWrLen %x\n", flashAddr, flashWrLen); if (store_logic_write(part, flashAddr, flashWrLen, dataBuf)) { sperr("Fail in flash raw trunk\n"); return -__LINE__; @@ -328,7 +340,8 @@ return -__LINE__; } const unsigned* fillVal = (unsigned*)dataBuf; - if (simg2img_fill_chunk_write((char*)part, chunkFlashSpace, fillVal, _spPacketStates.nextFlashAddr)) { + FB_DBG("fill wr: off/sz 0x%08llx flashWrLen %x\n", _spPacketStates.nextFlashAddr, chunkFlashSpace); + if (simg2img_fill_chunk_write((char*)part, chunkFlashSpace, fillVal, flashAddr)) { sperr("Fail in fill fill-chunk\n"); return -__LINE__; } @@ -338,6 +351,7 @@ sperr("DONT_CARE trunk sz %x err, should be 0\n", dataSize); return -__LINE__; } + FB_DBG("donnot care: off/sz 0x%08llx flashWrLen", _spPacketStates.nextFlashAddr, chunkFlashSpace); _spPacketStates.nextFlashAddr += chunkFlashSpace; } else { sperr("chunk(%x) should not be here", chunkType); @@ -444,6 +458,7 @@ int64_t flashAddr = _partOffset + chunkDataLen - _dataChunkLeft; while ( _dataChunkLeft ) { const int thisLen = min(vryBuffLen, _dataChunkLeft); + FB_DBG("rd chunk %x: off/sz 0x%08llx %x\n", backInf->chunk_type, flashAddr, thisLen); if (store_logic_read(partName, flashAddr, thisLen, dataBuf)) { sperr("Fail in read storage for verify\n"); goto _verify_end;
diff --git a/drivers/usb/gadget/v3_burning/v3_usb_tool/aml_dnl.c b/drivers/usb/gadget/v3_burning/v3_usb_tool/aml_dnl.c index 23a5039..dc43ba0 100644 --- a/drivers/usb/gadget/v3_burning/v3_usb_tool/aml_dnl.c +++ b/drivers/usb/gadget/v3_burning/v3_usb_tool/aml_dnl.c
@@ -27,9 +27,9 @@ * CONFIG_USB_GADGET_MANUFACTURER * at e.g. ./configs/<board>_defconfig */ -#define CONFIG_USB_GADGET_VENDOR_NUM 0x1b8e -#define CONFIG_USB_GADGET_PRODUCT_NUM 0xc004 -#define CONFIG_USB_GADGET_MANUFACTURER "Amlogic Inc" +//#define CONFIG_USB_GADGET_VENDOR_NUM 0x1b8e +//#define CONFIG_USB_GADGET_PRODUCT_NUM 0xc004 +//#define CONFIG_USB_GADGET_MANUFACTURER "Amlogic Inc" #define STRING_MANUFACTURER 25 #define STRING_PRODUCT 2
diff --git a/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c b/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c index 8c54a3a..d4c3d88 100644 --- a/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c +++ b/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c
@@ -18,7 +18,7 @@ #include <partition_table.h> #include <android_image.h> #include <image.h> -/*#include <emmc_partitions.h>*/ +#include <amlogic/cpu_id.h> #include "../include/v3_tool_def.h" DECLARE_GLOBAL_DATA_PTR; static void cb_aml_media_write(struct usb_ep *ep, struct usb_request *req); @@ -489,7 +489,7 @@ } static const char* getvar_list[] = { - "version", "serialno", "product", "erase-block-size", "secure", "HW_ID", + "version", "serialno", "product", "erase-block-size", "secure", }; static const char* getvar_list_ab[] = { "version", "serialno", "product", "erase-block-size", @@ -549,7 +549,9 @@ return; } else if (!strcmp_l1("identify", cmd)) { const int identifyLen = 8; - const char fwVer[] = {5, 0, 0, 16, 0, 0, 0, 0}; + char fwVer[] = {5, 0, 0, 16, 0, 0, 0, 0}; + cpu_id_t cpuid = get_cpu_id(); + if (cpuid.family_id >= MESON_CPU_MAJOR_ID_SC2) fwVer[0] = 6; memcpy(response + 4, fwVer, identifyLen); replyLen = 4 + identifyLen; adnl_identify_timeout = 0; @@ -567,6 +569,12 @@ const char* usid = get_usid_string(); if (usid) strncat(response, usid, chars_left); else strncat(response, DEVICE_SERIAL, chars_left); + } else if (!strcmp_l1("soctype", cmd)) { + cpu_id_t cpuid = get_cpu_id(); + *(unsigned*)(response+4) = cpuid.family_id; + *(unsigned*)(response+8) = cpuid.chip_rev; + FB_DBG("soctype 0x%08x, %08x\n", cpuid.family_id, cpuid.chip_rev); + replyLen = 4 + 8; } else if (!strcmp_l1("product", cmd)) { char* s1 = DEVICE_PRODUCT; strncat(response, s1, chars_left); @@ -574,11 +582,6 @@ strncat(response, "2", chars_left); } else if (!strcmp_l1("erase-block-size", cmd)) { strncat(response, "2000", chars_left); - } else if (!strcmp_l1("HW_ID", cmd)) { - char *hw_id; - run_command("get_board_hw_id", 0); - hw_id = env_get("hw_id"); - strncat(response, hw_id, chars_left); } else { FB_ERR("unknown variable: %s\n", cmd); strcpy(response, "FAILVariable not implemented"); @@ -1121,7 +1124,7 @@ } const char* _imgFmt[] = {"normal", "sparse", "ubifs"}; -const char* _mediatype[] = {"store", "mem", "key"}; +const char* _mediatype[] = {"store", "mem", "key", "mmc"}; static int _verify_partition_img(const int argc, char* argv[], char* ack) { @@ -1224,9 +1227,8 @@ FB_MSG("mem base %llx\n", commonInf->partStartOff); } break; case V3TOOL_MEDIA_TYPE_STORE: - { - //TODO: add part sz check (assert imgsz <= part cap) - }break; + case V3TOOL_MEDIA_TYPE_MMC: + { }break; case V3TOOL_MEDIA_TYPE_UNIFYKEY: { if ( imgSize >= _UNIFYKEY_MAX_SZ ) { @@ -1243,7 +1245,7 @@ FB_ERR("Fail in buffman init, ret %d\n", ret); return -__LINE__; } - printf("Flash 0x%08llx Bytes %s img to %s:%s\n", imgSize, imgFmt, media, partition); + printf("Flash 0x%08llx Bytes %s img to %s:%s at off 0x%llx\n", imgSize, imgFmt, media, partition, partOff); return ret; } @@ -1302,6 +1304,7 @@ } break; case V3TOOL_MEDIA_TYPE_STORE: case V3TOOL_MEDIA_TYPE_UNIFYKEY: + case V3TOOL_MEDIA_TYPE_MMC: { strncpy(commonInf->partName, partition,V3_PART_NAME_LEN); }break;
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c index 63df301..dc38569 100644 --- a/drivers/usb/host/xhci-dwc3.c +++ b/drivers/usb/host/xhci-dwc3.c
@@ -137,7 +137,6 @@ void xhci_dwc3_phy_tuning_1(struct udevice *dev, int port) { - unsigned long phy_reg_base; int ret, i; struct xhci_dwc3_platdata *plat; struct udevice *udev = dev; @@ -152,7 +151,6 @@ return ; } } - } static int xhci_dwc3_setup_phy(struct udevice *dev) @@ -207,7 +205,7 @@ } #ifdef CONFIG_AML_USB - int usb_type = 0; + unsigned int usb_type = 0; for (i = 0; i < plat->num_phys; i++) { dev_read_u32((&plat->usb_phys[i])->dev, "phy-version", &usb_type); @@ -235,33 +233,15 @@ return ret; } -static int xhci_dwc3_shutdown_phy(struct udevice *dev) -{ - struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); - int i, ret; - - for (i = 0; i < plat->num_phys; i++) { - if (!generic_phy_valid(&plat->usb_phys[i])) - continue; - - ret = generic_phy_power_off(&plat->usb_phys[i]); - ret |= generic_phy_exit(&plat->usb_phys[i]); - if (ret) { - pr_err("Can't shutdown USB PHY%d for %s\n", - i, dev->name); - } - } - - return 0; -} - static int xhci_dwc3_probe(struct udevice *dev) { struct xhci_hcor *hcor; struct xhci_hccr *hccr; struct dwc3 *dwc3_reg; enum usb_dr_mode dr_mode; +#ifndef CONFIG_AML_USB struct xhci_dwc3_platdata *plat = dev_get_platdata(dev); +#endif int ret; #ifdef CONFIG_AML_USB
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 1eae743..4e7866a 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c
@@ -1311,7 +1311,7 @@ return -ENOMEM; reg = xhci_readl(&hccr->cr_hcsparams1); -#ifdef CONFIG_AML_USB +#ifdef CONFIG_AML_USB2_PHY descriptor.hub.bNbrPorts = usb2portnum; #else descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
diff --git a/drivers/watchdog/meson_wdt.c b/drivers/watchdog/meson_wdt.c index 6aac18e..cd38b79 100644 --- a/drivers/watchdog/meson_wdt.c +++ b/drivers/watchdog/meson_wdt.c
@@ -1,244 +1,257 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <wdt.h> -#include <asm/io.h> -#include <linux/io.h> -#include <clk.h> -#include <asm/arch/bl31_apis.h> - -#define MESON_WDT_CTRL_REG 0x0 -#define MESON_WDT_TCNT_REG 0x8 -#define MESON_WDT_RSET_REG 0xc - -#define MESON_WDT_CTRL_CLKDIV_EN BIT(25) -#define MESON_WDT_CTRL_CLK_EN BIT(24) -#define MESON_WDT_CTRL_EE_RESET BIT(21) -#define MESON_WDT_CTRL_EN BIT(18) -#define MESON_WDT_CTRL_DIV_MASK (BIT(18) - 1) -#define MESON_WDT_TCNT_SETUP_MASK (BIT(16) - 1) -#define MESON_WDT_TCNT_CNT_SHIFT (16) - -#define WDT_DISABLE 1 -#define WDT_ENABLE 2 -#define WDT_PING 3 -#define WDT_INIT 4 -#define WDT_RESETNOW 5 -#define WDT_SETTIMEOUT 6 -#define WDT_OPS 0x82000086 - -#define DEFAULT_TIMEOUT 1 - -struct meson_wdt_priv { - void __iomem *regs; -}; - -struct meson_wdt_data { - struct wdt_ops *ops; -}; - -/***************** gxbb ***********************/ -static int meson_gxbb_wdt_reset(struct udevice *dev) -{ - struct meson_wdt_priv *priv; - - assert(dev); - priv = dev_get_priv(dev); - writel(0, priv->regs + MESON_WDT_RSET_REG); - - return 0; -} - -static int meson_gxbb_wdt_set_timeout(struct udevice *dev, unsigned int timeout) -{ - struct meson_wdt_priv *priv; - unsigned long tcnt = timeout * 1000; - - assert(dev); - priv = dev_get_priv(dev); - if (tcnt > MESON_WDT_TCNT_SETUP_MASK) - tcnt = MESON_WDT_TCNT_SETUP_MASK; - meson_gxbb_wdt_reset(dev); - writel(tcnt, priv->regs + MESON_WDT_TCNT_REG); - - return 0; -} - -static int meson_gxbb_wdt_start(struct udevice *dev, u64 timeout, ulong flags) -{ - struct meson_wdt_priv *priv; - - assert(dev); - priv = dev_get_priv(dev); - meson_gxbb_wdt_set_timeout(dev, timeout); - writel(readl(priv->regs + MESON_WDT_CTRL_REG) | MESON_WDT_CTRL_EN, - priv->regs + MESON_WDT_CTRL_REG); - - return 0; -} - -static int meson_gxbb_wdt_stop(struct udevice *dev) -{ - struct meson_wdt_priv *priv; - - assert(dev); - priv = dev_get_priv(dev); - writel(readl(priv->regs + MESON_WDT_CTRL_REG) & ~MESON_WDT_CTRL_EN, - priv->regs + MESON_WDT_CTRL_REG); - - return 0; -} - -static int meson_gxbb_wdt_expire_now(struct udevice *dev, ulong flags) -{ - meson_gxbb_wdt_start(dev, 1, flags); - - return 0; -} - -static int meson_gxbb_wdt_probe(struct udevice *dev) -{ - struct meson_wdt_priv *priv; - fdt_addr_t addr; - fdt_size_t size; - struct clk w_clk; - unsigned int rate = 0; - int ret; - - assert(dev); - priv = dev_get_priv(dev); - addr = devfdt_get_addr_size_index(dev, 0, &size); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - priv->regs = (void __iomem *)addr; - ret = clk_get_by_name(dev, "wdt-clk", &w_clk); - if (ret < 0) { - printf("Failed to get wdt-clk.\n"); - return ret; - } - rate = clk_get_rate(&w_clk); - if (rate < 0) { - printf("Failed to get wdt-clk rate.\n"); - return ret; - } - writel(((rate / 1000) & MESON_WDT_CTRL_DIV_MASK) | - MESON_WDT_CTRL_EE_RESET | - MESON_WDT_CTRL_CLK_EN | - MESON_WDT_CTRL_CLKDIV_EN, priv->regs + MESON_WDT_CTRL_REG); - meson_gxbb_wdt_set_timeout(dev, DEFAULT_TIMEOUT); - meson_gxbb_wdt_stop(dev); - - return 0; -} - -static struct wdt_ops meson_gxbb_wdt_ops = { - .start = meson_gxbb_wdt_start, - .stop = meson_gxbb_wdt_stop, - .expire_now = meson_gxbb_wdt_expire_now, - .reset = meson_gxbb_wdt_reset, -}; - -static struct meson_wdt_data meson_gxbb_data = { - .ops = &meson_gxbb_wdt_ops, -}; - -/**************** a1 **********************/ -void __attribute__((weak)) wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value) -{ - -} -static int meson_a1_wdt_start(struct udevice *dev, u64 timeout, ulong flags) -{ - wdt_send_cmd_to_bl31(WDT_INIT, timeout); - wdt_send_cmd_to_bl31(WDT_ENABLE, 0); - wdt_send_cmd_to_bl31(WDT_PING, 0); - - return 0; -} - -static int meson_a1_wdt_stop(struct udevice *dev) -{ - wdt_send_cmd_to_bl31(WDT_DISABLE, 0); - - return 0; -} - -static int meson_a1_wdt_expire_now(struct udevice *dev, ulong flags) -{ - meson_a1_wdt_start(dev, 1, flags); - - return 0; -} - -static int meson_a1_wdt_reset(struct udevice *dev) -{ - wdt_send_cmd_to_bl31(WDT_PING, 0); - - return 0; -} - -static struct wdt_ops meson_a1_ops = { - .start = meson_a1_wdt_start, - .stop = meson_a1_wdt_stop, - .expire_now = meson_a1_wdt_expire_now, - .reset = meson_a1_wdt_reset, -}; - -static struct meson_wdt_data meson_a1_data = { - .ops = &meson_a1_ops, -}; - -/************ common code *******************/ -static int meson_wdt_ofdata_to_platdata(struct udevice *dev) -{ - struct meson_wdt_priv *priv; - - assert(dev); - priv = dev_get_priv(dev); - priv->regs = devfdt_get_addr_ptr(dev); - if (IS_ERR(priv->regs)) - return PTR_ERR(priv->regs); - - return 0; -} - -static int meson_wdt_probe(struct udevice *dev) -{ - struct meson_wdt_data* priv; - struct driver* dri; - - priv =(struct meson_wdt_data *)dev_get_driver_data(dev); - dri = (struct driver*)dev->driver; - dri->ops = priv->ops; - if (device_is_compatible(dev,"amlogic,meson-gxbb-wdt")) - meson_gxbb_wdt_probe(dev); - - return 0; -} - -static const struct udevice_id meson_wdt_ids[] = -{ - { - .compatible = "amlogic,meson-gxbb-wdt", - .data = (ulong)&meson_gxbb_data, - }, - { - .compatible = "amlogic,meson-a1-wdt", - .data = (ulong)&meson_a1_data, - }, - {} -}; - -U_BOOT_DRIVER(meson_wdt) = { - .name = "meson_wdt", - .id = UCLASS_WDT, - .of_match = meson_wdt_ids, - .probe = meson_wdt_probe, - .priv_auto_alloc_size = sizeof(struct meson_wdt_priv), - .ofdata_to_platdata = meson_wdt_ofdata_to_platdata, -}; +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <wdt.h> +#include <asm/io.h> +#include <linux/io.h> +#include <clk.h> +#include <asm/arch/bl31_apis.h> + +#define MESON_WDT_CTRL_REG 0x0 +#define MESON_WDT_TCNT_REG 0x8 +#define MESON_WDT_RSET_REG 0xc + +#define MESON_WDT_CTRL_CLKDIV_EN BIT(25) +#define MESON_WDT_CTRL_CLK_EN BIT(24) +#define MESON_WDT_CTRL_EN BIT(18) +#define MESON_WDT_CTRL_DIV_MASK (BIT(18) - 1) +#define MESON_WDT_TCNT_SETUP_MASK (BIT(16) - 1) +#define MESON_WDT_TCNT_CNT_SHIFT (16) + +#define WDT_DISABLE 1 +#define WDT_ENABLE 2 +#define WDT_PING 3 +#define WDT_INIT 4 +#define WDT_RESETNOW 5 +#define WDT_SETTIMEOUT 6 +#define WDT_OPS 0x82000086 + +#define DEFAULT_TIMEOUT 1 /* second */ + +struct meson_wdt_priv { + void __iomem *regs; +}; + +struct meson_wdt_data { + unsigned char rst_shift; + struct wdt_ops *ops; +}; + +/***************** gxbb ***********************/ +static int meson_gxbb_wdt_reset(struct udevice *dev) +{ + struct meson_wdt_priv *priv; + + assert(dev); + priv = dev_get_priv(dev); + writel(0, priv->regs + MESON_WDT_RSET_REG); + + return 0; +} + +static int meson_gxbb_wdt_set_timeout(struct udevice *dev, u64 timeout_ms) +{ + struct meson_wdt_priv *priv; + unsigned long tcnt = timeout_ms; + + assert(dev); + priv = dev_get_priv(dev); + if (tcnt > MESON_WDT_TCNT_SETUP_MASK) + tcnt = MESON_WDT_TCNT_SETUP_MASK; + meson_gxbb_wdt_reset(dev); + writel(tcnt, priv->regs + MESON_WDT_TCNT_REG); + + return 0; +} + +static int meson_gxbb_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct meson_wdt_priv *priv; + + assert(dev); + priv = dev_get_priv(dev); + meson_gxbb_wdt_set_timeout(dev, timeout_ms); + writel(readl(priv->regs + MESON_WDT_CTRL_REG) | MESON_WDT_CTRL_EN, + priv->regs + MESON_WDT_CTRL_REG); + + return 0; +} + +static int meson_gxbb_wdt_stop(struct udevice *dev) +{ + struct meson_wdt_priv *priv; + + assert(dev); + priv = dev_get_priv(dev); + writel(readl(priv->regs + MESON_WDT_CTRL_REG) & ~MESON_WDT_CTRL_EN, + priv->regs + MESON_WDT_CTRL_REG); + + return 0; +} + +static int meson_gxbb_wdt_expire_now(struct udevice *dev, ulong flags) +{ + meson_gxbb_wdt_start(dev, 1, flags); + + return 0; +} + +static int meson_gxbb_wdt_probe(struct udevice *dev) +{ + struct meson_wdt_priv *priv; + struct meson_wdt_data *data; + + fdt_addr_t addr; + fdt_size_t size; + struct clk w_clk; + unsigned int rate = 0; + int ret; + + assert(dev); + priv = dev_get_priv(dev); + data = (struct meson_wdt_data *)dev_get_driver_data(dev); + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + priv->regs = (void __iomem *)addr; + ret = clk_get_by_name(dev, "wdt-clk", &w_clk); + if (ret < 0) { + printf("Failed to get wdt-clk.\n"); + return ret; + } + rate = clk_get_rate(&w_clk); + if (rate < 0) { + printf("Failed to get wdt-clk rate.\n"); + return ret; + } + writel(((rate / 1000) & MESON_WDT_CTRL_DIV_MASK) | + BIT(data->rst_shift) | + MESON_WDT_CTRL_CLK_EN | + MESON_WDT_CTRL_CLKDIV_EN, priv->regs + MESON_WDT_CTRL_REG); + meson_gxbb_wdt_set_timeout(dev, DEFAULT_TIMEOUT * 1000); + meson_gxbb_wdt_stop(dev); + + return 0; +} + +static struct wdt_ops meson_gxbb_wdt_ops = { + .start = meson_gxbb_wdt_start, + .stop = meson_gxbb_wdt_stop, + .expire_now = meson_gxbb_wdt_expire_now, + .reset = meson_gxbb_wdt_reset, +}; + +static struct meson_wdt_data meson_gxbb_data = { + .rst_shift = 21, + .ops = &meson_gxbb_wdt_ops, +}; + +static struct meson_wdt_data meson_sc2_data = { + .rst_shift = 22, + .ops = &meson_gxbb_wdt_ops, +}; +/**************** a1 **********************/ +void __attribute__((weak)) wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value) +{ + +} +static int meson_a1_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + wdt_send_cmd_to_bl31(WDT_INIT, timeout_ms); + wdt_send_cmd_to_bl31(WDT_ENABLE, 0); + wdt_send_cmd_to_bl31(WDT_PING, 0); + + return 0; +} + +static int meson_a1_wdt_stop(struct udevice *dev) +{ + wdt_send_cmd_to_bl31(WDT_DISABLE, 0); + + return 0; +} + +static int meson_a1_wdt_expire_now(struct udevice *dev, ulong flags) +{ + meson_a1_wdt_start(dev, 1, flags); + + return 0; +} + +static int meson_a1_wdt_reset(struct udevice *dev) +{ + wdt_send_cmd_to_bl31(WDT_PING, 0); + + return 0; +} + +static struct wdt_ops meson_a1_ops = { + .start = meson_a1_wdt_start, + .stop = meson_a1_wdt_stop, + .expire_now = meson_a1_wdt_expire_now, + .reset = meson_a1_wdt_reset, +}; + +static struct meson_wdt_data meson_a1_data = { + .ops = &meson_a1_ops, +}; + +/************ common code *******************/ +static int meson_wdt_ofdata_to_platdata(struct udevice *dev) +{ + struct meson_wdt_priv *priv; + + assert(dev); + priv = dev_get_priv(dev); + priv->regs = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + return 0; +} + +static int meson_wdt_probe(struct udevice *dev) +{ + struct meson_wdt_data* priv; + struct driver* dri; + + priv =(struct meson_wdt_data *)dev_get_driver_data(dev); + dri = (struct driver*)dev->driver; + dri->ops = priv->ops; + if (device_is_compatible(dev,"amlogic,meson-gxbb-wdt") || + device_is_compatible(dev,"amlogic,meson-sc2-wdt")) + meson_gxbb_wdt_probe(dev); + + return 0; +} + +static const struct udevice_id meson_wdt_ids[] = +{ + { + .compatible = "amlogic,meson-gxbb-wdt", + .data = (ulong)&meson_gxbb_data, + }, + { + .compatible = "amlogic,meson-a1-wdt", + .data = (ulong)&meson_a1_data, + }, + { + .compatible = "amlogic,meson-sc2-wdt", + .data = (ulong)&meson_sc2_data, + }, + {} +}; + +U_BOOT_DRIVER(meson_wdt) = { + .name = "meson_wdt", + .id = UCLASS_WDT, + .of_match = meson_wdt_ids, + .probe = meson_wdt_probe, + .priv_auto_alloc_size = sizeof(struct meson_wdt_priv), + .ofdata_to_platdata = meson_wdt_ofdata_to_platdata, +};
diff --git a/env/storage.c b/env/storage.c index 4c0a091..70eff85 100644 --- a/env/storage.c +++ b/env/storage.c
@@ -19,7 +19,7 @@ } ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); - if (env_export(buf)) { + if (env_export((env_t *)buf)) { printf("env_storage: export failed\n"); return -EINVAL; }
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index f01816f..7f83d49 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile
@@ -43,6 +43,8 @@ # We don't want gcc reordering functions if possible. This ensures that an # application's entry point will be the first function in the application's # source file. +ccflags-y := $(filter-out $(STACK_CFLAGS),$(ccflags-y)) +ccflags-y += $(call cc-option,-fno-stack-protector) ccflags-y += $(call cc-option,-fno-toplevel-reorder) LDFLAGS_STANDALONE += -Ttext $(CONFIG_STANDALONE_LOAD_ADDR)
diff --git a/fip/c2/aml_ddr.fw b/fip/c2/aml_ddr.fw new file mode 100644 index 0000000..32b9d3c --- /dev/null +++ b/fip/c2/aml_ddr.fw Binary files differ
diff --git a/fip/c2/aml_encrypt_c2 b/fip/c2/aml_encrypt_c2 new file mode 100755 index 0000000..7dbac71 --- /dev/null +++ b/fip/c2/aml_encrypt_c2 Binary files differ
diff --git a/fip/c2/bl2.bin b/fip/c2/bl2.bin new file mode 100755 index 0000000..91bf131 --- /dev/null +++ b/fip/c2/bl2.bin Binary files differ
diff --git a/fip/c2/bl31.img b/fip/c2/bl31.img new file mode 100644 index 0000000..1c42a7c --- /dev/null +++ b/fip/c2/bl31.img Binary files differ
diff --git a/fip/c2/bl32.img b/fip/c2/bl32.img new file mode 100644 index 0000000..467e425 --- /dev/null +++ b/fip/c2/bl32.img Binary files differ
diff --git a/fip/c2/build.sh b/fip/c2/build.sh new file mode 100644 index 0000000..4f90eee --- /dev/null +++ b/fip/c2/build.sh
@@ -0,0 +1,209 @@ +#!/bin/bash + +# include uboot pre-build macros +#declare CONFIG_FILE=("${buildtree}/.config") +#declare AUTOCFG_FILE=("${buildtree}/include/autoconf.mk") + +function init_vari() { + #source ${CONFIG_FILE} &> /dev/null # ignore warning/error + #source ${AUTOCFG_FILE} &> /dev/null # ignore warning/error + + AML_BL2_NAME="bl2.bin" + AML_KEY_BLOB_NANE="aml-user-key.sig" + + if [ "y" == "${CONFIG_AML_SECURE_BOOT_V3}" ]; then + V3_PROCESS_FLAG="--level v3" + fi + + if [ "y" == "${CONFIG_AML_CRYPTO_AES}" ]; then + BOOT_SIG_FLAG="--aeskey enable" + EFUSE_GEN_FLAG="--aeskey enable" + fi + + if [ "y" == "${CONFIG_AML_EFUSE_GEN_AES_ONLY}" ]; then + EFUSE_GEN_FLAG="--aeskey only" + fi + + if [ "y" == "${CONFIG_AML_BL33_COMPRESS_ENABLE}" ]; then + BL33_COMPRESS_FLAG="--compress lz4" + fi + + if [ "y" == "${CONFIG_FIP_IMG_SUPPORT}" ]; then + BL3X_SUFFIX="img" + fi +} + +function fix_blx() { + #bl2 file size 41K, bl21 file size 3K (file size not equal runtime size) + #total 44K + #after encrypt process, bl2 add 4K header, cut off 4K tail + + #bl2 file size 56K, acs file size 4K + #total 60K + #after encrypt process, bl2 add 4K header, cut off 4K tail + + #bl2 limit 56K + #acs limit 4K, but encrypt tool need 64K bl2.bin, so fix to 8192byte. + + declare blx_bin_limit=0 + declare blx01_bin_limit=0 + declare -i blx_size=0 + declare -i zero_size=0 + + #$7:name flag + if [ "$7" = "bl2" ]; then + blx_bin_limit=57344 + blx01_bin_limit=4096 + else + echo "blx_fix name flag not supported!" + exit 1 + fi + + # blx_size: blx.bin size, zero_size: fill with zeros + blx_size=`du -b $1 | awk '{print int($1)}'` + if [ $blx_size -gt $blx_bin_limit ]; then + echo "Error: $7 ($1) too big. $blx_size > $blx_bin_limit" + exit 1 + fi + + zero_size=$blx_bin_limit-$blx_size + dd if=/dev/zero of=$2 bs=1 count=$zero_size + cat $1 $2 > $3 + rm $2 + + blx_size=`du -b $4 | awk '{print int($1)}'` + zero_size=$blx01_bin_limit-$blx_size + dd if=/dev/zero of=$2 bs=1 count=$zero_size + cat $4 $2 > $5 + + cat $3 $5 > $6 + + rm $2 +} + +function cleanup() { + rm -f ${BUILD_PATH}/bl*.enc ${BUILD_PATH}/bl2*.sig +} + +function encrypt_step() { + dbg "encrypt: $@" + local ret=0 + ./${FIP_FOLDER}${CUR_SOC}/aml_encrypt_${CUR_SOC} $@ + ret=$? + if [ 0 != $ret ]; then + echo "Err! aml_encrypt_${CUR_SOC} return $ret" + exit $ret + fi +} + +function encrypt() { + #u-boot.bin generate + if [ "y" == "${CONFIG_AML_SECURE_BOOT_V3}" ]; then + encrypt_step --bl3sig --input ${BUILD_PATH}/bl31.${BL3X_SUFFIX} --output ${BUILD_PATH}/bl31.${BL3X_SUFFIX}.enc ${V3_PROCESS_FLAG} --type bl31 + if [ "${FIP_BL32}" == "${BUILD_PATH}/bl32.${BL3X_SUFFIX}" ]; then + encrypt_step --bl3sig --input ${BUILD_PATH}/bl32.${BL3X_SUFFIX} --output ${BUILD_PATH}/bl32.${BL3X_SUFFIX}.enc ${V3_PROCESS_FLAG} --type bl32 + fi + #encrypt_step --bl3sig --input ${BUILD_PATH}/bl33.bin ${BL33_COMPRESS_FLAG} --output ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} --type bl33 + encrypt_step --bl3sig --input ${BUILD_PATH}/bl33.bin --output ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} --type bl33 + fi + + encrypt_step --bl2sig --input ${BUILD_PATH}/bl2_new.bin --output ${BUILD_PATH}/bl2.n.bin.sig + + encrypt_step --bootmk --output ${BUILD_PATH}/u-boot.bin \ + --bl2 ${BUILD_PATH}/bl2.n.bin.sig \ + --bl31 ${BUILD_PATH}/bl31.${BL3X_SUFFIX}.enc ${FIP_BL32_PROCESS} --bl33 ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} \ + --ddrfw1 ./${FIP_FOLDER}${CUR_SOC}/${DDR_FW_NAME} + + if [ "y" == "${CONFIG_AML_CRYPTO_UBOOT}" ]; then + #encrypt_step --efsgen --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} \ + # --output ${BUILD_PATH}/u-boot.bin.encrypt.efuse ${V3_PROCESS_FLAG} ${EFUSE_GEN_FLAG} + encrypt_step --bootsig --input ${BUILD_PATH}/u-boot.bin --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} \ + ${BOOT_SIG_FLAG} --output ${BUILD_PATH}/u-boot.bin.encrypt ${V3_PROCESS_FLAG} + fi + + if [ "y" == "${CONFIG_AML_CRYPTO_IMG}" ]; then + encrypt_step --imgsig --input ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/boot.img --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} --output ${BUILD_PATH}/boot.img.encrypt + fi + + return +} + +function build_fip() { + + # acs_tool process ddr timing and configurable parameters + #python ${FIP_FOLDER}/acs_tool.pyc ${BUILD_PATH}/${AML_BL2_NAME} ${BUILD_PATH}/bl2_acs.bin ${BUILD_PATH}/acs.bin 0 + + # fix bl2/bl21 + fix_blx \ + ${BUILD_PATH}/bl2.bin \ + ${BUILD_PATH}/zero_tmp \ + ${BUILD_PATH}/bl2_zero.bin \ + ${BUILD_PATH}/acs.bin \ + ${BUILD_PATH}/bl21_zero.bin \ + ${BUILD_PATH}/bl2_new.bin \ + bl2 + + if [ "y" == "${CONFIG_NEED_BL32}" ]; then + FIP_BL32="`find ${BUILD_PATH} -name "bl32.${BL3X_SUFFIX}"`" + if [ "${FIP_BL32}" == "${BUILD_PATH}/bl32.${BL3X_SUFFIX}" ]; then + FIP_BL32_PROCESS=" --bl32 ${BUILD_PATH}/bl32.${BL3X_SUFFIX}.enc" + fi + fi + + return +} + +function copy_other_soc() { + cp ${BL33_BUILD_FOLDER}${BOARD_DIR}/firmware/acs.bin ${BUILD_PATH} -f + ./${FIP_FOLDER}/parse ${BUILD_PATH}/acs.bin +} + +function package() { + # BUILD_PATH without "/" + x=$((${#BUILD_PATH}-1)) + if [ "\\" == "${BUILD_PATH:$x:1}" ] || [ "/" == "${BUILD_PATH:$x:1}" ]; then + BUILD_PATH=${BUILD_PATH:0:$x} + fi + + init_vari $@ + build_fip $@ + if [ 1 -eq ${CONFIG_DDR_FW} ]; then + echo -n "Copy ddr fw..." + cp ${BLX_SRC_FOLDER}/${DDR_FW_NAME} ${FIP_FOLDER}/${CUR_SOC} -f + if [ 0 != $? ]; then + echo " failed!" + else + echo " ok!" + fi + fi + + if [ "y" == "${CONFIG_AML_SIGNED_UBOOT}" ]; then + + #mv -f ${BUILD_PATH}/bl33.bin ${BUILD_PATH}/bl33.bin.org + #encrypt_step --bl3sig --input ${BUILD_PATH}/bl33.bin.org --output ${BUILD_PATH}/bl33.bin.org.lz4 --compress lz4 --level v3 --type bl33 + #get LZ4 format bl33 image from bl33.bin.enc with offset 0x720 + #dd if=${BUILD_PATH}/bl33.bin.org.lz4 of=${BUILD_PATH}/bl33.bin bs=1 skip=1824 >& /dev/null + + list_pack="${BUILD_PATH}/bl2_new.bin ${BUILD_PATH}/bl31.img ${BUILD_PATH}/bl32.img ${BUILD_PATH}/bl33.bin" + list_pack="$list_pack ${FIP_FOLDER}/${CUR_SOC}/*.fw" + u_pack=${BUILD_FOLDER}/"$(basename ${BOARD_DIR})"-u-boot.aml.zip + zip -j $u_pack ${list_pack} >& /dev/null + + if [ "y" == "${CONFIG_AML_CRYPTO_AES}" ]; then + encryption_option= + else + encryption_option="-n" + fi + + ${FIP_FOLDER}/stool/sign.sh -s ${CUR_SOC} -z $u_pack -o ${BUILD_FOLDER} -r ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/aml-key -a ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/aml-key $encryption_option + + if [ "y" == "${CONFIG_AML_CRYPTO_IMG}" ]; then + ${FIP_FOLDER}/stool/sign.sh -s ${CUR_SOC} -p ${UBOOT_SRC_FOLDER}/${BOARD_DIR} -o ${BUILD_FOLDER} -r ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/aml-key -a ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/aml-key $encryption_option + fi + else + encrypt $@ + fi + #copy_file + #cleanup + echo "Bootloader build done!" +}
diff --git a/fip/c2/variable_soc.sh b/fip/c2/variable_soc.sh new file mode 100644 index 0000000..fcd29e0 --- /dev/null +++ b/fip/c2/variable_soc.sh
@@ -0,0 +1,37 @@ +#!/bin/bash + +# static +declare -a BLX_NAME=("bl2" "bl31" "bl32") + +declare -a BLX_SRC_FOLDER=("bl2/src" "bl31_1.3/src" "bl32/src" "bl33") +declare -a BLX_BIN_FOLDER=("bl2/bin" "bl31_1.3/bin" "bl32/bin") +declare -a BLX_BIN_NAME=("bl2.bin" "bl31.bin" "bl32.bin") +declare -a BLX_IMG_NAME=("NULL" "bl31.img" "bl32.img") +declare -a BLX_NEEDFUL=("true" "true" "false") + +declare -a BLX_SRC_GIT=("bootloader/spl" "ARM-software/arm-trusted-firmware" "OP-TEE/optee_os" "uboot") +declare -a BLX_BIN_GIT=("firmware/bin/bl2" "firmware/bin/bl31" "firmware/bin/bl32") + +# blx priority. null: default, source: src code, others: bin path +declare -a BIN_PATH=("null" "null" "null") + +# variables +declare -a CUR_REV # current version of each blx +declare -a BLX_READY=("false", "false", "false") # blx build/get flag + +# package variables +declare BL33_COMPRESS_FLAG="" +declare BL3X_SUFFIX="bin" +declare V3_PROCESS_FLAG="" +declare AML_BL2_NAME="" +declare AML_KEY_BLOB_NANE="" +declare FIP_BL32_PROCESS="" +declare BOOT_SIG_FLAG="" +declare EFUSE_GEN_FLAG="" + +BUILD_PATH=${FIP_BUILD_FOLDER} + +CONFIG_DDR_FW=0 +DDR_FW_NAME="aml_ddr.fw" + +CONFIG_DDR_PARSE=1
diff --git a/include/adc.h b/include/adc.h index c845e1e..6eca7ed 100644 --- a/include/adc.h +++ b/include/adc.h
@@ -15,14 +15,17 @@ #ifdef CONFIG_SARADC_MESON -#define ADC_CAPACITY_COMMON 0x00000000 #define ADC_CAPACITY_AVERAGE 0x00000001 #define ADC_CAPACITY_HIGH_PRECISION_VREF 0x00000002 +#define ADC_CAPACITY_DECIM_FILTER 0x00000004 -#define ADC_MODE_STARDAND ADC_CAPACITY_COMMON #define ADC_MODE_AVERAGE ADC_CAPACITY_AVERAGE #define ADC_MODE_HIGH_PRECISION (ADC_CAPACITY_AVERAGE | \ ADC_CAPACITY_HIGH_PRECISION_VREF) +/* The following modes are only used in C2 */ +#define ADC_MODE_HIGH_RESOLUTION (ADC_CAPACITY_DECIM_FILTER | \ + ADC_CAPACITY_HIGH_PRECISION_VREF) +#define ADC_MODE_DECIM_FILTER ADC_CAPACITY_DECIM_FILTER #endif /**
diff --git a/include/amlogic/aml_mtd.h b/include/amlogic/aml_mtd.h index 22891ab..1b9ef12 100644 --- a/include/amlogic/aml_mtd.h +++ b/include/amlogic/aml_mtd.h
@@ -11,15 +11,24 @@ #define CONFIG_DISCRETE_BOOTLOADER #endif -#if defined(CONFIG_SPI_NAND) && !defined(CONFIG_DISCRETE_BOOTLOADER) +/* spinor adds discrete modem base on advanced burning */ +#ifdef CONFIG_SPI_FLASH_AML_ADVANCED +#define CONFIG_DISCRETE_BOOTLOADER +#endif + +#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)) && !defined(CONFIG_DISCRETE_BOOTLOADER) #error SPI NAND only support discrete boot mode! #endif #ifdef CONFIG_DISCRETE_BOOTLOADER #define CONFIG_BL2_COPY_NUM 8 #define CONFIG_TPL_SIZE_PER_COPY 0x200000 +#ifdef CONFIG_SPI_FLASH +#define CONFIG_TPL_COPY_NUM 1 +#else #define CONFIG_TPL_COPY_NUM 4 -#endif/* CONFIG_DISCRETE_BOOTLOADER */ +#endif +#endif /* Mapping conversion between phyAddr and logicAddr,do not open it temporarily */ //#define CONFIG_MTD_LOGIC_MAP @@ -27,6 +36,10 @@ #define BOOT_LOADER "bootloader" #define BOOT_BL2 "bl2" #define BOOT_SPL "spl" +#define BOOT_BL2E "bl2e" +#define BOOT_BL2X "bl2x" +#define BOOT_DDRFIP "ddrfip" +#define BOOT_DEVFIP "devfip" #define BOOT_TPL "tpl" #define BOOT_FIP "fip" #define MAX_MTD_CNT 2
diff --git a/include/amlogic/amlkey_if.h b/include/amlogic/amlkey_if.h index fb8fbd1..948dfc8 100644 --- a/include/amlogic/amlkey_if.h +++ b/include/amlogic/amlkey_if.h
@@ -7,33 +7,73 @@ #define __AMLKEY_IF_H__ #define AMLKEY_NAME_LEN_MAX (80) + +struct amlkey_if { + int32_t (*init)(uint8_t *seed, uint32_t len, int encrypt_type); + int32_t (*exsit)(const uint8_t *name); + ssize_t (*size)(const uint8_t *name); + uint32_t (*get_attr)(const uint8_t *name); + ssize_t (*read)(const uint8_t *name, uint8_t *buffer, uint32_t len); + ssize_t (*write)(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr); + int32_t (*hash)(const uint8_t *name, uint8_t *hash); +}; + +extern struct amlkey_if *amlkey_if; + +static inline uint32_t amlkey_get_attr(const uint8_t *name) +{ + return amlkey_if->get_attr(name); +} + +int amlkey_if_init(const void* dt_addr); + //1.init -int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type); +static inline int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type) +{ + return amlkey_if->init(seed, len, encrypt_type); +} //2. query if the key already programmed, exsit 1, non 0 -int32_t amlkey_isexsit(const uint8_t * name); +static inline int32_t amlkey_isexsit(const uint8_t * name) +{ + return amlkey_if->exsit(name); +} //3. query attr, key must exsit before those functions were called. //3.1 whether the prgrammed key is secure, secure 1, non 0 int32_t amlkey_issecure(const uint8_t * name); + //3.2 whether the prgrammed key is encrypt, encrypt 1, non 0 int32_t amlkey_isencrypt(const uint8_t * name); //4. actual bytes of key value -ssize_t amlkey_size(const uint8_t *name); +static inline ssize_t amlkey_size(const uint8_t *name) +{ + return amlkey_if->size(name); +} //5. read non-secure key in bytes, return byets readback actully. -ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) ; +static inline ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) +{ + return amlkey_if->read(name, buffer, len); +} //6.write key with attribute in bytes , return byets readback actully //attr: bit0: secure/non-secure; // bit8: encrypt/non-encrypt #define UNIFYKEY_ATTR_SECURE_MASK (1<<0) #define UNIFYKEY_ATTR_ENCRYPT_MASK (1<<8) -ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr); +static inline ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, + uint32_t attr) +{ + return amlkey_if->write(name, buffer, len, attr); +} //7. get the hash value of programmed secure key | 32bytes length, sha256 -int32_t amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash); +static inline int32_t amlkey_hash_4_secure(const uint8_t *name, uint8_t *hash) +{ + return amlkey_if->hash(name, hash); +} #endif// #ifndef __AMLKEY_IF_H__
diff --git a/include/amlogic/anti-rollback.h b/include/amlogic/anti-rollback.h new file mode 100644 index 0000000..93a9168 --- /dev/null +++ b/include/amlogic/anti-rollback.h
@@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __ANTI_ROLLBACK_ +#define __ANTI_ROLLBACK_ + +#include <linux/types.h> + +bool check_antirollback(uint32_t kernel_version); + +bool set_avb_antirollback(uint32_t index, uint32_t version); +bool get_avb_antirollback(uint32_t index, uint32_t* version); +bool get_avb_lock_state(uint32_t* lock_state); +bool avb_lock(void); +bool avb_unlock(void); + +#endif
diff --git a/include/amlogic/auge_sound.h b/include/amlogic/auge_sound.h new file mode 100644 index 0000000..8368ed5 --- /dev/null +++ b/include/amlogic/auge_sound.h
@@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __AUGE_SOUND_H__ +#define __AUGE_SOUND_H__ + +/* auge audio register is defined in asm/arch/secure_apb.h */ + +int aml_audio_init(void); + +#endif
diff --git a/include/amlogic/cpu_id.h b/include/amlogic/cpu_id.h index 3273c10..5818ef3 100644 --- a/include/amlogic/cpu_id.h +++ b/include/amlogic/cpu_id.h
@@ -27,6 +27,9 @@ #define MESON_CPU_MAJOR_ID_TL1 0x2E #define MESON_CPU_MAJOR_ID_TM2 0x2F #define MESON_CPU_MAJOR_ID_C1 0x30 +#define MESON_CPU_MAJOR_ID_SC2 0x32 +#define MESON_CPU_MAJOR_ID_C2 0x33 + #define MESON_CPU_PACKAGE_ID_905D 0X00 #define MESON_CPU_PACKAGE_ID_905M 0x20
diff --git a/include/amlogic/cv_data.h b/include/amlogic/cv_data.h index f81aa57..883e2cf 100644 --- a/include/amlogic/cv_data.h +++ b/include/amlogic/cv_data.h
@@ -17,9 +17,6 @@ #define RTOS_STATUS_BASE_ADDR 0xfff62000 #define RTOS_STATUS_MAGIC 0xABBACDDC -#define STATUS_FOR_UBOOT_BASE_ADDR (0xFFF62400) -#define STATUS_FOR_UBOOT_SIZE_BYTES (256) - struct CvRodata { u16 size; u8 led[50]; @@ -35,8 +32,6 @@ u8 camera_vflip; u8 led_mode; u8 audio_enable; - u8 low_power_mode; - u32 reserved; u8 crc8; } __packed; @@ -44,7 +39,6 @@ u8 is_exposure_valid; u8 ir_mode_enabled; u8 ir_power_setting; - u8 max_ir_power_in_percent; u32 last_optimal_exposure_value; u32 last_optimal_short_expo_lines; u32 last_optimal_gain; @@ -57,20 +51,13 @@ struct RtosStatus { u32 magic; u8 corrupted; - u32 wakeup_reasons; + u16 wakeup_reasons; u8 day_night; u32 first_frame_te; struct CameraPara camera_data; u8 crc8; } __packed; -struct RtosStatusForUboot { - uint32_t magic; - uint32_t wakeup_reasons; - uint8_t crc8; -} __attribute__((packed)); - - #ifdef __cplusplus } #endif
diff --git a/include/amlogic/fb.h b/include/amlogic/fb.h index feddfeb..c3b31db 100644 --- a/include/amlogic/fb.h +++ b/include/amlogic/fb.h
@@ -293,6 +293,13 @@ #define VESA_HSYNC_SUSPEND 2 #define VESA_POWERDOWN 3 +#define CANVAS_ALIGNED(x) (((x) + 63) & ~63) + +enum osd_index_e { + OSD1 = 0, + OSD2, + VIU2_OSD1 +}; enum { /* screen: unblanked, hsync: on, vsync: on */
diff --git a/include/amlogic/jtag.h b/include/amlogic/jtag.h index 83af4c9..ace64e8 100644 --- a/include/amlogic/jtag.h +++ b/include/amlogic/jtag.h
@@ -25,6 +25,9 @@ #define SP 3 /* m4 */ #define DSPA 4 /* dsp-a */ #define DSPB 5 /* dsp-b */ +#define DIF 6 /* dif */ +#define AOCPU 7 /* aocpu */ +#define AUCPU 8 /* aucpu */ /* * bitmap for jtag select ID:
diff --git a/include/amlogic/led_aw2015.h b/include/amlogic/led_aw2015.h new file mode 100644 index 0000000..ae2fbeb --- /dev/null +++ b/include/amlogic/led_aw2015.h
@@ -0,0 +1,79 @@ +#ifndef AMLOGIC_SDK_SPENCER_U_BOOT_INCLUDE_AMLOGIC_LED_AW2015_H_ +#define AMLOGIC_SDK_SPENCER_U_BOOT_INCLUDE_AMLOGIC_LED_AW2015_H_ + +#include <common.h> + +#ifdef CONFIG_SYS_I2C_MESON +#include <i2c.h> +#include <dt-bindings/i2c/meson-i2c.h> +#include <fs.h> +#endif + +#define N_CAL_SETTINGS 6 +#define BUS_NUM 4 +#define I2C_LED_REG 0x64 +#define PAT_FIELD_NUMBER 5 + +#define AW2015_REG_RSTIDR 0x00 +#define AW2015_REG_GCR 0x01 +#define AW2015_REG_IMAX 0x03 +#define AW2015_REG_LCFG1 0x04 +#define AW2015_REG_LEDEN 0x07 +#define AW2015_REG_LEDCTR 0x08 +#define AW2015_REG_PATRUN 0x09 +#define AW2015_REG_ILED1 0x10 +#define AW2015_REG_PWM1 0x1C +#define AW2015_REG_PAT1_T1 0x30 +#define AW2015_REG_PAT1_T2 0x31 +#define AW2015_REG_PAT1_T4 0x33 + +#define AW2015_LED_RSTIDR_MASK 0xff +#define AW2015_LED_RSTIDR_RESET 0x55 + +#define AW2015_LED_LEDMD_MASK 0b1 +#define AW2015_LED_ON_MODE 0x00 +#define AW2015_LED_BLINK_MODE 0x01 + +#define AW2015_LED_CHIPEN_MASK 0b1 +#define AW2015_LED_CHIP_ENABLE 0x01 + +#define AW2015_LED_CHARGE_DISABLE_MASK 0b10 +#define AW2015_LED_CHARGE_DISABLE 0x02 + +#define AW2015_LED_IMX_MASK 0b11 +#define AW2015_LED_12_25mA 0x02 +#define AW2015_LED_25_5mA 0x03 + +#define AW2015_LED_PWMLOG_MASK 0b11 +#define AW2015_LED_PWMLOG_LEANER 0b11 + +#define AW2015_LED_LEDEN_MASK 0b111 +#define AW2015_LED_LEDEN_TURN_ON_ALL 0b111 + +#define AW2015_LED_PWM_MASK 0xff + +#define AW2015_LED_ILED_MASK 0xff + +#define AW2015_LED_PAT_TRISE_MASK 0xf0 + +#define AW2015_LED_PAT_TFALL_MASK 0xf0 + +#define AW2015_LED_PAT_TON_MASK 0x0f +#define AW2015_LED_PAT_ON_1SEC 0b0110 + +#define AW2015_LED_PAT_TOFF_MASK 0x0f +#define AW2015_LED_PAT_OFF_1SEC 0b0110 + +#define AW2015_LED_PAT_CTR_MASK 0x80 +#define AW2015_LED_PAT_CTR_INF_LOOP 0x0 + +#define AW2015_LED_PATRUN_MASK 0b111 +#define AW2015_LED_PATRUN_START_ALL 0b111 + +#define USB_AML_BC_OFFSET 0xA0 + + +enum LED_ANIMATION { WHITE, YELLOW, BLINK_YELLOW }; +void sys_led_init(enum LED_ANIMATION led_animation); + +#endif // AMLOGIC_SDK_SPENCER_U_BOOT_INCLUDE_AMLOGIC_LED_AW2015_H_
diff --git a/include/amlogic/leds-aw2026.h b/include/amlogic/leds-aw2026.h new file mode 100644 index 0000000..a79a005 --- /dev/null +++ b/include/amlogic/leds-aw2026.h
@@ -0,0 +1,75 @@ +#ifndef LEDS_AW2026_H_ +#define LEDS_AW2026_H_ + +#include <common.h> + +#ifdef CONFIG_SYS_I2C_MESON +#include <i2c.h> +#include <dt-bindings/i2c/meson-i2c.h> +#include <fs.h> +#endif + +#define N_CAL_SETTINGS 6 +#define I2C_BUS_NUM 3 +#define I2C_LED_REG 0x64 +#define PAT_FIELD_NUMBER 5 + +#define AW2026_REG_RSTIDR 0x00 +#define AW2026_REG_GCR 0x01 +#define AW2026_REG_IMAX 0x03 +#define AW2026_REG_LCFG1 0x04 +#define AW2026_REG_LEDEN 0x07 +#define AW2026_REG_LEDCTR 0x08 +#define AW2026_REG_PATRUN 0x09 +#define AW2026_REG_ILED1 0x10 +#define AW2026_REG_PWM1 0x1C +#define AW2026_REG_PAT1_T1 0x30 +#define AW2026_REG_PAT1_T2 0x31 +#define AW2026_REG_PAT1_T4 0x33 + +#define AW2026_LED_RSTIDR_MASK 0xff +#define AW2026_LED_RSTIDR_RESET 0x55 + +#define AW2026_LED_LEDMD_MASK 0b1 +#define AW2026_LED_ON_MODE 0x00 +#define AW2026_LED_BLINK_MODE 0x01 + +#define AW2026_LED_CHIPEN_MASK 0b1 +#define AW2026_LED_CHIP_ENABLE 0x01 + +#define AW2026_LED_IMX_MASK 0b11 +#define AW2026_LED_3_1875mA 0x00 +#define AW2026_LED_6_375mA 0x01 +#define AW2026_LED_12_75mA 0x02 +#define AW2026_LED_25_5mA 0x03 + +#define AW2026_LED_PWMLOG_MASK 0b11 +#define AW2026_LED_PWMLOG_LEANER 0b11 + +#define AW2026_LED_LEDEN_MASK 0b111 +#define AW2026_LED_LEDEN_TURN_ON_ALL 0b111 + +#define AW2026_LED_PWM_MASK 0xff + +#define AW2026_LED_ILED_MASK 0xff + +#define AW2026_LED_PAT_TRISE_MASK 0xf0 + +#define AW2026_LED_PAT_TFALL_MASK 0xf0 + +#define AW2026_LED_PAT_TON_MASK 0x0f +#define AW2026_LED_PAT_ON_1SEC 0b0110 + +#define AW2026_LED_PAT_TOFF_MASK 0x0f +#define AW2026_LED_PAT_OFF_1SEC 0b0110 + +#define AW2026_LED_PAT_CTR_MASK 0x80 +#define AW2026_LED_PAT_CTR_INF_LOOP 0x0 + +#define AW2026_LED_PATRUN_MASK 0b111 +#define AW2026_LED_PATRUN_START_ALL 0b111 + +enum LED_ANIMATION { WHITE, YELLOW, BLINK_YELLOW }; +void sys_led_init(enum LED_ANIMATION led_animation); + +#endif // LEDS_AW2026_H_
diff --git a/include/amlogic/leds-aw210xx.h b/include/amlogic/leds-aw210xx.h new file mode 100644 index 0000000..be33ccb --- /dev/null +++ b/include/amlogic/leds-aw210xx.h
@@ -0,0 +1,158 @@ +#ifndef LEDS_AW2026_H_ +#define LEDS_AW2026_H_ + +#include <common.h> + +#ifdef CONFIG_SYS_I2C_MESON +#include <i2c.h> +#include <dt-bindings/i2c/meson-i2c.h> +#include <fs.h> +#endif + +#define N_CAL_SETTINGS 6 +#define I2C_BUS_NUM 4 +#define I2C_LED_REG 0x20 + +/***************************************************** +* register about led mode +*****************************************************/ +#define AW210XX_REG_GCR (0x20) +#define AW210XX_REG_BR00L (0x21) +#define AW210XX_REG_BR00H (0x22) +#define AW210XX_REG_BR01L (0x23) +#define AW210XX_REG_BR01H (0x24) +#define AW210XX_REG_BR02L (0x25) +#define AW210XX_REG_BR02H (0x26) +#define AW210XX_REG_BR03L (0x27) +#define AW210XX_REG_BR03H (0x28) +#define AW210XX_REG_BR04L (0x29) +#define AW210XX_REG_BR04H (0x2A) +#define AW210XX_REG_BR05L (0x2B) +#define AW210XX_REG_BR05H (0x2C) +#define AW210XX_REG_BR06L (0x2D) +#define AW210XX_REG_BR06H (0x2E) +#define AW210XX_REG_BR07L (0x2F) +#define AW210XX_REG_BR07H (0x30) +#define AW210XX_REG_BR08L (0x31) +#define AW210XX_REG_BR08H (0x32) +#define AW210XX_REG_BR09L (0x33) +#define AW210XX_REG_BR09H (0x34) +#define AW210XX_REG_BR10L (0x35) +#define AW210XX_REG_BR10H (0x36) +#define AW210XX_REG_BR11L (0x37) +#define AW210XX_REG_BR11H (0x38) +#define AW210XX_REG_BR12L (0x39) +#define AW210XX_REG_BR12H (0x3A) +#define AW210XX_REG_BR13L (0x3B) +#define AW210XX_REG_BR13H (0x3C) +#define AW210XX_REG_BR14L (0x3D) +#define AW210XX_REG_BR14H (0x3E) +#define AW210XX_REG_BR15L (0x3F) +#define AW210XX_REG_BR15H (0x40) +#define AW210XX_REG_BR16L (0x41) +#define AW210XX_REG_BR16H (0x42) +#define AW210XX_REG_BR17L (0x43) +#define AW210XX_REG_BR17H (0x44) +#define AW210XX_REG_UPDATE (0x45) +#define AW210XX_REG_SL00 (0x46) +#define AW210XX_REG_SL01 (0x47) +#define AW210XX_REG_SL02 (0x48) +#define AW210XX_REG_SL03 (0x49) +#define AW210XX_REG_SL04 (0x4A) +#define AW210XX_REG_SL05 (0x4B) +#define AW210XX_REG_SL06 (0x4C) +#define AW210XX_REG_SL07 (0x4D) +#define AW210XX_REG_SL09 (0x4F) +#define AW210XX_REG_SL10 (0x50) +#define AW210XX_REG_SL11 (0x51) +#define AW210XX_REG_SL12 (0x52) +#define AW210XX_REG_SL13 (0x53) +#define AW210XX_REG_SL14 (0x54) +#define AW210XX_REG_SL15 (0x55) +#define AW210XX_REG_SL16 (0x56) +#define AW210XX_REG_SL17 (0x57) +#define AW210XX_REG_GCCR (0x58) +#define AW210XX_REG_PHCR (0x59) +#define AW210XX_REG_OSDCR (0x5A) +#define AW210XX_REG_OSST0 (0x5B) +#define AW210XX_REG_OSST1 (0x5C) +#define AW210XX_REG_OSST2 (0x5D) +#define AW210XX_REG_OTCR (0x5E) +#define AW210XX_REG_SSCR (0x5F) +#define AW210XX_REG_UVCR (0x60) +#define AW210XX_REG_GCR2 (0x61) +#define AW210XX_REG_GCR3 (0x62) +#define AW210XX_REG_RESET (0x70) +#define AW210XX_REG_ABMCFG (0x80) +#define AW210XX_REG_ABMGO (0x81) +#define AW210XX_REG_ABMT0 (0x82) +#define AW210XX_REG_ABMT1 (0x83) +#define AW210XX_REG_ABMT2 (0x84) +#define AW210XX_REG_ABMT3 (0x85) +#define AW210XX_REG_GBRH (0x86) +#define AW210XX_REG_GBRL (0x87) +#define AW210XX_REG_GSLR (0x88) +#define AW210XX_REG_GSLG (0x89) +#define AW210XX_REG_GSLB (0x8A) +#define AW210XX_REG_GCFG (0x8B) + +/***************************************************** + * define register Detail +*****************************************************/ +#define AW210XX_BIT_APSE_MASK (1 << 7) +#define AW210XX_BIT_APSE_ENABLE (1 << 7) +#define AW210XX_BIT_APSE_DISENA (0 << 7) +#define AW210XX_BIT_CHIPEN_MASK (1 << 0) +#define AW210XX_BIT_CHIPEN_ENABLE (1 << 0) +#define AW210XX_BIT_CHIPEN_DISENA (0 << 0) + +#define AW210XX_UPDATE_ENABLE (0x0) +#define AW210XX_UPDATE_MASK (0xff) +#define AW210XX_PDE_ENABLE (1 << 7) +#define AW210XX_PDE_MASK (1 << 7) +#define AW210XX_GE2_SET (1 << 2) +#define AW210XX_GE_MASK (0x7) +#define AW210XX_PATE_ENABLE (1 << 0) +#define AW210XX_PATMD_AUTO (1 << 1) +#define AW210XX_PATCFG_MASK (0x3) +#define AW210XX_PAT_RISE_TIME (0x0) +#define AW210XX_PAT_RISE_MASK (0xf << 4) +#define AW210XX_PAT_ON_TIME (0x6) +#define AW210XX_PAT_ON_MASK (0xf) +#define AW210XX_PAT_FALL_TIME (0x0) +#define AW210XX_PAT_FALL_MASK (0xf << 4) +#define AW210XX_PAT_OFF_TIME (0x6) +#define AW210XX_PAT_OFF_MASK (0xf) +#define AW210XX_PAT_RUN (0x1) +#define AW210XX_PAT_RUN_MASK (0x1) + + +#define AW210XX_RESET_MASK 0xff +#define AW210XX_GLOBAL_CURRENT_MASK 0xff +#define AW210XX_SLXX_MASK 0xff +#define AW210XX_BRXX_MASK 0xff + +/***************************************************** + * define register data +*****************************************************/ +#define AW210XX_RESET_CHIP (0x00) +#define AW210XX_UPDATE_BR_SL (0x00) +#define AW210XX_GROUP_ENABLE (0x38) +#define AW210XX_GROUP_DISABLE (0x40) +#define AW210XX_GLOBAL_DEFAULT_SET (0x66) +#define AW210XX_GBRH_DEFAULT_SET (0x60) +#define AW210XX_GBRL_DEFAULT_SET (0x00) +#define AW210XX_ABMT0_SET (0x99) +#define AW210XX_ABMT1_SET (0x99) +#define AW210XX_ABMT2_SET (0x00) +#define AW210XX_ABMT3_SET (0x00) +#define AW210XX_ABMCFG_SET (0x03) +#define AW210XX_ABMGO_SET (0x01) +#define AW210xx_MAX_CURRENT (0xff) +#define AW210xx_MAX_BRIGHTNESS (0xff) +#define AW210xx_MIN_BRIGHTNESS (0x0) + +enum LED_ANIMATION { WHITE, YELLOW, BLINK_YELLOW }; +void sys_led_init(enum LED_ANIMATION led_animation); + +#endif // LEDS_AW2026_H_
diff --git a/include/amlogic/media/dv/dolby_vision_func.h b/include/amlogic/media/dv/dolby_vision_func.h new file mode 100644 index 0000000..9040d0b --- /dev/null +++ b/include/amlogic/media/dv/dolby_vision_func.h
@@ -0,0 +1,383 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _DV_H_ +#define _DV_H_ + +#include <linux/types.h> + +#define DEF_G2L_LUT_SIZE_2P 8 +#define DEF_G2L_LUT_SIZE (1 << DEF_G2L_LUT_SIZE_2P) + +enum signal_format_e { + FORMAT_INVALID = -1, + FORMAT_DOVI = 0, + FORMAT_HDR10 = 1, + FORMAT_SDR = 2, + FORMAT_DOVI_LL = 3 +}; + +enum priority_mode_e { + VIDEO_PRIORITY = 0, + GRAPHIC_PRIORITY = 1 +}; + +enum cp_signal_range_e { + SIG_RANGE_SMPTE = 0, /* head range */ + SIG_RANGE_FULL = 1, /* full range */ + SIG_RANGE_SDI = 2 /* PQ */ +}; + +enum graphics_format_e +{ + GF_SDR_YUV = 0, /* BT.709 YUV BT1886 */ + GF_SDR_RGB = 1, /* BT.709 RGB BT1886 */ + GF_HDR_YUV = 2, /* BT.2020 YUV PQ */ + GF_HDR_RGB = 3 /* BT.2020 RGB PQ */ +}; + +struct composer_register_ipcore_s { + uint32_t Composer_Mode; + uint32_t VDR_Resolution; + uint32_t Bit_Depth; + uint32_t Coefficient_Log2_Denominator; + uint32_t BL_Num_Pivots_Y; + uint32_t BL_Pivot[5]; + uint32_t BL_Order; + uint32_t BL_Coefficient_Y[8][3]; + uint32_t EL_NLQ_Offset_Y; + uint32_t EL_Coefficient_Y[3]; + uint32_t Mapping_IDC_U; + uint32_t BL_Num_Pivots_U; + uint32_t BL_Pivot_U[3]; + uint32_t BL_Order_U; + uint32_t BL_Coefficient_U[4][3]; + uint32_t MMR_Coefficient_U[22][2]; + uint32_t MMR_Order_U; + uint32_t EL_NLQ_Offset_U; + uint32_t EL_Coefficient_U[3]; + uint32_t Mapping_IDC_V; + uint32_t BL_Num_Pivots_V; + uint32_t BL_Pivot_V[3]; + uint32_t BL_Order_V; + uint32_t BL_Coefficient_V[4][3]; + uint32_t MMR_Coefficient_V[22][2]; + uint32_t MMR_Order_V; + uint32_t EL_NLQ_Offset_V; + uint32_t EL_Coefficient_V[3]; +}; + +/** @brief DM registers for IPCORE 1 */ +struct dm_register_ipcore_1_s { + uint32_t SRange; + uint32_t Srange_Inverse; + uint32_t Frame_Format_1; + uint32_t Frame_Format_2; + uint32_t Frame_Pixel_Def; + uint32_t Y2RGB_Coefficient_1; + uint32_t Y2RGB_Coefficient_2; + uint32_t Y2RGB_Coefficient_3; + uint32_t Y2RGB_Coefficient_4; + uint32_t Y2RGB_Coefficient_5; + uint32_t Y2RGB_Offset_1; + uint32_t Y2RGB_Offset_2; + uint32_t Y2RGB_Offset_3; + uint32_t EOTF; + uint32_t A2B_Coefficient_1; + uint32_t A2B_Coefficient_2; + uint32_t A2B_Coefficient_3; + uint32_t A2B_Coefficient_4; + uint32_t A2B_Coefficient_5; + uint32_t C2D_Coefficient_1; + uint32_t C2D_Coefficient_2; + uint32_t C2D_Coefficient_3; + uint32_t C2D_Coefficient_4; + uint32_t C2D_Coefficient_5; + uint32_t C2D_Offset; + uint32_t Active_area_left_top; + uint32_t Active_area_bottom_right; +}; + +/** @brief DM registers for IPCORE 2 */ +struct dm_register_ipcore_2_s { + uint32_t SRange; + uint32_t Srange_Inverse; + uint32_t Y2RGB_Coefficient_1; + uint32_t Y2RGB_Coefficient_2; + uint32_t Y2RGB_Coefficient_3; + uint32_t Y2RGB_Coefficient_4; + uint32_t Y2RGB_Coefficient_5; + uint32_t Y2RGB_Offset_1; + uint32_t Y2RGB_Offset_2; + uint32_t Y2RGB_Offset_3; + uint32_t Frame_Format; + uint32_t EOTF; + uint32_t A2B_Coefficient_1; + uint32_t A2B_Coefficient_2; + uint32_t A2B_Coefficient_3; + uint32_t A2B_Coefficient_4; + uint32_t A2B_Coefficient_5; + uint32_t C2D_Coefficient_1; + uint32_t C2D_Coefficient_2; + uint32_t C2D_Coefficient_3; + uint32_t C2D_Coefficient_4; + uint32_t C2D_Coefficient_5; + uint32_t C2D_Offset; + uint32_t VDR_Resolution; +}; + +/** @brief DM registers for IPCORE 3 */ +struct dm_register_ipcore_3_s { + uint32_t D2C_coefficient_1; + uint32_t D2C_coefficient_2; + uint32_t D2C_coefficient_3; + uint32_t D2C_coefficient_4; + uint32_t D2C_coefficient_5; + uint32_t B2A_Coefficient_1; + uint32_t B2A_Coefficient_2; + uint32_t B2A_Coefficient_3; + uint32_t B2A_Coefficient_4; + uint32_t B2A_Coefficient_5; + uint32_t Eotf_param_1; + uint32_t Eotf_param_2; + uint32_t IPT_Scale; + uint32_t IPT_Offset_1; + uint32_t IPT_Offset_2; + uint32_t IPT_Offset_3; + uint32_t Output_range_1; + uint32_t Output_range_2; + uint32_t RGB2YUV_coefficient_register1; + uint32_t RGB2YUV_coefficient_register2; + uint32_t RGB2YUV_coefficient_register3; + uint32_t RGB2YUV_coefficient_register4; + uint32_t RGB2YUV_coefficient_register5; + uint32_t RGB2YUV_offset_0; + uint32_t RGB2YUV_offset_1; + uint32_t RGB2YUV_offset_2; +}; + +/** @brief DM luts for IPCORE 1 and 2 */ +struct dm_lut_ipcore_s { + uint32_t TmLutI[64*4]; + uint32_t TmLutS[64*4]; + uint32_t SmLutI[64*4]; + uint32_t SmLutS[64*4]; + uint32_t G2L[DEF_G2L_LUT_SIZE]; +}; + +/** @brief hdmi metadata for IPCORE 3 */ +struct md_reister_ipcore_3_s { + uint32_t raw_metadata[512]; + uint32_t size; +}; + +struct hdr_10_infoframe_s { + uint8_t infoframe_type_code; + uint8_t infoframe_version_number; + uint8_t length_of_info_frame; + uint8_t data_byte_1; + uint8_t data_byte_2; + uint8_t display_primaries_x_0_LSB; + uint8_t display_primaries_x_0_MSB; + uint8_t display_primaries_y_0_LSB; + uint8_t display_primaries_y_0_MSB; + uint8_t display_primaries_x_1_LSB; + uint8_t display_primaries_x_1_MSB; + uint8_t display_primaries_y_1_LSB; + uint8_t display_primaries_y_1_MSB; + uint8_t display_primaries_x_2_LSB; + uint8_t display_primaries_x_2_MSB; + uint8_t display_primaries_y_2_LSB; + uint8_t display_primaries_y_2_MSB; + uint8_t white_point_x_LSB; + uint8_t white_point_x_MSB; + uint8_t white_point_y_LSB; + uint8_t white_point_y_MSB; + uint8_t max_display_mastering_luminance_LSB; + uint8_t max_display_mastering_luminance_MSB; + uint8_t min_display_mastering_luminance_LSB; + uint8_t min_display_mastering_luminance_MSB; + uint8_t max_content_light_level_LSB; + uint8_t max_content_light_level_MSB; + uint8_t max_frame_average_light_level_LSB; + uint8_t max_frame_average_light_level_MSB; +}; + +struct hdr10_param_s { + uint32_t min_display_mastering_luminance; + uint32_t max_display_mastering_luminance; + uint16_t Rx; + uint16_t Ry; + uint16_t Gx; + uint16_t Gy; + uint16_t Bx; + uint16_t By; + uint16_t Wx; + uint16_t Wy; + uint16_t max_content_light_level; + uint16_t max_pic_average_light_level; +}; + +struct ext_level_1_s { + uint8_t min_PQ_hi; + uint8_t min_PQ_lo; + uint8_t max_PQ_hi; + uint8_t max_PQ_lo; + uint8_t avg_PQ_hi; + uint8_t avg_PQ_lo; +}; + +struct ext_level_2_s { + uint8_t target_max_PQ_hi; + uint8_t target_max_PQ_lo; + uint8_t trim_slope_hi; + uint8_t trim_slope_lo; + uint8_t trim_offset_hi; + uint8_t trim_offset_lo; + uint8_t trim_power_hi; + uint8_t trim_power_lo; + uint8_t trim_chroma_weight_hi; + uint8_t trim_chroma_weight_lo; + uint8_t trim_saturation_gain_hi; + uint8_t trim_saturation_gain_lo; + uint8_t ms_weight_hi; + uint8_t ms_weight_lo; +}; + +struct ext_level_4_s { + uint8_t anchor_PQ_hi; + uint8_t anchor_PQ_lo; + uint8_t anchor_power_hi; + uint8_t anchor_power_lo; +}; + +struct ext_level_5_s { + uint8_t active_area_left_offset_hi; + uint8_t active_area_left_offset_lo; + uint8_t active_area_right_offset_hi; + uint8_t active_area_right_offset_lo; + uint8_t active_area_top_offset_hi; + uint8_t active_area_top_offset_lo; + uint8_t active_area_bottom_offset_hi; + uint8_t active_area_bottom_offset_lo; +}; + +struct ext_level_6_s { + uint8_t max_display_mastering_luminance_hi; + uint8_t max_display_mastering_luminance_lo; + uint8_t min_display_mastering_luminance_hi; + uint8_t min_display_mastering_luminance_lo; + uint8_t max_content_light_level_hi; + uint8_t max_content_light_level_lo; + uint8_t max_frame_average_light_level_hi; + uint8_t max_frame_average_light_level_lo; +}; + +struct ext_level_255_s { + uint8_t dm_run_mode; + uint8_t dm_run_version; + uint8_t dm_debug0; + uint8_t dm_debug1; + uint8_t dm_debug2; + uint8_t dm_debug3; +}; + +struct ext_md_s { + uint32_t available_level_mask; + struct ext_level_1_s level_1; + struct ext_level_2_s level_2; + struct ext_level_4_s level_4; + struct ext_level_5_s level_5; + struct ext_level_6_s level_6; + struct ext_level_255_s level_255; +}; + +struct dovi_setting_s { + struct composer_register_ipcore_s comp_reg; + struct dm_register_ipcore_1_s dm_reg1; + struct dm_register_ipcore_2_s dm_reg2; + struct dm_register_ipcore_3_s dm_reg3; + struct dm_lut_ipcore_s dm_lut1; + struct dm_lut_ipcore_s dm_lut2; + /* for dovi output */ + struct md_reister_ipcore_3_s md_reg3; + /* for hdr10 output */ + struct hdr_10_infoframe_s hdr_info; + /* current process */ + enum signal_format_e src_format; + enum signal_format_e dst_format; + /* enhanced layer */ + bool el_flag; + bool el_halfsize_flag; + /* frame width & height */ + uint32_t video_width; + uint32_t video_height; + + /* use for stb 2.4 */ + enum graphics_format_e g_format; + uint32_t g_bitdepth; + uint32_t dovi2hdr10_nomapping; + uint32_t use_ll_flag; + uint32_t ll_rgb_desired; + uint32_t diagnostic_enable; + uint32_t diagnostic_mux_select; + uint32_t dovi_ll_enable; + uint32_t vout_width; + uint32_t vout_height; + u8 vsvdb_tbl[32]; + u8 hdrdb_tbl[7]; + struct ext_md_s ext_md; + uint32_t vsvdb_len; + uint32_t vsvdb_changed; + uint32_t mode_changed; +}; + + +extern int control_path( + enum signal_format_e in_format, + enum signal_format_e out_format, + char *in_comp, int in_comp_size, + char *in_md, int in_md_size, + enum priority_mode_e set_priority, + int set_bit_depth, int set_chroma_format, int set_yuv_range, + int set_graphic_min_lum, int set_graphic_max_lum, + int set_target_min_lum, int set_target_max_lum, + int set_no_el, + struct hdr10_param_s *hdr10_param, + struct dovi_setting_s *output); +extern void *metadata_parser_init(int flag); +extern int metadata_parser_reset(int flag); +extern int metadata_parser_process( + char *src_rpu, int rpu_len, + char *dst_comp, int *comp_len, + char *dst_md, int *md_len, bool src_eos); +extern void metadata_parser_release(void); + +struct dolby_vision_func_s { + const char *version_info; + void * (*metadata_parser_init)(int flag); + int (*metadata_parser_reset)(int flag); + int (*metadata_parser_process)( + char *src_rpu, int rpu_len, + char *dst_comp, int *comp_len, + char *dst_md, int *md_len, bool src_eos); + void (*metadata_parser_release)(void); + int (*control_path)( + enum signal_format_e in_format, + enum signal_format_e out_format, + char *in_comp, int in_comp_size, + char *in_md, int in_md_size, + enum priority_mode_e set_priority, + int set_bit_depth, int set_chroma_format, int set_yuv_range, + int set_graphic_min_lum, int set_graphic_max_lum, + int set_target_min_lum, int set_target_max_lum, + int set_no_el, + struct hdr10_param_s *hdr10_param, + struct dovi_setting_s *output); + int (*reserved_func)(void); +}; + +extern const struct dolby_vision_func_s DV_func; +#endif
diff --git a/include/amlogic/media/vout/aml_cvbs.h b/include/amlogic/media/vout/aml_cvbs.h index 4921549..e172deb 100644 --- a/include/amlogic/media/vout/aml_cvbs.h +++ b/include/amlogic/media/vout/aml_cvbs.h
@@ -8,12 +8,11 @@ void cvbs_init(void); void cvbs_show_valid_vmode(void); +int cvbs_outputmode_check(char *vmode_name, unsigned int frac); int cvbs_set_vmode(char* vmode_name); int cvbs_set_bist(char* bist_mode); int cvbs_set_vdac(int status); int cvbs_reg_debug(int argc, char* const argv[]); -extern int cvbs_outputmode_check(char *vmode_name); - #endif
diff --git a/include/amlogic/media/vout/aml_vout.h b/include/amlogic/media/vout/aml_vout.h index 5e347bc..513a2de 100644 --- a/include/amlogic/media/vout/aml_vout.h +++ b/include/amlogic/media/vout/aml_vout.h
@@ -8,12 +8,23 @@ #include <amlogic/media/vout/aml_vinfo.h> +#define VOUT_VIU1_SEL 1 +#define VOUT_VIU2_SEL 2 + +enum viu_mux_e { + VIU_MUX_ENCL = 0, + VIU_MUX_ENCI, + VIU_MUX_ENCP, + VIU_MUX_MAX, +}; + void vout_init(void); void vout_vinfo_dump(void); int vout_get_current_vmode(void); int vout_get_current_axis(int *axis); void vout_set_current_vmode(int mode); struct vinfo_s *vout_get_current_vinfo(void); +void vout_viu_mux(int viu_sel, int venc_sel); extern unsigned long get_fb_addr(void); #endif
diff --git a/include/amlogic/media/vout/hdmitx.h b/include/amlogic/media/vout/hdmitx.h deleted file mode 100644 index a7965b2..0000000 --- a/include/amlogic/media/vout/hdmitx.h +++ /dev/null
@@ -1,435 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - */ - -#ifndef __HDMI_COMMON_H__ -#define __HDMI_COMMON_H__ - -/* Little-Endian format */ -enum scdc_addr { - SINK_VER = 0x01, - SOURCE_VER, /* RW */ - UPDATE_0 = 0x10, /* RW */ - UPDATE_1, /* RW */ - TMDS_CFG = 0x20, /* RW */ - SCRAMBLER_ST, - CONFIG_0 = 0x30, /* RW */ - STATUS_FLAGS_0 = 0x40, - STATUS_FLAGS_1, - ERR_DET_0_L = 0x50, - ERR_DET_0_H, - ERR_DET_1_L, - ERR_DET_1_H, - ERR_DET_2_L, - ERR_DET_2_H, - ERR_DET_CHKSUM, - TEST_CONFIG_0 = 0xC0, /* RW */ - MANUFACT_IEEE_OUI_2 = 0xD0, - MANUFACT_IEEE_OUI_1, - MANUFACT_IEEE_OUI_0, - DEVICE_ID = 0xD3, /* 0xD3 ~ 0xDD */ - /* RW 0xDE ~ 0xFF */ - MANUFACT_SPECIFIC = 0xDE, -}; - -#define HDMITX_VIC420_OFFSET 0x100 -#define HDMITX_VESA_OFFSET 0x300 - -/* HDMI VIC definitions */ -enum hdmi_vic { - /* Refer to CEA 861-D */ - HDMI_unkown = 0, - HDMI_640x480p60_4x3 = 1, - HDMI_720x480p60_4x3 = 2, - HDMI_720x480p60_16x9 = 3, - HDMI_1280x720p60_16x9 = 4, - HDMI_1920x1080i60_16x9 = 5, - HDMI_720x480i60_4x3 = 6, - HDMI_720x480i60_16x9 = 7, - HDMI_720x240p60_4x3 = 8, - HDMI_720x240p60_16x9 = 9, - HDMI_2880x480i60_4x3 = 10, - HDMI_2880x480i60_16x9 = 11, - HDMI_2880x240p60_4x3 = 12, - HDMI_2880x240p60_16x9 = 13, - HDMI_1440x480p60_4x3 = 14, - HDMI_1440x480p60_16x9 = 15, - HDMI_1920x1080p60_16x9 = 16, - HDMI_720x576p50_4x3 = 17, - HDMI_720x576p50_16x9 = 18, - HDMI_1280x720p50_16x9 = 19, - HDMI_1920x1080i50_16x9 = 20, - HDMI_720x576i50_4x3 = 21, - HDMI_720x576i50_16x9 = 22, - HDMI_720x288p_4x3 = 23, - HDMI_720x288p_16x9 = 24, - HDMI_2880x576i50_4x3 = 25, - HDMI_2880x576i50_16x9 = 26, - HDMI_2880x288p50_4x3 = 27, - HDMI_2880x288p50_16x9 = 28, - HDMI_1440x576p_4x3 = 29, - HDMI_1440x576p_16x9 = 30, - HDMI_1920x1080p50_16x9 = 31, - HDMI_1920x1080p24_16x9 = 32, - HDMI_1920x1080p25_16x9 = 33, - HDMI_1920x1080p30_16x9 = 34, - HDMI_2880x480p60_4x3 = 35, - HDMI_2880x480p60_16x9 = 36, - HDMI_2880x576p50_4x3 = 37, - HDMI_2880x576p50_16x9 = 38, - HDMI_1920x1080i_t1250_50_16x9 = 39, - HDMI_1920x1080i100_16x9 = 40, - HDMI_1280x720p100_16x9 = 41, - HDMI_720x576p100_4x3 = 42, - HDMI_720x576p100_16x9 = 43, - HDMI_720x576i100_4x3 = 44, - HDMI_720x576i100_16x9 = 45, - HDMI_1920x1080i120_16x9 = 46, - HDMI_1280x720p120_16x9 = 47, - HDMI_720x480p120_4x3 = 48, - HDMI_720x480p120_16x9 = 49, - HDMI_720x480i120_4x3 = 50, - HDMI_720x480i120_16x9 = 51, - HDMI_720x576p200_4x3 = 52, - HDMI_720x576p200_16x9 = 53, - HDMI_720x576i200_4x3 = 54, - HDMI_720x576i200_16x9 = 55, - HDMI_720x480p240_4x3 = 56, - HDMI_720x480p240_16x9 = 57, - HDMI_720x480i240_4x3 = 58, - HDMI_720x480i240_16x9 = 59, - /* Refet to CEA 861-F */ - HDMI_1280x720p24_16x9 = 60, - HDMI_1280x720p25_16x9 = 61, - HDMI_1280x720p30_16x9 = 62, - HDMI_1920x1080p120_16x9 = 63, - HDMI_1920x1080p100_16x9 = 64, - HDMI_1280x720p24_64x27 = 65, - HDMI_1280x720p25_64x27 = 66, - HDMI_1280x720p30_64x27 = 67, - HDMI_1280x720p50_64x27 = 68, - HDMI_1280x720p60_64x27 = 69, - HDMI_1280x720p100_64x27 = 70, - HDMI_1280x720p120_64x27 = 71, - HDMI_1920x1080p24_64x27 = 72, - HDMI_1920x1080p25_64x27 = 73, - HDMI_1920x1080p30_64x27 = 74, - HDMI_1920x1080p50_64x27 = 75, - HDMI_1920x1080p60_64x27 = 76, - HDMI_1920x1080p100_64x27 = 77, - HDMI_1920x1080p120_64x27 = 78, - HDMI_1680x720p24_64x27 = 79, - HDMI_1680x720p25_64x27 = 80, - HDMI_1680x720p30_64x27 = 81, - HDMI_1680x720p50_64x27 = 82, - HDMI_1680x720p60_64x27 = 83, - HDMI_1680x720p100_64x27 = 84, - HDMI_1680x720p120_64x27 = 85, - HDMI_2560x1080p24_64x27 = 86, - HDMI_2560x1080p25_64x27 = 87, - HDMI_2560x1080p30_64x27 = 88, - HDMI_2560x1080p50_64x27 = 89, - HDMI_2560x1080p60_64x27 = 90, - HDMI_2560x1080p100_64x27 = 91, - HDMI_2560x1080p120_64x27 = 92, - HDMI_3840x2160p24_16x9 = 93, - HDMI_3840x2160p25_16x9 = 94, - HDMI_3840x2160p30_16x9 = 95, - HDMI_3840x2160p50_16x9 = 96, - HDMI_3840x2160p60_16x9 = 97, - HDMI_4096x2160p24_256x135 = 98, - HDMI_4096x2160p25_256x135 = 99, - HDMI_4096x2160p30_256x135 = 100, - HDMI_4096x2160p50_256x135 = 101, - HDMI_4096x2160p60_256x135 = 102, - HDMI_3840x2160p24_64x27 = 103, - HDMI_3840x2160p25_64x27 = 104, - HDMI_3840x2160p30_64x27 = 105, - HDMI_3840x2160p50_64x27 = 106, - HDMI_3840x2160p60_64x27 = 107, - HDMI_RESERVED = 108, - /* - the following vic is for those y420 mode - they are all beyond OFFSET_HDMITX_VIC420(0x1000) - and they has same vic with normal vic in the lower bytes. - */ - HDMI_VIC_Y420 = HDMITX_VIC420_OFFSET, - HDMI_3840x2160p50_16x9_Y420 = - HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_16x9, - HDMI_3840x2160p60_16x9_Y420 = - HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_16x9, - HDMI_4096x2160p50_256x135_Y420 = - HDMITX_VIC420_OFFSET + HDMI_4096x2160p50_256x135, - HDMI_4096x2160p60_256x135_Y420 = - HDMITX_VIC420_OFFSET + HDMI_4096x2160p60_256x135, - HDMI_3840x2160p50_64x27_Y420 = - HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_64x27, - HDMI_3840x2160p60_64x27_Y420 = - HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_64x27, - HDMIV_640x480p60hz = HDMITX_VESA_OFFSET, - HDMIV_800x480p60hz, - HDMIV_800x600p60hz, - HDMIV_852x480p60hz, - HDMIV_854x480p60hz, - HDMIV_1024x600p60hz, - HDMIV_1024x768p60hz, - HDMIV_1152x864p75hz, - HDMIV_1280x600p60hz, - HDMIV_1280x768p60hz, - HDMIV_1280x800p60hz, - HDMIV_1280x960p60hz, - HDMIV_1280x1024p60hz, - HDMIV_1360x768p60hz, - HDMIV_1366x768p60hz, - HDMIV_1400x1050p60hz, - HDMIV_1440x900p60hz, - HDMIV_1440x2560p60hz, - HDMIV_1440x2560p70hz, - HDMIV_1600x900p60hz, - HDMIV_1600x1200p60hz, - HDMIV_1680x1050p60hz, - HDMIV_1920x1200p60hz, - HDMIV_2160x1200p90hz, - HDMIV_2560x1080p60hz, - HDMIV_2560x1440p60hz, - HDMIV_2560x1600p60hz, - HDMIV_3440x1440p60hz, -}; - -/* CEA TIMING STRUCT DEFINITION */ -struct hdmi_cea_timing { - unsigned int pixel_freq; /* Unit: 1000 */ - unsigned int h_freq; /* Unit: Hz */ - unsigned int v_freq; /* Unit: 0.001 Hz */ - unsigned int vsync_polarity:1; /* 1: positive 0: negative */ - unsigned int hsync_polarity:1; - unsigned short h_active; - unsigned short h_total; - unsigned short h_blank; - unsigned short h_front; - unsigned short h_sync; - unsigned short h_back; - unsigned short v_active; - unsigned short v_total; - unsigned short v_blank; - unsigned short v_front; - unsigned short v_sync; - unsigned short v_back; - unsigned short v_sync_ln; -}; - -/* Refer CEA861-D Page 116 Table 55 */ -struct dtd { - unsigned short pixel_clock; - unsigned short h_active; - unsigned short h_blank; - unsigned short v_active; - unsigned short v_blank; - unsigned short h_sync_offset; - unsigned short h_sync; - unsigned short v_sync_offset; - unsigned short v_sync; - unsigned char h_image_size; - unsigned char v_image_size; - unsigned char h_border; - unsigned char v_border; - unsigned char flags; - enum hdmi_vic vic; -}; - -#define VIC_MAX_NUM 256 -struct rx_cap { - unsigned int native_Mode; - /*video*/ - unsigned int VIC[VIC_MAX_NUM]; - unsigned int VIC_count; - unsigned int native_VIC; - /*vendor*/ - unsigned int IEEEOUI; - unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */ - unsigned int HF_IEEEOUI; /* For HDMI Forum */ - unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */ - /* CEA861-F, Table 56, Colorimetry Data Block */ - unsigned int colorimetry_data; - unsigned int scdc_present:1; - unsigned int scdc_rr_capable:1; /* SCDC read request */ - unsigned int lte_340mcsc_scramble:1; - unsigned int dc_y444:1; - unsigned int dc_30bit:1; - unsigned int dc_36bit:1; - unsigned int dc_48bit:1; - unsigned int dc_30bit_420:1; - unsigned int dc_36bit_420:1; - unsigned int dc_48bit_420:1; - unsigned char edid_version; - unsigned char edid_revision; - unsigned int ColorDeepSupport; - unsigned int Video_Latency; - unsigned int Audio_Latency; - unsigned int Interlaced_Video_Latency; - unsigned int Interlaced_Audio_Latency; - unsigned int threeD_present; - unsigned int threeD_Multi_present; - unsigned int hdmi_vic_LEN; - enum hdmi_vic preferred_mode; - struct dtd dtd[16]; - unsigned char dtd_idx; - unsigned char flag_vfpdb; - unsigned char number_of_dtd; - unsigned char pref_colorspace; - /*blk0 check sum*/ - unsigned char chksum; -}; - -enum hdmi_color_depth { - HDMI_COLOR_DEPTH_24B = 4, - HDMI_COLOR_DEPTH_30B = 5, - HDMI_COLOR_DEPTH_36B = 6, - HDMI_COLOR_DEPTH_48B = 7, -}; - -enum hdmi_color_format { - HDMI_COLOR_FORMAT_RGB, - HDMI_COLOR_FORMAT_444, - HDMI_COLOR_FORMAT_422, - HDMI_COLOR_FORMAT_420, -}; - -enum hdmi_color_range { - HDMI_COLOR_RANGE_LIM, - HDMI_COLOR_RANGE_FUL, -}; - -enum hdmi_audio_packet { - HDMI_AUDIO_PACKET_SMP = 0x02, - HDMI_AUDIO_PACKET_1BT = 0x07, - HDMI_AUDIO_PACKET_DST = 0x08, - HDMI_AUDIO_PACKET_HBR = 0x09, -}; - -/* get hdmi cea timing - * t: struct hdmi_cea_timing * - */ -#define GET_TIMING(name) (t->name) - -struct parse_cd { - enum hdmi_color_depth cd; - const char *name; -}; - -struct parse_cs { - enum hdmi_color_format cs; - const char *name; -}; - -struct parse_cr { - enum hdmi_color_format cr; - const char *name; -}; - -#define EDID_BLK_NO 4 -#define EDID_BLK_SIZE 128 -struct hdmi_format_para { - enum hdmi_vic vic; - char *name; /* full name, 1280x720p60hz */ - char *sname; /* short name, 1280x720p60hz -> 720p60hz */ - char ext_name[32]; - enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */ - enum hdmi_color_format cs; /* rgb, y444, y422, y420 */ - enum hdmi_color_range cr; /* limit, full */ - unsigned int pixel_repetition_factor; - unsigned int progress_mode:1; /* 0: Interlace 1: Progressive */ - unsigned int scrambler_en:1; - unsigned int tmds_clk_div40:1; - unsigned int tmds_clk; /* Unit: 1000 */ - struct hdmi_cea_timing timing; -}; - -struct hdmi_support_mode { - enum hdmi_vic vic; - char *sname; - char y420; -}; - -struct hdmitx_dev { - unsigned char rx_edid[512]; /* some RX may exceeds 256Bytes */ - struct { - int (*get_hpd_state)(void); - int (*read_edid)(unsigned char *buf, unsigned char addr, - unsigned char blk_no); - void (*turn_off)(void); - void (*list_support_modes)(void); - void (*dump_regs)(void); - void (*test_bist)(unsigned int mode); - void (*output_blank)(unsigned int blank); - } HWOp; - unsigned char rawedid[EDID_BLK_SIZE * EDID_BLK_NO]; - struct rx_cap RXCap; - struct hdmi_format_para *para; - enum hdmi_vic vic; - unsigned int frac_rate_policy; - unsigned int mode420; - unsigned int dc30; -}; - -extern struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic); -extern enum hdmi_vic hdmi_get_fmt_vic(char const *name); -extern void hdmi_parse_attr(struct hdmi_format_para *para, char const *name); -extern void hdmi_tx_set(struct hdmitx_dev *hdev); -/* Parsing RAW EDID data from edid to pRXCap */ -extern unsigned int hdmi_edid_parsing(unsigned char *edid, struct rx_cap *pRXCap); -extern struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t); - - - - -/*These functions below are different in chip level*/ - -/*READ/WRITE REGISTERS*/ -extern unsigned long hd_read_reg(volatile unsigned int* addr); -extern void hd_write_reg(volatile unsigned int* addr, unsigned long val); -extern void hd_set_reg_bits(volatile unsigned int* addr, unsigned long value, - unsigned long offset, unsigned long len); -extern unsigned int hdmitx_rd_reg(unsigned int addr); -extern void hdmitx_wr_reg(unsigned int addr, unsigned int data); -extern void hdmitx_set_reg_bits(unsigned int addr, unsigned int value, - unsigned int offset, unsigned int len); -extern void hdmitx_poll_reg(unsigned int addr, unsigned int val, - unsigned long timeout); -extern void hdmitx_rd_check_reg (unsigned long addr, - unsigned long exp_data, unsigned long mask); -/*PHY*/ -extern void hdmitx_set_phy(struct hdmitx_dev *hdev); -extern void hdmitx_turnoff(void); -/*PLL*/ -extern void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev); -/*OD1 OD2 OD3*/ -extern void set_hpll_od1(unsigned div); -extern void set_hpll_od2(unsigned div); -extern void set_hpll_od3(unsigned div); -/*SSPLL*/ -extern void set_hpll_sspll(struct hdmitx_dev *hdev); -/*DDC CHANNEL*/ -extern void ddc_pinmux_init(void); -/*HPD*/ -extern int hdmitx_get_hpd_state(void); -/*PRBS*/ -extern void hdmitx_prbs(void); -/*APB3 bus for hdmitx DWC/TOP registers*/ -extern void hdmitx_enable_apb3(void); - -/*hdmitx init by called in board.c*/ -extern void hdmi_tx_init(void); -extern int hdmi_outputmode_check(char *mode); - -extern struct hdmitx_dev hdmitx_device; - -#ifndef printk -#define printk printf -#endif -#ifndef pr_info -#define pr_info printf -#endif - -#endif
diff --git a/include/amlogic/media/vout/hdmitx/hdmi_common.h b/include/amlogic/media/vout/hdmitx/hdmi_common.h new file mode 100644 index 0000000..3725363 --- /dev/null +++ b/include/amlogic/media/vout/hdmitx/hdmi_common.h
@@ -0,0 +1,660 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMI_COMMON_H__ +#define __HDMI_COMMON_H__ + +/* Little-Endian format */ +enum scdc_addr { + SINK_VER = 0x01, + SOURCE_VER, /* RW */ + UPDATE_0 = 0x10, /* RW */ + UPDATE_1, /* RW */ + TMDS_CFG = 0x20, /* RW */ + SCRAMBLER_ST, + CONFIG_0 = 0x30, /* RW */ + STATUS_FLAGS_0 = 0x40, + STATUS_FLAGS_1, + ERR_DET_0_L = 0x50, + ERR_DET_0_H, + ERR_DET_1_L, + ERR_DET_1_H, + ERR_DET_2_L, + ERR_DET_2_H, + ERR_DET_CHKSUM, + TEST_CONFIG_0 = 0xC0, /* RW */ + MANUFACT_IEEE_OUI_2 = 0xD0, + MANUFACT_IEEE_OUI_1, + MANUFACT_IEEE_OUI_0, + DEVICE_ID = 0xD3, /* 0xD3 ~ 0xDD */ + /* RW 0xDE ~ 0xFF */ + MANUFACT_SPECIFIC = 0xDE, +}; + +#define HDMITX_VIC420_OFFSET 0x100 +#define HDMITX_VESA_OFFSET 0x300 + +/* HDMI VIC definitions */ +enum hdmi_vic { + /* Refer to CEA 861-D */ + HDMI_unkown = 0, + HDMI_640x480p60_4x3 = 1, + HDMI_720x480p60_4x3 = 2, + HDMI_720x480p60_16x9 = 3, + HDMI_1280x720p60_16x9 = 4, + HDMI_1920x1080i60_16x9 = 5, + HDMI_720x480i60_4x3 = 6, + HDMI_720x480i60_16x9 = 7, + HDMI_720x240p60_4x3 = 8, + HDMI_720x240p60_16x9 = 9, + HDMI_2880x480i60_4x3 = 10, + HDMI_2880x480i60_16x9 = 11, + HDMI_2880x240p60_4x3 = 12, + HDMI_2880x240p60_16x9 = 13, + HDMI_1440x480p60_4x3 = 14, + HDMI_1440x480p60_16x9 = 15, + HDMI_1920x1080p60_16x9 = 16, + HDMI_720x576p50_4x3 = 17, + HDMI_720x576p50_16x9 = 18, + HDMI_1280x720p50_16x9 = 19, + HDMI_1920x1080i50_16x9 = 20, + HDMI_720x576i50_4x3 = 21, + HDMI_720x576i50_16x9 = 22, + HDMI_720x288p_4x3 = 23, + HDMI_720x288p_16x9 = 24, + HDMI_2880x576i50_4x3 = 25, + HDMI_2880x576i50_16x9 = 26, + HDMI_2880x288p50_4x3 = 27, + HDMI_2880x288p50_16x9 = 28, + HDMI_1440x576p_4x3 = 29, + HDMI_1440x576p_16x9 = 30, + HDMI_1920x1080p50_16x9 = 31, + HDMI_1920x1080p24_16x9 = 32, + HDMI_1920x1080p25_16x9 = 33, + HDMI_1920x1080p30_16x9 = 34, + HDMI_2880x480p60_4x3 = 35, + HDMI_2880x480p60_16x9 = 36, + HDMI_2880x576p50_4x3 = 37, + HDMI_2880x576p50_16x9 = 38, + HDMI_1920x1080i_t1250_50_16x9 = 39, + HDMI_1920x1080i100_16x9 = 40, + HDMI_1280x720p100_16x9 = 41, + HDMI_720x576p100_4x3 = 42, + HDMI_720x576p100_16x9 = 43, + HDMI_720x576i100_4x3 = 44, + HDMI_720x576i100_16x9 = 45, + HDMI_1920x1080i120_16x9 = 46, + HDMI_1280x720p120_16x9 = 47, + HDMI_720x480p120_4x3 = 48, + HDMI_720x480p120_16x9 = 49, + HDMI_720x480i120_4x3 = 50, + HDMI_720x480i120_16x9 = 51, + HDMI_720x576p200_4x3 = 52, + HDMI_720x576p200_16x9 = 53, + HDMI_720x576i200_4x3 = 54, + HDMI_720x576i200_16x9 = 55, + HDMI_720x480p240_4x3 = 56, + HDMI_720x480p240_16x9 = 57, + HDMI_720x480i240_4x3 = 58, + HDMI_720x480i240_16x9 = 59, + /* Refet to CEA 861-F */ + HDMI_1280x720p24_16x9 = 60, + HDMI_1280x720p25_16x9 = 61, + HDMI_1280x720p30_16x9 = 62, + HDMI_1920x1080p120_16x9 = 63, + HDMI_1920x1080p100_16x9 = 64, + HDMI_1280x720p24_64x27 = 65, + HDMI_1280x720p25_64x27 = 66, + HDMI_1280x720p30_64x27 = 67, + HDMI_1280x720p50_64x27 = 68, + HDMI_1280x720p60_64x27 = 69, + HDMI_1280x720p100_64x27 = 70, + HDMI_1280x720p120_64x27 = 71, + HDMI_1920x1080p24_64x27 = 72, + HDMI_1920x1080p25_64x27 = 73, + HDMI_1920x1080p30_64x27 = 74, + HDMI_1920x1080p50_64x27 = 75, + HDMI_1920x1080p60_64x27 = 76, + HDMI_1920x1080p100_64x27 = 77, + HDMI_1920x1080p120_64x27 = 78, + HDMI_1680x720p24_64x27 = 79, + HDMI_1680x720p25_64x27 = 80, + HDMI_1680x720p30_64x27 = 81, + HDMI_1680x720p50_64x27 = 82, + HDMI_1680x720p60_64x27 = 83, + HDMI_1680x720p100_64x27 = 84, + HDMI_1680x720p120_64x27 = 85, + HDMI_2560x1080p24_64x27 = 86, + HDMI_2560x1080p25_64x27 = 87, + HDMI_2560x1080p30_64x27 = 88, + HDMI_2560x1080p50_64x27 = 89, + HDMI_2560x1080p60_64x27 = 90, + HDMI_2560x1080p100_64x27 = 91, + HDMI_2560x1080p120_64x27 = 92, + HDMI_3840x2160p24_16x9 = 93, + HDMI_3840x2160p25_16x9 = 94, + HDMI_3840x2160p30_16x9 = 95, + HDMI_3840x2160p50_16x9 = 96, + HDMI_3840x2160p60_16x9 = 97, + HDMI_4096x2160p24_256x135 = 98, + HDMI_4096x2160p25_256x135 = 99, + HDMI_4096x2160p30_256x135 = 100, + HDMI_4096x2160p50_256x135 = 101, + HDMI_4096x2160p60_256x135 = 102, + HDMI_3840x2160p24_64x27 = 103, + HDMI_3840x2160p25_64x27 = 104, + HDMI_3840x2160p30_64x27 = 105, + HDMI_3840x2160p50_64x27 = 106, + HDMI_3840x2160p60_64x27 = 107, + HDMI_RESERVED = 108, + /* + the following vic is for those y420 mode + they are all beyond OFFSET_HDMITX_VIC420(0x1000) + and they has same vic with normal vic in the lower bytes. + */ + HDMI_VIC_Y420 = HDMITX_VIC420_OFFSET, + HDMI_3840x2160p50_16x9_Y420 = + HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_16x9, + HDMI_3840x2160p60_16x9_Y420 = + HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_16x9, + HDMI_4096x2160p50_256x135_Y420 = + HDMITX_VIC420_OFFSET + HDMI_4096x2160p50_256x135, + HDMI_4096x2160p60_256x135_Y420 = + HDMITX_VIC420_OFFSET + HDMI_4096x2160p60_256x135, + HDMI_3840x2160p50_64x27_Y420 = + HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_64x27, + HDMI_3840x2160p60_64x27_Y420 = + HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_64x27, + HDMIV_640x480p60hz = HDMITX_VESA_OFFSET, + HDMIV_800x480p60hz, + HDMIV_800x600p60hz, + HDMIV_852x480p60hz, + HDMIV_854x480p60hz, + HDMIV_1024x600p60hz, + HDMIV_1024x768p60hz, + HDMIV_1152x864p75hz, + HDMIV_1280x600p60hz, + HDMIV_1280x768p60hz, + HDMIV_1280x800p60hz, + HDMIV_1280x960p60hz, + HDMIV_1280x1024p60hz, + HDMIV_1360x768p60hz, + HDMIV_1366x768p60hz, + HDMIV_1400x1050p60hz, + HDMIV_1440x900p60hz, + HDMIV_1440x2560p60hz, + HDMIV_1440x2560p70hz, + HDMIV_1600x900p60hz, + HDMIV_1600x1200p60hz, + HDMIV_1680x1050p60hz, + HDMIV_1920x1200p60hz, + HDMIV_2160x1200p90hz, + HDMIV_2560x1080p60hz, + HDMIV_2560x1440p60hz, + HDMIV_2560x1600p60hz, + HDMIV_3440x1440p60hz, + HDMIV_2400x1200p90hz, +}; + +/* Compliance with old definitions */ +#define HDMI_640x480p60 HDMI_640x480p60_4x3 +#define HDMI_480p60 HDMI_720x480p60_4x3 +#define HDMI_480p60_16x9 HDMI_720x480p60_16x9 +#define HDMI_720p60 HDMI_1280x720p60_16x9 +#define HDMI_1080i60 HDMI_1920x1080i60_16x9 +#define HDMI_480i60 HDMI_720x480i60_4x3 +#define HDMI_480i60_16x9 HDMI_720x480i60_16x9 +#define HDMI_480i60_16x9_rpt HDMI_2880x480i60_16x9 +#define HDMI_1440x480p60 HDMI_1440x480p60_4x3 +#define HDMI_1440x480p60_16x9 HDMI_1440x480p60_16x9 +#define HDMI_1080p60 HDMI_1920x1080p60_16x9 +#define HDMI_576p50 HDMI_720x576p50_4x3 +#define HDMI_576p50_16x9 HDMI_720x576p50_16x9 +#define HDMI_720p50 HDMI_1280x720p50_16x9 +#define HDMI_1080i50 HDMI_1920x1080i50_16x9 +#define HDMI_576i50 HDMI_720x576i50_4x3 +#define HDMI_576i50_16x9 HDMI_720x576i50_16x9 +#define HDMI_576i50_16x9_rpt HDMI_2880x576i50_16x9 +#define HDMI_1080p50 HDMI_1920x1080p50_16x9 +#define HDMI_1080p24 HDMI_1920x1080p24_16x9 +#define HDMI_1080p25 HDMI_1920x1080p25_16x9 +#define HDMI_1080p30 HDMI_1920x1080p30_16x9 +#define HDMI_1080p120 HDMI_1920x1080p120_16x9 +#define HDMI_480p60_16x9_rpt HDMI_2880x480p60_16x9 +#define HDMI_576p50_16x9_rpt HDMI_2880x576p50_16x9 +#define HDMI_4k2k_24 HDMI_3840x2160p24_16x9 +#define HDMI_4k2k_25 HDMI_3840x2160p25_16x9 +#define HDMI_4k2k_30 HDMI_3840x2160p30_16x9 +#define HDMI_4k2k_50 HDMI_3840x2160p50_16x9 +#define HDMI_4k2k_60 HDMI_3840x2160p60_16x9 +#define HDMI_4k2k_smpte_24 HDMI_4096x2160p24_256x135 +#define HDMI_4k2k_smpte_50 HDMI_4096x2160p50_256x135 +#define HDMI_4k2k_smpte_60 HDMI_4096x2160p60_256x135 + +/* CEA TIMING STRUCT DEFINITION */ +struct hdmi_cea_timing { + unsigned int pixel_freq; /* Unit: 1000 */ + unsigned int h_freq; /* Unit: Hz */ + unsigned int v_freq; /* Unit: 0.001 Hz */ + unsigned int vsync_polarity:1; /* 1: positive 0: negative */ + unsigned int hsync_polarity:1; + unsigned short h_active; + unsigned short h_total; + unsigned short h_blank; + unsigned short h_front; + unsigned short h_sync; + unsigned short h_back; + unsigned short v_active; + unsigned short v_total; + unsigned short v_blank; + unsigned short v_front; + unsigned short v_sync; + unsigned short v_back; + unsigned short v_sync_ln; +}; + +/* Refer CEA861-D Page 116 Table 55 */ +struct dtd { + unsigned short pixel_clock; + unsigned short h_active; + unsigned short h_blank; + unsigned short v_active; + unsigned short v_blank; + unsigned short h_sync_offset; + unsigned short h_sync; + unsigned short v_sync_offset; + unsigned short v_sync; + unsigned char h_image_size; + unsigned char v_image_size; + unsigned char h_border; + unsigned char v_border; + unsigned char flags; + enum hdmi_vic vic; +}; + +/* Dolby Version support information from EDID*/ +/* Refer to DV Spec version2.9 page26 to page39*/ +enum block_type { + ERROR_NULL = 0, + ERROR_LENGTH, + ERROR_OUI, + ERROR_VER, + CORRECT, +}; + + + +#define DV_IEEE_OUI 0x00D046 +#define HDR10_PLUS_IEEE_OUI 0x90848B + +#define HDMI_PACKET_VEND 1 +#define HDMI_PACKET_DRM 0x86 + +#define CMD_CONF_OFFSET (0x14 << 24) +#define CONF_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x00) + #define CLR_AVI_BT2020 0x0 + #define SET_AVI_BT2020 0x1 +/* set value as COLORSPACE_RGB444, YUV422, YUV444, YUV420 */ +#define CONF_AVI_RGBYCC_INDIC (CMD_CONF_OFFSET + 0X2000 + 0x01) +#define CONF_AVI_Q01 (CMD_CONF_OFFSET + 0X2000 + 0x02) + #define RGB_RANGE_DEFAULT 0 + #define RGB_RANGE_LIM 1 + #define RGB_RANGE_FUL 2 + #define RGB_RANGE_RSVD 3 +#define CONF_AVI_YQ01 (CMD_CONF_OFFSET + 0X2000 + 0x03) + #define YCC_RANGE_LIM 0 + #define YCC_RANGE_FUL 1 + #define YCC_RANGE_RSVD 2 + +struct hdr_info { + unsigned int hdr_sup_eotf_sdr:1; + unsigned int hdr_sup_eotf_hdr:1; + unsigned int hdr_sup_eotf_smpte_st_2084:1; + unsigned int hdr_sup_eotf_hlg:1; + unsigned int hdr_sup_SMD_type1:1; + unsigned char hdr_lum_max; + unsigned char hdr_lum_avg; + unsigned char hdr_lum_min; + unsigned char rawdata[7]; +}; + +struct hdr10_plus_info { + uint32_t ieeeoui; + uint8_t length; + uint8_t application_version; +}; + +enum hdmi_hdr_transfer { + T_UNKNOWN = 0, + T_BT709, + T_UNDEF, + T_BT601, + T_BT470M, + T_BT470BG, + T_SMPTE170M, + T_SMPTE240M, + T_LINEAR, + T_LOG100, + T_LOG316, + T_IEC61966_2_4, + T_BT1361E, + T_IEC61966_2_1, + T_BT2020_10, + T_BT2020_12, + T_SMPTE_ST_2084, + T_SMPTE_ST_28, + T_HLG, +}; + +enum hdmi_hdr_color { + C_UNKNOWN = 0, + C_BT709, + C_UNDEF, + C_BT601, + C_BT470M, + C_BT470BG, + C_SMPTE170M, + C_SMPTE240M, + C_FILM, + C_BT2020, +}; + +/* master_display_info for display device */ +struct master_display_info_s { + u32 present_flag; + u32 features; /* feature bits bt2020/2084 */ + u32 primaries[3][2]; /* normalized 50000 in G,B,R order */ + u32 white_point[2]; /* normalized 50000 */ + u32 luminance[2]; /* max/min lumin, normalized 10000 */ + u32 max_content; /* Maximum Content Light Level */ + u32 max_frame_average; /* Maximum Frame-average Light Level */ +}; + +struct hdr10plus_para { + uint8_t application_version; + uint8_t targeted_max_lum; + uint8_t average_maxrgb; + uint8_t distribution_values[9]; + uint8_t num_bezier_curve_anchors; + uint32_t knee_point_x; + uint32_t knee_point_y; + uint8_t bezier_curve_anchors[9]; + uint8_t graphics_overlay_flag; + uint8_t no_delay_flag; +}; + +struct dv_info { + unsigned char rawdata[27]; + enum block_type block_flag; + uint32_t ieeeoui; + uint8_t ver; /* 0 or 1 or 2*/ + uint8_t length;/*ver1: 15 or 12*/ + + uint8_t sup_yuv422_12bit:1; + /* if as 0, then support RGB tunnel mode */ + uint8_t sup_2160p60hz:1; + /* if as 0, then support 2160p30hz */ + uint8_t sup_global_dimming:1; + uint16_t Rx; + uint16_t Ry; + uint16_t Gx; + uint16_t Gy; + uint16_t Bx; + uint16_t By; + uint16_t Wx; + uint16_t Wy; + uint16_t tminPQ; + uint16_t tmaxPQ; + uint8_t dm_major_ver; + uint8_t dm_minor_ver; + uint8_t dm_version; + uint8_t tmaxLUM; + uint8_t colorimetry:1;/* ver1*/ + uint8_t tminLUM; + uint8_t low_latency;/* ver1_12 and 2*/ + uint8_t sup_backlight_control:1;/*only ver2*/ + uint8_t backlt_min_luma;/*only ver2*/ + uint8_t Interface;/*only ver2*/ + uint8_t sup_10b_12b_444;/*only ver2*/ + uint8_t support_DV_RGB_444_8BIT; + uint8_t support_LL_YCbCr_422_12BIT; + uint8_t support_LL_RGB_444_10BIT; + uint8_t support_LL_RGB_444_12BIT; +}; + +enum eotf_type { + EOTF_T_NULL = 0, + EOTF_T_DOLBYVISION, + EOTF_T_HDR10, + EOTF_T_SDR, + EOTF_T_LL_MODE, + EOTF_T_MAX, +}; + +enum mode_type { + YUV422_BIT12 = 0, + RGB_8BIT, + RGB_10_12BIT, + YUV444_10_12BIT, +}; + +/* Dolby Version VSIF parameter*/ +struct dv_vsif_para { + uint8_t ver; /* 0 or 1 or 2*/ + uint8_t length;/*ver1: 15 or 12*/ + union { + struct { + uint8_t low_latency:1; + uint8_t dobly_vision_signal:1; + uint8_t backlt_ctrl_MD_present:1; + uint8_t auxiliary_MD_present:1; + uint8_t eff_tmax_PQ_hi; + uint8_t eff_tmax_PQ_low; + uint8_t auxiliary_runmode; + uint8_t auxiliary_runversion; + uint8_t auxiliary_debug0; + } ver2; + } vers; +}; + +#define Y420CMDB_MAX 32 +#define VIC_MAX_NUM 256 +struct rx_cap { + unsigned int native_Mode; + /*video*/ + unsigned int VIC[VIC_MAX_NUM]; + unsigned int VIC_count; + unsigned int native_VIC; + /*vendor*/ + unsigned int IEEEOUI; + unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */ + unsigned int HF_IEEEOUI; /* For HDMI Forum */ + unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */ + /* CEA861-F, Table 56, Colorimetry Data Block */ + unsigned int colorimetry_data; + unsigned int scdc_present:1; + unsigned int scdc_rr_capable:1; /* SCDC read request */ + unsigned int lte_340mcsc_scramble:1; + unsigned support_ycbcr444_flag:1; + unsigned support_ycbcr422_flag:1; + unsigned int dc_y444:1; + unsigned int dc_30bit:1; + unsigned int dc_36bit:1; + unsigned int dc_48bit:1; + unsigned int dc_y420:1; + unsigned int dc_30bit_420:1; + unsigned int dc_36bit_420:1; + unsigned int dc_48bit_420:1; + unsigned char edid_version; + unsigned char edid_revision; + unsigned int ColorDeepSupport; + unsigned int Video_Latency; + unsigned int Audio_Latency; + unsigned int Interlaced_Video_Latency; + unsigned int Interlaced_Audio_Latency; + unsigned int threeD_present; + unsigned int threeD_Multi_present; + unsigned int hdmi_vic_LEN; + enum hdmi_vic preferred_mode; + struct dtd dtd[16]; + unsigned char dtd_idx; + unsigned char flag_vfpdb; + unsigned char number_of_dtd; + unsigned char pref_colorspace; + struct hdr_info hdr_info; + struct dv_info dv_info; + struct hdr10_plus_info hdr10plus_info; + /*blk0 check sum*/ + unsigned char chksum; + /*blk0-3 check sum*/ + char checksum[10]; + unsigned char edid_changed; + /* for total = 32*8 = 256 VICs */ + /* for Y420CMDB bitmap */ + unsigned char bitmap_valid; + unsigned char bitmap_length; + unsigned char y420_all_vic; + unsigned char y420cmdb_bitmap[Y420CMDB_MAX]; +}; + +enum color_attr_type { + COLOR_ATTR_YCBCR444_12BIT = 0, + COLOR_ATTR_YCBCR422_12BIT, + COLOR_ATTR_YCBCR420_12BIT, + COLOR_ATTR_RGB_12BIT, + COLOR_ATTR_YCBCR444_10BIT, + COLOR_ATTR_YCBCR422_10BIT, + COLOR_ATTR_YCBCR420_10BIT, + COLOR_ATTR_RGB_10BIT, + COLOR_ATTR_YCBCR444_8BIT, + COLOR_ATTR_YCBCR422_8BIT, + COLOR_ATTR_YCBCR420_8BIT, + COLOR_ATTR_RGB_8BIT, + COLOR_ATTR_RESERVED, +}; + +struct color_attr_to_string { + enum color_attr_type color_attr; + const char *color_attr_string; +}; + +enum hdmi_color_depth { + HDMI_COLOR_DEPTH_24B = 4, + HDMI_COLOR_DEPTH_30B = 5, + HDMI_COLOR_DEPTH_36B = 6, + HDMI_COLOR_DEPTH_48B = 7, +}; + +enum hdmi_color_format { + HDMI_COLOR_FORMAT_RGB, + HDMI_COLOR_FORMAT_422, + HDMI_COLOR_FORMAT_444, + HDMI_COLOR_FORMAT_420, +}; + +enum hdmi_color_range { + HDMI_COLOR_RANGE_LIM, + HDMI_COLOR_RANGE_FUL, +}; + +enum hdmi_audio_packet { + HDMI_AUDIO_PACKET_SMP = 0x02, + HDMI_AUDIO_PACKET_1BT = 0x07, + HDMI_AUDIO_PACKET_DST = 0x08, + HDMI_AUDIO_PACKET_HBR = 0x09, +}; + +enum hdmi_phy_para { + HDMI_PHYPARA_6G = 1, /* 2160p60hz 444 8bit */ + HDMI_PHYPARA_4p5G, /* 2160p50hz 420 12bit */ + HDMI_PHYPARA_3p7G, /* 2160p30hz 444 10bit */ + HDMI_PHYPARA_3G, /* 2160p24hz 444 8bit */ + HDMI_PHYPARA_LT3G, /* 1080p60hz 444 12bit */ + HDMI_PHYPARA_DEF = HDMI_PHYPARA_LT3G, + HDMI_PHYPARA_270M, /* 480p60hz 444 8bit */ +}; + +/* get hdmi cea timing + * t: struct hdmi_cea_timing * + */ +#define GET_TIMING(name) (t->name) + +struct parse_cd { + enum hdmi_color_depth cd; + const char *name; +}; + +struct parse_cs { + enum hdmi_color_format cs; + const char *name; +}; + +struct parse_cr { + enum hdmi_color_format cr; + const char *name; +}; + +#define EDID_BLK_NO 4 +#define EDID_BLK_SIZE 128 +struct hdmi_format_para { + enum hdmi_vic vic; + char *name; /* full name, 1280x720p60hz */ + char *sname; /* short name, 1280x720p60hz -> 720p60hz */ + char ext_name[32]; + enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */ + enum hdmi_color_format cs; /* rgb, y444, y422, y420 */ + enum hdmi_color_range cr; /* limit, full */ + unsigned int pixel_repetition_factor; + unsigned int progress_mode:1; /* 0: Interlace 1: Progressive */ + unsigned int scrambler_en:1; + unsigned int tmds_clk_div40:1; + unsigned int tmds_clk; /* Unit: 1000 */ + struct hdmi_cea_timing timing; +}; + +struct hdmi_support_mode { + enum hdmi_vic vic; + char *sname; + char y420; +}; + +#define DOLBY_VISION_LL_RGB 3 +#define DOLBY_VISION_LL_YUV 2 +#define DOLBY_VISION_STD_ENABLE 1 +#define DOLBY_VISION_DISABLE 0 +#define DOLBY_VISION_ENABLE 1 + +#define HDMI_IEEEOUI 0x000C03 +#define MODE_LEN 32 +#define VESA_MAX_TIMING 64 + +typedef struct input_hdmi_data { + char ubootenv_hdmimode[MODE_LEN]; + char ubootenv_colorattribute[MODE_LEN]; + int ubootenv_dv_type; + #if 0 + bool isbestpolicy; + bool isSupport4K30Hz; + bool isSupport4K; + bool isDeepColor; + bool isframeratepriority; + bool isLowPowerMode; + #endif + struct rx_cap *pRXCap; +} hdmi_data_t; + +typedef struct scene_output_info { + char final_displaymode[MODE_LEN]; + char final_deepcolor[MODE_LEN]; + int final_dv_type; +} scene_output_info_t; + +struct dispmode_vic { + const char *disp_mode; + enum hdmi_vic VIC; +}; + +#endif +
diff --git a/include/amlogic/media/vout/hdmitx/hdmitx.h b/include/amlogic/media/vout/hdmitx/hdmitx.h new file mode 100644 index 0000000..e7e5ba5 --- /dev/null +++ b/include/amlogic/media/vout/hdmitx/hdmitx.h
@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMITX_H_ +#define __HDMITX_H_ +#include "hdmi_common.h" +#include "hdmitx_module.h" +#include "hdmitx_reg.h" +#include "mach_reg.h" + +int hdmitx_likely_frac_rate_mode(char *m); +int hdmi_outputmode_check(char *mode, unsigned int frac); + +#endif
diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_ext.h b/include/amlogic/media/vout/hdmitx/hdmitx_ext.h new file mode 100644 index 0000000..3bb671a --- /dev/null +++ b/include/amlogic/media/vout/hdmitx/hdmitx_ext.h
@@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMITX_EXT_H__ +#define __HDMITX_EXT_H__ + +void hdmitx_init(void); + +#endif
diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_module.h b/include/amlogic/media/vout/hdmitx/hdmitx_module.h new file mode 100644 index 0000000..a4a6ff8 --- /dev/null +++ b/include/amlogic/media/vout/hdmitx/hdmitx_module.h
@@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __HDMITX_MODULE_H__ +#define __HDMITX_MODULE_H__ + +#include "hdmi_common.h" +#include "hdmitx_ext.h" + +struct hdmitx_dev { + unsigned char rx_edid[512]; /* some RX may exceeds 256Bytes */ + struct { + int (*get_hpd_state)(void); + int (*read_edid)(unsigned char *buf, unsigned char addr, + unsigned char blk_no); + void (*turn_off)(void); + void (*list_support_modes)(void); + void (*dump_regs)(void); + void (*test_bist)(unsigned int mode); + void (*test_prbs)(void); + void (*set_div40)(bool div40); + void (*output_blank)(unsigned int blank); + } hwop; + unsigned char rawedid[EDID_BLK_SIZE * EDID_BLK_NO]; + struct rx_cap RXCap; + struct hdmi_format_para *para; + enum hdmi_vic vic; + unsigned int frac_rate_policy; + unsigned int mode420; + unsigned int dc30; + enum eotf_type hdmi_current_eotf_type; + enum mode_type hdmi_current_tunnel_mode; + /* Add dongle_mode, clock, phy may be different from mbox */ + unsigned int dongle_mode; +}; + +struct hdmitx_dev *hdmitx_get_hdev(void); + +struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic); +enum hdmi_vic hdmi_get_fmt_vic(char const *name); +void hdmi_parse_attr(struct hdmi_format_para *para, char const *name); +int hdmitx_edid_VIC_support(enum hdmi_vic vic); +enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode); +const char *hdmitx_edid_vic_tab_map_string(enum hdmi_vic vic); +const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic); +bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev, + struct hdmi_format_para *para); +enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev, + const char *disp_mode, char force_flag); +bool edid_parsing_ok(struct hdmitx_dev *hdev); +bool is_dolby_enabled(void); +bool is_tv_support_dv(struct hdmitx_dev *hdev); +void dolbyvision_scene_process(hdmi_data_t *hdmi_data, + scene_output_info_t *output_info); +void sdr_scene_process(hdmi_data_t *hdmi_data, + scene_output_info_t *output_info); +void get_hdmi_data(struct hdmitx_dev *hdev, hdmi_data_t *data); +bool pre_process_str(char *name); +struct hdmi_format_para *hdmi_tst_fmt_name(char const *name, char const *attr); +bool is_supported_mode_attr(hdmi_data_t *hdmi_data, char *mode_attr); +int get_ubootenv_dv_type(void); +void hdmi_tx_set(struct hdmitx_dev *hdev); +/* Parsing RAW EDID data from edid to pRXCap */ +unsigned int hdmi_edid_parsing(unsigned char *edid, struct rx_cap *pRXCap); +struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t); +bool hdmimode_is_interlaced(enum hdmi_vic vic); +void hdmitx_ddc_init(void); +void hdmitx_set_clk(struct hdmitx_dev *hdev); +void hdmitx_turnoff(void); +int hdmitx_get_hpd_state(void); +void hdmitx_prbs(void); +unsigned int hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data, + unsigned int mask); +void hdmitx_hdcp_init(void); +void hdmitx_set_phypara(enum hdmi_phy_para mode); +void hdmitx_test_prbs(void); +void hdmitx_set_div40(bool div40); + +extern void hdmitx_set_drm_pkt(struct master_display_info_s *data); +bool hdmitx_find_vendor(struct hdmitx_dev *hdev); +#ifndef CONFIG_AML_HDMITX20 +void __attribute__((weak))hdmitx_set_drm_pkt(struct master_display_info_s *data) +{ +} +#endif + +void hdmitx_set_vsif_pkt(enum eotf_type type, enum mode_type tunnel_mode, + struct dv_vsif_para *data); +void hdmitx_set_hdr10plus_pkt(unsigned int flag, + struct hdr10plus_para *data); + +#ifndef printk +#define printk printf +#endif +#ifndef pr_info +#define pr_info printf +#endif + +#define hdmitx_debug() /* printf("hd: %s[%d]\n", __func__, __LINE__) */ + +extern struct hdr_info *hdmitx_get_rx_hdr_info(void); +#ifndef CONFIG_AML_HDMITX20 +struct hdr_info * __attribute__((weak))hdmitx_get_rx_hdr_info(void) +{ + return NULL; +} +#endif + +#endif
diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_reg.h b/include/amlogic/media/vout/hdmitx/hdmitx_reg.h new file mode 100644 index 0000000..ebac0bc --- /dev/null +++ b/include/amlogic/media/vout/hdmitx/hdmitx_reg.h
@@ -0,0 +1,1026 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _HDMI_TX_REG_H +#define _HDMI_TX_REG_H + +/* TOP-level wrapper registers addresses */ +/* bit24: 1 means secure access */ +/* bit28: 1 means DWC, 0 means TOP */ +#define SEC_OFFSET (0x1UL << 24) +#define TOP_OFFSET_MASK (0x0UL << 24) +#define TOP_SEC_OFFSET_MASK ((TOP_OFFSET_MASK) | (SEC_OFFSET)) +#define DWC_OFFSET_MASK (0x10UL << 24) +#define DWC_SEC_OFFSET_MASK ((DWC_OFFSET_MASK) | (SEC_OFFSET)) + +/* Bit 7 RW Reserved. Default 1. */ +/* Bit 6 RW Reserved. Default 1. */ +/* Bit 5 RW Reserved. Default 1. */ +/* Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. + * Default 1. + * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; + * 0=Release from reset. Default 1. + * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset. + * Default 1. + * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset; + * 0=Release from reset. Default 1. + * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset; + * 0=Release from reset. Default 1. + */ +#define HDMITX_TOP_SW_RESET (TOP_OFFSET_MASK + 0x000) + +/* Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. */ +/* Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. */ +/* Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. */ +/* Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. */ +/* Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. */ +/* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. */ +/* Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. */ +/* Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. */ +/* Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. */ +/* Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. */ +#define HDMITX_TOP_CLK_CNTL (TOP_OFFSET_MASK + 0x001) + +/* Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. */ +/* Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. */ +#define HDMITX_TOP_HPD_FILTER (TOP_OFFSET_MASK + 0x002) + +/* intr_maskn: MASK_N, one bit per interrupt source. + * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. + * [ 4] hdcp22_rndnum_err + * [ 3] nonce_rfrsh_rise + * [ 2] hpd_fall_intr + * [ 1] hpd_rise_intr + * [ 0] core_intr + */ +#define HDMITX_TOP_INTR_MASKN (TOP_OFFSET_MASK + 0x003) + +/* Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt + * bit, read back the interrupt status. */ +/* Bit 31 R IP interrupt status */ +/* Bit 2 RW hpd_fall */ +/* Bit 1 RW hpd_rise */ +/* Bit 0 RW IP interrupt */ +#define HDMITX_TOP_INTR_STAT (TOP_OFFSET_MASK + 0x004) + +/* [4] hdcp22_rndnum_err */ +/* [3] nonce_rfrsh_rise */ +/* [2] hpd_fall */ +/* [1] hpd_rise */ +/* [0] core_intr_rise */ +#define HDMITX_TOP_INTR_STAT_CLR (TOP_OFFSET_MASK + 0x005) + +/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; + * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. + * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern + * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. + * Bit 8 RW shift_pttn_en: 1= Eanble shift pattern generator; 0=Disable. + * Default 0. + * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0. + * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern; + * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0. + * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0. + */ +#define HDMITX_TOP_BIST_CNTL (TOP_OFFSET_MASK + 0x006) + +/* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */ +/* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */ +/* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */ +#define HDMITX_TOP_SHIFT_PTTN_012 (TOP_OFFSET_MASK + 0x007) + +/* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */ +/* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */ +/* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */ +#define HDMITX_TOP_SHIFT_PTTN_345 (TOP_OFFSET_MASK + 0x008) + +/* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */ +/* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */ +#define HDMITX_TOP_SHIFT_PTTN_67 (TOP_OFFSET_MASK + 0x009) + +/* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */ +/* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */ +#define HDMITX_TOP_TMDS_CLK_PTTN_01 (TOP_OFFSET_MASK + 0x00A) + +/* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */ +/* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ +#define HDMITX_TOP_TMDS_CLK_PTTN_23 (TOP_OFFSET_MASK + 0x00B) + +/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, + * used when TMDS CLK rate = TMDS character rate /4. Default 0. + * Bit 0 R Reserved. Default 0. + */ +/* [ 1] shift_tmds_clk_pttn */ +/* [ 0] load_tmds_clk_pttn */ +#define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (TOP_OFFSET_MASK + 0x00C) + +/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM + * failure, write 1 to clear the failure flag. Default 0. + */ +#define HDMITX_TOP_REVOCMEM_STAT (TOP_OFFSET_MASK + 0x00D) + +/* Bit 0 R filtered HPD status. */ +#define HDMITX_TOP_STAT0 (TOP_OFFSET_MASK + 0x00E) +#define HDMITX_TOP_SKP_CNTL_STAT (TOP_SEC_OFFSET_MASK + 0x010) +#define HDMITX_TOP_NONCE_0 (TOP_SEC_OFFSET_MASK + 0x011) +#define HDMITX_TOP_NONCE_1 (TOP_SEC_OFFSET_MASK + 0x012) +#define HDMITX_TOP_NONCE_2 (TOP_SEC_OFFSET_MASK + 0x013) +#define HDMITX_TOP_NONCE_3 (TOP_SEC_OFFSET_MASK + 0x014) +#define HDMITX_TOP_PKF_0 (TOP_SEC_OFFSET_MASK + 0x015) +#define HDMITX_TOP_PKF_1 (TOP_SEC_OFFSET_MASK + 0x016) +#define HDMITX_TOP_PKF_2 (TOP_SEC_OFFSET_MASK + 0x017) +#define HDMITX_TOP_PKF_3 (TOP_SEC_OFFSET_MASK + 0x018) +#define HDMITX_TOP_DUK_0 (TOP_SEC_OFFSET_MASK + 0x019) +#define HDMITX_TOP_DUK_1 (TOP_SEC_OFFSET_MASK + 0x01A) +#define HDMITX_TOP_DUK_2 (TOP_SEC_OFFSET_MASK + 0x01B) +#define HDMITX_TOP_DUK_3 (TOP_SEC_OFFSET_MASK + 0x01C) +/* [26:24] infilter_ddc_intern_clk_divide */ +/* [23:16] infilter_ddc_sample_clk_divide */ +/* [10: 8] infilter_cec_intern_clk_divide */ +/* [ 7: 0] infilter_cec_sample_clk_divide */ +#define HDMITX_TOP_INFILTER (TOP_OFFSET_MASK + 0x01D) +#define HDMITX_TOP_NSEC_SCRATCH (TOP_OFFSET_MASK + 0x01E) +#define HDMITX_TOP_SEC_SCRATCH (TOP_SEC_OFFSET_MASK + 0x01F) +#define HDMITX_TOP_EMP_CNTL0 (TOP_OFFSET_MASK + 0x020) +#define HDMITX_TOP_EMP_CNTL1 (TOP_OFFSET_MASK + 0x021) +#define HDMITX_TOP_EMP_MEMADDR_START (TOP_OFFSET_MASK + 0x022) +#define HDMITX_TOP_EMP_STAT0 (TOP_OFFSET_MASK + 0x023) +#define HDMITX_TOP_EMP_STAT1 (TOP_OFFSET_MASK + 0x024) +#define HDMITX_TOP_AXI_ASYNC_CNTL0 (TOP_OFFSET_MASK + 0x025) +#define HDMITX_TOP_AXI_ASYNC_CNTL1 (TOP_OFFSET_MASK + 0x026) +#define HDMITX_TOP_AXI_ASYNC_STAT0 (TOP_OFFSET_MASK + 0x027) +#define HDMITX_TOP_I2C_BUSY_CNT_MAX (TOP_OFFSET_MASK + 0x028) +#define HDMITX_TOP_I2C_BUSY_CNT_STAT (TOP_OFFSET_MASK + 0x029) +#define HDMITX_TOP_HDCP22_BSOD (TOP_OFFSET_MASK + 0x02A) +#define HDMITX_TOP_DDC_CNTL (TOP_OFFSET_MASK + 0x02B) +#define HDMITX_TOP_REVOCMEM_ADDR_S (TOP_OFFSET_MASK + 0x2000 >> 2) +#define HDMITX_TOP_REVOCMEM_ADDR_E (TOP_OFFSET_MASK + 0x365E >> 2) + +#define HDMITX_TOP_DONT_TOUCH0 (TOP_OFFSET_MASK + 0x0FE) +#define HDMITX_TOP_DONT_TOUCH1 (TOP_OFFSET_MASK + 0x0FF) + +/* DWC_HDMI_TX Controller registers addresses */ + +/* Identification Registers */ +#define HDMITX_DWC_DESIGN_ID (DWC_OFFSET_MASK + 0x0000) +#define HDMITX_DWC_REVISION_ID (DWC_OFFSET_MASK + 0x0001) +#define HDMITX_DWC_PRODUCT_ID0 (DWC_OFFSET_MASK + 0x0002) +#define HDMITX_DWC_PRODUCT_ID1 (DWC_OFFSET_MASK + 0x0003) +#define HDMITX_DWC_CONFIG0_ID (DWC_OFFSET_MASK + 0x0004) +#define HDMITX_DWC_CONFIG1_ID (DWC_OFFSET_MASK + 0x0005) +#define HDMITX_DWC_CONFIG2_ID (DWC_OFFSET_MASK + 0x0006) +#define HDMITX_DWC_CONFIG3_ID (DWC_OFFSET_MASK + 0x0007) + +/* Interrupt Registers */ +#define HDMITX_DWC_IH_FC_STAT0 (DWC_OFFSET_MASK + 0x0100) +#define HDMITX_DWC_IH_FC_STAT1 (DWC_OFFSET_MASK + 0x0101) +#define HDMITX_DWC_IH_FC_STAT2 (DWC_OFFSET_MASK + 0x0102) +#define HDMITX_DWC_IH_AS_STAT0 (DWC_OFFSET_MASK + 0x0103) +#define HDMITX_DWC_IH_PHY_STAT0 (DWC_OFFSET_MASK + 0x0104) +#define HDMITX_DWC_IH_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0105) +#define HDMITX_DWC_IH_CEC_STAT0 (DWC_OFFSET_MASK + 0x0106) +#define HDMITX_DWC_IH_VP_STAT0 (DWC_OFFSET_MASK + 0x0107) +#define HDMITX_DWC_IH_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0108) +#define HDMITX_DWC_IH_DECODE (DWC_OFFSET_MASK + 0x0170) +/* [ 7] mute_AUDI */ +/* [ 6] mute_ACP */ +/* [ 5] mute_HBR */ +/* [ 4] mute_MAS */ +/* [ 3] mute_NVBI */ +/* [ 2] mute_AUDS */ +/* [ 1] mute_ACR */ +/* [ 0] mute_NULL */ +#define HDMITX_DWC_IH_MUTE_FC_STAT0 (DWC_OFFSET_MASK + 0x0180) +/* [ 7] mute_GMD */ +/* [ 6] mute_ISRC1 */ +/* [ 5] mute_ISRC2 */ +/* [ 4] mute_VSD */ +/* [ 3] mute_SPD */ +/* [ 2] mute_AMP */ +/* [ 1] mute_AVI */ +/* [ 0] mute_GCP */ +#define HDMITX_DWC_IH_MUTE_FC_STAT1 (DWC_OFFSET_MASK + 0x0181) +/* [ 1] mute_LowPriority_fifo_full */ +/* [ 0] mute_HighPriority_fifo_full */ +#define HDMITX_DWC_IH_MUTE_FC_STAT2 (DWC_OFFSET_MASK + 0x0182) +/* [ 4] mute_aud_fifo_underrun */ +/* [ 3] mute_aud_fifo_overrun */ +/* [ 2] mute_aud_fifo_empty_thr. oififoemptythr tied to 0. */ +/* [ 1] mute_aud_fifo_empty */ +/* [ 0] mute_aud_fifo_full */ +#define HDMITX_DWC_IH_MUTE_AS_STAT0 (DWC_OFFSET_MASK + 0x0183) +#define HDMITX_DWC_IH_MUTE_PHY_STAT0 (DWC_OFFSET_MASK + 0x0184) +/* [ 2] mute_scdc_readreq */ +/* [ 1] mute_edid_i2c_master_done */ +/* [ 0] mute_edid_i2c_master_error */ +#define HDMITX_DWC_IH_MUTE_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0185) +/* [ 6] cec_wakeup */ +/* [ 5] cec_error_follower */ +/* [ 4] cec_error_initiator */ +/* [ 3] cec_arb_lost */ +/* [ 2] cec_nack */ +/* [ 1] cec_eom */ +/* [ 0] cec_done */ +#define HDMITX_DWC_IH_MUTE_CEC_STAT0 (DWC_OFFSET_MASK + 0x0186) +#define HDMITX_DWC_IH_MUTE_VP_STAT0 (DWC_OFFSET_MASK + 0x0187) +#define HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0188) +/* [ 1] mute_wakeup_interrupt */ +/* [ 0] mute_all_interrupt */ +#define HDMITX_DWC_IH_MUTE (DWC_OFFSET_MASK + 0x01FF) + +/* Video Sampler Registers */ +/* [ 7] internal_de_generator */ +/* [4:0] video_mapping */ +#define HDMITX_DWC_TX_INVID0 (DWC_OFFSET_MASK + 0x0200) +/* [ 2] bcbdata_stuffing */ +/* [ 1] rcrdata_stuffing */ +/* [ 0] gydata_stuffing */ +#define HDMITX_DWC_TX_INSTUFFING (DWC_OFFSET_MASK + 0x0201) +#define HDMITX_DWC_TX_GYDATA0 (DWC_OFFSET_MASK + 0x0202) +#define HDMITX_DWC_TX_GYDATA1 (DWC_OFFSET_MASK + 0x0203) +#define HDMITX_DWC_TX_RCRDATA0 (DWC_OFFSET_MASK + 0x0204) +#define HDMITX_DWC_TX_RCRDATA1 (DWC_OFFSET_MASK + 0x0205) +#define HDMITX_DWC_TX_BCBDATA0 (DWC_OFFSET_MASK + 0x0206) +#define HDMITX_DWC_TX_BCBDATA1 (DWC_OFFSET_MASK + 0x0207) + +/* Video Packetizer Registers */ +#define HDMITX_DWC_VP_STATUS (DWC_OFFSET_MASK + 0x0800) +/* [3:0] desired_pr_factor */ +#define HDMITX_DWC_VP_PR_CD (DWC_OFFSET_MASK + 0x0801) +/* [ 5] default_phase */ +/* [ 2] ycc422_stuffing */ +/* [ 1] pp_stuffing */ +/* [ 0] pr_stuffing */ +#define HDMITX_DWC_VP_STUFF (DWC_OFFSET_MASK + 0x0802) +#define HDMITX_DWC_VP_REMAP (DWC_OFFSET_MASK + 0x0803) +#define HDMITX_DWC_VP_CONF (DWC_OFFSET_MASK + 0x0804) +/* [ 7] mask_int_full_prpt */ +/* [ 6] mask_int_empty_prpt */ +/* [ 5] mask_int_full_ppack */ +/* [ 4] mask_int_empty_ppack */ +/* [ 3] mask_int_full_remap */ +/* [ 2] mask_int_empty_remap */ +/* [ 1] mask_int_full_byp */ +/* [ 0] mask_int_empty_byp */ +#define HDMITX_DWC_VP_MASK (DWC_OFFSET_MASK + 0x0807) + +/* Frmae Composer Registers */ +/* [ 7] HDCP_keepout */ +/* [ 6] vs_in_pol: 0=active low; 1=active high. */ +/* [ 5] hs_in_pol: 0=active low; 1=active high. */ +/* [ 4] de_in_pol: 0=active low; 1=active high. */ +/* [ 3] dvi_modez: 0=dvi; 1=hdmi. */ +/* [ 1] r_v_blank_in_osc */ +/* [ 0] in_I_P: 0=progressive; 1=interlaced. */ +#define HDMITX_DWC_FC_INVIDCONF (DWC_OFFSET_MASK + 0x1000) +/* [7:0] H_in_active[7:0] */ +#define HDMITX_DWC_FC_INHACTV0 (DWC_OFFSET_MASK + 0x1001) +/* [5:0] H_in_active[13:8] */ +#define HDMITX_DWC_FC_INHACTV1 (DWC_OFFSET_MASK + 0x1002) +/* [7:0] H_in_blank[7:0] */ +#define HDMITX_DWC_FC_INHBLANK0 (DWC_OFFSET_MASK + 0x1003) +/* [4:0] H_in_blank[12:8] */ +#define HDMITX_DWC_FC_INHBLANK1 (DWC_OFFSET_MASK + 0x1004) +/* [7:0] V_in_active[7:0] */ +#define HDMITX_DWC_FC_INVACTV0 (DWC_OFFSET_MASK + 0x1005) +/* [4:0] V_in_active[12:8] */ +#define HDMITX_DWC_FC_INVACTV1 (DWC_OFFSET_MASK + 0x1006) +/* [7:0] V_in_blank */ +#define HDMITX_DWC_FC_INVBLANK (DWC_OFFSET_MASK + 0x1007) +/* [7:0] H_in_delay[7:0] */ +#define HDMITX_DWC_FC_HSYNCINDELAY0 (DWC_OFFSET_MASK + 0x1008) +/* [4:0] H_in_delay[12:8] */ +#define HDMITX_DWC_FC_HSYNCINDELAY1 (DWC_OFFSET_MASK + 0x1009) +/* [7:0] H_in_width[7:0] */ +#define HDMITX_DWC_FC_HSYNCINWIDTH0 (DWC_OFFSET_MASK + 0x100A) +/* [1:0] H_in_width[9:8] */ +#define HDMITX_DWC_FC_HSYNCINWIDTH1 (DWC_OFFSET_MASK + 0x100B) +/* [7:0] V_in_delay */ +#define HDMITX_DWC_FC_VSYNCINDELAY (DWC_OFFSET_MASK + 0x100C) +/* [5:0] V_in_width */ +#define HDMITX_DWC_FC_VSYNCINWIDTH (DWC_OFFSET_MASK + 0x100D) +#define HDMITX_DWC_FC_INFREQ0 (DWC_OFFSET_MASK + 0x100E) +#define HDMITX_DWC_FC_INFREQ1 (DWC_OFFSET_MASK + 0x100F) +#define HDMITX_DWC_FC_INFREQ2 (DWC_OFFSET_MASK + 0x1010) +#define HDMITX_DWC_FC_CTRLDUR (DWC_OFFSET_MASK + 0x1011) +#define HDMITX_DWC_FC_EXCTRLDUR (DWC_OFFSET_MASK + 0x1012) +#define HDMITX_DWC_FC_EXCTRLSPAC (DWC_OFFSET_MASK + 0x1013) +#define HDMITX_DWC_FC_CH0PREAM (DWC_OFFSET_MASK + 0x1014) +#define HDMITX_DWC_FC_CH1PREAM (DWC_OFFSET_MASK + 0x1015) +#define HDMITX_DWC_FC_CH2PREAM (DWC_OFFSET_MASK + 0x1016) +/* [3:2] YQ */ +/* [1:0] CN */ +#define HDMITX_DWC_FC_AVICONF3 (DWC_OFFSET_MASK + 0x1017) +/* [ 2] default_phase */ +/* [ 1] set_avmute */ +/* [ 0] clear_avmute */ +#define HDMITX_DWC_FC_GCP (DWC_OFFSET_MASK + 0x1018) +/* [ 7] rgb_ycc_indication[2] */ +/* [ 6] active_format_present */ +/* [5:4] scan_information */ +/* [3:2] bar_information */ +/* [1:0] rgb_ycc_indication[1:0] */ +#define HDMITX_DWC_FC_AVICONF0 (DWC_OFFSET_MASK + 0x1019) +/* [7:6] colorimetry */ +/* [5:4] picture_aspect_ratio */ +/* [3:0] active_aspect_ratio */ +#define HDMITX_DWC_FC_AVICONF1 (DWC_OFFSET_MASK + 0x101A) +/* [ 7] IT_content */ +/* [6:4] extended_colorimetry */ +/* [3:2] quantization_range */ +/* [1:0] non_uniform_picture_scaling */ +#define HDMITX_DWC_FC_AVICONF2 (DWC_OFFSET_MASK + 0x101B) +#define HDMITX_DWC_FC_AVIVID (DWC_OFFSET_MASK + 0x101C) +#define HDMITX_DWC_FC_AVIETB0 (DWC_OFFSET_MASK + 0x101D) +#define HDMITX_DWC_FC_AVIETB1 (DWC_OFFSET_MASK + 0x101E) +#define HDMITX_DWC_FC_AVISBB0 (DWC_OFFSET_MASK + 0x101F) +#define HDMITX_DWC_FC_AVISBB1 (DWC_OFFSET_MASK + 0x1020) +#define HDMITX_DWC_FC_AVIELB0 (DWC_OFFSET_MASK + 0x1021) +#define HDMITX_DWC_FC_AVIELB1 (DWC_OFFSET_MASK + 0x1022) +#define HDMITX_DWC_FC_AVISRB0 (DWC_OFFSET_MASK + 0x1023) +#define HDMITX_DWC_FC_AVISRB1 (DWC_OFFSET_MASK + 0x1024) +/* [3:0] CT: coding type */ +#define HDMITX_DWC_FC_AUDICONF0 (DWC_OFFSET_MASK + 0x1025) +/* [5:4] SS: sampling size */ +/* [2:0] SF: sampling frequency */ +#define HDMITX_DWC_FC_AUDICONF1 (DWC_OFFSET_MASK + 0x1026) +/* CA: channel allocation */ +#define HDMITX_DWC_FC_AUDICONF2 (DWC_OFFSET_MASK + 0x1027) +/* [6:5] LFEPBL: LFE playback info */ +/* [ 4] DM_INH: down mix enable */ +/* [3:0] LSv: Level shift value */ +#define HDMITX_DWC_FC_AUDICONF3 (DWC_OFFSET_MASK + 0x1028) +#define HDMITX_DWC_FC_VSDIEEEID0 (DWC_OFFSET_MASK + 0x1029) +#define HDMITX_DWC_FC_VSDSIZE (DWC_OFFSET_MASK + 0x102A) +#define HDMITX_DWC_FC_VSDIEEEID1 (DWC_OFFSET_MASK + 0x1030) +#define HDMITX_DWC_FC_VSDIEEEID2 (DWC_OFFSET_MASK + 0x1031) +#define HDMITX_DWC_FC_VSDPAYLOAD0 (DWC_OFFSET_MASK + 0x1032) +#define HDMITX_DWC_FC_VSDPAYLOAD1 (DWC_OFFSET_MASK + 0x1033) +#define HDMITX_DWC_FC_VSDPAYLOAD2 (DWC_OFFSET_MASK + 0x1034) +#define HDMITX_DWC_FC_VSDPAYLOAD3 (DWC_OFFSET_MASK + 0x1035) +#define HDMITX_DWC_FC_VSDPAYLOAD4 (DWC_OFFSET_MASK + 0x1036) +#define HDMITX_DWC_FC_VSDPAYLOAD5 (DWC_OFFSET_MASK + 0x1037) +#define HDMITX_DWC_FC_VSDPAYLOAD6 (DWC_OFFSET_MASK + 0x1038) +#define HDMITX_DWC_FC_VSDPAYLOAD7 (DWC_OFFSET_MASK + 0x1039) +#define HDMITX_DWC_FC_VSDPAYLOAD8 (DWC_OFFSET_MASK + 0x103A) +#define HDMITX_DWC_FC_VSDPAYLOAD9 (DWC_OFFSET_MASK + 0x103B) +#define HDMITX_DWC_FC_VSDPAYLOAD10 (DWC_OFFSET_MASK + 0x103C) +#define HDMITX_DWC_FC_VSDPAYLOAD11 (DWC_OFFSET_MASK + 0x103D) +#define HDMITX_DWC_FC_VSDPAYLOAD12 (DWC_OFFSET_MASK + 0x103E) +#define HDMITX_DWC_FC_VSDPAYLOAD13 (DWC_OFFSET_MASK + 0x103F) +#define HDMITX_DWC_FC_VSDPAYLOAD14 (DWC_OFFSET_MASK + 0x1040) +#define HDMITX_DWC_FC_VSDPAYLOAD15 (DWC_OFFSET_MASK + 0x1041) +#define HDMITX_DWC_FC_VSDPAYLOAD16 (DWC_OFFSET_MASK + 0x1042) +#define HDMITX_DWC_FC_VSDPAYLOAD17 (DWC_OFFSET_MASK + 0x1043) +#define HDMITX_DWC_FC_VSDPAYLOAD18 (DWC_OFFSET_MASK + 0x1044) +#define HDMITX_DWC_FC_VSDPAYLOAD19 (DWC_OFFSET_MASK + 0x1045) +#define HDMITX_DWC_FC_VSDPAYLOAD20 (DWC_OFFSET_MASK + 0x1046) +#define HDMITX_DWC_FC_VSDPAYLOAD21 (DWC_OFFSET_MASK + 0x1047) +#define HDMITX_DWC_FC_VSDPAYLOAD22 (DWC_OFFSET_MASK + 0x1048) +#define HDMITX_DWC_FC_VSDPAYLOAD23 (DWC_OFFSET_MASK + 0x1049) +#define HDMITX_DWC_FC_SPDVENDORNAME0 (DWC_OFFSET_MASK + 0x104A) +#define HDMITX_DWC_FC_SPDVENDORNAME1 (DWC_OFFSET_MASK + 0x104B) +#define HDMITX_DWC_FC_SPDVENDORNAME2 (DWC_OFFSET_MASK + 0x104C) +#define HDMITX_DWC_FC_SPDVENDORNAME3 (DWC_OFFSET_MASK + 0x104D) +#define HDMITX_DWC_FC_SPDVENDORNAME4 (DWC_OFFSET_MASK + 0x104E) +#define HDMITX_DWC_FC_SPDVENDORNAME5 (DWC_OFFSET_MASK + 0x104F) +#define HDMITX_DWC_FC_SPDVENDORNAME6 (DWC_OFFSET_MASK + 0x1050) +#define HDMITX_DWC_FC_SPDVENDORNAME7 (DWC_OFFSET_MASK + 0x1051) +#define HDMITX_DWC_FC_SDPPRODUCTNAME0 (DWC_OFFSET_MASK + 0x1052) +#define HDMITX_DWC_FC_SDPPRODUCTNAME1 (DWC_OFFSET_MASK + 0x1053) +#define HDMITX_DWC_FC_SDPPRODUCTNAME2 (DWC_OFFSET_MASK + 0x1054) +#define HDMITX_DWC_FC_SDPPRODUCTNAME3 (DWC_OFFSET_MASK + 0x1055) +#define HDMITX_DWC_FC_SDPPRODUCTNAME4 (DWC_OFFSET_MASK + 0x1056) +#define HDMITX_DWC_FC_SDPPRODUCTNAME5 (DWC_OFFSET_MASK + 0x1057) +#define HDMITX_DWC_FC_SDPPRODUCTNAME6 (DWC_OFFSET_MASK + 0x1058) +#define HDMITX_DWC_FC_SDPPRODUCTNAME7 (DWC_OFFSET_MASK + 0x1059) +#define HDMITX_DWC_FC_SDPPRODUCTNAME8 (DWC_OFFSET_MASK + 0x105A) +#define HDMITX_DWC_FC_SDPPRODUCTNAME9 (DWC_OFFSET_MASK + 0x105B) +#define HDMITX_DWC_FC_SDPPRODUCTNAME10 (DWC_OFFSET_MASK + 0x105C) +#define HDMITX_DWC_FC_SDPPRODUCTNAME11 (DWC_OFFSET_MASK + 0x105D) +#define HDMITX_DWC_FC_SDPPRODUCTNAME12 (DWC_OFFSET_MASK + 0x105E) +#define HDMITX_DWC_FC_SDPPRODUCTNAME13 (DWC_OFFSET_MASK + 0x105F) +#define HDMITX_DWC_FC_SDPPRODUCTNAME14 (DWC_OFFSET_MASK + 0x1060) +#define HDMITX_DWC_FC_SPDPRODUCTNAME15 (DWC_OFFSET_MASK + 0x1061) +#define HDMITX_DWC_FC_SPDDEVICEINF (DWC_OFFSET_MASK + 0x1062) +/* [7:4] aud_packet_sampflat */ +/* [ 0] aud_packet_layout */ +#define HDMITX_DWC_FC_AUDSCONF (DWC_OFFSET_MASK + 0x1063) +#define HDMITX_DWC_FC_AUDSSTAT (DWC_OFFSET_MASK + 0x1064) +/* [ 7] V3r */ +/* [ 6] V2r */ +/* [ 5] V1r */ +/* [ 4] V0r */ +/* [ 3] V3l */ +/* [ 2] V2l */ +/* [ 1] V1l */ +/* [ 0] V0l */ +#define HDMITX_DWC_FC_AUDSV (DWC_OFFSET_MASK + 0x1065) +#define HDMITX_DWC_FC_AUDSU (DWC_OFFSET_MASK + 0x1066) +#define HDMITX_DWC_FC_AUDSCHNLS0 (DWC_OFFSET_MASK + 0x1067) +#define HDMITX_DWC_FC_AUDSCHNLS1 (DWC_OFFSET_MASK + 0x1068) +#define HDMITX_DWC_FC_AUDSCHNLS2 (DWC_OFFSET_MASK + 0x1069) +#define HDMITX_DWC_FC_AUDSCHNLS3 (DWC_OFFSET_MASK + 0x106A) +#define HDMITX_DWC_FC_AUDSCHNLS4 (DWC_OFFSET_MASK + 0x106B) +#define HDMITX_DWC_FC_AUDSCHNLS5 (DWC_OFFSET_MASK + 0x106C) +#define HDMITX_DWC_FC_AUDSCHNLS6 (DWC_OFFSET_MASK + 0x106D) +#define HDMITX_DWC_FC_AUDSCHNLS7 (DWC_OFFSET_MASK + 0x106E) +#define HDMITX_DWC_FC_AUDSCHNLS8 (DWC_OFFSET_MASK + 0x106F) +#define HDMITX_DWC_FC_DATACH0FILL (DWC_OFFSET_MASK + 0x1070) +#define HDMITX_DWC_FC_DATACH1FILL (DWC_OFFSET_MASK + 0x1071) +#define HDMITX_DWC_FC_DATACH2FILL (DWC_OFFSET_MASK + 0x1072) +#define HDMITX_DWC_FC_CTRLQHIGH (DWC_OFFSET_MASK + 0x1073) +#define HDMITX_DWC_FC_CTRLQLOW (DWC_OFFSET_MASK + 0x1074) +#define HDMITX_DWC_FC_ACP0 (DWC_OFFSET_MASK + 0x1075) +#define HDMITX_DWC_FC_ACP16 (DWC_OFFSET_MASK + 0x1082) +#define HDMITX_DWC_FC_ACP15 (DWC_OFFSET_MASK + 0x1083) +#define HDMITX_DWC_FC_ACP14 (DWC_OFFSET_MASK + 0x1084) +#define HDMITX_DWC_FC_ACP13 (DWC_OFFSET_MASK + 0x1085) +#define HDMITX_DWC_FC_ACP12 (DWC_OFFSET_MASK + 0x1086) +#define HDMITX_DWC_FC_ACP11 (DWC_OFFSET_MASK + 0x1087) +#define HDMITX_DWC_FC_ACP10 (DWC_OFFSET_MASK + 0x1088) +#define HDMITX_DWC_FC_ACP9 (DWC_OFFSET_MASK + 0x1089) +#define HDMITX_DWC_FC_ACP8 (DWC_OFFSET_MASK + 0x108A) +#define HDMITX_DWC_FC_ACP7 (DWC_OFFSET_MASK + 0x108B) +#define HDMITX_DWC_FC_ACP6 (DWC_OFFSET_MASK + 0x108C) +#define HDMITX_DWC_FC_ACP5 (DWC_OFFSET_MASK + 0x108D) +#define HDMITX_DWC_FC_ACP4 (DWC_OFFSET_MASK + 0x108E) +#define HDMITX_DWC_FC_ACP3 (DWC_OFFSET_MASK + 0x108F) +#define HDMITX_DWC_FC_ACP2 (DWC_OFFSET_MASK + 0x1090) +#define HDMITX_DWC_FC_ACP1 (DWC_OFFSET_MASK + 0x1091) +#define HDMITX_DWC_FC_ISCR1_0 (DWC_OFFSET_MASK + 0x1092) +#define HDMITX_DWC_FC_ISCR1_16 (DWC_OFFSET_MASK + 0x1093) +#define HDMITX_DWC_FC_ISCR1_15 (DWC_OFFSET_MASK + 0x1094) +#define HDMITX_DWC_FC_ISCR1_14 (DWC_OFFSET_MASK + 0x1095) +#define HDMITX_DWC_FC_ISCR1_13 (DWC_OFFSET_MASK + 0x1096) +#define HDMITX_DWC_FC_ISCR1_12 (DWC_OFFSET_MASK + 0x1097) +#define HDMITX_DWC_FC_ISCR1_11 (DWC_OFFSET_MASK + 0x1098) +#define HDMITX_DWC_FC_ISCR1_10 (DWC_OFFSET_MASK + 0x1099) +#define HDMITX_DWC_FC_ISCR1_9 (DWC_OFFSET_MASK + 0x109A) +#define HDMITX_DWC_FC_ISCR1_8 (DWC_OFFSET_MASK + 0x109B) +#define HDMITX_DWC_FC_ISCR1_7 (DWC_OFFSET_MASK + 0x109C) +#define HDMITX_DWC_FC_ISCR1_6 (DWC_OFFSET_MASK + 0x109D) +#define HDMITX_DWC_FC_ISCR1_5 (DWC_OFFSET_MASK + 0x109E) +#define HDMITX_DWC_FC_ISCR1_4 (DWC_OFFSET_MASK + 0x109F) +#define HDMITX_DWC_FC_ISCR1_3 (DWC_OFFSET_MASK + 0x10A0) +#define HDMITX_DWC_FC_ISCR1_2 (DWC_OFFSET_MASK + 0x10A1) +#define HDMITX_DWC_FC_ISCR1_1 (DWC_OFFSET_MASK + 0x10A2) +#define HDMITX_DWC_FC_ISCR0_15 (DWC_OFFSET_MASK + 0x10A3) +#define HDMITX_DWC_FC_ISCR0_14 (DWC_OFFSET_MASK + 0x10A4) +#define HDMITX_DWC_FC_ISCR0_13 (DWC_OFFSET_MASK + 0x10A5) +#define HDMITX_DWC_FC_ISCR0_12 (DWC_OFFSET_MASK + 0x10A6) +#define HDMITX_DWC_FC_ISCR0_11 (DWC_OFFSET_MASK + 0x10A7) +#define HDMITX_DWC_FC_ISCR0_10 (DWC_OFFSET_MASK + 0x10A8) +#define HDMITX_DWC_FC_ISCR0_9 (DWC_OFFSET_MASK + 0x10A9) +#define HDMITX_DWC_FC_ISCR0_8 (DWC_OFFSET_MASK + 0x10AA) +#define HDMITX_DWC_FC_ISCR0_7 (DWC_OFFSET_MASK + 0x10AB) +#define HDMITX_DWC_FC_ISCR0_6 (DWC_OFFSET_MASK + 0x10AC) +#define HDMITX_DWC_FC_ISCR0_5 (DWC_OFFSET_MASK + 0x10AD) +#define HDMITX_DWC_FC_ISCR0_4 (DWC_OFFSET_MASK + 0x10AE) +#define HDMITX_DWC_FC_ISCR0_3 (DWC_OFFSET_MASK + 0x10AF) +#define HDMITX_DWC_FC_ISCR0_2 (DWC_OFFSET_MASK + 0x10B0) +#define HDMITX_DWC_FC_ISCR0_1 (DWC_OFFSET_MASK + 0x10B1) +#define HDMITX_DWC_FC_ISCR0_0 (DWC_OFFSET_MASK + 0x10B2) +/* [ 4] spd_auto */ +/* [ 3] vsd_auto */ +/* [ 2] isrc2_auto */ +/* [ 1] isrc1_auto */ +/* [ 0] acp_auto */ +#define HDMITX_DWC_FC_DATAUTO0 (DWC_OFFSET_MASK + 0x10B3) +#define HDMITX_DWC_FC_DATAUTO1 (DWC_OFFSET_MASK + 0x10B4) +#define HDMITX_DWC_FC_DATAUTO2 (DWC_OFFSET_MASK + 0x10B5) +#define HDMITX_DWC_FC_DATMAN (DWC_OFFSET_MASK + 0x10B6) +/* [ 5] nvbi_auto: insert on Vsync */ +/* [ 4] amp_auto: insert on Vsync */ +/* [ 3] avi_auto: insert on Vsync */ +/* [ 2] gcp_auto: insert on Vsync */ +/* [ 1] audi_auto: insert on Vsync */ +/* [ 0] acr_auto: insert on CTS update. Assert this bit later to avoid + * inital packets with false CTS value + */ +#define HDMITX_DWC_FC_DATAUTO3 (DWC_OFFSET_MASK + 0x10B7) +#define HDMITX_DWC_FC_RDRB0 (DWC_OFFSET_MASK + 0x10B8) +#define HDMITX_DWC_FC_RDRB1 (DWC_OFFSET_MASK + 0x10B9) +#define HDMITX_DWC_FC_RDRB2 (DWC_OFFSET_MASK + 0x10BA) +#define HDMITX_DWC_FC_RDRB3 (DWC_OFFSET_MASK + 0x10BB) +#define HDMITX_DWC_FC_RDRB4 (DWC_OFFSET_MASK + 0x10BC) +#define HDMITX_DWC_FC_RDRB5 (DWC_OFFSET_MASK + 0x10BD) +#define HDMITX_DWC_FC_RDRB6 (DWC_OFFSET_MASK + 0x10BE) +#define HDMITX_DWC_FC_RDRB7 (DWC_OFFSET_MASK + 0x10BF) +#define HDMITX_DWC_FC_RDRB8 (DWC_OFFSET_MASK + 0x10C0) +#define HDMITX_DWC_FC_RDRB9 (DWC_OFFSET_MASK + 0x10C1) +#define HDMITX_DWC_FC_RDRB10 (DWC_OFFSET_MASK + 0x10C2) +#define HDMITX_DWC_FC_RDRB11 (DWC_OFFSET_MASK + 0x10C3) +/* [ 7] AUDI_int_mask */ +/* [ 6] ACP_int_mask */ +/* [ 5] HBR_int_mask */ +/* [ 2] AUDS_int_mask */ +/* [ 1] ACR_int_mask */ +/* [ 0] NULL_int_mask */ +#define HDMITX_DWC_FC_MASK0 (DWC_OFFSET_MASK + 0x10D2) +/* [ 7] GMD_int_mask */ +/* [ 6] ISRC1_int_mask */ +/* [ 5] ISRC2_int_mask */ +/* [ 4] VSD_int_mask */ +/* [ 3] SPD_int_mask */ +/* [ 1] AVI_int_mask */ +/* [ 0] GCP_int_mask */ +#define HDMITX_DWC_FC_MASK1 (DWC_OFFSET_MASK + 0x10D6) +/* [ 1] LowPriority_fifo_full */ +/* [ 0] HighPriority_fifo_full */ +#define HDMITX_DWC_FC_MASK2 (DWC_OFFSET_MASK + 0x10DA) +/* [7:4] incoming_pr_factor */ +/* [3:0] output_pr_factor */ +#define HDMITX_DWC_FC_PRCONF (DWC_OFFSET_MASK + 0x10E0) +/* [ 4] scrambler_ucp_line */ +/* [ 0] scrambler_en. Only update this bit once we've sent SCDC message*/ +#define HDMITX_DWC_FC_SCRAMBLER_CTRL (DWC_OFFSET_MASK + 0x10E1) +#define HDMITX_DWC_FC_MULTISTREAM_CTRL (DWC_OFFSET_MASK + 0x10E2) +/* [ 6] nvbi_tx_en */ +/* [ 5] amp_tx_en */ +/* [ 4] aut_tx_en */ +/* [ 3] audi_tx_en */ +/* [ 2] avi_tx_en */ +/* [ 1] gcp_tx_en */ +/* [ 0] acr_tx_en */ +#define HDMITX_DWC_FC_PACKET_TX_EN (DWC_OFFSET_MASK + 0x10E3) +/* [ 1] actspc_hdlr_tgl */ +/* [ 0] actspc_hdlr_en */ +#define HDMITX_DWC_FC_ACTSPC_HDLR_CFG (DWC_OFFSET_MASK + 0x10E8) +#define HDMITX_DWC_FC_INVACT_2D_0 (DWC_OFFSET_MASK + 0x10E9) +/* [3:0] fc_invact_2d_0[11:8] */ +/* [7:0] fc_invact_2d_0[7:0] */ +#define HDMITX_DWC_FC_INVACT_2D_1 (DWC_OFFSET_MASK + 0x10EA) + +#define HDMITX_DWC_FC_GMD_STAT (DWC_OFFSET_MASK + 0x1100) +#define HDMITX_DWC_FC_GMD_EN (DWC_OFFSET_MASK + 0x1101) +#define HDMITX_DWC_FC_GMD_UP (DWC_OFFSET_MASK + 0x1102) +#define HDMITX_DWC_FC_GMD_CONF (DWC_OFFSET_MASK + 0x1103) +#define HDMITX_DWC_FC_GMD_HB (DWC_OFFSET_MASK + 0x1104) +#define HDMITX_DWC_FC_GMD_PB0 (DWC_OFFSET_MASK + 0x1105) +#define HDMITX_DWC_FC_GMD_PB1 (DWC_OFFSET_MASK + 0x1106) +#define HDMITX_DWC_FC_GMD_PB2 (DWC_OFFSET_MASK + 0x1107) +#define HDMITX_DWC_FC_GMD_PB3 (DWC_OFFSET_MASK + 0x1108) +#define HDMITX_DWC_FC_GMD_PB4 (DWC_OFFSET_MASK + 0x1109) +#define HDMITX_DWC_FC_GMD_PB5 (DWC_OFFSET_MASK + 0x110A) +#define HDMITX_DWC_FC_GMD_PB6 (DWC_OFFSET_MASK + 0x110B) +#define HDMITX_DWC_FC_GMD_PB7 (DWC_OFFSET_MASK + 0x110C) +#define HDMITX_DWC_FC_GMD_PB8 (DWC_OFFSET_MASK + 0x110D) +#define HDMITX_DWC_FC_GMD_PB9 (DWC_OFFSET_MASK + 0x110E) +#define HDMITX_DWC_FC_GMD_PB10 (DWC_OFFSET_MASK + 0x110F) +#define HDMITX_DWC_FC_GMD_PB11 (DWC_OFFSET_MASK + 0x1110) +#define HDMITX_DWC_FC_GMD_PB12 (DWC_OFFSET_MASK + 0x1111) +#define HDMITX_DWC_FC_GMD_PB13 (DWC_OFFSET_MASK + 0x1112) +#define HDMITX_DWC_FC_GMD_PB14 (DWC_OFFSET_MASK + 0x1113) +#define HDMITX_DWC_FC_GMD_PB15 (DWC_OFFSET_MASK + 0x1114) +#define HDMITX_DWC_FC_GMD_PB16 (DWC_OFFSET_MASK + 0x1115) +#define HDMITX_DWC_FC_GMD_PB17 (DWC_OFFSET_MASK + 0x1116) +#define HDMITX_DWC_FC_GMD_PB18 (DWC_OFFSET_MASK + 0x1117) +#define HDMITX_DWC_FC_GMD_PB19 (DWC_OFFSET_MASK + 0x1118) +#define HDMITX_DWC_FC_GMD_PB20 (DWC_OFFSET_MASK + 0x1119) +#define HDMITX_DWC_FC_GMD_PB21 (DWC_OFFSET_MASK + 0x111A) +#define HDMITX_DWC_FC_GMD_PB22 (DWC_OFFSET_MASK + 0x111B) +#define HDMITX_DWC_FC_GMD_PB23 (DWC_OFFSET_MASK + 0x111C) +#define HDMITX_DWC_FC_GMD_PB24 (DWC_OFFSET_MASK + 0x111D) +#define HDMITX_DWC_FC_GMD_PB25 (DWC_OFFSET_MASK + 0x111E) +#define HDMITX_DWC_FC_GMD_PB26 (DWC_OFFSET_MASK + 0x111F) +#define HDMITX_DWC_FC_GMD_PB27 (DWC_OFFSET_MASK + 0x1120) + +/* Audio Metadata Packet Registers */ +#define HDMITX_DWC_FC_AMP_HB01 (DWC_OFFSET_MASK + 0x1128) +#define HDMITX_DWC_FC_AMP_HB02 (DWC_OFFSET_MASK + 0x1129) +#define HDMITX_DWC_FC_AMP_PB00 (DWC_OFFSET_MASK + 0x112A) +#define HDMITX_DWC_FC_AMP_PB01 (DWC_OFFSET_MASK + 0x112B) +#define HDMITX_DWC_FC_AMP_PB02 (DWC_OFFSET_MASK + 0x112C) +#define HDMITX_DWC_FC_AMP_PB03 (DWC_OFFSET_MASK + 0x112D) +#define HDMITX_DWC_FC_AMP_PB04 (DWC_OFFSET_MASK + 0x112E) +#define HDMITX_DWC_FC_AMP_PB05 (DWC_OFFSET_MASK + 0x112F) +#define HDMITX_DWC_FC_AMP_PB06 (DWC_OFFSET_MASK + 0x1130) +#define HDMITX_DWC_FC_AMP_PB07 (DWC_OFFSET_MASK + 0x1131) +#define HDMITX_DWC_FC_AMP_PB08 (DWC_OFFSET_MASK + 0x1132) +#define HDMITX_DWC_FC_AMP_PB09 (DWC_OFFSET_MASK + 0x1133) +#define HDMITX_DWC_FC_AMP_PB10 (DWC_OFFSET_MASK + 0x1134) +#define HDMITX_DWC_FC_AMP_PB11 (DWC_OFFSET_MASK + 0x1135) +#define HDMITX_DWC_FC_AMP_PB12 (DWC_OFFSET_MASK + 0x1136) +#define HDMITX_DWC_FC_AMP_PB13 (DWC_OFFSET_MASK + 0x1137) +#define HDMITX_DWC_FC_AMP_PB14 (DWC_OFFSET_MASK + 0x1138) +#define HDMITX_DWC_FC_AMP_PB15 (DWC_OFFSET_MASK + 0x1139) +#define HDMITX_DWC_FC_AMP_PB16 (DWC_OFFSET_MASK + 0x113A) +#define HDMITX_DWC_FC_AMP_PB17 (DWC_OFFSET_MASK + 0x113B) +#define HDMITX_DWC_FC_AMP_PB18 (DWC_OFFSET_MASK + 0x113C) +#define HDMITX_DWC_FC_AMP_PB19 (DWC_OFFSET_MASK + 0x113D) +#define HDMITX_DWC_FC_AMP_PB20 (DWC_OFFSET_MASK + 0x113E) +#define HDMITX_DWC_FC_AMP_PB21 (DWC_OFFSET_MASK + 0x113F) +#define HDMITX_DWC_FC_AMP_PB22 (DWC_OFFSET_MASK + 0x1140) +#define HDMITX_DWC_FC_AMP_PB23 (DWC_OFFSET_MASK + 0x1141) +#define HDMITX_DWC_FC_AMP_PB24 (DWC_OFFSET_MASK + 0x1142) +#define HDMITX_DWC_FC_AMP_PB25 (DWC_OFFSET_MASK + 0x1143) +#define HDMITX_DWC_FC_AMP_PB26 (DWC_OFFSET_MASK + 0x1144) +#define HDMITX_DWC_FC_AMP_PB27 (DWC_OFFSET_MASK + 0x1145) + +/* NTSC VBI Packet Registers */ +#define HDMITX_DWC_FC_NVBI_HB01 (DWC_OFFSET_MASK + 0x1148) +#define HDMITX_DWC_FC_NVBI_HB02 (DWC_OFFSET_MASK + 0x1149) +#define HDMITX_DWC_FC_NVBI_PB01 (DWC_OFFSET_MASK + 0x114A) +#define HDMITX_DWC_FC_NVBI_PB02 (DWC_OFFSET_MASK + 0x114B) +#define HDMITX_DWC_FC_NVBI_PB03 (DWC_OFFSET_MASK + 0x114C) +#define HDMITX_DWC_FC_NVBI_PB04 (DWC_OFFSET_MASK + 0x114D) +#define HDMITX_DWC_FC_NVBI_PB05 (DWC_OFFSET_MASK + 0x114E) +#define HDMITX_DWC_FC_NVBI_PB06 (DWC_OFFSET_MASK + 0x114F) +#define HDMITX_DWC_FC_NVBI_PB07 (DWC_OFFSET_MASK + 0x1150) +#define HDMITX_DWC_FC_NVBI_PB08 (DWC_OFFSET_MASK + 0x1151) +#define HDMITX_DWC_FC_NVBI_PB09 (DWC_OFFSET_MASK + 0x1152) +#define HDMITX_DWC_FC_NVBI_PB10 (DWC_OFFSET_MASK + 0x1153) +#define HDMITX_DWC_FC_NVBI_PB11 (DWC_OFFSET_MASK + 0x1154) +#define HDMITX_DWC_FC_NVBI_PB12 (DWC_OFFSET_MASK + 0x1155) +#define HDMITX_DWC_FC_NVBI_PB13 (DWC_OFFSET_MASK + 0x1156) +#define HDMITX_DWC_FC_NVBI_PB14 (DWC_OFFSET_MASK + 0x1157) +#define HDMITX_DWC_FC_NVBI_PB15 (DWC_OFFSET_MASK + 0x1158) +#define HDMITX_DWC_FC_NVBI_PB16 (DWC_OFFSET_MASK + 0x1159) +#define HDMITX_DWC_FC_NVBI_PB17 (DWC_OFFSET_MASK + 0x115A) +#define HDMITX_DWC_FC_NVBI_PB18 (DWC_OFFSET_MASK + 0x115B) +#define HDMITX_DWC_FC_NVBI_PB19 (DWC_OFFSET_MASK + 0x115C) +#define HDMITX_DWC_FC_NVBI_PB20 (DWC_OFFSET_MASK + 0x115D) +#define HDMITX_DWC_FC_NVBI_PB21 (DWC_OFFSET_MASK + 0x115E) +#define HDMITX_DWC_FC_NVBI_PB22 (DWC_OFFSET_MASK + 0x115F) +#define HDMITX_DWC_FC_NVBI_PB23 (DWC_OFFSET_MASK + 0x1160) +#define HDMITX_DWC_FC_NVBI_PB24 (DWC_OFFSET_MASK + 0x1161) +#define HDMITX_DWC_FC_NVBI_PB25 (DWC_OFFSET_MASK + 0x1162) +#define HDMITX_DWC_FC_NVBI_PB26 (DWC_OFFSET_MASK + 0x1163) +#define HDMITX_DWC_FC_NVBI_PB27 (DWC_OFFSET_MASK + 0x1164) +#define HDMITX_DWC_FC_DRM_HB01 (DWC_OFFSET_MASK + 0x1168) +#define HDMITX_DWC_FC_DRM_HB02 (DWC_OFFSET_MASK + 0x1169) +#define HDMITX_DWC_FC_DRM_PB00 (DWC_OFFSET_MASK + 0x116A) +#define HDMITX_DWC_FC_DRM_PB01 (DWC_OFFSET_MASK + 0x116B) +#define HDMITX_DWC_FC_DRM_PB02 (DWC_OFFSET_MASK + 0x116C) +#define HDMITX_DWC_FC_DRM_PB03 (DWC_OFFSET_MASK + 0x116D) +#define HDMITX_DWC_FC_DRM_PB04 (DWC_OFFSET_MASK + 0x116E) +#define HDMITX_DWC_FC_DRM_PB05 (DWC_OFFSET_MASK + 0x116F) +#define HDMITX_DWC_FC_DRM_PB06 (DWC_OFFSET_MASK + 0x1170) +#define HDMITX_DWC_FC_DRM_PB07 (DWC_OFFSET_MASK + 0x1171) +#define HDMITX_DWC_FC_DRM_PB08 (DWC_OFFSET_MASK + 0x1172) +#define HDMITX_DWC_FC_DRM_PB09 (DWC_OFFSET_MASK + 0x1173) +#define HDMITX_DWC_FC_DRM_PB10 (DWC_OFFSET_MASK + 0x1174) +#define HDMITX_DWC_FC_DRM_PB11 (DWC_OFFSET_MASK + 0x1175) +#define HDMITX_DWC_FC_DRM_PB12 (DWC_OFFSET_MASK + 0x1176) +#define HDMITX_DWC_FC_DRM_PB13 (DWC_OFFSET_MASK + 0x1177) +#define HDMITX_DWC_FC_DRM_PB14 (DWC_OFFSET_MASK + 0x1178) +#define HDMITX_DWC_FC_DRM_PB15 (DWC_OFFSET_MASK + 0x1179) +#define HDMITX_DWC_FC_DRM_PB16 (DWC_OFFSET_MASK + 0x117A) +#define HDMITX_DWC_FC_DRM_PB17 (DWC_OFFSET_MASK + 0x117B) +#define HDMITX_DWC_FC_DRM_PB18 (DWC_OFFSET_MASK + 0x117C) +#define HDMITX_DWC_FC_DRM_PB19 (DWC_OFFSET_MASK + 0x117D) +#define HDMITX_DWC_FC_DRM_PB20 (DWC_OFFSET_MASK + 0x117E) +#define HDMITX_DWC_FC_DRM_PB21 (DWC_OFFSET_MASK + 0x117F) +#define HDMITX_DWC_FC_DRM_PB22 (DWC_OFFSET_MASK + 0x1180) +#define HDMITX_DWC_FC_DRM_PB23 (DWC_OFFSET_MASK + 0x1181) +#define HDMITX_DWC_FC_DRM_PB24 (DWC_OFFSET_MASK + 0x1182) +#define HDMITX_DWC_FC_DRM_PB25 (DWC_OFFSET_MASK + 0x1183) +#define HDMITX_DWC_FC_DRM_PB26 (DWC_OFFSET_MASK + 0x1184) + +#define HDMITX_DWC_FC_DBGFORCE (DWC_OFFSET_MASK + 0x1200) +#define HDMITX_DWC_FC_DBGAUD0CH0 (DWC_OFFSET_MASK + 0x1201) +#define HDMITX_DWC_FC_DBGAUD1CH0 (DWC_OFFSET_MASK + 0x1202) +#define HDMITX_DWC_FC_DBGAUD2CH0 (DWC_OFFSET_MASK + 0x1203) +#define HDMITX_DWC_FC_DBGAUD0CH1 (DWC_OFFSET_MASK + 0x1204) +#define HDMITX_DWC_FC_DBGAUD1CH1 (DWC_OFFSET_MASK + 0x1205) +#define HDMITX_DWC_FC_DBGAUD2CH1 (DWC_OFFSET_MASK + 0x1206) +#define HDMITX_DWC_FC_DBGAUD0CH2 (DWC_OFFSET_MASK + 0x1207) +#define HDMITX_DWC_FC_DBGAUD1CH2 (DWC_OFFSET_MASK + 0x1208) +#define HDMITX_DWC_FC_DBGAUD2CH2 (DWC_OFFSET_MASK + 0x1209) +#define HDMITX_DWC_FC_DBGAUD0CH3 (DWC_OFFSET_MASK + 0x120A) +#define HDMITX_DWC_FC_DBGAUD1CH3 (DWC_OFFSET_MASK + 0x120B) +#define HDMITX_DWC_FC_DBGAUD2CH3 (DWC_OFFSET_MASK + 0x120C) +#define HDMITX_DWC_FC_DBGAUD0CH4 (DWC_OFFSET_MASK + 0x120D) +#define HDMITX_DWC_FC_DBGAUD1CH4 (DWC_OFFSET_MASK + 0x120E) +#define HDMITX_DWC_FC_DBGAUD2CH4 (DWC_OFFSET_MASK + 0x120F) +#define HDMITX_DWC_FC_DBGAUD0CH5 (DWC_OFFSET_MASK + 0x1210) +#define HDMITX_DWC_FC_DBGAUD1CH5 (DWC_OFFSET_MASK + 0x1211) +#define HDMITX_DWC_FC_DBGAUD2CH5 (DWC_OFFSET_MASK + 0x1212) +#define HDMITX_DWC_FC_DBGAUD0CH6 (DWC_OFFSET_MASK + 0x1213) +#define HDMITX_DWC_FC_DBGAUD1CH6 (DWC_OFFSET_MASK + 0x1214) +#define HDMITX_DWC_FC_DBGAUD2CH6 (DWC_OFFSET_MASK + 0x1215) +#define HDMITX_DWC_FC_DBGAUD0CH7 (DWC_OFFSET_MASK + 0x1216) +#define HDMITX_DWC_FC_DBGAUD1CH7 (DWC_OFFSET_MASK + 0x1217) +#define HDMITX_DWC_FC_DBGAUD2CH7 (DWC_OFFSET_MASK + 0x1218) +#define HDMITX_DWC_FC_DBGTMDS0 (DWC_OFFSET_MASK + 0x1219) +#define HDMITX_DWC_FC_DBGTMDS1 (DWC_OFFSET_MASK + 0x121A) +#define HDMITX_DWC_FC_DBGTMDS2 (DWC_OFFSET_MASK + 0x121B) + +/* HDMI Source PHY Registers */ +#define HDMITX_DWC_PHY_CONF0 (DWC_OFFSET_MASK + 0x3000) +#define HDMITX_DWC_PHY_TST0 (DWC_OFFSET_MASK + 0x3001) +#define HDMITX_DWC_PHY_TST1 (DWC_OFFSET_MASK + 0x3002) +#define HDMITX_DWC_PHY_TST2 (DWC_OFFSET_MASK + 0x3003) +#define HDMITX_DWC_PHY_STAT0 (DWC_OFFSET_MASK + 0x3004) +#define HDMITX_DWC_PHY_INT0 (DWC_OFFSET_MASK + 0x3005) +#define HDMITX_DWC_PHY_MASK0 (DWC_OFFSET_MASK + 0x3006) +#define HDMITX_DWC_PHY_POL0 (DWC_OFFSET_MASK + 0x3007) + +/* I2C Master PHY Registers */ +#define HDMITX_DWC_I2CM_PHY_SLAVE (DWC_OFFSET_MASK + 0x3020) +#define HDMITX_DWC_I2CM_PHY_ADDRESS (DWC_OFFSET_MASK + 0x3021) +#define HDMITX_DWC_I2CM_PHY_DATAO_1 (DWC_OFFSET_MASK + 0x3022) +#define HDMITX_DWC_I2CM_PHY_DATAO_0 (DWC_OFFSET_MASK + 0x3023) +#define HDMITX_DWC_I2CM_PHY_DATAI_1 (DWC_OFFSET_MASK + 0x3024) +#define HDMITX_DWC_I2CM_PHY_DATAI_0 (DWC_OFFSET_MASK + 0x3025) +#define HDMITX_DWC_I2CM_PHY_OPERATION (DWC_OFFSET_MASK + 0x3026) +#define HDMITX_DWC_I2CM_PHY_INT (DWC_OFFSET_MASK + 0x3027) +#define HDMITX_DWC_I2CM_PHY_CTLINT (DWC_OFFSET_MASK + 0x3028) +#define HDMITX_DWC_I2CM_PHY_DIV (DWC_OFFSET_MASK + 0x3029) +#define HDMITX_DWC_I2CM_PHY_SOFTRSTZ (DWC_OFFSET_MASK + 0x302A) +#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302B) +#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x302C) +#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x302D) +#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x302E) +#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302F) +#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x3030) +#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x3031) +#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x3032) +#define HDMITX_DWC_I2CM_PHY_SDA_HOLD (DWC_OFFSET_MASK + 0x3033) + +/* Audio Sampler Registers */ + + /* [ 7] sw_audio_fifo_rst */ + /* [ 5] 0=select SPDIF; 1=select I2S. */ + /* [3:0] i2s_in_en: enable it later in test.c */ + +#define HDMITX_DWC_AUD_CONF0 (DWC_OFFSET_MASK + 0x3100) +/* [4:0] i2s_width */ +/* [7:5] i2s_mode: 0=standard I2S mode */ +#define HDMITX_DWC_AUD_CONF1 (DWC_OFFSET_MASK + 0x3101) +/* [ 3] fifo_empty_mask: 0=enable int; 1=mask int. */ +/* [ 2] fifo_full_mask: 0=enable int; 1=mask int. */ +#define HDMITX_DWC_AUD_INT (DWC_OFFSET_MASK + 0x3102) + /* [ 1] NLPCM */ +#define HDMITX_DWC_AUD_CONF2 (DWC_OFFSET_MASK + 0x3103) + +/* [ 4] fifo_overrun_mask: 0=enable int; 1=mask int. + * Enable it later when audio starts. + */ +#define HDMITX_DWC_AUD_INT1 (DWC_OFFSET_MASK + 0x3104) + +#define HDMITX_DWC_AUD_N1 (DWC_OFFSET_MASK + 0x3200) +#define HDMITX_DWC_AUD_N2 (DWC_OFFSET_MASK + 0x3201) +#define HDMITX_DWC_AUD_N3 (DWC_OFFSET_MASK + 0x3202) +#define HDMITX_DWC_AUD_CTS1 (DWC_OFFSET_MASK + 0x3203) +#define HDMITX_DWC_AUD_CTS2 (DWC_OFFSET_MASK + 0x3204) +#define HDMITX_DWC_AUD_CTS3 (DWC_OFFSET_MASK + 0x3205) +#define HDMITX_DWC_AUD_INPUTCLKFS (DWC_OFFSET_MASK + 0x3206) +/* [ 7] sw_audio_fifo_rst */ +#define HDMITX_DWC_AUD_SPDIF0 (DWC_OFFSET_MASK + 0x3300) +/* [4:0] spdif_width */ +/* [ 7] setnlpcm */ +#define HDMITX_DWC_AUD_SPDIF1 (DWC_OFFSET_MASK + 0x3301) +/* [ 3] SPDIF fifo_empty_mask: 0=enable int; 1=mask int. */ +/* [ 2] SPDIF fifo_full_mask: 0=enable int; 1=mask int. */ +#define HDMITX_DWC_AUD_SPDIFINT (DWC_OFFSET_MASK + 0x3302) +/* [ 4] SPDIF fifo_overrun_mask: 0=enable int; 1=mask int. */ +#define HDMITX_DWC_AUD_SPDIFINT1 (DWC_OFFSET_MASK + 0x3303) + +/* Generic Parallel Audio Interface Registers (DWC_OFFSET_MASK + 0x3500) */ +/* Audio DMA Registers (DWC_OFFSET_MASK + 0x3600) */ + +/* Main Controller Registers */ +/* [ 6] hdcpclk_disable */ +/* [ 5] cecclk_disable */ +/* [ 4] cscclk_disable */ +/* [ 3] audclk_disable */ +/* [ 2] prepclk_disable */ +/* [ 1] tmdsclk_disable */ +/* [ 0] pixelclk_disable */ +#define HDMITX_DWC_MC_CLKDIS (DWC_OFFSET_MASK + 0x4001) +/* + * [ 7] gpaswrst_req: 0=generate reset pulse; 1=no reset. + * [ 6] cecswrst_req: 0=generate reset pulse; 1=no reset. + * [ 4] spdifswrst_req: 0=generate reset pulse; 1=no reset. + * [ 3] i2sswrst_req: 0=generate reset pulse; 1=no reset. + * [ 2] prepswrst_req: 0=generate reset pulse; 1=no reset. + * [ 1] tmdsswrst_req: 0=generate reset pulse; 1=no reset. + * [ 0] pixelswrst_req: 0=generate reset pulse; 1=no reset. + */ +#define HDMITX_DWC_MC_SWRSTZREQ (DWC_OFFSET_MASK + 0x4002) +#define HDMITX_DWC_MC_OPCTRL (DWC_OFFSET_MASK + 0x4003) +/* [ 0] CSC enable */ +#define HDMITX_DWC_MC_FLOWCTRL (DWC_OFFSET_MASK + 0x4004) +#define HDMITX_DWC_MC_PHYRSTZ (DWC_OFFSET_MASK + 0x4005) +#define HDMITX_DWC_MC_LOCKONCLOCK (DWC_OFFSET_MASK + 0x4006) + +/* Color Space Converter Registers */ +/* [ 7] csc_limit */ +#define HDMITX_DWC_CSC_CFG (DWC_OFFSET_MASK + 0x4100) +#define HDMITX_DWC_CSC_SCALE (DWC_OFFSET_MASK + 0x4101) +#define HDMITX_DWC_CSC_COEF_A1_MSB (DWC_OFFSET_MASK + 0x4102) +#define HDMITX_DWC_CSC_COEF_A1_LSB (DWC_OFFSET_MASK + 0x4103) +#define HDMITX_DWC_CSC_COEF_A2_MSB (DWC_OFFSET_MASK + 0x4104) +#define HDMITX_DWC_CSC_COEF_A2_LSB (DWC_OFFSET_MASK + 0x4105) +#define HDMITX_DWC_CSC_COEF_A3_MSB (DWC_OFFSET_MASK + 0x4106) +#define HDMITX_DWC_CSC_COEF_A3_LSB (DWC_OFFSET_MASK + 0x4107) +#define HDMITX_DWC_CSC_COEF_A4_MSB (DWC_OFFSET_MASK + 0x4108) +#define HDMITX_DWC_CSC_COEF_A4_LSB (DWC_OFFSET_MASK + 0x4109) +#define HDMITX_DWC_CSC_COEF_B1_MSB (DWC_OFFSET_MASK + 0x410A) +#define HDMITX_DWC_CSC_COEF_B1_LSB (DWC_OFFSET_MASK + 0x410B) +#define HDMITX_DWC_CSC_COEF_B2_MSB (DWC_OFFSET_MASK + 0x410C) +#define HDMITX_DWC_CSC_COEF_B2_LSB (DWC_OFFSET_MASK + 0x410D) +#define HDMITX_DWC_CSC_COEF_B3_MSB (DWC_OFFSET_MASK + 0x410E) +#define HDMITX_DWC_CSC_COEF_B3_LSB (DWC_OFFSET_MASK + 0x410F) +#define HDMITX_DWC_CSC_COEF_B4_MSB (DWC_OFFSET_MASK + 0x4110) +#define HDMITX_DWC_CSC_COEF_B4_LSB (DWC_OFFSET_MASK + 0x4111) +#define HDMITX_DWC_CSC_COEF_C1_MSB (DWC_OFFSET_MASK + 0x4112) +#define HDMITX_DWC_CSC_COEF_C1_LSB (DWC_OFFSET_MASK + 0x4113) +#define HDMITX_DWC_CSC_COEF_C2_MSB (DWC_OFFSET_MASK + 0x4114) +#define HDMITX_DWC_CSC_COEF_C2_LSB (DWC_OFFSET_MASK + 0x4115) +#define HDMITX_DWC_CSC_COEF_C3_MSB (DWC_OFFSET_MASK + 0x4116) +#define HDMITX_DWC_CSC_COEF_C3_LSB (DWC_OFFSET_MASK + 0x4117) +#define HDMITX_DWC_CSC_COEF_C4_MSB (DWC_OFFSET_MASK + 0x4118) +#define HDMITX_DWC_CSC_COEF_C4_LSB (DWC_OFFSET_MASK + 0x4119) +#define HDMITX_DWC_CSC_LIMIT_UP_MSB (DWC_OFFSET_MASK + 0x411A) +#define HDMITX_DWC_CSC_LIMIT_UP_LSB (DWC_OFFSET_MASK + 0x411B) +#define HDMITX_DWC_CSC_LIMIT_DN_MSB (DWC_OFFSET_MASK + 0x411C) +#define HDMITX_DWC_CSC_LIMIT_DN_LSB (DWC_OFFSET_MASK + 0x411D) + +/* HDCP Encryption Engine Registers */ +#define HDMITX_DWC_A_HDCPCFG0 (DWC_SEC_OFFSET_MASK + 0x5000) +/* [ 4] hdcp_lock */ +/* [ 3] dissha1check */ +/* [ 2] ph2upshiftenc */ +/* [ 1] encryptiondisable */ +/* [ 0] swresetn. Write 0 to activate, self-clear to 1. */ +#define HDMITX_DWC_A_HDCPCFG1 (DWC_SEC_OFFSET_MASK + 0x5001) +#define HDMITX_DWC_A_HDCPOBS0 (DWC_OFFSET_MASK + 0x5002) +#define HDMITX_DWC_A_HDCPOBS1 (DWC_OFFSET_MASK + 0x5003) +#define HDMITX_DWC_A_HDCPOBS2 (DWC_OFFSET_MASK + 0x5004) +#define HDMITX_DWC_A_HDCPOBS3 (DWC_OFFSET_MASK + 0x5005) +#define HDMITX_DWC_A_APIINTCLR (DWC_OFFSET_MASK + 0x5006) +#define HDMITX_DWC_A_APIINTSTAT (DWC_OFFSET_MASK + 0x5007) +/* [ 7] hdcp_engaged_int_mask */ +/* [ 6] hdcp_failed_int_mask */ +/* [ 4] i2c_nack_int_mask */ +/* [ 3] lost_arbitration_int_mask */ +/* [ 2] keepout_error_int_mask */ +/* [ 1] ksv_sha1_calc_int_mask */ +/* [ 0] ksv_access_int_mask */ +#define HDMITX_DWC_A_APIINTMSK (DWC_OFFSET_MASK + 0x5008) +/* [6:5] unencryptconf */ +/* [ 4] dataenpol */ +/* [ 3] vsyncpol */ +/* [ 1] hsyncpol */ +#define HDMITX_DWC_A_VIDPOLCFG (DWC_OFFSET_MASK + 0x5009) +#define HDMITX_DWC_A_OESSWCFG (DWC_OFFSET_MASK + 0x500A) +#define HDMITX_DWC_A_COREVERLSB (DWC_OFFSET_MASK + 0x5014) +#define HDMITX_DWC_A_COREVERMSB (DWC_OFFSET_MASK + 0x5015) +/* [ 3] sha1_fail */ +/* [ 2] ksv_ctrl_update */ +/* [ 1] Rsvd for read-only ksv_mem_access */ +/* [ 0] ksv_mem_request */ +#define HDMITX_DWC_A_KSVMEMCTRL (DWC_OFFSET_MASK + 0x5016) + +#define HDMITX_DWC_HDCP_BSTATUS_0 (DWC_OFFSET_MASK + 0x5020) +#define HDMITX_DWC_HDCP_BSTATUS_1 (DWC_OFFSET_MASK + 0x5021) +#define HDMITX_DWC_HDCP_M0_0 (DWC_OFFSET_MASK + 0x5022) +#define HDMITX_DWC_HDCP_M0_1 (DWC_OFFSET_MASK + 0x5023) +#define HDMITX_DWC_HDCP_M0_2 (DWC_OFFSET_MASK + 0x5024) +#define HDMITX_DWC_HDCP_M0_3 (DWC_OFFSET_MASK + 0x5025) +#define HDMITX_DWC_HDCP_M0_4 (DWC_OFFSET_MASK + 0x5026) +#define HDMITX_DWC_HDCP_M0_5 (DWC_OFFSET_MASK + 0x5027) +#define HDMITX_DWC_HDCP_M0_6 (DWC_OFFSET_MASK + 0x5028) +#define HDMITX_DWC_HDCP_M0_7 (DWC_OFFSET_MASK + 0x5029) +#define HDMITX_DWC_HDCP_KSV (DWC_OFFSET_MASK + 0x502A) +#define HDMITX_DWC_HDCP_VH (DWC_OFFSET_MASK + 0x52A5) +#define HDMITX_DWC_HDCP_REVOC_SIZE_0 (DWC_OFFSET_MASK + 0x52B9) +#define HDMITX_DWC_HDCP_REVOC_SIZE_1 (DWC_OFFSET_MASK + 0x52BA) +#define HDMITX_DWC_HDCP_REVOC_LIST (DWC_OFFSET_MASK + 0x52BB) + +/* HDCP BKSV Registers */ +#define HDMITX_DWC_HDCPREG_BKSV0 (DWC_OFFSET_MASK + 0x7800) +#define HDMITX_DWC_HDCPREG_BKSV1 (DWC_OFFSET_MASK + 0x7801) +#define HDMITX_DWC_HDCPREG_BKSV2 (DWC_OFFSET_MASK + 0x7802) +#define HDMITX_DWC_HDCPREG_BKSV3 (DWC_OFFSET_MASK + 0x7803) +#define HDMITX_DWC_HDCPREG_BKSV4 (DWC_OFFSET_MASK + 0x7804) + +/* HDCP AN Registers */ +#define HDMITX_DWC_HDCPREG_ANCONF (DWC_OFFSET_MASK + 0x7805) +#define HDMITX_DWC_HDCPREG_AN0 (DWC_OFFSET_MASK + 0x7806) +#define HDMITX_DWC_HDCPREG_AN1 (DWC_OFFSET_MASK + 0x7807) +#define HDMITX_DWC_HDCPREG_AN2 (DWC_OFFSET_MASK + 0x7808) +#define HDMITX_DWC_HDCPREG_AN3 (DWC_OFFSET_MASK + 0x7809) +#define HDMITX_DWC_HDCPREG_AN4 (DWC_OFFSET_MASK + 0x780A) +#define HDMITX_DWC_HDCPREG_AN5 (DWC_OFFSET_MASK + 0x780B) +#define HDMITX_DWC_HDCPREG_AN6 (DWC_OFFSET_MASK + 0x780C) +#define HDMITX_DWC_HDCPREG_AN7 (DWC_OFFSET_MASK + 0x780D) +#define HDMITX_DWC_HDCPREG_RMLCTL (DWC_OFFSET_MASK + 0x780E) + +/* Encrypted DPK Embedded Storage Registers */ +#define HDMITX_DWC_HDCPREG_RMLSTS (DWC_OFFSET_MASK + 0x780F) +#define HDMITX_DWC_HDCPREG_SEED0 (DWC_SEC_OFFSET_MASK + 0x7810) +#define HDMITX_DWC_HDCPREG_SEED1 (DWC_SEC_OFFSET_MASK + 0x7811) +#define HDMITX_DWC_HDCPREG_DPK0 (DWC_SEC_OFFSET_MASK + 0x7812) +#define HDMITX_DWC_HDCPREG_DPK1 (DWC_SEC_OFFSET_MASK + 0x7813) +#define HDMITX_DWC_HDCPREG_DPK2 (DWC_SEC_OFFSET_MASK + 0x7814) +#define HDMITX_DWC_HDCPREG_DPK3 (DWC_SEC_OFFSET_MASK + 0x7815) +#define HDMITX_DWC_HDCPREG_DPK4 (DWC_SEC_OFFSET_MASK + 0x7816) +#define HDMITX_DWC_HDCPREG_DPK5 (DWC_SEC_OFFSET_MASK + 0x7817) +#define HDMITX_DWC_HDCPREG_DPK6 (DWC_SEC_OFFSET_MASK + 0x7818) + +/* HDCP22 Registers */ +#define HDMITX_DWC_HDCP22REG_ID (DWC_OFFSET_MASK + 0x7900) +#define HDMITX_DWC_HDCP22REG_CTRL (DWC_SEC_OFFSET_MASK + 0x7904) +#define HDMITX_DWC_HDCP22REG_CTRL1 (DWC_OFFSET_MASK + 0x7905) +#define HDMITX_DWC_HDCP22REG_STS (DWC_OFFSET_MASK + 0x7908) +#define HDMITX_DWC_HDCP22REG_MASK (DWC_OFFSET_MASK + 0x790C) +#define HDMITX_DWC_HDCP22REG_STAT (DWC_OFFSET_MASK + 0x790D) +#define HDMITX_DWC_HDCP22REG_MUTE (DWC_OFFSET_MASK + 0x790E) + + +/* ********** CEC related ********** */ + +/* CEC 2.0 Engine Registers */ +#define HDMITX_DWC_CEC_CTRL (DWC_OFFSET_MASK + 0x7D00) +#define HDMITX_DWC_CEC_INTR_MASK (DWC_OFFSET_MASK + 0x7D02) +#define HDMITX_DWC_CEC_LADD_LOW (DWC_OFFSET_MASK + 0x7D05) +#define HDMITX_DWC_CEC_LADD_HIGH (DWC_OFFSET_MASK + 0x7D06) +#define HDMITX_DWC_CEC_TX_CNT (DWC_OFFSET_MASK + 0x7D07) +#define HDMITX_DWC_CEC_RX_CNT (DWC_OFFSET_MASK + 0x7D08) +#define HDMITX_DWC_CEC_TX_DATA00 (DWC_OFFSET_MASK + 0x7D10) +#define HDMITX_DWC_CEC_TX_DATA01 (DWC_OFFSET_MASK + 0x7D11) +#define HDMITX_DWC_CEC_TX_DATA02 (DWC_OFFSET_MASK + 0x7D12) +#define HDMITX_DWC_CEC_TX_DATA03 (DWC_OFFSET_MASK + 0x7D13) +#define HDMITX_DWC_CEC_TX_DATA04 (DWC_OFFSET_MASK + 0x7D14) +#define HDMITX_DWC_CEC_TX_DATA05 (DWC_OFFSET_MASK + 0x7D15) +#define HDMITX_DWC_CEC_TX_DATA06 (DWC_OFFSET_MASK + 0x7D16) +#define HDMITX_DWC_CEC_TX_DATA07 (DWC_OFFSET_MASK + 0x7D17) +#define HDMITX_DWC_CEC_TX_DATA08 (DWC_OFFSET_MASK + 0x7D18) +#define HDMITX_DWC_CEC_TX_DATA09 (DWC_OFFSET_MASK + 0x7D19) +#define HDMITX_DWC_CEC_TX_DATA10 (DWC_OFFSET_MASK + 0x7D1A) +#define HDMITX_DWC_CEC_TX_DATA11 (DWC_OFFSET_MASK + 0x7D1B) +#define HDMITX_DWC_CEC_TX_DATA12 (DWC_OFFSET_MASK + 0x7D1C) +#define HDMITX_DWC_CEC_TX_DATA13 (DWC_OFFSET_MASK + 0x7D1D) +#define HDMITX_DWC_CEC_TX_DATA14 (DWC_OFFSET_MASK + 0x7D1E) +#define HDMITX_DWC_CEC_TX_DATA15 (DWC_OFFSET_MASK + 0x7D1F) +#define HDMITX_DWC_CEC_RX_DATA00 (DWC_OFFSET_MASK + 0x7D20) +#define HDMITX_DWC_CEC_RX_DATA01 (DWC_OFFSET_MASK + 0x7D21) +#define HDMITX_DWC_CEC_RX_DATA02 (DWC_OFFSET_MASK + 0x7D22) +#define HDMITX_DWC_CEC_RX_DATA03 (DWC_OFFSET_MASK + 0x7D23) +#define HDMITX_DWC_CEC_RX_DATA04 (DWC_OFFSET_MASK + 0x7D24) +#define HDMITX_DWC_CEC_RX_DATA05 (DWC_OFFSET_MASK + 0x7D25) +#define HDMITX_DWC_CEC_RX_DATA06 (DWC_OFFSET_MASK + 0x7D26) +#define HDMITX_DWC_CEC_RX_DATA07 (DWC_OFFSET_MASK + 0x7D27) +#define HDMITX_DWC_CEC_RX_DATA08 (DWC_OFFSET_MASK + 0x7D28) +#define HDMITX_DWC_CEC_RX_DATA09 (DWC_OFFSET_MASK + 0x7D29) +#define HDMITX_DWC_CEC_RX_DATA10 (DWC_OFFSET_MASK + 0x7D2A) +#define HDMITX_DWC_CEC_RX_DATA11 (DWC_OFFSET_MASK + 0x7D2B) +#define HDMITX_DWC_CEC_RX_DATA12 (DWC_OFFSET_MASK + 0x7D2C) +#define HDMITX_DWC_CEC_RX_DATA13 (DWC_OFFSET_MASK + 0x7D2D) +#define HDMITX_DWC_CEC_RX_DATA14 (DWC_OFFSET_MASK + 0x7D2E) +#define HDMITX_DWC_CEC_RX_DATA15 (DWC_OFFSET_MASK + 0x7D2F) +#define HDMITX_DWC_CEC_LOCK_BUF (DWC_OFFSET_MASK + 0x7D30) +#define HDMITX_DWC_CEC_WAKEUPCTRL (DWC_OFFSET_MASK + 0x7D31) + +/* I2C Master Registers(E-DDC/SCDC) */ +#define HDMITX_DWC_I2CM_SLAVE (DWC_OFFSET_MASK + 0x7E00) +#define HDMITX_DWC_I2CM_ADDRESS (DWC_OFFSET_MASK + 0x7E01) +#define HDMITX_DWC_I2CM_DATAO (DWC_OFFSET_MASK + 0x7E02) +#define HDMITX_DWC_I2CM_DATAI (DWC_OFFSET_MASK + 0x7E03) +#define HDMITX_DWC_I2CM_OPERATION (DWC_OFFSET_MASK + 0x7E04) +/* [ 2] done_mask */ +/* [ 6] read_req_mask */ +#define HDMITX_DWC_I2CM_INT (DWC_OFFSET_MASK + 0x7E05) +/* [ 6] nack_mask */ +/* [ 2] arbitration_error_mask */ +#define HDMITX_DWC_I2CM_CTLINT (DWC_OFFSET_MASK + 0x7E06) +/* [ 3] i2c_fast_mode: 0=standard mode; 1=fast mode. */ +#define HDMITX_DWC_I2CM_DIV (DWC_OFFSET_MASK + 0x7E07) +#define HDMITX_DWC_I2CM_SEGADDR (DWC_OFFSET_MASK + 0x7E08) +#define HDMITX_DWC_I2CM_SOFTRSTZ (DWC_OFFSET_MASK + 0x7E09) +#define HDMITX_DWC_I2CM_SEGPTR (DWC_OFFSET_MASK + 0x7E0A) +/* I2CM_SS_SCL_HCNT = RndUp(min_ss_scl_htime*Freq(sfrclkInMHz)/1000) */ +/* I2CM_SS_SCL_LCNT = RndUp(min_ss_scl_ltime*Freq(sfrclkInMHz)/1000) */ +/* I2CM_FS_SCL_HCNT = RndUp(min_fs_scl_htime*Freq(sfrclkInMHz)/1000) */ +/* I2CM_FS_SCL_LCNT = RndUp(min_fs_scl_ltime*Freq(sfrclkInMHz)/1000) */ +/* Where Freq(sfrclkInMHz)=24; */ +#define HDMITX_DWC_I2CM_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0B) +#define HDMITX_DWC_I2CM_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E0C) +#define HDMITX_DWC_I2CM_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E0D) +#define HDMITX_DWC_I2CM_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E0E) +#define HDMITX_DWC_I2CM_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0F) +#define HDMITX_DWC_I2CM_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E10) +#define HDMITX_DWC_I2CM_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E11) +#define HDMITX_DWC_I2CM_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E12) +#define HDMITX_DWC_I2CM_SDA_HOLD (DWC_OFFSET_MASK + 0x7E13) +/* [ 5] updt_rd_vsyncpoll_en */ +/* [ 4] read_request_en */ +/* [ 0] read_update */ +#define HDMITX_DWC_I2CM_SCDC_UPDATE (DWC_OFFSET_MASK + 0x7E14) +#define HDMITX_DWC_I2CM_READ_BUFF0 (DWC_OFFSET_MASK + 0x7E20) +#define HDMITX_DWC_I2CM_READ_BUFF1 (DWC_OFFSET_MASK + 0x7E21) +#define HDMITX_DWC_I2CM_READ_BUFF2 (DWC_OFFSET_MASK + 0x7E22) +#define HDMITX_DWC_I2CM_READ_BUFF3 (DWC_OFFSET_MASK + 0x7E23) +#define HDMITX_DWC_I2CM_READ_BUFF4 (DWC_OFFSET_MASK + 0x7E24) +#define HDMITX_DWC_I2CM_READ_BUFF5 (DWC_OFFSET_MASK + 0x7E25) +#define HDMITX_DWC_I2CM_READ_BUFF6 (DWC_OFFSET_MASK + 0x7E26) +#define HDMITX_DWC_I2CM_READ_BUFF7 (DWC_OFFSET_MASK + 0x7E27) +#define HDMITX_DWC_I2CM_SCDC_UPDATE0 (DWC_OFFSET_MASK + 0x7E30) +#define HDMITX_DWC_I2CM_SCDC_UPDATE1 (DWC_OFFSET_MASK + 0x7E31) + +#endif /* __HDMI_TX_REG_H_ */
diff --git a/include/amlogic/media/vout/hdmitx/mach_reg.h b/include/amlogic/media/vout/hdmitx/mach_reg.h new file mode 100644 index 0000000..be5419a --- /dev/null +++ b/include/amlogic/media/vout/hdmitx/mach_reg.h
@@ -0,0 +1,630 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __MACH_REG_H__ +#define __MACH_REG_H__ + +/* + * RePacket HDMI related registers rd/wr + */ +struct reg_map { + uint32_t base_addr; +}; + +#define CBUS_REG_IDX 0 +#define PERIPHS_REG_IDX 1 +#define VCBUS_REG_IDX 2 +#define AOBUS_REG_IDX 3 +#define HHI_REG_IDX 4 +#define RESET_CBUS_REG_IDX 5 +#define HDMITX_REG_IDX 6 +#define HDMITX_SEC_REG_IDX 7 +#define ELP_ESM_REG_IDX 8 +/* new added in SC2 */ +#define ANACTRL_REG_IDX 9 +#define PWRCTRL_REG_IDX 10 +#define RESETCTRL_REG_IDX 11 +#define SYSCTRL_REG_IDX 12 +#define REG_IDX_END 13 + +#define BASE_REG_OFFSET 24 + +#define PERIPHS_REG_ADDR(reg) \ + ((PERIPHS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define VCBUS_REG_ADDR(reg) \ + ((VCBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define AOBUS_REG_ADDR(reg) \ + ((AOBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define HHI_REG_ADDR(reg) \ + ((HHI_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define RESET_CBUS_REG_ADDR(reg) \ + ((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define HDMITX_SEC_REG_ADDR(reg) \ + ((HDMITX_SEC_REG_IDX << BASE_REG_OFFSET) + (reg))/*DWC*/ +#define HDMITX_REG_ADDR(reg) \ + ((HDMITX_REG_IDX << BASE_REG_OFFSET) + (reg))/*TOP*/ +#define ELP_ESM_REG_ADDR(reg) \ + ((ELP_ESM_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define ANACTRL_REG_ADDR(reg) \ + ((ANACTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define PWRCTRL_REG_ADDR(reg) \ + ((PWRCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define RESETCTRL_REG_ADDR(reg) \ + ((RESETCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) +#define SYSCTRL_REG_ADDR(reg) \ + ((SYSCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2)) + +struct reg_s { + unsigned int reg; + unsigned int val; +}; + +unsigned int hd_read_reg(unsigned int addr); +void hd_write_reg(unsigned int addr, unsigned int val); +void hd_set_reg_bits(unsigned int addr, unsigned int value, unsigned int offset, + unsigned int len); +uint32_t hd_get_paddr(uint32_t addr); +unsigned int hdmitx_rd_reg(unsigned int addr); +void hdmitx_wr_reg(unsigned int addr, unsigned int data); +void hdmitx_set_reg_bits(unsigned int addr, unsigned int value, + unsigned int offset, unsigned int len); +void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout); + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 */ +#define CLKCTRL_SYS_CLK_EN0_REG2 0x0013 +#define P_CLKCTRL_SYS_CLK_EN0_REG2 HHI_REG_ADDR(CLKCTRL_SYS_CLK_EN0_REG2) +#define CLKCTRL_VID_CLK_CTRL 0x0030 +#define P_CLKCTRL_VID_CLK_CTRL HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL) +#define CLKCTRL_VID_CLK_CTRL2 0x0031 +#define P_CLKCTRL_VID_CLK_CTRL2 HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL2) +#define CLKCTRL_VID_CLK_DIV 0x0032 +#define P_CLKCTRL_VID_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_CLK_DIV) +#define CLKCTRL_HDMI_CLK_CTRL 0x0038 +#define P_CLKCTRL_HDMI_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDMI_CLK_CTRL) +#define CLKCTRL_VID_PLL_CLK_DIV 0x0039 +#define P_CLKCTRL_VID_PLL_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_PLL_CLK_DIV) +#define CLKCTRL_HDCP22_CLK_CTRL 0x0040 +#define P_CLKCTRL_HDCP22_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDCP22_CLK_CTRL) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe002000 */ +#define RESETCTRL_RESET0 0x0000 +#define P_RESETCTRL_RESET0 RESETCTRL_REG_ADDR(RESETCTRL_RESET0) +#define RESETCTRL_RESET2 0x0002 +#define P_RESETCTRL_RESET2 RESETCTRL_REG_ADDR(RESETCTRL_RESET2) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe004000 */ +#define PADCTRL_PIN_MUX_REGB 0x0b +#define P_PADCTRL_PIN_MUX_REGB PERIPHS_REG_ADDR(PADCTRL_PIN_MUX_REGB) +#define PADCTRL_GPIOH_I 0x50 +#define P_PADCTRL_GPIOH_I PERIPHS_REG_ADDR(PADCTRL_GPIOH_I) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 */ +#define ANACTRL_HDMIPLL_CTRL0 0x0070 +#define P_ANACTRL_HDMIPLL_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL0) +#define ANACTRL_HDMIPLL_CTRL1 0x0071 +#define P_ANACTRL_HDMIPLL_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL1) +#define ANACTRL_HDMIPLL_CTRL2 0x0072 +#define P_ANACTRL_HDMIPLL_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL2) +#define ANACTRL_HDMIPLL_CTRL3 0x0073 +#define P_ANACTRL_HDMIPLL_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL3) +#define ANACTRL_HDMIPLL_CTRL4 0x0074 +#define P_ANACTRL_HDMIPLL_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL4) +#define ANACTRL_HDMIPLL_CTRL5 0x0075 +#define P_ANACTRL_HDMIPLL_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL5) +#define ANACTRL_HDMIPLL_CTRL6 0x0076 +#define P_ANACTRL_HDMIPLL_CTRL6 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL6) +#define ANACTRL_HDMIPLL_STS 0x0077 +#define P_ANACTRL_HDMIPLL_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_STS) +#define ANACTRL_HDMIPLL_VLOCK 0x0079 +#define P_ANACTRL_HDMIPLL_VLOCK ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_VLOCK) +#define ANACTRL_HDMIPHY_CTRL0 0x0080 +#define P_ANACTRL_HDMIPHY_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL0) +#define ANACTRL_HDMIPHY_CTRL1 0x0081 +#define P_ANACTRL_HDMIPHY_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL1) +#define ANACTRL_HDMIPHY_CTRL2 0x0082 +#define P_ANACTRL_HDMIPHY_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL2) +#define ANACTRL_HDMIPHY_CTRL3 0x0083 +#define P_ANACTRL_HDMIPHY_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL3) +#define ANACTRL_HDMIPHY_CTRL4 0x0084 +#define P_ANACTRL_HDMIPHY_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL4) +#define ANACTRL_HDMIPHY_CTRL5 0x0085 +#define P_ANACTRL_HDMIPHY_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL5) +#define ANACTRL_HDMIPHY_STS 0x0086 +#define P_ANACTRL_HDMIPHY_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_STS) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000 */ +#define PWRCTRL_MEM_PD11 0x001b +#define P_PWRCTRL_MEM_PD11 PWRCTRL_REG_ADDR(PWRCTRL_MEM_PD11) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xfe010000 */ +#define SYSCTRL_DEBUG_REG0 0x90 +#define P_SYSCTRL_DEBUG_REG0 SYSCTRL_REG_ADDR(SYSCTRL_DEBUG_REG0) + +/* REG_BASE: REGISTER_BASE_ADDR = 0xff000000 */ +#define VENC_DVI_SETTING 0x1b62 /* register.h:8014 */ +#define P_VENC_DVI_SETTING VCBUS_REG_ADDR(VENC_DVI_SETTING) + +#define VENC_VIDEO_TST_EN 0x1b70 +#define P_VENC_VIDEO_TST_EN VCBUS_REG_ADDR(VENC_VIDEO_TST_EN) +#define VENC_VIDEO_TST_MDSEL 0x1b71 +#define P_VENC_VIDEO_TST_MDSEL VCBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL) +#define VENC_VIDEO_TST_Y 0x1b72 +#define P_VENC_VIDEO_TST_Y VCBUS_REG_ADDR(VENC_VIDEO_TST_Y) +#define VENC_VIDEO_TST_CB 0x1b73 +#define P_VENC_VIDEO_TST_CB VCBUS_REG_ADDR(VENC_VIDEO_TST_CB) +#define VENC_VIDEO_TST_CR 0x1b74 +#define P_VENC_VIDEO_TST_CR VCBUS_REG_ADDR(VENC_VIDEO_TST_CR) +#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 +#define P_VENC_VIDEO_TST_CLRBAR_STRT VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT) +#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 +#define P_VENC_VIDEO_TST_CLRBAR_WIDTH \ + VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH) +#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 +#define P_VENC_VIDEO_TST_VDCNT_STSET VCBUS_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET) +#define VENC_VDAC_SETTING 0x1b7e +#define P_VENC_VDAC_SETTING VCBUS_REG_ADDR(VENC_VDAC_SETTING) +#define ENCP_VIDEO_EN 0x1b80 /* register.h:8078 */ +#define P_ENCP_VIDEO_EN VCBUS_REG_ADDR(ENCP_VIDEO_EN) +#define ENCP_VIDEO_SYNC_MODE 0x1b81 /* register.h:8079 */ +#define P_ENCP_VIDEO_SYNC_MODE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE) +#define ENCP_MACV_EN 0x1b82 /* register.h:8080 */ +#define P_ENCP_MACV_EN VCBUS_REG_ADDR(ENCP_MACV_EN) +#define ENCP_VIDEO_Y_SCL 0x1b83 /* register.h:8081 */ +#define P_ENCP_VIDEO_Y_SCL VCBUS_REG_ADDR(ENCP_VIDEO_Y_SCL) +#define ENCP_VIDEO_PB_SCL 0x1b84 /* register.h:8082 */ +#define P_ENCP_VIDEO_PB_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PB_SCL) +#define ENCP_VIDEO_PR_SCL 0x1b85 /* register.h:8083 */ +#define P_ENCP_VIDEO_PR_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PR_SCL) +#define ENCP_VIDEO_SYNC_SCL 0x1b86 /* register.h:8084 */ +#define P_ENCP_VIDEO_SYNC_SCL VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL) +#define ENCP_VIDEO_MACV_SCL 0x1b87 /* register.h:8085 */ +#define P_ENCP_VIDEO_MACV_SCL VCBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL) +#define ENCP_VIDEO_Y_OFFST 0x1b88 /* register.h:8086 */ +#define P_ENCP_VIDEO_Y_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST) +#define ENCP_VIDEO_PB_OFFST 0x1b89 /* register.h:8087 */ +#define P_ENCP_VIDEO_PB_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST) +#define ENCP_VIDEO_PR_OFFST 0x1b8a /* register.h:8088 */ +#define P_ENCP_VIDEO_PR_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST) +#define ENCP_VIDEO_SYNC_OFFST 0x1b8b /* register.h:8089 */ +#define P_ENCP_VIDEO_SYNC_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_OFFST) +#define ENCP_VIDEO_MACV_OFFST 0x1b8c /* register.h:8090 */ +#define P_ENCP_VIDEO_MACV_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_MACV_OFFST) +#define ENCP_VIDEO_MODE 0x1b8d /* register.h:8092 */ +#define P_ENCP_VIDEO_MODE VCBUS_REG_ADDR(ENCP_VIDEO_MODE) +#define ENCP_VIDEO_MODE_ADV 0x1b8e /* register.h:8093 */ +#define P_ENCP_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV) +#define ENCP_DBG_PX_RST 0x1b90 /* register.h:8095 */ +#define P_ENCP_DBG_PX_RST VCBUS_REG_ADDR(ENCP_DBG_PX_RST) +#define ENCP_DBG_LN_RST 0x1b91 /* register.h:8096 */ +#define P_ENCP_DBG_LN_RST VCBUS_REG_ADDR(ENCP_DBG_LN_RST) +#define ENCP_DBG_PX_INT 0x1b92 /* register.h:8097 */ +#define P_ENCP_DBG_PX_INT VCBUS_REG_ADDR(ENCP_DBG_PX_INT) +#define ENCP_DBG_LN_INT 0x1b93 /* register.h:8098 */ +#define P_ENCP_DBG_LN_INT VCBUS_REG_ADDR(ENCP_DBG_LN_INT) +#define ENCP_VIDEO_YFP1_HTIME 0x1b94 /* register.h:8100 */ +#define P_ENCP_VIDEO_YFP1_HTIME VCBUS_REG_ADDR(ENCP_VIDEO_YFP1_HTIME) +#define ENCP_VIDEO_YFP2_HTIME 0x1b95 /* register.h:8101 */ +#define P_ENCP_VIDEO_YFP2_HTIME VCBUS_REG_ADDR(ENCP_VIDEO_YFP2_HTIME) +#define ENCP_VIDEO_YC_DLY 0x1b96 /* register.h:8102 */ +#define P_ENCP_VIDEO_YC_DLY VCBUS_REG_ADDR(ENCP_VIDEO_YC_DLY) +#define ENCP_VIDEO_MAX_PXCNT 0x1b97 /* register.h:8103 */ +#define P_ENCP_VIDEO_MAX_PXCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT) +#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 /* register.h:8104 */ +#define P_ENCP_VIDEO_HSPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN) +#define ENCP_VIDEO_HSPULS_END 0x1b99 /* register.h:8105 */ +#define P_ENCP_VIDEO_HSPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_END) +#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a /* register.h:8106 */ +#define P_ENCP_VIDEO_HSPULS_SWITCH VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH) +#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b /* register.h:8107 */ +#define P_ENCP_VIDEO_VSPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN) +#define ENCP_VIDEO_VSPULS_END 0x1b9c /* register.h:8108 */ +#define P_ENCP_VIDEO_VSPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_END) +#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d /* register.h:8109 */ +#define P_ENCP_VIDEO_VSPULS_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE) +#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e /* register.h:8110 */ +#define P_ENCP_VIDEO_VSPULS_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE) +#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f /* register.h:8111 */ +#define P_ENCP_VIDEO_EQPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN) +#define ENCP_VIDEO_EQPULS_END 0x1ba0 /* register.h:8112 */ +#define P_ENCP_VIDEO_EQPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_END) +#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 /* register.h:8113 */ +#define P_ENCP_VIDEO_EQPULS_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE) +#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 /* register.h:8114 */ +#define P_ENCP_VIDEO_EQPULS_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE) +#define ENCP_VIDEO_HAVON_END 0x1ba3 /* register.h:8115 */ +#define P_ENCP_VIDEO_HAVON_END VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_END) +#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 /* register.h:8116 */ +#define P_ENCP_VIDEO_HAVON_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN) +#define ENCP_VIDEO_VAVON_ELINE 0x1baf /* register.h:8117 */ +#define P_ENCP_VIDEO_VAVON_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_ELINE) +#define ENCP_VIDEO_VAVON_BLINE 0x1ba6 /* register.h:8118 */ +#define P_ENCP_VIDEO_VAVON_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_BLINE) +#define ENCP_VIDEO_HSO_BEGIN 0x1ba7 /* register.h:8119 */ +#define P_ENCP_VIDEO_HSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HSO_BEGIN) +#define ENCP_VIDEO_HSO_END 0x1ba8 /* register.h:8120 */ +#define P_ENCP_VIDEO_HSO_END VCBUS_REG_ADDR(ENCP_VIDEO_HSO_END) +#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 /* register.h:8121 */ +#define P_ENCP_VIDEO_VSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN) +#define ENCP_VIDEO_VSO_END 0x1baa /* register.h:8122 */ +#define P_ENCP_VIDEO_VSO_END VCBUS_REG_ADDR(ENCP_VIDEO_VSO_END) +#define ENCP_VIDEO_VSO_BLINE 0x1bab /* register.h:8123 */ +#define P_ENCP_VIDEO_VSO_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE) +#define ENCP_VIDEO_VSO_ELINE 0x1bac /* register.h:8124 */ +#define P_ENCP_VIDEO_VSO_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE) +#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad /* register.h:8125 */ +#define P_ENCP_VIDEO_SYNC_WAVE_CURVE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE) +#define ENCP_VIDEO_MAX_LNCNT 0x1bae /* register.h:8126 */ +#define P_ENCP_VIDEO_MAX_LNCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT) +#define ENCP_VIDEO_SY_VAL 0x1bb0 /* register.h:8127 */ +#define P_ENCP_VIDEO_SY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY_VAL) +#define ENCP_VIDEO_SY2_VAL 0x1bb1 /* register.h:8128 */ +#define P_ENCP_VIDEO_SY2_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL) +#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 /* register.h:8129 */ +#define P_ENCP_VIDEO_BLANKY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKY_VAL) +#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 /* register.h:8130 */ +#define P_ENCP_VIDEO_BLANKPB_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL) +#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 /* register.h:8131 */ +#define P_ENCP_VIDEO_BLANKPR_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL) +#define ENCP_VIDEO_HOFFST 0x1bb5 /* register.h:8132 */ +#define P_ENCP_VIDEO_HOFFST VCBUS_REG_ADDR(ENCP_VIDEO_HOFFST) +#define ENCP_VIDEO_VOFFST 0x1bb6 /* register.h:8133 */ +#define P_ENCP_VIDEO_VOFFST VCBUS_REG_ADDR(ENCP_VIDEO_VOFFST) +#define ENCP_VIDEO_RGB_CTRL 0x1bb7 /* register.h:8134 */ +#define P_ENCP_VIDEO_RGB_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL) +#define ENCP_VIDEO_FILT_CTRL 0x1bb8 /* register.h:8135 */ +#define P_ENCP_VIDEO_FILT_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL) +#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 /* register.h:8136 */ +#define P_ENCP_VIDEO_OFLD_VPEQ_OFST VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST) +#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba /* register.h:8137 */ +#define P_ENCP_VIDEO_OFLD_VOAV_OFST VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST) +#define ENCP_VIDEO_MATRIX_CB 0x1bbb /* register.h:8138 */ +#define P_ENCP_VIDEO_MATRIX_CB VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CB) +#define ENCP_VIDEO_MATRIX_CR 0x1bbc /* register.h:8139 */ +#define P_ENCP_VIDEO_MATRIX_CR VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CR) +#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd /* register.h:8140 */ +#define P_ENCP_VIDEO_RGBIN_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL) +#define ENCP_MACV_BLANKY_VAL 0x1bc0 /* register.h:8142 */ +#define P_ENCP_MACV_BLANKY_VAL VCBUS_REG_ADDR(ENCP_MACV_BLANKY_VAL) +#define ENCP_MACV_MAXY_VAL 0x1bc1 /* register.h:8143 */ +#define P_ENCP_MACV_MAXY_VAL VCBUS_REG_ADDR(ENCP_MACV_MAXY_VAL) +#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 /* register.h:8144 */ +#define P_ENCP_MACV_1ST_PSSYNC_STRT VCBUS_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT) +#define ENCP_MACV_PSSYNC_STRT 0x1bc3 /* register.h:8145 */ +#define P_ENCP_MACV_PSSYNC_STRT VCBUS_REG_ADDR(ENCP_MACV_PSSYNC_STRT) +#define ENCP_MACV_AGC_STRT 0x1bc4 /* register.h:8146 */ +#define P_ENCP_MACV_AGC_STRT VCBUS_REG_ADDR(ENCP_MACV_AGC_STRT) +#define ENCP_MACV_AGC_END 0x1bc5 /* register.h:8147 */ +#define P_ENCP_MACV_AGC_END VCBUS_REG_ADDR(ENCP_MACV_AGC_END) +#define ENCP_MACV_WAVE_END 0x1bc6 /* register.h:8148 */ +#define P_ENCP_MACV_WAVE_END VCBUS_REG_ADDR(ENCP_MACV_WAVE_END) +#define ENCP_MACV_STRTLINE 0x1bc7 /* register.h:8149 */ +#define P_ENCP_MACV_STRTLINE VCBUS_REG_ADDR(ENCP_MACV_STRTLINE) +#define ENCP_MACV_ENDLINE 0x1bc8 /* register.h:8150 */ +#define P_ENCP_MACV_ENDLINE VCBUS_REG_ADDR(ENCP_MACV_ENDLINE) +#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 /* register.h:8151 */ +#define P_ENCP_MACV_TS_CNT_MAX_L VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L) +#define ENCP_MACV_TS_CNT_MAX_H 0x1bca /* register.h:8152 */ +#define P_ENCP_MACV_TS_CNT_MAX_H VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H) +#define ENCP_MACV_TIME_DOWN 0x1bcb /* register.h:8153 */ +#define P_ENCP_MACV_TIME_DOWN VCBUS_REG_ADDR(ENCP_MACV_TIME_DOWN) +#define ENCP_MACV_TIME_LO 0x1bcc /* register.h:8154 */ +#define P_ENCP_MACV_TIME_LO VCBUS_REG_ADDR(ENCP_MACV_TIME_LO) +#define ENCP_MACV_TIME_UP 0x1bcd /* register.h:8155 */ +#define P_ENCP_MACV_TIME_UP VCBUS_REG_ADDR(ENCP_MACV_TIME_UP) +#define ENCP_MACV_TIME_RST 0x1bce /* register.h:8156 */ +#define P_ENCP_MACV_TIME_RST VCBUS_REG_ADDR(ENCP_MACV_TIME_RST) +#define ENCP_VBI_CTRL 0x1bd0 /* register.h:8158 */ +#define P_ENCP_VBI_CTRL VCBUS_REG_ADDR(ENCP_VBI_CTRL) +#define ENCP_VBI_SETTING 0x1bd1 /* register.h:8159 */ +#define P_ENCP_VBI_SETTING VCBUS_REG_ADDR(ENCP_VBI_SETTING) +#define ENCP_VBI_BEGIN 0x1bd2 /* register.h:8160 */ +#define P_ENCP_VBI_BEGIN VCBUS_REG_ADDR(ENCP_VBI_BEGIN) +#define ENCP_VBI_WIDTH 0x1bd3 /* register.h:8161 */ +#define P_ENCP_VBI_WIDTH VCBUS_REG_ADDR(ENCP_VBI_WIDTH) +#define ENCP_VBI_HVAL 0x1bd4 /* register.h:8162 */ +#define P_ENCP_VBI_HVAL VCBUS_REG_ADDR(ENCP_VBI_HVAL) +#define ENCP_VBI_DATA0 0x1bd5 /* register.h:8163 */ +#define P_ENCP_VBI_DATA0 VCBUS_REG_ADDR(ENCP_VBI_DATA0) +#define ENCP_VBI_DATA1 0x1bd6 /* register.h:8164 */ +#define P_ENCP_VBI_DATA1 VCBUS_REG_ADDR(ENCP_VBI_DATA1) + +#define ENCI_VIDEO_MODE 0x1b00 /* register.h:8185 */ +#define P_ENCI_VIDEO_MODE VCBUS_REG_ADDR(ENCI_VIDEO_MODE) +#define ENCI_VIDEO_MODE_ADV 0x1b01 /* register.h:8186 */ +#define P_ENCI_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV) +#define ENCI_VIDEO_FSC_ADJ 0x1b02 /* register.h:8187 */ +#define P_ENCI_VIDEO_FSC_ADJ VCBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ) +#define ENCI_VIDEO_BRIGHT 0x1b03 /* register.h:8188 */ +#define P_ENCI_VIDEO_BRIGHT VCBUS_REG_ADDR(ENCI_VIDEO_BRIGHT) +#define ENCI_VIDEO_CONT 0x1b04 /* register.h:8189 */ +#define P_ENCI_VIDEO_CONT VCBUS_REG_ADDR(ENCI_VIDEO_CONT) +#define ENCI_VIDEO_SAT 0x1b05 /* register.h:8190 */ +#define P_ENCI_VIDEO_SAT VCBUS_REG_ADDR(ENCI_VIDEO_SAT) +#define ENCI_VIDEO_HUE 0x1b06 /* register.h:8191 */ +#define P_ENCI_VIDEO_HUE VCBUS_REG_ADDR(ENCI_VIDEO_HUE) +#define ENCI_VIDEO_SCH 0x1b07 /* register.h:8192 */ +#define P_ENCI_VIDEO_SCH VCBUS_REG_ADDR(ENCI_VIDEO_SCH) +#define ENCI_SYNC_MODE 0x1b08 /* register.h:8193 */ +#define P_ENCI_SYNC_MODE VCBUS_REG_ADDR(ENCI_SYNC_MODE) +#define ENCI_SYNC_CTRL 0x1b09 /* register.h:8194 */ +#define P_ENCI_SYNC_CTRL VCBUS_REG_ADDR(ENCI_SYNC_CTRL) +#define ENCI_SYNC_HSO_BEGIN 0x1b0a /* register.h:8195 */ +#define P_ENCI_SYNC_HSO_BEGIN VCBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN) +#define ENCI_SYNC_HSO_END 0x1b0b /* register.h:8196 */ +#define P_ENCI_SYNC_HSO_END VCBUS_REG_ADDR(ENCI_SYNC_HSO_END) +#define ENCI_SYNC_VSO_EVN 0x1b0c /* register.h:8197 */ +#define P_ENCI_SYNC_VSO_EVN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVN) +#define ENCI_SYNC_VSO_ODD 0x1b0d /* register.h:8198 */ +#define P_ENCI_SYNC_VSO_ODD VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODD) +#define ENCI_SYNC_VSO_EVNLN 0x1b0e /* register.h:8199 */ +#define P_ENCI_SYNC_VSO_EVNLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN) +#define ENCI_SYNC_VSO_ODDLN 0x1b0f /* register.h:8200 */ +#define P_ENCI_SYNC_VSO_ODDLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN) +#define ENCI_SYNC_HOFFST 0x1b10 /* register.h:8201 */ +#define P_ENCI_SYNC_HOFFST VCBUS_REG_ADDR(ENCI_SYNC_HOFFST) +#define ENCI_SYNC_VOFFST 0x1b11 /* register.h:8202 */ +#define P_ENCI_SYNC_VOFFST VCBUS_REG_ADDR(ENCI_SYNC_VOFFST) +#define ENCI_SYNC_ADJ 0x1b12 /* register.h:8203 */ +#define P_ENCI_SYNC_ADJ VCBUS_REG_ADDR(ENCI_SYNC_ADJ) +#define ENCI_RGB_SETTING 0x1b13 /* register.h:8204 */ +#define P_ENCI_RGB_SETTING VCBUS_REG_ADDR(ENCI_RGB_SETTING) +#define ENCI_DE_H_BEGIN 0x1b16 /* register.h:8207 */ +#define P_ENCI_DE_H_BEGIN VCBUS_REG_ADDR(ENCI_DE_H_BEGIN) +#define ENCI_DE_H_END 0x1b17 /* register.h:8208 */ +#define P_ENCI_DE_H_END VCBUS_REG_ADDR(ENCI_DE_H_END) +#define ENCI_DE_V_BEGIN_EVEN 0x1b18 /* register.h:8209 */ +#define P_ENCI_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN) +#define ENCI_DE_V_END_EVEN 0x1b19 /* register.h:8210 */ +#define P_ENCI_DE_V_END_EVEN VCBUS_REG_ADDR(ENCI_DE_V_END_EVEN) +#define ENCI_DE_V_BEGIN_ODD 0x1b1a /* register.h:8211 */ +#define P_ENCI_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD) +#define ENCI_DE_V_END_ODD 0x1b1b /* register.h:8212 */ +#define P_ENCI_DE_V_END_ODD VCBUS_REG_ADDR(ENCI_DE_V_END_ODD) +#define ENCI_VBI_SETTING 0x1b20 /* register.h:8213 */ +#define P_ENCI_VBI_SETTING VCBUS_REG_ADDR(ENCI_VBI_SETTING) +#define ENCI_VBI_CCDT_EVN 0x1b21 /* register.h:8214 */ +#define P_ENCI_VBI_CCDT_EVN VCBUS_REG_ADDR(ENCI_VBI_CCDT_EVN) +#define ENCI_VBI_CCDT_ODD 0x1b22 /* register.h:8215 */ +#define P_ENCI_VBI_CCDT_ODD VCBUS_REG_ADDR(ENCI_VBI_CCDT_ODD) +#define ENCI_VBI_CC525_LN 0x1b23 /* register.h:8216 */ +#define P_ENCI_VBI_CC525_LN VCBUS_REG_ADDR(ENCI_VBI_CC525_LN) +#define ENCI_VBI_CC625_LN 0x1b24 /* register.h:8217 */ +#define P_ENCI_VBI_CC625_LN VCBUS_REG_ADDR(ENCI_VBI_CC625_LN) +#define ENCI_VBI_WSSDT 0x1b25 /* register.h:8218 */ +#define P_ENCI_VBI_WSSDT VCBUS_REG_ADDR(ENCI_VBI_WSSDT) +#define ENCI_VBI_WSS_LN 0x1b26 /* register.h:8219 */ +#define P_ENCI_VBI_WSS_LN VCBUS_REG_ADDR(ENCI_VBI_WSS_LN) +#define ENCI_VBI_CGMSDT_L 0x1b27 /* register.h:8220 */ +#define P_ENCI_VBI_CGMSDT_L VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_L) +#define ENCI_VBI_CGMSDT_H 0x1b28 /* register.h:8221 */ +#define P_ENCI_VBI_CGMSDT_H VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_H) +#define ENCI_VBI_CGMS_LN 0x1b29 /* register.h:8222 */ +#define P_ENCI_VBI_CGMS_LN VCBUS_REG_ADDR(ENCI_VBI_CGMS_LN) +#define ENCI_VBI_TTX_HTIME 0x1b2a /* register.h:8223 */ +#define P_ENCI_VBI_TTX_HTIME VCBUS_REG_ADDR(ENCI_VBI_TTX_HTIME) +#define ENCI_VBI_TTX_LN 0x1b2b /* register.h:8224 */ +#define P_ENCI_VBI_TTX_LN VCBUS_REG_ADDR(ENCI_VBI_TTX_LN) +#define ENCI_VBI_TTXDT0 0x1b2c /* register.h:8225 */ +#define P_ENCI_VBI_TTXDT0 VCBUS_REG_ADDR(ENCI_VBI_TTXDT0) +#define ENCI_VBI_TTXDT1 0x1b2d /* register.h:8226 */ +#define P_ENCI_VBI_TTXDT1 VCBUS_REG_ADDR(ENCI_VBI_TTXDT1) +#define ENCI_VBI_TTXDT2 0x1b2e /* register.h:8227 */ +#define P_ENCI_VBI_TTXDT2 VCBUS_REG_ADDR(ENCI_VBI_TTXDT2) +#define ENCI_VBI_TTXDT3 0x1b2f /* register.h:8228 */ +#define P_ENCI_VBI_TTXDT3 VCBUS_REG_ADDR(ENCI_VBI_TTXDT3) +#define ENCI_MACV_N0 0x1b30 /* register.h:8229 */ +#define P_ENCI_MACV_N0 VCBUS_REG_ADDR(ENCI_MACV_N0) +#define ENCI_MACV_N1 0x1b31 /* register.h:8230 */ +#define P_ENCI_MACV_N1 VCBUS_REG_ADDR(ENCI_MACV_N1) +#define ENCI_MACV_N2 0x1b32 /* register.h:8231 */ +#define P_ENCI_MACV_N2 VCBUS_REG_ADDR(ENCI_MACV_N2) +#define ENCI_MACV_N3 0x1b33 /* register.h:8232 */ +#define P_ENCI_MACV_N3 VCBUS_REG_ADDR(ENCI_MACV_N3) +#define ENCI_MACV_N4 0x1b34 /* register.h:8233 */ +#define P_ENCI_MACV_N4 VCBUS_REG_ADDR(ENCI_MACV_N4) +#define ENCI_MACV_N5 0x1b35 /* register.h:8234 */ +#define P_ENCI_MACV_N5 VCBUS_REG_ADDR(ENCI_MACV_N5) +#define ENCI_MACV_N6 0x1b36 /* register.h:8235 */ +#define P_ENCI_MACV_N6 VCBUS_REG_ADDR(ENCI_MACV_N6) +#define ENCI_MACV_N7 0x1b37 /* register.h:8236 */ +#define P_ENCI_MACV_N7 VCBUS_REG_ADDR(ENCI_MACV_N7) +#define ENCI_MACV_N8 0x1b38 /* register.h:8237 */ +#define P_ENCI_MACV_N8 VCBUS_REG_ADDR(ENCI_MACV_N8) +#define ENCI_MACV_N9 0x1b39 /* register.h:8238 */ +#define P_ENCI_MACV_N9 VCBUS_REG_ADDR(ENCI_MACV_N9) +#define ENCI_MACV_N10 0x1b3a /* register.h:8239 */ +#define P_ENCI_MACV_N10 VCBUS_REG_ADDR(ENCI_MACV_N10) +#define ENCI_MACV_N11 0x1b3b /* register.h:8240 */ +#define P_ENCI_MACV_N11 VCBUS_REG_ADDR(ENCI_MACV_N11) +#define ENCI_MACV_N12 0x1b3c /* register.h:8241 */ +#define P_ENCI_MACV_N12 VCBUS_REG_ADDR(ENCI_MACV_N12) +#define ENCI_MACV_N13 0x1b3d /* register.h:8242 */ +#define P_ENCI_MACV_N13 VCBUS_REG_ADDR(ENCI_MACV_N13) +#define ENCI_MACV_N14 0x1b3e /* register.h:8243 */ +#define P_ENCI_MACV_N14 VCBUS_REG_ADDR(ENCI_MACV_N14) +#define ENCI_MACV_N15 0x1b3f /* register.h:8244 */ +#define P_ENCI_MACV_N15 VCBUS_REG_ADDR(ENCI_MACV_N15) +#define ENCI_MACV_N16 0x1b40 /* register.h:8245 */ +#define P_ENCI_MACV_N16 VCBUS_REG_ADDR(ENCI_MACV_N16) +#define ENCI_MACV_N17 0x1b41 /* register.h:8246 */ +#define P_ENCI_MACV_N17 VCBUS_REG_ADDR(ENCI_MACV_N17) +#define ENCI_MACV_N18 0x1b42 /* register.h:8247 */ +#define P_ENCI_MACV_N18 VCBUS_REG_ADDR(ENCI_MACV_N18) +#define ENCI_MACV_N19 0x1b43 /* register.h:8248 */ +#define P_ENCI_MACV_N19 VCBUS_REG_ADDR(ENCI_MACV_N19) +#define ENCI_MACV_N20 0x1b44 /* register.h:8249 */ +#define P_ENCI_MACV_N20 VCBUS_REG_ADDR(ENCI_MACV_N20) +#define ENCI_MACV_N21 0x1b45 /* register.h:8250 */ +#define P_ENCI_MACV_N21 VCBUS_REG_ADDR(ENCI_MACV_N21) +#define ENCI_MACV_N22 0x1b46 /* register.h:8251 */ +#define P_ENCI_MACV_N22 VCBUS_REG_ADDR(ENCI_MACV_N22) +#define ENCI_DBG_PX_RST 0x1b48 /* register.h:8253 */ +#define P_ENCI_DBG_PX_RST VCBUS_REG_ADDR(ENCI_DBG_PX_RST) +#define ENCI_DBG_FLDLN_RST 0x1b49 /* register.h:8254 */ +#define P_ENCI_DBG_FLDLN_RST VCBUS_REG_ADDR(ENCI_DBG_FLDLN_RST) +#define ENCI_DBG_PX_INT 0x1b4a /* register.h:8255 */ +#define P_ENCI_DBG_PX_INT VCBUS_REG_ADDR(ENCI_DBG_PX_INT) +#define ENCI_DBG_FLDLN_INT 0x1b4b /* register.h:8256 */ +#define P_ENCI_DBG_FLDLN_INT VCBUS_REG_ADDR(ENCI_DBG_FLDLN_INT) +#define ENCI_DBG_MAXPX 0x1b4c /* register.h:8257 */ +#define P_ENCI_DBG_MAXPX VCBUS_REG_ADDR(ENCI_DBG_MAXPX) +#define ENCI_DBG_MAXLN 0x1b4d /* register.h:8258 */ +#define P_ENCI_DBG_MAXLN VCBUS_REG_ADDR(ENCI_DBG_MAXLN) +#define ENCI_MACV_MAX_AMP 0x1b50 /* register.h:8259 */ +#define P_ENCI_MACV_MAX_AMP VCBUS_REG_ADDR(ENCI_MACV_MAX_AMP) +#define ENCI_MACV_PULSE_LO 0x1b51 /* register.h:8260 */ +#define P_ENCI_MACV_PULSE_LO VCBUS_REG_ADDR(ENCI_MACV_PULSE_LO) +#define ENCI_MACV_PULSE_HI 0x1b52 /* register.h:8261 */ +#define P_ENCI_MACV_PULSE_HI VCBUS_REG_ADDR(ENCI_MACV_PULSE_HI) +#define ENCI_MACV_BKP_MAX 0x1b53 /* register.h:8262 */ +#define P_ENCI_MACV_BKP_MAX VCBUS_REG_ADDR(ENCI_MACV_BKP_MAX) +#define ENCI_CFILT_CTRL 0x1b54 /* register.h:8263 */ +#define P_ENCI_CFILT_CTRL VCBUS_REG_ADDR(ENCI_CFILT_CTRL) +#define ENCI_CFILT7 0x1b55 /* register.h:8264 */ +#define P_ENCI_CFILT7 VCBUS_REG_ADDR(ENCI_CFILT7) +#define ENCI_YC_DELAY 0x1b56 /* register.h:8265 */ +#define P_ENCI_YC_DELAY VCBUS_REG_ADDR(ENCI_YC_DELAY) +#define ENCI_VIDEO_EN 0x1b57 /* register.h:8266 */ +#define P_ENCI_VIDEO_EN VCBUS_REG_ADDR(ENCI_VIDEO_EN) +#define VENC_VIDEO_PROG_MODE 0x1b68 /* /../ucode/register.h:8023 */ +#define P_VENC_VIDEO_PROG_MODE VCBUS_REG_ADDR(VENC_VIDEO_PROG_MODE) + +#define ENCI_DVI_HSO_BEGIN 0x1c00 /* register.h:8280 */ +#define P_ENCI_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN) +#define ENCI_DVI_HSO_END 0x1c01 /* register.h:8281 */ +#define P_ENCI_DVI_HSO_END VCBUS_REG_ADDR(ENCI_DVI_HSO_END) +#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 /* register.h:8282 */ +#define P_ENCI_DVI_VSO_BLINE_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN) +#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 /* register.h:8283 */ +#define P_ENCI_DVI_VSO_BLINE_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD) +#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 /* register.h:8284 */ +#define P_ENCI_DVI_VSO_ELINE_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN) +#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 /* register.h:8285 */ +#define P_ENCI_DVI_VSO_ELINE_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD) +#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 /* register.h:8286 */ +#define P_ENCI_DVI_VSO_BEGIN_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN) +#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 /* register.h:8287 */ +#define P_ENCI_DVI_VSO_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD) +#define ENCI_DVI_VSO_END_EVN 0x1c08 /* register.h:8288 */ +#define P_ENCI_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_END_EVN) +#define ENCI_DVI_VSO_END_ODD 0x1c09 /* register.h:8289 */ +#define P_ENCI_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD) +#define ENCI_CFILT_CTRL2 0x1c0a /* register.h:8295 */ +#define P_ENCI_CFILT_CTRL2 VCBUS_REG_ADDR(ENCI_CFILT_CTRL2) +#define ENCI_DACSEL_0 0x1c0b /* register.h:8296 */ +#define P_ENCI_DACSEL_0 VCBUS_REG_ADDR(ENCI_DACSEL_0) +#define ENCI_DACSEL_1 0x1c0c /* register.h:8297 */ +#define P_ENCI_DACSEL_1 VCBUS_REG_ADDR(ENCI_DACSEL_1) +#define ENCP_DACSEL_0 0x1c0d /* register.h:8298 */ +#define P_ENCP_DACSEL_0 VCBUS_REG_ADDR(ENCP_DACSEL_0) +#define ENCP_DACSEL_1 0x1c0e /* register.h:8299 */ +#define P_ENCP_DACSEL_1 VCBUS_REG_ADDR(ENCP_DACSEL_1) +#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f /* register.h:8300 */ +#define P_ENCP_MAX_LINE_SWITCH_POINT VCBUS_REG_ADDR(ENCP_MAX_LINE_SWITCH_POINT) +#define ENCI_TST_EN 0x1c10 /* register.h:8301 */ +#define P_ENCI_TST_EN VCBUS_REG_ADDR(ENCI_TST_EN) +#define ENCI_TST_MDSEL 0x1c11 /* register.h:8302 */ +#define P_ENCI_TST_MDSEL VCBUS_REG_ADDR(ENCI_TST_MDSEL) +#define ENCI_TST_Y 0x1c12 /* register.h:8303 */ +#define P_ENCI_TST_Y VCBUS_REG_ADDR(ENCI_TST_Y) +#define ENCI_TST_CB 0x1c13 /* register.h:8304 */ +#define P_ENCI_TST_CB VCBUS_REG_ADDR(ENCI_TST_CB) +#define ENCI_TST_CR 0x1c14 /* register.h:8305 */ +#define P_ENCI_TST_CR VCBUS_REG_ADDR(ENCI_TST_CR) +#define ENCI_TST_CLRBAR_STRT 0x1c15 /* register.h:8306 */ +#define P_ENCI_TST_CLRBAR_STRT VCBUS_REG_ADDR(ENCI_TST_CLRBAR_STRT) +#define ENCI_TST_CLRBAR_WIDTH 0x1c16 /* register.h:8307 */ +#define P_ENCI_TST_CLRBAR_WIDTH VCBUS_REG_ADDR(ENCI_TST_CLRBAR_WIDTH) +#define ENCI_TST_VDCNT_STSET 0x1c17 /* register.h:8308 */ +#define P_ENCI_TST_VDCNT_STSET VCBUS_REG_ADDR(ENCI_TST_VDCNT_STSET) +#define ENCI_VFIFO2VD_CTL 0x1c18 /* register.h:8313 */ +#define P_ENCI_VFIFO2VD_CTL VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL) +#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 /* register.h:8315 */ +#define P_ENCI_VFIFO2VD_PIXEL_START \ + VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_START) +#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a /* register.h:8317 */ +#define P_ENCI_VFIFO2VD_PIXEL_END VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_END) +#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b /* register.h:8319 */ +#define P_ENCI_VFIFO2VD_LINE_TOP_START \ + VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_START) +#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c /* register.h:8321 */ +#define P_ENCI_VFIFO2VD_LINE_TOP_END \ + VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_END) +#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d /* register.h:8323 */ +#define P_ENCI_VFIFO2VD_LINE_BOT_START \ + VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_START) +#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e /* register.h:8325 */ +#define P_ENCI_VFIFO2VD_LINE_BOT_END \ + VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_END) +#define ENCI_VFIFO2VD_CTL2 0x1c1f /* register.h:8326 */ +#define P_ENCI_VFIFO2VD_CTL2 VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL2) + +#define ENCP_DVI_HSO_BEGIN 0x1c30 /* register.h:8354 */ +#define P_ENCP_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN) +#define ENCP_DVI_HSO_END 0x1c31 /* register.h:8355 */ +#define P_ENCP_DVI_HSO_END VCBUS_REG_ADDR(ENCP_DVI_HSO_END) +#define ENCP_DVI_VSO_BLINE_EVN 0x1c32 /* register.h:8356 */ +#define P_ENCP_DVI_VSO_BLINE_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN) +#define ENCP_DVI_VSO_BLINE_ODD 0x1c33 /* register.h:8357 */ +#define P_ENCP_DVI_VSO_BLINE_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD) +#define ENCP_DVI_VSO_ELINE_EVN 0x1c34 /* register.h:8358 */ +#define P_ENCP_DVI_VSO_ELINE_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN) +#define ENCP_DVI_VSO_ELINE_ODD 0x1c35 /* register.h:8359 */ +#define P_ENCP_DVI_VSO_ELINE_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD) +#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 /* register.h:8360 */ +#define P_ENCP_DVI_VSO_BEGIN_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN) +#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 /* register.h:8361 */ +#define P_ENCP_DVI_VSO_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD) +#define ENCP_DVI_VSO_END_EVN 0x1c38 /* register.h:8362 */ +#define P_ENCP_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN) +#define ENCP_DVI_VSO_END_ODD 0x1c39 /* register.h:8363 */ +#define P_ENCP_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD) +#define ENCP_DE_H_BEGIN 0x1c3a /* register.h:8364 */ +#define P_ENCP_DE_H_BEGIN VCBUS_REG_ADDR(ENCP_DE_H_BEGIN) +#define ENCP_DE_H_END 0x1c3b /* register.h:8365 */ +#define P_ENCP_DE_H_END VCBUS_REG_ADDR(ENCP_DE_H_END) +#define ENCP_DE_V_BEGIN_EVEN 0x1c3c /* register.h:8366 */ +#define P_ENCP_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN) +#define ENCP_DE_V_END_EVEN 0x1c3d /* register.h:8367 */ +#define P_ENCP_DE_V_END_EVEN VCBUS_REG_ADDR(ENCP_DE_V_END_EVEN) +#define ENCP_DE_V_BEGIN_ODD 0x1c3e /* register.h:8368 */ +#define P_ENCP_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD) +#define ENCP_DE_V_END_ODD 0x1c3f /* register.h:8369 */ +#define P_ENCP_DE_V_END_ODD VCBUS_REG_ADDR(ENCP_DE_V_END_ODD) +#define ENCI_SYNC_LINE_LENGTH 0x1c40 /* register.h:8372 */ +#define P_ENCI_SYNC_LINE_LENGTH VCBUS_REG_ADDR(ENCI_SYNC_LINE_LENGTH) +#define ENCI_SYNC_PIXEL_EN 0x1c41 /* register.h:8375 */ +#define P_ENCI_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCI_SYNC_PIXEL_EN) +#define ENCI_SYNC_TO_LINE_EN 0x1c42 /* register.h:8382 */ +#define P_ENCI_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCI_SYNC_TO_LINE_EN) +#define ENCI_SYNC_TO_PIXEL 0x1c43 /* register.h:8384 */ +#define P_ENCI_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCI_SYNC_TO_PIXEL) +#define ENCP_SYNC_LINE_LENGTH 0x1c44 /* register.h:8387 */ +#define P_ENCP_SYNC_LINE_LENGTH VCBUS_REG_ADDR(ENCP_SYNC_LINE_LENGTH) +#define ENCP_SYNC_PIXEL_EN 0x1c45 /* register.h:8390 */ +#define P_ENCP_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCP_SYNC_PIXEL_EN) +#define ENCP_SYNC_TO_LINE_EN 0x1c46 /* register.h:8397 */ +#define P_ENCP_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCP_SYNC_TO_LINE_EN) +#define ENCP_SYNC_TO_PIXEL 0x1c47 /* register.h:8399 */ +#define P_ENCP_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCP_SYNC_TO_PIXEL) + +#define VPP_POSTBLEND_H_SIZE 0x1d21 +#define P_VPP_POSTBLEND_H_SIZE VCBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE) + + +#define VPU_VIU_VENC_MUX_CTRL 0x271a /* register.h:9214 */ +#define P_VPU_VIU_VENC_MUX_CTRL VCBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL) +#define VPU_HDMI_SETTING 0x271b /* register.h:9229 */ +#define P_VPU_HDMI_SETTING VCBUS_REG_ADDR(VPU_HDMI_SETTING) + +#define VPU_HDMI_DATA_OVR 0x2727 /* register.h:9270 */ +#define P_VPU_HDMI_DATA_OVR VCBUS_REG_ADDR(VPU_HDMI_DATA_OVR) +#define VPU_HDMI_FMT_CTRL 0x2743 +#define P_VPU_HDMI_FMT_CTRL VCBUS_REG_ADDR(VPU_HDMI_FMT_CTRL) +/* For GXM and later */ +#define VPU_HDMI_DITH_CNTL 0x27fc +#define P_VPU_HDMI_DITH_CNTL VCBUS_REG_ADDR(VPU_HDMI_DITH_CNTL) + +#endif
diff --git a/include/amlogic/media/vout/lcd/lcd_vout.h b/include/amlogic/media/vout/lcd/lcd_vout.h index 7f2a96e..d603437 100644 --- a/include/amlogic/media/vout/lcd/lcd_vout.h +++ b/include/amlogic/media/vout/lcd/lcd_vout.h
@@ -462,15 +462,16 @@ struct lcd_config_s *lcd_config; struct bl_config_s *bl_config; - int (*outputmode_check)(char *mode); - int (*config_check)(char *mode); + int (*outputmode_check)(char *mode, unsigned int frac); + int (*config_check)(char *mode, unsigned int frac); void (*driver_init_pre)(void); int (*driver_init)(void); void (*driver_disable)(void); void (*list_support_mode)(void); int (*lcd_probe)(void); - int (*lcd_outputmode_check)(char *mode); - void (*lcd_enable)(char *mode); + int (*lcd_outputmode_check)(char *mode, unsigned int frac); + void (*lcd_prepare)(char *mode, unsigned int frac); + void (*lcd_enable)(char *mode, unsigned int frac); void (*lcd_disable)(void); void (*lcd_set_ss)(int level); char *(*lcd_get_ss)(void);
diff --git a/include/amlogic/media/vpp/vpp.h b/include/amlogic/media/vpp/vpp.h index 58d1d7c..1e9b03c 100644 --- a/include/amlogic/media/vpp/vpp.h +++ b/include/amlogic/media/vpp/vpp.h
@@ -23,5 +23,7 @@ extern void vpp_init_lcd_gamma_table(void); extern void vpp_matrix_update(int type); +extern void vpp_viu2_matrix_update(int type); +extern void hdr_tx_pkt_cb(void); #endif
diff --git a/include/amlogic/saradc.h b/include/amlogic/saradc.h index ffcf27f..92a7080 100644 --- a/include/amlogic/saradc.h +++ b/include/amlogic/saradc.h
@@ -6,7 +6,9 @@ #ifndef __MESON_SARADC_H__ #define __MESON_SARADC_H__ +#include <common.h> #include <adc.h> +#include <clk.h> enum ADC_CHANNEL_TYPE { MESON_SARADC_CH0 = 0, @@ -20,6 +22,87 @@ MESON_SARADC_CH_MAX, }; +enum MESON_SARADC_AVG_MODE { + NO_AVERAGING = 0x0, + MEAN_AVERAGING = 0x1, + MEDIAN_AVERAGING = 0x2, +}; + +enum MESON_SARADC_NUM_SAMPLES { + ONE_SAMPLE = 0x0, + TWO_SAMPLES = 0x1, + FOUR_SAMPLES = 0x2, + EIGHT_SAMPLES = 0x3, +}; + +enum MESON_SARADC_RESOLUTION { + SARADC_10BIT = 10, + SARADC_12BIT = 12, + SARADC_22BIT = 22, +}; + +enum MESON_SARADC_BIT_STATE { + BIT_LOW = 0, + BIT_HIGH = 1, +}; + +struct meson_saradc; + +struct meson_saradc_diff_ops { + void (*extra_init)(struct meson_saradc *priv); + void (*set_ch7_mux)(struct meson_saradc *priv, int ch, int mux); + void (*enable_decim_filter)(struct meson_saradc *priv, + int ch, unsigned int mode); + void (*set_ref_voltage)(struct meson_saradc *priv, unsigned int mode); + int (*get_fifo_channel)(int val); + int (*get_fifo_data)(struct meson_saradc *priv, + struct adc_uclass_platdata *uc_pdata, int val); +}; + +/* + * struct meson_saradc_data - describe the differences of different platform + * + * @reg3_ring_counter_disable: to disable continuous ring counter. + * gxl and later: 1; others(gxtvbb etc): 0 + * @reg11_vref_en: g12a and later: 0; others(axg etc): 1 + * @reg11_cmv_sel: g12a and later: 0; others(axg etc): 1 + * @reg11_eoc: g12a and later: 1; others(axg etc): 0 + * @has_bl30_integration: + * @num_channels: the number of adc channels + * @self_test_channel: channel of self-test + * @resolution: gxl and later: 12bit; others(gxtvbb etc): 10bit + * @clock_rate: saradc clock rate + */ +struct meson_saradc_data { + bool reg3_ring_counter_disable; + bool reg11_vref_en; + bool reg11_cmv_sel; + bool reg11_eoc; + bool has_bl30_integration; + unsigned char self_test_channel; + unsigned char num_channels; + unsigned int resolution; + const struct meson_saradc_diff_ops *dops; + unsigned int capacity; + unsigned long clock_rate; +}; + +struct meson_saradc { + phys_addr_t base; + int active_channel; + unsigned int current_mode; + struct clk xtal; + struct clk adc_mux; + struct clk adc_div; + struct clk adc_gate; + struct meson_saradc_data *data; +}; + +extern const struct adc_ops meson_saradc_ops; +int meson_saradc_probe(struct udevice *dev); +int meson_saradc_remove(struct udevice *dev); +int meson_saradc_ofdata_to_platdata(struct udevice *dev); + #define SARADC_CH_SELF_TEST MESON_SARADC_CH7 #endif /*_MESON_SARADC_H_*/
diff --git a/include/amlogic/secure_storage.h b/include/amlogic/secure_storage.h index d3b838f..56b6eca 100644 --- a/include/amlogic/secure_storage.h +++ b/include/amlogic/secure_storage.h
@@ -15,8 +15,6 @@ #define RET_EUND -1 #define SMC_UNK 0xffffffff -/* Attribute*/ -#define OBJ_ATTR_SECURE (1<<0) #ifdef CONFIG_SECURE_STORAGE /* funtion name: secure_storage_write
diff --git a/include/amlogic/storage.h b/include/amlogic/storage.h index 539b8c0..5782e2b 100644 --- a/include/amlogic/storage.h +++ b/include/amlogic/storage.h
@@ -21,6 +21,7 @@ #define DISPROTECT_FBBT BIT(2) #define DISPROTECT_HYNIX BIT(3) +#define PART_PROTECT_FLAG BIT(4) enum boot_type_e { BOOT_EMMC = 1, BOOT_SD = 1 << 1, @@ -39,6 +40,98 @@ #define DISCRETE_BOOTLOADER 1 #define COMPACT_BOOTLOADER 0 +struct nand_startup_parameter { + int page_size; + int block_size; + int layout_reserve_size; + int pages_per_block; + int setup_data; + /* */ + int page0_disable; +}; + +#define IS_FEAT_DIS_EMMC_USER() (0) +#define IS_FEAT_DIS_EMMC_BOOT_0() (0) +#define IS_FEAT_DIS_EMMC_BOOT_1() (0) +#define IS_FEAT_EN_4BL2_SNOR() (0) +#define IS_FEAT_DIS_NBL2_SNOR() (0) +#define IS_FEAT_EN_8BL2_SNAND() (0) +#define IS_FEAT_DIS_NBL2_SNAND() (0) +#define IS_FEAT_DIS_8BL2_NAND() (0) +#define IS_FEAT_DIS_NBL2_NAND() (1) + +#define BL2E_STORAGE_PARAM_SIZE (0x80) +#define BOOT_FIRST_BLOB_SIZE (254*1024) +#define BOOT_FILLER_SIZE (4*1024) +#define BOOT_RESERVED_SIZE (4*1024) +#define BOOT_RANDOM_NONCE (16) +#define BOOT_BL2E_SIZE (66672) //74864-8K +#define BOOT_EBL2E_SIZE (BOOT_FILLER_SIZE + BOOT_RESERVED_SIZE + BOOT_BL2E_SIZE) +#define BOOT_BL2X_SIZE (66672) +#define MAX_BOOT_AREA_ENTRIES (8) +/* bl2 core address base */ +#define BL2_CORE_BASE_OFFSET_EMMC (0x200) +/* boot area entry index */ +#define BOOT_AREA_BB1ST (0) +/* filler and reserved are considered part of the bl2E in storage view */ +#define BOOT_AREA_BL2E (1) +#define BOOT_AREA_BL2X (2) +#define BOOT_AREA_DDRFIP (3) +#define BOOT_AREA_DEVFIP (4) +#define BOOT_AREA_INVALID (MAX_BOOT_AREA_ENTRIES) +/* boot area entry name */ +#define BAE_BB1ST "1STBLOB" +#define BAE_BL2E "BL2E" +#define BAE_BL2X "BL2X" +#define BAE_DDRFIP "DDRFIP" +#define BAE_DEVFIP "DEVFIP" +typedef struct boot_area_entry { + /* name */ + char name[11]; + /* index */ + uint8_t idx; + uint64_t offset; + uint64_t size; +} boot_area_entry_t; + +struct boot_layout { + boot_area_entry_t *boot_entry; +}; + +struct emmc_startup_parameter { + //sd_emmc_setup_t setup; +}; + +struct spi_nand_startup_parameter { + uint32_t pagesize; + uint32_t pages_per_eraseblock; + uint32_t eraseblocks_per_lun; + uint32_t planes_per_lun; + uint32_t luns_per_target; + uint32_t ntargets; + int layout_reserve_size; +}; + +struct storage_boot_entry { + uint32_t offset; + uint32_t size; +}; + +union storage_independent_parameter { + struct nand_startup_parameter nsp; + struct emmc_startup_parameter esp; + struct spi_nand_startup_parameter snasp; +}; + +struct storage_startup_parameter { + uint8_t boot_device; + uint8_t boot_seq; + uint8_t boot_bakups; + uint8_t reserved; + struct storage_boot_entry boot_entry[MAX_BOOT_AREA_ENTRIES]; + union storage_independent_parameter sip; +}; + struct storage_info_t { u8 name[32]; u8 id[8]; @@ -244,6 +337,27 @@ u8 store_boot_copy_num(const char *name); /** + * @usage: get the 1st boot copy nubmer of current device. + * for eMMC: 0 -> user partition; 1 -> boot0; 2 -> boot1 + */ +u8 store_boot_copy_start(void); + +/** + * @usage: get the bootup index of [name] + * + * @name: do not care discrete mode or compact mode + * "bl2" "spl" could be used as the one romboot loaded + * "fip" "devfip" "tpl" or "bootloader" would be the main u-boot. + * @return: the copy number of the "bootloader" or "tpl" + */ +u8 store_bootup_bootidx(const char *name); + +/** + * @usage: restore the bootidx/bootdev etc. + */ +void store_restore_bootidx(void); + +/** * @usage: get the copy size of [name] * * @name: name: only can be "bl2" or "tpl"/"fip" in discrete mode
diff --git a/include/amlogic/store_wrapper.h b/include/amlogic/store_wrapper.h index a181cf6..18cb582 100644 --- a/include/amlogic/store_wrapper.h +++ b/include/amlogic/store_wrapper.h
@@ -14,5 +14,37 @@ u64 store_logic_cap(const char* partName); +#define AML_MAGIC_HDR_L (0x4c4d4140) //"@AML" +#define AML_MAGIC_HDR_R (0x544f4f42) //"BOOT" + +#define AML_MAGIC_CORE (0X54534242) //"BBST" +#define AML_MAGIC_BL2E (0x45324c42) //"BL2E" +#define AML_MAGIC_BL2X (0x58324c42) //"BL2X" +#define AML_MAGIC_DDRF (0x46524444) //"DDRF" +#define AML_MAGIC_DEVF (0x46564544) //"DEVF" +typedef struct{ + unsigned int nMagic; //"BBST", "BL2E", "BL2X", "DDRF", "DEVF" + unsigned int nOffset; //offset from file head of file + unsigned int nPayLoadSize; //size of payload + unsigned int nReserved; //reserved for future +}payload_info_item_t, *p_payload_info_item_t; + +typedef struct{ + unsigned char szSHA2[32]; //sha256 of sizeof(payload_info_t) - sizeof(szSHA2) + unsigned int nMagicL; //"@AML" + unsigned int nMagicR; //"BOOT" + unsigned char byVersion; //version:0,1,2,.... + unsigned char byItemNum; //number of items + unsigned short nSize; //sizeof(this) = sizeof(hdr) + sizeof(item) * byItemNum + unsigned char szReserved1[4]; + char szTimeStamp[16];//"SC2-YYYYMMDDHHmm" e.g "SC2-202007082259" + +}payload_info_hdr_t, *p_payload_info_hdr_t; + +typedef struct{ + payload_info_hdr_t hdr; //header + payload_info_item_t arrItems[1]; //items +}payload_info_t, *p_payload_info_t; + #endif//#ifndef __STORE_WRAPPER_H__
diff --git a/include/android_image.h b/include/android_image.h old mode 100644 new mode 100755
diff --git a/include/android_vab.h b/include/android_vab.h new file mode 100644 index 0000000..7539250 --- /dev/null +++ b/include/android_vab.h
@@ -0,0 +1,58 @@ +/*Virtual A/B merge status information*/ + +// Spaces used by misc partition are as below: +// 0 - 2K For bootloader_message +// 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used +// as bootloader_message_ab struct) +// 16K - 32K Used by uncrypt and recovery to store wipe_package for A/B devices +// 32K - 64K System space, used for miscellanious AOSP features. See below. +// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they +// are not configurable without changing all of them. + +#ifndef _ANDROID_VAB_H_ +#define _ANDROID_VAB_H_ + +#define BOOTLOADER_MESSAGE_OFFSET_IN_MISC 0 +#define VENDOR_SPACE_OFFSET_IN_MISC 2 * 1024 +#define WIPE_PACKAGE_OFFSET_IN_MISC 16 * 1024 +#define SYSTEM_SPACE_OFFSET_IN_MISC 32 * 1024 +#define SYSTEM_SPACE_SIZE_IN_MISC 32 * 1024 + +enum MergeStatus { + /** + * No snapshot or merge is in progress. + */ + NONE = 0, + + /** + * The merge status could not be determined. + */ + UNKNOWN, + + /** + * Partitions are being snapshotted, but no merge has been started. + */ + SNAPSHOTTED, + + /** + * At least one partition has merge is in progress. + */ + MERGING, + + /** + * A merge was in progress, but it was canceled by the bootloader. + */ + CANCELLED, +}; + +// Holds Virtual A/B merge status information. Current version is 1. New fields +// must be added to the end. +struct misc_virtual_ab_message { + uint8_t version; + uint32_t magic; + uint8_t merge_status; // IBootControl 1.1, MergeStatus enum. + uint8_t source_slot; // Slot number when merge_status was written. + uint8_t reserved[57]; +}; + +#endif
diff --git a/include/dt-bindings/clock/a1-clkc.h b/include/dt-bindings/clock/a1-clkc.h index 1276e4f..cae55e9 100644 --- a/include/dt-bindings/clock/a1-clkc.h +++ b/include/dt-bindings/clock/a1-clkc.h
@@ -23,19 +23,22 @@ #define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 2) #define CLKID_SD_EMMC_XTAL_GATE (CLKID_GATE_BASE + 3) #define CLKID_SD_EMMC_GATE (CLKID_GATE_BASE + 4) +#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 5) -#define CLKID_MUX_BASE (CLKID_GATE_BASE + 5) +#define CLKID_MUX_BASE (CLKID_GATE_BASE + 6) #define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0) #define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1) #define CLKID_SD_EMMC_MUX (CLKID_MUX_BASE + 2) +#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 3) -#define CLKID_DIV_BASE (CLKID_MUX_BASE + 3) +#define CLKID_DIV_BASE (CLKID_MUX_BASE + 4) #define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0) #define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1) #define CLKID_SD_EMMC_DIV (CLKID_DIV_BASE + 2) +#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 3) /* CLKTREE_SYS_CLK_EN0 gates*/ -#define GATE_BASE0 (CLKID_DIV_BASE + 3) +#define GATE_BASE0 (CLKID_DIV_BASE + 4) #define CLKID_CLKTREE (GATE_BASE0 + 0) #define CLKID_RESET_CTRL (GATE_BASE0 + 1) #define CLKID_ANALOG_CTRL (GATE_BASE0 + 2)
diff --git a/include/dt-bindings/clock/c1-clkc.h b/include/dt-bindings/clock/c1-clkc.h index 27c73c4..eef6d95 100644 --- a/include/dt-bindings/clock/c1-clkc.h +++ b/include/dt-bindings/clock/c1-clkc.h
@@ -18,18 +18,23 @@ #define CLKID_FCLK_DIV4 7 #define CLKID_SYS_CLK 8 #define CLKID_SYS_PLL 9 +#define CLKID_SD_EMMC_A_XTAL_GATE 10 +#define CLKID_SD_EMMC_B_XTAL_GATE 11 +#define CLKID_SD_EMMC_C_XTAL_GATE 12 -#define CLKID_GATE_BASE 10 -#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 0) -#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 1) -#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 2) -#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 3) -#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 4) -#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 5) -#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 6) -#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 7) -#define CLKID_MUX_BASE (CLKID_GATE_BASE + 8) +#define CLKID_GATE_BASE 13 +#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0) +#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1) +#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 2) +#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 3) +#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 4) +#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 5) +#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 6) +#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 7) +#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 8) + +#define CLKID_MUX_BASE (CLKID_GATE_BASE + 9) #define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0) #define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1) #define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 2)
diff --git a/include/dt-bindings/clock/c2-clkc.h b/include/dt-bindings/clock/c2-clkc.h new file mode 100644 index 0000000..39c9435 --- /dev/null +++ b/include/dt-bindings/clock/c2-clkc.h
@@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_CLOCK_C2_H +#define __DT_BINDINGS_CLOCK_C2_H +/* + * CLKID index values + */ +#define CLKID_XTAL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV5 4 +#define CLKID_FCLK_DIV7 5 +#define CLKID_FCLK_DIV2P5 6 +#define CLKID_FCLK_DIV4 7 +#define CLKID_SYS_CLK 8 +#define CLKID_SYS_PLL 9 +#define CLKID_SD_EMMC_A_XTAL_GATE 10 +#define CLKID_SD_EMMC_B_XTAL_GATE 11 +#define CLKID_SD_EMMC_C_XTAL_GATE 12 + + +#define CLKID_GATE_BASE 13 +#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0) +#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1) +#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 2) +#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 3) +#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 4) +#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 5) +#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 6) +#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 7) +#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 8) + +#define CLKID_MUX_BASE (CLKID_GATE_BASE + 9) +#define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0) +#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1) +#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 2) +#define CLKID_SPICC_B_MUX (CLKID_MUX_BASE + 3) +#define CLKID_SD_EMMC_B_MUX (CLKID_MUX_BASE + 4) +#define CLKID_SD_EMMC_C_MUX (CLKID_MUX_BASE + 5) +#define CLKID_SD_EMMC_A_MUX (CLKID_MUX_BASE + 6) + +#define CLKID_DIV_BASE (CLKID_MUX_BASE + 7) +#define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0) +#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1) +#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 2) +#define CLKID_SPICC_B_DIV (CLKID_DIV_BASE + 3) +#define CLKID_SD_EMMC_B_DIV (CLKID_DIV_BASE + 4) +#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 5) +#define CLKID_SD_EMMC_A_DIV (CLKID_MUX_BASE + 6) + +/* CLKTREE_SYS_CLK_EN0 gates*/ +#define GATE_BASE0 (CLKID_DIV_BASE + 7) +#define CLKID_CLKTREE (GATE_BASE0 + 0) +#define CLKID_RESET_CTRL (GATE_BASE0 + 1) +#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2) +#define CLKID_PWR_CTRL (GATE_BASE0 + 3) +#define CLKID_PAD_CTRL (GATE_BASE0 + 4) +#define CLKID_SYS_CTRL (GATE_BASE0 + 5) +#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6) +#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7) +#define CLKID_SPICC_B (GATE_BASE0 + 8) +#define CLKID_SPICC_A (GATE_BASE0 + 9) +#define CLKID_CLK_MSR (GATE_BASE0 + 10) +#define CLKID_AUDIO (GATE_BASE0 + 11) +#define CLKID_JTAG_CTRL (GATE_BASE0 + 12) +#define CLKID_SARADC (GATE_BASE0 + 13) +#define CLKID_PWM_EF (GATE_BASE0 + 14) +#define CLKID_PWM_CD (GATE_BASE0 + 15) +#define CLKID_PWM_AB (GATE_BASE0 + 16) +#define CLKID_CEC (GATE_BASE0 + 17) +#define CLKID_I2C_S (GATE_BASE0 + 18) +#define CLKID_IR_CTRL (GATE_BASE0 + 19) +#define CLKID_I2C_M_D (GATE_BASE0 + 20) +#define CLKID_I2C_M_C (GATE_BASE0 + 21) +#define CLKID_I2C_M_B (GATE_BASE0 + 22) +#define CLKID_I2C_M_A (GATE_BASE0 + 23) +#define CLKID_ACODEC (GATE_BASE0 + 24) +#define CLKID_OTP (GATE_BASE0 + 25) +#define CLKID_SD_EMMC_A (GATE_BASE0 + 26) +#define CLKID_USB_PHY (GATE_BASE0 + 27) +#define CLKID_USB_CTRL (GATE_BASE0 + 28) +#define CLKID_SYS_DSPB (GATE_BASE0 + 29) +#define CLKID_SYS_DSPA (GATE_BASE0 + 30) +#define CLKID_DMA (GATE_BASE0 + 31) +/* CLKTREE_SYS_CLK_EN1 gates*/ +#define GATE_BASE1 (GATE_BASE0 + 32) +#define CLKID_IRQ_CTRL (GATE_BASE1 + 0) +#define CLKID_NIC (GATE_BASE1 + 1) +#define CLKID_GIC (GATE_BASE1 + 2) +#define CLKID_UART_C (GATE_BASE1 + 3) +#define CLKID_UART_B (GATE_BASE1 + 4) +#define CLKID_UART_A (GATE_BASE1 + 5) +#define CLKID_SYS_PSRAM (GATE_BASE1 + 6) +#define CLKID_RSA (GATE_BASE1 + 7) +#define CLKID_CORESIGHT (GATE_BASE1 + 8) +/* CLKTREE_AXI_CLK_EN gates */ +#define GATE_BASE2 (GATE_BASE1 + 9) +#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0) +#define CLKID_AUDIO_VAD (GATE_BASE2 + 1) +#define CLKID_AXI_DMC (GATE_BASE2 + 2) +#define CLKID_AXI_PSRAM (GATE_BASE2 + 3) +#define CLKID_RAMB (GATE_BASE2 + 4) +#define CLKID_RAMA (GATE_BASE2 + 5) +#define CLKID_AXI_SPIFC (GATE_BASE2 + 6) +#define CLKID_AXI_NIC (GATE_BASE2 + 7) +#define CLKID_AXI_DMA (GATE_BASE2 + 8) +#define CLKID_CPU_CTRL (GATE_BASE2 + 9) +#define CLKID_ROM (GATE_BASE2 + 10) +#define CLKID_PROC_I2C (GATE_BASE2 + 11) + +#define CLKID_UNREALIZED 100 + +#endif /* __A1_CLKC_H */
diff --git a/include/dt-bindings/clock/sc2-clkc.h b/include/dt-bindings/clock/sc2-clkc.h new file mode 100644 index 0000000..4c8b1ee --- /dev/null +++ b/include/dt-bindings/clock/sc2-clkc.h
@@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __DT_BINDINGS_CLOCK_SC2_H +#define __DT_BINDINGS_CLOCK_SC2_H +/* + * CLKID index values + */ +#define CLKID_XTAL 0 +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 2 +#define CLKID_FCLK_DIV3 3 +#define CLKID_FCLK_DIV5 4 +#define CLKID_FCLK_DIV7 5 +#define CLKID_FCLK_DIV2P5 6 +#define CLKID_FCLK_DIV4 7 +#define CLKID_SYS_CLK 8 +#define CLKID_SYS_PLL 9 +#define CLKID_SD_EMMC_A_XTAL_GATE 10 +#define CLKID_SD_EMMC_B_XTAL_GATE 11 +#define CLKID_SD_EMMC_C_XTAL_GATE 12 + + +#define CLKID_GATE_BASE 13 +#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0) +#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1) +#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 2) +#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 3) +#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 4) +#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 5) +#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 6) +#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 7) +#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 8) + +#define CLKID_MUX_BASE (CLKID_GATE_BASE + 9) +#define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0) +#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1) +#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 2) +#define CLKID_SPICC_B_MUX (CLKID_MUX_BASE + 3) +#define CLKID_SD_EMMC_B_MUX (CLKID_MUX_BASE + 4) +#define CLKID_SD_EMMC_C_MUX (CLKID_MUX_BASE + 5) +#define CLKID_SD_EMMC_A_MUX (CLKID_MUX_BASE + 6) + +#define CLKID_DIV_BASE (CLKID_MUX_BASE + 7) +#define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0) +#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1) +#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 2) +#define CLKID_SPICC_B_DIV (CLKID_DIV_BASE + 3) +#define CLKID_SD_EMMC_B_DIV (CLKID_DIV_BASE + 4) +#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 5) +#define CLKID_SD_EMMC_A_DIV (CLKID_MUX_BASE + 6) + +/* CLKTREE_SYS_CLK_EN0 gates*/ +#define GATE_BASE0 (CLKID_DIV_BASE + 7) +#define CLKID_CLKTREE (GATE_BASE0 + 0) +#define CLKID_RESET_CTRL (GATE_BASE0 + 1) +#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2) +#define CLKID_PWR_CTRL (GATE_BASE0 + 3) +#define CLKID_PAD_CTRL (GATE_BASE0 + 4) +#define CLKID_SYS_CTRL (GATE_BASE0 + 5) +#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6) +#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7) +#define CLKID_SPICC_B (GATE_BASE0 + 8) +#define CLKID_SPICC_A (GATE_BASE0 + 9) +#define CLKID_CLK_MSR (GATE_BASE0 + 10) +#define CLKID_AUDIO (GATE_BASE0 + 11) +#define CLKID_JTAG_CTRL (GATE_BASE0 + 12) +#define CLKID_SARADC (GATE_BASE0 + 13) +#define CLKID_PWM_EF (GATE_BASE0 + 14) +#define CLKID_PWM_CD (GATE_BASE0 + 15) +#define CLKID_PWM_AB (GATE_BASE0 + 16) +#define CLKID_CEC (GATE_BASE0 + 17) +#define CLKID_I2C_S (GATE_BASE0 + 18) +#define CLKID_IR_CTRL (GATE_BASE0 + 19) +#define CLKID_I2C_M_D (GATE_BASE0 + 20) +#define CLKID_I2C_M_C (GATE_BASE0 + 21) +#define CLKID_I2C_M_B (GATE_BASE0 + 22) +#define CLKID_I2C_M_A (GATE_BASE0 + 23) +#define CLKID_ACODEC (GATE_BASE0 + 24) +#define CLKID_OTP (GATE_BASE0 + 25) +#define CLKID_SD_EMMC_A (GATE_BASE0 + 26) +#define CLKID_USB_PHY (GATE_BASE0 + 27) +#define CLKID_USB_CTRL (GATE_BASE0 + 28) +#define CLKID_SYS_DSPB (GATE_BASE0 + 29) +#define CLKID_SYS_DSPA (GATE_BASE0 + 30) +#define CLKID_DMA (GATE_BASE0 + 31) +/* CLKTREE_SYS_CLK_EN1 gates*/ +#define GATE_BASE1 (GATE_BASE0 + 32) +#define CLKID_IRQ_CTRL (GATE_BASE1 + 0) +#define CLKID_NIC (GATE_BASE1 + 1) +#define CLKID_GIC (GATE_BASE1 + 2) +#define CLKID_UART_C (GATE_BASE1 + 3) +#define CLKID_UART_B (GATE_BASE1 + 4) +#define CLKID_UART_A (GATE_BASE1 + 5) +#define CLKID_SYS_PSRAM (GATE_BASE1 + 6) +#define CLKID_RSA (GATE_BASE1 + 7) +#define CLKID_CORESIGHT (GATE_BASE1 + 8) +/* CLKTREE_AXI_CLK_EN gates */ +#define GATE_BASE2 (GATE_BASE1 + 9) +#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0) +#define CLKID_AUDIO_VAD (GATE_BASE2 + 1) +#define CLKID_AXI_DMC (GATE_BASE2 + 2) +#define CLKID_AXI_PSRAM (GATE_BASE2 + 3) +#define CLKID_RAMB (GATE_BASE2 + 4) +#define CLKID_RAMA (GATE_BASE2 + 5) +#define CLKID_AXI_SPIFC (GATE_BASE2 + 6) +#define CLKID_AXI_NIC (GATE_BASE2 + 7) +#define CLKID_AXI_DMA (GATE_BASE2 + 8) +#define CLKID_CPU_CTRL (GATE_BASE2 + 9) +#define CLKID_ROM (GATE_BASE2 + 10) +#define CLKID_PROC_I2C (GATE_BASE2 + 11) + +#define CLKID_UNREALIZED 100 + +#endif /* __SC2_CLKC_H */
diff --git a/include/dt-bindings/gpio/meson-c2-gpio.h b/include/dt-bindings/gpio/meson-c2-gpio.h new file mode 100644 index 0000000..4f5e4eb --- /dev/null +++ b/include/dt-bindings/gpio/meson-c2-gpio.h
@@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MESON_C2_GPIO_H +#define _DT_BINDINGS_MESON_C2_GPIO_H +#define GPIOD_0 0 +#define GPIOD_1 1 +#define GPIOD_2 2 +#define GPIOD_3 3 +#define GPIOD_4 4 +#define GPIOD_5 5 +#define GPIOD_6 6 +#define GPIOD_7 7 +#define GPIOD_8 8 +#define GPIOD_9 9 +#define GPIOD_10 10 +#define GPIOD_11 11 +#define GPIOD_12 12 +#define GPIOD_13 13 + +#define GPIOE_0 14 +#define GPIOE_1 15 +#define GPIOE_2 16 + +#define GPIOB_0 17 +#define GPIOB_1 18 +#define GPIOB_2 19 +#define GPIOB_3 20 +#define GPIOB_4 21 +#define GPIOB_5 22 +#define GPIOB_6 23 +#define GPIOB_7 24 +#define GPIOB_8 25 +#define GPIOB_9 26 +#define GPIOB_10 27 +#define GPIOB_11 28 +#define GPIOB_12 29 +#define GPIOB_13 30 + +#define GPIOC_0 31 +#define GPIOC_1 32 +#define GPIOC_2 33 +#define GPIOC_3 34 +#define GPIOC_4 35 +#define GPIOC_5 36 +#define GPIOC_6 37 + +#define GPIOX_0 38 +#define GPIOX_1 39 +#define GPIOX_2 40 +#define GPIOX_3 41 +#define GPIOX_4 42 +#define GPIOX_5 43 +#define GPIOX_6 44 +#define GPIOX_7 45 +#define GPIOX_8 46 +#define GPIOX_9 47 +#define GPIOX_10 48 +#define GPIOX_11 49 +#define GPIOX_12 50 +#define GPIOX_13 51 +#define GPIOX_14 52 +#define GPIOX_15 53 +#define GPIOX_16 54 +#define GPIOX_17 55 +#define GPIOX_18 56 +#define GPIOX_19 57 +#define GPIOX_20 58 + +#define GPIOM_0 59 +#define GPIOM_1 60 +#define GPIOM_2 61 +#define GPIOM_3 62 +#define GPIOM_4 63 +#define GPIOM_5 64 +#define GPIOM_6 65 +#define GPIOM_7 66 +#define GPIOM_8 67 +#define GPIOM_9 68 +#define GPIOM_10 69 +#define GPIOM_11 70 +#define GPIOM_12 71 +#define GPIOM_13 72 + +#define GPIOA_0 73 +#define GPIOA_1 74 +#define GPIOA_2 75 +#define GPIOA_3 76 +#define GPIOA_4 77 +#define GPIOA_5 78 +#define GPIOA_6 79 +#define GPIOA_7 80 +#define GPIOA_8 81 +#define GPIOA_9 82 +#define GPIOA_10 83 +#define GPIOA_11 84 +#define GPIOA_12 85 +#define GPIOA_13 86 +#define GPIOA_14 87 +#define GPIOA_15 88 + +#define GPIO_TEST_N 89 +#endif /* _DT_BINDINGS_MESON_C2_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-sc2-gpio.h b/include/dt-bindings/gpio/meson-sc2-gpio.h new file mode 100644 index 0000000..a674bfd --- /dev/null +++ b/include/dt-bindings/gpio/meson-sc2-gpio.h
@@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_MESON_SC2_GPIO_H +#define _DT_BINDINGS_MESON_SC2_GPIO_H +#define GPIOA_14 0 +#define GPIOA_15 1 + +#define GPIOB_0 2 +#define GPIOB_1 3 +#define GPIOB_2 4 +#define GPIOB_3 5 +#define GPIOB_4 6 +#define GPIOB_5 7 +#define GPIOB_6 8 +#define GPIOB_7 9 +#define GPIOB_8 10 +#define GPIOB_9 11 +#define GPIOB_10 12 +#define GPIOB_11 13 +#define GPIOB_12 14 +#define GPIOB_13 15 +#define GPIOB_14 16 +#define GPIOB_15 17 + +#define GPIOC_0 18 +#define GPIOC_1 19 +#define GPIOC_2 20 +#define GPIOC_3 21 +#define GPIOC_4 22 +#define GPIOC_5 23 +#define GPIOC_6 24 +#define GPIOC_7 25 + +#define GPIOE_0 26 +#define GPIOE_1 27 +#define GPIOE_2 28 + +#define GPIOD_0 29 +#define GPIOD_1 30 +#define GPIOD_2 31 +#define GPIOD_3 32 +#define GPIOD_4 33 +#define GPIOD_5 34 +#define GPIOD_6 35 +#define GPIOD_7 36 +#define GPIOD_8 37 +#define GPIOD_9 38 +#define GPIOD_10 39 +#define GPIOD_11 40 + +#define GPIOH_0 41 +#define GPIOH_1 42 +#define GPIOH_2 43 +#define GPIOH_3 44 +#define GPIOH_4 45 +#define GPIOH_5 46 +#define GPIOH_6 47 +#define GPIOH_7 48 +#define GPIOH_8 49 + +#define GPIOX_0 50 +#define GPIOX_1 51 +#define GPIOX_2 52 +#define GPIOX_3 53 +#define GPIOX_4 54 +#define GPIOX_5 55 +#define GPIOX_6 56 +#define GPIOX_7 57 +#define GPIOX_8 58 +#define GPIOX_9 59 +#define GPIOX_10 60 +#define GPIOX_11 61 +#define GPIOX_12 62 +#define GPIOX_13 63 +#define GPIOX_14 64 +#define GPIOX_15 65 +#define GPIOX_16 66 +#define GPIOX_17 67 +#define GPIOX_18 68 +#define GPIOX_19 69 + +#define GPIOZ_0 70 +#define GPIOZ_1 71 +#define GPIOZ_2 72 +#define GPIOZ_3 73 +#define GPIOZ_4 74 +#define GPIOZ_5 75 +#define GPIOZ_6 76 +#define GPIOZ_7 77 +#define GPIOZ_8 78 +#define GPIOZ_9 79 +#define GPIOZ_10 80 +#define GPIOZ_11 81 +#define GPIOZ_12 82 +#define GPIOZ_13 83 +#define GPIOZ_14 84 +#define GPIOZ_15 85 + +#define GPIO_TEST_N 86 +#endif /* _DT_BINDINGS_MESON_SC2_GPIO_H */
diff --git a/include/emmc_partitions.h b/include/emmc_partitions.h index c09089c..91920cb 100644 --- a/include/emmc_partitions.h +++ b/include/emmc_partitions.h
@@ -99,6 +99,19 @@ #define CALI_PATTERN_OFFSET (SZ_1M * 3) #define CALI_PATTERN_SIZE (256 * 512) #define CALI_BLOCK_SIZE (512) +#define CALI_PATTERN (0x55aa55aa) + +#define MMC_MAGIC_NAME "magic" +#define MAGIC_OFFSET (SZ_1M * 6) +#define MAGIC_SIZE (256 * 512) +#define MAGIC_BLOCK_SIZE (512) +#define MAGIC_PATTERN (0X00FF00FF) + +#define MMC_RANDOM_NAME "random" +#define RANDOM_OFFSET (SZ_1M * 7) +#define RANDOM_SIZE (256 * 512) +#define RANDOM_BLOCK_SIZE (512) +#define RANDOM_PATTERN (0X52414E44) /* * 2 copies dtb were stored in dtb area. * each is 256K. @@ -130,6 +143,12 @@ #define VIRTUAL_PARTITION_ELEMENT(na, of, sz) {.name = na, .offset = of, .size = sz,} +struct aml_pattern { + char name[MAX_MMC_PART_NAME_LEN]; + unsigned int pattern; +}; +#define AML_PATTERN_ELEMENT(na, pa) {.name = na, .pattern = pa,} + #ifdef AML_MMC_DBG #define aml_mmc_dbg(fmt, ...) printk( "%s: line:%d " fmt "\n", \ __func__, __LINE__, ##__VA_ARGS__) @@ -202,14 +221,15 @@ #define LOCK_MAJOR_VERSION 1 #define LOCK_MINOR_VERSION 0 -#define LOCK_DATA_SIZE 8 +#define LOCK_DATA_SIZE 16 typedef struct LockData { uint8_t version_major; uint8_t version_minor; + uint8_t unlock_ability; /* Padding to eight bytes. */ - uint8_t reserved1[2]; + uint8_t reserved1; /* 0: unlock 1: lock*/ uint8_t lock_state;
diff --git a/include/emmc_storage.h b/include/emmc_storage.h index 65f07e0..5c4b4c4 100644 --- a/include/emmc_storage.h +++ b/include/emmc_storage.h
@@ -58,10 +58,10 @@ unsigned mask_flags; /* master flags to mask out for this partition */ #ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY #if CONFIG_IS_ENABLED(PARTITION_UUIDS) - char uuid[UUID_STR_LEN + 1]; /* filesystem UUID as string, if exists */ + efi_guid_t uuid; /* filesystem UUID as string, if exists */ #endif #ifdef CONFIG_PARTITION_TYPE_GUID - char type_guid[UUID_STR_LEN + 1]; /* type GUID as string, if exists */ + efi_guid_t type_guid; /* type GUID as string, if exists */ #endif gpt_entry_attributes attributes; #endif
diff --git a/include/fastboot.h b/include/fastboot.h index 1933b1d..229bed8 100644 --- a/include/fastboot.h +++ b/include/fastboot.h
@@ -12,31 +12,40 @@ #ifndef _FASTBOOT_H_ #define _FASTBOOT_H_ +#include <android_vab.h> + #define FASTBOOT_VERSION "0.4" /* The 64 defined bytes plus \0 */ #define FASTBOOT_COMMAND_LEN (64 + 1) #define FASTBOOT_RESPONSE_LEN (64 + 1) +extern int busy_flag; + /** * All known commands to fastboot */ enum { FASTBOOT_COMMAND_GETVAR = 0, FASTBOOT_COMMAND_DOWNLOAD, +#ifndef CONFIG_NO_FASTBOOT_FLASHING + FASTBOOT_COMMAND_FLASHING, +#endif //CONFIG_NO_FASTBOOT_FLASHING #if CONFIG_IS_ENABLED(FASTBOOT_FLASH) FASTBOOT_COMMAND_FLASH, FASTBOOT_COMMAND_ERASE, #endif FASTBOOT_COMMAND_BOOT, FASTBOOT_COMMAND_CONTINUE, - FASTBOOT_COMMAND_REBOOT, FASTBOOT_COMMAND_REBOOT_BOOTLOADER, + FASTBOOT_COMMAND_REBOOT_FASTBOOT, + FASTBOOT_COMMAND_REBOOT, FASTBOOT_COMMAND_SET_ACTIVE, + FASTBOOT_COMMAND_SNAOSHOT_UPDATE, #if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT) FASTBOOT_COMMAND_OEM_FORMAT, #endif - + FASTBOOT_COMMAND_OEM, FASTBOOT_COMMAND_COUNT }; @@ -60,6 +69,14 @@ void fastboot_fail(const char *reason, char *response); /** + * fastboot_busy() - Write a INFO response of the form "INFO$reason". + * + * @reason: Pointer to returned reason string + * @response: Pointer to fastboot response buffer + */ +void fastboot_busy(const char *reason, char *response); + +/** * fastboot_okay() - Write an OKAY response of the form "OKAY$reason". * * @reason: Pointer to returned reason string, or NULL to send a bare "OKAY" @@ -68,6 +85,23 @@ void fastboot_okay(const char *reason, char *response); /** + *check lock state + *return 1 if locked + *return 0 if unlocked + */ +int check_lock(void); + +/** + *get merge status +*/ +int get_mergestatus(struct misc_virtual_ab_message *message); + +/** + *set merge status +*/ +int set_mergestatus_cancel(struct misc_virtual_ab_message *message); + +/** * fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader * * Set flag which indicates that we should reboot into the bootloader
diff --git a/include/generic-phy.h b/include/generic-phy.h index 25ffde5..a0f1eb3 100644 --- a/include/generic-phy.h +++ b/include/generic-phy.h
@@ -121,6 +121,7 @@ */ int (*power_off)(struct phy *phy); int (*tuning)(struct phy *phy, int port); + int (*getinfo)(struct phy *phy); }; #ifdef CONFIG_PHY @@ -223,6 +224,7 @@ */ int generic_phy_get_by_name(struct udevice *user, const char *phy_name, struct phy *phy); +int generic_phy_getinfo(struct phy *phy); #else /* CONFIG_PHY */
diff --git a/include/image-android-dt.h b/include/image-android-dt.h index 9a3aa8f..92e21c0 100644 --- a/include/image-android-dt.h +++ b/include/image-android-dt.h
@@ -10,6 +10,7 @@ #include <linux/types.h> bool android_dt_check_header(ulong hdr_addr); +u32 android_dt_get_totalsize(ulong hdr_addr); bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr, u32 *size);
diff --git a/include/image.h b/include/image.h old mode 100644 new mode 100755
diff --git a/include/libavb/avb_slot_verify.h b/include/libavb/avb_slot_verify.h index 24acf1f..b57890d 100644 --- a/include/libavb/avb_slot_verify.h +++ b/include/libavb/avb_slot_verify.h
@@ -258,6 +258,8 @@ size_t num_loaded_partitions; char* cmdline; uint64_t rollback_indexes[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]; + uint8_t boot_key_hash[AVB_SHA256_DIGEST_SIZE]; + uint8_t vbmeta_digest[AVB_SHA256_DIGEST_SIZE]; } AvbSlotVerifyData; /* Frees a |AvbSlotVerifyData| including all data it points to. */
diff --git a/include/linux/kern_levels.h b/include/linux/kern_levels.h new file mode 100644 index 0000000..890a334 --- /dev/null +++ b/include/linux/kern_levels.h
@@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __KERN_LEVELS_H__ +#define __KERN_LEVELS_H__ + +#define KERN_SOH "\001" /* ASCII Start Of Header */ +#define KERN_SOH_ASCII '\001' + +#define KERN_EMERG KERN_SOH "0" /* system is unusable */ +#define KERN_ALERT KERN_SOH "1" /* action must be taken immediately */ +#define KERN_CRIT KERN_SOH "2" /* critical conditions */ +#define KERN_ERR KERN_SOH "3" /* error conditions */ +#define KERN_WARNING KERN_SOH "4" /* warning conditions */ +#define KERN_NOTICE KERN_SOH "5" /* normal but significant condition */ +#define KERN_INFO KERN_SOH "6" /* informational */ +#define KERN_DEBUG KERN_SOH "7" /* debug-level messages */ + +#define KERN_DEFAULT KERN_SOH "d" /* the default kernel loglevel */ + +/* + * Annotation for a "continued" line of log printout (only done after a + * line that had no enclosing \n). Only to be used by core/arch code + * during early bootup (a continued line is not SMP-safe otherwise). + */ +#define KERN_CONT KERN_SOH "c" + +/* integer equivalents of KERN_<LEVEL> */ +#define LOGLEVEL_SCHED -2 /* Deferred messages from sched code + * are set to this special level */ +#define LOGLEVEL_DEFAULT -1 /* default (or last) loglevel */ +#define LOGLEVEL_EMERG 0 /* system is unusable */ +#define LOGLEVEL_ALERT 1 /* action must be taken immediately */ +#define LOGLEVEL_CRIT 2 /* critical conditions */ +#define LOGLEVEL_ERR 3 /* error conditions */ +#define LOGLEVEL_WARNING 4 /* warning conditions */ +#define LOGLEVEL_NOTICE 5 /* normal but significant condition */ +#define LOGLEVEL_INFO 6 /* informational */ +#define LOGLEVEL_DEBUG 7 /* debug-level messages */ + +#endif
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index be01e1e..56b3dc5 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h
@@ -22,6 +22,51 @@ #include <spi-mem.h> #include <linux/mtd/nand.h> #endif +#define NAND_BLOCK_GOOD 0 +#define NAND_BLOCK_BAD 1 +#define NAND_FACTORY_BAD 2 + +#define SPINAND_MESON_RSV 1 +#ifdef CONFIG_SPI_NAND_AML_ADVANCED +/* Use dev parameters to send parameters in advanced mode */ +#define SPINAND_MESON_INFO_PAGE 0 +#else +#define SPINAND_MESON_INFO_PAGE 1 +#endif + + +#if SPINAND_MESON_INFO_PAGE +struct info_page { + char magic[8]; /* magic header of info page */ + /* info page version, +1 when you update this struct */ + u8 version; /* 1 for now */ + u8 mode; /* 1 discrete, 0 compact */ + u8 bl2_num; /* bl2 copy number */ + u8 fip_num; /* fip copy number */ + union { + struct { +#define SPINAND_MAGIC "AMLIFPG" +#define SPINAND_INFO_VER 1 + u8 rd_max; /* spi nand max read io */ + u8 oob_offset; /* user bytes offset */ + uint8_t planes_per_lun; + u8 rsv; + u32 fip_start; /* start pages */ + u32 fip_pages; /* pages per fip */ + u32 page_size; /* spi nand page size (bytes) */ + u32 page_per_blk; /* page number per block */ + u32 oob_size; /* valid oob size (bytes) */ + u32 bbt_start; /* bbt start pages */ + u32 bbt_valid; /* bbt valid offset pages */ + u32 bbt_size; /* bbt occupied bytes */ + } s;/* spi nand */ + struct { + u32 reserved; + } e;/* emmc */ + } dev; + +}; +#endif /** * Standard SPI NAND flash operations @@ -39,11 +84,20 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) +#if 0 #define SPINAND_READID_OP(ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_DUMMY(ndummy, 1), \ SPI_MEM_OP_DATA_IN(len, buf, 1)) +#else +/* Adjust the timing of read ID */ +#define SPINAND_READID_OP(ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \ + SPI_MEM_OP_ADDR(1, 0x00, 1), \ + SPI_MEM_OP_DUMMY(ndummy, 1), \ + SPI_MEM_OP_DATA_IN(len, buf, 1)) +#endif #define SPINAND_SET_FEATURE_OP(reg, valptr) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \ @@ -202,9 +256,12 @@ /* SPI NAND manufacturers */ extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; +extern const struct spinand_manufacturer toshiba_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; extern const struct spinand_manufacturer micron_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; +extern const struct spinand_manufacturer zetta_spinand_manufacturer; +extern const struct spinand_manufacturer xtx_spinand_manufacturer; /** * struct spinand_op_variants - SPI NAND operation variants @@ -362,7 +419,16 @@ u8 *oobbuf; u8 *scratchbuf; const struct spinand_manufacturer *manufacturer; + /* Record the current spinand */ + const char *model; void *priv; +#if SPINAND_MESON_RSV + /* add for aml rsv */ + struct meson_rsv_handler_t *rsv; + /* aml bbt */ + u8 *bbt; + u8 bbt_scan; +#endif }; /**
diff --git a/include/linux/ssr/ps13216.h b/include/linux/ssr/ps13216.h new file mode 100644 index 0000000..b6e4bb9 --- /dev/null +++ b/include/linux/ssr/ps13216.h
@@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** + * Copyright 2021 Google LLC. + */ + +#ifndef __SSR_PS13216_H_ +#define __SSR_PS13216_H_ + +#include <dm/device.h> + +enum gpio_state { + LOW, + HIGH, + NOT_AVAILABLE, +}; + +int get_ssr_hvsense_voltage(struct udevice *dev, int *mean_squared_voltage, + int *peak_voltage); +int ssr_probe(struct udevice **dev); +int check_power(struct udevice *dev, enum gpio_state pgood_state); + +#endif
diff --git a/include/linux/ssr/ps13216_regs.h b/include/linux/ssr/ps13216_regs.h new file mode 100644 index 0000000..e69a4fb --- /dev/null +++ b/include/linux/ssr/ps13216_regs.h
@@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/** + * Register map for PS13216 (Schumacher) + * + * Refer to nest-internal/platform/nlplatform/src/devices/i2c/ps13216_regs.h for a complete list of + * registers/values. + * + * Copyright 2021 Google LLC. + */ + +#ifndef __SSR_PS13216_SSR_REGS_H_ +#define __SSR_PS13216_SSR_REGS_H_ + +#include <common.h> + +// Register addresses +#define PS13216_REG_EVENT0 0x02 +#define PS13216_REG_EVENT1 0x03 +#define PS13216_REG_GLOBAL_EVENTS 0x04 +#define PS13216_REG_SETUP 0x06 +#define PS13216_REG_CTRL 0x0D +#define PS13216_REG_BB1XB 0x0E +#define PS13216_REG_BB0XB 0x0F +#define PS13216_REG_FORCE_ACTIVE 0x16 +#define PS13216_REG_EVENT0_MASK 0x1d +#define PS13216_REG_EVENT1_MASK 0x1e +#define PS13216_REG_ADC_CTRL 0x20 +#define PS13216_REG_ADC_FIFO 0x2B +#define PS13216_REG_ADC_FIFO_FILL_CNT_LSB 0x34 +#define PS13216_REG_ADC_FIFO_FILL_CNT_MSB 0x35 +#define PS13216_REG_TEST_SIGNAL_SPY 0xD8 +#define PS13216_REG_SW_TEST_MODE 0xFF + +#define PS13216_MAX_REGISTER 0xFF + +// Event masking register masks +#define PS13216_M_EVENT0_MASK_OVC0 BIT(0) +#define PS13216_M_EVENT0_MASK_OVC1 BIT(1) +#define PS13216_M_EVENT0_MASK_CP_PF0 BIT(2) +#define PS13216_M_EVENT0_MASK_CP_PF1 BIT(3) +#define PS13216_M_EVENT0_MASK_OT0 BIT(4) +#define PS13216_M_EVENT0_MASK_OT1 BIT(5) +#define PS13216_M_EVENT0_MASK_SW0_OFF BIT(6) +#define PS13216_M_EVENT0_MASK_SW1_OFF BIT(7) +#define PS13216_M_EVENT0_MASK_ALL \ + (PS13216_M_EVENT0_MASK_OVC0 \ + | PS13216_M_EVENT0_MASK_OVC1 \ + | PS13216_M_EVENT0_MASK_CP_PF0 \ + | PS13216_M_EVENT0_MASK_CP_PF1 \ + | PS13216_M_EVENT0_MASK_OT0 \ + | PS13216_M_EVENT0_MASK_OT1 \ + | PS13216_M_EVENT0_MASK_SW0_OFF \ + | PS13216_M_EVENT0_MASK_SW1_OFF) + +#define PS13216_V_EVENT0_MASK_OVCx(ch) (PS13216_M_EVENT0_MASK_OVC0 << (ch)) +#define PS13216_V_EVENT0_MASK_CP_PFx(ch) (PS13216_M_EVENT0_MASK_CP_PF0 << (ch)) +#define PS13216_V_EVENT0_MASK_OTx(ch) (PS13216_M_EVENT0_MASK_OT0 << (ch)) +#define PS13216_V_EVENT0_MASK_SWx_OFF(ch) (PS13216_M_EVENT0_MASK_SW0_OFF << (ch)) + +#define PS13216_M_EVENT1_MASK_RESET BIT(0) +#define PS13216_M_EVENT1_MASK_GPI BIT(1) +#define PS13216_M_EVENT1_MASK_SUPF BIT(2) +#define PS13216_M_EVENT1_MASK_EOC BIT(3) +#define PS13216_M_EVENT1_MASK_ADDR BIT(5) +#define PS13216_M_EVENT1_MASK_ALL \ + (PS13216_M_EVENT1_MASK_RESET \ + | PS13216_M_EVENT1_MASK_GPI \ + | PS13216_M_EVENT1_MASK_SUPF \ + | PS13216_M_EVENT1_MASK_EOC \ + | PS13216_M_EVENT1_MASK_ADDR) + +// Event and Status Masks +#define PS13216_M_EVENT0_OVC0 BIT(0) +#define PS13216_M_EVENT0_OVC1 BIT(1) +#define PS13216_M_EVENT0_CP_PF0 BIT(2) +#define PS13216_M_EVENT0_CP_PF1 BIT(3) +#define PS13216_M_EVENT0_OT0 BIT(4) +#define PS13216_M_EVENT0_OT1 BIT(5) +#define PS13216_M_EVENT0_SW0_OFF BIT(6) +#define PS13216_M_EVENT0_SW1_OFF BIT(7) +#define PS13216_M_EVENT0_ALL \ + (PS13216_M_EVENT0_OVC0 \ + | PS13216_M_EVENT0_OVC1 \ + | PS13216_M_EVENT0_CP_PF0 \ + | PS13216_M_EVENT0_CP_PF1 \ + | PS13216_M_EVENT0_OT0 \ + | PS13216_M_EVENT0_OT1 \ + | PS13216_M_EVENT0_SW0_OFF \ + | PS13216_M_EVENT0_SW1_OFF) + +#define PS13216_V_EVENT0_OVCx(ch) (PS13216_M_EVENT0_OVC0 << (ch)) +#define PS13216_V_EVENT0_CP_PFx(ch) (PS13216_M_EVENT0_CP_PF0 << (ch)) +#define PS13216_V_EVENT0_OTx(ch) (PS13216_M_EVENT0_OT0 << (ch)) +#define PS13216_V_EVENT0_SWx_OFF(ch) (PS13216_M_EVENT0_SW0_OFF << (ch)) + +#define PS13216_M_EVENT1_RESET BIT(0) +#define PS13216_M_EVENT1_GPI BIT(1) +#define PS13216_M_EVENT1_SUPF BIT(2) +#define PS13216_M_EVENT1_EOC BIT(3) +#define PS13216_M_EVENT1_ADDR BIT(5) +#define PS13216_M_EVENT1_ALL \ + (PS13216_M_EVENT1_RESET \ + | PS13216_M_EVENT1_GPI \ + | PS13216_M_EVENT1_SUPF \ + | PS13216_M_EVENT1_EOC \ + | PS13216_M_EVENT1_ADDR) + +#define PS13216_M_GLOBAL_EVENTS_BLACKOUT BIT(0) +#define PS13216_M_GLOBAL_EVENTS_BROWNOUT BIT(1) +#define PS13216_M_GLOBAL_EVENTS_OT_CORE BIT(2) +#define PS13216_M_GLOBAL_EVENTS_DEAD_MAN BIT(4) +#define PS13216_M_GLOBAL_EVENTS_LV2HV0 BIT(5) +#define PS13216_M_GLOBAL_EVENTS_LV2HV1 BIT(6) +#define PS13216_M_GLOBAL_EVENTS_ALL \ + (PS13216_M_GLOBAL_EVENTS_BLACKOUT \ + | PS13216_M_GLOBAL_EVENTS_BROWNOUT \ + | PS13216_M_GLOBAL_EVENTS_OT_CORE \ + | PS13216_M_GLOBAL_EVENTS_DEAD_MAN \ + | PS13216_M_GLOBAL_EVENTS_LV2HV0 \ + | PS13216_M_GLOBAL_EVENTS_LV2HV1) + +// Setup Register Masks and Macros +#define PS13216_M_SETUP_RESTART_CONFIG (BIT(0) | BIT(1)) +#define PS13216_G_SETUP_RESTART_CONFIG(r) (((r) >> 0) & 0x3u) +#define PS13216_V_SETUP_RESTART_CONFIG(x) ((x) << 0) +#define PS13216_SETUP_RESTART_DISABLED (0) +#define PS13216_SETUP_RESTART_4_TIMES (1) +#define PS13216_SETUP_RESTART_8_TIMES (2) +#define PS13216_SETUP_RESTART_15_TIMES (3) + +#define PS13216_M_SETUP_FAST_MODE_CONFIG (BIT(2) | BIT(3)) +#define PS13216_G_SETUP_FAST_MODE_CONFIG(r) (((r) >> 2) & 0x3u) +#define PS13216_V_SETUP_FAST_MODE_CONFIG(x) ((x) << 2) +#define PS13216_SETUP_FAST_MODE_DISABLED (0) +#define PS13216_SETUP_FAST_MODE_CH0 (1) +#define PS13216_SETUP_FAST_MODE_CH1 (2) +#define PS13216_SETUP_FAST_MODE_CH0_CH1 (3) + +#define PS13216_M_SETUP_PULSE_MODE_CONFIG (BIT(4) | BIT(5)) +#define PS13216_G_SETUP_PULSE_MODE_CONFIG(r) (((r) >> 4) & 0x3u) +#define PS13216_V_SETUP_PULSE_MODE_CONFIG(x) ((x) << 4) +#define PS13216_SETUP_PULSE_MODE_DISABLED (0) +#define PS13216_SETUP_PULSE_MODE_CH0 (1) +#define PS13216_SETUP_PULSE_MODE_CH1 (2) + +#define PS13216_M_SETUP_GP_CONFIG (BIT(6) | BIT(7)) +#define PS13216_G_SETUP_GP_CONFIG(r) (((r) >> 6) & 0x3u) +#define PS13216_V_SETUP_GP_CONFIG(x) ((x) << 6) +#define PS13216_SETUP_GP_DISABLED (0) +#define PS13216_SETUP_GP_CH0 (1) +#define PS13216_SETUP_GP_CH1 (2) + +// Bit-Banding Control Register Masks and Macros +#define PS13216_M_BB0XB_C0 BIT(0) + +#define PS13216_M_BB1XB_C0 BIT(0) + +// ADC Register Masks +#define PS13216_M_ADC_CTRL_VI0 BIT(0) +#define PS13216_M_ADC_CTRL_VI1 BIT(1) +#define PS13216_M_ADC_CTRL_T0 BIT(2) +#define PS13216_M_ADC_CTRL_T1 BIT(3) +#define PS13216_M_ADC_CTRL_HV_SENSE BIT(4) +#define PS13216_M_ADC_CTRL_ALL_CHANNELS \ + (PS13216_M_ADC_CTRL_VI0 \ + | PS13216_M_ADC_CTRL_VI1 \ + | PS13216_M_ADC_CTRL_T0 \ + | PS13216_M_ADC_CTRL_T1 \ + | PS13216_M_ADC_CTRL_HV_SENSE) + +#define PS13216_M_ADC_CTRL_COD BIT(5) +#define PS13216_M_ADC_CTRL_MODE (BIT(6) | BIT(7)) +#define PS13216_G_ADC_CTRL_MODE(r) (((r) >> 6) & 0x3) +#define PS13216_V_ADC_CTRL_MODE(x) ((x) << 6) +#define PS13216_ADC_MODE_DISABLED (0) +#define PS13216_ADC_MODE_MAM (1) +#define PS13216_ADC_MODE_SAM (2) +#define PS13216_ADC_MODE_CAM (3) + +// Force active register masks +#define PS13216_V_FORCE_ACTIVE(x) ((x) << 0) + +// Event and status masks +#define PS13216_M_EVENT1_EOC BIT(3) + +// Test mode commands +#define PS13216_ENTER_TEST_MODE_1ST_BYTE 0x4D +#define PS13216_ENTER_TEST_MODE_2ND_BYTE 0x53 + +#define PS13216_LEAVE_TEST_MODE_1ST_BYTE (~0x53) +#define PS13216_LEAVE_TEST_MODE_2ND_BYTE (~0x4D) + +#define PS13216_SIGNALSPY_ZERO_CROSS_CH0 0x8F +#define PS13216_SIGNALSPY_ZERO_CROSS_CH1 0x94 +#define PS13216_SIGNALSPY_DISABLE 0x00 + +#endif // __SSR_PS13216_SSR_REGS_H_
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h index 56ee018..0fdb6ee 100644 --- a/include/linux/usb/ch9.h +++ b/include/linux/usb/ch9.h
@@ -1059,9 +1059,5 @@ * If you're using usb_gadget_get_string(), use this to wrap a string * together with its ID. */ -struct usb_string { - u8 id; - const char *s; -}; #endif /* __LINUX_USB_CH9_H */
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 497798a..b6f802d 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h
@@ -935,7 +935,8 @@ #include <usb.h> static inline int usb_gadget_initialize(int index) { - return board_usb_init(index, USB_INIT_DEVICE); + //return board_usb_init(index, USB_INIT_DEVICE); + return 0; } static inline int usb_gadget_release(int index)
diff --git a/include/mmc.h b/include/mmc.h index 695b5d3..52f4c72 100644 --- a/include/mmc.h +++ b/include/mmc.h
@@ -112,7 +112,7 @@ #define MMC_CMD_SPI_READ_OCR 58 #define MMC_CMD_SPI_CRC_ON_OFF 59 #define MMC_CMD_RES_MAN 62 -#define MMC_SD_HS_TUNING 70 +#define MMC_SD_HS_TUNING 70 #define MMC_CMD62_ARG1 0xefac62ec #define MMC_CMD62_ARG2 0xcbaea7
diff --git a/include/nand.h b/include/nand.h index 763e6ea..735b819 100644 --- a/include/nand.h +++ b/include/nand.h
@@ -22,7 +22,7 @@ #else #if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\ || defined(CONFIG_NAND_FSL_IFC) || defined(CONFIG_SPI_NAND)\ - || defined(CONFIG_MESON_NFC) + || defined(CONFIG_MESON_NFC) || defined(CONFIG_MTD_SPI_NAND) #define CONFIG_SYS_NAND_SELF_INIT #endif #endif
diff --git a/include/part.h b/include/part.h index abedf20..a3f2550 100644 --- a/include/part.h +++ b/include/part.h
@@ -69,6 +69,8 @@ char type_guid[UUID_STR_LEN + 1]; /* type GUID as string, if exists */ #endif #ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY + efi_guid_t partition_type_guid; + efi_guid_t unique_partition_guid; gpt_entry_attributes attributes; #endif #ifdef CONFIG_DOS_PARTITION
diff --git a/include/partition_table.h b/include/partition_table.h index 94e3787..536ed4b 100644 --- a/include/partition_table.h +++ b/include/partition_table.h
@@ -59,6 +59,8 @@ extern int has_boot_slot; extern int has_system_slot; +extern bool dynamic_partition; +extern bool vendor_boot_partition; extern int get_partition_from_dts(unsigned char * buffer);
diff --git a/include/ramdump.h b/include/ramdump.h new file mode 100644 index 0000000..d851a80 --- /dev/null +++ b/include/ramdump.h
@@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __RAMDUMP_H__ +#define __RAMDUMP_H__ + +#define RAMDUMP_STICKY_DATA_MASK (0xFFFF) + +extern void check_ramdump(void); +extern void ramdump_init(void); + +extern unsigned long ramdump_base; +extern unsigned long ramdump_size; + +int ramdump_save_compress_data(void); + +#endif /* __RAMDUMP_H__ */
diff --git a/include/time_logging.h b/include/time_logging.h index b3e9dc6..b54fc1d 100644 --- a/include/time_logging.h +++ b/include/time_logging.h
@@ -15,12 +15,12 @@ static inline void logging_set_num(uint32_t num) { - *(uint32_t *)LOG_UBOOT_NUM = num; + //*(uint32_t *)LOG_UBOOT_NUM = num; } static inline void logging_set_entry(uint64_t entry) { - *(uint32_t *)entry = get_time(); + //*(uint32_t *)entry = get_time(); } #endif /* __TIME_LOGGING_H_ */
diff --git a/include/usb.h b/include/usb.h index 0881477..370013d 100644 --- a/include/usb.h +++ b/include/usb.h
@@ -17,8 +17,10 @@ #include <asm/cache.h> #include <part.h> -#define HEHE_DEBUG(x...) printf(x) -//#define HEHE_DEBUG(x...) +struct usb_string { + u8 id; + const char *s; +}; /* get from ch9.h fix compile error. start */ struct usb_ss_ep_comp_descriptor { @@ -1113,5 +1115,6 @@ unsigned short *portstat); int usb_tuning_port(struct usb_device *udev, int port); +int usb_aml_detect_operation(int argc, char * const argv[]); #endif /*_USB_H_ */
diff --git a/lib/Makefile b/lib/Makefile index 14fd604..a94e1ec 100644 --- a/lib/Makefile +++ b/lib/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_USB_TTY) += circbuf.o #obj-y += crc7.o obj-y += crc8.o -#obj-y += crc16.o +obj-y += crc16.o obj-$(CONFIG_ERRNO_STR) += errno_str.o obj-$(CONFIG_FIT) += fdtdec_common.o obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o @@ -39,7 +39,7 @@ obj-$(CONFIG_LMB) += lmb.o obj-y += ldiv.o obj-$(CONFIG_MD5) += md5.o -#obj-y += net_utils.o +obj-y += net_utils.o obj-$(CONFIG_PHYSMEM) += physmem.o obj-y += qsort.o #obj-y += rc4.o @@ -97,7 +97,7 @@ obj-y += string.o obj-y += tables_csum.o obj-y += time.o -#obj-y += hexdump.o +obj-y += hexdump.o obj-$(CONFIG_TRACE) += trace.o obj-$(CONFIG_LIB_UUID) += uuid.o obj-$(CONFIG_LIB_RAND) += rand.o
diff --git a/lib/libavb/avb_cmdline.c b/lib/libavb/avb_cmdline.c index bc43a0f..14c278b 100644 --- a/lib/libavb/avb_cmdline.c +++ b/lib/libavb/avb_cmdline.c
@@ -259,13 +259,16 @@ slot_data->vbmeta_images[n].vbmeta_size); total_size += slot_data->vbmeta_images[n].vbmeta_size; } + avb_memcpy(slot_data->vbmeta_digest, + avb_sha256_final(&ctx), + AVB_SHA256_DIGEST_SIZE); if (!cmdline_append_option( slot_data, "androidboot.vbmeta.hash_alg", "sha256") || !cmdline_append_uint64_base10( slot_data, "androidboot.vbmeta.size", total_size) || !cmdline_append_hex(slot_data, "androidboot.vbmeta.digest", - avb_sha256_final(&ctx), + slot_data->vbmeta_digest, AVB_SHA256_DIGEST_SIZE)) { ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; goto out; @@ -353,7 +356,15 @@ ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; goto out; } - +#if 0 + if (!cmdline_append_hex(slot_data, + "androidboot.vbmeta.bootkey_hash", + slot_data->boot_key_hash, + AVB_SHA256_DIGEST_SIZE)) { + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } +#endif ret = AVB_SLOT_VERIFY_RESULT_OK; out:
diff --git a/lib/libavb/avb_slot_verify.c b/lib/libavb/avb_slot_verify.c index 98ec619..6651e71 100644 --- a/lib/libavb/avb_slot_verify.c +++ b/lib/libavb/avb_slot_verify.c
@@ -15,6 +15,7 @@ #include <libavb/avb_util.h> #include <libavb/avb_vbmeta_image.h> #include <libavb/avb_version.h> +#include <u-boot/sha256.h> /* Maximum number of partitions that can be loaded with avb_slot_verify(). */ #define MAX_NUMBER_OF_LOADED_PARTITIONS 32 @@ -173,6 +174,7 @@ uint8_t* image_buf = NULL; bool image_preloaded = false; uint8_t* digest; + uint8_t sha_digest[SHA256_SUM_LEN]; size_t digest_len; const char* found; uint64_t image_size; @@ -276,11 +278,20 @@ } if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha256") == 0) { +#if 0 AvbSHA256Ctx sha256_ctx; avb_sha256_init(&sha256_ctx); avb_sha256_update(&sha256_ctx, desc_salt, hash_desc.salt_len); avb_sha256_update(&sha256_ctx, image_buf, hash_desc.image_size); digest = avb_sha256_final(&sha256_ctx); +#else + sha256_context ctx; + sha256_starts(&ctx); + sha256_update(&ctx, desc_salt, hash_desc.salt_len); + sha256_update(&ctx, image_buf, hash_desc.image_size); + sha256_finish(&ctx, sha_digest); + digest = sha_digest; +#endif digest_len = AVB_SHA256_DIGEST_SIZE; } else if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha512") == 0) { AvbSHA512Ctx sha512_ctx; @@ -470,6 +481,7 @@ bool is_main_vbmeta; bool is_vbmeta_partition; AvbVBMetaData* vbmeta_image_data = NULL; + bool out_is_unlocked = 0; ret = AVB_SLOT_VERIFY_RESULT_OK; @@ -606,6 +618,15 @@ switch (vbmeta_ret) { case AVB_VBMETA_VERIFY_RESULT_OK: avb_assert(pk_data != NULL && pk_len > 0); + io_ret = ops->read_is_device_unlocked(ops, &out_is_unlocked); + if (io_ret == AVB_IO_RESULT_OK && !out_is_unlocked) { + AvbSHA256Ctx boot_key_sha256_ctx; + avb_sha256_init(&boot_key_sha256_ctx); + avb_sha256_update(&boot_key_sha256_ctx, pk_data, pk_len); + avb_memcpy(slot_data->boot_key_hash, + avb_sha256_final(&boot_key_sha256_ctx), + AVB_SHA256_DIGEST_SIZE); + } break; case AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED: @@ -1250,6 +1271,9 @@ } void avb_slot_verify_data_free(AvbSlotVerifyData* data) { + if (data == NULL) { + return; + } if (data->ab_suffix != NULL) { avb_free(data->ab_suffix); }
diff --git a/lib/libavb/avb_slot_verify.h b/lib/libavb/avb_slot_verify.h index 73fd70d..f4a76fe 100644 --- a/lib/libavb/avb_slot_verify.h +++ b/lib/libavb/avb_slot_verify.h
@@ -239,6 +239,8 @@ size_t num_loaded_partitions; char* cmdline; uint64_t rollback_indexes[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]; + uint8_t boot_key_hash[AVB_SHA256_DIGEST_SIZE]; + uint8_t vbmeta_digest[AVB_SHA256_DIGEST_SIZE]; } AvbSlotVerifyData; /* Calculates a digest of all vbmeta images in |data| using
diff --git a/lib/libavb/testkey.c b/lib/libavb/testkey.c index 3440146..b968f1a 100644 --- a/lib/libavb/testkey.c +++ b/lib/libavb/testkey.c
@@ -1,4 +1,4 @@ -const char testkey2048[520] = { +const char avb2_kpub_default[520] = { 0x00, 0x00, 0x08, 0x00, 0xc9, 0xd8, 0x7d, 0x7b, 0xc6, 0x55, 0x51, 0xdd, 0x32, 0x24, 0xa2, 0xe0, 0x0e, 0xbc, 0x7e, 0xfd, 0xbd, 0xa2, 0x53, 0x80, 0x58, 0x69, 0x7e, 0xf5, 0x4a, 0x40, 0x87, 0x95, 0x90, @@ -48,5 +48,4 @@ 0xa9, 0x75, 0x7e, 0xe1, 0x4e, 0xe2, 0x95, 0x5b, 0x4f, 0xe6, 0xdc, 0x03, 0xb9, 0x81 }; - -const int testkey2048_length = 520; +const int avb2_kpub_default_len = sizeof(avb2_kpub_default) / sizeof(char);
diff --git a/lib/panic.c b/lib/panic.c index bae8a35..60259fa 100644 --- a/lib/panic.c +++ b/lib/panic.c
@@ -53,3 +53,18 @@ panic("%s:%u: %s: Assertion `%s' failed.", file, line, function, assertion); } + +#define STACK_CHECK_GUARD 0xdeadbeefdeadbeefUL +uintptr_t __stack_chk_guard = STACK_CHECK_GUARD; +void __attribute__ ((noreturn)) __stack_chk_fail(void) +{ + unsigned long pc_reg; + + __asm__ volatile("mov %0, x30\n" + : "=r" (pc_reg) + : + : "memory"); + /* This will not return */ + panic("Stack-protector: stack smashing detected at caller 0x%lx !\n", + (pc_reg - 0x4)); +}
diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c index fc0c6b0..dfb3236 100644 --- a/scripts/dtc/libfdt/fdt_ro.c +++ b/scripts/dtc/libfdt/fdt_ro.c
@@ -139,6 +139,7 @@ do { tag = fdt_next_tag(fdt, offset, &nextoffset); + switch (tag) { case FDT_END: if (nextoffset >= 0)