/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ | |
/* | |
* arch/arm/include/asm/arch-t5/gpio.h | |
* | |
* Copyright (C) 2020 Amlogic, Inc. All rights reserved. | |
* | |
*/ | |
#ifndef _MESON_T5_GPIO_H | |
#define _MESON_T5_GPIO_H | |
#define EE_OFFSET 14 | |
#define GPIOAO(x) (x) | |
#define GPIOEE(x) (EE_OFFSET + x) | |
/* First GPIO chip */ | |
#define GPIOD_0 0 | |
#define GPIOD_1 1 | |
#define GPIOD_2 2 | |
#define GPIOD_3 3 | |
#define GPIOD_4 4 | |
#define GPIOD_5 5 | |
#define GPIOD_6 6 | |
#define GPIOD_7 7 | |
#define GPIOD_8 8 | |
#define GPIOD_9 9 | |
#define GPIOD_10 10 | |
#define GPIOE_0 11 | |
#define GPIOE_1 12 | |
#define GPIOE_2 13 | |
/* Second GPIO chip */ | |
#define GPIOH_0 0 | |
#define GPIOH_1 1 | |
#define GPIOH_2 2 | |
#define GPIOH_3 3 | |
#define GPIOH_4 4 | |
#define GPIOH_5 5 | |
#define GPIOH_6 6 | |
#define GPIOH_7 7 | |
#define GPIOH_8 8 | |
#define GPIOH_9 9 | |
#define GPIOH_10 10 | |
#define GPIOH_11 11 | |
#define GPIOH_12 12 | |
#define GPIOH_13 13 | |
#define GPIOH_14 14 | |
#define GPIOH_15 15 | |
#define GPIOH_16 16 | |
#define GPIOH_17 17 | |
#define GPIOH_18 18 | |
#define GPIOH_19 19 | |
#define GPIOH_20 20 | |
#define GPIOH_21 21 | |
#define GPIOB_0 22 | |
#define GPIOB_1 23 | |
#define GPIOB_2 24 | |
#define GPIOB_3 25 | |
#define GPIOB_4 26 | |
#define GPIOB_5 27 | |
#define GPIOB_6 28 | |
#define GPIOB_7 29 | |
#define GPIOB_8 30 | |
#define GPIOB_9 31 | |
#define GPIOB_10 32 | |
#define GPIOB_11 33 | |
#define GPIOB_12 34 | |
#define GPIOB_13 35 | |
#define GPIOZ_0 36 | |
#define GPIOZ_1 37 | |
#define GPIOZ_2 38 | |
#define GPIOZ_3 39 | |
#define GPIOZ_4 40 | |
#define GPIOZ_5 41 | |
#define GPIOZ_6 42 | |
#define GPIOW_0 43 | |
#define GPIOW_1 44 | |
#define GPIOW_2 45 | |
#define GPIOW_3 46 | |
#define GPIOW_4 47 | |
#define GPIOW_5 48 | |
#define GPIOW_6 49 | |
#define GPIOW_7 50 | |
#define GPIOW_8 51 | |
#define GPIOW_9 52 | |
#define GPIOW_10 53 | |
#define GPIOW_11 54 | |
#define GPIOW_12 55 | |
#endif /* _MESON_T5_GPIO_H */ | |