blob: 38241911eb364793c9502700b17bf58488f69036 [file] [log] [blame]
#include <common.h>
//#include <u-boot/sha256.h>
//#include <asm/arch/register.h>
//#include <asm/cpu_id.h>
//#define USE_FOR_UBOOT_2018
#define USE_FOR_UBOOT_2015
#define GET_CHIP_ID
#ifdef USE_FOR_UBOOT_2018
#define DISABLE_ENV
#define USE_FOR_UBOOT_2018
#include <amlogic/cpu_id.h>
#endif
#ifdef USE_FOR_UBOOT_2015
//#define DISABLE_ENV
//#define USE_FOR_UBOOT_2018
#include <asm/cpu_id.h>
#endif
struct ddr_base_address_table{
char soc_family_name[16];
unsigned int chip_id;
unsigned int preg_sticky_reg0;
unsigned int ddr_phy_base_address;
unsigned int ddr_pctl_timing_base_address;
unsigned int ddr_pctl_timing_end_address;
unsigned int ddr_dmc_sticky0;
unsigned int sys_watchdog_base_address;
unsigned int sys_watchdog_enable_value;
unsigned int ddr_pll_base_address;
unsigned int ee_timer_base_address;
unsigned int ee_pwm_base_address;
unsigned int ddr_dmc_apd_address;
unsigned int ddr_dmc_asr_address;
};
typedef struct ddr_base_address_table ddr_base_address_table_t;
#define MESON_CPU_MAJOR_ID_GXBB 0x1F
#define MESON_CPU_MAJOR_ID_GXTVBB 0x20
#define MESON_CPU_MAJOR_ID_GXLBB 0x21
#define MESON_CPU_MAJOR_ID_GXM 0x22
#define MESON_CPU_MAJOR_ID_TXL 0x23
#define MESON_CPU_MAJOR_ID_TXLX 0x24
#define MESON_CPU_MAJOR_ID_AXG 0x25
#define MESON_CPU_MAJOR_ID_GXLX 0x26
#define MESON_CPU_MAJOR_ID_TXHD 0x27
#define MESON_CPU_MAJOR_ID_G12A 0x28
#define MESON_CPU_MAJOR_ID_G12B 0x29
#define MESON_CPU_MAJOR_ID_SM1 0x2B
#define MESON_CPU_MAJOR_ID_A1 0x2C
#define MESON_CPU_MAJOR_ID_TL1 0x2E
#define MESON_CPU_MAJOR_ID_TM2 0x2F
#define MESON_CPU_MAJOR_ID_C1 0x30
#define MESON_CPU_VERSION_LVL_MAJOR 0
#define MESON_CPU_VERSION_LVL_MINOR 1
#define MESON_CPU_VERSION_LVL_PACK 2
#define MESON_CPU_VERSION_LVL_MISC 3
#define MESON_CPU_VERSION_LVL_MAX MESON_CPU_VERSION_LVL_MISC
#define CHIP_ID_MASK 0xff
//#define CHIP_ID_G12A 1
//#define CHIP_ID_A1 2
char global_chip_id[12]={0};
#define MESON_CPU_CHIP_ID_SIZE 12 //4 //12byte
int ddr_get_chip_id(void)
{
int soc_family_id=0;
soc_family_id =get_cpu_id().family_id ;
printf("\nsoc_family_id==0x%08x",soc_family_id);
unsigned char chipid[16];
//unsigned char chipid_inv[12];
#ifdef GET_CHIP_ID
get_chip_id(chipid, 16);
#endif
int count=0;
for (count=0;count<16;count++ )
{
if (count>3)
{
global_chip_id[16-1-count]=chipid[count];
}
//printf("\nchipid[%d]==%08x",count,chipid[count]);
}
//for(int count=0;count<12;count++ )
//{
//printf("\nchipid_inv[%d]==%08x",count,chipid_inv[count]);
//}
return soc_family_id;
//return CHIP_ID_A1;
//return CHIP_ID_G12A;
//return CHIP_ID_MASK;
}
char CMD_VER[] = "Ver_12";
ddr_base_address_table_t __ddr_base_address_table[] = {
//g12a
{
.soc_family_name="G12A",
.chip_id=MESON_CPU_MAJOR_ID_G12A,
.preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0
.ddr_phy_base_address=0xfe000000,
.ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400),
.ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400),
.ddr_dmc_sticky0=0xff638800,
.sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000),
.ddr_pll_base_address=((0x0000 << 2) + 0xff638c00),
.ee_timer_base_address=((0x3c62 << 2) + 0xffd00000),
.ee_pwm_base_address=(0xff807000 + (0x001 << 2)),
.ddr_dmc_apd_address=((0x008c << 2) + 0xff638400),
.ddr_dmc_asr_address=((0x008d << 2) + 0xff638400),
},
//g12b
{
.soc_family_name="G12B",
.chip_id=MESON_CPU_MAJOR_ID_G12B,
.preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0
.ddr_phy_base_address=0xfe000000,
.ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400),
.ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400),
.ddr_dmc_sticky0=0xff638800,
.sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000),
.ddr_pll_base_address=((0x0000 << 2) + 0xff638c00),
.ee_timer_base_address=((0x3c62 << 2) + 0xffd00000),
.ee_pwm_base_address=(0xff807000 + (0x001 << 2)),
.ddr_dmc_apd_address=((0x008c << 2) + 0xff638400),
.ddr_dmc_asr_address=((0x008d << 2) + 0xff638400),
},
//tl1
{
.soc_family_name="TL1",
.chip_id=MESON_CPU_MAJOR_ID_TL1,
.preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0
.ddr_phy_base_address=0xfe000000,
.ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400),
.ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400),
.ddr_dmc_sticky0=0xff638800,
.sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000),
.ddr_pll_base_address=((0x0000 << 2) + 0xff638c00),
.ee_timer_base_address=((0x3c62 << 2) + 0xffd00000),
.ee_pwm_base_address=(0xff807000 + (0x001 << 2)),
.ddr_dmc_apd_address=((0x008c << 2) + 0xff638400),
.ddr_dmc_asr_address=((0x008d << 2) + 0xff638400),
},
//sm1
{
.soc_family_name="SM1",
.chip_id=MESON_CPU_MAJOR_ID_SM1,
.preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0
.ddr_phy_base_address=0xfe000000,
.ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400),
.ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400),
.ddr_dmc_sticky0=0xff638800,
.sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000),
.ddr_pll_base_address=((0x0000 << 2) + 0xff638c00),
.ee_timer_base_address=((0x3c62 << 2) + 0xffd00000),
.ee_pwm_base_address=(0xff807000 + (0x001 << 2)),
.ddr_dmc_apd_address=((0x008c << 2) + 0xff638400),
.ddr_dmc_asr_address=((0x008d << 2) + 0xff638400),
},
//tm2
{
.soc_family_name="TM2",
.chip_id=MESON_CPU_MAJOR_ID_TM2,
.preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0
.ddr_phy_base_address=0xfe000000,
.ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400),
.ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400),
.ddr_dmc_sticky0=0xff638800,
.sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000),
.ddr_pll_base_address=((0x0000 << 2) + 0xff638c00),
.ee_timer_base_address=((0x3c62 << 2) + 0xffd00000),
.ee_pwm_base_address=(0xff807000 + (0x001 << 2)),
.ddr_dmc_apd_address=((0x008c << 2) + 0xff638400),
.ddr_dmc_asr_address=((0x008d << 2) + 0xff638400),
},
//a1
{
.soc_family_name="A1",
.chip_id=MESON_CPU_MAJOR_ID_A1,
.preg_sticky_reg0=0xfffff400,//use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0
.ddr_phy_base_address=0xfc000000,
.ddr_pctl_timing_base_address=((0x0000 << 2) + 0xfd020400),
.ddr_pctl_timing_end_address=((0x00bb << 2) + 0xfd020400),
.ddr_dmc_sticky0=0xfd020800,
.ddr_dmc_apd_address=((0x008c << 2) + 0xfd020400),
.ddr_dmc_asr_address=((0x008d << 2) + 0xfd020400),
.sys_watchdog_base_address=0,//((0x0040 << 2) + 0xfe000000),
.sys_watchdog_enable_value=0x03c401ff,
},
//c1
{
.soc_family_name="C1",
.chip_id=MESON_CPU_MAJOR_ID_C1,
.preg_sticky_reg0=0xfffff400,//use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0
.ddr_phy_base_address=0xfd000000,
.ddr_pctl_timing_base_address=((0x0000 << 2) + 0xfe024400),
.ddr_pctl_timing_end_address=((0x00bb << 2) + 0xfe024400),
.ddr_dmc_sticky0=((0x0000 << 2) + 0xfe024800),
.ddr_pll_base_address=((0x0000 << 2) + 0xfe024c00),
.ddr_dmc_apd_address=((0x008c << 2) + 0xfe024400),
.ddr_dmc_asr_address=((0x008d << 2) + 0xfe024400),
.sys_watchdog_base_address=0,//((0x0040 << 2) + 0xfe000000),
.sys_watchdog_enable_value=0x03c401ff,
},
// force id use id mask
{
.soc_family_name="UKNOWN",
.chip_id=CHIP_ID_MASK,//MESON_CPU_MAJOR_ID_G12A,
.preg_sticky_reg0=(0xff634400 + (0x070 << 2)),//PREG_STICKY_G12A_REG0
.ddr_phy_base_address=0xfe000000,
.ddr_pctl_timing_base_address=((0x0000 << 2) + 0xff638400),
.ddr_pctl_timing_end_address=((0x00bb << 2) + 0xff638400),
.ddr_dmc_sticky0=0xff638800,
.sys_watchdog_base_address=((0x3c34 << 2) + 0xffd00000),
.ddr_pll_base_address=((0x0000 << 2) + 0xff638c00),
.ee_timer_base_address=((0x3c62 << 2) + 0xffd00000),
.ee_pwm_base_address=(0xff807000 + (0x001 << 2)),
.ddr_dmc_apd_address=((0x008c << 2) + 0xff638400),
.ddr_dmc_asr_address=((0x008d << 2) + 0xff638400),
},
};
ddr_base_address_table_t * p_ddr_base={0};
#ifdef DISABLE_ENV
int setenv(const char *varname, const char *varvalue)
{
return 1;
}
char *getenv(const char *name)
{
return NULL;
}
#endif
#define DWC_AC_PINMUX_TOTAL 28
#define DWC_DFI_PINMUX_TOTAL 26
//#define DDR_USE_DEFINE_TEMPLATE_CONFIG 1
#define DDR_STICKY_MAGIC_NUMBER 0x20180000
#define DDR_CHIP_ID 0x30
#define DDR_STICKY_SOURCE_DMC_STICKY 0x1
#define DDR_STICKY_SOURCE_SRAM 0x2
#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config
#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000
#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000
#define CONFIG_DDR_TYPE_DDR3 0
#define CONFIG_DDR_TYPE_DDR4 1
#define CONFIG_DDR_TYPE_LPDDR4 2
#define CONFIG_DDR_TYPE_LPDDR3 3
#define CONFIG_DDR_TYPE_LPDDR2 4
//#define CONFIG_DDR_TYPE_LPDDR4X 5
#define CONFIG_DDR_TYPE_AUTO 0xf
#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4
#define CONFIG_DDR0_16BIT_CH0 0x1
#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index)
{
uint32_t read_value=0;
uint32_t addr_t=0;
uint32_t offset=0;
if (size == 8) {
offset=((offset_index%4)<<3);
addr_t=(base_addr+((offset_index>>2) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
read_value=(read_value>>offset)&0xff;
}
if (size == 16) {
offset=((offset_index%2)<<4);
addr_t=(base_addr+((offset_index>>1) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
read_value=(read_value>>offset)&0xffff;
}
return read_value;
}
static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value)
{
uint32_t read_value=0;
uint32_t write_value=0;
uint32_t addr_t=0;
uint32_t offset=0;
if (size == 8) {
offset=((offset_index%4)<<3);
addr_t=(base_addr+((offset_index>>2) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
write_value=(value<<offset)|(read_value&(~(0xff<<offset)));
}
if (size == 16) {
offset=((offset_index%2)<<4);
addr_t=(base_addr+((offset_index>>1) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
}
*(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
return write_value;
}
typedef struct retraining_set{
unsigned short csr_pllctrl3;
unsigned short csr_pptctlstatic[4];
unsigned short csr_trainingincdecdtsmen[4];
unsigned short csr_tsmbyte0[4];
unsigned short csr_vrefinglobal;
//unsigned short csr_dfimrl[4];
unsigned short csr_dqsrcvcntrl[4];
unsigned short csr_pptdqscntinvtrntg0[4];
unsigned short csr_pptdqscntinvtrntg1[4];
unsigned short csr_seq0bgpr[9];
//unsigned short csr_seq0bgpr2;
//unsigned short csr_seq0bgpr3;
//unsigned short csr_seq0bgpr4;
//unsigned short csr_seq0bgpr5;
//unsigned short csr_seq0bgpr6;
//unsigned short csr_seq0bgpr7;
//unsigned short csr_seq0bgpr8;
unsigned short csr_dllgainctl;
unsigned short csr_dlllockpara;
//unsigned short csr_hwtmrl;
unsigned short csr_hwtcamode;
unsigned short csr_hwtlpcsena;
unsigned short csr_hwtlpcsenb;
unsigned short csr_acsmctrl13;
unsigned short csr_acsmctrl23;
//unsigned short rev_41;
} retraining_set_t;
typedef struct ddr_set{
unsigned int magic;
unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
// unsigned int rsv_int0;
unsigned char board_id;
//board id reserve,,do not modify
unsigned char version;
// firmware reserve version,,do not modify
unsigned char DramType;
//support DramType should confirm with amlogic
//#define CONFIG_DDR_TYPE_DDR3 0
//#define CONFIG_DDR_TYPE_DDR4 1
//#define CONFIG_DDR_TYPE_LPDDR4 2
//#define CONFIG_DDR_TYPE_LPDDR3 3
//#define CONFIG_DDR_TYPE_LPDDR2 4
unsigned char DisabledDbyte;
//use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
//bit 0 ---use byte 0 ,1 disable byte 0,
//bit 1 ---use byte 1 ,1 disable byte 1,
//bit 2 ---use byte 2 ,1 disable byte 2,
//bit 3 ---use byte 3 ,1 disable byte 3,
unsigned char Is2Ttiming;
//ddr3/ddr3 use 2t timing,now only support 2t timming
unsigned char HdtCtrl;
//training information control,do not modify
unsigned char dram_rank_config;
//support Dram connection type should confirm with amlogic
//#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
//#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
//#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
//#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1
//#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
//#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
//#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
//#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0
/* rsv_char0. update for diagnose type define */
unsigned char diagnose;
/* imem/dmem define */
unsigned int imem_load_addr;
//system reserve,do not modify
unsigned int dmem_load_addr;
//system reserve,do not modify
unsigned short imem_load_size;
//system reserve,do not modify
unsigned short dmem_load_size;
//system reserve,do not modify
unsigned int ddr_base_addr;
//system reserve,do not modify
unsigned int ddr_start_offset;
//system reserve,do not modify
unsigned short dram_cs0_size_MB;
//config cs0 dram size ,like 1G DRAM ,setting 1024
unsigned short dram_cs1_size_MB;
//config cs1 dram size,like 512M DRAM ,setting 512
/* align8 */
unsigned short training_SequenceCtrl[2];
//system reserve,do not modify
unsigned char phy_odt_config_rank[2];
//unsigned char rever1;
//unsigned char rever2;
unsigned short rank1_ca_vref_permil;
//training odt config ,only use for training
// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
unsigned int dfi_odt_config;
//normal go status od config,use for normal status
//bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
//bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
//bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
//bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
//bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
//bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
//bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
//bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
//bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
//bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
unsigned short DRAMFreq[4];
//config dram frequency,use DRAMFreq[0],ohter reserve
unsigned char PllBypassEn;
//system reserve,do not modify
unsigned char ddr_rdbi_wr_enable;
//system reserve,do not modify
unsigned char ddr_rfc_type;
//config dram rfc type,according dram type,also can use same dram type max config
//#define DDR_RFC_TYPE_DDR3_512Mbx1 0
//#define DDR_RFC_TYPE_DDR3_512Mbx2 1
//#define DDR_RFC_TYPE_DDR3_512Mbx4 2
//#define DDR_RFC_TYPE_DDR3_512Mbx8 3
//#define DDR_RFC_TYPE_DDR3_512Mbx16 4
//#define DDR_RFC_TYPE_DDR4_2Gbx1 5
//#define DDR_RFC_TYPE_DDR4_2Gbx2 6
//#define DDR_RFC_TYPE_DDR4_2Gbx4 7
//#define DDR_RFC_TYPE_DDR4_2Gbx8 8
//#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
//#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
//#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
unsigned char enable_lpddr4x_mode;
//system reserve,do not modify
/* align8 */
unsigned int pll_ssc_mode;
//
/* pll ssc config:
*
* pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
* ppm = strength * 500
* mode: 0=center, 1=up, 2=down
*
* eg:
* 1. config 1000ppm center ss. then mode=0, strength=2
* .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
* 2. config 3000ppm down ss. then mode=2, strength=6
* .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
*/
unsigned short clk_drv_ohm;
//config soc clk pin signal driver stength ,select 20,30,40,60ohm
unsigned short cs_drv_ohm;
//config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm
unsigned short ac_drv_ohm;
//config soc normal address command pin driver stength ,select 20,30,40,60ohm
unsigned short soc_data_drv_ohm_p;
//config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
unsigned short soc_data_drv_ohm_n;
//config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
unsigned short soc_data_odt_ohm_p;
//config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
unsigned short soc_data_odt_ohm_n;
//config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
unsigned short dram_data_drv_ohm;
//config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
unsigned short dram_data_odt_ohm;
//config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
unsigned short dram_ac_odt_ohm;
//config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm
unsigned short soc_clk_slew_rate;
//system reserve,do not modify
unsigned short soc_cs_slew_rate;
//system reserve,do not modify
unsigned short soc_ac_slew_rate;
//system reserve,do not modify
unsigned short soc_data_slew_rate;
//system reserve,do not modify
unsigned short vref_output_permil; //phy
//setting same with vref_dram_permil
unsigned short vref_receiver_permil; //soc
//soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
unsigned short vref_dram_permil;
//soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
unsigned short max_core_timmming_frequency;
//use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
/* align8 */
unsigned char ac_trace_delay[10];
unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
unsigned char lpddr4_x8_mode;
//system reserve,do not modify ,take care ,please follow SI
unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
//use for lpddr3 /lpddr4 ca pinmux remap
unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
//[1],slt test parameter ,use for force delay line offset
//system reserve,do not modify
unsigned short tdqs2dq;
unsigned char dram_data_wr_odt_ohm;
unsigned char bitTimeControl_2d;
//system reserve,do not modify
/* align8 */
unsigned int ddr_dmc_remap[5];
//system reserve,do not modify
/* align8 */
unsigned char ddr_lpddr34_ca_remap[4];
////use for lpddr3 /lpddr4 ca training data byte lane remap
unsigned char ddr_lpddr34_dq_remap[32];
////use for lpddr3 /lpddr4 ca pinmux remap
unsigned int dram_rtt_nom_wr_park[2];
//system reserve,do not modify
unsigned int ddr_func;
//system reserve,do not modify
/* align8 */
//unsigned long rsv_long0[2];
/* v1 end */
// /*
unsigned char read_dqs_delay[16];
unsigned char read_dq_bit_delay[72];
unsigned short write_dqs_delay[16];
// */
unsigned short write_dq_bit_delay[72];
unsigned short read_dqs_gate_delay[16];
unsigned char soc_bit_vref[32];
unsigned char dram_bit_vref[32];
///*
unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq
unsigned char dfi_mrl;
unsigned char dfi_hwtmrl;
unsigned char ARdPtrInitVal;
unsigned char retraining[16];
retraining_set_t retraining_extra_set_t;
//override read bit delay
}ddr_set_t;
ddr_set_t p_ddr_set_t;
#ifndef _SHA256_H
#define _SHA256_H
#define SHA256_SUM_LEN 32
#define SHA256_DER_LEN 19
//extern const uint8_t sha256_der_prefix[];
/* Reset watchdog each time we process this many bytes */
#define CHUNKSZ_SHA256 (64 * 1024)
typedef struct {
uint32_t total[2];
uint32_t state[8];
uint8_t buffer[64];
} sha256_context;
const uint8_t sha256_der_prefix_ddr[SHA256_DER_LEN] = {
0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
0x00, 0x04, 0x20
};
/*
* 32-bit integer manipulation macros (big endian)
*/
#ifndef GET_UINT32_BE
#define GET_UINT32_BE(n,b,i) { \
(n) = ( (unsigned long) (b)[(i) ] << 24 ) \
| ( (unsigned long) (b)[(i) + 1] << 16 ) \
| ( (unsigned long) (b)[(i) + 2] << 8 ) \
| ( (unsigned long) (b)[(i) + 3] ); \
}
#endif
#ifndef PUT_UINT32_BE
#define PUT_UINT32_BE(n,b,i) { \
(b)[(i) ] = (unsigned char) ( (n) >> 24 ); \
(b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \
(b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \
(b)[(i) + 3] = (unsigned char) ( (n) ); \
}
#endif
void sha256_starts_internal(sha256_context * ctx)
{
ctx->total[0] = 0;
ctx->total[1] = 0;
ctx->state[0] = 0x6A09E667;
ctx->state[1] = 0xBB67AE85;
ctx->state[2] = 0x3C6EF372;
ctx->state[3] = 0xA54FF53A;
ctx->state[4] = 0x510E527F;
ctx->state[5] = 0x9B05688C;
ctx->state[6] = 0x1F83D9AB;
ctx->state[7] = 0x5BE0CD19;
}
static void sha256_process_internal(sha256_context *ctx, const uint8_t data[64])
{
uint32_t temp1, temp2;
uint32_t W[64];
uint32_t A, B, C, D, E, F, G, H;
GET_UINT32_BE(W[0], data, 0);
GET_UINT32_BE(W[1], data, 4);
GET_UINT32_BE(W[2], data, 8);
GET_UINT32_BE(W[3], data, 12);
GET_UINT32_BE(W[4], data, 16);
GET_UINT32_BE(W[5], data, 20);
GET_UINT32_BE(W[6], data, 24);
GET_UINT32_BE(W[7], data, 28);
GET_UINT32_BE(W[8], data, 32);
GET_UINT32_BE(W[9], data, 36);
GET_UINT32_BE(W[10], data, 40);
GET_UINT32_BE(W[11], data, 44);
GET_UINT32_BE(W[12], data, 48);
GET_UINT32_BE(W[13], data, 52);
GET_UINT32_BE(W[14], data, 56);
GET_UINT32_BE(W[15], data, 60);
#define SHR(x,n) ((x & 0xFFFFFFFF) >> n)
#define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))
#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3))
#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10))
#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))
#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))
#define F0(x,y,z) ((x & y) | (z & (x | y)))
#define F1(x,y,z) (z ^ (x & (y ^ z)))
#define R(t) \
( \
W[t] = S1(W[t - 2]) + W[t - 7] + \
S0(W[t - 15]) + W[t - 16] \
)
#define P(a,b,c,d,e,f,g,h,x,K) { \
temp1 = h + S3(e) + F1(e,f,g) + K + x; \
temp2 = S2(a) + F0(a,b,c); \
d += temp1; h = temp1 + temp2; \
}
A = ctx->state[0];
B = ctx->state[1];
C = ctx->state[2];
D = ctx->state[3];
E = ctx->state[4];
F = ctx->state[5];
G = ctx->state[6];
H = ctx->state[7];
P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98);
P(H, A, B, C, D, E, F, G, W[1], 0x71374491);
P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF);
P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5);
P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B);
P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1);
P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4);
P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5);
P(A, B, C, D, E, F, G, H, W[8], 0xD807AA98);
P(H, A, B, C, D, E, F, G, W[9], 0x12835B01);
P(G, H, A, B, C, D, E, F, W[10], 0x243185BE);
P(F, G, H, A, B, C, D, E, W[11], 0x550C7DC3);
P(E, F, G, H, A, B, C, D, W[12], 0x72BE5D74);
P(D, E, F, G, H, A, B, C, W[13], 0x80DEB1FE);
P(C, D, E, F, G, H, A, B, W[14], 0x9BDC06A7);
P(B, C, D, E, F, G, H, A, W[15], 0xC19BF174);
P(A, B, C, D, E, F, G, H, R(16), 0xE49B69C1);
P(H, A, B, C, D, E, F, G, R(17), 0xEFBE4786);
P(G, H, A, B, C, D, E, F, R(18), 0x0FC19DC6);
P(F, G, H, A, B, C, D, E, R(19), 0x240CA1CC);
P(E, F, G, H, A, B, C, D, R(20), 0x2DE92C6F);
P(D, E, F, G, H, A, B, C, R(21), 0x4A7484AA);
P(C, D, E, F, G, H, A, B, R(22), 0x5CB0A9DC);
P(B, C, D, E, F, G, H, A, R(23), 0x76F988DA);
P(A, B, C, D, E, F, G, H, R(24), 0x983E5152);
P(H, A, B, C, D, E, F, G, R(25), 0xA831C66D);
P(G, H, A, B, C, D, E, F, R(26), 0xB00327C8);
P(F, G, H, A, B, C, D, E, R(27), 0xBF597FC7);
P(E, F, G, H, A, B, C, D, R(28), 0xC6E00BF3);
P(D, E, F, G, H, A, B, C, R(29), 0xD5A79147);
P(C, D, E, F, G, H, A, B, R(30), 0x06CA6351);
P(B, C, D, E, F, G, H, A, R(31), 0x14292967);
P(A, B, C, D, E, F, G, H, R(32), 0x27B70A85);
P(H, A, B, C, D, E, F, G, R(33), 0x2E1B2138);
P(G, H, A, B, C, D, E, F, R(34), 0x4D2C6DFC);
P(F, G, H, A, B, C, D, E, R(35), 0x53380D13);
P(E, F, G, H, A, B, C, D, R(36), 0x650A7354);
P(D, E, F, G, H, A, B, C, R(37), 0x766A0ABB);
P(C, D, E, F, G, H, A, B, R(38), 0x81C2C92E);
P(B, C, D, E, F, G, H, A, R(39), 0x92722C85);
P(A, B, C, D, E, F, G, H, R(40), 0xA2BFE8A1);
P(H, A, B, C, D, E, F, G, R(41), 0xA81A664B);
P(G, H, A, B, C, D, E, F, R(42), 0xC24B8B70);
P(F, G, H, A, B, C, D, E, R(43), 0xC76C51A3);
P(E, F, G, H, A, B, C, D, R(44), 0xD192E819);
P(D, E, F, G, H, A, B, C, R(45), 0xD6990624);
P(C, D, E, F, G, H, A, B, R(46), 0xF40E3585);
P(B, C, D, E, F, G, H, A, R(47), 0x106AA070);
P(A, B, C, D, E, F, G, H, R(48), 0x19A4C116);
P(H, A, B, C, D, E, F, G, R(49), 0x1E376C08);
P(G, H, A, B, C, D, E, F, R(50), 0x2748774C);
P(F, G, H, A, B, C, D, E, R(51), 0x34B0BCB5);
P(E, F, G, H, A, B, C, D, R(52), 0x391C0CB3);
P(D, E, F, G, H, A, B, C, R(53), 0x4ED8AA4A);
P(C, D, E, F, G, H, A, B, R(54), 0x5B9CCA4F);
P(B, C, D, E, F, G, H, A, R(55), 0x682E6FF3);
P(A, B, C, D, E, F, G, H, R(56), 0x748F82EE);
P(H, A, B, C, D, E, F, G, R(57), 0x78A5636F);
P(G, H, A, B, C, D, E, F, R(58), 0x84C87814);
P(F, G, H, A, B, C, D, E, R(59), 0x8CC70208);
P(E, F, G, H, A, B, C, D, R(60), 0x90BEFFFA);
P(D, E, F, G, H, A, B, C, R(61), 0xA4506CEB);
P(C, D, E, F, G, H, A, B, R(62), 0xBEF9A3F7);
P(B, C, D, E, F, G, H, A, R(63), 0xC67178F2);
ctx->state[0] += A;
ctx->state[1] += B;
ctx->state[2] += C;
ctx->state[3] += D;
ctx->state[4] += E;
ctx->state[5] += F;
ctx->state[6] += G;
ctx->state[7] += H;
}
void sha256_update_internal(sha256_context *ctx, const uint8_t *input, uint32_t length)
{
uint32_t left, fill;
if (!length)
return;
left = ctx->total[0] & 0x3F;
fill = 64 - left;
ctx->total[0] += length;
ctx->total[0] &= 0xFFFFFFFF;
if (ctx->total[0] < length)
ctx->total[1]++;
if (left && length >= fill) {
memcpy((void *) (ctx->buffer + left), (void *) input, fill);
sha256_process_internal(ctx, ctx->buffer);
length -= fill;
input += fill;
left = 0;
}
while (length >= 64) {
sha256_process_internal(ctx, input);
length -= 64;
input += 64;
}
if (length)
memcpy((void *) (ctx->buffer + left), (void *) input, length);
}
static uint8_t sha256_padding[64] = {
0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
void sha256_finish_internal(sha256_context * ctx, uint8_t digest[32])
{
uint32_t last, padn;
uint32_t high, low;
uint8_t msglen[8];
high = ((ctx->total[0] >> 29)
| (ctx->total[1] << 3));
low = (ctx->total[0] << 3);
PUT_UINT32_BE(high, msglen, 0);
PUT_UINT32_BE(low, msglen, 4);
last = ctx->total[0] & 0x3F;
padn = (last < 56) ? (56 - last) : (120 - last);
sha256_update_internal(ctx, sha256_padding, padn);
sha256_update_internal(ctx, msglen, 8);
PUT_UINT32_BE(ctx->state[0], digest, 0);
PUT_UINT32_BE(ctx->state[1], digest, 4);
PUT_UINT32_BE(ctx->state[2], digest, 8);
PUT_UINT32_BE(ctx->state[3], digest, 12);
PUT_UINT32_BE(ctx->state[4], digest, 16);
PUT_UINT32_BE(ctx->state[5], digest, 20);
PUT_UINT32_BE(ctx->state[6], digest, 24);
PUT_UINT32_BE(ctx->state[7], digest, 28);
}
/*
* Output = SHA-256( input buffer ). Trigger the watchdog every 'chunk_sz'
* bytes of input processed.
*/
void sha256_csum_wd_internal(const unsigned char *input, unsigned int ilen,
unsigned char *output, unsigned int chunk_sz)
{
#if 0
int count=0;
for ( count=0;count<ilen;count++)
{
printf("\ninput %08x,p+%08x,%08x",(unsigned int)(unsigned long)(input+count),count,*(input+count));
}
#endif
sha256_context ctx;
sha256_starts_internal(&ctx);
sha256_update_internal(&ctx, input, ilen);
sha256_finish_internal(&ctx, output);
#if 0
for ( count=0;count<32;count++)
{
printf("\noutput %08x,p+%08x,%08x",(unsigned int)(unsigned long)(output+count),count,*(output+count));
}
#endif
}
#endif
typedef struct ddr_sha_s {
unsigned char sha2[SHA256_SUM_LEN];
ddr_set_t ddrs;
unsigned char sha_chip_id[MESON_CPU_CHIP_ID_SIZE];
} ddr_sha_t;
ddr_sha_t ddr_sha = {{0}};
ddr_set_t *ddr_set_t_p_arrary = &ddr_sha.ddrs;
int check_base_address(void)
{
unsigned int table_max=(sizeof(__ddr_base_address_table))/(sizeof(ddr_base_address_table_t));
unsigned int table_index=0;
char chip_id=0;
chip_id=ddr_get_chip_id();
p_ddr_base=(ddr_base_address_table_t *)(&__ddr_base_address_table);
printf("\ntable_max=%08x,p_ddr_base_add=%08x,chip_id=%08x",table_max,(unsigned int)( unsigned long )p_ddr_base,chip_id);
if (chip_id == 0)
{
chip_id=CHIP_ID_MASK;
}
if (chip_id)
{
for (table_index=0;table_index<table_max;table_index++)
{//p_ddr_base=(p_ddr_base+1);
printf("\ntable_index=%08x,p_ddr_base_add=%08x,(p_ddr_base->chip_id==%08x",
table_index,(unsigned int)( unsigned long )p_ddr_base,(p_ddr_base->chip_id));
if ((p_ddr_base->chip_id == chip_id) && (chip_id<CHIP_ID_MASK))
{
printf("\nfind match chip id=0x%08x ,%s",chip_id,p_ddr_base->soc_family_name);
break;
}
else
{
printf("\nno find match chip id=0x%08x, ,%s will use default value",chip_id,p_ddr_base->soc_family_name);
}
p_ddr_base=(p_ddr_base+1);
}
}
int count=0;
for (count = 0; count <12; count++) {
ddr_sha.sha_chip_id[count]=global_chip_id[count];
}
return (unsigned int)( unsigned long )(p_ddr_base);
}
char* itoa_ddr_test(int num,char*str,int radix)
{/*Ë÷Òý±í*/
printf("\nitoa_ddr_test 1\n");
char index[]="0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
unsigned unum;/*Öмä±äÁ¿*/
char temp;
int i=0,j,k;
/*È·¶¨unumµÄÖµ*/
if (radix == 10 && num<0) /*Ê®½øÖƸºÊý*/
{
unum = (unsigned)-num;
str[i++] = '-';
}
else
unum = (unsigned)num;/*ÆäËûÇé¿ö*/
/*ת»»*/
printf("\nitoa_ddr_test 2\n");
printf("\nunum=0x%08x\n",unum);
printf("\nunum2=0x%08x\n",(unum%(unsigned)radix));
printf("\nradix=0x%08x\n",radix);
str[0] = index[0];
printf("\nitoa_ddr_test 22\n");
unum /= radix;
printf("\nitoa_ddr_test 23\n");
do {
str[i++] = index[unum%(unsigned)radix];
unum /= radix;
}while(unum);
printf("\nitoa_ddr_test 3\n");
str[i] = '\0';
/*ÄæÐò*/
if (str[0] == '-')
k = 1;/*Ê®½øÖƸºÊý*/
else
k = 0;
printf("\nitoa_ddr_test 4\n");
for (j = k;j <= (i-1)/2;j++)
{
temp = str[j];
str[j] = str[i-1+k-j];
str[i-1+k-j] = temp;
}
return str;
}
//#endif
/*
char *strsep(char **stringp, const char *delim)
{
char *s;
const char *spanp;
int c, sc;
char *tok;
if ((s = *stringp)== NULL)
return (NULL);
for (tok = s;;) {
c = *s++;
spanp = delim;
do {
if ((sc =*spanp++) == c) {
if (c == 0)
s = NULL;
else
s[-1] = 0;
*stringp = s;
return (tok);
}
} while (sc != 0);
}
}
*/
int TOLOWER(int ch)
{
if ((unsigned int)(ch - 'A') < 26u )
ch += 'a' - 'A';
return ch;
}//´óд×Öĸת»»ÎªÐ¡Ð´×Öĸ¡£
int isxdigit(int ch)
{
return (unsigned int)( ch - '0') < 10u ||
(unsigned int)((ch | 0x20) - 'a') < 6u;
}//ÅжÏ×Ö·ûcÊÇ·ñΪʮÁù½øÖÆÊý×Ö¡£
//µ±cΪA-F,a-f»ò0-9Ö®¼äµÄÊ®Áù½øÖÆÊý×Öʱ£¬·µ»Ø·ÇÁãÖµ£¬·ñÔò·µ»ØÁã¡£
int isdigit(int ch)
{
return (unsigned int)(ch - '0') < 10u;
}//ÅжÏ×Ö·ûcÊÇ·ñΪÊý×Ö
unsigned int simple_guess_base(const char *cp)
{
if (cp[0] == '0') {
if (TOLOWER(cp[1]) == 'x' && isxdigit(cp[2]))
return 16;
else
// return 8;
return 10;
} else {
return 10;
}
}
unsigned int simple_strtoull_ddr(const char *cp, char **endp, unsigned int base)
{
unsigned int result = 0;
//printf("test sizeof(str_buf)==%d\n",1);
if (cp == NULL) //jiaxing add 20170616
return 0;
if (!base)
base = simple_guess_base(cp);
if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x')
cp += 2;
if (base == 10) {
while ((*cp)== '0')
cp++;
}
while (isxdigit(*cp)) {//¼ì²éµ±Ç°cpÊÇ·ñÊǸöÊ®Áù½øÖÆÊýÖµ£¬²»ÊÇÖ±½Ó·µ»Ø0
unsigned int value;
value = isdigit(*cp) ? *cp - '0' : TOLOWER(*cp) - 'a' + 10;
if (value >= base)
break;
result = result * base + value;
cp++;
}
if (endp)
*endp = (char *)cp;
return result;
}
unsigned int env_to_a_num(const char *env_name)
{
char *str_buf = NULL;
char buf[48];
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
str_buf = getenv(env_name);
unsigned int a_num = 0;
char *endp;
printf("str==%s\n",str_buf);
a_num=simple_strtoull_ddr(str_buf, &endp, 0);
printf("%s==0x%08x\n",str_buf,a_num);
return a_num;
}
unsigned int a_num_to_env(const char *env_name ,unsigned int *a_num)
{
char *str_buf=NULL;
char buf[1024];
//unsigned int str_to_numarry[48];
//str_buf = (char *)malloc(sizeof(char)*1024);
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
str_buf = getenv(env_name);
printf("str==%s\n",str_buf);
sprintf(buf, "0x%08x", *a_num);
printf( "%s==0x%08x", buf,*a_num);
setenv(env_name, buf);
run_command("save",0);
return 1;
}
unsigned int env_to_num(const char *env_name,unsigned int *num_arry)
{
char *str_buf = NULL;
char buf[1024];
unsigned int str_to_numarry[48];
//str_buf = (char *)malloc(sizeof(char)*1024);
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
str_buf = getenv(env_name);
char * str[48];
char *endp;
int i;
for (i = 0; i < 48; i++)
str_to_numarry[i] = 0;
printf("str==%s\n",str_buf);
for (i = 0; i < 48; i++) {
str[i] = strsep(&str_buf, ";");
//str[i] = strsep(&str_buf, " ");
if (str[i] == NULL)
break;
str_to_numarry[i] = simple_strtoull_ddr(str[i], &endp, 0);
//printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
//num_arry[i]=str_to_numarry[i];
}
for (i = 0; i < 48; i++) {
printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
num_arry[i] = str_to_numarry[i];
}
//num_arry=(unsigned int *)(&str_to_numarry);
return 1;
}
unsigned int num_to_env(const char *env_name,unsigned int *num_arry)
{
char *str_buf=NULL;
char buf[1024];
int i;
//unsigned int str_to_numarry[48];
//str_buf = (char *)malloc(sizeof(char)*1024);
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
str_buf = getenv(env_name);
//char * str[48];
printf("str==%s\n",str_buf);
sprintf(buf, "0x%08x", num_arry[0]);
for (i = 1; i < 48; i++) {
//num_arry[i]=0;
sprintf(buf, "%s;0x%08x", buf,num_arry[i]);
printf("%d %d\n", i,num_arry[i]);
}
//sprintf(str, "%lx", value);
printf( "%s", buf);
setenv(env_name, buf);
run_command("save",0);
//num_arry=(unsigned int *)(&str_to_numarry);
return 1;
}
#define TDATA32F 0xffffffff
#define TDATA32A 0xaaaaaaaa
#define TDATA325 0x55555555
//#define PREG_STICKY_G12A_REG0 (0xff634400 + (0x070 << 2))
//#define PREG_STICKY_A1_REG0 ((0x00b0 << 2) + 0xfe005800)
//#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe005800)
//#define (p_ddr_base->ddr_phy_base_address) (0xfc000000)
//#define DDR_TEST_AUTO_TEST_CMD_MAGIC 0x01234567
//#define DMC_STICKY_0 ((0x0000 << 2) + 0xff639800)
//#define DMC_STICKY_0 ((0x0000 << 2) + 0xfd020800)
//#define (p_ddr_base->ddr_dmc_sticky0) (DMC_STICKY_0)
#define DMC_STICKY_MAGIC_0 0x12345678
#define DMC_STICKY_MAGIC_1 0xabcdbead
#define DMC_STICKY_UBOOT_WINDOW_MAGIC_1 0x22
#define DMC_STICKY_AUTO_TEST_CMD_INDEX_MAGIC_1 0x33
//#define (p_ddr_base->preg_sticky_reg0) SYSCTRL_STICKY_REG0//(DMC_STICKY_0)
//#define (p_ddr_base->preg_sticky_reg0+4) ((p_ddr_base->preg_sticky_reg0)+4)
//#define (p_ddr_base->ddr_ddr_pctl_timing_end_address) ((0x001d << 2) + 0xff638400)
//#define (p_ddr_base->ddr_pctl_timing_base_address) ((0x0000 << 2) + 0xff638400)
//#define (p_ddr_base->ddr_ddr_pctl_timing_end_address) ((0x001d << 2) + 0xfd020400)
//#define (p_ddr_base->ddr_pctl_timing_base_address) ((0x0000 << 2) + 0xfd020400)
//#define (p_ddr_base->ddr_dmc_sticky0) (DMC_STICKY_0)
unsigned int dmc_sticky[64];
unsigned int sticky_reg_base_add=0;
//#define DDR_TEST_ACLCDLR
unsigned int global_boot_times= 0;
unsigned int watchdog_time_s= 20;
unsigned int global_ddr_clk=1;
unsigned int bdlr_100step=0;
unsigned int ui_1_32_100step=0;
unsigned int error_count =0;
unsigned int error_outof_count_flag=0;
unsigned int copy_test_flag = 0;
unsigned int training_pattern_flag = 0;
unsigned int test_start_addr=0x1080000;
unsigned int dq_lcd_bdl_value_aclcdlr_org_a;
unsigned int dq_lcd_bdl_value_bdlr0_org_a;
unsigned int dq_lcd_bdl_value_aclcdlr_min_a;
unsigned int dq_lcd_bdl_value_bdlr0_min_a;
unsigned int dq_lcd_bdl_value_aclcdlr_max_a;
unsigned int dq_lcd_bdl_value_bdlr0_max_a;
unsigned int dq_lcd_bdl_value_aclcdlr_status_a;
unsigned int dq_lcd_bdl_value_bdlr0_status_a;
unsigned int dq_lcd_bdl_value_aclcdlr_org_b;
unsigned int dq_lcd_bdl_value_bdlr0_org_b;
unsigned int dq_lcd_bdl_value_aclcdlr_min_b;
unsigned int dq_lcd_bdl_value_bdlr0_min_b;
unsigned int dq_lcd_bdl_value_aclcdlr_max_b;
unsigned int dq_lcd_bdl_value_bdlr0_max_b;
unsigned int dq_lcd_bdl_value_wdq_org_a[4];
unsigned int dq_lcd_bdl_value_rdqs_org_a[4];
unsigned int dq_lcd_bdl_value_wdq_min_a[4];
unsigned int dq_lcd_bdl_value_wdq_max_a[4];
unsigned int dq_lcd_bdl_value_rdqs_min_a[4];
unsigned int dq_lcd_bdl_value_rdqs_max_a[4];
unsigned int dq_lcd_bdl_value_wdq_status_a[4];
unsigned int dq_lcd_bdl_value_rdqs_status_a[4];
unsigned int dq_lcd_bdl_value_wdq_org_b[4];
unsigned int dq_lcd_bdl_value_rdqs_org_b[4];
unsigned int dq_lcd_bdl_value_wdq_min_b[4];
unsigned int dq_lcd_bdl_value_wdq_max_b[4];
unsigned int dq_lcd_bdl_value_rdqs_min_b[4];
unsigned int dq_lcd_bdl_value_rdqs_max_b[4];
unsigned int dq_lcd_bdl_value_wdq_status_b[4];
unsigned int dq_lcd_bdl_value_rdqs_status_b[4];
unsigned int acbdlr0_9_reg_org[10];
unsigned int acbdlr0_9_reg_setup_max[40];
unsigned int acbdlr0_9_reg_hold_max[40];
unsigned int acbdlr0_9_reg_setup_time[40];
unsigned int acbdlr0_9_reg_hold_time[40];
//unsigned int data_bdlr0_5_reg_org[6];
unsigned int data_bdlr0_5_reg_org[28];//4//4lane
unsigned int bdlr0_9_reg_setup_max[24*4];//4//4 lane 96 bdlr
unsigned int bdlr0_9_reg_hold_max[24*4];
unsigned int bdlr0_9_reg_setup_time[24*4];
unsigned int bdlr0_9_reg_hold_time[24*4];
unsigned int pre_fetch_enable=0;
#define readl(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
#define writel(data ,addr) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
#define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
#define rd_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
//#define CONFIG_DDR_CMD_BDL_TUNE
//#define CONFIG_CMD_DDR_TEST
#ifndef CONFIG_CHIP
//#define CONFIG_CHIP CHIP_OLD //CHIP_OLD// //#define CHIP_OLD 0 //#define CHIP_TXLX 1
#define CHIP_OLD 0
#define CHIP_TXLX 1
#define CHIP_A113 2
#define CHIP_G12 3
#define CONFIG_CHIP CHIP_G12// CHIP_OLD//
#endif
#define P_DDR_PHY_DEFAULT 0
#define P_DDR_PHY_GX_BABY 1
#define P_DDR_PHY_GX_TV_BABY 2
#define P_DDR_PHY_905X 3
//#define P_DDR_PHY_OLD_TAG 0
#define P_DDR_PHY_G12 4
#define CONFIG_DDR_PHY P_DDR_PHY_G12
//#define G12_AM_DDR_PLL_CNTL0 0xff638c00
//#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
//#include <asm/arch/secure_apb.h>
//#endif
#define PATTERN_USE_DDR_DES
#define USE_64BIT_POINTER
//#define USE_32BIT_POINTER
#ifdef USE_64BIT_POINTER
#define p_convter_int(a) ( unsigned int )( unsigned long )(a)
#define int_convter_p(a) ( unsigned long )(a)
#else
#define p_convter_int(a) ( unsigned int )(a)
#define int_convter_p(a) ( unsigned int )(a)
#endif
#ifdef PATTERN_USE_DDR_DES
#define des_pattern(a,b,c,d) (des[a]^pattern_##b[c][d])
#define des_inv_pattern(a,b,c,d) ( des[a]^(~(pattern_##b[c][d])))
#define des_xor_pattern(a,b) ( a^b)
//des[temp_i]^pattern_2[temp_k][temp_i]
#else
#define des_pattern(a,b,c,d) (des[a]&0)+pattern_##b[c][d]
#define des_inv_pattern(a,b,c,d) (des[a]&0)+~(pattern_##b[c][d])
#define des_xor_pattern(a,b) (a&0+b)
#endif
#define DDR_LCDLR_CK_USE_FAST_PATTERN
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
#define DDR_PREFETCH_CACHE
#endif
#ifdef DDR_PREFETCH_CACHE
#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
#else
#define ddr_pld_cache(P)
#endif
#define DDR_TEST_START_ADDR 0x1080000// 0x10000000 //CONFIG_SYS_MEMTEST_START
#define DDR_TEST_SIZE 0x2000000
//#define DDR_TEST_SIZE 0x2000
#if (CONFIG_CHIP>=CHIP_TXLX)
//#define P_EE_TIMER_E (volatile unsigned int *)((0x3c62 << 2) + 0xffd00000)
//#define P_PIN_MUX_REG1 P_PERIPHS_PIN_MUX_1// (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
//#define P_PIN_MUX_REG2 P_PERIPHS_PIN_MUX_2// (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
//#define P_PIN_MUX_REG3 P_PERIPHS_PIN_MUX_3//(((volatile unsigned *)(0xda834400 + (0x2f << 2))))
//#define P_PIN_MUX_REG7 P_PERIPHS_PIN_MUX_7//(((volatile unsigned *)(0xda834400 + (0x33 << 2))))
#endif
#define get_us_time() (rd_reg(p_ddr_base->ee_timer_base_address))// (readl(P_ISA_TIMERE))
//#define DDR_PHY_BASE (0xfc000000)
//#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address)))=((uint16_t)dat)
//#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address)))
#define ACX_MAX 0x80
unsigned int dwc_ddrphy_apb_wr(unsigned int addr,unsigned int dat)
{
*(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address)))=((uint16_t)dat);
return 1;
}
unsigned int dwc_ddrphy_apb_rd(unsigned int addr)
{
return *(volatile uint16_t *)(int_convter_p(((addr) << 1)+(p_ddr_base->ddr_phy_base_address)));
}
void ddr_udelay(unsigned int us)
{
unsigned int t0 = (rd_reg((p_ddr_base->ee_timer_base_address)));
while ((rd_reg(((p_ddr_base->ee_timer_base_address)))) - t0 <= us) ;
}
#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1
#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2
#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3
#define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4
#define DDR_PARAMETER_READ 1
#define DDR_PARAMETER_WRITE 2
#define DDR_PARAMETER_LEFT 1
#define DDR_PARAMETER_RIGHT 2
typedef struct ddr_test_struct {
unsigned int ddr_data_source ;
unsigned int ddr_data_test_size ;
unsigned int ddr_address_test_size ;
unsigned int ddr_test_watchdog_times_s ;
unsigned int ddr_test_lane_disable ;
unsigned int ddr_test_window_flag[8] ;
unsigned int ddr_test_window_data[100] ;
} ddr_test_struct_t;
ddr_test_struct_t *g_ddr_test_struct;
unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
{
if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
{
sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0))&0xffff);
if (read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
if (read_write_flag == DDR_PARAMETER_READ)
parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
{
char *pre_env_name = "ddr_test_data_num";
char *env_name = "ddr_test_data_num_0000";
char *str_buf = NULL;
char *temp_s = NULL;
char *endp = NULL;
char buf[1024];
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
sprintf(buf, "0x%08x", parameter_value);
if (read_write_flag == DDR_PARAMETER_WRITE)
{
setenv(env_name, buf);
run_command("save",0);
}
if (read_write_flag == DDR_PARAMETER_READ)
{
temp_s = getenv(env_name);
if (temp_s)
parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
else
parameter_value = 0;
}
}
if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
{
sticky_reg_base_add=((p_ddr_base->preg_sticky_reg0));
if (read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
if (read_write_flag == DDR_PARAMETER_READ)
parameter_value=rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
return parameter_value;
}
unsigned int read_write_window_test_flag(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
{
if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
{
sticky_reg_base_add = p_ddr_base->preg_sticky_reg0;
if (read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
if (read_write_flag == DDR_PARAMETER_READ)
parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
{
sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0))&0xffff);
if (read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
if (read_write_flag == DDR_PARAMETER_READ)
parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
{
char *pre_env_name = "ddr_test_data_num";
char *env_name = "ddr_test_data_num_0000";
char *str_buf = NULL;
char *temp_s = NULL;
char *endp = NULL;
char buf[1024];
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
sprintf(buf, "0x%08x", parameter_value);
if (read_write_flag == DDR_PARAMETER_WRITE)
{
setenv(env_name, buf);
run_command("save",0);
}
if (read_write_flag == DDR_PARAMETER_READ)
{
temp_s = getenv(env_name);
if (temp_s)
parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
else
parameter_value = 0;
}
}
return parameter_value;
}
//#define (p_ddr_base->sys_watchdog_base_address) ((0x0040 << 2) + 0xfe000000)
//#define (p_ddr_base->sys_watchdog_base_address+4) ((0x0041 << 2) + 0xfe000000)
//#define (p_ddr_base->sys_watchdog_base_address+8) ((0x0042 << 2) + 0xfe000000)
//#define (p_ddr_base->sys_watchdog_base_address+12) ((0x0043 << 2) + 0xfe000000)
void ddr_test_watchdog_init(uint32_t msec)
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address) = (1<<24)|(1<<25)|(1<<22)|(1<<21)|(24000-1);
// set timeout
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+8) = msec;
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+12) = 0;
// enable
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address) |= (1<<18);
}
void ddr_test_watchdog_clear(void)
{
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+12) = 0;
}
void ddr_test_watchdog_disable(void)
{
// turn off internal counter and disable
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address) &= ~((1<<18)|(1<<25));
}
void ddr_test_watchdog_enable(uint32_t sec)
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
// writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address)=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
if (sec*100>0xffff)
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+8)=0xffff;
else
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+8)=sec*100; //max 655s
//writel(0,(unsigned int )P_WATCHDOG_RESET);
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address+12)=0;
//*P_WATCHDOG_RESET = 0;
// enable
*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address)=(*(volatile uint32_t *)( unsigned long )(p_ddr_base->sys_watchdog_base_address))|(1<<18);
//writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL |= (1<<18);
#endif
printf("\nP_WATCHDOG_ENABLE\n");
}
void ddr_test_watchdog_reset_system(void)
{
int i;
//_udelay(10000); //wait print
if (p_ddr_base->sys_watchdog_enable_value == 0)
p_ddr_base->sys_watchdog_enable_value=0x3 | (1 << 21) // sys reset en
| (1 << 23) // interrupt en
| (1 << 24) // clk en
| (1 << 25) // clk div en
| (1 << 26) ;// sys reset now
writel(0, (p_ddr_base->sys_watchdog_base_address+12));
while (1) {
writel(p_ddr_base->sys_watchdog_enable_value
, (p_ddr_base->sys_watchdog_base_address));
//writel(0, (p_ddr_base->sys_watchdog_base_address+12));
writel(0, (p_ddr_base->sys_watchdog_base_address+12));
writel((p_ddr_base->sys_watchdog_enable_value) | (1<<18),
(p_ddr_base->sys_watchdog_base_address));// watchdog en
for (i=0; i<100; i++)
readl((p_ddr_base->sys_watchdog_base_address));/*Deceive gcc for waiting some cycles */
}
}
#if 0
void ddr_test_watchdog_init(uint32_t msec)
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
// writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
*P_WATCHDOG_CNTL = (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1);
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
*P_WATCHDOG_TCNT = msec;
//writel(0,(unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET = 0;
//*P_WATCHDOG_RESET = 0;
// enable
*P_WATCHDOG_CNTL = (*P_WATCHDOG_CNTL)|(1<<18);
//writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL |= (1<<18);
#else
*P_WATCHDOG_CNTL = (0<<24)|(msec*8-1);
//*P_WATCHDOG_TCNT=msec;
#endif
}
void ddr_test_watchdog_enable(uint32_t sec)
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
// writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
*P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
if (sec*100>0xffff)
*P_WATCHDOG_TCNT=0xffff;
else
*P_WATCHDOG_TCNT=sec*100; //max 655s
//writel(0,(unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET=0;
//*P_WATCHDOG_RESET = 0;
// enable
*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
//writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL |= (1<<18);
#else
//*P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(sec*8000-1);
*P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(0xffff);
printf("\nm8baby_watchdog max only 5s,please take care test size not too long for m8baby\n");
#endif
printf("\nP_WATCHDOG_ENABLE\n");
}
void ddr_test_watchdog_disable(void )
{
// src: 24MHz
// div: 24000 for 1ms
// reset ao-22 and ee-21
// writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
*P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
//*P_WATCHDOG_TCNT=sec*100;
//writel(0,(unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET=0;
//*P_WATCHDOG_RESET = 0;
// enable
*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
//writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
//*P_WATCHDOG_CNTL |= (1<<18);
#else
*P_WATCHDOG_CNTL=(0<<24)|(0<<19)|(24000-1);
#endif
printf("\nP_WATCHDOG_DISABLE\n");
}
void ddr_test_watchdog_clear(void )
{
*P_WATCHDOG_RESET=0;
}
void ddr_test_watchdog_reset_system(void)
{
//#define P_WATCHDOG_CNTL 0xc11098d0
//#define P_WATCHDOG_CNTL1 0xc11098d4
//#define P_WATCHDOG_TCNT 0xc11098d8
//#define P_WATCHDOG_RESET 0xc11098dc
#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
int i;
while (1) {
/*
writel( 0x3 | (1 << 21) // sys reset en ao ee 3
| (1 << 23) // interrupt en
| (1 << 24) // clk en
| (1 << 25) // clk div en
| (1 << 26) // sys reset now ao ee 3
, (unsigned int )P_WATCHDOG_CNTL);
*/
*P_WATCHDOG_CNTL=
0x3 | (1 << 21) // sys reset en ao ee 3
| (1 << 23) // interrupt en
| (1 << 24) // clk en
| (1 << 25) // clk div en
| (1 << 26); // sys reset now ao ee 3;
//printf("\nP_WATCHDOG_CNTL reg_add_%x08==%x08",(unsigned int )P_WATCHDOG_CNTL,readl((unsigned int )P_WATCHDOG_CNTL));
//printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
//printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
printf("\nP_WATCHDOG_CNTLREG_ADD %x08==%x08",(unsigned int)(unsigned long)P_WATCHDOG_CNTL,
*P_WATCHDOG_CNTL);
//writel(0, (unsigned int )P_WATCHDOG_RESET);
*P_WATCHDOG_RESET=0;
// writel(readl((unsigned int )P_WATCHDOG_CNTL) | (1<<18), // watchdog en
//(unsigned int )P_WATCHDOG_CNTL);
*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
for (i=0; i<100; i++)
*P_WATCHDOG_CNTL;
//readl((unsigned int )P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */
}
#else
//WRITE_CBUS_REG(WATCHDOG_TC, 0xf080000 | 2000);
*P_WATCHDOG_CNTL=(0xf080000 | 2000);
#endif
while (1) ;
}
#endif
static void ddr_write(void *buff, unsigned int m_length)
{
unsigned int *p;
unsigned int i, j, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
for (j=0;j<32;j++)
{
if (m_len >= 128)
n = 32;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
switch (i)
{
case 0:
case 9:
case 14:
case 25:
case 30:
*(p+i) = TDATA32F;
break;
case 1:
case 6:
case 8:
case 17:
case 22:
*(p+i) = 0;
break;
case 16:
case 23:
case 31:
*(p+i) = TDATA32A;
break;
case 7:
case 15:
case 24:
*(p+i) = TDATA325;
break;
case 2:
case 4:
case 10:
case 12:
case 19:
case 21:
case 27:
case 29:
*(p+i) = 1<<j;
break;
case 3:
case 5:
case 11:
case 13:
case 18:
case 20:
case 26:
case 28:
*(p+i) = ~(1<<j);
break;
}
}
if (m_len > 128)
{
m_len -= 128;
p += 32;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_read(void *buff, unsigned int m_length)
{
unsigned int *p;
unsigned int i, j, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
for (j=0;j<32;j++)
{
if (m_len >= 128)
n = 32;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
if ((error_outof_count_flag) && (error_count))
{
printf("Error data out of count");
m_len=0;
break;
}
switch (i)
{
case 0:
case 9:
case 14:
case 25:
case 30:
if (*(p+i) != TDATA32F)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
}
break;
case 1:
case 6:
case 8:
case 17:
case 22:
if (*(p+i) != 0)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
}break;
case 16:
case 23:
case 31:
if (*(p+i) != TDATA32A)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
} break;
case 7:
case 15:
case 24:
if (*(p+i) != TDATA325)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
} break;
case 2:
case 4:
case 10:
case 12:
case 19:
case 21:
case 27:
case 29:
if (*(p+i) != 1<<j)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 1<<j);
} break;
case 3:
case 5:
case 11:
case 13:
case 18:
case 20:
case 26:
case 28:
if (*(p+i) != ~(1<<j))
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~(1<<j));
} break;
}
}
if (m_len > 128)
{
m_len -= 128;
p += 32;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_write4(void *buff, unsigned int m_length)
{
unsigned int *p;
unsigned int i, j, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
for (j=0;j<32;j++)
{
if (m_len >= 128)
n = 32;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
switch (i)
{
case 0:
case 1:
case 2:
case 3:
*(p+i) = 0xff00ff00;
break;
case 4:
case 5:
case 6:
case 7:
*(p+i) = ~0xff00ff00;
break;
case 8:
case 9:
case 10:
case 11:
*(p+i) = 0xaa55aa55;
break;
case 12:
case 13:
case 14:
case 15:
*(p+i) = ~0xaa55aa55;
break;
case 16:
case 17:
case 18:
case 19:
case 24:
case 25:
case 26:
case 27:
*(p+i) = 1<<j;
break;
case 20:
case 21:
case 22:
case 23:
case 28:
case 29:
case 30:
case 31:
*(p+i) = ~(1<<j);
break;
}
}
if (m_len > 128)
{
m_len -= 128;
p += 32;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_read4(void *buff, unsigned int m_length)
{
unsigned int *p;
unsigned int i, j, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
for (j=0;j<32;j++)
{
if (m_len >= 128)
n = 32;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
if ((error_outof_count_flag) && (error_count))
{
printf("Error data out of count");
m_len=0;
break;
}
switch (i)
{
case 0:
case 1:
case 2:
case 3:
// *(p+i) = 0xff00ff00;
if (*(p+i) != 0xff00ff00)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
}
break;
case 4:
case 5:
case 6:
case 7:
// *(p+i) = ~0xff00ff00;
if (*(p+i) != ~0xff00ff00)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
}
break;
case 8:
case 9:
case 10:
case 11:
// *(p+i) = 0xaa55aa55;
if (*(p+i) != 0xaa55aa55)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
}
break;
case 12:
case 13:
case 14:
case 15:
// *(p+i) = ~0xaa55aa55;
if (*(p+i) != ~0xaa55aa55)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
}
break;
case 16:
case 17:
case 18:
case 19:
case 24:
case 25:
case 26:
case 27:
// *(p+i) = 1<<j;
if (*(p+i) != (1<<j))
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
}
break;
case 20:
case 21:
case 22:
case 23:
case 28:
case 29:
case 30:
case 31:
// *(p+i) = ~(1<<j);
if (*(p+i) !=~( 1<<j))
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
}
break;
}
}
if (m_len > 128)
{
m_len -= 128;
p += 32;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_read_full(void *buff, unsigned int m_length,unsigned int start_pattern,
unsigned int pattern_offset)
{
unsigned int *p;
unsigned int i=0;
unsigned int m_len = m_length&0xfffffffc;
p = ( unsigned int *)buff;
//*(p)=start_pattern;
while (m_len)
{
m_len=m_len-4;
// *(p+i) = (*(p))+pattern_offset;
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p+i) ;
#endif
if ((error_outof_count_flag) && (error_count))
{
printf("Error data out of count");
m_len=0;
break;
}
if ((*(p+i)) !=(start_pattern+pattern_offset*i))
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),
(start_pattern+pattern_offset*i));
}
break;
i++;
}
}
static void ddr_write_full(void *buff, unsigned int m_length,unsigned int start_pattern,
unsigned int pattern_offset)
{
unsigned int *p;
unsigned int i=0;
unsigned int m_len = m_length&0xfffffffc;
p = ( unsigned int *)buff;
//*(p)=start_pattern;
while (m_len)
{
m_len=m_len-4;
*(p+i) = start_pattern+pattern_offset*i;
i++;
}
}
///*
static void ddr_test_copy(void *addr_dest,void *addr_src,unsigned int memcpy_size)
{
unsigned int *p_dest;
unsigned int *p_src;
unsigned int m_len = memcpy_size;
p_dest = ( unsigned int *)addr_dest;
p_src = ( unsigned int *)addr_src;
m_len = m_len/4; //assume it's multiple of 4
while (m_len--) {
ddr_pld_cache(p_src) ;//#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
*p_dest++ = *p_src++;
*p_dest++ = *p_src++;
*p_dest++ = *p_src++;
*p_dest++ = *p_src++;
}
}
//*/
int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *endp;
unsigned long loop = 1;
unsigned int print_flag =1;
// unsigned int start_addr = DDR_TEST_START_ADDR;
unsigned int src_addr = DDR_TEST_START_ADDR;
unsigned int dec_addr = DDR_TEST_START_ADDR+0x8000000;
unsigned int test_size = DDR_TEST_SIZE;
print_flag=1;
printf("\nargc== 0x%08x\n", argc);
int i ;
for (i = 0;i<argc;i++)
printf("\nargv[%d]=%s\n",i,argv[i]);
// printf("\nLINE== 0x%08x\n", __LINE__);
if (argc ==1) {
// start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
// if (*argv[2] == 0 || *endp != 0)
src_addr = DDR_TEST_START_ADDR;
loop = 1;
}
if (argc > 2) {
// start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
src_addr = DDR_TEST_START_ADDR;
}
if (argc > 3) {
src_addr = simple_strtoull_ddr(argv[1], &endp, 16);
dec_addr = simple_strtoull_ddr(argv[2], &endp, 16);
test_size = simple_strtoull_ddr(argv[3], &endp, 16);
loop = 1;
if (*argv[3] == 0 || *endp != 0)
test_size = DDR_TEST_SIZE;
}
if (test_size<0x1000)
test_size = DDR_TEST_SIZE;
if (argc > 4) {
loop = simple_strtoull_ddr(argv[4], &endp, 16);
if (*argv[4] == 0 || *endp != 0)
loop = 1;
}
if (argc > 5) {
print_flag = simple_strtoull_ddr(argv[5], &endp, 16);
if (*argv[5] == 0 || *endp != 0)
print_flag = 1;
}
//COPY_TEST_START:
///*
unsigned long time_start, time_end,test_loops;
test_loops=loop;
unsigned long size_count=0;
size_count=loop*test_size;
time_start = get_us_time();//us
do {
// loop = 1;
ddr_test_copy((void *)(int_convter_p(dec_addr)),(void *)(int_convter_p(src_addr)),test_size);
//bcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size);
//mcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size);
if (print_flag)
{
printf("\nloop==0x%08x", ( unsigned int )loop);
printf("\n \n");
}
}while(--loop);
//*/
time_end = get_us_time();//us
printf("\ncopy %d times use %dus\n \n",( unsigned int )test_loops,( unsigned int )(time_end-time_start));
printf("\nddr copy bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
printf("\rEnd ddr test. \n");
unsigned int m_len=0,counter=0;
unsigned int *p_dest;
p_dest= (void *)(int_convter_p(dec_addr));
m_len = test_size/4; //assume it's multiple of 4
counter=(unsigned int)test_loops;
size_count=counter*test_size;
time_start = get_us_time();//us
do {
loop = 1;
m_len = test_size/4;
while (m_len--) {
ddr_pld_cache(p_dest) ;
*p_dest++ = 0x12345678;
*p_dest++ = 0x12345678;
*p_dest++ = 0x12345678;
*p_dest++ = 0x12345678;
}
}while(--counter);
time_end = get_us_time();//us
printf("\nwrite %d bytes use %dus\n \n",( unsigned int )test_size,( unsigned int )(time_end-time_start));
printf("\nddr write bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
unsigned int *p_src;
p_src= (void *)(int_convter_p(src_addr));
m_len = test_size/4; //assume it's multiple of 4
unsigned int temp0=0;
//unsigned int temp1=0;
//unsigned int temp2=0;
//unsigned int temp3=0;
counter=(unsigned int)test_loops;
size_count=counter*test_size;
// #define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
//writel((1000000<<0), DMC_MON_CTRL1);
//writel((0<<31)|(1<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2);
//writel((1<<31)|(0<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2);
time_start = get_us_time();//us
do {
loop = 1;
m_len = test_size/4;
while (m_len--) {
// ddr_pld_cache(p_src++) ;
#ifdef DDR_PREFETCH_CACHE
__asm__ __volatile__ ("prfm PLDL1KEEP, [%0, #376]"::"r" (p_src));
#endif
p_src++;
temp0 =( *p_src);
m_len--;
m_len--;
m_len--;
m_len--;
m_len--;
m_len--;
m_len--;
}
}while(--counter);
*p_dest++ = temp0;
*p_dest++ = *p_src;
*p_dest++ = *p_src;
*p_dest++ = *p_src;
time_end = get_us_time();//us
printf("\nread %d Kbytes use %dus\n \n",(unsigned int)(size_count/1000),( unsigned int )(time_end-time_start));
printf("\nddr read bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
return 0;
}
U_BOOT_CMD(
ddr_test_copy, 7, 1, do_ddr_test_copy,
"ddr_test_copy function",
"ddr_test_copy 0x08000000 0x10000000 0x02000000 1 0 ? \n"
);
#define DDR_PATTERN_LOOP_1 32
#define DDR_PATTERN_LOOP_2 64
#define DDR_PATTERN_LOOP_3 96
static void ddr_write_pattern4_cross_talk_p(void *buff, unsigned int m_length)
{
unsigned int *p;
// unsigned int i, j, n;
unsigned int i, n;
unsigned int m_len = m_length;
//#define ddr_pattern_loop 32
p = ( unsigned int *)buff;
while (m_len)
{
// for(j=0;j<32;j++)
{
if (m_len >= 128*4)
n = 32*4;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
switch (i)
{
case 0:
case 1:
case 2:
case 3:
case 8:
case 9:
case 10:
case 11:
case 16:
case 17:
case 18:
case 19:
case 24:
case 25:
case 26:
case 27:
// case 30:
*(p+i) = TDATA32F;
break;
case 4:
case 5:
case 6:
case 7:
case 12:
case 13:
case 14:
case 15:
case 20:
case 21:
case 22:
case 23:
case 28:
case 29:
case 30:
case 31:
// case 22:
*(p+i) = 0;
break;
case DDR_PATTERN_LOOP_1+0:
case DDR_PATTERN_LOOP_1+1:
case DDR_PATTERN_LOOP_1+2:
case DDR_PATTERN_LOOP_1+3:
case DDR_PATTERN_LOOP_1+8:
case DDR_PATTERN_LOOP_1+9:
case DDR_PATTERN_LOOP_1+10:
case DDR_PATTERN_LOOP_1+11:
case DDR_PATTERN_LOOP_1+16:
case DDR_PATTERN_LOOP_1+17:
case DDR_PATTERN_LOOP_1+18:
case DDR_PATTERN_LOOP_1+19:
case DDR_PATTERN_LOOP_1+24:
case DDR_PATTERN_LOOP_1+25:
case DDR_PATTERN_LOOP_1+26:
case DDR_PATTERN_LOOP_1+27:
// case 30:
*(p+i) = TDATA32A;
break;
case DDR_PATTERN_LOOP_1+4:
case DDR_PATTERN_LOOP_1+5:
case DDR_PATTERN_LOOP_1+6:
case DDR_PATTERN_LOOP_1+7:
case DDR_PATTERN_LOOP_1+12:
case DDR_PATTERN_LOOP_1+13:
case DDR_PATTERN_LOOP_1+14:
case DDR_PATTERN_LOOP_1+15:
case DDR_PATTERN_LOOP_1+20:
case DDR_PATTERN_LOOP_1+21:
case DDR_PATTERN_LOOP_1+22:
case DDR_PATTERN_LOOP_1+23:
case DDR_PATTERN_LOOP_1+28:
case DDR_PATTERN_LOOP_1+29:
case DDR_PATTERN_LOOP_1+30:
case DDR_PATTERN_LOOP_1+31:
*(p+i) = TDATA325;
break;
case DDR_PATTERN_LOOP_2+0:
case DDR_PATTERN_LOOP_2+1:
case DDR_PATTERN_LOOP_2+2:
case DDR_PATTERN_LOOP_2+3:
*(p+i) =0xfe01fe01;
break;
case DDR_PATTERN_LOOP_2+4:
case DDR_PATTERN_LOOP_2+5:
case DDR_PATTERN_LOOP_2+6:
case DDR_PATTERN_LOOP_2+7:
*(p+i) =0xfd02fd02;
break;
case DDR_PATTERN_LOOP_2+8:
case DDR_PATTERN_LOOP_2+9:
case DDR_PATTERN_LOOP_2+10:
case DDR_PATTERN_LOOP_2+11:
*(p+i) =0xfb04fb04;
break;
case DDR_PATTERN_LOOP_2+12:
case DDR_PATTERN_LOOP_2+13:
case DDR_PATTERN_LOOP_2+14:
case DDR_PATTERN_LOOP_2+15:
*(p+i) =0xf708f708;
break;
case DDR_PATTERN_LOOP_2+16:
case DDR_PATTERN_LOOP_2+17:
case DDR_PATTERN_LOOP_2+18:
case DDR_PATTERN_LOOP_2+19:
*(p+i) =0xef10ef10;
break;
case DDR_PATTERN_LOOP_2+20:
case DDR_PATTERN_LOOP_2+21:
case DDR_PATTERN_LOOP_2+22:
case DDR_PATTERN_LOOP_2+23:
*(p+i) =0xdf20df20;
break;
case DDR_PATTERN_LOOP_2+24:
case DDR_PATTERN_LOOP_2+25:
case DDR_PATTERN_LOOP_2+26:
case DDR_PATTERN_LOOP_2+27:
*(p+i) =0xbf40bf40;
break;
case DDR_PATTERN_LOOP_2+28:
case DDR_PATTERN_LOOP_2+29:
case DDR_PATTERN_LOOP_2+30:
case DDR_PATTERN_LOOP_2+31:
*(p+i) =0x7f807f80;
break;
case DDR_PATTERN_LOOP_3+0:
case DDR_PATTERN_LOOP_3+1:
case DDR_PATTERN_LOOP_3+2:
case DDR_PATTERN_LOOP_3+3:
*(p+i) =0x00000100;
break;
case DDR_PATTERN_LOOP_3+4:
case DDR_PATTERN_LOOP_3+5:
case DDR_PATTERN_LOOP_3+6:
case DDR_PATTERN_LOOP_3+7:
*(p+i) =0x00000200;
break;
case DDR_PATTERN_LOOP_3+8:
case DDR_PATTERN_LOOP_3+9:
case DDR_PATTERN_LOOP_3+10:
case DDR_PATTERN_LOOP_3+11:
*(p+i) =0x00000400;
break;
case DDR_PATTERN_LOOP_3+12:
case DDR_PATTERN_LOOP_3+13:
case DDR_PATTERN_LOOP_3+14:
case DDR_PATTERN_LOOP_3+15:
*(p+i) =0x00000800;
break;
case DDR_PATTERN_LOOP_3+16:
case DDR_PATTERN_LOOP_3+17:
case DDR_PATTERN_LOOP_3+18:
case DDR_PATTERN_LOOP_3+19:
*(p+i) =0x00001000;
break;
case DDR_PATTERN_LOOP_3+20:
case DDR_PATTERN_LOOP_3+21:
case DDR_PATTERN_LOOP_3+22:
case DDR_PATTERN_LOOP_3+23:
*(p+i) =0x00002000;
break;
case DDR_PATTERN_LOOP_3+24:
case DDR_PATTERN_LOOP_3+25:
case DDR_PATTERN_LOOP_3+26:
case DDR_PATTERN_LOOP_3+27:
*(p+i) =0x00004000;
break;
case DDR_PATTERN_LOOP_3+28:
case DDR_PATTERN_LOOP_3+29:
case DDR_PATTERN_LOOP_3+30:
case DDR_PATTERN_LOOP_3+31:
*(p+i) =0x00008000;
break;
}
}
if (m_len >( 128*4))
{
m_len -=( 128*4);
p += 32*4;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_write_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
{
unsigned int *p;
// unsigned int i, j, n;
unsigned int i, n;
unsigned int m_len = m_length;
//#define ddr_pattern_loop 32
p = ( unsigned int *)buff;
while (m_len)
{
// for(j=0;j<32;j++)
{
if (m_len >= 128*4)
n = 32*4;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
switch (i)
{
case 0:
case DDR_PATTERN_LOOP_1+1:
case DDR_PATTERN_LOOP_2+2:
case DDR_PATTERN_LOOP_3+3:
*(p+i) = 0xfe01fe01;
break;
case 4:
case DDR_PATTERN_LOOP_1+5:
case DDR_PATTERN_LOOP_2+6:
case DDR_PATTERN_LOOP_3+7:
*(p+i) = 0xfd02fd02;
break;
case 8:
case DDR_PATTERN_LOOP_1+9:
case DDR_PATTERN_LOOP_2+10:
case DDR_PATTERN_LOOP_3+11:
*(p+i) = 0xfb04fb04;
break;
case 12:
case DDR_PATTERN_LOOP_1+13:
case DDR_PATTERN_LOOP_2+14:
case DDR_PATTERN_LOOP_3+15:
*(p+i) = 0xf708f708;
break;
case 16:
case DDR_PATTERN_LOOP_1+17:
case DDR_PATTERN_LOOP_2+18:
case DDR_PATTERN_LOOP_3+19:
*(p+i) = 0xef10ef10;
break;
case 20:
case DDR_PATTERN_LOOP_1+21:
case DDR_PATTERN_LOOP_2+22:
case DDR_PATTERN_LOOP_3+23:
*(p+i) = 0xdf20df20;
break;
case 24:
case DDR_PATTERN_LOOP_1+25:
case DDR_PATTERN_LOOP_2+26:
case DDR_PATTERN_LOOP_3+27:
*(p+i) = 0xbf40bf40;
break;
case 28:
case DDR_PATTERN_LOOP_1+29:
case DDR_PATTERN_LOOP_2+30:
case DDR_PATTERN_LOOP_3+31:
*(p+i) = 0x7f807f80;
break;
default:
*(p+i) = 0xff00ff00;
break;
break;
}
}
if (m_len >( 128*4))
{
m_len -=( 128*4);
p += 32*4;
}
else
{
p += (m_len>>2);
m_len = 0;
break;
}
}
}
}
static void ddr_read_pattern4_cross_talk_p(void *buff, unsigned int m_length)
{
unsigned int *p;
// unsigned int i, j, n;
unsigned int i, n;
unsigned int m_len = m_length;
p = ( unsigned int *)buff;
while (m_len)
{
// for(j=0;j<32;j++)
{
if (m_len >= 128*4)
n = 32*4;
else
n = m_len>>2;
for (i = 0; i < n; i++)
{
#ifdef DDR_PREFETCH_CACHE
ddr_pld_cache(p) ;
#endif
if ((error_outof_count_flag) && (error_count))
{
printf("Error data out of count");
m_len=0;
break;
}
switch (i)
{
case 0:
case 1:
case 2:
case 3:
case 8:
case 9:
case 10:
case 11:
case 16:
case 17:
case 18:
case 19:
case 24:
case 25:
case 26:
case 27:
// case 30:
// *(p+i) = TDATA32F;
if (*(p+i) != TDATA32F)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
break;
}
break;
case 4:
case 5:
case 6:
case 7:
case 12:
case 13:
case 14:
case 15:
case 20:
case 21:
case 22:
case 23:
case 28:
case 29:
case 30:
case 31:
// case 22:
// *(p+i) = 0;
if (*(p+i) != 0)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
break;}
break;
case DDR_PATTERN_LOOP_1+0:
case DDR_PATTERN_LOOP_1+1:
case DDR_PATTERN_LOOP_1+2:
case DDR_PATTERN_LOOP_1+3:
case DDR_PATTERN_LOOP_1+8:
case DDR_PATTERN_LOOP_1+9:
case DDR_PATTERN_LOOP_1+10:
case DDR_PATTERN_LOOP_1+11:
case DDR_PATTERN_LOOP_1+16:
case DDR_PATTERN_LOOP_1+17:
case DDR_PATTERN_LOOP_1+18:
case DDR_PATTERN_LOOP_1+19:
case DDR_PATTERN_LOOP_1+24:
case DDR_PATTERN_LOOP_1+25:
case DDR_PATTERN_LOOP_1+26:
case DDR_PATTERN_LOOP_1+27:
// case 30:
// *(p+i) = TDATA32A;
if (*(p+i) != TDATA32A)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
break;
}
break;
case DDR_PATTERN_LOOP_1+4:
case DDR_PATTERN_LOOP_1+5:
case DDR_PATTERN_LOOP_1+6:
case DDR_PATTERN_LOOP_1+7:
case DDR_PATTERN_LOOP_1+12:
case DDR_PATTERN_LOOP_1+13:
case DDR_PATTERN_LOOP_1+14:
case DDR_PATTERN_LOOP_1+15:
case DDR_PATTERN_LOOP_1+20:
case DDR_PATTERN_LOOP_1+21:
case DDR_PATTERN_LOOP_1+22:
case DDR_PATTERN_LOOP_1+23:
case DDR_PATTERN_LOOP_1+28:
case DDR_PATTERN_LOOP_1+29:
case DDR_PATTERN_LOOP_1+30:
case DDR_PATTERN_LOOP_1+31:
// *(p+i) = TDATA325;
if (*(p+i) != TDATA325)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
break;
}
break;
case DDR_PATTERN_LOOP_2+0:
case DDR_PATTERN_LOOP_2+1:
case DDR_PATTERN_LOOP_2+2:
case DDR_PATTERN_LOOP_2+3:
// *(p+i) =0xfe01fe01;
if (*(p+i) !=0xfe01fe01)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01);
break;
}
break;
case DDR_PATTERN_LOOP_2+4:
case DDR_PATTERN_LOOP_2+5:
case DDR_PATTERN_LOOP_2+6:
case DDR_PATTERN_LOOP_2+7:
// *(p+i) =0xfd02fd02;
if (*(p+i) != 0xfd02fd02)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02);
break;
}
break;
case DDR_PATTERN_LOOP_2+8:
case DDR_PATTERN_LOOP_2+9:
case DDR_PATTERN_LOOP_2+10:
case DDR_PATTERN_LOOP_2+11:
// *(p+i) =0xfb04fb04;
if (*(p+i) != 0xfb04fb04)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04);
break;
}
break;
case DDR_PATTERN_LOOP_2+12:
case DDR_PATTERN_LOOP_2+13:
case DDR_PATTERN_LOOP_2+14:
case DDR_PATTERN_LOOP_2+15:
// *(p+i) =0xf7b08f708;
if (*(p+i) != 0xf708f708)
{
error_count++;
printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708);
break;
}
break;
case DDR_PATTERN_LOOP_2+16:
case DDR_PATTERN_LOOP_2+17:
case DDR_PATTERN_LOOP_2+18:
case DDR_PATTERN_LOOP_2+19:
// *(p+i) =0xef10ef10;
if (*(p+i) != 0xef10ef10)
{