blob: 5821c3c84545ebc729611d85f64826920108c436 [file] [log] [blame]
Googler0bcd2362023-05-09 16:45:27 +08001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#ifndef __PLL_H
7#define __PLL_H
8
9#define PLL_TEST_SYS_TOTAL 8
10#define PLL_TEST_HDMI_TOTAL 3
11
12typedef struct sys_pll_set_s {
13 unsigned int cpu_clk;
14 unsigned int pll_cntl0;
15 unsigned int pll_cntl1;
16 unsigned int pll_cntl2;
17 unsigned int pll_cntl3;
18 unsigned int pll_cntl4;
19}sys_pll_set_t;
20
21typedef struct sys_pll_cfg_s {
22 sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL];
23}sys_pll_cfg_t;
24
25typedef struct hifi_pll_set_s {
26 unsigned int pll_clk;
27 unsigned int pll_cntl0;
28 unsigned int pll_cntl1;
29 unsigned int pll_cntl2;
30 unsigned int pll_cntl3;
31 unsigned int pll_cntl4;
32}hifi_pll_set_t;
33
34
35#if 0
36unsigned int fix_pll_cfg[6] = {
37 /* CNTL, CNTL2, CNTL3, CNTL4, CNTL5, CNTL6*/
38 /*2G*/ 0x600006FA, 0x59C80000, 0xCA753822, 0x00010006, 0x95520E1A, 0xFC454545,
39};
40
41unsigned int ddr_pll_cfg[][6] = {
42 {0, 0, 0, 0, 0, 0},
43 {0, 0, 0, 0, 0, 0},
44 {0, 0, 0, 0, 0, 0},
45 {0, 0, 0, 0, 0, 0},
46 {0, 0, 0, 0, 0, 0},
47 {0, 0, 0, 0, 0, 0},
48};
49#endif
50
51typedef struct hifipll_rate_table_s {
52 unsigned int rate;
53 unsigned int m;
54 unsigned int n;
55 unsigned int od;
56}hifipll_rate_table_t;
57
58typedef struct gpll_rate_table_s {
59 unsigned int rate;
60 unsigned int m;
61 unsigned int n;
62 unsigned int od;
63}gpll_rate_table_t;
64
65typedef struct ddspll_rate_table_t {
66 unsigned int RATE;
67 unsigned int CTS;
68 unsigned int N;
69}ddspll_rate_table_t;
70
71typedef struct gp_pll_set_s {
72 unsigned int pll_clk;
73 unsigned int pll_cntl0;
74 unsigned int pll_cntl1;
75 unsigned int pll_cntl2;
76 unsigned int pll_cntl3;
77 unsigned int pll_cntl4;
78 unsigned int pll_cntl5;
79}gp_pll_set_t;
80
81typedef struct dds_pll_set_s {
82 unsigned int pll_clk;
83 unsigned int misctop_cntl0;
84 unsigned int pll_cntl0;
85 unsigned int pll_cntl1;
86 unsigned int pll_cntl2;
87 unsigned int pll_cntl3;
88 unsigned int pll_cntl4;
89}dds_pll_set_t;
90
91typedef struct usbphy_pll_set_s {
92 unsigned int pll_clk;
93 unsigned int pll_cntl0;
94 unsigned int pll_cntl1;
95 unsigned int pll_cntl2;
96}usbphy_pll_set_t;
97
98typedef struct ethphy_pll_set_s {
99 unsigned int pll_clk;
100 unsigned int pll_cntl0;
101 unsigned int pll_cntl1;
102 unsigned int pll_cntl2;
103}ethphy_pll_set_t;
104
105#if 0
106unsigned int hdmi_pll_cfg[][7] = {
107 /* get from enc_clk_config.c */
108 /* freq, cntl, cntl1, cntl2, cntl3, cntl4, cntl5 */
109 {5940000, 0x4000027b, 0x800cb300, 0xc60f30e0, 0x0c8e0000, 0x001fa729, 0x01a31500},
110 {5405400, 0x400002e1, 0x800cb0e6, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
111 {4455000, 0x400002b9, 0x800cb280, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
112 {4324320, 0x400002b4, 0x800cb0b8, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
113 {3712500, 0x4000029a, 0x800cb2c0, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
114 {3450000, 0x4000028f, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
115 {3243240, 0x40000287, 0x800cb08a, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
116 {2970000, 0x4000027b, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
117};
118#endif
119
120enum pll_enum {
121 PLL_SYS = 0,
122 PLL_FIX,
123 PLL_DDR,
124 PLL_HIFI,
125 PLL_GP,
126 PLL_DDS,
127 PLL_USBPHY,
128 PLL_ETHPHY,
129 PLL_ENUM,
130};
131int pll_test(int argc, char * const argv[]);
132
133#endif /* __PLL_H */