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nest-open-source / manifest_repos / u-boot / 25e92cfac7f2fb1bd58122777283f02b5d66f4e0 / . / arch / arm / include / asm / arch-sc2 / clk_measure_tab.h
blob: 7bf2819b5f23cc3c94b07ee9e4fc99609a948567 [file] [log] [blame]
Googler25e92cf2023-12-13 10:05:01 +0000[diff] [blame^]1/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#ifndef _ARCH_MESON_SC2_MEASURE_H_
7#define _ARCH_MESON_SC2_MEASURE_H_
8
9static const char* clk_msr_table[] = {
10 [0] = "cts_sys_clk",
11 [1] = "cts_axi_clk",
12 [2] = "cts_rtc_clk",
13 [3] = "cts_dspa_clk",
14 [5] = "cts_mali_clk",
15 [6] = "sys_cpu_clk_div16",
16 [7] = "cts_ceca_clk",
17 [8] = "cts_cecb_clk",
18 [10] = "fclk_div5",
19 [11] = "mp0_clk_out",
20 [12] = "mp1_clk_out",
21 [13] = "mp2_clk_out",
22 [14] = "mp3_clk_out",
23 [15] = "mpll_clk_50m",
24 [16] = "pcie_clk_inp",
25 [17] = "pcie_clk_inn",
26 [18] = "mpll_clk_test_out",
27 [19] = "hifi_pll_clk",
28 [20] = "gp0_pll_clk",
29 [21] = "gp1_pll_clk",
30 [22] = "eth_mppll_50m_ckout",
31 [23] = "sys_pll_div16",
32 [24] = "ddr_dpll_pt_clk",
33 [25] = "earcrx_pll_ckout",
34 [30] = "mod_eth_phy_ref_clk",
35 [31] = "mod_eth_tx_clk",
36 [32] = "cts_eth_clk125Mhz",
37 [33] = "cts_eth_clk_rmii",
38 [34] = "co_clkin_to_mac",
39 [35] = "mod_eth_rx_clk_rmii",
40 [36] = "co_rx_clk",
41 [37] = "co_tx_clk",
42 [38] = "eth_phy_rxclk",
43 [39] = "eth_phy_plltxclk",
44 [40] = "ephy_test_clk",
45 [50] = "vid_pll_div_clk_out",
46 [51] = "cts_enci_clk",
47 [52] = "cts_encp_clk",
48 [53] = "cts_encl_clk",
49 [54] = "cts_vdac_clk",
50 [55] = "cts_cdac_clk_c",
51 [56] = "mod_tcon_clko",
52 [57] = "lcd_an_clk_ph2",
53 [58] = "lcd_an_clk_ph3",
54 [59] = "cts_hdmi_tx_pixel_clk",
55 [60] = "cts_vdin_meas_clk",
56 [61] = "cts_vpu_clk",
57 [62] = "cts_vpu_clkb",
58 [63] = "cts_vpu_clkb_tmp",
59 [64] = "cts_vpu_clkc",
60 [65] = "cts_vid_lock_clk",
61 [66] = "cts_vapbclk",
62 [67] = "cts_ge2d_clk",
63 [68] = "cts_hdcp22_esmclk",
64 [69] = "cts_hdcp22_skpclk",
65 [76] = "hdmitx_tmds_clk",
66 [77] = "cts_hdmitx_sys_clk",
67 [78] = "cts_hdmitx_fe_clk",
68 [79] = "cts_rama_clk",
69 [93] = "cts_vdec_clk",
70 [94] = "cts_wave420_aclk",
71 [95] = "cts_wave420_cclk",
72 [96] = "cts_wave420_bclk",
73 [97] = "cts_hcodec_clk",
74 [98] = "cts_hevcb_clk",
75 [99] = "cts_hevcf_clk",
76 [110] = "cts_sc_clk(smartcard)",
77 [111] = "cts_sar_adc_clk",
78 [113] = "cts_sd_emmc_C_clk(nand)",
79 [114] = "cts_sd_emmc_B_clk",
80 [115] = "cts_sd_emmc_A_clk",
81 [116] = "gpio_msr_clk",
82 [117] = "cts_spicc_1_clk",
83 [118] = "cts_spicc_0_clk",
84 [121] = "cts_ts_clk(temp sensor)",
85 [130] = "audio_vad_clk",
86 [131] = "acodec_dac_clk_x128",
87 [132] = "audio_locker_out_clk",
88 [133] = "audio_locker_in_clk",
89 [134] = "audio_tdmout_c_sclk",
90 [135] = "audio_tdmout_b_sclk",
91 [136] = "audio_tdmout_a_sclk",
92 [137] = "audio_tdmin_lb_sclk",
93 [138] = "audio_tdmin_c_sclk",
94 [139] = "audio_tdmin_b_sclk",
95 [140] = "audio_tdmin_a_sclk",
96 [141] = "audio_resamplea_clk",
97 [142] = "audio_pdm_sysclk",
98 [143] = "audio_spdifoutb_mst_clk",
99 [144] = "audio_spdifout_mst_clk",
100 [145] = "audio_spdifin_mst_clk",
101 [146] = "audio_pdm_dclk",
102 [147] = "audio_resampleb_clk",
103 [148] = "earcrx_pll_dmac_ck",
104 [160] = "pwm_j_clk",
105 [161] = "pwm_i_clk",
106 [162] = "pwm_h_clk",
107 [163] = "pwm_g_clk",
108 [164] = "pwm_f_clk",
109 [165] = "pwm_e_clk",
110 [166] = "pwm_d_clk",
111 [167] = "pwm_c_clk",
112 [168] = "pwm_b_clk",
113 [169] = "pwm_a_clk",
114 [176] = "rng_ring_0",
115 [177] = "rng_ring_1",
116 [178] = "rng_ring_2",
117 [179] = "rng_ring_3",
118 [180] = "dmc_osc_ring(LVT16)",
119 [181] = "gpu_osc_ring0(LVT16)",
120 [182] = "gpu_osc_ring1(ULVT16)",
121 [183] = "gpu_osc_ring2(SVT16)",
122 [184] = "vpu_osc_ring0(SVT24)",
123 [185] = "vpu_osc_ring1(LVT20)",
124 [186] = "vpu_osc_ring2(LVT16)",
125 [187] = "dos_osc_ring0(SVT24)",
126 [188] = "dos_osc_ring1(SVT16)",
127 [189] = "dos_osc_ring2(LVT16)",
128 [190] = "dos_osc_ring3(ULVT20)",
129 [191] = "ddr_osc_ring(LVT16)",
130 [192] = "sys_cpu_osc_ring0(ULVT16)",
131 [193] = "sys_cpu_osc_ring1(ULVT20)",
132 [194] = "sys_cpu_osc_ring2(ULVT16)",
133 [195] = "sys_cpu_osc_ring3(LVT16)",
134 [196] = "axi_sram_osc_ring(SVT16)",
135 [197] = "dspa_osc_ring(SVT16)",
136};
137
138#endif