Googler | 25e92cf | 2023-12-13 10:05:01 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <linux/compiler.h> |
| 9 | #include <amlogic/aml_gpio.h> |
| 10 | #include <asm/arch/gpio.h> |
| 11 | |
| 12 | struct pin_mux_desc { |
| 13 | unsigned char domain; |
| 14 | unsigned char reg; |
| 15 | unsigned char bit; |
| 16 | }; |
| 17 | |
| 18 | #define MUX_AO_DOMAIN 0 |
| 19 | #define MUX_EE_DOMAIN 1 |
| 20 | |
| 21 | #define PIN_MUX(d, r, b) \ |
| 22 | { \ |
| 23 | .domain = d, \ |
| 24 | .reg = r, \ |
| 25 | .bit = b, \ |
| 26 | } |
| 27 | |
| 28 | #define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ |
| 29 | { \ |
| 30 | .name = n, \ |
| 31 | .first = f, \ |
| 32 | .last = l, \ |
| 33 | .regs = { \ |
| 34 | [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \ |
| 35 | [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \ |
| 36 | [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \ |
| 37 | [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \ |
| 38 | [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \ |
| 39 | }, \ |
| 40 | } |
| 41 | #define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ |
| 42 | { \ |
| 43 | .name = n, \ |
| 44 | .first = f, \ |
| 45 | .last = l, \ |
| 46 | .regs = { \ |
| 47 | [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \ |
| 48 | [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \ |
| 49 | [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \ |
| 50 | [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \ |
| 51 | [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \ |
| 52 | }, \ |
| 53 | } |
| 54 | |
| 55 | static struct pin_mux_desc pin_to_gpio[] = { |
| 56 | [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0), |
| 57 | [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4), |
| 58 | [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8), |
| 59 | [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12), |
| 60 | [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16), |
| 61 | [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20), |
| 62 | [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24), |
| 63 | [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28), |
| 64 | [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0), |
| 65 | [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4), |
| 66 | [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8), |
| 67 | [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12), |
| 68 | [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16), |
| 69 | [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20), |
| 70 | [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24), |
| 71 | [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0), |
| 72 | [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4), |
| 73 | [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8), |
| 74 | [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12), |
| 75 | [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16), |
| 76 | [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20), |
| 77 | [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24), |
| 78 | [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28), |
| 79 | [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0), |
| 80 | [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4), |
| 81 | [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8), |
| 82 | [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12), |
| 83 | [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16), |
| 84 | [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20), |
| 85 | [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24), |
| 86 | [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28), |
| 87 | [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0), |
| 88 | [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4), |
| 89 | [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8), |
| 90 | [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12), |
| 91 | [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16), |
| 92 | [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20), |
| 93 | [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24), |
| 94 | [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28), |
| 95 | [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0), |
| 96 | [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0), |
| 97 | [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4), |
| 98 | [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8), |
| 99 | [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12), |
| 100 | [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16), |
| 101 | [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20), |
| 102 | [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24), |
| 103 | [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28), |
| 104 | [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0), |
| 105 | [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4), |
| 106 | [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8), |
| 107 | [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12), |
| 108 | [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16), |
| 109 | [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20), |
| 110 | [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24), |
| 111 | [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28), |
| 112 | [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0), |
| 113 | [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4), |
| 114 | [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8), |
| 115 | [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12), |
| 116 | [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16), |
| 117 | [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20), |
| 118 | [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24), |
| 119 | [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28), |
| 120 | [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0), |
| 121 | [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4), |
| 122 | [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8), |
| 123 | [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12), |
| 124 | [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16), |
| 125 | [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20), |
| 126 | [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24), |
| 127 | [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28), |
| 128 | [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0), |
| 129 | [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4), |
| 130 | [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8), |
| 131 | [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12), |
| 132 | [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16), |
| 133 | [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20), |
| 134 | [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24), |
| 135 | [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28), |
| 136 | [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0), |
| 137 | [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4), |
| 138 | [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8), |
| 139 | [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12), |
| 140 | [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16), |
| 141 | [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20), |
| 142 | [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24), |
| 143 | [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28), |
| 144 | [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0), |
| 145 | [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4), |
| 146 | [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8), |
| 147 | [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12), |
| 148 | [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16), |
| 149 | [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20), |
| 150 | [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24), |
| 151 | [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28), |
| 152 | [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0), |
| 153 | [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4), |
| 154 | [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8), |
| 155 | [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12), |
| 156 | }; |
| 157 | /*sequence of banks keep same as arch-g12a/gpio.h*/ |
| 158 | static struct meson_bank mesontxhd_banks[] = { |
| 159 | /*name first last pullen pull dir out in*/ |
| 160 | AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11), |
| 161 | 3, 0, 2, 0, 0, 0, 4, 0, 1, 0), |
| 162 | AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2), |
| 163 | 3, 16, 2, 16, 0, 16, 4, 16, 1, 16), |
| 164 | BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15), |
| 165 | 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), |
| 166 | BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8), |
| 167 | 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), |
| 168 | BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15), |
| 169 | 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), |
| 170 | BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7), |
| 171 | 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), |
| 172 | BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15), |
| 173 | 5, 0, 5, 0, 16, 0, 17, 0, 18, 0), |
| 174 | BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19), |
| 175 | 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), |
| 176 | }; |
| 177 | |
| 178 | U_BOOT_DEVICES(txhd_gpios) = { |
| 179 | { "gpio_aml", &mesontxhd_banks[0] }, |
| 180 | { "gpio_aml", &mesontxhd_banks[1] }, |
| 181 | { "gpio_aml", &mesontxhd_banks[2] }, |
| 182 | { "gpio_aml", &mesontxhd_banks[3] }, |
| 183 | { "gpio_aml", &mesontxhd_banks[4] }, |
| 184 | { "gpio_aml", &mesontxhd_banks[5] }, |
| 185 | { "gpio_aml", &mesontxhd_banks[6] }, |
| 186 | { "gpio_aml", &mesontxhd_banks[7] }, |
| 187 | }; |
| 188 | |
| 189 | static unsigned long domain[]={ |
| 190 | [MUX_AO_DOMAIN] = 0xff800014, |
| 191 | [MUX_EE_DOMAIN] = 0xff6346c0, |
| 192 | }; |
| 193 | |
| 194 | int clear_pinmux(unsigned int pin) |
| 195 | { |
| 196 | struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin]; |
| 197 | |
| 198 | regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2), |
| 199 | 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit)); |
| 200 | |
| 201 | return 0; |
| 202 | } |
| 203 | |
| 204 | #ifdef CONFIG_AML_SPICC |
| 205 | #include <asm/arch/secure_apb.h> |
| 206 | /* generic pins control for spicc1. |
| 207 | * if deleted, you have to add it into all g12a board files as necessary. |
| 208 | * GPIOH_4: MOSI:regB[19:16]=3 |
| 209 | * GPIOH_5: MISO:regB[23:20]=3 |
| 210 | * GPIOH_7: CLK:regB[31:28]=3 |
| 211 | */ |
| 212 | int spicc1_pinctrl_enable(bool enable) |
| 213 | { |
| 214 | unsigned int val; |
| 215 | |
| 216 | val = readl(P_PERIPHS_PIN_MUX_B); |
| 217 | val &= ~(0xf0ff << 16); |
| 218 | if (enable) |
| 219 | val |= 0x3033 << 16; |
| 220 | writel(val, P_PERIPHS_PIN_MUX_B); |
| 221 | return 0; |
| 222 | } |
| 223 | #endif /* CONFIG_AML_SPICC */ |