| Googler | 25e92cf | 2023-12-13 10:05:01 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. |
| 4 | * (c) Copyright 2016 Topic Embedded Products. |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARCH_PS7_INIT_GPL_H |
| 8 | #define _ASM_ARCH_PS7_INIT_GPL_H |
| 9 | |
| 10 | /* Opcode exit is 0 all the time */ |
| 11 | #define OPCODE_EXIT 0U |
| 12 | #define OPCODE_MASKWRITE 0U |
| 13 | #define OPCODE_MASKPOLL 1U |
| 14 | #define OPCODE_MASKDELAY 2U |
| 15 | #define OPCODE_WRITE 3U |
| 16 | #define OPCODE_ADDRESS_MASK (~3U) |
| 17 | |
| 18 | /* Sentinel */ |
| 19 | #define EMIT_EXIT() OPCODE_EXIT |
| 20 | /* Opcode is in lower 2 bits of address, address is always 4-byte aligned */ |
| 21 | #define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val |
| 22 | #define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask |
| 23 | #define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask |
| 24 | #define EMIT_WRITE(addr, val) OPCODE_WRITE | addr, val |
| 25 | |
| 26 | /* Returns codes of ps7_init* */ |
| 27 | #define PS7_INIT_SUCCESS (0) |
| 28 | #define PS7_INIT_CORRUPT (1) |
| 29 | #define PS7_INIT_TIMEOUT (2) |
| 30 | #define PS7_POLL_FAILED_DDR_INIT (3) |
| 31 | #define PS7_POLL_FAILED_DMA (4) |
| 32 | #define PS7_POLL_FAILED_PLL (5) |
| 33 | |
| 34 | #define PCW_SILICON_VERSION_1 0 |
| 35 | #define PCW_SILICON_VERSION_2 1 |
| 36 | #define PCW_SILICON_VERSION_3 2 |
| 37 | |
| 38 | /* Called by spl.c */ |
| 39 | int ps7_init(void); |
| 40 | int ps7_post_config(void); |
| 41 | |
| 42 | /* Defined in ps7_init_common.c */ |
| 43 | int ps7_config(unsigned long *ps7_config_init); |
| 44 | |
| 45 | unsigned long ps7GetSiliconVersion(void); |
| 46 | |
| 47 | #endif /* _ASM_ARCH_PS7_INIT_GPL_H */ |
