Googler | 40bc9d0 | 2023-12-15 16:42:49 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] |
| 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People |
| 6 | * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) |
| 7 | * |
| 8 | * Parallel I/O Controller (PIO) - System peripherals registers. |
| 9 | * Based on AT91RM9200 datasheet revision E. |
| 10 | * |
| 11 | * SPDX-License-Identifier: GPL-2.0+ |
| 12 | */ |
| 13 | |
| 14 | #ifndef AT91_PIO_H |
| 15 | #define AT91_PIO_H |
| 16 | |
| 17 | |
| 18 | #define AT91_ASM_PIO_RANGE 0x200 |
| 19 | #define AT91_ASM_PIOC_ASR \ |
| 20 | (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) |
| 21 | #define AT91_ASM_PIOC_BSR \ |
| 22 | (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) |
| 23 | #define AT91_ASM_PIOC_PDR \ |
| 24 | (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) |
| 25 | #define AT91_ASM_PIOC_PUDR \ |
| 26 | (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) |
| 27 | |
| 28 | #define AT91_ASM_PIOD_PDR \ |
| 29 | (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) |
| 30 | #define AT91_ASM_PIOD_PUDR \ |
| 31 | (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) |
| 32 | #define AT91_ASM_PIOD_ASR \ |
| 33 | (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) |
| 34 | |
| 35 | #ifndef __ASSEMBLY__ |
| 36 | |
| 37 | typedef struct at91_port { |
| 38 | u32 per; /* 0x00 PIO Enable Register */ |
| 39 | u32 pdr; /* 0x04 PIO Disable Register */ |
| 40 | u32 psr; /* 0x08 PIO Status Register */ |
| 41 | u32 reserved0; |
| 42 | u32 oer; /* 0x10 Output Enable Register */ |
| 43 | u32 odr; /* 0x14 Output Disable Registerr */ |
| 44 | u32 osr; /* 0x18 Output Status Register */ |
| 45 | u32 reserved1; |
| 46 | u32 ifer; /* 0x20 Input Filter Enable Register */ |
| 47 | u32 ifdr; /* 0x24 Input Filter Disable Register */ |
| 48 | u32 ifsr; /* 0x28 Input Filter Status Register */ |
| 49 | u32 reserved2; |
| 50 | u32 sodr; /* 0x30 Set Output Data Register */ |
| 51 | u32 codr; /* 0x34 Clear Output Data Register */ |
| 52 | u32 odsr; /* 0x38 Output Data Status Register */ |
| 53 | u32 pdsr; /* 0x3C Pin Data Status Register */ |
| 54 | u32 ier; /* 0x40 Interrupt Enable Register */ |
| 55 | u32 idr; /* 0x44 Interrupt Disable Register */ |
| 56 | u32 imr; /* 0x48 Interrupt Mask Register */ |
| 57 | u32 isr; /* 0x4C Interrupt Status Register */ |
| 58 | u32 mder; /* 0x50 Multi-driver Enable Register */ |
| 59 | u32 mddr; /* 0x54 Multi-driver Disable Register */ |
| 60 | u32 mdsr; /* 0x58 Multi-driver Status Register */ |
| 61 | u32 reserved3; |
| 62 | u32 pudr; /* 0x60 Pull-up Disable Register */ |
| 63 | u32 puer; /* 0x64 Pull-up Enable Register */ |
| 64 | u32 pusr; /* 0x68 Pad Pull-up Status Register */ |
| 65 | u32 reserved4; |
| 66 | #if defined(CPU_HAS_PIO3) |
| 67 | u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ |
| 68 | u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ |
| 69 | u32 reserved5[2]; |
| 70 | u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ |
| 71 | u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ |
| 72 | u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ |
| 73 | u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ |
| 74 | u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ |
| 75 | u32 ppder; /* 0x94 Pad Pull-down Enable Register */ |
| 76 | u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ |
| 77 | u32 reserved6; /* */ |
| 78 | #else |
| 79 | u32 asr; /* 0x70 Select A Register */ |
| 80 | u32 bsr; /* 0x74 Select B Register */ |
| 81 | u32 absr; /* 0x78 AB Select Status Register */ |
| 82 | u32 reserved5[9]; /* */ |
| 83 | #endif |
| 84 | u32 ower; /* 0xA0 Output Write Enable Register */ |
| 85 | u32 owdr; /* 0xA4 Output Write Disable Register */ |
| 86 | u32 owsr; /* OxA8 Output Write Status Register */ |
| 87 | #if defined(CPU_HAS_PIO3) |
| 88 | u32 reserved7; /* */ |
| 89 | u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ |
| 90 | u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ |
| 91 | u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */ |
| 92 | u32 reserved8; /* */ |
| 93 | u32 esr; /* 0xC0 Edge Select Register */ |
| 94 | u32 lsr; /* 0xC4 Level Select Register */ |
| 95 | u32 elsr; /* 0xC8 Edge/Level Status Register */ |
| 96 | u32 reserved9; /* 0xCC */ |
| 97 | u32 fellsr; /* 0xD0 Falling /Low Level Select Register */ |
| 98 | u32 rehlsr; /* 0xD4 Rising /High Level Select Register */ |
| 99 | u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ |
| 100 | u32 reserved10; /* */ |
| 101 | u32 locksr; /* 0xE0 Lock Status */ |
| 102 | u32 wpmr; /* 0xE4 Write Protect Mode Register */ |
| 103 | u32 wpsr; /* 0xE8 Write Protect Status Register */ |
| 104 | u32 reserved11[5]; /* */ |
| 105 | u32 schmitt; /* 0x100 Schmitt Trigger Register */ |
| 106 | u32 reserved12[63]; |
| 107 | #else |
| 108 | u32 reserved6[85]; |
| 109 | #endif |
| 110 | } at91_port_t; |
| 111 | |
| 112 | typedef union at91_pio { |
| 113 | struct { |
| 114 | at91_port_t pioa; |
| 115 | at91_port_t piob; |
| 116 | at91_port_t pioc; |
| 117 | #if (ATMEL_PIO_PORTS > 3) |
| 118 | at91_port_t piod; |
| 119 | #endif |
| 120 | #if (ATMEL_PIO_PORTS > 4) |
| 121 | at91_port_t pioe; |
| 122 | #endif |
| 123 | } ; |
| 124 | at91_port_t port[ATMEL_PIO_PORTS]; |
| 125 | } at91_pio_t; |
| 126 | |
| 127 | #ifdef CONFIG_AT91_GPIO |
| 128 | int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); |
| 129 | int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); |
| 130 | #if defined(CPU_HAS_PIO3) |
| 131 | int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); |
| 132 | int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); |
| 133 | int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); |
| 134 | int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); |
| 135 | int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); |
| 136 | #endif |
| 137 | int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); |
| 138 | int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); |
| 139 | int at91_set_pio_output(unsigned port, unsigned pin, int value); |
| 140 | int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup); |
| 141 | int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); |
| 142 | int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); |
| 143 | int at91_set_pio_value(unsigned port, unsigned pin, int value); |
| 144 | int at91_get_pio_value(unsigned port, unsigned pin); |
| 145 | #endif |
| 146 | #endif |
| 147 | |
| 148 | #define AT91_PIO_PORTA 0x0 |
| 149 | #define AT91_PIO_PORTB 0x1 |
| 150 | #define AT91_PIO_PORTC 0x2 |
| 151 | #define AT91_PIO_PORTD 0x3 |
| 152 | #define AT91_PIO_PORTE 0x4 |
| 153 | |
| 154 | #endif |