blob: 3d6ec843df3f156b7961975f6931552c434cb2ad [file] [log] [blame]
Googlere00b8eb2019-07-08 16:37:07 -07001/*
2 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2000
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Googler40bc9d02023-12-15 16:42:49 +08008 *
9 * SPDX-License-Identifier: GPL-2.0+
Googlere00b8eb2019-07-08 16:37:07 -070010 */
11
12#include <config.h>
13#include <common.h>
14#include <watchdog.h>
15#include <command.h>
16#include <fsl_esdhc.h>
17#include <asm/cache.h>
18#include <asm/io.h>
19#include <asm/mmu.h>
20#include <fsl_ifc.h>
21#include <asm/fsl_law.h>
22#include <asm/fsl_lbc.h>
23#include <post.h>
24#include <asm/processor.h>
25#include <fsl_ddr_sdram.h>
Googlere00b8eb2019-07-08 16:37:07 -070026
27DECLARE_GLOBAL_DATA_PTR;
28
29/*
30 * Default board reset function
31 */
32static void
33__board_reset(void)
34{
35 /* Do nothing */
36}
37void board_reset(void) __attribute__((weak, alias("__board_reset")));
38
39int checkcpu (void)
40{
41 sys_info_t sysinfo;
42 uint pvr, svr;
43 uint ver;
44 uint major, minor;
45 struct cpu_type *cpu;
46 char buf1[32], buf2[32];
47#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
48 ccsr_gur_t __iomem *gur =
49 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50#endif
51
52 /*
53 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
54 * mode. Previous platform use ddr ratio to do the same. This
55 * information is only for display here.
56 */
57#ifdef CONFIG_FSL_CORENET
58#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
59 u32 ddr_sync = 0; /* only async mode is supported */
60#else
61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
62 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
63#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
64#else /* CONFIG_FSL_CORENET */
65#ifdef CONFIG_DDR_CLK_FREQ
66 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
67 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
68#else
69 u32 ddr_ratio = 0;
70#endif /* CONFIG_DDR_CLK_FREQ */
71#endif /* CONFIG_FSL_CORENET */
72
73 unsigned int i, core, nr_cores = cpu_numcores();
74 u32 mask = cpu_mask();
75
Googlere00b8eb2019-07-08 16:37:07 -070076 svr = get_svr();
77 major = SVR_MAJ(svr);
78 minor = SVR_MIN(svr);
79
80#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
81 if (SVR_SOC_VER(svr) == SVR_T4080) {
82 ccsr_rcpm_t *rcpm =
83 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
84
85 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
86 FSL_CORENET_DEVDISR2_DTSEC1_9);
87 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
88 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
89
90 /* It needs SW to disable core4~7 as HW design sake on T4080 */
91 for (i = 4; i < 8; i++)
92 cpu_disable(i);
93
94 /* request core4~7 into PH20 state, prior to entering PCL10
95 * state, all cores in cluster should be placed in PH20 state.
96 */
97 setbits_be32(&rcpm->pcph20setr, 0xf0);
98
99 /* put the 2nd cluster into PCL10 state */
100 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
101 }
102#endif
103
104 if (cpu_numcores() > 1) {
105#ifndef CONFIG_MP
106 puts("Unicore software on multiprocessor system!!\n"
107 "To enable mutlticore build define CONFIG_MP\n");
108#endif
109 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
110 printf("CPU%d: ", pic->whoami);
111 } else {
112 puts("CPU: ");
113 }
114
115 cpu = gd->arch.cpu;
116
117 puts(cpu->name);
118 if (IS_E_PROCESSOR(svr))
119 puts("E");
120
121 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
122
123 pvr = get_pvr();
124 ver = PVR_VER(pvr);
125 major = PVR_MAJ(pvr);
126 minor = PVR_MIN(pvr);
127
128 printf("Core: ");
129 switch(ver) {
130 case PVR_VER_E500_V1:
131 case PVR_VER_E500_V2:
132 puts("e500");
133 break;
134 case PVR_VER_E500MC:
135 puts("e500mc");
136 break;
137 case PVR_VER_E5500:
138 puts("e5500");
139 break;
140 case PVR_VER_E6500:
141 puts("e6500");
142 break;
143 default:
144 puts("Unknown");
145 break;
146 }
147
148 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
149
150 if (nr_cores > CONFIG_MAX_CPUS) {
151 panic("\nUnexpected number of cores: %d, max is %d\n",
152 nr_cores, CONFIG_MAX_CPUS);
153 }
154
155 get_sys_info(&sysinfo);
156
157#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
158 if (sysinfo.diff_sysclk == 1)
159 puts("Single Source Clock Configuration\n");
160#endif
161
162 puts("Clock Configuration:");
163 for_each_cpu(i, core, nr_cores, mask) {
164 if (!(i & 3))
165 printf ("\n ");
166 printf("CPU%d:%-4s MHz, ", core,
167 strmhz(buf1, sysinfo.freq_processor[core]));
168 }
Googlere00b8eb2019-07-08 16:37:07 -0700169 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
170 printf("\n");
171
172#ifdef CONFIG_FSL_CORENET
173 if (ddr_sync == 1) {
174 printf(" DDR:%-4s MHz (%s MT/s data rate) "
175 "(Synchronous), ",
176 strmhz(buf1, sysinfo.freq_ddrbus/2),
177 strmhz(buf2, sysinfo.freq_ddrbus));
178 } else {
179 printf(" DDR:%-4s MHz (%s MT/s data rate) "
180 "(Asynchronous), ",
181 strmhz(buf1, sysinfo.freq_ddrbus/2),
182 strmhz(buf2, sysinfo.freq_ddrbus));
183 }
184#else
185 switch (ddr_ratio) {
186 case 0x0:
187 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
188 strmhz(buf1, sysinfo.freq_ddrbus/2),
189 strmhz(buf2, sysinfo.freq_ddrbus));
190 break;
191 case 0x7:
192 printf(" DDR:%-4s MHz (%s MT/s data rate) "
193 "(Synchronous), ",
194 strmhz(buf1, sysinfo.freq_ddrbus/2),
195 strmhz(buf2, sysinfo.freq_ddrbus));
196 break;
197 default:
198 printf(" DDR:%-4s MHz (%s MT/s data rate) "
199 "(Asynchronous), ",
200 strmhz(buf1, sysinfo.freq_ddrbus/2),
201 strmhz(buf2, sysinfo.freq_ddrbus));
202 break;
203 }
204#endif
205
206#if defined(CONFIG_FSL_LBC)
207 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
208 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
209 } else {
210 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
211 sysinfo.freq_localbus);
212 }
213#endif
214
215#if defined(CONFIG_FSL_IFC)
216 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
217#endif
218
219#ifdef CONFIG_CPM2
220 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
221#endif
222
223#ifdef CONFIG_QE
224 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
225#endif
226
Googlere00b8eb2019-07-08 16:37:07 -0700227#ifdef CONFIG_SYS_DPAA_FMAN
228 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
229 printf(" FMAN%d: %s MHz\n", i + 1,
230 strmhz(buf1, sysinfo.freq_fman[i]));
231 }
232#endif
233
234#ifdef CONFIG_SYS_DPAA_QBMAN
235 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
236#endif
237
238#ifdef CONFIG_SYS_DPAA_PME
239 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
240#endif
241
242 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
243
244#ifdef CONFIG_FSL_CORENET
245 /* Display the RCW, so that no one gets confused as to what RCW
246 * we're actually using for this boot.
247 */
248 puts("Reset Configuration Word (RCW):");
249 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
250 u32 rcw = in_be32(&gur->rcwsr[i]);
251
252 if ((i % 4) == 0)
253 printf("\n %08x:", i * 4);
254 printf(" %08x", rcw);
255 }
256 puts("\n");
257#endif
258
259 return 0;
260}
261
262
263/* ------------------------------------------------------------------------- */
264
265int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
266{
267/* Everything after the first generation of PQ3 parts has RSTCR */
Googler40bc9d02023-12-15 16:42:49 +0800268#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
269 defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
Googlere00b8eb2019-07-08 16:37:07 -0700270 unsigned long val, msr;
271
272 /*
273 * Initiate hard reset in debug control register DBCR0
274 * Make sure MSR[DE] = 1. This only resets the core.
275 */
276 msr = mfmsr ();
277 msr |= MSR_DE;
278 mtmsr (msr);
279
280 val = mfspr(DBCR0);
281 val |= 0x70000000;
282 mtspr(DBCR0,val);
283#else
284 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
285
286 /* Attempt board-specific reset */
287 board_reset();
288
289 /* Next try asserting HRESET_REQ */
290 out_be32(&gur->rstcr, 0x2);
291 udelay(100);
292#endif
293
294 return 1;
295}
296
297
298/*
299 * Get timebase clock frequency
300 */
301#ifndef CONFIG_SYS_FSL_TBCLK_DIV
302#define CONFIG_SYS_FSL_TBCLK_DIV 8
303#endif
304__weak unsigned long get_tbclk (void)
305{
306 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
307
308 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
309}
310
311
312#if defined(CONFIG_WATCHDOG)
313#define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
314void
315init_85xx_watchdog(void)
316{
317 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
318 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
319}
320
321void
322reset_85xx_watchdog(void)
323{
324 /*
325 * Clear TSR(WIS) bit by writing 1
326 */
327 mtspr(SPRN_TSR, TSR_WIS);
328}
329
330void
331watchdog_reset(void)
332{
333 int re_enable = disable_interrupts();
334
335 reset_85xx_watchdog();
336 if (re_enable)
337 enable_interrupts();
338}
339#endif /* CONFIG_WATCHDOG */
340
341/*
342 * Initializes on-chip MMC controllers.
343 * to override, implement board_mmc_init()
344 */
345int cpu_mmc_init(bd_t *bis)
346{
347#ifdef CONFIG_FSL_ESDHC
348 return fsl_esdhc_mmc_init(bis);
349#else
350 return 0;
351#endif
352}
353
354/*
355 * Print out the state of various machine registers.
356 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
357 * parameters for IFC and TLBs
358 */
Googler40bc9d02023-12-15 16:42:49 +0800359void mpc85xx_reginfo(void)
Googlere00b8eb2019-07-08 16:37:07 -0700360{
361 print_tlbcam();
362 print_laws();
363#if defined(CONFIG_FSL_LBC)
364 print_lbc_regs();
365#endif
366#ifdef CONFIG_FSL_IFC
367 print_ifc_regs();
368#endif
369
370}
371
372/* Common ddr init for non-corenet fsl 85xx platforms */
373#ifndef CONFIG_FSL_CORENET
374#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
375 !defined(CONFIG_SYS_INIT_L2_ADDR)
Googler40bc9d02023-12-15 16:42:49 +0800376phys_size_t initdram(int board_type)
Googlere00b8eb2019-07-08 16:37:07 -0700377{
378#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
Googler40bc9d02023-12-15 16:42:49 +0800379 defined(CONFIG_QEMU_E500)
380 return fsl_ddr_sdram_size();
Googlere00b8eb2019-07-08 16:37:07 -0700381#else
Googler40bc9d02023-12-15 16:42:49 +0800382 return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Googlere00b8eb2019-07-08 16:37:07 -0700383#endif
Googlere00b8eb2019-07-08 16:37:07 -0700384}
385#else /* CONFIG_SYS_RAMBOOT */
Googler40bc9d02023-12-15 16:42:49 +0800386phys_size_t initdram(int board_type)
Googlere00b8eb2019-07-08 16:37:07 -0700387{
388 phys_size_t dram_size = 0;
389
390#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
391 {
392 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
393 unsigned int x = 10;
394 unsigned int i;
395
396 /*
397 * Work around to stabilize DDR DLL
398 */
399 out_be32(&gur->ddrdllcr, 0x81000000);
400 asm("sync;isync;msync");
401 udelay(200);
402 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
403 setbits_be32(&gur->devdisr, 0x00010000);
404 for (i = 0; i < x; i++)
405 ;
406 clrbits_be32(&gur->devdisr, 0x00010000);
407 x++;
408 }
409 }
410#endif
411
412#if defined(CONFIG_SPD_EEPROM) || \
413 defined(CONFIG_DDR_SPD) || \
414 defined(CONFIG_SYS_DDR_RAW_TIMING)
415 dram_size = fsl_ddr_sdram();
416#else
417 dram_size = fixed_sdram();
418#endif
419 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
420 dram_size *= 0x100000;
421
422#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
423 /*
424 * Initialize and enable DDR ECC.
425 */
426 ddr_enable_ecc(dram_size);
427#endif
428
429#if defined(CONFIG_FSL_LBC)
430 /* Some boards also have sdram on the lbc */
431 lbc_sdram_init();
432#endif
433
434 debug("DDR: ");
Googler40bc9d02023-12-15 16:42:49 +0800435 return dram_size;
Googlere00b8eb2019-07-08 16:37:07 -0700436}
437#endif /* CONFIG_SYS_RAMBOOT */
438#endif
439
440#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
441
442/* Board-specific functions defined in each board's ddr.c */
443void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
444 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
445void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
446 phys_addr_t *rpn);
447unsigned int
448 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
449
450void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
451
452static void dump_spd_ddr_reg(void)
453{
454 int i, j, k, m;
455 u8 *p_8;
456 u32 *p_32;
Googler40bc9d02023-12-15 16:42:49 +0800457 struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS];
Googlere00b8eb2019-07-08 16:37:07 -0700458 generic_spd_eeprom_t
Googler40bc9d02023-12-15 16:42:49 +0800459 spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
Googlere00b8eb2019-07-08 16:37:07 -0700460
Googler40bc9d02023-12-15 16:42:49 +0800461 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
Googlere00b8eb2019-07-08 16:37:07 -0700462 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
463
Googler40bc9d02023-12-15 16:42:49 +0800464 puts("SPD data of all dimms (zero vaule is omitted)...\n");
Googlere00b8eb2019-07-08 16:37:07 -0700465 puts("Byte (hex) ");
466 k = 1;
Googler40bc9d02023-12-15 16:42:49 +0800467 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
Googlere00b8eb2019-07-08 16:37:07 -0700468 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
469 printf("Dimm%d ", k++);
470 }
471 puts("\n");
472 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
473 m = 0;
474 printf("%3d (0x%02x) ", k, k);
Googler40bc9d02023-12-15 16:42:49 +0800475 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
Googlere00b8eb2019-07-08 16:37:07 -0700476 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
477 p_8 = (u8 *) &spd[i][j];
478 if (p_8[k]) {
479 printf("0x%02x ", p_8[k]);
480 m++;
481 } else
482 puts(" ");
483 }
484 }
485 if (m)
486 puts("\n");
487 else
488 puts("\r");
489 }
490
Googler40bc9d02023-12-15 16:42:49 +0800491 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
Googlere00b8eb2019-07-08 16:37:07 -0700492 switch (i) {
493 case 0:
494 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
495 break;
Googler40bc9d02023-12-15 16:42:49 +0800496#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
Googlere00b8eb2019-07-08 16:37:07 -0700497 case 1:
498 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
499 break;
500#endif
Googler40bc9d02023-12-15 16:42:49 +0800501#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
Googlere00b8eb2019-07-08 16:37:07 -0700502 case 2:
503 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
504 break;
505#endif
Googler40bc9d02023-12-15 16:42:49 +0800506#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
Googlere00b8eb2019-07-08 16:37:07 -0700507 case 3:
508 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
509 break;
510#endif
511 default:
512 printf("%s unexpected controller number = %u\n",
513 __func__, i);
514 return;
515 }
516 }
517 printf("DDR registers dump for all controllers "
Googler40bc9d02023-12-15 16:42:49 +0800518 "(zero vaule is omitted)...\n");
Googlere00b8eb2019-07-08 16:37:07 -0700519 puts("Offset (hex) ");
Googler40bc9d02023-12-15 16:42:49 +0800520 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
Googlere00b8eb2019-07-08 16:37:07 -0700521 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
522 puts("\n");
523 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
524 m = 0;
525 printf("%6d (0x%04x)", k * 4, k * 4);
Googler40bc9d02023-12-15 16:42:49 +0800526 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
Googlere00b8eb2019-07-08 16:37:07 -0700527 p_32 = (u32 *) ddr[i];
528 if (p_32[k]) {
529 printf(" 0x%08x", p_32[k]);
530 m++;
531 } else
532 puts(" ");
533 }
534 if (m)
535 puts("\n");
536 else
537 puts("\r");
538 }
539 puts("\n");
540}
541
542/* invalid the TLBs for DDR and setup new ones to cover p_addr */
543static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
544{
545 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
546 unsigned long epn;
547 u32 tsize, valid, ptr;
548 int ddr_esel;
549
550 clear_ddr_tlbs_phys(p_addr, size>>20);
551
552 /* Setup new tlb to cover the physical address */
553 setup_ddr_tlbs_phys(p_addr, size>>20);
554
555 ptr = vstart;
556 ddr_esel = find_tlb_idx((void *)ptr, 1);
557 if (ddr_esel != -1) {
558 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
559 } else {
560 printf("TLB error in function %s\n", __func__);
561 return -1;
562 }
563
564 return 0;
565}
566
567/*
568 * slide the testing window up to test another area
569 * for 32_bit system, the maximum testable memory is limited to
570 * CONFIG_MAX_MEM_MAPPED
571 */
572int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
573{
574 phys_addr_t test_cap, p_addr;
575 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
576
577#if !defined(CONFIG_PHYS_64BIT) || \
578 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
579 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
580 test_cap = p_size;
581#else
582 test_cap = gd->ram_size;
583#endif
584 p_addr = (*vstart) + (*size) + (*phys_offset);
585 if (p_addr < test_cap - 1) {
586 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
587 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
588 return -1;
589 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
590 *size = (u32) p_size;
591 printf("Testing 0x%08llx - 0x%08llx\n",
592 (u64)(*vstart) + (*phys_offset),
593 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
594 } else
595 return 1;
596
597 return 0;
598}
599
600/* initialization for testing area */
601int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
602{
603 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
604
605 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
606 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
607 *phys_offset = 0;
608
609#if !defined(CONFIG_PHYS_64BIT) || \
610 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
611 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
612 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
613 puts("Cannot test more than ");
614 print_size(CONFIG_MAX_MEM_MAPPED,
615 " without proper 36BIT support.\n");
616 }
617#endif
618 printf("Testing 0x%08llx - 0x%08llx\n",
619 (u64)(*vstart) + (*phys_offset),
620 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
621
622 return 0;
623}
624
625/* invalid TLBs for DDR and remap as normal after testing */
626int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
627{
628 unsigned long epn;
629 u32 tsize, valid, ptr;
630 phys_addr_t rpn = 0;
631 int ddr_esel;
632
633 /* disable the TLBs for this testing */
634 ptr = *vstart;
635
636 while (ptr < (*vstart) + (*size)) {
637 ddr_esel = find_tlb_idx((void *)ptr, 1);
638 if (ddr_esel != -1) {
639 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
640 disable_tlb(ddr_esel);
641 }
642 ptr += TSIZE_TO_BYTES(tsize);
643 }
644
645 puts("Remap DDR ");
646 setup_ddr_tlbs(gd->ram_size>>20);
647 puts("\n");
648
649 return 0;
650}
651
652void arch_memory_failure_handle(void)
653{
654 dump_spd_ddr_reg();
655}
656#endif