| Googler | 3cec7d7 | 2023-12-13 10:05:01 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: Intel */ |
| 2 | /* |
| 3 | * Copyright (C) 2013, Intel Corporation |
| 4 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef _FSP_HEADER_H_ |
| 8 | #define _FSP_HEADER_H_ |
| 9 | |
| 10 | #define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */ |
| 11 | |
| 12 | struct __packed fsp_header { |
| 13 | u32 sign; /* 'FSPH' */ |
| 14 | u32 hdr_len; /* header length */ |
| 15 | u8 reserved1[3]; |
| 16 | u8 hdr_rev; /* header rev */ |
| 17 | u32 img_rev; /* image rev */ |
| 18 | char img_id[8]; /* signature string */ |
| 19 | u32 img_size; /* image size */ |
| 20 | u32 img_base; /* image base */ |
| 21 | u32 img_attr; /* image attribute */ |
| 22 | u32 cfg_region_off; /* configuration region offset */ |
| 23 | u32 cfg_region_size; /* configuration region size */ |
| 24 | u32 api_num; /* number of API entries */ |
| 25 | u32 fsp_tempram_init; /* tempram_init offset */ |
| 26 | u32 fsp_init; /* fsp_init offset */ |
| 27 | u32 fsp_notify; /* fsp_notify offset */ |
| 28 | u32 fsp_mem_init; /* fsp_mem_init offset */ |
| 29 | u32 fsp_tempram_exit; /* fsp_tempram_exit offset */ |
| 30 | u32 fsp_silicon_init; /* fsp_silicon_init offset */ |
| 31 | }; |
| 32 | |
| 33 | #define FSP_HEADER_REVISION_1 1 |
| 34 | #define FSP_HEADER_REVISION_2 2 |
| 35 | |
| 36 | #define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0) |
| 37 | |
| 38 | #endif |
