blob: 263f92e44393ca3d22abbf7eec044a6cc4590aaa [file] [log] [blame]
Googler54c966a2024-11-22 15:02:52 +08001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include "platform.h"
7#include <amlogic/cpu_id.h>
8#include <asm/arch/secure_apb.h>
9#include <asm/arch/usb.h>
10
Googler63dd2272024-10-23 19:29:29 +080011#ifndef CONFIG_USB_GADGET_CRG
Googler54c966a2024-11-22 15:02:52 +080012void dwc_write_reg32(unsigned int x, unsigned int v)
13{
14 unsigned int addr;
15
16 addr = usb_get_dwc_a_base_addr();
17 (*(volatile uint32_t *)(unsigned long)(x + addr))=v;
18}
19unsigned int dwc_read_reg32(unsigned int x)
20{
21 unsigned int addr;
22
23 addr = usb_get_dwc_a_base_addr();
24 return (*(volatile uint32_t*)((unsigned long)(x + addr)));
25}
26
27void dwc_modify_reg32(unsigned int x, unsigned int c, unsigned int s)
28{
29 unsigned int addr;
30
31 addr = usb_get_dwc_a_base_addr();
32 (*(volatile uint32_t *)(unsigned long)(x + addr)) =
33 ( ((dwc_read_reg32(x)) & (~c)) | (s));
34}
35
36void set_usb_phy21_tuning_update(void)
37{
38 unsigned long phy_reg_base = usb_get_device_mode_phy_base();
39
40 if (phy_reg_base == 0)
41 return;
42 usb2_phy_tuning(phy_reg_base, 1);
43 return;
44}
45
46void set_usb_phy21_tuning_update_reset(void)
47{
48 usb_phy_tuning_reset();
49}
50
51
52void set_usb_phy_config(int cfg)
53{
54 usb_device_mode_init();
55}
56
57//sleep sometime before and after disconnect,
58// to let usb_burning_tool.exe detect both fast plug-out and plug-in
59extern void dwc_otg_pullup(int is_on);
60void close_usb_phy_clock(int cfg)
61{
62 cfg = cfg;//avoid compiler warning
63
64 run_command("sleep 1", 0);//improve pc compatibility!!
65 dwc_otg_pullup(0);//disconnect
66 __udelay(20);
67 /*dwc_otg_power_off_phy();*///Don't call this as it may cause pull-down failed!!!!
68 run_command("sleep 1", 0);
69
70 return;
71}
Googler63dd2272024-10-23 19:29:29 +080072#endif