blob: 733a7d73a9399d9cf0e0bc9fe3d6715b70643f74 [file] [log] [blame]
Googler695f9d92023-09-11 15:38:29 +08001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * arch/arm/include/asm/arch-tm2/ddr.h
4 *
5 * Copyright (C) 2020 Amlogic, Inc. All rights reserved.
6 *
7 */
8
9#include <config.h>
10#include <io.h>
11#include <stdint.h>
12#include <asm/arch/ddr_define.h>
13
14/* io defines */
15//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data)
16//#define rd_reg(addr) (*((volatile uint32_t *)(addr)))
17#define wr_reg(addr, data) writel(data, addr)
18#define rd_reg(addr) readl(addr)
19/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/
20#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value)))
21#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc)));
22#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc)));
23#define wait_equal(addr, data) do{}while(data != (rd_reg(addr)));
24
25/* function defines */
26unsigned int ddr_init(void);
27unsigned int ddr_init_pll(void);
28unsigned int ddr_init_dmc(void);
29unsigned int ddr_init_pctl(void);
30unsigned int hot_boot(void);
31void ddr_print_info(void);
32void ddr_test(void);
33void ddr_pre_init(void);
34void ddr_debug(void);
35
36/* pctl status */
37#define UPCTL_STAT_MASK (7)
38#define UPCTL_STAT_INIT (0)
39#define UPCTL_STAT_CONFIG (1)
40#define UPCTL_STAT_ACCESS (3)
41#define UPCTL_STAT_LOW_POWER (5)
42
43/* pctl cmds */
44#define UPCTL_CMD_INIT (0)
45#define UPCTL_CMD_CONFIG (1)
46#define UPCTL_CMD_GO (2)
47#define UPCTL_CMD_SLEEP (3)
48#define UPCTL_CMD_WAKEUP (4)
49
50/* PUB PIR setting */
51#define PUB_PIR_INIT (1<<0)
52#define PUB_PIR_ZCAL (1<<1)
53#define PUB_PIR_CA (1<<2)
54#define PUB_PIR_PLLINIT (1<<4)
55#define PUB_PIR_DCAL (1<<5)
56#define PUB_PIR_PHYRST (1<<6)
57#define PUB_PIR_DRAMRST (1<<7)
58#define PUB_PIR_DRAMINIT (1<<8)
59#define PUB_PIR_WL (1<<9)
60#define PUB_PIR_QSGATE (1<<10)
61#define PUB_PIR_WLADJ (1<<11)
62#define PUB_PIR_RDDSKW (1<<12)
63#define PUB_PIR_WRDSKW (1<<13)
64#define PUB_PIR_RDEYE (1<<14)
65#define PUB_PIR_WREYE (1<<15)
66#define PUB_PIR_ICPC (1<<16)
67#define PUB_PIR_PLLBYP (1<<17)
68#define PUB_PIR_CTLDINIT (1<<18)
69#define PUB_PIR_RDIMMINIT (1<<19)
70#define PUB_PIR_CLRSR (1<<27)
71#define PUB_PIR_LOCKBYP (1<<28)
72#define PUB_PIR_DCALBYP (1<<29)
73#define PUB_PIR_ZCALBYP (1<<30)
74#define PUB_PIR_INITBYP (1<<31)
75
76/* PHY initialize register (PIR) */
77#define DDR_PIR ((PUB_PIR_ZCAL) |\
78 (PUB_PIR_PLLINIT) |\
79 (PUB_PIR_DCAL) |\
80 (PUB_PIR_PHYRST) |\
81 (PUB_PIR_DRAMRST) |\
82 (PUB_PIR_DRAMINIT) |\
83 (PUB_PIR_WL) |\
84 (PUB_PIR_QSGATE) |\
85 (PUB_PIR_WLADJ) |\
86 (PUB_PIR_RDDSKW) |\
87 (PUB_PIR_WRDSKW) |\
88 (PUB_PIR_RDEYE) |\
89 (PUB_PIR_WREYE) \
90 )
91
92/* PHY general status register (PGSR0) */
93#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
94#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \
95 (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff))
96#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
97#define DDR_PGSR0_CHECK()
98#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
99#define DDR_PGSR0_CHECK()
100#endif
101
102/* other regs */
103#define SCRATCH0 0xC1107D3C