| Googler | e00b8eb | 2019-07-08 16:37:07 -0700 | [diff] [blame] | 1 | /* |
| 2 | * modified from SH-IPL+g (init-r0p751rlc0011rl.S) |
| 3 | * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz) |
| 4 | * Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| 5 | */ |
| 6 | |
| 7 | #include <config.h> |
| Googler | 695f9d9 | 2023-09-11 15:38:29 +0800 | [diff] [blame^] | 8 | #include <version.h> |
| Googler | e00b8eb | 2019-07-08 16:37:07 -0700 | [diff] [blame] | 9 | |
| 10 | #include <asm/processor.h> |
| 11 | #include <asm/macro.h> |
| 12 | |
| 13 | .global lowlevel_init |
| 14 | .text |
| 15 | .align 2 |
| 16 | |
| 17 | lowlevel_init: |
| 18 | |
| 19 | write32 CCR_A, CCR_D_D |
| 20 | |
| 21 | write32 MMUCR_A, MMUCR_D |
| 22 | |
| 23 | write32 BCR1_A, BCR1_D |
| 24 | |
| 25 | write16 BCR2_A, BCR2_D |
| 26 | |
| 27 | write16 BCR3_A, BCR3_D |
| 28 | |
| 29 | write32 BCR4_A, BCR4_D |
| 30 | |
| 31 | write32 WCR1_A, WCR1_D |
| 32 | |
| 33 | write32 WCR2_A, WCR2_D |
| 34 | |
| 35 | write32 WCR3_A, WCR3_D |
| 36 | |
| 37 | write16 PCR_A, PCR_D |
| 38 | |
| 39 | write16 LED_A, LED_D |
| 40 | |
| 41 | write32 MCR_A, MCR_D1 |
| 42 | |
| 43 | write16 RTCNT_A, RTCNT_D |
| 44 | |
| 45 | write16 RTCOR_A, RTCOR_D |
| 46 | |
| 47 | write16 RFCR_A, RFCR_D |
| 48 | |
| 49 | write16 RTCSR_A, RTCSR_D |
| 50 | |
| 51 | write8 SDMR3_A, SDMR3_D0 |
| 52 | |
| 53 | /* Wait DRAM refresh 30 times */ |
| 54 | mov.l RFCR_A, r1 |
| 55 | mov #30, r3 |
| 56 | 1: |
| 57 | mov.w @r1, r0 |
| 58 | extu.w r0, r2 |
| 59 | cmp/hi r3, r2 |
| 60 | bf 1b |
| 61 | |
| 62 | write32 MCR_A, MCR_D2 |
| 63 | |
| 64 | write8 SDMR3_A, SDMR3_D1 |
| 65 | |
| 66 | write32 IRLMASK_A, IRLMASK_D |
| 67 | |
| 68 | write32 CCR_A, CCR_D_E |
| 69 | |
| 70 | rts |
| 71 | nop |
| 72 | |
| 73 | .align 2 |
| 74 | CCR_A: .long CCR /* Cache Control Register */ |
| 75 | CCR_D_D: .long 0x0808 /* Flush the cache, disable */ |
| 76 | CCR_D_E: .long 0x8000090B |
| 77 | |
| 78 | FRQCR_A: .long FRQCR /* FRQCR Address */ |
| 79 | FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ |
| 80 | BCR1_A: .long BCR1 /* BCR1 Address */ |
| 81 | BCR1_D: .long 0x00180008 |
| 82 | BCR2_A: .long BCR2 /* BCR2 Address */ |
| 83 | BCR2_D: .long 0xabe8 |
| 84 | BCR3_A: .long BCR3 /* BCR3 Address */ |
| 85 | BCR3_D: .long 0x0000 |
| 86 | BCR4_A: .long BCR4 /* BCR4 Address */ |
| 87 | BCR4_D: .long 0x00000010 |
| 88 | WCR1_A: .long WCR1 /* WCR1 Address */ |
| 89 | WCR1_D: .long 0x33343333 |
| 90 | WCR2_A: .long WCR2 /* WCR2 Address */ |
| 91 | WCR2_D: .long 0xcff86fbf |
| 92 | WCR3_A: .long WCR3 /* WCR3 Address */ |
| 93 | WCR3_D: .long 0x07777707 |
| 94 | LED_A: .long 0x04000036 /* LED Address */ |
| 95 | LED_D: .long 0xFF /* LED Data */ |
| 96 | RTCNT_A: .long RTCNT /* RTCNT Address */ |
| 97 | RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ |
| 98 | .align 2 |
| 99 | RTCOR_A: .long RTCOR /* RTCOR Address */ |
| 100 | RTCOR_D: .word 0xA534 /* RTCOR Write Code */ |
| 101 | .align 2 |
| 102 | RTCSR_A: .long RTCSR /* RTCSR Address */ |
| 103 | RTCSR_D: .word 0xA510 /* RTCSR Write Code */ |
| 104 | .align 2 |
| 105 | SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ |
| 106 | SDMR3_D0: .long 0x55 |
| 107 | SDMR3_D1: .long 0x00 |
| 108 | MCR_A: .long MCR /* MCR Address */ |
| 109 | MCR_D1: .long 0x081901F4 /* MRSET:'0' */ |
| 110 | MCR_D2: .long 0x481901F4 /* MRSET:'1' */ |
| 111 | RFCR_A: .long RFCR /* RFCR Address */ |
| 112 | RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ |
| 113 | PCR_A: .long PCR /* PCR Address */ |
| 114 | PCR_D: .long 0x0000 |
| 115 | MMUCR_A: .long MMUCR /* MMUCCR Address */ |
| 116 | MMUCR_D: .long 0x00000000 /* MMUCCR Data */ |
| 117 | IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */ |
| 118 | IRLMASK_D: .long 0x00000000 /* IRLMASK Data */ |
