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Googlere00b8eb2019-07-08 16:37:07 -07001/*
2 * Embest/Timll DevKit3250 board support
3 *
Googler695f9d92023-09-11 15:38:29 +08004 * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
Googlere00b8eb2019-07-08 16:37:07 -07007 */
8
9#include <common.h>
10#include <asm/arch/sys_proto.h>
Googlere00b8eb2019-07-08 16:37:07 -070011#include <asm/arch/cpu.h>
12#include <asm/arch/emc.h>
Googlere00b8eb2019-07-08 16:37:07 -070013
14DECLARE_GLOBAL_DATA_PTR;
15
16static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
Googlere00b8eb2019-07-08 16:37:07 -070017
18int board_early_init_f(void)
19{
20 lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
Googlere00b8eb2019-07-08 16:37:07 -070021
22 return 0;
23}
24
25int board_init(void)
26{
27 /* adress of boot parameters */
28 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
29
30#ifdef CONFIG_SYS_FLASH_CFI
31 /* Use 16-bit memory interface for NOR Flash */
32 emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
33
34 /* Change the NOR timings to optimum value to get maximum bandwidth */
35 emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
Googler695f9d92023-09-11 15:38:29 +080036 emc->stat[0].waitoen = EMC_STAT_WAITOEN(1);
Googlere00b8eb2019-07-08 16:37:07 -070037 emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
38 emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
39 emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
40 emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
41#endif
42
43 return 0;
44}
45
46int dram_init(void)
47{
48 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
49 CONFIG_SYS_SDRAM_SIZE);
50
51 return 0;
52}