blob: 291c249c86b64139a4696e16657011e018d22387 [file] [log] [blame]
Googlere00b8eb2019-07-08 16:37:07 -07001/*
Googler695f9d92023-09-11 15:38:29 +08002 * Copyright 2014 Freescale Semiconductor, Inc.
Googlere00b8eb2019-07-08 16:37:07 -07003 * Layerscape PCIe driver
Googler695f9d92023-09-11 15:38:29 +08004 *
5 * SPDX-License-Identifier: GPL-2.0+
Googlere00b8eb2019-07-08 16:37:07 -07006 */
7
8#include <common.h>
9#include <asm/arch/fsl_serdes.h>
10#include <pci.h>
11#include <asm/io.h>
Googler695f9d92023-09-11 15:38:29 +080012#include <asm/pcie_layerscape.h>
13
14#ifdef CONFIG_OF_BOARD_SETUP
15#include <libfdt.h>
16#include <fdt_support.h>
17
18static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
19 unsigned long ctrl_addr, enum srds_prtcl dev)
20{
21 int off;
22
23 off = fdt_node_offset_by_compat_reg(blob, pci_compat,
24 (phys_addr_t)ctrl_addr);
25 if (off < 0)
26 return;
27
28 if (!is_serdes_configured(dev))
29 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
30}
31
32void ft_pcie_setup(void *blob, bd_t *bd)
33{
34 #ifdef CONFIG_PCIE1
35 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
36 #endif
37
38 #ifdef CONFIG_PCIE2
39 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
40 #endif
41}
42
43#else
44void ft_pcie_setup(void *blob, bd_t *bd)
45{
46}
Googler25e92cf2023-12-13 10:05:01 +000047#endif
Googler40bc9d02023-12-15 16:42:49 +080048
Googler695f9d92023-09-11 15:38:29 +080049void pci_init_board(void)
Googler40bc9d02023-12-15 16:42:49 +080050{
Googler25e92cf2023-12-13 10:05:01 +000051}