blob: bdd1341d328ef90332b5d321a450e892be036073 [file] [log] [blame]
Googlera8fd56b2024-10-24 14:04:51 +08001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * board/amlogic/gxm_skt_v1/firmware/power.c
4 *
5 * Copyright (C) 2020 Amlogic, Inc. All rights reserved.
6 *
7 */
8
9#include "config.h"
10#include <serial.h>
11/* #include <stdio.h> */
12
13#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
14
15static int pwm_voltage_table[][2] = {
16 { 0x1c0000, 860},
17 { 0x1b0001, 870},
18 { 0x1a0002, 880},
19 { 0x190003, 890},
20 { 0x180004, 900},
21 { 0x170005, 910},
22 { 0x160006, 920},
23 { 0x150007, 930},
24 { 0x140008, 940},
25 { 0x130009, 950},
26 { 0x12000a, 960},
27 { 0x11000b, 970},
28 { 0x10000c, 980},
29 { 0x0f000d, 990},
30 { 0x0e000e, 1000},
31 { 0x0d000f, 1010},
32 { 0x0c0010, 1020},
33 { 0x0b0011, 1030},
34 { 0x0a0012, 1040},
35 { 0x090013, 1050},
36 { 0x080014, 1060},
37 { 0x070015, 1070},
38 { 0x060016, 1080},
39 { 0x050017, 1090},
40 { 0x040018, 1100},
41 { 0x030019, 1110},
42 { 0x02001a, 1120},
43 { 0x01001b, 1130},
44 { 0x00001c, 1140}
45};
46#define P_PIN_MUX_REG1 (*((volatile unsigned *)(0xda834400 + (0x2d << 2))))
47#define P_PIN_MUX_REG2 (*((volatile unsigned *)(0xda834400 + (0x2e << 2))))
48#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xda834400 + (0x2f << 2))))
49#define P_PIN_MUX_REG7 (*((volatile unsigned *)(0xda834400 + (0x33 << 2))))
50#define P_PIN_MUX_REG8 (*((volatile unsigned *)(0xda834400 + (0x34 << 2))))
51#define P_PIN_MUX_AO_REG (*((volatile unsigned *)(0xc8100000 + (0x5 << 2))))
52
53#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
54#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
55#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
56#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
57
58#define P_PWM_MISC_REG_EF (*((volatile unsigned *)(0xc1100000 + (0x21b2 << 2))))
59#define P_PWM_PWM_F (*((volatile unsigned *)(0xc1100000 + (0x21b1 << 2))))
60
61#undef P_AO_PWM_MISC_REG_AB
62#undef P_AO_PWM_PWM_A
63#define P_AO_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc8100400 + (0x56 << 2))))
64#define P_AO_PWM_PWM_A (*((volatile unsigned *)(0xc8100400 + (0x54 << 2))))
65
66#define P_EE_TIMER_E (*((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
67
68enum pwm_id {
69 pwm_a = 0,
70 pwm_b,
71 pwm_c,
72 pwm_d,
73 pwm_e,
74 pwm_f,
75 pwm_ao_a,
76};
77
78unsigned int _get_time(void)
79{
80 return P_EE_TIMER_E;
81}
82
83void _udelay_(unsigned int us)
84{
85 unsigned int t0 = _get_time();
86
87 while (_get_time() - t0 <= us)
88 ;
89}
90
91void pwm_init(int id)
92{
93 unsigned int reg;
94
95 /*
96 * TODO: support more pwm controllers, right now only support
97 * PWM_B, PWM_D
98 */
99
100 switch (id) {
101 case pwm_b:
102 reg = P_PWM_MISC_REG_AB;
103 reg &= ~(0x7f << 16);
104 reg |= ((1 << 23) | (1 << 1));
105 P_PWM_MISC_REG_AB = reg;
106 /*
107 * default set to max voltage
108 */
109 P_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
110 reg = P_PIN_MUX_REG1;
111 reg &= ~(1 << 10);
112 P_PIN_MUX_REG1 = reg;
113
114 reg = P_PIN_MUX_REG2;
115 reg &= ~(1 << 5);
116 reg |= (1 << 11); /* enable PWM_B */
117 P_PIN_MUX_REG2 = reg;
118 break;
119
120 case pwm_ao_a:
121 reg = P_AO_PWM_MISC_REG_AB;
122 reg &= ~(0x7f << 8);
123 reg |= ((1 << 15) | (1 << 0));
124 P_AO_PWM_MISC_REG_AB = reg;
125 /*
126 * default set to max voltage
127 */
128 P_AO_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
129 reg = P_PIN_MUX_AO_REG;
130 reg &= ~(1 << 9);
131 reg &= ~(1 << 7);
132 P_PIN_MUX_AO_REG = reg;
133
134 reg = P_PIN_MUX_AO_REG;
135 reg |= (1 << 22); /* enable PWM_AO_A */
136 P_PIN_MUX_AO_REG = reg;
137 break;
138
139 case pwm_f:
140 reg = P_PWM_MISC_REG_EF;
141 reg &= ~(0x7f << 16);
142 reg |= ((1 << 23) | (1 << 1));
143 P_PWM_MISC_REG_EF = reg;
144 /*
145 * default set to max voltage
146 */
147 P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
148 reg = P_PIN_MUX_REG8;
149 reg &= ~(1 << 29);
150 P_PIN_MUX_REG8 = reg;
151
152 reg = P_PIN_MUX_REG8;
153 reg |= (1 << 30); /* enable PWM_F */
154 P_PIN_MUX_REG8 = reg;
155 break;
156
157 default:
158 break;
159 }
160
161 _udelay_(200);
162}
163
164void pwm_set_voltage(unsigned int id, unsigned int voltage)
165{
166 int to;
167
168 for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
169 if (pwm_voltage_table[to][1] >= voltage) {
170 break;
171 }
172 }
173 if (to >= ARRAY_SIZE(pwm_voltage_table)) {
174 to = ARRAY_SIZE(pwm_voltage_table) - 1;
175 }
176 switch (id) {
177 case pwm_b:
178 P_PWM_PWM_B = pwm_voltage_table[to][0];
179 break;
180 case pwm_f:
181 P_PWM_PWM_F = pwm_voltage_table[to][0];
182 break;
183 case pwm_ao_a:
184 P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
185 break;
186 default:
187 break;
188 }
189 _udelay_(200);
190}
191
192void power_init(int mode)
193{
194 pwm_init(pwm_b);
195 pwm_init(pwm_ao_a);
196 pwm_init(pwm_f);
197 serial_puts("set vdd cpu_a to ");
198 serial_put_dec(CONFIG_VCCKA_INIT_VOLTAGE);
199 serial_puts(" mv\n");
200 pwm_set_voltage(pwm_ao_a, CONFIG_VCCKA_INIT_VOLTAGE);
201
202 serial_puts("set vdd cpu_b to ");
203 serial_put_dec(CONFIG_VCCKB_INIT_VOLTAGE);
204 serial_puts(" mv\n");
205 pwm_set_voltage(pwm_f, CONFIG_VCCKB_INIT_VOLTAGE);
206
207 serial_puts("set vddee to ");
208 serial_put_dec(CONFIG_VDDEE_INIT_VOLTAGE);
209 serial_puts(" mv\n");
210 pwm_set_voltage(pwm_b, CONFIG_VDDEE_INIT_VOLTAGE);
211}