Googler | e00b8eb | 2019-07-08 16:37:07 -0700 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010,2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
Googler | a8fd56b | 2024-10-24 14:04:51 +0800 | [diff] [blame^] | 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
Googler | e00b8eb | 2019-07-08 16:37:07 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <lcd.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/arch/funcmux.h> |
| 13 | #include <asm/arch/pinmux.h> |
| 14 | #include <asm/arch/tegra.h> |
| 15 | #include <asm/gpio.h> |
| 16 | |
Googler | a8fd56b | 2024-10-24 14:04:51 +0800 | [diff] [blame^] | 17 | #ifdef CONFIG_TEGRA_MMC |
Googler | e00b8eb | 2019-07-08 16:37:07 -0700 | [diff] [blame] | 18 | /* |
| 19 | * Routine: pin_mux_mmc |
| 20 | * Description: setup the pin muxes/tristate values for the SDMMC(s) |
| 21 | */ |
| 22 | void pin_mux_mmc(void) |
| 23 | { |
| 24 | funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); |
| 25 | funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT); |
| 26 | |
| 27 | /* For power GPIO PI6 */ |
| 28 | pinmux_tristate_disable(PMUX_PINGRP_ATA); |
| 29 | /* For CD GPIO PH2 */ |
| 30 | pinmux_tristate_disable(PMUX_PINGRP_ATD); |
| 31 | |
| 32 | /* For power GPIO PT3 */ |
| 33 | pinmux_tristate_disable(PMUX_PINGRP_DTB); |
| 34 | /* For CD GPIO PI5 */ |
| 35 | pinmux_tristate_disable(PMUX_PINGRP_ATC); |
| 36 | } |
| 37 | #endif |
| 38 | |
| 39 | void pin_mux_usb(void) |
| 40 | { |
| 41 | funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); |
| 42 | pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); |
| 43 | pinmux_tristate_disable(PMUX_PINGRP_CDEV2); |
| 44 | /* USB2 PHY reset GPIO */ |
| 45 | pinmux_tristate_disable(PMUX_PINGRP_UAC); |
| 46 | } |
| 47 | |
| 48 | void pin_mux_display(void) |
| 49 | { |
| 50 | pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); |
| 51 | pinmux_tristate_disable(PMUX_PINGRP_SDC); |
| 52 | } |