Googler | fc3e29a | 2022-11-22 14:17:45 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__ |
| 7 | #define __ARCH_ARM_MESON_USB_H_U_BOOT__ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <asm/types.h> |
| 11 | #include <asm/arch/io.h> |
| 12 | #include <asm/arch/secure_apb.h> |
| 13 | #include <generic-phy.h> |
| 14 | #include <asm-generic/gpio.h> |
| 15 | |
| 16 | #define USB_PHY_PORT_MAX 1 |
| 17 | /* Phy register MACRO definitions */ |
| 18 | |
| 19 | #define LINKSYSTEM_FLADJ_MASK (0x3f << 1) |
| 20 | #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) |
| 21 | #define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27) |
| 22 | |
| 23 | #define PHYUTMI_OTGDISABLE (1 << 6) |
| 24 | #define PHYUTMI_FORCESUSPEND (1 << 1) |
| 25 | #define PHYUTMI_FORCESLEEP (1 << 0) |
| 26 | |
| 27 | #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) |
| 28 | #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) |
| 29 | |
| 30 | #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) |
| 31 | #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) |
| 32 | |
| 33 | #define PHYCLKRST_SSC_EN (0x1 << 20) |
| 34 | #define PHYCLKRST_REF_SSP_EN (0x1 << 19) |
| 35 | #define PHYCLKRST_REF_CLKDIV2 (0x1 << 18) |
| 36 | |
| 37 | #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) |
| 38 | #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) |
| 39 | #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11) |
| 40 | #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) |
| 41 | #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) |
| 42 | #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) |
| 43 | |
| 44 | #define PHYCLKRST_FSEL_MASK (0x3f << 5) |
| 45 | #define PHYCLKRST_FSEL(_x) ((_x) << 5) |
| 46 | #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) |
| 47 | #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) |
| 48 | #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) |
| 49 | #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) |
| 50 | |
| 51 | #define PHYCLKRST_RETENABLEN (0x1 << 4) |
| 52 | |
| 53 | #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) |
| 54 | #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) |
| 55 | #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) |
| 56 | |
| 57 | #define PHYCLKRST_PORTRESET (0x1 << 1) |
| 58 | #define PHYCLKRST_COMMONONN (0x1 << 0) |
| 59 | |
| 60 | #define PHYPARAM0_REF_USE_PAD (0x1 << 31) |
| 61 | #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) |
| 62 | #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) |
| 63 | |
| 64 | #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) |
| 65 | #define PHYPARAM1_PCS_TXDEEMPH (0x1c) |
| 66 | |
| 67 | #define PHYTEST_POWERDOWN_SSP (0x1 << 3) |
| 68 | #define PHYTEST_POWERDOWN_HSP (0x1 << 2) |
| 69 | |
| 70 | #define PHYBATCHG_UTMI_CLKSEL (0x1 << 2) |
| 71 | |
| 72 | #define FSEL_CLKSEL_24M (0x5) |
| 73 | |
| 74 | #define USB_PHY2_ENABLE 0x10000000 |
| 75 | #define USB_PHY2_RESET 0x20000000 |
| 76 | |
| 77 | /* XHCI PHY register structure */ |
| 78 | #define PHY_REGISTER_SIZE 0x20 |
| 79 | |
| 80 | struct phy_aml_usb2_priv { |
| 81 | unsigned int base_addr; |
| 82 | unsigned int reset_addr; |
| 83 | unsigned int dwc2_a_addr; |
| 84 | unsigned int u2_port_num; |
| 85 | unsigned int usbphy_reset_bit[8]; |
| 86 | unsigned int usb_phy2_pll_base_addr[4]; |
| 87 | }; |
| 88 | |
| 89 | struct phy_aml_usb3_priv { |
| 90 | unsigned int base_addr; |
| 91 | unsigned int usb3_port_num; |
| 92 | struct gpio_desc desc; |
| 93 | }; |
| 94 | |
| 95 | /* Register definitions */ |
| 96 | typedef struct u2p_aml_regs { |
| 97 | volatile uint32_t u2p_r0; |
| 98 | volatile uint32_t u2p_r1; |
| 99 | } u2p_aml_regs_t; |
| 100 | |
| 101 | typedef union u2p_r0 { |
| 102 | /** raw register data */ |
| 103 | uint32_t d32; |
| 104 | /** register bits */ |
| 105 | struct { |
| 106 | unsigned host_device:1; |
| 107 | unsigned power_ok:1; |
| 108 | unsigned hast_mode:1; |
| 109 | unsigned POR:1; |
| 110 | unsigned IDPULLUP0:1; |
| 111 | unsigned DRVVBUS0:1; |
| 112 | unsigned reserved:26; |
| 113 | } b; |
| 114 | } u2p_r0_t; |
| 115 | |
| 116 | typedef union u2p_r1 { |
| 117 | /** raw register data */ |
| 118 | uint32_t d32; |
| 119 | /** register bits */ |
| 120 | struct { |
| 121 | unsigned phy_rdy:1; |
| 122 | unsigned IDDIG0:1; |
| 123 | unsigned OTGSESSVLD0:1; |
| 124 | unsigned VBUSVALID0:1; |
| 125 | unsigned reserved:28; |
| 126 | } b; |
| 127 | } u2p_r1_t; |
| 128 | |
| 129 | |
| 130 | typedef struct usb_aml_regs { |
| 131 | volatile uint32_t usb_r0; |
| 132 | volatile uint32_t usb_r1; |
| 133 | volatile uint32_t usb_r2; |
| 134 | volatile uint32_t usb_r3; |
| 135 | volatile uint32_t usb_r4; |
| 136 | volatile uint32_t usb_r5; |
| 137 | } usb_aml_regs_t; |
| 138 | |
| 139 | typedef union usb_r0 { |
| 140 | /** raw register data */ |
| 141 | uint32_t d32; |
| 142 | /** register bits */ |
| 143 | struct { |
| 144 | unsigned reserved:17; |
| 145 | unsigned p30_lane0_tx2rx_loopback:1; |
| 146 | unsigned p30_lane0_ext_pclk_reg:1; |
| 147 | unsigned p30_pcs_rx_los_mask_val:10; |
| 148 | unsigned u2d_ss_scaledown_mode:2; |
| 149 | unsigned u2d_act:1; |
| 150 | } b; |
| 151 | } usb_r0_t; |
| 152 | |
| 153 | typedef union usb_r1 { |
| 154 | /** raw register data */ |
| 155 | uint32_t d32; |
| 156 | /** register bits */ |
| 157 | struct { |
| 158 | unsigned u3h_bigendian_gs:1; |
| 159 | unsigned u3h_pme_en:1; |
| 160 | unsigned u3h_hub_port_overcurrent:3; |
| 161 | unsigned reserved_1:2; |
| 162 | unsigned u3h_hub_port_perm_attach:3; |
| 163 | unsigned reserved_2:2; |
| 164 | unsigned u3h_host_u2_port_disable:2; |
| 165 | unsigned reserved_3:2; |
| 166 | unsigned u3h_host_u3_port_disable:1; |
| 167 | unsigned u3h_host_port_power_control_present:1; |
| 168 | unsigned u3h_host_msi_enable:1; |
| 169 | unsigned u3h_fladj_30mhz_reg:6; |
| 170 | unsigned p30_pcs_tx_swing_full:7; |
| 171 | } b; |
| 172 | } usb_r1_t; |
| 173 | |
| 174 | typedef union usb_r2 { |
| 175 | /** raw register data */ |
| 176 | uint32_t d32; |
| 177 | /** register bits */ |
| 178 | struct { |
| 179 | unsigned reserved:20; |
| 180 | unsigned p30_pcs_tx_deemph_3p5db:6; |
| 181 | unsigned p30_pcs_tx_deemph_6db:6; |
| 182 | } b; |
| 183 | } usb_r2_t; |
| 184 | |
| 185 | typedef union usb_r3 { |
| 186 | /** raw register data */ |
| 187 | uint32_t d32; |
| 188 | /** register bits */ |
| 189 | struct { |
| 190 | unsigned p30_ssc_en:1; |
| 191 | unsigned p30_ssc_range:3; |
| 192 | unsigned p30_ssc_ref_clk_sel:9; |
| 193 | unsigned p30_ref_ssp_en:1; |
| 194 | unsigned reserved:18; |
| 195 | } b; |
| 196 | } usb_r3_t; |
| 197 | |
| 198 | typedef union usb_r4 { |
| 199 | /** raw register data */ |
| 200 | uint32_t d32; |
| 201 | /** register bits */ |
| 202 | struct { |
| 203 | unsigned p21_PORTRESET0:1; |
| 204 | unsigned p21_SLEEPM0:1; |
| 205 | unsigned mem_pd:2; |
| 206 | unsigned p21_only:1; |
| 207 | unsigned reserved:27; |
| 208 | } b; |
| 209 | } usb_r4_t; |
| 210 | |
| 211 | typedef union usb_r5 { |
| 212 | /** raw register data */ |
| 213 | uint32_t d32; |
| 214 | /** register bits */ |
| 215 | struct { |
| 216 | unsigned iddig_sync:1; |
| 217 | unsigned iddig_reg:1; |
| 218 | unsigned iddig_cfg:2; |
| 219 | unsigned iddig_en0:1; |
| 220 | unsigned iddig_en1:1; |
| 221 | unsigned iddig_curr:1; |
| 222 | unsigned usb_iddig_irq:1; |
| 223 | unsigned iddig_th:8; |
| 224 | unsigned iddig_cnt:8; |
| 225 | unsigned reserved:8; |
| 226 | } b; |
| 227 | } usb_r5_t; |
| 228 | |
| 229 | /* usb id mode, only after M2 |
| 230 | mode = 0 : HARDWARE |
| 231 | mode = 1 : SW_HOST |
| 232 | mode = 2 : SW_DEVICE |
| 233 | */ |
| 234 | #define USB_ID_MODE_HARDWARE (1) |
| 235 | #define USB_ID_MODE_SW_HOST (2) |
| 236 | #define USB_ID_MODE_SW_DEVICE (3) |
| 237 | int usb2_phy_tuning(uint32_t phy2_pll_base, int port); |
| 238 | void set_usb_pll(uint32_t phy2_pll_base); |
| 239 | int usb_save_phy_dev (unsigned int number, struct phy *phy); |
| 240 | int usb2_phy_init (struct phy *phy); |
| 241 | unsigned int usb_get_dwc_a_base_addr(void); |
| 242 | unsigned int usb_get_device_mode_phy_base(void); |
| 243 | void usb_phy_tuning_reset(void); |
| 244 | void usb_device_mode_init(void); |
| 245 | |
| 246 | #endif |