| Googler | fc3e29a | 2022-11-22 14:17:45 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| 2 | /* |
| 3 | * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #ifndef __MESON_FIRM_UART_H_ |
| 7 | #define __MESON_FIRM_UART_H_ |
| 8 | #include <config.h> |
| 9 | #include <common.h> |
| 10 | #include "register.h" |
| 11 | //#include "io.h" |
| 12 | #include <asm/arch/secure_apb.h> |
| 13 | |
| 14 | #ifndef CONFIG_CONS_INDEX |
| 15 | #error Please define CONFIG_CONS_INDEX==[0|1] |
| 16 | #endif |
| 17 | |
| 18 | #if CONFIG_CONS_INDEX==0 |
| 19 | #define UART_PORT_CONS UART_PORT_0 |
| 20 | #elif CONFIG_CONS_INDEX==1 |
| 21 | #define UART_PORT_CONS UART_PORT_1 |
| 22 | #elif CONFIG_CONS_INDEX==2 |
| 23 | #define UART_PORT_CONS UART_PORT_AO |
| 24 | #define USE_AO_UART 1 |
| 25 | #else |
| 26 | #error Please define CONFIG_CONS_INDEX==[0|1] |
| 27 | #endif |
| 28 | /* |
| 29 | #define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO) |
| 30 | #define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO) |
| 31 | #define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO) |
| 32 | #define UART_PORT_AO P_AO_UART_WFIFO |
| 33 | |
| 34 | #define UART_WFIFO (0<<2) |
| 35 | #define UART_RFIFO (1<<2) |
| 36 | #define UART_CONTROL (2<<2) |
| 37 | #define UART_STATUS (3<<2) |
| 38 | #define UART_MISC (4<<2) |
| 39 | */ |
| 40 | |
| 41 | #include "clock.h" |
| 42 | |
| 43 | #define UART_CLK_SRC CLK81 |
| 44 | #define UART_PORT_0 0xfe001c00 |
| 45 | #define UART_PORT_1 0xfe001c00 |
| 46 | #define UART_PORT_AO 0xfe001c00 |
| 47 | #define UART_WFIFO 0 |
| 48 | #define UART_RFIFO 1 |
| 49 | #define UART_CONTROL 2 |
| 50 | #define UART_STATUS 3 |
| 51 | #define UART_MISC 4 |
| 52 | |
| 53 | #if USE_AO_UART == 1 |
| 54 | #define P_UART(uart_base,reg) (uart_base + (reg<<2)) |
| 55 | #else |
| 56 | #define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg) |
| 57 | #endif |
| 58 | #define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO) |
| 59 | #define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO) |
| 60 | |
| 61 | #define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL) |
| 62 | #define UART_CNTL_MASK_BAUD_RATE (0xfff) |
| 63 | #define UART_CNTL_MASK_TX_EN (1<<12) |
| 64 | #define UART_CNTL_MASK_RX_EN (1<<13) |
| 65 | #define UART_CNTL_MASK_2WIRE (1<<15) |
| 66 | #define UART_CNTL_MASK_STP_BITS (3<<16) |
| 67 | #define UART_CNTL_MASK_STP_1BIT (0<<16) |
| 68 | #define UART_CNTL_MASK_STP_2BIT (1<<16) |
| 69 | #define UART_CNTL_MASK_PRTY_EVEN (0<<18) |
| 70 | #define UART_CNTL_MASK_PRTY_ODD (1<<18) |
| 71 | #define UART_CNTL_MASK_PRTY_TYPE (1<<18) |
| 72 | #define UART_CNTL_MASK_PRTY_EN (1<<19) |
| 73 | #define UART_CNTL_MASK_CHAR_LEN (3<<20) |
| 74 | #define UART_CNTL_MASK_CHAR_8BIT (0<<20) |
| 75 | #define UART_CNTL_MASK_CHAR_7BIT (1<<20) |
| 76 | #define UART_CNTL_MASK_CHAR_6BIT (2<<20) |
| 77 | #define UART_CNTL_MASK_CHAR_5BIT (3<<20) |
| 78 | #define UART_CNTL_MASK_RST_TX (1<<22) |
| 79 | #define UART_CNTL_MASK_RST_RX (1<<23) |
| 80 | #define UART_CNTL_MASK_CLR_ERR (1<<24) |
| 81 | #define UART_CNTL_MASK_INV_RX (1<<25) |
| 82 | #define UART_CNTL_MASK_INV_TX (1<<26) |
| 83 | #define UART_CNTL_MASK_RINT_EN (1<<27) |
| 84 | #define UART_CNTL_MASK_TINT_EN (1<<28) |
| 85 | #define UART_CNTL_MASK_INV_CTS (1<<29) |
| 86 | #define UART_CNTL_MASK_MASK_ERR (1<<30) |
| 87 | #define UART_CNTL_MASK_INV_RTS (1<<31) |
| 88 | #define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS ) |
| 89 | #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0) |
| 90 | #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8) |
| 91 | #define UART_STAT_MASK_PRTY_ERR (1<<16) |
| 92 | #define UART_STAT_MASK_FRAM_ERR (1<<17) |
| 93 | #define UART_STAT_MASK_WFULL_ERR (1<<18) |
| 94 | #define UART_STAT_MASK_RFIFO_FULL (1<<19) |
| 95 | #define UART_STAT_MASK_RFIFO_EMPTY (1<<20) |
| 96 | #define UART_STAT_MASK_TFIFO_FULL (1<<21) |
| 97 | #define UART_STAT_MASK_TFIFO_EMPTY (1<<22) |
| 98 | #define UART_STAT_MASK_XMIT_BUSY (1<<25) |
| 99 | #define UART_STAT_MASK_RECV_BUSY (1<<26) |
| 100 | #define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC ) |
| 101 | |
| 102 | |
| 103 | #ifndef CONFIG_SERIAL_STP_BITS |
| 104 | #define CONFIG_SERIAL_STP_BITS 1 // 1 , 2 |
| 105 | #endif |
| 106 | #if CONFIG_SERIAL_STP_BITS==1 |
| 107 | #define UART_STP_BIT UART_CNTL_MASK_STP_1BIT |
| 108 | #elif CONFIG_SERIAL_STP_BITS==2 |
| 109 | #define UART_STP_BIT UART_CNTL_MASK_STP_2BIT |
| 110 | #else |
| 111 | #error CONFIG_SERIAL_STP_BITS wrong |
| 112 | #endif |
| 113 | |
| 114 | |
| 115 | #ifndef CONFIG_SERIAL_PRTY_TYPE |
| 116 | #define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3 |
| 117 | #endif |
| 118 | #if CONFIG_SERIAL_PRTY_TYPE==0 |
| 119 | #define UART_PRTY_BIT 0 |
| 120 | #elif CONFIG_SERIAL_PRTY_TYPE==2 |
| 121 | #define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN) |
| 122 | #elif CONFIG_SERIAL_PRTY_TYPE==3 |
| 123 | #define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD) |
| 124 | #else |
| 125 | #error CONFIG_SERIAL_PRTY_TYPE wrong |
| 126 | #endif |
| 127 | |
| 128 | #ifndef CONFIG_SERIAL_CHAR_LEN |
| 129 | #define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8 |
| 130 | #endif |
| 131 | #if CONFIG_SERIAL_CHAR_LEN==5 |
| 132 | #define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT |
| 133 | #elif CONFIG_SERIAL_CHAR_LEN==6 |
| 134 | #define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT |
| 135 | #elif CONFIG_SERIAL_CHAR_LEN==7 |
| 136 | #define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT |
| 137 | #elif CONFIG_SERIAL_CHAR_LEN==8 |
| 138 | #define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT |
| 139 | #else |
| 140 | #error CONFIG_SERIAL_CHAR_LEN wrong |
| 141 | #endif |
| 142 | #define UART_CONTROL_SET(baud,clk81) \ |
| 143 | (((clk81)/(baud*4) -1) \ |
| 144 | | UART_STP_BIT \ |
| 145 | | UART_PRTY_BIT \ |
| 146 | | UART_CHAR_LEN \ |
| 147 | | UART_CNTL_MASK_TX_EN \ |
| 148 | | UART_CNTL_MASK_RX_EN \ |
| 149 | | UART_CNTL_MASK_RST_TX \ |
| 150 | | UART_CNTL_MASK_RST_RX \ |
| 151 | | UART_CNTL_MASK_CLR_ERR ) |
| 152 | #endif |
