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nest-open-source / manifest_repos / u-boot / fc3e29a3a807030f54f42519e72379efdfdf77c8 / . / board / amlogic / s4_ap222 / firmware / timing.c
blob: 22e9c3b7f3054965bb1dc0cd5e331545b42ab0e3 [file] [log] [blame]
Googlerfc3e29a2022-11-22 14:17:45 +0800[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include <asm/arch/secure_apb.h>
7#include <asm/arch/timing.h>
8#include <asm/arch/ddr_define.h>
9
10/* board clk defines */
11#define CPU_CLK 1512
12
13ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
14#if 1
15{
16 //timing_config,4layer 4pcs ddr4 rank01, ap222.
17 .cfg_board_common_setting.timming_magic = 0,
18 .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
19 .cfg_board_common_setting.timming_struct_version = 0,
20 .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
21 .cfg_board_common_setting.timming_struct_real_size = 0, //0
22 .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (2) },
23 .cfg_board_common_setting.ddr_func = 0,
24 .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
25 .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
26 .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
27 .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
28 .cfg_board_common_setting.dram_cs0_base_add = 0,
29 .cfg_board_common_setting.dram_cs1_base_add = 0,
30 .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
31 .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_1024MB,
32 .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
33 .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
34 .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
35 .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
36 .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
37 .cfg_board_common_setting.org_tdqs2dq = 0,
38 .cfg_board_common_setting.reserve1_test_function = { 0 },
39 .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
40 //af419 ac pinmux
41 #if 0
42 .cfg_board_common_setting.ac_pinmux =
43 {
44 0, 0, 0, 1, 2, 3, 27, 12,
45 21, 9, 8, 0, 14, 10, 6, 7,
46 20, 5, 22, 13, 15, 2, 0, 0,
47 0, 0, 11, 26, 4, 0, 0, 25,
48 3, 1,
49 },
50 #endif
51 //s4 ddr4 ac pinmux
52 .cfg_board_common_setting.ac_pinmux =
53 {
54 0, 0, 0, 1, 2, 3,
55 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
56 },
57 .cfg_board_common_setting.ddr_dqs_swap = 0,
58 .cfg_board_common_setting.ddr_dq_remap =
59 {
60 0, 1, 2, 3, 4, 5, 6, 7,
61 8, 9, 10, 11, 12, 13, 14, 15,
62 16, 17, 18, 19, 20, 21, 22, 23,
63 24, 25, 26, 27, 28, 29, 30, 31,
64 32, 33, 34, 35
65 }, //d0-d31 dm0 dm1 dm2 dm3
66 .cfg_board_common_setting.ddr_vddee_setting = { 0 },
67 .cfg_board_SI_setting_ps[0].DRAMFreq = 1176,
68 .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
69 .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
70 .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01__R_CS0_ODT1_CS1_ODT0,
71 .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
72 .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
73 .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
74 .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
75 .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
76 .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
77 .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
78 .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
79 .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
80 .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR4_WR_ODT_240_OHM,
81 .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
82 .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
83 .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
84 .cfg_board_SI_setting_ps[0].reserve2 = 0,
85 .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
86 .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
87 .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
88 .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
89 .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
90 .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
91 {
92 128, 128, 128 - 40, 128, 128, 128, 128, 128,
93 384, 384, 384, 384, 384, 384, 384, 384,
94 384, 384, 384, 384, 384, 384, 384, 384,
95 384, 384, 384, 384, 384, 384, 384, 384,
96 384, 384, 384, 384,
97 }, //total 36
98 .cfg_ddr_training_delay_ps[0].ac_trace_delay =
99 {
100 128, 128, 128 - 40, 128, 128, 128, 128, 384,
101 384, 384, 384, 384, 384, 384, 384, 384,
102 384, 384, 384, 384, 384, 384, 384, 384,
103 384, 384, 384, 384, 384, 384, 384, 384,
104 384, 384, 384, 384,
105 },
106
107 #if 1
108 .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000e1,// 225
109 .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000eb,// 235
110 .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000e1,// 225
111 .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000d7,// 215
112 .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000d7,// 215
113 .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000e1,// 225
114 .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000e1,// 225
115 .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000d7,// 215
116 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x00000130,// 304
117 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000120,// 288
118 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000132,// 306
119 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000125,// 293
120 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x0000012b,// 299
121 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000115,// 277
122 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x00000131,// 305
123 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000012d,// 301
124 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000124,// 292
125 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000134,// 308
126 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000115,// 277
127 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000127,// 295
128 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000011f,// 287
129 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x00000141,// 321
130 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000129,// 297
131 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000137,// 311
132 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000120,// 288
133 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000012a,// 298
134 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000127,// 295
135 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x00000112,// 274
136 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000119,// 281
137 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000115,// 277
138 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000012b,// 299
139 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000011c,// 284
140 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000116,// 278
141 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000120,// 288
142 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000011f,// 287
143 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000012b,// 299
144 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000113,// 275
145 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000011f,// 287
146 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000117,// 279
147 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000126,// 294
148 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x00000117,// 279
149 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000011c,// 284
150 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000113,// 275
151 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x0000011f,// 287
152 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x0000012d,// 301
153 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x0000011f,// 287
154 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000125,// 293
155 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x0000011e,// 286
156 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x0000011a,// 282
157 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000108,// 264
158 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000121,// 289
159 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x0000011f,// 287
160 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x0000011b,// 283
161 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x0000012a,// 298
162 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x0000010c,// 268
163 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000118,// 280
164 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000115,// 277
165 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x0000012f,// 303
166 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x0000011f,// 287
167 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000126,// 294
168 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000118,// 280
169 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x0000011d,// 285
170 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000139,// 313
171 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x0000011b,// 283
172 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x0000011e,// 286
173 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000123,// 291
174 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000127,// 295
175 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000118,// 280
176 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x0000011b,// 283
177 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x0000011e,// 286
178 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x0000012d,// 301
179 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x0000012c,// 300
180 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000117,// 279
181 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000122,// 290
182 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000118,// 280
183 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000127,// 295
184 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000119,// 281
185 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x0000011c,// 284
186 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000118,// 280
187 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000122,// 290
188 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000376,// 886
189 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000372,// 882
190 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000366,// 870
191 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000036c,// 876
192 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000378,// 888
193 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000373,// 883
194 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x0000036d,// 877
195 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000371,// 881
196 .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000059,// 89
197 .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000063,// 99
198 .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000075,// 117
199 .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000060,// 96
200 .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000071,// 113
201 .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000086,// 134
202 .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000079,// 121
203 .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000086,// 134
204 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000035,// 53
205 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000028,// 40
206 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58
207 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000002e,// 46
208 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000033,// 51
209 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000028,// 40
210 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000039,// 57
211 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x0000002f,// 47
212 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000031,// 49
213 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x0000003b,// 59
214 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x0000002a,// 42
215 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000035,// 53
216 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000002c,// 44
217 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004a,// 74
218 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000034,// 52
219 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000042,// 66
220 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002d,// 45
221 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000036,// 54
222 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003b,// 59
223 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000002b,// 43
224 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000036,// 54
225 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
226 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000004a,// 74
227 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000039,// 57
228 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
229 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000038,// 56
230 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000037,// 55
231 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000037,// 55
232 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000027,// 39
233 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000032,// 50
234 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000002b,// 43
235 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62
236 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000029,// 41
237 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49
238 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000002a,// 42
239 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x0000002f,// 47
240 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x0000004a,// 74
241 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000041,// 65
242 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000045,// 69
243 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x0000003f,// 63
244 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000044,// 68
245 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000031,// 49
246 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000049,// 73
247 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000040,// 64
248 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000041,// 65
249 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000050,// 80
250 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000035,// 53
251 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x0000004c,// 76
252 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003a,// 58
253 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000060,// 96
254 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000044,// 68
255 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000055,// 85
256 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000039,// 57
257 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000047,// 71
258 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x0000005b,// 91
259 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000044,// 68
260 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000053,// 83
261 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000043,// 67
262 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000052,// 82
263 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000043,// 67
264 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000051,// 81
265 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000037,// 55
266 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x0000004a,// 74
267 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000053,// 83
268 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000037,// 55
269 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000004c,// 76
270 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x0000003e,// 62
271 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000057,// 87
272 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x0000003e,// 62
273 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x0000004a,// 74
274 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000040,// 64
275 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000046,// 70
276 #endif
277 //total 72
278 .cfg_ddr_training_delay_ps[0].soc_bit_vref =
279 {
280 0, 40, 40, 40, 40, 40, 40, 40,
281 40, 40, 40, 40, 40, 40, 40, 40,
282 40, 40, 40, 40, 40, 40, 40, 40,
283 40, 40, 40, 40, 40, 40, 40, 40,
284 40, 40, 40, 40, 40, 48, 40, 48,
285 40, 48, 40, 48
286 }, //total 44
287 .cfg_ddr_training_delay_ps[0].dram_bit_vref =
288 {
289 0, 32, 32, 32, 32, 32, 32, 32,
290 32, 32, 32, 32, 32, 32, 32, 32,
291 32, 32, 32, 32, 32, 32, 32, 32,
292 32, 32, 32, 32, 32, 32, 32, 32,
293 32, 32, 32, 32
294 }, //total 36
295 .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
296
297 .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
298 .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
299 .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
300 .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
301 .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
302 .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
303 .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
304 .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
305 .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
306 .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
307 .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
308 .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
309 .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
310 .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
311 .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
312 .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
313 .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
314 .cfg_board_SI_setting_ps[1].reserve2 = 0,
315 .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
316 .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
317 .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
318 .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
319 .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
320 .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
321 {
322 128, 128, 128, 128, 128, 128, 128, 128,
323 128, 128, 128, 128, 128, 128, 128, 128,
324 128, 128, 128, 128, 128, 128, 128, 128,
325 128, 128, 128, 128, 128, 128, 128, 128,
326 128, 128, 128, 128,
327 }, //total 36
328 .cfg_ddr_training_delay_ps[1].ac_trace_delay =
329 {
330 128, 128, 128, 128, 128, 128, 128, 128,
331 128, 128, 128, 128, 128, 128, 128, 128,
332 128, 128, 128, 128, 128, 128, 128, 128,
333 128, 128, 128, 128, 128, 128, 128, 128,
334 128, 128, 128, 128,
335 }, //total 36
336 .cfg_ddr_training_delay_ps[1].write_dqs_delay =
337 {
338 0, 0, 0, 0, 0, 0, 0, 0
339 },
340 .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
341 {
342 50, 50, 50, 50, 50, 50, 50, 50,
343 50, 50, 50, 50, 50, 50, 50, 50,
344 50, 50, 50, 50, 50, 50, 50, 50,
345 50, 50, 50, 50, 50, 50, 50, 50,
346 50, 50, 50, 50, 50, 50, 50, 50,
347 50, 50, 50, 50, 50, 50, 50, 50,
348 50, 50, 50, 50, 50, 50, 50, 50,
349 50, 50, 50, 50, 50, 50, 50, 50,
350 50, 50, 50, 50, 50, 50, 50, 50,
351 },
352 .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
353 {
354 192, 192, 192, 192, 192, 192, 192, 192
355 }, //total 8
356 .cfg_ddr_training_delay_ps[1].read_dqs_delay =
357 {
358 64, 64, 64, 64, 64, 64, 64, 64
359 }, //total 8
360 .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
361 {
362 0, 0, 0, 0, 0, 0, 0, 0,
363 0, 0, 0, 0, 0, 0, 0, 0,
364 0, 0, 0, 0, 0, 0, 0, 0,
365 0, 0, 0, 0, 0, 0, 0, 0,
366 0, 0, 0, 0, 0, 0, 0, 0,
367 0, 0, 0, 0, 0, 0, 0, 0,
368 0, 0, 0, 0, 0, 0, 0, 0,
369 0, 0, 0, 0, 0, 0, 0, 0,
370 0, 0, 0, 0, 0, 0, 0, 0
371 }, //total 72
372 .cfg_ddr_training_delay_ps[1].soc_bit_vref =
373 {
374 0, 40, 40, 40, 40, 40, 40, 40,
375 40, 40, 40, 40, 40, 40, 40, 40,
376 40, 40, 40, 40, 40, 40, 40, 40,
377 40, 40, 40, 40, 40, 40, 40, 40,
378 40, 40, 40, 40, 40, 40, 40, 40,
379 40, 40, 40, 40
380 }, //total 44
381 .cfg_ddr_training_delay_ps[1].dram_bit_vref =
382 {
383 0, 32, 32, 32, 32, 32, 32, 32,
384 32, 32, 32, 32, 32, 32, 32, 32,
385 32, 32, 32, 32, 32, 32, 32, 32,
386 32, 32, 32, 32, 32, 32, 32, 32,
387 32, 32, 32, 32
388 }, //total 36
389 .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
390},
391#endif
392#if 0
393{
394 //timing_config,4layer 2pcs ddr4 rank0, gangzhen pcb.
395 .cfg_board_common_setting.timming_magic = 0,
396 .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
397 .cfg_board_common_setting.timming_struct_version = 0,
398 .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
399 .cfg_board_common_setting.timming_struct_real_size = 0, //0
400 .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
401 .cfg_board_common_setting.ddr_func = 0,
402 .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
403 .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
404 .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
405 .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
406 .cfg_board_common_setting.dram_cs0_base_add = 0,
407 .cfg_board_common_setting.dram_cs1_base_add = 0,
408 .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
409 .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
410 .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
411 .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
412 .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
413 .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
414 .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
415 .cfg_board_common_setting.org_tdqs2dq = 0,
416 .cfg_board_common_setting.reserve1_test_function = { 0 },
417 .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
418 //af419 ac pinmux
419 #if 0
420 .cfg_board_common_setting.ac_pinmux =
421 {
422 0, 0, 0, 1, 2, 3, 27, 12,
423 21, 9, 8, 0, 14, 10, 6, 7,
424 20, 5, 22, 13, 15, 2, 0, 0,
425 0, 0, 11, 26, 4, 0, 0, 25,
426 3, 1,
427 },
428 #endif
429 //s4 ddr4 ac pinmux
430 .cfg_board_common_setting.ac_pinmux =
431 {
432 0, 0, 0, 1, 2, 3,
433 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
434 },
435 .cfg_board_common_setting.ddr_dqs_swap = 0,
436 .cfg_board_common_setting.ddr_dq_remap =
437 {
438 0, 1, 2, 3, 4, 5, 6, 7,
439 8, 9, 10, 11, 12, 13, 14, 15,
440 16, 17, 18, 19, 20, 21, 22, 23,
441 24, 25, 26, 27, 28, 29, 30, 31,
442 32, 33, 34, 35
443 }, //d0-d31 dm0 dm1 dm2 dm3
444 .cfg_board_common_setting.ddr_vddee_setting = { 0 },
445 .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
446 .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
447 .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
448 .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
449 .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
450 .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
451 .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
452 .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
453 .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
454 .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
455 .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
456 .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
457 .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
458 .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
459 .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
460 .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
461 .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
462 .cfg_board_SI_setting_ps[0].reserve2 = 0,
463 .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
464 .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
465 .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
466 .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
467 .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
468 .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
469 {
470 128, 128, 128 - 40, 128, 128, 128, 128, 128,
471 384, 384, 384, 384, 384, 384, 384, 384,
472 384, 384, 384, 384, 384, 384, 384, 384,
473 384, 384, 384, 384, 384, 384, 384, 384,
474 384, 384, 384, 384,
475 }, //total 36
476 .cfg_ddr_training_delay_ps[0].ac_trace_delay =
477 {
478 128, 128, 128 - 40, 128, 128, 128, 128, 384,
479 384, 384, 384, 384, 384, 384, 384, 384,
480 384, 384, 384, 384, 384, 384, 384, 384,
481 384, 384, 384, 384, 384, 384, 384, 384,
482 384, 384, 384, 384,
483 },
484
485 #if 1
486 .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000c8,// 200
487 .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000c3,// 195
488 .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000b4,// 180
489 .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000af,// 175
490 .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
491 .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
492 .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
493 .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
494 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000010b,// 267
495 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000f7,// 247
496 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000105,// 261
497 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000100,// 256
498 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000f5,// 245
499 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000e4,// 228
500 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000ff,// 255
501 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000fe,// 254
502 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000f8,// 248
503 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x0000010e,// 270
504 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000f3,// 243
505 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000106,// 262
506 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000fa,// 250
507 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x00000100,// 256
508 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000fa,// 250
509 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000107,// 263
510 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000fd,// 253
511 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000100,// 256
512 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000102,// 258
513 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e9,// 233
514 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000ff,// 255
515 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ef,// 239
516 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000100,// 256
517 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000f8,// 248
518 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000f2,// 242
519 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000fa,// 250
520 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000f3,// 243
521 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000111,// 273
522 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000ec,// 236
523 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x00000103,// 259
524 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000f9,// 249
525 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x0000010c,// 268
526 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000f3,// 243
527 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000f9,// 249
528 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000f6,// 246
529 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000ff,// 255
530 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
531 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
532 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
533 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
534 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
535 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
536 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
537 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
538 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
539 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
540 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
541 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
542 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
543 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
544 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
545 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
546 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
547 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
548 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
549 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
550 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
551 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
552 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
553 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
554 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
555 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
556 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
557 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
558 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
559 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
560 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
561 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
562 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
563 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
564 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
565 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
566 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000032d,// 813
567 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000032a,// 810
568 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000337,// 823
569 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000344,// 836
570 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
571 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
572 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
573 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
574 .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000008c,// 140
575 .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000078,// 120
576 .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000007a,// 122
577 .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000063,// 99
578 .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
579 .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
580 .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
581 .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
582 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000050,// 80
583 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
584 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004b,// 75
585 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003f,// 63
586 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004c,// 76
587 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000033,// 51
588 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000004e,// 78
589 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x0000003a,// 58
590 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000043,// 67
591 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000053,// 83
592 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000035,// 53
593 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000045,// 69
594 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000002e,// 46
595 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045,// 69
596 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000003a,// 58
597 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000051,// 81
598 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c,// 60
599 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000040,// 64
600 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000050,// 80
601 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000002f,// 47
602 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000044,// 68
603 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000035,// 53
604 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000051,// 81
605 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000047,// 71
606 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000043,// 67
607 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000004d,// 77
608 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000044,// 68
609 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000054,// 84
610 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000030,// 48
611 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000043,// 67
612 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000030,// 48
613 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000051,// 81
614 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000032,// 50
615 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000041,// 65
616 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000030,// 48
617 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x0000003d,// 61
618 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
619 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
620 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
621 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
622 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
623 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
624 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
625 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
626 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
627 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
628 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
629 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
630 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
631 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
632 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
633 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
634 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
635 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
636 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
637 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
638 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
639 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
640 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
641 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
642 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
643 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
644 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
645 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
646 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
647 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
648 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
649 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
650 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
651 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
652 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
653 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
654 #endif
655 //total 72
656 .cfg_ddr_training_delay_ps[0].soc_bit_vref =
657 {
658 0, 40, 40, 40, 40, 40, 40, 40,
659 40, 40, 40, 40, 40, 40, 40, 40,
660 40, 40, 40, 40, 40, 40, 40, 40,
661 40, 40, 40, 40, 40, 40, 40, 40,
662 40, 40, 40, 40, 40, 48, 40, 48,
663 40, 48, 40, 48
664 }, //total 44
665 .cfg_ddr_training_delay_ps[0].dram_bit_vref =
666 {
667 0, 32, 32, 32, 32, 32, 32, 32,
668 32, 32, 32, 32, 32, 32, 32, 32,
669 32, 32, 32, 32, 32, 32, 32, 32,
670 32, 32, 32, 32, 32, 32, 32, 32,
671 32, 32, 32, 32
672 }, //total 36
673 .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
674
675 .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
676 .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
677 .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
678 .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
679 .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
680 .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
681 .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
682 .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
683 .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
684 .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
685 .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
686 .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
687 .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
688 .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
689 .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
690 .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
691 .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
692 .cfg_board_SI_setting_ps[1].reserve2 = 0,
693 .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
694 .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
695 .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
696 .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
697 .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
698 .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
699 {
700 128, 128, 128, 128, 128, 128, 128, 128,
701 128, 128, 128, 128, 128, 128, 128, 128,
702 128, 128, 128, 128, 128, 128, 128, 128,
703 128, 128, 128, 128, 128, 128, 128, 128,
704 128, 128, 128, 128,
705 }, //total 36
706 .cfg_ddr_training_delay_ps[1].ac_trace_delay =
707 {
708 128, 128, 128, 128, 128, 128, 128, 128,
709 128, 128, 128, 128, 128, 128, 128, 128,
710 128, 128, 128, 128, 128, 128, 128, 128,
711 128, 128, 128, 128, 128, 128, 128, 128,
712 128, 128, 128, 128,
713 }, //total 36
714 .cfg_ddr_training_delay_ps[1].write_dqs_delay =
715 {
716 0, 0, 0, 0, 0, 0, 0, 0
717 },
718 .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
719 {
720 50, 50, 50, 50, 50, 50, 50, 50,
721 50, 50, 50, 50, 50, 50, 50, 50,
722 50, 50, 50, 50, 50, 50, 50, 50,
723 50, 50, 50, 50, 50, 50, 50, 50,
724 50, 50, 50, 50, 50, 50, 50, 50,
725 50, 50, 50, 50, 50, 50, 50, 50,
726 50, 50, 50, 50, 50, 50, 50, 50,
727 50, 50, 50, 50, 50, 50, 50, 50,
728 50, 50, 50, 50, 50, 50, 50, 50,
729 },
730 .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
731 {
732 192, 192, 192, 192, 192, 192, 192, 192
733 }, //total 8
734 .cfg_ddr_training_delay_ps[1].read_dqs_delay =
735 {
736 64, 64, 64, 64, 64, 64, 64, 64
737 }, //total 8
738 .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
739 {
740 0, 0, 0, 0, 0, 0, 0, 0,
741 0, 0, 0, 0, 0, 0, 0, 0,
742 0, 0, 0, 0, 0, 0, 0, 0,
743 0, 0, 0, 0, 0, 0, 0, 0,
744 0, 0, 0, 0, 0, 0, 0, 0,
745 0, 0, 0, 0, 0, 0, 0, 0,
746 0, 0, 0, 0, 0, 0, 0, 0,
747 0, 0, 0, 0, 0, 0, 0, 0,
748 0, 0, 0, 0, 0, 0, 0, 0
749 }, //total 72
750 .cfg_ddr_training_delay_ps[1].soc_bit_vref =
751 {
752 0, 40, 40, 40, 40, 40, 40, 40,
753 40, 40, 40, 40, 40, 40, 40, 40,
754 40, 40, 40, 40, 40, 40, 40, 40,
755 40, 40, 40, 40, 40, 40, 40, 40,
756 40, 40, 40, 40, 40, 40, 40, 40,
757 40, 40, 40, 40
758 }, //total 44
759 .cfg_ddr_training_delay_ps[1].dram_bit_vref =
760 {
761 0, 32, 32, 32, 32, 32, 32, 32,
762 32, 32, 32, 32, 32, 32, 32, 32,
763 32, 32, 32, 32, 32, 32, 32, 32,
764 32, 32, 32, 32, 32, 32, 32, 32,
765 32, 32, 32, 32
766 }, //total 36
767 .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
768},
769#endif
770{
771 //timing_config,4layer 2pcs ddr4 rank0, ap229.
772 .cfg_board_common_setting.timming_magic = 0,
773 .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[1]) / sizeof(ddr_set_t),
774 .cfg_board_common_setting.timming_struct_version = 0,
775 .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
776 .cfg_board_common_setting.timming_struct_real_size = 0, //0
777 .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
778 .cfg_board_common_setting.ddr_func = 0,
779 .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
780 .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
781 .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
782 .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
783 .cfg_board_common_setting.dram_cs0_base_add = 0,
784 .cfg_board_common_setting.dram_cs1_base_add = 0,
785 .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
786 .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
787 .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
788 .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
789 .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
790 .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
791 .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
792 .cfg_board_common_setting.org_tdqs2dq = 0,
793 .cfg_board_common_setting.reserve1_test_function = { 0 },
794 .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
795 //af419 ac pinmux
796 #if 0
797 .cfg_board_common_setting.ac_pinmux =
798 {
799 0, 0, 0, 1, 2, 3, 27, 12,
800 21, 9, 8, 0, 14, 10, 6, 7,
801 20, 5, 22, 13, 15, 2, 0, 0,
802 0, 0, 11, 26, 4, 0, 0, 25,
803 3, 1,
804 },
805 #endif
806 //s4 ddr4 ac pinmux
807 .cfg_board_common_setting.ac_pinmux =
808 {
809 0, 0, 0, 1, 2, 3,
810 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
811 },
812 .cfg_board_common_setting.ddr_dqs_swap = 0,
813 .cfg_board_common_setting.ddr_dq_remap =
814 {
815 0, 1, 2, 3, 4, 5, 6, 7,
816 8, 9, 10, 11, 12, 13, 14, 15,
817 16, 17, 18, 19, 20, 21, 22, 23,
818 24, 25, 26, 27, 28, 29, 30, 31,
819 32, 33, 34, 35
820 }, //d0-d31 dm0 dm1 dm2 dm3
821 .cfg_board_common_setting.ddr_vddee_setting = { 0 },
822 .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
823 .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
824 .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
825 .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
826 .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
827 .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
828 .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
829 .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
830 .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
831 .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
832 .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
833 .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
834 .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
835 .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
836 .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
837 .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
838 .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
839 .cfg_board_SI_setting_ps[0].reserve2 = 0,
840 .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
841 .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
842 .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
843 .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
844 .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
845 .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
846 {
847 128, 128, 128 - 40, 128, 128, 128, 128, 128,
848 384, 384, 384, 384, 384, 384, 384, 384,
849 384, 384, 384, 384, 384, 384, 384, 384,
850 384, 384, 384, 384, 384, 384, 384, 384,
851 384, 384, 384, 384,
852 }, //total 36
853 .cfg_ddr_training_delay_ps[0].ac_trace_delay =
854 {
855 128, 128, 128 - 40, 128, 128, 128, 128, 384,
856 384, 384, 384, 384, 384, 384, 384, 384,
857 384, 384, 384, 384, 384, 384, 384, 384,
858 384, 384, 384, 384, 384, 384, 384, 384,
859 384, 384, 384, 384,
860 },
861
862 #if 1
863 .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
864 .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
865 .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
866 .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
867 .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
868 .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
869 .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
870 .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
871 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
872 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
873 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
874 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
875 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
876 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
877 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
878 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
879 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
880 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
881 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
882 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
883 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
884 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
885 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
886 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
887 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
888 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
889 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
890 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
891 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
892 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
893 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
894 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
895 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
896 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
897 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
898 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
899 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
900 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
901 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
902 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
903 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
904 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
905 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
906 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
907 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
908 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
909 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
910 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
911 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
912 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
913 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
914 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
915 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
916 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
917 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
918 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
919 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
920 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
921 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
922 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
923 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
924 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
925 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
926 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
927 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
928 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
929 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
930 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
931 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
932 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
933 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
934 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
935 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
936 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
937 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
938 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
939 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
940 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
941 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
942 .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
943 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
944 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
945 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
946 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
947 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
948 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
949 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
950 .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
951 .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
952 .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
953 .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
954 .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
955 .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
956 .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
957 .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
958 .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
959 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
960 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
961 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
962 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
963 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
964 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
965 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
966 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
967 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
968 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
969 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
970 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
971 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
972 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
973 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
974 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
975 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
976 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
977 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
978 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
979 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
980 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
981 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
982 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
983 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
984 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
985 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
986 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
987 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
988 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
989 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
990 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
991 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
992 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
993 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
994 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
995 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
996 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
997 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
998 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
999 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
1000 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
1001 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
1002 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
1003 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
1004 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
1005 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
1006 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
1007 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
1008 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
1009 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
1010 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
1011 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
1012 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
1013 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
1014 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
1015 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
1016 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
1017 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
1018 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
1019 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
1020 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
1021 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
1022 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
1023 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
1024 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
1025 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
1026 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
1027 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
1028 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
1029 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
1030 .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
1031 #endif
1032 //total 72
1033 .cfg_ddr_training_delay_ps[0].soc_bit_vref =
1034 {
1035 0, 40, 40, 40, 40, 40, 40, 40,
1036 40, 40, 40, 40, 40, 40, 40, 40,
1037 40, 40, 40, 40, 40, 40, 40, 40,
1038 40, 40, 40, 40, 40, 40, 40, 40,
1039 40, 40, 40, 40, 40, 48, 40, 48,
1040 40, 48, 40, 48
1041 }, //total 44
1042 .cfg_ddr_training_delay_ps[0].dram_bit_vref =
1043 {
1044 0, 32, 32, 32, 32, 32, 32, 32,
1045 32, 32, 32, 32, 32, 32, 32, 32,
1046 32, 32, 32, 32, 32, 32, 32, 32,
1047 32, 32, 32, 32, 32, 32, 32, 32,
1048 32, 32, 32, 32
1049 }, //total 36
1050 .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
1051
1052 .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
1053 .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
1054 .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
1055 .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
1056 .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
1057 .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
1058 .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
1059 .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
1060 .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
1061 .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
1062 .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
1063 .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
1064 .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
1065 .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
1066 .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
1067 .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
1068 .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
1069 .cfg_board_SI_setting_ps[1].reserve2 = 0,
1070 .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
1071 .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
1072 .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
1073 .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
1074 .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
1075 .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
1076 {
1077 128, 128, 128, 128, 128, 128, 128, 128,
1078 128, 128, 128, 128, 128, 128, 128, 128,
1079 128, 128, 128, 128, 128, 128, 128, 128,
1080 128, 128, 128, 128, 128, 128, 128, 128,
1081 128, 128, 128, 128,
1082 }, //total 36
1083 .cfg_ddr_training_delay_ps[1].ac_trace_delay =
1084 {
1085 128, 128, 128, 128, 128, 128, 128, 128,
1086 128, 128, 128, 128, 128, 128, 128, 128,
1087 128, 128, 128, 128, 128, 128, 128, 128,
1088 128, 128, 128, 128, 128, 128, 128, 128,
1089 128, 128, 128, 128,
1090 }, //total 36
1091 .cfg_ddr_training_delay_ps[1].write_dqs_delay =
1092 {
1093 0, 0, 0, 0, 0, 0, 0, 0
1094 },
1095 .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
1096 {
1097 50, 50, 50, 50, 50, 50, 50, 50,
1098 50, 50, 50, 50, 50, 50, 50, 50,
1099 50, 50, 50, 50, 50, 50, 50, 50,
1100 50, 50, 50, 50, 50, 50, 50, 50,
1101 50, 50, 50, 50, 50, 50, 50, 50,
1102 50, 50, 50, 50, 50, 50, 50, 50,
1103 50, 50, 50, 50, 50, 50, 50, 50,
1104 50, 50, 50, 50, 50, 50, 50, 50,
1105 50, 50, 50, 50, 50, 50, 50, 50,
1106 },
1107 .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
1108 {
1109 192, 192, 192, 192, 192, 192, 192, 192
1110 }, //total 8
1111 .cfg_ddr_training_delay_ps[1].read_dqs_delay =
1112 {
1113 64, 64, 64, 64, 64, 64, 64, 64
1114 }, //total 8
1115 .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
1116 {
1117 0, 0, 0, 0, 0, 0, 0, 0,
1118 0, 0, 0, 0, 0, 0, 0, 0,
1119 0, 0, 0, 0, 0, 0, 0, 0,
1120 0, 0, 0, 0, 0, 0, 0, 0,
1121 0, 0, 0, 0, 0, 0, 0, 0,
1122 0, 0, 0, 0, 0, 0, 0, 0,
1123 0, 0, 0, 0, 0, 0, 0, 0,
1124 0, 0, 0, 0, 0, 0, 0, 0,
1125 0, 0, 0, 0, 0, 0, 0, 0
1126 }, //total 72
1127 .cfg_ddr_training_delay_ps[1].soc_bit_vref =
1128 {
1129 0, 40, 40, 40, 40, 40, 40, 40,
1130 40, 40, 40, 40, 40, 40, 40, 40,
1131 40, 40, 40, 40, 40, 40, 40, 40,
1132 40, 40, 40, 40, 40, 40, 40, 40,
1133 40, 40, 40, 40, 40, 40, 40, 40,
1134 40, 40, 40, 40
1135 }, //total 44
1136 .cfg_ddr_training_delay_ps[1].dram_bit_vref =
1137 {
1138 0, 32, 32, 32, 32, 32, 32, 32,
1139 32, 32, 32, 32, 32, 32, 32, 32,
1140 32, 32, 32, 32, 32, 32, 32, 32,
1141 32, 32, 32, 32, 32, 32, 32, 32,
1142 32, 32, 32, 32
1143 }, //total 36
1144 .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
1145},
1146};
1147
1148board_clk_set_t __board_clk_setting
1149__attribute__ ((section(".clk_param"))) = {
1150 /* clock settings for bl2 */
1151 .cpu_clk = CPU_CLK / 24 * 24,
1152#ifdef CONFIG_PXP_DDR
1153 .pxp = 1,
1154#else
1155 .pxp = 0,
1156#endif
1157 .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
1158};
1159
1160
1161#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
1162#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
1163/* VCCK PWM table */
1164#if (VCCK_VAL == 1039)
1165 #define VCCK_VAL_REG 0x00000022
1166#elif (VCCK_VAL == 1029)
1167 #define VCCK_VAL_REG 0x00010021
1168#elif (VCCK_VAL == 1019)
1169 #define VCCK_VAL_REG 0x00020020
1170#elif (VCCK_VAL == 1009)
1171 #define VCCK_VAL_REG 0x0003001f
1172#elif (VCCK_VAL == 999)
1173 #define VCCK_VAL_REG 0x0004001e
1174#elif (VCCK_VAL == 989)
1175 #define VCCK_VAL_REG 0x0005001d
1176#elif (VCCK_VAL == 979)
1177 #define VCCK_VAL_REG 0x0006001c
1178#elif (VCCK_VAL == 969)
1179 #define VCCK_VAL_REG 0x0007001b
1180#elif (VCCK_VAL == 959)
1181 #define VCCK_VAL_REG 0x0008001a
1182#elif (VCCK_VAL == 949)
1183 #define VCCK_VAL_REG 0x00090019
1184#elif (VCCK_VAL == 939)
1185 #define VCCK_VAL_REG 0x000a0018
1186#elif (VCCK_VAL == 929)
1187 #define VCCK_VAL_REG 0x000b0017
1188#elif (VCCK_VAL == 919)
1189 #define VCCK_VAL_REG 0x000c0016
1190#elif (VCCK_VAL == 909)
1191 #define VCCK_VAL_REG 0x000d0015
1192#elif (VCCK_VAL == 899)
1193 #define VCCK_VAL_REG 0x000e0014
1194#elif (VCCK_VAL == 889)
1195 #define VCCK_VAL_REG 0x000f0013
1196#elif (VCCK_VAL == 879)
1197 #define VCCK_VAL_REG 0x00100012
1198#elif (VCCK_VAL == 869)
1199 #define VCCK_VAL_REG 0x00110011
1200#elif (VCCK_VAL == 859)
1201 #define VCCK_VAL_REG 0x00120010
1202#elif (VCCK_VAL == 849)
1203 #define VCCK_VAL_REG 0x0013000f
1204#elif (VCCK_VAL == 839)
1205 #define VCCK_VAL_REG 0x0014000e
1206#elif (VCCK_VAL == 829)
1207 #define VCCK_VAL_REG 0x0015000d
1208#elif (VCCK_VAL == 819)
1209 #define VCCK_VAL_REG 0x0016000c
1210#elif (VCCK_VAL == 809)
1211 #define VCCK_VAL_REG 0x0017000b
1212#elif (VCCK_VAL == 799)
1213 #define VCCK_VAL_REG 0x0018000a
1214#elif (VCCK_VAL == 789)
1215 #define VCCK_VAL_REG 0x00190009
1216#elif (VCCK_VAL == 779)
1217 #define VCCK_VAL_REG 0x001a0008
1218#elif (VCCK_VAL == 769)
1219 #define VCCK_VAL_REG 0x001b0007
1220#elif (VCCK_VAL == 759)
1221 #define VCCK_VAL_REG 0x001c0006
1222#elif (VCCK_VAL == 749)
1223 #define VCCK_VAL_REG 0x001d0005
1224#elif (VCCK_VAL == 739)
1225 #define VCCK_VAL_REG 0x001e0004
1226#elif (VCCK_VAL == 729)
1227 #define VCCK_VAL_REG 0x001f0003
1228#elif (VCCK_VAL == 719)
1229 #define VCCK_VAL_REG 0x00200002
1230#elif (VCCK_VAL == 709)
1231 #define VCCK_VAL_REG 0x00210001
1232#elif (VCCK_VAL == 699)
1233 #define VCCK_VAL_REG 0x00220000
1234#else
1235 #error "VCCK val out of range\n"
1236#endif
1237
1238/* VDDEE_VAL_REG */
1239#if (VDDEE_VAL == 700)
1240 #define VDDEE_VAL_REG 0x120000
1241#elif (VDDEE_VAL == 710)
1242 #define VDDEE_VAL_REG 0x110001
1243#elif (VDDEE_VAL == 720)
1244 #define VDDEE_VAL_REG 0x100002
1245#elif (VDDEE_VAL == 730)
1246 #define VDDEE_VAL_REG 0xf0003
1247#elif (VDDEE_VAL == 740)
1248 #define VDDEE_VAL_REG 0xe0004
1249#elif (VDDEE_VAL == 750)
1250 #define VDDEE_VAL_REG 0xd0005
1251#elif (VDDEE_VAL == 760)
1252 #define VDDEE_VAL_REG 0xc0006
1253#elif (VDDEE_VAL == 770)
1254 #define VDDEE_VAL_REG 0xb0007
1255#elif (VDDEE_VAL == 780)
1256 #define VDDEE_VAL_REG 0xa0008
1257#elif (VDDEE_VAL == 790)
1258 #define VDDEE_VAL_REG 0x90009
1259#elif (VDDEE_VAL == 800)
1260 #define VDDEE_VAL_REG 0x8000a
1261#elif (VDDEE_VAL == 810)
1262 #define VDDEE_VAL_REG 0x7000b
1263#elif (VDDEE_VAL == 820)
1264 #define VDDEE_VAL_REG 0x6000c
1265#elif (VDDEE_VAL == 830)
1266 #define VDDEE_VAL_REG 0x5000d
1267#elif (VDDEE_VAL == 840)
1268 #define VDDEE_VAL_REG 0x4000e
1269#elif (VDDEE_VAL == 850)
1270 #define VDDEE_VAL_REG 0x3000f
1271#elif (VDDEE_VAL == 860)
1272 #define VDDEE_VAL_REG 0x20010
1273#elif (VDDEE_VAL == 870)
1274 #define VDDEE_VAL_REG 0x10011
1275#elif (VDDEE_VAL == 880)
1276 #define VDDEE_VAL_REG 0x12
1277#else
1278 #error "VDDEE val out of range\n"
1279#endif
1280
1281bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
1282 //hxbao, need fine tune
1283 {0, 0, 0xffffffff, 0, 0, 0},
1284};
1285
1286/* gpio/pinmux/pwm init */
1287register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
1288__attribute__ ((section(".misc_param"))) = {
1289
1290 /* config vddee and vcck pwm - pwm_h and pwm_j*/
1291 {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
1292 {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
1293 {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
1294 {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
1295 /* set pwm h and pwm j clock rate to 24M, enable them */
1296 {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 24), 0xffffffff, 0, 0, 0},
1297 {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 24) , 0xffffffff, 0, 0, 0},
1298 /* set GPIOE_0 GPIOE_1 drive strength to 3 */
1299 {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
1300 /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
1301 {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
1302 {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
1303};
1304
1305#define DEV_FIP_SIZE 0x300000
1306#define DDR_FIP_SIZE 0x40000
1307/* for all the storage parameter */
1308storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
1309 .common = {
1310 .version = 0x01,
1311 .device_fip_container_size = DEV_FIP_SIZE,
1312 .device_fip_container_copies = 4,
1313 .ddr_fip_container_size = DDR_FIP_SIZE,
1314 },
1315 .nand = {
1316 .version = 0x01,
1317 .bbt_pages = 0x1,
1318 .bbt_start_block = 20,
1319 .discrete_mode = 1,
1320 .setup_data.nand_setup_data = (2 << 20) | \
1321 (0 << 19) | \
1322 (1 << 17) | \
1323 (1 << 14) | \
1324 (0 << 13) | \
1325 (64 << 6) | \
1326 (4 << 0),
1327 .reserved_area_blk_cnt = 48,
1328 .page_per_block = 64,
1329 .use_param_page_list = 0,
1330 },
1331};