arch/arm64/boot/dts/synaptics/as370-pcie-evk.dts

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2018 Synaptics Incorporated
 *
 * Author: Jisheng Zhang <jszhang@kernel.org>
 */

/dts-v1/;

/memreserve/ 0x1ff00000 0x00100000;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

#include "as370-evk.dtsi"


/ {
	model = "Synaptics AS370 EVK";
	compatible = "syna,as370-evk", "syna,as370";

	ion {
		compatible = "syna,ion-berlin-heaps";
		pool-num = <1>;
		reg-names = "NonSecure";
		reg = <0 0x1ff00000 0 0x100000>;
		attributes-num-per-pool = <2>;
		pool-attributes = <0x00000102 0x00000F36>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		vmmc_sdio0: vmmc_sdio0 {
			compatible = "regulator-fixed";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-name = "vmmc_sdio0";
			enable-active-high;
			regulator-boot-on;
			gpio = <&portb 31 GPIO_ACTIVE_HIGH>;
		};

		vqmmc_sdio0: vqmmc_sdio0 {
			compatible = "regulator-gpio";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <3300000>;
			regulator-name = "vqmmc_sdio0";
			regulator-type = "voltage";
			enable-active-high;
			gpios = <&portb 15 GPIO_ACTIVE_HIGH>;
			states = <3300000 0x1
				  1800000 0x0>;
		};
	};
};

&pinctrl {
	pcie0_gpio_pmux: pcie0_gpio-pmux {
		groups = "PWM2";
		function = "gpio";
	};

	sd0_pmux: sd0-pmux {
		groups = "SD0_CLK", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "SD0_CMD";
		function = "sd0";
	};

	sd0_gpio_pmux: sd0_gpio-pmux {
		groups = "SD0_WP", "PWM5", "SD0_CDn";
		function = "gpio";
	};
};

&pcie_phy0 {
	status = "okay";
};

&pcie0 {
	status = "okay";
	pinctrl-0 = <&pcie0_gpio_pmux>;
	pinctrl-names = "default";
	reset-gpios = <&portb 12 GPIO_ACTIVE_LOW>;
};

&sdhci0 {
	status = "okay";
	wp-inverted;
	cd-gpios = <&portb 30 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&vmmc_sdio0>;
	vqmmc-supply = <&vqmmc_sdio0>;
	pinctrl-0 = <&sd0_pmux>, <&sd0_gpio_pmux>;
	pinctrl-names = "default";
};