| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2018 Synaptics Incorporated |
| * |
| * Author: Jisheng Zhang <jszhang@kernel.org> |
| */ |
| |
| #include <dt-bindings/clock/as370.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| compatible = "syna,as370"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| operating-points-v2 = <&cpu_opp_table>; |
| clocks = <&cpupll 0>; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| operating-points-v2 = <&cpu_opp_table>; |
| clocks = <&cpupll 0>; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x2>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| operating-points-v2 = <&cpu_opp_table>; |
| clocks = <&cpupll 0>; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x3>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| cpu-idle-states = <&CPU_SLEEP_0>; |
| operating-points-v2 = <&cpu_opp_table>; |
| clocks = <&cpupll 0>; |
| }; |
| |
| l2: l2-cache0 { |
| compatible = "cache"; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| CPU_SLEEP_0: cpu-sleep-0 { |
| compatible = "arm,idle-state"; |
| local-timer-stop; |
| arm,psci-suspend-param = <0x0010000>; |
| entry-latency-us = <75>; |
| exit-latency-us = <155>; |
| min-residency-us = <50000>; |
| }; |
| }; |
| |
| cpu_opp_table: opp_table0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp@400000000 { |
| opp-hz = /bits/ 64 <400000000>; |
| opp-microvolt = <825000 825000 900000>; |
| clock-latency-ns = <17500000>; |
| }; |
| |
| opp@800000000 { |
| opp-hz = /bits/ 64 <800000000>; |
| opp-microvolt = <825000 825000 900000>; |
| clock-latency-ns = <17500000>; |
| }; |
| |
| opp@1200000000 { |
| opp-hz = /bits/ 64 <1200000000>; |
| opp-microvolt = <825000 825000 900000>; |
| clock-latency-ns = <17500000>; |
| }; |
| |
| opp@1400000000 { |
| opp-hz = /bits/ 64 <1400000000>; |
| opp-microvolt = <825000 825000 900000>; |
| clock-latency-ns = <17500000>; |
| }; |
| |
| opp@1500000000 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-microvolt = <900000 900000 900000>; |
| clock-latency-ns = <17500000>; |
| }; |
| |
| opp@1800000000 { |
| opp-hz = /bits/ 64 <1800000000>; |
| opp-microvolt = <900000 900000 900000>; |
| clock-latency-ns = <17500000>; |
| }; |
| }; |
| }; |
| |
| chosen { |
| bootargs = "console=ttyS0,115200"; |
| }; |
| |
| osc: osc { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <25000000>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&cpu0>, |
| <&cpu1>, |
| <&cpu2>, |
| <&cpu3>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0xf7000000 0x1000000 |
| 0xe0000000 0 0xe0000000 0x10000000>; |
| |
| apll0: apll0 { |
| compatible = "syna,as370-pll"; |
| reg = <0x420008 0x18>, <0x420044 0x4>; |
| #clock-cells = <1>; |
| clocks = <&osc>; |
| bypass-shift = /bits/ 8 <2>; |
| }; |
| |
| apll1: apll1 { |
| compatible = "syna,as370-pll"; |
| reg = <0x420028 0x18>, <0x420044 0x4>; |
| #clock-cells = <1>; |
| clocks = <&osc>; |
| bypass-shift = /bits/ 8 <3>; |
| }; |
| |
| axi_meter: axi_meter { |
| compatible = "syna,as370-axi-meter"; |
| reg = <0x940000 0x200>; |
| status = "disabled"; |
| }; |
| |
| aviodrv: aviodrv { |
| compatible = "marvell,berlin-avio"; |
| reg = <0x400000 0x200000>; |
| status = "disabled"; |
| }; |
| |
| avio@400000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x400000 0x100000>; |
| |
| avio64b_dhub@40000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x0 0x20000>; |
| |
| dhubctr_a: interrupt-controller@10000 { |
| compatible = "syna,as370-dhub-irq"; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x10000 0x418>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| }; |
| }; |
| |
| as370_outdai: as370-outdai { |
| compatible = "syna,as370-outdai"; |
| status = "disabled"; |
| interrupt-parent = <&dhubctr_a>; |
| reg = <0x40000 0x28>, |
| <0x4012C 0x4>, |
| <0x40138 0x4>, |
| <0x40044 0x10>, |
| <0x40164 0x4>, |
| <0x20000 0x5C>; |
| reg-names = "pri_base", |
| "pri_bclk", |
| "pri_fsync", |
| "spdif_base", |
| "pri_mclk", |
| "avioGbl_base"; |
| interrupts = <0>, <0xE>; |
| interrupt-names = "pri", "spdifo"; |
| }; |
| |
| as370_sec: as370-sec { |
| compatible = "syna,as370-sec"; |
| status = "disabled"; |
| interrupt-parent = <&dhubctr_a>; |
| reg = <0x40028 0x1C>, |
| <0x40130 0x4>, |
| <0x4013C 0x4>, |
| <0x4015C 0x4>, |
| <0x2005C 0x4>; |
| reg-names = "sec_base", |
| "sec_bclk", |
| "sec_fsync", |
| "sec_src", |
| "sec_oen"; |
| interrupts = <0x7>; |
| }; |
| |
| as370_mic1_0: as370-mic1-0 { |
| compatible = "syna,as370-mic1"; |
| status = "disabled"; |
| interrupt-parent = <&dhubctr_a>; |
| reg = <0x40054 0x3C>, |
| <0x40134 0x4>, |
| <0x40140 0x4>, |
| <0x40160 0x4>; |
| reg-names = "mic1_base", |
| "mic1_bclk", |
| "mic1_fsync", |
| "pdmmic_sel"; |
| interrupts = <0x4>; |
| }; |
| |
| as370_mic2: as370-mic2 { |
| compatible = "syna,as370-mic2"; |
| status = "disabled"; |
| interrupt-parent = <&dhubctr_a>; |
| reg = <0x40090 0x30>, |
| <0x40144 0x4>, |
| <0x40148 0x4>; |
| reg-names = "mic2_base", |
| "mic2_fsync", |
| "mic2_bclk"; |
| interrupts = <0xC>; |
| }; |
| |
| as370_pdmi0: as370-pdmi-0 { |
| compatible = "syna,as370-pdmi"; |
| status = "disabled"; |
| interrupt-parent = <&dhubctr_a>; |
| reg = <0x400c0 0x30>, |
| <0x4014c 0x4>, |
| <0x40160 0x4>; |
| reg-names = "pdm_base", |
| "iosel_pdm", |
| "pdmmic_sel"; |
| interrupts = <0xA>, <0xB>, <0x6>, <0x9>; |
| }; |
| |
| as370_pdmi1: as370-pdmi-1 { |
| compatible = "syna,as370-pdmi"; |
| status = "disabled"; |
| interrupt-parent = <&dhubctr_a>; |
| reg = <0x400c0 0x30>, |
| <0x4014c 0x4>, |
| <0x40160 0x4>; |
| reg-names = "pdm_base", |
| "iosel_pdm", |
| "pdmmic_sel"; |
| interrupts = <0xB>; |
| }; |
| |
| as370_pcm: as370-pcm { |
| compatible = "syna,as370-pcm"; |
| status = "disabled"; |
| interrupt-parent = <&dhubctr_a>; |
| }; |
| |
| as370_asoc: as370-asoc { |
| compatible = "syna,as370-asoc"; |
| status = "disabled"; |
| interrupt-parent = <&dhubctr_a>; |
| }; |
| }; |
| |
| gic: interrupt-controller@901000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x901000 0x1000>, |
| <0x902000 0x2000>, |
| <0x904000 0x2000>, |
| <0x906000 0x2000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| cpupll: cpupll { |
| compatible = "syna,as370-pll"; |
| reg = <0x922000 0x18>, <0xea0518 0x4>; |
| #clock-cells = <1>; |
| clocks = <&osc>; |
| bypass-shift = /bits/ 8 <2>; |
| }; |
| |
| mempll: mempll { |
| compatible = "syna,as370-pll"; |
| reg = <0x940004 0x18>, <0xea0518 0x4>; |
| #clock-cells = <1>; |
| clocks = <&osc>; |
| bypass-shift = /bits/ 8 <1>; |
| }; |
| |
| sdhci2: sdhci@aa0000 { |
| compatible = "snps,dwcmshc-sdhci"; |
| reg = <0xaa0000 0x1000>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_EMMC>, <&gateclk CLK_EMMCSYS>; |
| clock-names = "core", "bus"; |
| resets = <&chip 0x49c 11 0 0>; |
| bus-width = <8>; |
| non-removable; |
| no-sd; |
| no-sdio; |
| status = "disabled"; |
| }; |
| |
| sdhci0: sdhci@ab0000 { |
| compatible = "snps,dwcmshc-sdhci"; |
| reg = <0xab0000 0x200>; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_SD0>, <&gateclk CLK_SDIOSYS>; |
| clock-names = "core", "bus"; |
| resets = <&chip 0x49c 4 0 0>; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| pcie0: pcie@e10000 { |
| compatible = "syna,as370-pcie"; |
| reg = <0xe10000 0x8000>, <0xe1a000 0x58>, <0xe0000000 0x00800000>; |
| reg-names = "dbi", "ctrl", "config"; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk CLK_PCIE0SYS>; |
| resets = <&chip 0x508 0 1 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| num-lanes = <1>; |
| device_type = "pci"; |
| ranges = <0x81000000 0 0 0xe0800000 0 0x00800000 |
| 0x82000000 0 0xe1000000 0xe1000000 0 0x07000000>; |
| phys = <&pcie_phy0>; |
| phy-names = "pcie-phy"; |
| status = "disabled"; |
| }; |
| |
| pcie_phy0: phy@e20000 { |
| compatible = "syna,as370-pcie-phy"; |
| reg = <0xe20000 0x20000>; |
| resets = <&chip 0x508 5 1 0>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pcie_phy1: phy@e40000 { |
| compatible = "syna,as370-pcie-phy"; |
| reg = <0xe40000 0x20000>; |
| resets = <&chip 0x508 6 1 0>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pcie1: pcie@e60000 { |
| compatible = "syna,as370-pcie"; |
| reg = <0xe60000 0x8000>, <0xe6a000 0x58>, <0xe8000000 0x00800000>; |
| reg-names = "dbi", "ctrl", "config"; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk CLK_PCIE1SYS>; |
| resets = <&chip 0x508 1 1 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| num-lanes = <1>; |
| device_type = "pci"; |
| ranges = <0x81000000 0 0 0xe8800000 0 0x00800000 |
| 0x82000000 0 0xe9000000 0xe9000000 0 0x07000000>; |
| phys = <&pcie_phy1>; |
| phy-names = "pcie-phy"; |
| status = "disabled"; |
| }; |
| |
| apb@e80000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0xe80000 0x10000>; |
| |
| watchdog0: watchdog@0400 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x0400 0x100>; |
| clocks = <&osc>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@0800 { |
| compatible = "snps,designware-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0800 0x100>; |
| clocks = <&clk CLK_APBCORE>; |
| i2c-sda-hold-time-ns = <449>; |
| i2c-sda-falling-time-ns = <425>; |
| i2c-scl-falling-time-ns = <205>; |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| uart0: uart@0c00 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x0c00 0x100>; |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&osc>; |
| reg-shift = <2>; |
| no-suspend-resume; |
| status = "disabled"; |
| }; |
| |
| watchdog1: watchdog@1000 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x1000 0x100>; |
| clocks = <&osc>; |
| status = "disabled"; |
| }; |
| |
| watchdog2: watchdog@1400 { |
| compatible = "snps,dw-wdt"; |
| reg = <0x1400 0x100>; |
| clocks = <&osc>; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@1800 { |
| compatible = "snps,dw-apb-gpio"; |
| dev_name = "gpio_soc_0"; |
| reg = <0x1800 0x400>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| porta: gpio-port@0 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| snps,nr-gpios = <32>; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| timer0: timer@1c00 { |
| compatible = "snps,dw-apb-timer"; |
| reg = <0x1c00 0x14>; |
| clocks = <&clk CLK_APBCORE>; |
| clock-names = "timer"; |
| interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| timer1: timer@1c14 { |
| compatible = "snps,dw-apb-timer"; |
| reg = <0x1c14 0x14>; |
| clocks = <&clk CLK_APBCORE>; |
| clock-names = "timer"; |
| status = "disabled"; |
| }; |
| |
| timer2: timer@1c28 { |
| compatible = "snps,dw-apb-timer"; |
| reg = <0x1c28 0x14>; |
| clocks = <&clk CLK_APBCORE>; |
| clock-names = "timer"; |
| status = "disabled"; |
| }; |
| |
| timer3: timer@1c3c { |
| compatible = "snps,dw-apb-timer"; |
| reg = <0x1c3c 0x14>; |
| clocks = <&clk CLK_APBCORE>; |
| clock-names = "timer"; |
| status = "disabled"; |
| }; |
| |
| gpio1: gpio@2000 { |
| compatible = "snps,dw-apb-gpio"; |
| dev_name = "gpio_soc_1"; |
| reg = <0x2000 0x400>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| portb: gpio-port@1 { |
| compatible = "snps,dw-apb-gpio-port"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| snps,nr-gpios = <32>; |
| reg = <0>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| i2c0: i2c@2800 { |
| compatible = "snps,designware-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x2800 0x100>; |
| clocks = <&clk CLK_APBCORE>; |
| i2c-sda-hold-time-ns = <449>; |
| i2c-sda-falling-time-ns = <425>; |
| i2c-scl-falling-time-ns = <205>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| uart1: uart@2c00 { |
| compatible = "snps,dw-apb-uart"; |
| reg = <0x2c00 0x100>; |
| interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_APBCORE>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@3000 { |
| compatible = "snps,dw-apb-ssi"; |
| reg = <0x3000 0x100>; |
| num-cs = <4>; |
| clocks = <&clk CLK_APBCORE>; |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| chipid@ea0000 { |
| compatible = "marvell,berlin-chipid"; |
| reg = <0xea0000 12>; |
| }; |
| |
| chip: chip-control@ea0000 { |
| compatible = "marvell,berlin4ct-chip-ctrl"; |
| reg = <0xea0000 0x10000>; |
| #reset-cells = <4>; |
| }; |
| |
| syspll: syspll { |
| compatible = "syna,as370-pll"; |
| reg = <0xea0088 0x18>, <0xea0518 0x4>; |
| #clock-cells = <1>; |
| clocks = <&osc>; |
| bypass-shift = /bits/ 8 <0>; |
| }; |
| |
| gateclk: gateclk { |
| compatible = "syna,as370-gateclk"; |
| reg = <0xea0514 0x4>; |
| #clock-cells = <1>; |
| }; |
| |
| clk: clk { |
| compatible = "syna,as370-clk"; |
| reg = <0xea051c 0x5c>; |
| #clock-cells = <1>; |
| clocks = <&syspll 0>, <&apll0 1>, <&apll1 1>, <&mempll 1>, <&cpupll 1>, <&syspll 1>; |
| }; |
| |
| adc: adc { |
| compatible = "syna,as370-adc"; |
| reg = <0xea0800 0x10>; |
| interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| #io-channel-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| hwmon@ea0810 { |
| compatible = "syna,as370-hwmon"; |
| reg = <0xea0810 0xc>; |
| }; |
| |
| pinctrl: pinctrl@ea0840 { |
| compatible = "syna,as370-soc-pinctrl"; |
| reg = <0xea0840 0x20>; |
| }; |
| |
| usb0: usb@ed0000 { |
| compatible = "syna,berlin-usb"; |
| reg = <0xed0000 0x8000>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gateclk CLK_USB0CORE>; |
| clock-names = "otg"; |
| phys = <&usb_phy0>; |
| phy-names = "usb2-phy"; |
| resets = <&chip 0x508 2 1 0>, <&chip 0x508 3 1 0>; |
| reset-names = "dwc2", "dwc2-ecc"; |
| dr_mode = "otg"; |
| g-rx-fifo-size = <512>; |
| g-np-tx-fifo-size = <64>; |
| g-tx-fifo-size = <256 256 256 256 256 128 64 64 |
| 64 64 64 64 64 64 64>; |
| status = "disabled"; |
| }; |
| |
| usb_phy0: phy@ed8000 { |
| compatible = "syna,as370-usb2-phy"; |
| reg = <0xed8000 0x100>; |
| #phy-cells = <0>; |
| resets = <&chip 0x508 4 1 1>; |
| reset-names = "phy"; |
| status = "disabled"; |
| }; |
| |
| nand0: nand@f10000 { |
| compatible = "cdns,hpnfc-dt"; |
| reg = <0xf10000 0x10000>, <0xf00000 0x10000>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_NFCCORE>, <&clk CLK_NFCECC>, <&gateclk CLK_NFCSYS>; |
| clock-names = "core", "ecc", "sys"; |
| resets = <&chip 0x49c 2 0 0>, <&chip 0x49c 3 0 0>; |
| reset-names = "host", "reg"; |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm@f20000 { |
| compatible = "marvell,berlin-pwm"; |
| reg = <0xf20000 0x40>; |
| clocks = <&clk CLK_CFG>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| nna: nna@f30000 { |
| compatible = "vivante,galcore"; |
| reg = <0xf30000 0x10000>; |
| resets = <&chip 0x504 0 1 0>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk CLK_NNASYS>, <&clk CLK_NNACORE>; |
| clock-names = "sys", "core"; |
| status = "disabled"; |
| }; |
| |
| pwm1: pwm@f40000 { |
| compatible = "marvell,berlin-pwm"; |
| reg = <0xf40000 0x40>; |
| clocks = <&clk CLK_CFG>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
