| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* Copyright (C) 2019 Synaptics Incorporated */ |
| |
| #ifndef acpuview_memmap_h |
| #define acpuview_memmap_h (){} |
| |
| #pragma pack(1) |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #ifndef _DOCC_H_BITOPS_ |
| #define _DOCC_H_BITOPS_ (){} |
| |
| #define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0) |
| #define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb)) |
| #define _bCLRMASK_(b) (~_bSETMASK_(b)) |
| #define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb)) |
| #define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb))) |
| #define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0) |
| |
| #endif |
| |
| |
| |
| ////// |
| /// |
| /// $INTERFACE ACPU_MEMMAP (4,4) |
| /// # # ---------------------------------------------------------- |
| /// : SPICTL_REG_BASE 0xF8200000 |
| /// ### |
| /// * Base address of SPICTL Registers |
| /// * 4KB |
| /// ### |
| /// : SPICTL_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of SPICTL Registers |
| /// ### |
| /// : SPICTL_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : I3CTL0_REG_BASE 0xF8201000 |
| /// ### |
| /// * Base address of I3CTL0 Registers |
| /// * 4KB |
| /// ### |
| /// : I3CTL0_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of I3CTL0 Registers |
| /// ### |
| /// : I3CTL0_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : I3CTL1_REG_BASE 0xF8202000 |
| /// ### |
| /// * Base address of I3CTL1 Registers |
| /// * 4KB |
| /// ### |
| /// : I3CTL1_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of I3CTL1 Registers |
| /// ### |
| /// : I3CTL1_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : AUDDMA_REG_BASE 0xF8300000 |
| /// ### |
| /// * Base address of AUDDMA Registers |
| /// * 8KB |
| /// ### |
| /// : AUDDMA_REG_SIZE 0x2000 |
| /// ### |
| /// * Size of AUDDMA Registers |
| /// ### |
| /// : AUDDMA_REG_DEC_BIT 0xD |
| /// ### |
| /// * 8KB has 13-bit offset |
| /// ### |
| /// : SAIF00_REG_BASE 0xF8302000 |
| /// ### |
| /// * Base address of SAIF00 Registers |
| /// * 4KB |
| /// ### |
| /// : SAIF00_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of SAIF00 Registers |
| /// ### |
| /// : SAIF00_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : DIGMIC_REG_BASE 0xF8303000 |
| /// ### |
| /// * Base address of DIGMIC Registers |
| /// * 4KB |
| /// ### |
| /// : DIGMIC_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of DIGMIC Registers |
| /// ### |
| /// : DIGMIC_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : TIMERS_REG_BASE 0xF8310000 |
| /// ### |
| /// * Base address of TIMERS Registers |
| /// * 4KB |
| /// ### |
| /// : TIMERS_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of TIMERS Registers |
| /// ### |
| /// : TIMERS_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : RTCTRL_REG_BASE 0xF8311000 |
| /// ### |
| /// * Base address of RTCTRL Registers |
| /// * 4KB |
| /// ### |
| /// : RTCTRL_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of RTCTRL Registers |
| /// ### |
| /// : RTCTRL_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : PWRMGT_REG_BASE 0xF8312000 |
| /// ### |
| /// * Base address of PWRMGT Registers |
| /// * 4KB |
| /// ### |
| /// : PWRMGT_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of PWRMGT Registers |
| /// ### |
| /// : PWRMGT_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : INTROU_REG_BASE 0xF8313000 |
| /// ### |
| /// * Base address of INTROU Registers |
| /// * 4KB |
| /// ### |
| /// : INTROU_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of INTROU Registers |
| /// ### |
| /// : INTROU_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : IPCTRL_REG_BASE 0xF8314000 |
| /// ### |
| /// * Base address of IPCTRL Registers |
| /// * 4KB |
| /// ### |
| /// : IPCTRL_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of IPCTRL Registers |
| /// ### |
| /// : IPCTRL_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : SECCFG_REG_BASE 0xF8315000 |
| /// ### |
| /// * Base address of SECCFG Registers |
| /// * 4KB |
| /// ### |
| /// : SECCFG_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of SECCFG Registers |
| /// ### |
| /// : SECCFG_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : FABCTL_REG_BASE 0xF8316000 |
| /// ### |
| /// * Base address of FABCTL Registers |
| /// * 4KB |
| /// ### |
| /// : FABCTL_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of FABCTL Registers |
| /// ### |
| /// : FABCTL_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : M33WRP_REG_BASE 0xF8317000 |
| /// ### |
| /// * Base address of M33WRP Registers |
| /// * 4KB |
| /// ### |
| /// : M33WRP_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of M33WRP Registers |
| /// ### |
| /// : M33WRP_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : SMMISC_REG_BASE 0xF8318000 |
| /// ### |
| /// * Base address of SMMISC Registers |
| /// * Note: It is not used in current project. |
| /// * 4KB |
| /// ### |
| /// : SMMISC_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of SMMISC Registers |
| /// * Note: It is not used in current project. |
| /// ### |
| /// : SMMISC_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// * Note: It is not used in current project. |
| /// ### |
| /// : PVTSNR_REG_BASE 0xF8319000 |
| /// ### |
| /// * Base address of PVTSNR Registers |
| /// * 4KB |
| /// ### |
| /// : PVTSNR_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of PVTSNR Registers |
| /// ### |
| /// : PVTSNR_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : BLKRAM_0_BASE 0x3FF00000 |
| /// ### |
| /// * Base address of BLKRAM_0 |
| /// * 128KB |
| /// ### |
| /// : BLKRAM_0_SIZE 0x20000 |
| /// ### |
| /// * Size of BLKRAM_0 |
| /// ### |
| /// : BLKRAM_0_DEC_BIT 0x11 |
| /// ### |
| /// * 128KB has 17-bit offset |
| /// ### |
| /// : BLKRAM_1_BASE 0x3FF20000 |
| /// ### |
| /// * Base address of BLKRAM_1 |
| /// * 128KB |
| /// ### |
| /// : BLKRAM_1_SIZE 0x20000 |
| /// ### |
| /// * Size of BLKRAM_1 |
| /// ### |
| /// : BLKRAM_1_DEC_BIT 0x11 |
| /// ### |
| /// * 128KB has 17-bit offset |
| /// ### |
| /// : BLKRAM_2_BASE 0x3FF40000 |
| /// ### |
| /// * Base address of BLKRAM_2 |
| /// * 128KB |
| /// ### |
| /// : BLKRAM_2_SIZE 0x20000 |
| /// ### |
| /// * Size of BLKRAM_2 |
| /// ### |
| /// : BLKRAM_2_DEC_BIT 0x11 |
| /// ### |
| /// * 128KB has 17-bit offset |
| /// ### |
| /// : BLKRAM_3_BASE 0x3FF60000 |
| /// ### |
| /// * Base address of BLKRAM_3 |
| /// * 128KB |
| /// ### |
| /// : BLKRAM_3_SIZE 0x20000 |
| /// ### |
| /// * Size of BLKRAM_3 |
| /// ### |
| /// : BLKRAM_3_DEC_BIT 0x11 |
| /// ### |
| /// * 128KB has 17-bit offset |
| /// ### |
| /// : BLKRAM_4_BASE 0x3FF80000 |
| /// ### |
| /// * Base address of BLKRAM_4 |
| /// * 128KB |
| /// ### |
| /// : BLKRAM_4_SIZE 0x20000 |
| /// ### |
| /// * Size of BLKRAM_4 |
| /// ### |
| /// : BLKRAM_4_DEC_BIT 0x11 |
| /// ### |
| /// * 128KB has 17-bit offset |
| /// ### |
| /// : BLKRAM_5_BASE 0x3FFA0000 |
| /// ### |
| /// * Base address of BLKRAM_5 |
| /// * 128KB |
| /// ### |
| /// : BLKRAM_5_SIZE 0x20000 |
| /// ### |
| /// * Size of BLKRAM_5 |
| /// ### |
| /// : BLKRAM_5_DEC_BIT 0x11 |
| /// ### |
| /// * 128KB has 17-bit offset |
| /// ### |
| /// : BLKRAM_6_BASE 0x3FFC0000 |
| /// ### |
| /// * Base address of BLKRAM_6 |
| /// * 128KB |
| /// ### |
| /// : BLKRAM_6_SIZE 0x20000 |
| /// ### |
| /// * Size of BLKRAM_6 |
| /// ### |
| /// : BLKRAM_6_DEC_BIT 0x11 |
| /// ### |
| /// * 128KB has 17-bit offset |
| /// ### |
| /// : BLKRAM_7_BASE 0x3FFE0000 |
| /// ### |
| /// * Base address of BLKRAM_7 |
| /// * 128KB |
| /// ### |
| /// : BLKRAM_7_SIZE 0x20000 |
| /// ### |
| /// * Size of BLKRAM_7 |
| /// ### |
| /// : BLKRAM_7_DEC_BIT 0x11 |
| /// ### |
| /// * 128KB has 17-bit offset |
| /// ### |
| /// : GBLRST_REG_BASE 0xF8320000 |
| /// ### |
| /// * Base address of GBLRST Registers |
| /// * 4KB |
| /// ### |
| /// : GBLRST_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of GBLRST Registers |
| /// ### |
| /// : GBLRST_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : GBLCLK_REG_BASE 0xF8321000 |
| /// ### |
| /// * Base address of GBLCLK Registers |
| /// * 4KB |
| /// ### |
| /// : GBLCLK_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of GBLCLK Registers |
| /// ### |
| /// : GBLCLK_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : GBLREG_REG_BASE 0xF8322000 |
| /// ### |
| /// * Base address of GBLREG Registers |
| /// * 4KB |
| /// ### |
| /// : GBLREG_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of GBLREG Registers |
| /// ### |
| /// : GBLREG_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : PADREG_REG_BASE 0xF8323000 |
| /// ### |
| /// * Base address of PADREG Registers |
| /// * 4KB |
| /// ### |
| /// : PADREG_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of PADREG Registers |
| /// ### |
| /// : PADREG_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : OCTSPI_REG_BASE 0xF8330000 |
| /// ### |
| /// * Base address of OCTSPI Registers |
| /// * 4KB |
| /// ### |
| /// : OCTSPI_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of OCTSPI Registers |
| /// ### |
| /// : OCTSPI_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : NANMST_REG_BASE 0xF8331000 |
| /// ### |
| /// * Base address of NANMST Registers |
| /// * 4KB |
| /// ### |
| /// : NANMST_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of NANMST Registers |
| /// ### |
| /// : NANMST_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : UART00_REG_BASE 0xF8332000 |
| /// ### |
| /// * Base address of UART00 Registers |
| /// * 4KB |
| /// ### |
| /// : UART00_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of UART00 Registers |
| /// ### |
| /// : UART00_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : UART01_REG_BASE 0xF8333000 |
| /// ### |
| /// * Base address of UART01 Registers |
| /// * 4KB |
| /// ### |
| /// : UART01_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of UART01 Registers |
| /// ### |
| /// : UART01_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : GPIO00_REG_BASE 0xF8334000 |
| /// ### |
| /// * Base address of GPIO00 Registers |
| /// * 4KB |
| /// ### |
| /// : GPIO00_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of GPIO00 Registers |
| /// ### |
| /// : GPIO00_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : LEDPWM_REG_BASE 0xF8335000 |
| /// ### |
| /// * Base address of LEDPWM Registers |
| /// * 4KB |
| /// ### |
| /// : LEDPWM_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of LEDPWM Registers |
| /// ### |
| /// : LEDPWM_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// ### |
| /// : MONADC_REG_BASE 0xF8336000 |
| /// ### |
| /// * Base address of MONADC Registers |
| /// * Note: It is not used in current project. |
| /// * 4KB |
| /// ### |
| /// : MONADC_REG_SIZE 0x1000 |
| /// ### |
| /// * Size of MONADC Registers |
| /// * Note: It is not used in current project. |
| /// ### |
| /// : MONADC_REG_DEC_BIT 0xC |
| /// ### |
| /// * 4KB has 12-bit offset |
| /// * Note: It is not used in current project. |
| /// ### |
| /// : USBAHB_REG_BASE 0xF8100000 |
| /// ### |
| /// * Base address of USBAHB Registers |
| /// * 512KB |
| /// ### |
| /// : USBAHB_REG_SIZE 0x80000 |
| /// ### |
| /// * Size of USBAHB Registers |
| /// ### |
| /// : USBAHB_REG_DEC_BIT 0x13 |
| /// ### |
| /// * 512KB has 19-bit offset |
| /// ### |
| /// : OSPAHB_REG_BASE 0xF8180000 |
| /// ### |
| /// * Base address of OSPAHB Registers |
| /// * 64KB |
| /// ### |
| /// : OSPAHB_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of OSPAHB Registers |
| /// ### |
| /// : OSPAHB_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : NANAHB_REG_BASE 0xF8190000 |
| /// ### |
| /// * Base address of NANAHB Registers |
| /// * 64KB |
| /// ### |
| /// : NANAHB_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of NANAHB Registers |
| /// ### |
| /// : NANAHB_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 12-bit offset |
| /// ### |
| /// : SDIAHB_REG_BASE 0xF81A0000 |
| /// ### |
| /// * Base address of SDIAHB Registers |
| /// * 64KB |
| /// ### |
| /// : SDIAHB_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of SDIAHB Registers |
| /// ### |
| /// : SDIAHB_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : EMMAHB_REG_BASE 0xF81B0000 |
| /// ### |
| /// * Base address of EMMAHB Registers |
| /// * 64KB |
| /// ### |
| /// : EMMAHB_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of EMMAHB Registers |
| /// ### |
| /// : EMMAHB_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : PXBARAHB_REG_BASE 0xF81C0000 |
| /// ### |
| /// * Base address of PXBARAHB Registers |
| /// * 64KB |
| /// ### |
| /// : PXBARAHB_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of PXBARAHB Registers |
| /// ### |
| /// : PXBARAHB_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : CPUWRP_REG_BASE 0x48200000 |
| /// ### |
| /// * Base address of CPUWRP Registers |
| /// * 64KB |
| /// ### |
| /// : CPUWRP_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of CPUWRP Registers |
| /// ### |
| /// : CPUWRP_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : DSPWRP_REG_BASE 0x48210000 |
| /// ### |
| /// * Base address of DSPWRP Registers |
| /// * 64KB |
| /// ### |
| /// : DSPWRP_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of DSPWRP Registers |
| /// ### |
| /// : DSPWRP_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : DDRWRP_MC_REG_BASE 0x48220000 |
| /// ### |
| /// * Base address of DDRWRP_MC Registers |
| /// * 64KB |
| /// ### |
| /// : DDRWRP_MC_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of DDRWRP_MC Registers |
| /// ### |
| /// : DDRWRP_MC_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 12-bit offset |
| /// ### |
| /// : DDRWRP_PHY_REG_BASE 0x48230000 |
| /// ### |
| /// * Base address of DDRWRP_PHY Registers |
| /// * 64KB |
| /// ### |
| /// : DDRWRP_PHY_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of DDRWRP_PHY Registers |
| /// ### |
| /// : DDRWRP_PHY_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : DDRWRP_MISC_REG_BASE 0x48240000 |
| /// ### |
| /// * Base address of DDRWRP_MISC Registers |
| /// * 64KB |
| /// ### |
| /// : DDRWRP_MISC_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of DDRWRP_MISC Registers |
| /// ### |
| /// : DDRWRP_MISC_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : CPUSSRST_REG_BASE 0x48250000 |
| /// ### |
| /// * Base address of CPUSSRST Registers |
| /// * 64KB |
| /// ### |
| /// : CPUSSRST_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of CPUSSRST Registers |
| /// ### |
| /// : CPUSSRST_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : CPUSSCLK_REG_BASE 0x48260000 |
| /// ### |
| /// * Base address of CPUSSCLK Registers |
| /// * 64KB |
| /// ### |
| /// : CPUSSCLK_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of CPUSSCLK Registers |
| /// ### |
| /// : CPUSSCLK_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : BBGEN_REG_BASE 0x48270000 |
| /// ### |
| /// * Base address of BBGEN Registers |
| /// * 64KB |
| /// ### |
| /// : BBGEN_REG_SIZE 0x10000 |
| /// ### |
| /// * Size of BBGEN Registers |
| /// ### |
| /// : BBGEN_REG_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : MIPISS_REG_BASE 0x48300000 |
| /// ### |
| /// * Base address of MIPISS Registers |
| /// * 512KB |
| /// ### |
| /// : MIPISS_REG_SIZE 0x80000 |
| /// ### |
| /// * Size of MIPISS Registers |
| /// ### |
| /// : MIPISS_REG_DEC_BIT 0x13 |
| /// ### |
| /// * 512KB has 19-bit offset |
| /// ### |
| /// : SISS_BASE 0xF8000000 |
| /// ### |
| /// * Base address of SISS |
| /// * 512K |
| /// ### |
| /// : SISS_SIZE 0x80000 |
| /// ### |
| /// * Size of SISS |
| /// ### |
| /// : SISS_DEC_BIT 0x13 |
| /// ### |
| /// * 512K has 19-bit offset |
| /// ### |
| /// : BOOTVECTOR_BASE 0xFFFF0000 |
| /// ### |
| /// * Base address of BOOTVECTOR |
| /// * 16KB |
| /// ### |
| /// : BOOTVECTOR_SIZE 0x4000 |
| /// ### |
| /// * Size of BOOTVECTOR |
| /// ### |
| /// : BOOTVECTOR_DEC_BIT 0xE |
| /// ### |
| /// * 16KB has 14-bit offset |
| /// ### |
| /// : AHBFAB_APB_REG_BASE 0xF8300000 |
| /// ### |
| /// * Base address of AHBFAB_APB_REG |
| /// * 1MB |
| /// ### |
| /// : AHBFAB_APB_REG_SIZE 0x100000 |
| /// ### |
| /// * Size of AHBFAB_APB_REG |
| /// ### |
| /// : AHBFAB_APB_REG_DEC_BIT 0x14 |
| /// ### |
| /// * 1MB has 20-bit offset |
| /// ### |
| /// : AHBFAB_FASAPB_REG_BASE 0xF8200000 |
| /// ### |
| /// * Base address of AHBFAB_FASAPB_REG |
| /// * 1MB |
| /// ### |
| /// : AHBFAB_FASAPB_REG_SIZE 0x100000 |
| /// ### |
| /// * Size of AHBFAB_CFG_REG |
| /// ### |
| /// : AHBFAB_FASAPB_REG_DEC_BIT 0x14 |
| /// ### |
| /// * 1MB has 20-bit offset |
| /// ### |
| /// : AXI_CFG_REG_BASE 0x48000000 |
| /// ### |
| /// * Base address of AXI_CFG_REG |
| /// * 1MB |
| /// ### |
| /// : AXI_CFG_REG_SIZE 0x400000 |
| /// ### |
| /// * Size of AXI_CFG_REG |
| /// ### |
| /// : AXI_CFG_REG_DEC_BIT 0x16 |
| /// ### |
| /// * 4MB has 22-bit offset |
| /// ### |
| /// : CDXGPV_REG_BASE 0x48000000 |
| /// ### |
| /// * Base address of CDXGPV_REG |
| /// * 1MB |
| /// ### |
| /// : CDXGPV_REG_SIZE 0x100000 |
| /// ### |
| /// * Size of CDXGPV_REG |
| /// ### |
| /// : CDXGPV_REG_DEC_BIT 0x14 |
| /// ### |
| /// * 1MB has 20-bit offset |
| /// ### |
| /// : GIC400_REG_BASE 0x48100000 |
| /// ### |
| /// * Base address of GIC400_REG |
| /// * 1MB |
| /// ### |
| /// : GIC400_REG_SIZE 0x100000 |
| /// ### |
| /// * Size of GIC400_REG |
| /// ### |
| /// : GIC400_REG_DEC_BIT 0x14 |
| /// ### |
| /// * 1MB has 20-bit offset |
| /// ### |
| /// : HIFI_TCM_BASE 0x3FC00000 |
| /// ### |
| /// * Base address of HIFI_TCM |
| /// * 2MB |
| /// ### |
| /// : HIFI_TCM_SIZE 0x200000 |
| /// ### |
| /// * Size of HIFI_TCM |
| /// ### |
| /// : HIFI_TCM_DEC_BIT 0x15 |
| /// ### |
| /// * 2MB has 21-bit offset |
| /// ### |
| /// : BLKROM_BASE 0x3FE00000 |
| /// ### |
| /// * Base address of BLKROM |
| /// * 64KB |
| /// ### |
| /// : BLKROM_SIZE 0x10000 |
| /// ### |
| /// * Size of BLKROM |
| /// ### |
| /// : BLKROM_DEC_BIT 0x10 |
| /// ### |
| /// * 64KB has 16-bit offset |
| /// ### |
| /// : OSPI_FLASH_BASE 0xF0000000 |
| /// ### |
| /// * Base address of OSPI_FLASH |
| /// * 128MB |
| /// ### |
| /// : OSPI_FLASH_SIZE 0x8000000 |
| /// ### |
| /// * Size of OSPI_FLASH |
| /// ### |
| /// : OSPI_FLASH_DEC_BIT 0x1B |
| /// ### |
| /// * 128MB has 27-bit offset |
| /// ### |
| /// : DDR_1020M_BASE 0x0 |
| /// ### |
| /// * Base address of DDR_1020M |
| /// * 1020MB |
| /// ### |
| /// : DDR_1020M_SIZE 0x3FC00000 |
| /// ### |
| /// * Size of DDR_1020M |
| /// ### |
| /// : DDR_1G_BASE 0x80000000 |
| /// ### |
| /// * Base address of DDR_1G |
| /// * 1GB |
| /// ### |
| /// : DDR_1G_SIZE 0x40000000 |
| /// ### |
| /// * Size of DDR_1G |
| /// ### |
| /// : DDR_1G_DEC_BIT 0x1E |
| /// ### |
| /// * 1GB has 30-bit offset |
| /// ### |
| /// : USBPHY_REG_BASE 0xF8140000 |
| /// ### |
| /// * Base address of USBPHY Registers |
| /// * 256KB |
| /// ### |
| /// : USBPHY_REG_SIZE 0x40000 |
| /// ### |
| /// * Size of USBPHY Registers |
| /// ### |
| /// : USBPHY_REG_DEC_BIT 0x12 |
| /// ### |
| /// * 256KB has 18-bit offset |
| /// ### |
| /// : VECTOR_BASE 0xFFFF0000 |
| /// ### |
| /// * Interrupt Vectors Register base |
| /// * 32 bytes |
| /// * 8 vectors, with 0xFFFF0000 pointing to |
| /// * --- external flash on power up for TC1 or |
| /// * --- internal ROM some where Depending on strap pin |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : VECTOR_SIZE 0x20 |
| /// ### |
| /// * Size of Interrupt Vectors Registers |
| /// ### |
| /// : VECTOR_DEC_BIT 0x5 |
| /// ### |
| /// * 32 bytes has a 5 bits offset |
| /// ### |
| /// : HIGH_EXCEPT_RESET_REG 0xFFFF0000 |
| /// ### |
| /// * The first instruction address after reseting |
| /// * Readable/Writable for both software and hardware |
| /// * Default value is 0xe59ff018 {LDR pc, [pc + #0x20 - #8]} |
| /// * Default value is loading the content of 0xFFFF0020 as the PC |
| /// * address |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : HIGH_EXCEPT_UNDEF_REG 0xFFFF0004 |
| /// ### |
| /// * The first instruction address for undefined instruction |
| /// * exception |
| /// * Readable/Writable for both software and hardware |
| /// * Fix value is 0xe59ff018 {LDR pc, [pc + #0x20 - #8]} |
| /// * Fix value is loading the content of 0xFFFF0024 as the PC address |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : HIGH_EXCEPT_SOFT_REG 0xFFFF0008 |
| /// ### |
| /// * The first instruction address for software interrupt exception |
| /// * Readable/Writable for both software and hardware |
| /// * Fix value is 0xe59ff018 {LDR pc, [pc + #0x20 - #8]} |
| /// * Fix value is loading the content of 0xFFFF0028 as the PC address |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : HIGH_EXCEPT_PREFETCH_REG 0xFFFF000C |
| /// ### |
| /// * The first instruction address for instruction fetch memory abort |
| /// * Readable/Writable for both software and hardware |
| /// * Fix value is 0xe59ff018 {LDR pc, [pc + #0x20 - #8]} |
| /// * Fix value is loading the content of 0xFFFF002C as the PC address |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : HIGH_EXCEPT_DATA_REG 0xFFFF0010 |
| /// ### |
| /// * The first instruction address for data access memory abort |
| /// * Readable/Writable for both software and hardware |
| /// * Fix value is 0xe59ff018 {LDR pc, [pc + #0x20 - #8]} |
| /// * Fix value is loading the content of 0xFFFF0030 as the PC address |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : HIGH_EXCEPT_UNUSED_REG 0xFFFF0014 |
| /// ### |
| /// * Fix value is 0xe59ff018 {LDR pc, [pc + #0x20 - #8]} |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : HIGH_EXCEPT_IRQ_REG 0xFFFF0018 |
| /// ### |
| /// * The address for IRQ service routine entry |
| /// * Readable/Writable for both software and hardware |
| /// * Fix value is 0xe59ff018 {LDR pc, [pc + #0x20 - #8]} |
| /// * Fix value is loading the content of 0xFFFF0038 as the PC address |
| /// * ISR will be universal ISR for all CPUs. |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : HIGH_EXCEPT_FIQ_REG 0xFFFF001C |
| /// ### |
| /// * The address for FIQ service routine entry |
| /// * Readable/Writable for both software and hardware |
| /// * Fix value is 0xe59ff018 {LDR pc, [pc + #0x20 - #8]} |
| /// * Fix value is loading the content of 0xFFFF003C as the PC address |
| /// * FIQ service routine will be universal entry for all CPU's FIQ |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : ADDR_DATA_REG_BASE 0xFFFF0020 |
| /// ### |
| /// * Addr_data_?_? Table base address |
| /// * 128 bytes ¨C 3 x 8 registers ¨C 3x8x4=96 |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : ADDR_DATA_REG_SIZE 0x80 |
| /// ### |
| /// * Size of Addr_data_?_? Table |
| /// ### |
| /// : VECTOR_ADDR_0_REG 0xFFFF0020 |
| /// ### |
| /// * Vector address register for reset |
| /// * Software read ONLY/ hardware readable/writable |
| /// * Default value is 0xFFFFC000 (booting from DRAM) |
| /// * 0xFFFFC240 booting from ROM / 0xFFFFC200 booting from others |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : VECTOR_ADDR_1_REG 0xFFFF0024 |
| /// ### |
| /// * Vector address register for undefined instruction |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : VECTOR_ADDR_2_REG 0xFFFF0028 |
| /// ### |
| /// * Vector address register for software interrupt |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : VECTOR_ADDR_3_REG 0xFFFF002C |
| /// ### |
| /// * Vector address register for prefetch abort |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : VECTOR_ADDR_4_REG 0xFFFF0030 |
| /// ### |
| /// * Vector address register for Data Abort |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : VECTOR_ADDR_5_REG 0xFFFF0034 |
| /// ### |
| /// * Not used |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : VECTOR_ADDR_6_REG 0xFFFF0038 |
| /// ### |
| /// * Vector address register for universal IRQ service routine entry |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : VECTOR_ADDR_7_REG 0xFFFF003C |
| /// ### |
| /// * Vector address register for universal FIQ service routine entry |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_1_0_REG 0xFFFF0040 |
| /// ### |
| /// * Undefined Instruction Exception Handler entry address for CPU #0 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_1_1_REG 0xFFFF0044 |
| /// ### |
| /// * Undefined Instruction Exception Handler entry address for CPU #1 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_1_2_REG 0xFFFF0048 |
| /// ### |
| /// * Undefined Instruction Exception Handler entry address for CPU #2 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_2_0_REG 0xFFFF004C |
| /// ### |
| /// * Software Interrupt Exception Handler entry address for CPU #0 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_2_1_REG 0xFFFF0050 |
| /// ### |
| /// * Software Interrupt Exception Handler entry address for CPU #1 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_2_2_REG 0xFFFF0054 |
| /// ### |
| /// * Software Interrupt Exception Handler entry address for CPU #2 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_3_0_REG 0xFFFF0058 |
| /// ### |
| /// * Instruction Prefetch Abort Exception Handler entry address for |
| /// * CPU #0 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_3_1_REG 0xFFFF005C |
| /// ### |
| /// * Instruction Prefetch Abort Exception Handler entry address for |
| /// * CPU #1 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_3_2_REG 0xFFFF0060 |
| /// ### |
| /// * Instruction Prefetch Abort Exception Handler entry address for |
| /// * CPU #2 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_4_0_REG 0xFFFF0064 |
| /// ### |
| /// * Data Abort Exception Handler entry address for CPU #0 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_4_1_REG 0xFFFF0068 |
| /// ### |
| /// * Data Abort Exception Handler entry address for CPU #1 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_4_2_REG 0xFFFF006C |
| /// ### |
| /// * Data Abort Exception Handler entry address for CPU #2 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_5_0_REG 0xFFFF0070 |
| /// ### |
| /// * Not used |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_5_1_REG 0xFFFF0074 |
| /// ### |
| /// * Not used |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_5_2_REG 0xFFFF0078 |
| /// ### |
| /// * Not used |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_6_0_REG 0xFFFF007C |
| /// ### |
| /// * IRQ service routine entry address for CPU #0 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_6_1_REG 0xFFFF0080 |
| /// ### |
| /// * IRQ service routine entry address for CPU #1 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_6_2_REG 0xFFFF0084 |
| /// ### |
| /// * IRQ service routine entry address for CPU #2 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_7_0_REG 0xFFFF0088 |
| /// ### |
| /// * FIQ service routine entry address for CPU #0 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_7_1_REG 0xFFFF008C |
| /// ### |
| /// * FIQ service routine entry address for CPU #1 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// : BRCH_ADDR_7_2_REG 0xFFFF0090 |
| /// ### |
| /// * FIQ service routine entry address for CPU #2 |
| /// * Software and hardware readable and writable |
| /// * **INTERNAL_ONLY*****INTERNAL_ONLY** |
| /// ### |
| /// : SOFTWARE_RESET_ADDR_REG 0xFFFF0094 |
| /// ### |
| /// * After software reset the special CPU or whole system, |
| /// * The CPU(s) will fetch the value of this register as the address |
| /// * of |
| /// * The first instruction. |
| /// * To make it work, please change register HIGH_EXCEPT_RESET_REG |
| /// * (0xFFFF-0000) with value 0xe59ff08C {LDR pc, [pc + #0x94 - #8]} |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// @ 0x00000 memmap (R-) |
| /// %signed 32 dummy 0 |
| /// ### |
| /// * Dummy word for automatically generates header file |
| /// * **INTERNAL_ONLY** |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 4B, bits: 32b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_ACPU_MEMMAP |
| #define h_ACPU_MEMMAP (){} |
| |
| #define ACPU_MEMMAP_SPICTL_REG_BASE 0xF8200000 |
| #define ACPU_MEMMAP_SPICTL_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_SPICTL_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_I3CTL0_REG_BASE 0xF8201000 |
| #define ACPU_MEMMAP_I3CTL0_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_I3CTL0_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_I3CTL1_REG_BASE 0xF8202000 |
| #define ACPU_MEMMAP_I3CTL1_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_I3CTL1_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_AUDDMA_REG_BASE 0xF8300000 |
| #define ACPU_MEMMAP_AUDDMA_REG_SIZE 0x2000 |
| #define ACPU_MEMMAP_AUDDMA_REG_DEC_BIT 0xD |
| #define ACPU_MEMMAP_SAIF00_REG_BASE 0xF8302000 |
| #define ACPU_MEMMAP_SAIF00_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_SAIF00_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_DIGMIC_REG_BASE 0xF8303000 |
| #define ACPU_MEMMAP_DIGMIC_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_DIGMIC_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_TIMERS_REG_BASE 0xF8310000 |
| #define ACPU_MEMMAP_TIMERS_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_TIMERS_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_RTCTRL_REG_BASE 0xF8311000 |
| #define ACPU_MEMMAP_RTCTRL_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_RTCTRL_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_PWRMGT_REG_BASE 0xF8312000 |
| #define ACPU_MEMMAP_PWRMGT_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_PWRMGT_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_INTROU_REG_BASE 0xF8313000 |
| #define ACPU_MEMMAP_INTROU_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_INTROU_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_IPCTRL_REG_BASE 0xF8314000 |
| #define ACPU_MEMMAP_IPCTRL_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_IPCTRL_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_SECCFG_REG_BASE 0xF8315000 |
| #define ACPU_MEMMAP_SECCFG_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_SECCFG_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_FABCTL_REG_BASE 0xF8316000 |
| #define ACPU_MEMMAP_FABCTL_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_FABCTL_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_M33WRP_REG_BASE 0xF8317000 |
| #define ACPU_MEMMAP_M33WRP_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_M33WRP_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_SMMISC_REG_BASE 0xF8318000 |
| #define ACPU_MEMMAP_SMMISC_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_SMMISC_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_PVTSNR_REG_BASE 0xF8319000 |
| #define ACPU_MEMMAP_PVTSNR_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_PVTSNR_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_BLKRAM_0_BASE 0x3FF00000 |
| #define ACPU_MEMMAP_BLKRAM_0_SIZE 0x20000 |
| #define ACPU_MEMMAP_BLKRAM_0_DEC_BIT 0x11 |
| #define ACPU_MEMMAP_BLKRAM_1_BASE 0x3FF20000 |
| #define ACPU_MEMMAP_BLKRAM_1_SIZE 0x20000 |
| #define ACPU_MEMMAP_BLKRAM_1_DEC_BIT 0x11 |
| #define ACPU_MEMMAP_BLKRAM_2_BASE 0x3FF40000 |
| #define ACPU_MEMMAP_BLKRAM_2_SIZE 0x20000 |
| #define ACPU_MEMMAP_BLKRAM_2_DEC_BIT 0x11 |
| #define ACPU_MEMMAP_BLKRAM_3_BASE 0x3FF60000 |
| #define ACPU_MEMMAP_BLKRAM_3_SIZE 0x20000 |
| #define ACPU_MEMMAP_BLKRAM_3_DEC_BIT 0x11 |
| #define ACPU_MEMMAP_BLKRAM_4_BASE 0x3FF80000 |
| #define ACPU_MEMMAP_BLKRAM_4_SIZE 0x20000 |
| #define ACPU_MEMMAP_BLKRAM_4_DEC_BIT 0x11 |
| #define ACPU_MEMMAP_BLKRAM_5_BASE 0x3FFA0000 |
| #define ACPU_MEMMAP_BLKRAM_5_SIZE 0x20000 |
| #define ACPU_MEMMAP_BLKRAM_5_DEC_BIT 0x11 |
| #define ACPU_MEMMAP_BLKRAM_6_BASE 0x3FFC0000 |
| #define ACPU_MEMMAP_BLKRAM_6_SIZE 0x20000 |
| #define ACPU_MEMMAP_BLKRAM_6_DEC_BIT 0x11 |
| #define ACPU_MEMMAP_BLKRAM_7_BASE 0x3FFE0000 |
| #define ACPU_MEMMAP_BLKRAM_7_SIZE 0x20000 |
| #define ACPU_MEMMAP_BLKRAM_7_DEC_BIT 0x11 |
| #define ACPU_MEMMAP_GBLRST_REG_BASE 0xF8320000 |
| #define ACPU_MEMMAP_GBLRST_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_GBLRST_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_GBLCLK_REG_BASE 0xF8321000 |
| #define ACPU_MEMMAP_GBLCLK_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_GBLCLK_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_GBLREG_REG_BASE 0xF8322000 |
| #define ACPU_MEMMAP_GBLREG_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_GBLREG_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_PADREG_REG_BASE 0xF8323000 |
| #define ACPU_MEMMAP_PADREG_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_PADREG_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_OCTSPI_REG_BASE 0xF8330000 |
| #define ACPU_MEMMAP_OCTSPI_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_OCTSPI_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_NANMST_REG_BASE 0xF8331000 |
| #define ACPU_MEMMAP_NANMST_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_NANMST_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_UART00_REG_BASE 0xF8332000 |
| #define ACPU_MEMMAP_UART00_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_UART00_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_UART01_REG_BASE 0xF8333000 |
| #define ACPU_MEMMAP_UART01_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_UART01_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_GPIO00_REG_BASE 0xF8334000 |
| #define ACPU_MEMMAP_GPIO00_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_GPIO00_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_LEDPWM_REG_BASE 0xF8335000 |
| #define ACPU_MEMMAP_LEDPWM_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_LEDPWM_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_MONADC_REG_BASE 0xF8336000 |
| #define ACPU_MEMMAP_MONADC_REG_SIZE 0x1000 |
| #define ACPU_MEMMAP_MONADC_REG_DEC_BIT 0xC |
| #define ACPU_MEMMAP_USBAHB_REG_BASE 0xF8100000 |
| #define ACPU_MEMMAP_USBAHB_REG_SIZE 0x80000 |
| #define ACPU_MEMMAP_USBAHB_REG_DEC_BIT 0x13 |
| #define ACPU_MEMMAP_OSPAHB_REG_BASE 0xF8180000 |
| #define ACPU_MEMMAP_OSPAHB_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_OSPAHB_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_NANAHB_REG_BASE 0xF8190000 |
| #define ACPU_MEMMAP_NANAHB_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_NANAHB_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_SDIAHB_REG_BASE 0xF81A0000 |
| #define ACPU_MEMMAP_SDIAHB_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_SDIAHB_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_EMMAHB_REG_BASE 0xF81B0000 |
| #define ACPU_MEMMAP_EMMAHB_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_EMMAHB_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_PXBARAHB_REG_BASE 0xF81C0000 |
| #define ACPU_MEMMAP_PXBARAHB_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_PXBARAHB_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_CPUWRP_REG_BASE 0x48200000 |
| #define ACPU_MEMMAP_CPUWRP_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_CPUWRP_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_DSPWRP_REG_BASE 0x48210000 |
| #define ACPU_MEMMAP_DSPWRP_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_DSPWRP_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_DDRWRP_MC_REG_BASE 0x48220000 |
| #define ACPU_MEMMAP_DDRWRP_MC_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_DDRWRP_MC_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_DDRWRP_PHY_REG_BASE 0x48230000 |
| #define ACPU_MEMMAP_DDRWRP_PHY_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_DDRWRP_PHY_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_DDRWRP_MISC_REG_BASE 0x48240000 |
| #define ACPU_MEMMAP_DDRWRP_MISC_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_DDRWRP_MISC_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_CPUSSRST_REG_BASE 0x48250000 |
| #define ACPU_MEMMAP_CPUSSRST_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_CPUSSRST_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_CPUSSCLK_REG_BASE 0x48260000 |
| #define ACPU_MEMMAP_CPUSSCLK_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_CPUSSCLK_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_BBGEN_REG_BASE 0x48270000 |
| #define ACPU_MEMMAP_BBGEN_REG_SIZE 0x10000 |
| #define ACPU_MEMMAP_BBGEN_REG_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_MIPISS_REG_BASE 0x48300000 |
| #define ACPU_MEMMAP_MIPISS_REG_SIZE 0x80000 |
| #define ACPU_MEMMAP_MIPISS_REG_DEC_BIT 0x13 |
| #define ACPU_MEMMAP_SISS_BASE 0xF8000000 |
| #define ACPU_MEMMAP_SISS_SIZE 0x80000 |
| #define ACPU_MEMMAP_SISS_DEC_BIT 0x13 |
| #define ACPU_MEMMAP_BOOTVECTOR_BASE 0xFFFF0000 |
| #define ACPU_MEMMAP_BOOTVECTOR_SIZE 0x4000 |
| #define ACPU_MEMMAP_BOOTVECTOR_DEC_BIT 0xE |
| #define ACPU_MEMMAP_AHBFAB_APB_REG_BASE 0xF8300000 |
| #define ACPU_MEMMAP_AHBFAB_APB_REG_SIZE 0x100000 |
| #define ACPU_MEMMAP_AHBFAB_APB_REG_DEC_BIT 0x14 |
| #define ACPU_MEMMAP_AHBFAB_FASAPB_REG_BASE 0xF8200000 |
| #define ACPU_MEMMAP_AHBFAB_FASAPB_REG_SIZE 0x100000 |
| #define ACPU_MEMMAP_AHBFAB_FASAPB_REG_DEC_BIT 0x14 |
| #define ACPU_MEMMAP_AXI_CFG_REG_BASE 0x48000000 |
| #define ACPU_MEMMAP_AXI_CFG_REG_SIZE 0x400000 |
| #define ACPU_MEMMAP_AXI_CFG_REG_DEC_BIT 0x16 |
| #define ACPU_MEMMAP_CDXGPV_REG_BASE 0x48000000 |
| #define ACPU_MEMMAP_CDXGPV_REG_SIZE 0x100000 |
| #define ACPU_MEMMAP_CDXGPV_REG_DEC_BIT 0x14 |
| #define ACPU_MEMMAP_GIC400_REG_BASE 0x48100000 |
| #define ACPU_MEMMAP_GIC400_REG_SIZE 0x100000 |
| #define ACPU_MEMMAP_GIC400_REG_DEC_BIT 0x14 |
| #define ACPU_MEMMAP_HIFI_TCM_BASE 0x3FC00000 |
| #define ACPU_MEMMAP_HIFI_TCM_SIZE 0x200000 |
| #define ACPU_MEMMAP_HIFI_TCM_DEC_BIT 0x15 |
| #define ACPU_MEMMAP_BLKROM_BASE 0x3FE00000 |
| #define ACPU_MEMMAP_BLKROM_SIZE 0x10000 |
| #define ACPU_MEMMAP_BLKROM_DEC_BIT 0x10 |
| #define ACPU_MEMMAP_OSPI_FLASH_BASE 0xF0000000 |
| #define ACPU_MEMMAP_OSPI_FLASH_SIZE 0x8000000 |
| #define ACPU_MEMMAP_OSPI_FLASH_DEC_BIT 0x1B |
| #define ACPU_MEMMAP_DDR_1020M_BASE 0x0 |
| #define ACPU_MEMMAP_DDR_1020M_SIZE 0x3FC00000 |
| #define ACPU_MEMMAP_DDR_1G_BASE 0x80000000 |
| #define ACPU_MEMMAP_DDR_1G_SIZE 0x40000000 |
| #define ACPU_MEMMAP_DDR_1G_DEC_BIT 0x1E |
| #define ACPU_MEMMAP_USBPHY_REG_BASE 0xF8140000 |
| #define ACPU_MEMMAP_USBPHY_REG_SIZE 0x40000 |
| #define ACPU_MEMMAP_USBPHY_REG_DEC_BIT 0x12 |
| #define ACPU_MEMMAP_VECTOR_BASE 0xFFFF0000 |
| #define ACPU_MEMMAP_VECTOR_SIZE 0x20 |
| #define ACPU_MEMMAP_VECTOR_DEC_BIT 0x5 |
| #define ACPU_MEMMAP_HIGH_EXCEPT_RESET_REG 0xFFFF0000 |
| #define ACPU_MEMMAP_HIGH_EXCEPT_UNDEF_REG 0xFFFF0004 |
| #define ACPU_MEMMAP_HIGH_EXCEPT_SOFT_REG 0xFFFF0008 |
| #define ACPU_MEMMAP_HIGH_EXCEPT_PREFETCH_REG 0xFFFF000C |
| #define ACPU_MEMMAP_HIGH_EXCEPT_DATA_REG 0xFFFF0010 |
| #define ACPU_MEMMAP_HIGH_EXCEPT_UNUSED_REG 0xFFFF0014 |
| #define ACPU_MEMMAP_HIGH_EXCEPT_IRQ_REG 0xFFFF0018 |
| #define ACPU_MEMMAP_HIGH_EXCEPT_FIQ_REG 0xFFFF001C |
| #define ACPU_MEMMAP_ADDR_DATA_REG_BASE 0xFFFF0020 |
| #define ACPU_MEMMAP_ADDR_DATA_REG_SIZE 0x80 |
| #define ACPU_MEMMAP_VECTOR_ADDR_0_REG 0xFFFF0020 |
| #define ACPU_MEMMAP_VECTOR_ADDR_1_REG 0xFFFF0024 |
| #define ACPU_MEMMAP_VECTOR_ADDR_2_REG 0xFFFF0028 |
| #define ACPU_MEMMAP_VECTOR_ADDR_3_REG 0xFFFF002C |
| #define ACPU_MEMMAP_VECTOR_ADDR_4_REG 0xFFFF0030 |
| #define ACPU_MEMMAP_VECTOR_ADDR_5_REG 0xFFFF0034 |
| #define ACPU_MEMMAP_VECTOR_ADDR_6_REG 0xFFFF0038 |
| #define ACPU_MEMMAP_VECTOR_ADDR_7_REG 0xFFFF003C |
| #define ACPU_MEMMAP_BRCH_ADDR_1_0_REG 0xFFFF0040 |
| #define ACPU_MEMMAP_BRCH_ADDR_1_1_REG 0xFFFF0044 |
| #define ACPU_MEMMAP_BRCH_ADDR_1_2_REG 0xFFFF0048 |
| #define ACPU_MEMMAP_BRCH_ADDR_2_0_REG 0xFFFF004C |
| #define ACPU_MEMMAP_BRCH_ADDR_2_1_REG 0xFFFF0050 |
| #define ACPU_MEMMAP_BRCH_ADDR_2_2_REG 0xFFFF0054 |
| #define ACPU_MEMMAP_BRCH_ADDR_3_0_REG 0xFFFF0058 |
| #define ACPU_MEMMAP_BRCH_ADDR_3_1_REG 0xFFFF005C |
| #define ACPU_MEMMAP_BRCH_ADDR_3_2_REG 0xFFFF0060 |
| #define ACPU_MEMMAP_BRCH_ADDR_4_0_REG 0xFFFF0064 |
| #define ACPU_MEMMAP_BRCH_ADDR_4_1_REG 0xFFFF0068 |
| #define ACPU_MEMMAP_BRCH_ADDR_4_2_REG 0xFFFF006C |
| #define ACPU_MEMMAP_BRCH_ADDR_5_0_REG 0xFFFF0070 |
| #define ACPU_MEMMAP_BRCH_ADDR_5_1_REG 0xFFFF0074 |
| #define ACPU_MEMMAP_BRCH_ADDR_5_2_REG 0xFFFF0078 |
| #define ACPU_MEMMAP_BRCH_ADDR_6_0_REG 0xFFFF007C |
| #define ACPU_MEMMAP_BRCH_ADDR_6_1_REG 0xFFFF0080 |
| #define ACPU_MEMMAP_BRCH_ADDR_6_2_REG 0xFFFF0084 |
| #define ACPU_MEMMAP_BRCH_ADDR_7_0_REG 0xFFFF0088 |
| #define ACPU_MEMMAP_BRCH_ADDR_7_1_REG 0xFFFF008C |
| #define ACPU_MEMMAP_BRCH_ADDR_7_2_REG 0xFFFF0090 |
| #define ACPU_MEMMAP_SOFTWARE_RESET_ADDR_REG 0xFFFF0094 |
| /////////////////////////////////////////////////////////// |
| #define RA_ACPU_MEMMAP_memmap 0x0000 |
| |
| #define BA_ACPU_MEMMAP_memmap_dummy 0x0000 |
| #define B16ACPU_MEMMAP_memmap_dummy 0x0000 |
| #define LSb32ACPU_MEMMAP_memmap_dummy 0 |
| #define LSb16ACPU_MEMMAP_memmap_dummy 0 |
| #define bACPU_MEMMAP_memmap_dummy 32 |
| #define MSK32ACPU_MEMMAP_memmap_dummy 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_ACPU_MEMMAP { |
| /////////////////////////////////////////////////////////// |
| #define GET32ACPU_MEMMAP_memmap_dummy(r32) _BFGET_(r32,31, 0) |
| #define SET32ACPU_MEMMAP_memmap_dummy(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32ACPU_MEMMAP_memmap {\ |
| UNSG32 smemmap_dummy : 32;\ |
| } |
| union { UNSG32 u32ACPU_MEMMAP_memmap; |
| struct w32ACPU_MEMMAP_memmap; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_ACPU_MEMMAP; |
| |
| typedef union T32ACPU_MEMMAP_memmap |
| { UNSG32 u32; |
| struct w32ACPU_MEMMAP_memmap; |
| } T32ACPU_MEMMAP_memmap; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TACPU_MEMMAP_memmap |
| { UNSG32 u32[1]; |
| struct { |
| struct w32ACPU_MEMMAP_memmap; |
| }; |
| } TACPU_MEMMAP_memmap; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 ACPU_MEMMAP_drvrd(SIE_ACPU_MEMMAP *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 ACPU_MEMMAP_drvwr(SIE_ACPU_MEMMAP *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void ACPU_MEMMAP_reset(SIE_ACPU_MEMMAP *p); |
| SIGN32 ACPU_MEMMAP_cmp (SIE_ACPU_MEMMAP *p, SIE_ACPU_MEMMAP *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define ACPU_MEMMAP_check(p,pie,pfx,hLOG) ACPU_MEMMAP_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define ACPU_MEMMAP_print(p, pfx,hLOG) ACPU_MEMMAP_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: ACPU_MEMMAP |
| //////////////////////////////////////////////////////////// |
| |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| #pragma pack() |
| |
| #endif |
| ////// |
| /// ENDOFFILE: acpuview_memmap.h |
| //////////////////////////////////////////////////////////// |
| |
