drivers/soc/berlin/modules/berlin_inc/Firmware_AS390/mipiSS_memmap.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2019 Synaptics Incorporated */

#ifndef mipiSS_memmap_h
#define mipiSS_memmap_h (){}


#pragma pack(1)
#ifdef __cplusplus
  extern "C" {
#endif

#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}

    #define _bSETMASK_(b)                                      ((b)<32 ? (1<<((b)&31)) : 0)
    #define _NSETMASK_(msb,lsb)                                (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
    #define _bCLRMASK_(b)                                      (~_bSETMASK_(b))
    #define _NCLRMASK_(msb,lsb)                                (~_NSETMASK_(msb,lsb))
    #define _BFGET_(r,msb,lsb)                                 (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
    #define _BFSET_(r,msb,lsb,v)                               do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)

#endif



//////
///
/// $INTERFACE MIPISS_MEMMAP                            (4,4)
///     # # ----------------------------------------------------------
///               : MIPISS128B_DHUB_REG_BASE 0x0
///                            ###
///                            * Base address of MIPISS 128 bit DHUB control Registers
///                            * 256 KB
///                            ###
///               : MIPISS128B_DHUB_REG_SIZE 0x40000
///                            ###
///                            * Size of VPP 128bit DHUB Registers memory mapping
///                            ###
///               : MIPISS128B_DHUB_REG_DEC_BIT 0x12
///                            ###
///                            * 256 KB has a 16 bits offset
///                            ###
///               : MIPI_PIPE_REG_BASE 0x40000
///                            ###
///                            * Base address of MIPI PIPE Registers
///                            * 64 KB
///                            ###
///               : MIPI_PIPE_REG_SIZE 0x10000
///                            ###
///                            * Size of MIPI PIPE Registers memory mapping
///                            ###
///               : MIPI_PIPE_REG_DEC_BIT 0x10
///                            ###
///                            * 64 KB has a 16 bits offset
///                            ###
///               : MIPISS_GBL_BASE    0x50000
///                            ###
///                            * Base address for AVIO Global Registers
///                            * 64 KB
///                            ###
///               : MIPISS_GBL_SIZE    0x10000
///                            ###
///                            * Size of AVIO Global Registers
///                            ###
///               : MIPISS_GBL_DEC_BIT 0x10
///                            ###
///                            * 64 KB has a 16-bit offset
///                            ###
///               : MIPISS_BCM_REG_BASE 0x60000
///                            ###
///                            * AVIO BCM Registers
///                            * 64KB
///                            ###
///               : MIPISS_BCM_REG_SIZE 0x10000
///                            ###
///                            * Size of AVIO BCM Registers
///                            ###
///               : MIPISS_BCM_REG_DEC_BIT 0x10
///                            ###
///                            * 64KB has 16-bit offset
///                            ###
///               : MIPISS_RESERVED0_REG_BASE 0x70000
///                            ###
///                            * 64KB space reserved
///                            * 64KB
///                            ###
///               : MIPISS_RESERVED0_REG_SIZE 0x10000
///                            ###
///                            * Size of reserved0 registers
///                            ###
///               : MIPISS_RESERVED0_REG_DEC_BIT 0x10
///                            ###
///                            * 64KB has a 16 bits offset
///                            ###
///     # # ----------------------------------------------------------
/// $ENDOFINTERFACE  # size:       0B, bits:       0b, padding:     0B
////////////////////////////////////////////////////////////
#ifndef h_MIPISS_MEMMAP
#define h_MIPISS_MEMMAP (){}

    #define        MIPISS_MEMMAP_MIPISS128B_DHUB_REG_BASE      0x0
    #define        MIPISS_MEMMAP_MIPISS128B_DHUB_REG_SIZE      0x40000
    #define        MIPISS_MEMMAP_MIPISS128B_DHUB_REG_DEC_BIT   0x12
    #define        MIPISS_MEMMAP_MIPI_PIPE_REG_BASE            0x40000
    #define        MIPISS_MEMMAP_MIPI_PIPE_REG_SIZE            0x10000
    #define        MIPISS_MEMMAP_MIPI_PIPE_REG_DEC_BIT         0x10
    #define        MIPISS_MEMMAP_MIPISS_GBL_BASE               0x50000
    #define        MIPISS_MEMMAP_MIPISS_GBL_SIZE               0x10000
    #define        MIPISS_MEMMAP_MIPISS_GBL_DEC_BIT            0x10
    #define        MIPISS_MEMMAP_MIPISS_BCM_REG_BASE           0x60000
    #define        MIPISS_MEMMAP_MIPISS_BCM_REG_SIZE           0x10000
    #define        MIPISS_MEMMAP_MIPISS_BCM_REG_DEC_BIT        0x10
    #define        MIPISS_MEMMAP_MIPISS_RESERVED0_REG_BASE     0x70000
    #define        MIPISS_MEMMAP_MIPISS_RESERVED0_REG_SIZE     0x10000
    #define        MIPISS_MEMMAP_MIPISS_RESERVED0_REG_DEC_BIT  0x10
    ///////////////////////////////////////////////////////////

#endif



#ifdef __cplusplus
  }
#endif
#pragma  pack()

#endif