| /* |
| * cx9000.h -- CX9000 Smart Amplifier driver |
| * |
| * Copyright: (C) 2017 Synaptics Incorporated. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| */ |
| |
| #ifndef __CX9000_PRIV_H__ |
| #define __CX9000_PRIV_H__ |
| |
| #define CX9000_CLOCK_CONTROL0 0x0 |
| #define CX9000_CLOCK_CONTROL1 0x1 |
| #define CX9000_CLOCK_CONTROL2 0x2 |
| #define CX9000_CLOCK_CONTROL3 0x3 |
| #define CX9000_CLOCK_CONTROL4 0x4 |
| #define CX9000_CLOCK_CONTROL5 0x5 |
| #define CX9000_CLOCK_CONTROL6 0x6 |
| #define CX9000_PLL_CONTROL0 0x7 |
| #define CX9000_PLL_CONTROL1 0x8 |
| #define CX9000_PLL_CONTROL2 0x9 |
| #define CX9000_PLL_CONTROL3 0xA |
| #define CX9000_PLL_CONTROL4 0xB |
| #define CX9000_PLL_CONTROL5 0xC |
| #define CX9000_PLL_CONTROL6 0xD |
| #define CX9000_PLL_CONTROL7 0xE |
| #define CX9000_PLL_CONTROL8 0xF |
| #define CX9000_PLL_TRACK_CONTROL 0x10 |
| #define CX9000_PLL_TRACK_THRESHOLD0 0x11 |
| #define CX9000_PLL_TRACK_THRESHOLD1 0x12 |
| #define CX9000_PLL_TRACK_ADJUST0 0x13 |
| #define CX9000_PLL_TRACK_ADJUST1 0x14 |
| #define CX9000_SOFT_RESET 0x20 |
| #define CX9000_OSS_CSR 0x100 |
| #define CX9000_STATE_TRIGGERS_LP1_R1 0x101 |
| #define CX9000_STATE_TRIGGERS_LP1_R2 0x102 |
| #define CX9000_STATE_TRIGGERS_LP2_R1 0x103 |
| #define CX9000_STATE_TRIGGERS_LP2_R2 0x104 |
| #define CX9000_STATE_TRIGGERS_LP3_R1 0x105 |
| #define CX9000_STATE_TRIGGERS_LP3_R2 0x106 |
| #define CX9000_STATE_ACTIONS_LP1_R1 0x107 |
| #define CX9000_STATE_ACTIONS_LP1_R2 0x108 |
| #define CX9000_STATE_ACTIONS_LP1_R3 0x109 |
| #define CX9000_STATE_ACTIONS_LP2_R1 0x10A |
| #define CX9000_STATE_ACTIONS_LP2_R2 0x10B |
| #define CX9000_STATE_ACTIONS_LP2_R3 0x10C |
| #define CX9000_STATE_ACTIONS_LP3_R1 0x10D |
| #define CX9000_STATE_ACTIONS_LP3_R2 0x10E |
| #define CX9000_STATE_ACTIONS_LP3_R3 0x10F |
| #define CX9000_DEBUG_STATE_OVERRIDE 0x110 |
| #define CX9000_DEBUG_R1 0x111 |
| #define CX9000_DEBUG_R3 0x113 |
| #define CX9000_DEBUG_R5 0x115 |
| #define CX9000_DEBUG_R7 0x11D |
| #define CX9000_DEBUG_R2 0x112 |
| #define CX9000_DEBUG_R4 0x114 |
| #define CX9000_DEBUG_R6 0x116 |
| #define CX9000_SHORT_WAIT 0x120 |
| #define CX9000_LONG_WAIT 0x121 |
| #define CX9000_WAIT_ASSIGN_FORWARD_R1 0x122 |
| #define CX9000_WAIT_ASSIGN_FORWARD_R2 0x123 |
| #define CX9000_WAIT_ASSIGN_REVERSE_R1 0x124 |
| #define CX9000_WAIT_ASSIGN_REVERSE_R2 0x125 |
| #define CX9000_SYSTEM_CFG_TEST0 0x130 |
| #define CX9000_SYSTEM_CFG_TEST1 0x131 |
| #define CX9000_I2C_DEVICE_ADDRESS 0x301 |
| #define CX9000_I2S_PCM_REG1 0x500 |
| #define CX9000_I2S_PCM_REG2 0x501 |
| #define CX9000_I2S_PCM_REG3 0x502 |
| #define CX9000_I2S_PCM_REG4 0x503 |
| #define CX9000_I2S_PCM_REG5 0x504 |
| #define CX9000_I2S_PCM_REG6 0x505 |
| #define CX9000_I2S_PCM_REG7 0x506 |
| #define CX9000_I2S_PCM_REG8 0x507 |
| #define CX9000_I2S_PCM_REG9 0x508 |
| #define CX9000_I2S_PCM_REG10 0x509 |
| #define CX9000_I2S_PCM_REG11 0x50A |
| #define CX9000_I2S_PCM_REG12 0x50B |
| #define CX9000_I2S_PCM_REG13 0x50C |
| #define CX9000_I2S_PCM_REG14 0x50D |
| #define CX9000_I2S_PCM_REG15 0x50E |
| #define CX9000_I2S_PCM_REG16 0x50F |
| #define CX9000_I2S_PCM_REG17 0x510 |
| #define CX9000_I2S_PCM_REG18 0x511 |
| #define CX9000_I2S_PCM_REG19 0x512 |
| #define CX9000_I2S_PCM_REG20 0x513 |
| #define CX9000_I2S_PCM_REG21 0x514 |
| #define CX9000_I2S_PCM_REG22 0x515 |
| #define CX9000_I2S_PCM_REG23 0x516 |
| #define CX9000_I2S_PCM_REG24 0x517 |
| #define CX9000_I2S_PCM_REG25 0x518 |
| #define CX9000_I2S_PCM_REG26 0x519 |
| #define CX9000_I2S_PCM_REG27 0x51A |
| #define CX9000_I2S_PCM_REG28 0x51B |
| #define CX9000_I2S_PCM_REG29 0x51C |
| #define CX9000_I2S_PCM_REG30 0x51D |
| #define CX9000_I2S_PCM_REG31 0x51E |
| #define CX9000_I2S_PCM_REG32 0x51F |
| #define CX9000_I2S_PCM_REG33 0x520 |
| #define CX9000_I2S_PCM_REG34 0x521 |
| #define CX9000_I2S_PCM_REG35 0x522 |
| #define CX9000_I2S_PCM_REG36 0x523 |
| #define CX9000_I2S_PCM_REG37 0x524 |
| #define CX9000_GPIO_SELECT 0x200 |
| #define CX9000_GPIO_OUTPUT_ENABLE 0x201 |
| #define CX9000_GPIO_OUTPUT_LEVEL 0x202 |
| #define CX9000_GPIO_INPUT_ENABLE 0x203 |
| #define CX9000_GPIO_INPUT_STATUS 0x204 |
| #define CX9000_GPIO_IRQ_EN 0x205 |
| #define CX9000_GPIO_IRQ_EDGE 0x206 |
| #define CX9000_GPIO_IRQ_POLARITY 0x207 |
| #define CX9000_GPIO_IRQ_STATUS 0x208 |
| #define CX9000_GPIO_ELECTRICAL_CONTROL_1_0 0x209 |
| #define CX9000_GPIO_ELECTRICAL_CONTROL_3_2 0x20A |
| #define CX9000_GPIO_ELECTRICAL_CONTROL_5_4 0x20B |
| #define CX9000_GPIO_ELECTRICAL_CONTROL_7_6 0x20C |
| #define CX9000_ELECTRICAL_CONTROL_BCLK_WS 0x20E |
| #define CX9000_ELECTRICAL_CONTROL_SDIN 0x20F |
| #define CX9000_INTRPT_ENABLE_R1 0x210 |
| #define CX9000_INTRPT_ENABLE_R2 0x211 |
| #define CX9000_INTRPT_MASK_R1 0x212 |
| #define CX9000_INTRPT_MASK_R2 0x213 |
| #define CX9000_INTRPT_STATUS_R1 0x214 |
| #define CX9000_INTRPT_STATUS_R2 0x220 |
| #define CX9000_INTRPT_STATUS_MASKED_R1 0x221 |
| #define CX9000_INTRPT_STATUS_MASKED_R2 0x222 |
| #define CX9000_INTRPT_SET_R1 0x223 |
| #define CX9000_COEF_CTRL0 0x224 |
| #define CX9000_COEF_CTRL1 0x225 |
| #define CX9000_COEF_WRITE_0_L 0x226 |
| #define CX9000_COEF_WRITE_0_H 0x227 |
| #define CX9000_COEF_WRITE_1_L 0x228 |
| #define CX9000_COEF_WRITE_1_H 0x229 |
| #define CX9000_COEF_WRITE_2_L 0x22A |
| #define CX9000_COEF_WRITE_2_H 0x22B |
| #define CX9000_COEF_WRITE_3_L 0x22C |
| #define CX9000_COEF_WRITE_3_H 0x22D |
| #define CX9000_COEF_WRITE_4_L 0x22E |
| #define CX9000_COEF_WRITE_4_H 0x22F |
| #define CX9000_COEF_WRITE_5_L 0x230 |
| #define CX9000_COEF_WRITE_5_H 0x231 |
| #define CX9000_COEF_WRITE_6_L 0x232 |
| #define CX9000_COEF_WRITE_6_H 0x233 |
| #define CX9000_COEF_WRITE_7_L 0x234 |
| #define CX9000_COEF_WRITE_7_H 0x235 |
| #define CX9000_COEF_READ_0_L 0x236 |
| #define CX9000_COEF_READ_0_H 0x237 |
| #define CX9000_COEF_READ_1_L 0x238 |
| #define CX9000_COEF_READ_1_H 0x239 |
| #define CX9000_COEF_READ_2_L 0x23A |
| #define CX9000_COEF_READ_2_H 0x23B |
| #define CX9000_COEF_READ_3_L 0x23C |
| #define CX9000_COEF_READ_3_H 0x23D |
| #define CX9000_COEF_READ_4_L 0x23E |
| #define CX9000_COEF_READ_4_H 0x23F |
| #define CX9000_COEF_READ_5_L 0x240 |
| #define CX9000_COEF_READ_5_H 0x241 |
| #define CX9000_COEF_READ_6_L 0x242 |
| #define CX9000_COEF_READ_6_H 0x243 |
| #define CX9000_COEF_READ_7_L 0x244 |
| #define CX9000_COEF_READ_7_H 0x245 |
| #define CX9000_DEV_ID_0 0x250 |
| #define CX9000_DEV_ID_1 0x251 |
| #define CX9000_DEV_ID_2 0x252 |
| #define CX9000_DEV_ID_3 0x253 |
| #define CX9000_BOND_OPT 0x254 |
| #define CX9000_STEPPING_NUMBER 0x255 |
| #define CX9000_DAC_CONFIGURATION 0x260 |
| #define CX9000_HPF_LEFT_CONTROL 0x261 |
| #define CX9000_HPF_RIGHT_CONTROL 0x262 |
| #define CX9000_ZERODETECT_CSR 0x263 |
| #define CX9000_NOISEGATE_CSR 0x264 |
| #define CX9000_NOISE_GATE_THRESHOLD_H 0x265 |
| #define CX9000_NOISE_GATE_THRESHOLD_M 0x266 |
| #define CX9000_NOISE_GATE_THRESHOLD_L 0x267 |
| #define CX9000_FIFO_STATUS_OVERFLOW 0x268 |
| #define CX9000_FIFO_STATUS_UNDERFLOW 0x269 |
| #define CX9000_ANALOG_GAIN 0x270 |
| #define CX9000_ANALOG_TEST0_H 0x280 |
| #define CX9000_ANALOG_TEST0_L 0x281 |
| #define CX9000_ANALOG_TEST1_H 0x282 |
| #define CX9000_ANALOG_TEST1_L 0x283 |
| #define CX9000_ANALOG_TEST2_H 0x284 |
| #define CX9000_ANALOG_TEST2_L 0x285 |
| #define CX9000_ANALOG_TEST3_H 0x286 |
| #define CX9000_ANALOG_TEST3_L 0x287 |
| #define CX9000_RESERVED 0x288 |
| #define CX9000_ANALOG_TEST4_L 0x289 |
| #define CX9000_ANALOG_TEST5_H 0x28A |
| #define CX9000_ANALOG_TEST5_L 0x28B |
| #define CX9000_ANALOG_TEST7_H 0x28C |
| #define CX9000_ANALOG_TEST7_L 0x28D |
| #define CX9000_ANALOG_TEST8_H 0x28E |
| #define CX9000_ANALOG_TEST8_L 0x28F |
| #define CX9000_ANALOG_TEST9_H 0x290 |
| #define CX9000_ANALOG_TEST9_L 0x291 |
| #define CX9000_ANALOG_TEST18_H 0x292 |
| #define CX9000_ANALOG_TEST18_L 0x293 |
| #define CX9000_ANALOG_TEST19_H 0x294 |
| #define CX9000_ANALOG_TEST19_L 0x295 |
| #define CX9000_ANALOG_TEST20_H 0x296 |
| #define CX9000_ANALOG_TEST20_L 0x297 |
| #define CX9000_ANALOG_TEST21_H 0x298 |
| #define CX9000_ANALOG_TEST21_L 0x299 |
| #define CX9000_ANALOG_TEST22_H 0x29A |
| #define CX9000_ANALOG_TEST22_L 0x29B |
| #define CX9000_ANALOG_TEST23_H 0x29C |
| #define CX9000_ANALOG_TEST23_L 0x29D |
| #define CX9000_ANALOG_TEST25_H 0x29E |
| #define CX9000_ANALOG_TEST25_L 0x29F |
| #define CX9000_ANALOG_TEST26_H 0x2A0 |
| #define CX9000_ANALOG_TEST26_L 0x2A1 |
| #define CX9000_ANALOG_TEST27_H 0x2A2 |
| #define CX9000_ANALOG_TEST27_L 0x2A3 |
| #define CX9000_ANALOG_TEST28_H 0x2A4 |
| #define CX9000_ANALOG_TEST28_L 0x2A5 |
| #define CX9000_ANALOG_TEST29_H 0x2A6 |
| #define CX9000_ANALOG_TEST29_L 0x2A7 |
| #define CX9000_ANALOG_TEST30_H 0x2A8 |
| #define CX9000_ANALOG_TEST30_L 0x2A9 |
| #define CX9000_ANALOG_RELATED_CONTROL 0x2B0 |
| #define CX9000_ANALOG_STATE_STATUS 0x2B1 |
| #define CX9000_ANALOG_ERROR_STATUS 0x2B2 |
| #define CX9000_ANALOG_READOUT_1 0x2B3 |
| #define CX9000_ANALOG_READOUT_2 0x2B4 |
| #define CX9000_DAC_TEST_CTRL_REG0_L 0x2D0 |
| #define CX9000_DAC_TEST_CTRL_REG0_H 0x2D1 |
| #define CX9000_DAC_TEST_CTRL_REG1 0x2D2 |
| #define CX9000_DAC_TEST_CTRL_REG2 0x2D3 |
| #define CX9000_FE1_GAIN_L_B0 0x2F0 |
| #define CX9000_FE1_GAIN_L_B1 0x2F1 |
| #define CX9000_FE1_GAIN_L_B2 0x2F2 |
| #define CX9000_FE1_GAIN_R_B0 0x2F3 |
| #define CX9000_FE1_GAIN_R_B1 0x2F4 |
| #define CX9000_FE1_GAIN_R_B2 0x2F5 |
| #define CX9000_CLASSD_CALIBRATION 0x2F6 |
| #define CX9000_CLASSD_CALIBRATION 0x2F6 |
| #define CX9000_MUTE_PRE_DRC_VOLUME 0x600 |
| #define CX9000_VOLUME_LEFT 0x601 |
| #define CX9000_VOLUME_RIGHT 0x602 |
| #define CX9000_TBDRC_LP_RATE_RELEASE 0x71D |
| #define CX9000_VOLUME_BOTH 0x603 |
| #define CX9000_EQ_ENABLE_BYPASS 0x710 |
| #define CX9000_TBDRC_CTRL_REG0 0x711 |
| #define CX9000_TBDRC_CTRL_REG1 0x712 |
| #define CX9000_TBDRC_VOLUME_LEFT 0x713 |
| #define CX9000_TBDRC_VOLUME_RIGHT 0x714 |
| #define CX9000_TBDRC_LP_HIGH_INPUT_THRD 0x715 |
| #define CX9000_TBDRC_LP_LOW_INPUT_THRD 0x716 |
| #define CX9000_TBDRC_LP_HIGH_OUTPUT_THRD 0x717 |
| #define CX9000_TBDRC_LP_LOW_OUTPUT_THRD 0x718 |
| #define CX9000_TBDRC_LP_SLOOP 0x719 |
| #define CX9000_TBDRC_LP_ATTACH_RATE_GAIN_SHIFT 0x71A |
| #define CX9000_TBDRC_LP_RELEASE 0x71B |
| #define CX9000_TBDRC_LP_FAST_RELEASE 0x71C |
| #define CX9000_TBDRC_LP_RATE_RELEASE 0x71D |
| #define CX9000_TBDRC_LP_BALANCE_RAMP_STEP 0x71E |
| #define CX9000_TBDRC_LP_VOLUME_RAMP_STEP_SEL 0x71F |
| #define CX9000_TBDRC_HP_HIGH_INPUT_THRD 0x720 |
| #define CX9000_TBDRC_HP_LOW_INPUT_THRD 0x721 |
| #define CX9000_TBDRC_HP_HIGH_OUTPUT_THRD 0x722 |
| #define CX9000_TBDRC_HP_LOW_OUTPUT_THRD 0x723 |
| #define CX9000_TBDRC_HP_SLOOP 0x724 |
| #define CX9000_TBDRC_HP_ATTACH_RATE_GAIN_SHIFT 0x725 |
| #define CX9000_TBDRC_HP_RELEASE 0x726 |
| #define CX9000_TBDRC_HP_FAST_RELEASE 0x727 |
| #define CX9000_TBDRC_HP_RATE_RELEASE 0x728 |
| #define CX9000_TBDRC_HP_BALANCE_RAMP_STEP 0x729 |
| #define CX9000_TBDRC_HP_VOLUME_RAMP_STEP_SEL 0x72A |
| #define CX9000_TBDRC_MP_HIGH_INPUT_THRD 0x72B |
| #define CX9000_TBDRC_MP_LOW_INPUT_THRD 0x72C |
| #define CX9000_TBDRC_MP_HIGH_OUTPUT_THRD 0x72D |
| #define CX9000_TBDRC_MP_LOW_OUTPUT_THRD 0x72E |
| #define CX9000_TBDRC_MP_SLOOP 0x72F |
| #define CX9000_TBDRC_MP_ATTACH_RATE_GAIN_SHIFT 0x730 |
| #define CX9000_TBDRC_MP_RELEASE 0x731 |
| #define CX9000_TBDRC_MP_FAST_RELEASE 0x732 |
| #define CX9000_TBDRC_MP_RATE_RELEASE 0x733 |
| #define CX9000_TBDRC_MP_BALANCE_RAMP_STEP 0x734 |
| #define CX9000_TBDRC_MP_VOLUME_RAMP_STEP_SEL 0x735 |
| #define CX9000_TBDRC_PD_HIGH_INPUT_THRD 0x736 |
| #define CX9000_TBDRC_PD_LOW_INPUT_THRD 0x737 |
| #define CX9000_TBDRC_PD_HIGH_OUTPUT_THRD 0x738 |
| #define CX9000_TBDRC_PD_LOW_OUTPUT_THRD 0x739 |
| #define CX9000_TBDRC_PD_SLOOP 0x73A |
| #define CX9000_TBDRC_PD_ATTACH_RATE_GAIN_SHIFT 0x73B |
| #define CX9000_TBDRC_PD_RELEASE 0x73C |
| #define CX9000_TBDRC_PD_FAST_RELEASE 0x73D |
| #define CX9000_TBDRC_PD_RATE_RELEASE 0x73E |
| #define CX9000_TBDRC_PD_BALANCE_RAMP_STEP 0x73F |
| #define CX9000_TBDRC_PD_VOLUME_RAMP_STEP_SEL 0x740 |
| #define CX9000_CSR_CTRL 0x900 |
| #define CX9000_TEST_CTRL 0xE00 |
| #define CX9000_TEST_OVERRIDE 0xE01 |
| #define CX9000_IRQ_ALT_7_0 0xE02 |
| #define CX9000_IRQ_ALT_8 0xE03 |
| #define CX9000_CALIB_OVERRIDE 0xE04 |
| #define CX9000_SPKR_OFFCAL_L 0xE05 |
| #define CX9000_SPKR_OFFCAL_R 0xE06 |
| #define CX9000_FIFO_OVERFLOW_MASK1 0xE07 |
| #define CX9000_FIFO_OVERFLOW_MASK2 0xE08 |
| |
| #define CX9000_MAX_REG 0xe08 |
| |
| enum OSS_CUR_STATE { |
| CX9000_OSS_IDLE = 0, |
| CX9000_OSS_FULL = 1, |
| CX9000_OSS_LP1 = 2, |
| CX9000_OSS_LP2 = 3, |
| CX9000_OSS_LP3 = 4, |
| }; |
| |
| enum DAC_CONFIG { |
| CX9000_STEREO = 0, |
| CX9000_MONO_LEFT = 1, |
| CX9000_MONO_RIGHT = 2, |
| CX9000_BI_MONO = 3, |
| CX9000_MONO_MIXED = 4, |
| CX9000_BI_MIXED = 5, |
| }; |
| |
| enum SAMPLE_RATE { |
| CX9000_48K = 4, |
| CX9000_96K = 5, |
| CX9000_192K = 6, |
| }; |
| |
| union REG_I2SPCM_CTRL_REG1_REG2 { |
| struct { |
| u16 rx_lrck_frame:8; |
| u16 rx_sync_lng:8; |
| } r; |
| u16 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG3 { |
| struct { |
| u8 rx_lrck_low_first:1; |
| u8 rx_lrck_en:1; /* master mode use */ |
| u8 reserved:6; |
| } r; |
| u8 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG4_REG5 { |
| struct { |
| u16 tx_lrck_frame:8; |
| u16 tx_sync_lng:8; |
| } r; |
| u16 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG6 { |
| struct { |
| u8 tx_lrck_low_first:1; |
| u8 tx_lrck_en:1; /* mater mode use */ |
| u8 reserved:6; |
| } r; |
| u8 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG7_REG10 { |
| struct { |
| u32 rx1_sa_wdt:5; |
| u32 reserved:3; |
| u32 rx1_slot:8; |
| u32 tx1_sa_wdt:5; |
| u32 reserved2:3; |
| u32 tx1_slot:8; |
| } r; |
| u32 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG11_REG14 { |
| struct { |
| u32 rx2_sa_wdt:5; |
| u32 reserved:3; |
| u32 rx2_slot:8; |
| u32 tx2_sa_wdt:5; |
| u32 reserved2:3; |
| u32 tx2_slot:8; |
| } r; |
| u32 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG15_REG18 { |
| struct { |
| u32 tx3_sa_wdt:5; |
| u32 reserved:3; |
| u32 tx3_slot:8; |
| u32 tx4_sa_wdt:5; |
| u32 reserved2:3; |
| u32 tx4_slot:8; |
| } r; |
| u32 ulval; |
| }; |
| |
| /* ch5 and ch6 not use */ |
| union REG_I2SPCM_CTRL_REG19_REG22 { |
| struct { |
| u32 tx5_sa_wdt:5; |
| u32 reserved:3; |
| u32 tx5_slot:8; |
| u32 tx6_sa_wdt:5; |
| u32 reserved2:3; |
| u32 tx6_slot:8; |
| } r; |
| u32 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG23_REG26 { |
| struct { |
| u32 rxck_frame:8; |
| u32 txck_frame:8; |
| u32 rx_dstart_dly:1; |
| u32 rx_dshift_sel:1; |
| u32 rx_mode:1; |
| u32 rx_order:1; |
| u32 tx_dstart_dly:1; |
| u32 tx_dshift_sel:1; |
| u32 tx_mode:1; |
| u32 tx_order:1; |
| u32 rx_master:1; /* master mode use */ |
| u32 rx_on_posedge:1; |
| u32 rx_lrck_pol:1; |
| u32 tx_master:1; /* master mode use */ |
| u32 tx_on_posedge:1; |
| u32 tx_lrck_pol:1; |
| u32 tx_out_en:1; |
| u32 tdm_bi:1; |
| } r; |
| u32 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG27_REG30 { |
| struct { |
| u32 clk_share_en:1; |
| u32 clk_share_with_rx:1; |
| u32 lrck_share_en:1; |
| u32 lrck_share_with_rx:1; |
| u32 reserved:4; |
| u32 sd1_sel:6; |
| u32 reserved2:2; |
| u32 sd2_sel:6; |
| u32 reserved3:2; |
| u32 sd3_sel:6; |
| u32 reserved4:2; |
| } r; |
| u32 ulval; |
| }; |
| |
| union REG_I2SPCM_CTRL_REG31_REG32 { |
| struct { |
| u16 rx1_en:1; |
| u16 rx2_en:1; |
| u16 reserved:5; |
| u16 rx_mute:1; |
| u16 tx1_en:1; |
| u16 tx2_en:1; |
| u16 tx3_en:1; |
| u16 tx4_en:1; |
| u16 tx5_en:1; |
| u16 tx6_en:1; |
| u16 reserved2:1; |
| u16 tx_mute:1; |
| } r; |
| u16 ulval; |
| }; |
| |
| /* OSS */ |
| #define CX9000_OSS_STATE_GET(val) ((val >> 4) & 0x07) |
| #define CX9000_CHECK_DELAY 20 |
| #define CX9000_MUTE 0x30 |
| #define CX9000_UNMUTE 0x00 |
| #define CX9000_OSS_CSR_MASK 0x02 |
| #define CX9000_OSS_CSR_SOFT_DISABLE (1 << 1) |
| #define CX9000_OSS_CSR_SOFT_CLEAR (0 << 1) |
| |
| /* PLL */ |
| #define CX9000_PLL_PRE_DIV_RATIO 4 |
| #define CX9000_PLL_INT_DIV_RATIO 8 |
| #define CX9000_REF_FREQ_MIN 1400000 |
| #define CX9000_REF_FREQ_MAX 6000000 |
| #define CX9000_CLOCK_SRC_MAX 147456000 |
| #define CX9000_PLL_BYPASS (1 << 1) |
| #define CX9000_PLL_SRC_MASK (1 << 0) |
| #define CX9000_PLL_FRAC_LOWER(val) ((val >> 0) & 0xFF) |
| #define CX9000_PLL_FRAC_MIDDLE(val) ((val >> 8) & 0xFF) |
| #define CX9000_PLL_FRAC_UPPER(val) ((val >> 16) & 0xFF) |
| |
| /* EQ/DRC/SA2 Control */ |
| #define CX9000_PID_DISABLE 0x08 |
| #define CX9000_PID_HARDWARE 0x09 |
| #define CX9000_EQ_ENABLE_L (1 << 0) |
| #define CX9000_EQ_ENABLE_R (1 << 1) |
| #define CX9000_EQ_BYPASS_L 0x05 |
| #define CX9000_EQ_BYPASS_R 0x0A |
| #define CX9000_EQ_EN 1 |
| #define CX9000_EQ_ENABLE_L_MASK 0x05 |
| #define CX9000_EQ_ENABLE_R_MASK 0x0A |
| #define CX9000_DRC_SFT_RSTN (1 << 0) |
| #define CX9000_DRC_ENABLE (1 << 1) |
| #define CX9000_DRC_EN (CX9000_DRC_SFT_RSTN | CX9000_DRC_ENABLE) |
| #define CX9000_DRC_EN_MASK 0x03 |
| #define CX9000_DRC_COEFF_L 2 |
| #define CX9000_DRC_COEFF_R 3 |
| #define CX9000_EQ_COEFF_L 0 |
| #define CX9000_EQ_COEFF_R 1 |
| #define CX9000_SA2_COEFF_L 5 |
| #define CX9000_SA2_COEFF_R 6 |
| #define CX9000_FUNCTION_CHANNEL_SEL(val) (val << 3) |
| #define CX9000_FUNCTION_RATE_SEL(val) (val << 6) |
| #define CX9000_COEFF_CHECK_DELAY 20 |
| #define CX9000_COEFF_CHECK_DONE(val) ((val >> 1) & 0x01) |
| |
| /* SYS Clock */ |
| #define CX9000_PLL_CLKIN_MCLK 0x00 |
| #define CX9000_PLL_CLKIN_BCLK 0x01 |
| |
| /* DAC Configuration */ |
| #define CX9000_DAC_CONFIGURATION_MASK 0xF0 |
| #define CX9000_DAC_STEREO 0x0 |
| #define CX9000_DAC_MONO (1 << 7) |
| #define CX9000_DAC_DUPLICATE (1 << 6) |
| #define CX9000_DAC_MONO_RIGHT (CX9000_DAC_MONO | (1 << 5)) |
| #define CX9000_DAC_MONO_MIXED ((CX9000_DAC_MONO) | (1 << 4)) |
| |
| /* HPF configuration */ |
| #define CX9000_HPF_CUTOFF_MASK 0x1F |
| /* n * 30Hz */ |
| #define CX9000_HPF_CUTOFF_MAX 31 |
| #define CX9000_HPF_ORDER_MASK (1 << 5) |
| #define CX9000_HPF_ENABLE_MASK 0xC0 |
| #define CX9000_HPF_BYPASS 0xC0 |
| |
| #endif |
