| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* Copyright (C) 2018 Synaptics Incorporated */ |
| |
| #ifndef __AS370_AIO_H__ |
| #define __AS370_AIO_H__ |
| |
| #define RA_PRIAUD_CLKDIV 0x0000 |
| #define RA_PRIAUD_CTRL 0x0004 |
| #define RA_PRIAUD_CTRL1 0x0008 |
| #define RA_AIO_IOSEL 0x0124 |
| #define RA_AIO_IRQENABLE 0x0150 |
| #define RA_AIO_IRQSTS 0x0154 |
| #define RA_AIO_PDM_MIC_SEL 0x0160 |
| |
| #define SET32PRIAUD_CLKDIV_SETTING(r32, v) _BFSET_(r32, 3, 0, v) |
| #define SET32PRIAUD_CTRL_LEFTJFY(r32, v) _BFSET_(r32, 0, 0, v) |
| #define SET32PRIAUD_CTRL_INVCLK(r32, v) _BFSET_(r32, 1, 1, v) |
| #define SET32PRIAUD_CTRL_INVFS(r32, v) _BFSET_(r32, 2, 2, v) |
| #define SET32PRIAUD_CTRL_TLSB(r32, v) _BFSET_(r32, 3, 3, v) |
| #define SET32PRIAUD_CTRL_TDM(r32, v) _BFSET_(r32, 6, 4, v) |
| #define SET32PRIAUD_CTRL_TCF(r32, v) _BFSET_(r32, 9, 7, v) |
| #define SET32PRIAUD_CTRL_TFM(r32, v) _BFSET_(r32, 11, 10, v) |
| #define SET32PRIAUD_CTRL_TDMMODE(r32, v) _BFSET_(r32, 12, 12, v) |
| #define SET32PRIAUD_CTRL_TDMCHCNT(r32, v) _BFSET_(r32, 15, 13, v) |
| #define SET32PRIAUD_CTRL_TDMWSHIGH(r32, v) _BFSET_(r32, 23, 16, v) |
| #define SET32PRIAUD_CTRL_TCF_MANUAL(r32, v) _BFSET_(r32, 31, 24, v) |
| #define SET32PRIAUD_CTRL_TCF_MAN_MAR(r32, v) _BFSET_(r32, 2, 0, v) |
| #define SET32PRIAUD_CTRL_TDM_MANUAL(r32, v) _BFSET_(r32, 10, 3, v) |
| #define SET32PRIAUD_CTRL_PCM_MONO_CH(r32, v) _BFSET_(r32, 11, 11, v) |
| |
| #define SET32AUDCH_CTRL_ENABLE(r32, v) _BFSET_(r32, 0, 0, v) |
| #define SET32AUDCH_CTRL_MUTE(r32, v) _BFSET_(r32, 1, 1, v) |
| #define SET32AUDCH_CTRL_LRSWITCH(r32, v) _BFSET_(r32, 2, 2, v) |
| #define SET32AUDCH_CTRL_DEBUGEN(r32, v) _BFSET_(r32, 3, 3, v) |
| #define SET32AUDCH_CTRL_FLUSH(r32, v) _BFSET_(r32, 4, 4, v) |
| |
| #endif |
