| [ |
| { |
| "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", |
| "EventCode": "0xAE", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "ITLB.ITLB_FLUSH", |
| "SampleAfterValue": "100007", |
| "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x4F", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "EPT.WALK_PENDING", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", |
| "EventCode": "0x85", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Misses at all ITLB levels that cause page walks", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", |
| "EventCode": "0x85", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", |
| "EventCode": "0x85", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", |
| "EventCode": "0x85", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x85", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "ITLB_MISSES.WALK_PENDING", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake. ", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x85", |
| "Counter": "0,1,2,3", |
| "UMask": "0x20", |
| "EventName": "ITLB_MISSES.STLB_HIT", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", |
| "EventCode": "0x08", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Load misses in all DTLB levels that cause page walks", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", |
| "EventCode": "0x08", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", |
| "EventCode": "0x08", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", |
| "EventCode": "0x08", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x08", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x08", |
| "Counter": "0,1,2,3", |
| "UMask": "0x20", |
| "EventName": "DTLB_LOAD_MISSES.STLB_HIT", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Loads that miss the DTLB and hit the STLB.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", |
| "EventCode": "0x49", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Store misses in all DTLB levels that cause page walks", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", |
| "EventCode": "0x49", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", |
| "EventCode": "0x49", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", |
| "EventCode": "0x49", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x49", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "DTLB_STORE_MISSES.WALK_PENDING", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x49", |
| "Counter": "0,1,2,3", |
| "UMask": "0x20", |
| "EventName": "DTLB_STORE_MISSES.STLB_HIT", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Stores that miss the DTLB and hit the STLB.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", |
| "EventCode": "0xBD", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "TLB_FLUSH.DTLB_THREAD", |
| "SampleAfterValue": "100007", |
| "BriefDescription": "DTLB flush attempts of the thread-specific entries", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", |
| "EventCode": "0xBD", |
| "Counter": "0,1,2,3", |
| "UMask": "0x20", |
| "EventName": "TLB_FLUSH.STLB_ANY", |
| "SampleAfterValue": "100007", |
| "BriefDescription": "STLB flush attempts", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x85", |
| "Counter": "0,1,2,3", |
| "UMask": "0xe", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x08", |
| "Counter": "0,1,2,3", |
| "UMask": "0xe", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x49", |
| "Counter": "0,1,2,3", |
| "UMask": "0xe", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x49", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake. ", |
| "CounterMask": "1", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x08", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake. ", |
| "CounterMask": "1", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x85", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "ITLB_MISSES.WALK_ACTIVE", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.", |
| "CounterMask": "1", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| } |
| ] |
