FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/drivers/cortex-a/mmu.c

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/** \file */

/**
 * \addtogroup mmu MMU Initialization
 *
 * \section Usage
 *
 * Translation Lookaside Buffers (TLBs) are an implementation technique that caches translations or
 * translation table entries. TLBs avoid the requirement for every memory access to perform a translation table
 * lookup. The ARM architecture does not specify the exact form of the TLB structures for any design. In a
 * similar way to the requirements for caches, the architecture only defines certain principles for TLBs:
 *
 * The MMU supports memory accesses based on memory sections or pages:
 * Supersections Consist of 16MB blocks of memory. Support for Supersections is optional.
 * -# Sections Consist of 1MB blocks of memory.
 * -# Large pages Consist of 64KB blocks of memory.
 * -# Small pages Consist of 4KB blocks of memory.
 *
 * Access to a memory region is controlled by the access permission bits and the domain field in the TLB entry.
 * Memory region attributes
 * Each TLB entry has an associated set of memory region attributes. These control accesses to the caches,
 * how the write buffer is used, and if the memory region is Shareable and therefore must be kept coherent.
 *
 * Related files:\n
 * \ref mmu.c\n
 * \ref mmu.h \n
 */

/*------------------------------------------------------------------------------ */
/*         Headers                                                               */
/*------------------------------------------------------------------------------ */

#include "chip.h"
#include "board.h"
#include "cortex-a/cp15.h"
#include "cortex-a/mmu.h"

#include "compiler.h"

/*------------------------------------------------------------------------------ */
/*         Local variables                                                       */
/*------------------------------------------------------------------------------ */

ALIGNED(16384) static uint32_t _tlb[4096];

/*------------------------------------------------------------------------------ */
/*         Exported functions                                                    */
/*------------------------------------------------------------------------------ */

void mmu_initialize(void)
{
	board_setup_tlb(_tlb);
	cp15_write_ttb((unsigned int)_tlb);
	/* Program the domain access register */
	/* only domain 15: access are not checked */
	cp15_write_domain_access_control(0xC0000000);
	asm volatile("": : :"memory");
	asm("dsb");
	asm("isb");
}