FreeRTOS/Demo/CORTEX_A5_SAMA5D2x_Xplained_IAR/AtmelFiles/target/sama5d2/toolchain/iar/sram.mac

/*********************************************************************
* execUserReset()
*********************************************************************/
execUserReset()
{
    __message "------------------------------ execUserReset ---------------------------------";

    /* Reset peripherals (using RSTC_CR) */
    __writeMemory32(0xA5000004, 0xF8048000, "Memory");

    /* Disable Watchdog (using WDT_MR) */
    __writeMemory32(0x00008000, 0xF8048044, "Memory");

    /* Disable D-Cache, I-Cache and MMU */
    __jtagCP15WriteReg(1, 0, 0, 0, 0x00C50078);

    /* Reset L2 Cache controller */
    __writeMemory32(0x0, 0x00A00100, "Memory");

    /* Disable DDR clock and MPDDRC controller to avoid */
    /* corrupted RAM data on soft reset. */
    __writeMemory32(0x00000004, 0xF0014004, "Memory");
    __writeMemory32(0x00002000, 0xF0014014, "Memory");

    /* Disable all interrupts and go to supervisor mode */
    #CPSR = 0xD3;

    /* Zero registers (cannot reset core because it will disable JTAG) */
    #R8_fiq = 0;
    #R9_fiq = 0;
    #R10_fiq = 0;
    #R11_fiq = 0;
    #R12_fiq = 0;
    #SP_fiq = 0;
    #LR_fiq = 0;
    #SPSR_fiq = 0;
    #SP_irq = 0;
    #LR_irq = 0;
    #SPSR_irq = 0;
    #SP_abt = 0;
    #LR_abt = 0;
    #SPSR_abt = 0;
    #SP_und = 0;
    #LR_und = 0;
    #SPSR_und = 0;
    #SP_svc = 0;
    #LR_svc = 0;
    #SPSR_svc = 0;
    #R0 = 0;
    #R1 = 0;
    #R2 = 0;
    #R3 = 0;
    #R4 = 0;
    #R5 = 0;
    #R6 = 0;
    #R7 = 0;
    #R8_usr = 0;
    #R9_usr = 0;
    #R10_usr = 0;
    #R11_usr = 0;
    #R12_usr = 0;
    #SP_usr = 0;
    #LR_usr = 0;

    /* Initialize PC */
    #PC = 0x200000;
}

/*********************************************************************
* execUserPreload()
*********************************************************************/
execUserPreload()
{
    __message "------------------------------ execUserPreload ---------------------------------";
}