| /* |
| * Copyright (C) 2013 Ambarella,Inc. - http://www.ambarella.com/ |
| * Author: Cao Rongrong <rrcao@ambarella.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| /include/ "skeleton.dtsi" |
| |
| / { |
| compatible = "ambarella,s2e"; |
| interrupt-parent = <&intc>; |
| |
| aliases { |
| serial0 = &uart0; |
| serial1 = &uart1; |
| serial2 = &uart2; |
| serial3 = &uart3; |
| nand = &nand0; |
| sd0 = &sdmmc0; |
| sd1 = &sdmmc1; |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| spi0 = &spi0; |
| spi1 = &spi1; |
| ethernet0 = &mac0; |
| }; |
| |
| /* the memory node will be overwritten in Amboot, |
| * here is just the default value. */ |
| memory { |
| device_type = "memory"; |
| reg = <0x00200000 0x07e00000>; /* 126M */ |
| }; |
| |
| chosen { |
| linux,stdout-path = &uart0; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| amb,core-div = <1>; |
| clock-latency = <100000>; |
| /* the highest frequency is gotten in runtime */ |
| cpufreq_tbl = < /*core_clk cortex_clk*/ |
| 24000 24000 |
| 108000 504000>; |
| cpu@a00 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <0xa00>; |
| }; |
| cpu@a01 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <0xa01>; |
| }; |
| }; |
| |
| apb@70000000 { /* APB */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x70000000 0x01000000>; |
| ranges; |
| |
| timer7: timer@7000b064 { |
| compatible = "ambarella,clock-source"; |
| reg = <0x7000b064 0x10 0x7000b030 0x4>; |
| interrupts = <62 0x1>; |
| ctrl-offset = <24>; /* bit offset in timer-ctrl reg */ |
| }; |
| |
| timer8: timer@7000b074 { |
| compatible = "ambarella,clock-event"; |
| reg = <0x7000b074 0x10 0x7000b030 0x4>; |
| interrupts = <63 0x1>; |
| ctrl-offset = <28>; /* bit offset in timer-ctrl reg */ |
| }; |
| |
| /* timer6 and timer5 */ |
| local_timer: timer@7000b054 { |
| compatible = "ambarella,local-clock-event"; |
| reg = <0x7000b054 0x10 0x7000b030 0x4 0x7000b044 0x10 0x7000b030 0x4>; |
| interrupts = <61 0x1 60 0x1>; |
| ctrl-offset = <20 16>; /* bit offset in timer-ctrl reg */ |
| }; |
| |
| uart0: uart@70005000 { |
| compatible = "ambarella,uart"; |
| reg = <0x70005000 0x100>; |
| interrupts = <9 0x04>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart0_pins>; |
| status = "ok"; |
| /* amb,tx-fifo-fix; */ |
| }; |
| |
| uart1: uart@7001f000 { |
| compatible = "ambarella,uart"; |
| reg = <0x7001f000 0x100>; |
| interrupts = <25 0x04>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_pins>; |
| status = "ok"; |
| amb,msr-used; /* use Modem Status Register */ |
| amb,txdma-used; |
| amb,rxdma-used; |
| /* amb,tx-fifo-fix; */ |
| }; |
| |
| uart2: uart@70014000 { |
| compatible = "ambarella,uart"; |
| reg = <0x70014000 0x100>; |
| interrupts = <91 0x04>; |
| status = "disabled"; |
| amb,msr-used; /* use Modem Status Register */ |
| /* amb,tx-fifo-fix; */ |
| }; |
| |
| uart3: uart@70015000 { |
| compatible = "ambarella,uart"; |
| reg = <0x70015000 0x100>; |
| interrupts = <92 0x04>; |
| status = "disabled"; |
| amb,msr-used; /* use Modem Status Register */ |
| /* amb,tx-fifo-fix; */ |
| }; |
| |
| i2c0: i2c@70003000 { |
| compatible = "ambarella,i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x70003000 0x1000>; |
| interrupts = <19 0x04>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins>; |
| clock-frequency = <100000>; |
| amb,i2c-class = <0x81>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@70007000 { |
| compatible = "ambarella,i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x70007000 0x1000>; |
| interrupts = <36 0x04>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c1_pins>; |
| clock-frequency = <100000>; |
| amb,i2c-class = <0x08>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@70013000 { |
| compatible = "ambarella,i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x70013000 0x1000>; |
| interrupts = <90 0x04>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c2_pins>; |
| clock-frequency = <100000>; |
| amb,i2c-class = <0x81>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@70002000 { |
| compatible = "ambarella,spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x70002000 0x1000>; |
| interrupts = <20 0x4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi0_pins>; |
| amb,clk-freq = <60000000>; |
| amb,msb-first-only; |
| }; |
| |
| spi_slave@7001e000 { |
| compatible = "ambarella,spi-slave"; |
| reg = <0x7001e000 0x1000>; |
| interrupts = <26 0x4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_slave_pins>; |
| status = "disabled"; |
| }; |
| |
| adc@7000d000 { |
| compatible = "ambarella,adc"; |
| reg = <0x7000d000 0x1000>; |
| interrupts = <34 0x4>; |
| clock-frequency = <3000000>; |
| }; |
| |
| ir@70006000 { |
| compatible = "ambarella,ir"; |
| reg = <0x70006000 0x1000>; |
| interrupts = <22 0x4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ir_pins>; |
| }; |
| |
| wdt@7000c000 { |
| compatible = "ambarella,wdt"; |
| reg = <0x7000c000 0x1000>; |
| /* interrupts = <21 0x4>; */ |
| timeout-sec = <15>; |
| }; |
| |
| rtc@7000d000 { |
| compatible = "ambarella,rtc"; |
| reg = <0x7000d000 0x1000>; |
| rtc,wakeup; |
| }; |
| |
| pwm: pwm@70004000 { |
| compatible = "ambarella,pwm"; |
| reg = <0x70004000 0x1000 0x70008000 0x10>; |
| #pwm-cells = <3>; |
| }; |
| |
| pinctrl: pinctrl@70009000 { |
| compatible = "ambarella,pinctrl", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x70009000 0x1000>, |
| <0x7000a000 0x1000>, |
| <0x7000e000 0x1000>, |
| <0x70010000 0x1000>, |
| <0x70011000 0x1000>; |
| reg-names = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4"; |
| #gpio-range-cells = <3>; |
| |
| gpio: gpio@0 { |
| compatible = "ambarella,gpio"; |
| /* gpio interrupts to vic */ |
| interrupts = <10 0x04>, |
| <11 0x04>, |
| <30 0x04>, |
| <29 0x04>, |
| <48 0x04>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pinctrl 0 0 160>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| uart0_pins: uart0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x100e 0x100f>; |
| }; |
| |
| uart1_pins: uart1@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1034 0x1035>, |
| /* virtual pins, just for configuration purpose */ |
| <0x1021 0x0022 0x1032 0x1033>; |
| }; |
| |
| uart1_4pins: uart1_4pins@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1032 0x1033 0x1034 0x1035>, |
| /* virtual pins, just for configuration purpose */ |
| <0x1021 0x0022>; |
| }; |
| |
| uart2_pins: uart2@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x100a 0x1012>; |
| }; |
| |
| uart3_pins: uart3@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1013 0x1014>; |
| }; |
| |
| nand0_pins: nand0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1027>; /* just WP is shared with GPIO */ |
| }; |
| |
| sdmmc0_pins: sdmmc0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1041 0x1042 0x1043 0x1044>; |
| }; |
| |
| sdmmc1_pins_1bit: sdmmc1@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1045 0x1046 0x1047 |
| 0x104b 0x104c>; |
| }; |
| |
| sdmmc1_pins_4bit: sdmmc1@1 { |
| reg = <1>; |
| amb,pinmux-ids = <0x1045 0x1046 0x1047 0x1048 |
| 0x1049 0x104a 0x104b 0x104c>; |
| }; |
| |
| eth_pins: eth0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1008 0x101c 0x101d 0x101e 0x101f |
| 0x1028 0x1029 0x102a 0x102b 0x102c |
| 0x102f 0x1030 0x1052 0x1053 0x105c |
| 0x105d 0x105e 0x105f 0x107c 0x107d |
| 0x107e 0x107f 0x1080 0x1088 0x1089 |
| 0x108a>; |
| }; |
| |
| i2c0_pins: i2c0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1000 0x1001>; |
| }; |
| |
| i2c1_pins: i2c1@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1056 0x1057>; |
| }; |
| |
| i2c2_pins: i2c2@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1024 0x1025>, |
| /* virtual pins, just for configuration purpose */ |
| <0x1011>; |
| }; |
| |
| ir_pins: ir0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1023>; |
| }; |
| |
| i2s0_pins: i2s0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x104d 0x104e 0x104f 0x1050 0x1051>, |
| /* virtual pins, just for configuration purpose.*/ |
| <0x0064 0x0065>; |
| }; |
| |
| usb_host_pins: uhc0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1007 0x1009>, |
| /* virtual pins, just for configuration purpose. |
| EHCI_PRT_PWR and APP_PRT_OVCURR share the hw |
| mode with SPI enable pin. */ |
| <0x1060 0x1061>; |
| }; |
| |
| pwm0_pins: pwm0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x102d>; |
| }; |
| |
| pwm1_pins: pwm1@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x102e>; |
| }; |
| |
| pwm2_pins: pwm2@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1032>, |
| /* virtual pins, just for |
| configuration purpose.*/ |
| <0x0021 0x0022>; |
| }; |
| |
| pwm3_pins: pwm3@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1033>, |
| /* virtual pins, just for |
| configuration purpose. |
| <0x0022>: kernel may throw out error, |
| ignore it.*/ |
| <0x0022 0x0023>; |
| }; |
| |
| pwmVD_pins: pwmVD@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1010>; |
| }; |
| |
| spi0_pins: spi0@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1002 0x1003 0x1004>; |
| }; |
| |
| spi1_pins: spi1@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1058 0x1059 0x105A>; |
| }; |
| |
| spi_slave_pins: spi_slave@0 { |
| reg = <0>; |
| amb,pinmux-ids = <0x1032 0x1033 0x1034 0x1035>, |
| /* virtual pins, just for |
| configuration purpose.*/ |
| <0x0021 0x1022>; |
| }; |
| }; |
| }; |
| |
| ahb@60000000 { /* AHB */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x60000000 0x01000000>; |
| ranges; |
| |
| intc: interrupt-controller@60003000 { |
| compatible = "ambarella,vic"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| reg = <0x60003000 0x1000>, |
| <0x60010000 0x1000>, |
| <0x6001c000 0x1000>; |
| }; |
| |
| dma: dma@60005000 { |
| compatible = "ambarella,dma"; |
| reg = <0x60005000 0x1000>; |
| interrupts = <15 0x4>; |
| #dma-cells = <2>; |
| dma-channels = <8>; |
| dma-requests = <8>; |
| dma-trans-type = <1 1 1 1 1 1 1 1>; /* 0-memcpy ,1-slave*/ |
| amb,copy-align = <0>; |
| /* support pause/resume/stop */ |
| amb,support-prs; |
| }; |
| |
| nand0: nand@60001000 { |
| compatible = "ambarella,nand"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x60001000 0x1000>, /* fio reg address */ |
| <0x60012000 0x1000>, /* fdma reg address */ |
| <0x60000000 0x4>; /* fifo base */ |
| interrupts = <16 0x04>, /* fio_cmd_irq */ |
| <17 0x04>, /* fio_dma_irq */ |
| <33 0x04>; /* fdma_irq */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&nand0_pins>; |
| nand-on-flash-bbt; |
| amb,enable-wp; |
| /* amb,soft-ecc = <1>; */ |
| }; |
| |
| spinor0: spinor@6000d000 { |
| compatible = "ambarella,spinor"; |
| reg = <0x6000d000 0x2ff>, /* spi nor controller */ |
| <0x60005300 0x20>; /* dma reg */ |
| status = "disabled"; |
| }; |
| |
| spi1: spi@6001f000 { |
| compatible = "ambarella,spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x6001f000 0x1000>; |
| interrupts = <53 0x4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi1_pins>; |
| amb,clk-freq = <54000000>; |
| status = "disabled"; |
| }; |
| |
| i2s0: i2s@6000a000 { |
| compatible = "ambarella,i2s"; |
| reg = <0x6000a000 0x1000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2s0_pins>; |
| amb,i2s-channels = <2>; |
| amb,default-mclk = <12288000>; |
| dmas = <&dma 2 1>, |
| <&dma 1 1>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| udc@60006000 { |
| compatible = "ambarella,udc"; |
| reg = <0x60006000 0x2000 0x70170088 0x4>; |
| interrupts = <4 0x04>; |
| amb,usbphy = <&usbphy>; |
| }; |
| |
| ehci@60018000 { |
| compatible = "ambarella,ehci"; |
| reg = <0x60018000 0x1000>; |
| interrupts = <73 0x04>; |
| amb,usbphy = <&usbphy>; |
| }; |
| |
| ohci@60019000 { |
| compatible = "ambarella,ohci"; |
| reg = <0x60019000 0x1000>; |
| interrupts = <89 0x04>; |
| amb,usbphy = <&usbphy>; |
| }; |
| |
| sdmmc0: sdmmc0@60002000 { |
| compatible = "ambarella,sdmmc"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x60002000 0x1000>, |
| <0x60001000 0x80>, /* fio reg address */ |
| <0x70170340 0x8>; |
| interrupts = <18 0x4>; |
| amb,clk-name = "gclk_sd"; |
| amb,wait-tmo = <10000>; /* in millisecond */ |
| amb,switch_vol_tmo = <20>; |
| amb,max-blk-size = <524288>; /* valid value: 4K<<n */ |
| amb,auto-tuning; |
| amb,phy-type = <0>;/*0:rct phy, 1: sd controller phy, 2: for s2e*/ |
| amb,phy-timing = <0x00000001 0x04070000 0x00000000>, |
| <0x000000a4 0x00000005 0x00001111>, |
| <0x00000040 0x00000001 0x00001111>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&sdmmc0_pins>; |
| |
| slot@0 { |
| reg = <0>; |
| global-id = <0>; |
| max-frequency = <50000000>; |
| bus-width = <8>; |
| amb,caps-adma; |
| cap-sdio-irq; |
| }; |
| }; |
| |
| sdmmc1: sdmmc1@6000c000 { |
| compatible = "ambarella,sdmmc"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x6000c000 0x1000>, |
| <0x60001000 0x80>, /* fio reg address */ |
| <0x701701d0 0x4>; |
| interrupts = <52 0x4>; |
| amb,clk-name = "gclk_sdio"; |
| amb,wait-tmo = <10000>; /* in millisecond */ |
| amb,switch_vol_tmo = <20>; |
| amb,max-blk-size = <524288>; /* valid value: 4K<<n */ |
| amb,auto-tuning; |
| amb,phy-type = <2>;/*0:rct phy, 1: sd controller phy, 2: for s2e*/ |
| amb,phy-timing = <0x00000001 0x1c1f1c1f 0x00000000>, |
| <0x00000080 0x1c1f1c1f 0x00e0e000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&sdmmc1_pins_4bit>; |
| |
| slot@0 { |
| reg = <0>; |
| global-id = <1>; |
| max-frequency = <50000000>; |
| bus-width = <4>; |
| amb,caps-adma; |
| cap-sdio-irq; |
| }; |
| }; |
| |
| mac0: ethernet@6000e000 { |
| compatible = "ambarella,eth"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x6000e000 0x2000>; |
| interrupts = <27 0x4>; |
| amb,support-gmii; |
| amb,tx-ring-size = <64>; |
| amb,rx-ring-size = <64>; |
| amb,ipc-rx; |
| pinctrl-names = "default"; |
| pinctrl-0 = <ð_pins>; |
| }; |
| }; |
| |
| axi@f0000000 { /* AXI */ |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0xf0000000 0x00030000>; |
| ranges; |
| |
| crypto@f0020000 { |
| compatible = "ambarella,crypto"; |
| reg = <0xf0020000 0x8000>; |
| interrupts = <44 0x1>, <45 0x1>, <47 0x1>, <88 0x1>; |
| interrupt-names = "aes-irq", "des-irq", "md5-irq", "sha1-irq"; |
| amb,cap-md5-sha1; |
| amb,data-swap; |
| amb,reg-64bit; |
| }; |
| l2-cache@f0002000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0xf0002000 0x1000>; |
| cache-unified; |
| cache-level = <2>; |
| arm,tag_latency = <3 3 3>; |
| arm,data_latency = <3 3 3>; |
| }; |
| }; |
| |
| rct@70170000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x70170000 0x1000>; |
| ranges; |
| |
| usbphy: usbphy@70170050 { |
| compatible = "ambarella,usbphy"; |
| reg = <0x70170050 0x4 0x6001b00c 0x4 0x70170088 0x4>; |
| amb,host-phy-num = <1>; |
| }; |
| }; |
| |
| iav { |
| compatible = "ambarella,iav"; |
| }; |
| |
| bogus_bus { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| dummycodec: codec@0 { |
| compatible = "ambarella,dummycodec"; |
| }; |
| }; |
| }; |
