Project import
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..ee5d152
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,106 @@
+#
+# Copyright (c) 2010 Nest Labs, Inc.
+# All rights reserved.
+#
+# This document is the property of Nest Labs. It is considered
+# confidential and proprietary information.
+#
+# This document may not be reproduced or transmitted in any form,
+# in whole or in part, without the express written permission of
+# Nest Labs.
+#
+# Description:
+# This file is the make file for X-Loader, an initial program
+# loader (IPL) for embedded boards based on Texas Instruments
+# OMAP processors.
+#
+
+include pre.mak
+
+PackageRoot := .
+
+PackageName := x-loader
+
+PackageSeparator :=
+
+PackageVersion :=
+PackageSourceDir := $(PackageRoot)/$(PackageName)$(PackageSeparator)$(PackageVersion)
+
+PackageBuildMakefile = $(call GenerateBuildPaths,include/config.mk)
+
+CleanPaths += $(PackageLicenseFile)
+
+all: $(PackageDefaultGoal)
+
+# Generate the package license contents.
+
+$(PackageSourceDir)/README: source
+
+$(PackageLicenseFile): $(PackageSourceDir)/README
+ $(Echo) "Extracting \"$(call GenerateBuildRootEllipsedPath,$(@))\""
+ $(Verbose)$(SED) -n -e '10,25p' < $< > $@
+
+# We are building this package from version-controller source, so
+# there is nothing to do for this target goal.
+
+$(PackageSourceDir):
+
+# Prepare the sources.
+
+.PHONY: source
+source: | $(PackageSourceDir)
+
+# Patch the sources, if necessary.
+
+.PHONY: patch
+patch: source
+
+# X-Loader has no way of explicitly setting CC, LD, OBJCOPY, et al and
+# instead relies on the value of CROSS_COMPILE. Consequently, we have
+# to ensure that 'ToolBinDir' is in 'PATH' so that the kernel build
+# infrastructure can find $(CROSS_COMPILE)gcc, $(CROSS_COMPILE)ld, et al.
+
+configure build stage: PATH := $(PATH):$(ToolBinDir)
+configure build stage: CROSS_COMPILE := $(CCACHE) $(CROSS_COMPILE)
+
+# Generate the package build makefile.
+
+$(PackageBuildMakefile): | $(PackageSourceDir) $(BuildDirectory)
+ $(Verbose)unset MAKEFLAGS && \
+ $(MAKE) $(JOBSFLAG) -C $(PackageSourceDir) O=$(CURDIR)/$(BuildDirectory) \
+ INSTALL="$(INSTALL) $(INSTALLFLAGS)" \
+ $(XLoaderProductionConfig)
+
+# Configure the source for building.
+
+.PHONY: configure
+configure: source $(PackageBuildMakefile)
+
+# Build the source.
+
+.PHONY: build
+build: configure
+ $(Verbose)unset MAKEFLAGS && \
+ $(MAKE) $(JOBSFLAG) -C $(PackageSourceDir) O=$(CURDIR)/$(BuildDirectory) \
+ INSTALL="$(INSTALL) $(INSTALLFLAGS)" \
+ all
+
+# Stage the build to a temporary installation area.
+#
+# X-Loader does not support a notion of installing, so we have to
+# cherry-pick the components we want from the build directory and
+# copy/install them to the results directory.
+
+.PHONY: stage
+stage: copy
+
+.PHONY: copy
+$(call GenerateResultPaths,fw/x-loader,x-load.bin) copy: build | $(ResultDirectory)
+ $(Verbose)cp -f $(wildcard $(call GenerateBuildPaths,x-load*)) $(ResultDirectory)
+ $(Verbose)cp -f $(call GenerateBuildPaths,System.map) $(ResultDirectory)
+
+clean:
+ $(Verbose)$(RM) $(RMFLAGS) -r $(BuildDirectory)
+ $(Verbose)$(RM) $(RMFLAGS) -r $(ResultDirectory)
+
+include post.mak
diff --git a/x-loader.version b/x-loader.version
new file mode 100644
index 0000000..dbf095b
--- /dev/null
+++ b/x-loader.version
@@ -0,0 +1 @@
+1.46_OMAPPSP_03.00.01.06
diff --git a/x-loader/.file-list b/x-loader/.file-list
new file mode 100644
index 0000000..c1d5069
--- /dev/null
+++ b/x-loader/.file-list
@@ -0,0 +1,111 @@
+.@@/main/x-load_tid_int_x.x/2
+./Makefile@@/main/x-load_tid_int_x.x/5
+./README@@/main/x-load_tid_int_x.x/3
+./arm_config.mk@@/main/x-load_tid_int_x.x/1
+./board@@/main/x-load_tid_int_x.x/4
+./board/omap1710h3@@/main/x-load_tid_int_x.x/1
+./board/omap1710h3/Makefile@@/main/x-load_tid_int_x.x/1
+./board/omap1710h3/config.mk@@/main/x-load_tid_int_x.x/1
+./board/omap1710h3/omap1710h3.c@@/main/x-load_tid_int_x.x/1
+./board/omap1710h3/platform.S@@/main/x-load_tid_int_x.x/1
+./board/omap1710h3/x-load.lds@@/main/x-load_tid_int_x.x/1
+./board/omap2420h4@@/main/x-load_tid_int_x.x/1
+./board/omap2420h4/Makefile@@/main/x-load_tid_int_x.x/1
+./board/omap2420h4/config.mk@@/main/x-load_tid_int_x.x/1
+./board/omap2420h4/omap2420h4.c@@/main/x-load_tid_int_x.x/3
+./board/omap2420h4/platform.S@@/main/x-load_tid_int_x.x/3
+./board/omap2420h4/x-load.lds@@/main/x-load_tid_int_x.x/1
+./board/omap2430sdp@@/main/x-load_tid_int_x.x/2
+./board/omap2430sdp/Makefile@@/main/x-load_tid_int_x.x/2
+./board/omap2430sdp/config.mk@@/main/x-load_tid_int_x.x/1
+./board/omap2430sdp/omap2430sdp.c@@/main/x-load_tid_int_x.x/7
+./board/omap2430sdp/platform.S@@/main/x-load_tid_int_x.x/2
+./board/omap2430sdp/x-load.lds@@/main/x-load_tid_int_x.x/1
+./board/omap3430sdp@@/main/x-load_tid_int_x.x/1
+./board/omap3430sdp/Makefile@@/main/x-load_tid_int_x.x/1
+./board/omap3430sdp/config.mk@@/main/x-load_tid_int_x.x/1
+./board/omap3430sdp/omap3430sdp.c@@/main/x-load_tid_int_x.x/2
+./board/omap3430sdp/platform.S@@/main/x-load_tid_int_x.x/2
+./board/omap3430sdp/x-load.lds@@/main/x-load_tid_int_x.x/1
+./config.mk@@/main/x-load_tid_int_x.x/2
+./cpu@@/main/x-load_tid_int_x.x/3
+./cpu/arm1136@@/main/x-load_tid_int_x.x/1
+./cpu/arm1136/Makefile@@/main/x-load_tid_int_x.x/1
+./cpu/arm1136/config.mk@@/main/x-load_tid_int_x.x/7
+./cpu/arm1136/cpu.c@@/main/x-load_tid_int_x.x/1
+./cpu/arm1136/start.S@@/main/x-load_tid_int_x.x/1
+./cpu/arm926ejs@@/main/x-load_tid_int_x.x/1
+./cpu/arm926ejs/Makefile@@/main/x-load_tid_int_x.x/1
+./cpu/arm926ejs/config.mk@@/main/x-load_tid_int_x.x/3
+./cpu/arm926ejs/cpu.c@@/main/x-load_tid_int_x.x/1
+./cpu/arm926ejs/start.S@@/main/x-load_tid_int_x.x/2
+./cpu/omap3@@/main/x-load_tid_int_x.x/1
+./cpu/omap3/Makefile@@/main/x-load_tid_int_x.x/1
+./cpu/omap3/config.mk@@/main/x-load_tid_int_x.x/1
+./cpu/omap3/cpu.c@@/main/x-load_tid_int_x.x/1
+./cpu/omap3/start.S@@/main/x-load_tid_int_x.x/1
+./drivers@@/main/x-load_tid_int_x.x/3
+./drivers/Makefile@@/main/x-load_tid_int_x.x/3
+./drivers/k9f5616.c@@/main/x-load_tid_int_x.x/2
+./drivers/k9k1216.c@@/main/x-load_tid_int_x.x/1
+./drivers/ns16550.c@@/main/x-load_tid_int_x.x/2
+./drivers/onenand.c@@/main/x-load_tid_int_x.x/1
+./drivers/onenand_regs.h@@/main/x-load_tid_int_x.x/1
+./drivers/serial.c@@/main/x-load_tid_int_x.x/1
+./include@@/main/x-load_tid_int_x.x/1
+./include/asm@@/main/x-load_tid_int_x.x/3
+./include/asm/arch-arm1136@@/main/x-load_tid_int_x.x/3
+./include/asm/arch-arm1136/bits.h@@/main/x-load_tid_int_x.x/1
+./include/asm/arch-arm1136/clocks.h
+./include/asm/arch-arm1136/clocks242x.h
+./include/asm/arch-arm1136/clocks243x.h
+./include/asm/arch-arm1136/mem.h
+./include/asm/arch-arm1136/omap2420.h@@/main/x-load_tid_int_x.x/3
+./include/asm/arch-arm1136/omap2430.h@@/main/x-load_tid_int_x.x/2
+./include/asm/arch-arm1136/sizes.h@@/main/x-load_tid_int_x.x/1
+./include/asm/arch-arm1136/sys_info.h@@/main/x-load_tid_int_x.x/1
+./include/asm/arch-arm926ejs@@/main/x-load_tid_int_x.x/1
+./include/asm/arch-arm926ejs/sizes.h@@/main/x-load_tid_int_x.x/1
+./include/asm/arch-omap3@@/main/x-load_tid_int_x.x/1
+./include/asm/arch-omap3/bits.h
+./include/asm/arch-omap3/clocks.h
+./include/asm/arch-omap3/clocks343x.h
+./include/asm/arch-omap3/cpu.h
+./include/asm/arch-omap3/mem.h
+./include/asm/arch-omap3/mux.h
+./include/asm/arch-omap3/omap3430.h
+./include/asm/arch-omap3/sizes.h
+./include/asm/arch-omap3/sys_info.h
+./include/asm/arch-omap3/sys_proto.h
+./include/asm/atomic.h@@/main/x-load_tid_int_x.x/1
+./include/asm/posix_types.h@@/main/x-load_tid_int_x.x/1
+./include/asm/proc-armv@@/main/x-load_tid_int_x.x/1
+./include/asm/setup.h@@/main/x-load_tid_int_x.x/1
+./include/asm/sizes.h@@/main/x-load_tid_int_x.x/1
+./include/asm/string.h@@/main/x-load_tid_int_x.x/1
+./include/asm/types.h@@/main/x-load_tid_int_x.x/1
+./include/asm/x-load-arm.h@@/main/x-load_tid_int_x.x/1
+./include/common.h@@/main/x-load_tid_int_x.x/2
+./include/configs@@/main/x-load_tid_int_x.x/4
+./include/configs/omap1510.h@@/main/x-load_tid_int_x.x/1
+./include/configs/omap1710h3.h@@/main/x-load_tid_int_x.x/2
+./include/configs/omap2420h4.h@@/main/x-load_tid_int_x.x/4
+./include/configs/omap2430sdp.h@@/main/x-load_tid_int_x.x/6
+./include/configs/omap3430sdp.h@@/main/x-load_tid_int_x.x/1
+./include/linux@@/main/x-load_tid_int_x.x/1
+./include/linux/config.h@@/main/x-load_tid_int_x.x/1
+./include/linux/posix_types.h@@/main/x-load_tid_int_x.x/1
+./include/linux/stddef.h@@/main/x-load_tid_int_x.x/1
+./include/linux/types.h@@/main/x-load_tid_int_x.x/1
+./include/ns16550.h@@/main/x-load_tid_int_x.x/2
+./lib@@/main/x-load_tid_int_x.x/2
+./lib/Makefile@@/main/x-load_tid_int_x.x/2
+./lib/_udivsi3.S@@/main/x-load_tid_int_x.x/1
+./lib/_umodsi3.S@@/main/x-load_tid_int_x.x/1
+./lib/board.c@@/main/x-load_tid_int_x.x/8
+./lib/div0.c@@/main/x-load_tid_int_x.x/1
+./lib/ecc.c@@/main/x-load_tid_int_x.x/1
+./lib/printf.c@@/main/x-load_tid_int_x.x/1
+./mkconfig@@/main/x-load_tid_int_x.x/1
+./scripts@@/main/x-load_tid_int_x.x/1
+./scripts/mkoneboot.sh@@/main/x-load_tid_int_x.x/1
diff --git a/x-loader/Makefile b/x-loader/Makefile
new file mode 100644
index 0000000..2c43dae
--- /dev/null
+++ b/x-loader/Makefile
@@ -0,0 +1,386 @@
+#
+# (C) Copyright 2004-2006, Texas Instruments, <www.ti.com>
+# Jian Zhang <jzhang@ti.com>
+#
+# (C) Copyright 2000-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+VERSION = 1
+PATCHLEVEL = 46
+SUBLEVEL =
+EXTRAVERSION =
+ifneq "$(SUBLEVEL)" ""
+X_LOADER_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+else
+X_LOADER_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION)
+endif
+TIMESTAMP_FILE = $(obj)include/timestamp_autogenerated.h
+VERSION_FILE = $(obj)include/version_autogenerated.h
+
+HOSTARCH := $(shell uname -m | \
+ sed -e s/i.86/i386/ \
+ -e s/sun4u/sparc64/ \
+ -e s/arm.*/arm/ \
+ -e s/sa110/arm/ \
+ -e s/ppc64/powerpc/ \
+ -e s/ppc/powerpc/ \
+ -e s/macppc/powerpc/\
+ -e s/sh.*/sh/)
+
+HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
+ sed -e 's/\(cygwin\).*/cygwin/')
+
+# Set shell to bash if possible, otherwise fall back to sh
+SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+ else if [ -x /bin/bash ]; then echo /bin/bash; \
+ else echo sh; fi; fi)
+
+export HOSTARCH HOSTOS SHELL
+
+# Deal with colliding definitions from tcsh etc.
+VENDOR=
+
+#########################################################################
+# Allow for silent builds
+ifeq (,$(findstring s,$(MAKEFLAGS)))
+XECHO = echo
+else
+XECHO = :
+endif
+
+#########################################################################
+#
+# X-loader build supports producing a object files to the separate external
+# directory. Two use cases are supported:
+#
+# 1) Add O= to the make command line
+# 'make O=/tmp/build all'
+#
+# 2) Set environement variable BUILD_DIR to point to the desired location
+# 'export BUILD_DIR=/tmp/build'
+# 'make'
+#
+# The second approach can also be used with a MAKEALL script
+# 'export BUILD_DIR=/tmp/build'
+# './MAKEALL'
+#
+# Command line 'O=' setting overrides BUILD_DIR environent variable.
+#
+# When none of the above methods is used the local build is performed and
+# the object files are placed in the source directory.
+#
+
+ifdef O
+ifeq ("$(origin O)", "command line")
+BUILD_DIR := $(O)
+endif
+endif
+
+ifneq ($(BUILD_DIR),)
+saved-output := $(BUILD_DIR)
+
+# Attempt to create a output directory.
+$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR})
+
+# Verify if it was successful.
+BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd)
+$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist))
+endif # ifneq ($(BUILD_DIR),)
+
+OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR))
+SRCTREE := $(CURDIR)
+TOPDIR := $(SRCTREE)
+LNDIR := $(OBJTREE)
+export TOPDIR SRCTREE OBJTREE
+
+MKCONFIG := $(SRCTREE)/mkconfig
+export MKCONFIG
+
+ifneq ($(OBJTREE),$(SRCTREE))
+REMOTE_BUILD := 1
+export REMOTE_BUILD
+endif
+
+# $(obj) and (src) are defined in config.mk but here in main Makefile
+# we also need them before config.mk is included which is the case for
+# some targets like unconfig, clean, clobber, distclean, etc.
+ifneq ($(OBJTREE),$(SRCTREE))
+obj := $(OBJTREE)/
+src := $(SRCTREE)/
+else
+obj :=
+src :=
+endif
+export obj src
+
+#########################################################################
+
+# The "tools" are needed early, so put this first
+# Don't include stuff already done in $(LIBS)
+SUBDIRS = tools
+.PHONY : $(SUBDIRS)
+
+ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk))
+
+# Include autoconf.mk before config.mk so that the config options are available
+# to all top level build files. We need the dummy all: target to prevent the
+# dependency target in autoconf.mk.dep from being the default.
+all:
+sinclude $(obj)include/autoconf.mk.dep
+sinclude $(obj)include/autoconf.mk
+
+# load ARCH, BOARD, and CPU configuration
+include $(obj)include/config.mk
+export ARCH CPU BOARD VENDOR SOC
+
+# set default to nothing for native builds
+ifeq ($(HOSTARCH),$(ARCH))
+CROSS_COMPILE ?=
+endif
+
+# load other configuration
+include $(TOPDIR)/config.mk
+
+#########################################################################
+# X-Load objects....order is important (i.e. start must be first)
+
+OBJS = $(CPUDIR)/start.o
+
+OBJS := $(addprefix $(obj),$(OBJS))
+
+LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
+ "board/$(VENDOR)/common/lib$(VENDOR).a"; fi)
+LIBS += $(CPUDIR)/lib$(CPU).a
+LIBS += lib/lib$(ARCH).a
+LIBS += common/libcommon.a
+LIBS += fs/fat/libfat.a
+LIBS += disk/libdisk.a
+LIBS += drivers/mtd/nand/libnand.a
+LIBS += drivers/mtd/onenand/libonenand.a
+LIBS += drivers/rtc/librtc.a
+LIBS += drivers/serial/libserial.a
+LIBS += drivers/usb/libusb.a
+
+LIBS := $(addprefix $(obj),$(LIBS))
+.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
+
+LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a
+LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
+
+# Add GCC lib
+PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBS += $(PLATFORM_LIBGCC)
+export PLATFORM_LIBS
+
+__OBJS := $(subst $(obj),,$(OBJS))
+__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
+
+#########################################################################
+#########################################################################
+
+# Always append ALL so that arch config.mk's can add custom ones
+ALL += $(obj)x-load.srec $(obj)x-load.bin $(obj)x-load.bin.ift $(obj)System.map
+
+all: $(ALL)
+
+$(obj)x-load.hex: $(obj)x-load
+ $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
+
+$(obj)x-load.srec: $(obj)x-load
+ $(OBJCOPY) -O srec $< $@
+
+$(obj)x-load.bin: $(obj)x-load
+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(obj)x-load.bin.ift: $(obj)x-load.bin
+ $(obj)tools/signGP $<
+
+$(obj)x-load.dis: $(obj)x-load
+ $(OBJDUMP) -d $< > $@
+
+GEN_XLOAD = \
+ UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+ sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
+ -Map x-load.map -o x-load
+$(obj)x-load: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)x-load.lds
+ $(GEN_XLOAD)
+
+$(OBJS): depend
+ $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
+
+$(LIBS): depend $(SUBDIRS)
+ $(MAKE) -C $(dir $(subst $(obj),,$@))
+
+$(LIBBOARD): depend $(LIBS)
+ $(MAKE) -C $(dir $(subst $(obj),,$@))
+
+$(SUBDIRS): depend
+ $(MAKE) -C $@ all
+
+$(LDSCRIPT): depend
+ $(MAKE) -C $(dir $@) $(notdir $@)
+
+$(obj)x-load.lds: $(LDSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+
+$(obj)oneboot: $(obj)x-load.bin
+ scripts/mkoneboot.sh
+$(VERSION_FILE):
+ @( printf '#define X_LOADER_VERSION "Texas Instruments X-Loader %s%s"\n' "$(X_LOADER_VERSION)" \
+ '$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ) > $@.tmp
+ @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@
+
+$(TIMESTAMP_FILE):
+ @LC_ALL=C date +'#define X_LOADER_DATE "%b %d %C%y"' > $@
+ @LC_ALL=C date +'#define X_LOADER_TIME "%T"' >> $@
+
+# Explicitly make _depend in subdirs containing multiple targets to prevent
+# parallel sub-makes creating .depend files simultaneously.
+depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE)
+ for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \
+ $(MAKE) -C $$dir _depend ; done
+
+TAG_SUBDIRS = $(SUBDIRS)
+TAG_SUBDIRS += $(dir $(__LIBS))
+TAG_SUBDIRS += include
+
+tags ctags:
+ ctags -w -o $(obj)ctags `find $(TAG_SUBDIRS) \
+ -name '*.[chS]' -print`
+
+etags:
+ etags -a -o $(obj)etags `find $(TAG_SUBDIRS) \
+ -name '*.[chS]' -print`
+cscope:
+ find $(TAG_SUBDIRS) -name '*.[chS]' -print > cscope.files
+ cscope -b -q -k
+
+SYSTEM_MAP = \
+ $(NM) $1 | \
+ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+ LC_ALL=C sort
+$(obj)System.map: $(obj)x-load
+ @$(call SYSTEM_MAP,$<) > $(obj)System.map
+
+
+
+#########################################################################
+else # !config.mk
+all $(obj)x-load.hex $(obj)x-load.srec $(obj)x-load.bin \
+$(obj)x-load.dis $(obj)x-load \
+$(obj)oneboot \
+$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) \
+depend dep tags ctags etags cscope $(obj)System.map:
+ @echo "System not configured - see README" >&2
+ @ exit 1
+
+tools:
+ $(MAKE) -C tools
+tools-all:
+ $(MAKE) -C tools HOST_TOOLS_ALL=y
+endif # config.mk
+
+#########################################################################
+
+unconfig:
+ @rm -f $(obj)include/config.h $(obj)include/config.mk
+
+%_config:: unconfig
+ @$(MKCONFIG) -A $(@:_config=)
+
+#
+# Functions to generate common board directory names
+#
+lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
+ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
+
+#========================================================================
+# ARM
+#========================================================================
+#########################################################################
+## OMAP1 (ARM92xT) Systems
+#########################################################################
+
+omap1710h3_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs omap1710h3
+
+#########################################################################
+## OMAP2 (ARM1136) Systems
+#########################################################################
+
+omap2420h4_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4
+
+omap2430sdp_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm1136 omap2430sdp
+
+#########################################################################
+## OMAP3 (ARM-CortexA8) Systems
+#########################################################################
+omap3430sdp_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm omap3 omap3430sdp
+
+omap3430labrador_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm omap3 omap3430labrador
+
+omap3evm_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm omap3 omap3evm
+
+am3517evm_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm omap3 am3517evm
+
+#########################################################################
+#########################################################################
+clean:
+ @rm -f $(obj)tools/signGP
+ @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
+ @find $(OBJTREE) -type f \
+ \( -name 'core' -o -name '*.bak' -o -name '*~' \
+ -o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
+ | xargs rm -f
+
+clobber: clean
+ @find $(OBJTREE) -type f \( -name .depend \
+ -o -name '*.srec' -o -name '*.bin' -o -name '*.bin.ift' \) \
+ -print0 \
+ | xargs -0 rm -f
+ @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \
+ $(obj)cscope.* $(obj)*.*~
+ @rm -f $(obj)x-load $(obj)x-load.map $(obj)x-load.hex $(ALL)
+ @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
+
+ifeq ($(OBJTREE),$(SRCTREE))
+mrproper \
+distclean: clobber unconfig
+else
+mrproper \
+distclean: clobber unconfig
+ rm -rf $(obj)*
+endif
+
+backup:
+ F=`basename $(TOPDIR)` ; cd .. ; \
+ gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
+
+#########################################################################
diff --git a/x-loader/README b/x-loader/README
new file mode 100644
index 0000000..ae2662a
--- /dev/null
+++ b/x-loader/README
@@ -0,0 +1,152 @@
+#
+# (C) Copyright 2004-2006 Texas Instruments
+#
+# Some cut/paste from U-Boot README
+# (C) Copyright 2000 - 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+Summary:
+========
+
+This directory contains the source code for X-Loader, an initial program
+loader for Embedded boards based on OMAP processors. X-Loader can be
+signed by Texas Instruments IFT and installed to Nand flash to achieve
+Nand booting.
+
+
+Status:
+=======
+
+The support for Texas Instruments H3 board (OMAP1710) has been implemented
+and tested. (May 2004)
+The support for Texas Instruments H4 board (OMAP2420) has been implemented
+and tested. (Nov 2004)
+The support for Texas Instruments 2430SDP board (OMAP2430) has been implemented
+and tested. (Jul 2006)
+The support for Texas Instruments 3430SDP board (OMAP3430) has been implemented
+and tested. (Dec 2006)
+
+
+Support for other OMAP boards can be added.
+
+
+Directory Hierarchy:
+====================
+
+- board Board dependent files
+- cpu CPU specific files
+- drivers Commonly used device drivers
+- lib Libraries
+
+- cpu/arm926ejs Files specific to ARM 926 CPUs
+- cpu/arm1136 Files specific to ARM 1136 CPUs
+- cpu/omap3 Files specific to ARM CortexA8 CPU
+
+
+- board/omap1710h3
+ Files specific to OMAP 1710 H3 boards
+- board/omap2420h4
+ Files specific to OMAP 2420 H4 boards
+- board/omap2430sdp
+ Files specific to OMAP 2430 2430sdp boards
+- board/omap3430sdp
+ Files specific to OMAP 3420sdp boards
+
+
+Software Configuration:
+=======================
+
+Configuration is usually done using C preprocessor defines. Configuration
+depends on the combination of board and CPU type; all such information is
+kept in a configuration file "include/configs/<board_name>.h".
+
+Example: For a H3 module, all configuration settings are in
+"include/configs/omap1710h3.h".
+
+For all supported boards there are ready-to-use default
+configurations available; just type "make <board_name>_config".
+
+Example: For a H3 module type:
+
+ cd x-load
+ make omap1710h3_config
+
+After a board has been configured, type "make" to build it supposing the
+needed cross tools are in your path.
+
+
+Image Format:
+=============
+
+X-Loader expects OS boot loader (e.g. U-Boot) in Nand flash using
+JFFS2 style ECC.
+
+
+Prepare Booting Nand Flash:
+===========================
+
+After you have built x-load.bin for your board, you need to do the
+followings to get it into Nand flash:
+
+1. Use Texas Instruments IFT to sign x-load.bin. This results in a
+signed image called x-load.bin.ift.
+2. Use Texas Instruments FlashPrep to generate a .out file using
+FlashWriterNand and specifying 0 as nand target address.
+3. Use Texas instrumnets Code Composer Studio to run the .out file
+which flashes x-load.bin.ift to Nand flash.
+
+Next you need to get your OS boot loader to Nand at the address your
+X-Loader expects. For the H3 example, you can use U-Boot to flash U-Boot.
+You can't use FlashWriterNand because it uses ROM code ECC style.
+
+
+More Information
+================
+
+OMAP1710 NAND Booting Design Document has more information.
+
+Implemenation notes:
+====================
+H3, H4 support NAND flash booting
+2430sdp & 3430sdp support OneNAND booting
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/x-loader/arm_config.mk b/x-loader/arm_config.mk
new file mode 100644
index 0000000..73d9625
--- /dev/null
+++ b/x-loader/arm_config.mk
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
diff --git a/x-loader/board/am3517evm/Makefile b/x-loader/board/am3517evm/Makefile
new file mode 100644
index 0000000..4ac2924
--- /dev/null
+++ b/x-loader/board/am3517evm/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2009
+# Texas Instruments, <www.ti.com>
+# Manikandan Pillai<mani.pillai@ti.com>
+# This file is copied from board/omap3evm/Makefile
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+OBJS := am3517evm.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/am3517evm/am3517evm.c b/x-loader/board/am3517evm/am3517evm.c
new file mode 100644
index 0000000..5e44be9
--- /dev/null
+++ b/x-loader/board/am3517evm/am3517evm.c
@@ -0,0 +1,908 @@
+/*
+ * (C) Copyright 2009
+ * Texas Instruments, <www.ti.com>
+ * Manikandan Pillai<mani.pillai@ti.com>
+ * This file is copied from board/omap3evm/omap3evm.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <part.h>
+#include <fat.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+
+/* Used to index into DPLL parameter tables */
+struct dpll_param {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+};
+
+typedef struct dpll_param dpll_param;
+
+#define MAX_SIL_INDEX 3
+
+/* Definitions for EMIF4 configuration values */
+#define EMIF4_TIM1_T_RP 0x3
+#define EMIF4_TIM1_T_RCD 0x3
+#define EMIF4_TIM1_T_WR 0x3
+#define EMIF4_TIM1_T_RAS 0x8
+#define EMIF4_TIM1_T_RC 0xA
+#define EMIF4_TIM1_T_RRD 0x2
+#define EMIF4_TIM1_T_WTR 0x2
+
+#define EMIF4_TIM2_T_XP 0x2
+#define EMIF4_TIM2_T_ODT 0x0
+#define EMIF4_TIM2_T_XSNR 0x1C
+#define EMIF4_TIM2_T_XSRD 0xC8
+#define EMIF4_TIM2_T_RTP 0x1
+#define EMIF4_TIM2_T_CKE 0x2
+
+#define EMIF4_TIM3_T_TDQSCKMAX 0x0
+#define EMIF4_TIM3_T_RFC 0x25
+#define EMIF4_TIM3_T_RAS_MAX 0x7
+
+#define EMIF4_PWR_IDLE 0x2
+#define EMIF4_PWR_DPD_EN 0x0
+#define EMIF4_PWR_PM_EN 0x0
+#define EMIF4_PWR_PM_TIM 0x0
+
+#define EMIF4_INITREF_DIS 0x0
+#define EMIF4_PASR 0x0
+#define EMIF4_REFRESH_RATE 0x50F
+
+/*
+ * SDRAM Config register
+ */
+#define EMIF4_CFG_SDRAM_TYP 0x2
+#define EMIF4_CFG_IBANK_POS 0x0
+#define EMIF4_CFG_DDR_TERM 0x0
+#define EMIF4_CFG_DDR2_DDQS 0x1
+#define EMIF4_CFG_DYN_ODT 0x0
+#define EMIF4_CFG_DDR_DIS_DLL 0x0
+#define EMIF4_CFG_SDR_DRV 0x0
+#define EMIF4_CFG_CWL 0x0
+#define EMIF4_CFG_NARROW_MD 0x0
+#define EMIF4_CFG_CL 0x5
+#define EMIF4_CFG_ROWSIZE 0x0
+#define EMIF4_CFG_IBANK 0x3
+#define EMIF4_CFG_EBANK 0x0
+#define EMIF4_CFG_PGSIZE 0x2
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_RD_LAT 0x6
+#define EMIF4_DDR1_PWRDN_DIS 0x0
+#define EMIF4_DDR1_STRBEN_EXT 0x0
+#define EMIF4_DDR1_DLL_MODE 0x0
+#define EMIF4_DDR1_VTP_DYN 0x0
+#define EMIF4_DDR1_LB_CK_SEL 0x0
+
+/*
+ * EMIF4 PHY Control 2 register configuration
+ */
+#define EMIF4_DDR2_TX_DATA_ALIGN 0x0
+#define EMIF4_DDR2_RX_DLL_BYPASS 0x0
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+#if 0
+extern dpll_param *get_iva_dpll_param(void);
+#endif
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+
+extern int mmc_init(int verbose);
+extern block_dev_desc_t *mmc_get_dev(int dev);
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+ return 0;
+}
+
+/* TODO: Move it to common place so that should be used
+ * for all OMAP series of devices
+ */
+u32 is_cpu_family(void)
+{
+ u32 cpuid = 0, cpu_family = 0;
+ u16 hawkeye;
+
+ cpuid = __raw_readl(OMAP34XX_CONTROL_ID);
+ hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
+
+ switch (hawkeye) {
+ case HAWKEYE_AM35XX:
+ default:
+ cpu_family = CPU_AM35XX;
+ break;
+ }
+ return cpu_family;
+}
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+ return(mode >>= 8);
+}
+
+/************************************************
+ * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ ************************************************/
+u32 get_sysboot_value(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
+ return mode;
+}
+/*************************************************************
+ * Routine: get_mem_type(void) - returns the kind of memory connected
+ * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+ u32 mem_type = get_sysboot_value();
+ switch (mem_type){
+
+ case 1:
+ case 12:
+ case 15:
+ case 21:
+ case 27: return GPMC_NAND;
+
+
+
+ case 13:
+ return MMC_NAND;
+
+ default: return GPMC_NAND;
+ }
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 cpuid=0;
+ /* On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate
+ * between ES2.0 and ES1.0.
+ */
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
+ if((cpuid & 0xf) == 0x0)
+ return CPU_3430_ES1;
+ else
+ return CPU_3430_ES2;
+
+}
+
+/*****************************************************************
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ *****************************************************************/
+void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = __raw_readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ __raw_writel(tmp, addr);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
+
+/*********************************************************************
+ * config_emif4_ddr() - Init/Configure DDR on AM3517 EVM board.
+ *********************************************************************/
+void config_emif4_ddr(void)
+{
+ unsigned int regval;
+
+ /* Set the DDR PHY parameters in PHY ctrl registers */
+ regval = (EMIF4_DDR1_RD_LAT | (EMIF4_DDR1_PWRDN_DIS << 6) |
+ (EMIF4_DDR1_STRBEN_EXT << 7) | (EMIF4_DDR1_DLL_MODE << 12) |
+ (EMIF4_DDR1_VTP_DYN << 15) | (EMIF4_DDR1_LB_CK_SEL << 23));
+ __raw_writel(regval, EMIF4_DDR_PHYCTL1);
+ __raw_writel(regval, EMIF4_DDR_PHYCTL1_SHDW);
+
+ regval = (EMIF4_DDR2_TX_DATA_ALIGN | (EMIF4_DDR2_RX_DLL_BYPASS << 1));
+ __raw_writel(regval, EMIF4_DDR_PHYCTL2);
+
+ /* Reset the DDR PHY and wait till completed */
+ sr32(EMIF4_IODFT_TLGC, 10, 1, 1);
+ /*Wait till that bit clears*/
+ while ((__raw_readl(EMIF4_IODFT_TLGC) & BIT10) == 0x1);
+ /*Re-verify the DDR PHY status*/
+ while ((__raw_readl(EMIF4_SDRAM_STS) & BIT2) == 0x0);
+
+ sr32(EMIF4_IODFT_TLGC, 0, 1, 1);
+ /* Set SDR timing registers */
+ regval = (EMIF4_TIM1_T_WTR | (EMIF4_TIM1_T_RRD << 3) |
+ (EMIF4_TIM1_T_RC << 6) | (EMIF4_TIM1_T_RAS << 12) |
+ (EMIF4_TIM1_T_WR << 17) | (EMIF4_TIM1_T_RCD << 21) |
+ (EMIF4_TIM1_T_RP << 25));
+ __raw_writel(regval, EMIF4_SDRAM_TIM1);
+ __raw_writel(regval, EMIF4_SDRAM_TIM1_SHDW);
+
+ regval = (EMIF4_TIM2_T_CKE | (EMIF4_TIM2_T_RTP << 3) |
+ (EMIF4_TIM2_T_XSRD << 6) | (EMIF4_TIM2_T_XSNR << 16) |
+ (EMIF4_TIM2_T_ODT << 25) | (EMIF4_TIM2_T_XP << 28));
+ __raw_writel(regval, EMIF4_SDRAM_TIM2);
+ __raw_writel(regval, EMIF4_SDRAM_TIM2_SHDW);
+
+ regval = (EMIF4_TIM3_T_RAS_MAX | (EMIF4_TIM3_T_RFC << 4) |
+ (EMIF4_TIM3_T_TDQSCKMAX << 13));
+ __raw_writel(regval, EMIF4_SDRAM_TIM3);
+ __raw_writel(regval, EMIF4_SDRAM_TIM3_SHDW);
+
+ /* Set the PWR control register */
+ regval = (EMIF4_PWR_PM_TIM | (EMIF4_PWR_PM_EN << 8) |
+ (EMIF4_PWR_DPD_EN << 10) | (EMIF4_PWR_IDLE << 30));
+ __raw_writel(regval, EMIF4_PWR_MGT_CTRL);
+ __raw_writel(regval, EMIF4_PWR_MGT_CTRL_SHDW);
+
+ /* Set the DDR refresh rate control register */
+ regval = (EMIF4_REFRESH_RATE | (EMIF4_PASR << 24) |
+ (EMIF4_INITREF_DIS << 31));
+ __raw_writel(regval, EMIF4_SDRAM_RFCR);
+ __raw_writel(regval, EMIF4_SDRAM_RFCR_SHDW);
+
+ /* set the SDRAM configuration register */
+ regval = (EMIF4_CFG_PGSIZE | (EMIF4_CFG_EBANK << 3) |
+ (EMIF4_CFG_IBANK << 4) | (EMIF4_CFG_ROWSIZE << 7) |
+ (EMIF4_CFG_CL << 10) | (EMIF4_CFG_NARROW_MD << 14) |
+ (EMIF4_CFG_CWL << 16) | (EMIF4_CFG_SDR_DRV << 18) |
+ (EMIF4_CFG_DDR_DIS_DLL << 20) | (EMIF4_CFG_DYN_ODT << 21) |
+ (EMIF4_CFG_DDR2_DDQS << 23) | (EMIF4_CFG_DDR_TERM << 24) |
+ (EMIF4_CFG_IBANK_POS << 27) | (EMIF4_CFG_SDRAM_TYP << 29));
+ __raw_writel(regval, EMIF4_SDRAM_CFG);
+}
+
+/*************************************************************
+ * get_sys_clk_speed - determine reference oscillator speed
+ * based on known 32kHz clock and gptimer.
+ *************************************************************/
+u32 get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, val;
+
+ val = __raw_readl(PRM_CLKSRC_CTRL);
+ /* If SYS_CLK is being divided by 2, remove for now */
+ val = (val & (~BIT7)) | BIT6;
+ __raw_writel(val, PRM_CLKSRC_CTRL);
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
+
+ /* Enable I and F Clocks for GPT1 */
+ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+ __raw_writel(val, CM_ICLKEN_WKUP);
+ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
+ __raw_writel(val, CM_FCLKEN_WKUP);
+
+ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
+ /* enable 32kHz source *//* enabled out of reset */
+ /* determine sys_clk via gauging */
+
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
+ while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
+ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
+ while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
+ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return (S38_4M);
+ else if (cdiff > 15200)
+ return (S26M);
+ else if (cdiff > 13000)
+ return (S24M);
+ else if (cdiff > 9000)
+ return (S19_2M);
+ else if (cdiff > 7600)
+ return (S13M);
+ else
+ return (S12M);
+}
+
+/******************************************************************************
+ * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
+ * -- input oscillator clock frequency.
+ *
+ *****************************************************************************/
+void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
+{
+ if(osc_clk == S38_4M)
+ *sys_clkin_sel= 4;
+ else if(osc_clk == S26M)
+ *sys_clkin_sel = 3;
+ else if(osc_clk == S19_2M)
+ *sys_clkin_sel = 2;
+ else if(osc_clk == S13M)
+ *sys_clkin_sel = 1;
+ else if(osc_clk == S12M)
+ *sys_clkin_sel = 0;
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * -- called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+ u32 osc_clk=0, sys_clkin_sel;
+ dpll_param *dpll_param_p;
+ u32 clk_index, sil_index;
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ osc_clk = get_osc_clk_speed();
+ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+ sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
+
+ /* If the input clock is greater than 19.2M always divide/2 */
+ if(sys_clkin_sel > 2) {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
+ clk_index = sys_clkin_sel/2;
+ } else {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
+ clk_index = sys_clkin_sel;
+ }
+
+ /* The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+ sil_index = get_cpu_rev() - 1;
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address of Core DPLL param table*/
+ dpll_param_p = (dpll_param *)get_core_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
+ /* CORE DPLL */
+ /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
+ sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+ sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to PER DPLL param table*/
+ dpll_param_p = (dpll_param *)get_per_dpll_param();
+ /* Moving it to the right sysclk base */
+ dpll_param_p = dpll_param_p + clk_index;
+ /* PER DPLL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
+ sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
+ sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
+ sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to MPU DPLL param table*/
+ dpll_param_p = (dpll_param *)get_mpu_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
+ /* MPU DPLL (unlocked already) */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+ sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+ delay(5000);
+}
+
+/*****************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ * (GP Device only)
+ *****************************************/
+void secure_unlock(void)
+{
+ /* Permission values for registers -Full fledged permissions to all */
+ #define UNLOCK_1 0xFFFFFFFF
+ #define UNLOCK_2 0x00000000
+ #define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT)*/
+ __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+ __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+ __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+ __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+void try_unlock_memory(void)
+{
+ int mode;
+
+ /* if GP device unlock device SRAM for general use */
+ /* secure code breaks for Secure/Emulation device - HS/E/T*/
+ mode = get_device_type();
+ if (mode == GP_DEVICE) {
+ secure_unlock();
+ }
+ return;
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+
+void s_init(void)
+{
+ watchdog_init();
+#ifdef CONFIG_3430_AS_3410
+ /* setup the scalability control register for
+ * 3430 to work in 3410 mode
+ */
+ __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
+#endif
+ try_unlock_memory();
+ set_muxconf_regs();
+ delay(100);
+ prcm_init();
+ per_clocks_enable();
+
+ /* enable the DDRPHY clk */
+ sr32((OMAP34XX_CTRL_BASE + 0x588), 15, 15, 0x1);
+ /* enable the EMIF4 clk */
+ sr32((OMAP34XX_CTRL_BASE + 0x588), 14, 14, 0x1);
+ /* Enable the peripheral clocks */
+ sr32((OMAP34XX_CTRL_BASE + 0x59C), 0, 4, 0xF);
+ sr32((OMAP34XX_CTRL_BASE + 0x59C), 8, 10, 0x7);
+
+ /* bring cpgmac out of reset */
+ sr32((OMAP34XX_CTRL_BASE + 0x598), 1, 1, 0x1);
+
+ /* Configure the EMIF4 for our DDR */
+ config_emif4_ddr();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r (void)
+{
+ return(0);
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+ sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+ sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+ wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init (void)
+{
+ return 0;
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void per_clocks_enable(void)
+{
+ /* Enable GP2 timer. */
+ sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CFG_NS16550
+ /* Enable UART1 clocks */
+ sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+
+ /* Enable UART2 clocks */
+ sr32(CM_FCLKEN1_CORE, 14, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 14, 1, 0x1);
+
+ /* Enable UART2 clocks */
+ sr32(CM_FCLKEN_PER, 11, 1, 0x1);
+ sr32(CM_ICLKEN_PER, 11, 1, 0x1);
+#endif
+ /* Enable MMC1 clocks */
+ sr32(CM_FCLKEN1_CORE, 24, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 24, 1, 0x1);
+
+ /* Enable MMC2 clocks */
+ sr32(CM_FCLKEN1_CORE, 25, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 25, 1, 0x1);
+
+ delay(1000);
+}
+
+/* Set MUX for UART, GPMC, SDRC, GPIO */
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ MUX_VAL(CP(sdrc_cke0), (M0)) /*SDRC_CKE0*/\
+ MUX_VAL(CP(sdrc_cke1), (M0)) /*SDRC_CKE1*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_NCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_NCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_NCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_NCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_NCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_NCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_NCS6*/\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_NCS7*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_NADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_NOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_NWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_NBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_NWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
+ MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
+ MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
+ MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
+ MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | DIS | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | DIS | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | DIS | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M0)) /*MMC1_DAT7*/\
+ MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
+ MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
+ MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
+ MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
+ MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
+ MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
+ MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need
+ * to be moved from protect to primary mode.
+ *********************************************************/
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
+
+/**********************************************************
+ * Routine: nand+_init
+ * Description: Set up nand for nand and jffs2 commands
+ *********************************************************/
+
+int nand_init(void)
+{
+ /* global settings */
+ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
+ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
+ __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
+
+ /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0
+ * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0.
+ * We configure only GPMC CS0 with required values. Configiring other devices
+ * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
+ */
+ __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
+ delay(1000);
+
+ if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){
+ __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+ /* Enable the GPMC Mapping */
+ __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+ ((NAND_BASE_ADR>>24) & 0x3F) |
+ (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+ delay(2000);
+
+ if (nand_chip()){
+#ifdef CFG_PRINTF
+ printf("Unsupported Chip!\n");
+#endif
+ return 1;
+ }
+
+ }
+
+ if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
+ __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+ /* Enable the GPMC Mapping */
+ __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+ ((ONENAND_BASE>>24) & 0x3F) |
+ (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+ delay(2000);
+
+ if (onenand_chip()){
+#ifdef CFG_PRINTF
+ printf("OneNAND Unsupported !\n");
+#endif
+ return 1;
+ }
+ }
+ return 0;
+}
+
+
+typedef int (mmc_boot_addr) (void);
+int mmc_boot(unsigned char *buf)
+{
+
+ long size = 0;
+#ifdef CFG_CMD_FAT
+ block_dev_desc_t *dev_desc = NULL;
+ unsigned char ret = 0;
+
+ printf("Starting X-loader on MMC \n");
+
+ ret = mmc_init(1);
+ if(ret == 0){
+ printf("\n MMC init failed \n");
+ return 0;
+ }
+
+ dev_desc = mmc_get_dev(0);
+ fat_register_device(dev_desc, 1);
+ size = file_fat_read("u-boot.bin", buf, 0);
+ if (size == -1) {
+ return 0;
+ }
+ printf("\n%ld Bytes Read from MMC \n", size);
+
+ printf("Starting OS Bootloader from MMC...\n");
+#endif
+ return size;
+}
+
+/* optionally do something like blinking LED */
+void board_hang (void)
+{ while (0) {};}
diff --git a/x-loader/board/am3517evm/config.mk b/x-loader/board/am3517evm/config.mk
new file mode 100644
index 0000000..0a212a4
--- /dev/null
+++ b/x-loader/board/am3517evm/config.mk
@@ -0,0 +1,19 @@
+# (C) Copyright 2009
+# Texas Instruments, <www.ti.com>
+#
+# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments#
+#
+# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+
+# For use if you want X-Loader to relocate from SRAM to DDR
+#TEXT_BASE = 0x80e80000
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+TEXT_BASE = 0x40200800
diff --git a/x-loader/board/am3517evm/platform.S b/x-loader/board/am3517evm/platform.S
new file mode 100644
index 0000000..c98f6e7
--- /dev/null
+++ b/x-loader/board/am3517evm/platform.S
@@ -0,0 +1,436 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2009
+ * Texas Instruments, <www.ti.com>
+ * Manikandan Pillai <mani.pillai@ti.com>
+ * This file is copied from board/omap3evm/platform.S
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * NOTE: 3430 X-loader currently does not use this code.
+* It could be removed its is kept for compatabily with u-boot.
+ *
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ * confused. A reset of the controller gets it back. Taking away its
+ * L3 when its not in self refresh seems bad for it. Normally, this code
+ * runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4-r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4-r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE
+.word 0x07
+.word 0x05
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x1F4
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179
+.word 0x12
+.word 0x04
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D
+.word 0x19
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA
+.word 0x32
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x2F
+.word 0x03
+.word 0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D
+.word 0x05
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x168
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082
+.word 0x09
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x0B
+.word 0x06
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D
+.word 0x0C
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F
+.word 0x30
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x17
+.word 0x06
+.word 0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x19F
+.word 0x0E
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x10
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x14C
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x21
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8
+.word 0x05
+.word 0x07
+.word 0x09
+
+/* 13MHz */
+.word 0x1B0
+.word 0x0C
+.word 0x03
+.word 0x09
+
+/* 19.2MHz */
+.word 0xE1
+.word 0x09
+.word 0x07
+.word 0x09
+
+/* 26MHz */
+.word 0xD8
+.word 0x0C
+.word 0x07
+.word 0x09
+
+/* 38.4MHz */
+.word 0xE1
+.word 0x13
+.word 0x07
+.word 0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
+
diff --git a/x-loader/board/am3517evm/x-load.lds b/x-loader/board/am3517evm/x-load.lds
new file mode 100644
index 0000000..d2e0ce5
--- /dev/null
+++ b/x-loader/board/am3517evm/x-load.lds
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2009
+ * Manikandan Pillai<mani.pillai@ti.com>
+ * This file is copied from board/omap3evm/x-load.lds
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/omap3/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/nest/diamond/Makefile b/x-loader/board/nest/diamond/Makefile
new file mode 100644
index 0000000..7eb6795
--- /dev/null
+++ b/x-loader/board/nest/diamond/Makefile
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2010-2011 Nest Labs, Inc.
+# All rights reserved.
+#
+# Description:
+# This file is the make file for portions of X-Loader specific
+# to the Nest Learning Thermostat board.
+#
+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := diamond.o mux.o prcm.o
+SOBJS := platform.o
+
+CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/nest/diamond/config.mk b/x-loader/board/nest/diamond/config.mk
new file mode 100644
index 0000000..881380c
--- /dev/null
+++ b/x-loader/board/nest/diamond/config.mk
@@ -0,0 +1,21 @@
+
+
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments#
+#
+# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+
+# For use if you want X-Loader to relocate from SRAM to DDR
+#TEXT_BASE = 0x80e80000
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+TEXT_BASE = 0x40200800
diff --git a/x-loader/board/nest/diamond/diamond.c b/x-loader/board/nest/diamond/diamond.c
new file mode 100644
index 0000000..1806f67
--- /dev/null
+++ b/x-loader/board/nest/diamond/diamond.c
@@ -0,0 +1,1075 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * (C) Copyright 2006
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703ACUS, focusing
+ * primarily on GPIO, RAM and flash initialization.
+ *
+ * This is inherited from the OMAP3 EVM equivalent file.
+ *
+ * Initialization function order is roughly:
+ *
+ * 1) s_init
+ * 2) board_init
+ * 3) misc_init_r
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+
+#include "platform.h"
+
+#define MAX_DIAMOND_BOOT_DEVICES (1)
+
+
+void
+udelay(unsigned long usecs) {
+ delay(usecs);
+}
+
+static inline u32
+get_cpu_id(void)
+{
+ u32 cpuid = 0;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
+
+ return (cpuid);
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32
+get_cpu_rev(void)
+{
+ const u32 cpuid = get_cpu_id();
+
+ /* On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate
+ * between ES2.0 and ES1.0.
+ */
+ if ((cpuid & 0xf) == 0x0) {
+ return (CPU_3430_ES1);
+
+ } else {
+ return (CPU_3430_ES2);
+
+ }
+
+}
+
+u32
+is_cpu_family(void)
+{
+ const u32 cpuid = get_cpu_id();
+ u32 cpu_family = 0, omap34xx_id = 0;
+ u16 hawkeye;
+
+ if ((cpuid & 0xf) == 0x0) {
+ cpu_family = CPU_OMAP34XX;
+
+ } else {
+ omap34xx_id = __raw_readl(OMAP34XX_CONTROL_ID);
+ hawkeye = (omap34xx_id >> HAWKEYE_SHIFT) & 0xffff;
+
+ switch (hawkeye) {
+
+ case HAWKEYE_AM35XX:
+ cpu_family = CPU_AM35XX;
+ break;
+
+ case HAWKEYE_OMAP36XX:
+ cpu_family = CPU_OMAP36XX;
+ break;
+
+ case HAWKEYE_OMAP34XX:
+ default:
+ cpu_family = CPU_OMAP34XX;
+ break;
+
+ }
+ }
+
+ return (cpu_family);
+}
+/******************************************
+ * cpu_is_3410(void) - returns true for 3410
+ ******************************************/
+u32
+cpu_is_3410(void)
+{
+ int status;
+ if(get_cpu_rev() < CPU_3430_ES2) {
+ return 0;
+ } else {
+ /* read scalability status and return 1 for 3410*/
+ status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
+ /* Check whether MPU frequency is set to 266 MHz which
+ * is nominal for 3410. If yes return true else false
+ */
+ if (((status >> 8) & 0x3) == 0x2)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/*
+ * void sr32()
+ *
+ * Description:
+ * This routine clears and sets a value in a bit extent for a
+ * 32-bit value at the specified address.
+ *
+ * Input(s):
+ * addr - The address at which to clear and set the specified
+ * specified 32-bit value.
+ * start_bit - The first bit of the 32-bit data to clear and set.
+ * num_bits - The range of bits of the 32-bit data to clear and set.
+ * value - The value to set.
+ *
+ * Output(s):
+ * addr - The address with the specified bit extent cleared and
+ * set to the specified value.
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+
+ msk = (1 << num_bits);
+ --msk;
+ tmp = __raw_readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ __raw_writel(tmp, addr);
+}
+
+/*
+ * u32 wait_on_value()
+ *
+ * Description:
+ * This routine reads the register at the specified address and
+ * busy waits until the specified match value is read or until the
+ * bounded number of loops have been reached.
+ *
+ * Input(s):
+ * read_bit_mask - The bit mask to apply after reading the register.
+ * match_value - The value to match on after reading and masking.
+ * read_addr - The register address to read.
+ * bound - The maximum number of times to read before giving
+ * up.
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * True (1) if the match_value was reached; otherwise, false (0).
+ *
+ */
+u32
+wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
+
+/*****************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ * (GP Device only)
+ *****************************************/
+static void
+secure_unlock(void)
+{
+ /* Permission values for registers -Full fledged permissions to all */
+ #define UNLOCK_1 0xFFFFFFFF
+ #define UNLOCK_2 0x00000000
+ #define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT)*/
+ __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+ __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+ __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+ /* IVA Changes */
+ __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+static void
+try_unlock_memory(void)
+{
+ const int type = get_device_type();
+
+ /*
+ * If the processor is a GP device, unlock the device SRAM for
+ * general use.
+ */
+
+ if (type == CONTROL_STATUS_DEVICETYPE_GP) {
+ secure_unlock();
+ }
+
+ return;
+}
+
+#if defined(CFG_SDRAM_DEBUG)
+static void
+omap3_sdrc_register_dump(void)
+{
+ printf("\n SDRC Register Dump:\n");
+
+ DUMP_REGL(SDRC_REVISION);
+ DUMP_REGL(SDRC_SYSCONFIG);
+ DUMP_REGL(SDRC_SYSSTATUS);
+ DUMP_REGL(SDRC_CS_CFG);
+ DUMP_REGL(SDRC_SHARING);
+ DUMP_REGL(SDRC_ERR_ADDR);
+ DUMP_REGL(SDRC_ERR_TYPE);
+ DUMP_REGL(SDRC_DLLA_CTRL);
+ DUMP_REGL(SDRC_DLLA_STATUS);
+ DUMP_REGL(SDRC_POWER_REG);
+ DUMP_REGL(SDRC_MCFG_0);
+ DUMP_REGL(SDRC_MR_0);
+ DUMP_REGL(SDRC_EMR2_0);
+ DUMP_REGL(SDRC_ACTIM_CTRLA_0);
+ DUMP_REGL(SDRC_ACTIM_CTRLB_0);
+ DUMP_REGL(SDRC_RFR_CTRL_0);
+ DUMP_REGL(SDRC_MANUAL_0);
+ DUMP_REGL(SDRC_MCFG_1);
+ DUMP_REGL(SDRC_MR_1);
+ DUMP_REGL(SDRC_EMR2_1);
+ DUMP_REGL(SDRC_ACTIM_CTRLA_1);
+ DUMP_REGL(SDRC_ACTIM_CTRLB_1);
+ DUMP_REGL(SDRC_RFR_CTRL_1);
+ DUMP_REGL(SDRC_MANUAL_1);
+}
+#else
+# define omap3_sdrc_register_dump() do { } while (0)
+#endif /* defined(CFG_SDRAM_DEBUG) */
+
+#if defined(CFG_GPMC_DEBUG)
+static void
+omap3_gpmc_register_dump(void)
+{
+ printf("\n GPMC Register Dump:\n");
+
+ DUMP_REGL(GPMC_REVISION);
+ DUMP_REGL(GPMC_SYSCONFIG);
+ DUMP_REGL(GPMC_SYSSTATUS);
+ DUMP_REGL(GPMC_IRQSTATUS);
+ DUMP_REGL(GPMC_IRQENABLE);
+ DUMP_REGL(GPMC_TIMEOUT_CONTROL);
+ DUMP_REGL(GPMC_ERR_ADDRESS);
+ DUMP_REGL(GPMC_ERR_TYPE );
+ DUMP_REGL(GPMC_CONFIG );
+ DUMP_REGL(GPMC_STATUS );
+
+ DUMP_REGL(GPMC_CONFIG1_0);
+ DUMP_REGL(GPMC_CONFIG2_0);
+ DUMP_REGL(GPMC_CONFIG3_0);
+ DUMP_REGL(GPMC_CONFIG4_0);
+ DUMP_REGL(GPMC_CONFIG5_0);
+ DUMP_REGL(GPMC_CONFIG6_0);
+ DUMP_REGL(GPMC_CONFIG7_0);
+
+ DUMP_REGL(GPMC_CONFIG1_1);
+ DUMP_REGL(GPMC_CONFIG2_1);
+ DUMP_REGL(GPMC_CONFIG3_1);
+ DUMP_REGL(GPMC_CONFIG4_1);
+ DUMP_REGL(GPMC_CONFIG5_1);
+ DUMP_REGL(GPMC_CONFIG6_1);
+ DUMP_REGL(GPMC_CONFIG7_1);
+
+ DUMP_REGL(GPMC_CONFIG1_2);
+ DUMP_REGL(GPMC_CONFIG2_2);
+ DUMP_REGL(GPMC_CONFIG3_2);
+ DUMP_REGL(GPMC_CONFIG5_2);
+ DUMP_REGL(GPMC_CONFIG4_2);
+ DUMP_REGL(GPMC_CONFIG6_2);
+ DUMP_REGL(GPMC_CONFIG7_2);
+
+ DUMP_REGL(GPMC_CONFIG1_3);
+ DUMP_REGL(GPMC_CONFIG2_3);
+ DUMP_REGL(GPMC_CONFIG3_3);
+ DUMP_REGL(GPMC_CONFIG4_3);
+ DUMP_REGL(GPMC_CONFIG5_3);
+ DUMP_REGL(GPMC_CONFIG6_3);
+ DUMP_REGL(GPMC_CONFIG7_3);
+
+ DUMP_REGL(GPMC_CONFIG1_4);
+ DUMP_REGL(GPMC_CONFIG2_4);
+ DUMP_REGL(GPMC_CONFIG3_4);
+ DUMP_REGL(GPMC_CONFIG4_4);
+ DUMP_REGL(GPMC_CONFIG5_4);
+ DUMP_REGL(GPMC_CONFIG6_4);
+ DUMP_REGL(GPMC_CONFIG7_4);
+
+ DUMP_REGL(GPMC_CONFIG1_5);
+ DUMP_REGL(GPMC_CONFIG2_5);
+ DUMP_REGL(GPMC_CONFIG3_5);
+ DUMP_REGL(GPMC_CONFIG4_5);
+ DUMP_REGL(GPMC_CONFIG5_5);
+ DUMP_REGL(GPMC_CONFIG6_5);
+ DUMP_REGL(GPMC_CONFIG7_5);
+
+ DUMP_REGL(GPMC_CONFIG1_6);
+ DUMP_REGL(GPMC_CONFIG2_6);
+ DUMP_REGL(GPMC_CONFIG3_6);
+ DUMP_REGL(GPMC_CONFIG4_6);
+ DUMP_REGL(GPMC_CONFIG5_6);
+ DUMP_REGL(GPMC_CONFIG6_6);
+ DUMP_REGL(GPMC_CONFIG7_6);
+
+ DUMP_REGL(GPMC_CONFIG1_7);
+ DUMP_REGL(GPMC_CONFIG2_7);
+ DUMP_REGL(GPMC_CONFIG3_7);
+ DUMP_REGL(GPMC_CONFIG4_7);
+ DUMP_REGL(GPMC_CONFIG5_7);
+ DUMP_REGL(GPMC_CONFIG6_7);
+ DUMP_REGL(GPMC_CONFIG7_7);
+
+#if 0
+ DUMP_REGL(GPMC_NAND_COMMAND_0);
+ DUMP_REGL(GPMC_NAND_COMMAND_1);
+ DUMP_REGL(GPMC_NAND_COMMAND_2);
+ DUMP_REGL(GPMC_NAND_COMMAND_3);
+ DUMP_REGL(GPMC_NAND_COMMAND_4);
+ DUMP_REGL(GPMC_NAND_COMMAND_5);
+ DUMP_REGL(GPMC_NAND_COMMAND_6);
+ DUMP_REGL(GPMC_NAND_COMMAND_7);
+
+ DUMP_REGL(GPMC_NAND_ADDRESS_0);
+ DUMP_REGL(GPMC_NAND_ADDRESS_1);
+ DUMP_REGL(GPMC_NAND_ADDRESS_2);
+ DUMP_REGL(GPMC_NAND_ADDRESS_3);
+ DUMP_REGL(GPMC_NAND_ADDRESS_4);
+ DUMP_REGL(GPMC_NAND_ADDRESS_5);
+ DUMP_REGL(GPMC_NAND_ADDRESS_6);
+ DUMP_REGL(GPMC_NAND_ADDRESS_7);
+
+ DUMP_REGL(GPMC_NAND_DATA_0);
+ DUMP_REGL(GPMC_NAND_DATA_1);
+ DUMP_REGL(GPMC_NAND_DATA_2);
+ DUMP_REGL(GPMC_NAND_DATA_3);
+ DUMP_REGL(GPMC_NAND_DATA_4);
+ DUMP_REGL(GPMC_NAND_DATA_5);
+ DUMP_REGL(GPMC_NAND_DATA_6);
+ DUMP_REGL(GPMC_NAND_DATA_7);
+
+ DUMP_REGL(GPMC_PREFETCH_CONFIG1);
+ DUMP_REGL(GPMC_PREFETCH_CONFIG2);
+ DUMP_REGL(GPMC_PREFETCH_CONTROL);
+ DUMP_REGL(GPMC_PREFETCH_STATUS);
+
+ DUMP_REGL(GPMC_ECC_CONFIG);
+ DUMP_REGL(GPMC_ECC_CONTROL);
+ DUMP_REGL(GPMC_ECC_SIZE_CONFIG);
+
+ DUMP_REGL(GPMC_ECC1_RESULT);
+ DUMP_REGL(GPMC_ECC2_RESULT);
+ DUMP_REGL(GPMC_ECC3_RESULT);
+ DUMP_REGL(GPMC_ECC4_RESULT);
+ DUMP_REGL(GPMC_ECC5_RESULT);
+ DUMP_REGL(GPMC_ECC6_RESULT);
+ DUMP_REGL(GPMC_ECC7_RESULT);
+ DUMP_REGL(GPMC_ECC8_RESULT);
+ DUMP_REGL(GPMC_ECC9_RESULT);
+
+ DUMP_REGL(GPMC_BCH_RESULT0_0);
+ DUMP_REGL(GPMC_BCH_RESULT0_1);
+ DUMP_REGL(GPMC_BCH_RESULT0_2);
+ DUMP_REGL(GPMC_BCH_RESULT0_3);
+ DUMP_REGL(GPMC_BCH_RESULT0_4);
+ DUMP_REGL(GPMC_BCH_RESULT0_5);
+ DUMP_REGL(GPMC_BCH_RESULT0_6);
+ DUMP_REGL(GPMC_BCH_RESULT0_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT1_0);
+ DUMP_REGL(GPMC_BCH_RESULT1_1);
+ DUMP_REGL(GPMC_BCH_RESULT1_2);
+ DUMP_REGL(GPMC_BCH_RESULT1_3);
+ DUMP_REGL(GPMC_BCH_RESULT1_4);
+ DUMP_REGL(GPMC_BCH_RESULT1_5);
+ DUMP_REGL(GPMC_BCH_RESULT1_6);
+ DUMP_REGL(GPMC_BCH_RESULT1_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT2_0);
+ DUMP_REGL(GPMC_BCH_RESULT2_1);
+ DUMP_REGL(GPMC_BCH_RESULT2_2);
+ DUMP_REGL(GPMC_BCH_RESULT2_3);
+ DUMP_REGL(GPMC_BCH_RESULT2_4);
+ DUMP_REGL(GPMC_BCH_RESULT2_5);
+ DUMP_REGL(GPMC_BCH_RESULT2_6);
+ DUMP_REGL(GPMC_BCH_RESULT2_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT3_0);
+ DUMP_REGL(GPMC_BCH_RESULT3_1);
+ DUMP_REGL(GPMC_BCH_RESULT3_2);
+ DUMP_REGL(GPMC_BCH_RESULT3_3);
+ DUMP_REGL(GPMC_BCH_RESULT3_4);
+ DUMP_REGL(GPMC_BCH_RESULT3_5);
+ DUMP_REGL(GPMC_BCH_RESULT3_6);
+ DUMP_REGL(GPMC_BCH_RESULT3_7);
+
+ DUMP_REGL(GPMC_BCH_SWDATA);
+#endif
+}
+#else
+# define omap3_gpmc_register_dump() do { } while (0)
+#endif /* defined(CFG_NAND_DEBUG) */
+
+#if defined(CFG_PRCM_DEBUG)
+static void
+omap3_prcm_register_dump(void)
+{
+ printf("\n PRCM Register Dump:\n");
+
+ DUMP_REGL(PRCM_PRM_CCR_CLKSEL);
+ DUMP_REGL(PRCM_PRM_GR_CLKSRC_CTRL);
+ DUMP_REGL(CM_CLKSEL1_PLL);
+ DUMP_REGL(CM_CLKSEL2_PLL);
+ DUMP_REGL(CM_CLKSEL3_PLL);
+ DUMP_REGL(CM_CLKEN_PLL);
+ DUMP_REGL(CM_CLKSEL1_PLL_MPU);
+ DUMP_REGL(CM_CLKSEL2_PLL_MPU);
+ DUMP_REGL(CM_CLKEN_PLL_MPU);
+ DUMP_REGL(CM_CLKSEL1_PLL_IVA2);
+ DUMP_REGL(CM_CLKSEL2_PLL_IVA2);
+ DUMP_REGL(CM_CLKEN_PLL_IVA2);
+ DUMP_REGL(CM_CLKSEL_CAM);
+ DUMP_REGL(CM_CLKSEL_CORE);
+ DUMP_REGL(CM_CLKSEL_DSS);
+ DUMP_REGL(CM_CLKSEL1_EMU);
+}
+#else
+#define omap3_prcm_register_dump() do { } while (0)
+#endif /* CFG_PRCM_DEBUG */
+
+/*
+ * void config_diamond_sdram()
+ *
+ * Description:
+ * This routine initializes the processor's SDRAM Controller (SDRC)
+ * as appropriate for the Samsung K4X51163PI-FCG6 32 Mb x 16 b (64
+ * MiB) DDR SDRAM on the Nest Learning Thermostat board.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+config_diamond_sdram(void)
+{
+ u32 value, actim_ctrla, actim_ctrlb;
+
+ /*
+ * Step 1: Reset the SDRC controller and then wait for the reset
+ * event to clear.
+ */
+
+ __raw_writel(SDRC_SYSCONFIG_SOFTRESET_SET, SDRC_SYSCONFIG);
+ wait_on_value(SDRC_SYSSTATUS_RESETDONE,
+ SDRC_SYSSTATUS_RESETDONE,
+ SDRC_STATUS,
+ 12000000);
+ __raw_writel(SDRC_SYSCONFIG_SOFTRESET_CLEAR, SDRC_SYSCONFIG);
+
+ /*
+ * Step 2: Setup the position and geometry of the SDRAM device on
+ * the controller's bus.
+ */
+
+ value =
+ (SDRC_SHARING_LOCK_OFF |
+ SDRC_SHARING_CS1MUXCFG_ENCODE(SDRC_SHARING_CS1MUXCFG_16_BIT_16_0) |
+ SDRC_SHARING_CS0MUXCFG_ENCODE(SDRC_SHARING_CS0MUXCFG_16_BIT_16_0) |
+ SDRC_SHARING_SDRCTRISTATE_OFF);
+ __raw_writel(value, SDRC_SHARING);
+
+ /*
+ * Step 3: Setup the memory configuration, including RAS width,
+ * CAS width, address multiplexing, size, bank mapping, bus width,
+ * power mode, DDR type and memory type.
+ */
+
+ value =
+ (SDRC_MCFG_LOCKSTATUS_RW |
+ SDRC_MCFG_RASWIDTH_ENCODE(SDRC_MCFG_RASWIDTH_14_BITS) |
+ SDRC_MCFG_CASWIDTH_ENCODE(SDRC_MCFG_CASWIDTH_10_BITS) |
+ SDRC_MCFG_ADDRMUXLEGACY_FLEXIBLE |
+ SDRC_MCFG_RAMSIZE_ENCODE(CFG_SDRAM_SIZE_MB) |
+ SDRC_MCFG_BANKALLOCATION_ENCODE(SDRC_MCFG_BANKALLOCATION_R_B_C)|
+ SDRC_MCFG_B32NOT16_OFF |
+ SDRC_MCFG_DEEPPD_SUPPORTED |
+ SDRC_MCFG_DDRTYPE_ENCODE(SDRC_MCFG_DDRTYPE_MOBILE_DDR) |
+ SDRC_MCFG_RAMTYPE_ENCODE(SDRC_MCFG_RAMTYPE_DDR));
+ __raw_writel(value, SDRC_MCFG_0);
+
+ /*
+ * Step 4: Establish the AC fine tuning timing characteristics.
+ */
+
+ actim_ctrla
+ = (SDRC_ACTIM_CTRLA_TRFC_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRFC) |
+ SDRC_ACTIM_CTRLA_TRC_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRC) |
+ SDRC_ACTIM_CTRLA_TRAS_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRAS) |
+ SDRC_ACTIM_CTRLA_TRP_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRP) |
+ SDRC_ACTIM_CTRLA_TRCD_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRCD) |
+ SDRC_ACTIM_CTRLA_TRRD_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRRD) |
+ SDRC_ACTIM_CTRLA_TDPL_ENCODE(CFG_SDRC_ACTIM_CTRLA_TDPL) |
+ SDRC_ACTIM_CTRLA_TDAL_ENCODE(CFG_SDRC_ACTIM_CTRLA_TDAL));
+
+ actim_ctrlb
+ = (SDRC_ACTIM_CTRLB_TWTR_ENCODE(CFG_SDRC_ACTIM_CTRLB_TWTR) |
+ SDRC_ACTIM_CTRLB_TCKE_ENCODE(CFG_SDRC_ACTIM_CTRLB_TCKE) |
+ SDRC_ACTIM_CTRLB_TXP_ENCODE(CFG_SDRC_ACTIM_CTRLB_TXP) |
+ SDRC_ACTIM_CTRLB_TXSR_ENCODE(CFG_SDRC_ACTIM_CTRLB_TXSR));
+
+ __raw_writel(actim_ctrla, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(actim_ctrlb, SDRC_ACTIM_CTRLB_0);
+
+ /*
+ * Step 5: Establish the memory autorefresh control
+ */
+
+ value =
+ (SDRC_RFR_CTRL_ARCV_ENCODE(1244) |
+ SDRC_RFR_CTRL_ARE_ENCODE(SDRC_RFR_CTRL_ARE_1_ARCV));
+ __raw_writel(value, SDRC_RFR_CTRL_0);
+
+ value =
+ (SDRC_POWER_REG_WAKEUP_DELAYED |
+ SDRC_POWER_REG_AUTOCOUNT_ENCODE(0) |
+ SDRC_POWER_REG_SRFR_ON_RST_ENABLE |
+ SDRC_POWER_REG_SRFR_ON_IDLE_DISABLE |
+ SDRC_POWER_REG_CLKCTRL_ENCODE(SDRC_POWER_REG_CLKCTRL_NONE) |
+ SDRC_POWER_REG_PAGEPOLICY_HPHB);
+ __raw_writel(value, SDRC_POWER_REG);
+
+ /*
+ * Step 6: Establish the JEDEC-defined mode and DLL parameters.
+ */
+
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+
+ delay(5000);
+
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_PRECHARGE_ALL),
+ SDRC_MANUAL_0);
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+
+ value =
+ (SDRC_MR_ZERO_1 |
+ SDRC_MR_WBST_ENABLE |
+ SDRC_MR_ZERO_0 |
+ SDRC_MR_CASL_ENCODE(SDRC_MR_CASL_3) |
+ SDRC_MR_SIL_SERIAL |
+ SDRC_MR_BL_ENCODE(SDRC_MR_BL_4));
+ __raw_writel(value, SDRC_MR_0);
+
+ value =
+ (SDRC_DLLA_CTRL_FIXED_DELAY_ENCODE(0) |
+ SDRC_DLLA_CTRL_INIT_LAT_ENCODE(0) |
+ SDRC_DLLA_CTRL_MODE_ON_IDLE_ENCODE(SDRC_DLLA_CTRL_MODE_ON_IDLE_PWD) |
+ SDRC_DLLA_CTRL_DLL_ENABLE |
+ SDRC_DLLA_CTRL_LOCK_TRACKINGDELAY);
+ __raw_writel(value, SDRC_DLLA_CTRL);
+
+ /*
+ * Delay for a "reasonably long" period of time to allow the
+ * requested changes to take effect.
+ */
+
+ delay(0x20000);
+}
+
+/*
+ * void s_init()
+ *
+ * Description:
+ * This routine performs very early system initialization of chip
+ * pin multiplexing and clocks and is called when ONLY an
+ * SRAM-based stack is available (i.e. no SDRAM).
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+s_init(void)
+{
+ watchdog_init();
+ try_unlock_memory();
+ set_muxconf_regs();
+
+ delay(100);
+
+ prcm_init();
+ per_clocks_enable();
+ config_diamond_sdram();
+}
+
+/*
+ * int board_init()
+ *
+ * Description:
+ * This routine performs any early, board-specific initialization
+ * following core CPU initialization but prior to serial and NAND
+ * initialization.
+ *
+ * At present, there is nothing board-specific to do.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if OK; otherwise, non-zero on error.
+ *
+ */
+int
+board_init(void)
+{
+ return (0);
+}
+
+/*
+ * u32 get_device_type()
+ *
+ * Description:
+ * This routine returns the decoded value from the CPU's
+ * CONTROL_STATUS register DEVICETYPE field, indicating whether the
+ * device is of TST, EMU, HS or GP type.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The decoded CONTROL_STATUS register DEVICETYPE field.
+ *
+ */
+u32
+get_device_type(void)
+{
+ const int value = __raw_readl(CONTROL_STATUS);
+
+ return (CONTROL_STATUS_DEVICETYPE_DECODE(value));
+}
+
+/*
+ * u32 get_sysboot_value()
+ *
+ * Description:
+ * This routine returns the decoded value from the CPU's
+ * CONTROL_STATUS register SYSBOOT order subfield, indicating the
+ * order of memory interfaces from which the processor will attempt
+ * to boot itself.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The decoded CONTROL_STATUS register SYSBOOT order subfield.
+ *
+ */
+u32
+get_sysboot_value(void)
+{
+ const u32 value = __raw_readl(CONTROL_STATUS);
+ const u32 peripheral_type = CONTROL_STATUS_SYSBOOT_TYPE_PERIPHERAL;
+
+ /*
+ * This routine and callers of it are implicitly expecting the
+ * MEMORY interface (SYSBOOT[5] == 0) not the PERHIPHERAL
+ * interface (SYSBOOT[5] == 1) boot order, so check that is
+ * actually the case.
+ */
+
+ if (CONTROL_STATUS_SYSBOOT_TYPE_DECODE(value) == peripheral_type) {
+ hang();
+ }
+
+ return (CONTROL_STATUS_SYSBOOT_ORDER_DECODE(value));
+}
+
+/*
+ * int get_boot_device_list(const u32** device_list)
+ *
+ * Description:
+ * This routine returns a constant list indicating the preferred
+ * device boot list.
+ * It gets called from start_armboot in board.c
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The preferred first processor memory boot interface.
+ *
+ */
+
+int
+get_boot_devices_list(const u32** devices_list)
+{
+ static u32 list[MAX_DIAMOND_BOOT_DEVICES];
+ const u32 mem_order = get_sysboot_value();
+
+ // set defaults
+ int number_of_devices = 0;
+ *devices_list = &list[0];
+
+ switch (mem_order) {
+
+ case 0:
+ case 2:
+ case 4:
+ case 16:
+ case 22:
+ list[0] = GPMC_ONENAND;
+ number_of_devices = MAX_DIAMOND_BOOT_DEVICES;
+ break;
+ case 1:
+ case 12:
+ case 15:
+ case 21:
+ case 27:
+ list[0] = GPMC_NAND;
+ number_of_devices = MAX_DIAMOND_BOOT_DEVICES;
+ break;
+ case 3:
+ case 6:
+ list[0] = MMC_ONENAND;
+ number_of_devices = MAX_DIAMOND_BOOT_DEVICES;
+ break;
+ case 8:
+ case 11:
+ case 14:
+ case 20:
+ case 26:
+ list[0] = GPMC_MDOC;
+ number_of_devices = MAX_DIAMOND_BOOT_DEVICES;
+ break;
+ case 17:
+ case 18:
+ case 24:
+ list[0] = MMC_NAND;
+ number_of_devices = MAX_DIAMOND_BOOT_DEVICES;
+ break;
+ case 7:
+ case 10:
+ case 13:
+ case 19:
+ case 25:
+
+ default:
+ list[0] = GPMC_NOR;
+ number_of_devices = MAX_DIAMOND_BOOT_DEVICES;
+ break;
+ }
+ return number_of_devices;
+}
+
+/*
+ * int misc_init_r()
+ *
+ * Description:
+ * This routine performs any miscellaneous, board-specific
+ * initialization following CPU, early board, serial and NAND
+ * initialization but prior to loading the secondary program loader
+ * to RAM.
+ *
+ * At present, there is nothing board-specific to do.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if OK; otherwise, non-zero on error.
+ *
+ */
+int
+misc_init_r(void)
+{
+ return (0);
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+static void
+wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void
+watchdog_init(void)
+{
+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+ sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+ sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+ wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+/*
+ * void foobar()
+ *
+ * Description:
+ * This routine...
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+per_clocks_enable(void)
+{
+ /* Enable GP2 timer. */
+ sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CFG_NS16550
+ /* Enable UART1 clocks */
+ sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+#endif
+
+#ifdef CONFIG_MMC
+ /* Enable MMC1 clocks */
+ sr32(CM_FCLKEN1_CORE, 24, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 24, 1, 0x1);
+#endif
+ delay(1000);
+}
+
+static int
+gpmc_config_0(void)
+{
+#if defined(CFG_GPMC_CONFIG1_0)
+ /*
+ * First, disable the interface and wait.
+ */
+ __raw_writel(GPMC_CONFIG7_CSVALID_DISABLED, GPMC_CONFIG7_0);
+
+ delay(1000);
+
+ /*
+ * Next, program the configuration parameters.
+ */
+ __raw_writel(CFG_GPMC_CONFIG1_0, GPMC_CONFIG1_0);
+ __raw_writel(CFG_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+ __raw_writel(CFG_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+ __raw_writel(CFG_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+ __raw_writel(CFG_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+ __raw_writel(CFG_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+
+ /*
+ * Finally, enable the GPMC mapping and spin for the parameters to
+ * become active.
+ */
+ __raw_writel((CFG_GPMC_CONFIG7_0 | GPMC_CONFIG7_CSVALID_ENABLED),
+ GPMC_CONFIG7_0);
+
+ delay(2000);
+
+ if (nand_chip()){
+ return (1);
+ }
+#endif /* defined(CFG_GPMC_CONFIG1_0) */
+
+ return (0);
+}
+
+/*
+ * int nand_init()
+ *
+ * Description:
+ * This routine initializes the General Purpose Memory Controller
+ * (GPMC) such that on-board NAND devices may be accessed for
+ * second-stage boot.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if NAND was successfully initialized; otherwise, 1.
+ *
+ */
+int
+nand_init(void)
+{
+ int status = 1;
+
+ /*
+ * Establish GPMC global settings.
+ */
+
+ __raw_writel(GPMC_SYSCONFIG_IDLEMODE_SMART, GPMC_SYSCONFIG);
+
+ __raw_writel(GPMC_IRQENABLE_ALL_DISABLE, GPMC_IRQENABLE);
+
+ __raw_writel(GPMC_TIMEOUTENABLE_OFF, GPMC_TIMEOUT_CONTROL);
+
+ if (gpmc_config_0()) {
+ puts("Unsupported NAND device @ GPMC0!\n");
+ goto done;
+ }
+
+ status = 0;
+
+ done:
+ /* Dump GPMC and SDRC registers if so configured. */
+
+ omap3_sdrc_register_dump();
+ omap3_gpmc_register_dump();
+ omap3_prcm_register_dump();
+
+ return (status);
+}
+
+/*
+ * void board_hang()
+ *
+ * Description:
+ * This routine performs any board-specific actions when the system
+ * hangs by executing hang(). At present, there is nothing to do;
+ * however, we might later drive the piezo or a LED.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+board_hang (void)
+{
+ return;
+}
diff --git a/x-loader/board/nest/diamond/mux.c b/x-loader/board/nest/diamond/mux.c
new file mode 100644
index 0000000..42f92f9
--- /dev/null
+++ b/x-loader/board/nest/diamond/mux.c
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703CUS, focusing
+ * primarily I/O pad multiplexer configuration.
+ *
+ * This is originally inherited and split from the OMAP3 EVM
+ * board file.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+
+#include "platform.h"
+
+/*
+ * void set_muxconf_regs()
+ *
+ * Description:
+ * This routines sets the I/O pad multiplexers for UART, GPMC, SDRC,
+ * GPIO.
+ *
+ * The commented string gives the final mux configuration for that pin
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ */
+void
+set_muxconf_regs(void)
+{
+ /*
+ * The bit fields for these settings are as follows:
+ *
+ * I{EN,DIS} - Input Enable/Disable
+ * PT[DU] - Pull-down, -up
+ * DIS,EN - Pull-down, -up disabled/enabled
+ * M[01234567] - Configuration mode 0-7
+ */
+
+ /*
+ * SDRAM Controller (SDRC)
+ *
+ * Most of the SDRC signals are used to drive the Samsung
+ * K4X51163PI-FCG6 512 Mb x 16-bit (64 MiB) DDR SDRAM. Because we
+ * interface in 16-bit rather than 32-bit mode, we place the
+ * unused pins in safe mode (Mode 7).
+ */
+
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); // SDRC_D0
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); // SDRC_D1
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); // SDRC_D2
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); // SDRC_D3
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); // SDRC_D4
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); // SDRC_D5
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); // SDRC_D6
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); // SDRC_D7
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); // SDRC_D8
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); // SDRC_D9
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); // SDRC_D10
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); // SDRC_D11
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); // SDRC_D12
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); // SDRC_D13
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); // SDRC_D14
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); // SDRC_D15
+
+ // Because we interface SDRAM in 16-bit mode, place
+ // SDRC_DATA[31:16] in safe mode (Mode 7).
+
+ MUX_VAL(CP(SDRC_D16), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D17), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D18), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D19), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D20), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D21), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D22), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D23), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D24), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D25), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D26), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D27), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D28), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D29), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D30), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D31), (IDIS | PTD | DIS | M7)); // Unused
+
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); // SDRC_CLK
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); // SDRC_DQS0
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); // SDRC_DQS1
+
+ // Place unused DQ pins in safe mode (Mode 7).
+
+ MUX_VAL(CP(SDRC_DQS2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_DQS3), (IDIS | PTD | DIS | M7)); // Unused
+
+ /*
+ * General Purpose Memory Controller (GPMC)
+ *
+ */
+
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); // GPMC_A1
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); // GPMC_A2
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); // GPMC_A3
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); // GPMC_A4
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); // GPMC_A5
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); // GPMC_A6
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); // GPMC_A7
+
+ // Place the unused GPMC_A8 pin in safe mode (Mode 7).
+
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M7)); // Unused
+
+ // Assign GPMC_A9 to GPIO_42 used as a push-pull, active low input
+ // from the USB PHY for USB suspend notification.
+
+ MUX_VAL(CP(GPMC_A9), (IEN | PTU | DIS | M4)); // GPIO_42
+
+#if defined(CONFIG_DIAMOND_BOARD_DEVELOPMENT)
+ // Assign GPMC_A10 to GPIO_43 used as push-pull, active low output
+ // LCD_nENBUFFER for the 1.8V to 3.3V LCD buffer enable.
+
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M4)); // GPIO_43
+#else
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M7)); // Unused
+#endif /* defined(CONFIG_DIAMOND_BOARD_DEVELOPMENT) */
+
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); // GPMC_D0
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); // GPMC_D1
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); // GPMC_D2
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); // GPMC_D3
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); // GPMC_D4
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); // GPMC_D5
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); // GPMC_D6
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); // GPMC_D7
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); // GPMC_D8
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); // GPMC_D9
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); // GPMC_D10
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); // GPMC_D11
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); // GPMC_D12
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); // GPMC_D13
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); // GPMC_D14
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); // GPMC_D15
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); // GPMC_nCS0
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); // GPMC_nCS1
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); // GPMC_nCS2
+#if defined(CONFIG_DIAMOND_BOARD_DEVELOPMENT)
+ // Assign to GPMC_NCS3 for Samsung K9F4G08U0C 512 MiB SLC NAND
+ // Flash
+
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); // GPMC_nCS3
+#else
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M7)); // Unused
+#endif /* defined(CONFIG_DIAMOND_BOARD_DEVELOPMENT) */
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M7)); // Unused
+#if defined(CONFIG_DIAMOND_BOARD_DEVELOPMENT)
+ // Assign to GPMC_NCS5 for SMSC LAN9220 10/100 Mbit Ethernet MAC
+ // and PHY
+
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); // GPMC_nCS5
+#else
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)); // Unused
+#endif /* defined(CONFIG_DIAMOND_BOARD_DEVELOPMENT) */
+
+ // Assign GPMC_NCS6 to GPT11_PWM_EVT used as a push-pull pulse width
+ // modulated (PWM) signal for the piezo.
+
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M3)); // GPT11_PWM_EVT
+
+ // Assign GPMC_NCS7 to GPIO_58 used as a push-pull output
+ // PIEZO_NENABLE to the TI SN74LVC2G240 Dual Buffer/Driver With
+ // 3-State Outputs inputs.
+
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M4)); // GPIO_58
+
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); // GPMC_CLK
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); // GPMC_nADV_ALE
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); // GPMC_nOE
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); // GPMC_nWE
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); // GPMC_nBE0_CLE
+
+ // Assign GPMC_NBE1 to GPIO_61 used as a push-pull output to the
+ // ZigBee active-low reset.
+
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); // GPIO_61
+
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); // GPMC_nWP
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); // GPMC_WAIT0
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); // GPMC_WAIT1
+ MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M7)); // Unavailable
+
+ // Assign GPMC_WAIT3 to GPIO_65 used as an active-high, push-pull
+ // backplate detect input.
+
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M4)); // GPIO_65
+
+ /*
+ * Display Subsystem (DSS)
+ *
+ * All DSS signals are used in their normal, default mode (Mode 0)
+ * to drive the Samsung LMS350DF0[13] LCD display panel.
+ */
+
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); // DSS_PCLK
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); // DSS_HSYNC
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); // DSS_VSYNC
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); // DSS_ACBIAS
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); // DSS_DATA0
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); // DSS_DATA1
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); // DSS_DATA2
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); // DSS_DATA3
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); // DSS_DATA4
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); // DSS_DATA5
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); // DSS_DATA6
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); // DSS_DATA7
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); // DSS_DATA8
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); // DSS_DATA9
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); // DSS_DATA10
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); // DSS_DATA11
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); // DSS_DATA12
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); // DSS_DATA13
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); // DSS_DATA14
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); // DSS_DATA15
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); // DSS_DATA16
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); // DSS_DATA17
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); // DSS_DATA18
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); // DSS_DATA19
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); // DSS_DATA20
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); // DSS_DATA21
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); // DSS_DATA22
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); // DSS_DATA23
+
+ MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M7)); // Unused
+
+ /*
+ * Universal Asynchronous Receiver / Transmitter (UART)
+ *
+ */
+
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); // UART1_TX
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); // UART1_RTS
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); // UART1_CTS
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); // UART1_RX
+ /*
+ * Control and Debug
+ *
+ */
+
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); // SYS_32K
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M0)); // SYS_BOOT0
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0)); // SYS_BOOT1
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)); // SYS_BOOT2
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0)); // SYS_BOOT3
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0)); // SYS_BOOT4
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0)); // SYS_BOOT5
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M0)); // SYS_BOOT6
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTU | EN | M0)); // SYS_CLKOUT1
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); // JTAG_nTRST
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); // JTAG_TCK
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); // JTAG_TMS
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); // JTAG_TDI
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); // JTAG_EMU0
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); // JTAG_EMU1
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M7)); // Unused
+
+ // Assign ETK_D1[45] as MM2_RXRCV and MM2_TXSE0 USB FS/LS Host
+ // (Mode 5)
+
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M5)); // MM2_RXRCV
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M5)); // MM2_TXSE0
+}
diff --git a/x-loader/board/nest/diamond/platform.S b/x-loader/board/nest/diamond/platform.S
new file mode 100644
index 0000000..0549d27
--- /dev/null
+++ b/x-loader/board/nest/diamond/platform.S
@@ -0,0 +1,557 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific setup for the Nest Learning
+ * Thermostat board.
+ *
+ * It inherits entirely from the equivalent TI OMAP3 EVM
+ * file.
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * NOTE: 3430 X-loader currently does not use this code.
+* It could be removed its is kept for compatabily with u-boot.
+ *
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ * confused. A reset of the controller gets it back. Taking away its
+ * L3 when its not in self refresh seems bad for it. Normally, this code
+ * runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4-r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4-r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG1_0)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG3_0)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG4_0)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG5_0)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+#endif /* !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) */
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE
+.word 0x07
+.word 0x05
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x1F4
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179
+.word 0x12
+.word 0x04
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D
+.word 0x19
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA
+.word 0x32
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x2F
+.word 0x03
+.word 0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D
+.word 0x05
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x168
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082
+.word 0x09
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x0B
+.word 0x06
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D
+.word 0x0C
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F
+.word 0x30
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x17
+.word 0x06
+.word 0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x19F
+.word 0x0E
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x10
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x14C
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x21
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8
+.word 0x05
+.word 0x07
+.word 0x09
+
+/* 13MHz */
+.word 0x1B0
+.word 0x0C
+.word 0x03
+.word 0x09
+
+/* 19.2MHz */
+.word 0xE1
+.word 0x09
+.word 0x07
+.word 0x09
+
+/* 26MHz */
+.word 0xD8
+.word 0x0C
+.word 0x07
+.word 0x09
+
+/* 38.4MHz */
+.word 0xE1
+.word 0x13
+.word 0x07
+.word 0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
+
+/*
+ * Tables for 36x/37x devices
+ *
+ * (Populated for 13MHz only)
+ */
+mpu_36x_dpll_param:
+// M N FS M2
+#if defined(CONFIG_SYS_MPU_DPLL_300MHZ)
+.word 150, 5, 0, 1 // 12 MHz
+.word 300, 12, 0, 1 // 13 MHz
+.word 125, 7, 0, 1 // 19.2 MHz
+.word 150, 12, 0, 1 // 26 MHz
+.word 125, 15, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_MPU_DPLL_600MHZ)
+.word 300, 5, 0, 1 // 12 MHz
+.word 600, 12, 0, 1 // 13 MHz
+.word 125, 3, 0, 1 // 19.2 MHz
+.word 300, 12, 0, 1 // 26 MHz
+.word 125, 7, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#else
+# error "MPU DPLL settings are not defined!"
+#endif /* defined(CONFIG_SYS_MPU_DPLL_600MHZ) */
+
+iva_36x_dpll_param:
+// M N FS M2
+.word 10, 0, 0, 1 // 12 MHz
+.word 10, 0, 0, 1 // 13 MHz
+.word 10, 0, 0, 1 // 19.2 MHz
+.word 10, 0, 0, 1 // 26 MHz
+.word 10, 0, 0, 1 // 38.4 MHz
+.word 10, 0, 0, 1 // 16.8 MHz
+
+core_36x_dpll_param:
+// M N FS M2
+#if defined(CONFIG_SYS_CORE_DPLL_200MHZ)
+.word 100, 5, 0, 1 // 12 MHz
+.word 200, 12, 0, 1 // 13 MHz
+.word 375, 35, 0, 1 // 19.2 MHz
+.word 100, 12, 0, 1 // 26 MHz
+.word 375, 71, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_CORE_DPLL_332MHZ)
+.word 166, 5, 0, 1 // 12 MHz
+.word 332, 12, 0, 1 // 13 MHz
+.word 415, 23, 0, 1 // 19.2 MHz
+.word 166, 12, 0, 1 // 26 MHz
+.word 415, 47, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_CORE_DPLL_400MHZ)
+.word 200, 5, 0, 1 // 12 MHz
+.word 400, 12, 0, 1 // 13 MHz
+.word 375, 17, 0, 1 // 19.2 MHz
+.word 200, 12, 0, 1 // 26 MHz
+.word 375, 35, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#else
+# error "Core DPLL settings are not defined!"
+#endif /* defined(CONFIG_SYS_CORE_DPLL_400MHZ) */
+
+/*
+ * For the peripheral (PER) (aka DPLL4) clock settings, there are only
+ * effectively two clock choices, 96 MHz or 192 MHz. However, the only
+ * time 192 MHz is apt to be used in an application is if both SGX and
+ * TV output are used.
+ *
+ * For any given system clock, the dividers are configured thus (per
+ * Section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" of the OMAP3 TRM):
+ *
+ * PER[clkout] = (SYS[clkout] * M) / (N + 1)
+ *
+ * M2[clkout]: PER[clkout] / M2 used by UART, MMC, I2C, etc.
+ * M3[clkout]: PER[clkout] / M3 used by TV out.
+ * M4[clkout]: PER[clkout] / M4 used by DSS.
+ * M5[clkout]: PER[clkout] / M5 used by camera.
+ * M6[clkout]: PER[clkout] / M6 used by emulation.
+ *
+ * So, for a 19.2 MHz system clock and the scalar entries below:
+ *
+ * PER[clkout] = (19.2 * 540) / (11 + 1) = 864
+ *
+ * M2[clkout]: 864 / 9 = 96 MHz
+ * M3[clkout]: 864 / 16 = 54 MHz
+ * M4[clkout]: 864 / 5 = 172.8 MHz
+ * M5[clkout]: 864 / 4 = 216 MHz
+ * M6[clkout]: 864 / 3 = 288 MHz
+ */
+per_36x_dpll_param:
+// SYS_CLK M N M2 M3 M4 M5 M6 m2DIV
+.word 12000, 432, 5, 9, 16, 9, 4, 3, 1 // 12 MHz
+.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 // 13 MHz
+.word 19200, 540, 11, 9, 16, 9, 4, 3, 1 // 19.2 MHz
+.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 // 26 MHz
+.word 38400, 270, 11, 9, 16, 9, 4, 3, 1 // 38.4 MHz
+.word 16800, 360, 6, 9, 16, 9, 4, 3, 1 // 16.8 MHz
+
+.globl get_36x_mpu_dpll_param
+get_36x_mpu_dpll_param:
+ adr r0, mpu_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_iva_dpll_param
+get_36x_iva_dpll_param:
+ adr r0, iva_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_core_dpll_param
+get_36x_core_dpll_param:
+ adr r0, core_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_per_dpll_param
+get_36x_per_dpll_param:
+ adr r0, per_36x_dpll_param
+ mov pc, lr
diff --git a/x-loader/board/nest/diamond/platform.h b/x-loader/board/nest/diamond/platform.h
new file mode 100644
index 0000000..c836e5a
--- /dev/null
+++ b/x-loader/board/nest/diamond/platform.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file defines data structures and function prototypes for
+ * accessing Digital Phased Lock Loop (DPLL) parameters and
+ * settings.
+ *
+ */
+
+#ifndef _NEST_DIAMOND_PLATFORM_H_
+#define _NEST_DIAMOND_PLATFORM_H_
+
+#include <asm/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Type Definitions
+ */
+
+/* Used to index into DPLL parameter tables */
+
+struct dpll_param {
+ u32 m;
+ u32 n;
+ u32 fsel;
+ u32 m2;
+};
+
+struct dpll_per_36x_param {
+ u32 sys_clk;
+ u32 m;
+ u32 n;
+ u32 m2;
+ u32 m3;
+ u32 m4;
+ u32 m5;
+ u32 m6;
+ u32 m2div;
+};
+
+typedef struct dpll_param dpll_param;
+
+/*
+ * Inline Functions
+ */
+static inline void
+delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+
+/*
+ * Function Prototypes
+ *
+ * The following functions are exported from platform.S.
+ */
+
+extern dpll_param * get_mpu_dpll_param(void);
+extern dpll_param * get_iva_dpll_param(void);
+extern dpll_param * get_core_dpll_param(void);
+extern dpll_param * get_per_dpll_param(void);
+
+extern dpll_param * get_36x_mpu_dpll_param(void);
+extern dpll_param * get_36x_iva_dpll_param(void);
+extern dpll_param * get_36x_core_dpll_param(void);
+extern dpll_param * get_36x_per_dpll_param(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _NEST_DIAMOND_PLATFORM_H_ */
diff --git a/x-loader/board/nest/diamond/prcm.c b/x-loader/board/nest/diamond/prcm.c
new file mode 100644
index 0000000..5625ad7
--- /dev/null
+++ b/x-loader/board/nest/diamond/prcm.c
@@ -0,0 +1,565 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703CUS, focusing
+ * primarily clock set-up for the processor's Power, Reset and
+ * Clock Manager (PRCM)
+ *
+ * This is originally inherited and split from the OMAP3 EVM
+ * board file.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+
+#include "platform.h"
+
+/*
+ * u32 get_osc_clk_speed()
+ *
+ * Description:
+ * This routine determines the reference oscillator speed based on
+ * a known 32 kHz clock and general purpose timer.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The reference oscillator clock speed.
+ *
+ */
+static u32
+get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, cdiv, val;
+
+ val = __raw_readl(PRM_CLKSRC_CTRL);
+
+ if (val & BIT7)
+ cdiv = 2;
+ else if (val & BIT6)
+ cdiv = 1;
+ else
+ /*
+ * Should never reach here!
+ * TBD: Add a WARN()/BUG()
+ * For now, assume divider as 1.
+ */
+ cdiv = 1;
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
+
+ /* Enable I and F Clocks for GPT1 */
+ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+ __raw_writel(val, CM_ICLKEN_WKUP);
+ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
+ __raw_writel(val, CM_FCLKEN_WKUP);
+
+ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
+ /* enable 32kHz source *//* enabled out of reset */
+ /* determine sys_clk via gauging */
+
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
+ while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
+ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
+ while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
+ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+
+ if (cdiv == 2)
+ {
+ cdiff *= 2;
+ }
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return (S38_4M);
+ else if (cdiff > 15200)
+ return (S26M);
+ else if (cdiff > 13000)
+ return (S24M);
+ else if (cdiff > 9000)
+ return (S19_2M);
+ else if (cdiff > 7600)
+ return (S13M);
+ else
+ return (S12M);
+}
+
+/*
+ * void get_sys_clkin_sel()
+ *
+ * Description:
+ * This routine sets the value for the PRCM PRM system clock
+ * frequency selector, which should be written to PRM_CLKSEL.
+ *
+ * Input(s):
+ * hertz - The speed, in MHz, that the system clock is believed
+ * to be running at.
+ * sys_clkin_sel - A pointer to storage for the index used to access the
+ * digital PLL settings.
+ *
+ * Output(s):
+ * sys_clkin_sel - A pointer to the index for the digital PLL settings
+ * appropriate for the specified system clock rate.
+ *
+ * Returns:
+ * N/A
+ *
+ */
+static void
+get_sys_clkin_sel(u32 hertz, u32 *sys_clkin_sel)
+{
+ switch (hertz) {
+
+ case S38_4M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_38_4_MHZ;
+ break;
+
+ case S26M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_26_0_MHZ;
+ break;
+
+ case S19_2M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_19_2_MHZ;
+ break;
+
+ case S16_8M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_16_8_MHZ;
+ break;
+
+ case S13M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_13_0_MHZ;
+ break;
+
+ case S12M:
+ default:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_12_0_MHZ;
+ break;
+
+ }
+}
+
+/*
+ * OMAP34x/35x specific functions
+ */
+static void
+dpll3_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address of Core DPLL param table*/
+ ptr = (dpll_param *)get_core_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* CORE DPLL */
+ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(CM_CLKSEL1_PLL, 27, 5, ptr->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(CM_CLKSEL1_PLL, 16, 11, ptr->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(CM_CLKSEL1_PLL, 8, 7, ptr->n);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0);
+
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV_34X); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(CM_CLKEN_PLL, 4, 4, ptr->fsel);
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+dpll4_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ ptr = (dpll_param *)get_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr = ptr + clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ sr32(CM_CLKSEL3_PLL, 0, 5, ptr->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
+ sr32(CM_CLKSEL2_PLL, 8, 11, ptr->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(CM_CLKSEL2_PLL, 0, 7, ptr->n);
+
+ /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
+ sr32(CM_CLKEN_PLL, 20, 4, ptr->fsel);
+
+ /* LOCK MODE (EN_PERIPH_DPLL) : CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+mpu_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to MPU DPLL param table*/
+ ptr = (dpll_param *)get_mpu_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, ptr->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, ptr->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, ptr->n);
+
+ /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
+ sr32(CM_CLKEN_PLL_MPU, 4, 4, ptr->fsel);
+}
+
+static void
+iva_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to IVA DPLL param table*/
+ ptr = (dpll_param *)get_iva_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* IVA DPLL */
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, ptr->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, ptr->n);
+
+ /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
+ sr32(CM_CLKEN_PLL_IVA2, 4, 4, ptr->fsel);
+
+ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);
+
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+}
+
+/*
+ * OMAP3630 specific functions
+ */
+static void
+dpll3_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address of Core DPLL param table*/
+ ptr = (dpll_param *)get_36x_core_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr += clk_index;
+
+ /* CORE DPLL */
+ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(CM_CLKSEL1_PLL, 27, 5, ptr->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(CM_CLKSEL1_PLL, 16, 11, ptr->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(CM_CLKSEL1_PLL, 8, 7, ptr->n);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0);
+
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV_36X); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(CM_CLKEN_PLL, 4, 4, ptr->fsel);
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+dpll4_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct dpll_per_36x_param *ptr;
+
+ ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr += clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
+ sr32(CM_CLKSEL1_EMU, 24, 6, ptr->m6);
+
+ /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
+ sr32(CM_CLKSEL_CAM, 0, 6, ptr->m5);
+
+ /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
+ sr32(CM_CLKSEL_DSS, 0, 6, ptr->m4);
+
+ /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
+ sr32(CM_CLKSEL_DSS, 8, 6, ptr->m3);
+
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ sr32(CM_CLKSEL3_PLL, 0, 5, ptr->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
+ sr32(CM_CLKSEL2_PLL, 8, 12, ptr->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(CM_CLKSEL2_PLL, 0, 7, ptr->n);
+
+ /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
+ sr32(CM_CLKSEL_CORE, 12, 2, ptr->m2div);
+
+ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+mpu_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to MPU DPLL param table*/
+ ptr = (dpll_param *)get_36x_mpu_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + (2*clk_index) + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, ptr->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, ptr->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, ptr->n);
+
+ /* LOCK MODE (EN_MPU_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+}
+
+static void
+iva_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to IVA DPLL param table*/
+ ptr = (dpll_param *)get_36x_iva_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + (2*clk_index) + sil_index;
+
+ /* IVA DPLL */
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, ptr->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, ptr->n);
+
+ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);
+
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+}
+
+/*
+ * void prcm_init()
+ *
+ * Description:
+ * This routine initializes clocks in a board-specific manner for
+ * the processor's Power, Reset and Clock Manager (PRCM) and is
+ * called only when an SRAM-based stack is available (i.e. no
+ * SDRAM).
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+prcm_init(void)
+{
+ u32 sys_clk_rate = 0, sys_clkin_sel, sys_clk_div;
+ u32 clk_index, sil_index;
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ sys_clk_rate = get_osc_clk_speed();
+ get_sys_clkin_sel(sys_clk_rate, &sys_clkin_sel);
+
+ /* Set the PRM_CLKSEL_SYS_CLKIN_SEL value in the processor. */
+
+ sr32(PRCM_PRM_CCR_CLKSEL,
+ PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_START,
+ PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_BITS,
+ sys_clkin_sel);
+
+ /* If the input clock is greater than 19.2M always divide by two.
+ *
+ * On OMAP3630, DDR data corruption has been observed on OFF mode
+ * exit if the sys clock was lower than 26M. As a work around,
+ * OMAP3630 is operated at 26M sys clock and this internal division
+ * is not performed.
+ */
+
+ if((is_cpu_family() != CPU_OMAP36XX) &&
+ (sys_clkin_sel > PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_19_2_MHZ)) {
+ sys_clk_div = PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BY_2;
+ clk_index = sys_clkin_sel / 2;
+
+ } else {
+ sys_clk_div = PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BY_1;
+ clk_index = sys_clkin_sel / 1;
+
+ }
+
+ sr32(PRCM_PRM_GR_CLKSRC_CTRL,
+ PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_START,
+ PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BITS,
+ sys_clk_div);
+
+ if (is_cpu_family() == CPU_OMAP36XX) {
+ dpll3_init_36xx(0, clk_index);
+ dpll4_init_36xx(0, clk_index);
+ mpu_init_36xx(0, clk_index);
+ iva_init_36xx(0, clk_index);
+
+ } else {
+ sil_index = get_cpu_rev() - 1;
+
+ /* The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+ dpll3_init_34xx(sil_index, clk_index);
+ dpll4_init_34xx(sil_index, clk_index);
+ iva_init_34xx(sil_index, clk_index);
+ mpu_init_34xx(sil_index, clk_index);
+
+ /* Lock MPU DPLL to set frequency */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+ }
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+ sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+ delay(5000);
+}
diff --git a/x-loader/board/nest/diamond/x-load.lds b/x-loader/board/nest/diamond/x-load.lds
new file mode 100644
index 0000000..e0603a2
--- /dev/null
+++ b/x-loader/board/nest/diamond/x-load.lds
@@ -0,0 +1,65 @@
+/*
+ *
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ * All rights reserved.
+ *
+ * Description:
+ * This file is the X-Loader linker scatter file for the Nest
+ * Learning Thermostat board.
+ *
+ */
+
+/*
+ * November 2006 - Changed to support 3430sdp device
+ * Copyright (c) 2004-2006 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/omap3/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/nest/j49-usb-loader/Makefile b/x-loader/board/nest/j49-usb-loader/Makefile
new file mode 100644
index 0000000..ece4a90
--- /dev/null
+++ b/x-loader/board/nest/j49-usb-loader/Makefile
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2010-2011 Nest Labs, Inc.
+# All rights reserved.
+#
+# Description:
+# This file is the make file for portions of X-Loader specific
+# to the Nest Learning Thermostat board.
+#
+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := j49.o mux.o prcm.o
+SOBJS := platform.o
+
+CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/nest/j49-usb-loader/config.mk b/x-loader/board/nest/j49-usb-loader/config.mk
new file mode 100644
index 0000000..f5d960c
--- /dev/null
+++ b/x-loader/board/nest/j49-usb-loader/config.mk
@@ -0,0 +1,21 @@
+
+
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments#
+#
+# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+
+TEXT_BASE = 0x40200000
+STACK_BASE = 0x4020FCB0
diff --git a/x-loader/board/nest/j49-usb-loader/j49.c b/x-loader/board/nest/j49-usb-loader/j49.c
new file mode 100644
index 0000000..9609bbc
--- /dev/null
+++ b/x-loader/board/nest/j49-usb-loader/j49.c
@@ -0,0 +1,1046 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * (C) Copyright 2006
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703ACUS, focusing
+ * primarily on GPIO, RAM and flash initialization.
+ *
+ * This is inherited from the OMAP3 EVM equivalent file.
+ *
+ * Initialization function order is roughly:
+ *
+ * 1) s_init
+ * 2) board_init
+ * 3) misc_init_r
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+
+#include "platform.h"
+
+#define MAX_J49_BOOT_DEVICES (3)
+
+void
+udelay(unsigned long usecs) {
+ delay(usecs);
+}
+
+static inline u32
+get_cpu_id(void)
+{
+ u32 cpuid = 0;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
+
+ return (cpuid);
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32
+get_cpu_rev(void)
+{
+ const u32 cpuid = get_cpu_id();
+
+ /* On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate
+ * between ES2.0 and ES1.0.
+ */
+ if ((cpuid & 0xf) == 0x0) {
+ return (CPU_3430_ES1);
+
+ } else {
+ return (CPU_3430_ES2);
+
+ }
+
+}
+
+u32
+is_cpu_family(void)
+{
+ const u32 cpuid = get_cpu_id();
+ u32 cpu_family = 0, omap34xx_id = 0;
+ u16 hawkeye;
+
+ if ((cpuid & 0xf) == 0x0) {
+ cpu_family = CPU_OMAP34XX;
+
+ } else {
+ omap34xx_id = __raw_readl(OMAP34XX_CONTROL_ID);
+ hawkeye = (omap34xx_id >> HAWKEYE_SHIFT) & 0xffff;
+
+ switch (hawkeye) {
+
+ case HAWKEYE_AM35XX:
+ cpu_family = CPU_AM35XX;
+ break;
+
+ case HAWKEYE_OMAP36XX:
+ cpu_family = CPU_OMAP36XX;
+ break;
+
+ case HAWKEYE_OMAP34XX:
+ default:
+ cpu_family = CPU_OMAP34XX;
+ break;
+
+ }
+ }
+
+ return (cpu_family);
+}
+/******************************************
+ * cpu_is_3410(void) - returns true for 3410
+ ******************************************/
+u32
+cpu_is_3410(void)
+{
+ int status;
+ if(get_cpu_rev() < CPU_3430_ES2) {
+ return 0;
+ } else {
+ /* read scalability status and return 1 for 3410*/
+ status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
+ /* Check whether MPU frequency is set to 266 MHz which
+ * is nominal for 3410. If yes return true else false
+ */
+ if (((status >> 8) & 0x3) == 0x2)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/*
+ * void sr32()
+ *
+ * Description:
+ * This routine clears and sets a value in a bit extent for a
+ * 32-bit value at the specified address.
+ *
+ * Input(s):
+ * addr - The address at which to clear and set the specified
+ * specified 32-bit value.
+ * start_bit - The first bit of the 32-bit data to clear and set.
+ * num_bits - The range of bits of the 32-bit data to clear and set.
+ * value - The value to set.
+ *
+ * Output(s):
+ * addr - The address with the specified bit extent cleared and
+ * set to the specified value.
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+
+ msk = (1 << num_bits);
+ --msk;
+ tmp = __raw_readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ __raw_writel(tmp, addr);
+}
+
+/*
+ * u32 wait_on_value()
+ *
+ * Description:
+ * This routine reads the register at the specified address and
+ * busy waits until the specified match value is read or until the
+ * bounded number of loops have been reached.
+ *
+ * Input(s):
+ * read_bit_mask - The bit mask to apply after reading the register.
+ * match_value - The value to match on after reading and masking.
+ * read_addr - The register address to read.
+ * bound - The maximum number of times to read before giving
+ * up.
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * True (1) if the match_value was reached; otherwise, false (0).
+ *
+ */
+u32
+wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
+
+/*****************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ * (GP Device only)
+ *****************************************/
+static void
+secure_unlock(void)
+{
+ /* Permission values for registers -Full fledged permissions to all */
+ #define UNLOCK_1 0xFFFFFFFF
+ #define UNLOCK_2 0x00000000
+ #define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT)*/
+ __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+ __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+ __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+ /* IVA Changes */
+ __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+static void
+try_unlock_memory(void)
+{
+ const int type = get_device_type();
+
+ /*
+ * If the processor is a GP device, unlock the device SRAM for
+ * general use.
+ */
+
+ if (type == CONTROL_STATUS_DEVICETYPE_GP) {
+ secure_unlock();
+ }
+
+ return;
+}
+
+#if defined(CFG_SDRAM_DEBUG)
+static void
+omap3_sdrc_register_dump(void)
+{
+ printf("\n SDRC Register Dump:\n");
+
+ DUMP_REGL(SDRC_REVISION);
+ DUMP_REGL(SDRC_SYSCONFIG);
+ DUMP_REGL(SDRC_SYSSTATUS);
+ DUMP_REGL(SDRC_CS_CFG);
+ DUMP_REGL(SDRC_SHARING);
+ DUMP_REGL(SDRC_ERR_ADDR);
+ DUMP_REGL(SDRC_ERR_TYPE);
+ DUMP_REGL(SDRC_DLLA_CTRL);
+ DUMP_REGL(SDRC_DLLA_STATUS);
+ DUMP_REGL(SDRC_POWER_REG);
+ DUMP_REGL(SDRC_MCFG_0);
+ DUMP_REGL(SDRC_MR_0);
+ DUMP_REGL(SDRC_EMR2_0);
+ DUMP_REGL(SDRC_ACTIM_CTRLA_0);
+ DUMP_REGL(SDRC_ACTIM_CTRLB_0);
+ DUMP_REGL(SDRC_RFR_CTRL_0);
+ DUMP_REGL(SDRC_MANUAL_0);
+ DUMP_REGL(SDRC_MCFG_1);
+ DUMP_REGL(SDRC_MR_1);
+ DUMP_REGL(SDRC_EMR2_1);
+ DUMP_REGL(SDRC_ACTIM_CTRLA_1);
+ DUMP_REGL(SDRC_ACTIM_CTRLB_1);
+ DUMP_REGL(SDRC_RFR_CTRL_1);
+ DUMP_REGL(SDRC_MANUAL_1);
+}
+#else
+# define omap3_sdrc_register_dump() do { } while (0)
+#endif /* defined(CFG_SDRAM_DEBUG) */
+
+#if defined(CFG_GPMC_DEBUG)
+static void
+omap3_gpmc_register_dump(void)
+{
+ printf("\n GPMC Register Dump:\n");
+
+ DUMP_REGL(GPMC_REVISION);
+ DUMP_REGL(GPMC_SYSCONFIG);
+ DUMP_REGL(GPMC_SYSSTATUS);
+ DUMP_REGL(GPMC_IRQSTATUS);
+ DUMP_REGL(GPMC_IRQENABLE);
+ DUMP_REGL(GPMC_TIMEOUT_CONTROL);
+ DUMP_REGL(GPMC_ERR_ADDRESS);
+ DUMP_REGL(GPMC_ERR_TYPE );
+ DUMP_REGL(GPMC_CONFIG );
+ DUMP_REGL(GPMC_STATUS );
+
+ DUMP_REGL(GPMC_CONFIG1_0);
+ DUMP_REGL(GPMC_CONFIG2_0);
+ DUMP_REGL(GPMC_CONFIG3_0);
+ DUMP_REGL(GPMC_CONFIG4_0);
+ DUMP_REGL(GPMC_CONFIG5_0);
+ DUMP_REGL(GPMC_CONFIG6_0);
+ DUMP_REGL(GPMC_CONFIG7_0);
+
+ DUMP_REGL(GPMC_CONFIG1_1);
+ DUMP_REGL(GPMC_CONFIG2_1);
+ DUMP_REGL(GPMC_CONFIG3_1);
+ DUMP_REGL(GPMC_CONFIG4_1);
+ DUMP_REGL(GPMC_CONFIG5_1);
+ DUMP_REGL(GPMC_CONFIG6_1);
+ DUMP_REGL(GPMC_CONFIG7_1);
+
+ DUMP_REGL(GPMC_CONFIG1_2);
+ DUMP_REGL(GPMC_CONFIG2_2);
+ DUMP_REGL(GPMC_CONFIG3_2);
+ DUMP_REGL(GPMC_CONFIG5_2);
+ DUMP_REGL(GPMC_CONFIG4_2);
+ DUMP_REGL(GPMC_CONFIG6_2);
+ DUMP_REGL(GPMC_CONFIG7_2);
+
+ DUMP_REGL(GPMC_CONFIG1_3);
+ DUMP_REGL(GPMC_CONFIG2_3);
+ DUMP_REGL(GPMC_CONFIG3_3);
+ DUMP_REGL(GPMC_CONFIG4_3);
+ DUMP_REGL(GPMC_CONFIG5_3);
+ DUMP_REGL(GPMC_CONFIG6_3);
+ DUMP_REGL(GPMC_CONFIG7_3);
+
+ DUMP_REGL(GPMC_CONFIG1_4);
+ DUMP_REGL(GPMC_CONFIG2_4);
+ DUMP_REGL(GPMC_CONFIG3_4);
+ DUMP_REGL(GPMC_CONFIG4_4);
+ DUMP_REGL(GPMC_CONFIG5_4);
+ DUMP_REGL(GPMC_CONFIG6_4);
+ DUMP_REGL(GPMC_CONFIG7_4);
+
+ DUMP_REGL(GPMC_CONFIG1_5);
+ DUMP_REGL(GPMC_CONFIG2_5);
+ DUMP_REGL(GPMC_CONFIG3_5);
+ DUMP_REGL(GPMC_CONFIG4_5);
+ DUMP_REGL(GPMC_CONFIG5_5);
+ DUMP_REGL(GPMC_CONFIG6_5);
+ DUMP_REGL(GPMC_CONFIG7_5);
+
+ DUMP_REGL(GPMC_CONFIG1_6);
+ DUMP_REGL(GPMC_CONFIG2_6);
+ DUMP_REGL(GPMC_CONFIG3_6);
+ DUMP_REGL(GPMC_CONFIG4_6);
+ DUMP_REGL(GPMC_CONFIG5_6);
+ DUMP_REGL(GPMC_CONFIG6_6);
+ DUMP_REGL(GPMC_CONFIG7_6);
+
+ DUMP_REGL(GPMC_CONFIG1_7);
+ DUMP_REGL(GPMC_CONFIG2_7);
+ DUMP_REGL(GPMC_CONFIG3_7);
+ DUMP_REGL(GPMC_CONFIG4_7);
+ DUMP_REGL(GPMC_CONFIG5_7);
+ DUMP_REGL(GPMC_CONFIG6_7);
+ DUMP_REGL(GPMC_CONFIG7_7);
+
+#if 0
+ DUMP_REGL(GPMC_NAND_COMMAND_0);
+ DUMP_REGL(GPMC_NAND_COMMAND_1);
+ DUMP_REGL(GPMC_NAND_COMMAND_2);
+ DUMP_REGL(GPMC_NAND_COMMAND_3);
+ DUMP_REGL(GPMC_NAND_COMMAND_4);
+ DUMP_REGL(GPMC_NAND_COMMAND_5);
+ DUMP_REGL(GPMC_NAND_COMMAND_6);
+ DUMP_REGL(GPMC_NAND_COMMAND_7);
+
+ DUMP_REGL(GPMC_NAND_ADDRESS_0);
+ DUMP_REGL(GPMC_NAND_ADDRESS_1);
+ DUMP_REGL(GPMC_NAND_ADDRESS_2);
+ DUMP_REGL(GPMC_NAND_ADDRESS_3);
+ DUMP_REGL(GPMC_NAND_ADDRESS_4);
+ DUMP_REGL(GPMC_NAND_ADDRESS_5);
+ DUMP_REGL(GPMC_NAND_ADDRESS_6);
+ DUMP_REGL(GPMC_NAND_ADDRESS_7);
+
+ DUMP_REGL(GPMC_NAND_DATA_0);
+ DUMP_REGL(GPMC_NAND_DATA_1);
+ DUMP_REGL(GPMC_NAND_DATA_2);
+ DUMP_REGL(GPMC_NAND_DATA_3);
+ DUMP_REGL(GPMC_NAND_DATA_4);
+ DUMP_REGL(GPMC_NAND_DATA_5);
+ DUMP_REGL(GPMC_NAND_DATA_6);
+ DUMP_REGL(GPMC_NAND_DATA_7);
+
+ DUMP_REGL(GPMC_PREFETCH_CONFIG1);
+ DUMP_REGL(GPMC_PREFETCH_CONFIG2);
+ DUMP_REGL(GPMC_PREFETCH_CONTROL);
+ DUMP_REGL(GPMC_PREFETCH_STATUS);
+
+ DUMP_REGL(GPMC_ECC_CONFIG);
+ DUMP_REGL(GPMC_ECC_CONTROL);
+ DUMP_REGL(GPMC_ECC_SIZE_CONFIG);
+
+ DUMP_REGL(GPMC_ECC1_RESULT);
+ DUMP_REGL(GPMC_ECC2_RESULT);
+ DUMP_REGL(GPMC_ECC3_RESULT);
+ DUMP_REGL(GPMC_ECC4_RESULT);
+ DUMP_REGL(GPMC_ECC5_RESULT);
+ DUMP_REGL(GPMC_ECC6_RESULT);
+ DUMP_REGL(GPMC_ECC7_RESULT);
+ DUMP_REGL(GPMC_ECC8_RESULT);
+ DUMP_REGL(GPMC_ECC9_RESULT);
+
+ DUMP_REGL(GPMC_BCH_RESULT0_0);
+ DUMP_REGL(GPMC_BCH_RESULT0_1);
+ DUMP_REGL(GPMC_BCH_RESULT0_2);
+ DUMP_REGL(GPMC_BCH_RESULT0_3);
+ DUMP_REGL(GPMC_BCH_RESULT0_4);
+ DUMP_REGL(GPMC_BCH_RESULT0_5);
+ DUMP_REGL(GPMC_BCH_RESULT0_6);
+ DUMP_REGL(GPMC_BCH_RESULT0_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT1_0);
+ DUMP_REGL(GPMC_BCH_RESULT1_1);
+ DUMP_REGL(GPMC_BCH_RESULT1_2);
+ DUMP_REGL(GPMC_BCH_RESULT1_3);
+ DUMP_REGL(GPMC_BCH_RESULT1_4);
+ DUMP_REGL(GPMC_BCH_RESULT1_5);
+ DUMP_REGL(GPMC_BCH_RESULT1_6);
+ DUMP_REGL(GPMC_BCH_RESULT1_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT2_0);
+ DUMP_REGL(GPMC_BCH_RESULT2_1);
+ DUMP_REGL(GPMC_BCH_RESULT2_2);
+ DUMP_REGL(GPMC_BCH_RESULT2_3);
+ DUMP_REGL(GPMC_BCH_RESULT2_4);
+ DUMP_REGL(GPMC_BCH_RESULT2_5);
+ DUMP_REGL(GPMC_BCH_RESULT2_6);
+ DUMP_REGL(GPMC_BCH_RESULT2_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT3_0);
+ DUMP_REGL(GPMC_BCH_RESULT3_1);
+ DUMP_REGL(GPMC_BCH_RESULT3_2);
+ DUMP_REGL(GPMC_BCH_RESULT3_3);
+ DUMP_REGL(GPMC_BCH_RESULT3_4);
+ DUMP_REGL(GPMC_BCH_RESULT3_5);
+ DUMP_REGL(GPMC_BCH_RESULT3_6);
+ DUMP_REGL(GPMC_BCH_RESULT3_7);
+
+ DUMP_REGL(GPMC_BCH_SWDATA);
+#endif
+}
+#else
+# define omap3_gpmc_register_dump() do { } while (0)
+#endif /* defined(CFG_NAND_DEBUG) */
+
+#if defined(CFG_PRCM_DEBUG)
+static void
+omap3_prcm_register_dump(void)
+{
+ printf("\n PRCM Register Dump:\n");
+
+ DUMP_REGL(PRCM_PRM_CCR_CLKSEL);
+ DUMP_REGL(PRCM_PRM_GR_CLKSRC_CTRL);
+ DUMP_REGL(CM_CLKSEL1_PLL);
+ DUMP_REGL(CM_CLKSEL2_PLL);
+ DUMP_REGL(CM_CLKSEL3_PLL);
+ DUMP_REGL(CM_CLKEN_PLL);
+ DUMP_REGL(CM_CLKSEL1_PLL_MPU);
+ DUMP_REGL(CM_CLKSEL2_PLL_MPU);
+ DUMP_REGL(CM_CLKEN_PLL_MPU);
+ DUMP_REGL(CM_CLKSEL1_PLL_IVA2);
+ DUMP_REGL(CM_CLKSEL2_PLL_IVA2);
+ DUMP_REGL(CM_CLKEN_PLL_IVA2);
+ DUMP_REGL(CM_CLKSEL_CAM);
+ DUMP_REGL(CM_CLKSEL_CORE);
+ DUMP_REGL(CM_CLKSEL_DSS);
+ DUMP_REGL(CM_CLKSEL1_EMU);
+}
+#else
+#define omap3_prcm_register_dump() do { } while (0)
+#endif /* CFG_PRCM_DEBUG */
+
+/*
+ * void config_diamond_sdram()
+ *
+ * Description:
+ * This routine initializes the processor's SDRAM Controller (SDRC)
+ * as appropriate for the Samsung K4X51163PI-FCG6 32 Mb x 16 b (64
+ * MiB) DDR SDRAM on the Nest Learning Thermostat board.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+config_diamond_sdram(void)
+{
+ u32 value, actim_ctrla, actim_ctrlb;
+
+ /*
+ * Step 1: Reset the SDRC controller and then wait for the reset
+ * event to clear.
+ */
+
+ __raw_writel(SDRC_SYSCONFIG_SOFTRESET_SET, SDRC_SYSCONFIG);
+ wait_on_value(SDRC_SYSSTATUS_RESETDONE,
+ SDRC_SYSSTATUS_RESETDONE,
+ SDRC_STATUS,
+ 12000000);
+ __raw_writel(SDRC_SYSCONFIG_SOFTRESET_CLEAR, SDRC_SYSCONFIG);
+
+ /*
+ * Step 2: Setup the position and geometry of the SDRAM device on
+ * the controller's bus.
+ */
+
+ value =
+ (SDRC_SHARING_LOCK_OFF |
+ SDRC_SHARING_CS1MUXCFG_ENCODE(SDRC_SHARING_CS1MUXCFG_16_BIT_16_0) |
+ SDRC_SHARING_CS0MUXCFG_ENCODE(SDRC_SHARING_CS0MUXCFG_16_BIT_16_0) |
+ SDRC_SHARING_SDRCTRISTATE_OFF);
+ __raw_writel(value, SDRC_SHARING);
+
+ /*
+ * Step 3: Setup the memory configuration, including RAS width,
+ * CAS width, address multiplexing, size, bank mapping, bus width,
+ * power mode, DDR type and memory type.
+ */
+
+ value =
+ (SDRC_MCFG_LOCKSTATUS_RW |
+ SDRC_MCFG_RASWIDTH_ENCODE(SDRC_MCFG_RASWIDTH_14_BITS) |
+ SDRC_MCFG_CASWIDTH_ENCODE(SDRC_MCFG_CASWIDTH_10_BITS) |
+ SDRC_MCFG_ADDRMUXLEGACY_FLEXIBLE |
+ SDRC_MCFG_RAMSIZE_ENCODE(CFG_SDRAM_SIZE_MB) |
+ SDRC_MCFG_BANKALLOCATION_ENCODE(SDRC_MCFG_BANKALLOCATION_R_B_C)|
+ SDRC_MCFG_B32NOT16_OFF |
+ SDRC_MCFG_DEEPPD_SUPPORTED |
+ SDRC_MCFG_DDRTYPE_ENCODE(SDRC_MCFG_DDRTYPE_MOBILE_DDR) |
+ SDRC_MCFG_RAMTYPE_ENCODE(SDRC_MCFG_RAMTYPE_DDR));
+ __raw_writel(value, SDRC_MCFG_0);
+
+ /*
+ * Step 4: Establish the AC fine tuning timing characteristics.
+ */
+
+ actim_ctrla
+ = (SDRC_ACTIM_CTRLA_TRFC_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRFC) |
+ SDRC_ACTIM_CTRLA_TRC_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRC) |
+ SDRC_ACTIM_CTRLA_TRAS_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRAS) |
+ SDRC_ACTIM_CTRLA_TRP_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRP) |
+ SDRC_ACTIM_CTRLA_TRCD_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRCD) |
+ SDRC_ACTIM_CTRLA_TRRD_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRRD) |
+ SDRC_ACTIM_CTRLA_TDPL_ENCODE(CFG_SDRC_ACTIM_CTRLA_TDPL) |
+ SDRC_ACTIM_CTRLA_TDAL_ENCODE(CFG_SDRC_ACTIM_CTRLA_TDAL));
+
+ actim_ctrlb
+ = (SDRC_ACTIM_CTRLB_TWTR_ENCODE(CFG_SDRC_ACTIM_CTRLB_TWTR) |
+ SDRC_ACTIM_CTRLB_TCKE_ENCODE(CFG_SDRC_ACTIM_CTRLB_TCKE) |
+ SDRC_ACTIM_CTRLB_TXP_ENCODE(CFG_SDRC_ACTIM_CTRLB_TXP) |
+ SDRC_ACTIM_CTRLB_TXSR_ENCODE(CFG_SDRC_ACTIM_CTRLB_TXSR));
+
+ __raw_writel(actim_ctrla, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(actim_ctrlb, SDRC_ACTIM_CTRLB_0);
+
+ /*
+ * Step 5: Establish the memory autorefresh control
+ */
+
+ value =
+ (SDRC_RFR_CTRL_ARCV_ENCODE(1244) |
+ SDRC_RFR_CTRL_ARE_ENCODE(SDRC_RFR_CTRL_ARE_1_ARCV));
+ __raw_writel(value, SDRC_RFR_CTRL_0);
+
+ value =
+ (SDRC_POWER_REG_WAKEUP_DELAYED |
+ SDRC_POWER_REG_AUTOCOUNT_ENCODE(0) |
+ SDRC_POWER_REG_SRFR_ON_RST_ENABLE |
+ SDRC_POWER_REG_SRFR_ON_IDLE_DISABLE |
+ SDRC_POWER_REG_CLKCTRL_ENCODE(SDRC_POWER_REG_CLKCTRL_NONE) |
+ SDRC_POWER_REG_PAGEPOLICY_HPHB);
+ __raw_writel(value, SDRC_POWER_REG);
+
+ /*
+ * Step 6: Establish the JEDEC-defined mode and DLL parameters.
+ */
+
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+
+ delay(5000);
+
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_PRECHARGE_ALL),
+ SDRC_MANUAL_0);
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+
+ value =
+ (SDRC_MR_ZERO_1 |
+ SDRC_MR_WBST_ENABLE |
+ SDRC_MR_ZERO_0 |
+ SDRC_MR_CASL_ENCODE(SDRC_MR_CASL_3) |
+ SDRC_MR_SIL_SERIAL |
+ SDRC_MR_BL_ENCODE(SDRC_MR_BL_4));
+ __raw_writel(value, SDRC_MR_0);
+
+ value =
+ (SDRC_DLLA_CTRL_FIXED_DELAY_ENCODE(0) |
+ SDRC_DLLA_CTRL_INIT_LAT_ENCODE(0) |
+ SDRC_DLLA_CTRL_MODE_ON_IDLE_ENCODE(SDRC_DLLA_CTRL_MODE_ON_IDLE_PWD) |
+ SDRC_DLLA_CTRL_DLL_ENABLE |
+ SDRC_DLLA_CTRL_LOCK_TRACKINGDELAY);
+ __raw_writel(value, SDRC_DLLA_CTRL);
+
+ /*
+ * Delay for a "reasonably long" period of time to allow the
+ * requested changes to take effect.
+ */
+
+ delay(0x20000);
+}
+
+/*
+ * void s_init()
+ *
+ * Description:
+ * This routine performs very early system initialization of chip
+ * pin multiplexing and clocks and is called when ONLY an
+ * SRAM-based stack is available (i.e. no SDRAM).
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+s_init(void)
+{
+ watchdog_init();
+ try_unlock_memory();
+ set_muxconf_regs();
+
+ delay(100);
+
+ prcm_init();
+ per_clocks_enable();
+ config_diamond_sdram();
+}
+
+/*
+ * int board_init()
+ *
+ * Description:
+ * This routine performs any early, board-specific initialization
+ * following core CPU initialization but prior to serial and NAND
+ * initialization.
+ *
+ * At present, there is nothing board-specific to do.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if OK; otherwise, non-zero on error.
+ *
+ */
+int
+board_init(void)
+{
+ return (0);
+}
+
+/*
+ * u32 get_device_type()
+ *
+ * Description:
+ * This routine returns the decoded value from the CPU's
+ * CONTROL_STATUS register DEVICETYPE field, indicating whether the
+ * device is of TST, EMU, HS or GP type.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The decoded CONTROL_STATUS register DEVICETYPE field.
+ *
+ */
+u32
+get_device_type(void)
+{
+ const int value = __raw_readl(CONTROL_STATUS);
+
+ return (CONTROL_STATUS_DEVICETYPE_DECODE(value));
+}
+
+/*
+ * u32 get_sysboot_value()
+ *
+ * Description:
+ * This routine returns the decoded value from the CPU's
+ * CONTROL_STATUS register SYSBOOT order subfield, indicating the
+ * order of memory interfaces from which the processor will attempt
+ * to boot itself.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The decoded CONTROL_STATUS register SYSBOOT order subfield.
+ *
+ */
+u32
+get_sysboot_value(void)
+{
+#if 0
+ const u32 value = __raw_readl(CONTROL_STATUS);
+ const u32 peripheral_type = CONTROL_STATUS_SYSBOOT_TYPE_PERIPHERAL;
+
+ /*
+ * This routine and callers of it are implicitly expecting the
+ * MEMORY interface (SYSBOOT[5] == 0) not the PERHIPHERAL
+ * interface (SYSBOOT[5] == 1) boot order, so check that is
+ * actually the case.
+ */
+
+ if (CONTROL_STATUS_SYSBOOT_TYPE_DECODE(value) == peripheral_type) {
+ hang();
+ }
+
+ return (CONTROL_STATUS_SYSBOOT_ORDER_DECODE(value));
+#else
+ return __raw_readl(CONTROL_STATUS) & 0x3f;
+#endif
+}
+
+/*
+ * int get_boot_device_list(const u32** device_list)
+ *
+ * Description:
+ * This routine returns a constant list indicating the preferred
+ * device boot list.
+ * It gets called from start_armboot in board.c
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The preferred first processor memory boot interface.
+ *
+ */
+
+int
+get_boot_devices_list(const u32** devices_list)
+{
+ static u32 list[MAX_J49_BOOT_DEVICES];
+ const u32 mem_order = get_sysboot_value();
+
+ // set defaults
+ int number_of_devices = 0;
+ *devices_list = &list[0];
+
+ switch (mem_order) {
+ case 15:
+ list[0] = GPMC_NAND;
+ list[1] = USB_PERIPHERAL;
+ list[2] = MMC_NAND;
+ number_of_devices = MAX_J49_BOOT_DEVICES;
+ break;
+ case 47:
+ list[0] = USB_PERIPHERAL;
+ list[1] = MMC_NAND;
+ list[2] = GPMC_NAND;
+ number_of_devices = MAX_J49_BOOT_DEVICES;
+ break;
+ default:
+ break;
+ }
+ return number_of_devices;
+}
+
+/*
+ * int misc_init_r()
+ *
+ * Description:
+ * This routine performs any miscellaneous, board-specific
+ * initialization following CPU, early board, serial and NAND
+ * initialization but prior to loading the secondary program loader
+ * to RAM.
+ *
+ * At present, there is nothing board-specific to do.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if OK; otherwise, non-zero on error.
+ *
+ */
+int
+misc_init_r(void)
+{
+ return (0);
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+static void
+wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void
+watchdog_init(void)
+{
+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+ sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+ sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+ wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+/*
+ * void foobar()
+ *
+ * Description:
+ * This routine...
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+per_clocks_enable(void)
+{
+ /* Enable GP2 timer. */
+ sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CFG_NS16550
+ /* Enable UART1 clocks */
+ sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+#endif
+
+#ifdef CONFIG_MMC
+ /* Enable MMC1 clocks */
+ sr32(CM_FCLKEN1_CORE, 24, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 24, 1, 0x1);
+#endif
+ delay(1000);
+}
+
+static int
+gpmc_config_0(void)
+{
+#if defined(CFG_GPMC_CONFIG1_0)
+ /*
+ * First, disable the interface and wait.
+ */
+ __raw_writel(GPMC_CONFIG7_CSVALID_DISABLED, GPMC_CONFIG7_0);
+
+ delay(1000);
+
+ /*
+ * Next, program the configuration parameters.
+ */
+ __raw_writel(CFG_GPMC_CONFIG1_0, GPMC_CONFIG1_0);
+ __raw_writel(CFG_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+ __raw_writel(CFG_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+ __raw_writel(CFG_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+ __raw_writel(CFG_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+ __raw_writel(CFG_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+
+ /*
+ * Finally, enable the GPMC mapping and spin for the parameters to
+ * become active.
+ */
+ __raw_writel((CFG_GPMC_CONFIG7_0 | GPMC_CONFIG7_CSVALID_ENABLED),
+ GPMC_CONFIG7_0);
+
+ delay(2000);
+
+ if (nand_chip()){
+ return (1);
+ }
+#endif /* defined(CFG_GPMC_CONFIG1_0) */
+
+ return (0);
+}
+
+/*
+ * int nand_init()
+ *
+ * Description:
+ * This routine initializes the General Purpose Memory Controller
+ * (GPMC) such that on-board NAND devices may be accessed for
+ * second-stage boot.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if NAND was successfully initialized; otherwise, 1.
+ *
+ */
+int
+nand_init(void)
+{
+ int status = 1;
+
+ /*
+ * Establish GPMC global settings.
+ */
+
+ __raw_writel(GPMC_SYSCONFIG_IDLEMODE_SMART, GPMC_SYSCONFIG);
+
+ __raw_writel(GPMC_IRQENABLE_ALL_DISABLE, GPMC_IRQENABLE);
+
+ __raw_writel(GPMC_TIMEOUTENABLE_OFF, GPMC_TIMEOUT_CONTROL);
+
+ if (gpmc_config_0()) {
+ puts("Unsupported NAND device @ GPMC0!\n");
+ goto done;
+ }
+
+ status = 0;
+
+ done:
+ /* Dump GPMC and SDRC registers if so configured. */
+
+ omap3_sdrc_register_dump();
+ omap3_gpmc_register_dump();
+ omap3_prcm_register_dump();
+
+ return (status);
+}
+
+/*
+ * void board_hang()
+ *
+ * Description:
+ * This routine performs any board-specific actions when the system
+ * hangs by executing hang(). At present, there is nothing to do;
+ * however, we might later drive the piezo or a LED.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+board_hang (void)
+{
+ return;
+}
diff --git a/x-loader/board/nest/j49-usb-loader/mux.c b/x-loader/board/nest/j49-usb-loader/mux.c
new file mode 100644
index 0000000..b8c7df0
--- /dev/null
+++ b/x-loader/board/nest/j49-usb-loader/mux.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703CUS, focusing
+ * primarily I/O pad multiplexer configuration.
+ *
+ * This is originally inherited and split from the OMAP3 EVM
+ * board file.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+
+#include "platform.h"
+
+/*
+ * void set_muxconf_regs()
+ *
+ * Description:
+ * This routines sets the I/O pad multiplexers for UART, GPMC, SDRC,
+ * GPIO.
+ *
+ * The commented string gives the final mux configuration for that pin
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ */
+void
+set_muxconf_regs(void)
+{
+ /*
+ * The bit fields for these settings are as follows:
+ *
+ * I{EN,DIS} - Input Enable/Disable
+ * PT[DU] - Pull-down, -up
+ * DIS,EN - Pull-down, -up disabled/enabled
+ * M[01234567] - Configuration mode 0-7
+ */
+
+ /*
+ * SDRAM Controller (SDRC)
+ *
+ * Most of the SDRC signals are used to drive the Samsung
+ * K4X51163PI-FCG6 512 Mb x 16-bit (64 MiB) DDR SDRAM. Because we
+ * interface in 16-bit rather than 32-bit mode, we place the
+ * unused pins in safe mode (Mode 7).
+ */
+
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); // SDRC_D0
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); // SDRC_D1
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); // SDRC_D2
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); // SDRC_D3
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); // SDRC_D4
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); // SDRC_D5
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); // SDRC_D6
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); // SDRC_D7
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); // SDRC_D8
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); // SDRC_D9
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); // SDRC_D10
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); // SDRC_D11
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); // SDRC_D12
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); // SDRC_D13
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); // SDRC_D14
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); // SDRC_D15
+
+ // Because we interface SDRAM in 16-bit mode, place
+ // SDRC_DATA[31:16] in safe mode (Mode 7).
+
+ MUX_VAL(CP(SDRC_D16), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D17), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D18), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D19), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D20), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D21), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D22), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D23), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D24), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D25), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D26), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D27), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D28), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D29), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D30), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D31), (IDIS | PTD | DIS | M7)); // Unused
+
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); // SDRC_CLK
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); // SDRC_DQS0
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); // SDRC_DQS1
+
+ // Place unused DQ pins in safe mode (Mode 7).
+
+ MUX_VAL(CP(SDRC_DQS2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_DQS3), (IDIS | PTD | DIS | M7)); // Unused
+
+ /*
+ * General Purpose Memory Controller (GPMC)
+ *
+ */
+
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); // GPMC_A1
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); // GPMC_A2
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); // GPMC_A3
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); // GPMC_A4
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); // GPMC_A5
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); // GPMC_A6
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); // GPMC_A7
+
+ // Place the unused GPMC_A8 pin in safe mode (Mode 7).
+
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M7)); // Unused
+
+ // Assign GPMC_A9 to GPIO_42 used as a push-pull, active low input
+ // from the USB PHY for USB suspend notification.
+
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M7)); // GPIO_42
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M7)); // Unused
+
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); // GPMC_D0
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); // GPMC_D1
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); // GPMC_D2
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); // GPMC_D3
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); // GPMC_D4
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); // GPMC_D5
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); // GPMC_D6
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); // GPMC_D7
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); // GPMC_D8
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); // GPMC_D9
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); // GPMC_D10
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); // GPMC_D11
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); // GPMC_D12
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); // GPMC_D13
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); // GPMC_D14
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); // GPMC_D15
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); // GPMC_nCS0
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); // GPMC_nCS1
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); // GPMC_nCS2
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)); // Unused
+
+ // Assign GPMC_NCS6 to GPT11_PWM_EVT used as a push-pull pulse width
+ // modulated (PWM) signal for the piezo.
+
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M3)); // GPT11_PWM_EVT
+
+ // Assign GPMC_NCS7 to GPIO_58 used as a push-pull output
+ // PIEZO_NENABLE to the TI SN74LVC2G240 Dual Buffer/Driver With
+ // 3-State Outputs inputs.
+
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M4)); // GPIO_58
+
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); // GPMC_CLK
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); // GPMC_nADV_ALE
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); // GPMC_nOE
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); // GPMC_nWE
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); // GPMC_nBE0_CLE
+
+ // Assign GPMC_NBE1 to GPIO_61 used as a push-pull output to the
+ // ZigBee active-low reset.
+
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); // GPIO_61
+
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); // GPMC_nWP
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); // GPMC_WAIT0
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); // GPMC_WAIT1
+ MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M7)); // Unavailable
+
+ // Assign GPMC_WAIT3 to GPIO_65 used as an active-high, push-pull
+ // backplate detect input.
+
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M4)); // GPIO_65
+
+ /*
+ * Display Subsystem (DSS)
+ *
+ * All DSS signals are used in their normal, default mode (Mode 0)
+ * to drive the Samsung LMS350DF0[13] LCD display panel.
+ */
+
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); // DSS_PCLK
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); // DSS_HSYNC
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); // DSS_VSYNC
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); // DSS_ACBIAS
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); // DSS_DATA0
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); // DSS_DATA1
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); // DSS_DATA2
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); // DSS_DATA3
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); // DSS_DATA4
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); // DSS_DATA5
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); // DSS_DATA6
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); // DSS_DATA7
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); // DSS_DATA8
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); // DSS_DATA9
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); // DSS_DATA10
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); // DSS_DATA11
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); // DSS_DATA12
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); // DSS_DATA13
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); // DSS_DATA14
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); // DSS_DATA15
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); // DSS_DATA16
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); // DSS_DATA17
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); // DSS_DATA18
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); // DSS_DATA19
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); // DSS_DATA20
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); // DSS_DATA21
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); // DSS_DATA22
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); // DSS_DATA23
+
+ MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M7)); // Unused
+
+ /*
+ * Universal Asynchronous Receiver / Transmitter (UART)
+ *
+ */
+
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); // UART1_TX
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M7)); // UART1_RTS
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M7)); // UART1_CTS
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); // UART1_RX
+ /*
+ * Control and Debug
+ *
+ */
+
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); // SYS_32K
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M0)); // SYS_BOOT0
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0)); // SYS_BOOT1
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)); // SYS_BOOT2
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0)); // SYS_BOOT3
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0)); // SYS_BOOT4
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0)); // SYS_BOOT5
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M0)); // SYS_BOOT6
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTU | EN | M0)); // SYS_CLKOUT1
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); // JTAG_nTRST
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); // JTAG_TCK
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); // JTAG_TMS
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); // JTAG_TDI
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); // JTAG_EMU0
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); // JTAG_EMU1
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M7)); // Unused
+
+ // Assign ETK_D1[45] as MM2_RXRCV and MM2_TXSE0 USB FS/LS Host
+ // (Mode 5)
+
+ MUX_VAL(CP(ETK_D14_ES2), (IDIS | PTD | DIS | M7)); // MM2_RXRCV
+ MUX_VAL(CP(ETK_D15_ES2), (IDIS | PTD | DIS | M7)); // MM2_TXSE0
+}
diff --git a/x-loader/board/nest/j49-usb-loader/platform.S b/x-loader/board/nest/j49-usb-loader/platform.S
new file mode 100644
index 0000000..0549d27
--- /dev/null
+++ b/x-loader/board/nest/j49-usb-loader/platform.S
@@ -0,0 +1,557 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific setup for the Nest Learning
+ * Thermostat board.
+ *
+ * It inherits entirely from the equivalent TI OMAP3 EVM
+ * file.
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * NOTE: 3430 X-loader currently does not use this code.
+* It could be removed its is kept for compatabily with u-boot.
+ *
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ * confused. A reset of the controller gets it back. Taking away its
+ * L3 when its not in self refresh seems bad for it. Normally, this code
+ * runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4-r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4-r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG1_0)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG3_0)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG4_0)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG5_0)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+#endif /* !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) */
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE
+.word 0x07
+.word 0x05
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x1F4
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179
+.word 0x12
+.word 0x04
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D
+.word 0x19
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA
+.word 0x32
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x2F
+.word 0x03
+.word 0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D
+.word 0x05
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x168
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082
+.word 0x09
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x0B
+.word 0x06
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D
+.word 0x0C
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F
+.word 0x30
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x17
+.word 0x06
+.word 0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x19F
+.word 0x0E
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x10
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x14C
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x21
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8
+.word 0x05
+.word 0x07
+.word 0x09
+
+/* 13MHz */
+.word 0x1B0
+.word 0x0C
+.word 0x03
+.word 0x09
+
+/* 19.2MHz */
+.word 0xE1
+.word 0x09
+.word 0x07
+.word 0x09
+
+/* 26MHz */
+.word 0xD8
+.word 0x0C
+.word 0x07
+.word 0x09
+
+/* 38.4MHz */
+.word 0xE1
+.word 0x13
+.word 0x07
+.word 0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
+
+/*
+ * Tables for 36x/37x devices
+ *
+ * (Populated for 13MHz only)
+ */
+mpu_36x_dpll_param:
+// M N FS M2
+#if defined(CONFIG_SYS_MPU_DPLL_300MHZ)
+.word 150, 5, 0, 1 // 12 MHz
+.word 300, 12, 0, 1 // 13 MHz
+.word 125, 7, 0, 1 // 19.2 MHz
+.word 150, 12, 0, 1 // 26 MHz
+.word 125, 15, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_MPU_DPLL_600MHZ)
+.word 300, 5, 0, 1 // 12 MHz
+.word 600, 12, 0, 1 // 13 MHz
+.word 125, 3, 0, 1 // 19.2 MHz
+.word 300, 12, 0, 1 // 26 MHz
+.word 125, 7, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#else
+# error "MPU DPLL settings are not defined!"
+#endif /* defined(CONFIG_SYS_MPU_DPLL_600MHZ) */
+
+iva_36x_dpll_param:
+// M N FS M2
+.word 10, 0, 0, 1 // 12 MHz
+.word 10, 0, 0, 1 // 13 MHz
+.word 10, 0, 0, 1 // 19.2 MHz
+.word 10, 0, 0, 1 // 26 MHz
+.word 10, 0, 0, 1 // 38.4 MHz
+.word 10, 0, 0, 1 // 16.8 MHz
+
+core_36x_dpll_param:
+// M N FS M2
+#if defined(CONFIG_SYS_CORE_DPLL_200MHZ)
+.word 100, 5, 0, 1 // 12 MHz
+.word 200, 12, 0, 1 // 13 MHz
+.word 375, 35, 0, 1 // 19.2 MHz
+.word 100, 12, 0, 1 // 26 MHz
+.word 375, 71, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_CORE_DPLL_332MHZ)
+.word 166, 5, 0, 1 // 12 MHz
+.word 332, 12, 0, 1 // 13 MHz
+.word 415, 23, 0, 1 // 19.2 MHz
+.word 166, 12, 0, 1 // 26 MHz
+.word 415, 47, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_CORE_DPLL_400MHZ)
+.word 200, 5, 0, 1 // 12 MHz
+.word 400, 12, 0, 1 // 13 MHz
+.word 375, 17, 0, 1 // 19.2 MHz
+.word 200, 12, 0, 1 // 26 MHz
+.word 375, 35, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#else
+# error "Core DPLL settings are not defined!"
+#endif /* defined(CONFIG_SYS_CORE_DPLL_400MHZ) */
+
+/*
+ * For the peripheral (PER) (aka DPLL4) clock settings, there are only
+ * effectively two clock choices, 96 MHz or 192 MHz. However, the only
+ * time 192 MHz is apt to be used in an application is if both SGX and
+ * TV output are used.
+ *
+ * For any given system clock, the dividers are configured thus (per
+ * Section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" of the OMAP3 TRM):
+ *
+ * PER[clkout] = (SYS[clkout] * M) / (N + 1)
+ *
+ * M2[clkout]: PER[clkout] / M2 used by UART, MMC, I2C, etc.
+ * M3[clkout]: PER[clkout] / M3 used by TV out.
+ * M4[clkout]: PER[clkout] / M4 used by DSS.
+ * M5[clkout]: PER[clkout] / M5 used by camera.
+ * M6[clkout]: PER[clkout] / M6 used by emulation.
+ *
+ * So, for a 19.2 MHz system clock and the scalar entries below:
+ *
+ * PER[clkout] = (19.2 * 540) / (11 + 1) = 864
+ *
+ * M2[clkout]: 864 / 9 = 96 MHz
+ * M3[clkout]: 864 / 16 = 54 MHz
+ * M4[clkout]: 864 / 5 = 172.8 MHz
+ * M5[clkout]: 864 / 4 = 216 MHz
+ * M6[clkout]: 864 / 3 = 288 MHz
+ */
+per_36x_dpll_param:
+// SYS_CLK M N M2 M3 M4 M5 M6 m2DIV
+.word 12000, 432, 5, 9, 16, 9, 4, 3, 1 // 12 MHz
+.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 // 13 MHz
+.word 19200, 540, 11, 9, 16, 9, 4, 3, 1 // 19.2 MHz
+.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 // 26 MHz
+.word 38400, 270, 11, 9, 16, 9, 4, 3, 1 // 38.4 MHz
+.word 16800, 360, 6, 9, 16, 9, 4, 3, 1 // 16.8 MHz
+
+.globl get_36x_mpu_dpll_param
+get_36x_mpu_dpll_param:
+ adr r0, mpu_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_iva_dpll_param
+get_36x_iva_dpll_param:
+ adr r0, iva_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_core_dpll_param
+get_36x_core_dpll_param:
+ adr r0, core_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_per_dpll_param
+get_36x_per_dpll_param:
+ adr r0, per_36x_dpll_param
+ mov pc, lr
diff --git a/x-loader/board/nest/j49-usb-loader/platform.h b/x-loader/board/nest/j49-usb-loader/platform.h
new file mode 100644
index 0000000..8f8c12d
--- /dev/null
+++ b/x-loader/board/nest/j49-usb-loader/platform.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file defines data structures and function prototypes for
+ * accessing Digital Phased Lock Loop (DPLL) parameters and
+ * settings.
+ *
+ */
+
+#ifndef _NEST_J49_PLATFORM_H_
+#define _NEST_J49_PLATFORM_H_
+
+#include <asm/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Type Definitions
+ */
+
+/* Used to index into DPLL parameter tables */
+
+struct dpll_param {
+ u32 m;
+ u32 n;
+ u32 fsel;
+ u32 m2;
+};
+
+struct dpll_per_36x_param {
+ u32 sys_clk;
+ u32 m;
+ u32 n;
+ u32 m2;
+ u32 m3;
+ u32 m4;
+ u32 m5;
+ u32 m6;
+ u32 m2div;
+};
+
+typedef struct dpll_param dpll_param;
+
+/*
+ * Inline Functions
+ */
+static inline void
+delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+
+/*
+ * Function Prototypes
+ *
+ * The following functions are exported from platform.S.
+ */
+
+extern dpll_param * get_mpu_dpll_param(void);
+extern dpll_param * get_iva_dpll_param(void);
+extern dpll_param * get_core_dpll_param(void);
+extern dpll_param * get_per_dpll_param(void);
+
+extern dpll_param * get_36x_mpu_dpll_param(void);
+extern dpll_param * get_36x_iva_dpll_param(void);
+extern dpll_param * get_36x_core_dpll_param(void);
+extern dpll_param * get_36x_per_dpll_param(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _NEST_J49_PLATFORM_H_ */
diff --git a/x-loader/board/nest/j49-usb-loader/prcm.c b/x-loader/board/nest/j49-usb-loader/prcm.c
new file mode 100644
index 0000000..5625ad7
--- /dev/null
+++ b/x-loader/board/nest/j49-usb-loader/prcm.c
@@ -0,0 +1,565 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703CUS, focusing
+ * primarily clock set-up for the processor's Power, Reset and
+ * Clock Manager (PRCM)
+ *
+ * This is originally inherited and split from the OMAP3 EVM
+ * board file.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+
+#include "platform.h"
+
+/*
+ * u32 get_osc_clk_speed()
+ *
+ * Description:
+ * This routine determines the reference oscillator speed based on
+ * a known 32 kHz clock and general purpose timer.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The reference oscillator clock speed.
+ *
+ */
+static u32
+get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, cdiv, val;
+
+ val = __raw_readl(PRM_CLKSRC_CTRL);
+
+ if (val & BIT7)
+ cdiv = 2;
+ else if (val & BIT6)
+ cdiv = 1;
+ else
+ /*
+ * Should never reach here!
+ * TBD: Add a WARN()/BUG()
+ * For now, assume divider as 1.
+ */
+ cdiv = 1;
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
+
+ /* Enable I and F Clocks for GPT1 */
+ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+ __raw_writel(val, CM_ICLKEN_WKUP);
+ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
+ __raw_writel(val, CM_FCLKEN_WKUP);
+
+ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
+ /* enable 32kHz source *//* enabled out of reset */
+ /* determine sys_clk via gauging */
+
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
+ while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
+ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
+ while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
+ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+
+ if (cdiv == 2)
+ {
+ cdiff *= 2;
+ }
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return (S38_4M);
+ else if (cdiff > 15200)
+ return (S26M);
+ else if (cdiff > 13000)
+ return (S24M);
+ else if (cdiff > 9000)
+ return (S19_2M);
+ else if (cdiff > 7600)
+ return (S13M);
+ else
+ return (S12M);
+}
+
+/*
+ * void get_sys_clkin_sel()
+ *
+ * Description:
+ * This routine sets the value for the PRCM PRM system clock
+ * frequency selector, which should be written to PRM_CLKSEL.
+ *
+ * Input(s):
+ * hertz - The speed, in MHz, that the system clock is believed
+ * to be running at.
+ * sys_clkin_sel - A pointer to storage for the index used to access the
+ * digital PLL settings.
+ *
+ * Output(s):
+ * sys_clkin_sel - A pointer to the index for the digital PLL settings
+ * appropriate for the specified system clock rate.
+ *
+ * Returns:
+ * N/A
+ *
+ */
+static void
+get_sys_clkin_sel(u32 hertz, u32 *sys_clkin_sel)
+{
+ switch (hertz) {
+
+ case S38_4M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_38_4_MHZ;
+ break;
+
+ case S26M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_26_0_MHZ;
+ break;
+
+ case S19_2M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_19_2_MHZ;
+ break;
+
+ case S16_8M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_16_8_MHZ;
+ break;
+
+ case S13M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_13_0_MHZ;
+ break;
+
+ case S12M:
+ default:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_12_0_MHZ;
+ break;
+
+ }
+}
+
+/*
+ * OMAP34x/35x specific functions
+ */
+static void
+dpll3_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address of Core DPLL param table*/
+ ptr = (dpll_param *)get_core_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* CORE DPLL */
+ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(CM_CLKSEL1_PLL, 27, 5, ptr->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(CM_CLKSEL1_PLL, 16, 11, ptr->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(CM_CLKSEL1_PLL, 8, 7, ptr->n);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0);
+
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV_34X); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(CM_CLKEN_PLL, 4, 4, ptr->fsel);
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+dpll4_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ ptr = (dpll_param *)get_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr = ptr + clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ sr32(CM_CLKSEL3_PLL, 0, 5, ptr->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
+ sr32(CM_CLKSEL2_PLL, 8, 11, ptr->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(CM_CLKSEL2_PLL, 0, 7, ptr->n);
+
+ /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
+ sr32(CM_CLKEN_PLL, 20, 4, ptr->fsel);
+
+ /* LOCK MODE (EN_PERIPH_DPLL) : CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+mpu_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to MPU DPLL param table*/
+ ptr = (dpll_param *)get_mpu_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, ptr->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, ptr->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, ptr->n);
+
+ /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
+ sr32(CM_CLKEN_PLL_MPU, 4, 4, ptr->fsel);
+}
+
+static void
+iva_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to IVA DPLL param table*/
+ ptr = (dpll_param *)get_iva_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* IVA DPLL */
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, ptr->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, ptr->n);
+
+ /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
+ sr32(CM_CLKEN_PLL_IVA2, 4, 4, ptr->fsel);
+
+ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);
+
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+}
+
+/*
+ * OMAP3630 specific functions
+ */
+static void
+dpll3_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address of Core DPLL param table*/
+ ptr = (dpll_param *)get_36x_core_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr += clk_index;
+
+ /* CORE DPLL */
+ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(CM_CLKSEL1_PLL, 27, 5, ptr->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(CM_CLKSEL1_PLL, 16, 11, ptr->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(CM_CLKSEL1_PLL, 8, 7, ptr->n);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0);
+
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV_36X); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(CM_CLKEN_PLL, 4, 4, ptr->fsel);
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+dpll4_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct dpll_per_36x_param *ptr;
+
+ ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr += clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
+ sr32(CM_CLKSEL1_EMU, 24, 6, ptr->m6);
+
+ /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
+ sr32(CM_CLKSEL_CAM, 0, 6, ptr->m5);
+
+ /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
+ sr32(CM_CLKSEL_DSS, 0, 6, ptr->m4);
+
+ /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
+ sr32(CM_CLKSEL_DSS, 8, 6, ptr->m3);
+
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ sr32(CM_CLKSEL3_PLL, 0, 5, ptr->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
+ sr32(CM_CLKSEL2_PLL, 8, 12, ptr->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(CM_CLKSEL2_PLL, 0, 7, ptr->n);
+
+ /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
+ sr32(CM_CLKSEL_CORE, 12, 2, ptr->m2div);
+
+ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+mpu_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to MPU DPLL param table*/
+ ptr = (dpll_param *)get_36x_mpu_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + (2*clk_index) + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, ptr->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, ptr->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, ptr->n);
+
+ /* LOCK MODE (EN_MPU_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+}
+
+static void
+iva_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to IVA DPLL param table*/
+ ptr = (dpll_param *)get_36x_iva_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + (2*clk_index) + sil_index;
+
+ /* IVA DPLL */
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, ptr->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, ptr->n);
+
+ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);
+
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+}
+
+/*
+ * void prcm_init()
+ *
+ * Description:
+ * This routine initializes clocks in a board-specific manner for
+ * the processor's Power, Reset and Clock Manager (PRCM) and is
+ * called only when an SRAM-based stack is available (i.e. no
+ * SDRAM).
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+prcm_init(void)
+{
+ u32 sys_clk_rate = 0, sys_clkin_sel, sys_clk_div;
+ u32 clk_index, sil_index;
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ sys_clk_rate = get_osc_clk_speed();
+ get_sys_clkin_sel(sys_clk_rate, &sys_clkin_sel);
+
+ /* Set the PRM_CLKSEL_SYS_CLKIN_SEL value in the processor. */
+
+ sr32(PRCM_PRM_CCR_CLKSEL,
+ PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_START,
+ PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_BITS,
+ sys_clkin_sel);
+
+ /* If the input clock is greater than 19.2M always divide by two.
+ *
+ * On OMAP3630, DDR data corruption has been observed on OFF mode
+ * exit if the sys clock was lower than 26M. As a work around,
+ * OMAP3630 is operated at 26M sys clock and this internal division
+ * is not performed.
+ */
+
+ if((is_cpu_family() != CPU_OMAP36XX) &&
+ (sys_clkin_sel > PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_19_2_MHZ)) {
+ sys_clk_div = PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BY_2;
+ clk_index = sys_clkin_sel / 2;
+
+ } else {
+ sys_clk_div = PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BY_1;
+ clk_index = sys_clkin_sel / 1;
+
+ }
+
+ sr32(PRCM_PRM_GR_CLKSRC_CTRL,
+ PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_START,
+ PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BITS,
+ sys_clk_div);
+
+ if (is_cpu_family() == CPU_OMAP36XX) {
+ dpll3_init_36xx(0, clk_index);
+ dpll4_init_36xx(0, clk_index);
+ mpu_init_36xx(0, clk_index);
+ iva_init_36xx(0, clk_index);
+
+ } else {
+ sil_index = get_cpu_rev() - 1;
+
+ /* The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+ dpll3_init_34xx(sil_index, clk_index);
+ dpll4_init_34xx(sil_index, clk_index);
+ iva_init_34xx(sil_index, clk_index);
+ mpu_init_34xx(sil_index, clk_index);
+
+ /* Lock MPU DPLL to set frequency */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+ }
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+ sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+ delay(5000);
+}
diff --git a/x-loader/board/nest/j49-usb-loader/x-load.lds b/x-loader/board/nest/j49-usb-loader/x-load.lds
new file mode 100644
index 0000000..e0603a2
--- /dev/null
+++ b/x-loader/board/nest/j49-usb-loader/x-load.lds
@@ -0,0 +1,65 @@
+/*
+ *
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ * All rights reserved.
+ *
+ * Description:
+ * This file is the X-Loader linker scatter file for the Nest
+ * Learning Thermostat board.
+ *
+ */
+
+/*
+ * November 2006 - Changed to support 3430sdp device
+ * Copyright (c) 2004-2006 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/omap3/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/nest/j49/Makefile b/x-loader/board/nest/j49/Makefile
new file mode 100644
index 0000000..ece4a90
--- /dev/null
+++ b/x-loader/board/nest/j49/Makefile
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2010-2011 Nest Labs, Inc.
+# All rights reserved.
+#
+# Description:
+# This file is the make file for portions of X-Loader specific
+# to the Nest Learning Thermostat board.
+#
+
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := j49.o mux.o prcm.o
+SOBJS := platform.o
+
+CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/nest/j49/config.mk b/x-loader/board/nest/j49/config.mk
new file mode 100644
index 0000000..881380c
--- /dev/null
+++ b/x-loader/board/nest/j49/config.mk
@@ -0,0 +1,21 @@
+
+
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments#
+#
+# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+
+# For use if you want X-Loader to relocate from SRAM to DDR
+#TEXT_BASE = 0x80e80000
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+TEXT_BASE = 0x40200800
diff --git a/x-loader/board/nest/j49/j49.c b/x-loader/board/nest/j49/j49.c
new file mode 100644
index 0000000..c934c50
--- /dev/null
+++ b/x-loader/board/nest/j49/j49.c
@@ -0,0 +1,1046 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * (C) Copyright 2006
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703ACUS, focusing
+ * primarily on GPIO, RAM and flash initialization.
+ *
+ * This is inherited from the OMAP3 EVM equivalent file.
+ *
+ * Initialization function order is roughly:
+ *
+ * 1) s_init
+ * 2) board_init
+ * 3) misc_init_r
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+
+#include "platform.h"
+
+#define MAX_J49_BOOT_DEVICES (3)
+
+void
+udelay(unsigned long usecs) {
+ delay(usecs);
+}
+
+static inline u32
+get_cpu_id(void)
+{
+ u32 cpuid = 0;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
+
+ return (cpuid);
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32
+get_cpu_rev(void)
+{
+ const u32 cpuid = get_cpu_id();
+
+ /* On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate
+ * between ES2.0 and ES1.0.
+ */
+ if ((cpuid & 0xf) == 0x0) {
+ return (CPU_3430_ES1);
+
+ } else {
+ return (CPU_3430_ES2);
+
+ }
+
+}
+
+u32
+is_cpu_family(void)
+{
+ const u32 cpuid = get_cpu_id();
+ u32 cpu_family = 0, omap34xx_id = 0;
+ u16 hawkeye;
+
+ if ((cpuid & 0xf) == 0x0) {
+ cpu_family = CPU_OMAP34XX;
+
+ } else {
+ omap34xx_id = __raw_readl(OMAP34XX_CONTROL_ID);
+ hawkeye = (omap34xx_id >> HAWKEYE_SHIFT) & 0xffff;
+
+ switch (hawkeye) {
+
+ case HAWKEYE_AM35XX:
+ cpu_family = CPU_AM35XX;
+ break;
+
+ case HAWKEYE_OMAP36XX:
+ cpu_family = CPU_OMAP36XX;
+ break;
+
+ case HAWKEYE_OMAP34XX:
+ default:
+ cpu_family = CPU_OMAP34XX;
+ break;
+
+ }
+ }
+
+ return (cpu_family);
+}
+/******************************************
+ * cpu_is_3410(void) - returns true for 3410
+ ******************************************/
+u32
+cpu_is_3410(void)
+{
+ int status;
+ if(get_cpu_rev() < CPU_3430_ES2) {
+ return 0;
+ } else {
+ /* read scalability status and return 1 for 3410*/
+ status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
+ /* Check whether MPU frequency is set to 266 MHz which
+ * is nominal for 3410. If yes return true else false
+ */
+ if (((status >> 8) & 0x3) == 0x2)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/*
+ * void sr32()
+ *
+ * Description:
+ * This routine clears and sets a value in a bit extent for a
+ * 32-bit value at the specified address.
+ *
+ * Input(s):
+ * addr - The address at which to clear and set the specified
+ * specified 32-bit value.
+ * start_bit - The first bit of the 32-bit data to clear and set.
+ * num_bits - The range of bits of the 32-bit data to clear and set.
+ * value - The value to set.
+ *
+ * Output(s):
+ * addr - The address with the specified bit extent cleared and
+ * set to the specified value.
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+
+ msk = (1 << num_bits);
+ --msk;
+ tmp = __raw_readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ __raw_writel(tmp, addr);
+}
+
+/*
+ * u32 wait_on_value()
+ *
+ * Description:
+ * This routine reads the register at the specified address and
+ * busy waits until the specified match value is read or until the
+ * bounded number of loops have been reached.
+ *
+ * Input(s):
+ * read_bit_mask - The bit mask to apply after reading the register.
+ * match_value - The value to match on after reading and masking.
+ * read_addr - The register address to read.
+ * bound - The maximum number of times to read before giving
+ * up.
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * True (1) if the match_value was reached; otherwise, false (0).
+ *
+ */
+u32
+wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
+
+/*****************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ * (GP Device only)
+ *****************************************/
+static void
+secure_unlock(void)
+{
+ /* Permission values for registers -Full fledged permissions to all */
+ #define UNLOCK_1 0xFFFFFFFF
+ #define UNLOCK_2 0x00000000
+ #define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT)*/
+ __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+ __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+ __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+ /* IVA Changes */
+ __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+static void
+try_unlock_memory(void)
+{
+ const int type = get_device_type();
+
+ /*
+ * If the processor is a GP device, unlock the device SRAM for
+ * general use.
+ */
+
+ if (type == CONTROL_STATUS_DEVICETYPE_GP) {
+ secure_unlock();
+ }
+
+ return;
+}
+
+#if defined(CFG_SDRAM_DEBUG)
+static void
+omap3_sdrc_register_dump(void)
+{
+ printf("\n SDRC Register Dump:\n");
+
+ DUMP_REGL(SDRC_REVISION);
+ DUMP_REGL(SDRC_SYSCONFIG);
+ DUMP_REGL(SDRC_SYSSTATUS);
+ DUMP_REGL(SDRC_CS_CFG);
+ DUMP_REGL(SDRC_SHARING);
+ DUMP_REGL(SDRC_ERR_ADDR);
+ DUMP_REGL(SDRC_ERR_TYPE);
+ DUMP_REGL(SDRC_DLLA_CTRL);
+ DUMP_REGL(SDRC_DLLA_STATUS);
+ DUMP_REGL(SDRC_POWER_REG);
+ DUMP_REGL(SDRC_MCFG_0);
+ DUMP_REGL(SDRC_MR_0);
+ DUMP_REGL(SDRC_EMR2_0);
+ DUMP_REGL(SDRC_ACTIM_CTRLA_0);
+ DUMP_REGL(SDRC_ACTIM_CTRLB_0);
+ DUMP_REGL(SDRC_RFR_CTRL_0);
+ DUMP_REGL(SDRC_MANUAL_0);
+ DUMP_REGL(SDRC_MCFG_1);
+ DUMP_REGL(SDRC_MR_1);
+ DUMP_REGL(SDRC_EMR2_1);
+ DUMP_REGL(SDRC_ACTIM_CTRLA_1);
+ DUMP_REGL(SDRC_ACTIM_CTRLB_1);
+ DUMP_REGL(SDRC_RFR_CTRL_1);
+ DUMP_REGL(SDRC_MANUAL_1);
+}
+#else
+# define omap3_sdrc_register_dump() do { } while (0)
+#endif /* defined(CFG_SDRAM_DEBUG) */
+
+#if defined(CFG_GPMC_DEBUG)
+static void
+omap3_gpmc_register_dump(void)
+{
+ printf("\n GPMC Register Dump:\n");
+
+ DUMP_REGL(GPMC_REVISION);
+ DUMP_REGL(GPMC_SYSCONFIG);
+ DUMP_REGL(GPMC_SYSSTATUS);
+ DUMP_REGL(GPMC_IRQSTATUS);
+ DUMP_REGL(GPMC_IRQENABLE);
+ DUMP_REGL(GPMC_TIMEOUT_CONTROL);
+ DUMP_REGL(GPMC_ERR_ADDRESS);
+ DUMP_REGL(GPMC_ERR_TYPE );
+ DUMP_REGL(GPMC_CONFIG );
+ DUMP_REGL(GPMC_STATUS );
+
+ DUMP_REGL(GPMC_CONFIG1_0);
+ DUMP_REGL(GPMC_CONFIG2_0);
+ DUMP_REGL(GPMC_CONFIG3_0);
+ DUMP_REGL(GPMC_CONFIG4_0);
+ DUMP_REGL(GPMC_CONFIG5_0);
+ DUMP_REGL(GPMC_CONFIG6_0);
+ DUMP_REGL(GPMC_CONFIG7_0);
+
+ DUMP_REGL(GPMC_CONFIG1_1);
+ DUMP_REGL(GPMC_CONFIG2_1);
+ DUMP_REGL(GPMC_CONFIG3_1);
+ DUMP_REGL(GPMC_CONFIG4_1);
+ DUMP_REGL(GPMC_CONFIG5_1);
+ DUMP_REGL(GPMC_CONFIG6_1);
+ DUMP_REGL(GPMC_CONFIG7_1);
+
+ DUMP_REGL(GPMC_CONFIG1_2);
+ DUMP_REGL(GPMC_CONFIG2_2);
+ DUMP_REGL(GPMC_CONFIG3_2);
+ DUMP_REGL(GPMC_CONFIG5_2);
+ DUMP_REGL(GPMC_CONFIG4_2);
+ DUMP_REGL(GPMC_CONFIG6_2);
+ DUMP_REGL(GPMC_CONFIG7_2);
+
+ DUMP_REGL(GPMC_CONFIG1_3);
+ DUMP_REGL(GPMC_CONFIG2_3);
+ DUMP_REGL(GPMC_CONFIG3_3);
+ DUMP_REGL(GPMC_CONFIG4_3);
+ DUMP_REGL(GPMC_CONFIG5_3);
+ DUMP_REGL(GPMC_CONFIG6_3);
+ DUMP_REGL(GPMC_CONFIG7_3);
+
+ DUMP_REGL(GPMC_CONFIG1_4);
+ DUMP_REGL(GPMC_CONFIG2_4);
+ DUMP_REGL(GPMC_CONFIG3_4);
+ DUMP_REGL(GPMC_CONFIG4_4);
+ DUMP_REGL(GPMC_CONFIG5_4);
+ DUMP_REGL(GPMC_CONFIG6_4);
+ DUMP_REGL(GPMC_CONFIG7_4);
+
+ DUMP_REGL(GPMC_CONFIG1_5);
+ DUMP_REGL(GPMC_CONFIG2_5);
+ DUMP_REGL(GPMC_CONFIG3_5);
+ DUMP_REGL(GPMC_CONFIG4_5);
+ DUMP_REGL(GPMC_CONFIG5_5);
+ DUMP_REGL(GPMC_CONFIG6_5);
+ DUMP_REGL(GPMC_CONFIG7_5);
+
+ DUMP_REGL(GPMC_CONFIG1_6);
+ DUMP_REGL(GPMC_CONFIG2_6);
+ DUMP_REGL(GPMC_CONFIG3_6);
+ DUMP_REGL(GPMC_CONFIG4_6);
+ DUMP_REGL(GPMC_CONFIG5_6);
+ DUMP_REGL(GPMC_CONFIG6_6);
+ DUMP_REGL(GPMC_CONFIG7_6);
+
+ DUMP_REGL(GPMC_CONFIG1_7);
+ DUMP_REGL(GPMC_CONFIG2_7);
+ DUMP_REGL(GPMC_CONFIG3_7);
+ DUMP_REGL(GPMC_CONFIG4_7);
+ DUMP_REGL(GPMC_CONFIG5_7);
+ DUMP_REGL(GPMC_CONFIG6_7);
+ DUMP_REGL(GPMC_CONFIG7_7);
+
+#if 0
+ DUMP_REGL(GPMC_NAND_COMMAND_0);
+ DUMP_REGL(GPMC_NAND_COMMAND_1);
+ DUMP_REGL(GPMC_NAND_COMMAND_2);
+ DUMP_REGL(GPMC_NAND_COMMAND_3);
+ DUMP_REGL(GPMC_NAND_COMMAND_4);
+ DUMP_REGL(GPMC_NAND_COMMAND_5);
+ DUMP_REGL(GPMC_NAND_COMMAND_6);
+ DUMP_REGL(GPMC_NAND_COMMAND_7);
+
+ DUMP_REGL(GPMC_NAND_ADDRESS_0);
+ DUMP_REGL(GPMC_NAND_ADDRESS_1);
+ DUMP_REGL(GPMC_NAND_ADDRESS_2);
+ DUMP_REGL(GPMC_NAND_ADDRESS_3);
+ DUMP_REGL(GPMC_NAND_ADDRESS_4);
+ DUMP_REGL(GPMC_NAND_ADDRESS_5);
+ DUMP_REGL(GPMC_NAND_ADDRESS_6);
+ DUMP_REGL(GPMC_NAND_ADDRESS_7);
+
+ DUMP_REGL(GPMC_NAND_DATA_0);
+ DUMP_REGL(GPMC_NAND_DATA_1);
+ DUMP_REGL(GPMC_NAND_DATA_2);
+ DUMP_REGL(GPMC_NAND_DATA_3);
+ DUMP_REGL(GPMC_NAND_DATA_4);
+ DUMP_REGL(GPMC_NAND_DATA_5);
+ DUMP_REGL(GPMC_NAND_DATA_6);
+ DUMP_REGL(GPMC_NAND_DATA_7);
+
+ DUMP_REGL(GPMC_PREFETCH_CONFIG1);
+ DUMP_REGL(GPMC_PREFETCH_CONFIG2);
+ DUMP_REGL(GPMC_PREFETCH_CONTROL);
+ DUMP_REGL(GPMC_PREFETCH_STATUS);
+
+ DUMP_REGL(GPMC_ECC_CONFIG);
+ DUMP_REGL(GPMC_ECC_CONTROL);
+ DUMP_REGL(GPMC_ECC_SIZE_CONFIG);
+
+ DUMP_REGL(GPMC_ECC1_RESULT);
+ DUMP_REGL(GPMC_ECC2_RESULT);
+ DUMP_REGL(GPMC_ECC3_RESULT);
+ DUMP_REGL(GPMC_ECC4_RESULT);
+ DUMP_REGL(GPMC_ECC5_RESULT);
+ DUMP_REGL(GPMC_ECC6_RESULT);
+ DUMP_REGL(GPMC_ECC7_RESULT);
+ DUMP_REGL(GPMC_ECC8_RESULT);
+ DUMP_REGL(GPMC_ECC9_RESULT);
+
+ DUMP_REGL(GPMC_BCH_RESULT0_0);
+ DUMP_REGL(GPMC_BCH_RESULT0_1);
+ DUMP_REGL(GPMC_BCH_RESULT0_2);
+ DUMP_REGL(GPMC_BCH_RESULT0_3);
+ DUMP_REGL(GPMC_BCH_RESULT0_4);
+ DUMP_REGL(GPMC_BCH_RESULT0_5);
+ DUMP_REGL(GPMC_BCH_RESULT0_6);
+ DUMP_REGL(GPMC_BCH_RESULT0_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT1_0);
+ DUMP_REGL(GPMC_BCH_RESULT1_1);
+ DUMP_REGL(GPMC_BCH_RESULT1_2);
+ DUMP_REGL(GPMC_BCH_RESULT1_3);
+ DUMP_REGL(GPMC_BCH_RESULT1_4);
+ DUMP_REGL(GPMC_BCH_RESULT1_5);
+ DUMP_REGL(GPMC_BCH_RESULT1_6);
+ DUMP_REGL(GPMC_BCH_RESULT1_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT2_0);
+ DUMP_REGL(GPMC_BCH_RESULT2_1);
+ DUMP_REGL(GPMC_BCH_RESULT2_2);
+ DUMP_REGL(GPMC_BCH_RESULT2_3);
+ DUMP_REGL(GPMC_BCH_RESULT2_4);
+ DUMP_REGL(GPMC_BCH_RESULT2_5);
+ DUMP_REGL(GPMC_BCH_RESULT2_6);
+ DUMP_REGL(GPMC_BCH_RESULT2_7);
+
+ DUMP_REGL(GPMC_BCH_RESULT3_0);
+ DUMP_REGL(GPMC_BCH_RESULT3_1);
+ DUMP_REGL(GPMC_BCH_RESULT3_2);
+ DUMP_REGL(GPMC_BCH_RESULT3_3);
+ DUMP_REGL(GPMC_BCH_RESULT3_4);
+ DUMP_REGL(GPMC_BCH_RESULT3_5);
+ DUMP_REGL(GPMC_BCH_RESULT3_6);
+ DUMP_REGL(GPMC_BCH_RESULT3_7);
+
+ DUMP_REGL(GPMC_BCH_SWDATA);
+#endif
+}
+#else
+# define omap3_gpmc_register_dump() do { } while (0)
+#endif /* defined(CFG_NAND_DEBUG) */
+
+#if defined(CFG_PRCM_DEBUG)
+static void
+omap3_prcm_register_dump(void)
+{
+ printf("\n PRCM Register Dump:\n");
+
+ DUMP_REGL(PRCM_PRM_CCR_CLKSEL);
+ DUMP_REGL(PRCM_PRM_GR_CLKSRC_CTRL);
+ DUMP_REGL(CM_CLKSEL1_PLL);
+ DUMP_REGL(CM_CLKSEL2_PLL);
+ DUMP_REGL(CM_CLKSEL3_PLL);
+ DUMP_REGL(CM_CLKEN_PLL);
+ DUMP_REGL(CM_CLKSEL1_PLL_MPU);
+ DUMP_REGL(CM_CLKSEL2_PLL_MPU);
+ DUMP_REGL(CM_CLKEN_PLL_MPU);
+ DUMP_REGL(CM_CLKSEL1_PLL_IVA2);
+ DUMP_REGL(CM_CLKSEL2_PLL_IVA2);
+ DUMP_REGL(CM_CLKEN_PLL_IVA2);
+ DUMP_REGL(CM_CLKSEL_CAM);
+ DUMP_REGL(CM_CLKSEL_CORE);
+ DUMP_REGL(CM_CLKSEL_DSS);
+ DUMP_REGL(CM_CLKSEL1_EMU);
+}
+#else
+#define omap3_prcm_register_dump() do { } while (0)
+#endif /* CFG_PRCM_DEBUG */
+
+/*
+ * void config_diamond_sdram()
+ *
+ * Description:
+ * This routine initializes the processor's SDRAM Controller (SDRC)
+ * as appropriate for the Samsung K4X51163PI-FCG6 32 Mb x 16 b (64
+ * MiB) DDR SDRAM on the Nest Learning Thermostat board.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+config_diamond_sdram(void)
+{
+ u32 value, actim_ctrla, actim_ctrlb;
+
+ /*
+ * Step 1: Reset the SDRC controller and then wait for the reset
+ * event to clear.
+ */
+
+ __raw_writel(SDRC_SYSCONFIG_SOFTRESET_SET, SDRC_SYSCONFIG);
+ wait_on_value(SDRC_SYSSTATUS_RESETDONE,
+ SDRC_SYSSTATUS_RESETDONE,
+ SDRC_STATUS,
+ 12000000);
+ __raw_writel(SDRC_SYSCONFIG_SOFTRESET_CLEAR, SDRC_SYSCONFIG);
+
+ /*
+ * Step 2: Setup the position and geometry of the SDRAM device on
+ * the controller's bus.
+ */
+
+ value =
+ (SDRC_SHARING_LOCK_OFF |
+ SDRC_SHARING_CS1MUXCFG_ENCODE(SDRC_SHARING_CS1MUXCFG_16_BIT_16_0) |
+ SDRC_SHARING_CS0MUXCFG_ENCODE(SDRC_SHARING_CS0MUXCFG_16_BIT_16_0) |
+ SDRC_SHARING_SDRCTRISTATE_OFF);
+ __raw_writel(value, SDRC_SHARING);
+
+ /*
+ * Step 3: Setup the memory configuration, including RAS width,
+ * CAS width, address multiplexing, size, bank mapping, bus width,
+ * power mode, DDR type and memory type.
+ */
+
+ value =
+ (SDRC_MCFG_LOCKSTATUS_RW |
+ SDRC_MCFG_RASWIDTH_ENCODE(SDRC_MCFG_RASWIDTH_14_BITS) |
+ SDRC_MCFG_CASWIDTH_ENCODE(SDRC_MCFG_CASWIDTH_10_BITS) |
+ SDRC_MCFG_ADDRMUXLEGACY_FLEXIBLE |
+ SDRC_MCFG_RAMSIZE_ENCODE(CFG_SDRAM_SIZE_MB) |
+ SDRC_MCFG_BANKALLOCATION_ENCODE(SDRC_MCFG_BANKALLOCATION_R_B_C)|
+ SDRC_MCFG_B32NOT16_OFF |
+ SDRC_MCFG_DEEPPD_SUPPORTED |
+ SDRC_MCFG_DDRTYPE_ENCODE(SDRC_MCFG_DDRTYPE_MOBILE_DDR) |
+ SDRC_MCFG_RAMTYPE_ENCODE(SDRC_MCFG_RAMTYPE_DDR));
+ __raw_writel(value, SDRC_MCFG_0);
+
+ /*
+ * Step 4: Establish the AC fine tuning timing characteristics.
+ */
+
+ actim_ctrla
+ = (SDRC_ACTIM_CTRLA_TRFC_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRFC) |
+ SDRC_ACTIM_CTRLA_TRC_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRC) |
+ SDRC_ACTIM_CTRLA_TRAS_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRAS) |
+ SDRC_ACTIM_CTRLA_TRP_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRP) |
+ SDRC_ACTIM_CTRLA_TRCD_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRCD) |
+ SDRC_ACTIM_CTRLA_TRRD_ENCODE(CFG_SDRC_ACTIM_CTRLA_TRRD) |
+ SDRC_ACTIM_CTRLA_TDPL_ENCODE(CFG_SDRC_ACTIM_CTRLA_TDPL) |
+ SDRC_ACTIM_CTRLA_TDAL_ENCODE(CFG_SDRC_ACTIM_CTRLA_TDAL));
+
+ actim_ctrlb
+ = (SDRC_ACTIM_CTRLB_TWTR_ENCODE(CFG_SDRC_ACTIM_CTRLB_TWTR) |
+ SDRC_ACTIM_CTRLB_TCKE_ENCODE(CFG_SDRC_ACTIM_CTRLB_TCKE) |
+ SDRC_ACTIM_CTRLB_TXP_ENCODE(CFG_SDRC_ACTIM_CTRLB_TXP) |
+ SDRC_ACTIM_CTRLB_TXSR_ENCODE(CFG_SDRC_ACTIM_CTRLB_TXSR));
+
+ __raw_writel(actim_ctrla, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(actim_ctrlb, SDRC_ACTIM_CTRLB_0);
+
+ /*
+ * Step 5: Establish the memory autorefresh control
+ */
+
+ value =
+ (SDRC_RFR_CTRL_ARCV_ENCODE(1244) |
+ SDRC_RFR_CTRL_ARE_ENCODE(SDRC_RFR_CTRL_ARE_1_ARCV));
+ __raw_writel(value, SDRC_RFR_CTRL_0);
+
+ value =
+ (SDRC_POWER_REG_WAKEUP_DELAYED |
+ SDRC_POWER_REG_AUTOCOUNT_ENCODE(0) |
+ SDRC_POWER_REG_SRFR_ON_RST_ENABLE |
+ SDRC_POWER_REG_SRFR_ON_IDLE_DISABLE |
+ SDRC_POWER_REG_CLKCTRL_ENCODE(SDRC_POWER_REG_CLKCTRL_NONE) |
+ SDRC_POWER_REG_PAGEPOLICY_HPHB);
+ __raw_writel(value, SDRC_POWER_REG);
+
+ /*
+ * Step 6: Establish the JEDEC-defined mode and DLL parameters.
+ */
+
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+
+ delay(5000);
+
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_PRECHARGE_ALL),
+ SDRC_MANUAL_0);
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+ __raw_writel(SDRC_MANUAL_CMDCODE_ENCODE(SDRC_MANUAL_CMDCODE_AUTOREFRESH),
+ SDRC_MANUAL_0);
+
+ value =
+ (SDRC_MR_ZERO_1 |
+ SDRC_MR_WBST_ENABLE |
+ SDRC_MR_ZERO_0 |
+ SDRC_MR_CASL_ENCODE(SDRC_MR_CASL_3) |
+ SDRC_MR_SIL_SERIAL |
+ SDRC_MR_BL_ENCODE(SDRC_MR_BL_4));
+ __raw_writel(value, SDRC_MR_0);
+
+ value =
+ (SDRC_DLLA_CTRL_FIXED_DELAY_ENCODE(0) |
+ SDRC_DLLA_CTRL_INIT_LAT_ENCODE(0) |
+ SDRC_DLLA_CTRL_MODE_ON_IDLE_ENCODE(SDRC_DLLA_CTRL_MODE_ON_IDLE_PWD) |
+ SDRC_DLLA_CTRL_DLL_ENABLE |
+ SDRC_DLLA_CTRL_LOCK_TRACKINGDELAY);
+ __raw_writel(value, SDRC_DLLA_CTRL);
+
+ /*
+ * Delay for a "reasonably long" period of time to allow the
+ * requested changes to take effect.
+ */
+
+ delay(0x20000);
+}
+
+/*
+ * void s_init()
+ *
+ * Description:
+ * This routine performs very early system initialization of chip
+ * pin multiplexing and clocks and is called when ONLY an
+ * SRAM-based stack is available (i.e. no SDRAM).
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+s_init(void)
+{
+ watchdog_init();
+ try_unlock_memory();
+ set_muxconf_regs();
+
+ delay(100);
+
+ prcm_init();
+ per_clocks_enable();
+ config_diamond_sdram();
+}
+
+/*
+ * int board_init()
+ *
+ * Description:
+ * This routine performs any early, board-specific initialization
+ * following core CPU initialization but prior to serial and NAND
+ * initialization.
+ *
+ * At present, there is nothing board-specific to do.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if OK; otherwise, non-zero on error.
+ *
+ */
+int
+board_init(void)
+{
+ return (0);
+}
+
+/*
+ * u32 get_device_type()
+ *
+ * Description:
+ * This routine returns the decoded value from the CPU's
+ * CONTROL_STATUS register DEVICETYPE field, indicating whether the
+ * device is of TST, EMU, HS or GP type.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The decoded CONTROL_STATUS register DEVICETYPE field.
+ *
+ */
+u32
+get_device_type(void)
+{
+ const int value = __raw_readl(CONTROL_STATUS);
+
+ return (CONTROL_STATUS_DEVICETYPE_DECODE(value));
+}
+
+/*
+ * u32 get_sysboot_value()
+ *
+ * Description:
+ * This routine returns the decoded value from the CPU's
+ * CONTROL_STATUS register SYSBOOT order subfield, indicating the
+ * order of memory interfaces from which the processor will attempt
+ * to boot itself.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The decoded CONTROL_STATUS register SYSBOOT order subfield.
+ *
+ */
+u32
+get_sysboot_value(void)
+{
+#if 0
+ const u32 value = __raw_readl(CONTROL_STATUS);
+ const u32 peripheral_type = CONTROL_STATUS_SYSBOOT_TYPE_PERIPHERAL;
+
+ /*
+ * This routine and callers of it are implicitly expecting the
+ * MEMORY interface (SYSBOOT[5] == 0) not the PERHIPHERAL
+ * interface (SYSBOOT[5] == 1) boot order, so check that is
+ * actually the case.
+ */
+
+ if (CONTROL_STATUS_SYSBOOT_TYPE_DECODE(value) == peripheral_type) {
+ hang();
+ }
+
+ return (CONTROL_STATUS_SYSBOOT_ORDER_DECODE(value));
+#else
+ return __raw_readl(CONTROL_STATUS) & 0x3f;
+#endif
+}
+
+/*
+ * int get_boot_device_list(const u32** device_list)
+ *
+ * Description:
+ * This routine returns a constant list indicating the preferred
+ * device boot list.
+ * It gets called from start_armboot in board.c
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The preferred first processor memory boot interface.
+ *
+ */
+
+int
+get_boot_devices_list(const u32** devices_list)
+{
+ static u32 list[MAX_J49_BOOT_DEVICES];
+ const u32 mem_order = get_sysboot_value();
+
+ // set defaults
+ int number_of_devices = 0;
+ *devices_list = &list[0];
+
+ switch (mem_order) {
+ case 15:
+ list[0] = GPMC_NAND;
+ list[1] = USB_PERIPHERAL;
+ list[2] = MMC_NAND;
+ number_of_devices = MAX_J49_BOOT_DEVICES;
+ break;
+ case 47:
+ list[0] = MMC_NAND;
+ list[1] = GPMC_NAND;
+ list[2] = USB_PERIPHERAL;
+ number_of_devices = MAX_J49_BOOT_DEVICES;
+ break;
+ default:
+ break;
+ }
+ return number_of_devices;
+}
+
+/*
+ * int misc_init_r()
+ *
+ * Description:
+ * This routine performs any miscellaneous, board-specific
+ * initialization following CPU, early board, serial and NAND
+ * initialization but prior to loading the secondary program loader
+ * to RAM.
+ *
+ * At present, there is nothing board-specific to do.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if OK; otherwise, non-zero on error.
+ *
+ */
+int
+misc_init_r(void)
+{
+ return (0);
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+static void
+wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void
+watchdog_init(void)
+{
+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+ sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+ sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+ wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+/*
+ * void foobar()
+ *
+ * Description:
+ * This routine...
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+per_clocks_enable(void)
+{
+ /* Enable GP2 timer. */
+ sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CFG_NS16550
+ /* Enable UART1 clocks */
+ sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+#endif
+
+#ifdef CONFIG_MMC
+ /* Enable MMC1 clocks */
+ sr32(CM_FCLKEN1_CORE, 24, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 24, 1, 0x1);
+#endif
+ delay(1000);
+}
+
+static int
+gpmc_config_0(void)
+{
+#if defined(CFG_GPMC_CONFIG1_0)
+ /*
+ * First, disable the interface and wait.
+ */
+ __raw_writel(GPMC_CONFIG7_CSVALID_DISABLED, GPMC_CONFIG7_0);
+
+ delay(1000);
+
+ /*
+ * Next, program the configuration parameters.
+ */
+ __raw_writel(CFG_GPMC_CONFIG1_0, GPMC_CONFIG1_0);
+ __raw_writel(CFG_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+ __raw_writel(CFG_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+ __raw_writel(CFG_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+ __raw_writel(CFG_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+ __raw_writel(CFG_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+
+ /*
+ * Finally, enable the GPMC mapping and spin for the parameters to
+ * become active.
+ */
+ __raw_writel((CFG_GPMC_CONFIG7_0 | GPMC_CONFIG7_CSVALID_ENABLED),
+ GPMC_CONFIG7_0);
+
+ delay(2000);
+
+ if (nand_chip()){
+ return (1);
+ }
+#endif /* defined(CFG_GPMC_CONFIG1_0) */
+
+ return (0);
+}
+
+/*
+ * int nand_init()
+ *
+ * Description:
+ * This routine initializes the General Purpose Memory Controller
+ * (GPMC) such that on-board NAND devices may be accessed for
+ * second-stage boot.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * 0 if NAND was successfully initialized; otherwise, 1.
+ *
+ */
+int
+nand_init(void)
+{
+ int status = 1;
+
+ /*
+ * Establish GPMC global settings.
+ */
+
+ __raw_writel(GPMC_SYSCONFIG_IDLEMODE_SMART, GPMC_SYSCONFIG);
+
+ __raw_writel(GPMC_IRQENABLE_ALL_DISABLE, GPMC_IRQENABLE);
+
+ __raw_writel(GPMC_TIMEOUTENABLE_OFF, GPMC_TIMEOUT_CONTROL);
+
+ if (gpmc_config_0()) {
+ puts("Unsupported NAND device @ GPMC0!\n");
+ goto done;
+ }
+
+ status = 0;
+
+ done:
+ /* Dump GPMC and SDRC registers if so configured. */
+
+ omap3_sdrc_register_dump();
+ omap3_gpmc_register_dump();
+ omap3_prcm_register_dump();
+
+ return (status);
+}
+
+/*
+ * void board_hang()
+ *
+ * Description:
+ * This routine performs any board-specific actions when the system
+ * hangs by executing hang(). At present, there is nothing to do;
+ * however, we might later drive the piezo or a LED.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+board_hang (void)
+{
+ return;
+}
diff --git a/x-loader/board/nest/j49/mux.c b/x-loader/board/nest/j49/mux.c
new file mode 100644
index 0000000..b8c7df0
--- /dev/null
+++ b/x-loader/board/nest/j49/mux.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703CUS, focusing
+ * primarily I/O pad multiplexer configuration.
+ *
+ * This is originally inherited and split from the OMAP3 EVM
+ * board file.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+
+#include "platform.h"
+
+/*
+ * void set_muxconf_regs()
+ *
+ * Description:
+ * This routines sets the I/O pad multiplexers for UART, GPMC, SDRC,
+ * GPIO.
+ *
+ * The commented string gives the final mux configuration for that pin
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ */
+void
+set_muxconf_regs(void)
+{
+ /*
+ * The bit fields for these settings are as follows:
+ *
+ * I{EN,DIS} - Input Enable/Disable
+ * PT[DU] - Pull-down, -up
+ * DIS,EN - Pull-down, -up disabled/enabled
+ * M[01234567] - Configuration mode 0-7
+ */
+
+ /*
+ * SDRAM Controller (SDRC)
+ *
+ * Most of the SDRC signals are used to drive the Samsung
+ * K4X51163PI-FCG6 512 Mb x 16-bit (64 MiB) DDR SDRAM. Because we
+ * interface in 16-bit rather than 32-bit mode, we place the
+ * unused pins in safe mode (Mode 7).
+ */
+
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); // SDRC_D0
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); // SDRC_D1
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); // SDRC_D2
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); // SDRC_D3
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); // SDRC_D4
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); // SDRC_D5
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); // SDRC_D6
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); // SDRC_D7
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); // SDRC_D8
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); // SDRC_D9
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); // SDRC_D10
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); // SDRC_D11
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); // SDRC_D12
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); // SDRC_D13
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); // SDRC_D14
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); // SDRC_D15
+
+ // Because we interface SDRAM in 16-bit mode, place
+ // SDRC_DATA[31:16] in safe mode (Mode 7).
+
+ MUX_VAL(CP(SDRC_D16), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D17), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D18), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D19), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D20), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D21), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D22), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D23), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D24), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D25), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D26), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D27), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D28), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D29), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D30), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_D31), (IDIS | PTD | DIS | M7)); // Unused
+
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); // SDRC_CLK
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); // SDRC_DQS0
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); // SDRC_DQS1
+
+ // Place unused DQ pins in safe mode (Mode 7).
+
+ MUX_VAL(CP(SDRC_DQS2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(SDRC_DQS3), (IDIS | PTD | DIS | M7)); // Unused
+
+ /*
+ * General Purpose Memory Controller (GPMC)
+ *
+ */
+
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); // GPMC_A1
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); // GPMC_A2
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); // GPMC_A3
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); // GPMC_A4
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); // GPMC_A5
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); // GPMC_A6
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); // GPMC_A7
+
+ // Place the unused GPMC_A8 pin in safe mode (Mode 7).
+
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M7)); // Unused
+
+ // Assign GPMC_A9 to GPIO_42 used as a push-pull, active low input
+ // from the USB PHY for USB suspend notification.
+
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M7)); // GPIO_42
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M7)); // Unused
+
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); // GPMC_D0
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); // GPMC_D1
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); // GPMC_D2
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); // GPMC_D3
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); // GPMC_D4
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); // GPMC_D5
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); // GPMC_D6
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); // GPMC_D7
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); // GPMC_D8
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); // GPMC_D9
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); // GPMC_D10
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); // GPMC_D11
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); // GPMC_D12
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); // GPMC_D13
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); // GPMC_D14
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); // GPMC_D15
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); // GPMC_nCS0
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); // GPMC_nCS1
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); // GPMC_nCS2
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)); // Unused
+
+ // Assign GPMC_NCS6 to GPT11_PWM_EVT used as a push-pull pulse width
+ // modulated (PWM) signal for the piezo.
+
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M3)); // GPT11_PWM_EVT
+
+ // Assign GPMC_NCS7 to GPIO_58 used as a push-pull output
+ // PIEZO_NENABLE to the TI SN74LVC2G240 Dual Buffer/Driver With
+ // 3-State Outputs inputs.
+
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M4)); // GPIO_58
+
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)); // GPMC_CLK
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); // GPMC_nADV_ALE
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); // GPMC_nOE
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); // GPMC_nWE
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); // GPMC_nBE0_CLE
+
+ // Assign GPMC_NBE1 to GPIO_61 used as a push-pull output to the
+ // ZigBee active-low reset.
+
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); // GPIO_61
+
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); // GPMC_nWP
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); // GPMC_WAIT0
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); // GPMC_WAIT1
+ MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTD | DIS | M7)); // Unavailable
+
+ // Assign GPMC_WAIT3 to GPIO_65 used as an active-high, push-pull
+ // backplate detect input.
+
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | DIS | M4)); // GPIO_65
+
+ /*
+ * Display Subsystem (DSS)
+ *
+ * All DSS signals are used in their normal, default mode (Mode 0)
+ * to drive the Samsung LMS350DF0[13] LCD display panel.
+ */
+
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); // DSS_PCLK
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); // DSS_HSYNC
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); // DSS_VSYNC
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); // DSS_ACBIAS
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); // DSS_DATA0
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); // DSS_DATA1
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); // DSS_DATA2
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); // DSS_DATA3
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); // DSS_DATA4
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); // DSS_DATA5
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); // DSS_DATA6
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); // DSS_DATA7
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); // DSS_DATA8
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); // DSS_DATA9
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); // DSS_DATA10
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); // DSS_DATA11
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); // DSS_DATA12
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); // DSS_DATA13
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); // DSS_DATA14
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); // DSS_DATA15
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); // DSS_DATA16
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); // DSS_DATA17
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); // DSS_DATA18
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); // DSS_DATA19
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); // DSS_DATA20
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); // DSS_DATA21
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); // DSS_DATA22
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); // DSS_DATA23
+
+ MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M7)); // Unused
+
+ /*
+ * Universal Asynchronous Receiver / Transmitter (UART)
+ *
+ */
+
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); // UART1_TX
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M7)); // UART1_RTS
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M7)); // UART1_CTS
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); // UART1_RX
+ /*
+ * Control and Debug
+ *
+ */
+
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); // SYS_32K
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M0)); // SYS_BOOT0
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0)); // SYS_BOOT1
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)); // SYS_BOOT2
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0)); // SYS_BOOT3
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0)); // SYS_BOOT4
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0)); // SYS_BOOT5
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M0)); // SYS_BOOT6
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTU | EN | M0)); // SYS_CLKOUT1
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); // JTAG_nTRST
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); // JTAG_TCK
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); // JTAG_TMS
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); // JTAG_TDI
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); // JTAG_EMU0
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); // JTAG_EMU1
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D8_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D12_ES2), (IDIS | PTD | DIS | M7)); // Unused
+ MUX_VAL(CP(ETK_D13_ES2), (IDIS | PTD | DIS | M7)); // Unused
+
+ // Assign ETK_D1[45] as MM2_RXRCV and MM2_TXSE0 USB FS/LS Host
+ // (Mode 5)
+
+ MUX_VAL(CP(ETK_D14_ES2), (IDIS | PTD | DIS | M7)); // MM2_RXRCV
+ MUX_VAL(CP(ETK_D15_ES2), (IDIS | PTD | DIS | M7)); // MM2_TXSE0
+}
diff --git a/x-loader/board/nest/j49/platform.S b/x-loader/board/nest/j49/platform.S
new file mode 100644
index 0000000..0549d27
--- /dev/null
+++ b/x-loader/board/nest/j49/platform.S
@@ -0,0 +1,557 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific setup for the Nest Learning
+ * Thermostat board.
+ *
+ * It inherits entirely from the equivalent TI OMAP3 EVM
+ * file.
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * NOTE: 3430 X-loader currently does not use this code.
+* It could be removed its is kept for compatabily with u-boot.
+ *
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ * confused. A reset of the controller gets it back. Taking away its
+ * L3 when its not in self refresh seems bad for it. Normally, this code
+ * runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4-r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4-r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG1_0)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG3_0)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG4_0)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG5_0)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+#endif /* !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) */
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE
+.word 0x07
+.word 0x05
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x1F4
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179
+.word 0x12
+.word 0x04
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D
+.word 0x19
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA
+.word 0x32
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x2F
+.word 0x03
+.word 0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D
+.word 0x05
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x168
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082
+.word 0x09
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x0B
+.word 0x06
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D
+.word 0x0C
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F
+.word 0x30
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x17
+.word 0x06
+.word 0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x19F
+.word 0x0E
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x10
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x14C
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x21
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8
+.word 0x05
+.word 0x07
+.word 0x09
+
+/* 13MHz */
+.word 0x1B0
+.word 0x0C
+.word 0x03
+.word 0x09
+
+/* 19.2MHz */
+.word 0xE1
+.word 0x09
+.word 0x07
+.word 0x09
+
+/* 26MHz */
+.word 0xD8
+.word 0x0C
+.word 0x07
+.word 0x09
+
+/* 38.4MHz */
+.word 0xE1
+.word 0x13
+.word 0x07
+.word 0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
+
+/*
+ * Tables for 36x/37x devices
+ *
+ * (Populated for 13MHz only)
+ */
+mpu_36x_dpll_param:
+// M N FS M2
+#if defined(CONFIG_SYS_MPU_DPLL_300MHZ)
+.word 150, 5, 0, 1 // 12 MHz
+.word 300, 12, 0, 1 // 13 MHz
+.word 125, 7, 0, 1 // 19.2 MHz
+.word 150, 12, 0, 1 // 26 MHz
+.word 125, 15, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_MPU_DPLL_600MHZ)
+.word 300, 5, 0, 1 // 12 MHz
+.word 600, 12, 0, 1 // 13 MHz
+.word 125, 3, 0, 1 // 19.2 MHz
+.word 300, 12, 0, 1 // 26 MHz
+.word 125, 7, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#else
+# error "MPU DPLL settings are not defined!"
+#endif /* defined(CONFIG_SYS_MPU_DPLL_600MHZ) */
+
+iva_36x_dpll_param:
+// M N FS M2
+.word 10, 0, 0, 1 // 12 MHz
+.word 10, 0, 0, 1 // 13 MHz
+.word 10, 0, 0, 1 // 19.2 MHz
+.word 10, 0, 0, 1 // 26 MHz
+.word 10, 0, 0, 1 // 38.4 MHz
+.word 10, 0, 0, 1 // 16.8 MHz
+
+core_36x_dpll_param:
+// M N FS M2
+#if defined(CONFIG_SYS_CORE_DPLL_200MHZ)
+.word 100, 5, 0, 1 // 12 MHz
+.word 200, 12, 0, 1 // 13 MHz
+.word 375, 35, 0, 1 // 19.2 MHz
+.word 100, 12, 0, 1 // 26 MHz
+.word 375, 71, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_CORE_DPLL_332MHZ)
+.word 166, 5, 0, 1 // 12 MHz
+.word 332, 12, 0, 1 // 13 MHz
+.word 415, 23, 0, 1 // 19.2 MHz
+.word 166, 12, 0, 1 // 26 MHz
+.word 415, 47, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#elif defined(CONFIG_SYS_CORE_DPLL_400MHZ)
+.word 200, 5, 0, 1 // 12 MHz
+.word 400, 12, 0, 1 // 13 MHz
+.word 375, 17, 0, 1 // 19.2 MHz
+.word 200, 12, 0, 1 // 26 MHz
+.word 375, 35, 0, 1 // 38.4 MHz
+.word 0, 0, 0, 1 // 16.8 MHz - TBD
+#else
+# error "Core DPLL settings are not defined!"
+#endif /* defined(CONFIG_SYS_CORE_DPLL_400MHZ) */
+
+/*
+ * For the peripheral (PER) (aka DPLL4) clock settings, there are only
+ * effectively two clock choices, 96 MHz or 192 MHz. However, the only
+ * time 192 MHz is apt to be used in an application is if both SGX and
+ * TV output are used.
+ *
+ * For any given system clock, the dividers are configured thus (per
+ * Section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" of the OMAP3 TRM):
+ *
+ * PER[clkout] = (SYS[clkout] * M) / (N + 1)
+ *
+ * M2[clkout]: PER[clkout] / M2 used by UART, MMC, I2C, etc.
+ * M3[clkout]: PER[clkout] / M3 used by TV out.
+ * M4[clkout]: PER[clkout] / M4 used by DSS.
+ * M5[clkout]: PER[clkout] / M5 used by camera.
+ * M6[clkout]: PER[clkout] / M6 used by emulation.
+ *
+ * So, for a 19.2 MHz system clock and the scalar entries below:
+ *
+ * PER[clkout] = (19.2 * 540) / (11 + 1) = 864
+ *
+ * M2[clkout]: 864 / 9 = 96 MHz
+ * M3[clkout]: 864 / 16 = 54 MHz
+ * M4[clkout]: 864 / 5 = 172.8 MHz
+ * M5[clkout]: 864 / 4 = 216 MHz
+ * M6[clkout]: 864 / 3 = 288 MHz
+ */
+per_36x_dpll_param:
+// SYS_CLK M N M2 M3 M4 M5 M6 m2DIV
+.word 12000, 432, 5, 9, 16, 9, 4, 3, 1 // 12 MHz
+.word 13000, 864, 12, 9, 16, 9, 4, 3, 1 // 13 MHz
+.word 19200, 540, 11, 9, 16, 9, 4, 3, 1 // 19.2 MHz
+.word 26000, 432, 12, 9, 16, 9, 4, 3, 1 // 26 MHz
+.word 38400, 270, 11, 9, 16, 9, 4, 3, 1 // 38.4 MHz
+.word 16800, 360, 6, 9, 16, 9, 4, 3, 1 // 16.8 MHz
+
+.globl get_36x_mpu_dpll_param
+get_36x_mpu_dpll_param:
+ adr r0, mpu_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_iva_dpll_param
+get_36x_iva_dpll_param:
+ adr r0, iva_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_core_dpll_param
+get_36x_core_dpll_param:
+ adr r0, core_36x_dpll_param
+ mov pc, lr
+
+.globl get_36x_per_dpll_param
+get_36x_per_dpll_param:
+ adr r0, per_36x_dpll_param
+ mov pc, lr
diff --git a/x-loader/board/nest/j49/platform.h b/x-loader/board/nest/j49/platform.h
new file mode 100644
index 0000000..8f8c12d
--- /dev/null
+++ b/x-loader/board/nest/j49/platform.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file defines data structures and function prototypes for
+ * accessing Digital Phased Lock Loop (DPLL) parameters and
+ * settings.
+ *
+ */
+
+#ifndef _NEST_J49_PLATFORM_H_
+#define _NEST_J49_PLATFORM_H_
+
+#include <asm/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*
+ * Type Definitions
+ */
+
+/* Used to index into DPLL parameter tables */
+
+struct dpll_param {
+ u32 m;
+ u32 n;
+ u32 fsel;
+ u32 m2;
+};
+
+struct dpll_per_36x_param {
+ u32 sys_clk;
+ u32 m;
+ u32 n;
+ u32 m2;
+ u32 m3;
+ u32 m4;
+ u32 m5;
+ u32 m6;
+ u32 m2div;
+};
+
+typedef struct dpll_param dpll_param;
+
+/*
+ * Inline Functions
+ */
+static inline void
+delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+
+/*
+ * Function Prototypes
+ *
+ * The following functions are exported from platform.S.
+ */
+
+extern dpll_param * get_mpu_dpll_param(void);
+extern dpll_param * get_iva_dpll_param(void);
+extern dpll_param * get_core_dpll_param(void);
+extern dpll_param * get_per_dpll_param(void);
+
+extern dpll_param * get_36x_mpu_dpll_param(void);
+extern dpll_param * get_36x_iva_dpll_param(void);
+extern dpll_param * get_36x_core_dpll_param(void);
+extern dpll_param * get_36x_per_dpll_param(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _NEST_J49_PLATFORM_H_ */
diff --git a/x-loader/board/nest/j49/prcm.c b/x-loader/board/nest/j49/prcm.c
new file mode 100644
index 0000000..5625ad7
--- /dev/null
+++ b/x-loader/board/nest/j49/prcm.c
@@ -0,0 +1,565 @@
+/*
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this program; if not, write to the Free
+ * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description:
+ * This file is the board-specific set-up for the Nest Learning
+ * Thermostat board, based on the TI OMAP3 AM3703CUS, focusing
+ * primarily clock set-up for the processor's Power, Reset and
+ * Clock Manager (PRCM)
+ *
+ * This is originally inherited and split from the OMAP3 EVM
+ * board file.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+
+#include "platform.h"
+
+/*
+ * u32 get_osc_clk_speed()
+ *
+ * Description:
+ * This routine determines the reference oscillator speed based on
+ * a known 32 kHz clock and general purpose timer.
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * The reference oscillator clock speed.
+ *
+ */
+static u32
+get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, cdiv, val;
+
+ val = __raw_readl(PRM_CLKSRC_CTRL);
+
+ if (val & BIT7)
+ cdiv = 2;
+ else if (val & BIT6)
+ cdiv = 1;
+ else
+ /*
+ * Should never reach here!
+ * TBD: Add a WARN()/BUG()
+ * For now, assume divider as 1.
+ */
+ cdiv = 1;
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
+
+ /* Enable I and F Clocks for GPT1 */
+ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+ __raw_writel(val, CM_ICLKEN_WKUP);
+ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
+ __raw_writel(val, CM_FCLKEN_WKUP);
+
+ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
+ /* enable 32kHz source *//* enabled out of reset */
+ /* determine sys_clk via gauging */
+
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
+ while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
+ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
+ while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
+ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+
+ if (cdiv == 2)
+ {
+ cdiff *= 2;
+ }
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return (S38_4M);
+ else if (cdiff > 15200)
+ return (S26M);
+ else if (cdiff > 13000)
+ return (S24M);
+ else if (cdiff > 9000)
+ return (S19_2M);
+ else if (cdiff > 7600)
+ return (S13M);
+ else
+ return (S12M);
+}
+
+/*
+ * void get_sys_clkin_sel()
+ *
+ * Description:
+ * This routine sets the value for the PRCM PRM system clock
+ * frequency selector, which should be written to PRM_CLKSEL.
+ *
+ * Input(s):
+ * hertz - The speed, in MHz, that the system clock is believed
+ * to be running at.
+ * sys_clkin_sel - A pointer to storage for the index used to access the
+ * digital PLL settings.
+ *
+ * Output(s):
+ * sys_clkin_sel - A pointer to the index for the digital PLL settings
+ * appropriate for the specified system clock rate.
+ *
+ * Returns:
+ * N/A
+ *
+ */
+static void
+get_sys_clkin_sel(u32 hertz, u32 *sys_clkin_sel)
+{
+ switch (hertz) {
+
+ case S38_4M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_38_4_MHZ;
+ break;
+
+ case S26M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_26_0_MHZ;
+ break;
+
+ case S19_2M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_19_2_MHZ;
+ break;
+
+ case S16_8M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_16_8_MHZ;
+ break;
+
+ case S13M:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_13_0_MHZ;
+ break;
+
+ case S12M:
+ default:
+ *sys_clkin_sel = PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_12_0_MHZ;
+ break;
+
+ }
+}
+
+/*
+ * OMAP34x/35x specific functions
+ */
+static void
+dpll3_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address of Core DPLL param table*/
+ ptr = (dpll_param *)get_core_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* CORE DPLL */
+ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(CM_CLKSEL1_PLL, 27, 5, ptr->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(CM_CLKSEL1_PLL, 16, 11, ptr->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(CM_CLKSEL1_PLL, 8, 7, ptr->n);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0);
+
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV_34X); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(CM_CLKEN_PLL, 4, 4, ptr->fsel);
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+dpll4_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ ptr = (dpll_param *)get_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr = ptr + clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ sr32(CM_CLKSEL3_PLL, 0, 5, ptr->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
+ sr32(CM_CLKSEL2_PLL, 8, 11, ptr->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(CM_CLKSEL2_PLL, 0, 7, ptr->n);
+
+ /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
+ sr32(CM_CLKEN_PLL, 20, 4, ptr->fsel);
+
+ /* LOCK MODE (EN_PERIPH_DPLL) : CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+mpu_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to MPU DPLL param table*/
+ ptr = (dpll_param *)get_mpu_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, ptr->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, ptr->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, ptr->n);
+
+ /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
+ sr32(CM_CLKEN_PLL_MPU, 4, 4, ptr->fsel);
+}
+
+static void
+iva_init_34xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to IVA DPLL param table*/
+ ptr = (dpll_param *)get_iva_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + 2*clk_index + sil_index;
+
+ /* IVA DPLL */
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, ptr->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, ptr->n);
+
+ /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
+ sr32(CM_CLKEN_PLL_IVA2, 4, 4, ptr->fsel);
+
+ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);
+
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+}
+
+/*
+ * OMAP3630 specific functions
+ */
+static void
+dpll3_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address of Core DPLL param table*/
+ ptr = (dpll_param *)get_36x_core_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr += clk_index;
+
+ /* CORE DPLL */
+ /* Select relock bypass: CM_CLKEN_PLL[0:2] */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* CM_CLKSEL1_EMU[DIV_DPLL3] */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);
+
+ /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
+ sr32(CM_CLKSEL1_PLL, 27, 5, ptr->m2);
+
+ /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
+ sr32(CM_CLKSEL1_PLL, 16, 11, ptr->m);
+
+ /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
+ sr32(CM_CLKSEL1_PLL, 8, 7, ptr->n);
+
+ /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0);
+
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV_36X); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+
+ /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
+ sr32(CM_CLKEN_PLL, 4, 4, ptr->fsel);
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+dpll4_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct dpll_per_36x_param *ptr;
+
+ ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr += clk_index;
+
+ /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
+ sr32(CM_CLKSEL1_EMU, 24, 6, ptr->m6);
+
+ /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
+ sr32(CM_CLKSEL_CAM, 0, 6, ptr->m5);
+
+ /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
+ sr32(CM_CLKSEL_DSS, 0, 6, ptr->m4);
+
+ /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
+ sr32(CM_CLKSEL_DSS, 8, 6, ptr->m3);
+
+ /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
+ sr32(CM_CLKSEL3_PLL, 0, 5, ptr->m2);
+
+ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
+ sr32(CM_CLKSEL2_PLL, 8, 12, ptr->m);
+
+ /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
+ sr32(CM_CLKSEL2_PLL, 0, 7, ptr->n);
+
+ /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
+ sr32(CM_CLKSEL_CORE, 12, 2, ptr->m2div);
+
+ /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+}
+
+static void
+mpu_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to MPU DPLL param table*/
+ ptr = (dpll_param *)get_36x_mpu_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + (2*clk_index) + sil_index;
+
+ /* MPU DPLL (unlocked already) */
+ /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, ptr->m2);
+
+ /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, ptr->m);
+
+ /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, ptr->n);
+
+ /* LOCK MODE (EN_MPU_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+}
+
+static void
+iva_init_36xx(u32 sil_index, u32 clk_index)
+{
+ dpll_param *ptr;
+
+ /* Getting the base address to IVA DPLL param table*/
+ ptr = (dpll_param *)get_36x_iva_dpll_param();
+
+ /* Moving it to the right sysclk and ES rev base */
+ ptr = ptr + (2*clk_index) + sil_index;
+
+ /* IVA DPLL */
+ /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, ptr->m2);
+
+ /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, ptr->m);
+
+ /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, ptr->n);
+
+ /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);
+
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+}
+
+/*
+ * void prcm_init()
+ *
+ * Description:
+ * This routine initializes clocks in a board-specific manner for
+ * the processor's Power, Reset and Clock Manager (PRCM) and is
+ * called only when an SRAM-based stack is available (i.e. no
+ * SDRAM).
+ *
+ * Input(s):
+ * N/A
+ *
+ * Output(s):
+ * N/A
+ *
+ * Returns:
+ * N/A
+ *
+ */
+void
+prcm_init(void)
+{
+ u32 sys_clk_rate = 0, sys_clkin_sel, sys_clk_div;
+ u32 clk_index, sil_index;
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ sys_clk_rate = get_osc_clk_speed();
+ get_sys_clkin_sel(sys_clk_rate, &sys_clkin_sel);
+
+ /* Set the PRM_CLKSEL_SYS_CLKIN_SEL value in the processor. */
+
+ sr32(PRCM_PRM_CCR_CLKSEL,
+ PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_START,
+ PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_BITS,
+ sys_clkin_sel);
+
+ /* If the input clock is greater than 19.2M always divide by two.
+ *
+ * On OMAP3630, DDR data corruption has been observed on OFF mode
+ * exit if the sys clock was lower than 26M. As a work around,
+ * OMAP3630 is operated at 26M sys clock and this internal division
+ * is not performed.
+ */
+
+ if((is_cpu_family() != CPU_OMAP36XX) &&
+ (sys_clkin_sel > PRCM_PRM_CCR_CLKSEL_SYS_CLKIN_SEL_19_2_MHZ)) {
+ sys_clk_div = PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BY_2;
+ clk_index = sys_clkin_sel / 2;
+
+ } else {
+ sys_clk_div = PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BY_1;
+ clk_index = sys_clkin_sel / 1;
+
+ }
+
+ sr32(PRCM_PRM_GR_CLKSRC_CTRL,
+ PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_START,
+ PRCM_PRM_GR_CLKSRC_CTRL_SYSCLKDIV_BITS,
+ sys_clk_div);
+
+ if (is_cpu_family() == CPU_OMAP36XX) {
+ dpll3_init_36xx(0, clk_index);
+ dpll4_init_36xx(0, clk_index);
+ mpu_init_36xx(0, clk_index);
+ iva_init_36xx(0, clk_index);
+
+ } else {
+ sil_index = get_cpu_rev() - 1;
+
+ /* The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+ dpll3_init_34xx(sil_index, clk_index);
+ dpll4_init_34xx(sil_index, clk_index);
+ iva_init_34xx(sil_index, clk_index);
+ mpu_init_34xx(sil_index, clk_index);
+
+ /* Lock MPU DPLL to set frequency */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+ }
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+ sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+ delay(5000);
+}
diff --git a/x-loader/board/nest/j49/x-load.lds b/x-loader/board/nest/j49/x-load.lds
new file mode 100644
index 0000000..e0603a2
--- /dev/null
+++ b/x-loader/board/nest/j49/x-load.lds
@@ -0,0 +1,65 @@
+/*
+ *
+ * Copyright (c) 2010-2011 Nest Labs, Inc.
+ * All rights reserved.
+ *
+ * Description:
+ * This file is the X-Loader linker scatter file for the Nest
+ * Learning Thermostat board.
+ *
+ */
+
+/*
+ * November 2006 - Changed to support 3430sdp device
+ * Copyright (c) 2004-2006 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/omap3/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/omap1710h3/Makefile b/x-loader/board/omap1710h3/Makefile
new file mode 100644
index 0000000..f4020af
--- /dev/null
+++ b/x-loader/board/omap1710h3/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+OBJS := omap1710h3.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/omap1710h3/config.mk b/x-loader/board/omap1710h3/config.mk
new file mode 100644
index 0000000..d9e3c76
--- /dev/null
+++ b/x-loader/board/omap1710h3/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+# Kshitij Gupta <Kshitij@ti.com>
+#
+# TI H3 board with OMAP1710 (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Innovator has 1 bank of 256 MB SDRAM
+# Physical Address:
+# 1000'0000 to 2000'0000
+#
+#
+# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
+# (mem base + reserved)
+#
+# we load ourself to 1108'0000
+#
+#
+
+PLATFORM_LDFLAGS += -no-warn-mismatch
+TEXT_BASE = 0x11080000
diff --git a/x-loader/board/omap1710h3/omap1710h3.c b/x-loader/board/omap1710h3/omap1710h3.c
new file mode 100644
index 0000000..245cfe2
--- /dev/null
+++ b/x-loader/board/omap1710h3/omap1710h3.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_OMAP1710)
+#include <./configs/omap1510.h>
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+int board_init (void)
+{
+#ifdef CFG_PRINTF
+
+ /* setup for UART1 */
+ *(volatile unsigned int *) ((unsigned int)FUNC_MUX_CTRL_0) &= ~(0x02000000); /* bit 25 */
+ /* bit 29 for UART1 */
+ *(volatile unsigned int *) ((unsigned int)MOD_CONF_CTRL_0) &= ~(0x00002000);
+
+ /* Enable the power for UART1 */
+#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
+#define SW_CLOCK_REQUEST 0xFFFE0834
+ *((volatile unsigned short *)SW_CLOCK_REQUEST) |= UART1_48MHZ_ENABLE;
+
+#endif
+
+ *(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0) = COMP_MODE_ENABLE;
+ return 0;
+}
+
+#define GPIO1_DIRECTION 0xFFFBE434
+#define FUNC_MUX_CTRL_F 0xFFFE1094
+#define PU_PD_SEL_4 0xFFFE10C4
+/*
+ * On H3 board, Nand R/B is tied to GPIO_10
+ * We setup this GPIO pin
+ */
+int nand_init (void)
+{
+
+ /* GPIO_10 for input. it is in GPIO1 module */
+ *(volatile unsigned int *) ((unsigned int)GPIO1_DIRECTION) |= 0x0400;
+
+ /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
+ *(volatile unsigned int *) ((unsigned int)FUNC_MUX_CTRL_F) &= 0xC7FFFFFF;
+ *(volatile unsigned int *) ((unsigned int)FUNC_MUX_CTRL_F) |= 0x08000000;
+
+ /* GPIO10 pullup/down register, Enable pullup on GPIO10 */
+ *(volatile unsigned int *) ((unsigned int)PU_PD_SEL_4) |= 0x08;
+
+ if (nand_chip()){
+ printf("Unsupported Chip!\n");
+ return 1;
+ }
+ return 0;
+}
+
+/* optionally do something like blinking LED */
+void board_hang (void)
+{}
+
diff --git a/x-loader/board/omap1710h3/platform.S b/x-loader/board/omap1710h3/platform.S
new file mode 100644
index 0000000..ef64e3e
--- /dev/null
+++ b/x-loader/board/omap1710h3/platform.S
@@ -0,0 +1,410 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#if defined(CONFIG_OMAP1710)
+#include <./configs/omap1510.h>
+#endif
+
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+.globl platformsetup
+platformsetup:
+
+
+ /*------------------------------------------------------*
+ * Set up ARM CLM registers (IDLECT1) *
+ *------------------------------------------------------*/
+ ldr r0, REG_ARM_IDLECT1
+ ldr r1, VAL_ARM_IDLECT1
+ str r1, [r0]
+
+ /*------------------------------------------------------*
+ * Set up ARM CLM registers (IDLECT2) *
+ *------------------------------------------------------*/
+ ldr r0, REG_ARM_IDLECT2
+ ldr r1, VAL_ARM_IDLECT2
+ str r1, [r0]
+
+ /*------------------------------------------------------*
+ * Set up ARM CLM registers (IDLECT3) *
+ *------------------------------------------------------*/
+ ldr r0, REG_ARM_IDLECT3
+ ldr r1, VAL_ARM_IDLECT3
+ str r1, [r0]
+
+
+ mov r1, #0x05 /* PER_EN bit */
+ ldr r0, REG_ARM_RSTCT2
+ strh r1, [r0] /* CLKM; Peripheral reset. */
+
+ /* Set CLKM to Sync-Scalable */
+ /* I supposedly need to enable the dsp clock before switching */
+ ldr r1, VAL_ARM_SYSST
+ ldr r0, REG_ARM_SYSST
+ strh r1, [r0]
+ mov r0, #0x400
+1:
+ subs r0, r0, #0x1 /* wait for any bubbles to finish */
+ bne 1b
+ ldr r1, VAL_ARM_CKCTL
+ ldr r0, REG_ARM_CKCTL
+ strh r1, [r0]
+
+ /* a few nops to let settle */
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ /* setup DPLL 1 */
+ /* Ramp up the clock to 96Mhz */
+ ldr r1, VAL_DPLL1_CTL
+ ldr r0, REG_DPLL1_CTL
+ strh r1, [r0]
+ ands r1, r1, #0x10 /* Check if PLL is enabled. */
+ beq lock_end /* Do not look for lock if BYPASS selected */
+2:
+ ldrh r1, [r0]
+ ands r1, r1, #0x01 /* Check the LOCK bit.*/
+ beq 2b /* loop until bit goes hi. */
+lock_end:
+
+
+ /*------------------------------------------------------*
+ * Turn off the watchdog during init... *
+ *------------------------------------------------------*/
+ ldr r0, REG_WATCHDOG
+ ldr r1, WATCHDOG_VAL1
+ str r1, [r0]
+ ldr r1, WATCHDOG_VAL2
+ str r1, [r0]
+ ldr r0, REG_WSPRDOG
+ ldr r1, WSPRDOG_VAL1
+ str r1, [r0]
+ ldr r0, REG_WWPSDOG
+
+watch1Wait:
+ ldr r1, [r0]
+ tst r1, #0x10
+ bne watch1Wait
+
+ ldr r0, REG_WSPRDOG
+ ldr r1, WSPRDOG_VAL2
+ str r1, [r0]
+ ldr r0, REG_WWPSDOG
+watch2Wait:
+ ldr r1, [r0]
+ tst r1, #0x10
+ bne watch2Wait
+
+
+ /* Set memory timings corresponding to the new clock speed */
+
+ /*
+ * Delay for SDRAM initialization.
+ */
+ mov r3, #0x1800 /* value should be checked */
+3:
+ subs r3, r3, #0x1 /* Decrement count */
+ bne 3b
+
+
+ /*
+ * Set SDRAM control values. Disable refresh before MRS command.
+ */
+
+ /* mobile ddr operation */
+ ldr r0, REG_SDRAM_OPERATION
+ mov r2, #07
+ str r2, [r0]
+
+ /* config register */
+ ldr r0, REG_SDRAM_CONFIG
+ ldr r1, SDRAM_CONFIG_VAL
+ str r1, [r0]
+
+ /* manual command register */
+ ldr r0, REG_SDRAM_MANUAL_CMD
+ /* issue set cke high */
+ mov r1, #CMD_SDRAM_CKE_SET_HIGH
+ str r1, [r0]
+ /* issue nop */
+ mov r1, #CMD_SDRAM_NOP
+ str r1, [r0]
+
+ mov r2, #0x0100
+waitMDDR1:
+ subs r2, r2, #1
+ bne waitMDDR1 /* delay loop */
+
+ /* issue precharge */
+ mov r1, #CMD_SDRAM_PRECHARGE
+ str r1, [r0]
+
+
+ /* issue autorefresh x 2 */
+ mov r1, #CMD_SDRAM_AUTOREFRESH
+ str r1, [r0]
+ str r1, [r0]
+
+ /* mrs register ddr mobile */
+ ldr r0, REG_SDRAM_MRS
+ mov r1, #0x33
+ str r1, [r0]
+
+ /* emrs1 low-power register */
+ ldr r0, REG_SDRAM_EMRS1
+ /* self refresh on all banks */
+ mov r1, #0
+ str r1, [r0]
+
+ ldr r0, REG_DLL_URD_CONTROL
+ ldr r1, DLL_URD_CONTROL_VAL
+ str r1, [r0]
+
+ ldr r0, REG_DLL_LRD_CONTROL
+ ldr r1, DLL_LRD_CONTROL_VAL
+ str r1, [r0]
+
+ ldr r0, REG_DLL_WRT_CONTROL
+ ldr r1, DLL_WRT_CONTROL_VAL
+ str r1, [r0]
+
+ /* delay loop */
+ mov r2, #0x0100
+waitMDDR2:
+ subs r2, r2, #1
+ bne waitMDDR2
+
+ /*
+ * Delay for SDRAM initialization.
+ */
+ mov r3, #0x1800
+4:
+ subs r3, r3, #1 /* Decrement count. */
+ bne 4b
+ b common_tc
+
+skip_sdram:
+
+ ldr r0, REG_SDRAM_CONFIG
+ ldr r1, SDRAM_CONFIG_VAL
+ str r1, [r0]
+
+ /* Enable EMIFF TC Doubler in OMAP1710 */
+ ldr r0, REG_EMIFF_DOUBLER
+ mov r0, #0x1;
+
+common_tc:
+ /* slow interface */
+ ldr r1, VAL_TC_EMIFS_CONFIG
+ ldr r0, REG_TC_EMIFS_CONFIG
+ str r1, [r0]
+
+#ifdef CFG_BOOT_CS0
+ /* Chip Select 3 for NAND*/
+ ldr r1, VAL_TC_EMIFS_CS3_CONFIG
+ ldr r0, REG_TC_EMIFS_CS3_CONFIG
+ str r1, [r0]
+#else
+ /* Chip Select 2 for NAND*/
+ ldr r1, VAL_TC_EMIFS_CS2_CONFIG
+ ldr r0, REG_TC_EMIFS_CS2_CONFIG
+ str r1, [r0]
+#endif
+
+ /* Start MPU Timer 1 */
+ ldr r0, REG_MPU_LOAD_TIMER
+ ldr r1, VAL_MPU_LOAD_TIMER
+ str r1, [r0]
+
+ ldr r0, REG_MPU_CNTL_TIMER
+ ldr r1, VAL_MPU_CNTL_TIMER
+ str r1, [r0]
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+
+REG_TC_EMIFS_CONFIG: /* 32 bits */
+ .word 0xfffecc0c
+#ifdef CFG_BOOT_CS0
+REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
+ .word 0xfffecc1c
+#else
+REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
+ .word 0xfffecc18
+#endif
+
+/* MPU clock/reset/power mode control registers */
+REG_ARM_CKCTL: /* 16 bits */
+ .word 0xfffece00
+
+REG_ARM_IDLECT3: /* 16 bits */
+ .word 0xfffece24
+REG_ARM_IDLECT2: /* 16 bits */
+ .word 0xfffece08
+REG_ARM_IDLECT1: /* 16 bits */
+ .word 0xfffece04
+
+REG_ARM_RSTCT2: /* 16 bits */
+ .word 0xfffece14
+REG_ARM_SYSST: /* 16 bits */
+ .word 0xfffece18
+/* DPLL control registers */
+REG_DPLL1_CTL: /* 16 bits */
+ .word 0xfffecf00
+
+/* Watch Dog register */
+/* secure watchdog stop */
+REG_WSPRDOG:
+ .word 0xfffeb048
+/* watchdog write pending */
+REG_WWPSDOG:
+ .word 0xfffeb034
+
+WSPRDOG_VAL1:
+ .word 0x0000aaaa
+WSPRDOG_VAL2:
+ .word 0x00005555
+
+/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
+ counter @8192 rows, 10 ns, 8 burst */
+REG_SDRAM_CONFIG:
+ .word 0xfffecc20
+
+/* Operation register */
+REG_SDRAM_OPERATION:
+ .word 0xfffecc80
+
+REG_EMIFF_DOUBLER:
+ .word 0xfffecc60
+
+/* Manual command register */
+REG_SDRAM_MANUAL_CMD:
+ .word 0xfffecc84
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_MRS:
+ .word 0xfffecc70
+
+/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
+REG_SDRAM_EMRS1:
+ .word 0xfffecc78
+
+/* WRT DLL register */
+REG_DLL_WRT_CONTROL:
+ .word 0xfffecc64
+DLL_WRT_CONTROL_VAL:
+ .word 0x03500002
+
+/* URD DLL register */
+REG_DLL_URD_CONTROL:
+ .word 0xfffeccc0
+DLL_URD_CONTROL_VAL:
+ .word 0x00000006
+
+/* LRD DLL register */
+REG_DLL_LRD_CONTROL:
+ .word 0xfffecccc
+
+REG_WATCHDOG:
+ .word 0xfffec808
+
+REG_MPU_LOAD_TIMER:
+ .word 0xfffec600
+REG_MPU_CNTL_TIMER:
+ .word 0xfffec500
+
+/* 96 MHz Samsung Mobile DDR */
+SDRAM_CONFIG_VAL:
+ .word 0x0c028af4
+
+DLL_LRD_CONTROL_VAL:
+ .word 0x00000006
+
+VAL_ARM_CKCTL:
+ .word 0x350e
+VAL_ARM_SYSST:
+ .word 0x1001
+
+VAL_DPLL1_CTL:
+ .word 0x2810
+
+#ifdef CFG_BOOT_CS0
+VAL_TC_EMIFS_CONFIG:
+ .word 0x00000010
+VAL_TC_EMIFS_CS3_CONFIG:
+ .word 0xff80fff3
+#else
+VAL_TC_EMIFS_CONFIG:
+ .word 0x00000012 /*swap CS0/CS3 addressing */
+VAL_TC_EMIFS_CS2_CONFIG:
+ .word 0xff80fff3
+#endif
+
+
+VAL_TC_EMIFF_SDRAM_CONFIG:
+ .word 0x010290fc
+VAL_TC_EMIFF_MRS:
+ .word 0x00000027
+
+VAL_ARM_IDLECT1:
+ .word 0x000014c6
+
+VAL_ARM_IDLECT2:
+ .word 0x000009ff
+VAL_ARM_IDLECT3:
+ .word 0x0000003f
+
+WATCHDOG_VAL1:
+ .word 0x000000f5
+WATCHDOG_VAL2:
+ .word 0x000000a0
+
+VAL_MPU_LOAD_TIMER:
+ .word 0xffffffff
+VAL_MPU_CNTL_TIMER:
+ .word 0xffffffa1
+
+/* command values */
+.equ CMD_SDRAM_NOP, 0x00000000
+.equ CMD_SDRAM_PRECHARGE, 0x00000001
+.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
+.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
diff --git a/x-loader/board/omap1710h3/x-load.lds b/x-loader/board/omap1710h3/x-load.lds
new file mode 100644
index 0000000..7b84eea
--- /dev/null
+++ b/x-loader/board/omap1710h3/x-load.lds
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm926ejs/start.o (.text)
+ *(.text)
+ }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .data : { *(.data) }
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/omap2420h4/Makefile b/x-loader/board/omap2420h4/Makefile
new file mode 100644
index 0000000..5a47428
--- /dev/null
+++ b/x-loader/board/omap2420h4/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+OBJS := omap2420h4.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/omap2420h4/config.mk b/x-loader/board/omap2420h4/config.mk
new file mode 100644
index 0000000..1c770f3
--- /dev/null
+++ b/x-loader/board/omap2420h4/config.mk
@@ -0,0 +1,26 @@
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+#
+# TI H4 board with OMAP2420 (ARM1136) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
+# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1) ES2 will be configurable
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+# CONFIG_PARTIAL_SRAM must be defined to use this.
+TEXT_BASE = 0x80e80000
+
+# Used with full SRAM boot.
+# This is either with a GP system or a signed boot image.
+# easiest, and safest way to go if you can.
+# Comment out //CONFIG_PARTIAL_SRAM for this one.
+#
+#TEXT_BASE = 0x40280000
+
diff --git a/x-loader/board/omap2420h4/omap2420h4.c b/x-loader/board/omap2420h4/omap2420h4.c
new file mode 100644
index 0000000..ef81b49
--- /dev/null
+++ b/x-loader/board/omap2420h4/omap2420h4.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright (C) 2005 Texas Instruments.
+ * Jian Zhang <jzhang@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/bits.h>
+
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+
+static void wait_for_command_complete(unsigned int wd_base);
+static void watchdog_init(void);
+static void peripheral_enable(void);
+static void muxSetupUART1(void);
+static u32 get_cpu_rev(void);
+
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay (unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+ return 0;
+}
+
+#ifdef CFG_SDRAM_DDR
+void
+config_sdram_ddr(u32 rev)
+{
+ /* ball D11, mode 0 */
+ __raw_writeb(0x08, 0x48000032);
+
+ /* SDRC_CS0 Configuration */
+ if (rev == CPU_2420_2422_ES1) {
+ __raw_writel(H4_2422_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+ __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
+ } else {
+ __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+ __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
+ }
+
+ __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
+ __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0);
+
+ /* Manual Command sequence */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+
+ /*
+ * CS0 SDRC Mode Register
+ * Burst length = 4 - DDR memory
+ * Serial mode
+ * CAS latency = 3
+ */
+ __raw_writel(0x00000032, SDRC_MR_0);
+
+ /* SDRC DLLA control register */
+ /* Delay is 90 degrees */
+ if (rev == CPU_2420_2422_ES1) {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00000002, SDRC_DLLA_CTRL);
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00000002, SDRC_DLLB_CTRL);
+ } else {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x
+ }
+
+}
+#endif // CFG_SDRAM_DDR
+
+
+#ifdef CFG_SDRAM_COMBO
+void
+config_sdram_combo(u32 rev)
+{
+
+ u32 dllctrl=0;
+
+ /* ball C12, mode 0 */
+ __raw_writeb(0x00, 0x480000a1);
+ /* ball D11, mode 0 */
+ __raw_writeb(0x00, 0x48000032);
+ /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */
+ __raw_writeb(0x00, 0x480000a3);
+
+ /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */
+ __raw_writel(0x00000012, SDRC_SYSCONFIG);
+ delay(200000);
+ __raw_writel(0x00000010, SDRC_SYSCONFIG);
+
+ /* SDRCTriState: no Tris */
+ /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
+ __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
+
+
+ /* CS0 SDRC Memory Configuration, */
+ /* DDR-SDRAM, External SDRAM is x32bit, */
+ /* Configure to MUX9: 1x8Mbx32 */
+ __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0);
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+ __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
+
+ /* Manual Command sequence */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+ /* CS0 SDRC Mode Register */
+ /* Burst length = 4 - DDR memory */
+ /* Serial mode */
+ /* CAS latency = 3 */
+ __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0);
+
+ /* CS1 SDRC Memory Configuration, */
+ /* DDR-SDRAM, External SDRAM is x32bit, */
+ /* Configure to MUX9: 1x8Mbx32 */
+ __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1);
+ __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1);
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
+ __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4);
+
+ /* Manual Command sequence */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_1);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
+
+ /* CS1 SDRC Mode Register */
+ /* Burst length = 4 - DDR memory */
+ /* Serial mode */
+ /* CAS latency = 3 */
+ __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_1);
+
+ /* SDRC DLLA control register */
+ /* Delay is 90 degrees */
+ if (rev == CPU_242X_ES1)
+ dllctrl = (BIT0|BIT3);
+ else
+ dllctrl = BIT0;
+
+ if (rev == CPU_2420_2422_ES1) {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00007306, SDRC_DLLA_CTRL);
+ __raw_writel(0x00007302, SDRC_DLLA_CTRL);
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
+ __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
+ }
+ else {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ?
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
+ }
+}
+
+#endif // CFG_SDRAM_COMBO
+
+#ifdef CFG_SDRAM_SDR
+void
+config_sdram_sdr(u32 rev)
+{
+ u32 dllctrl=0;
+
+ /* ball D11, mode 0 */
+ __raw_writeb(0x00, 0x48000032);
+
+ __raw_writel(0x00000012, SDRC_SYSCONFIG);
+ delay(200000);
+ __raw_writel(0x00000010, SDRC_SYSCONFIG);
+
+ /* Chip-level shared interface management */
+ /* SDRCTriState: no Tris */
+ /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
+ /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */
+ if (rev == CPU_2420_2422_ES1)
+ __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
+ else
+ __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
+
+ /* CS0 SDRC Memory Configuration, */
+ /* DDR-SDRAM, External SDRAM is x32bit, */
+ /* Configure to MUX14: 32Mbx32 */
+ __raw_writel(H4_2420_SDRC_MDCFG_0_SDR, SDRC_MCFG_0); /* diff from combo case */
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+ __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
+
+ /* Manual Command sequence */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+ /* CS0 SDRC Mode Register */
+ /* Burst length = 2 - SDR memory */
+ /* Serial mode */
+ /* CAS latency = 3 */
+ __raw_writel(H4_2420_SDRC_MR_0_SDR, SDRC_MR_0); /* diff from combo case */
+
+ /* SDRC DLLA control register */
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ /* Delay is 90 degrees */
+
+ if (rev == CPU_242X_ES1)
+ dllctrl = (BIT0|BIT3);
+ else
+ dllctrl = BIT0;
+
+ if (rev == CPU_2420_2422_ES1) {
+ __raw_writel(0x00007306, SDRC_DLLA_CTRL);
+ __raw_writel(0x00007302, SDRC_DLLA_CTRL);
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
+ __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
+ }
+ else {
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
+ }
+
+}
+#endif // CFG_SDRAM_SDR
+
+#ifdef CFG_SDRAM_STACKED
+void
+config_sdram_stacked(u32 rev)
+{
+
+ /* Pin Muxing for SDRC */
+ __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */
+ __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */
+ __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */
+ __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */
+
+ /* configure sdrc 32 bit for COMBO ddr sdram */
+ __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */
+ delay(200000);
+ __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */
+
+ /* SDRC_SHARING */
+ /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */
+ //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
+
+ __raw_writel(0x00004900, SDRC_SHARING);
+
+ /* SDRC_CS0 Configuration */
+ /* None for ES2.1 */
+
+ /* SDRC_CS1 Configuration */
+ __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */
+
+ /* Disable power down of CKE */
+ __raw_writel(0x00000085, SDRC_POWER);
+
+ __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */
+ __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */
+ __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */
+ __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */
+
+ /*Manual Command sequence */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_1);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
+
+ /* CS0 SDRC Mode Register */
+ /* Burst length = 4 - DDR memory */
+ /* Serial mode */
+ /* CAS latency = 3 */
+ __raw_writel(0x00000032, SDRC_MR_1);
+ __raw_writel(0x00000020, SDRC_EMR2_1); /* weak-strength driver */
+
+ /* SDRC DLLA control register */
+ /* Delay is 90 degrees */
+ if (rev == CPU_2420_2422_ES1) {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00007302, SDRC_DLLA_CTRL);
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00007302, SDRC_DLLB_CTRL);
+ }
+ else {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x
+ }
+}
+#endif // CFG_SDRAM_STACKED
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+int s_init(int skip)
+{
+ u32 rev;
+
+ rev = get_cpu_rev();
+
+ watchdog_init();
+ muxSetupUART1();
+ delay(100);
+
+ /*DPLL out = 2x DPLL --> core clock */
+ __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL);
+
+ /*DPLL into low power bypass (others off) */
+ __raw_writel(0x00000001, CM_CLKEN_PLL);
+
+ /*MPU core clock = Core /2 = 300 */
+ __raw_writel(MPU_DIV, CM_CLKSEL_MPU);
+
+ /*DSPif=200, DSPif=100, IVA=200 */
+ __raw_writel(DSP_DIV, CM_CLKSEL_DSP);
+
+ /*GFX clock (L3/2) 50MHz */
+ __raw_writel(GFX_DIV, CM_CLKSEL_GFX);
+
+ /*L3=100, L4=100, DisplaySS=50 Vlync=96Mhz,ssi=100, usb=50 */
+ __raw_writel(BUS_DIV, CM_CLKSEL1_CORE);
+
+ /*12MHz apll src, 12/(1+1)*50=300 */
+ __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);
+
+ /*Valid the configuration */
+ __raw_writel(0x00000001, PRCM_CLKCFG_CTRL);
+ delay(1000);
+
+ /*Enable DPLL=300, 96MHz APLL locked. */
+ __raw_writel(0x0000000F, CM_CLKEN_PLL);
+ delay(200000);
+
+#ifdef CFG_SDRAM_DDR
+ config_sdram_ddr(rev);
+#elif defined(CFG_SDRAM_COMBO)
+ config_sdram_combo(rev);
+#elif defined(CFG_SDRAM_SDR)
+ config_sdram_sdr(rev);
+#elif defined(CFG_SDRAM_STACKED)
+ config_sdram_stacked(rev);
+#else
+#error SDRAM type not supported
+#endif
+
+ delay(20000);
+ peripheral_enable();
+ return(0);
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r (void)
+{
+ return(0);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+static void watchdog_init(void)
+{
+#define GP (BIT8|BIT9)
+
+ /* There are 4 watch dogs. 1 secure, and 3 general purpose.
+ * I would expect that the ROM takes care of the secure one,
+ * but we will try also. Of the 3 GP ones, 1 can reset us
+ * directly, the other 2 only generate MPU interrupts.
+ */
+ __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
+
+#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
+ __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
+ wait_for_command_complete(WD3_BASE);
+ __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
+
+ __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
+ wait_for_command_complete(WD4_BASE);
+ __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
+#endif
+
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+static void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base+WWPS);
+ } while (pending);
+}
+
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init (void)
+{
+ return 0;
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+static void peripheral_enable(void)
+{
+ unsigned int v, if_clks=0, func_clks=0;
+
+ /* Enable GP2 timer.*/
+ if_clks |= BIT4;
+ func_clks |= BIT4;
+ v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
+ __raw_writel(v, CM_CLKSEL2_CORE);
+ __raw_writel(0x1, CM_CLKSEL_WKUP);
+
+#ifdef CFG_NS16550
+ /* Enable UART1 clock */
+ func_clks |= BIT21;
+ if_clks |= BIT21;
+#endif
+ v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
+ __raw_writel(v,CM_ICLKEN1_CORE );
+ v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
+ __raw_writel(v, CM_FCLKEN1_CORE);
+ delay(1000);
+
+#ifndef KERNEL_UPDATED
+ {
+#define V1 0xffffffff
+#define V2 0x00000007
+
+ __raw_writel(V1, CM_FCLKEN1_CORE);
+ __raw_writel(V2, CM_FCLKEN2_CORE);
+ __raw_writel(V1, CM_ICLKEN1_CORE);
+ __raw_writel(V1, CM_ICLKEN2_CORE);
+ }
+#endif
+
+}
+
+/* Pin Muxing registers used for UART1 */
+#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5)
+#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6)
+#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7)
+#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8)
+/****************************************
+ * Routine: muxSetupUART1 (ostboot)
+ * Description: Set up uart1 muxing
+ *****************************************/
+static void muxSetupUART1(void)
+{
+ volatile unsigned char *MuxConfigReg;
+
+ /* UART1_CTS pin configuration, PIN = D21 */
+ MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+ /* UART1_RTS pin configuration, PIN = H21 */
+ MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+ /* UART1_TX pin configuration, PIN = L20 */
+ MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+
+ /* UART1_RX pin configuration, PIN = T21 */
+ MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
+ *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
+}
+
+int nand_init(void)
+{
+ u32 rev;
+
+ rev = get_cpu_rev();
+
+
+ /* GPMC pin muxing */
+ (*(volatile int*)0x48000070) &= 0x000000FF;
+ (*(volatile int*)0x48000074) &= 0x00000000;
+ (*(volatile int*)0x48000078) &= 0x00000000;
+ (*(volatile int*)0x4800007C) &= 0x00000000;
+ (*(volatile int*)0x48000080) &= 0xFF000000;
+
+ /* GPMC_IO_DIR */
+ (*(volatile int*)0x4800008C) = 0x19000000;
+
+ /* GPMC Configuration */
+ (*(volatile int*)0x6800A010) = 0x0000000A;
+ while (((*(volatile int *)0x6800A014) & 0x00000001) == 0);
+
+ (*(volatile int*)0x6800A050) = 0x00000001;
+ (*(volatile int*)0x6800A060) = 0x00001800;
+ (*(volatile int*)0x6800A064) = 0x00141400;
+ (*(volatile int*)0x6800A068) = 0x00141400;
+ (*(volatile int*)0x6800A06C) = 0x0F010F01;
+ (*(volatile int*)0x6800A070) = 0x010C1414;
+ (*(volatile int*)0x6800A074) = 0x00000A80;
+ (*(volatile int*)0x6800A078) = 0x00000C44; //base 0x04000000
+
+ (*(volatile int*)0x6800A0A8) = 0x00000000;
+ delay(1000);
+#ifdef CFG_SDRAM_STACKED
+ (*(volatile int*)0x6800A090) = 0x00011000;
+#else
+ (*(volatile int*)0x6800A090) = 0x00011200;
+#endif
+ (*(volatile int*)0x6800A094) = 0x001f1f00;
+ (*(volatile int*)0x6800A098) = 0x00080802;
+ (*(volatile int*)0x6800A09C) = 0x1C091C09;
+ (*(volatile int*)0x6800A0A0) = 0x031A1F1F;
+ (*(volatile int*)0x6800A0A4) = 0x000003C2;
+ (*(volatile int*)0x6800A0A8) = 0x00000F48;
+
+ if (rev != CPU_2420_2422_ES1)
+ (*(volatile int*)0x6800A040) = 0x1FF0; // es2.x
+
+ if (nand_chip()){
+ printf("Unsupported Chip!\n");
+ return 1;
+ }
+ return 0;
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 v;
+ v = __raw_readl(TAP_IDCODE_REG);
+ v = v >> 28;
+ return(v+1); /* currently 2422 and 2420 match up */
+}
+
+/* optionally do something like blinking LED */
+void board_hang (void)
+{}
+
+
+
diff --git a/x-loader/board/omap2420h4/platform.S b/x-loader/board/omap2420h4/platform.S
new file mode 100644
index 0000000..5cc37e5
--- /dev/null
+++ b/x-loader/board/omap2420h4/platform.S
@@ -0,0 +1,218 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/omap2420.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#ifdef CONFIG_PARTIAL_SRAM
+
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
+ * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
+ * R2 = dpll value
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ sub sp, sp, #0x4 /* get some stack space */
+ str r4, [sp] /* save r4's value */
+
+ /* move into fast relock bypass */
+ ldr r8, pll_ctl_add
+ mov r4, #0x2
+ str r4, [r8]
+ ldr r4, pll_stat
+block:
+ ldr r8, [r4] /* wait for bypass to take effect */
+ and r8, r8, #0x3
+ cmp r8, #0x1
+ bne block
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r4, pll_div_add
+ ldr r8, pll_div_val
+ str r8, [r4]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r4, cfg3_0_addr
+ ldr r8, cfg3_0_val
+ str r8, [r4]
+ ldr r4, cfg4_0_addr
+ ldr r8, cfg4_0_val
+ str r8, [r4]
+ ldr r4, cfg1_0_addr
+ ldr r8, [r4]
+ orr r8, r8, #0x3 /* up gpmc divider */
+ str r8, [r4]
+
+ /* setup to 2x loop though code. The first loop pre-loads the
+ * icache, the 2nd commits the prcm config, and locks the dpll
+ */
+ mov r4, #0x1000 /* spin spin spin */
+ mov r8, #0x4 /* first pass condition & set registers */
+ cmp r8, #0x4
+2:
+ ldrne r8, [r3] /* DPLL lock check */
+ and r8, r8, #0x7
+ cmp r8, #0x2
+ beq 4f
+3:
+ subeq r8, r8, #0x1
+ streq r8, [r0] /* commit dividers (2nd time) */
+ nop
+lloop1:
+ sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
+ nop
+ cmp r4, #0x0
+ bne lloop1
+ mov r4, #0x40000
+ cmp r8, #0x1
+ nop
+ streq r2, [r1] /* lock dpll (2nd time) */
+ nop
+lloop2:
+ sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
+ nop
+ cmp r4, #0x0
+ bne lloop2
+ mov r4, #0x40000
+ cmp r8, #0x1
+ nop
+ ldreq r8, [r3] /* get lock condition for dpll */
+ cmp r8, #0x4 /* first time though? */
+ bne 2b
+ moveq r8, #0x2 /* set to dpll check condition. */
+ beq 3b /* if condition not true branch */
+4:
+ ldr r4, [sp]
+ add sp, sp, #0x4 /* return stack space */
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+cfg3_0_addr:
+ .word GPMC_CONFIG3_0
+cfg3_0_val:
+ .word SMNAND_GPMC_CONFIG3
+cfg4_0_addr:
+ .word GPMC_CONFIG4_0
+cfg4_0_val:
+ .word SMNAND_GPMC_CONFIG4
+cfg1_0_addr:
+ .word GPMC_CONFIG1_0
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_stat:
+ .word CM_IDLEST_CKGEN
+pll_div_add:
+ .word CM_CLKSEL1_PLL
+pll_div_val:
+ .word DPLL_VAL /* DPLL setting (300MHz default) */
+#endif
+
+.globl platformsetup
+platformsetup:
+ mov r3, r0 /* save skip information */
+#ifdef CONFIG_APTIX
+ ldr r0, REG_SDRC_MCFG_0
+ ldr r1, VAL_SDRC_MCFG_0
+ str r1, [r0]
+ ldr r0, REG_SDRC_MR_0
+ ldr r1, VAL_SDRC_MR_0
+ str r1, [r0]
+ /* a ddr needs emr1 set here */
+ ldr r0, REG_SDRC_SHARING
+ ldr r1, VAL_SDRC_SHARING
+ str r1, [r0]
+ ldr r0, REG_SDRC_RFR_CTRL_0
+ ldr r1, VAL_SDRC_RFR_CTRL_0
+ str r1, [r0]
+
+ /* little delay after init */
+ mov r2, #0x1800
+1:
+ subs r2, r2, #0x1
+ bne 1b
+#endif
+#ifdef CONFIG_PARTIAL_SRAM
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ mov r0, r3 /* pass skip info to s_init */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+#endif
+
+ /* map interrupt controller */
+ ldr r0, VAL_INTH_SETUP
+ mcr p15, 0, r0, c15, c2, 4
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+VAL_INTH_SETUP:
+ .word PERIFERAL_PORT_BASE
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+
+
+
+
+
diff --git a/x-loader/board/omap2420h4/x-load.lds b/x-loader/board/omap2420h4/x-load.lds
new file mode 100644
index 0000000..f664ca7
--- /dev/null
+++ b/x-loader/board/omap2420h4/x-load.lds
@@ -0,0 +1,54 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/omap2430sdp/Makefile b/x-loader/board/omap2430sdp/Makefile
new file mode 100644
index 0000000..56c941d
--- /dev/null
+++ b/x-loader/board/omap2430sdp/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+OBJS := omap2430sdp.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/omap2430sdp/config.mk b/x-loader/board/omap2430sdp/config.mk
new file mode 100644
index 0000000..7bc5078
--- /dev/null
+++ b/x-loader/board/omap2430sdp/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2004
+# Texas Instruments, <www.ti.com>
+#
+# TI H4 board with OMAP2420 (ARM1136) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# H4 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0
+# H4 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1) ES2 will be configurable
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# 2430 h4 has same mem configuration as h4.
+
+# For use with external or internal boots.
+# CONFIG_PARTIAL_SRAM must be defined to use this.
+TEXT_BASE = 0x80e80000
+
+# Used with full SRAM boot.
+# This is either with a GP system or a signed boot image.
+# easiest, and safest way to go if you can.
+# Comment out //CONFIG_PARTIAL_SRAM for this one.
+#
+#TEXT_BASE = 0x40280000
+
diff --git a/x-loader/board/omap2430sdp/omap2430sdp.c b/x-loader/board/omap2430sdp/omap2430sdp.c
new file mode 100644
index 0000000..f2a7b42
--- /dev/null
+++ b/x-loader/board/omap2430sdp/omap2430sdp.c
@@ -0,0 +1,746 @@
+/*
+ * (C) Copyright 2004-2005
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap2430.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+
+static void wait_for_command_complete(unsigned int wd_base);
+static void watchdog_init(void);
+static void peripheral_enable(void);
+static void muxSetupAll(void);
+static u32 get_cpu_rev(void);
+static u32 get_device_type(void);
+static void prcm_init(void);
+
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay (unsigned long loops)
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+ return 0;
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 v;
+ v = __raw_readl(TAP_IDCODE_REG);
+ v = v >> 28;
+ return(v+1); /* currently 2422 and 2420 match up */
+}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+ return(mode >>= 8);
+}
+
+/*************************************************************
+ * Helper function to wait for the status of a register
+ *************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return(1);
+ if (i==bound)
+ return(0);
+ } while (1);
+}
+
+/*************************************************************
+ * Support for multiple type of memory types
+ *************************************************************/
+#ifdef CFG_SDRAM_DDR
+void
+config_sdram_ddr(u32 rev)
+{
+ /* ball D11, mode 0 */
+ __raw_writeb(0x08, 0x48000032);
+
+ /* SDRC_CS0 Configuration */
+ __raw_writel(H4_2420_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+ __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
+
+ __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
+ __raw_writel(H4_242x_SDRC_ACTIM_CTRLA_0_ES1, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(H4_242x_SDRC_ACTIM_CTRLB_0_ES1, SDRC_ACTIM_CTRLB_0);
+
+ /* Manual Command sequence */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+
+ /*
+ * CS0 SDRC Mode Register
+ * Burst length = 4 - DDR memory
+ * Serial mode
+ * CAS latency = 3
+ */
+ __raw_writel(0x00000032, SDRC_MR_0);
+
+ /* SDRC DLLA control register */
+ /* Delay is 90 degrees */
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00000008, SDRC_DLLA_CTRL); // ES2.x
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00000008, SDRC_DLLB_CTRL); // ES2.x
+
+}
+#endif // CFG_SDRAM_DDR
+
+#ifdef CFG_SDRAM_COMBO
+void
+config_sdram_combo(u32 rev)
+{
+
+ u32 dllctrl=0;
+
+ /* ball C12, mode 0 */
+ __raw_writeb(0x00, 0x480000a1);
+ /* ball D11, mode 0 */
+ __raw_writeb(0x00, 0x48000032);
+ /* ball B13, mode 0 - for CKE1 (not needed rkw for combo) */
+ __raw_writeb(0x00, 0x480000a3);
+
+ /*configure sdrc 32 bit for COMBO ddr sdram. Issue soft reset */
+ __raw_writel(0x00000012, SDRC_SYSCONFIG);
+ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
+ __raw_writel(0x00000000, SDRC_SYSCONFIG);
+
+ /* SDRCTriState: no Tris */
+ /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
+ if (rev == CPU_2420_2422_ES1)
+ __raw_writel(H4_2422_SDRC_SHARING, SDRC_SHARING);
+ else
+ __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
+
+
+ /* CS0 SDRC Memory Configuration, */
+ /* DDR-SDRAM, External SDRAM is x32bit, */
+ /* Configure to MUX9: 1x8Mbx32 */
+ __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0);
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+
+ /* This is reqd only for ES1 */
+ if (rev == CPU_242X_ES1)
+ __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, SDRC_RFR_CTRL);
+
+ /* Manual Command sequence */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ delay(5000);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+ /* CS0 SDRC Mode Register */
+ /* Burst length = 4 - DDR memory */
+ /* Serial mode */
+ /* CAS latency = 3 */
+ __raw_writel(H4_2422_SDRC_MR_0_DDR, SDRC_MR_0);
+
+ /* CS1 SDRC Memory Configuration, */
+ /* DDR-SDRAM, External SDRAM is x32bit, */
+ /* Configure to MUX9: 1x8Mbx32 */
+ __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_1);
+ __raw_writel(H4_242X_SDRC_ACTIM_CTRLA_0_100MHz, SDRC_ACTIM_CTRLA_1);
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
+ /* This is reqd only for ES1 */
+ if (rev == CPU_242X_ES1)
+ __raw_writel(H4_242x_SDRC_RFR_CTRL_ES1, 0x680090d4);
+
+ /* Manual Command sequence */
+ __raw_writel(CMD_NOP, 0x680090d8);
+ __raw_writel(CMD_PRECHARGE, 0x680090d8);
+ __raw_writel(CMD_AUTOREFRESH, 0x680090d8);
+ __raw_writel(CMD_AUTOREFRESH, 0x680090d8);
+
+ /* CS1 SDRC Mode Register */
+ /* Burst length = 4 - DDR memory */
+ /* Serial mode */
+ /* CAS latency = 3 */
+ __raw_writel(H4_2422_SDRC_MR_0_DDR, 0x680090b4);
+
+ /* SDRC DLLA control register */
+ /* Delay is 90 degrees */
+
+ if (rev == CPU_242X_ES1)
+ dllctrl = (BIT0|BIT3);
+ else
+ dllctrl = BIT0;
+
+ if (rev == CPU_2420_2422_ES1) {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00007306, SDRC_DLLA_CTRL);
+ __raw_writel(0x00007302, SDRC_DLLA_CTRL);
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00007306, SDRC_DLLB_CTRL); /* load ctr value */
+ __raw_writel(0x00007302, SDRC_DLLB_CTRL); /* lock and go */
+ }
+ else {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); // ES2.x
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); // ES2.x
+ // __raw_writel(0x00009808, SDRC_DLLA_CTRL); // ES2.x
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL, SDRC_DLLB_CTRL); // ES2.x ?
+ __raw_writel(H4_2420_SDRC_DLLAB_CTRL & ~(LOADDLL|dllctrl), SDRC_DLLB_CTRL); // ES2.x
+ //__raw_writel(0x00009808, SDRC_DLLB_CTRL); // ES2.x
+ }
+}
+
+#endif // CFG_SDRAM_COMBO
+
+#ifdef CFG_2430SDRAM_DDR
+void
+config_2430sdram_ddr(u32 rev)
+{
+ u32 dllstat, dllctrl;
+
+ __raw_writel(0x00000012, SDRC_SYSCONFIG);
+ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */
+ __raw_writel(0x00000000, SDRC_SYSCONFIG);
+
+ /* Chip-level shared interface management */
+ /* SDRCTriState: no Tris */
+ /* CS0MuxCfg: 000 (32-bit SDRAM on D31..0) */
+ /* CS1MuxCfg: 000 (32-bit SDRAM on D31..0) */
+ __raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
+
+ /* CS0 SDRC Memory Configuration, */
+ /* DDR-SDRAM, External SDRAM is x32bit, */
+ /* Configure to MUX14: 32Mbx32 */
+ __raw_writel(SDP_2430_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+ __raw_writel(SDP_2430_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(H4_2420_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+
+ __raw_writel(H4_2420_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
+
+ /* Manual Command sequence */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ delay(5000);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+ /* CS0 SDRC Mode Register */
+ /* Burst length = 2 - SDR memory */
+ /* Serial mode */
+ /* CAS latency = 3 */
+ __raw_writel(H4_2420_SDRC_MR_0_DDR, SDRC_MR_0);
+
+ /* Set up SDRC DLL values for 2430 DDR */
+ dllctrl = (SDP_2430_SDRC_DLLAB_CTRL & ~BIT2); /* set target ctrl val */
+ __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set lock mode */
+ __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set lock mode */
+ delay(0x1000); /* time to track to center */
+ dllstat = __raw_readl(SDRC_DLLA_STATUS) & 0xFF00; /* get status */
+ dllctrl = (dllctrl & 0x00FF) | dllstat | BIT2; /* build unlock value */
+ __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* set unlock mode */
+ __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* set unlock mode */
+}
+#endif // CFG_2430SDRAM_DDR
+
+#ifdef CFG_SDRAM_STACKED
+void
+config_sdram_stacked(u32 rev)
+{
+
+ /* Pin Muxing for SDRC */
+ __raw_writeb(0x00, 0x480000a1); /* mux mode 0 (CS1) */
+ __raw_writeb(0x00, 0x480000a3); /* mux mode 0 (CKE1) */
+ __raw_writeb(0x00, 0x48000032); /* connect sdrc_a12 */
+ __raw_writeb(0x00, 0x48000031); /* connect sdrc_a13 */
+
+ /* configure sdrc 32 bit for COMBO ddr sdram */
+ __raw_writel(0x00000010, SDRC_SYSCONFIG); /* no idle ack and RESET enable */
+ delay(200000);
+ __raw_writel(0x00000010, SDRC_SYSCONFIG); /* smart idle mode */
+
+ /* SDRC_SHARING */
+ /* U-boot is writing 0x00000100 though (H4_2420_SDRC_SHARING ) */
+ //__raw_writel(H4_2420_SDRC_SHARING, SDRC_SHARING);
+
+ __raw_writel(0x00004900, SDRC_SHARING);
+
+ /* SDRC_CS0 Configuration */
+ /* None for ES2.1 */
+
+ /* SDRC_CS1 Configuration */
+ __raw_writel(0x00000000, SDRC_CS_CFG); /* Remap CS1 to 0x80000000 */
+
+ /* Disable power down of CKE */
+ __raw_writel(0x00000085, SDRC_POWER);
+
+ __raw_writel(0x01A02019, SDRC_MCFG_1); /* SDRC_MCFG1 */
+ __raw_writel(0x0003DD03, SDRC_RFR_CTRL1); /* SDRC_RFR_CTRL1 */
+ __raw_writel(0x92DDC485, SDRC_ACTIM_CTRLA_1); /* SDRC_ACTIM_CTRLA0 */
+ __raw_writel(0x00000014, SDRC_ACTIM_CTRLB_1); /* SDRC_ACTIM_CTRLB0 */
+
+ /*Manual Command sequence */
+ __raw_writel(0x00000000, 0x680090D8);
+ __raw_writel(0x00000001, 0x680090D8);
+ __raw_writel(0x00000002, 0x680090D8);
+ __raw_writel(0x00000002, 0x680090D8);
+
+ /* CS0 SDRC Mode Register */
+ /* Burst length = 4 - DDR memory */
+ /* Serial mode */
+ /* CAS latency = 3 */
+ __raw_writel(0x00000032, 0x680090B4);
+ __raw_writel(0x00000020, 0x680090BC); /* weak-strength driver */
+
+ /* SDRC DLLA control register */
+ /* Delay is 90 degrees */
+ if (rev == CPU_2420_2422_ES1) {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00007302, SDRC_DLLA_CTRL);
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00007302, SDRC_DLLB_CTRL);
+ }
+ else {
+ /* Enable DLL, Load counter with 115 (middle of range) */
+ __raw_writel(0x00003108, SDRC_DLLA_CTRL); // ES2.x
+ /* Enable DLL, Load counter with 128 (middle of range) */
+ __raw_writel(0x00003108, SDRC_DLLB_CTRL); // ES2.x
+ }
+}
+#endif // CFG_SDRAM_STACKED
+
+/*************************************************************
+ * get_sys_clk_speed - determine reference oscillator speed
+ * based on known 32kHz clock and gptimer.
+ *************************************************************/
+u32 get_osc_clk_speed(u32 *shift)
+{
+#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */
+#define GPT_CTR OMAP24XX_GPT2+TCRR /* read counter address */
+ u32 start, cstart, cend, cdiff, val;
+ unsigned int v, if_clks=0, func_clks=0 ;
+
+
+
+ if(__raw_readl(PRCM_CLKSRC_CTRL) & BIT7){ /* if currently /2 */
+ *shift = 1;
+ }else{
+ *shift = 0;
+ }
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* mask for sys_clk use */
+ __raw_writel(val, CM_CLKSEL2_CORE); /* timer2 source to sys_clk */
+ __raw_writel(BIT4, CM_ICLKEN1_CORE); /* timer2 interface clock on */
+ __raw_writel(BIT4, CM_FCLKEN1_CORE); /* timer2 function clock on */
+ /* Enable GP2 timer.*/
+ if_clks |= BIT4;
+ func_clks |= BIT4;
+ v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
+ __raw_writel(v,CM_ICLKEN1_CORE );
+ v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
+ __raw_writel(v, CM_FCLKEN1_CORE);
+ __raw_writel(0, OMAP24XX_GPT2+TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP24XX_GPT2+TCLR); /* enable clock */
+ /* enable 32kHz source */ /* enabled out of reset */
+ /* determine sys_clk via gauging */
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles*/
+ while(__raw_readl(S32K_CR) < start); /* dead loop till start time */
+ cstart = __raw_readl(GPT_CTR); /* get start sys_clk count */
+ while(__raw_readl(S32K_CR) < (start+20)); /* wait for 40 cycles */
+ cend = __raw_readl(GPT_CTR); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+ /* based on number of ticks assign speed */
+ if(cdiff > (19000 >> *shift))
+ return(S38_4M);
+ else if (cdiff > (15200 >> *shift))
+ return(S26M);
+ else if (cdiff > (13000 >> *shift))
+ return(S24M);
+ else if (cdiff > (9000 >> *shift))
+ return(S19_2M);
+ else if (cdiff > (7600 >> *shift))
+ return(S13M);
+ else
+ return(S12M);
+}
+
+/*********************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
+ * -- called from SRAM
+ *********************************************************************************/
+void
+prcm_init()
+{
+ u32 div, speed, val, div_by_2;
+
+ val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0);
+#if defined(OMAP2430_SQUARE_CLOCK_INPUT)
+ __raw_writel(val, PRCM_CLKSRC_CTRL);
+#else
+ __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL);
+#endif
+ speed = get_osc_clk_speed(&div_by_2);
+ if((speed > S19_2M) && (!div_by_2)){ /* if fast && /2 off, enable it */
+ val = ~(BIT6|BIT7) & __raw_readl(PRCM_CLKSRC_CTRL);
+ val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2) */
+ __raw_writel(val, PRCM_CLKSRC_CTRL);
+ }
+
+ __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */
+ __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */
+ __raw_writel(0, CM_ICLKEN1_CORE);
+ __raw_writel(0, CM_ICLKEN2_CORE);
+
+ /*DPLL into low power bypass (others off) */
+ __raw_writel(0x00000001, CM_CLKEN_PLL);
+
+ __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */
+ __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */
+ __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */
+ __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */
+ __raw_writel(MDM_DIV, CM_CLKSEL_MDM); /* set mdm dividers */
+
+ div = BUS_DIV;
+ __raw_writel(div, CM_CLKSEL1_CORE);/* set L3/L4/USB/Display/SSi dividers */
+ delay(1000);
+
+ /*13MHz apll src, PRCM 'x' DPLL rate */
+ __raw_writel(DPLL_VAL, CM_CLKSEL1_PLL);
+
+ /*Valid the configuration */
+ __raw_writel(0x00000001, PRCM_CLKCFG_CTRL);
+ delay(1000);
+
+ /* set up APLLS_CLKIN per crystal */
+ if (speed > S19_2M)
+ speed >>= 1; /* if fast shift to /2 range */
+ val = (0x2 << 23); /* default to 13Mhz for 2430c */
+ if (speed == S12M)
+ val = (0x3 << 23);
+ else if (speed == S19_2M)
+ val = (0x0 << 23);
+ val |= (~(BIT23|BIT24|BIT25) & __raw_readl(CM_CLKSEL1_PLL));
+ __raw_writel(val, CM_CLKSEL1_PLL);
+
+ __raw_writel(DPLL_LOCK|APLL_LOCK, CM_CLKEN_PLL); /* enable apll */
+ wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY);/* wait for apll lock */
+
+ delay(200000);
+}
+
+void SEC_generic(void)
+{
+/* Permission values for registers -Full fledged permissions to all */
+#define UNLOCK_1 0xFFFFFFFF
+#define UNLOCK_2 0x00000000
+#define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT)*/
+ __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/
+ __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/
+
+
+ __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
+
+ __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); /* ADDR_MATCH_2 L*/
+
+ /* IVA Changes */
+ __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/
+ __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for general use.
+ ***********************************************************/
+void try_unlock_sram(void)
+{
+ int mode;
+
+ /* if GP device unlock device SRAM for general use */
+ mode = get_device_type();
+
+ if ((mode == GP_DEVICE) || (mode == HS_DEVICE) || (mode == EMU_DEVICE)
+ || (mode == TST_DEVICE)) {
+ /* Secure or Emulation device - HS/E/T */
+ SEC_generic();
+ }
+ return;
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+
+int s_init(int skip)
+{
+ u32 rev;
+
+ rev = get_cpu_rev();
+
+ watchdog_init();
+ try_unlock_sram();
+ muxSetupAll();
+ delay(100);
+ prcm_init();
+
+#ifdef CFG_SDRAM_DDR
+ config_sdram_ddr(rev);
+#elif defined(CFG_SDRAM_COMBO)
+ config_sdram_combo(rev);
+#elif defined(CFG_2430SDRAM_DDR)
+ config_2430sdram_ddr(rev);
+#elif defined(CFG_SDRAM_STACKED)
+ config_sdram_stacked(rev);
+#else
+#error SDRAM type not supported
+#endif
+
+ delay(20000);
+ peripheral_enable();
+ return(0);
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r (void)
+{
+ return(0);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+static void watchdog_init(void)
+{
+#define GP (BIT8|BIT9)
+
+ /* There are 4 watch dogs. 1 secure, and 3 general purpose.
+ * I would expect that the ROM takes care of the secure one,
+ * but we will try also. Of the 3 GP ones, 1 can reset us
+ * directly, the other 2 only generate MPU interrupts.
+ */
+ __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
+
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+static void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base+WWPS);
+ } while (pending);
+}
+
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init (void)
+{
+ return 0;
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+static void peripheral_enable(void)
+{
+ unsigned int v, if_clks=0, if_clks2 = 0, func_clks=0, func_clks2 = 0;
+
+ /* Enable GP2 timer.*/
+ if_clks |= BIT4;
+ func_clks |= BIT4;
+ v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP24XX_GPT2 */
+ __raw_writel(v, CM_CLKSEL2_CORE);
+ __raw_writel(0x1, CM_CLKSEL_WKUP);
+
+#ifdef CFG_NS16550
+ /* Enable UART1 clock */
+ func_clks |= BIT21;
+ if_clks |= BIT21;
+#endif
+ v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
+ __raw_writel(v,CM_ICLKEN1_CORE );
+ v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2; /* Interface clocks on */
+ __raw_writel(v, CM_ICLKEN2_CORE);
+ v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
+ __raw_writel(v, CM_FCLKEN1_CORE);
+ v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2; /* Functional Clocks on */
+ __raw_writel(v, CM_FCLKEN2_CORE);
+ delay(1000);
+
+}
+
+/* Do pin muxing for all the devices used in X-Loader */
+#define MUX_VAL(OFFSET,VALUE)\
+ __raw_writeb(VALUE, OMAP24XX_CTRL_BASE + OFFSET);
+static void muxSetupAll(void)
+{
+ /* UART 1*/
+ MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */
+ MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */
+ MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */
+ MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */
+ MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */
+ MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */
+ MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */
+ MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */
+
+ /* Mux settings for SDRC */
+ MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */
+ MUX_VAL(0x0055, 0x1B) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */
+ MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */
+ MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */
+ MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */
+ /* GPMC */
+ MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */
+ MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */
+ MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */
+ MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */
+ MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */
+ MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */
+ MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */
+ MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */
+ MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */
+ MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */
+ MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */
+ MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */
+}
+
+int nand_init(void)
+{
+ u32 rev;
+
+ /* GPMC Configuration */
+ rev = get_cpu_rev();
+
+ /* global settings */
+ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
+ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
+ __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
+#ifdef CFG_NAND
+ __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
+#endif
+
+ /* Set the GPMC Vals . For NAND boot on 2430SDP, NAND is mapped at CS0
+ * , NOR at CS1 and MPDB at CS5. And oneNAND boot, we map oneNAND at CS0.
+ * We configure only GPMC CS0 with required values. Configiring other devices
+ * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
+ */
+ __raw_writel(0, GPMC_CONFIG7_0);
+ sdelay(1000);
+
+#ifdef CFG_NAND
+ __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1_0);
+ __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2_0);
+ __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3_0);
+ __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4_0);
+ __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5_0);
+ __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6_0);
+
+#else /* CFG_ONENAND */
+ __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1_0);
+ __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2_0);
+ __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3_0);
+ __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4_0);
+ __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5_0);
+ __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6_0);
+#endif
+
+ /* Enable the GPMC Mapping */
+ __raw_writel(( ((OMAP24XX_GPMC_CS0_SIZE & 0xF)<<8) |
+ ((OMAP24XX_GPMC_CS0_MAP>>24) & 0x3F) |
+ (1<<6) ), GPMC_CONFIG7_0);
+ sdelay(2000);
+#ifdef CFG_NAND
+ if (nand_chip()){
+#ifdef CFG_PRINTF
+ printf("Unsupported Chip!\n");
+#endif
+ return 1;
+ }
+#else
+ if (onenand_chip()){
+#ifdef CFG_PRINTF
+ printf("OneNAND Unsupported !\n");
+#endif
+ return 1;
+ }
+
+#endif
+ return 0;
+}
+
+/* optionally do something like blinking LED */
+void board_hang (void)
+{ while (0) {};}
diff --git a/x-loader/board/omap2430sdp/platform.S b/x-loader/board/omap2430sdp/platform.S
new file mode 100644
index 0000000..f221d7e
--- /dev/null
+++ b/x-loader/board/omap2430sdp/platform.S
@@ -0,0 +1,198 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004-2005
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/omap2430.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = PRCM_CLKCFG_CTRL - addr of valid reg
+ * R1 = CM_CLKEN_PLL - addr dpll ctlr reg
+ * R2 = dpll value
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ sub sp, sp, #0x4 /* get some stack space */
+ str r4, [sp] /* save r4's value */
+
+ /* move into fast relock bypass */
+ ldr r8, pll_ctl_add
+ mov r4, #0x2
+ str r4, [r8]
+ ldr r4, pll_stat
+block:
+ ldr r8, [r4] /* wait for bypass to take effect */
+ and r8, r8, #0x3
+ cmp r8, #0x1
+ bne block
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r4, pll_div_add
+ ldr r8, pll_div_val
+ str r8, [r4]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r4, flash_cfg3_addr
+ ldr r8, flash_cfg3_val
+ str r8, [r4]
+ ldr r4, flash_cfg4_addr
+ ldr r8, flash_cfg4_val
+ str r8, [r4]
+ ldr r4, flash_cfg1_addr
+ ldr r8, [r4]
+ orr r8, r8, #0x3 /* up gpmc divider */
+ str r8, [r4]
+
+ /* setup to 2x loop though code. The first loop pre-loads the
+ * icache, the 2nd commits the prcm config, and locks the dpll
+ */
+ mov r4, #0x1000 /* spin spin spin */
+ mov r8, #0x4 /* first pass condition & set registers */
+ cmp r8, #0x4
+2:
+ ldrne r8, [r3] /* DPLL lock check */
+ and r8, r8, #0x7
+ cmp r8, #0x2
+ beq 4f
+3:
+ subeq r8, r8, #0x1
+ streq r8, [r0] /* commit dividers (2nd time) */
+ nop
+lloop1:
+ sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
+ nop
+ cmp r4, #0x0
+ bne lloop1
+ mov r4, #0x40000
+ cmp r8, #0x1
+ nop
+ streq r2, [r1] /* lock dpll (2nd time) */
+ nop
+lloop2:
+ sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
+ nop
+ cmp r4, #0x0
+ bne lloop2
+ mov r4, #0x40000
+ cmp r8, #0x1
+ nop
+ ldreq r8, [r3] /* get lock condition for dpll */
+ cmp r8, #0x4 /* first time though? */
+ bne 2b
+ moveq r8, #0x2 /* set to dpll check condition. */
+ beq 3b /* if condition not true branch */
+4:
+ ldr r4, [sp]
+ add sp, sp, #0x4 /* return stack space */
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+#ifdef CFG_ONENAND
+flash_cfg3_addr:
+ .word GPMC_CONFIG3_0
+flash_cfg3_val:
+ .word ONENAND_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word GPMC_CONFIG4_0
+flash_cfg4_val:
+ .word ONENAND_GPMC_CONFIG4
+flash_cfg1_addr:
+ .word GPMC_CONFIG1_0
+#else
+flash_cfg3_addr:
+ .word GPMC_CONFIG3_0
+flash_cfg3_val:
+ .word SMNAND_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word GPMC_CONFIG4_0
+flash_cfg4_val:
+ .word SMNAND_GPMC_CONFIG4
+flash_cfg1_addr:
+ .word GPMC_CONFIG1_0
+#endif
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_stat:
+ .word CM_IDLEST_CKGEN
+pll_div_add:
+ .word CM_CLKSEL1_PLL
+pll_div_val:
+ .word DPLL_VAL /* DPLL setting (300MHz default) */
+
+.globl platformsetup
+platformsetup:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* map interrupt controller */
+ ldr r0, VAL_INTH_SETUP
+ mcr p15, 0, r0, c15, c2, 4
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+VAL_INTH_SETUP:
+ .word PERIFERAL_PORT_BASE
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
diff --git a/x-loader/board/omap2430sdp/x-load.lds b/x-loader/board/omap2430sdp/x-load.lds
new file mode 100644
index 0000000..f12e8f8
--- /dev/null
+++ b/x-loader/board/omap2430sdp/x-load.lds
@@ -0,0 +1,54 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2005 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm1136/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/omap3430labrador/Makefile b/x-loader/board/omap3430labrador/Makefile
new file mode 100755
index 0000000..d78b8a3
--- /dev/null
+++ b/x-loader/board/omap3430labrador/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+OBJS := omap3430sdp.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/omap3430labrador/config.mk b/x-loader/board/omap3430labrador/config.mk
new file mode 100755
index 0000000..d6ad6c5
--- /dev/null
+++ b/x-loader/board/omap3430labrador/config.mk
@@ -0,0 +1,22 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0
+# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000'0000 (bank1) - re-mappable below CS1
+
+# For use if you want X-Loader to relocate from SRAM to DDR
+#TEXT_BASE = 0x80e80000
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+TEXT_BASE = 0x40208800
diff --git a/x-loader/board/omap3430labrador/omap3430sdp.c b/x-loader/board/omap3430labrador/omap3430sdp.c
new file mode 100755
index 0000000..af9fedb
--- /dev/null
+++ b/x-loader/board/omap3430labrador/omap3430sdp.c
@@ -0,0 +1,744 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+
+/* Used to index into DPLL parameter tables */
+struct dpll_param {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+};
+
+typedef struct dpll_param dpll_param;
+
+#define MAX_SIL_INDEX 3
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param * get_mpu_dpll_param(void);
+extern dpll_param * get_iva_dpll_param(void);
+extern dpll_param * get_core_dpll_param(void);
+extern dpll_param * get_per_dpll_param(void);
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+ return 0;
+}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+ return(mode >>= 8);
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 cpuid=0;
+ /* On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate
+ * between ES2.0 and ES1.0.
+ */
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
+ if((cpuid & 0xf) == 0x0)
+ return CPU_3430_ES1;
+ else
+ return CPU_3430_ES2;
+
+}
+
+/******************************************
+ * cpu_is_3410(void) - returns true for 3410
+ ******************************************/
+u32 cpu_is_3410(void)
+{
+ int status;
+ if(get_cpu_rev() < CPU_3430_ES2) {
+ return 0;
+ } else {
+ /* read scalability status and return 1 for 3410*/
+ status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
+ /* Check whether MPU frequency is set to 266 MHz which
+ * is nominal for 3410. If yes return true else false
+ */
+ if (((status >> 8) & 0x3) == 0x2)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/*****************************************************************
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ *****************************************************************/
+void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = __raw_readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ __raw_writel(tmp, addr);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
+
+#ifdef CFG_3430SDRAM_DDR
+/*********************************************************************
+ * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
+ *********************************************************************/
+void config_3430sdram_ddr(void)
+{
+ /* reset sdrc controller */
+ __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
+ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
+ __raw_writel(0, SDRC_SYSCONFIG);
+
+ /* setup sdrc to ball mux */
+ __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
+
+ /* set mdcfg */
+ __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+
+ /* set timing */
+ __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+ __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
+
+ /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ delay(5000);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+ /* set mr0 */
+ __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
+
+ /* set up dll */
+ __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
+ delay(0x2000); /* give time to lock */
+
+}
+#endif // CFG_3430SDRAM_DDR
+
+/*************************************************************
+ * get_sys_clk_speed - determine reference oscillator speed
+ * based on known 32kHz clock and gptimer.
+ *************************************************************/
+u32 get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, val;
+
+ val = __raw_readl(PRM_CLKSRC_CTRL);
+ /* If SYS_CLK is being divided by 2, remove for now */
+ val = (val & (~BIT7)) | BIT6;
+ __raw_writel(val, PRM_CLKSRC_CTRL);
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
+
+ /* Enable I and F Clocks for GPT1 */
+ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+ __raw_writel(val, CM_ICLKEN_WKUP);
+ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
+ __raw_writel(val, CM_FCLKEN_WKUP);
+
+ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
+ /* enable 32kHz source *//* enabled out of reset */
+ /* determine sys_clk via gauging */
+
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
+ while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
+ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
+ while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
+ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return (S38_4M);
+ else if (cdiff > 15200)
+ return (S26M);
+ else if (cdiff > 13000)
+ return (S24M);
+ else if (cdiff > 9000)
+ return (S19_2M);
+ else if (cdiff > 7600)
+ return (S13M);
+ else
+ return (S12M);
+}
+
+/******************************************************************************
+ * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
+ * -- input oscillator clock frequency.
+ *
+ *****************************************************************************/
+void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
+{
+ if(osc_clk == S38_4M)
+ *sys_clkin_sel= 4;
+ else if(osc_clk == S26M)
+ *sys_clkin_sel = 3;
+ else if(osc_clk == S19_2M)
+ *sys_clkin_sel = 2;
+ else if(osc_clk == S13M)
+ *sys_clkin_sel = 1;
+ else if(osc_clk == S12M)
+ *sys_clkin_sel = 0;
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * -- called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+ u32 osc_clk=0, sys_clkin_sel;
+ dpll_param *dpll_param_p;
+ u32 clk_index, sil_index;
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ osc_clk = get_osc_clk_speed();
+ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+ sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
+
+ /* If the input clock is greater than 19.2M always divide/2 */
+ if(sys_clkin_sel > 2) {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
+ clk_index = sys_clkin_sel/2;
+ } else {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
+ clk_index = sys_clkin_sel;
+ }
+
+ sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
+
+ /* The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+ if(cpu_is_3410())
+ sil_index = 2;
+ else {
+ if(get_cpu_rev() == CPU_3430_ES1)
+ sil_index = 0;
+ else if(get_cpu_rev() == CPU_3430_ES2)
+ sil_index = 1;
+ }
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address of Core DPLL param table*/
+ dpll_param_p = (dpll_param *)get_core_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
+ /* CORE DPLL */
+ /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+ /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
+ work. write another value and then default value. */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
+ sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+ sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to PER DPLL param table*/
+ dpll_param_p = (dpll_param *)get_per_dpll_param();
+ /* Moving it to the right sysclk base */
+ dpll_param_p = dpll_param_p + clk_index;
+ /* PER DPLL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
+ sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
+ sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
+ sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to MPU DPLL param table*/
+ dpll_param_p = (dpll_param *)get_mpu_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
+ /* MPU DPLL (unlocked already) */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address to IVA DPLL param table*/
+ dpll_param_p = (dpll_param *)get_iva_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
+ /* IVA DPLL (set to 12*20=240MHz) */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
+ sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+ sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+ delay(5000);
+}
+
+/*****************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ * (GP Device only)
+ *****************************************/
+void secure_unlock(void)
+{
+ /* Permission values for registers -Full fledged permissions to all */
+ #define UNLOCK_1 0xFFFFFFFF
+ #define UNLOCK_2 0x00000000
+ #define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT)*/
+ __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+ __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+ __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+ /* IVA Changes */
+ __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+void try_unlock_memory(void)
+{
+ int mode;
+
+ /* if GP device unlock device SRAM for general use */
+ /* secure code breaks for Secure/Emulation device - HS/E/T*/
+ mode = get_device_type();
+ if (mode == GP_DEVICE) {
+ secure_unlock();
+ }
+ return;
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+
+void s_init(void)
+{
+ watchdog_init();
+#ifdef CONFIG_3430_AS_3410
+ /* setup the scalability control register for
+ * 3430 to work in 3410 mode
+ */
+ __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
+#endif
+ try_unlock_memory();
+ set_muxconf_regs();
+ delay(100);
+ prcm_init();
+ per_clocks_enable();
+ config_3430sdram_ddr();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r (void)
+{
+ return(0);
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+ sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+ sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+ wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init (void)
+{
+ return 0;
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void per_clocks_enable(void)
+{
+ /* Enable GP2 timer. */
+ sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CFG_NS16550
+////#ifdef CONFIG_SERIAL3
+ sr32(CM_FCLKEN_PER, 11, 1, 0x1);
+ sr32(CM_ICLKEN_PER, 11, 1, 0x1);
+////#else
+ /* Enable UART1 clocks */
+ sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+////#endif
+#endif
+ delay(1000);
+}
+
+/* Set MUX for UART, GPMC, SDRC, GPIO */
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_NCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_NCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_NCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_NCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_NCS4 lab*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_NCS5 lab*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_NADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_NOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_NWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_NBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_NBE1 lab*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_NWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
+ MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
+ MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
+ MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
+ MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
+ MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
+ MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
+ MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need
+ * to be moved from protect to primary mode.
+ *********************************************************/
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
+
+/**********************************************************
+ * Routine: nand+_init
+ * Description: Set up nand for nand and jffs2 commands
+ *********************************************************/
+int nand_init(void)
+{
+ /* global settings */
+ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
+ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
+ __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
+#ifdef CFG_NAND
+ __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
+#endif
+
+ /* setup CS0 for Micron NAND, leave other CS's to u-boot */
+ __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
+ delay(1000);
+
+#ifdef CFG_NAND
+ __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+ __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+#else /* CFG_ONENAND */
+ __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+#endif
+
+ /* Enable the GPMC Mapping */
+ __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+ ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) |
+ (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+ delay(2000);
+
+#ifdef CFG_NAND
+ if (nand_chip()){
+#ifdef CFG_PRINTF
+ printf("Unsupported Chip!\n");
+#endif
+ return 1;
+ }
+#else
+ if (onenand_chip()){
+#ifdef CFG_PRINTF
+ printf("OneNAND Unsupported !\n");
+#endif
+ return 1;
+ }
+#endif
+ return 0;
+}
+
+/* optionally do something like blinking LED */
+void board_hang (void)
+{ while (0) {};}
diff --git a/x-loader/board/omap3430labrador/platform.S b/x-loader/board/omap3430labrador/platform.S
new file mode 100755
index 0000000..5869270
--- /dev/null
+++ b/x-loader/board/omap3430labrador/platform.S
@@ -0,0 +1,360 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * NOTE: 3430 X-loader currently does not use this code.
+* It could be removed its is kept for compatabily with u-boot.
+ *
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ * confused. A reset of the controller gets it back. Taking away its
+ * L3 when its not in self refresh seems bad for it. Normally, this code
+ * runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4-r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4-r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE,0x07,0x05,0x01
+/* ES2 */
+.word 0x0FA,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D,0x0C,0x03,0x01
+/* ES2 */
+.word 0x1F4,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179,0x12,0x04,0x01
+/* ES2 */
+.word 0x271,0x17,0x03,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D,0x19,0x03,0x01
+/* ES2 */
+.word 0x0FA,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA,0x32,0x03,0x01
+/* ES2 */
+.word 0x271,0x2F,0x03,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D,0x05,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA,0x0C,0x03,0x01
+/* ES2 */
+.word 0x168,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082,0x09,0x07,0x01
+/* ES2 */
+.word 0x0E1,0x0B,0x06,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D,0x0C,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F,0x30,0x03,0x01
+/* ES2 */
+.word 0x0E1,0x17,0x06,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+/* Core DPLL targets for L3 at 166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
+/* ES2 */
+.word M_12,N_12,FSEL_12,M2_12
+/* 3410 */
+.word M_12,N_12,FSEL_12,M2_12
+
+/* 13MHz */
+/* ES1 */
+.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
+/* ES2 */
+.word M_13,N_13,FSEL_13,M2_13
+/* 3410 */
+.word M_13,N_13,FSEL_13,M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
+/* ES2 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+/* 3410 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+
+/* 26MHz */
+/* ES1 */
+.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
+/* ES2 */
+.word M_26,N_26,FSEL_26,M2_26
+/* 3410 */
+.word M_26,N_26,FSEL_26,M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
+/* ES2 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+/* 3410 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8,0x05,0x07,0x09
+
+/* 13MHz */
+.word 0x1B0,0x0C,0x03,0x09
+
+/* 19.2MHz */
+.word 0xE1,0x09,0x07,0x09
+
+/* 26MHz */
+.word 0xD8,0x0C,0x07,0x09
+
+/* 38.4MHz */
+.word 0xE1,0x13,0x07,0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
+
diff --git a/x-loader/board/omap3430labrador/x-load.lds b/x-loader/board/omap3430labrador/x-load.lds
new file mode 100755
index 0000000..9402f74
--- /dev/null
+++ b/x-loader/board/omap3430labrador/x-load.lds
@@ -0,0 +1,54 @@
+/*
+ * November 2006 - Changed to support 3430sdp device
+ * Copyright (c) 2004-2006 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/omap3/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/omap3430sdp/Makefile b/x-loader/board/omap3430sdp/Makefile
new file mode 100644
index 0000000..5d5ce17
--- /dev/null
+++ b/x-loader/board/omap3430sdp/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+OBJS := omap3430sdp.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/omap3430sdp/config.mk b/x-loader/board/omap3430sdp/config.mk
new file mode 100644
index 0000000..d6ad6c5
--- /dev/null
+++ b/x-loader/board/omap3430sdp/config.mk
@@ -0,0 +1,22 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# SDP3430 has 1 bank of 32MB or 128MB mDDR-SDRAM on CS0
+# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1
+# Physical Address:
+# 8000'0000 (bank0)
+# A000'0000 (bank1) - re-mappable below CS1
+
+# For use if you want X-Loader to relocate from SRAM to DDR
+#TEXT_BASE = 0x80e80000
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+TEXT_BASE = 0x40208800
diff --git a/x-loader/board/omap3430sdp/omap3430sdp.c b/x-loader/board/omap3430sdp/omap3430sdp.c
new file mode 100644
index 0000000..b609aaf
--- /dev/null
+++ b/x-loader/board/omap3430sdp/omap3430sdp.c
@@ -0,0 +1,774 @@
+/*
+ * (C) Copyright 2006
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <part.h>
+#include <fat.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+
+/* Used to index into DPLL parameter tables */
+struct dpll_param {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+};
+
+typedef struct dpll_param dpll_param;
+
+#define MAX_SIL_INDEX 3
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param * get_mpu_dpll_param();
+extern dpll_param * get_iva_dpll_param();
+extern dpll_param * get_core_dpll_param();
+extern dpll_param * get_per_dpll_param();
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+ return 0;
+}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+ return(mode >>= 8);
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 cpuid=0;
+ /* On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate
+ * between ES2.0 and ES1.0.
+ */
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
+ if((cpuid & 0xf) == 0x0)
+ return CPU_3430_ES1;
+ else
+ return CPU_3430_ES2;
+
+}
+
+/******************************************
+ * cpu_is_3410(void) - returns true for 3410
+ ******************************************/
+u32 cpu_is_3410(void)
+{
+ int status;
+ if(get_cpu_rev() < CPU_3430_ES2) {
+ return 0;
+ } else {
+ /* read scalability status and return 1 for 3410*/
+ status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
+ /* Check whether MPU frequency is set to 266 MHz which
+ * is nominal for 3410. If yes return true else false
+ */
+ if (((status >> 8) & 0x3) == 0x2)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/*****************************************************************
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ *****************************************************************/
+void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = __raw_readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ __raw_writel(tmp, addr);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
+
+#ifdef CFG_3430SDRAM_DDR
+/*********************************************************************
+ * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
+ *********************************************************************/
+void config_3430sdram_ddr(void)
+{
+ /* reset sdrc controller */
+ __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
+ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
+ __raw_writel(0, SDRC_SYSCONFIG);
+
+ /* setup sdrc to ball mux */
+ __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
+
+ /* set mdcfg */
+ __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+
+ /* set timing */
+ __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+ __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
+
+ /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ delay(5000);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+ /* set mr0 */
+ __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
+
+ /* set up dll */
+ __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
+ delay(0x2000); /* give time to lock */
+
+}
+#endif // CFG_3430SDRAM_DDR
+
+/*************************************************************
+ * get_sys_clk_speed - determine reference oscillator speed
+ * based on known 32kHz clock and gptimer.
+ *************************************************************/
+u32 get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, val;
+
+ val = __raw_readl(PRM_CLKSRC_CTRL);
+ /* If SYS_CLK is being divided by 2, remove for now */
+ val = (val & (~BIT7)) | BIT6;
+ __raw_writel(val, PRM_CLKSRC_CTRL);
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
+
+ /* Enable I and F Clocks for GPT1 */
+ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+ __raw_writel(val, CM_ICLKEN_WKUP);
+ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
+ __raw_writel(val, CM_FCLKEN_WKUP);
+
+ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
+ /* enable 32kHz source *//* enabled out of reset */
+ /* determine sys_clk via gauging */
+
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
+ while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
+ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
+ while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
+ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
+ cdiff = cend - cstart; /* get elapsed ticks */
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return (S38_4M);
+ else if (cdiff > 15200)
+ return (S26M);
+ else if (cdiff > 13000)
+ return (S24M);
+ else if (cdiff > 9000)
+ return (S19_2M);
+ else if (cdiff > 7600)
+ return (S13M);
+ else
+ return (S12M);
+}
+
+/******************************************************************************
+ * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
+ * -- input oscillator clock frequency.
+ *
+ *****************************************************************************/
+void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
+{
+ if(osc_clk == S38_4M)
+ *sys_clkin_sel= 4;
+ else if(osc_clk == S26M)
+ *sys_clkin_sel = 3;
+ else if(osc_clk == S19_2M)
+ *sys_clkin_sel = 2;
+ else if(osc_clk == S13M)
+ *sys_clkin_sel = 1;
+ else if(osc_clk == S12M)
+ *sys_clkin_sel = 0;
+}
+
+/******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * -- called from SRAM, or Flash (using temp SRAM stack).
+ *****************************************************************************/
+void prcm_init(void)
+{
+ u32 osc_clk=0, sys_clkin_sel;
+ dpll_param *dpll_param_p;
+ u32 clk_index, sil_index;
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ osc_clk = get_osc_clk_speed();
+ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+ sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
+
+ /* If the input clock is greater than 19.2M always divide/2 */
+ if(sys_clkin_sel > 2) {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
+ clk_index = sys_clkin_sel/2;
+ } else {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
+ clk_index = sys_clkin_sel;
+ }
+
+ /* The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+ if(cpu_is_3410())
+ sil_index = 2;
+ else {
+ if(get_cpu_rev() == CPU_3430_ES1)
+ sil_index = 0;
+ else if(get_cpu_rev() == CPU_3430_ES2)
+ sil_index = 1;
+ }
+
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address of Core DPLL param table*/
+ dpll_param_p = (dpll_param *)get_core_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
+ /* CORE DPLL */
+ /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
+ sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+ sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to PER DPLL param table*/
+ dpll_param_p = (dpll_param *)get_per_dpll_param();
+ /* Moving it to the right sysclk base */
+ dpll_param_p = dpll_param_p + clk_index;
+ /* PER DPLL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
+ sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
+ sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
+ sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to MPU DPLL param table*/
+ dpll_param_p = (dpll_param *)get_mpu_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
+ /* MPU DPLL (unlocked already) */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address to IVA DPLL param table*/
+ dpll_param_p = (dpll_param *)get_iva_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index;
+ /* IVA DPLL (set to 12*20=240MHz) */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
+ sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+ sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+ delay(5000);
+}
+
+/*****************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ * (GP Device only)
+ *****************************************/
+void secure_unlock(void)
+{
+ /* Permission values for registers -Full fledged permissions to all */
+ #define UNLOCK_1 0xFFFFFFFF
+ #define UNLOCK_2 0x00000000
+ #define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT)*/
+ __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+ __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+ __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+ /* IVA Changes */
+ __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+void try_unlock_memory(void)
+{
+ int mode;
+
+ /* if GP device unlock device SRAM for general use */
+ /* secure code breaks for Secure/Emulation device - HS/E/T*/
+ mode = get_device_type();
+ if (mode == GP_DEVICE) {
+ secure_unlock();
+ }
+ return;
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called at time when only stack is available.
+ **********************************************************/
+
+void s_init(void)
+{
+ watchdog_init();
+#ifdef CONFIG_3430_AS_3410
+ /* setup the scalability control register for
+ * 3430 to work in 3410 mode
+ */
+ __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
+#endif
+ try_unlock_memory();
+ set_muxconf_regs();
+ delay(100);
+ prcm_init();
+ per_clocks_enable();
+ config_3430sdram_ddr();
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r (void)
+{
+ return(0);
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+ sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+ sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+ wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init (void)
+{
+ return 0;
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void per_clocks_enable(void)
+{
+ /* Enable GP2 timer. */
+ sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CFG_NS16550
+ /* Enable UART1 clocks */
+ sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+#endif
+ delay(1000);
+}
+
+/* Set MUX for UART, GPMC, SDRC, GPIO */
+
+#define MUX_VAL(OFFSET,VALUE)\
+ __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#define CP(x) (CONTROL_PADCONF_##x)
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_NCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_NCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_NCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_NCS3*/\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_NCS4*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_NCS5*/\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_NCS6*/\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_NCS7*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_NADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_NOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_NWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_NBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_NWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
+ MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
+ MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
+ MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
+ MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
+ MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
+ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
+ MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
+ MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
+ MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
+ MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
+ MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
+ MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need
+ * to be moved from protect to primary mode.
+ *********************************************************/
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
+
+/**********************************************************
+ * Routine: nand+_init
+ * Description: Set up nand for nand and jffs2 commands
+ *********************************************************/
+int nand_init(void)
+{
+ /* global settings */
+ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
+ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
+ __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
+#ifdef CFG_NAND
+ __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
+#endif
+
+ /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0
+ * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0.
+ * We configure only GPMC CS0 with required values. Configiring other devices
+ * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
+ */
+ __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
+ delay(1000);
+
+#ifdef CFG_NAND
+ __raw_writel( SMNAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ __raw_writel( SMNAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+ __raw_writel( SMNAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+ __raw_writel( SMNAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+ __raw_writel( SMNAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+ __raw_writel( SMNAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+#else /* CFG_ONENAND */
+ __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+ __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+#endif
+
+ /* Enable the GPMC Mapping */
+ __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+ ((OMAP34XX_GPMC_CS0_MAP>>24) & 0x3F) |
+ (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+ delay(2000);
+#if defined(CFG_NAND)
+ if (nand_chip()){
+#ifdef CFG_PRINTF
+ printf("Unsupported Chip!\n");
+#endif
+ return 1;
+ }
+#elif defined(CFG_ONENAND)
+ if (onenand_chip()){
+#ifdef CFG_PRINTF
+ printf("OneNAND Unsupported !\n");
+#endif
+ return 1;
+ }
+#endif
+ return 0;
+}
+
+#ifdef CFG_CMD_FAT
+typedef int (mmc_boot_addr) (void);
+int mmc_boot(void)
+{
+ long size, i;
+ unsigned long offset = CFG_LOADADDR;
+ unsigned long count;
+ char buf[12];
+ block_dev_desc_t *dev_desc = NULL;
+ int dev = 0;
+ int part = 1;
+ char *ep;
+ unsigned char ret = 0;
+
+ printf("Starting X-loader on MMC \n");
+
+ ret = mmc_init(1);
+ if(ret == 0){
+ printf("\n MMC init failed \n");
+ return 0;
+ }
+
+ dev_desc = mmc_get_dev(0);
+ fat_register_device(dev_desc, 1);
+ size = file_fat_read("u-boot.bin", (unsigned char *)offset, 0);
+ if (size == -1) {
+ return 0;
+ }
+ printf("\n%ld Bytes Read from MMC \n", size);
+
+ printf("Starting OS Bootloader from MMC...\n");
+
+ ((mmc_boot_addr *) CFG_LOADADDR) ();
+
+ return 0;
+}
+#endif
+
+/* optionally do something like blinking LED */
+void board_hang (void)
+{ while (0) {};}
diff --git a/x-loader/board/omap3430sdp/platform.S b/x-loader/board/omap3430sdp/platform.S
new file mode 100644
index 0000000..5869270
--- /dev/null
+++ b/x-loader/board/omap3430sdp/platform.S
@@ -0,0 +1,360 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting code */
+ mov r2, #384 /* r2 size to copy (div by 32 bytes) */
+ mov r1, r1 /* r1 <- dest address (passed in) */
+ add r2, r2, r0 /* r2 <- source end address */
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/* ****************************************************************************
+ * NOTE: 3430 X-loader currently does not use this code.
+* It could be removed its is kept for compatabily with u-boot.
+ *
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ * confused. A reset of the controller gets it back. Taking away its
+ * L3 when its not in self refresh seems bad for it. Normally, this code
+ * runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4-r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4-r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE,0x07,0x05,0x01
+/* ES2 */
+.word 0x0FA,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D,0x0C,0x03,0x01
+/* ES2 */
+.word 0x1F4,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179,0x12,0x04,0x01
+/* ES2 */
+.word 0x271,0x17,0x03,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D,0x19,0x03,0x01
+/* ES2 */
+.word 0x0FA,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA,0x32,0x03,0x01
+/* ES2 */
+.word 0x271,0x2F,0x03,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D,0x05,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA,0x0C,0x03,0x01
+/* ES2 */
+.word 0x168,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082,0x09,0x07,0x01
+/* ES2 */
+.word 0x0E1,0x0B,0x06,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D,0x0C,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F,0x30,0x03,0x01
+/* ES2 */
+.word 0x0E1,0x17,0x06,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+/* Core DPLL targets for L3 at 166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
+/* ES2 */
+.word M_12,N_12,FSEL_12,M2_12
+/* 3410 */
+.word M_12,N_12,FSEL_12,M2_12
+
+/* 13MHz */
+/* ES1 */
+.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
+/* ES2 */
+.word M_13,N_13,FSEL_13,M2_13
+/* 3410 */
+.word M_13,N_13,FSEL_13,M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
+/* ES2 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+/* 3410 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+
+/* 26MHz */
+/* ES1 */
+.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
+/* ES2 */
+.word M_26,N_26,FSEL_26,M2_26
+/* 3410 */
+.word M_26,N_26,FSEL_26,M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
+/* ES2 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+/* 3410 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8,0x05,0x07,0x09
+
+/* 13MHz */
+.word 0x1B0,0x0C,0x03,0x09
+
+/* 19.2MHz */
+.word 0xE1,0x09,0x07,0x09
+
+/* 26MHz */
+.word 0xD8,0x0C,0x07,0x09
+
+/* 38.4MHz */
+.word 0xE1,0x13,0x07,0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
+
diff --git a/x-loader/board/omap3430sdp/x-load.lds b/x-loader/board/omap3430sdp/x-load.lds
new file mode 100644
index 0000000..9402f74
--- /dev/null
+++ b/x-loader/board/omap3430sdp/x-load.lds
@@ -0,0 +1,54 @@
+/*
+ * November 2006 - Changed to support 3430sdp device
+ * Copyright (c) 2004-2006 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/omap3/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/x-loader/board/omap3evm/Makefile b/x-loader/board/omap3evm/Makefile
new file mode 100755
index 0000000..e399c5b
--- /dev/null
+++ b/x-loader/board/omap3evm/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+OBJS := omap3evm.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/x-loader/board/omap3evm/config.mk b/x-loader/board/omap3evm/config.mk
new file mode 100755
index 0000000..a45ec22
--- /dev/null
+++ b/x-loader/board/omap3evm/config.mk
@@ -0,0 +1,19 @@
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# OMAP3EVM board uses OMAP3430 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments#
+#
+# OMAP3EVM has 1 bank of 128MB mPOP-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+
+# For use if you want X-Loader to relocate from SRAM to DDR
+#TEXT_BASE = 0x80e80000
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+TEXT_BASE = 0x40200800
diff --git a/x-loader/board/omap3evm/omap3evm.c b/x-loader/board/omap3evm/omap3evm.c
new file mode 100755
index 0000000..1d7b994
--- /dev/null
+++ b/x-loader/board/omap3evm/omap3evm.c
@@ -0,0 +1,1239 @@
+/*
+ * (C) Copyright 2006
+ * Texas Instruments, <www.ti.com>
+ * Jian Zhang <jzhang@ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <command.h>
+#include <part.h>
+#include <fat.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+
+/* Used to index into DPLL parameter tables */
+struct dpll_param {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+};
+
+struct dpll_per_36x_param {
+ unsigned int sys_clk;
+ unsigned int m;
+ unsigned int n;
+ unsigned int m2;
+ unsigned int m3;
+ unsigned int m4;
+ unsigned int m5;
+ unsigned int m6;
+ unsigned int m2div;
+};
+
+typedef struct dpll_param dpll_param;
+
+#define MAX_SIL_INDEX 3
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+
+extern dpll_param *get_36x_mpu_dpll_param(void);
+extern dpll_param *get_36x_iva_dpll_param(void);
+extern dpll_param *get_36x_core_dpll_param(void);
+extern dpll_param *get_36x_per_dpll_param(void);
+
+extern int mmc_init(int verbose);
+extern block_dev_desc_t *mmc_get_dev(int dev);
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+void udelay (unsigned long usecs) {
+ delay(usecs);
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init (void)
+{
+ return 0;
+}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+ return(mode >>= 8);
+}
+
+/************************************************
+ * get_sysboot_value(void) - return SYS_BOOT[4:0]
+ ************************************************/
+u32 get_sysboot_value(void)
+{
+ int mode;
+ mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
+ return mode;
+}
+/*************************************************************
+ * Routine: get_mem_type(void) - returns the kind of memory connected
+ * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
+ *************************************************************/
+u32 get_mem_type(void)
+{
+ u32 mem_type = get_sysboot_value();
+ switch (mem_type){
+ case 0:
+ case 2:
+ case 4:
+ case 16:
+ case 22: return GPMC_ONENAND;
+
+ case 1:
+ case 12:
+ case 15:
+ case 21:
+ case 27: return GPMC_NAND;
+
+ case 3:
+ case 6: return MMC_ONENAND;
+
+ case 8:
+ case 11:
+ case 14:
+ case 20:
+ case 26: return GPMC_MDOC;
+
+ case 17:
+ case 18:
+ case 24: return MMC_NAND;
+
+ case 7:
+ case 10:
+ case 13:
+ case 19:
+ case 25:
+ default: return GPMC_NOR;
+ }
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 cpuid=0;
+ /* On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate
+ * between ES2.0 and ES1.0.
+ */
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
+ if((cpuid & 0xf) == 0x0)
+ return CPU_3430_ES1;
+ else
+ return CPU_3430_ES2;
+
+}
+
+u32 is_cpu_family(void)
+{
+ u32 cpuid = 0, cpu_family = 0;
+ u16 hawkeye;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
+ if ((cpuid & 0xf) == 0x0) {
+ cpu_family = CPU_OMAP34XX;
+ } else {
+ cpuid = __raw_readl(OMAP34XX_CONTROL_ID);
+ hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
+
+ switch (hawkeye) {
+ case HAWKEYE_OMAP34XX:
+ cpu_family = CPU_OMAP34XX;
+ break;
+ case HAWKEYE_AM35XX:
+ cpu_family = CPU_AM35XX;
+ break;
+ case HAWKEYE_OMAP36XX:
+ cpu_family = CPU_OMAP36XX;
+ break;
+ default:
+ cpu_family = CPU_OMAP34XX;
+ break;
+ }
+ }
+ return cpu_family;
+}
+/******************************************
+ * cpu_is_3410(void) - returns true for 3410
+ ******************************************/
+u32 cpu_is_3410(void)
+{
+ int status;
+ if(get_cpu_rev() < CPU_3430_ES2) {
+ return 0;
+ } else {
+ /* read scalability status and return 1 for 3410*/
+ status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
+ /* Check whether MPU frequency is set to 266 MHz which
+ * is nominal for 3410. If yes return true else false
+ */
+ if (((status >> 8) & 0x3) == 0x2)
+ return 1;
+ else
+ return 0;
+ }
+}
+
+/*****************************************************************
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ *****************************************************************/
+void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = __raw_readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ __raw_writel(tmp, addr);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
+
+#ifdef CFG_OMAPEVM_DDR
+#ifdef CONFIG_DDR_256MB_STACKED
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ * command line mem=xyz use all memory with out discontinuous support
+ * compiled in. Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+ u32 size, a_add_low, a_add_high;
+
+ size = get_sdr_cs_size(SDRC_CS0_OSET);
+ size /= SZ_32M; /* find size to offset CS1 */
+ a_add_high = (size & 3) << 8; /* set up low field */
+ a_add_low = (size & 0x3C) >> 2; /* set up high field */
+ __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+ u32 size;
+
+ /* get ram size field */
+ size = __raw_readl(SDRC_MCFG_0 + offset) >> 8;
+ size &= 0x3FF; /* remove unwanted bits */
+ size *= SZ_2M; /* find size in MB */
+ return size;
+}
+#endif
+
+/*********************************************************************
+ * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
+ *********************************************************************/
+void config_3430sdram_ddr(void)
+{
+
+#ifndef CONFIG_DDR_256MB_STACKED
+ /* reset sdrc controller */
+ __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
+ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
+ __raw_writel(0, SDRC_SYSCONFIG);
+
+ /* setup sdrc to ball mux */
+ __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
+
+ /* set mdcfg */
+ __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+
+ /* set timing */
+ if (is_cpu_family() == CPU_OMAP36XX) {
+ __raw_writel(HYNIX_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(HYNIX_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+
+ } else {
+ if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
+ __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+ }
+ if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){
+ __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+ __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+ }
+ }
+
+ __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
+ __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
+
+ /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
+ __raw_writel(CMD_NOP, SDRC_MANUAL_0);
+ delay(5000);
+ __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+ __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
+
+ /* set mr0 */
+ __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
+
+ /* set up dll */
+ __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
+ delay(0x2000); /* give time to lock */
+#else
